1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
66 #include "basic-block.h"
68 #include "hard-reg-set.h"
69 #include "insn-config.h"
70 #include "insn-attr.h"
75 /* Next quantity number available for allocation. */
79 /* In all the following vectors indexed by quantity number. */
81 /* Element Q is the hard reg number chosen for quantity Q,
82 or -1 if none was found. */
84 static short *qty_phys_reg;
86 /* We maintain two hard register sets that indicate suggested hard registers
87 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
88 that are tied to the quantity by a simple copy. The second contains all
89 hard registers that are tied to the quantity via an arithmetic operation.
91 The former register set is given priority for allocation. This tends to
92 eliminate copy insns. */
94 /* Element Q is a set of hard registers that are suggested for quantity Q by
97 static HARD_REG_SET *qty_phys_copy_sugg;
99 /* Element Q is a set of hard registers that are suggested for quantity Q by
102 static HARD_REG_SET *qty_phys_sugg;
104 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
106 static short *qty_phys_num_copy_sugg;
108 /* Element Q is the number of suggested registers in qty_phys_sugg. */
110 static short *qty_phys_num_sugg;
112 /* Element Q is the number of refs to quantity Q. */
114 static int *qty_n_refs;
116 /* Element Q is a reg class contained in (smaller than) the
117 preferred classes of all the pseudo regs that are tied in quantity Q.
118 This is the preferred class for allocating that quantity. */
120 static enum reg_class *qty_min_class;
122 /* Insn number (counting from head of basic block)
123 where quantity Q was born. -1 if birth has not been recorded. */
125 static int *qty_birth;
127 /* Insn number (counting from head of basic block)
128 where quantity Q died. Due to the way tying is done,
129 and the fact that we consider in this pass only regs that die but once,
130 a quantity can die only once. Each quantity's life span
131 is a set of consecutive insns. -1 if death has not been recorded. */
133 static int *qty_death;
135 /* Number of words needed to hold the data in quantity Q.
136 This depends on its machine mode. It is used for these purposes:
137 1. It is used in computing the relative importances of qtys,
138 which determines the order in which we look for regs for them.
139 2. It is used in rules that prevent tying several registers of
140 different sizes in a way that is geometrically impossible
141 (see combine_regs). */
143 static int *qty_size;
145 /* This holds the mode of the registers that are tied to qty Q,
146 or VOIDmode if registers with differing modes are tied together. */
148 static enum machine_mode *qty_mode;
150 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
152 static int *qty_n_calls_crossed;
154 /* Register class within which we allocate qty Q if we can't get
155 its preferred class. */
157 static enum reg_class *qty_alternate_class;
159 /* Element Q is the SCRATCH expression for which this quantity is being
160 allocated or 0 if this quantity is allocating registers. */
162 static rtx *qty_scratch_rtx;
164 /* Element Q is nonzero if this quantity has been used in a SUBREG
165 that changes its size. */
167 static char *qty_changes_size;
169 /* Element Q is the register number of one pseudo register whose
170 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
171 register should be the head of the chain maintained in reg_next_in_qty. */
173 static int *qty_first_reg;
175 /* If (REG N) has been assigned a quantity number, is a register number
176 of another register assigned the same quantity number, or -1 for the
177 end of the chain. qty_first_reg point to the head of this chain. */
179 static int *reg_next_in_qty;
181 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
183 of -1 if this register cannot be allocated by local-alloc,
184 or -2 if not known yet.
186 Note that if we see a use or death of pseudo register N with
187 reg_qty[N] == -2, register N must be local to the current block. If
188 it were used in more than one block, we would have reg_qty[N] == -1.
189 This relies on the fact that if reg_basic_block[N] is >= 0, register N
190 will not appear in any other block. We save a considerable number of
191 tests by exploiting this.
193 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
198 /* The offset (in words) of register N within its quantity.
199 This can be nonzero if register N is SImode, and has been tied
200 to a subreg of a DImode register. */
202 static char *reg_offset;
204 /* Vector of substitutions of register numbers,
205 used to map pseudo regs into hardware regs.
206 This is set up as a result of register allocation.
207 Element N is the hard reg assigned to pseudo reg N,
208 or is -1 if no hard reg was assigned.
209 If N is a hard reg number, element N is N. */
213 /* Set of hard registers live at the current point in the scan
214 of the instructions in a basic block. */
216 static HARD_REG_SET regs_live;
218 /* Each set of hard registers indicates registers live at a particular
219 point in the basic block. For N even, regs_live_at[N] says which
220 hard registers are needed *after* insn N/2 (i.e., they may not
221 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
223 If an object is to conflict with the inputs of insn J but not the
224 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
225 if it is to conflict with the outputs of insn J but not the inputs of
226 insn J + 1, it is said to die at index J*2 + 1. */
228 static HARD_REG_SET *regs_live_at;
232 int scratch_list_length;
233 static int scratch_index;
235 /* Communicate local vars `insn_number' and `insn'
236 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
237 static int this_insn_number;
238 static rtx this_insn;
240 /* Used to communicate changes made by update_equiv_regs to
241 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
242 found or created, so that we can keep track of what memory accesses might
243 be created later, e.g. by reload. */
245 static rtx *reg_equiv_replacement;
247 static void alloc_qty PROTO((int, enum machine_mode, int, int));
248 static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int));
249 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
250 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
251 static int contains_replace_regs PROTO((rtx, char *));
252 static int memref_referenced_p PROTO((rtx, rtx));
253 static int memref_used_between_p PROTO((rtx, rtx, rtx));
254 static void update_equiv_regs PROTO((void));
255 static void block_alloc PROTO((int));
256 static int qty_sugg_compare PROTO((int, int));
257 static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
258 static int qty_compare PROTO((int, int));
259 static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
260 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
261 static int reg_meets_class_p PROTO((int, enum reg_class));
262 static void update_qty_class PROTO((int, int));
263 static void reg_is_set PROTO((rtx, rtx));
264 static void reg_is_born PROTO((rtx, int));
265 static void wipe_dead_reg PROTO((rtx, int));
266 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
267 int, int, int, int, int));
268 static void mark_life PROTO((int, enum machine_mode, int));
269 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
270 static int no_conflict_p PROTO((rtx, rtx, rtx));
271 static int requires_inout PROTO((char *));
273 /* Allocate a new quantity (new within current basic block)
274 for register number REGNO which is born at index BIRTH
275 within the block. MODE and SIZE are info on reg REGNO. */
278 alloc_qty (regno, mode, size, birth)
280 enum machine_mode mode;
283 register int qty = next_qty++;
285 reg_qty[regno] = qty;
286 reg_offset[regno] = 0;
287 reg_next_in_qty[regno] = -1;
289 qty_first_reg[qty] = regno;
290 qty_size[qty] = size;
291 qty_mode[qty] = mode;
292 qty_birth[qty] = birth;
293 qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno);
294 qty_min_class[qty] = reg_preferred_class (regno);
295 qty_alternate_class[qty] = reg_alternate_class (regno);
296 qty_n_refs[qty] = REG_N_REFS (regno);
297 qty_changes_size[qty] = REG_CHANGES_SIZE (regno);
300 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
301 used as operand N in INSN. We assume here that the SCRATCH is used in
305 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
309 int insn_code_num, insn_number;
312 enum reg_class class;
316 #ifdef REGISTER_CONSTRAINTS
317 /* If we haven't yet computed which alternative will be used, do so now.
318 Then set P to the constraints for that alternative. */
319 if (which_alternative == -1)
320 if (! constrain_operands (insn_code_num, 0))
323 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
324 *p && i < which_alternative; p++)
328 /* Compute the class required for this SCRATCH. If we don't need a
329 register, the class will remain NO_REGS. If we guessed the alternative
330 number incorrectly, reload will fix things up for us. */
333 while ((c = *p++) != '\0' && c != ',')
336 case '=': case '+': case '?':
337 case '#': case '&': case '!':
339 case '0': case '1': case '2': case '3': case '4':
340 case 'm': case '<': case '>': case 'V': case 'o':
341 case 'E': case 'F': case 'G': case 'H':
342 case 's': case 'i': case 'n':
343 case 'I': case 'J': case 'K': case 'L':
344 case 'M': case 'N': case 'O': case 'P':
345 #ifdef EXTRA_CONSTRAINT
346 case 'Q': case 'R': case 'S': case 'T': case 'U':
349 /* These don't say anything we care about. */
353 /* We don't need to allocate this SCRATCH. */
357 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
362 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
366 if (class == NO_REGS)
369 #else /* REGISTER_CONSTRAINTS */
371 class = GENERAL_REGS;
377 qty_first_reg[qty] = -1;
378 qty_scratch_rtx[qty] = scratch;
379 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
380 qty_mode[qty] = GET_MODE (scratch);
381 qty_birth[qty] = 2 * insn_number - 1;
382 qty_death[qty] = 2 * insn_number + 1;
383 qty_n_calls_crossed[qty] = 0;
384 qty_min_class[qty] = class;
385 qty_alternate_class[qty] = NO_REGS;
387 qty_changes_size[qty] = 0;
390 /* Main entry point of this file. */
398 /* Leaf functions and non-leaf functions have different needs.
399 If defined, let the machine say what kind of ordering we
401 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
402 ORDER_REGS_FOR_LOCAL_ALLOC;
405 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
407 update_equiv_regs ();
409 /* This sets the maximum number of quantities we can have. Quantity
410 numbers start at zero and we can have one for each pseudo plus the
411 number of SCRATCHes in the largest block, in the worst case. */
412 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
414 /* Allocate vectors of temporary data.
415 See the declarations of these variables, above,
416 for what they mean. */
418 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
419 Instead of allocating this much memory from now until the end of
420 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
421 reload will allocate them. */
423 scratch_list_length = max_qty;
424 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
425 bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx));
426 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
427 bzero ((char *) scratch_block, scratch_list_length * sizeof (int));
430 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
432 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
433 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
434 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
435 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
436 qty_birth = (int *) alloca (max_qty * sizeof (int));
437 qty_death = (int *) alloca (max_qty * sizeof (int));
438 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
439 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
440 qty_size = (int *) alloca (max_qty * sizeof (int));
442 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
443 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
445 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
447 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
448 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
449 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
451 reg_qty = (int *) alloca (max_regno * sizeof (int));
452 reg_offset = (char *) alloca (max_regno * sizeof (char));
453 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
455 /* Allocate the reg_renumber array */
456 allocate_reg_info (max_regno, FALSE, TRUE);
458 /* Determine which pseudo-registers can be allocated by local-alloc.
459 In general, these are the registers used only in a single block and
460 which only die once. However, if a register's preferred class has only
461 a few entries, don't allocate this register here unless it is preferred
462 or nothing since retry_global_alloc won't be able to move it to
463 GENERAL_REGS if a reload register of this class is needed.
465 We need not be concerned with which block actually uses the register
466 since we will never see it outside that block. */
468 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
470 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
471 && (reg_alternate_class (i) == NO_REGS
472 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
478 /* Force loop below to initialize entire quantity array. */
481 /* Allocate each block's local registers, block by block. */
483 for (b = 0; b < n_basic_blocks; b++)
485 /* NEXT_QTY indicates which elements of the `qty_...'
486 vectors might need to be initialized because they were used
487 for the previous block; it is set to the entire array before
488 block 0. Initialize those, with explicit loop if there are few,
489 else with bzero and bcopy. Do not initialize vectors that are
490 explicit set by `alloc_qty'. */
494 for (i = 0; i < next_qty; i++)
496 qty_scratch_rtx[i] = 0;
497 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
498 qty_phys_num_copy_sugg[i] = 0;
499 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
500 qty_phys_num_sugg[i] = 0;
505 #define CLEAR(vector) \
506 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
508 CLEAR (qty_scratch_rtx);
509 CLEAR (qty_phys_copy_sugg);
510 CLEAR (qty_phys_num_copy_sugg);
511 CLEAR (qty_phys_sugg);
512 CLEAR (qty_phys_num_sugg);
524 /* Depth of loops we are in while in update_equiv_regs. */
525 static int loop_depth;
527 /* Used for communication between the following two functions: contains
528 a MEM that we wish to ensure remains unchanged. */
529 static rtx equiv_mem;
531 /* Set nonzero if EQUIV_MEM is modified. */
532 static int equiv_mem_modified;
534 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
535 Called via note_stores. */
538 validate_equiv_mem_from_store (dest, set)
542 if ((GET_CODE (dest) == REG
543 && reg_overlap_mentioned_p (dest, equiv_mem))
544 || (GET_CODE (dest) == MEM
545 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
546 equiv_mem_modified = 1;
549 /* Verify that no store between START and the death of REG invalidates
550 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
551 by storing into an overlapping memory location, or with a non-const
554 Return 1 if MEMREF remains valid. */
557 validate_equiv_mem (start, reg, memref)
566 equiv_mem_modified = 0;
568 /* If the memory reference has side effects or is volatile, it isn't a
569 valid equivalence. */
570 if (side_effects_p (memref))
573 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
575 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
578 if (find_reg_note (insn, REG_DEAD, reg))
581 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
582 && ! CONST_CALL_P (insn))
585 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
587 /* If a register mentioned in MEMREF is modified via an
588 auto-increment, we lose the equivalence. Do the same if one
589 dies; although we could extend the life, it doesn't seem worth
592 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
593 if ((REG_NOTE_KIND (note) == REG_INC
594 || REG_NOTE_KIND (note) == REG_DEAD)
595 && GET_CODE (XEXP (note, 0)) == REG
596 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
603 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
606 contains_replace_regs (x, reg_equiv_replace)
608 char *reg_equiv_replace;
612 enum rtx_code code = GET_CODE (x);
628 return reg_equiv_replace[REGNO (x)];
634 fmt = GET_RTX_FORMAT (code);
635 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
639 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
643 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
644 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
652 /* TRUE if X references a memory location that would be affected by a store
656 memref_referenced_p (memref, x)
662 enum rtx_code code = GET_CODE (x);
678 return (reg_equiv_replacement[REGNO (x)]
679 && memref_referenced_p (memref,
680 reg_equiv_replacement[REGNO (x)]));
683 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
688 /* If we are setting a MEM, it doesn't count (its address does), but any
689 other SET_DEST that has a MEM in it is referencing the MEM. */
690 if (GET_CODE (SET_DEST (x)) == MEM)
692 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
695 else if (memref_referenced_p (memref, SET_DEST (x)))
698 return memref_referenced_p (memref, SET_SRC (x));
704 fmt = GET_RTX_FORMAT (code);
705 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
709 if (memref_referenced_p (memref, XEXP (x, i)))
713 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
714 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
722 /* TRUE if some insn in the range (START, END] references a memory location
723 that would be affected by a store to MEMREF. */
726 memref_used_between_p (memref, start, end)
733 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
734 insn = NEXT_INSN (insn))
735 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
736 && memref_referenced_p (memref, PATTERN (insn)))
742 /* Find registers that are equivalent to a single value throughout the
743 compilation (either because they can be referenced in memory or are set once
744 from a single constant). Lower their priority for a register.
746 If such a register is only referenced once, try substituting its value
747 into the using insn. If it succeeds, we can eliminate the register
753 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
754 /* Set when an attempt should be made to replace a register with the
755 associated reg_equiv_replacement entry at the end of this function. */
756 char *reg_equiv_replace
757 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
761 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
763 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *));
764 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *));
765 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
767 init_alias_analysis ();
771 /* Scan the insns and find which registers have equivalences. Do this
772 in a separate scan of the insns because (due to -fcse-follow-jumps)
773 a register can be set below its use. */
774 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
777 rtx set = single_set (insn);
781 if (GET_CODE (insn) == NOTE)
783 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
785 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
789 /* If this insn contains more (or less) than a single SET, ignore it. */
793 dest = SET_DEST (set);
796 /* If this sets a MEM to the contents of a REG that is only used
797 in a single basic block, see if the register is always equivalent
798 to that memory location and if moving the store from INSN to the
799 insn that set REG is safe. If so, put a REG_EQUIV note on the
802 Don't add a REG_EQUIV note if the insn already has one. The existing
803 REG_EQUIV is likely more useful than the one we are adding.
805 If one of the regs in the address is marked as reg_equiv_replace,
806 then we can't add this REG_EQUIV note. The reg_equiv_replace
807 optimization may move the set of this register immediately before
808 insn, which puts it after reg_equiv_init_insn[regno], and hence
809 the mention in the REG_EQUIV note would be to an uninitialized
812 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
813 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
814 && REG_BASIC_BLOCK (regno) >= 0
815 && reg_equiv_init_insn[regno] != 0
816 && ! find_reg_note (insn, REG_EQUIV, NULL_RTX)
817 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace)
818 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
820 && ! memref_used_between_p (SET_DEST (set),
821 reg_equiv_init_insn[regno], insn))
822 REG_NOTES (reg_equiv_init_insn[regno])
823 = gen_rtx_EXPR_LIST (REG_EQUIV, dest,
824 REG_NOTES (reg_equiv_init_insn[regno]));
826 /* We only handle the case of a pseudo register being set
827 once and only if neither the source nor the destination are
828 in a register class that's likely to be spilled. */
829 if (GET_CODE (dest) != REG
830 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
831 || REG_N_SETS (regno) != 1
832 || CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (dest)))
833 || (GET_CODE (src) == REG
834 && REGNO (src) >= FIRST_PSEUDO_REGISTER
835 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src)))))
838 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
840 #ifdef DONT_RECORD_EQUIVALENCE
841 /* Allow the target to reject promotions of some REG_EQUAL notes to
844 In some cases this can improve register allocation if the existence
845 of the REG_EQUIV note is likely to increase the lifetime of a register
846 that is likely to be spilled.
848 It may also be necessary if the target can't handle certain constant
849 expressions appearing randomly in insns, but for whatever reason
850 those expressions must be considered legitimate constant expressions
851 to prevent them from being forced into memory. */
852 if (note && DONT_RECORD_EQUIVALENCE (note))
856 /* Record this insn as initializing this register. */
857 reg_equiv_init_insn[regno] = insn;
859 /* If this register is known to be equal to a constant, record that
860 it is always equivalent to the constant. */
861 if (note && CONSTANT_P (XEXP (note, 0)))
862 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
864 /* If this insn introduces a "constant" register, decrease the priority
865 of that register. Record this insn if the register is only used once
866 more and the equivalence value is the same as our source.
868 The latter condition is checked for two reasons: First, it is an
869 indication that it may be more efficient to actually emit the insn
870 as written (if no registers are available, reload will substitute
871 the equivalence). Secondly, it avoids problems with any registers
872 dying in this insn whose death notes would be missed.
874 If we don't have a REG_EQUIV note, see if this insn is loading
875 a register used only in one basic block from a MEM. If so, and the
876 MEM remains unchanged for the life of the register, add a REG_EQUIV
879 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
881 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
882 && GET_CODE (SET_SRC (set)) == MEM
883 && validate_equiv_mem (insn, dest, SET_SRC (set)))
884 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
889 int regno = REGNO (dest);
891 reg_equiv_replacement[regno] = XEXP (note, 0);
893 /* Don't mess with things live during setjmp. */
894 if (REG_LIVE_LENGTH (regno) >= 0)
896 /* Note that the statement below does not affect the priority
898 REG_LIVE_LENGTH (regno) *= 2;
901 /* If the register is referenced exactly twice, meaning it is
902 set once and used once, indicate that the reference may be
903 replaced by the equivalence we computed above. If the
904 register is only used in one basic block, this can't succeed
905 or combine would have done it.
907 It would be nice to use "loop_depth * 2" in the compare
908 below. Unfortunately, LOOP_DEPTH need not be constant within
909 a basic block so this would be too complicated.
911 This case normally occurs when a parameter is read from
912 memory and then used exactly once, not in a loop. */
914 if (REG_N_REFS (regno) == 2
915 && REG_BASIC_BLOCK (regno) < 0
916 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
917 reg_equiv_replace[regno] = 1;
922 /* Now scan all regs killed in an insn to see if any of them are
923 registers only used that once. If so, see if we can replace the
924 reference with the equivalent from. If we can, delete the
925 initializing reference and this register will go away. If we
926 can't replace the reference, and the instruction is not in a
927 loop, then move the register initialization just before the use,
928 so that they are in the same basic block. */
931 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
935 /* Keep track of which basic block we are in. */
936 if (block + 1 < n_basic_blocks
937 && basic_block_head[block + 1] == insn)
940 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
942 if (GET_CODE (insn) == NOTE)
944 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
946 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
957 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
959 if (REG_NOTE_KIND (link) == REG_DEAD
960 /* Make sure this insn still refers to the register. */
961 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
963 int regno = REGNO (XEXP (link, 0));
966 if (! reg_equiv_replace[regno])
969 equiv_insn = reg_equiv_init_insn[regno];
971 if (validate_replace_rtx (regno_reg_rtx[regno],
972 reg_equiv_replacement[regno], insn))
974 remove_death (regno, insn);
975 REG_N_REFS (regno) = 0;
976 PUT_CODE (equiv_insn, NOTE);
977 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
978 NOTE_SOURCE_FILE (equiv_insn) = 0;
980 /* If we aren't in a loop, and there are no calls in
981 INSN or in the initialization of the register, then
982 move the initialization of the register to just
983 before INSN. Update the flow information. */
985 && GET_CODE (equiv_insn) == INSN
986 && GET_CODE (insn) == INSN
987 && REG_BASIC_BLOCK (regno) < 0)
991 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
992 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
994 PUT_CODE (equiv_insn, NOTE);
995 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
996 NOTE_SOURCE_FILE (equiv_insn) = 0;
997 REG_NOTES (equiv_insn) = 0;
1000 REG_BASIC_BLOCK (regno) = 0;
1002 REG_BASIC_BLOCK (regno) = block;
1003 REG_N_CALLS_CROSSED (regno) = 0;
1004 REG_LIVE_LENGTH (regno) = 2;
1006 if (block >= 0 && insn == basic_block_head[block])
1007 basic_block_head[block] = PREV_INSN (insn);
1009 for (l = 0; l < n_basic_blocks; l++)
1010 CLEAR_REGNO_REG_SET (basic_block_live_at_start[l], regno);
1017 /* Allocate hard regs to the pseudo regs used only within block number B.
1018 Only the pseudos that die but once can be handled. */
1027 int insn_number = 0;
1029 int max_uid = get_max_uid ();
1031 int no_conflict_combined_regno = -1;
1032 /* Counter to prevent allocating more SCRATCHes than can be stored
1034 int scratches_allocated = scratch_index;
1036 /* Count the instructions in the basic block. */
1038 insn = basic_block_end[b];
1041 if (GET_CODE (insn) != NOTE)
1042 if (++insn_count > max_uid)
1044 if (insn == basic_block_head[b])
1046 insn = PREV_INSN (insn);
1049 /* +2 to leave room for a post_mark_life at the last insn and for
1050 the birth of a CLOBBER in the first insn. */
1051 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1052 * sizeof (HARD_REG_SET));
1053 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1055 /* Initialize table of hardware registers currently live. */
1057 REG_SET_TO_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1059 /* This loop scans the instructions of the basic block
1060 and assigns quantities to registers.
1061 It computes which registers to tie. */
1063 insn = basic_block_head[b];
1066 register rtx body = PATTERN (insn);
1068 if (GET_CODE (insn) != NOTE)
1071 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1073 register rtx link, set;
1074 register int win = 0;
1075 register rtx r0, r1;
1076 int combined_regno = -1;
1078 int insn_code_number = recog_memoized (insn);
1080 this_insn_number = insn_number;
1083 if (insn_code_number >= 0)
1084 insn_extract (insn);
1085 which_alternative = -1;
1087 /* Is this insn suitable for tying two registers?
1088 If so, try doing that.
1089 Suitable insns are those with at least two operands and where
1090 operand 0 is an output that is a register that is not
1093 We can tie operand 0 with some operand that dies in this insn.
1094 First look for operands that are required to be in the same
1095 register as operand 0. If we find such, only try tying that
1096 operand or one that can be put into that operand if the
1097 operation is commutative. If we don't find an operand
1098 that is required to be in the same register as operand 0,
1099 we can tie with any operand.
1101 Subregs in place of regs are also ok.
1103 If tying is done, WIN is set nonzero. */
1105 if (insn_code_number >= 0
1106 #ifdef REGISTER_CONSTRAINTS
1107 && insn_n_operands[insn_code_number] > 1
1108 && insn_operand_constraint[insn_code_number][0][0] == '='
1109 && insn_operand_constraint[insn_code_number][0][1] != '&'
1111 && GET_CODE (PATTERN (insn)) == SET
1112 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1116 #ifdef REGISTER_CONSTRAINTS
1117 /* If non-negative, is an operand that must match operand 0. */
1118 int must_match_0 = -1;
1119 /* Counts number of alternatives that require a match with
1121 int n_matching_alts = 0;
1123 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1125 char *p = insn_operand_constraint[insn_code_number][i];
1126 int this_match = (requires_inout (p));
1128 n_matching_alts += this_match;
1129 if (this_match == insn_n_alternatives[insn_code_number])
1134 r0 = recog_operand[0];
1135 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1137 #ifdef REGISTER_CONSTRAINTS
1138 /* Skip this operand if we found an operand that
1139 must match operand 0 and this operand isn't it
1140 and can't be made to be it by commutativity. */
1142 if (must_match_0 >= 0 && i != must_match_0
1143 && ! (i == must_match_0 + 1
1144 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1145 && ! (i == must_match_0 - 1
1146 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1149 /* Likewise if each alternative has some operand that
1150 must match operand zero. In that case, skip any
1151 operand that doesn't list operand 0 since we know that
1152 the operand always conflicts with operand 0. We
1153 ignore commutatity in this case to keep things simple. */
1154 if (n_matching_alts == insn_n_alternatives[insn_code_number]
1155 && (0 == requires_inout
1156 (insn_operand_constraint[insn_code_number][i])))
1160 r1 = recog_operand[i];
1162 /* If the operand is an address, find a register in it.
1163 There may be more than one register, but we only try one
1166 #ifdef REGISTER_CONSTRAINTS
1167 insn_operand_constraint[insn_code_number][i][0] == 'p'
1169 insn_operand_address_p[insn_code_number][i]
1172 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1175 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1177 /* We have two priorities for hard register preferences.
1178 If we have a move insn or an insn whose first input
1179 can only be in the same register as the output, give
1180 priority to an equivalence found from that insn. */
1182 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1183 #ifdef REGISTER_CONSTRAINTS
1184 || (r1 == recog_operand[i] && must_match_0 >= 0)
1188 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1189 win = combine_regs (r1, r0, may_save_copy,
1190 insn_number, insn, 0);
1197 /* Recognize an insn sequence with an ultimate result
1198 which can safely overlap one of the inputs.
1199 The sequence begins with a CLOBBER of its result,
1200 and ends with an insn that copies the result to itself
1201 and has a REG_EQUAL note for an equivalent formula.
1202 That note indicates what the inputs are.
1203 The result and the input can overlap if each insn in
1204 the sequence either doesn't mention the input
1205 or has a REG_NO_CONFLICT note to inhibit the conflict.
1207 We do the combining test at the CLOBBER so that the
1208 destination register won't have had a quantity number
1209 assigned, since that would prevent combining. */
1211 if (GET_CODE (PATTERN (insn)) == CLOBBER
1212 && (r0 = XEXP (PATTERN (insn), 0),
1213 GET_CODE (r0) == REG)
1214 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1215 && XEXP (link, 0) != 0
1216 && GET_CODE (XEXP (link, 0)) == INSN
1217 && (set = single_set (XEXP (link, 0))) != 0
1218 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1219 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1222 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1223 /* Check that we have such a sequence. */
1224 && no_conflict_p (insn, r0, r1))
1225 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1226 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1227 && (r1 = XEXP (XEXP (note, 0), 0),
1228 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1229 && no_conflict_p (insn, r0, r1))
1230 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1232 /* Here we care if the operation to be computed is
1234 else if ((GET_CODE (XEXP (note, 0)) == EQ
1235 || GET_CODE (XEXP (note, 0)) == NE
1236 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1237 && (r1 = XEXP (XEXP (note, 0), 1),
1238 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1239 && no_conflict_p (insn, r0, r1))
1240 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1242 /* If we did combine something, show the register number
1243 in question so that we know to ignore its death. */
1245 no_conflict_combined_regno = REGNO (r1);
1248 /* If registers were just tied, set COMBINED_REGNO
1249 to the number of the register used in this insn
1250 that was tied to the register set in this insn.
1251 This register's qty should not be "killed". */
1255 while (GET_CODE (r1) == SUBREG)
1256 r1 = SUBREG_REG (r1);
1257 combined_regno = REGNO (r1);
1260 /* Mark the death of everything that dies in this instruction,
1261 except for anything that was just combined. */
1263 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1264 if (REG_NOTE_KIND (link) == REG_DEAD
1265 && GET_CODE (XEXP (link, 0)) == REG
1266 && combined_regno != REGNO (XEXP (link, 0))
1267 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1268 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1269 wipe_dead_reg (XEXP (link, 0), 0);
1271 /* Allocate qty numbers for all registers local to this block
1272 that are born (set) in this instruction.
1273 A pseudo that already has a qty is not changed. */
1275 note_stores (PATTERN (insn), reg_is_set);
1277 /* If anything is set in this insn and then unused, mark it as dying
1278 after this insn, so it will conflict with our outputs. This
1279 can't match with something that combined, and it doesn't matter
1280 if it did. Do this after the calls to reg_is_set since these
1281 die after, not during, the current insn. */
1283 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1284 if (REG_NOTE_KIND (link) == REG_UNUSED
1285 && GET_CODE (XEXP (link, 0)) == REG)
1286 wipe_dead_reg (XEXP (link, 0), 1);
1288 /* Allocate quantities for any SCRATCH operands of this insn. */
1290 if (insn_code_number >= 0)
1291 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1292 if (GET_CODE (recog_operand[i]) == SCRATCH
1293 && scratches_allocated++ < scratch_list_length)
1294 alloc_qty_for_scratch (recog_operand[i], i, insn,
1295 insn_code_number, insn_number);
1297 /* If this is an insn that has a REG_RETVAL note pointing at a
1298 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1299 block, so clear any register number that combined within it. */
1300 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1301 && GET_CODE (XEXP (note, 0)) == INSN
1302 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1303 no_conflict_combined_regno = -1;
1306 /* Set the registers live after INSN_NUMBER. Note that we never
1307 record the registers live before the block's first insn, since no
1308 pseudos we care about are live before that insn. */
1310 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1311 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1313 if (insn == basic_block_end[b])
1316 insn = NEXT_INSN (insn);
1319 /* Now every register that is local to this basic block
1320 should have been given a quantity, or else -1 meaning ignore it.
1321 Every quantity should have a known birth and death.
1323 Order the qtys so we assign them registers in order of the
1324 number of suggested registers they need so we allocate those with
1325 the most restrictive needs first. */
1327 qty_order = (int *) alloca (next_qty * sizeof (int));
1328 for (i = 0; i < next_qty; i++)
1331 #define EXCHANGE(I1, I2) \
1332 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1337 /* Make qty_order[2] be the one to allocate last. */
1338 if (qty_sugg_compare (0, 1) > 0)
1340 if (qty_sugg_compare (1, 2) > 0)
1343 /* ... Fall through ... */
1345 /* Put the best one to allocate in qty_order[0]. */
1346 if (qty_sugg_compare (0, 1) > 0)
1349 /* ... Fall through ... */
1353 /* Nothing to do here. */
1357 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1360 /* Try to put each quantity in a suggested physical register, if it has one.
1361 This may cause registers to be allocated that otherwise wouldn't be, but
1362 this seems acceptable in local allocation (unlike global allocation). */
1363 for (i = 0; i < next_qty; i++)
1366 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1367 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1368 0, 1, qty_birth[q], qty_death[q]);
1370 qty_phys_reg[q] = -1;
1373 /* Order the qtys so we assign them registers in order of
1374 decreasing length of life. Normally call qsort, but if we
1375 have only a very small number of quantities, sort them ourselves. */
1377 for (i = 0; i < next_qty; i++)
1380 #define EXCHANGE(I1, I2) \
1381 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1386 /* Make qty_order[2] be the one to allocate last. */
1387 if (qty_compare (0, 1) > 0)
1389 if (qty_compare (1, 2) > 0)
1392 /* ... Fall through ... */
1394 /* Put the best one to allocate in qty_order[0]. */
1395 if (qty_compare (0, 1) > 0)
1398 /* ... Fall through ... */
1402 /* Nothing to do here. */
1406 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1409 /* Now for each qty that is not a hardware register,
1410 look for a hardware register to put it in.
1411 First try the register class that is cheapest for this qty,
1412 if there is more than one class. */
1414 for (i = 0; i < next_qty; i++)
1417 if (qty_phys_reg[q] < 0)
1419 #ifdef INSN_SCHEDULING
1420 /* These values represent the adjusted lifetime of a qty so
1421 that it conflicts with qtys which appear near the start/end
1422 of this qty's lifetime.
1424 The purpose behind extending the lifetime of this qty is to
1425 discourage the register allocator from creating false
1428 The adjustment by the value +-3 indicates precisely that
1429 this qty conflicts with qtys in the instructions immediately
1430 before and after the lifetime of this qty.
1432 Experiments have shown that higher values tend to hurt
1433 overall code performance.
1435 If allocation using the extended lifetime fails we will try
1436 again with the qty's unadjusted lifetime. */
1437 int fake_birth = MAX (0, qty_birth[q] - 3);
1438 int fake_death = MIN (insn_number * 2 + 1, qty_death[q] + 3);
1441 if (N_REG_CLASSES > 1)
1443 #ifdef INSN_SCHEDULING
1444 /* We try to avoid using hard registers allocated to qtys which
1445 are born immediately after this qty or die immediately before
1448 This optimization is only appropriate when we will run
1449 a scheduling pass after reload and we are not optimizing
1451 if (flag_schedule_insns_after_reload
1453 && !SMALL_REGISTER_CLASSES)
1456 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1457 qty_mode[q], q, 0, 0,
1458 fake_birth, fake_death);
1459 if (qty_phys_reg[q] >= 0)
1463 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1464 qty_mode[q], q, 0, 0,
1465 qty_birth[q], qty_death[q]);
1466 if (qty_phys_reg[q] >= 0)
1470 #ifdef INSN_SCHEDULING
1471 /* Similarly, avoid false dependencies. */
1472 if (flag_schedule_insns_after_reload
1474 && !SMALL_REGISTER_CLASSES
1475 && qty_alternate_class[q] != NO_REGS)
1476 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1477 qty_mode[q], q, 0, 0,
1478 fake_birth, fake_death);
1480 if (qty_alternate_class[q] != NO_REGS)
1481 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1482 qty_mode[q], q, 0, 0,
1483 qty_birth[q], qty_death[q]);
1487 /* Now propagate the register assignments
1488 to the pseudo regs belonging to the qtys. */
1490 for (q = 0; q < next_qty; q++)
1491 if (qty_phys_reg[q] >= 0)
1493 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1494 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1495 if (qty_scratch_rtx[q])
1497 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1499 qty_scratch_rtx[q] = gen_rtx_REG (GET_MODE (qty_scratch_rtx[q]),
1501 scratch_block[scratch_index] = b;
1502 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1508 /* Compare two quantities' priority for getting real registers.
1509 We give shorter-lived quantities higher priority.
1510 Quantities with more references are also preferred, as are quantities that
1511 require multiple registers. This is the identical prioritization as
1512 done by global-alloc.
1514 We used to give preference to registers with *longer* lives, but using
1515 the same algorithm in both local- and global-alloc can speed up execution
1516 of some programs by as much as a factor of three! */
1518 /* Note that the quotient will never be bigger than
1519 the value of floor_log2 times the maximum number of
1520 times a register can occur in one insn (surely less than 100).
1521 Multiplying this by 10000 can't overflow.
1522 QTY_CMP_PRI is also used by qty_sugg_compare. */
1524 #define QTY_CMP_PRI(q) \
1525 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1526 / (qty_death[q] - qty_birth[q])) * 10000))
1529 qty_compare (q1, q2)
1532 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1536 qty_compare_1 (q1p, q2p)
1537 const GENERIC_PTR q1p;
1538 const GENERIC_PTR q2p;
1540 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1541 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1546 /* If qtys are equally good, sort by qty number,
1547 so that the results of qsort leave nothing to chance. */
1551 /* Compare two quantities' priority for getting real registers. This version
1552 is called for quantities that have suggested hard registers. First priority
1553 goes to quantities that have copy preferences, then to those that have
1554 normal preferences. Within those groups, quantities with the lower
1555 number of preferences have the highest priority. Of those, we use the same
1556 algorithm as above. */
1558 #define QTY_CMP_SUGG(q) \
1559 (qty_phys_num_copy_sugg[q] \
1560 ? qty_phys_num_copy_sugg[q] \
1561 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1564 qty_sugg_compare (q1, q2)
1567 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1572 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1576 qty_sugg_compare_1 (q1p, q2p)
1577 const GENERIC_PTR q1p;
1578 const GENERIC_PTR q2p;
1580 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1581 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1586 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1590 /* If qtys are equally good, sort by qty number,
1591 so that the results of qsort leave nothing to chance. */
1598 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1599 Returns 1 if have done so, or 0 if cannot.
1601 Combining registers means marking them as having the same quantity
1602 and adjusting the offsets within the quantity if either of
1605 We don't actually combine a hard reg with a pseudo; instead
1606 we just record the hard reg as the suggestion for the pseudo's quantity.
1607 If we really combined them, we could lose if the pseudo lives
1608 across an insn that clobbers the hard reg (eg, movstr).
1610 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1611 there is no REG_DEAD note on INSN. This occurs during the processing
1612 of REG_NO_CONFLICT blocks.
1614 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1615 SETREG or if the input and output must share a register.
1616 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1618 There are elaborate checks for the validity of combining. */
1622 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1623 rtx usedreg, setreg;
1629 register int ureg, sreg;
1630 register int offset = 0;
1634 /* Determine the numbers and sizes of registers being used. If a subreg
1635 is present that does not change the entire register, don't consider
1636 this a copy insn. */
1638 while (GET_CODE (usedreg) == SUBREG)
1640 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1642 offset += SUBREG_WORD (usedreg);
1643 usedreg = SUBREG_REG (usedreg);
1645 if (GET_CODE (usedreg) != REG)
1647 ureg = REGNO (usedreg);
1648 usize = REG_SIZE (usedreg);
1650 while (GET_CODE (setreg) == SUBREG)
1652 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1654 offset -= SUBREG_WORD (setreg);
1655 setreg = SUBREG_REG (setreg);
1657 if (GET_CODE (setreg) != REG)
1659 sreg = REGNO (setreg);
1660 ssize = REG_SIZE (setreg);
1662 /* If UREG is a pseudo-register that hasn't already been assigned a
1663 quantity number, it means that it is not local to this block or dies
1664 more than once. In either event, we can't do anything with it. */
1665 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1666 /* Do not combine registers unless one fits within the other. */
1667 || (offset > 0 && usize + offset > ssize)
1668 || (offset < 0 && usize + offset < ssize)
1669 /* Do not combine with a smaller already-assigned object
1670 if that smaller object is already combined with something bigger. */
1671 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1672 && usize < qty_size[reg_qty[ureg]])
1673 /* Can't combine if SREG is not a register we can allocate. */
1674 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1675 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1676 These have already been taken care of. This probably wouldn't
1677 combine anyway, but don't take any chances. */
1678 || (ureg >= FIRST_PSEUDO_REGISTER
1679 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1680 /* Don't tie something to itself. In most cases it would make no
1681 difference, but it would screw up if the reg being tied to itself
1682 also dies in this insn. */
1684 /* Don't try to connect two different hardware registers. */
1685 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1686 /* Don't connect two different machine modes if they have different
1687 implications as to which registers may be used. */
1688 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1691 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1692 qty_phys_sugg for the pseudo instead of tying them.
1694 Return "failure" so that the lifespan of UREG is terminated here;
1695 that way the two lifespans will be disjoint and nothing will prevent
1696 the pseudo reg from being given this hard reg. */
1698 if (ureg < FIRST_PSEUDO_REGISTER)
1700 /* Allocate a quantity number so we have a place to put our
1702 if (reg_qty[sreg] == -2)
1703 reg_is_born (setreg, 2 * insn_number);
1705 if (reg_qty[sreg] >= 0)
1708 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1710 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1711 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1713 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1715 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1716 qty_phys_num_sugg[reg_qty[sreg]]++;
1722 /* Similarly for SREG a hard register and UREG a pseudo register. */
1724 if (sreg < FIRST_PSEUDO_REGISTER)
1727 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1729 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1730 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1732 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1734 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1735 qty_phys_num_sugg[reg_qty[ureg]]++;
1740 /* At this point we know that SREG and UREG are both pseudos.
1741 Do nothing if SREG already has a quantity or is a register that we
1743 if (reg_qty[sreg] >= -1
1744 /* If we are not going to let any regs live across calls,
1745 don't tie a call-crossing reg to a non-call-crossing reg. */
1746 || (current_function_has_nonlocal_label
1747 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1748 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1751 /* We don't already know about SREG, so tie it to UREG
1752 if this is the last use of UREG, provided the classes they want
1755 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1756 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1758 /* Add SREG to UREG's quantity. */
1759 sqty = reg_qty[ureg];
1760 reg_qty[sreg] = sqty;
1761 reg_offset[sreg] = reg_offset[ureg] + offset;
1762 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1763 qty_first_reg[sqty] = sreg;
1765 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1766 update_qty_class (sqty, sreg);
1768 /* Update info about quantity SQTY. */
1769 qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg);
1770 qty_n_refs[sqty] += REG_N_REFS (sreg);
1775 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1776 reg_offset[i] -= offset;
1778 qty_size[sqty] = ssize;
1779 qty_mode[sqty] = GET_MODE (setreg);
1788 /* Return 1 if the preferred class of REG allows it to be tied
1789 to a quantity or register whose class is CLASS.
1790 True if REG's reg class either contains or is contained in CLASS. */
1793 reg_meets_class_p (reg, class)
1795 enum reg_class class;
1797 register enum reg_class rclass = reg_preferred_class (reg);
1798 return (reg_class_subset_p (rclass, class)
1799 || reg_class_subset_p (class, rclass));
1802 /* Update the class of QTY assuming that REG is being tied to it. */
1805 update_qty_class (qty, reg)
1809 enum reg_class rclass = reg_preferred_class (reg);
1810 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1811 qty_min_class[qty] = rclass;
1813 rclass = reg_alternate_class (reg);
1814 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1815 qty_alternate_class[qty] = rclass;
1817 if (REG_CHANGES_SIZE (reg))
1818 qty_changes_size[qty] = 1;
1821 /* Handle something which alters the value of an rtx REG.
1823 REG is whatever is set or clobbered. SETTER is the rtx that
1824 is modifying the register.
1826 If it is not really a register, we do nothing.
1827 The file-global variables `this_insn' and `this_insn_number'
1828 carry info from `block_alloc'. */
1831 reg_is_set (reg, setter)
1835 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1836 a hard register. These may actually not exist any more. */
1838 if (GET_CODE (reg) != SUBREG
1839 && GET_CODE (reg) != REG)
1842 /* Mark this register as being born. If it is used in a CLOBBER, mark
1843 it as being born halfway between the previous insn and this insn so that
1844 it conflicts with our inputs but not the outputs of the previous insn. */
1846 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1849 /* Handle beginning of the life of register REG.
1850 BIRTH is the index at which this is happening. */
1853 reg_is_born (reg, birth)
1859 if (GET_CODE (reg) == SUBREG)
1860 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1862 regno = REGNO (reg);
1864 if (regno < FIRST_PSEUDO_REGISTER)
1866 mark_life (regno, GET_MODE (reg), 1);
1868 /* If the register was to have been born earlier that the present
1869 insn, mark it as live where it is actually born. */
1870 if (birth < 2 * this_insn_number)
1871 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1875 if (reg_qty[regno] == -2)
1876 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1878 /* If this register has a quantity number, show that it isn't dead. */
1879 if (reg_qty[regno] >= 0)
1880 qty_death[reg_qty[regno]] = -1;
1884 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1885 REG is an output that is dying (i.e., it is never used), otherwise it
1886 is an input (the normal case).
1887 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1890 wipe_dead_reg (reg, output_p)
1894 register int regno = REGNO (reg);
1896 /* If this insn has multiple results,
1897 and the dead reg is used in one of the results,
1898 extend its life to after this insn,
1899 so it won't get allocated together with any other result of this insn. */
1900 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
1901 && !single_set (this_insn))
1904 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
1906 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
1907 if (GET_CODE (set) == SET
1908 && GET_CODE (SET_DEST (set)) != REG
1909 && !rtx_equal_p (reg, SET_DEST (set))
1910 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1915 /* If this register is used in an auto-increment address, then extend its
1916 life to after this insn, so that it won't get allocated together with
1917 the result of this insn. */
1918 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
1921 if (regno < FIRST_PSEUDO_REGISTER)
1923 mark_life (regno, GET_MODE (reg), 0);
1925 /* If a hard register is dying as an output, mark it as in use at
1926 the beginning of this insn (the above statement would cause this
1929 post_mark_life (regno, GET_MODE (reg), 1,
1930 2 * this_insn_number, 2 * this_insn_number+ 1);
1933 else if (reg_qty[regno] >= 0)
1934 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
1937 /* Find a block of SIZE words of hard regs in reg_class CLASS
1938 that can hold something of machine-mode MODE
1939 (but actually we test only the first of the block for holding MODE)
1940 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1941 and return the number of the first of them.
1942 Return -1 if such a block cannot be found.
1943 If QTY crosses calls, insist on a register preserved by calls,
1944 unless ACCEPT_CALL_CLOBBERED is nonzero.
1946 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1947 register is available. If not, return -1. */
1950 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
1951 born_index, dead_index)
1952 enum reg_class class;
1953 enum machine_mode mode;
1955 int accept_call_clobbered;
1956 int just_try_suggested;
1957 int born_index, dead_index;
1959 register int i, ins;
1961 register /* Declare it register if it's a scalar. */
1963 HARD_REG_SET used, first_used;
1964 #ifdef ELIMINABLE_REGS
1965 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
1968 /* Validate our parameters. */
1969 if (born_index < 0 || born_index > dead_index)
1972 /* Don't let a pseudo live in a reg across a function call
1973 if we might get a nonlocal goto. */
1974 if (current_function_has_nonlocal_label
1975 && qty_n_calls_crossed[qty] > 0)
1978 if (accept_call_clobbered)
1979 COPY_HARD_REG_SET (used, call_fixed_reg_set);
1980 else if (qty_n_calls_crossed[qty] == 0)
1981 COPY_HARD_REG_SET (used, fixed_reg_set);
1983 COPY_HARD_REG_SET (used, call_used_reg_set);
1985 if (accept_call_clobbered)
1986 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
1988 for (ins = born_index; ins < dead_index; ins++)
1989 IOR_HARD_REG_SET (used, regs_live_at[ins]);
1991 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
1993 /* Don't use the frame pointer reg in local-alloc even if
1994 we may omit the frame pointer, because if we do that and then we
1995 need a frame pointer, reload won't know how to move the pseudo
1996 to another hard reg. It can move only regs made by global-alloc.
1998 This is true of any register that can be eliminated. */
1999 #ifdef ELIMINABLE_REGS
2000 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
2001 SET_HARD_REG_BIT (used, eliminables[i].from);
2002 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2003 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2004 that it might be eliminated into. */
2005 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2008 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2011 #ifdef CLASS_CANNOT_CHANGE_SIZE
2012 if (qty_changes_size[qty])
2013 IOR_HARD_REG_SET (used,
2014 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
2017 /* Normally, the registers that can be used for the first register in
2018 a multi-register quantity are the same as those that can be used for
2019 subsequent registers. However, if just trying suggested registers,
2020 restrict our consideration to them. If there are copy-suggested
2021 register, try them. Otherwise, try the arithmetic-suggested
2023 COPY_HARD_REG_SET (first_used, used);
2025 if (just_try_suggested)
2027 if (qty_phys_num_copy_sugg[qty] != 0)
2028 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2030 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2033 /* If all registers are excluded, we can't do anything. */
2034 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2036 /* If at least one would be suitable, test each hard reg. */
2038 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2040 #ifdef REG_ALLOC_ORDER
2041 int regno = reg_alloc_order[i];
2045 if (! TEST_HARD_REG_BIT (first_used, regno)
2046 && HARD_REGNO_MODE_OK (regno, mode))
2049 register int size1 = HARD_REGNO_NREGS (regno, mode);
2050 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2053 /* Mark that this register is in use between its birth and death
2055 post_mark_life (regno, mode, 1, born_index, dead_index);
2058 #ifndef REG_ALLOC_ORDER
2059 i += j; /* Skip starting points we know will lose */
2066 /* If we are just trying suggested register, we have just tried copy-
2067 suggested registers, and there are arithmetic-suggested registers,
2070 /* If it would be profitable to allocate a call-clobbered register
2071 and save and restore it around calls, do that. */
2072 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2073 && qty_phys_num_sugg[qty] != 0)
2075 /* Don't try the copy-suggested regs again. */
2076 qty_phys_num_copy_sugg[qty] = 0;
2077 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2078 born_index, dead_index);
2081 /* We need not check to see if the current function has nonlocal
2082 labels because we don't put any pseudos that are live over calls in
2083 registers in that case. */
2085 if (! accept_call_clobbered
2086 && flag_caller_saves
2087 && ! just_try_suggested
2088 && qty_n_calls_crossed[qty] != 0
2089 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2091 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2093 caller_save_needed = 1;
2099 /* Mark that REGNO with machine-mode MODE is live starting from the current
2100 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2104 mark_life (regno, mode, life)
2106 enum machine_mode mode;
2109 register int j = HARD_REGNO_NREGS (regno, mode);
2112 SET_HARD_REG_BIT (regs_live, regno + j);
2115 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2118 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2119 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2120 to insn number DEATH (exclusive). */
2123 post_mark_life (regno, mode, life, birth, death)
2125 enum machine_mode mode;
2126 int life, birth, death;
2128 register int j = HARD_REGNO_NREGS (regno, mode);
2130 register /* Declare it register if it's a scalar. */
2132 HARD_REG_SET this_reg;
2134 CLEAR_HARD_REG_SET (this_reg);
2136 SET_HARD_REG_BIT (this_reg, regno + j);
2139 while (birth < death)
2141 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2145 while (birth < death)
2147 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2152 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2153 is the register being clobbered, and R1 is a register being used in
2154 the equivalent expression.
2156 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2157 in which it is used, return 1.
2159 Otherwise, return 0. */
2162 no_conflict_p (insn, r0, r1)
2166 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2169 /* If R1 is a hard register, return 0 since we handle this case
2170 when we scan the insns that actually use it. */
2173 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2174 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2175 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2178 last = XEXP (note, 0);
2180 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2181 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2183 if (find_reg_note (p, REG_DEAD, r1))
2186 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2187 some earlier optimization pass has inserted instructions into
2188 the sequence, and it is not safe to perform this optimization.
2189 Note that emit_no_conflict_block always ensures that this is
2190 true when these sequences are created. */
2191 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2198 #ifdef REGISTER_CONSTRAINTS
2200 /* Return the number of alternatives for which the constraint string P
2201 indicates that the operand must be equal to operand 0 and that no register
2210 int reg_allowed = 0;
2211 int num_matching_alts = 0;
2216 case '=': case '+': case '?':
2217 case '#': case '&': case '!':
2219 case '1': case '2': case '3': case '4':
2220 case 'm': case '<': case '>': case 'V': case 'o':
2221 case 'E': case 'F': case 'G': case 'H':
2222 case 's': case 'i': case 'n':
2223 case 'I': case 'J': case 'K': case 'L':
2224 case 'M': case 'N': case 'O': case 'P':
2225 #ifdef EXTRA_CONSTRAINT
2226 case 'Q': case 'R': case 'S': case 'T': case 'U':
2229 /* These don't say anything we care about. */
2233 if (found_zero && ! reg_allowed)
2234 num_matching_alts++;
2236 found_zero = reg_allowed = 0;
2250 if (found_zero && ! reg_allowed)
2251 num_matching_alts++;
2253 return num_matching_alts;
2255 #endif /* REGISTER_CONSTRAINTS */
2258 dump_local_alloc (file)
2262 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2263 if (reg_renumber[i] != -1)
2264 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);
OSDN Git Service
