1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000 Free Software Foundation, Inc.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
31 #include "insn-flags.h"
32 #include "insn-codes.h"
33 #include "insn-config.h"
38 static void store_fixed_bit_field PARAMS ((rtx, unsigned HOST_WIDE_INT,
39 unsigned HOST_WIDE_INT,
40 unsigned HOST_WIDE_INT, rtx,
42 static void store_split_bit_field PARAMS ((rtx, unsigned HOST_WIDE_INT,
43 unsigned HOST_WIDE_INT, rtx,
45 static rtx extract_fixed_bit_field PARAMS ((enum machine_mode, rtx,
46 unsigned HOST_WIDE_INT,
47 unsigned HOST_WIDE_INT,
48 unsigned HOST_WIDE_INT,
49 rtx, int, unsigned int));
50 static rtx mask_rtx PARAMS ((enum machine_mode, int,
52 static rtx lshift_value PARAMS ((enum machine_mode, rtx,
54 static rtx extract_split_bit_field PARAMS ((rtx, unsigned HOST_WIDE_INT,
55 unsigned HOST_WIDE_INT, int,
57 static void do_cmp_and_jump PARAMS ((rtx, rtx, enum rtx_code,
58 enum machine_mode, rtx));
60 /* Non-zero means divides or modulus operations are relatively cheap for
61 powers of two, so don't use branches; emit the operation instead.
62 Usually, this will mean that the MD file will emit non-branch
65 static int sdiv_pow2_cheap, smod_pow2_cheap;
67 #ifndef SLOW_UNALIGNED_ACCESS
68 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
71 /* For compilers that support multiple targets with different word sizes,
72 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
73 is the H8/300(H) compiler. */
75 #ifndef MAX_BITS_PER_WORD
76 #define MAX_BITS_PER_WORD BITS_PER_WORD
79 /* Cost of various pieces of RTL. Note that some of these are indexed by
80 shift count and some by mode. */
81 static int add_cost, negate_cost, zero_cost;
82 static int shift_cost[MAX_BITS_PER_WORD];
83 static int shiftadd_cost[MAX_BITS_PER_WORD];
84 static int shiftsub_cost[MAX_BITS_PER_WORD];
85 static int mul_cost[NUM_MACHINE_MODES];
86 static int div_cost[NUM_MACHINE_MODES];
87 static int mul_widen_cost[NUM_MACHINE_MODES];
88 static int mul_highpart_cost[NUM_MACHINE_MODES];
93 /* This is "some random pseudo register" for purposes of calling recog
94 to see what insns exist. */
95 rtx reg = gen_rtx_REG (word_mode, 10000);
96 rtx shift_insn, shiftadd_insn, shiftsub_insn;
99 enum machine_mode mode, wider_mode;
103 reg = gen_rtx_REG (word_mode, 10000);
105 zero_cost = rtx_cost (const0_rtx, 0);
106 add_cost = rtx_cost (gen_rtx_PLUS (word_mode, reg, reg), SET);
108 shift_insn = emit_insn (gen_rtx_SET (VOIDmode, reg,
109 gen_rtx_ASHIFT (word_mode, reg,
113 = emit_insn (gen_rtx_SET (VOIDmode, reg,
114 gen_rtx_PLUS (word_mode,
115 gen_rtx_MULT (word_mode,
120 = emit_insn (gen_rtx_SET (VOIDmode, reg,
121 gen_rtx_MINUS (word_mode,
122 gen_rtx_MULT (word_mode,
129 shiftadd_cost[0] = shiftsub_cost[0] = add_cost;
131 for (m = 1; m < MAX_BITS_PER_WORD; m++)
133 shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000;
135 XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m);
136 if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0)
137 shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET);
139 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1)
140 = GEN_INT ((HOST_WIDE_INT) 1 << m);
141 if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0)
142 shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET);
144 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1)
145 = GEN_INT ((HOST_WIDE_INT) 1 << m);
146 if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0)
147 shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET);
150 negate_cost = rtx_cost (gen_rtx_NEG (word_mode, reg), SET);
153 = (rtx_cost (gen_rtx_DIV (word_mode, reg, GEN_INT (32)), SET)
156 = (rtx_cost (gen_rtx_MOD (word_mode, reg, GEN_INT (32)), SET)
159 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
161 mode = GET_MODE_WIDER_MODE (mode))
163 reg = gen_rtx_REG (mode, 10000);
164 div_cost[(int) mode] = rtx_cost (gen_rtx_UDIV (mode, reg, reg), SET);
165 mul_cost[(int) mode] = rtx_cost (gen_rtx_MULT (mode, reg, reg), SET);
166 wider_mode = GET_MODE_WIDER_MODE (mode);
167 if (wider_mode != VOIDmode)
169 mul_widen_cost[(int) wider_mode]
170 = rtx_cost (gen_rtx_MULT (wider_mode,
171 gen_rtx_ZERO_EXTEND (wider_mode, reg),
172 gen_rtx_ZERO_EXTEND (wider_mode, reg)),
174 mul_highpart_cost[(int) mode]
175 = rtx_cost (gen_rtx_TRUNCATE
177 gen_rtx_LSHIFTRT (wider_mode,
178 gen_rtx_MULT (wider_mode,
183 GEN_INT (GET_MODE_BITSIZE (mode)))),
191 /* Return an rtx representing minus the value of X.
192 MODE is the intended mode of the result,
193 useful if X is a CONST_INT. */
197 enum machine_mode mode;
200 rtx result = simplify_unary_operation (NEG, mode, x, mode);
203 result = expand_unop (mode, neg_optab, x, NULL_RTX, 0);
208 /* Generate code to store value from rtx VALUE
209 into a bit-field within structure STR_RTX
210 containing BITSIZE bits starting at bit BITNUM.
211 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
212 ALIGN is the alignment that STR_RTX is known to have.
213 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
215 /* ??? Note that there are two different ideas here for how
216 to determine the size to count bits within, for a register.
217 One is BITS_PER_WORD, and the other is the size of operand 3
220 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
221 else, we use the mode of operand 3. */
224 store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size)
226 unsigned HOST_WIDE_INT bitsize;
227 unsigned HOST_WIDE_INT bitnum;
228 enum machine_mode fieldmode;
231 HOST_WIDE_INT total_size;
234 = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
235 unsigned HOST_WIDE_INT offset = bitnum / unit;
236 unsigned HOST_WIDE_INT bitpos = bitnum % unit;
237 register rtx op0 = str_rtx;
239 unsigned HOST_WIDE_INT insv_bitsize;
240 enum machine_mode op_mode;
242 op_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
243 if (op_mode == VOIDmode)
245 insv_bitsize = GET_MODE_BITSIZE (op_mode);
248 /* Discount the part of the structure before the desired byte.
249 We need to know how many bytes are safe to reference after it. */
251 total_size -= (bitpos / BIGGEST_ALIGNMENT
252 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
254 while (GET_CODE (op0) == SUBREG)
256 /* The following line once was done only if WORDS_BIG_ENDIAN,
257 but I think that is a mistake. WORDS_BIG_ENDIAN is
258 meaningful at a much higher level; when structures are copied
259 between memory and regs, the higher-numbered regs
260 always get higher addresses. */
261 offset += SUBREG_WORD (op0);
262 /* We used to adjust BITPOS here, but now we do the whole adjustment
263 right after the loop. */
264 op0 = SUBREG_REG (op0);
267 /* Make sure we are playing with integral modes. Pun with subregs
270 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
271 if (imode != GET_MODE (op0))
273 if (GET_CODE (op0) == MEM)
274 op0 = change_address (op0, imode, NULL_RTX);
275 else if (imode != BLKmode)
276 op0 = gen_lowpart (imode, op0);
282 /* If OP0 is a register, BITPOS must count within a word.
283 But as we have it, it counts within whatever size OP0 now has.
284 On a bigendian machine, these are not the same, so convert. */
286 && GET_CODE (op0) != MEM
287 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
288 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
290 value = protect_from_queue (value, 0);
293 value = force_not_mem (value);
295 if ((GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
296 || (GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode)
297 && GET_MODE_SIZE (fieldmode) != 0))
298 && (GET_CODE (op0) != MEM
299 || ! SLOW_UNALIGNED_ACCESS (fieldmode, align)
300 || (offset * BITS_PER_UNIT % bitsize == 0
301 && align % GET_MODE_BITSIZE (fieldmode) == 0))
302 && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0)
303 && bitsize == GET_MODE_BITSIZE (fieldmode))
305 /* Storing in a full-word or multi-word field in a register
306 can be done with just SUBREG. Also, storing in the entire object
307 can be done with just SUBREG. */
308 if (GET_MODE (op0) != fieldmode)
310 if (GET_CODE (op0) == SUBREG)
312 if (GET_MODE (SUBREG_REG (op0)) == fieldmode
313 || GET_MODE_CLASS (fieldmode) == MODE_INT
314 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT)
315 op0 = SUBREG_REG (op0);
317 /* Else we've got some float mode source being extracted into
318 a different float mode destination -- this combination of
319 subregs results in Severe Tire Damage. */
322 if (GET_CODE (op0) == REG)
323 op0 = gen_rtx_SUBREG (fieldmode, op0, offset);
325 op0 = change_address (op0, fieldmode,
326 plus_constant (XEXP (op0, 0), offset));
328 emit_move_insn (op0, value);
332 /* Storing an lsb-aligned field in a register
333 can be done with a movestrict instruction. */
335 if (GET_CODE (op0) != MEM
336 && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0)
337 && bitsize == GET_MODE_BITSIZE (fieldmode)
338 && (movstrict_optab->handlers[(int) fieldmode].insn_code
339 != CODE_FOR_nothing))
341 int icode = movstrict_optab->handlers[(int) fieldmode].insn_code;
343 /* Get appropriate low part of the value being stored. */
344 if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG)
345 value = gen_lowpart (fieldmode, value);
346 else if (!(GET_CODE (value) == SYMBOL_REF
347 || GET_CODE (value) == LABEL_REF
348 || GET_CODE (value) == CONST))
349 value = convert_to_mode (fieldmode, value, 0);
351 if (! (*insn_data[icode].operand[1].predicate) (value, fieldmode))
352 value = copy_to_mode_reg (fieldmode, value);
354 if (GET_CODE (op0) == SUBREG)
356 if (GET_MODE (SUBREG_REG (op0)) == fieldmode
357 || GET_MODE_CLASS (fieldmode) == MODE_INT
358 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT)
359 op0 = SUBREG_REG (op0);
361 /* Else we've got some float mode source being extracted into
362 a different float mode destination -- this combination of
363 subregs results in Severe Tire Damage. */
367 emit_insn (GEN_FCN (icode)
368 (gen_rtx_SUBREG (fieldmode, op0, offset), value));
373 /* Handle fields bigger than a word. */
375 if (bitsize > BITS_PER_WORD)
377 /* Here we transfer the words of the field
378 in the order least significant first.
379 This is because the most significant word is the one which may
381 However, only do that if the value is not BLKmode. */
383 unsigned int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode;
384 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
387 /* This is the mode we must force value to, so that there will be enough
388 subwords to extract. Note that fieldmode will often (always?) be
389 VOIDmode, because that is what store_field uses to indicate that this
390 is a bit field, but passing VOIDmode to operand_subword_force will
391 result in an abort. */
392 fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0);
394 for (i = 0; i < nwords; i++)
396 /* If I is 0, use the low-order word in both field and target;
397 if I is 1, use the next to lowest word; and so on. */
398 unsigned int wordnum = (backwards ? nwords - i - 1 : i);
399 unsigned int bit_offset = (backwards
400 ? MAX ((int) bitsize - ((int) i + 1)
403 : (int) i * BITS_PER_WORD);
405 store_bit_field (op0, MIN (BITS_PER_WORD,
406 bitsize - i * BITS_PER_WORD),
407 bitnum + bit_offset, word_mode,
408 operand_subword_force (value, wordnum,
409 (GET_MODE (value) == VOIDmode
411 : GET_MODE (value))),
417 /* From here on we can assume that the field to be stored in is
418 a full-word (whatever type that is), since it is shorter than a word. */
420 /* OFFSET is the number of words or bytes (UNIT says which)
421 from STR_RTX to the first word or byte containing part of the field. */
423 if (GET_CODE (op0) != MEM)
426 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
428 if (GET_CODE (op0) != REG)
430 /* Since this is a destination (lvalue), we can't copy it to a
431 pseudo. We can trivially remove a SUBREG that does not
432 change the size of the operand. Such a SUBREG may have been
433 added above. Otherwise, abort. */
434 if (GET_CODE (op0) == SUBREG
435 && (GET_MODE_SIZE (GET_MODE (op0))
436 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))
437 op0 = SUBREG_REG (op0);
441 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
448 op0 = protect_from_queue (op0, 1);
451 /* If VALUE is a floating-point mode, access it as an integer of the
452 corresponding size. This can occur on a machine with 64 bit registers
453 that uses SFmode for float. This can also occur for unaligned float
455 if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT)
457 if (GET_CODE (value) != REG)
458 value = copy_to_reg (value);
459 value = gen_rtx_SUBREG (word_mode, value, 0);
462 /* Now OFFSET is nonzero only if OP0 is memory
463 and is therefore always measured in bytes. */
467 && GET_MODE (value) != BLKmode
468 && !(bitsize == 1 && GET_CODE (value) == CONST_INT)
469 /* Ensure insv's size is wide enough for this field. */
470 && (insv_bitsize >= bitsize)
471 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
472 && (bitsize + bitpos > insv_bitsize)))
474 int xbitpos = bitpos;
477 rtx last = get_last_insn ();
479 enum machine_mode maxmode;
480 int save_volatile_ok = volatile_ok;
482 maxmode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
483 if (maxmode == VOIDmode)
488 /* If this machine's insv can only insert into a register, copy OP0
489 into a register and save it back later. */
490 /* This used to check flag_force_mem, but that was a serious
491 de-optimization now that flag_force_mem is enabled by -O2. */
492 if (GET_CODE (op0) == MEM
493 && ! ((*insn_data[(int) CODE_FOR_insv].operand[0].predicate)
497 enum machine_mode bestmode;
499 /* Get the mode to use for inserting into this field. If OP0 is
500 BLKmode, get the smallest mode consistent with the alignment. If
501 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
502 mode. Otherwise, use the smallest mode containing the field. */
504 if (GET_MODE (op0) == BLKmode
505 || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode))
507 = get_best_mode (bitsize, bitnum, align, maxmode,
508 MEM_VOLATILE_P (op0));
510 bestmode = GET_MODE (op0);
512 if (bestmode == VOIDmode
513 || (SLOW_UNALIGNED_ACCESS (bestmode, align)
514 && GET_MODE_BITSIZE (bestmode) > align))
517 /* Adjust address to point to the containing unit of that mode. */
518 unit = GET_MODE_BITSIZE (bestmode);
519 /* Compute offset as multiple of this unit, counting in bytes. */
520 offset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
521 bitpos = bitnum % unit;
522 op0 = change_address (op0, bestmode,
523 plus_constant (XEXP (op0, 0), offset));
525 /* Fetch that unit, store the bitfield in it, then store
527 tempreg = copy_to_reg (op0);
528 store_bit_field (tempreg, bitsize, bitpos, fieldmode, value,
530 emit_move_insn (op0, tempreg);
533 volatile_ok = save_volatile_ok;
535 /* Add OFFSET into OP0's address. */
536 if (GET_CODE (xop0) == MEM)
537 xop0 = change_address (xop0, byte_mode,
538 plus_constant (XEXP (xop0, 0), offset));
540 /* If xop0 is a register, we need it in MAXMODE
541 to make it acceptable to the format of insv. */
542 if (GET_CODE (xop0) == SUBREG)
543 /* We can't just change the mode, because this might clobber op0,
544 and we will need the original value of op0 if insv fails. */
545 xop0 = gen_rtx_SUBREG (maxmode, SUBREG_REG (xop0), SUBREG_WORD (xop0));
546 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
547 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
549 /* On big-endian machines, we count bits from the most significant.
550 If the bit field insn does not, we must invert. */
552 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
553 xbitpos = unit - bitsize - xbitpos;
555 /* We have been counting XBITPOS within UNIT.
556 Count instead within the size of the register. */
557 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
558 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
560 unit = GET_MODE_BITSIZE (maxmode);
562 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
564 if (GET_MODE (value) != maxmode)
566 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
568 /* Optimization: Don't bother really extending VALUE
569 if it has all the bits we will actually use. However,
570 if we must narrow it, be sure we do it correctly. */
572 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode))
574 /* Avoid making subreg of a subreg, or of a mem. */
575 if (GET_CODE (value1) != REG)
576 value1 = copy_to_reg (value1);
577 value1 = gen_rtx_SUBREG (maxmode, value1, 0);
580 value1 = gen_lowpart (maxmode, value1);
582 else if (!CONSTANT_P (value))
583 /* Parse phase is supposed to make VALUE's data type
584 match that of the component reference, which is a type
585 at least as wide as the field; so VALUE should have
586 a mode that corresponds to that type. */
590 /* If this machine's insv insists on a register,
591 get VALUE1 into a register. */
592 if (! ((*insn_data[(int) CODE_FOR_insv].operand[3].predicate)
594 value1 = force_reg (maxmode, value1);
596 pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1);
601 delete_insns_since (last);
602 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
608 /* Insv is not available; store using shifts and boolean ops. */
609 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
613 /* Use shifts and boolean operations to store VALUE
614 into a bit field of width BITSIZE
615 in a memory location specified by OP0 except offset by OFFSET bytes.
616 (OFFSET must be 0 if OP0 is a register.)
617 The field starts at position BITPOS within the byte.
618 (If OP0 is a register, it may be a full word or a narrower mode,
619 but BITPOS still counts within a full word,
620 which is significant on bigendian machines.)
621 STRUCT_ALIGN is the alignment the structure is known to have.
623 Note that protect_from_queue has already been done on OP0 and VALUE. */
626 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align)
628 unsigned HOST_WIDE_INT offset, bitsize, bitpos;
630 unsigned int struct_align;
632 register enum machine_mode mode;
633 unsigned int total_bits = BITS_PER_WORD;
638 if (! SLOW_UNALIGNED_ACCESS (word_mode, struct_align))
639 struct_align = BIGGEST_ALIGNMENT;
641 /* There is a case not handled here:
642 a structure with a known alignment of just a halfword
643 and a field split across two aligned halfwords within the structure.
644 Or likewise a structure with a known alignment of just a byte
645 and a field split across two bytes.
646 Such cases are not supposed to be able to occur. */
648 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
652 /* Special treatment for a bit field split across two registers. */
653 if (bitsize + bitpos > BITS_PER_WORD)
655 store_split_bit_field (op0, bitsize, bitpos,
656 value, BITS_PER_WORD);
662 /* Get the proper mode to use for this field. We want a mode that
663 includes the entire field. If such a mode would be larger than
664 a word, we won't be doing the extraction the normal way. */
666 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
667 struct_align, word_mode,
668 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
670 if (mode == VOIDmode)
672 /* The only way this should occur is if the field spans word
674 store_split_bit_field (op0,
675 bitsize, bitpos + offset * BITS_PER_UNIT,
676 value, struct_align);
680 total_bits = GET_MODE_BITSIZE (mode);
682 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
683 be in the range 0 to total_bits-1, and put any excess bytes in
685 if (bitpos >= total_bits)
687 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
688 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
692 /* Get ref to an aligned byte, halfword, or word containing the field.
693 Adjust BITPOS to be position within a word,
694 and OFFSET to be the offset of that word.
695 Then alter OP0 to refer to that word. */
696 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
697 offset -= (offset % (total_bits / BITS_PER_UNIT));
698 op0 = change_address (op0, mode,
699 plus_constant (XEXP (op0, 0), offset));
702 mode = GET_MODE (op0);
704 /* Now MODE is either some integral mode for a MEM as OP0,
705 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
706 The bit field is contained entirely within OP0.
707 BITPOS is the starting bit number within OP0.
708 (OP0's mode may actually be narrower than MODE.) */
710 if (BYTES_BIG_ENDIAN)
711 /* BITPOS is the distance between our msb
712 and that of the containing datum.
713 Convert it to the distance from the lsb. */
714 bitpos = total_bits - bitsize - bitpos;
716 /* Now BITPOS is always the distance between our lsb
719 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
720 we must first convert its mode to MODE. */
722 if (GET_CODE (value) == CONST_INT)
724 register HOST_WIDE_INT v = INTVAL (value);
726 if (bitsize < HOST_BITS_PER_WIDE_INT)
727 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
731 else if ((bitsize < HOST_BITS_PER_WIDE_INT
732 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
733 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
736 value = lshift_value (mode, value, bitpos, bitsize);
740 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
741 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
743 if (GET_MODE (value) != mode)
745 if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
746 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
747 value = gen_lowpart (mode, value);
749 value = convert_to_mode (mode, value, 1);
753 value = expand_binop (mode, and_optab, value,
754 mask_rtx (mode, 0, bitsize, 0),
755 NULL_RTX, 1, OPTAB_LIB_WIDEN);
757 value = expand_shift (LSHIFT_EXPR, mode, value,
758 build_int_2 (bitpos, 0), NULL_RTX, 1);
761 /* Now clear the chosen bits in OP0,
762 except that if VALUE is -1 we need not bother. */
764 subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0;
768 temp = expand_binop (mode, and_optab, op0,
769 mask_rtx (mode, bitpos, bitsize, 1),
770 subtarget, 1, OPTAB_LIB_WIDEN);
776 /* Now logical-or VALUE into OP0, unless it is zero. */
779 temp = expand_binop (mode, ior_optab, temp, value,
780 subtarget, 1, OPTAB_LIB_WIDEN);
782 emit_move_insn (op0, temp);
785 /* Store a bit field that is split across multiple accessible memory objects.
787 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
788 BITSIZE is the field width; BITPOS the position of its first bit
790 VALUE is the value to store.
791 ALIGN is the known alignment of OP0.
792 This is also the size of the memory objects to be used.
794 This does not yet handle fields wider than BITS_PER_WORD. */
797 store_split_bit_field (op0, bitsize, bitpos, value, align)
799 unsigned HOST_WIDE_INT bitsize, bitpos;
804 unsigned int bitsdone = 0;
806 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
808 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
809 unit = BITS_PER_WORD;
811 unit = MIN (align, BITS_PER_WORD);
813 /* If VALUE is a constant other than a CONST_INT, get it into a register in
814 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
815 that VALUE might be a floating-point constant. */
816 if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT)
818 rtx word = gen_lowpart_common (word_mode, value);
820 if (word && (value != word))
823 value = gen_lowpart_common (word_mode,
824 force_reg (GET_MODE (value) != VOIDmode
826 : word_mode, value));
828 else if (GET_CODE (value) == ADDRESSOF)
829 value = copy_to_reg (value);
831 while (bitsdone < bitsize)
833 unsigned HOST_WIDE_INT thissize;
835 unsigned HOST_WIDE_INT thispos;
836 unsigned HOST_WIDE_INT offset;
838 offset = (bitpos + bitsdone) / unit;
839 thispos = (bitpos + bitsdone) % unit;
841 /* THISSIZE must not overrun a word boundary. Otherwise,
842 store_fixed_bit_field will call us again, and we will mutually
844 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
845 thissize = MIN (thissize, unit - thispos);
847 if (BYTES_BIG_ENDIAN)
851 /* We must do an endian conversion exactly the same way as it is
852 done in extract_bit_field, so that the two calls to
853 extract_fixed_bit_field will have comparable arguments. */
854 if (GET_CODE (value) != MEM || GET_MODE (value) == BLKmode)
855 total_bits = BITS_PER_WORD;
857 total_bits = GET_MODE_BITSIZE (GET_MODE (value));
859 /* Fetch successively less significant portions. */
860 if (GET_CODE (value) == CONST_INT)
861 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
862 >> (bitsize - bitsdone - thissize))
863 & (((HOST_WIDE_INT) 1 << thissize) - 1));
865 /* The args are chosen so that the last part includes the
866 lsb. Give extract_bit_field the value it needs (with
867 endianness compensation) to fetch the piece we want.
869 ??? We have no idea what the alignment of VALUE is, so
870 we have to use a guess. */
872 = extract_fixed_bit_field
873 (word_mode, value, 0, thissize,
874 total_bits - bitsize + bitsdone, NULL_RTX, 1,
875 GET_MODE (value) == VOIDmode
877 : (GET_MODE (value) == BLKmode
878 ? 1 : GET_MODE_ALIGNMENT (GET_MODE (value))));
882 /* Fetch successively more significant portions. */
883 if (GET_CODE (value) == CONST_INT)
884 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
886 & (((HOST_WIDE_INT) 1 << thissize) - 1));
889 = extract_fixed_bit_field
890 (word_mode, value, 0, thissize, bitsdone, NULL_RTX, 1,
891 GET_MODE (value) == VOIDmode
893 : (GET_MODE (value) == BLKmode
894 ? 1 : GET_MODE_ALIGNMENT (GET_MODE (value))));
897 /* If OP0 is a register, then handle OFFSET here.
899 When handling multiword bitfields, extract_bit_field may pass
900 down a word_mode SUBREG of a larger REG for a bitfield that actually
901 crosses a word boundary. Thus, for a SUBREG, we must find
902 the current word starting from the base register. */
903 if (GET_CODE (op0) == SUBREG)
905 word = operand_subword_force (SUBREG_REG (op0),
906 SUBREG_WORD (op0) + offset,
907 GET_MODE (SUBREG_REG (op0)));
910 else if (GET_CODE (op0) == REG)
912 word = operand_subword_force (op0, offset, GET_MODE (op0));
918 /* OFFSET is in UNITs, and UNIT is in bits.
919 store_fixed_bit_field wants offset in bytes. */
920 store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT,
921 thissize, thispos, part, align);
922 bitsdone += thissize;
926 /* Generate code to extract a byte-field from STR_RTX
927 containing BITSIZE bits, starting at BITNUM,
928 and put it in TARGET if possible (if TARGET is nonzero).
929 Regardless of TARGET, we return the rtx for where the value is placed.
932 STR_RTX is the structure containing the byte (a REG or MEM).
933 UNSIGNEDP is nonzero if this is an unsigned bit field.
934 MODE is the natural mode of the field value once extracted.
935 TMODE is the mode the caller would like the value to have;
936 but the value may be returned with type MODE instead.
938 ALIGN is the alignment that STR_RTX is known to have.
939 TOTAL_SIZE is the size in bytes of the containing structure,
942 If a TARGET is specified and we can store in it at no extra cost,
943 we do so, and return TARGET.
944 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
945 if they are equally easy. */
948 extract_bit_field (str_rtx, bitsize, bitnum, unsignedp,
949 target, mode, tmode, align, total_size)
951 unsigned HOST_WIDE_INT bitsize;
952 unsigned HOST_WIDE_INT bitnum;
955 enum machine_mode mode, tmode;
957 HOST_WIDE_INT total_size;
960 = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
961 unsigned HOST_WIDE_INT offset = bitnum / unit;
962 unsigned HOST_WIDE_INT bitpos = bitnum % unit;
963 register rtx op0 = str_rtx;
964 rtx spec_target = target;
965 rtx spec_target_subreg = 0;
966 enum machine_mode int_mode;
968 unsigned HOST_WIDE_INT extv_bitsize;
969 enum machine_mode extv_mode;
972 unsigned HOST_WIDE_INT extzv_bitsize;
973 enum machine_mode extzv_mode;
977 extv_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
978 if (extv_mode == VOIDmode)
979 extv_mode = word_mode;
980 extv_bitsize = GET_MODE_BITSIZE (extv_mode);
984 extzv_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
985 if (extzv_mode == VOIDmode)
986 extzv_mode = word_mode;
987 extzv_bitsize = GET_MODE_BITSIZE (extzv_mode);
990 /* Discount the part of the structure before the desired byte.
991 We need to know how many bytes are safe to reference after it. */
993 total_size -= (bitpos / BIGGEST_ALIGNMENT
994 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
996 if (tmode == VOIDmode)
998 while (GET_CODE (op0) == SUBREG)
1000 int outer_size = GET_MODE_BITSIZE (GET_MODE (op0));
1001 int inner_size = GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)));
1003 offset += SUBREG_WORD (op0);
1005 inner_size = MIN (inner_size, BITS_PER_WORD);
1007 if (BYTES_BIG_ENDIAN && (outer_size < inner_size))
1009 bitpos += inner_size - outer_size;
1012 offset += (bitpos / unit);
1017 op0 = SUBREG_REG (op0);
1020 /* Make sure we are playing with integral modes. Pun with subregs
1023 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
1024 if (imode != GET_MODE (op0))
1026 if (GET_CODE (op0) == MEM)
1027 op0 = change_address (op0, imode, NULL_RTX);
1028 else if (imode != BLKmode)
1029 op0 = gen_lowpart (imode, op0);
1035 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1036 If that's wrong, the solution is to test for it and set TARGET to 0
1039 /* If OP0 is a register, BITPOS must count within a word.
1040 But as we have it, it counts within whatever size OP0 now has.
1041 On a bigendian machine, these are not the same, so convert. */
1042 if (BYTES_BIG_ENDIAN
1043 && GET_CODE (op0) != MEM
1044 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
1045 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
1047 /* Extracting a full-word or multi-word value
1048 from a structure in a register or aligned memory.
1049 This can be done with just SUBREG.
1050 So too extracting a subword value in
1051 the least significant part of the register. */
1053 if (((GET_CODE (op0) != MEM
1054 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
1055 GET_MODE_BITSIZE (GET_MODE (op0))))
1056 || (GET_CODE (op0) == MEM
1057 && (! SLOW_UNALIGNED_ACCESS (mode, align)
1058 || (offset * BITS_PER_UNIT % bitsize == 0
1059 && align % bitsize == 0))))
1060 && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
1061 && bitpos % BITS_PER_WORD == 0)
1062 || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode
1063 /* ??? The big endian test here is wrong. This is correct
1064 if the value is in a register, and if mode_for_size is not
1065 the same mode as op0. This causes us to get unnecessarily
1066 inefficient code from the Thumb port when -mbig-endian. */
1067 && (BYTES_BIG_ENDIAN
1068 ? bitpos + bitsize == BITS_PER_WORD
1071 enum machine_mode mode1
1072 = (VECTOR_MODE_P (tmode) ? mode
1073 : mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0));
1075 if (mode1 != GET_MODE (op0))
1077 if (GET_CODE (op0) == SUBREG)
1079 if (GET_MODE (SUBREG_REG (op0)) == mode1
1080 || GET_MODE_CLASS (mode1) == MODE_INT
1081 || GET_MODE_CLASS (mode1) == MODE_PARTIAL_INT)
1082 op0 = SUBREG_REG (op0);
1084 /* Else we've got some float mode source being extracted into
1085 a different float mode destination -- this combination of
1086 subregs results in Severe Tire Damage. */
1089 if (GET_CODE (op0) == REG)
1090 op0 = gen_rtx_SUBREG (mode1, op0, offset);
1092 op0 = change_address (op0, mode1,
1093 plus_constant (XEXP (op0, 0), offset));
1096 return convert_to_mode (tmode, op0, unsignedp);
1100 /* Handle fields bigger than a word. */
1102 if (bitsize > BITS_PER_WORD)
1104 /* Here we transfer the words of the field
1105 in the order least significant first.
1106 This is because the most significant word is the one which may
1107 be less than full. */
1109 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
1112 if (target == 0 || GET_CODE (target) != REG)
1113 target = gen_reg_rtx (mode);
1115 /* Indicate for flow that the entire target reg is being set. */
1116 emit_insn (gen_rtx_CLOBBER (VOIDmode, target));
1118 for (i = 0; i < nwords; i++)
1120 /* If I is 0, use the low-order word in both field and target;
1121 if I is 1, use the next to lowest word; and so on. */
1122 /* Word number in TARGET to use. */
1123 unsigned int wordnum
1125 ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1
1127 /* Offset from start of field in OP0. */
1128 unsigned int bit_offset = (WORDS_BIG_ENDIAN
1129 ? MAX (0, ((int) bitsize - ((int) i + 1)
1130 * (int) BITS_PER_WORD))
1131 : (int) i * BITS_PER_WORD);
1132 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1134 = extract_bit_field (op0, MIN (BITS_PER_WORD,
1135 bitsize - i * BITS_PER_WORD),
1136 bitnum + bit_offset, 1, target_part, mode,
1137 word_mode, align, total_size);
1139 if (target_part == 0)
1142 if (result_part != target_part)
1143 emit_move_insn (target_part, result_part);
1148 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1149 need to be zero'd out. */
1150 if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD)
1152 unsigned int i, total_words;
1154 total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD;
1155 for (i = nwords; i < total_words; i++)
1157 int wordnum = WORDS_BIG_ENDIAN ? total_words - i - 1 : i;
1158 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1159 emit_move_insn (target_part, const0_rtx);
1165 /* Signed bit field: sign-extend with two arithmetic shifts. */
1166 target = expand_shift (LSHIFT_EXPR, mode, target,
1167 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1169 return expand_shift (RSHIFT_EXPR, mode, target,
1170 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1174 /* From here on we know the desired field is smaller than a word. */
1176 /* Check if there is a correspondingly-sized integer field, so we can
1177 safely extract it as one size of integer, if necessary; then
1178 truncate or extend to the size that is wanted; then use SUBREGs or
1179 convert_to_mode to get one of the modes we really wanted. */
1181 int_mode = int_mode_for_mode (tmode);
1182 if (int_mode == BLKmode)
1183 int_mode = int_mode_for_mode (mode);
1184 if (int_mode == BLKmode)
1185 abort(); /* Should probably push op0 out to memory and then
1188 /* OFFSET is the number of words or bytes (UNIT says which)
1189 from STR_RTX to the first word or byte containing part of the field. */
1191 if (GET_CODE (op0) != MEM)
1194 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
1196 if (GET_CODE (op0) != REG)
1197 op0 = copy_to_reg (op0);
1198 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
1205 op0 = protect_from_queue (str_rtx, 1);
1208 /* Now OFFSET is nonzero only for memory operands. */
1214 && (extzv_bitsize >= bitsize)
1215 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1216 && (bitsize + bitpos > extzv_bitsize)))
1218 unsigned HOST_WIDE_INT xbitpos = bitpos, xoffset = offset;
1219 rtx bitsize_rtx, bitpos_rtx;
1220 rtx last = get_last_insn ();
1222 rtx xtarget = target;
1223 rtx xspec_target = spec_target;
1224 rtx xspec_target_subreg = spec_target_subreg;
1226 enum machine_mode maxmode;
1228 maxmode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
1229 if (maxmode == VOIDmode)
1230 maxmode = word_mode;
1232 if (GET_CODE (xop0) == MEM)
1234 int save_volatile_ok = volatile_ok;
1237 /* Is the memory operand acceptable? */
1238 if (! ((*insn_data[(int) CODE_FOR_extzv].operand[1].predicate)
1239 (xop0, GET_MODE (xop0))))
1241 /* No, load into a reg and extract from there. */
1242 enum machine_mode bestmode;
1244 /* Get the mode to use for inserting into this field. If
1245 OP0 is BLKmode, get the smallest mode consistent with the
1246 alignment. If OP0 is a non-BLKmode object that is no
1247 wider than MAXMODE, use its mode. Otherwise, use the
1248 smallest mode containing the field. */
1250 if (GET_MODE (xop0) == BLKmode
1251 || (GET_MODE_SIZE (GET_MODE (op0))
1252 > GET_MODE_SIZE (maxmode)))
1253 bestmode = get_best_mode (bitsize, bitnum, align, maxmode,
1254 MEM_VOLATILE_P (xop0));
1256 bestmode = GET_MODE (xop0);
1258 if (bestmode == VOIDmode
1259 || (SLOW_UNALIGNED_ACCESS (bestmode, align)
1260 && GET_MODE_BITSIZE (bestmode) > align))
1263 /* Compute offset as multiple of this unit,
1264 counting in bytes. */
1265 unit = GET_MODE_BITSIZE (bestmode);
1266 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1267 xbitpos = bitnum % unit;
1268 xop0 = change_address (xop0, bestmode,
1269 plus_constant (XEXP (xop0, 0),
1271 /* Fetch it to a register in that size. */
1272 xop0 = force_reg (bestmode, xop0);
1274 /* XBITPOS counts within UNIT, which is what is expected. */
1277 /* Get ref to first byte containing part of the field. */
1278 xop0 = change_address (xop0, byte_mode,
1279 plus_constant (XEXP (xop0, 0), xoffset));
1281 volatile_ok = save_volatile_ok;
1284 /* If op0 is a register, we need it in MAXMODE (which is usually
1285 SImode). to make it acceptable to the format of extzv. */
1286 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1288 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1289 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
1291 /* On big-endian machines, we count bits from the most significant.
1292 If the bit field insn does not, we must invert. */
1293 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1294 xbitpos = unit - bitsize - xbitpos;
1296 /* Now convert from counting within UNIT to counting in MAXMODE. */
1297 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
1298 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
1300 unit = GET_MODE_BITSIZE (maxmode);
1303 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1304 xtarget = xspec_target = gen_reg_rtx (tmode);
1306 if (GET_MODE (xtarget) != maxmode)
1308 if (GET_CODE (xtarget) == REG)
1310 int wider = (GET_MODE_SIZE (maxmode)
1311 > GET_MODE_SIZE (GET_MODE (xtarget)));
1312 xtarget = gen_lowpart (maxmode, xtarget);
1314 xspec_target_subreg = xtarget;
1317 xtarget = gen_reg_rtx (maxmode);
1320 /* If this machine's extzv insists on a register target,
1321 make sure we have one. */
1322 if (! ((*insn_data[(int) CODE_FOR_extzv].operand[0].predicate)
1323 (xtarget, maxmode)))
1324 xtarget = gen_reg_rtx (maxmode);
1326 bitsize_rtx = GEN_INT (bitsize);
1327 bitpos_rtx = GEN_INT (xbitpos);
1329 pat = gen_extzv (protect_from_queue (xtarget, 1),
1330 xop0, bitsize_rtx, bitpos_rtx);
1335 spec_target = xspec_target;
1336 spec_target_subreg = xspec_target_subreg;
1340 delete_insns_since (last);
1341 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1342 bitpos, target, 1, align);
1348 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1349 bitpos, target, 1, align);
1355 && (extv_bitsize >= bitsize)
1356 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1357 && (bitsize + bitpos > extv_bitsize)))
1359 int xbitpos = bitpos, xoffset = offset;
1360 rtx bitsize_rtx, bitpos_rtx;
1361 rtx last = get_last_insn ();
1362 rtx xop0 = op0, xtarget = target;
1363 rtx xspec_target = spec_target;
1364 rtx xspec_target_subreg = spec_target_subreg;
1366 enum machine_mode maxmode;
1368 maxmode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
1369 if (maxmode == VOIDmode)
1370 maxmode = word_mode;
1372 if (GET_CODE (xop0) == MEM)
1374 /* Is the memory operand acceptable? */
1375 if (! ((*insn_data[(int) CODE_FOR_extv].operand[1].predicate)
1376 (xop0, GET_MODE (xop0))))
1378 /* No, load into a reg and extract from there. */
1379 enum machine_mode bestmode;
1381 /* Get the mode to use for inserting into this field. If
1382 OP0 is BLKmode, get the smallest mode consistent with the
1383 alignment. If OP0 is a non-BLKmode object that is no
1384 wider than MAXMODE, use its mode. Otherwise, use the
1385 smallest mode containing the field. */
1387 if (GET_MODE (xop0) == BLKmode
1388 || (GET_MODE_SIZE (GET_MODE (op0))
1389 > GET_MODE_SIZE (maxmode)))
1390 bestmode = get_best_mode (bitsize, bitnum, align, maxmode,
1391 MEM_VOLATILE_P (xop0));
1393 bestmode = GET_MODE (xop0);
1395 if (bestmode == VOIDmode
1396 || (SLOW_UNALIGNED_ACCESS (bestmode, align)
1397 && GET_MODE_BITSIZE (bestmode) > align))
1400 /* Compute offset as multiple of this unit,
1401 counting in bytes. */
1402 unit = GET_MODE_BITSIZE (bestmode);
1403 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1404 xbitpos = bitnum % unit;
1405 xop0 = change_address (xop0, bestmode,
1406 plus_constant (XEXP (xop0, 0),
1408 /* Fetch it to a register in that size. */
1409 xop0 = force_reg (bestmode, xop0);
1411 /* XBITPOS counts within UNIT, which is what is expected. */
1414 /* Get ref to first byte containing part of the field. */
1415 xop0 = change_address (xop0, byte_mode,
1416 plus_constant (XEXP (xop0, 0), xoffset));
1419 /* If op0 is a register, we need it in MAXMODE (which is usually
1420 SImode) to make it acceptable to the format of extv. */
1421 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1423 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1424 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
1426 /* On big-endian machines, we count bits from the most significant.
1427 If the bit field insn does not, we must invert. */
1428 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1429 xbitpos = unit - bitsize - xbitpos;
1431 /* XBITPOS counts within a size of UNIT.
1432 Adjust to count within a size of MAXMODE. */
1433 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
1434 xbitpos += (GET_MODE_BITSIZE (maxmode) - unit);
1436 unit = GET_MODE_BITSIZE (maxmode);
1439 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1440 xtarget = xspec_target = gen_reg_rtx (tmode);
1442 if (GET_MODE (xtarget) != maxmode)
1444 if (GET_CODE (xtarget) == REG)
1446 int wider = (GET_MODE_SIZE (maxmode)
1447 > GET_MODE_SIZE (GET_MODE (xtarget)));
1448 xtarget = gen_lowpart (maxmode, xtarget);
1450 xspec_target_subreg = xtarget;
1453 xtarget = gen_reg_rtx (maxmode);
1456 /* If this machine's extv insists on a register target,
1457 make sure we have one. */
1458 if (! ((*insn_data[(int) CODE_FOR_extv].operand[0].predicate)
1459 (xtarget, maxmode)))
1460 xtarget = gen_reg_rtx (maxmode);
1462 bitsize_rtx = GEN_INT (bitsize);
1463 bitpos_rtx = GEN_INT (xbitpos);
1465 pat = gen_extv (protect_from_queue (xtarget, 1),
1466 xop0, bitsize_rtx, bitpos_rtx);
1471 spec_target = xspec_target;
1472 spec_target_subreg = xspec_target_subreg;
1476 delete_insns_since (last);
1477 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1478 bitpos, target, 0, align);
1484 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1485 bitpos, target, 0, align);
1487 if (target == spec_target)
1489 if (target == spec_target_subreg)
1491 if (GET_MODE (target) != tmode && GET_MODE (target) != mode)
1493 /* If the target mode is floating-point, first convert to the
1494 integer mode of that size and then access it as a floating-point
1495 value via a SUBREG. */
1496 if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1498 target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode),
1501 if (GET_CODE (target) != REG)
1502 target = copy_to_reg (target);
1503 return gen_rtx_SUBREG (tmode, target, 0);
1506 return convert_to_mode (tmode, target, unsignedp);
1511 /* Extract a bit field using shifts and boolean operations
1512 Returns an rtx to represent the value.
1513 OP0 addresses a register (word) or memory (byte).
1514 BITPOS says which bit within the word or byte the bit field starts in.
1515 OFFSET says how many bytes farther the bit field starts;
1516 it is 0 if OP0 is a register.
1517 BITSIZE says how many bits long the bit field is.
1518 (If OP0 is a register, it may be narrower than a full word,
1519 but BITPOS still counts within a full word,
1520 which is significant on bigendian machines.)
1522 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1523 If TARGET is nonzero, attempts to store the value there
1524 and return TARGET, but this is not guaranteed.
1525 If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
1527 ALIGN is the alignment that STR_RTX is known to have. */
1530 extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1531 target, unsignedp, align)
1532 enum machine_mode tmode;
1533 register rtx op0, target;
1534 unsigned HOST_WIDE_INT offset, bitsize, bitpos;
1538 unsigned int total_bits = BITS_PER_WORD;
1539 enum machine_mode mode;
1541 if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
1543 /* Special treatment for a bit field split across two registers. */
1544 if (bitsize + bitpos > BITS_PER_WORD)
1545 return extract_split_bit_field (op0, bitsize, bitpos,
1550 /* Get the proper mode to use for this field. We want a mode that
1551 includes the entire field. If such a mode would be larger than
1552 a word, we won't be doing the extraction the normal way. */
1554 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, align,
1556 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
1558 if (mode == VOIDmode)
1559 /* The only way this should occur is if the field spans word
1561 return extract_split_bit_field (op0, bitsize,
1562 bitpos + offset * BITS_PER_UNIT,
1565 total_bits = GET_MODE_BITSIZE (mode);
1567 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1568 be in the range 0 to total_bits-1, and put any excess bytes in
1570 if (bitpos >= total_bits)
1572 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
1573 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
1577 /* Get ref to an aligned byte, halfword, or word containing the field.
1578 Adjust BITPOS to be position within a word,
1579 and OFFSET to be the offset of that word.
1580 Then alter OP0 to refer to that word. */
1581 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1582 offset -= (offset % (total_bits / BITS_PER_UNIT));
1583 op0 = change_address (op0, mode,
1584 plus_constant (XEXP (op0, 0), offset));
1587 mode = GET_MODE (op0);
1589 if (BYTES_BIG_ENDIAN)
1591 /* BITPOS is the distance between our msb and that of OP0.
1592 Convert it to the distance from the lsb. */
1594 bitpos = total_bits - bitsize - bitpos;
1597 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1598 We have reduced the big-endian case to the little-endian case. */
1604 /* If the field does not already start at the lsb,
1605 shift it so it does. */
1606 tree amount = build_int_2 (bitpos, 0);
1607 /* Maybe propagate the target for the shift. */
1608 /* But not if we will return it--could confuse integrate.c. */
1609 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1610 && !REG_FUNCTION_VALUE_P (target)
1612 if (tmode != mode) subtarget = 0;
1613 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1615 /* Convert the value to the desired mode. */
1617 op0 = convert_to_mode (tmode, op0, 1);
1619 /* Unless the msb of the field used to be the msb when we shifted,
1620 mask out the upper bits. */
1622 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize
1624 #ifdef SLOW_ZERO_EXTEND
1625 /* Always generate an `and' if
1626 we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
1627 will combine fruitfully with the zero-extend. */
1632 return expand_binop (GET_MODE (op0), and_optab, op0,
1633 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1634 target, 1, OPTAB_LIB_WIDEN);
1638 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1639 then arithmetic-shift its lsb to the lsb of the word. */
1640 op0 = force_reg (mode, op0);
1644 /* Find the narrowest integer mode that contains the field. */
1646 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1647 mode = GET_MODE_WIDER_MODE (mode))
1648 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1650 op0 = convert_to_mode (mode, op0, 0);
1654 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1656 tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
1657 /* Maybe propagate the target for the shift. */
1658 /* But not if we will return the result--could confuse integrate.c. */
1659 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1660 && ! REG_FUNCTION_VALUE_P (target)
1662 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1665 return expand_shift (RSHIFT_EXPR, mode, op0,
1666 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1670 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1671 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1672 complement of that if COMPLEMENT. The mask is truncated if
1673 necessary to the width of mode MODE. The mask is zero-extended if
1674 BITSIZE+BITPOS is too small for MODE. */
1677 mask_rtx (mode, bitpos, bitsize, complement)
1678 enum machine_mode mode;
1679 int bitpos, bitsize, complement;
1681 HOST_WIDE_INT masklow, maskhigh;
1683 if (bitpos < HOST_BITS_PER_WIDE_INT)
1684 masklow = (HOST_WIDE_INT) -1 << bitpos;
1688 if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT)
1689 masklow &= ((unsigned HOST_WIDE_INT) -1
1690 >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1692 if (bitpos <= HOST_BITS_PER_WIDE_INT)
1695 maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT);
1697 if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT)
1698 maskhigh &= ((unsigned HOST_WIDE_INT) -1
1699 >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1705 maskhigh = ~maskhigh;
1709 return immed_double_const (masklow, maskhigh, mode);
1712 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1713 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1716 lshift_value (mode, value, bitpos, bitsize)
1717 enum machine_mode mode;
1719 int bitpos, bitsize;
1721 unsigned HOST_WIDE_INT v = INTVAL (value);
1722 HOST_WIDE_INT low, high;
1724 if (bitsize < HOST_BITS_PER_WIDE_INT)
1725 v &= ~((HOST_WIDE_INT) -1 << bitsize);
1727 if (bitpos < HOST_BITS_PER_WIDE_INT)
1730 high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0);
1735 high = v << (bitpos - HOST_BITS_PER_WIDE_INT);
1738 return immed_double_const (low, high, mode);
1741 /* Extract a bit field that is split across two words
1742 and return an RTX for the result.
1744 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1745 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1746 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
1748 ALIGN is the known alignment of OP0. This is also the size of the
1749 memory objects to be used. */
1752 extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align)
1754 unsigned HOST_WIDE_INT bitsize, bitpos;
1759 unsigned int bitsdone = 0;
1760 rtx result = NULL_RTX;
1763 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1765 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1766 unit = BITS_PER_WORD;
1768 unit = MIN (align, BITS_PER_WORD);
1770 while (bitsdone < bitsize)
1772 unsigned HOST_WIDE_INT thissize;
1774 unsigned HOST_WIDE_INT thispos;
1775 unsigned HOST_WIDE_INT offset;
1777 offset = (bitpos + bitsdone) / unit;
1778 thispos = (bitpos + bitsdone) % unit;
1780 /* THISSIZE must not overrun a word boundary. Otherwise,
1781 extract_fixed_bit_field will call us again, and we will mutually
1783 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1784 thissize = MIN (thissize, unit - thispos);
1786 /* If OP0 is a register, then handle OFFSET here.
1788 When handling multiword bitfields, extract_bit_field may pass
1789 down a word_mode SUBREG of a larger REG for a bitfield that actually
1790 crosses a word boundary. Thus, for a SUBREG, we must find
1791 the current word starting from the base register. */
1792 if (GET_CODE (op0) == SUBREG)
1794 word = operand_subword_force (SUBREG_REG (op0),
1795 SUBREG_WORD (op0) + offset,
1796 GET_MODE (SUBREG_REG (op0)));
1799 else if (GET_CODE (op0) == REG)
1801 word = operand_subword_force (op0, offset, GET_MODE (op0));
1807 /* Extract the parts in bit-counting order,
1808 whose meaning is determined by BYTES_PER_UNIT.
1809 OFFSET is in UNITs, and UNIT is in bits.
1810 extract_fixed_bit_field wants offset in bytes. */
1811 part = extract_fixed_bit_field (word_mode, word,
1812 offset * unit / BITS_PER_UNIT,
1813 thissize, thispos, 0, 1, align);
1814 bitsdone += thissize;
1816 /* Shift this part into place for the result. */
1817 if (BYTES_BIG_ENDIAN)
1819 if (bitsize != bitsdone)
1820 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1821 build_int_2 (bitsize - bitsdone, 0), 0, 1);
1825 if (bitsdone != thissize)
1826 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1827 build_int_2 (bitsdone - thissize, 0), 0, 1);
1833 /* Combine the parts with bitwise or. This works
1834 because we extracted each part as an unsigned bit field. */
1835 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
1841 /* Unsigned bit field: we are done. */
1844 /* Signed bit field: sign-extend with two arithmetic shifts. */
1845 result = expand_shift (LSHIFT_EXPR, word_mode, result,
1846 build_int_2 (BITS_PER_WORD - bitsize, 0),
1848 return expand_shift (RSHIFT_EXPR, word_mode, result,
1849 build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0);
1852 /* Add INC into TARGET. */
1855 expand_inc (target, inc)
1858 rtx value = expand_binop (GET_MODE (target), add_optab,
1860 target, 0, OPTAB_LIB_WIDEN);
1861 if (value != target)
1862 emit_move_insn (target, value);
1865 /* Subtract DEC from TARGET. */
1868 expand_dec (target, dec)
1871 rtx value = expand_binop (GET_MODE (target), sub_optab,
1873 target, 0, OPTAB_LIB_WIDEN);
1874 if (value != target)
1875 emit_move_insn (target, value);
1878 /* Output a shift instruction for expression code CODE,
1879 with SHIFTED being the rtx for the value to shift,
1880 and AMOUNT the tree for the amount to shift by.
1881 Store the result in the rtx TARGET, if that is convenient.
1882 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1883 Return the rtx for where the value is. */
1886 expand_shift (code, mode, shifted, amount, target, unsignedp)
1887 enum tree_code code;
1888 register enum machine_mode mode;
1891 register rtx target;
1894 register rtx op1, temp = 0;
1895 register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
1896 register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
1899 /* Previously detected shift-counts computed by NEGATE_EXPR
1900 and shifted in the other direction; but that does not work
1903 op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0);
1905 #ifdef SHIFT_COUNT_TRUNCATED
1906 if (SHIFT_COUNT_TRUNCATED)
1908 if (GET_CODE (op1) == CONST_INT
1909 && ((unsigned HOST_WIDE_INT) INTVAL (op1) >=
1910 (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))
1911 op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
1912 % GET_MODE_BITSIZE (mode));
1913 else if (GET_CODE (op1) == SUBREG
1914 && SUBREG_WORD (op1) == 0)
1915 op1 = SUBREG_REG (op1);
1919 if (op1 == const0_rtx)
1922 for (try = 0; temp == 0 && try < 3; try++)
1924 enum optab_methods methods;
1927 methods = OPTAB_DIRECT;
1929 methods = OPTAB_WIDEN;
1931 methods = OPTAB_LIB_WIDEN;
1935 /* Widening does not work for rotation. */
1936 if (methods == OPTAB_WIDEN)
1938 else if (methods == OPTAB_LIB_WIDEN)
1940 /* If we have been unable to open-code this by a rotation,
1941 do it as the IOR of two shifts. I.e., to rotate A
1942 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
1943 where C is the bitsize of A.
1945 It is theoretically possible that the target machine might
1946 not be able to perform either shift and hence we would
1947 be making two libcalls rather than just the one for the
1948 shift (similarly if IOR could not be done). We will allow
1949 this extremely unlikely lossage to avoid complicating the
1952 rtx subtarget = target == shifted ? 0 : target;
1954 tree type = TREE_TYPE (amount);
1955 tree new_amount = make_tree (type, op1);
1957 = fold (build (MINUS_EXPR, type,
1959 build_int_2 (GET_MODE_BITSIZE (mode),
1963 shifted = force_reg (mode, shifted);
1965 temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR,
1966 mode, shifted, new_amount, subtarget, 1);
1967 temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR,
1968 mode, shifted, other_amount, 0, 1);
1969 return expand_binop (mode, ior_optab, temp, temp1, target,
1970 unsignedp, methods);
1973 temp = expand_binop (mode,
1974 left ? rotl_optab : rotr_optab,
1975 shifted, op1, target, unsignedp, methods);
1977 /* If we don't have the rotate, but we are rotating by a constant
1978 that is in range, try a rotate in the opposite direction. */
1980 if (temp == 0 && GET_CODE (op1) == CONST_INT
1981 && INTVAL (op1) > 0 && INTVAL (op1) < GET_MODE_BITSIZE (mode))
1982 temp = expand_binop (mode,
1983 left ? rotr_optab : rotl_optab,
1985 GEN_INT (GET_MODE_BITSIZE (mode)
1987 target, unsignedp, methods);
1990 temp = expand_binop (mode,
1991 left ? ashl_optab : lshr_optab,
1992 shifted, op1, target, unsignedp, methods);
1994 /* Do arithmetic shifts.
1995 Also, if we are going to widen the operand, we can just as well
1996 use an arithmetic right-shift instead of a logical one. */
1997 if (temp == 0 && ! rotate
1998 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
2000 enum optab_methods methods1 = methods;
2002 /* If trying to widen a log shift to an arithmetic shift,
2003 don't accept an arithmetic shift of the same size. */
2005 methods1 = OPTAB_MUST_WIDEN;
2007 /* Arithmetic shift */
2009 temp = expand_binop (mode,
2010 left ? ashl_optab : ashr_optab,
2011 shifted, op1, target, unsignedp, methods1);
2014 /* We used to try extzv here for logical right shifts, but that was
2015 only useful for one machine, the VAX, and caused poor code
2016 generation there for lshrdi3, so the code was deleted and a
2017 define_expand for lshrsi3 was added to vax.md. */
2025 enum alg_code { alg_zero, alg_m, alg_shift,
2026 alg_add_t_m2, alg_sub_t_m2,
2027 alg_add_factor, alg_sub_factor,
2028 alg_add_t2_m, alg_sub_t2_m,
2029 alg_add, alg_subtract, alg_factor, alg_shiftop };
2031 /* This structure records a sequence of operations.
2032 `ops' is the number of operations recorded.
2033 `cost' is their total cost.
2034 The operations are stored in `op' and the corresponding
2035 logarithms of the integer coefficients in `log'.
2037 These are the operations:
2038 alg_zero total := 0;
2039 alg_m total := multiplicand;
2040 alg_shift total := total * coeff
2041 alg_add_t_m2 total := total + multiplicand * coeff;
2042 alg_sub_t_m2 total := total - multiplicand * coeff;
2043 alg_add_factor total := total * coeff + total;
2044 alg_sub_factor total := total * coeff - total;
2045 alg_add_t2_m total := total * coeff + multiplicand;
2046 alg_sub_t2_m total := total * coeff - multiplicand;
2048 The first operand must be either alg_zero or alg_m. */
2054 /* The size of the OP and LOG fields are not directly related to the
2055 word size, but the worst-case algorithms will be if we have few
2056 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2057 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2058 in total wordsize operations. */
2059 enum alg_code op[MAX_BITS_PER_WORD];
2060 char log[MAX_BITS_PER_WORD];
2063 static void synth_mult PARAMS ((struct algorithm *,
2064 unsigned HOST_WIDE_INT,
2066 static unsigned HOST_WIDE_INT choose_multiplier PARAMS ((unsigned HOST_WIDE_INT,
2068 unsigned HOST_WIDE_INT *,
2070 static unsigned HOST_WIDE_INT invert_mod2n PARAMS ((unsigned HOST_WIDE_INT,
2072 /* Compute and return the best algorithm for multiplying by T.
2073 The algorithm must cost less than cost_limit
2074 If retval.cost >= COST_LIMIT, no algorithm was found and all
2075 other field of the returned struct are undefined. */
2078 synth_mult (alg_out, t, cost_limit)
2079 struct algorithm *alg_out;
2080 unsigned HOST_WIDE_INT t;
2084 struct algorithm *alg_in, *best_alg;
2086 unsigned HOST_WIDE_INT q;
2088 /* Indicate that no algorithm is yet found. If no algorithm
2089 is found, this value will be returned and indicate failure. */
2090 alg_out->cost = cost_limit;
2092 if (cost_limit <= 0)
2095 /* t == 1 can be done in zero cost. */
2100 alg_out->op[0] = alg_m;
2104 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2108 if (zero_cost >= cost_limit)
2113 alg_out->cost = zero_cost;
2114 alg_out->op[0] = alg_zero;
2119 /* We'll be needing a couple extra algorithm structures now. */
2121 alg_in = (struct algorithm *)alloca (sizeof (struct algorithm));
2122 best_alg = (struct algorithm *)alloca (sizeof (struct algorithm));
2124 /* If we have a group of zero bits at the low-order part of T, try
2125 multiplying by the remaining bits and then doing a shift. */
2129 m = floor_log2 (t & -t); /* m = number of low zero bits */
2131 cost = shift_cost[m];
2132 synth_mult (alg_in, q, cost_limit - cost);
2134 cost += alg_in->cost;
2135 if (cost < cost_limit)
2137 struct algorithm *x;
2138 x = alg_in, alg_in = best_alg, best_alg = x;
2139 best_alg->log[best_alg->ops] = m;
2140 best_alg->op[best_alg->ops] = alg_shift;
2145 /* If we have an odd number, add or subtract one. */
2148 unsigned HOST_WIDE_INT w;
2150 for (w = 1; (w & t) != 0; w <<= 1)
2152 /* If T was -1, then W will be zero after the loop. This is another
2153 case where T ends with ...111. Handling this with (T + 1) and
2154 subtract 1 produces slightly better code and results in algorithm
2155 selection much faster than treating it like the ...0111 case
2159 /* Reject the case where t is 3.
2160 Thus we prefer addition in that case. */
2163 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2166 synth_mult (alg_in, t + 1, cost_limit - cost);
2168 cost += alg_in->cost;
2169 if (cost < cost_limit)
2171 struct algorithm *x;
2172 x = alg_in, alg_in = best_alg, best_alg = x;
2173 best_alg->log[best_alg->ops] = 0;
2174 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2180 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2183 synth_mult (alg_in, t - 1, cost_limit - cost);
2185 cost += alg_in->cost;
2186 if (cost < cost_limit)
2188 struct algorithm *x;
2189 x = alg_in, alg_in = best_alg, best_alg = x;
2190 best_alg->log[best_alg->ops] = 0;
2191 best_alg->op[best_alg->ops] = alg_add_t_m2;
2197 /* Look for factors of t of the form
2198 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2199 If we find such a factor, we can multiply by t using an algorithm that
2200 multiplies by q, shift the result by m and add/subtract it to itself.
2202 We search for large factors first and loop down, even if large factors
2203 are less probable than small; if we find a large factor we will find a
2204 good sequence quickly, and therefore be able to prune (by decreasing
2205 COST_LIMIT) the search. */
2207 for (m = floor_log2 (t - 1); m >= 2; m--)
2209 unsigned HOST_WIDE_INT d;
2211 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
2212 if (t % d == 0 && t > d)
2214 cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]);
2215 synth_mult (alg_in, t / d, cost_limit - cost);
2217 cost += alg_in->cost;
2218 if (cost < cost_limit)
2220 struct algorithm *x;
2221 x = alg_in, alg_in = best_alg, best_alg = x;
2222 best_alg->log[best_alg->ops] = m;
2223 best_alg->op[best_alg->ops] = alg_add_factor;
2226 /* Other factors will have been taken care of in the recursion. */
2230 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
2231 if (t % d == 0 && t > d)
2233 cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]);
2234 synth_mult (alg_in, t / d, cost_limit - cost);
2236 cost += alg_in->cost;
2237 if (cost < cost_limit)
2239 struct algorithm *x;
2240 x = alg_in, alg_in = best_alg, best_alg = x;
2241 best_alg->log[best_alg->ops] = m;
2242 best_alg->op[best_alg->ops] = alg_sub_factor;
2249 /* Try shift-and-add (load effective address) instructions,
2250 i.e. do a*3, a*5, a*9. */
2258 cost = shiftadd_cost[m];
2259 synth_mult (alg_in, (t - 1) >> m, cost_limit - cost);
2261 cost += alg_in->cost;
2262 if (cost < cost_limit)
2264 struct algorithm *x;
2265 x = alg_in, alg_in = best_alg, best_alg = x;
2266 best_alg->log[best_alg->ops] = m;
2267 best_alg->op[best_alg->ops] = alg_add_t2_m;
2277 cost = shiftsub_cost[m];
2278 synth_mult (alg_in, (t + 1) >> m, cost_limit - cost);
2280 cost += alg_in->cost;
2281 if (cost < cost_limit)
2283 struct algorithm *x;
2284 x = alg_in, alg_in = best_alg, best_alg = x;
2285 best_alg->log[best_alg->ops] = m;
2286 best_alg->op[best_alg->ops] = alg_sub_t2_m;
2292 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2293 we have not found any algorithm. */
2294 if (cost_limit == alg_out->cost)
2297 /* If we are getting a too long sequence for `struct algorithm'
2298 to record, make this search fail. */
2299 if (best_alg->ops == MAX_BITS_PER_WORD)
2302 /* Copy the algorithm from temporary space to the space at alg_out.
2303 We avoid using structure assignment because the majority of
2304 best_alg is normally undefined, and this is a critical function. */
2305 alg_out->ops = best_alg->ops + 1;
2306 alg_out->cost = cost_limit;
2307 bcopy ((char *) best_alg->op, (char *) alg_out->op,
2308 alg_out->ops * sizeof *alg_out->op);
2309 bcopy ((char *) best_alg->log, (char *) alg_out->log,
2310 alg_out->ops * sizeof *alg_out->log);
2313 /* Perform a multiplication and return an rtx for the result.
2314 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2315 TARGET is a suggestion for where to store the result (an rtx).
2317 We check specially for a constant integer as OP1.
2318 If you want this check for OP0 as well, then before calling
2319 you should swap the two operands if OP0 would be constant. */
2322 expand_mult (mode, op0, op1, target, unsignedp)
2323 enum machine_mode mode;
2324 register rtx op0, op1, target;
2327 rtx const_op1 = op1;
2329 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2330 less than or equal in size to `unsigned int' this doesn't matter.
2331 If the mode is larger than `unsigned int', then synth_mult works only
2332 if the constant value exactly fits in an `unsigned int' without any
2333 truncation. This means that multiplying by negative values does
2334 not work; results are off by 2^32 on a 32 bit machine. */
2336 /* If we are multiplying in DImode, it may still be a win
2337 to try to work with shifts and adds. */
2338 if (GET_CODE (op1) == CONST_DOUBLE
2339 && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT
2340 && HOST_BITS_PER_INT >= BITS_PER_WORD
2341 && CONST_DOUBLE_HIGH (op1) == 0)
2342 const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2343 else if (HOST_BITS_PER_INT < GET_MODE_BITSIZE (mode)
2344 && GET_CODE (op1) == CONST_INT
2345 && INTVAL (op1) < 0)
2348 /* We used to test optimize here, on the grounds that it's better to
2349 produce a smaller program when -O is not used.
2350 But this causes such a terrible slowdown sometimes
2351 that it seems better to use synth_mult always. */
2353 if (const_op1 && GET_CODE (const_op1) == CONST_INT)
2355 struct algorithm alg;
2356 struct algorithm alg2;
2357 HOST_WIDE_INT val = INTVAL (op1);
2358 HOST_WIDE_INT val_so_far;
2361 enum {basic_variant, negate_variant, add_variant} variant = basic_variant;
2363 /* Try to do the computation three ways: multiply by the negative of OP1
2364 and then negate, do the multiplication directly, or do multiplication
2367 mult_cost = rtx_cost (gen_rtx_MULT (mode, op0, op1), SET);
2368 mult_cost = MIN (12 * add_cost, mult_cost);
2370 synth_mult (&alg, val, mult_cost);
2372 /* This works only if the inverted value actually fits in an
2374 if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode))
2376 synth_mult (&alg2, - val,
2377 (alg.cost < mult_cost ? alg.cost : mult_cost) - negate_cost);
2378 if (alg2.cost + negate_cost < alg.cost)
2379 alg = alg2, variant = negate_variant;
2382 /* This proves very useful for division-by-constant. */
2383 synth_mult (&alg2, val - 1,
2384 (alg.cost < mult_cost ? alg.cost : mult_cost) - add_cost);
2385 if (alg2.cost + add_cost < alg.cost)
2386 alg = alg2, variant = add_variant;
2388 if (alg.cost < mult_cost)
2390 /* We found something cheaper than a multiply insn. */
2394 op0 = protect_from_queue (op0, 0);
2396 /* Avoid referencing memory over and over.
2397 For speed, but also for correctness when mem is volatile. */
2398 if (GET_CODE (op0) == MEM)
2399 op0 = force_reg (mode, op0);
2401 /* ACCUM starts out either as OP0 or as a zero, depending on
2402 the first operation. */
2404 if (alg.op[0] == alg_zero)
2406 accum = copy_to_mode_reg (mode, const0_rtx);
2409 else if (alg.op[0] == alg_m)
2411 accum = copy_to_mode_reg (mode, op0);
2417 for (opno = 1; opno < alg.ops; opno++)
2419 int log = alg.log[opno];
2420 int preserve = preserve_subexpressions_p ();
2421 rtx shift_subtarget = preserve ? 0 : accum;
2423 = (opno == alg.ops - 1 && target != 0 && variant != add_variant
2426 rtx accum_target = preserve ? 0 : accum;
2428 switch (alg.op[opno])
2431 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2432 build_int_2 (log, 0), NULL_RTX, 0);
2437 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2438 build_int_2 (log, 0), NULL_RTX, 0);
2439 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2441 ? add_target : accum_target);
2442 val_so_far += (HOST_WIDE_INT) 1 << log;
2446 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2447 build_int_2 (log, 0), NULL_RTX, 0);
2448 accum = force_operand (gen_rtx_MINUS (mode, accum, tem),
2450 ? add_target : accum_target);
2451 val_so_far -= (HOST_WIDE_INT) 1 << log;
2455 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2456 build_int_2 (log, 0), shift_subtarget,
2458 accum = force_operand (gen_rtx_PLUS (mode, accum, op0),
2460 ? add_target : accum_target);
2461 val_so_far = (val_so_far << log) + 1;
2465 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2466 build_int_2 (log, 0), shift_subtarget,
2468 accum = force_operand (gen_rtx_MINUS (mode, accum, op0),
2470 ? add_target : accum_target);
2471 val_so_far = (val_so_far << log) - 1;
2474 case alg_add_factor:
2475 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2476 build_int_2 (log, 0), NULL_RTX, 0);
2477 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2479 ? add_target : accum_target);
2480 val_so_far += val_so_far << log;
2483 case alg_sub_factor:
2484 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2485 build_int_2 (log, 0), NULL_RTX, 0);
2486 accum = force_operand (gen_rtx_MINUS (mode, tem, accum),
2487 (add_target ? add_target
2488 : preserve ? 0 : tem));
2489 val_so_far = (val_so_far << log) - val_so_far;
2496 /* Write a REG_EQUAL note on the last insn so that we can cse
2497 multiplication sequences. */
2499 insn = get_last_insn ();
2500 set_unique_reg_note (insn,
2502 gen_rtx_MULT (mode, op0,
2503 GEN_INT (val_so_far)));
2506 if (variant == negate_variant)
2508 val_so_far = - val_so_far;
2509 accum = expand_unop (mode, neg_optab, accum, target, 0);
2511 else if (variant == add_variant)
2513 val_so_far = val_so_far + 1;
2514 accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target);
2517 if (val != val_so_far)
2524 /* This used to use umul_optab if unsigned, but for non-widening multiply
2525 there is no difference between signed and unsigned. */
2526 op0 = expand_binop (mode, smul_optab,
2527 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
2533 /* Return the smallest n such that 2**n >= X. */
2537 unsigned HOST_WIDE_INT x;
2539 return floor_log2 (x - 1) + 1;
2542 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2543 replace division by D, and put the least significant N bits of the result
2544 in *MULTIPLIER_PTR and return the most significant bit.
2546 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2547 needed precision is in PRECISION (should be <= N).
2549 PRECISION should be as small as possible so this function can choose
2550 multiplier more freely.
2552 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2553 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2555 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2556 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2559 unsigned HOST_WIDE_INT
2560 choose_multiplier (d, n, precision, multiplier_ptr, post_shift_ptr, lgup_ptr)
2561 unsigned HOST_WIDE_INT d;
2564 unsigned HOST_WIDE_INT *multiplier_ptr;
2565 int *post_shift_ptr;
2568 HOST_WIDE_INT mhigh_hi, mlow_hi;
2569 unsigned HOST_WIDE_INT mhigh_lo, mlow_lo;
2570 int lgup, post_shift;
2572 unsigned HOST_WIDE_INT nl, dummy1;
2573 HOST_WIDE_INT nh, dummy2;
2575 /* lgup = ceil(log2(divisor)); */
2576 lgup = ceil_log2 (d);
2582 pow2 = n + lgup - precision;
2584 if (pow == 2 * HOST_BITS_PER_WIDE_INT)
2586 /* We could handle this with some effort, but this case is much better
2587 handled directly with a scc insn, so rely on caller using that. */
2591 /* mlow = 2^(N + lgup)/d */
2592 if (pow >= HOST_BITS_PER_WIDE_INT)
2594 nh = (HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT);
2600 nl = (unsigned HOST_WIDE_INT) 1 << pow;
2602 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2603 &mlow_lo, &mlow_hi, &dummy1, &dummy2);
2605 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2606 if (pow2 >= HOST_BITS_PER_WIDE_INT)
2607 nh |= (HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT);
2609 nl |= (unsigned HOST_WIDE_INT) 1 << pow2;
2610 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2611 &mhigh_lo, &mhigh_hi, &dummy1, &dummy2);
2613 if (mhigh_hi && nh - d >= d)
2615 if (mhigh_hi > 1 || mlow_hi > 1)
2617 /* assert that mlow < mhigh. */
2618 if (! (mlow_hi < mhigh_hi || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo)))
2621 /* If precision == N, then mlow, mhigh exceed 2^N
2622 (but they do not exceed 2^(N+1)). */
2624 /* Reduce to lowest terms */
2625 for (post_shift = lgup; post_shift > 0; post_shift--)
2627 unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1);
2628 unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1);
2638 *post_shift_ptr = post_shift;
2640 if (n < HOST_BITS_PER_WIDE_INT)
2642 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1;
2643 *multiplier_ptr = mhigh_lo & mask;
2644 return mhigh_lo >= mask;
2648 *multiplier_ptr = mhigh_lo;
2653 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2654 congruent to 1 (mod 2**N). */
2656 static unsigned HOST_WIDE_INT
2658 unsigned HOST_WIDE_INT x;
2661 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2663 /* The algorithm notes that the choice y = x satisfies
2664 x*y == 1 mod 2^3, since x is assumed odd.
2665 Each iteration doubles the number of bits of significance in y. */
2667 unsigned HOST_WIDE_INT mask;
2668 unsigned HOST_WIDE_INT y = x;
2671 mask = (n == HOST_BITS_PER_WIDE_INT
2672 ? ~(unsigned HOST_WIDE_INT) 0
2673 : ((unsigned HOST_WIDE_INT) 1 << n) - 1);
2677 y = y * (2 - x*y) & mask; /* Modulo 2^N */
2683 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2684 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2685 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2686 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2689 The result is put in TARGET if that is convenient.
2691 MODE is the mode of operation. */
2694 expand_mult_highpart_adjust (mode, adj_operand, op0, op1, target, unsignedp)
2695 enum machine_mode mode;
2696 register rtx adj_operand, op0, op1, target;
2700 enum rtx_code adj_code = unsignedp ? PLUS : MINUS;
2702 tem = expand_shift (RSHIFT_EXPR, mode, op0,
2703 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2705 tem = expand_and (tem, op1, NULL_RTX);
2707 = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
2710 tem = expand_shift (RSHIFT_EXPR, mode, op1,
2711 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2713 tem = expand_and (tem, op0, NULL_RTX);
2714 target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
2720 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
2721 in TARGET if that is convenient, and return where the result is. If the
2722 operation can not be performed, 0 is returned.
2724 MODE is the mode of operation and result.
2726 UNSIGNEDP nonzero means unsigned multiply.
2728 MAX_COST is the total allowed cost for the expanded RTL. */
2731 expand_mult_highpart (mode, op0, cnst1, target, unsignedp, max_cost)
2732 enum machine_mode mode;
2733 register rtx op0, target;
2734 unsigned HOST_WIDE_INT cnst1;
2738 enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode);
2739 optab mul_highpart_optab;
2742 int size = GET_MODE_BITSIZE (mode);
2745 /* We can't support modes wider than HOST_BITS_PER_INT. */
2746 if (size > HOST_BITS_PER_WIDE_INT)
2749 op1 = GEN_INT (cnst1);
2751 if (GET_MODE_BITSIZE (wider_mode) <= HOST_BITS_PER_INT)
2755 = immed_double_const (cnst1,
2758 : -(cnst1 >> (HOST_BITS_PER_WIDE_INT - 1))),
2761 /* expand_mult handles constant multiplication of word_mode
2762 or narrower. It does a poor job for large modes. */
2763 if (size < BITS_PER_WORD
2764 && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost)
2766 /* We have to do this, since expand_binop doesn't do conversion for
2767 multiply. Maybe change expand_binop to handle widening multiply? */
2768 op0 = convert_to_mode (wider_mode, op0, unsignedp);
2770 tem = expand_mult (wider_mode, op0, wide_op1, NULL_RTX, unsignedp);
2771 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2772 build_int_2 (size, 0), NULL_RTX, 1);
2773 return convert_modes (mode, wider_mode, tem, unsignedp);
2777 target = gen_reg_rtx (mode);
2779 /* Firstly, try using a multiplication insn that only generates the needed
2780 high part of the product, and in the sign flavor of unsignedp. */
2781 if (mul_highpart_cost[(int) mode] < max_cost)
2783 mul_highpart_optab = unsignedp ? umul_highpart_optab : smul_highpart_optab;
2784 target = expand_binop (mode, mul_highpart_optab,
2785 op0, op1, target, unsignedp, OPTAB_DIRECT);
2790 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2791 Need to adjust the result after the multiplication. */
2792 if (mul_highpart_cost[(int) mode] + 2 * shift_cost[size-1] + 4 * add_cost < max_cost)
2794 mul_highpart_optab = unsignedp ? smul_highpart_optab : umul_highpart_optab;
2795 target = expand_binop (mode, mul_highpart_optab,
2796 op0, op1, target, unsignedp, OPTAB_DIRECT);
2798 /* We used the wrong signedness. Adjust the result. */
2799 return expand_mult_highpart_adjust (mode, target, op0,
2800 op1, target, unsignedp);
2803 /* Try widening multiplication. */
2804 moptab = unsignedp ? umul_widen_optab : smul_widen_optab;
2805 if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
2806 && mul_widen_cost[(int) wider_mode] < max_cost)
2808 op1 = force_reg (mode, op1);
2812 /* Try widening the mode and perform a non-widening multiplication. */
2813 moptab = smul_optab;
2814 if (smul_optab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
2815 && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost)
2821 /* Try widening multiplication of opposite signedness, and adjust. */
2822 moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
2823 if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
2824 && (mul_widen_cost[(int) wider_mode]
2825 + 2 * shift_cost[size-1] + 4 * add_cost < max_cost))
2827 rtx regop1 = force_reg (mode, op1);
2828 tem = expand_binop (wider_mode, moptab, op0, regop1,
2829 NULL_RTX, ! unsignedp, OPTAB_WIDEN);
2832 /* Extract the high half of the just generated product. */
2833 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2834 build_int_2 (size, 0), NULL_RTX, 1);
2835 tem = convert_modes (mode, wider_mode, tem, unsignedp);
2836 /* We used the wrong signedness. Adjust the result. */
2837 return expand_mult_highpart_adjust (mode, tem, op0, op1,
2845 /* Pass NULL_RTX as target since TARGET has wrong mode. */
2846 tem = expand_binop (wider_mode, moptab, op0, op1,
2847 NULL_RTX, unsignedp, OPTAB_WIDEN);
2851 /* Extract the high half of the just generated product. */
2852 if (mode == word_mode)
2854 return gen_highpart (mode, tem);
2858 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2859 build_int_2 (size, 0), NULL_RTX, 1);
2860 return convert_modes (mode, wider_mode, tem, unsignedp);
2864 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2865 if that is convenient, and returning where the result is.
2866 You may request either the quotient or the remainder as the result;
2867 specify REM_FLAG nonzero to get the remainder.
2869 CODE is the expression code for which kind of division this is;
2870 it controls how rounding is done. MODE is the machine mode to use.
2871 UNSIGNEDP nonzero means do unsigned division. */
2873 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2874 and then correct it by or'ing in missing high bits
2875 if result of ANDI is nonzero.
2876 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2877 This could optimize to a bfexts instruction.
2878 But C doesn't use these operations, so their optimizations are
2880 /* ??? For modulo, we don't actually need the highpart of the first product,
2881 the low part will do nicely. And for small divisors, the second multiply
2882 can also be a low-part only multiply or even be completely left out.
2883 E.g. to calculate the remainder of a division by 3 with a 32 bit
2884 multiply, multiply with 0x55555556 and extract the upper two bits;
2885 the result is exact for inputs up to 0x1fffffff.
2886 The input range can be reduced by using cross-sum rules.
2887 For odd divisors >= 3, the following table gives right shift counts
2888 so that if an number is shifted by an integer multiple of the given
2889 amount, the remainder stays the same:
2890 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
2891 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
2892 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
2893 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
2894 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
2896 Cross-sum rules for even numbers can be derived by leaving as many bits
2897 to the right alone as the divisor has zeros to the right.
2898 E.g. if x is an unsigned 32 bit number:
2899 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
2902 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
2905 expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp)
2907 enum tree_code code;
2908 enum machine_mode mode;
2909 register rtx op0, op1, target;
2912 enum machine_mode compute_mode;
2913 register rtx tquotient;
2914 rtx quotient = 0, remainder = 0;
2918 optab optab1, optab2;
2919 int op1_is_constant, op1_is_pow2;
2920 int max_cost, extra_cost;
2921 static HOST_WIDE_INT last_div_const = 0;
2923 op1_is_constant = GET_CODE (op1) == CONST_INT;
2924 op1_is_pow2 = (op1_is_constant
2925 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
2926 || (! unsignedp && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1))))));
2929 This is the structure of expand_divmod:
2931 First comes code to fix up the operands so we can perform the operations
2932 correctly and efficiently.
2934 Second comes a switch statement with code specific for each rounding mode.
2935 For some special operands this code emits all RTL for the desired
2936 operation, for other cases, it generates only a quotient and stores it in
2937 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
2938 to indicate that it has not done anything.
2940 Last comes code that finishes the operation. If QUOTIENT is set and
2941 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
2942 QUOTIENT is not set, it is computed using trunc rounding.
2944 We try to generate special code for division and remainder when OP1 is a
2945 constant. If |OP1| = 2**n we can use shifts and some other fast
2946 operations. For other values of OP1, we compute a carefully selected
2947 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
2950 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
2951 half of the product. Different strategies for generating the product are
2952 implemented in expand_mult_highpart.
2954 If what we actually want is the remainder, we generate that by another
2955 by-constant multiplication and a subtraction. */
2957 /* We shouldn't be called with OP1 == const1_rtx, but some of the
2958 code below will malfunction if we are, so check here and handle
2959 the special case if so. */
2960 if (op1 == const1_rtx)
2961 return rem_flag ? const0_rtx : op0;
2964 /* Don't use the function value register as a target
2965 since we have to read it as well as write it,
2966 and function-inlining gets confused by this. */
2967 && ((REG_P (target) && REG_FUNCTION_VALUE_P (target))
2968 /* Don't clobber an operand while doing a multi-step calculation. */
2969 || ((rem_flag || op1_is_constant)
2970 && (reg_mentioned_p (target, op0)
2971 || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM)))
2972 || reg_mentioned_p (target, op1)
2973 || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM)))
2976 /* Get the mode in which to perform this computation. Normally it will
2977 be MODE, but sometimes we can't do the desired operation in MODE.
2978 If so, pick a wider mode in which we can do the operation. Convert
2979 to that mode at the start to avoid repeated conversions.
2981 First see what operations we need. These depend on the expression
2982 we are evaluating. (We assume that divxx3 insns exist under the
2983 same conditions that modxx3 insns and that these insns don't normally
2984 fail. If these assumptions are not correct, we may generate less
2985 efficient code in some cases.)
2987 Then see if we find a mode in which we can open-code that operation
2988 (either a division, modulus, or shift). Finally, check for the smallest
2989 mode for which we can do the operation with a library call. */
2991 /* We might want to refine this now that we have division-by-constant
2992 optimization. Since expand_mult_highpart tries so many variants, it is
2993 not straightforward to generalize this. Maybe we should make an array
2994 of possible modes in init_expmed? Save this for GCC 2.7. */
2996 optab1 = (op1_is_pow2 ? (unsignedp ? lshr_optab : ashr_optab)
2997 : (unsignedp ? udiv_optab : sdiv_optab));
2998 optab2 = (op1_is_pow2 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab));
3000 for (compute_mode = mode; compute_mode != VOIDmode;
3001 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3002 if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing
3003 || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing)
3006 if (compute_mode == VOIDmode)
3007 for (compute_mode = mode; compute_mode != VOIDmode;
3008 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3009 if (optab1->handlers[(int) compute_mode].libfunc
3010 || optab2->handlers[(int) compute_mode].libfunc)
3013 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3015 if (compute_mode == VOIDmode)
3016 compute_mode = mode;
3018 if (target && GET_MODE (target) == compute_mode)
3021 tquotient = gen_reg_rtx (compute_mode);
3023 size = GET_MODE_BITSIZE (compute_mode);
3025 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3026 (mode), and thereby get better code when OP1 is a constant. Do that
3027 later. It will require going over all usages of SIZE below. */
3028 size = GET_MODE_BITSIZE (mode);
3031 /* Only deduct something for a REM if the last divide done was
3032 for a different constant. Then set the constant of the last
3034 max_cost = div_cost[(int) compute_mode]
3035 - (rem_flag && ! (last_div_const != 0 && op1_is_constant
3036 && INTVAL (op1) == last_div_const)
3037 ? mul_cost[(int) compute_mode] + add_cost : 0);
3039 last_div_const = ! rem_flag && op1_is_constant ? INTVAL (op1) : 0;
3041 /* Now convert to the best mode to use. */
3042 if (compute_mode != mode)
3044 op0 = convert_modes (compute_mode, mode, op0, unsignedp);
3045 op1 = convert_modes (compute_mode, mode, op1, unsignedp);
3047 /* convert_modes may have placed op1 into a register, so we
3048 must recompute the following. */
3049 op1_is_constant = GET_CODE (op1) == CONST_INT;
3050 op1_is_pow2 = (op1_is_constant
3051 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3053 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))) ;
3056 /* If one of the operands is a volatile MEM, copy it into a register. */
3058 if (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0))
3059 op0 = force_reg (compute_mode, op0);
3060 if (GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1))
3061 op1 = force_reg (compute_mode, op1);
3063 /* If we need the remainder or if OP1 is constant, we need to
3064 put OP0 in a register in case it has any queued subexpressions. */
3065 if (rem_flag || op1_is_constant)
3066 op0 = force_reg (compute_mode, op0);
3068 last = get_last_insn ();
3070 /* Promote floor rounding to trunc rounding for unsigned operations. */
3073 if (code == FLOOR_DIV_EXPR)
3074 code = TRUNC_DIV_EXPR;
3075 if (code == FLOOR_MOD_EXPR)
3076 code = TRUNC_MOD_EXPR;
3077 if (code == EXACT_DIV_EXPR && op1_is_pow2)
3078 code = TRUNC_DIV_EXPR;
3081 if (op1 != const0_rtx)
3084 case TRUNC_MOD_EXPR:
3085 case TRUNC_DIV_EXPR:
3086 if (op1_is_constant)
3090 unsigned HOST_WIDE_INT mh, ml;
3091 int pre_shift, post_shift;
3093 unsigned HOST_WIDE_INT d = INTVAL (op1);
3095 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3097 pre_shift = floor_log2 (d);
3101 = expand_binop (compute_mode, and_optab, op0,
3102 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3106 return gen_lowpart (mode, remainder);
3108 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3109 build_int_2 (pre_shift, 0),
3112 else if (size <= HOST_BITS_PER_WIDE_INT)
3114 if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1)))
3116 /* Most significant bit of divisor is set; emit an scc
3118 quotient = emit_store_flag (tquotient, GEU, op0, op1,
3119 compute_mode, 1, 1);
3125 /* Find a suitable multiplier and right shift count
3126 instead of multiplying with D. */
3128 mh = choose_multiplier (d, size, size,
3129 &ml, &post_shift, &dummy);
3131 /* If the suggested multiplier is more than SIZE bits,
3132 we can do better for even divisors, using an
3133 initial right shift. */
3134 if (mh != 0 && (d & 1) == 0)
3136 pre_shift = floor_log2 (d & -d);
3137 mh = choose_multiplier (d >> pre_shift, size,
3139 &ml, &post_shift, &dummy);
3150 extra_cost = (shift_cost[post_shift - 1]
3151 + shift_cost[1] + 2 * add_cost);
3152 t1 = expand_mult_highpart (compute_mode, op0, ml,
3154 max_cost - extra_cost);
3157 t2 = force_operand (gen_rtx_MINUS (compute_mode,
3160 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3161 build_int_2 (1, 0), NULL_RTX,1);
3162 t4 = force_operand (gen_rtx_PLUS (compute_mode,
3166 = expand_shift (RSHIFT_EXPR, compute_mode, t4,
3167 build_int_2 (post_shift - 1, 0),
3174 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3175 build_int_2 (pre_shift, 0),
3177 extra_cost = (shift_cost[pre_shift]
3178 + shift_cost[post_shift]);
3179 t2 = expand_mult_highpart (compute_mode, t1, ml,
3181 max_cost - extra_cost);
3185 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3186 build_int_2 (post_shift, 0),
3191 else /* Too wide mode to use tricky code */
3194 insn = get_last_insn ();
3196 && (set = single_set (insn)) != 0
3197 && SET_DEST (set) == quotient)
3198 set_unique_reg_note (insn,
3200 gen_rtx_UDIV (compute_mode, op0, op1));
3202 else /* TRUNC_DIV, signed */
3204 unsigned HOST_WIDE_INT ml;
3205 int lgup, post_shift;
3206 HOST_WIDE_INT d = INTVAL (op1);
3207 unsigned HOST_WIDE_INT abs_d = d >= 0 ? d : -d;
3209 /* n rem d = n rem -d */
3210 if (rem_flag && d < 0)
3213 op1 = GEN_INT (abs_d);
3219 quotient = expand_unop (compute_mode, neg_optab, op0,
3221 else if (abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1))
3223 /* This case is not handled correctly below. */
3224 quotient = emit_store_flag (tquotient, EQ, op0, op1,
3225 compute_mode, 1, 1);
3229 else if (EXACT_POWER_OF_2_OR_ZERO_P (d)
3230 && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap))
3232 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d))
3234 lgup = floor_log2 (abs_d);
3235 if (abs_d != 2 && BRANCH_COST < 3)
3237 rtx label = gen_label_rtx ();
3240 t1 = copy_to_mode_reg (compute_mode, op0);
3241 do_cmp_and_jump (t1, const0_rtx, GE,
3242 compute_mode, label);
3243 expand_inc (t1, GEN_INT (abs_d - 1));
3245 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3246 build_int_2 (lgup, 0),
3252 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3253 build_int_2 (size - 1, 0),
3255 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3256 build_int_2 (size - lgup, 0),
3258 t3 = force_operand (gen_rtx_PLUS (compute_mode,
3261 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3262 build_int_2 (lgup, 0),
3266 /* We have computed OP0 / abs(OP1). If OP1 is negative, negate
3270 insn = get_last_insn ();
3272 && (set = single_set (insn)) != 0
3273 && SET_DEST (set) == quotient
3274 && abs_d < ((unsigned HOST_WIDE_INT) 1
3275 << (HOST_BITS_PER_WIDE_INT - 1)))
3276 set_unique_reg_note (insn,
3278 gen_rtx_DIV (compute_mode,
3282 quotient = expand_unop (compute_mode, neg_optab,
3283 quotient, quotient, 0);
3286 else if (size <= HOST_BITS_PER_WIDE_INT)
3288 choose_multiplier (abs_d, size, size - 1,
3289 &ml, &post_shift, &lgup);
3290 if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1))
3294 extra_cost = (shift_cost[post_shift]
3295 + shift_cost[size - 1] + add_cost);
3296 t1 = expand_mult_highpart (compute_mode, op0, ml,
3298 max_cost - extra_cost);
3301 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3302 build_int_2 (post_shift, 0), NULL_RTX, 0);
3303 t3 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3304 build_int_2 (size - 1, 0), NULL_RTX, 0);
3307 = force_operand (gen_rtx_MINUS (compute_mode,
3312 = force_operand (gen_rtx_MINUS (compute_mode,
3320 ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1);
3321 extra_cost = (shift_cost[post_shift]
3322 + shift_cost[size - 1] + 2 * add_cost);
3323 t1 = expand_mult_highpart (compute_mode, op0, ml,
3325 max_cost - extra_cost);
3328 t2 = force_operand (gen_rtx_PLUS (compute_mode,
3331 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3332 build_int_2 (post_shift, 0),
3334 t4 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3335 build_int_2 (size - 1, 0),
3339 = force_operand (gen_rtx_MINUS (compute_mode,
3344 = force_operand (gen_rtx_MINUS (compute_mode,
3349 else /* Too wide mode to use tricky code */
3352 insn = get_last_insn ();
3354 && (set = single_set (insn)) != 0
3355 && SET_DEST (set) == quotient)
3356 set_unique_reg_note (insn,
3358 gen_rtx_DIV (compute_mode, op0, op1));
3363 delete_insns_since (last);
3366 case FLOOR_DIV_EXPR:
3367 case FLOOR_MOD_EXPR:
3368 /* We will come here only for signed operations. */
3369 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3371 unsigned HOST_WIDE_INT mh, ml;
3372 int pre_shift, lgup, post_shift;
3373 HOST_WIDE_INT d = INTVAL (op1);
3377 /* We could just as easily deal with negative constants here,
3378 but it does not seem worth the trouble for GCC 2.6. */
3379 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3381 pre_shift = floor_log2 (d);
3384 remainder = expand_binop (compute_mode, and_optab, op0,
3385 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3386 remainder, 0, OPTAB_LIB_WIDEN);
3388 return gen_lowpart (mode, remainder);
3390 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3391 build_int_2 (pre_shift, 0),
3398 mh = choose_multiplier (d, size, size - 1,
3399 &ml, &post_shift, &lgup);
3403 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3404 build_int_2 (size - 1, 0), NULL_RTX, 0);
3405 t2 = expand_binop (compute_mode, xor_optab, op0, t1,
3406 NULL_RTX, 0, OPTAB_WIDEN);
3407 extra_cost = (shift_cost[post_shift]
3408 + shift_cost[size - 1] + 2 * add_cost);
3409 t3 = expand_mult_highpart (compute_mode, t2, ml,
3411 max_cost - extra_cost);
3414 t4 = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3415 build_int_2 (post_shift, 0),
3417 quotient = expand_binop (compute_mode, xor_optab,
3418 t4, t1, tquotient, 0,
3425 rtx nsign, t1, t2, t3, t4;
3426 t1 = force_operand (gen_rtx_PLUS (compute_mode,
3427 op0, constm1_rtx), NULL_RTX);
3428 t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX,
3430 nsign = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3431 build_int_2 (size - 1, 0), NULL_RTX, 0);
3432 t3 = force_operand (gen_rtx_MINUS (compute_mode, t1, nsign),
3434 t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1,
3439 t5 = expand_unop (compute_mode, one_cmpl_optab, nsign,
3441 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3450 delete_insns_since (last);
3452 /* Try using an instruction that produces both the quotient and
3453 remainder, using truncation. We can easily compensate the quotient
3454 or remainder to get floor rounding, once we have the remainder.
3455 Notice that we compute also the final remainder value here,
3456 and return the result right away. */
3457 if (target == 0 || GET_MODE (target) != compute_mode)
3458 target = gen_reg_rtx (compute_mode);
3463 = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
3464 quotient = gen_reg_rtx (compute_mode);
3469 = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
3470 remainder = gen_reg_rtx (compute_mode);
3473 if (expand_twoval_binop (sdivmod_optab, op0, op1,
3474 quotient, remainder, 0))
3476 /* This could be computed with a branch-less sequence.
3477 Save that for later. */
3479 rtx label = gen_label_rtx ();
3480 do_cmp_and_jump (remainder, const0_rtx, EQ, compute_mode, label);
3481 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3482 NULL_RTX, 0, OPTAB_WIDEN);
3483 do_cmp_and_jump (tem, const0_rtx, GE, compute_mode, label);
3484 expand_dec (quotient, const1_rtx);
3485 expand_inc (remainder, op1);
3487 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3490 /* No luck with division elimination or divmod. Have to do it
3491 by conditionally adjusting op0 *and* the result. */
3493 rtx label1, label2, label3, label4, label5;
3497 quotient = gen_reg_rtx (compute_mode);
3498 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3499 label1 = gen_label_rtx ();
3500 label2 = gen_label_rtx ();
3501 label3 = gen_label_rtx ();
3502 label4 = gen_label_rtx ();
3503 label5 = gen_label_rtx ();
3504 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
3505 do_cmp_and_jump (adjusted_op0, const0_rtx, LT, compute_mode, label1);
3506 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3507 quotient, 0, OPTAB_LIB_WIDEN);
3508 if (tem != quotient)
3509 emit_move_insn (quotient, tem);
3510 emit_jump_insn (gen_jump (label5));
3512 emit_label (label1);
3513 expand_inc (adjusted_op0, const1_rtx);
3514 emit_jump_insn (gen_jump (label4));
3516 emit_label (label2);
3517 do_cmp_and_jump (adjusted_op0, const0_rtx, GT, compute_mode, label3);
3518 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3519 quotient, 0, OPTAB_LIB_WIDEN);
3520 if (tem != quotient)
3521 emit_move_insn (quotient, tem);
3522 emit_jump_insn (gen_jump (label5));
3524 emit_label (label3);
3525 expand_dec (adjusted_op0, const1_rtx);
3526 emit_label (label4);
3527 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3528 quotient, 0, OPTAB_LIB_WIDEN);
3529 if (tem != quotient)
3530 emit_move_insn (quotient, tem);
3531 expand_dec (quotient, const1_rtx);
3532 emit_label (label5);
3540 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)))
3543 unsigned HOST_WIDE_INT d = INTVAL (op1);
3544 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3545 build_int_2 (floor_log2 (d), 0),
3547 t2 = expand_binop (compute_mode, and_optab, op0,
3549 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3550 t3 = gen_reg_rtx (compute_mode);
3551 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3552 compute_mode, 1, 1);
3556 lab = gen_label_rtx ();
3557 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
3558 expand_inc (t1, const1_rtx);
3563 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3569 /* Try using an instruction that produces both the quotient and
3570 remainder, using truncation. We can easily compensate the
3571 quotient or remainder to get ceiling rounding, once we have the
3572 remainder. Notice that we compute also the final remainder
3573 value here, and return the result right away. */
3574 if (target == 0 || GET_MODE (target) != compute_mode)
3575 target = gen_reg_rtx (compute_mode);
3579 remainder = (GET_CODE (target) == REG
3580 ? target : gen_reg_rtx (compute_mode));
3581 quotient = gen_reg_rtx (compute_mode);
3585 quotient = (GET_CODE (target) == REG
3586 ? target : gen_reg_rtx (compute_mode));
3587 remainder = gen_reg_rtx (compute_mode);
3590 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient,
3593 /* This could be computed with a branch-less sequence.
3594 Save that for later. */
3595 rtx label = gen_label_rtx ();
3596 do_cmp_and_jump (remainder, const0_rtx, EQ,
3597 compute_mode, label);
3598 expand_inc (quotient, const1_rtx);
3599 expand_dec (remainder, op1);
3601 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3604 /* No luck with division elimination or divmod. Have to do it
3605 by conditionally adjusting op0 *and* the result. */
3608 rtx adjusted_op0, tem;
3610 quotient = gen_reg_rtx (compute_mode);
3611 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3612 label1 = gen_label_rtx ();
3613 label2 = gen_label_rtx ();
3614 do_cmp_and_jump (adjusted_op0, const0_rtx, NE,
3615 compute_mode, label1);
3616 emit_move_insn (quotient, const0_rtx);
3617 emit_jump_insn (gen_jump (label2));
3619 emit_label (label1);
3620 expand_dec (adjusted_op0, const1_rtx);
3621 tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1,
3622 quotient, 1, OPTAB_LIB_WIDEN);
3623 if (tem != quotient)
3624 emit_move_insn (quotient, tem);
3625 expand_inc (quotient, const1_rtx);
3626 emit_label (label2);
3631 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3632 && INTVAL (op1) >= 0)
3634 /* This is extremely similar to the code for the unsigned case
3635 above. For 2.7 we should merge these variants, but for
3636 2.6.1 I don't want to touch the code for unsigned since that
3637 get used in C. The signed case will only be used by other
3641 unsigned HOST_WIDE_INT d = INTVAL (op1);
3642 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3643 build_int_2 (floor_log2 (d), 0),
3645 t2 = expand_binop (compute_mode, and_optab, op0,
3647 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3648 t3 = gen_reg_rtx (compute_mode);
3649 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3650 compute_mode, 1, 1);
3654 lab = gen_label_rtx ();
3655 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
3656 expand_inc (t1, const1_rtx);
3661 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3667 /* Try using an instruction that produces both the quotient and
3668 remainder, using truncation. We can easily compensate the
3669 quotient or remainder to get ceiling rounding, once we have the
3670 remainder. Notice that we compute also the final remainder
3671 value here, and return the result right away. */
3672 if (target == 0 || GET_MODE (target) != compute_mode)
3673 target = gen_reg_rtx (compute_mode);
3676 remainder= (GET_CODE (target) == REG
3677 ? target : gen_reg_rtx (compute_mode));
3678 quotient = gen_reg_rtx (compute_mode);
3682 quotient = (GET_CODE (target) == REG
3683 ? target : gen_reg_rtx (compute_mode));
3684 remainder = gen_reg_rtx (compute_mode);
3687 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient,
3690 /* This could be computed with a branch-less sequence.
3691 Save that for later. */
3693 rtx label = gen_label_rtx ();
3694 do_cmp_and_jump (remainder, const0_rtx, EQ,
3695 compute_mode, label);
3696 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3697 NULL_RTX, 0, OPTAB_WIDEN);
3698 do_cmp_and_jump (tem, const0_rtx, LT, compute_mode, label);
3699 expand_inc (quotient, const1_rtx);
3700 expand_dec (remainder, op1);
3702 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3705 /* No luck with division elimination or divmod. Have to do it
3706 by conditionally adjusting op0 *and* the result. */
3708 rtx label1, label2, label3, label4, label5;
3712 quotient = gen_reg_rtx (compute_mode);
3713 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3714 label1 = gen_label_rtx ();
3715 label2 = gen_label_rtx ();
3716 label3 = gen_label_rtx ();
3717 label4 = gen_label_rtx ();
3718 label5 = gen_label_rtx ();
3719 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
3720 do_cmp_and_jump (adjusted_op0, const0_rtx, GT,
3721 compute_mode, label1);
3722 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3723 quotient, 0, OPTAB_LIB_WIDEN);
3724 if (tem != quotient)
3725 emit_move_insn (quotient, tem);
3726 emit_jump_insn (gen_jump (label5));
3728 emit_label (label1);
3729 expand_dec (adjusted_op0, const1_rtx);
3730 emit_jump_insn (gen_jump (label4));
3732 emit_label (label2);
3733 do_cmp_and_jump (adjusted_op0, const0_rtx, LT,
3734 compute_mode, label3);
3735 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3736 quotient, 0, OPTAB_LIB_WIDEN);
3737 if (tem != quotient)
3738 emit_move_insn (quotient, tem);
3739 emit_jump_insn (gen_jump (label5));
3741 emit_label (label3);
3742 expand_inc (adjusted_op0, const1_rtx);
3743 emit_label (label4);
3744 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3745 quotient, 0, OPTAB_LIB_WIDEN);
3746 if (tem != quotient)
3747 emit_move_insn (quotient, tem);
3748 expand_inc (quotient, const1_rtx);
3749 emit_label (label5);
3754 case EXACT_DIV_EXPR:
3755 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3757 HOST_WIDE_INT d = INTVAL (op1);
3758 unsigned HOST_WIDE_INT ml;
3762 post_shift = floor_log2 (d & -d);
3763 ml = invert_mod2n (d >> post_shift, size);
3764 t1 = expand_mult (compute_mode, op0, GEN_INT (ml), NULL_RTX,
3766 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3767 build_int_2 (post_shift, 0),
3768 NULL_RTX, unsignedp);
3770 insn = get_last_insn ();
3771 set_unique_reg_note (insn,
3773 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
3779 case ROUND_DIV_EXPR:
3780 case ROUND_MOD_EXPR:
3785 label = gen_label_rtx ();
3786 quotient = gen_reg_rtx (compute_mode);
3787 remainder = gen_reg_rtx (compute_mode);
3788 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0)
3791 quotient = expand_binop (compute_mode, udiv_optab, op0, op1,
3792 quotient, 1, OPTAB_LIB_WIDEN);
3793 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1);
3794 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
3795 remainder, 1, OPTAB_LIB_WIDEN);
3797 tem = plus_constant (op1, -1);
3798 tem = expand_shift (RSHIFT_EXPR, compute_mode, tem,
3799 build_int_2 (1, 0), NULL_RTX, 1);
3800 do_cmp_and_jump (remainder, tem, LEU, compute_mode, label);
3801 expand_inc (quotient, const1_rtx);
3802 expand_dec (remainder, op1);
3807 rtx abs_rem, abs_op1, tem, mask;
3809 label = gen_label_rtx ();
3810 quotient = gen_reg_rtx (compute_mode);
3811 remainder = gen_reg_rtx (compute_mode);
3812 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0)
3815 quotient = expand_binop (compute_mode, sdiv_optab, op0, op1,
3816 quotient, 0, OPTAB_LIB_WIDEN);
3817 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0);
3818 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
3819 remainder, 0, OPTAB_LIB_WIDEN);
3821 abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 0);
3822 abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 0);
3823 tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem,
3824 build_int_2 (1, 0), NULL_RTX, 1);
3825 do_cmp_and_jump (tem, abs_op1, LTU, compute_mode, label);
3826 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3827 NULL_RTX, 0, OPTAB_WIDEN);
3828 mask = expand_shift (RSHIFT_EXPR, compute_mode, tem,
3829 build_int_2 (size - 1, 0), NULL_RTX, 0);
3830 tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx,
3831 NULL_RTX, 0, OPTAB_WIDEN);
3832 tem = expand_binop (compute_mode, sub_optab, tem, mask,
3833 NULL_RTX, 0, OPTAB_WIDEN);
3834 expand_inc (quotient, tem);
3835 tem = expand_binop (compute_mode, xor_optab, mask, op1,
3836 NULL_RTX, 0, OPTAB_WIDEN);
3837 tem = expand_binop (compute_mode, sub_optab, tem, mask,
3838 NULL_RTX, 0, OPTAB_WIDEN);
3839 expand_dec (remainder, tem);
3842 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3850 if (target && GET_MODE (target) != compute_mode)
3855 /* Try to produce the remainder without producing the quotient.
3856 If we seem to have a divmod patten that does not require widening,
3857 don't try windening here. We should really have an WIDEN argument
3858 to expand_twoval_binop, since what we'd really like to do here is
3859 1) try a mod insn in compute_mode
3860 2) try a divmod insn in compute_mode
3861 3) try a div insn in compute_mode and multiply-subtract to get
3863 4) try the same things with widening allowed. */
3865 = sign_expand_binop (compute_mode, umod_optab, smod_optab,
3868 ((optab2->handlers[(int) compute_mode].insn_code
3869 != CODE_FOR_nothing)
3870 ? OPTAB_DIRECT : OPTAB_WIDEN));
3873 /* No luck there. Can we do remainder and divide at once
3874 without a library call? */
3875 remainder = gen_reg_rtx (compute_mode);
3876 if (! expand_twoval_binop ((unsignedp
3880 NULL_RTX, remainder, unsignedp))
3885 return gen_lowpart (mode, remainder);
3888 /* Produce the quotient. Try a quotient insn, but not a library call.
3889 If we have a divmod in this mode, use it in preference to widening
3890 the div (for this test we assume it will not fail). Note that optab2
3891 is set to the one of the two optabs that the call below will use. */
3893 = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
3894 op0, op1, rem_flag ? NULL_RTX : target,
3896 ((optab2->handlers[(int) compute_mode].insn_code
3897 != CODE_FOR_nothing)
3898 ? OPTAB_DIRECT : OPTAB_WIDEN));
3902 /* No luck there. Try a quotient-and-remainder insn,
3903 keeping the quotient alone. */
3904 quotient = gen_reg_rtx (compute_mode);
3905 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
3907 quotient, NULL_RTX, unsignedp))
3911 /* Still no luck. If we are not computing the remainder,
3912 use a library call for the quotient. */
3913 quotient = sign_expand_binop (compute_mode,
3914 udiv_optab, sdiv_optab,
3916 unsignedp, OPTAB_LIB_WIDEN);
3923 if (target && GET_MODE (target) != compute_mode)
3927 /* No divide instruction either. Use library for remainder. */
3928 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
3930 unsignedp, OPTAB_LIB_WIDEN);
3933 /* We divided. Now finish doing X - Y * (X / Y). */
3934 remainder = expand_mult (compute_mode, quotient, op1,
3935 NULL_RTX, unsignedp);
3936 remainder = expand_binop (compute_mode, sub_optab, op0,
3937 remainder, target, unsignedp,
3942 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3945 /* Return a tree node with data type TYPE, describing the value of X.
3946 Usually this is an RTL_EXPR, if there is no obvious better choice.
3947 X may be an expression, however we only support those expressions
3948 generated by loop.c. */
3957 switch (GET_CODE (x))
3960 t = build_int_2 (INTVAL (x),
3961 (TREE_UNSIGNED (type)
3962 && (GET_MODE_BITSIZE (TYPE_MODE (type)) < HOST_BITS_PER_WIDE_INT))
3963 || INTVAL (x) >= 0 ? 0 : -1);
3964 TREE_TYPE (t) = type;
3968 if (GET_MODE (x) == VOIDmode)
3970 t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
3971 TREE_TYPE (t) = type;
3977 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
3978 t = build_real (type, d);
3984 return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
3985 make_tree (type, XEXP (x, 1))));
3988 return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
3989 make_tree (type, XEXP (x, 1))));
3992 return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0))));
3995 return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
3996 make_tree (type, XEXP (x, 1))));
3999 return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
4000 make_tree (type, XEXP (x, 1))));
4003 return fold (convert (type,
4004 build (RSHIFT_EXPR, unsigned_type (type),
4005 make_tree (unsigned_type (type),
4007 make_tree (type, XEXP (x, 1)))));
4010 return fold (convert (type,
4011 build (RSHIFT_EXPR, signed_type (type),
4012 make_tree (signed_type (type), XEXP (x, 0)),
4013 make_tree (type, XEXP (x, 1)))));
4016 if (TREE_CODE (type) != REAL_TYPE)
4017 t = signed_type (type);
4021 return fold (convert (type,
4022 build (TRUNC_DIV_EXPR, t,
4023 make_tree (t, XEXP (x, 0)),
4024 make_tree (t, XEXP (x, 1)))));
4026 t = unsigned_type (type);
4027 return fold (convert (type,
4028 build (TRUNC_DIV_EXPR, t,
4029 make_tree (t, XEXP (x, 0)),
4030 make_tree (t, XEXP (x, 1)))));
4032 t = make_node (RTL_EXPR);
4033 TREE_TYPE (t) = type;
4034 RTL_EXPR_RTL (t) = x;
4035 /* There are no insns to be output
4036 when this rtl_expr is used. */
4037 RTL_EXPR_SEQUENCE (t) = 0;
4042 /* Return an rtx representing the value of X * MULT + ADD.
4043 TARGET is a suggestion for where to store the result (an rtx).
4044 MODE is the machine mode for the computation.
4045 X and MULT must have mode MODE. ADD may have a different mode.
4046 So can X (defaults to same as MODE).
4047 UNSIGNEDP is non-zero to do unsigned multiplication.
4048 This may emit insns. */
4051 expand_mult_add (x, target, mult, add, mode, unsignedp)
4052 rtx x, target, mult, add;
4053 enum machine_mode mode;
4056 tree type = type_for_mode (mode, unsignedp);
4057 tree add_type = (GET_MODE (add) == VOIDmode
4058 ? type : type_for_mode (GET_MODE (add), unsignedp));
4059 tree result = fold (build (PLUS_EXPR, type,
4060 fold (build (MULT_EXPR, type,
4061 make_tree (type, x),
4062 make_tree (type, mult))),
4063 make_tree (add_type, add)));
4065 return expand_expr (result, target, VOIDmode, 0);
4068 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4069 and returning TARGET.
4071 If TARGET is 0, a pseudo-register or constant is returned. */
4074 expand_and (op0, op1, target)
4075 rtx op0, op1, target;
4077 enum machine_mode mode = VOIDmode;
4080 if (GET_MODE (op0) != VOIDmode)
4081 mode = GET_MODE (op0);
4082 else if (GET_MODE (op1) != VOIDmode)
4083 mode = GET_MODE (op1);
4085 if (mode != VOIDmode)
4086 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
4087 else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT)
4088 tem = GEN_INT (INTVAL (op0) & INTVAL (op1));
4094 else if (tem != target)
4095 emit_move_insn (target, tem);
4099 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
4100 and storing in TARGET. Normally return TARGET.
4101 Return 0 if that cannot be done.
4103 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
4104 it is VOIDmode, they cannot both be CONST_INT.
4106 UNSIGNEDP is for the case where we have to widen the operands
4107 to perform the operation. It says to use zero-extension.
4109 NORMALIZEP is 1 if we should convert the result to be either zero
4110 or one. Normalize is -1 if we should convert the result to be
4111 either zero or -1. If NORMALIZEP is zero, the result will be left
4112 "raw" out of the scc insn. */
4115 emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep)
4119 enum machine_mode mode;
4124 enum insn_code icode;
4125 enum machine_mode compare_mode;
4126 enum machine_mode target_mode = GET_MODE (target);
4128 rtx last = get_last_insn ();
4129 rtx pattern, comparison;
4132 code = unsigned_condition (code);
4134 /* If one operand is constant, make it the second one. Only do this
4135 if the other operand is not constant as well. */
4137 if ((CONSTANT_P (op0) && ! CONSTANT_P (op1))
4138 || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT))
4143 code = swap_condition (code);
4146 if (mode == VOIDmode)
4147 mode = GET_MODE (op0);
4149 /* For some comparisons with 1 and -1, we can convert this to
4150 comparisons with zero. This will often produce more opportunities for
4151 store-flag insns. */
4156 if (op1 == const1_rtx)
4157 op1 = const0_rtx, code = LE;
4160 if (op1 == constm1_rtx)
4161 op1 = const0_rtx, code = LT;
4164 if (op1 == const1_rtx)
4165 op1 = const0_rtx, code = GT;
4168 if (op1 == constm1_rtx)
4169 op1 = const0_rtx, code = GE;
4172 if (op1 == const1_rtx)
4173 op1 = const0_rtx, code = NE;
4176 if (op1 == const1_rtx)
4177 op1 = const0_rtx, code = EQ;
4183 /* If we are comparing a double-word integer with zero, we can convert
4184 the comparison into one involving a single word. */
4185 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD * 2
4186 && GET_MODE_CLASS (mode) == MODE_INT
4187 && op1 == const0_rtx)
4189 if (code == EQ || code == NE)
4191 /* Do a logical OR of the two words and compare the result. */
4192 rtx op0h = gen_highpart (word_mode, op0);
4193 rtx op0l = gen_lowpart (word_mode, op0);
4194 rtx op0both = expand_binop (word_mode, ior_optab, op0h, op0l,
4195 NULL_RTX, unsignedp, OPTAB_DIRECT);
4197 return emit_store_flag (target, code, op0both, op1, word_mode,
4198 unsignedp, normalizep);
4200 else if (code == LT || code == GE)
4201 /* If testing the sign bit, can just test on high word. */
4202 return emit_store_flag (target, code, gen_highpart (word_mode, op0),
4203 op1, word_mode, unsignedp, normalizep);
4206 /* From now on, we won't change CODE, so set ICODE now. */
4207 icode = setcc_gen_code[(int) code];
4209 /* If this is A < 0 or A >= 0, we can do this by taking the ones
4210 complement of A (for GE) and shifting the sign bit to the low bit. */
4211 if (op1 == const0_rtx && (code == LT || code == GE)
4212 && GET_MODE_CLASS (mode) == MODE_INT
4213 && (normalizep || STORE_FLAG_VALUE == 1
4214 || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4215 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4216 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))))
4220 /* If the result is to be wider than OP0, it is best to convert it
4221 first. If it is to be narrower, it is *incorrect* to convert it
4223 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
4225 op0 = protect_from_queue (op0, 0);
4226 op0 = convert_modes (target_mode, mode, op0, 0);
4230 if (target_mode != mode)
4234 op0 = expand_unop (mode, one_cmpl_optab, op0,
4235 ((STORE_FLAG_VALUE == 1 || normalizep)
4236 ? 0 : subtarget), 0);
4238 if (STORE_FLAG_VALUE == 1 || normalizep)
4239 /* If we are supposed to produce a 0/1 value, we want to do
4240 a logical shift from the sign bit to the low-order bit; for
4241 a -1/0 value, we do an arithmetic shift. */
4242 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
4243 size_int (GET_MODE_BITSIZE (mode) - 1),
4244 subtarget, normalizep != -1);
4246 if (mode != target_mode)
4247 op0 = convert_modes (target_mode, mode, op0, 0);
4252 if (icode != CODE_FOR_nothing)
4254 insn_operand_predicate_fn pred;
4256 /* We think we may be able to do this with a scc insn. Emit the
4257 comparison and then the scc insn.
4259 compare_from_rtx may call emit_queue, which would be deleted below
4260 if the scc insn fails. So call it ourselves before setting LAST.
4261 Likewise for do_pending_stack_adjust. */
4264 do_pending_stack_adjust ();
4265 last = get_last_insn ();
4268 = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0);
4269 if (GET_CODE (comparison) == CONST_INT)
4270 return (comparison == const0_rtx ? const0_rtx
4271 : normalizep == 1 ? const1_rtx
4272 : normalizep == -1 ? constm1_rtx
4275 /* If the code of COMPARISON doesn't match CODE, something is
4276 wrong; we can no longer be sure that we have the operation.
4277 We could handle this case, but it should not happen. */
4279 if (GET_CODE (comparison) != code)
4282 /* Get a reference to the target in the proper mode for this insn. */
4283 compare_mode = insn_data[(int) icode].operand[0].mode;
4285 pred = insn_data[(int) icode].operand[0].predicate;
4286 if (preserve_subexpressions_p ()
4287 || ! (*pred) (subtarget, compare_mode))
4288 subtarget = gen_reg_rtx (compare_mode);
4290 pattern = GEN_FCN (icode) (subtarget);
4293 emit_insn (pattern);
4295 /* If we are converting to a wider mode, first convert to
4296 TARGET_MODE, then normalize. This produces better combining
4297 opportunities on machines that have a SIGN_EXTRACT when we are
4298 testing a single bit. This mostly benefits the 68k.
4300 If STORE_FLAG_VALUE does not have the sign bit set when
4301 interpreted in COMPARE_MODE, we can do this conversion as
4302 unsigned, which is usually more efficient. */
4303 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
4305 convert_move (target, subtarget,
4306 (GET_MODE_BITSIZE (compare_mode)
4307 <= HOST_BITS_PER_WIDE_INT)
4308 && 0 == (STORE_FLAG_VALUE
4309 & ((HOST_WIDE_INT) 1
4310 << (GET_MODE_BITSIZE (compare_mode) -1))));
4312 compare_mode = target_mode;
4317 /* If we want to keep subexpressions around, don't reuse our
4320 if (preserve_subexpressions_p ())
4323 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
4324 we don't have to do anything. */
4325 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
4327 /* STORE_FLAG_VALUE might be the most negative number, so write
4328 the comparison this way to avoid a compiler-time warning. */
4329 else if (- normalizep == STORE_FLAG_VALUE)
4330 op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
4332 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
4333 makes it hard to use a value of just the sign bit due to
4334 ANSI integer constant typing rules. */
4335 else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT
4336 && (STORE_FLAG_VALUE
4337 & ((HOST_WIDE_INT) 1
4338 << (GET_MODE_BITSIZE (compare_mode) - 1))))
4339 op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
4340 size_int (GET_MODE_BITSIZE (compare_mode) - 1),
4341 subtarget, normalizep == 1);
4342 else if (STORE_FLAG_VALUE & 1)
4344 op0 = expand_and (op0, const1_rtx, subtarget);
4345 if (normalizep == -1)
4346 op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
4351 /* If we were converting to a smaller mode, do the
4353 if (target_mode != compare_mode)
4355 convert_move (target, op0, 0);
4363 delete_insns_since (last);
4365 /* If expensive optimizations, use different pseudo registers for each
4366 insn, instead of reusing the same pseudo. This leads to better CSE,
4367 but slows down the compiler, since there are more pseudos */
4368 subtarget = (!flag_expensive_optimizations
4369 && (target_mode == mode)) ? target : NULL_RTX;
4371 /* If we reached here, we can't do this with a scc insn. However, there
4372 are some comparisons that can be done directly. For example, if
4373 this is an equality comparison of integers, we can try to exclusive-or
4374 (or subtract) the two operands and use a recursive call to try the
4375 comparison with zero. Don't do any of these cases if branches are
4379 && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE)
4380 && op1 != const0_rtx)
4382 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
4386 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
4389 tem = emit_store_flag (target, code, tem, const0_rtx,
4390 mode, unsignedp, normalizep);
4392 delete_insns_since (last);
4396 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
4397 the constant zero. Reject all other comparisons at this point. Only
4398 do LE and GT if branches are expensive since they are expensive on
4399 2-operand machines. */
4401 if (BRANCH_COST == 0
4402 || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx
4403 || (code != EQ && code != NE
4404 && (BRANCH_COST <= 1 || (code != LE && code != GT))))
4407 /* See what we need to return. We can only return a 1, -1, or the
4410 if (normalizep == 0)
4412 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4413 normalizep = STORE_FLAG_VALUE;
4415 else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4416 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4417 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
4423 /* Try to put the result of the comparison in the sign bit. Assume we can't
4424 do the necessary operation below. */
4428 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
4429 the sign bit set. */
4433 /* This is destructive, so SUBTARGET can't be OP0. */
4434 if (rtx_equal_p (subtarget, op0))
4437 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
4440 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
4444 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
4445 number of bits in the mode of OP0, minus one. */
4449 if (rtx_equal_p (subtarget, op0))
4452 tem = expand_shift (RSHIFT_EXPR, mode, op0,
4453 size_int (GET_MODE_BITSIZE (mode) - 1),
4455 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
4459 if (code == EQ || code == NE)
4461 /* For EQ or NE, one way to do the comparison is to apply an operation
4462 that converts the operand into a positive number if it is non-zero
4463 or zero if it was originally zero. Then, for EQ, we subtract 1 and
4464 for NE we negate. This puts the result in the sign bit. Then we
4465 normalize with a shift, if needed.
4467 Two operations that can do the above actions are ABS and FFS, so try
4468 them. If that doesn't work, and MODE is smaller than a full word,
4469 we can use zero-extension to the wider mode (an unsigned conversion)
4470 as the operation. */
4472 if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
4473 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
4474 else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
4475 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
4476 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
4478 op0 = protect_from_queue (op0, 0);
4479 tem = convert_modes (word_mode, mode, op0, 1);
4486 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
4489 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
4492 /* If we couldn't do it that way, for NE we can "or" the two's complement
4493 of the value with itself. For EQ, we take the one's complement of
4494 that "or", which is an extra insn, so we only handle EQ if branches
4497 if (tem == 0 && (code == NE || BRANCH_COST > 1))
4499 if (rtx_equal_p (subtarget, op0))
4502 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
4503 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
4506 if (tem && code == EQ)
4507 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
4511 if (tem && normalizep)
4512 tem = expand_shift (RSHIFT_EXPR, mode, tem,
4513 size_int (GET_MODE_BITSIZE (mode) - 1),
4514 subtarget, normalizep == 1);
4518 if (GET_MODE (tem) != target_mode)
4520 convert_move (target, tem, 0);
4523 else if (!subtarget)
4525 emit_move_insn (target, tem);
4530 delete_insns_since (last);
4535 /* Like emit_store_flag, but always succeeds. */
4538 emit_store_flag_force (target, code, op0, op1, mode, unsignedp, normalizep)
4542 enum machine_mode mode;
4548 /* First see if emit_store_flag can do the job. */
4549 tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep);
4553 if (normalizep == 0)
4556 /* If this failed, we have to do this with set/compare/jump/set code. */
4558 if (GET_CODE (target) != REG
4559 || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1))
4560 target = gen_reg_rtx (GET_MODE (target));
4562 emit_move_insn (target, const1_rtx);
4563 label = gen_label_rtx ();
4564 do_compare_rtx_and_jump (op0, op1, code, unsignedp, mode, NULL_RTX, 0,
4567 emit_move_insn (target, const0_rtx);
4573 /* Perform possibly multi-word comparison and conditional jump to LABEL
4574 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
4576 The algorithm is based on the code in expr.c:do_jump.
4578 Note that this does not perform a general comparison. Only variants
4579 generated within expmed.c are correctly handled, others abort (but could
4580 be handled if needed). */
4583 do_cmp_and_jump (arg1, arg2, op, mode, label)
4584 rtx arg1, arg2, label;
4586 enum machine_mode mode;
4588 /* If this mode is an integer too wide to compare properly,
4589 compare word by word. Rely on cse to optimize constant cases. */
4591 if (GET_MODE_CLASS (mode) == MODE_INT
4592 && ! can_compare_p (op, mode, ccp_jump))
4594 rtx label2 = gen_label_rtx ();
4599 do_jump_by_parts_greater_rtx (mode, 1, arg2, arg1, label2, label);
4603 do_jump_by_parts_greater_rtx (mode, 1, arg1, arg2, label, label2);
4607 do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label2, label);
4611 do_jump_by_parts_greater_rtx (mode, 0, arg1, arg2, label2, label);
4615 do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label, label2);
4618 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
4619 that's the only equality operations we do */
4621 if (arg2 != const0_rtx || mode != GET_MODE(arg1))
4623 do_jump_by_parts_equality_rtx (arg1, label2, label);
4627 if (arg2 != const0_rtx || mode != GET_MODE(arg1))
4629 do_jump_by_parts_equality_rtx (arg1, label, label2);
4636 emit_label (label2);
4640 emit_cmp_and_jump_insns (arg1, arg2, op, NULL_RTX, mode, 0, 0, label);