1 /* Emit RTL for the GCC expander.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 Free Software Foundation, Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
24 /* Middle-to-low level generation of rtx code and insns.
26 This file contains support functions for creating rtl expressions
27 and manipulating them in the doubly-linked chain of insns.
29 The patterns of the insns are created by machine-dependent
30 routines in insn-emit.c, which is generated automatically from
31 the machine description. These routines make the individual rtx's
32 of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch],
33 which are automatically generated from rtl.def; what is machine
34 dependent is the kind of rtx's they make and what arguments they
39 #include "coretypes.h"
41 #include "diagnostic-core.h"
50 #include "hard-reg-set.h"
52 #include "insn-config.h"
55 #include "basic-block.h"
58 #include "langhooks.h"
59 #include "tree-pass.h"
64 /* Commonly used modes. */
66 enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */
67 enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */
68 enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */
69 enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */
71 /* Datastructures maintained for currently processed function in RTL form. */
73 struct rtl_data x_rtl;
75 /* Indexed by pseudo register number, gives the rtx for that pseudo.
76 Allocated in parallel with regno_pointer_align.
77 FIXME: We could put it into emit_status struct, but gengtype is not able to deal
78 with length attribute nested in top level structures. */
82 /* This is *not* reset after each function. It gives each CODE_LABEL
83 in the entire compilation a unique label number. */
85 static GTY(()) int label_num = 1;
87 /* Commonly used rtx's, so that we only need space for one copy.
88 These are initialized once for the entire compilation.
89 All of these are unique; no other rtx-object will be equal to any
92 rtx global_rtl[GR_MAX];
94 /* Commonly used RTL for hard registers. These objects are not necessarily
95 unique, so we allocate them separately from global_rtl. They are
96 initialized once per compilation unit, then copied into regno_reg_rtx
97 at the beginning of each function. */
98 static GTY(()) rtx static_regno_reg_rtx[FIRST_PSEUDO_REGISTER];
100 /* We record floating-point CONST_DOUBLEs in each floating-point mode for
101 the values of 0, 1, and 2. For the integer entries and VOIDmode, we
102 record a copy of const[012]_rtx. */
104 rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE];
108 REAL_VALUE_TYPE dconst0;
109 REAL_VALUE_TYPE dconst1;
110 REAL_VALUE_TYPE dconst2;
111 REAL_VALUE_TYPE dconstm1;
112 REAL_VALUE_TYPE dconsthalf;
114 /* Record fixed-point constant 0 and 1. */
115 FIXED_VALUE_TYPE fconst0[MAX_FCONST0];
116 FIXED_VALUE_TYPE fconst1[MAX_FCONST1];
118 /* All references to the following fixed hard registers go through
119 these unique rtl objects. On machines where the frame-pointer and
120 arg-pointer are the same register, they use the same unique object.
122 After register allocation, other rtl objects which used to be pseudo-regs
123 may be clobbered to refer to the frame-pointer register.
124 But references that were originally to the frame-pointer can be
125 distinguished from the others because they contain frame_pointer_rtx.
127 When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little
128 tricky: until register elimination has taken place hard_frame_pointer_rtx
129 should be used if it is being set, and frame_pointer_rtx otherwise. After
130 register elimination hard_frame_pointer_rtx should always be used.
131 On machines where the two registers are same (most) then these are the
134 In an inline procedure, the stack and frame pointer rtxs may not be
135 used for anything else. */
136 rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */
138 /* This is used to implement __builtin_return_address for some machines.
139 See for instance the MIPS port. */
140 rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */
142 /* We make one copy of (const_int C) where C is in
143 [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT]
144 to save space during the compilation and simplify comparisons of
147 rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1];
149 /* A hash table storing CONST_INTs whose absolute value is greater
150 than MAX_SAVED_CONST_INT. */
152 static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def)))
153 htab_t const_int_htab;
155 /* A hash table storing memory attribute structures. */
156 static GTY ((if_marked ("ggc_marked_p"), param_is (struct mem_attrs)))
157 htab_t mem_attrs_htab;
159 /* A hash table storing register attribute structures. */
160 static GTY ((if_marked ("ggc_marked_p"), param_is (struct reg_attrs)))
161 htab_t reg_attrs_htab;
163 /* A hash table storing all CONST_DOUBLEs. */
164 static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def)))
165 htab_t const_double_htab;
167 /* A hash table storing all CONST_FIXEDs. */
168 static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def)))
169 htab_t const_fixed_htab;
171 #define cur_insn_uid (crtl->emit.x_cur_insn_uid)
172 #define cur_debug_insn_uid (crtl->emit.x_cur_debug_insn_uid)
173 #define last_location (crtl->emit.x_last_location)
174 #define first_label_num (crtl->emit.x_first_label_num)
176 static rtx make_call_insn_raw (rtx);
177 static rtx change_address_1 (rtx, enum machine_mode, rtx, int);
178 static void set_used_decls (tree);
179 static void mark_label_nuses (rtx);
180 static hashval_t const_int_htab_hash (const void *);
181 static int const_int_htab_eq (const void *, const void *);
182 static hashval_t const_double_htab_hash (const void *);
183 static int const_double_htab_eq (const void *, const void *);
184 static rtx lookup_const_double (rtx);
185 static hashval_t const_fixed_htab_hash (const void *);
186 static int const_fixed_htab_eq (const void *, const void *);
187 static rtx lookup_const_fixed (rtx);
188 static hashval_t mem_attrs_htab_hash (const void *);
189 static int mem_attrs_htab_eq (const void *, const void *);
190 static mem_attrs *get_mem_attrs (alias_set_type, tree, rtx, rtx, unsigned int,
191 addr_space_t, enum machine_mode);
192 static hashval_t reg_attrs_htab_hash (const void *);
193 static int reg_attrs_htab_eq (const void *, const void *);
194 static reg_attrs *get_reg_attrs (tree, int);
195 static rtx gen_const_vector (enum machine_mode, int);
196 static void copy_rtx_if_shared_1 (rtx *orig);
198 /* Probability of the conditional branch currently proceeded by try_split.
199 Set to -1 otherwise. */
200 int split_branch_probability = -1;
202 /* Returns a hash code for X (which is a really a CONST_INT). */
205 const_int_htab_hash (const void *x)
207 return (hashval_t) INTVAL ((const_rtx) x);
210 /* Returns nonzero if the value represented by X (which is really a
211 CONST_INT) is the same as that given by Y (which is really a
215 const_int_htab_eq (const void *x, const void *y)
217 return (INTVAL ((const_rtx) x) == *((const HOST_WIDE_INT *) y));
220 /* Returns a hash code for X (which is really a CONST_DOUBLE). */
222 const_double_htab_hash (const void *x)
224 const_rtx const value = (const_rtx) x;
227 if (GET_MODE (value) == VOIDmode)
228 h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value);
231 h = real_hash (CONST_DOUBLE_REAL_VALUE (value));
232 /* MODE is used in the comparison, so it should be in the hash. */
233 h ^= GET_MODE (value);
238 /* Returns nonzero if the value represented by X (really a ...)
239 is the same as that represented by Y (really a ...) */
241 const_double_htab_eq (const void *x, const void *y)
243 const_rtx const a = (const_rtx)x, b = (const_rtx)y;
245 if (GET_MODE (a) != GET_MODE (b))
247 if (GET_MODE (a) == VOIDmode)
248 return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b)
249 && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b));
251 return real_identical (CONST_DOUBLE_REAL_VALUE (a),
252 CONST_DOUBLE_REAL_VALUE (b));
255 /* Returns a hash code for X (which is really a CONST_FIXED). */
258 const_fixed_htab_hash (const void *x)
260 const_rtx const value = (const_rtx) x;
263 h = fixed_hash (CONST_FIXED_VALUE (value));
264 /* MODE is used in the comparison, so it should be in the hash. */
265 h ^= GET_MODE (value);
269 /* Returns nonzero if the value represented by X (really a ...)
270 is the same as that represented by Y (really a ...). */
273 const_fixed_htab_eq (const void *x, const void *y)
275 const_rtx const a = (const_rtx) x, b = (const_rtx) y;
277 if (GET_MODE (a) != GET_MODE (b))
279 return fixed_identical (CONST_FIXED_VALUE (a), CONST_FIXED_VALUE (b));
282 /* Returns a hash code for X (which is a really a mem_attrs *). */
285 mem_attrs_htab_hash (const void *x)
287 const mem_attrs *const p = (const mem_attrs *) x;
289 return (p->alias ^ (p->align * 1000)
290 ^ (p->addrspace * 4000)
291 ^ ((p->offset ? INTVAL (p->offset) : 0) * 50000)
292 ^ ((p->size ? INTVAL (p->size) : 0) * 2500000)
293 ^ (size_t) iterative_hash_expr (p->expr, 0));
296 /* Returns nonzero if the value represented by X (which is really a
297 mem_attrs *) is the same as that given by Y (which is also really a
301 mem_attrs_htab_eq (const void *x, const void *y)
303 const mem_attrs *const p = (const mem_attrs *) x;
304 const mem_attrs *const q = (const mem_attrs *) y;
306 return (p->alias == q->alias && p->offset == q->offset
307 && p->size == q->size && p->align == q->align
308 && p->addrspace == q->addrspace
309 && (p->expr == q->expr
310 || (p->expr != NULL_TREE && q->expr != NULL_TREE
311 && operand_equal_p (p->expr, q->expr, 0))));
314 /* Allocate a new mem_attrs structure and insert it into the hash table if
315 one identical to it is not already in the table. We are doing this for
319 get_mem_attrs (alias_set_type alias, tree expr, rtx offset, rtx size,
320 unsigned int align, addr_space_t addrspace, enum machine_mode mode)
325 /* If everything is the default, we can just return zero.
326 This must match what the corresponding MEM_* macros return when the
327 field is not present. */
328 if (alias == 0 && expr == 0 && offset == 0 && addrspace == 0
330 || (mode != BLKmode && GET_MODE_SIZE (mode) == INTVAL (size)))
331 && (STRICT_ALIGNMENT && mode != BLKmode
332 ? align == GET_MODE_ALIGNMENT (mode) : align == BITS_PER_UNIT))
337 attrs.offset = offset;
340 attrs.addrspace = addrspace;
342 slot = htab_find_slot (mem_attrs_htab, &attrs, INSERT);
345 *slot = ggc_alloc_mem_attrs ();
346 memcpy (*slot, &attrs, sizeof (mem_attrs));
349 return (mem_attrs *) *slot;
352 /* Returns a hash code for X (which is a really a reg_attrs *). */
355 reg_attrs_htab_hash (const void *x)
357 const reg_attrs *const p = (const reg_attrs *) x;
359 return ((p->offset * 1000) ^ (long) p->decl);
362 /* Returns nonzero if the value represented by X (which is really a
363 reg_attrs *) is the same as that given by Y (which is also really a
367 reg_attrs_htab_eq (const void *x, const void *y)
369 const reg_attrs *const p = (const reg_attrs *) x;
370 const reg_attrs *const q = (const reg_attrs *) y;
372 return (p->decl == q->decl && p->offset == q->offset);
374 /* Allocate a new reg_attrs structure and insert it into the hash table if
375 one identical to it is not already in the table. We are doing this for
379 get_reg_attrs (tree decl, int offset)
384 /* If everything is the default, we can just return zero. */
385 if (decl == 0 && offset == 0)
389 attrs.offset = offset;
391 slot = htab_find_slot (reg_attrs_htab, &attrs, INSERT);
394 *slot = ggc_alloc_reg_attrs ();
395 memcpy (*slot, &attrs, sizeof (reg_attrs));
398 return (reg_attrs *) *slot;
403 /* Generate an empty ASM_INPUT, which is used to block attempts to schedule
409 rtx x = gen_rtx_ASM_INPUT (VOIDmode, "");
410 MEM_VOLATILE_P (x) = true;
416 /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and
417 don't attempt to share with the various global pieces of rtl (such as
418 frame_pointer_rtx). */
421 gen_raw_REG (enum machine_mode mode, int regno)
423 rtx x = gen_rtx_raw_REG (mode, regno);
424 ORIGINAL_REGNO (x) = regno;
428 /* There are some RTL codes that require special attention; the generation
429 functions do the raw handling. If you add to this list, modify
430 special_rtx in gengenrtl.c as well. */
433 gen_rtx_CONST_INT (enum machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg)
437 if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT)
438 return const_int_rtx[arg + MAX_SAVED_CONST_INT];
440 #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1
441 if (const_true_rtx && arg == STORE_FLAG_VALUE)
442 return const_true_rtx;
445 /* Look up the CONST_INT in the hash table. */
446 slot = htab_find_slot_with_hash (const_int_htab, &arg,
447 (hashval_t) arg, INSERT);
449 *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg);
455 gen_int_mode (HOST_WIDE_INT c, enum machine_mode mode)
457 return GEN_INT (trunc_int_for_mode (c, mode));
460 /* CONST_DOUBLEs might be created from pairs of integers, or from
461 REAL_VALUE_TYPEs. Also, their length is known only at run time,
462 so we cannot use gen_rtx_raw_CONST_DOUBLE. */
464 /* Determine whether REAL, a CONST_DOUBLE, already exists in the
465 hash table. If so, return its counterpart; otherwise add it
466 to the hash table and return it. */
468 lookup_const_double (rtx real)
470 void **slot = htab_find_slot (const_double_htab, real, INSERT);
477 /* Return a CONST_DOUBLE rtx for a floating-point value specified by
478 VALUE in mode MODE. */
480 const_double_from_real_value (REAL_VALUE_TYPE value, enum machine_mode mode)
482 rtx real = rtx_alloc (CONST_DOUBLE);
483 PUT_MODE (real, mode);
487 return lookup_const_double (real);
490 /* Determine whether FIXED, a CONST_FIXED, already exists in the
491 hash table. If so, return its counterpart; otherwise add it
492 to the hash table and return it. */
495 lookup_const_fixed (rtx fixed)
497 void **slot = htab_find_slot (const_fixed_htab, fixed, INSERT);
504 /* Return a CONST_FIXED rtx for a fixed-point value specified by
505 VALUE in mode MODE. */
508 const_fixed_from_fixed_value (FIXED_VALUE_TYPE value, enum machine_mode mode)
510 rtx fixed = rtx_alloc (CONST_FIXED);
511 PUT_MODE (fixed, mode);
515 return lookup_const_fixed (fixed);
518 /* Constructs double_int from rtx CST. */
521 rtx_to_double_int (const_rtx cst)
525 if (CONST_INT_P (cst))
526 r = shwi_to_double_int (INTVAL (cst));
527 else if (CONST_DOUBLE_P (cst) && GET_MODE (cst) == VOIDmode)
529 r.low = CONST_DOUBLE_LOW (cst);
530 r.high = CONST_DOUBLE_HIGH (cst);
539 /* Return a CONST_DOUBLE or CONST_INT for a value specified as
543 immed_double_int_const (double_int i, enum machine_mode mode)
545 return immed_double_const (i.low, i.high, mode);
548 /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair
549 of ints: I0 is the low-order word and I1 is the high-order word.
550 Do not use this routine for non-integer modes; convert to
551 REAL_VALUE_TYPE and use CONST_DOUBLE_FROM_REAL_VALUE. */
554 immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode)
559 /* There are the following cases (note that there are no modes with
560 HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < 2 * HOST_BITS_PER_WIDE_INT):
562 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use
564 2) GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT, but the value of
565 the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only
566 from copies of the sign bit, and sign of i0 and i1 are the same), then
567 we return a CONST_INT for i0.
568 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */
569 if (mode != VOIDmode)
571 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT
572 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
573 /* We can get a 0 for an error mark. */
574 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
575 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT);
577 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
578 return gen_int_mode (i0, mode);
580 gcc_assert (GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT);
583 /* If this integer fits in one word, return a CONST_INT. */
584 if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0))
587 /* We use VOIDmode for integers. */
588 value = rtx_alloc (CONST_DOUBLE);
589 PUT_MODE (value, VOIDmode);
591 CONST_DOUBLE_LOW (value) = i0;
592 CONST_DOUBLE_HIGH (value) = i1;
594 for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++)
595 XWINT (value, i) = 0;
597 return lookup_const_double (value);
601 gen_rtx_REG (enum machine_mode mode, unsigned int regno)
603 /* In case the MD file explicitly references the frame pointer, have
604 all such references point to the same frame pointer. This is
605 used during frame pointer elimination to distinguish the explicit
606 references to these registers from pseudos that happened to be
609 If we have eliminated the frame pointer or arg pointer, we will
610 be using it as a normal register, for example as a spill
611 register. In such cases, we might be accessing it in a mode that
612 is not Pmode and therefore cannot use the pre-allocated rtx.
614 Also don't do this when we are making new REGs in reload, since
615 we don't want to get confused with the real pointers. */
617 if (mode == Pmode && !reload_in_progress)
619 if (regno == FRAME_POINTER_REGNUM
620 && (!reload_completed || frame_pointer_needed))
621 return frame_pointer_rtx;
622 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
623 if (regno == HARD_FRAME_POINTER_REGNUM
624 && (!reload_completed || frame_pointer_needed))
625 return hard_frame_pointer_rtx;
627 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
628 if (regno == ARG_POINTER_REGNUM)
629 return arg_pointer_rtx;
631 #ifdef RETURN_ADDRESS_POINTER_REGNUM
632 if (regno == RETURN_ADDRESS_POINTER_REGNUM)
633 return return_address_pointer_rtx;
635 if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM
636 && fixed_regs[PIC_OFFSET_TABLE_REGNUM])
637 return pic_offset_table_rtx;
638 if (regno == STACK_POINTER_REGNUM)
639 return stack_pointer_rtx;
643 /* If the per-function register table has been set up, try to re-use
644 an existing entry in that table to avoid useless generation of RTL.
646 This code is disabled for now until we can fix the various backends
647 which depend on having non-shared hard registers in some cases. Long
648 term we want to re-enable this code as it can significantly cut down
649 on the amount of useless RTL that gets generated.
651 We'll also need to fix some code that runs after reload that wants to
652 set ORIGINAL_REGNO. */
657 && regno < FIRST_PSEUDO_REGISTER
658 && reg_raw_mode[regno] == mode)
659 return regno_reg_rtx[regno];
662 return gen_raw_REG (mode, regno);
666 gen_rtx_MEM (enum machine_mode mode, rtx addr)
668 rtx rt = gen_rtx_raw_MEM (mode, addr);
670 /* This field is not cleared by the mere allocation of the rtx, so
677 /* Generate a memory referring to non-trapping constant memory. */
680 gen_const_mem (enum machine_mode mode, rtx addr)
682 rtx mem = gen_rtx_MEM (mode, addr);
683 MEM_READONLY_P (mem) = 1;
684 MEM_NOTRAP_P (mem) = 1;
688 /* Generate a MEM referring to fixed portions of the frame, e.g., register
692 gen_frame_mem (enum machine_mode mode, rtx addr)
694 rtx mem = gen_rtx_MEM (mode, addr);
695 MEM_NOTRAP_P (mem) = 1;
696 set_mem_alias_set (mem, get_frame_alias_set ());
700 /* Generate a MEM referring to a temporary use of the stack, not part
701 of the fixed stack frame. For example, something which is pushed
702 by a target splitter. */
704 gen_tmp_stack_mem (enum machine_mode mode, rtx addr)
706 rtx mem = gen_rtx_MEM (mode, addr);
707 MEM_NOTRAP_P (mem) = 1;
708 if (!cfun->calls_alloca)
709 set_mem_alias_set (mem, get_frame_alias_set ());
713 /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if
714 this construct would be valid, and false otherwise. */
717 validate_subreg (enum machine_mode omode, enum machine_mode imode,
718 const_rtx reg, unsigned int offset)
720 unsigned int isize = GET_MODE_SIZE (imode);
721 unsigned int osize = GET_MODE_SIZE (omode);
723 /* All subregs must be aligned. */
724 if (offset % osize != 0)
727 /* The subreg offset cannot be outside the inner object. */
731 /* ??? This should not be here. Temporarily continue to allow word_mode
732 subregs of anything. The most common offender is (subreg:SI (reg:DF)).
733 Generally, backends are doing something sketchy but it'll take time to
735 if (omode == word_mode)
737 /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field
738 is the culprit here, and not the backends. */
739 else if (osize >= UNITS_PER_WORD && isize >= osize)
741 /* Allow component subregs of complex and vector. Though given the below
742 extraction rules, it's not always clear what that means. */
743 else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode))
744 && GET_MODE_INNER (imode) == omode)
746 /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs,
747 i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to
748 represent this. It's questionable if this ought to be represented at
749 all -- why can't this all be hidden in post-reload splitters that make
750 arbitrarily mode changes to the registers themselves. */
751 else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode)
753 /* Subregs involving floating point modes are not allowed to
754 change size. Therefore (subreg:DI (reg:DF) 0) is fine, but
755 (subreg:SI (reg:DF) 0) isn't. */
756 else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode))
762 /* Paradoxical subregs must have offset zero. */
766 /* This is a normal subreg. Verify that the offset is representable. */
768 /* For hard registers, we already have most of these rules collected in
769 subreg_offset_representable_p. */
770 if (reg && REG_P (reg) && HARD_REGISTER_P (reg))
772 unsigned int regno = REGNO (reg);
774 #ifdef CANNOT_CHANGE_MODE_CLASS
775 if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode))
776 && GET_MODE_INNER (imode) == omode)
778 else if (REG_CANNOT_CHANGE_MODE_P (regno, imode, omode))
782 return subreg_offset_representable_p (regno, imode, offset, omode);
785 /* For pseudo registers, we want most of the same checks. Namely:
786 If the register no larger than a word, the subreg must be lowpart.
787 If the register is larger than a word, the subreg must be the lowpart
788 of a subword. A subreg does *not* perform arbitrary bit extraction.
789 Given that we've already checked mode/offset alignment, we only have
790 to check subword subregs here. */
791 if (osize < UNITS_PER_WORD)
793 enum machine_mode wmode = isize > UNITS_PER_WORD ? word_mode : imode;
794 unsigned int low_off = subreg_lowpart_offset (omode, wmode);
795 if (offset % UNITS_PER_WORD != low_off)
802 gen_rtx_SUBREG (enum machine_mode mode, rtx reg, int offset)
804 gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset));
805 return gen_rtx_raw_SUBREG (mode, reg, offset);
808 /* Generate a SUBREG representing the least-significant part of REG if MODE
809 is smaller than mode of REG, otherwise paradoxical SUBREG. */
812 gen_lowpart_SUBREG (enum machine_mode mode, rtx reg)
814 enum machine_mode inmode;
816 inmode = GET_MODE (reg);
817 if (inmode == VOIDmode)
819 return gen_rtx_SUBREG (mode, reg,
820 subreg_lowpart_offset (mode, inmode));
824 /* Create an rtvec and stores within it the RTXen passed in the arguments. */
827 gen_rtvec (int n, ...)
835 /* Don't allocate an empty rtvec... */
839 rt_val = rtvec_alloc (n);
841 for (i = 0; i < n; i++)
842 rt_val->elem[i] = va_arg (p, rtx);
849 gen_rtvec_v (int n, rtx *argp)
854 /* Don't allocate an empty rtvec... */
858 rt_val = rtvec_alloc (n);
860 for (i = 0; i < n; i++)
861 rt_val->elem[i] = *argp++;
866 /* Return the number of bytes between the start of an OUTER_MODE
867 in-memory value and the start of an INNER_MODE in-memory value,
868 given that the former is a lowpart of the latter. It may be a
869 paradoxical lowpart, in which case the offset will be negative
870 on big-endian targets. */
873 byte_lowpart_offset (enum machine_mode outer_mode,
874 enum machine_mode inner_mode)
876 if (GET_MODE_SIZE (outer_mode) < GET_MODE_SIZE (inner_mode))
877 return subreg_lowpart_offset (outer_mode, inner_mode);
879 return -subreg_lowpart_offset (inner_mode, outer_mode);
882 /* Generate a REG rtx for a new pseudo register of mode MODE.
883 This pseudo is assigned the next sequential register number. */
886 gen_reg_rtx (enum machine_mode mode)
889 unsigned int align = GET_MODE_ALIGNMENT (mode);
891 gcc_assert (can_create_pseudo_p ());
893 /* If a virtual register with bigger mode alignment is generated,
894 increase stack alignment estimation because it might be spilled
896 if (SUPPORTS_STACK_ALIGNMENT
897 && crtl->stack_alignment_estimated < align
898 && !crtl->stack_realign_processed)
900 unsigned int min_align = MINIMUM_ALIGNMENT (NULL, mode, align);
901 if (crtl->stack_alignment_estimated < min_align)
902 crtl->stack_alignment_estimated = min_align;
905 if (generating_concat_p
906 && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
907 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT))
909 /* For complex modes, don't make a single pseudo.
910 Instead, make a CONCAT of two pseudos.
911 This allows noncontiguous allocation of the real and imaginary parts,
912 which makes much better code. Besides, allocating DCmode
913 pseudos overstrains reload on some machines like the 386. */
914 rtx realpart, imagpart;
915 enum machine_mode partmode = GET_MODE_INNER (mode);
917 realpart = gen_reg_rtx (partmode);
918 imagpart = gen_reg_rtx (partmode);
919 return gen_rtx_CONCAT (mode, realpart, imagpart);
922 /* Make sure regno_pointer_align, and regno_reg_rtx are large
923 enough to have an element for this pseudo reg number. */
925 if (reg_rtx_no == crtl->emit.regno_pointer_align_length)
927 int old_size = crtl->emit.regno_pointer_align_length;
931 tmp = XRESIZEVEC (char, crtl->emit.regno_pointer_align, old_size * 2);
932 memset (tmp + old_size, 0, old_size);
933 crtl->emit.regno_pointer_align = (unsigned char *) tmp;
935 new1 = GGC_RESIZEVEC (rtx, regno_reg_rtx, old_size * 2);
936 memset (new1 + old_size, 0, old_size * sizeof (rtx));
937 regno_reg_rtx = new1;
939 crtl->emit.regno_pointer_align_length = old_size * 2;
942 val = gen_raw_REG (mode, reg_rtx_no);
943 regno_reg_rtx[reg_rtx_no++] = val;
947 /* Update NEW with the same attributes as REG, but with OFFSET added
948 to the REG_OFFSET. */
951 update_reg_offset (rtx new_rtx, rtx reg, int offset)
953 REG_ATTRS (new_rtx) = get_reg_attrs (REG_EXPR (reg),
954 REG_OFFSET (reg) + offset);
957 /* Generate a register with same attributes as REG, but with OFFSET
958 added to the REG_OFFSET. */
961 gen_rtx_REG_offset (rtx reg, enum machine_mode mode, unsigned int regno,
964 rtx new_rtx = gen_rtx_REG (mode, regno);
966 update_reg_offset (new_rtx, reg, offset);
970 /* Generate a new pseudo-register with the same attributes as REG, but
971 with OFFSET added to the REG_OFFSET. */
974 gen_reg_rtx_offset (rtx reg, enum machine_mode mode, int offset)
976 rtx new_rtx = gen_reg_rtx (mode);
978 update_reg_offset (new_rtx, reg, offset);
982 /* Adjust REG in-place so that it has mode MODE. It is assumed that the
983 new register is a (possibly paradoxical) lowpart of the old one. */
986 adjust_reg_mode (rtx reg, enum machine_mode mode)
988 update_reg_offset (reg, reg, byte_lowpart_offset (mode, GET_MODE (reg)));
989 PUT_MODE (reg, mode);
992 /* Copy REG's attributes from X, if X has any attributes. If REG and X
993 have different modes, REG is a (possibly paradoxical) lowpart of X. */
996 set_reg_attrs_from_value (rtx reg, rtx x)
1000 /* Hard registers can be reused for multiple purposes within the same
1001 function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN
1002 on them is wrong. */
1003 if (HARD_REGISTER_P (reg))
1006 offset = byte_lowpart_offset (GET_MODE (reg), GET_MODE (x));
1009 if (MEM_OFFSET (x) && CONST_INT_P (MEM_OFFSET (x)))
1011 = get_reg_attrs (MEM_EXPR (x), INTVAL (MEM_OFFSET (x)) + offset);
1012 if (MEM_POINTER (x))
1013 mark_reg_pointer (reg, 0);
1018 update_reg_offset (reg, x, offset);
1019 if (REG_POINTER (x))
1020 mark_reg_pointer (reg, REGNO_POINTER_ALIGN (REGNO (x)));
1024 /* Generate a REG rtx for a new pseudo register, copying the mode
1025 and attributes from X. */
1028 gen_reg_rtx_and_attrs (rtx x)
1030 rtx reg = gen_reg_rtx (GET_MODE (x));
1031 set_reg_attrs_from_value (reg, x);
1035 /* Set the register attributes for registers contained in PARM_RTX.
1036 Use needed values from memory attributes of MEM. */
1039 set_reg_attrs_for_parm (rtx parm_rtx, rtx mem)
1041 if (REG_P (parm_rtx))
1042 set_reg_attrs_from_value (parm_rtx, mem);
1043 else if (GET_CODE (parm_rtx) == PARALLEL)
1045 /* Check for a NULL entry in the first slot, used to indicate that the
1046 parameter goes both on the stack and in registers. */
1047 int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1;
1048 for (; i < XVECLEN (parm_rtx, 0); i++)
1050 rtx x = XVECEXP (parm_rtx, 0, i);
1051 if (REG_P (XEXP (x, 0)))
1052 REG_ATTRS (XEXP (x, 0))
1053 = get_reg_attrs (MEM_EXPR (mem),
1054 INTVAL (XEXP (x, 1)));
1059 /* Set the REG_ATTRS for registers in value X, given that X represents
1063 set_reg_attrs_for_decl_rtl (tree t, rtx x)
1065 if (GET_CODE (x) == SUBREG)
1067 gcc_assert (subreg_lowpart_p (x));
1072 = get_reg_attrs (t, byte_lowpart_offset (GET_MODE (x),
1074 if (GET_CODE (x) == CONCAT)
1076 if (REG_P (XEXP (x, 0)))
1077 REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0);
1078 if (REG_P (XEXP (x, 1)))
1079 REG_ATTRS (XEXP (x, 1))
1080 = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0))));
1082 if (GET_CODE (x) == PARALLEL)
1086 /* Check for a NULL entry, used to indicate that the parameter goes
1087 both on the stack and in registers. */
1088 if (XEXP (XVECEXP (x, 0, 0), 0))
1093 for (i = start; i < XVECLEN (x, 0); i++)
1095 rtx y = XVECEXP (x, 0, i);
1096 if (REG_P (XEXP (y, 0)))
1097 REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1)));
1102 /* Assign the RTX X to declaration T. */
1105 set_decl_rtl (tree t, rtx x)
1107 DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x;
1109 set_reg_attrs_for_decl_rtl (t, x);
1112 /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true
1113 if the ABI requires the parameter to be passed by reference. */
1116 set_decl_incoming_rtl (tree t, rtx x, bool by_reference_p)
1118 DECL_INCOMING_RTL (t) = x;
1119 if (x && !by_reference_p)
1120 set_reg_attrs_for_decl_rtl (t, x);
1123 /* Identify REG (which may be a CONCAT) as a user register. */
1126 mark_user_reg (rtx reg)
1128 if (GET_CODE (reg) == CONCAT)
1130 REG_USERVAR_P (XEXP (reg, 0)) = 1;
1131 REG_USERVAR_P (XEXP (reg, 1)) = 1;
1135 gcc_assert (REG_P (reg));
1136 REG_USERVAR_P (reg) = 1;
1140 /* Identify REG as a probable pointer register and show its alignment
1141 as ALIGN, if nonzero. */
1144 mark_reg_pointer (rtx reg, int align)
1146 if (! REG_POINTER (reg))
1148 REG_POINTER (reg) = 1;
1151 REGNO_POINTER_ALIGN (REGNO (reg)) = align;
1153 else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg)))
1154 /* We can no-longer be sure just how aligned this pointer is. */
1155 REGNO_POINTER_ALIGN (REGNO (reg)) = align;
1158 /* Return 1 plus largest pseudo reg number used in the current function. */
1166 /* Return 1 + the largest label number used so far in the current function. */
1169 max_label_num (void)
1174 /* Return first label number used in this function (if any were used). */
1177 get_first_label_num (void)
1179 return first_label_num;
1182 /* If the rtx for label was created during the expansion of a nested
1183 function, then first_label_num won't include this label number.
1184 Fix this now so that array indices work later. */
1187 maybe_set_first_label_num (rtx x)
1189 if (CODE_LABEL_NUMBER (x) < first_label_num)
1190 first_label_num = CODE_LABEL_NUMBER (x);
1193 /* Return a value representing some low-order bits of X, where the number
1194 of low-order bits is given by MODE. Note that no conversion is done
1195 between floating-point and fixed-point values, rather, the bit
1196 representation is returned.
1198 This function handles the cases in common between gen_lowpart, below,
1199 and two variants in cse.c and combine.c. These are the cases that can
1200 be safely handled at all points in the compilation.
1202 If this is not a case we can handle, return 0. */
1205 gen_lowpart_common (enum machine_mode mode, rtx x)
1207 int msize = GET_MODE_SIZE (mode);
1210 enum machine_mode innermode;
1212 /* Unfortunately, this routine doesn't take a parameter for the mode of X,
1213 so we have to make one up. Yuk. */
1214 innermode = GET_MODE (x);
1216 && msize * BITS_PER_UNIT <= HOST_BITS_PER_WIDE_INT)
1217 innermode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1218 else if (innermode == VOIDmode)
1219 innermode = mode_for_size (HOST_BITS_PER_WIDE_INT * 2, MODE_INT, 0);
1221 xsize = GET_MODE_SIZE (innermode);
1223 gcc_assert (innermode != VOIDmode && innermode != BLKmode);
1225 if (innermode == mode)
1228 /* MODE must occupy no more words than the mode of X. */
1229 if ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD
1230 > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
1233 /* Don't allow generating paradoxical FLOAT_MODE subregs. */
1234 if (SCALAR_FLOAT_MODE_P (mode) && msize > xsize)
1237 offset = subreg_lowpart_offset (mode, innermode);
1239 if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
1240 && (GET_MODE_CLASS (mode) == MODE_INT
1241 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT))
1243 /* If we are getting the low-order part of something that has been
1244 sign- or zero-extended, we can either just use the object being
1245 extended or make a narrower extension. If we want an even smaller
1246 piece than the size of the object being extended, call ourselves
1249 This case is used mostly by combine and cse. */
1251 if (GET_MODE (XEXP (x, 0)) == mode)
1253 else if (msize < GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
1254 return gen_lowpart_common (mode, XEXP (x, 0));
1255 else if (msize < xsize)
1256 return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0));
1258 else if (GET_CODE (x) == SUBREG || REG_P (x)
1259 || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR
1260 || GET_CODE (x) == CONST_DOUBLE || CONST_INT_P (x))
1261 return simplify_gen_subreg (mode, x, innermode, offset);
1263 /* Otherwise, we can't do this. */
1268 gen_highpart (enum machine_mode mode, rtx x)
1270 unsigned int msize = GET_MODE_SIZE (mode);
1273 /* This case loses if X is a subreg. To catch bugs early,
1274 complain if an invalid MODE is used even in other cases. */
1275 gcc_assert (msize <= UNITS_PER_WORD
1276 || msize == (unsigned int) GET_MODE_UNIT_SIZE (GET_MODE (x)));
1278 result = simplify_gen_subreg (mode, x, GET_MODE (x),
1279 subreg_highpart_offset (mode, GET_MODE (x)));
1280 gcc_assert (result);
1282 /* simplify_gen_subreg is not guaranteed to return a valid operand for
1283 the target if we have a MEM. gen_highpart must return a valid operand,
1284 emitting code if necessary to do so. */
1287 result = validize_mem (result);
1288 gcc_assert (result);
1294 /* Like gen_highpart, but accept mode of EXP operand in case EXP can
1295 be VOIDmode constant. */
1297 gen_highpart_mode (enum machine_mode outermode, enum machine_mode innermode, rtx exp)
1299 if (GET_MODE (exp) != VOIDmode)
1301 gcc_assert (GET_MODE (exp) == innermode);
1302 return gen_highpart (outermode, exp);
1304 return simplify_gen_subreg (outermode, exp, innermode,
1305 subreg_highpart_offset (outermode, innermode));
1308 /* Return the SUBREG_BYTE for an OUTERMODE lowpart of an INNERMODE value. */
1311 subreg_lowpart_offset (enum machine_mode outermode, enum machine_mode innermode)
1313 unsigned int offset = 0;
1314 int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode));
1318 if (WORDS_BIG_ENDIAN)
1319 offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
1320 if (BYTES_BIG_ENDIAN)
1321 offset += difference % UNITS_PER_WORD;
1327 /* Return offset in bytes to get OUTERMODE high part
1328 of the value in mode INNERMODE stored in memory in target format. */
1330 subreg_highpart_offset (enum machine_mode outermode, enum machine_mode innermode)
1332 unsigned int offset = 0;
1333 int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode));
1335 gcc_assert (GET_MODE_SIZE (innermode) >= GET_MODE_SIZE (outermode));
1339 if (! WORDS_BIG_ENDIAN)
1340 offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
1341 if (! BYTES_BIG_ENDIAN)
1342 offset += difference % UNITS_PER_WORD;
1348 /* Return 1 iff X, assumed to be a SUBREG,
1349 refers to the least significant part of its containing reg.
1350 If X is not a SUBREG, always return 1 (it is its own low part!). */
1353 subreg_lowpart_p (const_rtx x)
1355 if (GET_CODE (x) != SUBREG)
1357 else if (GET_MODE (SUBREG_REG (x)) == VOIDmode)
1360 return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x)))
1361 == SUBREG_BYTE (x));
1364 /* Return subword OFFSET of operand OP.
1365 The word number, OFFSET, is interpreted as the word number starting
1366 at the low-order address. OFFSET 0 is the low-order word if not
1367 WORDS_BIG_ENDIAN, otherwise it is the high-order word.
1369 If we cannot extract the required word, we return zero. Otherwise,
1370 an rtx corresponding to the requested word will be returned.
1372 VALIDATE_ADDRESS is nonzero if the address should be validated. Before
1373 reload has completed, a valid address will always be returned. After
1374 reload, if a valid address cannot be returned, we return zero.
1376 If VALIDATE_ADDRESS is zero, we simply form the required address; validating
1377 it is the responsibility of the caller.
1379 MODE is the mode of OP in case it is a CONST_INT.
1381 ??? This is still rather broken for some cases. The problem for the
1382 moment is that all callers of this thing provide no 'goal mode' to
1383 tell us to work with. This exists because all callers were written
1384 in a word based SUBREG world.
1385 Now use of this function can be deprecated by simplify_subreg in most
1390 operand_subword (rtx op, unsigned int offset, int validate_address, enum machine_mode mode)
1392 if (mode == VOIDmode)
1393 mode = GET_MODE (op);
1395 gcc_assert (mode != VOIDmode);
1397 /* If OP is narrower than a word, fail. */
1399 && (GET_MODE_SIZE (mode) < UNITS_PER_WORD))
1402 /* If we want a word outside OP, return zero. */
1404 && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode))
1407 /* Form a new MEM at the requested address. */
1410 rtx new_rtx = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD);
1412 if (! validate_address)
1415 else if (reload_completed)
1417 if (! strict_memory_address_addr_space_p (word_mode,
1419 MEM_ADDR_SPACE (op)))
1423 return replace_equiv_address (new_rtx, XEXP (new_rtx, 0));
1426 /* Rest can be handled by simplify_subreg. */
1427 return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD));
1430 /* Similar to `operand_subword', but never return 0. If we can't
1431 extract the required subword, put OP into a register and try again.
1432 The second attempt must succeed. We always validate the address in
1435 MODE is the mode of OP, in case it is CONST_INT. */
1438 operand_subword_force (rtx op, unsigned int offset, enum machine_mode mode)
1440 rtx result = operand_subword (op, offset, 1, mode);
1445 if (mode != BLKmode && mode != VOIDmode)
1447 /* If this is a register which can not be accessed by words, copy it
1448 to a pseudo register. */
1450 op = copy_to_reg (op);
1452 op = force_reg (mode, op);
1455 result = operand_subword (op, offset, 1, mode);
1456 gcc_assert (result);
1461 /* Returns 1 if both MEM_EXPR can be considered equal
1465 mem_expr_equal_p (const_tree expr1, const_tree expr2)
1470 if (! expr1 || ! expr2)
1473 if (TREE_CODE (expr1) != TREE_CODE (expr2))
1476 return operand_equal_p (expr1, expr2, 0);
1479 /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN
1480 bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or
1484 get_mem_align_offset (rtx mem, unsigned int align)
1487 unsigned HOST_WIDE_INT offset;
1489 /* This function can't use
1490 if (!MEM_EXPR (mem) || !MEM_OFFSET (mem)
1491 || !CONST_INT_P (MEM_OFFSET (mem))
1492 || (get_object_alignment (MEM_EXPR (mem), MEM_ALIGN (mem), align)
1496 return (- INTVAL (MEM_OFFSET (mem))) & (align / BITS_PER_UNIT - 1);
1498 - COMPONENT_REFs in MEM_EXPR can have NULL first operand,
1499 for <variable>. get_inner_reference doesn't handle it and
1500 even if it did, the alignment in that case needs to be determined
1501 from DECL_FIELD_CONTEXT's TYPE_ALIGN.
1502 - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR
1503 isn't sufficiently aligned, the object it is in might be. */
1504 gcc_assert (MEM_P (mem));
1505 expr = MEM_EXPR (mem);
1506 if (expr == NULL_TREE
1507 || MEM_OFFSET (mem) == NULL_RTX
1508 || !CONST_INT_P (MEM_OFFSET (mem)))
1511 offset = INTVAL (MEM_OFFSET (mem));
1514 if (DECL_ALIGN (expr) < align)
1517 else if (INDIRECT_REF_P (expr))
1519 if (TYPE_ALIGN (TREE_TYPE (expr)) < (unsigned int) align)
1522 else if (TREE_CODE (expr) == COMPONENT_REF)
1526 tree inner = TREE_OPERAND (expr, 0);
1527 tree field = TREE_OPERAND (expr, 1);
1528 tree byte_offset = component_ref_field_offset (expr);
1529 tree bit_offset = DECL_FIELD_BIT_OFFSET (field);
1532 || !host_integerp (byte_offset, 1)
1533 || !host_integerp (bit_offset, 1))
1536 offset += tree_low_cst (byte_offset, 1);
1537 offset += tree_low_cst (bit_offset, 1) / BITS_PER_UNIT;
1539 if (inner == NULL_TREE)
1541 if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field))
1542 < (unsigned int) align)
1546 else if (DECL_P (inner))
1548 if (DECL_ALIGN (inner) < align)
1552 else if (TREE_CODE (inner) != COMPONENT_REF)
1560 return offset & ((align / BITS_PER_UNIT) - 1);
1563 /* Given REF (a MEM) and T, either the type of X or the expression
1564 corresponding to REF, set the memory attributes. OBJECTP is nonzero
1565 if we are making a new object of this type. BITPOS is nonzero if
1566 there is an offset outstanding on T that will be applied later. */
1569 set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp,
1570 HOST_WIDE_INT bitpos)
1572 alias_set_type alias = MEM_ALIAS_SET (ref);
1573 tree expr = MEM_EXPR (ref);
1574 rtx offset = MEM_OFFSET (ref);
1575 rtx size = MEM_SIZE (ref);
1576 unsigned int align = MEM_ALIGN (ref);
1577 HOST_WIDE_INT apply_bitpos = 0;
1580 /* It can happen that type_for_mode was given a mode for which there
1581 is no language-level type. In which case it returns NULL, which
1586 type = TYPE_P (t) ? t : TREE_TYPE (t);
1587 if (type == error_mark_node)
1590 /* If we have already set DECL_RTL = ref, get_alias_set will get the
1591 wrong answer, as it assumes that DECL_RTL already has the right alias
1592 info. Callers should not set DECL_RTL until after the call to
1593 set_mem_attributes. */
1594 gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t));
1596 /* Get the alias set from the expression or type (perhaps using a
1597 front-end routine) and use it. */
1598 alias = get_alias_set (t);
1600 MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type);
1601 MEM_IN_STRUCT_P (ref)
1602 = AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE;
1603 MEM_POINTER (ref) = POINTER_TYPE_P (type);
1605 /* If we are making an object of this type, or if this is a DECL, we know
1606 that it is a scalar if the type is not an aggregate. */
1607 if ((objectp || DECL_P (t))
1608 && ! AGGREGATE_TYPE_P (type)
1609 && TREE_CODE (type) != COMPLEX_TYPE)
1610 MEM_SCALAR_P (ref) = 1;
1612 /* We can set the alignment from the type if we are making an object,
1613 this is an INDIRECT_REF, or if TYPE_ALIGN_OK. */
1614 if (objectp || TREE_CODE (t) == INDIRECT_REF || TYPE_ALIGN_OK (type))
1615 align = MAX (align, TYPE_ALIGN (type));
1617 else if (TREE_CODE (t) == MEM_REF)
1619 tree op0 = TREE_OPERAND (t, 0);
1620 unsigned HOST_WIDE_INT aoff = BITS_PER_UNIT;
1621 if (host_integerp (TREE_OPERAND (t, 1), 1))
1623 unsigned HOST_WIDE_INT ioff = TREE_INT_CST_LOW (TREE_OPERAND (t, 1));
1624 aoff = (ioff & -ioff) * BITS_PER_UNIT;
1626 if (TREE_CODE (op0) == ADDR_EXPR && DECL_P (TREE_OPERAND (op0, 0)))
1627 align = MAX (align, DECL_ALIGN (TREE_OPERAND (op0, 0)));
1628 else if (TREE_CODE (op0) == ADDR_EXPR
1629 && CONSTANT_CLASS_P (TREE_OPERAND (op0, 0)))
1631 align = TYPE_ALIGN (TREE_TYPE (TREE_OPERAND (op0, 0)));
1632 #ifdef CONSTANT_ALIGNMENT
1633 align = CONSTANT_ALIGNMENT (TREE_OPERAND (op0, 0), align);
1637 /* ??? This isn't fully correct, we can't set the alignment from the
1638 type in all cases. */
1639 align = MAX (align, TYPE_ALIGN (type));
1641 if (!integer_zerop (TREE_OPERAND (t, 1)) && aoff < align)
1645 else if (TREE_CODE (t) == MISALIGNED_INDIRECT_REF)
1647 if (integer_zerop (TREE_OPERAND (t, 1)))
1648 /* We don't know anything about the alignment. */
1649 align = BITS_PER_UNIT;
1651 align = tree_low_cst (TREE_OPERAND (t, 1), 1);
1654 /* If the size is known, we can set that. */
1655 if (TYPE_SIZE_UNIT (type) && host_integerp (TYPE_SIZE_UNIT (type), 1))
1656 size = GEN_INT (tree_low_cst (TYPE_SIZE_UNIT (type), 1));
1658 /* If T is not a type, we may be able to deduce some more information about
1663 bool align_computed = false;
1665 if (TREE_THIS_VOLATILE (t))
1666 MEM_VOLATILE_P (ref) = 1;
1668 /* Now remove any conversions: they don't change what the underlying
1669 object is. Likewise for SAVE_EXPR. */
1670 while (CONVERT_EXPR_P (t)
1671 || TREE_CODE (t) == VIEW_CONVERT_EXPR
1672 || TREE_CODE (t) == SAVE_EXPR)
1673 t = TREE_OPERAND (t, 0);
1675 /* We may look through structure-like accesses for the purposes of
1676 examining TREE_THIS_NOTRAP, but not array-like accesses. */
1678 while (TREE_CODE (base) == COMPONENT_REF
1679 || TREE_CODE (base) == REALPART_EXPR
1680 || TREE_CODE (base) == IMAGPART_EXPR
1681 || TREE_CODE (base) == BIT_FIELD_REF)
1682 base = TREE_OPERAND (base, 0);
1684 if (TREE_CODE (base) == MEM_REF
1685 && TREE_CODE (TREE_OPERAND (base, 0)) == ADDR_EXPR)
1686 base = TREE_OPERAND (TREE_OPERAND (base, 0), 0);
1689 if (CODE_CONTAINS_STRUCT (TREE_CODE (base), TS_DECL_WITH_VIS))
1690 MEM_NOTRAP_P (ref) = !DECL_WEAK (base);
1692 MEM_NOTRAP_P (ref) = 1;
1695 MEM_NOTRAP_P (ref) = TREE_THIS_NOTRAP (base);
1697 base = get_base_address (base);
1698 if (base && DECL_P (base)
1699 && TREE_READONLY (base)
1700 && (TREE_STATIC (base) || DECL_EXTERNAL (base)))
1701 MEM_READONLY_P (ref) = 1;
1703 /* If this expression uses it's parent's alias set, mark it such
1704 that we won't change it. */
1705 if (component_uses_parent_alias_set (t))
1706 MEM_KEEP_ALIAS_SET_P (ref) = 1;
1708 /* If this is a decl, set the attributes of the MEM from it. */
1712 offset = const0_rtx;
1713 apply_bitpos = bitpos;
1714 size = (DECL_SIZE_UNIT (t)
1715 && host_integerp (DECL_SIZE_UNIT (t), 1)
1716 ? GEN_INT (tree_low_cst (DECL_SIZE_UNIT (t), 1)) : 0);
1717 align = DECL_ALIGN (t);
1718 align_computed = true;
1721 /* If this is a constant, we know the alignment. */
1722 else if (CONSTANT_CLASS_P (t))
1724 align = TYPE_ALIGN (type);
1725 #ifdef CONSTANT_ALIGNMENT
1726 align = CONSTANT_ALIGNMENT (t, align);
1728 align_computed = true;
1731 /* If this is a field reference and not a bit-field, record it. */
1732 /* ??? There is some information that can be gleaned from bit-fields,
1733 such as the word offset in the structure that might be modified.
1734 But skip it for now. */
1735 else if (TREE_CODE (t) == COMPONENT_REF
1736 && ! DECL_BIT_FIELD (TREE_OPERAND (t, 1)))
1739 offset = const0_rtx;
1740 apply_bitpos = bitpos;
1741 /* ??? Any reason the field size would be different than
1742 the size we got from the type? */
1745 /* If this is an array reference, look for an outer field reference. */
1746 else if (TREE_CODE (t) == ARRAY_REF)
1748 tree off_tree = size_zero_node;
1749 /* We can't modify t, because we use it at the end of the
1755 tree index = TREE_OPERAND (t2, 1);
1756 tree low_bound = array_ref_low_bound (t2);
1757 tree unit_size = array_ref_element_size (t2);
1759 /* We assume all arrays have sizes that are a multiple of a byte.
1760 First subtract the lower bound, if any, in the type of the
1761 index, then convert to sizetype and multiply by the size of
1762 the array element. */
1763 if (! integer_zerop (low_bound))
1764 index = fold_build2 (MINUS_EXPR, TREE_TYPE (index),
1767 off_tree = size_binop (PLUS_EXPR,
1768 size_binop (MULT_EXPR,
1769 fold_convert (sizetype,
1773 t2 = TREE_OPERAND (t2, 0);
1775 while (TREE_CODE (t2) == ARRAY_REF);
1781 if (host_integerp (off_tree, 1))
1783 HOST_WIDE_INT ioff = tree_low_cst (off_tree, 1);
1784 HOST_WIDE_INT aoff = (ioff & -ioff) * BITS_PER_UNIT;
1785 align = DECL_ALIGN (t2);
1786 if (aoff && (unsigned HOST_WIDE_INT) aoff < align)
1788 align_computed = true;
1789 offset = GEN_INT (ioff);
1790 apply_bitpos = bitpos;
1793 else if (TREE_CODE (t2) == COMPONENT_REF)
1797 if (host_integerp (off_tree, 1))
1799 offset = GEN_INT (tree_low_cst (off_tree, 1));
1800 apply_bitpos = bitpos;
1802 /* ??? Any reason the field size would be different than
1803 the size we got from the type? */
1806 /* If this is an indirect reference, record it. */
1807 else if (TREE_CODE (t) == MEM_REF
1808 || TREE_CODE (t) == MISALIGNED_INDIRECT_REF)
1811 offset = const0_rtx;
1812 apply_bitpos = bitpos;
1816 /* If this is an indirect reference, record it. */
1817 else if (TREE_CODE (t) == MEM_REF
1818 || TREE_CODE (t) == MISALIGNED_INDIRECT_REF)
1821 offset = const0_rtx;
1822 apply_bitpos = bitpos;
1825 if (!align_computed && !INDIRECT_REF_P (t))
1827 unsigned int obj_align
1828 = get_object_alignment (t, align, BIGGEST_ALIGNMENT);
1829 align = MAX (align, obj_align);
1833 /* If we modified OFFSET based on T, then subtract the outstanding
1834 bit position offset. Similarly, increase the size of the accessed
1835 object to contain the negative offset. */
1838 offset = plus_constant (offset, -(apply_bitpos / BITS_PER_UNIT));
1840 size = plus_constant (size, apply_bitpos / BITS_PER_UNIT);
1843 /* Now set the attributes we computed above. */
1845 = get_mem_attrs (alias, expr, offset, size, align,
1846 TYPE_ADDR_SPACE (type), GET_MODE (ref));
1848 /* If this is already known to be a scalar or aggregate, we are done. */
1849 if (MEM_IN_STRUCT_P (ref) || MEM_SCALAR_P (ref))
1852 /* If it is a reference into an aggregate, this is part of an aggregate.
1853 Otherwise we don't know. */
1854 else if (TREE_CODE (t) == COMPONENT_REF || TREE_CODE (t) == ARRAY_REF
1855 || TREE_CODE (t) == ARRAY_RANGE_REF
1856 || TREE_CODE (t) == BIT_FIELD_REF)
1857 MEM_IN_STRUCT_P (ref) = 1;
1861 set_mem_attributes (rtx ref, tree t, int objectp)
1863 set_mem_attributes_minus_bitpos (ref, t, objectp, 0);
1866 /* Set the alias set of MEM to SET. */
1869 set_mem_alias_set (rtx mem, alias_set_type set)
1871 #ifdef ENABLE_CHECKING
1872 /* If the new and old alias sets don't conflict, something is wrong. */
1873 gcc_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem)));
1876 MEM_ATTRS (mem) = get_mem_attrs (set, MEM_EXPR (mem), MEM_OFFSET (mem),
1877 MEM_SIZE (mem), MEM_ALIGN (mem),
1878 MEM_ADDR_SPACE (mem), GET_MODE (mem));
1881 /* Set the address space of MEM to ADDRSPACE (target-defined). */
1884 set_mem_addr_space (rtx mem, addr_space_t addrspace)
1886 MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem),
1887 MEM_OFFSET (mem), MEM_SIZE (mem),
1888 MEM_ALIGN (mem), addrspace, GET_MODE (mem));
1891 /* Set the alignment of MEM to ALIGN bits. */
1894 set_mem_align (rtx mem, unsigned int align)
1896 MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem),
1897 MEM_OFFSET (mem), MEM_SIZE (mem), align,
1898 MEM_ADDR_SPACE (mem), GET_MODE (mem));
1901 /* Set the expr for MEM to EXPR. */
1904 set_mem_expr (rtx mem, tree expr)
1907 = get_mem_attrs (MEM_ALIAS_SET (mem), expr, MEM_OFFSET (mem),
1908 MEM_SIZE (mem), MEM_ALIGN (mem),
1909 MEM_ADDR_SPACE (mem), GET_MODE (mem));
1912 /* Set the offset of MEM to OFFSET. */
1915 set_mem_offset (rtx mem, rtx offset)
1917 MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem),
1918 offset, MEM_SIZE (mem), MEM_ALIGN (mem),
1919 MEM_ADDR_SPACE (mem), GET_MODE (mem));
1922 /* Set the size of MEM to SIZE. */
1925 set_mem_size (rtx mem, rtx size)
1927 MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem),
1928 MEM_OFFSET (mem), size, MEM_ALIGN (mem),
1929 MEM_ADDR_SPACE (mem), GET_MODE (mem));
1932 /* Return a memory reference like MEMREF, but with its mode changed to MODE
1933 and its address changed to ADDR. (VOIDmode means don't change the mode.
1934 NULL for ADDR means don't change the address.) VALIDATE is nonzero if the
1935 returned memory location is required to be valid. The memory
1936 attributes are not changed. */
1939 change_address_1 (rtx memref, enum machine_mode mode, rtx addr, int validate)
1944 gcc_assert (MEM_P (memref));
1945 as = MEM_ADDR_SPACE (memref);
1946 if (mode == VOIDmode)
1947 mode = GET_MODE (memref);
1949 addr = XEXP (memref, 0);
1950 if (mode == GET_MODE (memref) && addr == XEXP (memref, 0)
1951 && (!validate || memory_address_addr_space_p (mode, addr, as)))
1956 if (reload_in_progress || reload_completed)
1957 gcc_assert (memory_address_addr_space_p (mode, addr, as));
1959 addr = memory_address_addr_space (mode, addr, as);
1962 if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref))
1965 new_rtx = gen_rtx_MEM (mode, addr);
1966 MEM_COPY_ATTRIBUTES (new_rtx, memref);
1970 /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what
1971 way we are changing MEMREF, so we only preserve the alias set. */
1974 change_address (rtx memref, enum machine_mode mode, rtx addr)
1976 rtx new_rtx = change_address_1 (memref, mode, addr, 1), size;
1977 enum machine_mode mmode = GET_MODE (new_rtx);
1980 size = mmode == BLKmode ? 0 : GEN_INT (GET_MODE_SIZE (mmode));
1981 align = mmode == BLKmode ? BITS_PER_UNIT : GET_MODE_ALIGNMENT (mmode);
1983 /* If there are no changes, just return the original memory reference. */
1984 if (new_rtx == memref)
1986 if (MEM_ATTRS (memref) == 0
1987 || (MEM_EXPR (memref) == NULL
1988 && MEM_OFFSET (memref) == NULL
1989 && MEM_SIZE (memref) == size
1990 && MEM_ALIGN (memref) == align))
1993 new_rtx = gen_rtx_MEM (mmode, XEXP (memref, 0));
1994 MEM_COPY_ATTRIBUTES (new_rtx, memref);
1998 = get_mem_attrs (MEM_ALIAS_SET (memref), 0, 0, size, align,
1999 MEM_ADDR_SPACE (memref), mmode);
2004 /* Return a memory reference like MEMREF, but with its mode changed
2005 to MODE and its address offset by OFFSET bytes. If VALIDATE is
2006 nonzero, the memory address is forced to be valid.
2007 If ADJUST is zero, OFFSET is only used to update MEM_ATTRS
2008 and caller is responsible for adjusting MEMREF base register. */
2011 adjust_address_1 (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset,
2012 int validate, int adjust)
2014 rtx addr = XEXP (memref, 0);
2016 rtx memoffset = MEM_OFFSET (memref);
2018 unsigned int memalign = MEM_ALIGN (memref);
2019 addr_space_t as = MEM_ADDR_SPACE (memref);
2020 enum machine_mode address_mode = targetm.addr_space.address_mode (as);
2023 /* If there are no changes, just return the original memory reference. */
2024 if (mode == GET_MODE (memref) && !offset
2025 && (!validate || memory_address_addr_space_p (mode, addr, as)))
2028 /* ??? Prefer to create garbage instead of creating shared rtl.
2029 This may happen even if offset is nonzero -- consider
2030 (plus (plus reg reg) const_int) -- so do this always. */
2031 addr = copy_rtx (addr);
2033 /* Convert a possibly large offset to a signed value within the
2034 range of the target address space. */
2035 pbits = GET_MODE_BITSIZE (address_mode);
2036 if (HOST_BITS_PER_WIDE_INT > pbits)
2038 int shift = HOST_BITS_PER_WIDE_INT - pbits;
2039 offset = (((HOST_WIDE_INT) ((unsigned HOST_WIDE_INT) offset << shift))
2045 /* If MEMREF is a LO_SUM and the offset is within the alignment of the
2046 object, we can merge it into the LO_SUM. */
2047 if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM
2049 && (unsigned HOST_WIDE_INT) offset
2050 < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT)
2051 addr = gen_rtx_LO_SUM (address_mode, XEXP (addr, 0),
2052 plus_constant (XEXP (addr, 1), offset));
2054 addr = plus_constant (addr, offset);
2057 new_rtx = change_address_1 (memref, mode, addr, validate);
2059 /* If the address is a REG, change_address_1 rightfully returns memref,
2060 but this would destroy memref's MEM_ATTRS. */
2061 if (new_rtx == memref && offset != 0)
2062 new_rtx = copy_rtx (new_rtx);
2064 /* Compute the new values of the memory attributes due to this adjustment.
2065 We add the offsets and update the alignment. */
2067 memoffset = GEN_INT (offset + INTVAL (memoffset));
2069 /* Compute the new alignment by taking the MIN of the alignment and the
2070 lowest-order set bit in OFFSET, but don't change the alignment if OFFSET
2075 (unsigned HOST_WIDE_INT) (offset & -offset) * BITS_PER_UNIT);
2077 /* We can compute the size in a number of ways. */
2078 if (GET_MODE (new_rtx) != BLKmode)
2079 size = GEN_INT (GET_MODE_SIZE (GET_MODE (new_rtx)));
2080 else if (MEM_SIZE (memref))
2081 size = plus_constant (MEM_SIZE (memref), -offset);
2083 MEM_ATTRS (new_rtx) = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref),
2084 memoffset, size, memalign, as,
2085 GET_MODE (new_rtx));
2087 /* At some point, we should validate that this offset is within the object,
2088 if all the appropriate values are known. */
2092 /* Return a memory reference like MEMREF, but with its mode changed
2093 to MODE and its address changed to ADDR, which is assumed to be
2094 MEMREF offset by OFFSET bytes. If VALIDATE is
2095 nonzero, the memory address is forced to be valid. */
2098 adjust_automodify_address_1 (rtx memref, enum machine_mode mode, rtx addr,
2099 HOST_WIDE_INT offset, int validate)
2101 memref = change_address_1 (memref, VOIDmode, addr, validate);
2102 return adjust_address_1 (memref, mode, offset, validate, 0);
2105 /* Return a memory reference like MEMREF, but whose address is changed by
2106 adding OFFSET, an RTX, to it. POW2 is the highest power of two factor
2107 known to be in OFFSET (possibly 1). */
2110 offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2)
2112 rtx new_rtx, addr = XEXP (memref, 0);
2113 addr_space_t as = MEM_ADDR_SPACE (memref);
2114 enum machine_mode address_mode = targetm.addr_space.address_mode (as);
2116 new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset);
2118 /* At this point we don't know _why_ the address is invalid. It
2119 could have secondary memory references, multiplies or anything.
2121 However, if we did go and rearrange things, we can wind up not
2122 being able to recognize the magic around pic_offset_table_rtx.
2123 This stuff is fragile, and is yet another example of why it is
2124 bad to expose PIC machinery too early. */
2125 if (! memory_address_addr_space_p (GET_MODE (memref), new_rtx, as)
2126 && GET_CODE (addr) == PLUS
2127 && XEXP (addr, 0) == pic_offset_table_rtx)
2129 addr = force_reg (GET_MODE (addr), addr);
2130 new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset);
2133 update_temp_slot_address (XEXP (memref, 0), new_rtx);
2134 new_rtx = change_address_1 (memref, VOIDmode, new_rtx, 1);
2136 /* If there are no changes, just return the original memory reference. */
2137 if (new_rtx == memref)
2140 /* Update the alignment to reflect the offset. Reset the offset, which
2143 = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), 0, 0,
2144 MIN (MEM_ALIGN (memref), pow2 * BITS_PER_UNIT),
2145 as, GET_MODE (new_rtx));
2149 /* Return a memory reference like MEMREF, but with its address changed to
2150 ADDR. The caller is asserting that the actual piece of memory pointed
2151 to is the same, just the form of the address is being changed, such as
2152 by putting something into a register. */
2155 replace_equiv_address (rtx memref, rtx addr)
2157 /* change_address_1 copies the memory attribute structure without change
2158 and that's exactly what we want here. */
2159 update_temp_slot_address (XEXP (memref, 0), addr);
2160 return change_address_1 (memref, VOIDmode, addr, 1);
2163 /* Likewise, but the reference is not required to be valid. */
2166 replace_equiv_address_nv (rtx memref, rtx addr)
2168 return change_address_1 (memref, VOIDmode, addr, 0);
2171 /* Return a memory reference like MEMREF, but with its mode widened to
2172 MODE and offset by OFFSET. This would be used by targets that e.g.
2173 cannot issue QImode memory operations and have to use SImode memory
2174 operations plus masking logic. */
2177 widen_memory_access (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset)
2179 rtx new_rtx = adjust_address_1 (memref, mode, offset, 1, 1);
2180 tree expr = MEM_EXPR (new_rtx);
2181 rtx memoffset = MEM_OFFSET (new_rtx);
2182 unsigned int size = GET_MODE_SIZE (mode);
2184 /* If there are no changes, just return the original memory reference. */
2185 if (new_rtx == memref)
2188 /* If we don't know what offset we were at within the expression, then
2189 we can't know if we've overstepped the bounds. */
2195 if (TREE_CODE (expr) == COMPONENT_REF)
2197 tree field = TREE_OPERAND (expr, 1);
2198 tree offset = component_ref_field_offset (expr);
2200 if (! DECL_SIZE_UNIT (field))
2206 /* Is the field at least as large as the access? If so, ok,
2207 otherwise strip back to the containing structure. */
2208 if (TREE_CODE (DECL_SIZE_UNIT (field)) == INTEGER_CST
2209 && compare_tree_int (DECL_SIZE_UNIT (field), size) >= 0
2210 && INTVAL (memoffset) >= 0)
2213 if (! host_integerp (offset, 1))
2219 expr = TREE_OPERAND (expr, 0);
2221 = (GEN_INT (INTVAL (memoffset)
2222 + tree_low_cst (offset, 1)
2223 + (tree_low_cst (DECL_FIELD_BIT_OFFSET (field), 1)
2226 /* Similarly for the decl. */
2227 else if (DECL_P (expr)
2228 && DECL_SIZE_UNIT (expr)
2229 && TREE_CODE (DECL_SIZE_UNIT (expr)) == INTEGER_CST
2230 && compare_tree_int (DECL_SIZE_UNIT (expr), size) >= 0
2231 && (! memoffset || INTVAL (memoffset) >= 0))
2235 /* The widened memory access overflows the expression, which means
2236 that it could alias another expression. Zap it. */
2243 memoffset = NULL_RTX;
2245 /* The widened memory may alias other stuff, so zap the alias set. */
2246 /* ??? Maybe use get_alias_set on any remaining expression. */
2248 MEM_ATTRS (new_rtx) = get_mem_attrs (0, expr, memoffset, GEN_INT (size),
2249 MEM_ALIGN (new_rtx),
2250 MEM_ADDR_SPACE (new_rtx), mode);
2255 /* A fake decl that is used as the MEM_EXPR of spill slots. */
2256 static GTY(()) tree spill_slot_decl;
2259 get_spill_slot_decl (bool force_build_p)
2261 tree d = spill_slot_decl;
2264 if (d || !force_build_p)
2267 d = build_decl (DECL_SOURCE_LOCATION (current_function_decl),
2268 VAR_DECL, get_identifier ("%sfp"), void_type_node);
2269 DECL_ARTIFICIAL (d) = 1;
2270 DECL_IGNORED_P (d) = 1;
2272 TREE_THIS_NOTRAP (d) = 1;
2273 spill_slot_decl = d;
2275 rd = gen_rtx_MEM (BLKmode, frame_pointer_rtx);
2276 MEM_NOTRAP_P (rd) = 1;
2277 MEM_ATTRS (rd) = get_mem_attrs (new_alias_set (), d, const0_rtx,
2278 NULL_RTX, 0, ADDR_SPACE_GENERIC, BLKmode);
2279 SET_DECL_RTL (d, rd);
2284 /* Given MEM, a result from assign_stack_local, fill in the memory
2285 attributes as appropriate for a register allocator spill slot.
2286 These slots are not aliasable by other memory. We arrange for
2287 them all to use a single MEM_EXPR, so that the aliasing code can
2288 work properly in the case of shared spill slots. */
2291 set_mem_attrs_for_spill (rtx mem)
2293 alias_set_type alias;
2297 expr = get_spill_slot_decl (true);
2298 alias = MEM_ALIAS_SET (DECL_RTL (expr));
2300 /* We expect the incoming memory to be of the form:
2301 (mem:MODE (plus (reg sfp) (const_int offset)))
2302 with perhaps the plus missing for offset = 0. */
2303 addr = XEXP (mem, 0);
2304 offset = const0_rtx;
2305 if (GET_CODE (addr) == PLUS
2306 && CONST_INT_P (XEXP (addr, 1)))
2307 offset = XEXP (addr, 1);
2309 MEM_ATTRS (mem) = get_mem_attrs (alias, expr, offset,
2310 MEM_SIZE (mem), MEM_ALIGN (mem),
2311 ADDR_SPACE_GENERIC, GET_MODE (mem));
2312 MEM_NOTRAP_P (mem) = 1;
2315 /* Return a newly created CODE_LABEL rtx with a unique label number. */
2318 gen_label_rtx (void)
2320 return gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, NULL_RTX,
2321 NULL, label_num++, NULL);
2324 /* For procedure integration. */
2326 /* Install new pointers to the first and last insns in the chain.
2327 Also, set cur_insn_uid to one higher than the last in use.
2328 Used for an inline-procedure after copying the insn chain. */
2331 set_new_first_and_last_insn (rtx first, rtx last)
2335 set_first_insn (first);
2336 set_last_insn (last);
2339 if (MIN_NONDEBUG_INSN_UID || MAY_HAVE_DEBUG_INSNS)
2341 int debug_count = 0;
2343 cur_insn_uid = MIN_NONDEBUG_INSN_UID - 1;
2344 cur_debug_insn_uid = 0;
2346 for (insn = first; insn; insn = NEXT_INSN (insn))
2347 if (INSN_UID (insn) < MIN_NONDEBUG_INSN_UID)
2348 cur_debug_insn_uid = MAX (cur_debug_insn_uid, INSN_UID (insn));
2351 cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn));
2352 if (DEBUG_INSN_P (insn))
2357 cur_debug_insn_uid = MIN_NONDEBUG_INSN_UID + debug_count;
2359 cur_debug_insn_uid++;
2362 for (insn = first; insn; insn = NEXT_INSN (insn))
2363 cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn));
2368 /* Go through all the RTL insn bodies and copy any invalid shared
2369 structure. This routine should only be called once. */
2372 unshare_all_rtl_1 (rtx insn)
2374 /* Unshare just about everything else. */
2375 unshare_all_rtl_in_chain (insn);
2377 /* Make sure the addresses of stack slots found outside the insn chain
2378 (such as, in DECL_RTL of a variable) are not shared
2379 with the insn chain.
2381 This special care is necessary when the stack slot MEM does not
2382 actually appear in the insn chain. If it does appear, its address
2383 is unshared from all else at that point. */
2384 stack_slot_list = copy_rtx_if_shared (stack_slot_list);
2387 /* Go through all the RTL insn bodies and copy any invalid shared
2388 structure, again. This is a fairly expensive thing to do so it
2389 should be done sparingly. */
2392 unshare_all_rtl_again (rtx insn)
2397 for (p = insn; p; p = NEXT_INSN (p))
2400 reset_used_flags (PATTERN (p));
2401 reset_used_flags (REG_NOTES (p));
2404 /* Make sure that virtual stack slots are not shared. */
2405 set_used_decls (DECL_INITIAL (cfun->decl));
2407 /* Make sure that virtual parameters are not shared. */
2408 for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl))
2409 set_used_flags (DECL_RTL (decl));
2411 reset_used_flags (stack_slot_list);
2413 unshare_all_rtl_1 (insn);
2417 unshare_all_rtl (void)
2419 unshare_all_rtl_1 (get_insns ());
2423 struct rtl_opt_pass pass_unshare_all_rtl =
2427 "unshare", /* name */
2429 unshare_all_rtl, /* execute */
2432 0, /* static_pass_number */
2433 TV_NONE, /* tv_id */
2434 0, /* properties_required */
2435 0, /* properties_provided */
2436 0, /* properties_destroyed */
2437 0, /* todo_flags_start */
2438 TODO_dump_func | TODO_verify_rtl_sharing /* todo_flags_finish */
2443 /* Check that ORIG is not marked when it should not be and mark ORIG as in use,
2444 Recursively does the same for subexpressions. */
2447 verify_rtx_sharing (rtx orig, rtx insn)
2452 const char *format_ptr;
2457 code = GET_CODE (x);
2459 /* These types may be freely shared. */
2477 /* SCRATCH must be shared because they represent distinct values. */
2479 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2484 if (shared_const_p (orig))
2489 /* A MEM is allowed to be shared if its address is constant. */
2490 if (CONSTANT_ADDRESS_P (XEXP (x, 0))
2491 || reload_completed || reload_in_progress)
2500 /* This rtx may not be shared. If it has already been seen,
2501 replace it with a copy of itself. */
2502 #ifdef ENABLE_CHECKING
2503 if (RTX_FLAG (x, used))
2505 error ("invalid rtl sharing found in the insn");
2507 error ("shared rtx");
2509 internal_error ("internal consistency failure");
2512 gcc_assert (!RTX_FLAG (x, used));
2514 RTX_FLAG (x, used) = 1;
2516 /* Now scan the subexpressions recursively. */
2518 format_ptr = GET_RTX_FORMAT (code);
2520 for (i = 0; i < GET_RTX_LENGTH (code); i++)
2522 switch (*format_ptr++)
2525 verify_rtx_sharing (XEXP (x, i), insn);
2529 if (XVEC (x, i) != NULL)
2532 int len = XVECLEN (x, i);
2534 for (j = 0; j < len; j++)
2536 /* We allow sharing of ASM_OPERANDS inside single
2538 if (j && GET_CODE (XVECEXP (x, i, j)) == SET
2539 && (GET_CODE (SET_SRC (XVECEXP (x, i, j)))
2541 verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn);
2543 verify_rtx_sharing (XVECEXP (x, i, j), insn);
2552 /* Go through all the RTL insn bodies and check that there is no unexpected
2553 sharing in between the subexpressions. */
2556 verify_rtl_sharing (void)
2560 for (p = get_insns (); p; p = NEXT_INSN (p))
2563 reset_used_flags (PATTERN (p));
2564 reset_used_flags (REG_NOTES (p));
2565 if (GET_CODE (PATTERN (p)) == SEQUENCE)
2568 rtx q, sequence = PATTERN (p);
2570 for (i = 0; i < XVECLEN (sequence, 0); i++)
2572 q = XVECEXP (sequence, 0, i);
2573 gcc_assert (INSN_P (q));
2574 reset_used_flags (PATTERN (q));
2575 reset_used_flags (REG_NOTES (q));
2580 for (p = get_insns (); p; p = NEXT_INSN (p))
2583 verify_rtx_sharing (PATTERN (p), p);
2584 verify_rtx_sharing (REG_NOTES (p), p);
2588 /* Go through all the RTL insn bodies and copy any invalid shared structure.
2589 Assumes the mark bits are cleared at entry. */
2592 unshare_all_rtl_in_chain (rtx insn)
2594 for (; insn; insn = NEXT_INSN (insn))
2597 PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn));
2598 REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn));
2602 /* Go through all virtual stack slots of a function and mark them as
2603 shared. We never replace the DECL_RTLs themselves with a copy,
2604 but expressions mentioned into a DECL_RTL cannot be shared with
2605 expressions in the instruction stream.
2607 Note that reload may convert pseudo registers into memories in-place.
2608 Pseudo registers are always shared, but MEMs never are. Thus if we
2609 reset the used flags on MEMs in the instruction stream, we must set
2610 them again on MEMs that appear in DECL_RTLs. */
2613 set_used_decls (tree blk)
2618 for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t))
2619 if (DECL_RTL_SET_P (t))
2620 set_used_flags (DECL_RTL (t));
2622 /* Now process sub-blocks. */
2623 for (t = BLOCK_SUBBLOCKS (blk); t; t = BLOCK_CHAIN (t))
2627 /* Mark ORIG as in use, and return a copy of it if it was already in use.
2628 Recursively does the same for subexpressions. Uses
2629 copy_rtx_if_shared_1 to reduce stack space. */
2632 copy_rtx_if_shared (rtx orig)
2634 copy_rtx_if_shared_1 (&orig);
2638 /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in
2639 use. Recursively does the same for subexpressions. */
2642 copy_rtx_if_shared_1 (rtx *orig1)
2648 const char *format_ptr;
2652 /* Repeat is used to turn tail-recursion into iteration. */
2659 code = GET_CODE (x);
2661 /* These types may be freely shared. */
2678 /* SCRATCH must be shared because they represent distinct values. */
2681 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2686 if (shared_const_p (x))
2696 /* The chain of insns is not being copied. */
2703 /* This rtx may not be shared. If it has already been seen,
2704 replace it with a copy of itself. */
2706 if (RTX_FLAG (x, used))
2708 x = shallow_copy_rtx (x);
2711 RTX_FLAG (x, used) = 1;
2713 /* Now scan the subexpressions recursively.
2714 We can store any replaced subexpressions directly into X
2715 since we know X is not shared! Any vectors in X
2716 must be copied if X was copied. */
2718 format_ptr = GET_RTX_FORMAT (code);
2719 length = GET_RTX_LENGTH (code);
2722 for (i = 0; i < length; i++)
2724 switch (*format_ptr++)
2728 copy_rtx_if_shared_1 (last_ptr);
2729 last_ptr = &XEXP (x, i);
2733 if (XVEC (x, i) != NULL)
2736 int len = XVECLEN (x, i);
2738 /* Copy the vector iff I copied the rtx and the length
2740 if (copied && len > 0)
2741 XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem);
2743 /* Call recursively on all inside the vector. */
2744 for (j = 0; j < len; j++)
2747 copy_rtx_if_shared_1 (last_ptr);
2748 last_ptr = &XVECEXP (x, i, j);
2763 /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used
2764 to look for shared sub-parts. */
2767 reset_used_flags (rtx x)
2771 const char *format_ptr;
2774 /* Repeat is used to turn tail-recursion into iteration. */
2779 code = GET_CODE (x);
2781 /* These types may be freely shared so we needn't do any resetting
2806 /* The chain of insns is not being copied. */
2813 RTX_FLAG (x, used) = 0;
2815 format_ptr = GET_RTX_FORMAT (code);
2816 length = GET_RTX_LENGTH (code);
2818 for (i = 0; i < length; i++)
2820 switch (*format_ptr++)
2828 reset_used_flags (XEXP (x, i));
2832 for (j = 0; j < XVECLEN (x, i); j++)
2833 reset_used_flags (XVECEXP (x, i, j));
2839 /* Set all the USED bits in X to allow copy_rtx_if_shared to be used
2840 to look for shared sub-parts. */
2843 set_used_flags (rtx x)
2847 const char *format_ptr;
2852 code = GET_CODE (x);
2854 /* These types may be freely shared so we needn't do any resetting
2879 /* The chain of insns is not being copied. */
2886 RTX_FLAG (x, used) = 1;
2888 format_ptr = GET_RTX_FORMAT (code);
2889 for (i = 0; i < GET_RTX_LENGTH (code); i++)
2891 switch (*format_ptr++)
2894 set_used_flags (XEXP (x, i));
2898 for (j = 0; j < XVECLEN (x, i); j++)
2899 set_used_flags (XVECEXP (x, i, j));
2905 /* Copy X if necessary so that it won't be altered by changes in OTHER.
2906 Return X or the rtx for the pseudo reg the value of X was copied into.
2907 OTHER must be valid as a SET_DEST. */
2910 make_safe_from (rtx x, rtx other)
2913 switch (GET_CODE (other))
2916 other = SUBREG_REG (other);
2918 case STRICT_LOW_PART:
2921 other = XEXP (other, 0);
2930 && GET_CODE (x) != SUBREG)
2932 && (REGNO (other) < FIRST_PSEUDO_REGISTER
2933 || reg_mentioned_p (other, x))))
2935 rtx temp = gen_reg_rtx (GET_MODE (x));
2936 emit_move_insn (temp, x);
2942 /* Emission of insns (adding them to the doubly-linked list). */
2944 /* Return the last insn emitted, even if it is in a sequence now pushed. */
2947 get_last_insn_anywhere (void)
2949 struct sequence_stack *stack;
2950 if (get_last_insn ())
2951 return get_last_insn ();
2952 for (stack = seq_stack; stack; stack = stack->next)
2953 if (stack->last != 0)
2958 /* Return the first nonnote insn emitted in current sequence or current
2959 function. This routine looks inside SEQUENCEs. */
2962 get_first_nonnote_insn (void)
2964 rtx insn = get_insns ();
2969 for (insn = next_insn (insn);
2970 insn && NOTE_P (insn);
2971 insn = next_insn (insn))
2975 if (NONJUMP_INSN_P (insn)
2976 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2977 insn = XVECEXP (PATTERN (insn), 0, 0);
2984 /* Return the last nonnote insn emitted in current sequence or current
2985 function. This routine looks inside SEQUENCEs. */
2988 get_last_nonnote_insn (void)
2990 rtx insn = get_last_insn ();
2995 for (insn = previous_insn (insn);
2996 insn && NOTE_P (insn);
2997 insn = previous_insn (insn))
3001 if (NONJUMP_INSN_P (insn)
3002 && GET_CODE (PATTERN (insn)) == SEQUENCE)
3003 insn = XVECEXP (PATTERN (insn), 0,
3004 XVECLEN (PATTERN (insn), 0) - 1);
3011 /* Return the number of actual (non-debug) insns emitted in this
3015 get_max_insn_count (void)
3017 int n = cur_insn_uid;
3019 /* The table size must be stable across -g, to avoid codegen
3020 differences due to debug insns, and not be affected by
3021 -fmin-insn-uid, to avoid excessive table size and to simplify
3022 debugging of -fcompare-debug failures. */
3023 if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID)
3024 n -= cur_debug_insn_uid;
3026 n -= MIN_NONDEBUG_INSN_UID;
3032 /* Return the next insn. If it is a SEQUENCE, return the first insn
3036 next_insn (rtx insn)
3040 insn = NEXT_INSN (insn);
3041 if (insn && NONJUMP_INSN_P (insn)
3042 && GET_CODE (PATTERN (insn)) == SEQUENCE)
3043 insn = XVECEXP (PATTERN (insn), 0, 0);
3049 /* Return the previous insn. If it is a SEQUENCE, return the last insn
3053 previous_insn (rtx insn)
3057 insn = PREV_INSN (insn);
3058 if (insn && NONJUMP_INSN_P (insn)
3059 && GET_CODE (PATTERN (insn)) == SEQUENCE)
3060 insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1);
3066 /* Return the next insn after INSN that is not a NOTE. This routine does not
3067 look inside SEQUENCEs. */
3070 next_nonnote_insn (rtx insn)
3074 insn = NEXT_INSN (insn);
3075 if (insn == 0 || !NOTE_P (insn))
3082 /* Return the next insn after INSN that is not a NOTE, but stop the
3083 search before we enter another basic block. This routine does not
3084 look inside SEQUENCEs. */
3087 next_nonnote_insn_bb (rtx insn)
3091 insn = NEXT_INSN (insn);
3092 if (insn == 0 || !NOTE_P (insn))
3094 if (NOTE_INSN_BASIC_BLOCK_P (insn))
3101 /* Return the previous insn before INSN that is not a NOTE. This routine does
3102 not look inside SEQUENCEs. */
3105 prev_nonnote_insn (rtx insn)
3109 insn = PREV_INSN (insn);
3110 if (insn == 0 || !NOTE_P (insn))
3117 /* Return the previous insn before INSN that is not a NOTE, but stop
3118 the search before we enter another basic block. This routine does
3119 not look inside SEQUENCEs. */
3122 prev_nonnote_insn_bb (rtx insn)
3126 insn = PREV_INSN (insn);
3127 if (insn == 0 || !NOTE_P (insn))
3129 if (NOTE_INSN_BASIC_BLOCK_P (insn))
3136 /* Return the next insn after INSN that is not a DEBUG_INSN. This
3137 routine does not look inside SEQUENCEs. */
3140 next_nondebug_insn (rtx insn)
3144 insn = NEXT_INSN (insn);
3145 if (insn == 0 || !DEBUG_INSN_P (insn))
3152 /* Return the previous insn before INSN that is not a DEBUG_INSN.
3153 This routine does not look inside SEQUENCEs. */
3156 prev_nondebug_insn (rtx insn)
3160 insn = PREV_INSN (insn);
3161 if (insn == 0 || !DEBUG_INSN_P (insn))
3168 /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN;
3169 or 0, if there is none. This routine does not look inside
3173 next_real_insn (rtx insn)
3177 insn = NEXT_INSN (insn);
3178 if (insn == 0 || INSN_P (insn))
3185 /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN;
3186 or 0, if there is none. This routine does not look inside
3190 prev_real_insn (rtx insn)
3194 insn = PREV_INSN (insn);
3195 if (insn == 0 || INSN_P (insn))
3202 /* Return the last CALL_INSN in the current list, or 0 if there is none.
3203 This routine does not look inside SEQUENCEs. */
3206 last_call_insn (void)
3210 for (insn = get_last_insn ();
3211 insn && !CALL_P (insn);
3212 insn = PREV_INSN (insn))
3218 /* Find the next insn after INSN that really does something. This routine
3219 does not look inside SEQUENCEs. After reload this also skips over
3220 standalone USE and CLOBBER insn. */
3223 active_insn_p (const_rtx insn)
3225 return (CALL_P (insn) || JUMP_P (insn)
3226 || (NONJUMP_INSN_P (insn)
3227 && (! reload_completed
3228 || (GET_CODE (PATTERN (insn)) != USE
3229 && GET_CODE (PATTERN (insn)) != CLOBBER))));
3233 next_active_insn (rtx insn)
3237 insn = NEXT_INSN (insn);
3238 if (insn == 0 || active_insn_p (insn))
3245 /* Find the last insn before INSN that really does something. This routine
3246 does not look inside SEQUENCEs. After reload this also skips over
3247 standalone USE and CLOBBER insn. */
3250 prev_active_insn (rtx insn)
3254 insn = PREV_INSN (insn);
3255 if (insn == 0 || active_insn_p (insn))
3262 /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */
3265 next_label (rtx insn)
3269 insn = NEXT_INSN (insn);
3270 if (insn == 0 || LABEL_P (insn))
3277 /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */
3280 prev_label (rtx insn)
3284 insn = PREV_INSN (insn);
3285 if (insn == 0 || LABEL_P (insn))
3292 /* Return the last label to mark the same position as LABEL. Return null
3293 if LABEL itself is null. */
3296 skip_consecutive_labels (rtx label)
3300 for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn))
3308 /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER
3309 and REG_CC_USER notes so we can find it. */
3312 link_cc0_insns (rtx insn)
3314 rtx user = next_nonnote_insn (insn);
3316 if (NONJUMP_INSN_P (user) && GET_CODE (PATTERN (user)) == SEQUENCE)
3317 user = XVECEXP (PATTERN (user), 0, 0);
3319 add_reg_note (user, REG_CC_SETTER, insn);
3320 add_reg_note (insn, REG_CC_USER, user);
3323 /* Return the next insn that uses CC0 after INSN, which is assumed to
3324 set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter
3325 applied to the result of this function should yield INSN).
3327 Normally, this is simply the next insn. However, if a REG_CC_USER note
3328 is present, it contains the insn that uses CC0.
3330 Return 0 if we can't find the insn. */
3333 next_cc0_user (rtx insn)
3335 rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX);
3338 return XEXP (note, 0);
3340 insn = next_nonnote_insn (insn);
3341 if (insn && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
3342 insn = XVECEXP (PATTERN (insn), 0, 0);
3344 if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn)))
3350 /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER
3351 note, it is the previous insn. */
3354 prev_cc0_setter (rtx insn)
3356 rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
3359 return XEXP (note, 0);
3361 insn = prev_nonnote_insn (insn);
3362 gcc_assert (sets_cc0_p (PATTERN (insn)));
3369 /* Find a RTX_AUTOINC class rtx which matches DATA. */
3372 find_auto_inc (rtx *xp, void *data)
3375 rtx reg = (rtx) data;
3377 if (GET_RTX_CLASS (GET_CODE (x)) != RTX_AUTOINC)
3380 switch (GET_CODE (x))
3388 if (rtx_equal_p (reg, XEXP (x, 0)))
3399 /* Increment the label uses for all labels present in rtx. */
3402 mark_label_nuses (rtx x)
3408 code = GET_CODE (x);
3409 if (code == LABEL_REF && LABEL_P (XEXP (x, 0)))
3410 LABEL_NUSES (XEXP (x, 0))++;
3412 fmt = GET_RTX_FORMAT (code);
3413 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3416 mark_label_nuses (XEXP (x, i));
3417 else if (fmt[i] == 'E')
3418 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3419 mark_label_nuses (XVECEXP (x, i, j));
3424 /* Try splitting insns that can be split for better scheduling.
3425 PAT is the pattern which might split.
3426 TRIAL is the insn providing PAT.
3427 LAST is nonzero if we should return the last insn of the sequence produced.
3429 If this routine succeeds in splitting, it returns the first or last
3430 replacement insn depending on the value of LAST. Otherwise, it
3431 returns TRIAL. If the insn to be returned can be split, it will be. */
3434 try_split (rtx pat, rtx trial, int last)
3436 rtx before = PREV_INSN (trial);
3437 rtx after = NEXT_INSN (trial);
3438 int has_barrier = 0;
3441 rtx insn_last, insn;
3444 /* We're not good at redistributing frame information. */
3445 if (RTX_FRAME_RELATED_P (trial))
3448 if (any_condjump_p (trial)
3449 && (note = find_reg_note (trial, REG_BR_PROB, 0)))
3450 split_branch_probability = INTVAL (XEXP (note, 0));
3451 probability = split_branch_probability;
3453 seq = split_insns (pat, trial);
3455 split_branch_probability = -1;
3457 /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER.
3458 We may need to handle this specially. */
3459 if (after && BARRIER_P (after))
3462 after = NEXT_INSN (after);
3468 /* Avoid infinite loop if any insn of the result matches
3469 the original pattern. */
3473 if (INSN_P (insn_last)
3474 && rtx_equal_p (PATTERN (insn_last), pat))
3476 if (!NEXT_INSN (insn_last))
3478 insn_last = NEXT_INSN (insn_last);
3481 /* We will be adding the new sequence to the function. The splitters
3482 may have introduced invalid RTL sharing, so unshare the sequence now. */
3483 unshare_all_rtl_in_chain (seq);
3486 for (insn = insn_last; insn ; insn = PREV_INSN (insn))
3490 mark_jump_label (PATTERN (insn), insn, 0);
3492 if (probability != -1
3493 && any_condjump_p (insn)
3494 && !find_reg_note (insn, REG_BR_PROB, 0))
3496 /* We can preserve the REG_BR_PROB notes only if exactly
3497 one jump is created, otherwise the machine description
3498 is responsible for this step using
3499 split_branch_probability variable. */
3500 gcc_assert (njumps == 1);
3501 add_reg_note (insn, REG_BR_PROB, GEN_INT (probability));
3506 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3507 in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */
3510 for (insn = insn_last; insn ; insn = PREV_INSN (insn))
3513 rtx *p = &CALL_INSN_FUNCTION_USAGE (insn);
3516 *p = CALL_INSN_FUNCTION_USAGE (trial);
3517 SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial);
3519 /* Update the debug information for the CALL_INSN. */
3520 if (flag_enable_icf_debug)
3521 (*debug_hooks->copy_call_info) (trial, insn);
3525 /* Copy notes, particularly those related to the CFG. */
3526 for (note = REG_NOTES (trial); note; note = XEXP (note, 1))
3528 switch (REG_NOTE_KIND (note))
3531 copy_reg_eh_region_note_backward (note, insn_last, NULL);
3536 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3539 add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0));
3543 case REG_NON_LOCAL_GOTO:
3544 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3547 add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0));
3553 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3555 rtx reg = XEXP (note, 0);
3556 if (!FIND_REG_INC_NOTE (insn, reg)
3557 && for_each_rtx (&PATTERN (insn), find_auto_inc, reg) > 0)
3558 add_reg_note (insn, REG_INC, reg);
3568 /* If there are LABELS inside the split insns increment the
3569 usage count so we don't delete the label. */
3573 while (insn != NULL_RTX)
3575 /* JUMP_P insns have already been "marked" above. */
3576 if (NONJUMP_INSN_P (insn))
3577 mark_label_nuses (PATTERN (insn));
3579 insn = PREV_INSN (insn);
3583 tem = emit_insn_after_setloc (seq, trial, INSN_LOCATOR (trial));
3585 delete_insn (trial);
3587 emit_barrier_after (tem);
3589 /* Recursively call try_split for each new insn created; by the
3590 time control returns here that insn will be fully split, so
3591 set LAST and continue from the insn after the one returned.
3592 We can't use next_active_insn here since AFTER may be a note.
3593 Ignore deleted insns, which can be occur if not optimizing. */
3594 for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem))
3595 if (! INSN_DELETED_P (tem) && INSN_P (tem))
3596 tem = try_split (PATTERN (tem), tem, 1);
3598 /* Return either the first or the last insn, depending on which was
3601 ? (after ? PREV_INSN (after) : get_last_insn ())
3602 : NEXT_INSN (before);
3605 /* Make and return an INSN rtx, initializing all its slots.
3606 Store PATTERN in the pattern slots. */
3609 make_insn_raw (rtx pattern)
3613 insn = rtx_alloc (INSN);
3615 INSN_UID (insn) = cur_insn_uid++;
3616 PATTERN (insn) = pattern;
3617 INSN_CODE (insn) = -1;
3618 REG_NOTES (insn) = NULL;
3619 INSN_LOCATOR (insn) = curr_insn_locator ();
3620 BLOCK_FOR_INSN (insn) = NULL;
3622 #ifdef ENABLE_RTL_CHECKING
3625 && (returnjump_p (insn)
3626 || (GET_CODE (insn) == SET
3627 && SET_DEST (insn) == pc_rtx)))
3629 warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n");
3637 /* Like `make_insn_raw' but make a DEBUG_INSN instead of an insn. */
3640 make_debug_insn_raw (rtx pattern)
3644 insn = rtx_alloc (DEBUG_INSN);
3645 INSN_UID (insn) = cur_debug_insn_uid++;
3646 if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID)
3647 INSN_UID (insn) = cur_insn_uid++;
3649 PATTERN (insn) = pattern;
3650 INSN_CODE (insn) = -1;
3651 REG_NOTES (insn) = NULL;
3652 INSN_LOCATOR (insn) = curr_insn_locator ();
3653 BLOCK_FOR_INSN (insn) = NULL;
3658 /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */
3661 make_jump_insn_raw (rtx pattern)
3665 insn = rtx_alloc (JUMP_INSN);
3666 INSN_UID (insn) = cur_insn_uid++;
3668 PATTERN (insn) = pattern;
3669 INSN_CODE (insn) = -1;
3670 REG_NOTES (insn) = NULL;
3671 JUMP_LABEL (insn) = NULL;
3672 INSN_LOCATOR (insn) = curr_insn_locator ();
3673 BLOCK_FOR_INSN (insn) = NULL;
3678 /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */
3681 make_call_insn_raw (rtx pattern)
3685 insn = rtx_alloc (CALL_INSN);
3686 INSN_UID (insn) = cur_insn_uid++;
3688 PATTERN (insn) = pattern;
3689 INSN_CODE (insn) = -1;
3690 REG_NOTES (insn) = NULL;
3691 CALL_INSN_FUNCTION_USAGE (insn) = NULL;
3692 INSN_LOCATOR (insn) = curr_insn_locator ();
3693 BLOCK_FOR_INSN (insn) = NULL;
3698 /* Add INSN to the end of the doubly-linked list.
3699 INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */
3704 PREV_INSN (insn) = get_last_insn();
3705 NEXT_INSN (insn) = 0;
3707 if (NULL != get_last_insn())
3708 NEXT_INSN (get_last_insn ()) = insn;
3710 if (NULL == get_insns ())
3711 set_first_insn (insn);
3713 set_last_insn (insn);
3716 /* Add INSN into the doubly-linked list after insn AFTER. This and
3717 the next should be the only functions called to insert an insn once
3718 delay slots have been filled since only they know how to update a
3722 add_insn_after (rtx insn, rtx after, basic_block bb)
3724 rtx next = NEXT_INSN (after);
3726 gcc_assert (!optimize || !INSN_DELETED_P (after));
3728 NEXT_INSN (insn) = next;
3729 PREV_INSN (insn) = after;
3733 PREV_INSN (next) = insn;
3734 if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
3735 PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn;
3737 else if (get_last_insn () == after)
3738 set_last_insn (insn);
3741 struct sequence_stack *stack = seq_stack;
3742 /* Scan all pending sequences too. */
3743 for (; stack; stack = stack->next)
3744 if (after == stack->last)
3753 if (!BARRIER_P (after)
3754 && !BARRIER_P (insn)
3755 && (bb = BLOCK_FOR_INSN (after)))
3757 set_block_for_insn (insn, bb);
3759 df_insn_rescan (insn);
3760 /* Should not happen as first in the BB is always
3761 either NOTE or LABEL. */
3762 if (BB_END (bb) == after
3763 /* Avoid clobbering of structure when creating new BB. */
3764 && !BARRIER_P (insn)
3765 && !NOTE_INSN_BASIC_BLOCK_P (insn))
3769 NEXT_INSN (after) = insn;
3770 if (NONJUMP_INSN_P (after) && GET_CODE (PATTERN (after)) == SEQUENCE)
3772 rtx sequence = PATTERN (after);
3773 NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn;
3777 /* Add INSN into the doubly-linked list before insn BEFORE. This and
3778 the previous should be the only functions called to insert an insn
3779 once delay slots have been filled since only they know how to
3780 update a SEQUENCE. If BB is NULL, an attempt is made to infer the
3784 add_insn_before (rtx insn, rtx before, basic_block bb)
3786 rtx prev = PREV_INSN (before);
3788 gcc_assert (!optimize || !INSN_DELETED_P (before));
3790 PREV_INSN (insn) = prev;
3791 NEXT_INSN (insn) = before;
3795 NEXT_INSN (prev) = insn;
3796 if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE)
3798 rtx sequence = PATTERN (prev);
3799 NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn;
3802 else if (get_insns () == before)
3803 set_first_insn (insn);
3806 struct sequence_stack *stack = seq_stack;
3807 /* Scan all pending sequences too. */
3808 for (; stack; stack = stack->next)
3809 if (before == stack->first)
3811 stack->first = insn;
3819 && !BARRIER_P (before)
3820 && !BARRIER_P (insn))
3821 bb = BLOCK_FOR_INSN (before);
3825 set_block_for_insn (insn, bb);
3827 df_insn_rescan (insn);
3828 /* Should not happen as first in the BB is always either NOTE or
3830 gcc_assert (BB_HEAD (bb) != insn
3831 /* Avoid clobbering of structure when creating new BB. */
3833 || NOTE_INSN_BASIC_BLOCK_P (insn));
3836 PREV_INSN (before) = insn;
3837 if (NONJUMP_INSN_P (before) && GET_CODE (PATTERN (before)) == SEQUENCE)
3838 PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn;
3842 /* Replace insn with an deleted instruction note. */
3845 set_insn_deleted (rtx insn)
3847 df_insn_delete (BLOCK_FOR_INSN (insn), INSN_UID (insn));
3848 PUT_CODE (insn, NOTE);
3849 NOTE_KIND (insn) = NOTE_INSN_DELETED;
3853 /* Remove an insn from its doubly-linked list. This function knows how
3854 to handle sequences. */
3856 remove_insn (rtx insn)
3858 rtx next = NEXT_INSN (insn);
3859 rtx prev = PREV_INSN (insn);
3862 /* Later in the code, the block will be marked dirty. */
3863 df_insn_delete (NULL, INSN_UID (insn));
3867 NEXT_INSN (prev) = next;
3868 if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE)
3870 rtx sequence = PATTERN (prev);
3871 NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next;
3874 else if (get_insns () == insn)
3877 PREV_INSN (next) = NULL;
3878 set_first_insn (next);
3882 struct sequence_stack *stack = seq_stack;
3883 /* Scan all pending sequences too. */
3884 for (; stack; stack = stack->next)
3885 if (insn == stack->first)
3887 stack->first = next;
3896 PREV_INSN (next) = prev;
3897 if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
3898 PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev;
3900 else if (get_last_insn () == insn)
3901 set_last_insn (prev);
3904 struct sequence_stack *stack = seq_stack;
3905 /* Scan all pending sequences too. */
3906 for (; stack; stack = stack->next)
3907 if (insn == stack->last)
3915 if (!BARRIER_P (insn)
3916 && (bb = BLOCK_FOR_INSN (insn)))
3919 df_set_bb_dirty (bb);
3920 if (BB_HEAD (bb) == insn)
3922 /* Never ever delete the basic block note without deleting whole
3924 gcc_assert (!NOTE_P (insn));
3925 BB_HEAD (bb) = next;
3927 if (BB_END (bb) == insn)
3932 /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */
3935 add_function_usage_to (rtx call_insn, rtx call_fusage)
3937 gcc_assert (call_insn && CALL_P (call_insn));
3939 /* Put the register usage information on the CALL. If there is already
3940 some usage information, put ours at the end. */
3941 if (CALL_INSN_FUNCTION_USAGE (call_insn))
3945 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0;
3946 link = XEXP (link, 1))
3949 XEXP (link, 1) = call_fusage;
3952 CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage;
3955 /* Delete all insns made since FROM.
3956 FROM becomes the new last instruction. */
3959 delete_insns_since (rtx from)
3964 NEXT_INSN (from) = 0;
3965 set_last_insn (from);
3968 /* This function is deprecated, please use sequences instead.
3970 Move a consecutive bunch of insns to a different place in the chain.
3971 The insns to be moved are those between FROM and TO.
3972 They are moved to a new position after the insn AFTER.
3973 AFTER must not be FROM or TO or any insn in between.
3975 This function does not know about SEQUENCEs and hence should not be
3976 called after delay-slot filling has been done. */
3979 reorder_insns_nobb (rtx from, rtx to, rtx after)
3981 /* Splice this bunch out of where it is now. */
3982 if (PREV_INSN (from))
3983 NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to);
3985 PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from);
3986 if (get_last_insn () == to)
3987 set_last_insn (PREV_INSN (from));
3988 if (get_insns () == from)
3989 set_first_insn (NEXT_INSN (to));
3991 /* Make the new neighbors point to it and it to them. */
3992 if (NEXT_INSN (after))
3993 PREV_INSN (NEXT_INSN (after)) = to;
3995 NEXT_INSN (to) = NEXT_INSN (after);
3996 PREV_INSN (from) = after;
3997 NEXT_INSN (after) = from;
3998 if (after == get_last_insn())
4002 /* Same as function above, but take care to update BB boundaries. */
4004 reorder_insns (rtx from, rtx to, rtx after)
4006 rtx prev = PREV_INSN (from);
4007 basic_block bb, bb2;
4009 reorder_insns_nobb (from, to, after);
4011 if (!BARRIER_P (after)
4012 && (bb = BLOCK_FOR_INSN (after)))
4015 df_set_bb_dirty (bb);
4017 if (!BARRIER_P (from)
4018 && (bb2 = BLOCK_FOR_INSN (from)))
4020 if (BB_END (bb2) == to)
4021 BB_END (bb2) = prev;
4022 df_set_bb_dirty (bb2);
4025 if (BB_END (bb) == after)
4028 for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x))
4030 df_insn_change_bb (x, bb);
4035 /* Emit insn(s) of given code and pattern
4036 at a specified place within the doubly-linked list.
4038 All of the emit_foo global entry points accept an object
4039 X which is either an insn list or a PATTERN of a single
4042 There are thus a few canonical ways to generate code and
4043 emit it at a specific place in the instruction stream. For
4044 example, consider the instruction named SPOT and the fact that
4045 we would like to emit some instructions before SPOT. We might
4049 ... emit the new instructions ...
4050 insns_head = get_insns ();
4053 emit_insn_before (insns_head, SPOT);
4055 It used to be common to generate SEQUENCE rtl instead, but that
4056 is a relic of the past which no longer occurs. The reason is that
4057 SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE
4058 generated would almost certainly die right after it was created. */
4060 /* Make X be output before the instruction BEFORE. */
4063 emit_insn_before_noloc (rtx x, rtx before, basic_block bb)
4068 gcc_assert (before);
4073 switch (GET_CODE (x))
4085 rtx next = NEXT_INSN (insn);
4086 add_insn_before (insn, before, bb);
4092 #ifdef ENABLE_RTL_CHECKING
4099 last = make_insn_raw (x);
4100 add_insn_before (last, before, bb);
4107 /* Make an instruction with body X and code JUMP_INSN
4108 and output it before the instruction BEFORE. */
4111 emit_jump_insn_before_noloc (rtx x, rtx before)
4113 rtx insn, last = NULL_RTX;
4115 gcc_assert (before);
4117 switch (GET_CODE (x))
4129 rtx next = NEXT_INSN (insn);
4130 add_insn_before (insn, before, NULL);
4136 #ifdef ENABLE_RTL_CHECKING
4143 last = make_jump_insn_raw (x);
4144 add_insn_before (last, before, NULL);
4151 /* Make an instruction with body X and code CALL_INSN
4152 and output it before the instruction BEFORE. */
4155 emit_call_insn_before_noloc (rtx x, rtx before)
4157 rtx last = NULL_RTX, insn;
4159 gcc_assert (before);
4161 switch (GET_CODE (x))
4173 rtx next = NEXT_INSN (insn);
4174 add_insn_before (insn, before, NULL);
4180 #ifdef ENABLE_RTL_CHECKING
4187 last = make_call_insn_raw (x);
4188 add_insn_before (last, before, NULL);
4195 /* Make an instruction with body X and code DEBUG_INSN
4196 and output it before the instruction BEFORE. */
4199 emit_debug_insn_before_noloc (rtx x, rtx before)
4201 rtx last = NULL_RTX, insn;
4203 gcc_assert (before);
4205 switch (GET_CODE (x))
4217 rtx next = NEXT_INSN (insn);
4218 add_insn_before (insn, before, NULL);
4224 #ifdef ENABLE_RTL_CHECKING
4231 last = make_debug_insn_raw (x);
4232 add_insn_before (last, before, NULL);
4239 /* Make an insn of code BARRIER
4240 and output it before the insn BEFORE. */
4243 emit_barrier_before (rtx before)
4245 rtx insn = rtx_alloc (BARRIER);
4247 INSN_UID (insn) = cur_insn_uid++;
4249 add_insn_before (insn, before, NULL);
4253 /* Emit the label LABEL before the insn BEFORE. */
4256 emit_label_before (rtx label, rtx before)
4258 /* This can be called twice for the same label as a result of the
4259 confusion that follows a syntax error! So make it harmless. */
4260 if (INSN_UID (label) == 0)
4262 INSN_UID (label) = cur_insn_uid++;
4263 add_insn_before (label, before, NULL);
4269 /* Emit a note of subtype SUBTYPE before the insn BEFORE. */
4272 emit_note_before (enum insn_note subtype, rtx before)
4274 rtx note = rtx_alloc (NOTE);
4275 INSN_UID (note) = cur_insn_uid++;
4276 NOTE_KIND (note) = subtype;
4277 BLOCK_FOR_INSN (note) = NULL;
4278 memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note)));
4280 add_insn_before (note, before, NULL);
4284 /* Helper for emit_insn_after, handles lists of instructions
4288 emit_insn_after_1 (rtx first, rtx after, basic_block bb)
4292 if (!bb && !BARRIER_P (after))
4293 bb = BLOCK_FOR_INSN (after);
4297 df_set_bb_dirty (bb);
4298 for (last = first; NEXT_INSN (last); last = NEXT_INSN (last))
4299 if (!BARRIER_P (last))
4301 set_block_for_insn (last, bb);
4302 df_insn_rescan (last);
4304 if (!BARRIER_P (last))
4306 set_block_for_insn (last, bb);
4307 df_insn_rescan (last);
4309 if (BB_END (bb) == after)
4313 for (last = first; NEXT_INSN (last); last = NEXT_INSN (last))
4316 after_after = NEXT_INSN (after);
4318 NEXT_INSN (after) = first;
4319 PREV_INSN (first) = after;
4320 NEXT_INSN (last) = after_after;
4322 PREV_INSN (after_after) = last;
4324 if (after == get_last_insn())
4325 set_last_insn (last);
4330 /* Make X be output after the insn AFTER and set the BB of insn. If
4331 BB is NULL, an attempt is made to infer the BB from AFTER. */
4334 emit_insn_after_noloc (rtx x, rtx after, basic_block bb)
4343 switch (GET_CODE (x))
4352 last = emit_insn_after_1 (x, after, bb);
4355 #ifdef ENABLE_RTL_CHECKING
4362 last = make_insn_raw (x);
4363 add_insn_after (last, after, bb);
4371 /* Make an insn of code JUMP_INSN with body X
4372 and output it after the insn AFTER. */
4375 emit_jump_insn_after_noloc (rtx x, rtx after)
4381 switch (GET_CODE (x))
4390 last = emit_insn_after_1 (x, after, NULL);
4393 #ifdef ENABLE_RTL_CHECKING
4400 last = make_jump_insn_raw (x);
4401 add_insn_after (last, after, NULL);
4408 /* Make an instruction with body X and code CALL_INSN
4409 and output it after the instruction AFTER. */
4412 emit_call_insn_after_noloc (rtx x, rtx after)
4418 switch (GET_CODE (x))
4427 last = emit_insn_after_1 (x, after, NULL);
4430 #ifdef ENABLE_RTL_CHECKING
4437 last = make_call_insn_raw (x);
4438 add_insn_after (last, after, NULL);
4445 /* Make an instruction with body X and code CALL_INSN
4446 and output it after the instruction AFTER. */
4449 emit_debug_insn_after_noloc (rtx x, rtx after)
4455 switch (GET_CODE (x))
4464 last = emit_insn_after_1 (x, after, NULL);
4467 #ifdef ENABLE_RTL_CHECKING
4474 last = make_debug_insn_raw (x);
4475 add_insn_after (last, after, NULL);
4482 /* Make an insn of code BARRIER
4483 and output it after the insn AFTER. */
4486 emit_barrier_after (rtx after)
4488 rtx insn = rtx_alloc (BARRIER);
4490 INSN_UID (insn) = cur_insn_uid++;
4492 add_insn_after (insn, after, NULL);
4496 /* Emit the label LABEL after the insn AFTER. */
4499 emit_label_after (rtx label, rtx after)
4501 /* This can be called twice for the same label
4502 as a result of the confusion that follows a syntax error!
4503 So make it harmless. */
4504 if (INSN_UID (label) == 0)
4506 INSN_UID (label) = cur_insn_uid++;
4507 add_insn_after (label, after, NULL);
4513 /* Emit a note of subtype SUBTYPE after the insn AFTER. */
4516 emit_note_after (enum insn_note subtype, rtx after)
4518 rtx note = rtx_alloc (NOTE);
4519 INSN_UID (note) = cur_insn_uid++;
4520 NOTE_KIND (note) = subtype;
4521 BLOCK_FOR_INSN (note) = NULL;
4522 memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note)));
4523 add_insn_after (note, after, NULL);
4527 /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4529 emit_insn_after_setloc (rtx pattern, rtx after, int loc)
4531 rtx last = emit_insn_after_noloc (pattern, after, NULL);
4533 if (pattern == NULL_RTX || !loc)
4536 after = NEXT_INSN (after);
4539 if (active_insn_p (after) && !INSN_LOCATOR (after))
4540 INSN_LOCATOR (after) = loc;
4543 after = NEXT_INSN (after);
4548 /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4550 emit_insn_after (rtx pattern, rtx after)
4554 while (DEBUG_INSN_P (prev))
4555 prev = PREV_INSN (prev);
4558 return emit_insn_after_setloc (pattern, after, INSN_LOCATOR (prev));
4560 return emit_insn_after_noloc (pattern, after, NULL);
4563 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4565 emit_jump_insn_after_setloc (rtx pattern, rtx after, int loc)
4567 rtx last = emit_jump_insn_after_noloc (pattern, after);
4569 if (pattern == NULL_RTX || !loc)
4572 after = NEXT_INSN (after);
4575 if (active_insn_p (after) && !INSN_LOCATOR (after))
4576 INSN_LOCATOR (after) = loc;
4579 after = NEXT_INSN (after);
4584 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4586 emit_jump_insn_after (rtx pattern, rtx after)
4590 while (DEBUG_INSN_P (prev))
4591 prev = PREV_INSN (prev);
4594 return emit_jump_insn_after_setloc (pattern, after, INSN_LOCATOR (prev));
4596 return emit_jump_insn_after_noloc (pattern, after);
4599 /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4601 emit_call_insn_after_setloc (rtx pattern, rtx after, int loc)
4603 rtx last = emit_call_insn_after_noloc (pattern, after);
4605 if (pattern == NULL_RTX || !loc)
4608 after = NEXT_INSN (after);
4611 if (active_insn_p (after) && !INSN_LOCATOR (after))
4612 INSN_LOCATOR (after) = loc;
4615 after = NEXT_INSN (after);
4620 /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4622 emit_call_insn_after (rtx pattern, rtx after)
4626 while (DEBUG_INSN_P (prev))
4627 prev = PREV_INSN (prev);
4630 return emit_call_insn_after_setloc (pattern, after, INSN_LOCATOR (prev));
4632 return emit_call_insn_after_noloc (pattern, after);
4635 /* Like emit_debug_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4637 emit_debug_insn_after_setloc (rtx pattern, rtx after, int loc)
4639 rtx last = emit_debug_insn_after_noloc (pattern, after);
4641 if (pattern == NULL_RTX || !loc)
4644 after = NEXT_INSN (after);
4647 if (active_insn_p (after) && !INSN_LOCATOR (after))
4648 INSN_LOCATOR (after) = loc;
4651 after = NEXT_INSN (after);
4656 /* Like emit_debug_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4658 emit_debug_insn_after (rtx pattern, rtx after)
4661 return emit_debug_insn_after_setloc (pattern, after, INSN_LOCATOR (after));
4663 return emit_debug_insn_after_noloc (pattern, after);
4666 /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to SCOPE. */
4668 emit_insn_before_setloc (rtx pattern, rtx before, int loc)
4670 rtx first = PREV_INSN (before);
4671 rtx last = emit_insn_before_noloc (pattern, before, NULL);
4673 if (pattern == NULL_RTX || !loc)
4677 first = get_insns ();
4679 first = NEXT_INSN (first);
4682 if (active_insn_p (first) && !INSN_LOCATOR (first))
4683 INSN_LOCATOR (first) = loc;
4686 first = NEXT_INSN (first);
4691 /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */
4693 emit_insn_before (rtx pattern, rtx before)
4697 while (DEBUG_INSN_P (next))
4698 next = PREV_INSN (next);
4701 return emit_insn_before_setloc (pattern, before, INSN_LOCATOR (next));
4703 return emit_insn_before_noloc (pattern, before, NULL);
4706 /* like emit_insn_before_noloc, but set insn_locator according to scope. */
4708 emit_jump_insn_before_setloc (rtx pattern, rtx before, int loc)
4710 rtx first = PREV_INSN (before);
4711 rtx last = emit_jump_insn_before_noloc (pattern, before);
4713 if (pattern == NULL_RTX)
4716 first = NEXT_INSN (first);
4719 if (active_insn_p (first) && !INSN_LOCATOR (first))
4720 INSN_LOCATOR (first) = loc;
4723 first = NEXT_INSN (first);
4728 /* Like emit_jump_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */
4730 emit_jump_insn_before (rtx pattern, rtx before)
4734 while (DEBUG_INSN_P (next))
4735 next = PREV_INSN (next);
4738 return emit_jump_insn_before_setloc (pattern, before, INSN_LOCATOR (next));
4740 return emit_jump_insn_before_noloc (pattern, before);
4743 /* like emit_insn_before_noloc, but set insn_locator according to scope. */
4745 emit_call_insn_before_setloc (rtx pattern, rtx before, int loc)
4747 rtx first = PREV_INSN (before);
4748 rtx last = emit_call_insn_before_noloc (pattern, before);
4750 if (pattern == NULL_RTX)
4753 first = NEXT_INSN (first);
4756 if (active_insn_p (first) && !INSN_LOCATOR (first))
4757 INSN_LOCATOR (first) = loc;
4760 first = NEXT_INSN (first);
4765 /* like emit_call_insn_before_noloc,
4766 but set insn_locator according to before. */
4768 emit_call_insn_before (rtx pattern, rtx before)
4772 while (DEBUG_INSN_P (next))
4773 next = PREV_INSN (next);
4776 return emit_call_insn_before_setloc (pattern, before, INSN_LOCATOR (next));
4778 return emit_call_insn_before_noloc (pattern, before);
4781 /* like emit_insn_before_noloc, but set insn_locator according to scope. */
4783 emit_debug_insn_before_setloc (rtx pattern, rtx before, int loc)
4785 rtx first = PREV_INSN (before);
4786 rtx last = emit_debug_insn_before_noloc (pattern, before);
4788 if (pattern == NULL_RTX)
4791 first = NEXT_INSN (first);
4794 if (active_insn_p (first) && !INSN_LOCATOR (first))
4795 INSN_LOCATOR (first) = loc;
4798 first = NEXT_INSN (first);
4803 /* like emit_debug_insn_before_noloc,
4804 but set insn_locator according to before. */
4806 emit_debug_insn_before (rtx pattern, rtx before)
4808 if (INSN_P (before))
4809 return emit_debug_insn_before_setloc (pattern, before, INSN_LOCATOR (before));
4811 return emit_debug_insn_before_noloc (pattern, before);
4814 /* Take X and emit it at the end of the doubly-linked
4817 Returns the last insn emitted. */
4822 rtx last = get_last_insn();
4828 switch (GET_CODE (x))
4840 rtx next = NEXT_INSN (insn);
4847 #ifdef ENABLE_RTL_CHECKING
4854 last = make_insn_raw (x);
4862 /* Make an insn of code DEBUG_INSN with pattern X
4863 and add it to the end of the doubly-linked list. */
4866 emit_debug_insn (rtx x)
4868 rtx last = get_last_insn();
4874 switch (GET_CODE (x))
4886 rtx next = NEXT_INSN (insn);
4893 #ifdef ENABLE_RTL_CHECKING
4900 last = make_debug_insn_raw (x);
4908 /* Make an insn of code JUMP_INSN with pattern X
4909 and add it to the end of the doubly-linked list. */
4912 emit_jump_insn (rtx x)
4914 rtx last = NULL_RTX, insn;
4916 switch (GET_CODE (x))
4928 rtx next = NEXT_INSN (insn);
4935 #ifdef ENABLE_RTL_CHECKING
4942 last = make_jump_insn_raw (x);
4950 /* Make an insn of code CALL_INSN with pattern X
4951 and add it to the end of the doubly-linked list. */
4954 emit_call_insn (rtx x)
4958 switch (GET_CODE (x))
4967 insn = emit_insn (x);
4970 #ifdef ENABLE_RTL_CHECKING
4977 insn = make_call_insn_raw (x);
4985 /* Add the label LABEL to the end of the doubly-linked list. */
4988 emit_label (rtx label)
4990 /* This can be called twice for the same label
4991 as a result of the confusion that follows a syntax error!
4992 So make it harmless. */
4993 if (INSN_UID (label) == 0)
4995 INSN_UID (label) = cur_insn_uid++;
5001 /* Make an insn of code BARRIER
5002 and add it to the end of the doubly-linked list. */
5007 rtx barrier = rtx_alloc (BARRIER);
5008 INSN_UID (barrier) = cur_insn_uid++;
5013 /* Emit a copy of note ORIG. */
5016 emit_note_copy (rtx orig)
5020 note = rtx_alloc (NOTE);
5022 INSN_UID (note) = cur_insn_uid++;
5023 NOTE_DATA (note) = NOTE_DATA (orig);
5024 NOTE_KIND (note) = NOTE_KIND (orig);
5025 BLOCK_FOR_INSN (note) = NULL;
5031 /* Make an insn of code NOTE or type NOTE_NO
5032 and add it to the end of the doubly-linked list. */
5035 emit_note (enum insn_note kind)
5039 note = rtx_alloc (NOTE);
5040 INSN_UID (note) = cur_insn_uid++;
5041 NOTE_KIND (note) = kind;
5042 memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note)));
5043 BLOCK_FOR_INSN (note) = NULL;
5048 /* Emit a clobber of lvalue X. */
5051 emit_clobber (rtx x)
5053 /* CONCATs should not appear in the insn stream. */
5054 if (GET_CODE (x) == CONCAT)
5056 emit_clobber (XEXP (x, 0));
5057 return emit_clobber (XEXP (x, 1));
5059 return emit_insn (gen_rtx_CLOBBER (VOIDmode, x));
5062 /* Return a sequence of insns to clobber lvalue X. */
5076 /* Emit a use of rvalue X. */
5081 /* CONCATs should not appear in the insn stream. */
5082 if (GET_CODE (x) == CONCAT)
5084 emit_use (XEXP (x, 0));
5085 return emit_use (XEXP (x, 1));
5087 return emit_insn (gen_rtx_USE (VOIDmode, x));
5090 /* Return a sequence of insns to use rvalue X. */
5104 /* Cause next statement to emit a line note even if the line number
5108 force_next_line_note (void)
5113 /* Place a note of KIND on insn INSN with DATUM as the datum. If a
5114 note of this type already exists, remove it first. */
5117 set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum)
5119 rtx note = find_reg_note (insn, kind, NULL_RTX);
5125 /* Don't add REG_EQUAL/REG_EQUIV notes if the insn
5126 has multiple sets (some callers assume single_set
5127 means the insn only has one set, when in fact it
5128 means the insn only has one * useful * set). */
5129 if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
5135 /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes.
5136 It serves no useful purpose and breaks eliminate_regs. */
5137 if (GET_CODE (datum) == ASM_OPERANDS)
5142 XEXP (note, 0) = datum;
5143 df_notes_rescan (insn);
5151 XEXP (note, 0) = datum;
5157 add_reg_note (insn, kind, datum);
5163 df_notes_rescan (insn);
5169 return REG_NOTES (insn);
5172 /* Return an indication of which type of insn should have X as a body.
5173 The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */
5175 static enum rtx_code
5176 classify_insn (rtx x)
5180 if (GET_CODE (x) == CALL)
5182 if (GET_CODE (x) == RETURN)
5184 if (GET_CODE (x) == SET)
5186 if (SET_DEST (x) == pc_rtx)
5188 else if (GET_CODE (SET_SRC (x)) == CALL)
5193 if (GET_CODE (x) == PARALLEL)
5196 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
5197 if (GET_CODE (XVECEXP (x, 0, j)) == CALL)
5199 else if (GET_CODE (XVECEXP (x, 0, j)) == SET
5200 && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx)
5202 else if (GET_CODE (XVECEXP (x, 0, j)) == SET
5203 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL)
5209 /* Emit the rtl pattern X as an appropriate kind of insn.
5210 If X is a label, it is simply added into the insn chain. */
5215 enum rtx_code code = classify_insn (x);
5220 return emit_label (x);
5222 return emit_insn (x);
5225 rtx insn = emit_jump_insn (x);
5226 if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN)
5227 return emit_barrier ();
5231 return emit_call_insn (x);
5233 return emit_debug_insn (x);
5239 /* Space for free sequence stack entries. */
5240 static GTY ((deletable)) struct sequence_stack *free_sequence_stack;
5242 /* Begin emitting insns to a sequence. If this sequence will contain
5243 something that might cause the compiler to pop arguments to function
5244 calls (because those pops have previously been deferred; see
5245 INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust
5246 before calling this function. That will ensure that the deferred
5247 pops are not accidentally emitted in the middle of this sequence. */
5250 start_sequence (void)
5252 struct sequence_stack *tem;
5254 if (free_sequence_stack != NULL)
5256 tem = free_sequence_stack;
5257 free_sequence_stack = tem->next;
5260 tem = ggc_alloc_sequence_stack ();
5262 tem->next = seq_stack;
5263 tem->first = get_insns ();
5264 tem->last = get_last_insn ();
5272 /* Set up the insn chain starting with FIRST as the current sequence,
5273 saving the previously current one. See the documentation for
5274 start_sequence for more information about how to use this function. */
5277 push_to_sequence (rtx first)
5283 for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last));
5285 set_first_insn (first);
5286 set_last_insn (last);
5289 /* Like push_to_sequence, but take the last insn as an argument to avoid
5290 looping through the list. */
5293 push_to_sequence2 (rtx first, rtx last)
5297 set_first_insn (first);
5298 set_last_insn (last);
5301 /* Set up the outer-level insn chain
5302 as the current sequence, saving the previously current one. */
5305 push_topmost_sequence (void)
5307 struct sequence_stack *stack, *top = NULL;
5311 for (stack = seq_stack; stack; stack = stack->next)
5314 set_first_insn (top->first);
5315 set_last_insn (top->last);
5318 /* After emitting to the outer-level insn chain, update the outer-level
5319 insn chain, and restore the previous saved state. */
5322 pop_topmost_sequence (void)
5324 struct sequence_stack *stack, *top = NULL;
5326 for (stack = seq_stack; stack; stack = stack->next)
5329 top->first = get_insns ();
5330 top->last = get_last_insn ();
5335 /* After emitting to a sequence, restore previous saved state.
5337 To get the contents of the sequence just made, you must call
5338 `get_insns' *before* calling here.
5340 If the compiler might have deferred popping arguments while
5341 generating this sequence, and this sequence will not be immediately
5342 inserted into the instruction stream, use do_pending_stack_adjust
5343 before calling get_insns. That will ensure that the deferred
5344 pops are inserted into this sequence, and not into some random
5345 location in the instruction stream. See INHIBIT_DEFER_POP for more
5346 information about deferred popping of arguments. */
5351 struct sequence_stack *tem = seq_stack;
5353 set_first_insn (tem->first);
5354 set_last_insn (tem->last);
5355 seq_stack = tem->next;
5357 memset (tem, 0, sizeof (*tem));
5358 tem->next = free_sequence_stack;
5359 free_sequence_stack = tem;
5362 /* Return 1 if currently emitting into a sequence. */
5365 in_sequence_p (void)
5367 return seq_stack != 0;
5370 /* Put the various virtual registers into REGNO_REG_RTX. */
5373 init_virtual_regs (void)
5375 regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx;
5376 regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx;
5377 regno_reg_rtx[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx;
5378 regno_reg_rtx[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx;
5379 regno_reg_rtx[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx;
5383 /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */
5384 static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS];
5385 static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS];
5386 static int copy_insn_n_scratches;
5388 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
5389 copied an ASM_OPERANDS.
5390 In that case, it is the original input-operand vector. */
5391 static rtvec orig_asm_operands_vector;
5393 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
5394 copied an ASM_OPERANDS.
5395 In that case, it is the copied input-operand vector. */
5396 static rtvec copy_asm_operands_vector;
5398 /* Likewise for the constraints vector. */
5399 static rtvec orig_asm_constraints_vector;
5400 static rtvec copy_asm_constraints_vector;
5402 /* Recursively create a new copy of an rtx for copy_insn.
5403 This function differs from copy_rtx in that it handles SCRATCHes and
5404 ASM_OPERANDs properly.
5405 Normally, this function is not used directly; use copy_insn as front end.
5406 However, you could first copy an insn pattern with copy_insn and then use
5407 this function afterwards to properly copy any REG_NOTEs containing
5411 copy_insn_1 (rtx orig)
5416 const char *format_ptr;
5421 code = GET_CODE (orig);
5436 if (REG_P (XEXP (orig, 0)) && REGNO (XEXP (orig, 0)) < FIRST_PSEUDO_REGISTER)
5441 for (i = 0; i < copy_insn_n_scratches; i++)
5442 if (copy_insn_scratch_in[i] == orig)
5443 return copy_insn_scratch_out[i];
5447 if (shared_const_p (orig))
5451 /* A MEM with a constant address is not sharable. The problem is that
5452 the constant address may need to be reloaded. If the mem is shared,
5453 then reloading one copy of this mem will cause all copies to appear
5454 to have been reloaded. */
5460 /* Copy the various flags, fields, and other information. We assume
5461 that all fields need copying, and then clear the fields that should
5462 not be copied. That is the sensible default behavior, and forces
5463 us to explicitly document why we are *not* copying a flag. */
5464 copy = shallow_copy_rtx (orig);
5466 /* We do not copy the USED flag, which is used as a mark bit during
5467 walks over the RTL. */
5468 RTX_FLAG (copy, used) = 0;
5470 /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */
5473 RTX_FLAG (copy, jump) = 0;
5474 RTX_FLAG (copy, call) = 0;
5475 RTX_FLAG (copy, frame_related) = 0;
5478 format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
5480 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
5481 switch (*format_ptr++)
5484 if (XEXP (orig, i) != NULL)
5485 XEXP (copy, i) = copy_insn_1 (XEXP (orig, i));
5490 if (XVEC (orig, i) == orig_asm_constraints_vector)
5491 XVEC (copy, i) = copy_asm_constraints_vector;
5492 else if (XVEC (orig, i) == orig_asm_operands_vector)
5493 XVEC (copy, i) = copy_asm_operands_vector;
5494 else if (XVEC (orig, i) != NULL)
5496 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
5497 for (j = 0; j < XVECLEN (copy, i); j++)
5498 XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j));
5509 /* These are left unchanged. */
5516 if (code == SCRATCH)
5518 i = copy_insn_n_scratches++;
5519 gcc_assert (i < MAX_RECOG_OPERANDS);
5520 copy_insn_scratch_in[i] = orig;
5521 copy_insn_scratch_out[i] = copy;
5523 else if (code == ASM_OPERANDS)
5525 orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig);
5526 copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy);
5527 orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig);
5528 copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy);
5534 /* Create a new copy of an rtx.
5535 This function differs from copy_rtx in that it handles SCRATCHes and
5536 ASM_OPERANDs properly.
5537 INSN doesn't really have to be a full INSN; it could be just the
5540 copy_insn (rtx insn)
5542 copy_insn_n_scratches = 0;
5543 orig_asm_operands_vector = 0;
5544 orig_asm_constraints_vector = 0;
5545 copy_asm_operands_vector = 0;
5546 copy_asm_constraints_vector = 0;
5547 return copy_insn_1 (insn);
5550 /* Initialize data structures and variables in this file
5551 before generating rtl for each function. */
5556 set_first_insn (NULL);
5557 set_last_insn (NULL);
5558 if (MIN_NONDEBUG_INSN_UID)
5559 cur_insn_uid = MIN_NONDEBUG_INSN_UID;
5562 cur_debug_insn_uid = 1;
5563 reg_rtx_no = LAST_VIRTUAL_REGISTER + 1;
5564 last_location = UNKNOWN_LOCATION;
5565 first_label_num = label_num;
5568 /* Init the tables that describe all the pseudo regs. */
5570 crtl->emit.regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101;
5572 crtl->emit.regno_pointer_align
5573 = XCNEWVEC (unsigned char, crtl->emit.regno_pointer_align_length);
5575 regno_reg_rtx = ggc_alloc_vec_rtx (crtl->emit.regno_pointer_align_length);
5577 /* Put copies of all the hard registers into regno_reg_rtx. */
5578 memcpy (regno_reg_rtx,
5579 static_regno_reg_rtx,
5580 FIRST_PSEUDO_REGISTER * sizeof (rtx));
5582 /* Put copies of all the virtual register rtx into regno_reg_rtx. */
5583 init_virtual_regs ();
5585 /* Indicate that the virtual registers and stack locations are
5587 REG_POINTER (stack_pointer_rtx) = 1;
5588 REG_POINTER (frame_pointer_rtx) = 1;
5589 REG_POINTER (hard_frame_pointer_rtx) = 1;
5590 REG_POINTER (arg_pointer_rtx) = 1;
5592 REG_POINTER (virtual_incoming_args_rtx) = 1;
5593 REG_POINTER (virtual_stack_vars_rtx) = 1;
5594 REG_POINTER (virtual_stack_dynamic_rtx) = 1;
5595 REG_POINTER (virtual_outgoing_args_rtx) = 1;
5596 REG_POINTER (virtual_cfa_rtx) = 1;
5598 #ifdef STACK_BOUNDARY
5599 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY;
5600 REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY;
5601 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY;
5602 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY;
5604 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY;
5605 REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY;
5606 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY;
5607 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY;
5608 REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD;
5611 #ifdef INIT_EXPANDERS
5616 /* Generate a vector constant for mode MODE and constant value CONSTANT. */
5619 gen_const_vector (enum machine_mode mode, int constant)
5624 enum machine_mode inner;
5626 units = GET_MODE_NUNITS (mode);
5627 inner = GET_MODE_INNER (mode);
5629 gcc_assert (!DECIMAL_FLOAT_MODE_P (inner));
5631 v = rtvec_alloc (units);
5633 /* We need to call this function after we set the scalar const_tiny_rtx
5635 gcc_assert (const_tiny_rtx[constant][(int) inner]);
5637 for (i = 0; i < units; ++i)
5638 RTVEC_ELT (v, i) = const_tiny_rtx[constant][(int) inner];
5640 tem = gen_rtx_raw_CONST_VECTOR (mode, v);
5644 /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when
5645 all elements are zero, and the one vector when all elements are one. */
5647 gen_rtx_CONST_VECTOR (enum machine_mode mode, rtvec v)
5649 enum machine_mode inner = GET_MODE_INNER (mode);
5650 int nunits = GET_MODE_NUNITS (mode);
5654 /* Check to see if all of the elements have the same value. */
5655 x = RTVEC_ELT (v, nunits - 1);
5656 for (i = nunits - 2; i >= 0; i--)
5657 if (RTVEC_ELT (v, i) != x)
5660 /* If the values are all the same, check to see if we can use one of the
5661 standard constant vectors. */
5664 if (x == CONST0_RTX (inner))
5665 return CONST0_RTX (mode);
5666 else if (x == CONST1_RTX (inner))
5667 return CONST1_RTX (mode);
5670 return gen_rtx_raw_CONST_VECTOR (mode, v);
5673 /* Initialise global register information required by all functions. */
5676 init_emit_regs (void)
5680 /* Reset register attributes */
5681 htab_empty (reg_attrs_htab);
5683 /* We need reg_raw_mode, so initialize the modes now. */
5684 init_reg_modes_target ();
5686 /* Assign register numbers to the globally defined register rtx. */
5687 pc_rtx = gen_rtx_PC (VOIDmode);
5688 cc0_rtx = gen_rtx_CC0 (VOIDmode);
5689 stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM);
5690 frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM);
5691 hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
5692 arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM);
5693 virtual_incoming_args_rtx =
5694 gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM);
5695 virtual_stack_vars_rtx =
5696 gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM);
5697 virtual_stack_dynamic_rtx =
5698 gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM);
5699 virtual_outgoing_args_rtx =
5700 gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM);
5701 virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM);
5703 /* Initialize RTL for commonly used hard registers. These are
5704 copied into regno_reg_rtx as we begin to compile each function. */
5705 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5706 static_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i);
5708 #ifdef RETURN_ADDRESS_POINTER_REGNUM
5709 return_address_pointer_rtx
5710 = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM);
5713 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
5714 pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
5716 pic_offset_table_rtx = NULL_RTX;
5719 /* Create some permanent unique rtl objects shared between all functions. */
5722 init_emit_once (void)
5725 enum machine_mode mode;
5726 enum machine_mode double_mode;
5728 /* Initialize the CONST_INT, CONST_DOUBLE, CONST_FIXED, and memory attribute
5730 const_int_htab = htab_create_ggc (37, const_int_htab_hash,
5731 const_int_htab_eq, NULL);
5733 const_double_htab = htab_create_ggc (37, const_double_htab_hash,
5734 const_double_htab_eq, NULL);
5736 const_fixed_htab = htab_create_ggc (37, const_fixed_htab_hash,
5737 const_fixed_htab_eq, NULL);
5739 mem_attrs_htab = htab_create_ggc (37, mem_attrs_htab_hash,
5740 mem_attrs_htab_eq, NULL);
5741 reg_attrs_htab = htab_create_ggc (37, reg_attrs_htab_hash,
5742 reg_attrs_htab_eq, NULL);
5744 /* Compute the word and byte modes. */
5746 byte_mode = VOIDmode;
5747 word_mode = VOIDmode;
5748 double_mode = VOIDmode;
5750 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
5752 mode = GET_MODE_WIDER_MODE (mode))
5754 if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT
5755 && byte_mode == VOIDmode)
5758 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD
5759 && word_mode == VOIDmode)
5763 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
5765 mode = GET_MODE_WIDER_MODE (mode))
5767 if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE
5768 && double_mode == VOIDmode)
5772 ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0);
5774 #ifdef INIT_EXPANDERS
5775 /* This is to initialize {init|mark|free}_machine_status before the first
5776 call to push_function_context_to. This is needed by the Chill front
5777 end which calls push_function_context_to before the first call to
5778 init_function_start. */
5782 /* Create the unique rtx's for certain rtx codes and operand values. */
5784 /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case
5785 tries to use these variables. */
5786 for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++)
5787 const_int_rtx[i + MAX_SAVED_CONST_INT] =
5788 gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i);
5790 if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT
5791 && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT)
5792 const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT];
5794 const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE);
5796 REAL_VALUE_FROM_INT (dconst0, 0, 0, double_mode);
5797 REAL_VALUE_FROM_INT (dconst1, 1, 0, double_mode);
5798 REAL_VALUE_FROM_INT (dconst2, 2, 0, double_mode);
5803 dconsthalf = dconst1;
5804 SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1);
5806 for (i = 0; i < (int) ARRAY_SIZE (const_tiny_rtx); i++)
5808 const REAL_VALUE_TYPE *const r =
5809 (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2);
5811 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
5813 mode = GET_MODE_WIDER_MODE (mode))
5814 const_tiny_rtx[i][(int) mode] =
5815 CONST_DOUBLE_FROM_REAL_VALUE (*r, mode);
5817 for (mode = GET_CLASS_NARROWEST_MODE (MODE_DECIMAL_FLOAT);
5819 mode = GET_MODE_WIDER_MODE (mode))
5820 const_tiny_rtx[i][(int) mode] =
5821 CONST_DOUBLE_FROM_REAL_VALUE (*r, mode);
5823 const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i);
5825 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
5827 mode = GET_MODE_WIDER_MODE (mode))
5828 const_tiny_rtx[i][(int) mode] = GEN_INT (i);
5830 for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT);
5832 mode = GET_MODE_WIDER_MODE (mode))
5833 const_tiny_rtx[i][(int) mode] = GEN_INT (i);
5836 for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_INT);
5838 mode = GET_MODE_WIDER_MODE (mode))
5840 rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)];
5841 const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner);
5844 for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT);
5846 mode = GET_MODE_WIDER_MODE (mode))
5848 rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)];
5849 const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner);
5852 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT);
5854 mode = GET_MODE_WIDER_MODE (mode))
5856 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
5857 const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1);
5860 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT);
5862 mode = GET_MODE_WIDER_MODE (mode))
5864 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
5865 const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1);
5868 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FRACT);
5870 mode = GET_MODE_WIDER_MODE (mode))
5872 FCONST0(mode).data.high = 0;
5873 FCONST0(mode).data.low = 0;
5874 FCONST0(mode).mode = mode;
5875 const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE (
5876 FCONST0 (mode), mode);
5879 for (mode = GET_CLASS_NARROWEST_MODE (MODE_UFRACT);
5881 mode = GET_MODE_WIDER_MODE (mode))
5883 FCONST0(mode).data.high = 0;
5884 FCONST0(mode).data.low = 0;
5885 FCONST0(mode).mode = mode;
5886 const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE (
5887 FCONST0 (mode), mode);
5890 for (mode = GET_CLASS_NARROWEST_MODE (MODE_ACCUM);
5892 mode = GET_MODE_WIDER_MODE (mode))
5894 FCONST0(mode).data.high = 0;
5895 FCONST0(mode).data.low = 0;
5896 FCONST0(mode).mode = mode;
5897 const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE (
5898 FCONST0 (mode), mode);
5900 /* We store the value 1. */
5901 FCONST1(mode).data.high = 0;
5902 FCONST1(mode).data.low = 0;
5903 FCONST1(mode).mode = mode;
5904 lshift_double (1, 0, GET_MODE_FBIT (mode),
5905 2 * HOST_BITS_PER_WIDE_INT,
5906 &FCONST1(mode).data.low,
5907 &FCONST1(mode).data.high,
5908 SIGNED_FIXED_POINT_MODE_P (mode));
5909 const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE (
5910 FCONST1 (mode), mode);
5913 for (mode = GET_CLASS_NARROWEST_MODE (MODE_UACCUM);
5915 mode = GET_MODE_WIDER_MODE (mode))
5917 FCONST0(mode).data.high = 0;
5918 FCONST0(mode).data.low = 0;
5919 FCONST0(mode).mode = mode;
5920 const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE (
5921 FCONST0 (mode), mode);
5923 /* We store the value 1. */
5924 FCONST1(mode).data.high = 0;
5925 FCONST1(mode).data.low = 0;
5926 FCONST1(mode).mode = mode;
5927 lshift_double (1, 0, GET_MODE_FBIT (mode),
5928 2 * HOST_BITS_PER_WIDE_INT,
5929 &FCONST1(mode).data.low,
5930 &FCONST1(mode).data.high,
5931 SIGNED_FIXED_POINT_MODE_P (mode));
5932 const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE (
5933 FCONST1 (mode), mode);
5936 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FRACT);
5938 mode = GET_MODE_WIDER_MODE (mode))
5940 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
5943 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UFRACT);
5945 mode = GET_MODE_WIDER_MODE (mode))
5947 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
5950 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_ACCUM);
5952 mode = GET_MODE_WIDER_MODE (mode))
5954 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
5955 const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1);
5958 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UACCUM);
5960 mode = GET_MODE_WIDER_MODE (mode))
5962 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
5963 const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1);
5966 for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i)
5967 if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC)
5968 const_tiny_rtx[0][i] = const0_rtx;
5970 const_tiny_rtx[0][(int) BImode] = const0_rtx;
5971 if (STORE_FLAG_VALUE == 1)
5972 const_tiny_rtx[1][(int) BImode] = const1_rtx;
5975 /* Produce exact duplicate of insn INSN after AFTER.
5976 Care updating of libcall regions if present. */
5979 emit_copy_of_insn_after (rtx insn, rtx after)
5983 switch (GET_CODE (insn))
5986 new_rtx = emit_insn_after (copy_insn (PATTERN (insn)), after);
5990 new_rtx = emit_jump_insn_after (copy_insn (PATTERN (insn)), after);
5994 new_rtx = emit_debug_insn_after (copy_insn (PATTERN (insn)), after);
5998 new_rtx = emit_call_insn_after (copy_insn (PATTERN (insn)), after);
5999 if (CALL_INSN_FUNCTION_USAGE (insn))
6000 CALL_INSN_FUNCTION_USAGE (new_rtx)
6001 = copy_insn (CALL_INSN_FUNCTION_USAGE (insn));
6002 SIBLING_CALL_P (new_rtx) = SIBLING_CALL_P (insn);
6003 RTL_CONST_CALL_P (new_rtx) = RTL_CONST_CALL_P (insn);
6004 RTL_PURE_CALL_P (new_rtx) = RTL_PURE_CALL_P (insn);
6005 RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx)
6006 = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn);
6013 /* Update LABEL_NUSES. */
6014 mark_jump_label (PATTERN (new_rtx), new_rtx, 0);
6016 INSN_LOCATOR (new_rtx) = INSN_LOCATOR (insn);
6018 /* If the old insn is frame related, then so is the new one. This is
6019 primarily needed for IA-64 unwind info which marks epilogue insns,
6020 which may be duplicated by the basic block reordering code. */
6021 RTX_FRAME_RELATED_P (new_rtx) = RTX_FRAME_RELATED_P (insn);
6023 /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label
6024 will make them. REG_LABEL_TARGETs are created there too, but are
6025 supposed to be sticky, so we copy them. */
6026 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
6027 if (REG_NOTE_KIND (link) != REG_LABEL_OPERAND)
6029 if (GET_CODE (link) == EXPR_LIST)
6030 add_reg_note (new_rtx, REG_NOTE_KIND (link),
6031 copy_insn_1 (XEXP (link, 0)));
6033 add_reg_note (new_rtx, REG_NOTE_KIND (link), XEXP (link, 0));
6036 INSN_CODE (new_rtx) = INSN_CODE (insn);
6040 static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
6042 gen_hard_reg_clobber (enum machine_mode mode, unsigned int regno)
6044 if (hard_reg_clobbers[mode][regno])
6045 return hard_reg_clobbers[mode][regno];
6047 return (hard_reg_clobbers[mode][regno] =
6048 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno)));
6051 #include "gt-emit-rtl.h"