1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
3 @c Free Software Foundation, Inc.
4 @c This is part of the GCC manual.
5 @c For copying conditions, see the file gcc.texi.
9 @chapter Machine Descriptions
10 @cindex machine descriptions
12 A machine description has two parts: a file of instruction patterns
13 (@file{.md} file) and a C header file of macro definitions.
15 The @file{.md} file for a target machine contains a pattern for each
16 instruction that the target machine supports (or at least each instruction
17 that is worth telling the compiler about). It may also contain comments.
18 A semicolon causes the rest of the line to be a comment, unless the semicolon
19 is inside a quoted string.
21 See the next chapter for information on the C header file.
24 * Overview:: How the machine description is used.
25 * Patterns:: How to write instruction patterns.
26 * Example:: An explained example of a @code{define_insn} pattern.
27 * RTL Template:: The RTL template defines what insns match a pattern.
28 * Output Template:: The output template says how to make assembler code
30 * Output Statement:: For more generality, write C code to output
32 * Predicates:: Controlling what kinds of operands can be used
34 * Constraints:: Fine-tuning operand selection.
35 * Standard Names:: Names mark patterns to use for code generation.
36 * Pattern Ordering:: When the order of patterns makes a difference.
37 * Dependent Patterns:: Having one pattern may make you need another.
38 * Jump Patterns:: Special considerations for patterns for jump insns.
39 * Looping Patterns:: How to define patterns for special looping insns.
40 * Insn Canonicalizations::Canonicalization of Instructions
41 * Expander Definitions::Generating a sequence of several RTL insns
42 for a standard operation.
43 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
44 * Including Patterns:: Including Patterns in Machine Descriptions.
45 * Peephole Definitions::Defining machine-specific peephole optimizations.
46 * Insn Attributes:: Specifying the value of attributes for generated insns.
47 * Conditional Execution::Generating @code{define_insn} patterns for
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 Each instruction pattern contains an incomplete RTL expression, with pieces
109 to be filled in later, operand constraints that restrict how the pieces can
110 be filled in, and an output pattern or C code to generate the assembler
111 output, all wrapped up in a @code{define_insn} expression.
113 A @code{define_insn} is an RTL expression containing four or five operands:
117 An optional name. The presence of a name indicate that this instruction
118 pattern can perform a certain standard job for the RTL-generation
119 pass of the compiler. This pass knows certain names and will use
120 the instruction patterns with those names, if the names are defined
121 in the machine description.
123 The absence of a name is indicated by writing an empty string
124 where the name should go. Nameless instruction patterns are never
125 used for generating RTL code, but they may permit several simpler insns
126 to be combined later on.
128 Names that are not thus known and used in RTL-generation have no
129 effect; they are equivalent to no name at all.
131 For the purpose of debugging the compiler, you may also specify a
132 name beginning with the @samp{*} character. Such a name is used only
133 for identifying the instruction in RTL dumps; it is entirely equivalent
134 to having a nameless pattern for all other purposes.
137 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
138 RTL expressions which show what the instruction should look like. It is
139 incomplete because it may contain @code{match_operand},
140 @code{match_operator}, and @code{match_dup} expressions that stand for
141 operands of the instruction.
143 If the vector has only one element, that element is the template for the
144 instruction pattern. If the vector has multiple elements, then the
145 instruction pattern is a @code{parallel} expression containing the
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 A condition. This is a string which contains a C expression that is
152 the final test to decide whether an insn body matches this pattern.
154 @cindex named patterns and conditions
155 For a named pattern, the condition (if present) may not depend on
156 the data in the insn being matched, but only the target-machine-type
157 flags. The compiler needs to test these conditions during
158 initialization in order to learn exactly which named instructions are
159 available in a particular run.
162 For nameless patterns, the condition is applied only when matching an
163 individual insn, and only after the insn has matched the pattern's
164 recognition template. The insn's operands may be found in the vector
165 @code{operands}. For an insn where the condition has once matched, it
166 can't be used to control register allocation, for example by excluding
167 certain hard registers or hard register combinations.
170 The @dfn{output template}: a string that says how to output matching
171 insns as assembler code. @samp{%} in this string specifies where
172 to substitute the value of an operand. @xref{Output Template}.
174 When simple substitution isn't general enough, you can specify a piece
175 of C code to compute the output. @xref{Output Statement}.
178 Optionally, a vector containing the values of attributes for insns matching
179 this pattern. @xref{Insn Attributes}.
183 @section Example of @code{define_insn}
184 @cindex @code{define_insn} example
186 Here is an actual example of an instruction pattern, for the 68000/68020.
191 (match_operand:SI 0 "general_operand" "rm"))]
195 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
197 return \"cmpl #0,%0\";
202 This can also be written using braced strings:
207 (match_operand:SI 0 "general_operand" "rm"))]
210 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
216 This is an instruction that sets the condition codes based on the value of
217 a general operand. It has no condition, so any insn whose RTL description
218 has the form shown may be handled according to this pattern. The name
219 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
220 pass that, when it is necessary to test such a value, an insn to do so
221 can be constructed using this pattern.
223 The output control string is a piece of C code which chooses which
224 output template to return based on the kind of operand and the specific
225 type of CPU for which code is being generated.
227 @samp{"rm"} is an operand constraint. Its meaning is explained below.
230 @section RTL Template
231 @cindex RTL insn template
232 @cindex generating insns
233 @cindex insns, generating
234 @cindex recognizing insns
235 @cindex insns, recognizing
237 The RTL template is used to define which insns match the particular pattern
238 and how to find their operands. For named patterns, the RTL template also
239 says how to construct an insn from specified operands.
241 Construction involves substituting specified operands into a copy of the
242 template. Matching involves determining the values that serve as the
243 operands in the insn being matched. Both of these activities are
244 controlled by special expression types that direct matching and
245 substitution of the operands.
248 @findex match_operand
249 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
250 This expression is a placeholder for operand number @var{n} of
251 the insn. When constructing an insn, operand number @var{n}
252 will be substituted at this point. When matching an insn, whatever
253 appears at this position in the insn will be taken as operand
254 number @var{n}; but it must satisfy @var{predicate} or this instruction
255 pattern will not match at all.
257 Operand numbers must be chosen consecutively counting from zero in
258 each instruction pattern. There may be only one @code{match_operand}
259 expression in the pattern for each operand number. Usually operands
260 are numbered in the order of appearance in @code{match_operand}
261 expressions. In the case of a @code{define_expand}, any operand numbers
262 used only in @code{match_dup} expressions have higher values than all
263 other operand numbers.
265 @var{predicate} is a string that is the name of a function that
266 accepts two arguments, an expression and a machine mode.
267 @xref{Predicates}. During matching, the function will be called with
268 the putative operand as the expression and @var{m} as the mode
269 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
270 which normally causes @var{predicate} to accept any mode). If it
271 returns zero, this instruction pattern fails to match.
272 @var{predicate} may be an empty string; then it means no test is to be
273 done on the operand, so anything which occurs in this position is
276 Most of the time, @var{predicate} will reject modes other than @var{m}---but
277 not always. For example, the predicate @code{address_operand} uses
278 @var{m} as the mode of memory ref that the address should be valid for.
279 Many predicates accept @code{const_int} nodes even though their mode is
282 @var{constraint} controls reloading and the choice of the best register
283 class to use for a value, as explained later (@pxref{Constraints}).
284 If the constraint would be an empty string, it can be omitted.
286 People are often unclear on the difference between the constraint and the
287 predicate. The predicate helps decide whether a given insn matches the
288 pattern. The constraint plays no role in this decision; instead, it
289 controls various decisions in the case of an insn which does match.
291 @findex match_scratch
292 @item (match_scratch:@var{m} @var{n} @var{constraint})
293 This expression is also a placeholder for operand number @var{n}
294 and indicates that operand must be a @code{scratch} or @code{reg}
297 When matching patterns, this is equivalent to
300 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
303 but, when generating RTL, it produces a (@code{scratch}:@var{m})
306 If the last few expressions in a @code{parallel} are @code{clobber}
307 expressions whose operands are either a hard register or
308 @code{match_scratch}, the combiner can add or delete them when
309 necessary. @xref{Side Effects}.
312 @item (match_dup @var{n})
313 This expression is also a placeholder for operand number @var{n}.
314 It is used when the operand needs to appear more than once in the
317 In construction, @code{match_dup} acts just like @code{match_operand}:
318 the operand is substituted into the insn being constructed. But in
319 matching, @code{match_dup} behaves differently. It assumes that operand
320 number @var{n} has already been determined by a @code{match_operand}
321 appearing earlier in the recognition template, and it matches only an
322 identical-looking expression.
324 Note that @code{match_dup} should not be used to tell the compiler that
325 a particular register is being used for two operands (example:
326 @code{add} that adds one register to another; the second register is
327 both an input operand and the output operand). Use a matching
328 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
329 operand is used in two places in the template, such as an instruction
330 that computes both a quotient and a remainder, where the opcode takes
331 two input operands but the RTL template has to refer to each of those
332 twice; once for the quotient pattern and once for the remainder pattern.
334 @findex match_operator
335 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
336 This pattern is a kind of placeholder for a variable RTL expression
339 When constructing an insn, it stands for an RTL expression whose
340 expression code is taken from that of operand @var{n}, and whose
341 operands are constructed from the patterns @var{operands}.
343 When matching an expression, it matches an expression if the function
344 @var{predicate} returns nonzero on that expression @emph{and} the
345 patterns @var{operands} match the operands of the expression.
347 Suppose that the function @code{commutative_operator} is defined as
348 follows, to match any expression whose operator is one of the
349 commutative arithmetic operators of RTL and whose mode is @var{mode}:
353 commutative_integer_operator (x, mode)
355 enum machine_mode mode;
357 enum rtx_code code = GET_CODE (x);
358 if (GET_MODE (x) != mode)
360 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
361 || code == EQ || code == NE);
365 Then the following pattern will match any RTL expression consisting
366 of a commutative operator applied to two general operands:
369 (match_operator:SI 3 "commutative_operator"
370 [(match_operand:SI 1 "general_operand" "g")
371 (match_operand:SI 2 "general_operand" "g")])
374 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
375 because the expressions to be matched all contain two operands.
377 When this pattern does match, the two operands of the commutative
378 operator are recorded as operands 1 and 2 of the insn. (This is done
379 by the two instances of @code{match_operand}.) Operand 3 of the insn
380 will be the entire commutative expression: use @code{GET_CODE
381 (operands[3])} to see which commutative operator was used.
383 The machine mode @var{m} of @code{match_operator} works like that of
384 @code{match_operand}: it is passed as the second argument to the
385 predicate function, and that function is solely responsible for
386 deciding whether the expression to be matched ``has'' that mode.
388 When constructing an insn, argument 3 of the gen-function will specify
389 the operation (i.e.@: the expression code) for the expression to be
390 made. It should be an RTL expression, whose expression code is copied
391 into a new expression whose operands are arguments 1 and 2 of the
392 gen-function. The subexpressions of argument 3 are not used;
393 only its expression code matters.
395 When @code{match_operator} is used in a pattern for matching an insn,
396 it usually best if the operand number of the @code{match_operator}
397 is higher than that of the actual operands of the insn. This improves
398 register allocation because the register allocator often looks at
399 operands 1 and 2 of insns to see if it can do register tying.
401 There is no way to specify constraints in @code{match_operator}. The
402 operand of the insn which corresponds to the @code{match_operator}
403 never has any constraints because it is never reloaded as a whole.
404 However, if parts of its @var{operands} are matched by
405 @code{match_operand} patterns, those parts may have constraints of
409 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
410 Like @code{match_dup}, except that it applies to operators instead of
411 operands. When constructing an insn, operand number @var{n} will be
412 substituted at this point. But in matching, @code{match_op_dup} behaves
413 differently. It assumes that operand number @var{n} has already been
414 determined by a @code{match_operator} appearing earlier in the
415 recognition template, and it matches only an identical-looking
418 @findex match_parallel
419 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
420 This pattern is a placeholder for an insn that consists of a
421 @code{parallel} expression with a variable number of elements. This
422 expression should only appear at the top level of an insn pattern.
424 When constructing an insn, operand number @var{n} will be substituted at
425 this point. When matching an insn, it matches if the body of the insn
426 is a @code{parallel} expression with at least as many elements as the
427 vector of @var{subpat} expressions in the @code{match_parallel}, if each
428 @var{subpat} matches the corresponding element of the @code{parallel},
429 @emph{and} the function @var{predicate} returns nonzero on the
430 @code{parallel} that is the body of the insn. It is the responsibility
431 of the predicate to validate elements of the @code{parallel} beyond
432 those listed in the @code{match_parallel}.
434 A typical use of @code{match_parallel} is to match load and store
435 multiple expressions, which can contain a variable number of elements
436 in a @code{parallel}. For example,
440 [(match_parallel 0 "load_multiple_operation"
441 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
442 (match_operand:SI 2 "memory_operand" "m"))
444 (clobber (reg:SI 179))])]
449 This example comes from @file{a29k.md}. The function
450 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
451 that subsequent elements in the @code{parallel} are the same as the
452 @code{set} in the pattern, except that they are referencing subsequent
453 registers and memory locations.
455 An insn that matches this pattern might look like:
459 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
461 (clobber (reg:SI 179))
463 (mem:SI (plus:SI (reg:SI 100)
466 (mem:SI (plus:SI (reg:SI 100)
470 @findex match_par_dup
471 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
472 Like @code{match_op_dup}, but for @code{match_parallel} instead of
473 @code{match_operator}.
477 @node Output Template
478 @section Output Templates and Operand Substitution
479 @cindex output templates
480 @cindex operand substitution
482 @cindex @samp{%} in template
484 The @dfn{output template} is a string which specifies how to output the
485 assembler code for an instruction pattern. Most of the template is a
486 fixed string which is output literally. The character @samp{%} is used
487 to specify where to substitute an operand; it can also be used to
488 identify places where different variants of the assembler require
491 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
492 operand @var{n} at that point in the string.
494 @samp{%} followed by a letter and a digit says to output an operand in an
495 alternate fashion. Four letters have standard, built-in meanings described
496 below. The machine description macro @code{PRINT_OPERAND} can define
497 additional letters with nonstandard meanings.
499 @samp{%c@var{digit}} can be used to substitute an operand that is a
500 constant value without the syntax that normally indicates an immediate
503 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
504 the constant is negated before printing.
506 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
507 memory reference, with the actual operand treated as the address. This may
508 be useful when outputting a ``load address'' instruction, because often the
509 assembler syntax for such an instruction requires you to write the operand
510 as if it were a memory reference.
512 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
515 @samp{%=} outputs a number which is unique to each instruction in the
516 entire compilation. This is useful for making local labels to be
517 referred to more than once in a single template that generates multiple
518 assembler instructions.
520 @samp{%} followed by a punctuation character specifies a substitution that
521 does not use an operand. Only one case is standard: @samp{%%} outputs a
522 @samp{%} into the assembler code. Other nonstandard cases can be
523 defined in the @code{PRINT_OPERAND} macro. You must also define
524 which punctuation characters are valid with the
525 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
529 The template may generate multiple assembler instructions. Write the text
530 for the instructions, with @samp{\;} between them.
532 @cindex matching operands
533 When the RTL contains two operands which are required by constraint to match
534 each other, the output template must refer only to the lower-numbered operand.
535 Matching operands are not always identical, and the rest of the compiler
536 arranges to put the proper RTL expression for printing into the lower-numbered
539 One use of nonstandard letters or punctuation following @samp{%} is to
540 distinguish between different assembler languages for the same machine; for
541 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
542 requires periods in most opcode names, while MIT syntax does not. For
543 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
544 syntax. The same file of patterns is used for both kinds of output syntax,
545 but the character sequence @samp{%.} is used in each place where Motorola
546 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
547 defines the sequence to output a period; the macro for MIT syntax defines
550 @cindex @code{#} in template
551 As a special case, a template consisting of the single character @code{#}
552 instructs the compiler to first split the insn, and then output the
553 resulting instructions separately. This helps eliminate redundancy in the
554 output templates. If you have a @code{define_insn} that needs to emit
555 multiple assembler instructions, and there is a matching @code{define_split}
556 already defined, then you can simply use @code{#} as the output template
557 instead of writing an output template that emits the multiple assembler
560 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
561 of the form @samp{@{option0|option1|option2@}} in the templates. These
562 describe multiple variants of assembler language syntax.
563 @xref{Instruction Output}.
565 @node Output Statement
566 @section C Statements for Assembler Output
567 @cindex output statements
568 @cindex C statements for assembler output
569 @cindex generating assembler output
571 Often a single fixed template string cannot produce correct and efficient
572 assembler code for all the cases that are recognized by a single
573 instruction pattern. For example, the opcodes may depend on the kinds of
574 operands; or some unfortunate combinations of operands may require extra
575 machine instructions.
577 If the output control string starts with a @samp{@@}, then it is actually
578 a series of templates, each on a separate line. (Blank lines and
579 leading spaces and tabs are ignored.) The templates correspond to the
580 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
581 if a target machine has a two-address add instruction @samp{addr} to add
582 into a register and another @samp{addm} to add a register to memory, you
583 might write this pattern:
586 (define_insn "addsi3"
587 [(set (match_operand:SI 0 "general_operand" "=r,m")
588 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
589 (match_operand:SI 2 "general_operand" "g,r")))]
596 @cindex @code{*} in template
597 @cindex asterisk in template
598 If the output control string starts with a @samp{*}, then it is not an
599 output template but rather a piece of C program that should compute a
600 template. It should execute a @code{return} statement to return the
601 template-string you want. Most such templates use C string literals, which
602 require doublequote characters to delimit them. To include these
603 doublequote characters in the string, prefix each one with @samp{\}.
605 If the output control string is written as a brace block instead of a
606 double-quoted string, it is automatically assumed to be C code. In that
607 case, it is not necessary to put in a leading asterisk, or to escape the
608 doublequotes surrounding C string literals.
610 The operands may be found in the array @code{operands}, whose C data type
613 It is very common to select different ways of generating assembler code
614 based on whether an immediate operand is within a certain range. Be
615 careful when doing this, because the result of @code{INTVAL} is an
616 integer on the host machine. If the host machine has more bits in an
617 @code{int} than the target machine has in the mode in which the constant
618 will be used, then some of the bits you get from @code{INTVAL} will be
619 superfluous. For proper results, you must carefully disregard the
620 values of those bits.
622 @findex output_asm_insn
623 It is possible to output an assembler instruction and then go on to output
624 or compute more of them, using the subroutine @code{output_asm_insn}. This
625 receives two arguments: a template-string and a vector of operands. The
626 vector may be @code{operands}, or it may be another array of @code{rtx}
627 that you declare locally and initialize yourself.
629 @findex which_alternative
630 When an insn pattern has multiple alternatives in its constraints, often
631 the appearance of the assembler code is determined mostly by which alternative
632 was matched. When this is so, the C code can test the variable
633 @code{which_alternative}, which is the ordinal number of the alternative
634 that was actually satisfied (0 for the first, 1 for the second alternative,
637 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
638 for registers and @samp{clrmem} for memory locations. Here is how
639 a pattern could use @code{which_alternative} to choose between them:
643 [(set (match_operand:SI 0 "general_operand" "=r,m")
647 return (which_alternative == 0
648 ? "clrreg %0" : "clrmem %0");
652 The example above, where the assembler code to generate was
653 @emph{solely} determined by the alternative, could also have been specified
654 as follows, having the output control string start with a @samp{@@}:
659 [(set (match_operand:SI 0 "general_operand" "=r,m")
671 @cindex operand predicates
672 @cindex operator predicates
674 A predicate determines whether a @code{match_operand} or
675 @code{match_operator} expression matches, and therefore whether the
676 surrounding instruction pattern will be used for that combination of
677 operands. GCC has a number of machine-independent predicates, and you
678 can define machine-specific predicates as needed. By convention,
679 predicates used with @code{match_operand} have names that end in
680 @samp{_operand}, and those used with @code{match_operator} have names
681 that end in @samp{_operator}.
683 All predicates are Boolean functions (in the mathematical sense) of
684 two arguments: the RTL expression that is being considered at that
685 position in the instruction pattern, and the machine mode that the
686 @code{match_operand} or @code{match_operator} specifies. In this
687 section, the first argument is called @var{op} and the second argument
688 @var{mode}. Predicates can be called from C as ordinary two-argument
689 functions; this can be useful in output templates or other
690 machine-specific code.
692 Operand predicates can allow operands that are not actually acceptable
693 to the hardware, as long as the constraints give reload the ability to
694 fix them up (@pxref{Constraints}). However, GCC will usually generate
695 better code if the predicates specify the requirements of the machine
696 instructions as closely as possible. Reload cannot fix up operands
697 that must be constants (``immediate operands''); you must use a
698 predicate that allows only constants, or else enforce the requirement
699 in the extra condition.
701 @cindex predicates and machine modes
702 @cindex normal predicates
703 @cindex special predicates
704 Most predicates handle their @var{mode} argument in a uniform manner.
705 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
706 any mode. If @var{mode} is anything else, then @var{op} must have the
707 same mode, unless @var{op} is a @code{CONST_INT} or integer
708 @code{CONST_DOUBLE}. These RTL expressions always have
709 @code{VOIDmode}, so it would be counterproductive to check that their
710 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
711 integer @code{CONST_DOUBLE} check that the value stored in the
712 constant will fit in the requested mode.
714 Predicates with this behavior are called @dfn{normal}.
715 @command{genrecog} can optimize the instruction recognizer based on
716 knowledge of how normal predicates treat modes. It can also diagnose
717 certain kinds of common errors in the use of normal predicates; for
718 instance, it is almost always an error to use a normal predicate
719 without specifying a mode.
721 Predicates that do something different with their @var{mode} argument
722 are called @dfn{special}. The generic predicates
723 @code{address_operand} and @code{pmode_register_operand} are special
724 predicates. @command{genrecog} does not do any optimizations or
725 diagnosis when special predicates are used.
728 * Machine-Independent Predicates:: Predicates available to all back ends.
729 * Defining Predicates:: How to write machine-specific predicate
733 @node Machine-Independent Predicates
734 @subsection Machine-Independent Predicates
735 @cindex machine-independent predicates
736 @cindex generic predicates
738 These are the generic predicates available to all back ends. They are
739 defined in @file{recog.c}. The first category of predicates allow
740 only constant, or @dfn{immediate}, operands.
742 @defun immediate_operand
743 This predicate allows any sort of constant that fits in @var{mode}.
744 It is an appropriate choice for instructions that take operands that
748 @defun const_int_operand
749 This predicate allows any @code{CONST_INT} expression that fits in
750 @var{mode}. It is an appropriate choice for an immediate operand that
751 does not allow a symbol or label.
754 @defun const_double_operand
755 This predicate accepts any @code{CONST_DOUBLE} expression that has
756 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
757 accept @code{CONST_INT}. It is intended for immediate floating point
762 The second category of predicates allow only some kind of machine
765 @defun register_operand
766 This predicate allows any @code{REG} or @code{SUBREG} expression that
767 is valid for @var{mode}. It is often suitable for arithmetic
768 instruction operands on a RISC machine.
771 @defun pmode_register_operand
772 This is a slight variant on @code{register_operand} which works around
773 a limitation in the machine-description reader.
776 (match_operand @var{n} "pmode_register_operand" @var{constraint})
783 (match_operand:P @var{n} "register_operand" @var{constraint})
787 would mean, if the machine-description reader accepted @samp{:P}
788 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
789 alias for some other mode, and might vary with machine-specific
790 options. @xref{Misc}.
793 @defun scratch_operand
794 This predicate allows hard registers and @code{SCRATCH} expressions,
795 but not pseudo-registers. It is used internally by @code{match_scratch};
796 it should not be used directly.
800 The third category of predicates allow only some kind of memory reference.
802 @defun memory_operand
803 This predicate allows any valid reference to a quantity of mode
804 @var{mode} in memory, as determined by the weak form of
805 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
808 @defun address_operand
809 This predicate is a little unusual; it allows any operand that is a
810 valid expression for the @emph{address} of a quantity of mode
811 @var{mode}, again determined by the weak form of
812 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
813 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
814 @code{memory_operand}, then @var{exp} is acceptable to
815 @code{address_operand}. Note that @var{exp} does not necessarily have
819 @defun indirect_operand
820 This is a stricter form of @code{memory_operand} which allows only
821 memory references with a @code{general_operand} as the address
822 expression. New uses of this predicate are discouraged, because
823 @code{general_operand} is very permissive, so it's hard to tell what
824 an @code{indirect_operand} does or does not allow. If a target has
825 different requirements for memory operands for different instructions,
826 it is better to define target-specific predicates which enforce the
827 hardware's requirements explicitly.
831 This predicate allows a memory reference suitable for pushing a value
832 onto the stack. This will be a @code{MEM} which refers to
833 @code{stack_pointer_rtx}, with a side-effect in its address expression
834 (@pxref{Incdec}); which one is determined by the
835 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
839 This predicate allows a memory reference suitable for popping a value
840 off the stack. Again, this will be a @code{MEM} referring to
841 @code{stack_pointer_rtx}, with a side-effect in its address
842 expression. However, this time @code{STACK_POP_CODE} is expected.
846 The fourth category of predicates allow some combination of the above
849 @defun nonmemory_operand
850 This predicate allows any immediate or register operand valid for @var{mode}.
853 @defun nonimmediate_operand
854 This predicate allows any register or memory operand valid for @var{mode}.
857 @defun general_operand
858 This predicate allows any immediate, register, or memory operand
859 valid for @var{mode}.
863 Finally, there are two generic operator predicates.
865 @defun comparison_operator
866 This predicate matches any expression which performs an arithmetic
867 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
871 @defun ordered_comparison_operator
872 This predicate matches any expression which performs an arithmetic
873 comparison in @var{mode} and whose expression code is valid for integer
874 modes; that is, the expression code will be one of @code{eq}, @code{ne},
875 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
876 @code{ge}, @code{geu}.
879 @node Defining Predicates
880 @subsection Defining Machine-Specific Predicates
881 @cindex defining predicates
882 @findex define_predicate
883 @findex define_special_predicate
885 Many machines have requirements for their operands that cannot be
886 expressed precisely using the generic predicates. You can define
887 additional predicates using @code{define_predicate} and
888 @code{define_special_predicate} expressions. These expressions have
893 The name of the predicate, as it will be referred to in
894 @code{match_operand} or @code{match_operator} expressions.
897 An RTL expression which evaluates to true if the predicate allows the
898 operand @var{op}, false if it does not. This expression can only use
899 the following RTL codes:
903 When written inside a predicate expression, a @code{MATCH_OPERAND}
904 expression evaluates to true if the predicate it names would allow
905 @var{op}. The operand number and constraint are ignored. Due to
906 limitations in @command{genrecog}, you can only refer to generic
907 predicates and predicates that have already been defined.
910 This expression evaluates to true if @var{op} or a specified
911 subexpression of @var{op} has one of a given list of RTX codes.
913 The first operand of this expression is a string constant containing a
914 comma-separated list of RTX code names (in lower case). These are the
915 codes for which the @code{MATCH_CODE} will be true.
917 The second operand is a string constant which indicates what
918 subexpression of @var{op} to examine. If it is absent or the empty
919 string, @var{op} itself is examined. Otherwise, the string constant
920 must be a sequence of digits and/or lowercase letters. Each character
921 indicates a subexpression to extract from the current expression; for
922 the first character this is @var{op}, for the second and subsequent
923 characters it is the result of the previous character. A digit
924 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
925 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
926 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
927 @code{MATCH_CODE} then examines the RTX code of the subexpression
928 extracted by the complete string. It is not possible to extract
929 components of an @code{rtvec} that is not at position 0 within its RTX
933 This expression has one operand, a string constant containing a C
934 expression. The predicate's arguments, @var{op} and @var{mode}, are
935 available with those names in the C expression. The @code{MATCH_TEST}
936 evaluates to true if the C expression evaluates to a nonzero value.
937 @code{MATCH_TEST} expressions must not have side effects.
943 The basic @samp{MATCH_} expressions can be combined using these
944 logical operators, which have the semantics of the C operators
945 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
946 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
947 arbitrary number of arguments; this has exactly the same effect as
948 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
952 An optional block of C code, which should execute
953 @samp{@w{return true}} if the predicate is found to match and
954 @samp{@w{return false}} if it does not. It must not have any side
955 effects. The predicate arguments, @var{op} and @var{mode}, are
956 available with those names.
958 If a code block is present in a predicate definition, then the RTL
959 expression must evaluate to true @emph{and} the code block must
960 execute @samp{@w{return true}} for the predicate to allow the operand.
961 The RTL expression is evaluated first; do not re-check anything in the
962 code block that was checked in the RTL expression.
965 The program @command{genrecog} scans @code{define_predicate} and
966 @code{define_special_predicate} expressions to determine which RTX
967 codes are possibly allowed. You should always make this explicit in
968 the RTL predicate expression, using @code{MATCH_OPERAND} and
971 Here is an example of a simple predicate definition, from the IA64
976 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
977 (define_predicate "small_addr_symbolic_operand"
978 (and (match_code "symbol_ref")
979 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
984 And here is another, showing the use of the C block.
988 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
989 (define_predicate "gr_register_operand"
990 (match_operand 0 "register_operand")
993 if (GET_CODE (op) == SUBREG)
994 op = SUBREG_REG (op);
997 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1002 Predicates written with @code{define_predicate} automatically include
1003 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1004 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1005 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1006 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1007 kind of constant fits in the requested mode. This is because
1008 target-specific predicates that take constants usually have to do more
1009 stringent value checks anyway. If you need the exact same treatment
1010 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1011 provide, use a @code{MATCH_OPERAND} subexpression to call
1012 @code{const_int_operand}, @code{const_double_operand}, or
1013 @code{immediate_operand}.
1015 Predicates written with @code{define_special_predicate} do not get any
1016 automatic mode checks, and are treated as having special mode handling
1017 by @command{genrecog}.
1019 The program @command{genpreds} is responsible for generating code to
1020 test predicates. It also writes a header file containing function
1021 declarations for all machine-specific predicates. It is not necessary
1022 to declare these predicates in @file{@var{cpu}-protos.h}.
1025 @c Most of this node appears by itself (in a different place) even
1026 @c when the INTERNALS flag is clear. Passages that require the internals
1027 @c manual's context are conditionalized to appear only in the internals manual.
1030 @section Operand Constraints
1031 @cindex operand constraints
1034 Each @code{match_operand} in an instruction pattern can specify
1035 constraints for the operands allowed. The constraints allow you to
1036 fine-tune matching within the set of operands allowed by the
1042 @section Constraints for @code{asm} Operands
1043 @cindex operand constraints, @code{asm}
1044 @cindex constraints, @code{asm}
1045 @cindex @code{asm} constraints
1047 Here are specific details on what constraint letters you can use with
1048 @code{asm} operands.
1050 Constraints can say whether
1051 an operand may be in a register, and which kinds of register; whether the
1052 operand can be a memory reference, and which kinds of address; whether the
1053 operand may be an immediate constant, and which possible values it may
1054 have. Constraints can also require two operands to match.
1055 Side-effects aren't allowed in operands of inline @code{asm}, unless
1056 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1057 that the side-effects will happen exactly once in an instruction that can update
1058 the addressing register.
1062 * Simple Constraints:: Basic use of constraints.
1063 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1064 * Class Preferences:: Constraints guide which hard register to put things in.
1065 * Modifiers:: More precise control over effects of constraints.
1066 * Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute.
1067 * Machine Constraints:: Existing constraints for some particular machines.
1068 * Define Constraints:: How to define machine-specific constraints.
1069 * C Constraint Interface:: How to test constraints from C code.
1075 * Simple Constraints:: Basic use of constraints.
1076 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1077 * Modifiers:: More precise control over effects of constraints.
1078 * Machine Constraints:: Special constraints for some particular machines.
1082 @node Simple Constraints
1083 @subsection Simple Constraints
1084 @cindex simple constraints
1086 The simplest kind of constraint is a string full of letters, each of
1087 which describes one kind of operand that is permitted. Here are
1088 the letters that are allowed:
1092 Whitespace characters are ignored and can be inserted at any position
1093 except the first. This enables each alternative for different operands to
1094 be visually aligned in the machine description even if they have different
1095 number of constraints and modifiers.
1097 @cindex @samp{m} in constraint
1098 @cindex memory references in constraints
1100 A memory operand is allowed, with any kind of address that the machine
1101 supports in general.
1102 Note that the letter used for the general memory constraint can be
1103 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1105 @cindex offsettable address
1106 @cindex @samp{o} in constraint
1108 A memory operand is allowed, but only if the address is
1109 @dfn{offsettable}. This means that adding a small integer (actually,
1110 the width in bytes of the operand, as determined by its machine mode)
1111 may be added to the address and the result is also a valid memory
1114 @cindex autoincrement/decrement addressing
1115 For example, an address which is constant is offsettable; so is an
1116 address that is the sum of a register and a constant (as long as a
1117 slightly larger constant is also within the range of address-offsets
1118 supported by the machine); but an autoincrement or autodecrement
1119 address is not offsettable. More complicated indirect/indexed
1120 addresses may or may not be offsettable depending on the other
1121 addressing modes that the machine supports.
1123 Note that in an output operand which can be matched by another
1124 operand, the constraint letter @samp{o} is valid only when accompanied
1125 by both @samp{<} (if the target machine has predecrement addressing)
1126 and @samp{>} (if the target machine has preincrement addressing).
1128 @cindex @samp{V} in constraint
1130 A memory operand that is not offsettable. In other words, anything that
1131 would fit the @samp{m} constraint but not the @samp{o} constraint.
1133 @cindex @samp{<} in constraint
1135 A memory operand with autodecrement addressing (either predecrement or
1136 postdecrement) is allowed. In inline @code{asm} this constraint is only
1137 allowed if the operand is used exactly once in an instruction that can
1138 handle the side-effects. Not using an operand with @samp{<} in constraint
1139 string in the inline @code{asm} pattern at all or using it in multiple
1140 instructions isn't valid, because the side-effects wouldn't be performed
1141 or would be performed more than once. Furthermore, on some targets
1142 the operand with @samp{<} in constraint string must be accompanied by
1143 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1144 or @code{%P0} on IA-64.
1146 @cindex @samp{>} in constraint
1148 A memory operand with autoincrement addressing (either preincrement or
1149 postincrement) is allowed. In inline @code{asm} the same restrictions
1150 as for @samp{<} apply.
1152 @cindex @samp{r} in constraint
1153 @cindex registers in constraints
1155 A register operand is allowed provided that it is in a general
1158 @cindex constants in constraints
1159 @cindex @samp{i} in constraint
1161 An immediate integer operand (one with constant value) is allowed.
1162 This includes symbolic constants whose values will be known only at
1163 assembly time or later.
1165 @cindex @samp{n} in constraint
1167 An immediate integer operand with a known numeric value is allowed.
1168 Many systems cannot support assembly-time constants for operands less
1169 than a word wide. Constraints for these operands should use @samp{n}
1170 rather than @samp{i}.
1172 @cindex @samp{I} in constraint
1173 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1174 Other letters in the range @samp{I} through @samp{P} may be defined in
1175 a machine-dependent fashion to permit immediate integer operands with
1176 explicit integer values in specified ranges. For example, on the
1177 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1178 This is the range permitted as a shift count in the shift
1181 @cindex @samp{E} in constraint
1183 An immediate floating operand (expression code @code{const_double}) is
1184 allowed, but only if the target floating point format is the same as
1185 that of the host machine (on which the compiler is running).
1187 @cindex @samp{F} in constraint
1189 An immediate floating operand (expression code @code{const_double} or
1190 @code{const_vector}) is allowed.
1192 @cindex @samp{G} in constraint
1193 @cindex @samp{H} in constraint
1194 @item @samp{G}, @samp{H}
1195 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1196 permit immediate floating operands in particular ranges of values.
1198 @cindex @samp{s} in constraint
1200 An immediate integer operand whose value is not an explicit integer is
1203 This might appear strange; if an insn allows a constant operand with a
1204 value not known at compile time, it certainly must allow any known
1205 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1206 better code to be generated.
1208 For example, on the 68000 in a fullword instruction it is possible to
1209 use an immediate operand; but if the immediate value is between @minus{}128
1210 and 127, better code results from loading the value into a register and
1211 using the register. This is because the load into the register can be
1212 done with a @samp{moveq} instruction. We arrange for this to happen
1213 by defining the letter @samp{K} to mean ``any integer outside the
1214 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1217 @cindex @samp{g} in constraint
1219 Any register, memory or immediate integer operand is allowed, except for
1220 registers that are not general registers.
1222 @cindex @samp{X} in constraint
1225 Any operand whatsoever is allowed, even if it does not satisfy
1226 @code{general_operand}. This is normally used in the constraint of
1227 a @code{match_scratch} when certain alternatives will not actually
1228 require a scratch register.
1231 Any operand whatsoever is allowed.
1234 @cindex @samp{0} in constraint
1235 @cindex digits in constraint
1236 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1237 An operand that matches the specified operand number is allowed. If a
1238 digit is used together with letters within the same alternative, the
1239 digit should come last.
1241 This number is allowed to be more than a single digit. If multiple
1242 digits are encountered consecutively, they are interpreted as a single
1243 decimal integer. There is scant chance for ambiguity, since to-date
1244 it has never been desirable that @samp{10} be interpreted as matching
1245 either operand 1 @emph{or} operand 0. Should this be desired, one
1246 can use multiple alternatives instead.
1248 @cindex matching constraint
1249 @cindex constraint, matching
1250 This is called a @dfn{matching constraint} and what it really means is
1251 that the assembler has only a single operand that fills two roles
1253 considered separate in the RTL insn. For example, an add insn has two
1254 input operands and one output operand in the RTL, but on most CISC
1257 which @code{asm} distinguishes. For example, an add instruction uses
1258 two input operands and an output operand, but on most CISC
1260 machines an add instruction really has only two operands, one of them an
1261 input-output operand:
1267 Matching constraints are used in these circumstances.
1268 More precisely, the two operands that match must include one input-only
1269 operand and one output-only operand. Moreover, the digit must be a
1270 smaller number than the number of the operand that uses it in the
1274 For operands to match in a particular case usually means that they
1275 are identical-looking RTL expressions. But in a few special cases
1276 specific kinds of dissimilarity are allowed. For example, @code{*x}
1277 as an input operand will match @code{*x++} as an output operand.
1278 For proper results in such cases, the output template should always
1279 use the output-operand's number when printing the operand.
1282 @cindex load address instruction
1283 @cindex push address instruction
1284 @cindex address constraints
1285 @cindex @samp{p} in constraint
1287 An operand that is a valid memory address is allowed. This is
1288 for ``load address'' and ``push address'' instructions.
1290 @findex address_operand
1291 @samp{p} in the constraint must be accompanied by @code{address_operand}
1292 as the predicate in the @code{match_operand}. This predicate interprets
1293 the mode specified in the @code{match_operand} as the mode of the memory
1294 reference for which the address would be valid.
1296 @cindex other register constraints
1297 @cindex extensible constraints
1298 @item @var{other-letters}
1299 Other letters can be defined in machine-dependent fashion to stand for
1300 particular classes of registers or other arbitrary operand types.
1301 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1302 for data, address and floating point registers.
1306 In order to have valid assembler code, each operand must satisfy
1307 its constraint. But a failure to do so does not prevent the pattern
1308 from applying to an insn. Instead, it directs the compiler to modify
1309 the code so that the constraint will be satisfied. Usually this is
1310 done by copying an operand into a register.
1312 Contrast, therefore, the two instruction patterns that follow:
1316 [(set (match_operand:SI 0 "general_operand" "=r")
1317 (plus:SI (match_dup 0)
1318 (match_operand:SI 1 "general_operand" "r")))]
1324 which has two operands, one of which must appear in two places, and
1328 [(set (match_operand:SI 0 "general_operand" "=r")
1329 (plus:SI (match_operand:SI 1 "general_operand" "0")
1330 (match_operand:SI 2 "general_operand" "r")))]
1336 which has three operands, two of which are required by a constraint to be
1337 identical. If we are considering an insn of the form
1340 (insn @var{n} @var{prev} @var{next}
1342 (plus:SI (reg:SI 6) (reg:SI 109)))
1347 the first pattern would not apply at all, because this insn does not
1348 contain two identical subexpressions in the right place. The pattern would
1349 say, ``That does not look like an add instruction; try other patterns''.
1350 The second pattern would say, ``Yes, that's an add instruction, but there
1351 is something wrong with it''. It would direct the reload pass of the
1352 compiler to generate additional insns to make the constraint true. The
1353 results might look like this:
1356 (insn @var{n2} @var{prev} @var{n}
1357 (set (reg:SI 3) (reg:SI 6))
1360 (insn @var{n} @var{n2} @var{next}
1362 (plus:SI (reg:SI 3) (reg:SI 109)))
1366 It is up to you to make sure that each operand, in each pattern, has
1367 constraints that can handle any RTL expression that could be present for
1368 that operand. (When multiple alternatives are in use, each pattern must,
1369 for each possible combination of operand expressions, have at least one
1370 alternative which can handle that combination of operands.) The
1371 constraints don't need to @emph{allow} any possible operand---when this is
1372 the case, they do not constrain---but they must at least point the way to
1373 reloading any possible operand so that it will fit.
1377 If the constraint accepts whatever operands the predicate permits,
1378 there is no problem: reloading is never necessary for this operand.
1380 For example, an operand whose constraints permit everything except
1381 registers is safe provided its predicate rejects registers.
1383 An operand whose predicate accepts only constant values is safe
1384 provided its constraints include the letter @samp{i}. If any possible
1385 constant value is accepted, then nothing less than @samp{i} will do;
1386 if the predicate is more selective, then the constraints may also be
1390 Any operand expression can be reloaded by copying it into a register.
1391 So if an operand's constraints allow some kind of register, it is
1392 certain to be safe. It need not permit all classes of registers; the
1393 compiler knows how to copy a register into another register of the
1394 proper class in order to make an instruction valid.
1396 @cindex nonoffsettable memory reference
1397 @cindex memory reference, nonoffsettable
1399 A nonoffsettable memory reference can be reloaded by copying the
1400 address into a register. So if the constraint uses the letter
1401 @samp{o}, all memory references are taken care of.
1404 A constant operand can be reloaded by allocating space in memory to
1405 hold it as preinitialized data. Then the memory reference can be used
1406 in place of the constant. So if the constraint uses the letters
1407 @samp{o} or @samp{m}, constant operands are not a problem.
1410 If the constraint permits a constant and a pseudo register used in an insn
1411 was not allocated to a hard register and is equivalent to a constant,
1412 the register will be replaced with the constant. If the predicate does
1413 not permit a constant and the insn is re-recognized for some reason, the
1414 compiler will crash. Thus the predicate must always recognize any
1415 objects allowed by the constraint.
1418 If the operand's predicate can recognize registers, but the constraint does
1419 not permit them, it can make the compiler crash. When this operand happens
1420 to be a register, the reload pass will be stymied, because it does not know
1421 how to copy a register temporarily into memory.
1423 If the predicate accepts a unary operator, the constraint applies to the
1424 operand. For example, the MIPS processor at ISA level 3 supports an
1425 instruction which adds two registers in @code{SImode} to produce a
1426 @code{DImode} result, but only if the registers are correctly sign
1427 extended. This predicate for the input operands accepts a
1428 @code{sign_extend} of an @code{SImode} register. Write the constraint
1429 to indicate the type of register that is required for the operand of the
1433 @node Multi-Alternative
1434 @subsection Multiple Alternative Constraints
1435 @cindex multiple alternative constraints
1437 Sometimes a single instruction has multiple alternative sets of possible
1438 operands. For example, on the 68000, a logical-or instruction can combine
1439 register or an immediate value into memory, or it can combine any kind of
1440 operand into a register; but it cannot combine one memory location into
1443 These constraints are represented as multiple alternatives. An alternative
1444 can be described by a series of letters for each operand. The overall
1445 constraint for an operand is made from the letters for this operand
1446 from the first alternative, a comma, the letters for this operand from
1447 the second alternative, a comma, and so on until the last alternative.
1449 Here is how it is done for fullword logical-or on the 68000:
1452 (define_insn "iorsi3"
1453 [(set (match_operand:SI 0 "general_operand" "=m,d")
1454 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1455 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1459 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1460 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1461 2. The second alternative has @samp{d} (data register) for operand 0,
1462 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1463 @samp{%} in the constraints apply to all the alternatives; their
1464 meaning is explained in the next section (@pxref{Class Preferences}).
1467 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1468 If all the operands fit any one alternative, the instruction is valid.
1469 Otherwise, for each alternative, the compiler counts how many instructions
1470 must be added to copy the operands so that that alternative applies.
1471 The alternative requiring the least copying is chosen. If two alternatives
1472 need the same amount of copying, the one that comes first is chosen.
1473 These choices can be altered with the @samp{?} and @samp{!} characters:
1476 @cindex @samp{?} in constraint
1477 @cindex question mark
1479 Disparage slightly the alternative that the @samp{?} appears in,
1480 as a choice when no alternative applies exactly. The compiler regards
1481 this alternative as one unit more costly for each @samp{?} that appears
1484 @cindex @samp{!} in constraint
1485 @cindex exclamation point
1487 Disparage severely the alternative that the @samp{!} appears in.
1488 This alternative can still be used if it fits without reloading,
1489 but if reloading is needed, some other alternative will be used.
1493 When an insn pattern has multiple alternatives in its constraints, often
1494 the appearance of the assembler code is determined mostly by which
1495 alternative was matched. When this is so, the C code for writing the
1496 assembler code can use the variable @code{which_alternative}, which is
1497 the ordinal number of the alternative that was actually satisfied (0 for
1498 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1502 @node Class Preferences
1503 @subsection Register Class Preferences
1504 @cindex class preference constraints
1505 @cindex register class preference constraints
1507 @cindex voting between constraint alternatives
1508 The operand constraints have another function: they enable the compiler
1509 to decide which kind of hardware register a pseudo register is best
1510 allocated to. The compiler examines the constraints that apply to the
1511 insns that use the pseudo register, looking for the machine-dependent
1512 letters such as @samp{d} and @samp{a} that specify classes of registers.
1513 The pseudo register is put in whichever class gets the most ``votes''.
1514 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1515 favor of a general register. The machine description says which registers
1516 are considered general.
1518 Of course, on some machines all registers are equivalent, and no register
1519 classes are defined. Then none of this complexity is relevant.
1523 @subsection Constraint Modifier Characters
1524 @cindex modifiers in constraints
1525 @cindex constraint modifier characters
1527 @c prevent bad page break with this line
1528 Here are constraint modifier characters.
1531 @cindex @samp{=} in constraint
1533 Means that this operand is write-only for this instruction: the previous
1534 value is discarded and replaced by output data.
1536 @cindex @samp{+} in constraint
1538 Means that this operand is both read and written by the instruction.
1540 When the compiler fixes up the operands to satisfy the constraints,
1541 it needs to know which operands are inputs to the instruction and
1542 which are outputs from it. @samp{=} identifies an output; @samp{+}
1543 identifies an operand that is both input and output; all other operands
1544 are assumed to be input only.
1546 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1547 first character of the constraint string.
1549 @cindex @samp{&} in constraint
1550 @cindex earlyclobber operand
1552 Means (in a particular alternative) that this operand is an
1553 @dfn{earlyclobber} operand, which is modified before the instruction is
1554 finished using the input operands. Therefore, this operand may not lie
1555 in a register that is used as an input operand or as part of any memory
1558 @samp{&} applies only to the alternative in which it is written. In
1559 constraints with multiple alternatives, sometimes one alternative
1560 requires @samp{&} while others do not. See, for example, the
1561 @samp{movdf} insn of the 68000.
1563 An input operand can be tied to an earlyclobber operand if its only
1564 use as an input occurs before the early result is written. Adding
1565 alternatives of this form often allows GCC to produce better code
1566 when only some of the inputs can be affected by the earlyclobber.
1567 See, for example, the @samp{mulsi3} insn of the ARM@.
1569 @samp{&} does not obviate the need to write @samp{=}.
1571 @cindex @samp{%} in constraint
1573 Declares the instruction to be commutative for this operand and the
1574 following operand. This means that the compiler may interchange the
1575 two operands if that is the cheapest way to make all operands fit the
1578 This is often used in patterns for addition instructions
1579 that really have only two operands: the result must go in one of the
1580 arguments. Here for example, is how the 68000 halfword-add
1581 instruction is defined:
1584 (define_insn "addhi3"
1585 [(set (match_operand:HI 0 "general_operand" "=m,r")
1586 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1587 (match_operand:HI 2 "general_operand" "di,g")))]
1591 GCC can only handle one commutative pair in an asm; if you use more,
1592 the compiler may fail. Note that you need not use the modifier if
1593 the two alternatives are strictly identical; this would only waste
1594 time in the reload pass. The modifier is not operational after
1595 register allocation, so the result of @code{define_peephole2}
1596 and @code{define_split}s performed after reload cannot rely on
1597 @samp{%} to make the intended insn match.
1599 @cindex @samp{#} in constraint
1601 Says that all following characters, up to the next comma, are to be
1602 ignored as a constraint. They are significant only for choosing
1603 register preferences.
1605 @cindex @samp{*} in constraint
1607 Says that the following character should be ignored when choosing
1608 register preferences. @samp{*} has no effect on the meaning of the
1609 constraint as a constraint, and no effect on reloading.
1612 Here is an example: the 68000 has an instruction to sign-extend a
1613 halfword in a data register, and can also sign-extend a value by
1614 copying it into an address register. While either kind of register is
1615 acceptable, the constraints on an address-register destination are
1616 less strict, so it is best if register allocation makes an address
1617 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1618 constraint letter (for data register) is ignored when computing
1619 register preferences.
1622 (define_insn "extendhisi2"
1623 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1625 (match_operand:HI 1 "general_operand" "0,g")))]
1631 @node Machine Constraints
1632 @subsection Constraints for Particular Machines
1633 @cindex machine specific constraints
1634 @cindex constraints, machine specific
1636 Whenever possible, you should use the general-purpose constraint letters
1637 in @code{asm} arguments, since they will convey meaning more readily to
1638 people reading your code. Failing that, use the constraint letters
1639 that usually have very similar meanings across architectures. The most
1640 commonly used constraints are @samp{m} and @samp{r} (for memory and
1641 general-purpose registers respectively; @pxref{Simple Constraints}), and
1642 @samp{I}, usually the letter indicating the most common
1643 immediate-constant format.
1645 Each architecture defines additional constraints. These constraints
1646 are used by the compiler itself for instruction generation, as well as
1647 for @code{asm} statements; therefore, some of the constraints are not
1648 particularly useful for @code{asm}. Here is a summary of some of the
1649 machine-dependent constraints available on some particular machines;
1650 it includes both constraints that are useful for @code{asm} and
1651 constraints that aren't. The compiler source file mentioned in the
1652 table heading for each architecture is the definitive reference for
1653 the meanings of that architecture's constraints.
1656 @item ARM family---@file{config/arm/arm.h}
1659 Floating-point register
1662 VFP floating-point register
1665 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1669 Floating-point constant that would satisfy the constraint @samp{F} if it
1673 Integer that is valid as an immediate operand in a data processing
1674 instruction. That is, an integer in the range 0 to 255 rotated by a
1678 Integer in the range @minus{}4095 to 4095
1681 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1684 Integer that satisfies constraint @samp{I} when negated (twos complement)
1687 Integer in the range 0 to 32
1690 A memory reference where the exact address is in a single register
1691 (`@samp{m}' is preferable for @code{asm} statements)
1694 An item in the constant pool
1697 A symbol in the text segment of the current file
1700 A memory reference suitable for VFP load/store insns (reg+constant offset)
1703 A memory reference suitable for iWMMXt load/store instructions.
1706 A memory reference suitable for the ARMv4 ldrsb instruction.
1709 @item AVR family---@file{config/avr/constraints.md}
1712 Registers from r0 to r15
1715 Registers from r16 to r23
1718 Registers from r16 to r31
1721 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1724 Pointer register (r26--r31)
1727 Base pointer register (r28--r31)
1730 Stack pointer register (SPH:SPL)
1733 Temporary register r0
1736 Register pair X (r27:r26)
1739 Register pair Y (r29:r28)
1742 Register pair Z (r31:r30)
1745 Constant greater than @minus{}1, less than 64
1748 Constant greater than @minus{}64, less than 1
1757 Constant that fits in 8 bits
1760 Constant integer @minus{}1
1763 Constant integer 8, 16, or 24
1769 A floating point constant 0.0
1772 Integer constant in the range @minus{}6 @dots{} 5.
1775 A memory address based on Y or Z pointer with displacement.
1778 @item CRX Architecture---@file{config/crx/crx.h}
1782 Registers from r0 to r14 (registers without stack pointer)
1785 Register r16 (64-bit accumulator lo register)
1788 Register r17 (64-bit accumulator hi register)
1791 Register pair r16-r17. (64-bit accumulator lo-hi pair)
1794 Constant that fits in 3 bits
1797 Constant that fits in 4 bits
1800 Constant that fits in 5 bits
1803 Constant that is one of @minus{}1, 4, @minus{}4, 7, 8, 12, 16, 20, 32, 48
1806 Floating point constant that is legal for store immediate
1809 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
1815 Floating point register
1818 Shift amount register
1821 Floating point register (deprecated)
1824 Upper floating point register (32-bit), floating point register (64-bit)
1830 Signed 11-bit integer constant
1833 Signed 14-bit integer constant
1836 Integer constant that can be deposited with a @code{zdepi} instruction
1839 Signed 5-bit integer constant
1845 Integer constant that can be loaded with a @code{ldil} instruction
1848 Integer constant whose value plus one is a power of 2
1851 Integer constant that can be used for @code{and} operations in @code{depi}
1852 and @code{extru} instructions
1861 Floating-point constant 0.0
1864 A @code{lo_sum} data-linkage-table memory operand
1867 A memory operand that can be used as the destination operand of an
1868 integer store instruction
1871 A scaled or unscaled indexed memory operand
1874 A memory operand for floating-point loads and stores
1877 A register indirect memory operand
1880 @item picoChip family---@file{picochip.h}
1886 Pointer register. A register which can be used to access memory without
1887 supplying an offset. Any other register can be used to access memory,
1888 but will need a constant offset. In the case of the offset being zero,
1889 it is more efficient to use a pointer register, since this reduces code
1893 A twin register. A register which may be paired with an adjacent
1894 register to create a 32-bit register.
1897 Any absolute memory address (e.g., symbolic constant, symbolic
1901 4-bit signed integer.
1904 4-bit unsigned integer.
1907 8-bit signed integer.
1910 Any constant whose absolute value is no greater than 4-bits.
1913 10-bit signed integer
1916 16-bit signed integer.
1920 @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
1923 Address base register
1926 Floating point register (containing 64-bit value)
1929 Floating point register (containing 32-bit value)
1932 Altivec vector register
1935 VSX vector register to hold vector double data
1938 VSX vector register to hold vector float data
1941 VSX vector register to hold scalar float data
1947 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1956 @samp{LINK} register
1959 @samp{CR} register (condition register) number 0
1962 @samp{CR} register (condition register)
1965 @samp{XER[CA]} carry bit (part of the XER register)
1968 Signed 16-bit constant
1971 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1972 @code{SImode} constants)
1975 Unsigned 16-bit constant
1978 Signed 16-bit constant shifted left 16 bits
1981 Constant larger than 31
1990 Constant whose negation is a signed 16-bit constant
1993 Floating point constant that can be loaded into a register with one
1994 instruction per word
1997 Integer/Floating point constant that can be loaded into a register using
2002 Normally, @code{m} does not allow addresses that update the base register.
2003 If @samp{<} or @samp{>} constraint is also used, they are allowed and
2004 therefore on PowerPC targets in that case it is only safe
2005 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
2006 accesses the operand exactly once. The @code{asm} statement must also
2007 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
2008 corresponding load or store instruction. For example:
2011 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
2017 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
2023 A ``stable'' memory operand; that is, one which does not include any
2024 automodification of the base register. This used to be useful when
2025 @samp{m} allowed automodification of the base register, but as those are now only
2026 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
2027 as @samp{m} without @samp{<} and @samp{>}.
2030 Memory operand that is an offset from a register (it is usually better
2031 to use @samp{m} or @samp{es} in @code{asm} statements)
2034 Memory operand that is an indexed or indirect from a register (it is
2035 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
2041 Address operand that is an indexed or indirect from a register (@samp{p} is
2042 preferable for @code{asm} statements)
2045 Constant suitable as a 64-bit mask operand
2048 Constant suitable as a 32-bit mask operand
2051 System V Release 4 small data area reference
2054 AND masks that can be performed by two rldic@{l, r@} instructions
2057 Vector constant that does not require memory
2060 Vector constant that is all zeros.
2064 @item Intel 386---@file{config/i386/constraints.md}
2067 Legacy register---the eight integer registers available on all
2068 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
2069 @code{si}, @code{di}, @code{bp}, @code{sp}).
2072 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
2073 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
2076 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
2077 @code{c}, and @code{d}.
2081 Any register that can be used as the index in a base+index memory
2082 access: that is, any general register except the stack pointer.
2086 The @code{a} register.
2089 The @code{b} register.
2092 The @code{c} register.
2095 The @code{d} register.
2098 The @code{si} register.
2101 The @code{di} register.
2104 The @code{a} and @code{d} registers, as a pair (for instructions that
2105 return half the result in one and half in the other).
2108 Any 80387 floating-point (stack) register.
2111 Top of 80387 floating-point stack (@code{%st(0)}).
2114 Second from top of 80387 floating-point stack (@code{%st(1)}).
2123 First SSE register (@code{%xmm0}).
2127 Any SSE register, when SSE2 is enabled.
2130 Any SSE register, when SSE2 and inter-unit moves are enabled.
2133 Any MMX register, when inter-unit moves are enabled.
2137 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2140 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2143 Signed 8-bit integer constant.
2146 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2149 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2152 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2157 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2161 Standard 80387 floating point constant.
2164 Standard SSE floating point constant.
2167 32-bit signed integer constant, or a symbolic reference known
2168 to fit that range (for immediate operands in sign-extending x86-64
2172 32-bit unsigned integer constant, or a symbolic reference known
2173 to fit that range (for immediate operands in zero-extending x86-64
2178 @item Intel IA-64---@file{config/ia64/ia64.h}
2181 General register @code{r0} to @code{r3} for @code{addl} instruction
2187 Predicate register (@samp{c} as in ``conditional'')
2190 Application register residing in M-unit
2193 Application register residing in I-unit
2196 Floating-point register
2199 Memory operand. If used together with @samp{<} or @samp{>},
2200 the operand can have postincrement and postdecrement which
2201 require printing with @samp{%Pn} on IA-64.
2204 Floating-point constant 0.0 or 1.0
2207 14-bit signed integer constant
2210 22-bit signed integer constant
2213 8-bit signed integer constant for logical instructions
2216 8-bit adjusted signed integer constant for compare pseudo-ops
2219 6-bit unsigned integer constant for shift counts
2222 9-bit signed integer constant for load and store postincrements
2228 0 or @minus{}1 for @code{dep} instruction
2231 Non-volatile memory for floating-point loads and stores
2234 Integer constant in the range 1 to 4 for @code{shladd} instruction
2237 Memory operand except postincrement and postdecrement. This is
2238 now roughly the same as @samp{m} when not used together with @samp{<}
2242 @item FRV---@file{config/frv/frv.h}
2245 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2248 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2251 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2252 @code{icc0} to @code{icc3}).
2255 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2258 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2259 Odd registers are excluded not in the class but through the use of a machine
2260 mode larger than 4 bytes.
2263 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2266 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2267 Odd registers are excluded not in the class but through the use of a machine
2268 mode larger than 4 bytes.
2271 Register in the class @code{LR_REG} (the @code{lr} register).
2274 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2275 Register numbers not divisible by 4 are excluded not in the class but through
2276 the use of a machine mode larger than 8 bytes.
2279 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2282 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2285 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2288 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2291 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2292 Register numbers not divisible by 4 are excluded not in the class but through
2293 the use of a machine mode larger than 8 bytes.
2296 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2299 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2302 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2305 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2308 Floating point constant zero
2311 6-bit signed integer constant
2314 10-bit signed integer constant
2317 16-bit signed integer constant
2320 16-bit unsigned integer constant
2323 12-bit signed integer constant that is negative---i.e.@: in the
2324 range of @minus{}2048 to @minus{}1
2330 12-bit signed integer constant that is greater than zero---i.e.@: in the
2335 @item Blackfin family---@file{config/bfin/constraints.md}
2344 A call clobbered P register.
2347 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2348 register. If it is @code{A}, then the register P0.
2351 Even-numbered D register
2354 Odd-numbered D register
2357 Accumulator register.
2360 Even-numbered accumulator register.
2363 Odd-numbered accumulator register.
2375 Registers used for circular buffering, i.e. I, B, or L registers.
2390 Any D, P, B, M, I or L register.
2393 Additional registers typically used only in prologues and epilogues: RETS,
2394 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2397 Any register except accumulators or CC.
2400 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2403 Unsigned 16 bit integer (in the range 0 to 65535)
2406 Signed 7 bit integer (in the range @minus{}64 to 63)
2409 Unsigned 7 bit integer (in the range 0 to 127)
2412 Unsigned 5 bit integer (in the range 0 to 31)
2415 Signed 4 bit integer (in the range @minus{}8 to 7)
2418 Signed 3 bit integer (in the range @minus{}3 to 4)
2421 Unsigned 3 bit integer (in the range 0 to 7)
2424 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2427 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2428 use with either accumulator.
2431 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2432 use only with accumulator A1.
2441 An integer constant with exactly a single bit set.
2444 An integer constant with all bits set except exactly one.
2452 @item M32C---@file{config/m32c/m32c.c}
2457 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2460 Any control register, when they're 16 bits wide (nothing if control
2461 registers are 24 bits wide)
2464 Any control register, when they're 24 bits wide.
2473 $r0 or $r2, or $r2r0 for 32 bit values.
2476 $r1 or $r3, or $r3r1 for 32 bit values.
2479 A register that can hold a 64 bit value.
2482 $r0 or $r1 (registers with addressable high/low bytes)
2491 Address registers when they're 16 bits wide.
2494 Address registers when they're 24 bits wide.
2497 Registers that can hold QI values.
2500 Registers that can be used with displacements ($a0, $a1, $sb).
2503 Registers that can hold 32 bit values.
2506 Registers that can hold 16 bit values.
2509 Registers chat can hold 16 bit values, including all control
2513 $r0 through R1, plus $a0 and $a1.
2519 The memory-based pseudo-registers $mem0 through $mem15.
2522 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2523 bit registers for m32cm, m32c).
2526 Matches multiple registers in a PARALLEL to form a larger register.
2527 Used to match function return values.
2533 @minus{}128 @dots{} 127
2536 @minus{}32768 @dots{} 32767
2542 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2545 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2548 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2551 @minus{}65536 @dots{} @minus{}1
2554 An 8 bit value with exactly one bit set.
2557 A 16 bit value with exactly one bit set.
2560 The common src/dest memory addressing modes.
2563 Memory addressed using $a0 or $a1.
2566 Memory addressed with immediate addresses.
2569 Memory addressed using the stack pointer ($sp).
2572 Memory addressed using the frame base register ($fb).
2575 Memory addressed using the small base register ($sb).
2581 @item MeP---@file{config/mep/constraints.md}
2591 Any control register.
2594 Either the $hi or the $lo register.
2597 Coprocessor registers that can be directly loaded ($c0-$c15).
2600 Coprocessor registers that can be moved to each other.
2603 Coprocessor registers that can be moved to core registers.
2615 Registers which can be used in $tp-relative addressing.
2621 The coprocessor registers.
2624 The coprocessor control registers.
2630 User-defined register set A.
2633 User-defined register set B.
2636 User-defined register set C.
2639 User-defined register set D.
2642 Offsets for $gp-rel addressing.
2645 Constants that can be used directly with boolean insns.
2648 Constants that can be moved directly to registers.
2651 Small constants that can be added to registers.
2657 Small constants that can be compared to registers.
2660 Constants that can be loaded into the top half of registers.
2663 Signed 8-bit immediates.
2666 Symbols encoded for $tp-rel or $gp-rel addressing.
2669 Non-constant addresses for loading/saving coprocessor registers.
2672 The top half of a symbol's value.
2675 A register indirect address without offset.
2678 Symbolic references to the control bus.
2682 @item MicroBlaze---@file{config/microblaze/constraints.md}
2685 A general register (@code{r0} to @code{r31}).
2688 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2692 @item MIPS---@file{config/mips/constraints.md}
2695 An address register. This is equivalent to @code{r} unless
2696 generating MIPS16 code.
2699 A floating-point register (if available).
2702 Formerly the @code{hi} register. This constraint is no longer supported.
2705 The @code{lo} register. Use this register to store values that are
2706 no bigger than a word.
2709 The concatenated @code{hi} and @code{lo} registers. Use this register
2710 to store doubleword values.
2713 A register suitable for use in an indirect jump. This will always be
2714 @code{$25} for @option{-mabicalls}.
2717 Register @code{$3}. Do not use this constraint in new code;
2718 it is retained only for compatibility with glibc.
2721 Equivalent to @code{r}; retained for backwards compatibility.
2724 A floating-point condition code register.
2727 A signed 16-bit constant (for arithmetic instructions).
2733 An unsigned 16-bit constant (for logic instructions).
2736 A signed 32-bit constant in which the lower 16 bits are zero.
2737 Such constants can be loaded using @code{lui}.
2740 A constant that cannot be loaded using @code{lui}, @code{addiu}
2744 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2747 A signed 15-bit constant.
2750 A constant in the range 1 to 65535 (inclusive).
2753 Floating-point zero.
2756 An address that can be used in a non-macro load or store.
2759 @item Motorola 680x0---@file{config/m68k/constraints.md}
2768 68881 floating-point register, if available
2771 Integer in the range 1 to 8
2774 16-bit signed number
2777 Signed number whose magnitude is greater than 0x80
2780 Integer in the range @minus{}8 to @minus{}1
2783 Signed number whose magnitude is greater than 0x100
2786 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2789 16 (for rotate using swap)
2792 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2795 Numbers that mov3q can handle
2798 Floating point constant that is not a 68881 constant
2801 Operands that satisfy 'm' when -mpcrel is in effect
2804 Operands that satisfy 's' when -mpcrel is not in effect
2807 Address register indirect addressing mode
2810 Register offset addressing
2825 Range of signed numbers that don't fit in 16 bits
2828 Integers valid for mvq
2831 Integers valid for a moveq followed by a swap
2834 Integers valid for mvz
2837 Integers valid for mvs
2843 Non-register operands allowed in clr
2847 @item Motorola 68HC11 & 68HC12 families---@file{config/m68hc11/m68hc11.h}
2862 Temporary soft register _.tmp
2865 A soft register _.d1 to _.d31
2868 Stack pointer register
2877 Pseudo register `z' (replaced by `x' or `y' at the end)
2880 An address register: x, y or z
2883 An address register: x or y
2886 Register pair (x:d) to form a 32-bit value
2889 Constants in the range @minus{}65536 to 65535
2892 Constants whose 16-bit low part is zero
2895 Constant integer 1 or @minus{}1
2901 Constants in the range @minus{}8 to 2
2905 @item Moxie---@file{config/moxie/constraints.md}
2914 A register indirect memory operand
2917 A constant in the range of 0 to 255.
2920 A constant in the range of 0 to @minus{}255.
2924 @item RX---@file{config/rx/constraints.md}
2927 An address which does not involve register indirect addressing or
2928 pre/post increment/decrement addressing.
2934 A constant in the range @minus{}256 to 255, inclusive.
2937 A constant in the range @minus{}128 to 127, inclusive.
2940 A constant in the range @minus{}32768 to 32767, inclusive.
2943 A constant in the range @minus{}8388608 to 8388607, inclusive.
2946 A constant in the range 0 to 15, inclusive.
2951 @item SPARC---@file{config/sparc/sparc.h}
2954 Floating-point register on the SPARC-V8 architecture and
2955 lower floating-point register on the SPARC-V9 architecture.
2958 Floating-point register. It is equivalent to @samp{f} on the
2959 SPARC-V8 architecture and contains both lower and upper
2960 floating-point registers on the SPARC-V9 architecture.
2963 Floating-point condition code register.
2966 Lower floating-point register. It is only valid on the SPARC-V9
2967 architecture when the Visual Instruction Set is available.
2970 Floating-point register. It is only valid on the SPARC-V9 architecture
2971 when the Visual Instruction Set is available.
2974 64-bit global or out register for the SPARC-V8+ architecture.
2980 Signed 13-bit constant
2986 32-bit constant with the low 12 bits clear (a constant that can be
2987 loaded with the @code{sethi} instruction)
2990 A constant in the range supported by @code{movcc} instructions
2993 A constant in the range supported by @code{movrcc} instructions
2996 Same as @samp{K}, except that it verifies that bits that are not in the
2997 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2998 modes wider than @code{SImode}
3007 Signed 13-bit constant, sign-extended to 32 or 64 bits
3010 Floating-point constant whose integral representation can
3011 be moved into an integer register using a single sethi
3015 Floating-point constant whose integral representation can
3016 be moved into an integer register using a single mov
3020 Floating-point constant whose integral representation can
3021 be moved into an integer register using a high/lo_sum
3022 instruction sequence
3025 Memory address aligned to an 8-byte boundary
3031 Memory address for @samp{e} constraint registers
3038 @item SPU---@file{config/spu/spu.h}
3041 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3044 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3047 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3050 An immediate which can be loaded with @code{fsmbi}.
3053 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3056 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3059 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3062 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3065 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3068 An unsigned 7-bit constant for conversion/nop/channel instructions.
3071 A signed 10-bit constant for most arithmetic instructions.
3074 A signed 16 bit immediate for @code{stop}.
3077 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3080 An unsigned 7-bit constant whose 3 least significant bits are 0.
3083 An unsigned 3-bit constant for 16-byte rotates and shifts
3086 Call operand, reg, for indirect calls
3089 Call operand, symbol, for relative calls.
3092 Call operand, const_int, for absolute calls.
3095 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3098 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3101 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3104 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3108 @item S/390 and zSeries---@file{config/s390/s390.h}
3111 Address register (general purpose register except r0)
3114 Condition code register
3117 Data register (arbitrary general purpose register)
3120 Floating-point register
3123 Unsigned 8-bit constant (0--255)
3126 Unsigned 12-bit constant (0--4095)
3129 Signed 16-bit constant (@minus{}32768--32767)
3132 Value appropriate as displacement.
3135 for short displacement
3136 @item (@minus{}524288..524287)
3137 for long displacement
3141 Constant integer with a value of 0x7fffffff.
3144 Multiple letter constraint followed by 4 parameter letters.
3147 number of the part counting from most to least significant
3151 mode of the containing operand
3153 value of the other parts (F---all bits set)
3155 The constraint matches if the specified part of a constant
3156 has a value different from its other parts.
3159 Memory reference without index register and with short displacement.
3162 Memory reference with index register and short displacement.
3165 Memory reference without index register but with long displacement.
3168 Memory reference with index register and long displacement.
3171 Pointer with short displacement.
3174 Pointer with long displacement.
3177 Shift count operand.
3181 @item Score family---@file{config/score/score.h}
3184 Registers from r0 to r32.
3187 Registers from r0 to r16.
3190 r8---r11 or r22---r27 registers.
3211 cnt + lcb + scb register.
3214 cr0---cr15 register.
3226 cp1 + cp2 + cp3 registers.
3229 High 16-bit constant (32-bit constant with 16 LSBs zero).
3232 Unsigned 5 bit integer (in the range 0 to 31).
3235 Unsigned 16 bit integer (in the range 0 to 65535).
3238 Signed 16 bit integer (in the range @minus{}32768 to 32767).
3241 Unsigned 14 bit integer (in the range 0 to 16383).
3244 Signed 14 bit integer (in the range @minus{}8192 to 8191).
3250 @item Xstormy16---@file{config/stormy16/stormy16.h}
3265 Registers r0 through r7.
3268 Registers r0 and r1.
3274 Registers r8 and r9.
3277 A constant between 0 and 3 inclusive.
3280 A constant that has exactly one bit set.
3283 A constant that has exactly one bit clear.
3286 A constant between 0 and 255 inclusive.
3289 A constant between @minus{}255 and 0 inclusive.
3292 A constant between @minus{}3 and 0 inclusive.
3295 A constant between 1 and 4 inclusive.
3298 A constant between @minus{}4 and @minus{}1 inclusive.
3301 A memory reference that is a stack push.
3304 A memory reference that is a stack pop.
3307 A memory reference that refers to a constant address of known value.
3310 The register indicated by Rx (not implemented yet).
3313 A constant that is not between 2 and 15 inclusive.
3320 @item Xtensa---@file{config/xtensa/constraints.md}
3323 General-purpose 32-bit register
3326 One-bit boolean register
3329 MAC16 40-bit accumulator register
3332 Signed 12-bit integer constant, for use in MOVI instructions
3335 Signed 8-bit integer constant, for use in ADDI instructions
3338 Integer constant valid for BccI instructions
3341 Unsigned constant valid for BccUI instructions
3348 @node Disable Insn Alternatives
3349 @subsection Disable insn alternatives using the @code{enabled} attribute
3352 The @code{enabled} insn attribute may be used to disable certain insn
3353 alternatives for machine-specific reasons. This is useful when adding
3354 new instructions to an existing pattern which are only available for
3355 certain cpu architecture levels as specified with the @code{-march=}
3358 If an insn alternative is disabled, then it will never be used. The
3359 compiler treats the constraints for the disabled alternative as
3362 In order to make use of the @code{enabled} attribute a back end has to add
3363 in the machine description files:
3367 A definition of the @code{enabled} insn attribute. The attribute is
3368 defined as usual using the @code{define_attr} command. This
3369 definition should be based on other insn attributes and/or target flags.
3370 The @code{enabled} attribute is a numeric attribute and should evaluate to
3371 @code{(const_int 1)} for an enabled alternative and to
3372 @code{(const_int 0)} otherwise.
3374 A definition of another insn attribute used to describe for what
3375 reason an insn alternative might be available or
3376 not. E.g. @code{cpu_facility} as in the example below.
3378 An assignment for the second attribute to each insn definition
3379 combining instructions which are not all available under the same
3380 circumstances. (Note: It obviously only makes sense for definitions
3381 with more than one alternative. Otherwise the insn pattern should be
3382 disabled or enabled using the insn condition.)
3385 E.g. the following two patterns could easily be merged using the @code{enabled}
3390 (define_insn "*movdi_old"
3391 [(set (match_operand:DI 0 "register_operand" "=d")
3392 (match_operand:DI 1 "register_operand" " d"))]
3396 (define_insn "*movdi_new"
3397 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3398 (match_operand:DI 1 "register_operand" " d,d,f"))]
3411 (define_insn "*movdi_combined"
3412 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3413 (match_operand:DI 1 "register_operand" " d,d,f"))]
3419 [(set_attr "cpu_facility" "*,new,new")])
3423 with the @code{enabled} attribute defined like this:
3427 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
3429 (define_attr "enabled" ""
3430 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
3431 (and (eq_attr "cpu_facility" "new")
3432 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
3441 @node Define Constraints
3442 @subsection Defining Machine-Specific Constraints
3443 @cindex defining constraints
3444 @cindex constraints, defining
3446 Machine-specific constraints fall into two categories: register and
3447 non-register constraints. Within the latter category, constraints
3448 which allow subsets of all possible memory or address operands should
3449 be specially marked, to give @code{reload} more information.
3451 Machine-specific constraints can be given names of arbitrary length,
3452 but they must be entirely composed of letters, digits, underscores
3453 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
3454 must begin with a letter or underscore.
3456 In order to avoid ambiguity in operand constraint strings, no
3457 constraint can have a name that begins with any other constraint's
3458 name. For example, if @code{x} is defined as a constraint name,
3459 @code{xy} may not be, and vice versa. As a consequence of this rule,
3460 no constraint may begin with one of the generic constraint letters:
3461 @samp{E F V X g i m n o p r s}.
3463 Register constraints correspond directly to register classes.
3464 @xref{Register Classes}. There is thus not much flexibility in their
3467 @deffn {MD Expression} define_register_constraint name regclass docstring
3468 All three arguments are string constants.
3469 @var{name} is the name of the constraint, as it will appear in
3470 @code{match_operand} expressions. If @var{name} is a multi-letter
3471 constraint its length shall be the same for all constraints starting
3472 with the same letter. @var{regclass} can be either the
3473 name of the corresponding register class (@pxref{Register Classes}),
3474 or a C expression which evaluates to the appropriate register class.
3475 If it is an expression, it must have no side effects, and it cannot
3476 look at the operand. The usual use of expressions is to map some
3477 register constraints to @code{NO_REGS} when the register class
3478 is not available on a given subarchitecture.
3480 @var{docstring} is a sentence documenting the meaning of the
3481 constraint. Docstrings are explained further below.
3484 Non-register constraints are more like predicates: the constraint
3485 definition gives a Boolean expression which indicates whether the
3488 @deffn {MD Expression} define_constraint name docstring exp
3489 The @var{name} and @var{docstring} arguments are the same as for
3490 @code{define_register_constraint}, but note that the docstring comes
3491 immediately after the name for these expressions. @var{exp} is an RTL
3492 expression, obeying the same rules as the RTL expressions in predicate
3493 definitions. @xref{Defining Predicates}, for details. If it
3494 evaluates true, the constraint matches; if it evaluates false, it
3495 doesn't. Constraint expressions should indicate which RTL codes they
3496 might match, just like predicate expressions.
3498 @code{match_test} C expressions have access to the
3499 following variables:
3503 The RTL object defining the operand.
3505 The machine mode of @var{op}.
3507 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
3509 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
3510 @code{const_double}.
3512 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
3513 @code{const_double}.
3515 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
3516 @code{const_double}.
3519 The @var{*val} variables should only be used once another piece of the
3520 expression has verified that @var{op} is the appropriate kind of RTL
3524 Most non-register constraints should be defined with
3525 @code{define_constraint}. The remaining two definition expressions
3526 are only appropriate for constraints that should be handled specially
3527 by @code{reload} if they fail to match.
3529 @deffn {MD Expression} define_memory_constraint name docstring exp
3530 Use this expression for constraints that match a subset of all memory
3531 operands: that is, @code{reload} can make them match by converting the
3532 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
3533 base register (from the register class specified by
3534 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
3536 For example, on the S/390, some instructions do not accept arbitrary
3537 memory references, but only those that do not make use of an index
3538 register. The constraint letter @samp{Q} is defined to represent a
3539 memory address of this type. If @samp{Q} is defined with
3540 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
3541 memory operand, because @code{reload} knows it can simply copy the
3542 memory address into a base register if required. This is analogous to
3543 the way an @samp{o} constraint can handle any memory operand.
3545 The syntax and semantics are otherwise identical to
3546 @code{define_constraint}.
3549 @deffn {MD Expression} define_address_constraint name docstring exp
3550 Use this expression for constraints that match a subset of all address
3551 operands: that is, @code{reload} can make the constraint match by
3552 converting the operand to the form @samp{@w{(reg @var{X})}}, again
3553 with @var{X} a base register.
3555 Constraints defined with @code{define_address_constraint} can only be
3556 used with the @code{address_operand} predicate, or machine-specific
3557 predicates that work the same way. They are treated analogously to
3558 the generic @samp{p} constraint.
3560 The syntax and semantics are otherwise identical to
3561 @code{define_constraint}.
3564 For historical reasons, names beginning with the letters @samp{G H}
3565 are reserved for constraints that match only @code{const_double}s, and
3566 names beginning with the letters @samp{I J K L M N O P} are reserved
3567 for constraints that match only @code{const_int}s. This may change in
3568 the future. For the time being, constraints with these names must be
3569 written in a stylized form, so that @code{genpreds} can tell you did
3574 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
3576 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
3577 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
3580 @c the semicolons line up in the formatted manual
3582 It is fine to use names beginning with other letters for constraints
3583 that match @code{const_double}s or @code{const_int}s.
3585 Each docstring in a constraint definition should be one or more complete
3586 sentences, marked up in Texinfo format. @emph{They are currently unused.}
3587 In the future they will be copied into the GCC manual, in @ref{Machine
3588 Constraints}, replacing the hand-maintained tables currently found in
3589 that section. Also, in the future the compiler may use this to give
3590 more helpful diagnostics when poor choice of @code{asm} constraints
3591 causes a reload failure.
3593 If you put the pseudo-Texinfo directive @samp{@@internal} at the
3594 beginning of a docstring, then (in the future) it will appear only in
3595 the internals manual's version of the machine-specific constraint tables.
3596 Use this for constraints that should not appear in @code{asm} statements.
3598 @node C Constraint Interface
3599 @subsection Testing constraints from C
3600 @cindex testing constraints
3601 @cindex constraints, testing
3603 It is occasionally useful to test a constraint from C code rather than
3604 implicitly via the constraint string in a @code{match_operand}. The
3605 generated file @file{tm_p.h} declares a few interfaces for working
3606 with machine-specific constraints. None of these interfaces work with
3607 the generic constraints described in @ref{Simple Constraints}. This
3608 may change in the future.
3610 @strong{Warning:} @file{tm_p.h} may declare other functions that
3611 operate on constraints, besides the ones documented here. Do not use
3612 those functions from machine-dependent code. They exist to implement
3613 the old constraint interface that machine-independent components of
3614 the compiler still expect. They will change or disappear in the
3617 Some valid constraint names are not valid C identifiers, so there is a
3618 mangling scheme for referring to them from C@. Constraint names that
3619 do not contain angle brackets or underscores are left unchanged.
3620 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
3621 each @samp{>} with @samp{_g}. Here are some examples:
3623 @c the @c's prevent double blank lines in the printed manual.
3625 @multitable {Original} {Mangled}
3626 @item @strong{Original} @tab @strong{Mangled} @c
3627 @item @code{x} @tab @code{x} @c
3628 @item @code{P42x} @tab @code{P42x} @c
3629 @item @code{P4_x} @tab @code{P4__x} @c
3630 @item @code{P4>x} @tab @code{P4_gx} @c
3631 @item @code{P4>>} @tab @code{P4_g_g} @c
3632 @item @code{P4_g>} @tab @code{P4__g_g} @c
3636 Throughout this section, the variable @var{c} is either a constraint
3637 in the abstract sense, or a constant from @code{enum constraint_num};
3638 the variable @var{m} is a mangled constraint name (usually as part of
3639 a larger identifier).
3641 @deftp Enum constraint_num
3642 For each machine-specific constraint, there is a corresponding
3643 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
3644 constraint. Functions that take an @code{enum constraint_num} as an
3645 argument expect one of these constants.
3647 Machine-independent constraints do not have associated constants.
3648 This may change in the future.
3651 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
3652 For each machine-specific, non-register constraint @var{m}, there is
3653 one of these functions; it returns @code{true} if @var{exp} satisfies the
3654 constraint. These functions are only visible if @file{rtl.h} was included
3655 before @file{tm_p.h}.
3658 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
3659 Like the @code{satisfies_constraint_@var{m}} functions, but the
3660 constraint to test is given as an argument, @var{c}. If @var{c}
3661 specifies a register constraint, this function will always return
3665 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
3666 Returns the register class associated with @var{c}. If @var{c} is not
3667 a register constraint, or those registers are not available for the
3668 currently selected subtarget, returns @code{NO_REGS}.
3671 Here is an example use of @code{satisfies_constraint_@var{m}}. In
3672 peephole optimizations (@pxref{Peephole Definitions}), operand
3673 constraint strings are ignored, so if there are relevant constraints,
3674 they must be tested in the C condition. In the example, the
3675 optimization is applied if operand 2 does @emph{not} satisfy the
3676 @samp{K} constraint. (This is a simplified version of a peephole
3677 definition from the i386 machine description.)
3681 [(match_scratch:SI 3 "r")
3682 (set (match_operand:SI 0 "register_operand" "")
3683 (mult:SI (match_operand:SI 1 "memory_operand" "")
3684 (match_operand:SI 2 "immediate_operand" "")))]
3686 "!satisfies_constraint_K (operands[2])"
3688 [(set (match_dup 3) (match_dup 1))
3689 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
3694 @node Standard Names
3695 @section Standard Pattern Names For Generation
3696 @cindex standard pattern names
3697 @cindex pattern names
3698 @cindex names, pattern
3700 Here is a table of the instruction names that are meaningful in the RTL
3701 generation pass of the compiler. Giving one of these names to an
3702 instruction pattern tells the RTL generation pass that it can use the
3703 pattern to accomplish a certain task.
3706 @cindex @code{mov@var{m}} instruction pattern
3707 @item @samp{mov@var{m}}
3708 Here @var{m} stands for a two-letter machine mode name, in lowercase.
3709 This instruction pattern moves data with that machine mode from operand
3710 1 to operand 0. For example, @samp{movsi} moves full-word data.
3712 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
3713 own mode is wider than @var{m}, the effect of this instruction is
3714 to store the specified value in the part of the register that corresponds
3715 to mode @var{m}. Bits outside of @var{m}, but which are within the
3716 same target word as the @code{subreg} are undefined. Bits which are
3717 outside the target word are left unchanged.
3719 This class of patterns is special in several ways. First of all, each
3720 of these names up to and including full word size @emph{must} be defined,
3721 because there is no other way to copy a datum from one place to another.
3722 If there are patterns accepting operands in larger modes,
3723 @samp{mov@var{m}} must be defined for integer modes of those sizes.
3725 Second, these patterns are not used solely in the RTL generation pass.
3726 Even the reload pass can generate move insns to copy values from stack
3727 slots into temporary registers. When it does so, one of the operands is
3728 a hard register and the other is an operand that can need to be reloaded
3732 Therefore, when given such a pair of operands, the pattern must generate
3733 RTL which needs no reloading and needs no temporary registers---no
3734 registers other than the operands. For example, if you support the
3735 pattern with a @code{define_expand}, then in such a case the
3736 @code{define_expand} mustn't call @code{force_reg} or any other such
3737 function which might generate new pseudo registers.
3739 This requirement exists even for subword modes on a RISC machine where
3740 fetching those modes from memory normally requires several insns and
3741 some temporary registers.
3743 @findex change_address
3744 During reload a memory reference with an invalid address may be passed
3745 as an operand. Such an address will be replaced with a valid address
3746 later in the reload pass. In this case, nothing may be done with the
3747 address except to use it as it stands. If it is copied, it will not be
3748 replaced with a valid address. No attempt should be made to make such
3749 an address into a valid address and no routine (such as
3750 @code{change_address}) that will do so may be called. Note that
3751 @code{general_operand} will fail when applied to such an address.
3753 @findex reload_in_progress
3754 The global variable @code{reload_in_progress} (which must be explicitly
3755 declared if required) can be used to determine whether such special
3756 handling is required.
3758 The variety of operands that have reloads depends on the rest of the
3759 machine description, but typically on a RISC machine these can only be
3760 pseudo registers that did not get hard registers, while on other
3761 machines explicit memory references will get optional reloads.
3763 If a scratch register is required to move an object to or from memory,
3764 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
3766 If there are cases which need scratch registers during or after reload,
3767 you must provide an appropriate secondary_reload target hook.
3769 @findex can_create_pseudo_p
3770 The macro @code{can_create_pseudo_p} can be used to determine if it
3771 is unsafe to create new pseudo registers. If this variable is nonzero, then
3772 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
3774 The constraints on a @samp{mov@var{m}} must permit moving any hard
3775 register to any other hard register provided that
3776 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
3777 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
3780 It is obligatory to support floating point @samp{mov@var{m}}
3781 instructions into and out of any registers that can hold fixed point
3782 values, because unions and structures (which have modes @code{SImode} or
3783 @code{DImode}) can be in those registers and they may have floating
3786 There may also be a need to support fixed point @samp{mov@var{m}}
3787 instructions in and out of floating point registers. Unfortunately, I
3788 have forgotten why this was so, and I don't know whether it is still
3789 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
3790 floating point registers, then the constraints of the fixed point
3791 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
3792 reload into a floating point register.
3794 @cindex @code{reload_in} instruction pattern
3795 @cindex @code{reload_out} instruction pattern
3796 @item @samp{reload_in@var{m}}
3797 @itemx @samp{reload_out@var{m}}
3798 These named patterns have been obsoleted by the target hook
3799 @code{secondary_reload}.
3801 Like @samp{mov@var{m}}, but used when a scratch register is required to
3802 move between operand 0 and operand 1. Operand 2 describes the scratch
3803 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
3804 macro in @pxref{Register Classes}.
3806 There are special restrictions on the form of the @code{match_operand}s
3807 used in these patterns. First, only the predicate for the reload
3808 operand is examined, i.e., @code{reload_in} examines operand 1, but not
3809 the predicates for operand 0 or 2. Second, there may be only one
3810 alternative in the constraints. Third, only a single register class
3811 letter may be used for the constraint; subsequent constraint letters
3812 are ignored. As a special exception, an empty constraint string
3813 matches the @code{ALL_REGS} register class. This may relieve ports
3814 of the burden of defining an @code{ALL_REGS} constraint letter just
3817 @cindex @code{movstrict@var{m}} instruction pattern
3818 @item @samp{movstrict@var{m}}
3819 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
3820 with mode @var{m} of a register whose natural mode is wider,
3821 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
3822 any of the register except the part which belongs to mode @var{m}.
3824 @cindex @code{movmisalign@var{m}} instruction pattern
3825 @item @samp{movmisalign@var{m}}
3826 This variant of a move pattern is designed to load or store a value
3827 from a memory address that is not naturally aligned for its mode.
3828 For a store, the memory will be in operand 0; for a load, the memory
3829 will be in operand 1. The other operand is guaranteed not to be a
3830 memory, so that it's easy to tell whether this is a load or store.
3832 This pattern is used by the autovectorizer, and when expanding a
3833 @code{MISALIGNED_INDIRECT_REF} expression.
3835 @cindex @code{load_multiple} instruction pattern
3836 @item @samp{load_multiple}
3837 Load several consecutive memory locations into consecutive registers.
3838 Operand 0 is the first of the consecutive registers, operand 1
3839 is the first memory location, and operand 2 is a constant: the
3840 number of consecutive registers.
3842 Define this only if the target machine really has such an instruction;
3843 do not define this if the most efficient way of loading consecutive
3844 registers from memory is to do them one at a time.
3846 On some machines, there are restrictions as to which consecutive
3847 registers can be stored into memory, such as particular starting or
3848 ending register numbers or only a range of valid counts. For those
3849 machines, use a @code{define_expand} (@pxref{Expander Definitions})
3850 and make the pattern fail if the restrictions are not met.
3852 Write the generated insn as a @code{parallel} with elements being a
3853 @code{set} of one register from the appropriate memory location (you may
3854 also need @code{use} or @code{clobber} elements). Use a
3855 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
3856 @file{rs6000.md} for examples of the use of this insn pattern.
3858 @cindex @samp{store_multiple} instruction pattern
3859 @item @samp{store_multiple}
3860 Similar to @samp{load_multiple}, but store several consecutive registers
3861 into consecutive memory locations. Operand 0 is the first of the
3862 consecutive memory locations, operand 1 is the first register, and
3863 operand 2 is a constant: the number of consecutive registers.
3865 @cindex @code{vec_set@var{m}} instruction pattern
3866 @item @samp{vec_set@var{m}}
3867 Set given field in the vector value. Operand 0 is the vector to modify,
3868 operand 1 is new value of field and operand 2 specify the field index.
3870 @cindex @code{vec_extract@var{m}} instruction pattern
3871 @item @samp{vec_extract@var{m}}
3872 Extract given field from the vector value. Operand 1 is the vector, operand 2
3873 specify field index and operand 0 place to store value into.
3875 @cindex @code{vec_extract_even@var{m}} instruction pattern
3876 @item @samp{vec_extract_even@var{m}}
3877 Extract even elements from the input vectors (operand 1 and operand 2).
3878 The even elements of operand 2 are concatenated to the even elements of operand
3879 1 in their original order. The result is stored in operand 0.
3880 The output and input vectors should have the same modes.
3882 @cindex @code{vec_extract_odd@var{m}} instruction pattern
3883 @item @samp{vec_extract_odd@var{m}}
3884 Extract odd elements from the input vectors (operand 1 and operand 2).
3885 The odd elements of operand 2 are concatenated to the odd elements of operand
3886 1 in their original order. The result is stored in operand 0.
3887 The output and input vectors should have the same modes.
3889 @cindex @code{vec_interleave_high@var{m}} instruction pattern
3890 @item @samp{vec_interleave_high@var{m}}
3891 Merge high elements of the two input vectors into the output vector. The output
3892 and input vectors should have the same modes (@code{N} elements). The high
3893 @code{N/2} elements of the first input vector are interleaved with the high
3894 @code{N/2} elements of the second input vector.
3896 @cindex @code{vec_interleave_low@var{m}} instruction pattern
3897 @item @samp{vec_interleave_low@var{m}}
3898 Merge low elements of the two input vectors into the output vector. The output
3899 and input vectors should have the same modes (@code{N} elements). The low
3900 @code{N/2} elements of the first input vector are interleaved with the low
3901 @code{N/2} elements of the second input vector.
3903 @cindex @code{vec_init@var{m}} instruction pattern
3904 @item @samp{vec_init@var{m}}
3905 Initialize the vector to given values. Operand 0 is the vector to initialize
3906 and operand 1 is parallel containing values for individual fields.
3908 @cindex @code{push@var{m}1} instruction pattern
3909 @item @samp{push@var{m}1}
3910 Output a push instruction. Operand 0 is value to push. Used only when
3911 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
3912 missing and in such case an @code{mov} expander is used instead, with a
3913 @code{MEM} expression forming the push operation. The @code{mov} expander
3914 method is deprecated.
3916 @cindex @code{add@var{m}3} instruction pattern
3917 @item @samp{add@var{m}3}
3918 Add operand 2 and operand 1, storing the result in operand 0. All operands
3919 must have mode @var{m}. This can be used even on two-address machines, by
3920 means of constraints requiring operands 1 and 0 to be the same location.
3922 @cindex @code{ssadd@var{m}3} instruction pattern
3923 @cindex @code{usadd@var{m}3} instruction pattern
3924 @cindex @code{sub@var{m}3} instruction pattern
3925 @cindex @code{sssub@var{m}3} instruction pattern
3926 @cindex @code{ussub@var{m}3} instruction pattern
3927 @cindex @code{mul@var{m}3} instruction pattern
3928 @cindex @code{ssmul@var{m}3} instruction pattern
3929 @cindex @code{usmul@var{m}3} instruction pattern
3930 @cindex @code{div@var{m}3} instruction pattern
3931 @cindex @code{ssdiv@var{m}3} instruction pattern
3932 @cindex @code{udiv@var{m}3} instruction pattern
3933 @cindex @code{usdiv@var{m}3} instruction pattern
3934 @cindex @code{mod@var{m}3} instruction pattern
3935 @cindex @code{umod@var{m}3} instruction pattern
3936 @cindex @code{umin@var{m}3} instruction pattern
3937 @cindex @code{umax@var{m}3} instruction pattern
3938 @cindex @code{and@var{m}3} instruction pattern
3939 @cindex @code{ior@var{m}3} instruction pattern
3940 @cindex @code{xor@var{m}3} instruction pattern
3941 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
3942 @item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
3943 @item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
3944 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
3945 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
3946 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
3947 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
3948 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
3949 Similar, for other arithmetic operations.
3951 @cindex @code{fma@var{m}4} instruction pattern
3952 @item @samp{fma@var{m}4}
3953 Multiply operand 2 and operand 1, then add operand 3, storing the
3954 result in operand 0. All operands must have mode @var{m}. This
3955 pattern is used to implement the @code{fma}, @code{fmaf}, and
3956 @code{fmal} builtin functions from the ISO C99 standard. The
3957 @code{fma} operation may produce different results than doing the
3958 multiply followed by the add if the machine does not perform a
3959 rounding step between the operations.
3961 @cindex @code{fms@var{m}4} instruction pattern
3962 @item @samp{fms@var{m}4}
3963 Like @code{fma@var{m}4}, except operand 3 subtracted from the
3964 product instead of added to the product. This is represented
3968 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
3971 @cindex @code{fnma@var{m}4} instruction pattern
3972 @item @samp{fnma@var{m}4}
3973 Like @code{fma@var{m}4} except that the intermediate product
3974 is negated before being added to operand 3. This is represented
3978 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
3981 @cindex @code{fnms@var{m}4} instruction pattern
3982 @item @samp{fnms@var{m}4}
3983 Like @code{fms@var{m}4} except that the intermediate product
3984 is negated before subtracting operand 3. This is represented
3988 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
3991 @cindex @code{min@var{m}3} instruction pattern
3992 @cindex @code{max@var{m}3} instruction pattern
3993 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
3994 Signed minimum and maximum operations. When used with floating point,
3995 if both operands are zeros, or if either operand is @code{NaN}, then
3996 it is unspecified which of the two operands is returned as the result.
3998 @cindex @code{reduc_smin_@var{m}} instruction pattern
3999 @cindex @code{reduc_smax_@var{m}} instruction pattern
4000 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
4001 Find the signed minimum/maximum of the elements of a vector. The vector is
4002 operand 1, and the scalar result is stored in the least significant bits of
4003 operand 0 (also a vector). The output and input vector should have the same
4006 @cindex @code{reduc_umin_@var{m}} instruction pattern
4007 @cindex @code{reduc_umax_@var{m}} instruction pattern
4008 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
4009 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4010 operand 1, and the scalar result is stored in the least significant bits of
4011 operand 0 (also a vector). The output and input vector should have the same
4014 @cindex @code{reduc_splus_@var{m}} instruction pattern
4015 @item @samp{reduc_splus_@var{m}}
4016 Compute the sum of the signed elements of a vector. The vector is operand 1,
4017 and the scalar result is stored in the least significant bits of operand 0
4018 (also a vector). The output and input vector should have the same modes.
4020 @cindex @code{reduc_uplus_@var{m}} instruction pattern
4021 @item @samp{reduc_uplus_@var{m}}
4022 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
4023 and the scalar result is stored in the least significant bits of operand 0
4024 (also a vector). The output and input vector should have the same modes.
4026 @cindex @code{sdot_prod@var{m}} instruction pattern
4027 @item @samp{sdot_prod@var{m}}
4028 @cindex @code{udot_prod@var{m}} instruction pattern
4029 @item @samp{udot_prod@var{m}}
4030 Compute the sum of the products of two signed/unsigned elements.
4031 Operand 1 and operand 2 are of the same mode. Their product, which is of a
4032 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
4033 wider than the mode of the product. The result is placed in operand 0, which
4034 is of the same mode as operand 3.
4036 @cindex @code{ssum_widen@var{m3}} instruction pattern
4037 @item @samp{ssum_widen@var{m3}}
4038 @cindex @code{usum_widen@var{m3}} instruction pattern
4039 @item @samp{usum_widen@var{m3}}
4040 Operands 0 and 2 are of the same mode, which is wider than the mode of
4041 operand 1. Add operand 1 to operand 2 and place the widened result in
4042 operand 0. (This is used express accumulation of elements into an accumulator
4045 @cindex @code{vec_shl_@var{m}} instruction pattern
4046 @cindex @code{vec_shr_@var{m}} instruction pattern
4047 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
4048 Whole vector left/right shift in bits.
4049 Operand 1 is a vector to be shifted.
4050 Operand 2 is an integer shift amount in bits.
4051 Operand 0 is where the resulting shifted vector is stored.
4052 The output and input vectors should have the same modes.
4054 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
4055 @item @samp{vec_pack_trunc_@var{m}}
4056 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4057 are vectors of the same mode having N integral or floating point elements
4058 of size S@. Operand 0 is the resulting vector in which 2*N elements of
4059 size N/2 are concatenated after narrowing them down using truncation.
4061 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
4062 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
4063 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
4064 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4065 are vectors of the same mode having N integral elements of size S.
4066 Operand 0 is the resulting vector in which the elements of the two input
4067 vectors are concatenated after narrowing them down using signed/unsigned
4068 saturating arithmetic.
4070 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
4071 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
4072 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
4073 Narrow, convert to signed/unsigned integral type and merge the elements
4074 of two vectors. Operands 1 and 2 are vectors of the same mode having N
4075 floating point elements of size S@. Operand 0 is the resulting vector
4076 in which 2*N elements of size N/2 are concatenated.
4078 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
4079 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
4080 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
4081 Extract and widen (promote) the high/low part of a vector of signed
4082 integral or floating point elements. The input vector (operand 1) has N
4083 elements of size S@. Widen (promote) the high/low elements of the vector
4084 using signed or floating point extension and place the resulting N/2
4085 values of size 2*S in the output vector (operand 0).
4087 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
4088 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
4089 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
4090 Extract and widen (promote) the high/low part of a vector of unsigned
4091 integral elements. The input vector (operand 1) has N elements of size S.
4092 Widen (promote) the high/low elements of the vector using zero extension and
4093 place the resulting N/2 values of size 2*S in the output vector (operand 0).
4095 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
4096 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
4097 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
4098 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
4099 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
4100 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
4101 Extract, convert to floating point type and widen the high/low part of a
4102 vector of signed/unsigned integral elements. The input vector (operand 1)
4103 has N elements of size S@. Convert the high/low elements of the vector using
4104 floating point conversion and place the resulting N/2 values of size 2*S in
4105 the output vector (operand 0).
4107 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
4108 @cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern
4109 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
4110 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
4111 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
4112 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
4113 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
4114 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
4115 elements of the two vectors, and put the N/2 products of size 2*S in the
4116 output vector (operand 0).
4118 @cindex @code{mulhisi3} instruction pattern
4119 @item @samp{mulhisi3}
4120 Multiply operands 1 and 2, which have mode @code{HImode}, and store
4121 a @code{SImode} product in operand 0.
4123 @cindex @code{mulqihi3} instruction pattern
4124 @cindex @code{mulsidi3} instruction pattern
4125 @item @samp{mulqihi3}, @samp{mulsidi3}
4126 Similar widening-multiplication instructions of other widths.
4128 @cindex @code{umulqihi3} instruction pattern
4129 @cindex @code{umulhisi3} instruction pattern
4130 @cindex @code{umulsidi3} instruction pattern
4131 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
4132 Similar widening-multiplication instructions that do unsigned
4135 @cindex @code{usmulqihi3} instruction pattern
4136 @cindex @code{usmulhisi3} instruction pattern
4137 @cindex @code{usmulsidi3} instruction pattern
4138 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
4139 Similar widening-multiplication instructions that interpret the first
4140 operand as unsigned and the second operand as signed, then do a signed
4143 @cindex @code{smul@var{m}3_highpart} instruction pattern
4144 @item @samp{smul@var{m}3_highpart}
4145 Perform a signed multiplication of operands 1 and 2, which have mode
4146 @var{m}, and store the most significant half of the product in operand 0.
4147 The least significant half of the product is discarded.
4149 @cindex @code{umul@var{m}3_highpart} instruction pattern
4150 @item @samp{umul@var{m}3_highpart}
4151 Similar, but the multiplication is unsigned.
4153 @cindex @code{madd@var{m}@var{n}4} instruction pattern
4154 @item @samp{madd@var{m}@var{n}4}
4155 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
4156 operand 3, and store the result in operand 0. Operands 1 and 2
4157 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4158 Both modes must be integer or fixed-point modes and @var{n} must be twice
4159 the size of @var{m}.
4161 In other words, @code{madd@var{m}@var{n}4} is like
4162 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
4164 These instructions are not allowed to @code{FAIL}.
4166 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
4167 @item @samp{umadd@var{m}@var{n}4}
4168 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
4169 operands instead of sign-extending them.
4171 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
4172 @item @samp{ssmadd@var{m}@var{n}4}
4173 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
4176 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
4177 @item @samp{usmadd@var{m}@var{n}4}
4178 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
4179 unsigned-saturating.
4181 @cindex @code{msub@var{m}@var{n}4} instruction pattern
4182 @item @samp{msub@var{m}@var{n}4}
4183 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
4184 result from operand 3, and store the result in operand 0. Operands 1 and 2
4185 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4186 Both modes must be integer or fixed-point modes and @var{n} must be twice
4187 the size of @var{m}.
4189 In other words, @code{msub@var{m}@var{n}4} is like
4190 @code{mul@var{m}@var{n}3} except that it also subtracts the result
4193 These instructions are not allowed to @code{FAIL}.
4195 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
4196 @item @samp{umsub@var{m}@var{n}4}
4197 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
4198 operands instead of sign-extending them.
4200 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
4201 @item @samp{ssmsub@var{m}@var{n}4}
4202 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
4205 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
4206 @item @samp{usmsub@var{m}@var{n}4}
4207 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
4208 unsigned-saturating.
4210 @cindex @code{divmod@var{m}4} instruction pattern
4211 @item @samp{divmod@var{m}4}
4212 Signed division that produces both a quotient and a remainder.
4213 Operand 1 is divided by operand 2 to produce a quotient stored
4214 in operand 0 and a remainder stored in operand 3.
4216 For machines with an instruction that produces both a quotient and a
4217 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
4218 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
4219 allows optimization in the relatively common case when both the quotient
4220 and remainder are computed.
4222 If an instruction that just produces a quotient or just a remainder
4223 exists and is more efficient than the instruction that produces both,
4224 write the output routine of @samp{divmod@var{m}4} to call
4225 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
4226 quotient or remainder and generate the appropriate instruction.
4228 @cindex @code{udivmod@var{m}4} instruction pattern
4229 @item @samp{udivmod@var{m}4}
4230 Similar, but does unsigned division.
4232 @anchor{shift patterns}
4233 @cindex @code{ashl@var{m}3} instruction pattern
4234 @cindex @code{ssashl@var{m}3} instruction pattern
4235 @cindex @code{usashl@var{m}3} instruction pattern
4236 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
4237 Arithmetic-shift operand 1 left by a number of bits specified by operand
4238 2, and store the result in operand 0. Here @var{m} is the mode of
4239 operand 0 and operand 1; operand 2's mode is specified by the
4240 instruction pattern, and the compiler will convert the operand to that
4241 mode before generating the instruction. The meaning of out-of-range shift
4242 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
4243 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
4245 @cindex @code{ashr@var{m}3} instruction pattern
4246 @cindex @code{lshr@var{m}3} instruction pattern
4247 @cindex @code{rotl@var{m}3} instruction pattern
4248 @cindex @code{rotr@var{m}3} instruction pattern
4249 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
4250 Other shift and rotate instructions, analogous to the
4251 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
4253 @cindex @code{vashl@var{m}3} instruction pattern
4254 @cindex @code{vashr@var{m}3} instruction pattern
4255 @cindex @code{vlshr@var{m}3} instruction pattern
4256 @cindex @code{vrotl@var{m}3} instruction pattern
4257 @cindex @code{vrotr@var{m}3} instruction pattern
4258 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
4259 Vector shift and rotate instructions that take vectors as operand 2
4260 instead of a scalar type.
4262 @cindex @code{neg@var{m}2} instruction pattern
4263 @cindex @code{ssneg@var{m}2} instruction pattern
4264 @cindex @code{usneg@var{m}2} instruction pattern
4265 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
4266 Negate operand 1 and store the result in operand 0.
4268 @cindex @code{abs@var{m}2} instruction pattern
4269 @item @samp{abs@var{m}2}
4270 Store the absolute value of operand 1 into operand 0.
4272 @cindex @code{sqrt@var{m}2} instruction pattern
4273 @item @samp{sqrt@var{m}2}
4274 Store the square root of operand 1 into operand 0.
4276 The @code{sqrt} built-in function of C always uses the mode which
4277 corresponds to the C data type @code{double} and the @code{sqrtf}
4278 built-in function uses the mode which corresponds to the C data
4281 @cindex @code{fmod@var{m}3} instruction pattern
4282 @item @samp{fmod@var{m}3}
4283 Store the remainder of dividing operand 1 by operand 2 into
4284 operand 0, rounded towards zero to an integer.
4286 The @code{fmod} built-in function of C always uses the mode which
4287 corresponds to the C data type @code{double} and the @code{fmodf}
4288 built-in function uses the mode which corresponds to the C data
4291 @cindex @code{remainder@var{m}3} instruction pattern
4292 @item @samp{remainder@var{m}3}
4293 Store the remainder of dividing operand 1 by operand 2 into
4294 operand 0, rounded to the nearest integer.
4296 The @code{remainder} built-in function of C always uses the mode
4297 which corresponds to the C data type @code{double} and the
4298 @code{remainderf} built-in function uses the mode which corresponds
4299 to the C data type @code{float}.
4301 @cindex @code{cos@var{m}2} instruction pattern
4302 @item @samp{cos@var{m}2}
4303 Store the cosine of operand 1 into operand 0.
4305 The @code{cos} built-in function of C always uses the mode which
4306 corresponds to the C data type @code{double} and the @code{cosf}
4307 built-in function uses the mode which corresponds to the C data
4310 @cindex @code{sin@var{m}2} instruction pattern
4311 @item @samp{sin@var{m}2}
4312 Store the sine of operand 1 into operand 0.
4314 The @code{sin} built-in function of C always uses the mode which
4315 corresponds to the C data type @code{double} and the @code{sinf}
4316 built-in function uses the mode which corresponds to the C data
4319 @cindex @code{exp@var{m}2} instruction pattern
4320 @item @samp{exp@var{m}2}
4321 Store the exponential of operand 1 into operand 0.
4323 The @code{exp} built-in function of C always uses the mode which
4324 corresponds to the C data type @code{double} and the @code{expf}
4325 built-in function uses the mode which corresponds to the C data
4328 @cindex @code{log@var{m}2} instruction pattern
4329 @item @samp{log@var{m}2}
4330 Store the natural logarithm of operand 1 into operand 0.
4332 The @code{log} built-in function of C always uses the mode which
4333 corresponds to the C data type @code{double} and the @code{logf}
4334 built-in function uses the mode which corresponds to the C data
4337 @cindex @code{pow@var{m}3} instruction pattern
4338 @item @samp{pow@var{m}3}
4339 Store the value of operand 1 raised to the exponent operand 2
4342 The @code{pow} built-in function of C always uses the mode which
4343 corresponds to the C data type @code{double} and the @code{powf}
4344 built-in function uses the mode which corresponds to the C data
4347 @cindex @code{atan2@var{m}3} instruction pattern
4348 @item @samp{atan2@var{m}3}
4349 Store the arc tangent (inverse tangent) of operand 1 divided by
4350 operand 2 into operand 0, using the signs of both arguments to
4351 determine the quadrant of the result.
4353 The @code{atan2} built-in function of C always uses the mode which
4354 corresponds to the C data type @code{double} and the @code{atan2f}
4355 built-in function uses the mode which corresponds to the C data
4358 @cindex @code{floor@var{m}2} instruction pattern
4359 @item @samp{floor@var{m}2}
4360 Store the largest integral value not greater than argument.
4362 The @code{floor} built-in function of C always uses the mode which
4363 corresponds to the C data type @code{double} and the @code{floorf}
4364 built-in function uses the mode which corresponds to the C data
4367 @cindex @code{btrunc@var{m}2} instruction pattern
4368 @item @samp{btrunc@var{m}2}
4369 Store the argument rounded to integer towards zero.
4371 The @code{trunc} built-in function of C always uses the mode which
4372 corresponds to the C data type @code{double} and the @code{truncf}
4373 built-in function uses the mode which corresponds to the C data
4376 @cindex @code{round@var{m}2} instruction pattern
4377 @item @samp{round@var{m}2}
4378 Store the argument rounded to integer away from zero.
4380 The @code{round} built-in function of C always uses the mode which
4381 corresponds to the C data type @code{double} and the @code{roundf}
4382 built-in function uses the mode which corresponds to the C data
4385 @cindex @code{ceil@var{m}2} instruction pattern
4386 @item @samp{ceil@var{m}2}
4387 Store the argument rounded to integer away from zero.
4389 The @code{ceil} built-in function of C always uses the mode which
4390 corresponds to the C data type @code{double} and the @code{ceilf}
4391 built-in function uses the mode which corresponds to the C data
4394 @cindex @code{nearbyint@var{m}2} instruction pattern
4395 @item @samp{nearbyint@var{m}2}
4396 Store the argument rounded according to the default rounding mode
4398 The @code{nearbyint} built-in function of C always uses the mode which
4399 corresponds to the C data type @code{double} and the @code{nearbyintf}
4400 built-in function uses the mode which corresponds to the C data
4403 @cindex @code{rint@var{m}2} instruction pattern
4404 @item @samp{rint@var{m}2}
4405 Store the argument rounded according to the default rounding mode and
4406 raise the inexact exception when the result differs in value from
4409 The @code{rint} built-in function of C always uses the mode which
4410 corresponds to the C data type @code{double} and the @code{rintf}
4411 built-in function uses the mode which corresponds to the C data
4414 @cindex @code{lrint@var{m}@var{n}2}
4415 @item @samp{lrint@var{m}@var{n}2}
4416 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4417 point mode @var{n} as a signed number according to the current
4418 rounding mode and store in operand 0 (which has mode @var{n}).
4420 @cindex @code{lround@var{m}@var{n}2}
4421 @item @samp{lround@var{m}@var{n}2}
4422 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4423 point mode @var{n} as a signed number rounding to nearest and away
4424 from zero and store in operand 0 (which has mode @var{n}).
4426 @cindex @code{lfloor@var{m}@var{n}2}
4427 @item @samp{lfloor@var{m}@var{n}2}
4428 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4429 point mode @var{n} as a signed number rounding down and store in
4430 operand 0 (which has mode @var{n}).
4432 @cindex @code{lceil@var{m}@var{n}2}
4433 @item @samp{lceil@var{m}@var{n}2}
4434 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4435 point mode @var{n} as a signed number rounding up and store in
4436 operand 0 (which has mode @var{n}).
4438 @cindex @code{copysign@var{m}3} instruction pattern
4439 @item @samp{copysign@var{m}3}
4440 Store a value with the magnitude of operand 1 and the sign of operand
4443 The @code{copysign} built-in function of C always uses the mode which
4444 corresponds to the C data type @code{double} and the @code{copysignf}
4445 built-in function uses the mode which corresponds to the C data
4448 @cindex @code{ffs@var{m}2} instruction pattern
4449 @item @samp{ffs@var{m}2}
4450 Store into operand 0 one plus the index of the least significant 1-bit
4451 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
4452 of operand 0; operand 1's mode is specified by the instruction
4453 pattern, and the compiler will convert the operand to that mode before
4454 generating the instruction.
4456 The @code{ffs} built-in function of C always uses the mode which
4457 corresponds to the C data type @code{int}.
4459 @cindex @code{clz@var{m}2} instruction pattern
4460 @item @samp{clz@var{m}2}
4461 Store into operand 0 the number of leading 0-bits in @var{x}, starting
4462 at the most significant bit position. If @var{x} is 0, the
4463 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4464 the result is undefined or has a useful value.
4465 @var{m} is the mode of operand 0; operand 1's mode is
4466 specified by the instruction pattern, and the compiler will convert the
4467 operand to that mode before generating the instruction.
4469 @cindex @code{ctz@var{m}2} instruction pattern
4470 @item @samp{ctz@var{m}2}
4471 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
4472 at the least significant bit position. If @var{x} is 0, the
4473 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4474 the result is undefined or has a useful value.
4475 @var{m} is the mode of operand 0; operand 1's mode is
4476 specified by the instruction pattern, and the compiler will convert the
4477 operand to that mode before generating the instruction.
4479 @cindex @code{popcount@var{m}2} instruction pattern
4480 @item @samp{popcount@var{m}2}
4481 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
4482 mode of operand 0; operand 1's mode is specified by the instruction
4483 pattern, and the compiler will convert the operand to that mode before
4484 generating the instruction.
4486 @cindex @code{parity@var{m}2} instruction pattern
4487 @item @samp{parity@var{m}2}
4488 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
4489 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
4490 is specified by the instruction pattern, and the compiler will convert
4491 the operand to that mode before generating the instruction.
4493 @cindex @code{one_cmpl@var{m}2} instruction pattern
4494 @item @samp{one_cmpl@var{m}2}
4495 Store the bitwise-complement of operand 1 into operand 0.
4497 @cindex @code{movmem@var{m}} instruction pattern
4498 @item @samp{movmem@var{m}}
4499 Block move instruction. The destination and source blocks of memory
4500 are the first two operands, and both are @code{mem:BLK}s with an
4501 address in mode @code{Pmode}.
4503 The number of bytes to move is the third operand, in mode @var{m}.
4504 Usually, you specify @code{word_mode} for @var{m}. However, if you can
4505 generate better code knowing the range of valid lengths is smaller than
4506 those representable in a full word, you should provide a pattern with a
4507 mode corresponding to the range of values you can handle efficiently
4508 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
4509 that appear negative) and also a pattern with @code{word_mode}.
4511 The fourth operand is the known shared alignment of the source and
4512 destination, in the form of a @code{const_int} rtx. Thus, if the
4513 compiler knows that both source and destination are word-aligned,
4514 it may provide the value 4 for this operand.
4516 Optional operands 5 and 6 specify expected alignment and size of block
4517 respectively. The expected alignment differs from alignment in operand 4
4518 in a way that the blocks are not required to be aligned according to it in
4519 all cases. This expected alignment is also in bytes, just like operand 4.
4520 Expected size, when unknown, is set to @code{(const_int -1)}.
4522 Descriptions of multiple @code{movmem@var{m}} patterns can only be
4523 beneficial if the patterns for smaller modes have fewer restrictions
4524 on their first, second and fourth operands. Note that the mode @var{m}
4525 in @code{movmem@var{m}} does not impose any restriction on the mode of
4526 individually moved data units in the block.
4528 These patterns need not give special consideration to the possibility
4529 that the source and destination strings might overlap.
4531 @cindex @code{movstr} instruction pattern
4533 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
4534 an output operand in mode @code{Pmode}. The addresses of the
4535 destination and source strings are operands 1 and 2, and both are
4536 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
4537 the expansion of this pattern should store in operand 0 the address in
4538 which the @code{NUL} terminator was stored in the destination string.
4540 @cindex @code{setmem@var{m}} instruction pattern
4541 @item @samp{setmem@var{m}}
4542 Block set instruction. The destination string is the first operand,
4543 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
4544 number of bytes to set is the second operand, in mode @var{m}. The value to
4545 initialize the memory with is the third operand. Targets that only support the
4546 clearing of memory should reject any value that is not the constant 0. See
4547 @samp{movmem@var{m}} for a discussion of the choice of mode.
4549 The fourth operand is the known alignment of the destination, in the form
4550 of a @code{const_int} rtx. Thus, if the compiler knows that the
4551 destination is word-aligned, it may provide the value 4 for this
4554 Optional operands 5 and 6 specify expected alignment and size of block
4555 respectively. The expected alignment differs from alignment in operand 4
4556 in a way that the blocks are not required to be aligned according to it in
4557 all cases. This expected alignment is also in bytes, just like operand 4.
4558 Expected size, when unknown, is set to @code{(const_int -1)}.
4560 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
4562 @cindex @code{cmpstrn@var{m}} instruction pattern
4563 @item @samp{cmpstrn@var{m}}
4564 String compare instruction, with five operands. Operand 0 is the output;
4565 it has mode @var{m}. The remaining four operands are like the operands
4566 of @samp{movmem@var{m}}. The two memory blocks specified are compared
4567 byte by byte in lexicographic order starting at the beginning of each
4568 string. The instruction is not allowed to prefetch more than one byte
4569 at a time since either string may end in the first byte and reading past
4570 that may access an invalid page or segment and cause a fault. The
4571 effect of the instruction is to store a value in operand 0 whose sign
4572 indicates the result of the comparison.
4574 @cindex @code{cmpstr@var{m}} instruction pattern
4575 @item @samp{cmpstr@var{m}}
4576 String compare instruction, without known maximum length. Operand 0 is the
4577 output; it has mode @var{m}. The second and third operand are the blocks of
4578 memory to be compared; both are @code{mem:BLK} with an address in mode
4581 The fourth operand is the known shared alignment of the source and
4582 destination, in the form of a @code{const_int} rtx. Thus, if the
4583 compiler knows that both source and destination are word-aligned,
4584 it may provide the value 4 for this operand.
4586 The two memory blocks specified are compared byte by byte in lexicographic
4587 order starting at the beginning of each string. The instruction is not allowed
4588 to prefetch more than one byte at a time since either string may end in the
4589 first byte and reading past that may access an invalid page or segment and
4590 cause a fault. The effect of the instruction is to store a value in operand 0
4591 whose sign indicates the result of the comparison.
4593 @cindex @code{cmpmem@var{m}} instruction pattern
4594 @item @samp{cmpmem@var{m}}
4595 Block compare instruction, with five operands like the operands
4596 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
4597 byte by byte in lexicographic order starting at the beginning of each
4598 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
4599 any bytes in the two memory blocks. The effect of the instruction is
4600 to store a value in operand 0 whose sign indicates the result of the
4603 @cindex @code{strlen@var{m}} instruction pattern
4604 @item @samp{strlen@var{m}}
4605 Compute the length of a string, with three operands.
4606 Operand 0 is the result (of mode @var{m}), operand 1 is
4607 a @code{mem} referring to the first character of the string,
4608 operand 2 is the character to search for (normally zero),
4609 and operand 3 is a constant describing the known alignment
4610 of the beginning of the string.
4612 @cindex @code{float@var{m}@var{n}2} instruction pattern
4613 @item @samp{float@var{m}@var{n}2}
4614 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
4615 floating point mode @var{n} and store in operand 0 (which has mode
4618 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
4619 @item @samp{floatuns@var{m}@var{n}2}
4620 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
4621 to floating point mode @var{n} and store in operand 0 (which has mode
4624 @cindex @code{fix@var{m}@var{n}2} instruction pattern
4625 @item @samp{fix@var{m}@var{n}2}
4626 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4627 point mode @var{n} as a signed number and store in operand 0 (which
4628 has mode @var{n}). This instruction's result is defined only when
4629 the value of operand 1 is an integer.
4631 If the machine description defines this pattern, it also needs to
4632 define the @code{ftrunc} pattern.
4634 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
4635 @item @samp{fixuns@var{m}@var{n}2}
4636 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4637 point mode @var{n} as an unsigned number and store in operand 0 (which
4638 has mode @var{n}). This instruction's result is defined only when the
4639 value of operand 1 is an integer.
4641 @cindex @code{ftrunc@var{m}2} instruction pattern
4642 @item @samp{ftrunc@var{m}2}
4643 Convert operand 1 (valid for floating point mode @var{m}) to an
4644 integer value, still represented in floating point mode @var{m}, and
4645 store it in operand 0 (valid for floating point mode @var{m}).
4647 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
4648 @item @samp{fix_trunc@var{m}@var{n}2}
4649 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
4650 of mode @var{m} by converting the value to an integer.
4652 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
4653 @item @samp{fixuns_trunc@var{m}@var{n}2}
4654 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
4655 value of mode @var{m} by converting the value to an integer.
4657 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
4658 @item @samp{trunc@var{m}@var{n}2}
4659 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
4660 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4661 point or both floating point.
4663 @cindex @code{extend@var{m}@var{n}2} instruction pattern
4664 @item @samp{extend@var{m}@var{n}2}
4665 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4666 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4667 point or both floating point.
4669 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
4670 @item @samp{zero_extend@var{m}@var{n}2}
4671 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4672 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4675 @cindex @code{fract@var{m}@var{n}2} instruction pattern
4676 @item @samp{fract@var{m}@var{n}2}
4677 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4678 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4679 could be fixed-point to fixed-point, signed integer to fixed-point,
4680 fixed-point to signed integer, floating-point to fixed-point,
4681 or fixed-point to floating-point.
4682 When overflows or underflows happen, the results are undefined.
4684 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
4685 @item @samp{satfract@var{m}@var{n}2}
4686 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4687 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4688 could be fixed-point to fixed-point, signed integer to fixed-point,
4689 or floating-point to fixed-point.
4690 When overflows or underflows happen, the instruction saturates the
4691 results to the maximum or the minimum.
4693 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
4694 @item @samp{fractuns@var{m}@var{n}2}
4695 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4696 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4697 could be unsigned integer to fixed-point, or
4698 fixed-point to unsigned integer.
4699 When overflows or underflows happen, the results are undefined.
4701 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
4702 @item @samp{satfractuns@var{m}@var{n}2}
4703 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
4704 @var{n} and store in operand 0 (which has mode @var{n}).
4705 When overflows or underflows happen, the instruction saturates the
4706 results to the maximum or the minimum.
4708 @cindex @code{extv} instruction pattern
4710 Extract a bit-field from operand 1 (a register or memory operand), where
4711 operand 2 specifies the width in bits and operand 3 the starting bit,
4712 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
4713 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
4714 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
4715 be valid for @code{word_mode}.
4717 The RTL generation pass generates this instruction only with constants
4718 for operands 2 and 3 and the constant is never zero for operand 2.
4720 The bit-field value is sign-extended to a full word integer
4721 before it is stored in operand 0.
4723 @cindex @code{extzv} instruction pattern
4725 Like @samp{extv} except that the bit-field value is zero-extended.
4727 @cindex @code{insv} instruction pattern
4729 Store operand 3 (which must be valid for @code{word_mode}) into a
4730 bit-field in operand 0, where operand 1 specifies the width in bits and
4731 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
4732 @code{word_mode}; often @code{word_mode} is allowed only for registers.
4733 Operands 1 and 2 must be valid for @code{word_mode}.
4735 The RTL generation pass generates this instruction only with constants
4736 for operands 1 and 2 and the constant is never zero for operand 1.
4738 @cindex @code{mov@var{mode}cc} instruction pattern
4739 @item @samp{mov@var{mode}cc}
4740 Conditionally move operand 2 or operand 3 into operand 0 according to the
4741 comparison in operand 1. If the comparison is true, operand 2 is moved
4742 into operand 0, otherwise operand 3 is moved.
4744 The mode of the operands being compared need not be the same as the operands
4745 being moved. Some machines, sparc64 for example, have instructions that
4746 conditionally move an integer value based on the floating point condition
4747 codes and vice versa.
4749 If the machine does not have conditional move instructions, do not
4750 define these patterns.
4752 @cindex @code{add@var{mode}cc} instruction pattern
4753 @item @samp{add@var{mode}cc}
4754 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
4755 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
4756 comparison in operand 1. If the comparison is true, operand 2 is moved into
4757 operand 0, otherwise (operand 2 + operand 3) is moved.
4759 @cindex @code{cstore@var{mode}4} instruction pattern
4760 @item @samp{cstore@var{mode}4}
4761 Store zero or nonzero in operand 0 according to whether a comparison
4762 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
4763 are the first and second operand of the comparison, respectively.
4764 You specify the mode that operand 0 must have when you write the
4765 @code{match_operand} expression. The compiler automatically sees which
4766 mode you have used and supplies an operand of that mode.
4768 The value stored for a true condition must have 1 as its low bit, or
4769 else must be negative. Otherwise the instruction is not suitable and
4770 you should omit it from the machine description. You describe to the
4771 compiler exactly which value is stored by defining the macro
4772 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
4773 found that can be used for all the possible comparison operators, you
4774 should pick one and use a @code{define_expand} to map all results
4775 onto the one you chose.
4777 These operations may @code{FAIL}, but should do so only in relatively
4778 uncommon cases; if they would @code{FAIL} for common cases involving
4779 integer comparisons, it is best to restrict the predicates to not
4780 allow these operands. Likewise if a given comparison operator will
4781 always fail, independent of the operands (for floating-point modes, the
4782 @code{ordered_comparison_operator} predicate is often useful in this case).
4784 If this pattern is omitted, the compiler will generate a conditional
4785 branch---for example, it may copy a constant one to the target and branching
4786 around an assignment of zero to the target---or a libcall. If the predicate
4787 for operand 1 only rejects some operators, it will also try reordering the
4788 operands and/or inverting the result value (e.g.@: by an exclusive OR).
4789 These possibilities could be cheaper or equivalent to the instructions
4790 used for the @samp{cstore@var{mode}4} pattern followed by those required
4791 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
4792 case, you can and should make operand 1's predicate reject some operators
4793 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
4794 from the machine description.
4796 @cindex @code{cbranch@var{mode}4} instruction pattern
4797 @item @samp{cbranch@var{mode}4}
4798 Conditional branch instruction combined with a compare instruction.
4799 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
4800 first and second operands of the comparison, respectively. Operand 3
4801 is a @code{label_ref} that refers to the label to jump to.
4803 @cindex @code{jump} instruction pattern
4805 A jump inside a function; an unconditional branch. Operand 0 is the
4806 @code{label_ref} of the label to jump to. This pattern name is mandatory
4809 @cindex @code{call} instruction pattern
4811 Subroutine call instruction returning no value. Operand 0 is the
4812 function to call; operand 1 is the number of bytes of arguments pushed
4813 as a @code{const_int}; operand 2 is the number of registers used as
4816 On most machines, operand 2 is not actually stored into the RTL
4817 pattern. It is supplied for the sake of some RISC machines which need
4818 to put this information into the assembler code; they can put it in
4819 the RTL instead of operand 1.
4821 Operand 0 should be a @code{mem} RTX whose address is the address of the
4822 function. Note, however, that this address can be a @code{symbol_ref}
4823 expression even if it would not be a legitimate memory address on the
4824 target machine. If it is also not a valid argument for a call
4825 instruction, the pattern for this operation should be a
4826 @code{define_expand} (@pxref{Expander Definitions}) that places the
4827 address into a register and uses that register in the call instruction.
4829 @cindex @code{call_value} instruction pattern
4830 @item @samp{call_value}
4831 Subroutine call instruction returning a value. Operand 0 is the hard
4832 register in which the value is returned. There are three more
4833 operands, the same as the three operands of the @samp{call}
4834 instruction (but with numbers increased by one).
4836 Subroutines that return @code{BLKmode} objects use the @samp{call}
4839 @cindex @code{call_pop} instruction pattern
4840 @cindex @code{call_value_pop} instruction pattern
4841 @item @samp{call_pop}, @samp{call_value_pop}
4842 Similar to @samp{call} and @samp{call_value}, except used if defined and
4843 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
4844 that contains both the function call and a @code{set} to indicate the
4845 adjustment made to the frame pointer.
4847 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
4848 patterns increases the number of functions for which the frame pointer
4849 can be eliminated, if desired.
4851 @cindex @code{untyped_call} instruction pattern
4852 @item @samp{untyped_call}
4853 Subroutine call instruction returning a value of any type. Operand 0 is
4854 the function to call; operand 1 is a memory location where the result of
4855 calling the function is to be stored; operand 2 is a @code{parallel}
4856 expression where each element is a @code{set} expression that indicates
4857 the saving of a function return value into the result block.
4859 This instruction pattern should be defined to support
4860 @code{__builtin_apply} on machines where special instructions are needed
4861 to call a subroutine with arbitrary arguments or to save the value
4862 returned. This instruction pattern is required on machines that have
4863 multiple registers that can hold a return value
4864 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
4866 @cindex @code{return} instruction pattern
4868 Subroutine return instruction. This instruction pattern name should be
4869 defined only if a single instruction can do all the work of returning
4872 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
4873 RTL generation phase. In this case it is to support machines where
4874 multiple instructions are usually needed to return from a function, but
4875 some class of functions only requires one instruction to implement a
4876 return. Normally, the applicable functions are those which do not need
4877 to save any registers or allocate stack space.
4879 @findex reload_completed
4880 @findex leaf_function_p
4881 For such machines, the condition specified in this pattern should only
4882 be true when @code{reload_completed} is nonzero and the function's
4883 epilogue would only be a single instruction. For machines with register
4884 windows, the routine @code{leaf_function_p} may be used to determine if
4885 a register window push is required.
4887 Machines that have conditional return instructions should define patterns
4893 (if_then_else (match_operator
4894 0 "comparison_operator"
4895 [(cc0) (const_int 0)])
4902 where @var{condition} would normally be the same condition specified on the
4903 named @samp{return} pattern.
4905 @cindex @code{untyped_return} instruction pattern
4906 @item @samp{untyped_return}
4907 Untyped subroutine return instruction. This instruction pattern should
4908 be defined to support @code{__builtin_return} on machines where special
4909 instructions are needed to return a value of any type.
4911 Operand 0 is a memory location where the result of calling a function
4912 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
4913 expression where each element is a @code{set} expression that indicates
4914 the restoring of a function return value from the result block.
4916 @cindex @code{nop} instruction pattern
4918 No-op instruction. This instruction pattern name should always be defined
4919 to output a no-op in assembler code. @code{(const_int 0)} will do as an
4922 @cindex @code{indirect_jump} instruction pattern
4923 @item @samp{indirect_jump}
4924 An instruction to jump to an address which is operand zero.
4925 This pattern name is mandatory on all machines.
4927 @cindex @code{casesi} instruction pattern
4929 Instruction to jump through a dispatch table, including bounds checking.
4930 This instruction takes five operands:
4934 The index to dispatch on, which has mode @code{SImode}.
4937 The lower bound for indices in the table, an integer constant.
4940 The total range of indices in the table---the largest index
4941 minus the smallest one (both inclusive).
4944 A label that precedes the table itself.
4947 A label to jump to if the index has a value outside the bounds.
4950 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
4951 @code{jump_insn}. The number of elements in the table is one plus the
4952 difference between the upper bound and the lower bound.
4954 @cindex @code{tablejump} instruction pattern
4955 @item @samp{tablejump}
4956 Instruction to jump to a variable address. This is a low-level
4957 capability which can be used to implement a dispatch table when there
4958 is no @samp{casesi} pattern.
4960 This pattern requires two operands: the address or offset, and a label
4961 which should immediately precede the jump table. If the macro
4962 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
4963 operand is an offset which counts from the address of the table; otherwise,
4964 it is an absolute address to jump to. In either case, the first operand has
4967 The @samp{tablejump} insn is always the last insn before the jump
4968 table it uses. Its assembler code normally has no need to use the
4969 second operand, but you should incorporate it in the RTL pattern so
4970 that the jump optimizer will not delete the table as unreachable code.
4973 @cindex @code{decrement_and_branch_until_zero} instruction pattern
4974 @item @samp{decrement_and_branch_until_zero}
4975 Conditional branch instruction that decrements a register and
4976 jumps if the register is nonzero. Operand 0 is the register to
4977 decrement and test; operand 1 is the label to jump to if the
4978 register is nonzero. @xref{Looping Patterns}.
4980 This optional instruction pattern is only used by the combiner,
4981 typically for loops reversed by the loop optimizer when strength
4982 reduction is enabled.
4984 @cindex @code{doloop_end} instruction pattern
4985 @item @samp{doloop_end}
4986 Conditional branch instruction that decrements a register and jumps if
4987 the register is nonzero. This instruction takes five operands: Operand
4988 0 is the register to decrement and test; operand 1 is the number of loop
4989 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
4990 determined until run-time; operand 2 is the actual or estimated maximum
4991 number of iterations as a @code{const_int}; operand 3 is the number of
4992 enclosed loops as a @code{const_int} (an innermost loop has a value of
4993 1); operand 4 is the label to jump to if the register is nonzero.
4994 @xref{Looping Patterns}.
4996 This optional instruction pattern should be defined for machines with
4997 low-overhead looping instructions as the loop optimizer will try to
4998 modify suitable loops to utilize it. If nested low-overhead looping is
4999 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
5000 and make the pattern fail if operand 3 is not @code{const1_rtx}.
5001 Similarly, if the actual or estimated maximum number of iterations is
5002 too large for this instruction, make it fail.
5004 @cindex @code{doloop_begin} instruction pattern
5005 @item @samp{doloop_begin}
5006 Companion instruction to @code{doloop_end} required for machines that
5007 need to perform some initialization, such as loading special registers
5008 used by a low-overhead looping instruction. If initialization insns do
5009 not always need to be emitted, use a @code{define_expand}
5010 (@pxref{Expander Definitions}) and make it fail.
5013 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
5014 @item @samp{canonicalize_funcptr_for_compare}
5015 Canonicalize the function pointer in operand 1 and store the result
5018 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
5019 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
5020 and also has mode @code{Pmode}.
5022 Canonicalization of a function pointer usually involves computing
5023 the address of the function which would be called if the function
5024 pointer were used in an indirect call.
5026 Only define this pattern if function pointers on the target machine
5027 can have different values but still call the same function when
5028 used in an indirect call.
5030 @cindex @code{save_stack_block} instruction pattern
5031 @cindex @code{save_stack_function} instruction pattern
5032 @cindex @code{save_stack_nonlocal} instruction pattern
5033 @cindex @code{restore_stack_block} instruction pattern
5034 @cindex @code{restore_stack_function} instruction pattern
5035 @cindex @code{restore_stack_nonlocal} instruction pattern
5036 @item @samp{save_stack_block}
5037 @itemx @samp{save_stack_function}
5038 @itemx @samp{save_stack_nonlocal}
5039 @itemx @samp{restore_stack_block}
5040 @itemx @samp{restore_stack_function}
5041 @itemx @samp{restore_stack_nonlocal}
5042 Most machines save and restore the stack pointer by copying it to or
5043 from an object of mode @code{Pmode}. Do not define these patterns on
5046 Some machines require special handling for stack pointer saves and
5047 restores. On those machines, define the patterns corresponding to the
5048 non-standard cases by using a @code{define_expand} (@pxref{Expander
5049 Definitions}) that produces the required insns. The three types of
5050 saves and restores are:
5054 @samp{save_stack_block} saves the stack pointer at the start of a block
5055 that allocates a variable-sized object, and @samp{restore_stack_block}
5056 restores the stack pointer when the block is exited.
5059 @samp{save_stack_function} and @samp{restore_stack_function} do a
5060 similar job for the outermost block of a function and are used when the
5061 function allocates variable-sized objects or calls @code{alloca}. Only
5062 the epilogue uses the restored stack pointer, allowing a simpler save or
5063 restore sequence on some machines.
5066 @samp{save_stack_nonlocal} is used in functions that contain labels
5067 branched to by nested functions. It saves the stack pointer in such a
5068 way that the inner function can use @samp{restore_stack_nonlocal} to
5069 restore the stack pointer. The compiler generates code to restore the
5070 frame and argument pointer registers, but some machines require saving
5071 and restoring additional data such as register window information or
5072 stack backchains. Place insns in these patterns to save and restore any
5076 When saving the stack pointer, operand 0 is the save area and operand 1
5077 is the stack pointer. The mode used to allocate the save area defaults
5078 to @code{Pmode} but you can override that choice by defining the
5079 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
5080 specify an integral mode, or @code{VOIDmode} if no save area is needed
5081 for a particular type of save (either because no save is needed or
5082 because a machine-specific save area can be used). Operand 0 is the
5083 stack pointer and operand 1 is the save area for restore operations. If
5084 @samp{save_stack_block} is defined, operand 0 must not be
5085 @code{VOIDmode} since these saves can be arbitrarily nested.
5087 A save area is a @code{mem} that is at a constant offset from
5088 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
5089 nonlocal gotos and a @code{reg} in the other two cases.
5091 @cindex @code{allocate_stack} instruction pattern
5092 @item @samp{allocate_stack}
5093 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
5094 the stack pointer to create space for dynamically allocated data.
5096 Store the resultant pointer to this space into operand 0. If you
5097 are allocating space from the main stack, do this by emitting a
5098 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
5099 If you are allocating the space elsewhere, generate code to copy the
5100 location of the space to operand 0. In the latter case, you must
5101 ensure this space gets freed when the corresponding space on the main
5104 Do not define this pattern if all that must be done is the subtraction.
5105 Some machines require other operations such as stack probes or
5106 maintaining the back chain. Define this pattern to emit those
5107 operations in addition to updating the stack pointer.
5109 @cindex @code{check_stack} instruction pattern
5110 @item @samp{check_stack}
5111 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
5112 probing the stack, define this pattern to perform the needed check and signal
5113 an error if the stack has overflowed. The single operand is the address in
5114 the stack farthest from the current stack pointer that you need to validate.
5115 Normally, on platforms where this pattern is needed, you would obtain the
5116 stack limit from a global or thread-specific variable or register.
5118 @cindex @code{probe_stack} instruction pattern
5119 @item @samp{probe_stack}
5120 If stack checking (@pxref{Stack Checking}) can be done on your system by
5121 probing the stack but doing it with a ``store zero'' instruction is not valid
5122 or optimal, define this pattern to do the probing differently and signal an
5123 error if the stack has overflowed. The single operand is the memory reference
5124 in the stack that needs to be probed.
5126 @cindex @code{nonlocal_goto} instruction pattern
5127 @item @samp{nonlocal_goto}
5128 Emit code to generate a non-local goto, e.g., a jump from one function
5129 to a label in an outer function. This pattern has four arguments,
5130 each representing a value to be used in the jump. The first
5131 argument is to be loaded into the frame pointer, the second is
5132 the address to branch to (code to dispatch to the actual label),
5133 the third is the address of a location where the stack is saved,
5134 and the last is the address of the label, to be placed in the
5135 location for the incoming static chain.
5137 On most machines you need not define this pattern, since GCC will
5138 already generate the correct code, which is to load the frame pointer
5139 and static chain, restore the stack (using the
5140 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
5141 to the dispatcher. You need only define this pattern if this code will
5142 not work on your machine.
5144 @cindex @code{nonlocal_goto_receiver} instruction pattern
5145 @item @samp{nonlocal_goto_receiver}
5146 This pattern, if defined, contains code needed at the target of a
5147 nonlocal goto after the code already generated by GCC@. You will not
5148 normally need to define this pattern. A typical reason why you might
5149 need this pattern is if some value, such as a pointer to a global table,
5150 must be restored when the frame pointer is restored. Note that a nonlocal
5151 goto only occurs within a unit-of-translation, so a global table pointer
5152 that is shared by all functions of a given module need not be restored.
5153 There are no arguments.
5155 @cindex @code{exception_receiver} instruction pattern
5156 @item @samp{exception_receiver}
5157 This pattern, if defined, contains code needed at the site of an
5158 exception handler that isn't needed at the site of a nonlocal goto. You
5159 will not normally need to define this pattern. A typical reason why you
5160 might need this pattern is if some value, such as a pointer to a global
5161 table, must be restored after control flow is branched to the handler of
5162 an exception. There are no arguments.
5164 @cindex @code{builtin_setjmp_setup} instruction pattern
5165 @item @samp{builtin_setjmp_setup}
5166 This pattern, if defined, contains additional code needed to initialize
5167 the @code{jmp_buf}. You will not normally need to define this pattern.
5168 A typical reason why you might need this pattern is if some value, such
5169 as a pointer to a global table, must be restored. Though it is
5170 preferred that the pointer value be recalculated if possible (given the
5171 address of a label for instance). The single argument is a pointer to
5172 the @code{jmp_buf}. Note that the buffer is five words long and that
5173 the first three are normally used by the generic mechanism.
5175 @cindex @code{builtin_setjmp_receiver} instruction pattern
5176 @item @samp{builtin_setjmp_receiver}
5177 This pattern, if defined, contains code needed at the site of a
5178 built-in setjmp that isn't needed at the site of a nonlocal goto. You
5179 will not normally need to define this pattern. A typical reason why you
5180 might need this pattern is if some value, such as a pointer to a global
5181 table, must be restored. It takes one argument, which is the label
5182 to which builtin_longjmp transfered control; this pattern may be emitted
5183 at a small offset from that label.
5185 @cindex @code{builtin_longjmp} instruction pattern
5186 @item @samp{builtin_longjmp}
5187 This pattern, if defined, performs the entire action of the longjmp.
5188 You will not normally need to define this pattern unless you also define
5189 @code{builtin_setjmp_setup}. The single argument is a pointer to the
5192 @cindex @code{eh_return} instruction pattern
5193 @item @samp{eh_return}
5194 This pattern, if defined, affects the way @code{__builtin_eh_return},
5195 and thence the call frame exception handling library routines, are
5196 built. It is intended to handle non-trivial actions needed along
5197 the abnormal return path.
5199 The address of the exception handler to which the function should return
5200 is passed as operand to this pattern. It will normally need to copied by
5201 the pattern to some special register or memory location.
5202 If the pattern needs to determine the location of the target call
5203 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
5204 if defined; it will have already been assigned.
5206 If this pattern is not defined, the default action will be to simply
5207 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
5208 that macro or this pattern needs to be defined if call frame exception
5209 handling is to be used.
5211 @cindex @code{prologue} instruction pattern
5212 @anchor{prologue instruction pattern}
5213 @item @samp{prologue}
5214 This pattern, if defined, emits RTL for entry to a function. The function
5215 entry is responsible for setting up the stack frame, initializing the frame
5216 pointer register, saving callee saved registers, etc.
5218 Using a prologue pattern is generally preferred over defining
5219 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
5221 The @code{prologue} pattern is particularly useful for targets which perform
5222 instruction scheduling.
5224 @cindex @code{epilogue} instruction pattern
5225 @anchor{epilogue instruction pattern}
5226 @item @samp{epilogue}
5227 This pattern emits RTL for exit from a function. The function
5228 exit is responsible for deallocating the stack frame, restoring callee saved
5229 registers and emitting the return instruction.
5231 Using an epilogue pattern is generally preferred over defining
5232 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
5234 The @code{epilogue} pattern is particularly useful for targets which perform
5235 instruction scheduling or which have delay slots for their return instruction.
5237 @cindex @code{sibcall_epilogue} instruction pattern
5238 @item @samp{sibcall_epilogue}
5239 This pattern, if defined, emits RTL for exit from a function without the final
5240 branch back to the calling function. This pattern will be emitted before any
5241 sibling call (aka tail call) sites.
5243 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
5244 parameter passing or any stack slots for arguments passed to the current
5247 @cindex @code{trap} instruction pattern
5249 This pattern, if defined, signals an error, typically by causing some
5250 kind of signal to be raised. Among other places, it is used by the Java
5251 front end to signal `invalid array index' exceptions.
5253 @cindex @code{ctrap@var{MM}4} instruction pattern
5254 @item @samp{ctrap@var{MM}4}
5255 Conditional trap instruction. Operand 0 is a piece of RTL which
5256 performs a comparison, and operands 1 and 2 are the arms of the
5257 comparison. Operand 3 is the trap code, an integer.
5259 A typical @code{ctrap} pattern looks like
5262 (define_insn "ctrapsi4"
5263 [(trap_if (match_operator 0 "trap_operator"
5264 [(match_operand 1 "register_operand")
5265 (match_operand 2 "immediate_operand")])
5266 (match_operand 3 "const_int_operand" "i"))]
5271 @cindex @code{prefetch} instruction pattern
5272 @item @samp{prefetch}
5274 This pattern, if defined, emits code for a non-faulting data prefetch
5275 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
5276 is a constant 1 if the prefetch is preparing for a write to the memory
5277 address, or a constant 0 otherwise. Operand 2 is the expected degree of
5278 temporal locality of the data and is a value between 0 and 3, inclusive; 0
5279 means that the data has no temporal locality, so it need not be left in the
5280 cache after the access; 3 means that the data has a high degree of temporal
5281 locality and should be left in all levels of cache possible; 1 and 2 mean,
5282 respectively, a low or moderate degree of temporal locality.
5284 Targets that do not support write prefetches or locality hints can ignore
5285 the values of operands 1 and 2.
5287 @cindex @code{blockage} instruction pattern
5288 @item @samp{blockage}
5290 This pattern defines a pseudo insn that prevents the instruction
5291 scheduler from moving instructions across the boundary defined by the
5292 blockage insn. Normally an UNSPEC_VOLATILE pattern.
5294 @cindex @code{memory_barrier} instruction pattern
5295 @item @samp{memory_barrier}
5297 If the target memory model is not fully synchronous, then this pattern
5298 should be defined to an instruction that orders both loads and stores
5299 before the instruction with respect to loads and stores after the instruction.
5300 This pattern has no operands.
5302 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
5303 @item @samp{sync_compare_and_swap@var{mode}}
5305 This pattern, if defined, emits code for an atomic compare-and-swap
5306 operation. Operand 1 is the memory on which the atomic operation is
5307 performed. Operand 2 is the ``old'' value to be compared against the
5308 current contents of the memory location. Operand 3 is the ``new'' value
5309 to store in the memory if the compare succeeds. Operand 0 is the result
5310 of the operation; it should contain the contents of the memory
5311 before the operation. If the compare succeeds, this should obviously be
5312 a copy of operand 2.
5314 This pattern must show that both operand 0 and operand 1 are modified.
5316 This pattern must issue any memory barrier instructions such that all
5317 memory operations before the atomic operation occur before the atomic
5318 operation and all memory operations after the atomic operation occur
5319 after the atomic operation.
5321 For targets where the success or failure of the compare-and-swap
5322 operation is available via the status flags, it is possible to
5323 avoid a separate compare operation and issue the subsequent
5324 branch or store-flag operation immediately after the compare-and-swap.
5325 To this end, GCC will look for a @code{MODE_CC} set in the
5326 output of @code{sync_compare_and_swap@var{mode}}; if the machine
5327 description includes such a set, the target should also define special
5328 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
5329 be able to take the destination of the @code{MODE_CC} set and pass it
5330 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
5331 operand of the comparison (the second will be @code{(const_int 0)}).
5333 @cindex @code{sync_add@var{mode}} instruction pattern
5334 @cindex @code{sync_sub@var{mode}} instruction pattern
5335 @cindex @code{sync_ior@var{mode}} instruction pattern
5336 @cindex @code{sync_and@var{mode}} instruction pattern
5337 @cindex @code{sync_xor@var{mode}} instruction pattern
5338 @cindex @code{sync_nand@var{mode}} instruction pattern
5339 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
5340 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
5341 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
5343 These patterns emit code for an atomic operation on memory.
5344 Operand 0 is the memory on which the atomic operation is performed.
5345 Operand 1 is the second operand to the binary operator.
5347 This pattern must issue any memory barrier instructions such that all
5348 memory operations before the atomic operation occur before the atomic
5349 operation and all memory operations after the atomic operation occur
5350 after the atomic operation.
5352 If these patterns are not defined, the operation will be constructed
5353 from a compare-and-swap operation, if defined.
5355 @cindex @code{sync_old_add@var{mode}} instruction pattern
5356 @cindex @code{sync_old_sub@var{mode}} instruction pattern
5357 @cindex @code{sync_old_ior@var{mode}} instruction pattern
5358 @cindex @code{sync_old_and@var{mode}} instruction pattern
5359 @cindex @code{sync_old_xor@var{mode}} instruction pattern
5360 @cindex @code{sync_old_nand@var{mode}} instruction pattern
5361 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
5362 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
5363 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
5365 These patterns are emit code for an atomic operation on memory,
5366 and return the value that the memory contained before the operation.
5367 Operand 0 is the result value, operand 1 is the memory on which the
5368 atomic operation is performed, and operand 2 is the second operand
5369 to the binary operator.
5371 This pattern must issue any memory barrier instructions such that all
5372 memory operations before the atomic operation occur before the atomic
5373 operation and all memory operations after the atomic operation occur
5374 after the atomic operation.
5376 If these patterns are not defined, the operation will be constructed
5377 from a compare-and-swap operation, if defined.
5379 @cindex @code{sync_new_add@var{mode}} instruction pattern
5380 @cindex @code{sync_new_sub@var{mode}} instruction pattern
5381 @cindex @code{sync_new_ior@var{mode}} instruction pattern
5382 @cindex @code{sync_new_and@var{mode}} instruction pattern
5383 @cindex @code{sync_new_xor@var{mode}} instruction pattern
5384 @cindex @code{sync_new_nand@var{mode}} instruction pattern
5385 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
5386 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
5387 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
5389 These patterns are like their @code{sync_old_@var{op}} counterparts,
5390 except that they return the value that exists in the memory location
5391 after the operation, rather than before the operation.
5393 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
5394 @item @samp{sync_lock_test_and_set@var{mode}}
5396 This pattern takes two forms, based on the capabilities of the target.
5397 In either case, operand 0 is the result of the operand, operand 1 is
5398 the memory on which the atomic operation is performed, and operand 2
5399 is the value to set in the lock.
5401 In the ideal case, this operation is an atomic exchange operation, in
5402 which the previous value in memory operand is copied into the result
5403 operand, and the value operand is stored in the memory operand.
5405 For less capable targets, any value operand that is not the constant 1
5406 should be rejected with @code{FAIL}. In this case the target may use
5407 an atomic test-and-set bit operation. The result operand should contain
5408 1 if the bit was previously set and 0 if the bit was previously clear.
5409 The true contents of the memory operand are implementation defined.
5411 This pattern must issue any memory barrier instructions such that the
5412 pattern as a whole acts as an acquire barrier, that is all memory
5413 operations after the pattern do not occur until the lock is acquired.
5415 If this pattern is not defined, the operation will be constructed from
5416 a compare-and-swap operation, if defined.
5418 @cindex @code{sync_lock_release@var{mode}} instruction pattern
5419 @item @samp{sync_lock_release@var{mode}}
5421 This pattern, if defined, releases a lock set by
5422 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
5423 that contains the lock; operand 1 is the value to store in the lock.
5425 If the target doesn't implement full semantics for
5426 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
5427 the constant 0 should be rejected with @code{FAIL}, and the true contents
5428 of the memory operand are implementation defined.
5430 This pattern must issue any memory barrier instructions such that the
5431 pattern as a whole acts as a release barrier, that is the lock is
5432 released only after all previous memory operations have completed.
5434 If this pattern is not defined, then a @code{memory_barrier} pattern
5435 will be emitted, followed by a store of the value to the memory operand.
5437 @cindex @code{stack_protect_set} instruction pattern
5438 @item @samp{stack_protect_set}
5440 This pattern, if defined, moves a @code{Pmode} value from the memory
5441 in operand 1 to the memory in operand 0 without leaving the value in
5442 a register afterward. This is to avoid leaking the value some place
5443 that an attacker might use to rewrite the stack guard slot after
5444 having clobbered it.
5446 If this pattern is not defined, then a plain move pattern is generated.
5448 @cindex @code{stack_protect_test} instruction pattern
5449 @item @samp{stack_protect_test}
5451 This pattern, if defined, compares a @code{Pmode} value from the
5452 memory in operand 1 with the memory in operand 0 without leaving the
5453 value in a register afterward and branches to operand 2 if the values
5456 If this pattern is not defined, then a plain compare pattern and
5457 conditional branch pattern is used.
5459 @cindex @code{clear_cache} instruction pattern
5460 @item @samp{clear_cache}
5462 This pattern, if defined, flushes the instruction cache for a region of
5463 memory. The region is bounded to by the Pmode pointers in operand 0
5464 inclusive and operand 1 exclusive.
5466 If this pattern is not defined, a call to the library function
5467 @code{__clear_cache} is used.
5472 @c Each of the following nodes are wrapped in separate
5473 @c "@ifset INTERNALS" to work around memory limits for the default
5474 @c configuration in older tetex distributions. Known to not work:
5475 @c tetex-1.0.7, known to work: tetex-2.0.2.
5477 @node Pattern Ordering
5478 @section When the Order of Patterns Matters
5479 @cindex Pattern Ordering
5480 @cindex Ordering of Patterns
5482 Sometimes an insn can match more than one instruction pattern. Then the
5483 pattern that appears first in the machine description is the one used.
5484 Therefore, more specific patterns (patterns that will match fewer things)
5485 and faster instructions (those that will produce better code when they
5486 do match) should usually go first in the description.
5488 In some cases the effect of ordering the patterns can be used to hide
5489 a pattern when it is not valid. For example, the 68000 has an
5490 instruction for converting a fullword to floating point and another
5491 for converting a byte to floating point. An instruction converting
5492 an integer to floating point could match either one. We put the
5493 pattern to convert the fullword first to make sure that one will
5494 be used rather than the other. (Otherwise a large integer might
5495 be generated as a single-byte immediate quantity, which would not work.)
5496 Instead of using this pattern ordering it would be possible to make the
5497 pattern for convert-a-byte smart enough to deal properly with any
5502 @node Dependent Patterns
5503 @section Interdependence of Patterns
5504 @cindex Dependent Patterns
5505 @cindex Interdependence of Patterns
5507 In some cases machines support instructions identical except for the
5508 machine mode of one or more operands. For example, there may be
5509 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
5513 (set (match_operand:SI 0 @dots{})
5514 (extend:SI (match_operand:HI 1 @dots{})))
5516 (set (match_operand:SI 0 @dots{})
5517 (extend:SI (match_operand:QI 1 @dots{})))
5521 Constant integers do not specify a machine mode, so an instruction to
5522 extend a constant value could match either pattern. The pattern it
5523 actually will match is the one that appears first in the file. For correct
5524 results, this must be the one for the widest possible mode (@code{HImode},
5525 here). If the pattern matches the @code{QImode} instruction, the results
5526 will be incorrect if the constant value does not actually fit that mode.
5528 Such instructions to extend constants are rarely generated because they are
5529 optimized away, but they do occasionally happen in nonoptimized
5532 If a constraint in a pattern allows a constant, the reload pass may
5533 replace a register with a constant permitted by the constraint in some
5534 cases. Similarly for memory references. Because of this substitution,
5535 you should not provide separate patterns for increment and decrement
5536 instructions. Instead, they should be generated from the same pattern
5537 that supports register-register add insns by examining the operands and
5538 generating the appropriate machine instruction.
5543 @section Defining Jump Instruction Patterns
5544 @cindex jump instruction patterns
5545 @cindex defining jump instruction patterns
5547 GCC does not assume anything about how the machine realizes jumps.
5548 The machine description should define a single pattern, usually
5549 a @code{define_expand}, which expands to all the required insns.
5551 Usually, this would be a comparison insn to set the condition code
5552 and a separate branch insn testing the condition code and branching
5553 or not according to its value. For many machines, however,
5554 separating compares and branches is limiting, which is why the
5555 more flexible approach with one @code{define_expand} is used in GCC.
5556 The machine description becomes clearer for architectures that
5557 have compare-and-branch instructions but no condition code. It also
5558 works better when different sets of comparison operators are supported
5559 by different kinds of conditional branches (e.g. integer vs. floating-point),
5560 or by conditional branches with respect to conditional stores.
5562 Two separate insns are always used if the machine description represents
5563 a condition code register using the legacy RTL expression @code{(cc0)},
5564 and on most machines that use a separate condition code register
5565 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
5566 fact, the set and use of the condition code must be separate and
5567 adjacent@footnote{@code{note} insns can separate them, though.}, thus
5568 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
5569 so that the comparison and branch insns could be located from each other
5570 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
5572 Even in this case having a single entry point for conditional branches
5573 is advantageous, because it handles equally well the case where a single
5574 comparison instruction records the results of both signed and unsigned
5575 comparison of the given operands (with the branch insns coming in distinct
5576 signed and unsigned flavors) as in the x86 or SPARC, and the case where
5577 there are distinct signed and unsigned compare instructions and only
5578 one set of conditional branch instructions as in the PowerPC.
5582 @node Looping Patterns
5583 @section Defining Looping Instruction Patterns
5584 @cindex looping instruction patterns
5585 @cindex defining looping instruction patterns
5587 Some machines have special jump instructions that can be utilized to
5588 make loops more efficient. A common example is the 68000 @samp{dbra}
5589 instruction which performs a decrement of a register and a branch if the
5590 result was greater than zero. Other machines, in particular digital
5591 signal processors (DSPs), have special block repeat instructions to
5592 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
5593 DSPs have a block repeat instruction that loads special registers to
5594 mark the top and end of a loop and to count the number of loop
5595 iterations. This avoids the need for fetching and executing a
5596 @samp{dbra}-like instruction and avoids pipeline stalls associated with
5599 GCC has three special named patterns to support low overhead looping.
5600 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
5601 and @samp{doloop_end}. The first pattern,
5602 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
5603 generation but may be emitted during the instruction combination phase.
5604 This requires the assistance of the loop optimizer, using information
5605 collected during strength reduction, to reverse a loop to count down to
5606 zero. Some targets also require the loop optimizer to add a
5607 @code{REG_NONNEG} note to indicate that the iteration count is always
5608 positive. This is needed if the target performs a signed loop
5609 termination test. For example, the 68000 uses a pattern similar to the
5610 following for its @code{dbra} instruction:
5614 (define_insn "decrement_and_branch_until_zero"
5617 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
5620 (label_ref (match_operand 1 "" ""))
5623 (plus:SI (match_dup 0)
5625 "find_reg_note (insn, REG_NONNEG, 0)"
5630 Note that since the insn is both a jump insn and has an output, it must
5631 deal with its own reloads, hence the `m' constraints. Also note that
5632 since this insn is generated by the instruction combination phase
5633 combining two sequential insns together into an implicit parallel insn,
5634 the iteration counter needs to be biased by the same amount as the
5635 decrement operation, in this case @minus{}1. Note that the following similar
5636 pattern will not be matched by the combiner.
5640 (define_insn "decrement_and_branch_until_zero"
5643 (ge (match_operand:SI 0 "general_operand" "+d*am")
5645 (label_ref (match_operand 1 "" ""))
5648 (plus:SI (match_dup 0)
5650 "find_reg_note (insn, REG_NONNEG, 0)"
5655 The other two special looping patterns, @samp{doloop_begin} and
5656 @samp{doloop_end}, are emitted by the loop optimizer for certain
5657 well-behaved loops with a finite number of loop iterations using
5658 information collected during strength reduction.
5660 The @samp{doloop_end} pattern describes the actual looping instruction
5661 (or the implicit looping operation) and the @samp{doloop_begin} pattern
5662 is an optional companion pattern that can be used for initialization
5663 needed for some low-overhead looping instructions.
5665 Note that some machines require the actual looping instruction to be
5666 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
5667 the true RTL for a looping instruction at the top of the loop can cause
5668 problems with flow analysis. So instead, a dummy @code{doloop} insn is
5669 emitted at the end of the loop. The machine dependent reorg pass checks
5670 for the presence of this @code{doloop} insn and then searches back to
5671 the top of the loop, where it inserts the true looping insn (provided
5672 there are no instructions in the loop which would cause problems). Any
5673 additional labels can be emitted at this point. In addition, if the
5674 desired special iteration counter register was not allocated, this
5675 machine dependent reorg pass could emit a traditional compare and jump
5678 The essential difference between the
5679 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
5680 patterns is that the loop optimizer allocates an additional pseudo
5681 register for the latter as an iteration counter. This pseudo register
5682 cannot be used within the loop (i.e., general induction variables cannot
5683 be derived from it), however, in many cases the loop induction variable
5684 may become redundant and removed by the flow pass.
5689 @node Insn Canonicalizations
5690 @section Canonicalization of Instructions
5691 @cindex canonicalization of instructions
5692 @cindex insn canonicalization
5694 There are often cases where multiple RTL expressions could represent an
5695 operation performed by a single machine instruction. This situation is
5696 most commonly encountered with logical, branch, and multiply-accumulate
5697 instructions. In such cases, the compiler attempts to convert these
5698 multiple RTL expressions into a single canonical form to reduce the
5699 number of insn patterns required.
5701 In addition to algebraic simplifications, following canonicalizations
5706 For commutative and comparison operators, a constant is always made the
5707 second operand. If a machine only supports a constant as the second
5708 operand, only patterns that match a constant in the second operand need
5712 For associative operators, a sequence of operators will always chain
5713 to the left; for instance, only the left operand of an integer @code{plus}
5714 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
5715 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
5716 @code{umax} are associative when applied to integers, and sometimes to
5720 @cindex @code{neg}, canonicalization of
5721 @cindex @code{not}, canonicalization of
5722 @cindex @code{mult}, canonicalization of
5723 @cindex @code{plus}, canonicalization of
5724 @cindex @code{minus}, canonicalization of
5725 For these operators, if only one operand is a @code{neg}, @code{not},
5726 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
5730 In combinations of @code{neg}, @code{mult}, @code{plus}, and
5731 @code{minus}, the @code{neg} operations (if any) will be moved inside
5732 the operations as far as possible. For instance,
5733 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
5734 @code{(plus (mult (neg B) C) A)} is canonicalized as
5735 @code{(minus A (mult B C))}.
5737 @cindex @code{compare}, canonicalization of
5739 For the @code{compare} operator, a constant is always the second operand
5740 if the first argument is a condition code register or @code{(cc0)}.
5743 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
5744 @code{minus} is made the first operand under the same conditions as
5748 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
5749 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
5753 @code{(minus @var{x} (const_int @var{n}))} is converted to
5754 @code{(plus @var{x} (const_int @var{-n}))}.
5757 Within address computations (i.e., inside @code{mem}), a left shift is
5758 converted into the appropriate multiplication by a power of two.
5760 @cindex @code{ior}, canonicalization of
5761 @cindex @code{and}, canonicalization of
5762 @cindex De Morgan's law
5764 De Morgan's Law is used to move bitwise negation inside a bitwise
5765 logical-and or logical-or operation. If this results in only one
5766 operand being a @code{not} expression, it will be the first one.
5768 A machine that has an instruction that performs a bitwise logical-and of one
5769 operand with the bitwise negation of the other should specify the pattern
5770 for that instruction as
5774 [(set (match_operand:@var{m} 0 @dots{})
5775 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5776 (match_operand:@var{m} 2 @dots{})))]
5782 Similarly, a pattern for a ``NAND'' instruction should be written
5786 [(set (match_operand:@var{m} 0 @dots{})
5787 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5788 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
5793 In both cases, it is not necessary to include patterns for the many
5794 logically equivalent RTL expressions.
5796 @cindex @code{xor}, canonicalization of
5798 The only possible RTL expressions involving both bitwise exclusive-or
5799 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
5800 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
5803 The sum of three items, one of which is a constant, will only appear in
5807 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
5810 @cindex @code{zero_extract}, canonicalization of
5811 @cindex @code{sign_extract}, canonicalization of
5813 Equality comparisons of a group of bits (usually a single bit) with zero
5814 will be written using @code{zero_extract} rather than the equivalent
5815 @code{and} or @code{sign_extract} operations.
5819 Further canonicalization rules are defined in the function
5820 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
5824 @node Expander Definitions
5825 @section Defining RTL Sequences for Code Generation
5826 @cindex expander definitions
5827 @cindex code generation RTL sequences
5828 @cindex defining RTL sequences for code generation
5830 On some target machines, some standard pattern names for RTL generation
5831 cannot be handled with single insn, but a sequence of RTL insns can
5832 represent them. For these target machines, you can write a
5833 @code{define_expand} to specify how to generate the sequence of RTL@.
5835 @findex define_expand
5836 A @code{define_expand} is an RTL expression that looks almost like a
5837 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
5838 only for RTL generation and it can produce more than one RTL insn.
5840 A @code{define_expand} RTX has four operands:
5844 The name. Each @code{define_expand} must have a name, since the only
5845 use for it is to refer to it by name.
5848 The RTL template. This is a vector of RTL expressions representing
5849 a sequence of separate instructions. Unlike @code{define_insn}, there
5850 is no implicit surrounding @code{PARALLEL}.
5853 The condition, a string containing a C expression. This expression is
5854 used to express how the availability of this pattern depends on
5855 subclasses of target machine, selected by command-line options when GCC
5856 is run. This is just like the condition of a @code{define_insn} that
5857 has a standard name. Therefore, the condition (if present) may not
5858 depend on the data in the insn being matched, but only the
5859 target-machine-type flags. The compiler needs to test these conditions
5860 during initialization in order to learn exactly which named instructions
5861 are available in a particular run.
5864 The preparation statements, a string containing zero or more C
5865 statements which are to be executed before RTL code is generated from
5868 Usually these statements prepare temporary registers for use as
5869 internal operands in the RTL template, but they can also generate RTL
5870 insns directly by calling routines such as @code{emit_insn}, etc.
5871 Any such insns precede the ones that come from the RTL template.
5874 Every RTL insn emitted by a @code{define_expand} must match some
5875 @code{define_insn} in the machine description. Otherwise, the compiler
5876 will crash when trying to generate code for the insn or trying to optimize
5879 The RTL template, in addition to controlling generation of RTL insns,
5880 also describes the operands that need to be specified when this pattern
5881 is used. In particular, it gives a predicate for each operand.
5883 A true operand, which needs to be specified in order to generate RTL from
5884 the pattern, should be described with a @code{match_operand} in its first
5885 occurrence in the RTL template. This enters information on the operand's
5886 predicate into the tables that record such things. GCC uses the
5887 information to preload the operand into a register if that is required for
5888 valid RTL code. If the operand is referred to more than once, subsequent
5889 references should use @code{match_dup}.
5891 The RTL template may also refer to internal ``operands'' which are
5892 temporary registers or labels used only within the sequence made by the
5893 @code{define_expand}. Internal operands are substituted into the RTL
5894 template with @code{match_dup}, never with @code{match_operand}. The
5895 values of the internal operands are not passed in as arguments by the
5896 compiler when it requests use of this pattern. Instead, they are computed
5897 within the pattern, in the preparation statements. These statements
5898 compute the values and store them into the appropriate elements of
5899 @code{operands} so that @code{match_dup} can find them.
5901 There are two special macros defined for use in the preparation statements:
5902 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
5909 Use the @code{DONE} macro to end RTL generation for the pattern. The
5910 only RTL insns resulting from the pattern on this occasion will be
5911 those already emitted by explicit calls to @code{emit_insn} within the
5912 preparation statements; the RTL template will not be generated.
5916 Make the pattern fail on this occasion. When a pattern fails, it means
5917 that the pattern was not truly available. The calling routines in the
5918 compiler will try other strategies for code generation using other patterns.
5920 Failure is currently supported only for binary (addition, multiplication,
5921 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
5925 If the preparation falls through (invokes neither @code{DONE} nor
5926 @code{FAIL}), then the @code{define_expand} acts like a
5927 @code{define_insn} in that the RTL template is used to generate the
5930 The RTL template is not used for matching, only for generating the
5931 initial insn list. If the preparation statement always invokes
5932 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
5933 list of operands, such as this example:
5937 (define_expand "addsi3"
5938 [(match_operand:SI 0 "register_operand" "")
5939 (match_operand:SI 1 "register_operand" "")
5940 (match_operand:SI 2 "register_operand" "")]
5946 handle_add (operands[0], operands[1], operands[2]);
5952 Here is an example, the definition of left-shift for the SPUR chip:
5956 (define_expand "ashlsi3"
5957 [(set (match_operand:SI 0 "register_operand" "")
5961 (match_operand:SI 1 "register_operand" "")
5962 (match_operand:SI 2 "nonmemory_operand" "")))]
5971 if (GET_CODE (operands[2]) != CONST_INT
5972 || (unsigned) INTVAL (operands[2]) > 3)
5979 This example uses @code{define_expand} so that it can generate an RTL insn
5980 for shifting when the shift-count is in the supported range of 0 to 3 but
5981 fail in other cases where machine insns aren't available. When it fails,
5982 the compiler tries another strategy using different patterns (such as, a
5985 If the compiler were able to handle nontrivial condition-strings in
5986 patterns with names, then it would be possible to use a
5987 @code{define_insn} in that case. Here is another case (zero-extension
5988 on the 68000) which makes more use of the power of @code{define_expand}:
5991 (define_expand "zero_extendhisi2"
5992 [(set (match_operand:SI 0 "general_operand" "")
5994 (set (strict_low_part
5998 (match_operand:HI 1 "general_operand" ""))]
6000 "operands[1] = make_safe_from (operands[1], operands[0]);")
6004 @findex make_safe_from
6005 Here two RTL insns are generated, one to clear the entire output operand
6006 and the other to copy the input operand into its low half. This sequence
6007 is incorrect if the input operand refers to [the old value of] the output
6008 operand, so the preparation statement makes sure this isn't so. The
6009 function @code{make_safe_from} copies the @code{operands[1]} into a
6010 temporary register if it refers to @code{operands[0]}. It does this
6011 by emitting another RTL insn.
6013 Finally, a third example shows the use of an internal operand.
6014 Zero-extension on the SPUR chip is done by @code{and}-ing the result
6015 against a halfword mask. But this mask cannot be represented by a
6016 @code{const_int} because the constant value is too large to be legitimate
6017 on this machine. So it must be copied into a register with
6018 @code{force_reg} and then the register used in the @code{and}.
6021 (define_expand "zero_extendhisi2"
6022 [(set (match_operand:SI 0 "register_operand" "")
6024 (match_operand:HI 1 "register_operand" "")
6029 = force_reg (SImode, GEN_INT (65535)); ")
6032 @emph{Note:} If the @code{define_expand} is used to serve a
6033 standard binary or unary arithmetic operation or a bit-field operation,
6034 then the last insn it generates must not be a @code{code_label},
6035 @code{barrier} or @code{note}. It must be an @code{insn},
6036 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
6037 at the end, emit an insn to copy the result of the operation into
6038 itself. Such an insn will generate no code, but it can avoid problems
6043 @node Insn Splitting
6044 @section Defining How to Split Instructions
6045 @cindex insn splitting
6046 @cindex instruction splitting
6047 @cindex splitting instructions
6049 There are two cases where you should specify how to split a pattern
6050 into multiple insns. On machines that have instructions requiring
6051 delay slots (@pxref{Delay Slots}) or that have instructions whose
6052 output is not available for multiple cycles (@pxref{Processor pipeline
6053 description}), the compiler phases that optimize these cases need to
6054 be able to move insns into one-instruction delay slots. However, some
6055 insns may generate more than one machine instruction. These insns
6056 cannot be placed into a delay slot.
6058 Often you can rewrite the single insn as a list of individual insns,
6059 each corresponding to one machine instruction. The disadvantage of
6060 doing so is that it will cause the compilation to be slower and require
6061 more space. If the resulting insns are too complex, it may also
6062 suppress some optimizations. The compiler splits the insn if there is a
6063 reason to believe that it might improve instruction or delay slot
6066 The insn combiner phase also splits putative insns. If three insns are
6067 merged into one insn with a complex expression that cannot be matched by
6068 some @code{define_insn} pattern, the combiner phase attempts to split
6069 the complex pattern into two insns that are recognized. Usually it can
6070 break the complex pattern into two patterns by splitting out some
6071 subexpression. However, in some other cases, such as performing an
6072 addition of a large constant in two insns on a RISC machine, the way to
6073 split the addition into two insns is machine-dependent.
6075 @findex define_split
6076 The @code{define_split} definition tells the compiler how to split a
6077 complex insn into several simpler insns. It looks like this:
6081 [@var{insn-pattern}]
6083 [@var{new-insn-pattern-1}
6084 @var{new-insn-pattern-2}
6086 "@var{preparation-statements}")
6089 @var{insn-pattern} is a pattern that needs to be split and
6090 @var{condition} is the final condition to be tested, as in a
6091 @code{define_insn}. When an insn matching @var{insn-pattern} and
6092 satisfying @var{condition} is found, it is replaced in the insn list
6093 with the insns given by @var{new-insn-pattern-1},
6094 @var{new-insn-pattern-2}, etc.
6096 The @var{preparation-statements} are similar to those statements that
6097 are specified for @code{define_expand} (@pxref{Expander Definitions})
6098 and are executed before the new RTL is generated to prepare for the
6099 generated code or emit some insns whose pattern is not fixed. Unlike
6100 those in @code{define_expand}, however, these statements must not
6101 generate any new pseudo-registers. Once reload has completed, they also
6102 must not allocate any space in the stack frame.
6104 Patterns are matched against @var{insn-pattern} in two different
6105 circumstances. If an insn needs to be split for delay slot scheduling
6106 or insn scheduling, the insn is already known to be valid, which means
6107 that it must have been matched by some @code{define_insn} and, if
6108 @code{reload_completed} is nonzero, is known to satisfy the constraints
6109 of that @code{define_insn}. In that case, the new insn patterns must
6110 also be insns that are matched by some @code{define_insn} and, if
6111 @code{reload_completed} is nonzero, must also satisfy the constraints
6112 of those definitions.
6114 As an example of this usage of @code{define_split}, consider the following
6115 example from @file{a29k.md}, which splits a @code{sign_extend} from
6116 @code{HImode} to @code{SImode} into a pair of shift insns:
6120 [(set (match_operand:SI 0 "gen_reg_operand" "")
6121 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
6124 (ashift:SI (match_dup 1)
6127 (ashiftrt:SI (match_dup 0)
6130 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
6133 When the combiner phase tries to split an insn pattern, it is always the
6134 case that the pattern is @emph{not} matched by any @code{define_insn}.
6135 The combiner pass first tries to split a single @code{set} expression
6136 and then the same @code{set} expression inside a @code{parallel}, but
6137 followed by a @code{clobber} of a pseudo-reg to use as a scratch
6138 register. In these cases, the combiner expects exactly two new insn
6139 patterns to be generated. It will verify that these patterns match some
6140 @code{define_insn} definitions, so you need not do this test in the
6141 @code{define_split} (of course, there is no point in writing a
6142 @code{define_split} that will never produce insns that match).
6144 Here is an example of this use of @code{define_split}, taken from
6149 [(set (match_operand:SI 0 "gen_reg_operand" "")
6150 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
6151 (match_operand:SI 2 "non_add_cint_operand" "")))]
6153 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
6154 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
6157 int low = INTVAL (operands[2]) & 0xffff;
6158 int high = (unsigned) INTVAL (operands[2]) >> 16;
6161 high++, low |= 0xffff0000;
6163 operands[3] = GEN_INT (high << 16);
6164 operands[4] = GEN_INT (low);
6168 Here the predicate @code{non_add_cint_operand} matches any
6169 @code{const_int} that is @emph{not} a valid operand of a single add
6170 insn. The add with the smaller displacement is written so that it
6171 can be substituted into the address of a subsequent operation.
6173 An example that uses a scratch register, from the same file, generates
6174 an equality comparison of a register and a large constant:
6178 [(set (match_operand:CC 0 "cc_reg_operand" "")
6179 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
6180 (match_operand:SI 2 "non_short_cint_operand" "")))
6181 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
6182 "find_single_use (operands[0], insn, 0)
6183 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
6184 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
6185 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
6186 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
6189 /* @r{Get the constant we are comparing against, C, and see what it
6190 looks like sign-extended to 16 bits. Then see what constant
6191 could be XOR'ed with C to get the sign-extended value.} */
6193 int c = INTVAL (operands[2]);
6194 int sextc = (c << 16) >> 16;
6195 int xorv = c ^ sextc;
6197 operands[4] = GEN_INT (xorv);
6198 operands[5] = GEN_INT (sextc);
6202 To avoid confusion, don't write a single @code{define_split} that
6203 accepts some insns that match some @code{define_insn} as well as some
6204 insns that don't. Instead, write two separate @code{define_split}
6205 definitions, one for the insns that are valid and one for the insns that
6208 The splitter is allowed to split jump instructions into sequence of
6209 jumps or create new jumps in while splitting non-jump instructions. As
6210 the central flowgraph and branch prediction information needs to be updated,
6211 several restriction apply.
6213 Splitting of jump instruction into sequence that over by another jump
6214 instruction is always valid, as compiler expect identical behavior of new
6215 jump. When new sequence contains multiple jump instructions or new labels,
6216 more assistance is needed. Splitter is required to create only unconditional
6217 jumps, or simple conditional jump instructions. Additionally it must attach a
6218 @code{REG_BR_PROB} note to each conditional jump. A global variable
6219 @code{split_branch_probability} holds the probability of the original branch in case
6220 it was a simple conditional jump, @minus{}1 otherwise. To simplify
6221 recomputing of edge frequencies, the new sequence is required to have only
6222 forward jumps to the newly created labels.
6224 @findex define_insn_and_split
6225 For the common case where the pattern of a define_split exactly matches the
6226 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
6230 (define_insn_and_split
6231 [@var{insn-pattern}]
6233 "@var{output-template}"
6234 "@var{split-condition}"
6235 [@var{new-insn-pattern-1}
6236 @var{new-insn-pattern-2}
6238 "@var{preparation-statements}"
6239 [@var{insn-attributes}])
6243 @var{insn-pattern}, @var{condition}, @var{output-template}, and
6244 @var{insn-attributes} are used as in @code{define_insn}. The
6245 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
6246 in a @code{define_split}. The @var{split-condition} is also used as in
6247 @code{define_split}, with the additional behavior that if the condition starts
6248 with @samp{&&}, the condition used for the split will be the constructed as a
6249 logical ``and'' of the split condition with the insn condition. For example,
6253 (define_insn_and_split "zero_extendhisi2_and"
6254 [(set (match_operand:SI 0 "register_operand" "=r")
6255 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
6256 (clobber (reg:CC 17))]
6257 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
6259 "&& reload_completed"
6260 [(parallel [(set (match_dup 0)
6261 (and:SI (match_dup 0) (const_int 65535)))
6262 (clobber (reg:CC 17))])]
6264 [(set_attr "type" "alu1")])
6268 In this case, the actual split condition will be
6269 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
6271 The @code{define_insn_and_split} construction provides exactly the same
6272 functionality as two separate @code{define_insn} and @code{define_split}
6273 patterns. It exists for compactness, and as a maintenance tool to prevent
6274 having to ensure the two patterns' templates match.
6278 @node Including Patterns
6279 @section Including Patterns in Machine Descriptions.
6280 @cindex insn includes
6283 The @code{include} pattern tells the compiler tools where to
6284 look for patterns that are in files other than in the file
6285 @file{.md}. This is used only at build time and there is no preprocessing allowed.
6299 (include "filestuff")
6303 Where @var{pathname} is a string that specifies the location of the file,
6304 specifies the include file to be in @file{gcc/config/target/filestuff}. The
6305 directory @file{gcc/config/target} is regarded as the default directory.
6308 Machine descriptions may be split up into smaller more manageable subsections
6309 and placed into subdirectories.
6315 (include "BOGUS/filestuff")
6319 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
6321 Specifying an absolute path for the include file such as;
6324 (include "/u2/BOGUS/filestuff")
6327 is permitted but is not encouraged.
6329 @subsection RTL Generation Tool Options for Directory Search
6330 @cindex directory options .md
6331 @cindex options, directory search
6332 @cindex search options
6334 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
6339 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
6344 Add the directory @var{dir} to the head of the list of directories to be
6345 searched for header files. This can be used to override a system machine definition
6346 file, substituting your own version, since these directories are
6347 searched before the default machine description file directories. If you use more than
6348 one @option{-I} option, the directories are scanned in left-to-right
6349 order; the standard default directory come after.
6354 @node Peephole Definitions
6355 @section Machine-Specific Peephole Optimizers
6356 @cindex peephole optimizer definitions
6357 @cindex defining peephole optimizers
6359 In addition to instruction patterns the @file{md} file may contain
6360 definitions of machine-specific peephole optimizations.
6362 The combiner does not notice certain peephole optimizations when the data
6363 flow in the program does not suggest that it should try them. For example,
6364 sometimes two consecutive insns related in purpose can be combined even
6365 though the second one does not appear to use a register computed in the
6366 first one. A machine-specific peephole optimizer can detect such
6369 There are two forms of peephole definitions that may be used. The
6370 original @code{define_peephole} is run at assembly output time to
6371 match insns and substitute assembly text. Use of @code{define_peephole}
6374 A newer @code{define_peephole2} matches insns and substitutes new
6375 insns. The @code{peephole2} pass is run after register allocation
6376 but before scheduling, which may result in much better code for
6377 targets that do scheduling.
6380 * define_peephole:: RTL to Text Peephole Optimizers
6381 * define_peephole2:: RTL to RTL Peephole Optimizers
6386 @node define_peephole
6387 @subsection RTL to Text Peephole Optimizers
6388 @findex define_peephole
6391 A definition looks like this:
6395 [@var{insn-pattern-1}
6396 @var{insn-pattern-2}
6400 "@var{optional-insn-attributes}")
6404 The last string operand may be omitted if you are not using any
6405 machine-specific information in this machine description. If present,
6406 it must obey the same rules as in a @code{define_insn}.
6408 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
6409 consecutive insns. The optimization applies to a sequence of insns when
6410 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
6411 the next, and so on.
6413 Each of the insns matched by a peephole must also match a
6414 @code{define_insn}. Peepholes are checked only at the last stage just
6415 before code generation, and only optionally. Therefore, any insn which
6416 would match a peephole but no @code{define_insn} will cause a crash in code
6417 generation in an unoptimized compilation, or at various optimization
6420 The operands of the insns are matched with @code{match_operands},
6421 @code{match_operator}, and @code{match_dup}, as usual. What is not
6422 usual is that the operand numbers apply to all the insn patterns in the
6423 definition. So, you can check for identical operands in two insns by
6424 using @code{match_operand} in one insn and @code{match_dup} in the
6427 The operand constraints used in @code{match_operand} patterns do not have
6428 any direct effect on the applicability of the peephole, but they will
6429 be validated afterward, so make sure your constraints are general enough
6430 to apply whenever the peephole matches. If the peephole matches
6431 but the constraints are not satisfied, the compiler will crash.
6433 It is safe to omit constraints in all the operands of the peephole; or
6434 you can write constraints which serve as a double-check on the criteria
6437 Once a sequence of insns matches the patterns, the @var{condition} is
6438 checked. This is a C expression which makes the final decision whether to
6439 perform the optimization (we do so if the expression is nonzero). If
6440 @var{condition} is omitted (in other words, the string is empty) then the
6441 optimization is applied to every sequence of insns that matches the
6444 The defined peephole optimizations are applied after register allocation
6445 is complete. Therefore, the peephole definition can check which
6446 operands have ended up in which kinds of registers, just by looking at
6449 @findex prev_active_insn
6450 The way to refer to the operands in @var{condition} is to write
6451 @code{operands[@var{i}]} for operand number @var{i} (as matched by
6452 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
6453 to refer to the last of the insns being matched; use
6454 @code{prev_active_insn} to find the preceding insns.
6456 @findex dead_or_set_p
6457 When optimizing computations with intermediate results, you can use
6458 @var{condition} to match only when the intermediate results are not used
6459 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
6460 @var{op})}, where @var{insn} is the insn in which you expect the value
6461 to be used for the last time (from the value of @code{insn}, together
6462 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
6463 value (from @code{operands[@var{i}]}).
6465 Applying the optimization means replacing the sequence of insns with one
6466 new insn. The @var{template} controls ultimate output of assembler code
6467 for this combined insn. It works exactly like the template of a
6468 @code{define_insn}. Operand numbers in this template are the same ones
6469 used in matching the original sequence of insns.
6471 The result of a defined peephole optimizer does not need to match any of
6472 the insn patterns in the machine description; it does not even have an
6473 opportunity to match them. The peephole optimizer definition itself serves
6474 as the insn pattern to control how the insn is output.
6476 Defined peephole optimizers are run as assembler code is being output,
6477 so the insns they produce are never combined or rearranged in any way.
6479 Here is an example, taken from the 68000 machine description:
6483 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6484 (set (match_operand:DF 0 "register_operand" "=f")
6485 (match_operand:DF 1 "register_operand" "ad"))]
6486 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6489 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6491 output_asm_insn ("move.l %1,(sp)", xoperands);
6492 output_asm_insn ("move.l %1,-(sp)", operands);
6493 return "fmove.d (sp)+,%0";
6495 output_asm_insn ("movel %1,sp@@", xoperands);
6496 output_asm_insn ("movel %1,sp@@-", operands);
6497 return "fmoved sp@@+,%0";
6503 The effect of this optimization is to change
6529 If a peephole matches a sequence including one or more jump insns, you must
6530 take account of the flags such as @code{CC_REVERSED} which specify that the
6531 condition codes are represented in an unusual manner. The compiler
6532 automatically alters any ordinary conditional jumps which occur in such
6533 situations, but the compiler cannot alter jumps which have been replaced by
6534 peephole optimizations. So it is up to you to alter the assembler code
6535 that the peephole produces. Supply C code to write the assembler output,
6536 and in this C code check the condition code status flags and change the
6537 assembler code as appropriate.
6540 @var{insn-pattern-1} and so on look @emph{almost} like the second
6541 operand of @code{define_insn}. There is one important difference: the
6542 second operand of @code{define_insn} consists of one or more RTX's
6543 enclosed in square brackets. Usually, there is only one: then the same
6544 action can be written as an element of a @code{define_peephole}. But
6545 when there are multiple actions in a @code{define_insn}, they are
6546 implicitly enclosed in a @code{parallel}. Then you must explicitly
6547 write the @code{parallel}, and the square brackets within it, in the
6548 @code{define_peephole}. Thus, if an insn pattern looks like this,
6551 (define_insn "divmodsi4"
6552 [(set (match_operand:SI 0 "general_operand" "=d")
6553 (div:SI (match_operand:SI 1 "general_operand" "0")
6554 (match_operand:SI 2 "general_operand" "dmsK")))
6555 (set (match_operand:SI 3 "general_operand" "=d")
6556 (mod:SI (match_dup 1) (match_dup 2)))]
6558 "divsl%.l %2,%3:%0")
6562 then the way to mention this insn in a peephole is as follows:
6568 [(set (match_operand:SI 0 "general_operand" "=d")
6569 (div:SI (match_operand:SI 1 "general_operand" "0")
6570 (match_operand:SI 2 "general_operand" "dmsK")))
6571 (set (match_operand:SI 3 "general_operand" "=d")
6572 (mod:SI (match_dup 1) (match_dup 2)))])
6579 @node define_peephole2
6580 @subsection RTL to RTL Peephole Optimizers
6581 @findex define_peephole2
6583 The @code{define_peephole2} definition tells the compiler how to
6584 substitute one sequence of instructions for another sequence,
6585 what additional scratch registers may be needed and what their
6590 [@var{insn-pattern-1}
6591 @var{insn-pattern-2}
6594 [@var{new-insn-pattern-1}
6595 @var{new-insn-pattern-2}
6597 "@var{preparation-statements}")
6600 The definition is almost identical to @code{define_split}
6601 (@pxref{Insn Splitting}) except that the pattern to match is not a
6602 single instruction, but a sequence of instructions.
6604 It is possible to request additional scratch registers for use in the
6605 output template. If appropriate registers are not free, the pattern
6606 will simply not match.
6608 @findex match_scratch
6610 Scratch registers are requested with a @code{match_scratch} pattern at
6611 the top level of the input pattern. The allocated register (initially) will
6612 be dead at the point requested within the original sequence. If the scratch
6613 is used at more than a single point, a @code{match_dup} pattern at the
6614 top level of the input pattern marks the last position in the input sequence
6615 at which the register must be available.
6617 Here is an example from the IA-32 machine description:
6621 [(match_scratch:SI 2 "r")
6622 (parallel [(set (match_operand:SI 0 "register_operand" "")
6623 (match_operator:SI 3 "arith_or_logical_operator"
6625 (match_operand:SI 1 "memory_operand" "")]))
6626 (clobber (reg:CC 17))])]
6627 "! optimize_size && ! TARGET_READ_MODIFY"
6628 [(set (match_dup 2) (match_dup 1))
6629 (parallel [(set (match_dup 0)
6630 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
6631 (clobber (reg:CC 17))])]
6636 This pattern tries to split a load from its use in the hopes that we'll be
6637 able to schedule around the memory load latency. It allocates a single
6638 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
6639 to be live only at the point just before the arithmetic.
6641 A real example requiring extended scratch lifetimes is harder to come by,
6642 so here's a silly made-up example:
6646 [(match_scratch:SI 4 "r")
6647 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
6648 (set (match_operand:SI 2 "" "") (match_dup 1))
6650 (set (match_operand:SI 3 "" "") (match_dup 1))]
6651 "/* @r{determine 1 does not overlap 0 and 2} */"
6652 [(set (match_dup 4) (match_dup 1))
6653 (set (match_dup 0) (match_dup 4))
6654 (set (match_dup 2) (match_dup 4))]
6655 (set (match_dup 3) (match_dup 4))]
6660 If we had not added the @code{(match_dup 4)} in the middle of the input
6661 sequence, it might have been the case that the register we chose at the
6662 beginning of the sequence is killed by the first or second @code{set}.
6666 @node Insn Attributes
6667 @section Instruction Attributes
6668 @cindex insn attributes
6669 @cindex instruction attributes
6671 In addition to describing the instruction supported by the target machine,
6672 the @file{md} file also defines a group of @dfn{attributes} and a set of
6673 values for each. Every generated insn is assigned a value for each attribute.
6674 One possible attribute would be the effect that the insn has on the machine's
6675 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
6676 to track the condition codes.
6679 * Defining Attributes:: Specifying attributes and their values.
6680 * Expressions:: Valid expressions for attribute values.
6681 * Tagging Insns:: Assigning attribute values to insns.
6682 * Attr Example:: An example of assigning attributes.
6683 * Insn Lengths:: Computing the length of insns.
6684 * Constant Attributes:: Defining attributes that are constant.
6685 * Delay Slots:: Defining delay slots required for a machine.
6686 * Processor pipeline description:: Specifying information for insn scheduling.
6691 @node Defining Attributes
6692 @subsection Defining Attributes and their Values
6693 @cindex defining attributes and their values
6694 @cindex attributes, defining
6697 The @code{define_attr} expression is used to define each attribute required
6698 by the target machine. It looks like:
6701 (define_attr @var{name} @var{list-of-values} @var{default})
6704 @var{name} is a string specifying the name of the attribute being defined.
6706 @var{list-of-values} is either a string that specifies a comma-separated
6707 list of values that can be assigned to the attribute, or a null string to
6708 indicate that the attribute takes numeric values.
6710 @var{default} is an attribute expression that gives the value of this
6711 attribute for insns that match patterns whose definition does not include
6712 an explicit value for this attribute. @xref{Attr Example}, for more
6713 information on the handling of defaults. @xref{Constant Attributes},
6714 for information on attributes that do not depend on any particular insn.
6717 For each defined attribute, a number of definitions are written to the
6718 @file{insn-attr.h} file. For cases where an explicit set of values is
6719 specified for an attribute, the following are defined:
6723 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
6726 An enumerated class is defined for @samp{attr_@var{name}} with
6727 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
6728 the attribute name and value are first converted to uppercase.
6731 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
6732 returns the attribute value for that insn.
6735 For example, if the following is present in the @file{md} file:
6738 (define_attr "type" "branch,fp,load,store,arith" @dots{})
6742 the following lines will be written to the file @file{insn-attr.h}.
6745 #define HAVE_ATTR_type
6746 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
6747 TYPE_STORE, TYPE_ARITH@};
6748 extern enum attr_type get_attr_type ();
6751 If the attribute takes numeric values, no @code{enum} type will be
6752 defined and the function to obtain the attribute's value will return
6755 There are attributes which are tied to a specific meaning. These
6756 attributes are not free to use for other purposes:
6760 The @code{length} attribute is used to calculate the length of emitted
6761 code chunks. This is especially important when verifying branch
6762 distances. @xref{Insn Lengths}.
6765 The @code{enabled} attribute can be defined to prevent certain
6766 alternatives of an insn definition from being used during code
6767 generation. @xref{Disable Insn Alternatives}.
6770 @findex define_enum_attr
6771 @anchor{define_enum_attr}
6772 Another way of defining an attribute is to use:
6775 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
6778 This works in just the same way as @code{define_attr}, except that
6779 the list of values is taken from a separate enumeration called
6780 @var{enum} (@pxref{define_enum}). This form allows you to use
6781 the same list of values for several attributes without having to
6782 repeat the list each time. For example:
6785 (define_enum "processor" [
6790 (define_enum_attr "arch" "processor"
6791 (const (symbol_ref "target_arch")))
6792 (define_enum_attr "tune" "processor"
6793 (const (symbol_ref "target_tune")))
6796 defines the same attributes as:
6799 (define_attr "arch" "model_a,model_b,@dots{}"
6800 (const (symbol_ref "target_arch")))
6801 (define_attr "tune" "model_a,model_b,@dots{}"
6802 (const (symbol_ref "target_tune")))
6805 but without duplicating the processor list. The second example defines two
6806 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
6807 defines a single C enum (@code{processor}).
6811 @subsection Attribute Expressions
6812 @cindex attribute expressions
6814 RTL expressions used to define attributes use the codes described above
6815 plus a few specific to attribute definitions, to be discussed below.
6816 Attribute value expressions must have one of the following forms:
6819 @cindex @code{const_int} and attributes
6820 @item (const_int @var{i})
6821 The integer @var{i} specifies the value of a numeric attribute. @var{i}
6822 must be non-negative.
6824 The value of a numeric attribute can be specified either with a
6825 @code{const_int}, or as an integer represented as a string in
6826 @code{const_string}, @code{eq_attr} (see below), @code{attr},
6827 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
6828 overrides on specific instructions (@pxref{Tagging Insns}).
6830 @cindex @code{const_string} and attributes
6831 @item (const_string @var{value})
6832 The string @var{value} specifies a constant attribute value.
6833 If @var{value} is specified as @samp{"*"}, it means that the default value of
6834 the attribute is to be used for the insn containing this expression.
6835 @samp{"*"} obviously cannot be used in the @var{default} expression
6836 of a @code{define_attr}.
6838 If the attribute whose value is being specified is numeric, @var{value}
6839 must be a string containing a non-negative integer (normally
6840 @code{const_int} would be used in this case). Otherwise, it must
6841 contain one of the valid values for the attribute.
6843 @cindex @code{if_then_else} and attributes
6844 @item (if_then_else @var{test} @var{true-value} @var{false-value})
6845 @var{test} specifies an attribute test, whose format is defined below.
6846 The value of this expression is @var{true-value} if @var{test} is true,
6847 otherwise it is @var{false-value}.
6849 @cindex @code{cond} and attributes
6850 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
6851 The first operand of this expression is a vector containing an even
6852 number of expressions and consisting of pairs of @var{test} and @var{value}
6853 expressions. The value of the @code{cond} expression is that of the
6854 @var{value} corresponding to the first true @var{test} expression. If
6855 none of the @var{test} expressions are true, the value of the @code{cond}
6856 expression is that of the @var{default} expression.
6859 @var{test} expressions can have one of the following forms:
6862 @cindex @code{const_int} and attribute tests
6863 @item (const_int @var{i})
6864 This test is true if @var{i} is nonzero and false otherwise.
6866 @cindex @code{not} and attributes
6867 @cindex @code{ior} and attributes
6868 @cindex @code{and} and attributes
6869 @item (not @var{test})
6870 @itemx (ior @var{test1} @var{test2})
6871 @itemx (and @var{test1} @var{test2})
6872 These tests are true if the indicated logical function is true.
6874 @cindex @code{match_operand} and attributes
6875 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
6876 This test is true if operand @var{n} of the insn whose attribute value
6877 is being determined has mode @var{m} (this part of the test is ignored
6878 if @var{m} is @code{VOIDmode}) and the function specified by the string
6879 @var{pred} returns a nonzero value when passed operand @var{n} and mode
6880 @var{m} (this part of the test is ignored if @var{pred} is the null
6883 The @var{constraints} operand is ignored and should be the null string.
6885 @cindex @code{le} and attributes
6886 @cindex @code{leu} and attributes
6887 @cindex @code{lt} and attributes
6888 @cindex @code{gt} and attributes
6889 @cindex @code{gtu} and attributes
6890 @cindex @code{ge} and attributes
6891 @cindex @code{geu} and attributes
6892 @cindex @code{ne} and attributes
6893 @cindex @code{eq} and attributes
6894 @cindex @code{plus} and attributes
6895 @cindex @code{minus} and attributes
6896 @cindex @code{mult} and attributes
6897 @cindex @code{div} and attributes
6898 @cindex @code{mod} and attributes
6899 @cindex @code{abs} and attributes
6900 @cindex @code{neg} and attributes
6901 @cindex @code{ashift} and attributes
6902 @cindex @code{lshiftrt} and attributes
6903 @cindex @code{ashiftrt} and attributes
6904 @item (le @var{arith1} @var{arith2})
6905 @itemx (leu @var{arith1} @var{arith2})
6906 @itemx (lt @var{arith1} @var{arith2})
6907 @itemx (ltu @var{arith1} @var{arith2})
6908 @itemx (gt @var{arith1} @var{arith2})
6909 @itemx (gtu @var{arith1} @var{arith2})
6910 @itemx (ge @var{arith1} @var{arith2})
6911 @itemx (geu @var{arith1} @var{arith2})
6912 @itemx (ne @var{arith1} @var{arith2})
6913 @itemx (eq @var{arith1} @var{arith2})
6914 These tests are true if the indicated comparison of the two arithmetic
6915 expressions is true. Arithmetic expressions are formed with
6916 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
6917 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
6918 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
6921 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
6922 Lengths},for additional forms). @code{symbol_ref} is a string
6923 denoting a C expression that yields an @code{int} when evaluated by the
6924 @samp{get_attr_@dots{}} routine. It should normally be a global
6928 @item (eq_attr @var{name} @var{value})
6929 @var{name} is a string specifying the name of an attribute.
6931 @var{value} is a string that is either a valid value for attribute
6932 @var{name}, a comma-separated list of values, or @samp{!} followed by a
6933 value or list. If @var{value} does not begin with a @samp{!}, this
6934 test is true if the value of the @var{name} attribute of the current
6935 insn is in the list specified by @var{value}. If @var{value} begins
6936 with a @samp{!}, this test is true if the attribute's value is
6937 @emph{not} in the specified list.
6942 (eq_attr "type" "load,store")
6949 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
6952 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
6953 value of the compiler variable @code{which_alternative}
6954 (@pxref{Output Statement}) and the values must be small integers. For
6958 (eq_attr "alternative" "2,3")
6965 (ior (eq (symbol_ref "which_alternative") (const_int 2))
6966 (eq (symbol_ref "which_alternative") (const_int 3)))
6969 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
6970 where the value of the attribute being tested is known for all insns matching
6971 a particular pattern. This is by far the most common case.
6974 @item (attr_flag @var{name})
6975 The value of an @code{attr_flag} expression is true if the flag
6976 specified by @var{name} is true for the @code{insn} currently being
6979 @var{name} is a string specifying one of a fixed set of flags to test.
6980 Test the flags @code{forward} and @code{backward} to determine the
6981 direction of a conditional branch. Test the flags @code{very_likely},
6982 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
6983 if a conditional branch is expected to be taken.
6985 If the @code{very_likely} flag is true, then the @code{likely} flag is also
6986 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
6988 This example describes a conditional branch delay slot which
6989 can be nullified for forward branches that are taken (annul-true) or
6990 for backward branches which are not taken (annul-false).
6993 (define_delay (eq_attr "type" "cbranch")
6994 [(eq_attr "in_branch_delay" "true")
6995 (and (eq_attr "in_branch_delay" "true")
6996 (attr_flag "forward"))
6997 (and (eq_attr "in_branch_delay" "true")
6998 (attr_flag "backward"))])
7001 The @code{forward} and @code{backward} flags are false if the current
7002 @code{insn} being scheduled is not a conditional branch.
7004 The @code{very_likely} and @code{likely} flags are true if the
7005 @code{insn} being scheduled is not a conditional branch.
7006 The @code{very_unlikely} and @code{unlikely} flags are false if the
7007 @code{insn} being scheduled is not a conditional branch.
7009 @code{attr_flag} is only used during delay slot scheduling and has no
7010 meaning to other passes of the compiler.
7013 @item (attr @var{name})
7014 The value of another attribute is returned. This is most useful
7015 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
7016 produce more efficient code for non-numeric attributes.
7022 @subsection Assigning Attribute Values to Insns
7023 @cindex tagging insns
7024 @cindex assigning attribute values to insns
7026 The value assigned to an attribute of an insn is primarily determined by
7027 which pattern is matched by that insn (or which @code{define_peephole}
7028 generated it). Every @code{define_insn} and @code{define_peephole} can
7029 have an optional last argument to specify the values of attributes for
7030 matching insns. The value of any attribute not specified in a particular
7031 insn is set to the default value for that attribute, as specified in its
7032 @code{define_attr}. Extensive use of default values for attributes
7033 permits the specification of the values for only one or two attributes
7034 in the definition of most insn patterns, as seen in the example in the
7037 The optional last argument of @code{define_insn} and
7038 @code{define_peephole} is a vector of expressions, each of which defines
7039 the value for a single attribute. The most general way of assigning an
7040 attribute's value is to use a @code{set} expression whose first operand is an
7041 @code{attr} expression giving the name of the attribute being set. The
7042 second operand of the @code{set} is an attribute expression
7043 (@pxref{Expressions}) giving the value of the attribute.
7045 When the attribute value depends on the @samp{alternative} attribute
7046 (i.e., which is the applicable alternative in the constraint of the
7047 insn), the @code{set_attr_alternative} expression can be used. It
7048 allows the specification of a vector of attribute expressions, one for
7052 When the generality of arbitrary attribute expressions is not required,
7053 the simpler @code{set_attr} expression can be used, which allows
7054 specifying a string giving either a single attribute value or a list
7055 of attribute values, one for each alternative.
7057 The form of each of the above specifications is shown below. In each case,
7058 @var{name} is a string specifying the attribute to be set.
7061 @item (set_attr @var{name} @var{value-string})
7062 @var{value-string} is either a string giving the desired attribute value,
7063 or a string containing a comma-separated list giving the values for
7064 succeeding alternatives. The number of elements must match the number
7065 of alternatives in the constraint of the insn pattern.
7067 Note that it may be useful to specify @samp{*} for some alternative, in
7068 which case the attribute will assume its default value for insns matching
7071 @findex set_attr_alternative
7072 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
7073 Depending on the alternative of the insn, the value will be one of the
7074 specified values. This is a shorthand for using a @code{cond} with
7075 tests on the @samp{alternative} attribute.
7078 @item (set (attr @var{name}) @var{value})
7079 The first operand of this @code{set} must be the special RTL expression
7080 @code{attr}, whose sole operand is a string giving the name of the
7081 attribute being set. @var{value} is the value of the attribute.
7084 The following shows three different ways of representing the same
7085 attribute value specification:
7088 (set_attr "type" "load,store,arith")
7090 (set_attr_alternative "type"
7091 [(const_string "load") (const_string "store")
7092 (const_string "arith")])
7095 (cond [(eq_attr "alternative" "1") (const_string "load")
7096 (eq_attr "alternative" "2") (const_string "store")]
7097 (const_string "arith")))
7101 @findex define_asm_attributes
7102 The @code{define_asm_attributes} expression provides a mechanism to
7103 specify the attributes assigned to insns produced from an @code{asm}
7104 statement. It has the form:
7107 (define_asm_attributes [@var{attr-sets}])
7111 where @var{attr-sets} is specified the same as for both the
7112 @code{define_insn} and the @code{define_peephole} expressions.
7114 These values will typically be the ``worst case'' attribute values. For
7115 example, they might indicate that the condition code will be clobbered.
7117 A specification for a @code{length} attribute is handled specially. The
7118 way to compute the length of an @code{asm} insn is to multiply the
7119 length specified in the expression @code{define_asm_attributes} by the
7120 number of machine instructions specified in the @code{asm} statement,
7121 determined by counting the number of semicolons and newlines in the
7122 string. Therefore, the value of the @code{length} attribute specified
7123 in a @code{define_asm_attributes} should be the maximum possible length
7124 of a single machine instruction.
7129 @subsection Example of Attribute Specifications
7130 @cindex attribute specifications example
7131 @cindex attribute specifications
7133 The judicious use of defaulting is important in the efficient use of
7134 insn attributes. Typically, insns are divided into @dfn{types} and an
7135 attribute, customarily called @code{type}, is used to represent this
7136 value. This attribute is normally used only to define the default value
7137 for other attributes. An example will clarify this usage.
7139 Assume we have a RISC machine with a condition code and in which only
7140 full-word operations are performed in registers. Let us assume that we
7141 can divide all insns into loads, stores, (integer) arithmetic
7142 operations, floating point operations, and branches.
7144 Here we will concern ourselves with determining the effect of an insn on
7145 the condition code and will limit ourselves to the following possible
7146 effects: The condition code can be set unpredictably (clobbered), not
7147 be changed, be set to agree with the results of the operation, or only
7148 changed if the item previously set into the condition code has been
7151 Here is part of a sample @file{md} file for such a machine:
7154 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
7156 (define_attr "cc" "clobber,unchanged,set,change0"
7157 (cond [(eq_attr "type" "load")
7158 (const_string "change0")
7159 (eq_attr "type" "store,branch")
7160 (const_string "unchanged")
7161 (eq_attr "type" "arith")
7162 (if_then_else (match_operand:SI 0 "" "")
7163 (const_string "set")
7164 (const_string "clobber"))]
7165 (const_string "clobber")))
7168 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
7169 (match_operand:SI 1 "general_operand" "r,m,r"))]
7175 [(set_attr "type" "arith,load,store")])
7178 Note that we assume in the above example that arithmetic operations
7179 performed on quantities smaller than a machine word clobber the condition
7180 code since they will set the condition code to a value corresponding to the
7186 @subsection Computing the Length of an Insn
7187 @cindex insn lengths, computing
7188 @cindex computing the length of an insn
7190 For many machines, multiple types of branch instructions are provided, each
7191 for different length branch displacements. In most cases, the assembler
7192 will choose the correct instruction to use. However, when the assembler
7193 cannot do so, GCC can when a special attribute, the @code{length}
7194 attribute, is defined. This attribute must be defined to have numeric
7195 values by specifying a null string in its @code{define_attr}.
7197 In the case of the @code{length} attribute, two additional forms of
7198 arithmetic terms are allowed in test expressions:
7201 @cindex @code{match_dup} and attributes
7202 @item (match_dup @var{n})
7203 This refers to the address of operand @var{n} of the current insn, which
7204 must be a @code{label_ref}.
7206 @cindex @code{pc} and attributes
7208 This refers to the address of the @emph{current} insn. It might have
7209 been more consistent with other usage to make this the address of the
7210 @emph{next} insn but this would be confusing because the length of the
7211 current insn is to be computed.
7214 @cindex @code{addr_vec}, length of
7215 @cindex @code{addr_diff_vec}, length of
7216 For normal insns, the length will be determined by value of the
7217 @code{length} attribute. In the case of @code{addr_vec} and
7218 @code{addr_diff_vec} insn patterns, the length is computed as
7219 the number of vectors multiplied by the size of each vector.
7221 Lengths are measured in addressable storage units (bytes).
7223 The following macros can be used to refine the length computation:
7226 @findex ADJUST_INSN_LENGTH
7227 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
7228 If defined, modifies the length assigned to instruction @var{insn} as a
7229 function of the context in which it is used. @var{length} is an lvalue
7230 that contains the initially computed length of the insn and should be
7231 updated with the correct length of the insn.
7233 This macro will normally not be required. A case in which it is
7234 required is the ROMP@. On this machine, the size of an @code{addr_vec}
7235 insn must be increased by two to compensate for the fact that alignment
7239 @findex get_attr_length
7240 The routine that returns @code{get_attr_length} (the value of the
7241 @code{length} attribute) can be used by the output routine to
7242 determine the form of the branch instruction to be written, as the
7243 example below illustrates.
7245 As an example of the specification of variable-length branches, consider
7246 the IBM 360. If we adopt the convention that a register will be set to
7247 the starting address of a function, we can jump to labels within 4k of
7248 the start using a four-byte instruction. Otherwise, we need a six-byte
7249 sequence to load the address from memory and then branch to it.
7251 On such a machine, a pattern for a branch instruction might be specified
7257 (label_ref (match_operand 0 "" "")))]
7260 return (get_attr_length (insn) == 4
7261 ? "b %l0" : "l r15,=a(%l0); br r15");
7263 [(set (attr "length")
7264 (if_then_else (lt (match_dup 0) (const_int 4096))
7271 @node Constant Attributes
7272 @subsection Constant Attributes
7273 @cindex constant attributes
7275 A special form of @code{define_attr}, where the expression for the
7276 default value is a @code{const} expression, indicates an attribute that
7277 is constant for a given run of the compiler. Constant attributes may be
7278 used to specify which variety of processor is used. For example,
7281 (define_attr "cpu" "m88100,m88110,m88000"
7283 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
7284 (symbol_ref "TARGET_88110") (const_string "m88110")]
7285 (const_string "m88000"))))
7287 (define_attr "memory" "fast,slow"
7289 (if_then_else (symbol_ref "TARGET_FAST_MEM")
7290 (const_string "fast")
7291 (const_string "slow"))))
7294 The routine generated for constant attributes has no parameters as it
7295 does not depend on any particular insn. RTL expressions used to define
7296 the value of a constant attribute may use the @code{symbol_ref} form,
7297 but may not use either the @code{match_operand} form or @code{eq_attr}
7298 forms involving insn attributes.
7303 @subsection Delay Slot Scheduling
7304 @cindex delay slots, defining
7306 The insn attribute mechanism can be used to specify the requirements for
7307 delay slots, if any, on a target machine. An instruction is said to
7308 require a @dfn{delay slot} if some instructions that are physically
7309 after the instruction are executed as if they were located before it.
7310 Classic examples are branch and call instructions, which often execute
7311 the following instruction before the branch or call is performed.
7313 On some machines, conditional branch instructions can optionally
7314 @dfn{annul} instructions in the delay slot. This means that the
7315 instruction will not be executed for certain branch outcomes. Both
7316 instructions that annul if the branch is true and instructions that
7317 annul if the branch is false are supported.
7319 Delay slot scheduling differs from instruction scheduling in that
7320 determining whether an instruction needs a delay slot is dependent only
7321 on the type of instruction being generated, not on data flow between the
7322 instructions. See the next section for a discussion of data-dependent
7323 instruction scheduling.
7325 @findex define_delay
7326 The requirement of an insn needing one or more delay slots is indicated
7327 via the @code{define_delay} expression. It has the following form:
7330 (define_delay @var{test}
7331 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
7332 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
7336 @var{test} is an attribute test that indicates whether this
7337 @code{define_delay} applies to a particular insn. If so, the number of
7338 required delay slots is determined by the length of the vector specified
7339 as the second argument. An insn placed in delay slot @var{n} must
7340 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
7341 attribute test that specifies which insns may be annulled if the branch
7342 is true. Similarly, @var{annul-false-n} specifies which insns in the
7343 delay slot may be annulled if the branch is false. If annulling is not
7344 supported for that delay slot, @code{(nil)} should be coded.
7346 For example, in the common case where branch and call insns require
7347 a single delay slot, which may contain any insn other than a branch or
7348 call, the following would be placed in the @file{md} file:
7351 (define_delay (eq_attr "type" "branch,call")
7352 [(eq_attr "type" "!branch,call") (nil) (nil)])
7355 Multiple @code{define_delay} expressions may be specified. In this
7356 case, each such expression specifies different delay slot requirements
7357 and there must be no insn for which tests in two @code{define_delay}
7358 expressions are both true.
7360 For example, if we have a machine that requires one delay slot for branches
7361 but two for calls, no delay slot can contain a branch or call insn,
7362 and any valid insn in the delay slot for the branch can be annulled if the
7363 branch is true, we might represent this as follows:
7366 (define_delay (eq_attr "type" "branch")
7367 [(eq_attr "type" "!branch,call")
7368 (eq_attr "type" "!branch,call")
7371 (define_delay (eq_attr "type" "call")
7372 [(eq_attr "type" "!branch,call") (nil) (nil)
7373 (eq_attr "type" "!branch,call") (nil) (nil)])
7375 @c the above is *still* too long. --mew 4feb93
7379 @node Processor pipeline description
7380 @subsection Specifying processor pipeline description
7381 @cindex processor pipeline description
7382 @cindex processor functional units
7383 @cindex instruction latency time
7384 @cindex interlock delays
7385 @cindex data dependence delays
7386 @cindex reservation delays
7387 @cindex pipeline hazard recognizer
7388 @cindex automaton based pipeline description
7389 @cindex regular expressions
7390 @cindex deterministic finite state automaton
7391 @cindex automaton based scheduler
7395 To achieve better performance, most modern processors
7396 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
7397 processors) have many @dfn{functional units} on which several
7398 instructions can be executed simultaneously. An instruction starts
7399 execution if its issue conditions are satisfied. If not, the
7400 instruction is stalled until its conditions are satisfied. Such
7401 @dfn{interlock (pipeline) delay} causes interruption of the fetching
7402 of successor instructions (or demands nop instructions, e.g.@: for some
7405 There are two major kinds of interlock delays in modern processors.
7406 The first one is a data dependence delay determining @dfn{instruction
7407 latency time}. The instruction execution is not started until all
7408 source data have been evaluated by prior instructions (there are more
7409 complex cases when the instruction execution starts even when the data
7410 are not available but will be ready in given time after the
7411 instruction execution start). Taking the data dependence delays into
7412 account is simple. The data dependence (true, output, and
7413 anti-dependence) delay between two instructions is given by a
7414 constant. In most cases this approach is adequate. The second kind
7415 of interlock delays is a reservation delay. The reservation delay
7416 means that two instructions under execution will be in need of shared
7417 processors resources, i.e.@: buses, internal registers, and/or
7418 functional units, which are reserved for some time. Taking this kind
7419 of delay into account is complex especially for modern @acronym{RISC}
7422 The task of exploiting more processor parallelism is solved by an
7423 instruction scheduler. For a better solution to this problem, the
7424 instruction scheduler has to have an adequate description of the
7425 processor parallelism (or @dfn{pipeline description}). GCC
7426 machine descriptions describe processor parallelism and functional
7427 unit reservations for groups of instructions with the aid of
7428 @dfn{regular expressions}.
7430 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
7431 figure out the possibility of the instruction issue by the processor
7432 on a given simulated processor cycle. The pipeline hazard recognizer is
7433 automatically generated from the processor pipeline description. The
7434 pipeline hazard recognizer generated from the machine description
7435 is based on a deterministic finite state automaton (@acronym{DFA}):
7436 the instruction issue is possible if there is a transition from one
7437 automaton state to another one. This algorithm is very fast, and
7438 furthermore, its speed is not dependent on processor
7439 complexity@footnote{However, the size of the automaton depends on
7440 processor complexity. To limit this effect, machine descriptions
7441 can split orthogonal parts of the machine description among several
7442 automata: but then, since each of these must be stepped independently,
7443 this does cause a small decrease in the algorithm's performance.}.
7445 @cindex automaton based pipeline description
7446 The rest of this section describes the directives that constitute
7447 an automaton-based processor pipeline description. The order of
7448 these constructions within the machine description file is not
7451 @findex define_automaton
7452 @cindex pipeline hazard recognizer
7453 The following optional construction describes names of automata
7454 generated and used for the pipeline hazards recognition. Sometimes
7455 the generated finite state automaton used by the pipeline hazard
7456 recognizer is large. If we use more than one automaton and bind functional
7457 units to the automata, the total size of the automata is usually
7458 less than the size of the single automaton. If there is no one such
7459 construction, only one finite state automaton is generated.
7462 (define_automaton @var{automata-names})
7465 @var{automata-names} is a string giving names of the automata. The
7466 names are separated by commas. All the automata should have unique names.
7467 The automaton name is used in the constructions @code{define_cpu_unit} and
7468 @code{define_query_cpu_unit}.
7470 @findex define_cpu_unit
7471 @cindex processor functional units
7472 Each processor functional unit used in the description of instruction
7473 reservations should be described by the following construction.
7476 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
7479 @var{unit-names} is a string giving the names of the functional units
7480 separated by commas. Don't use name @samp{nothing}, it is reserved
7483 @var{automaton-name} is a string giving the name of the automaton with
7484 which the unit is bound. The automaton should be described in
7485 construction @code{define_automaton}. You should give
7486 @dfn{automaton-name}, if there is a defined automaton.
7488 The assignment of units to automata are constrained by the uses of the
7489 units in insn reservations. The most important constraint is: if a
7490 unit reservation is present on a particular cycle of an alternative
7491 for an insn reservation, then some unit from the same automaton must
7492 be present on the same cycle for the other alternatives of the insn
7493 reservation. The rest of the constraints are mentioned in the
7494 description of the subsequent constructions.
7496 @findex define_query_cpu_unit
7497 @cindex querying function unit reservations
7498 The following construction describes CPU functional units analogously
7499 to @code{define_cpu_unit}. The reservation of such units can be
7500 queried for an automaton state. The instruction scheduler never
7501 queries reservation of functional units for given automaton state. So
7502 as a rule, you don't need this construction. This construction could
7503 be used for future code generation goals (e.g.@: to generate
7504 @acronym{VLIW} insn templates).
7507 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
7510 @var{unit-names} is a string giving names of the functional units
7511 separated by commas.
7513 @var{automaton-name} is a string giving the name of the automaton with
7514 which the unit is bound.
7516 @findex define_insn_reservation
7517 @cindex instruction latency time
7518 @cindex regular expressions
7520 The following construction is the major one to describe pipeline
7521 characteristics of an instruction.
7524 (define_insn_reservation @var{insn-name} @var{default_latency}
7525 @var{condition} @var{regexp})
7528 @var{default_latency} is a number giving latency time of the
7529 instruction. There is an important difference between the old
7530 description and the automaton based pipeline description. The latency
7531 time is used for all dependencies when we use the old description. In
7532 the automaton based pipeline description, the given latency time is only
7533 used for true dependencies. The cost of anti-dependencies is always
7534 zero and the cost of output dependencies is the difference between
7535 latency times of the producing and consuming insns (if the difference
7536 is negative, the cost is considered to be zero). You can always
7537 change the default costs for any description by using the target hook
7538 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
7540 @var{insn-name} is a string giving the internal name of the insn. The
7541 internal names are used in constructions @code{define_bypass} and in
7542 the automaton description file generated for debugging. The internal
7543 name has nothing in common with the names in @code{define_insn}. It is a
7544 good practice to use insn classes described in the processor manual.
7546 @var{condition} defines what RTL insns are described by this
7547 construction. You should remember that you will be in trouble if
7548 @var{condition} for two or more different
7549 @code{define_insn_reservation} constructions is TRUE for an insn. In
7550 this case what reservation will be used for the insn is not defined.
7551 Such cases are not checked during generation of the pipeline hazards
7552 recognizer because in general recognizing that two conditions may have
7553 the same value is quite difficult (especially if the conditions
7554 contain @code{symbol_ref}). It is also not checked during the
7555 pipeline hazard recognizer work because it would slow down the
7556 recognizer considerably.
7558 @var{regexp} is a string describing the reservation of the cpu's functional
7559 units by the instruction. The reservations are described by a regular
7560 expression according to the following syntax:
7563 regexp = regexp "," oneof
7566 oneof = oneof "|" allof
7569 allof = allof "+" repeat
7572 repeat = element "*" number
7575 element = cpu_function_unit_name
7584 @samp{,} is used for describing the start of the next cycle in
7588 @samp{|} is used for describing a reservation described by the first
7589 regular expression @strong{or} a reservation described by the second
7590 regular expression @strong{or} etc.
7593 @samp{+} is used for describing a reservation described by the first
7594 regular expression @strong{and} a reservation described by the
7595 second regular expression @strong{and} etc.
7598 @samp{*} is used for convenience and simply means a sequence in which
7599 the regular expression are repeated @var{number} times with cycle
7600 advancing (see @samp{,}).
7603 @samp{cpu_function_unit_name} denotes reservation of the named
7607 @samp{reservation_name} --- see description of construction
7608 @samp{define_reservation}.
7611 @samp{nothing} denotes no unit reservations.
7614 @findex define_reservation
7615 Sometimes unit reservations for different insns contain common parts.
7616 In such case, you can simplify the pipeline description by describing
7617 the common part by the following construction
7620 (define_reservation @var{reservation-name} @var{regexp})
7623 @var{reservation-name} is a string giving name of @var{regexp}.
7624 Functional unit names and reservation names are in the same name
7625 space. So the reservation names should be different from the
7626 functional unit names and can not be the reserved name @samp{nothing}.
7628 @findex define_bypass
7629 @cindex instruction latency time
7631 The following construction is used to describe exceptions in the
7632 latency time for given instruction pair. This is so called bypasses.
7635 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
7639 @var{number} defines when the result generated by the instructions
7640 given in string @var{out_insn_names} will be ready for the
7641 instructions given in string @var{in_insn_names}. The instructions in
7642 the string are separated by commas.
7644 @var{guard} is an optional string giving the name of a C function which
7645 defines an additional guard for the bypass. The function will get the
7646 two insns as parameters. If the function returns zero the bypass will
7647 be ignored for this case. The additional guard is necessary to
7648 recognize complicated bypasses, e.g.@: when the consumer is only an address
7649 of insn @samp{store} (not a stored value).
7651 If there are more one bypass with the same output and input insns, the
7652 chosen bypass is the first bypass with a guard in description whose
7653 guard function returns nonzero. If there is no such bypass, then
7654 bypass without the guard function is chosen.
7656 @findex exclusion_set
7657 @findex presence_set
7658 @findex final_presence_set
7660 @findex final_absence_set
7663 The following five constructions are usually used to describe
7664 @acronym{VLIW} processors, or more precisely, to describe a placement
7665 of small instructions into @acronym{VLIW} instruction slots. They
7666 can be used for @acronym{RISC} processors, too.
7669 (exclusion_set @var{unit-names} @var{unit-names})
7670 (presence_set @var{unit-names} @var{patterns})
7671 (final_presence_set @var{unit-names} @var{patterns})
7672 (absence_set @var{unit-names} @var{patterns})
7673 (final_absence_set @var{unit-names} @var{patterns})
7676 @var{unit-names} is a string giving names of functional units
7677 separated by commas.
7679 @var{patterns} is a string giving patterns of functional units
7680 separated by comma. Currently pattern is one unit or units
7681 separated by white-spaces.
7683 The first construction (@samp{exclusion_set}) means that each
7684 functional unit in the first string can not be reserved simultaneously
7685 with a unit whose name is in the second string and vice versa. For
7686 example, the construction is useful for describing processors
7687 (e.g.@: some SPARC processors) with a fully pipelined floating point
7688 functional unit which can execute simultaneously only single floating
7689 point insns or only double floating point insns.
7691 The second construction (@samp{presence_set}) means that each
7692 functional unit in the first string can not be reserved unless at
7693 least one of pattern of units whose names are in the second string is
7694 reserved. This is an asymmetric relation. For example, it is useful
7695 for description that @acronym{VLIW} @samp{slot1} is reserved after
7696 @samp{slot0} reservation. We could describe it by the following
7700 (presence_set "slot1" "slot0")
7703 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
7704 reservation. In this case we could write
7707 (presence_set "slot1" "slot0 b0")
7710 The third construction (@samp{final_presence_set}) is analogous to
7711 @samp{presence_set}. The difference between them is when checking is
7712 done. When an instruction is issued in given automaton state
7713 reflecting all current and planned unit reservations, the automaton
7714 state is changed. The first state is a source state, the second one
7715 is a result state. Checking for @samp{presence_set} is done on the
7716 source state reservation, checking for @samp{final_presence_set} is
7717 done on the result reservation. This construction is useful to
7718 describe a reservation which is actually two subsequent reservations.
7719 For example, if we use
7722 (presence_set "slot1" "slot0")
7725 the following insn will be never issued (because @samp{slot1} requires
7726 @samp{slot0} which is absent in the source state).
7729 (define_reservation "insn_and_nop" "slot0 + slot1")
7732 but it can be issued if we use analogous @samp{final_presence_set}.
7734 The forth construction (@samp{absence_set}) means that each functional
7735 unit in the first string can be reserved only if each pattern of units
7736 whose names are in the second string is not reserved. This is an
7737 asymmetric relation (actually @samp{exclusion_set} is analogous to
7738 this one but it is symmetric). For example it might be useful in a
7739 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
7740 after either @samp{slot1} or @samp{slot2} have been reserved. This
7741 can be described as:
7744 (absence_set "slot0" "slot1, slot2")
7747 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
7748 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
7749 this case we could write
7752 (absence_set "slot2" "slot0 b0, slot1 b1")
7755 All functional units mentioned in a set should belong to the same
7758 The last construction (@samp{final_absence_set}) is analogous to
7759 @samp{absence_set} but checking is done on the result (state)
7760 reservation. See comments for @samp{final_presence_set}.
7762 @findex automata_option
7763 @cindex deterministic finite state automaton
7764 @cindex nondeterministic finite state automaton
7765 @cindex finite state automaton minimization
7766 You can control the generator of the pipeline hazard recognizer with
7767 the following construction.
7770 (automata_option @var{options})
7773 @var{options} is a string giving options which affect the generated
7774 code. Currently there are the following options:
7778 @dfn{no-minimization} makes no minimization of the automaton. This is
7779 only worth to do when we are debugging the description and need to
7780 look more accurately at reservations of states.
7783 @dfn{time} means printing time statistics about the generation of
7787 @dfn{stats} means printing statistics about the generated automata
7788 such as the number of DFA states, NDFA states and arcs.
7791 @dfn{v} means a generation of the file describing the result automata.
7792 The file has suffix @samp{.dfa} and can be used for the description
7793 verification and debugging.
7796 @dfn{w} means a generation of warning instead of error for
7797 non-critical errors.
7800 @dfn{ndfa} makes nondeterministic finite state automata. This affects
7801 the treatment of operator @samp{|} in the regular expressions. The
7802 usual treatment of the operator is to try the first alternative and,
7803 if the reservation is not possible, the second alternative. The
7804 nondeterministic treatment means trying all alternatives, some of them
7805 may be rejected by reservations in the subsequent insns.
7808 @dfn{progress} means output of a progress bar showing how many states
7809 were generated so far for automaton being processed. This is useful
7810 during debugging a @acronym{DFA} description. If you see too many
7811 generated states, you could interrupt the generator of the pipeline
7812 hazard recognizer and try to figure out a reason for generation of the
7816 As an example, consider a superscalar @acronym{RISC} machine which can
7817 issue three insns (two integer insns and one floating point insn) on
7818 the cycle but can finish only two insns. To describe this, we define
7819 the following functional units.
7822 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
7823 (define_cpu_unit "port0, port1")
7826 All simple integer insns can be executed in any integer pipeline and
7827 their result is ready in two cycles. The simple integer insns are
7828 issued into the first pipeline unless it is reserved, otherwise they
7829 are issued into the second pipeline. Integer division and
7830 multiplication insns can be executed only in the second integer
7831 pipeline and their results are ready correspondingly in 8 and 4
7832 cycles. The integer division is not pipelined, i.e.@: the subsequent
7833 integer division insn can not be issued until the current division
7834 insn finished. Floating point insns are fully pipelined and their
7835 results are ready in 3 cycles. Where the result of a floating point
7836 insn is used by an integer insn, an additional delay of one cycle is
7837 incurred. To describe all of this we could specify
7840 (define_cpu_unit "div")
7842 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7843 "(i0_pipeline | i1_pipeline), (port0 | port1)")
7845 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
7846 "i1_pipeline, nothing*2, (port0 | port1)")
7848 (define_insn_reservation "div" 8 (eq_attr "type" "div")
7849 "i1_pipeline, div*7, div + (port0 | port1)")
7851 (define_insn_reservation "float" 3 (eq_attr "type" "float")
7852 "f_pipeline, nothing, (port0 | port1))
7854 (define_bypass 4 "float" "simple,mult,div")
7857 To simplify the description we could describe the following reservation
7860 (define_reservation "finish" "port0|port1")
7863 and use it in all @code{define_insn_reservation} as in the following
7867 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7868 "(i0_pipeline | i1_pipeline), finish")
7874 @node Conditional Execution
7875 @section Conditional Execution
7876 @cindex conditional execution
7879 A number of architectures provide for some form of conditional
7880 execution, or predication. The hallmark of this feature is the
7881 ability to nullify most of the instructions in the instruction set.
7882 When the instruction set is large and not entirely symmetric, it
7883 can be quite tedious to describe these forms directly in the
7884 @file{.md} file. An alternative is the @code{define_cond_exec} template.
7886 @findex define_cond_exec
7889 [@var{predicate-pattern}]
7891 "@var{output-template}")
7894 @var{predicate-pattern} is the condition that must be true for the
7895 insn to be executed at runtime and should match a relational operator.
7896 One can use @code{match_operator} to match several relational operators
7897 at once. Any @code{match_operand} operands must have no more than one
7900 @var{condition} is a C expression that must be true for the generated
7903 @findex current_insn_predicate
7904 @var{output-template} is a string similar to the @code{define_insn}
7905 output template (@pxref{Output Template}), except that the @samp{*}
7906 and @samp{@@} special cases do not apply. This is only useful if the
7907 assembly text for the predicate is a simple prefix to the main insn.
7908 In order to handle the general case, there is a global variable
7909 @code{current_insn_predicate} that will contain the entire predicate
7910 if the current insn is predicated, and will otherwise be @code{NULL}.
7912 When @code{define_cond_exec} is used, an implicit reference to
7913 the @code{predicable} instruction attribute is made.
7914 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
7915 exactly two elements in its @var{list-of-values}). Further, it must
7916 not be used with complex expressions. That is, the default and all
7917 uses in the insns must be a simple constant, not dependent on the
7918 alternative or anything else.
7920 For each @code{define_insn} for which the @code{predicable}
7921 attribute is true, a new @code{define_insn} pattern will be
7922 generated that matches a predicated version of the instruction.
7926 (define_insn "addsi"
7927 [(set (match_operand:SI 0 "register_operand" "r")
7928 (plus:SI (match_operand:SI 1 "register_operand" "r")
7929 (match_operand:SI 2 "register_operand" "r")))]
7934 [(ne (match_operand:CC 0 "register_operand" "c")
7941 generates a new pattern
7946 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
7947 (set (match_operand:SI 0 "register_operand" "r")
7948 (plus:SI (match_operand:SI 1 "register_operand" "r")
7949 (match_operand:SI 2 "register_operand" "r"))))]
7950 "(@var{test2}) && (@var{test1})"
7951 "(%3) add %2,%1,%0")
7956 @node Constant Definitions
7957 @section Constant Definitions
7958 @cindex constant definitions
7959 @findex define_constants
7961 Using literal constants inside instruction patterns reduces legibility and
7962 can be a maintenance problem.
7964 To overcome this problem, you may use the @code{define_constants}
7965 expression. It contains a vector of name-value pairs. From that
7966 point on, wherever any of the names appears in the MD file, it is as
7967 if the corresponding value had been written instead. You may use
7968 @code{define_constants} multiple times; each appearance adds more
7969 constants to the table. It is an error to redefine a constant with
7972 To come back to the a29k load multiple example, instead of
7976 [(match_parallel 0 "load_multiple_operation"
7977 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7978 (match_operand:SI 2 "memory_operand" "m"))
7980 (clobber (reg:SI 179))])]
7996 [(match_parallel 0 "load_multiple_operation"
7997 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7998 (match_operand:SI 2 "memory_operand" "m"))
8000 (clobber (reg:SI R_CR))])]
8005 The constants that are defined with a define_constant are also output
8006 in the insn-codes.h header file as #defines.
8008 @cindex enumerations
8009 @findex define_c_enum
8010 You can also use the machine description file to define enumerations.
8011 Like the constants defined by @code{define_constant}, these enumerations
8012 are visible to both the machine description file and the main C code.
8014 The syntax is as follows:
8017 (define_c_enum "@var{name}" [
8025 This definition causes the equivalent of the following C code to appear
8026 in @file{insn-constants.h}:
8033 @var{valuen} = @var{n}
8035 #define NUM_@var{cname}_VALUES (@var{n} + 1)
8038 where @var{cname} is the capitalized form of @var{name}.
8039 It also makes each @var{valuei} available in the machine description
8040 file, just as if it had been declared with:
8043 (define_constants [(@var{valuei} @var{i})])
8046 Each @var{valuei} is usually an upper-case identifier and usually
8047 begins with @var{cname}.
8049 You can split the enumeration definition into as many statements as
8050 you like. The above example is directly equivalent to:
8053 (define_c_enum "@var{name}" [@var{value0}])
8054 (define_c_enum "@var{name}" [@var{value1}])
8056 (define_c_enum "@var{name}" [@var{valuen}])
8059 Splitting the enumeration helps to improve the modularity of each
8060 individual @code{.md} file. For example, if a port defines its
8061 synchronization instructions in a separate @file{sync.md} file,
8062 it is convenient to define all synchronization-specific enumeration
8063 values in @file{sync.md} rather than in the main @file{.md} file.
8065 Some enumeration names have special significance to GCC:
8069 @findex unspec_volatile
8070 If an enumeration called @code{unspecv} is defined, GCC will use it
8071 when printing out @code{unspec_volatile} expressions. For example:
8074 (define_c_enum "unspecv" [
8079 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
8082 (unspec_volatile ... UNSPECV_BLOCKAGE)
8087 If an enumeration called @code{unspec} is defined, GCC will use
8088 it when printing out @code{unspec} expressions. GCC will also use
8089 it when printing out @code{unspec_volatile} expressions unless an
8090 @code{unspecv} enumeration is also defined. You can therefore
8091 decide whether to keep separate enumerations for volatile and
8092 non-volatile expressions or whether to use the same enumeration
8097 @anchor{define_enum}
8098 Another way of defining an enumeration is to use @code{define_enum}:
8101 (define_enum "@var{name}" [
8109 This directive implies:
8112 (define_c_enum "@var{name}" [
8113 @var{cname}_@var{cvalue0}
8114 @var{cname}_@var{cvalue1}
8116 @var{cname}_@var{cvaluen}
8120 @findex define_enum_attr
8121 where @var{cvaluei} is the capitalized form of @var{valuei}.
8122 However, unlike @code{define_c_enum}, the enumerations defined
8123 by @code{define_enum} can be used in attribute specifications
8124 (@pxref{define_enum_attr}).
8129 @cindex iterators in @file{.md} files
8131 Ports often need to define similar patterns for more than one machine
8132 mode or for more than one rtx code. GCC provides some simple iterator
8133 facilities to make this process easier.
8136 * Mode Iterators:: Generating variations of patterns for different modes.
8137 * Code Iterators:: Doing the same for codes.
8140 @node Mode Iterators
8141 @subsection Mode Iterators
8142 @cindex mode iterators in @file{.md} files
8144 Ports often need to define similar patterns for two or more different modes.
8149 If a processor has hardware support for both single and double
8150 floating-point arithmetic, the @code{SFmode} patterns tend to be
8151 very similar to the @code{DFmode} ones.
8154 If a port uses @code{SImode} pointers in one configuration and
8155 @code{DImode} pointers in another, it will usually have very similar
8156 @code{SImode} and @code{DImode} patterns for manipulating pointers.
8159 Mode iterators allow several patterns to be instantiated from one
8160 @file{.md} file template. They can be used with any type of
8161 rtx-based construct, such as a @code{define_insn},
8162 @code{define_split}, or @code{define_peephole2}.
8165 * Defining Mode Iterators:: Defining a new mode iterator.
8166 * Substitutions:: Combining mode iterators with substitutions
8167 * Examples:: Examples
8170 @node Defining Mode Iterators
8171 @subsubsection Defining Mode Iterators
8172 @findex define_mode_iterator
8174 The syntax for defining a mode iterator is:
8177 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
8180 This allows subsequent @file{.md} file constructs to use the mode suffix
8181 @code{:@var{name}}. Every construct that does so will be expanded
8182 @var{n} times, once with every use of @code{:@var{name}} replaced by
8183 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
8184 and so on. In the expansion for a particular @var{modei}, every
8185 C condition will also require that @var{condi} be true.
8190 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
8193 defines a new mode suffix @code{:P}. Every construct that uses
8194 @code{:P} will be expanded twice, once with every @code{:P} replaced
8195 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
8196 The @code{:SI} version will only apply if @code{Pmode == SImode} and
8197 the @code{:DI} version will only apply if @code{Pmode == DImode}.
8199 As with other @file{.md} conditions, an empty string is treated
8200 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
8201 to @code{@var{mode}}. For example:
8204 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
8207 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
8208 but that the @code{:SI} expansion has no such constraint.
8210 Iterators are applied in the order they are defined. This can be
8211 significant if two iterators are used in a construct that requires
8212 substitutions. @xref{Substitutions}.
8215 @subsubsection Substitution in Mode Iterators
8216 @findex define_mode_attr
8218 If an @file{.md} file construct uses mode iterators, each version of the
8219 construct will often need slightly different strings or modes. For
8224 When a @code{define_expand} defines several @code{add@var{m}3} patterns
8225 (@pxref{Standard Names}), each expander will need to use the
8226 appropriate mode name for @var{m}.
8229 When a @code{define_insn} defines several instruction patterns,
8230 each instruction will often use a different assembler mnemonic.
8233 When a @code{define_insn} requires operands with different modes,
8234 using an iterator for one of the operand modes usually requires a specific
8235 mode for the other operand(s).
8238 GCC supports such variations through a system of ``mode attributes''.
8239 There are two standard attributes: @code{mode}, which is the name of
8240 the mode in lower case, and @code{MODE}, which is the same thing in
8241 upper case. You can define other attributes using:
8244 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
8247 where @var{name} is the name of the attribute and @var{valuei}
8248 is the value associated with @var{modei}.
8250 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
8251 each string and mode in the pattern for sequences of the form
8252 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
8253 mode attribute. If the attribute is defined for @var{mode}, the whole
8254 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
8257 For example, suppose an @file{.md} file has:
8260 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
8261 (define_mode_attr load [(SI "lw") (DI "ld")])
8264 If one of the patterns that uses @code{:P} contains the string
8265 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
8266 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
8269 Here is an example of using an attribute for a mode:
8272 (define_mode_iterator LONG [SI DI])
8273 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
8274 (define_insn @dots{}
8275 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
8278 The @code{@var{iterator}:} prefix may be omitted, in which case the
8279 substitution will be attempted for every iterator expansion.
8282 @subsubsection Mode Iterator Examples
8284 Here is an example from the MIPS port. It defines the following
8285 modes and attributes (among others):
8288 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
8289 (define_mode_attr d [(SI "") (DI "d")])
8292 and uses the following template to define both @code{subsi3}
8296 (define_insn "sub<mode>3"
8297 [(set (match_operand:GPR 0 "register_operand" "=d")
8298 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
8299 (match_operand:GPR 2 "register_operand" "d")))]
8302 [(set_attr "type" "arith")
8303 (set_attr "mode" "<MODE>")])
8306 This is exactly equivalent to:
8309 (define_insn "subsi3"
8310 [(set (match_operand:SI 0 "register_operand" "=d")
8311 (minus:SI (match_operand:SI 1 "register_operand" "d")
8312 (match_operand:SI 2 "register_operand" "d")))]
8315 [(set_attr "type" "arith")
8316 (set_attr "mode" "SI")])
8318 (define_insn "subdi3"
8319 [(set (match_operand:DI 0 "register_operand" "=d")
8320 (minus:DI (match_operand:DI 1 "register_operand" "d")
8321 (match_operand:DI 2 "register_operand" "d")))]
8324 [(set_attr "type" "arith")
8325 (set_attr "mode" "DI")])
8328 @node Code Iterators
8329 @subsection Code Iterators
8330 @cindex code iterators in @file{.md} files
8331 @findex define_code_iterator
8332 @findex define_code_attr
8334 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
8339 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
8342 defines a pseudo rtx code @var{name} that can be instantiated as
8343 @var{codei} if condition @var{condi} is true. Each @var{codei}
8344 must have the same rtx format. @xref{RTL Classes}.
8346 As with mode iterators, each pattern that uses @var{name} will be
8347 expanded @var{n} times, once with all uses of @var{name} replaced by
8348 @var{code1}, once with all uses replaced by @var{code2}, and so on.
8349 @xref{Defining Mode Iterators}.
8351 It is possible to define attributes for codes as well as for modes.
8352 There are two standard code attributes: @code{code}, the name of the
8353 code in lower case, and @code{CODE}, the name of the code in upper case.
8354 Other attributes are defined using:
8357 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
8360 Here's an example of code iterators in action, taken from the MIPS port:
8363 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
8364 eq ne gt ge lt le gtu geu ltu leu])
8366 (define_expand "b<code>"
8368 (if_then_else (any_cond:CC (cc0)
8370 (label_ref (match_operand 0 ""))
8374 gen_conditional_branch (operands, <CODE>);
8379 This is equivalent to:
8382 (define_expand "bunordered"
8384 (if_then_else (unordered:CC (cc0)
8386 (label_ref (match_operand 0 ""))
8390 gen_conditional_branch (operands, UNORDERED);
8394 (define_expand "bordered"
8396 (if_then_else (ordered:CC (cc0)
8398 (label_ref (match_operand 0 ""))
8402 gen_conditional_branch (operands, ORDERED);