1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Get Xtensa configuration settings */
23 #include "xtensa-config.h"
25 /* Standard GCC variables that we reference. */
26 extern int current_function_calls_alloca;
27 extern int target_flags;
30 /* External variables defined in xtensa.c. */
34 CMP_SI, /* four byte integers */
35 CMP_DI, /* eight byte integers */
36 CMP_SF, /* single precision floats */
37 CMP_DF, /* double precision floats */
38 CMP_MAX /* max comparison type */
41 extern struct rtx_def * branch_cmp[2]; /* operands for compare */
42 extern enum cmp_type branch_type; /* what type of branch to use */
43 extern unsigned xtensa_current_frame_size;
45 /* Masks for the -m switches */
46 #define MASK_NO_FUSED_MADD 0x00000001 /* avoid f-p mul/add */
47 #define MASK_CONST16 0x00000002 /* use CONST16 instruction */
49 /* Macros used in the machine description to select various Xtensa
50 configuration options. */
51 #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE
52 #define TARGET_DENSITY XCHAL_HAVE_DENSITY
53 #define TARGET_MAC16 XCHAL_HAVE_MAC16
54 #define TARGET_MUL16 XCHAL_HAVE_MUL16
55 #define TARGET_MUL32 XCHAL_HAVE_MUL32
56 #define TARGET_DIV32 XCHAL_HAVE_DIV32
57 #define TARGET_NSA XCHAL_HAVE_NSA
58 #define TARGET_MINMAX XCHAL_HAVE_MINMAX
59 #define TARGET_SEXT XCHAL_HAVE_SEXT
60 #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS
61 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP
62 #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV
63 #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP
64 #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT
65 #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT
66 #define TARGET_ABS XCHAL_HAVE_ABS
67 #define TARGET_ADDX XCHAL_HAVE_ADDX
69 /* Macros controlled by command-line options. */
70 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
71 #define TARGET_CONST16 (target_flags & MASK_CONST16)
73 #define TARGET_DEFAULT ( \
74 (XCHAL_HAVE_L32R ? 0 : MASK_CONST16))
76 #define TARGET_SWITCHES \
78 {"const16", MASK_CONST16, \
79 N_("Use CONST16 instruction to load constants")}, \
80 {"no-const16", -MASK_CONST16, \
81 N_("Use PC-relative L32R instruction to load constants")}, \
82 {"no-fused-madd", MASK_NO_FUSED_MADD, \
83 N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \
84 {"fused-madd", -MASK_NO_FUSED_MADD, \
85 N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \
86 {"text-section-literals", 0, \
87 N_("Intersperse literal pools with code in the text section")}, \
88 {"no-text-section-literals", 0, \
89 N_("Put literal pools in a separate literal section")}, \
91 N_("Automatically align branch targets to reduce branch penalties")}, \
92 {"no-target-align", 0, \
93 N_("Do not automatically align branch targets")}, \
95 N_("Use indirect CALLXn instructions for large programs")}, \
97 N_("Use direct CALLn instructions for fast calls")}, \
98 {"", TARGET_DEFAULT, 0} \
102 #define OVERRIDE_OPTIONS override_options ()
104 /* Target CPU builtins. */
105 #define TARGET_CPU_CPP_BUILTINS() \
107 builtin_assert ("cpu=xtensa"); \
108 builtin_assert ("machine=xtensa"); \
109 builtin_define ("__xtensa__"); \
110 builtin_define ("__XTENSA__"); \
111 builtin_define ("__XTENSA_WINDOWED_ABI__"); \
112 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
113 if (!TARGET_HARD_FLOAT) \
114 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
117 builtin_define ("__PIC__"); \
118 builtin_define ("__pic__"); \
122 #define CPP_SPEC " %(subtarget_cpp_spec) "
124 #ifndef SUBTARGET_CPP_SPEC
125 #define SUBTARGET_CPP_SPEC ""
128 #define EXTRA_SPECS \
129 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
132 #define LIBGCC2_WORDS_BIG_ENDIAN 1
134 #define LIBGCC2_WORDS_BIG_ENDIAN 0
137 /* Show we can debug even without a frame pointer. */
138 #define CAN_DEBUG_WITHOUT_FP
141 /* Target machine storage layout */
143 /* Define this if most significant bit is lowest numbered
144 in instructions that operate on numbered bit-fields. */
145 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
147 /* Define this if most significant byte of a word is the lowest numbered. */
148 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
150 /* Define this if most significant word of a multiword number is the lowest. */
151 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
153 #define MAX_BITS_PER_WORD 32
155 /* Width of a word, in units (bytes). */
156 #define UNITS_PER_WORD 4
157 #define MIN_UNITS_PER_WORD 4
159 /* Width of a floating point register. */
160 #define UNITS_PER_FPREG 4
162 /* Size in bits of various types on the target machine. */
163 #define INT_TYPE_SIZE 32
164 #define SHORT_TYPE_SIZE 16
165 #define LONG_TYPE_SIZE 32
166 #define LONG_LONG_TYPE_SIZE 64
167 #define FLOAT_TYPE_SIZE 32
168 #define DOUBLE_TYPE_SIZE 64
169 #define LONG_DOUBLE_TYPE_SIZE 64
171 /* Allocation boundary (in *bits*) for storing pointers in memory. */
172 #define POINTER_BOUNDARY 32
174 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
175 #define PARM_BOUNDARY 32
177 /* Allocation boundary (in *bits*) for the code of a function. */
178 #define FUNCTION_BOUNDARY 32
180 /* Alignment of field after 'int : 0' in a structure. */
181 #define EMPTY_FIELD_BOUNDARY 32
183 /* Every structure's size must be a multiple of this. */
184 #define STRUCTURE_SIZE_BOUNDARY 8
186 /* There is no point aligning anything to a rounder boundary than this. */
187 #define BIGGEST_ALIGNMENT 128
189 /* Set this nonzero if move instructions will actually fail to work
190 when given unaligned data. */
191 #define STRICT_ALIGNMENT 1
193 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
194 for QImode, because there is no 8-bit load from memory with sign
195 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
196 loads both with and without sign extension. */
197 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
199 if (GET_MODE_CLASS (MODE) == MODE_INT \
200 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
202 if ((MODE) == QImode) \
208 /* Imitate the way many other C compilers handle alignment of
209 bitfields and the structures that contain them. */
210 #define PCC_BITFIELD_TYPE_MATTERS 1
212 /* Disable the use of word-sized or smaller complex modes for structures,
213 and for function arguments in particular, where they cause problems with
214 register a7. The xtensa_copy_incoming_a7 function assumes that there is
215 a single reference to an argument in a7, but with small complex modes the
216 real and imaginary components may be extracted separately, leading to two
217 uses of the register, only one of which would be replaced. */
218 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
219 ((MODE) == CQImode || (MODE) == CHImode)
221 /* Align string constants and constructors to at least a word boundary.
222 The typical use of this macro is to increase alignment for string
223 constants to be word aligned so that 'strcpy' calls that copy
224 constants can be done inline. */
225 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
226 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
227 && (ALIGN) < BITS_PER_WORD \
231 /* Align arrays, unions and records to at least a word boundary.
232 One use of this macro is to increase alignment of medium-size
233 data to make it all fit in fewer cache lines. Another is to
234 cause character arrays to be word-aligned so that 'strcpy' calls
235 that copy constants to character arrays can be done inline. */
236 #undef DATA_ALIGNMENT
237 #define DATA_ALIGNMENT(TYPE, ALIGN) \
238 ((((ALIGN) < BITS_PER_WORD) \
239 && (TREE_CODE (TYPE) == ARRAY_TYPE \
240 || TREE_CODE (TYPE) == UNION_TYPE \
241 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
243 /* Operations between registers always perform the operation
244 on the full register even if a narrower mode is specified. */
245 #define WORD_REGISTER_OPERATIONS
247 /* Xtensa loads are zero-extended by default. */
248 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
250 /* Standard register usage. */
252 /* Number of actual hardware registers.
253 The hardware registers are assigned numbers for the compiler
254 from 0 to just below FIRST_PSEUDO_REGISTER.
255 All registers that the compiler knows about must be given numbers,
256 even those that are not normally considered general registers.
258 The fake frame pointer and argument pointer will never appear in
259 the generated code, since they will always be eliminated and replaced
260 by either the stack pointer or the hard frame pointer.
262 0 - 15 AR[0] - AR[15]
263 16 FRAME_POINTER (fake = initial sp)
264 17 ARG_POINTER (fake = initial sp + framesize)
265 18 BR[0] for floating-point CC
266 19 - 34 FR[0] - FR[15]
267 35 MAC16 accumulator */
269 #define FIRST_PSEUDO_REGISTER 36
271 /* Return the stabs register number to use for REGNO. */
272 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
274 /* 1 for registers that have pervasive standard uses
275 and are not available for the register allocator. */
276 #define FIXED_REGISTERS \
278 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
280 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
284 /* 1 for registers not available across function calls.
285 These must include the FIXED_REGISTERS and also any
286 registers that can be used without being saved.
287 The latter must include the registers where values are returned
288 and the register where structure-value addresses are passed.
289 Aside from that, you can include as many other registers as you like. */
290 #define CALL_USED_REGISTERS \
292 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
294 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
298 /* For non-leaf procedures on Xtensa processors, the allocation order
299 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
300 want to use the lowest numbered registers first to minimize
301 register window overflows. However, local-alloc is not smart
302 enough to consider conflicts with incoming arguments. If an
303 incoming argument in a2 is live throughout the function and
304 local-alloc decides to use a2, then the incoming argument must
305 either be spilled or copied to another register. To get around
306 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
307 reg_alloc_order for leaf functions such that lowest numbered
308 registers are used first with the exception that the incoming
309 argument registers are not used until after other register choices
310 have been exhausted. */
312 #define REG_ALLOC_ORDER \
313 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
315 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
320 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
322 /* For Xtensa, the only point of this is to prevent GCC from otherwise
323 giving preference to call-used registers. To minimize window
324 overflows for the AR registers, we want to give preference to the
325 lower-numbered AR registers. For other register files, which are
326 not windowed, we still prefer call-used registers, if there are any. */
327 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
328 #define LEAF_REGISTERS xtensa_leaf_regs
330 /* For Xtensa, no remapping is necessary, but this macro must be
331 defined if LEAF_REGISTERS is defined. */
332 #define LEAF_REG_REMAP(REGNO) (REGNO)
334 /* This must be declared if LEAF_REGISTERS is set. */
335 extern int leaf_function;
337 /* Internal macros to classify a register number. */
339 /* 16 address registers + fake registers */
340 #define GP_REG_FIRST 0
341 #define GP_REG_LAST 17
342 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
344 /* Coprocessor registers */
345 #define BR_REG_FIRST 18
346 #define BR_REG_LAST 18
347 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
349 /* 16 floating-point registers */
350 #define FP_REG_FIRST 19
351 #define FP_REG_LAST 34
352 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
354 /* MAC16 accumulator */
355 #define ACC_REG_FIRST 35
356 #define ACC_REG_LAST 35
357 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
359 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
360 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
361 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
362 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
364 /* Return number of consecutive hard regs needed starting at reg REGNO
365 to hold something of mode MODE. */
366 #define HARD_REGNO_NREGS(REGNO, MODE) \
367 (FP_REG_P (REGNO) ? \
368 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
369 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
371 /* Value is 1 if hard register REGNO can hold a value of machine-mode
373 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
375 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
376 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
378 /* Value is 1 if it is a good idea to tie two pseudo registers
379 when one has mode MODE1 and one has mode MODE2.
380 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
381 for any hard reg, then this must be 0 for correct output. */
382 #define MODES_TIEABLE_P(MODE1, MODE2) \
383 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
384 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
385 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
386 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
388 /* Register to use for pushing function arguments. */
389 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
391 /* Base register for access to local variables of the function. */
392 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
394 /* The register number of the frame pointer register, which is used to
395 access automatic variables in the stack frame. For Xtensa, this
396 register never appears in the output. It is always eliminated to
397 either the stack pointer or the hard frame pointer. */
398 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
400 /* Value should be nonzero if functions must have frame pointers.
401 Zero means the frame pointer need not be set up (and parms
402 may be accessed via the stack pointer) in functions that seem suitable.
403 This is computed in 'reload', in reload1.c. */
404 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
406 /* Base register for access to arguments of the function. */
407 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
409 /* If the static chain is passed in memory, these macros provide rtx
410 giving 'mem' expressions that denote where they are stored.
411 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
412 seen by the calling and called functions, respectively. */
414 #define STATIC_CHAIN \
415 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
417 #define STATIC_CHAIN_INCOMING \
418 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
420 /* For now we don't try to use the full set of boolean registers. Without
421 software pipelining of FP operations, there's not much to gain and it's
422 a real pain to get them reloaded. */
423 #define FPCC_REGNUM (BR_REG_FIRST + 0)
425 /* It is as good or better to call a constant function address than to
426 call an address kept in a register. */
427 #define NO_FUNCTION_CSE 1
429 /* Xtensa processors have "register windows". GCC does not currently
430 take advantage of the possibility for variable-sized windows; instead,
431 we use a fixed window size of 8. */
433 #define INCOMING_REGNO(OUT) \
434 ((GP_REG_P (OUT) && \
435 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
436 (OUT) - WINDOW_SIZE : (OUT))
438 #define OUTGOING_REGNO(IN) \
440 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
441 (IN) + WINDOW_SIZE : (IN))
444 /* Define the classes of registers for register constraints in the
445 machine description. */
448 NO_REGS, /* no registers in set */
449 BR_REGS, /* coprocessor boolean registers */
450 FP_REGS, /* floating point registers */
451 ACC_REG, /* MAC16 accumulator */
452 SP_REG, /* sp register (aka a1) */
453 RL_REGS, /* preferred reload regs (not sp or fp) */
454 GR_REGS, /* integer registers except sp */
455 AR_REGS, /* all integer registers */
456 ALL_REGS, /* all registers */
457 LIM_REG_CLASSES /* max value + 1 */
460 #define N_REG_CLASSES (int) LIM_REG_CLASSES
462 #define GENERAL_REGS AR_REGS
464 /* An initializer containing the names of the register classes as C
465 string constants. These names are used in writing some of the
467 #define REG_CLASS_NAMES \
480 /* Contents of the register classes. The Nth integer specifies the
481 contents of class N. The way the integer MASK is interpreted is
482 that register R is in the class if 'MASK & (1 << R)' is 1. */
483 #define REG_CLASS_CONTENTS \
485 { 0x00000000, 0x00000000 }, /* no registers */ \
486 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
487 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
488 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
489 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
490 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
491 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
492 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
493 { 0xffffffff, 0x0000000f } /* all registers */ \
496 /* A C expression whose value is a register class containing hard
497 register REGNO. In general there is more that one such class;
498 choose a class which is "minimal", meaning that no smaller class
499 also contains the register. */
500 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
502 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
504 /* Use the Xtensa AR register file for base registers.
505 No index registers. */
506 #define BASE_REG_CLASS AR_REGS
507 #define INDEX_REG_CLASS NO_REGS
509 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
510 16 AR registers may be explicitly used in the RTL, as either
511 incoming or outgoing arguments. */
512 #define SMALL_REGISTER_CLASSES 1
515 /* REGISTER AND CONSTANT CLASSES */
517 /* Get reg_class from a letter such as appears in the machine
520 Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z
522 DEFINED REGISTER CLASSES:
524 'a' general-purpose registers except sp
526 'D' general-purpose registers (only if density option enabled)
527 'd' general-purpose registers, including sp (only if density enabled)
528 'A' MAC16 accumulator (only if MAC16 option enabled)
529 'B' general-purpose registers (only if sext instruction enabled)
530 'C' general-purpose registers (only if mul16 option enabled)
531 'W' general-purpose registers (only if const16 option enabled)
532 'b' coprocessor boolean registers
533 'f' floating-point registers
536 extern enum reg_class xtensa_char_to_class[256];
538 #define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ]
540 /* The letters I, J, K, L, M, N, O, and P in a register constraint
541 string can be used to stand for particular ranges of immediate
542 operands. This macro defines what the ranges are. C is the
543 letter, and VALUE is a constant value. Return 1 if VALUE is
544 in the range specified by C.
548 I = 12-bit signed immediate for movi
549 J = 8-bit signed immediate for addi
550 K = 4-bit value in (b4const U {0})
551 L = 4-bit value in b4constu
552 M = 7-bit value in simm7
553 N = 8-bit unsigned immediate shifted left by 8 bits for addmi
554 O = 4-bit value in ai4const
555 P = valid immediate mask value for extui */
557 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
558 ((C) == 'I' ? (xtensa_simm12b (VALUE)) \
559 : (C) == 'J' ? (xtensa_simm8 (VALUE)) \
560 : (C) == 'K' ? (((VALUE) == 0) || xtensa_b4const (VALUE)) \
561 : (C) == 'L' ? (xtensa_b4constu (VALUE)) \
562 : (C) == 'M' ? (xtensa_simm7 (VALUE)) \
563 : (C) == 'N' ? (xtensa_simm8x256 (VALUE)) \
564 : (C) == 'O' ? (xtensa_ai4const (VALUE)) \
565 : (C) == 'P' ? (xtensa_mask_immediate (VALUE)) \
569 /* Similar, but for floating constants, and defining letters G and H.
570 Here VALUE is the CONST_DOUBLE rtx itself. */
571 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0)
574 /* Other letters can be defined in a machine-dependent fashion to
575 stand for particular classes of registers or other arbitrary
578 R = memory that can be accessed with a 4-bit unsigned offset
579 T = memory in a constant pool (addressable with a pc-relative load)
580 U = memory *NOT* in a constant pool
582 The offset range should not be checked here (except to distinguish
583 denser versions of the instructions for which more general versions
584 are available). Doing so leads to problems in reloading: an
585 argptr-relative address may become invalid when the phony argptr is
586 eliminated in favor of the stack pointer (the offset becomes too
587 large to fit in the instruction's immediate field); a reload is
588 generated to fix this but the RTL is not immediately updated; in
589 the meantime, the constraints are checked and none match. The
590 solution seems to be to simply skip the offset check here. The
591 address will be checked anyway because of the code in
592 GO_IF_LEGITIMATE_ADDRESS. */
594 #define EXTRA_CONSTRAINT(OP, CODE) \
595 ((GET_CODE (OP) != MEM) ? \
596 ((CODE) >= 'R' && (CODE) <= 'U' \
597 && reload_in_progress && GET_CODE (OP) == REG \
598 && REGNO (OP) >= FIRST_PSEUDO_REGISTER) \
599 : ((CODE) == 'R') ? smalloffset_mem_p (OP) \
600 : ((CODE) == 'T') ? !TARGET_CONST16 && constantpool_mem_p (OP) \
601 : ((CODE) == 'U') ? !constantpool_mem_p (OP) \
604 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
605 xtensa_preferred_reload_class (X, CLASS, 0)
607 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
608 xtensa_preferred_reload_class (X, CLASS, 1)
610 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
611 xtensa_secondary_reload_class (CLASS, MODE, X, 0)
613 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
614 xtensa_secondary_reload_class (CLASS, MODE, X, 1)
616 /* Return the maximum number of consecutive registers
617 needed to represent mode MODE in a register of class CLASS. */
618 #define CLASS_UNITS(mode, size) \
619 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
621 #define CLASS_MAX_NREGS(CLASS, MODE) \
622 (CLASS_UNITS (MODE, UNITS_PER_WORD))
625 /* Stack layout; function entry, exit and calling. */
627 #define STACK_GROWS_DOWNWARD
629 /* Offset within stack frame to start allocating local variables at. */
630 #define STARTING_FRAME_OFFSET \
631 current_function_outgoing_args_size
633 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
634 they are eliminated to either the stack pointer or hard frame pointer. */
635 #define ELIMINABLE_REGS \
636 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
637 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
638 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
639 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
641 #define CAN_ELIMINATE(FROM, TO) 1
643 /* Specify the initial difference between the specified pair of registers. */
644 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
646 compute_frame_size (get_frame_size ()); \
647 if ((FROM) == FRAME_POINTER_REGNUM) \
649 else if ((FROM) == ARG_POINTER_REGNUM) \
650 (OFFSET) = xtensa_current_frame_size; \
655 /* If defined, the maximum amount of space required for outgoing
656 arguments will be computed and placed into the variable
657 'current_function_outgoing_args_size'. No space will be pushed
658 onto the stack for each call; instead, the function prologue
659 should increase the stack frame size by this amount. */
660 #define ACCUMULATE_OUTGOING_ARGS 1
662 /* Offset from the argument pointer register to the first argument's
663 address. On some machines it may depend on the data type of the
664 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
665 location above the first argument's address. */
666 #define FIRST_PARM_OFFSET(FNDECL) 0
668 /* Align stack frames on 128 bits for Xtensa. This is necessary for
669 128-bit datatypes defined in TIE (e.g., for Vectra). */
670 #define STACK_BOUNDARY 128
672 /* Functions do not pop arguments off the stack. */
673 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
675 /* Use a fixed register window size of 8. */
676 #define WINDOW_SIZE 8
678 /* Symbolic macros for the registers used to return integer, floating
679 point, and values of coprocessor and user-defined modes. */
680 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
681 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
683 /* Symbolic macros for the first/last argument registers. */
684 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
685 #define GP_ARG_LAST (GP_REG_FIRST + 7)
686 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
687 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
689 #define MAX_ARGS_IN_REGISTERS 6
691 /* Don't worry about compatibility with PCC. */
692 #define DEFAULT_PCC_STRUCT_RETURN 0
694 /* Define how to find the value returned by a library function
695 assuming the value has mode MODE. Because we have defined
696 TARGET_PROMOTE_FUNCTION_RETURN that returns true, we have to
697 perform the same promotions as PROMOTE_MODE. */
698 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
699 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
700 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
702 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
704 #define LIBCALL_VALUE(MODE) \
705 XTENSA_LIBCALL_VALUE ((MODE), 0)
707 #define LIBCALL_OUTGOING_VALUE(MODE) \
708 XTENSA_LIBCALL_VALUE ((MODE), 1)
710 /* Define how to find the value returned by a function.
711 VALTYPE is the data type of the value (as a tree).
712 If the precise function being called is known, FUNC is its FUNCTION_DECL;
713 otherwise, FUNC is 0. */
714 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \
715 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
716 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
717 ? SImode: TYPE_MODE (VALTYPE), \
718 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
720 #define FUNCTION_VALUE(VALTYPE, FUNC) \
721 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
723 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
724 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
726 /* A C expression that is nonzero if REGNO is the number of a hard
727 register in which the values of called function may come back. A
728 register whose use for returning values is limited to serving as
729 the second of a pair (for a value of type 'double', say) need not
730 be recognized by this macro. If the machine has register windows,
731 so that the caller and the called function use different registers
732 for the return value, this macro should recognize only the caller's
734 #define FUNCTION_VALUE_REGNO_P(N) \
737 /* A C expression that is nonzero if REGNO is the number of a hard
738 register in which function arguments are sometimes passed. This
739 does *not* include implicit arguments such as the static chain and
740 the structure-value address. On many machines, no registers can be
741 used for this purpose since all function arguments are pushed on
743 #define FUNCTION_ARG_REGNO_P(N) \
744 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
746 /* Record the number of argument words seen so far, along with a flag to
747 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG
748 is used for both incoming and outgoing args, so a separate flag is
750 typedef struct xtensa_args
756 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
757 init_cumulative_args (&CUM, 0)
759 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
760 init_cumulative_args (&CUM, 1)
762 /* Update the data in CUM to advance over an argument
763 of mode MODE and data type TYPE.
764 (TYPE is null for libcalls where that information may not be available.) */
765 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
766 function_arg_advance (&CUM, MODE, TYPE)
768 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
769 function_arg (&CUM, MODE, TYPE, FALSE)
771 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
772 function_arg (&CUM, MODE, TYPE, TRUE)
774 /* Specify function argument alignment. */
775 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
777 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
779 : TYPE_ALIGN (TYPE)) \
780 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
782 : GET_MODE_ALIGNMENT (MODE)))
784 /* Profiling Xtensa code is typically done with the built-in profiling
785 feature of Tensilica's instruction set simulator, which does not
786 require any compiler support. Profiling code on a real (i.e.,
787 non-simulated) Xtensa processor is currently only supported by
788 GNU/Linux with glibc. The glibc version of _mcount doesn't require
789 counter variables. The _mcount function needs the current PC and
790 the current return address to identify an arc in the call graph.
791 Pass the current return address as the first argument; the current
792 PC is available as a0 in _mcount's register window. Both of these
793 values contain window size information in the two most significant
794 bits; we assume that _mcount will mask off those bits. The call to
795 _mcount uses a window size of 8 to make sure that it doesn't clobber
796 any incoming argument values. */
798 #define NO_PROFILE_COUNTERS 1
800 #define FUNCTION_PROFILER(FILE, LABELNO) \
802 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
805 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \
806 fprintf (FILE, "\tcallx8\ta8\n"); \
809 fprintf (FILE, "\tcall8\t_mcount\n"); \
812 /* Stack pointer value doesn't matter at exit. */
813 #define EXIT_IGNORE_STACK 1
815 /* A C statement to output, on the stream FILE, assembler code for a
816 block of data that contains the constant parts of a trampoline.
817 This code should not include a label--the label is taken care of
820 For Xtensa, the trampoline must perform an entry instruction with a
821 minimal stack frame in order to get some free registers. Once the
822 actual call target is known, the proper stack frame size is extracted
823 from the entry instruction at the target and the current frame is
824 adjusted to match. The trampoline then transfers control to the
825 instruction following the entry at the target. Note: this assumes
826 that the target begins with an entry instruction. */
828 /* minimum frame = reg save area (4 words) plus static chain (1 word)
829 and the total number of words must be a multiple of 128 bits */
830 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
832 #define TRAMPOLINE_TEMPLATE(STREAM) \
834 fprintf (STREAM, "\t.begin no-transform\n"); \
835 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \
837 /* save the return address */ \
838 fprintf (STREAM, "\tmov\ta10, a0\n"); \
840 /* Use a CALL0 instruction to skip past the constants and in the \
841 process get the PC into A0. This allows PC-relative access to \
842 the constants without relying on L32R, which may not always be \
845 fprintf (STREAM, "\tcall0\t.Lskipconsts\n"); \
846 fprintf (STREAM, "\t.align\t4\n"); \
847 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \
848 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \
849 fprintf (STREAM, ".Lskipconsts:\n"); \
851 /* store the static chain */ \
852 fprintf (STREAM, "\taddi\ta0, a0, 3\n"); \
853 fprintf (STREAM, "\tl32i\ta8, a0, 0\n"); \
854 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", MIN_FRAME_SIZE - 20); \
856 /* set the proper stack pointer value */ \
857 fprintf (STREAM, "\tl32i\ta8, a0, 4\n"); \
858 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \
859 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \
860 TARGET_BIG_ENDIAN ? 8 : 12); \
861 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \
862 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \
863 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \
864 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \
866 /* restore the return address */ \
867 fprintf (STREAM, "\tmov\ta0, a10\n"); \
869 /* jump to the instruction following the entry */ \
870 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \
871 fprintf (STREAM, "\tjx\ta8\n"); \
872 fprintf (STREAM, "\t.end no-transform\n"); \
875 /* Size in bytes of the trampoline, as an integer. */
876 #define TRAMPOLINE_SIZE 59
878 /* Alignment required for trampolines, in bits. */
879 #define TRAMPOLINE_ALIGNMENT (32)
881 /* A C statement to initialize the variable parts of a trampoline. */
882 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
885 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
886 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 16)), FUNC); \
887 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"), \
888 0, VOIDmode, 1, addr, Pmode); \
891 /* Implement `va_start' for varargs and stdarg. */
892 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
893 xtensa_va_start (valist, nextarg)
895 /* If defined, a C expression that produces the machine-specific code
896 to setup the stack so that arbitrary frames can be accessed.
898 On Xtensa, a stack back-trace must always begin from the stack pointer,
899 so that the register overflow save area can be located. However, the
900 stack-walking code in GCC always begins from the hard_frame_pointer
901 register, not the stack pointer. The frame pointer is usually equal
902 to the stack pointer, but the __builtin_return_address and
903 __builtin_frame_address functions will not work if count > 0 and
904 they are called from a routine that uses alloca. These functions
905 are not guaranteed to work at all if count > 0 so maybe that is OK.
907 A nicer solution would be to allow the architecture-specific files to
908 specify whether to start from the stack pointer or frame pointer. That
909 would also allow us to skip the machine->accesses_prev_frame stuff that
910 we currently need to ensure that there is a frame pointer when these
911 builtin functions are used. */
913 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
915 /* A C expression whose value is RTL representing the address in a
916 stack frame where the pointer to the caller's frame is stored.
917 Assume that FRAMEADDR is an RTL expression for the address of the
920 For Xtensa, there is no easy way to get the frame pointer if it is
921 not equivalent to the stack pointer. Moreover, the result of this
922 macro is used for continuing to walk back up the stack, so it must
923 return the stack pointer address. Thus, there is some inconsistency
924 here in that __builtin_frame_address will return the frame pointer
925 when count == 0 and the stack pointer when count > 0. */
927 #define DYNAMIC_CHAIN_ADDRESS(frame) \
928 gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD))
930 /* Define this if the return address of a particular stack frame is
931 accessed from the frame pointer of the previous stack frame. */
932 #define RETURN_ADDR_IN_PREVIOUS_FRAME
934 /* A C expression whose value is RTL representing the value of the
935 return address for the frame COUNT steps up from the current
936 frame, after the prologue. */
937 #define RETURN_ADDR_RTX xtensa_return_addr
939 /* Addressing modes, and classification of registers for them. */
941 /* C expressions which are nonzero if register number NUM is suitable
942 for use as a base or index register in operand addresses. It may
943 be either a suitable hard register or a pseudo register that has
944 been allocated such a hard register. The difference between an
945 index register and a base register is that the index register may
948 #define REGNO_OK_FOR_BASE_P(NUM) \
949 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
951 #define REGNO_OK_FOR_INDEX_P(NUM) 0
953 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
954 valid for use as a base or index register. For hard registers, it
955 should always accept those which the hardware permits and reject
956 the others. Whether the macro accepts or rejects pseudo registers
957 must be controlled by `REG_OK_STRICT'. This usually requires two
958 variant definitions, of which `REG_OK_STRICT' controls the one
959 actually used. The difference between an index register and a base
960 register is that the index register may be scaled. */
964 #define REG_OK_FOR_INDEX_P(X) 0
965 #define REG_OK_FOR_BASE_P(X) \
966 REGNO_OK_FOR_BASE_P (REGNO (X))
968 #else /* !REG_OK_STRICT */
970 #define REG_OK_FOR_INDEX_P(X) 0
971 #define REG_OK_FOR_BASE_P(X) \
972 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X))))
974 #endif /* !REG_OK_STRICT */
976 /* Maximum number of registers that can appear in a valid memory address. */
977 #define MAX_REGS_PER_ADDRESS 1
979 /* Identify valid Xtensa addresses. */
980 #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \
982 rtx xinsn = (ADDR); \
984 /* allow constant pool addresses */ \
985 if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \
986 && !TARGET_CONST16 && constantpool_address_p (xinsn)) \
989 while (GET_CODE (xinsn) == SUBREG) \
990 xinsn = SUBREG_REG (xinsn); \
992 /* allow base registers */ \
993 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
996 /* check for "register + offset" addressing */ \
997 if (GET_CODE (xinsn) == PLUS) \
999 rtx xplus0 = XEXP (xinsn, 0); \
1000 rtx xplus1 = XEXP (xinsn, 1); \
1001 enum rtx_code code0; \
1002 enum rtx_code code1; \
1004 while (GET_CODE (xplus0) == SUBREG) \
1005 xplus0 = SUBREG_REG (xplus0); \
1006 code0 = GET_CODE (xplus0); \
1008 while (GET_CODE (xplus1) == SUBREG) \
1009 xplus1 = SUBREG_REG (xplus1); \
1010 code1 = GET_CODE (xplus1); \
1012 /* swap operands if necessary so the register is first */ \
1013 if (code0 != REG && code1 == REG) \
1015 xplus0 = XEXP (xinsn, 1); \
1016 xplus1 = XEXP (xinsn, 0); \
1017 code0 = GET_CODE (xplus0); \
1018 code1 = GET_CODE (xplus1); \
1021 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
1022 && code1 == CONST_INT \
1023 && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \
1030 /* A C expression that is 1 if the RTX X is a constant which is a
1031 valid address. This is defined to be the same as 'CONSTANT_P (X)',
1032 but rejecting CONST_DOUBLE. */
1033 #define CONSTANT_ADDRESS_P(X) \
1034 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1035 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1036 || (GET_CODE (X) == CONST)))
1038 /* Nonzero if the constant value X is a legitimate general operand.
1039 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1040 #define LEGITIMATE_CONSTANT_P(X) 1
1042 /* A C expression that is nonzero if X is a legitimate immediate
1043 operand on the target machine when generating position independent
1045 #define LEGITIMATE_PIC_OPERAND_P(X) \
1046 ((GET_CODE (X) != SYMBOL_REF \
1047 || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \
1048 && GET_CODE (X) != LABEL_REF \
1049 && GET_CODE (X) != CONST)
1051 /* Tell GCC how to use ADDMI to generate addresses. */
1052 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1055 if (GET_CODE (xinsn) == PLUS) \
1057 rtx plus0 = XEXP (xinsn, 0); \
1058 rtx plus1 = XEXP (xinsn, 1); \
1060 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \
1062 plus0 = XEXP (xinsn, 1); \
1063 plus1 = XEXP (xinsn, 0); \
1066 if (GET_CODE (plus0) == REG \
1067 && GET_CODE (plus1) == CONST_INT \
1068 && !xtensa_mem_offset (INTVAL (plus1), MODE) \
1069 && !xtensa_simm8 (INTVAL (plus1)) \
1070 && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \
1071 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \
1073 rtx temp = gen_reg_rtx (Pmode); \
1074 emit_insn (gen_rtx_SET (Pmode, temp, \
1075 gen_rtx_PLUS (Pmode, plus0, \
1076 GEN_INT (INTVAL (plus1) & ~0xff)))); \
1077 (X) = gen_rtx_PLUS (Pmode, temp, \
1078 GEN_INT (INTVAL (plus1) & 0xff)); \
1085 /* Treat constant-pool references as "mode dependent" since they can
1086 only be accessed with SImode loads. This works around a bug in the
1087 combiner where a constant pool reference is temporarily converted
1088 to an HImode load, which is then assumed to zero-extend based on
1089 our definition of LOAD_EXTEND_OP. This is wrong because the high
1090 bits of a 16-bit value in the constant pool are now sign-extended
1093 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1095 if (constantpool_address_p (ADDR)) \
1099 /* Specify the machine mode that this machine uses
1100 for the index in the tablejump instruction. */
1101 #define CASE_VECTOR_MODE (SImode)
1103 /* Define this as 1 if 'char' should by default be signed; else as 0. */
1104 #define DEFAULT_SIGNED_CHAR 0
1106 /* Max number of bytes we can move from memory to memory
1107 in one reasonably fast instruction. */
1109 #define MAX_MOVE_MAX 4
1111 /* Prefer word-sized loads. */
1112 #define SLOW_BYTE_ACCESS 1
1114 /* Shift instructions ignore all but the low-order few bits. */
1115 #define SHIFT_COUNT_TRUNCATED 1
1117 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1118 is done just by pretending it is already truncated. */
1119 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1121 /* Specify the machine mode that pointers have.
1122 After generation of rtl, the compiler makes no further distinction
1123 between pointers and any other objects of this machine mode. */
1124 #define Pmode SImode
1126 /* A function address in a call instruction is a word address (for
1127 indexing purposes) so give the MEM rtx a words's mode. */
1128 #define FUNCTION_MODE SImode
1130 /* A C expression for the cost of moving data from a register in
1131 class FROM to one in class TO. The classes are expressed using
1132 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
1133 the default; other values are interpreted relative to that. */
1134 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1135 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
1137 : (reg_class_subset_p ((FROM), AR_REGS) \
1138 && reg_class_subset_p ((TO), AR_REGS) \
1140 : (reg_class_subset_p ((FROM), AR_REGS) \
1141 && (TO) == ACC_REG \
1143 : ((FROM) == ACC_REG \
1144 && reg_class_subset_p ((TO), AR_REGS) \
1148 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
1150 #define BRANCH_COST 3
1152 /* Optionally define this if you have added predicates to
1153 'MACHINE.c'. This macro is called within an initializer of an
1154 array of structures. The first field in the structure is the
1155 name of a predicate and the second field is an array of rtl
1156 codes. For each predicate, list all rtl codes that can be in
1157 expressions matched by the predicate. The list should have a
1160 #define PREDICATE_CODES \
1161 {"add_operand", { REG, CONST_INT, SUBREG }}, \
1162 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
1163 {"nonimmed_operand", { REG, SUBREG, MEM }}, \
1164 {"mem_operand", { MEM }}, \
1165 {"mask_operand", { REG, CONST_INT, SUBREG }}, \
1166 {"extui_fldsz_operand", { CONST_INT }}, \
1167 {"sext_fldsz_operand", { CONST_INT }}, \
1168 {"lsbitnum_operand", { CONST_INT }}, \
1169 {"fpmem_offset_operand", { CONST_INT }}, \
1170 {"sext_operand", { REG, SUBREG, MEM }}, \
1171 {"branch_operand", { REG, CONST_INT, SUBREG }}, \
1172 {"ubranch_operand", { REG, CONST_INT, SUBREG }}, \
1173 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG }}, \
1174 {"move_operand", { REG, SUBREG, MEM, CONST_INT, CONST_DOUBLE, \
1175 CONST, SYMBOL_REF, LABEL_REF }}, \
1176 {"const_float_1_operand", { CONST_DOUBLE }}, \
1177 {"branch_operator", { EQ, NE, LT, GE }}, \
1178 {"ubranch_operator", { LTU, GEU }}, \
1179 {"boolean_operator", { EQ, NE }},
1181 /* Control the assembler format that we output. */
1183 /* How to refer to registers in assembler output.
1184 This sequence is indexed by compiler's hard-register-number (see above). */
1185 #define REGISTER_NAMES \
1187 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
1188 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
1189 "fp", "argp", "b0", \
1190 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1191 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
1195 /* If defined, a C initializer for an array of structures containing a
1196 name and a register number. This macro defines additional names
1197 for hard registers, thus allowing the 'asm' option in declarations
1198 to refer to registers using alternate names. */
1199 #define ADDITIONAL_REGISTER_NAMES \
1201 { "a1", 1 + GP_REG_FIRST } \
1204 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1205 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1207 /* Recognize machine-specific patterns that may appear within
1208 constants. Used for PIC-specific UNSPECs. */
1209 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
1211 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
1213 switch (XINT ((X), 1)) \
1216 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
1217 fputs ("@PLT", (STREAM)); \
1228 /* Globalizing directive for a label. */
1229 #define GLOBAL_ASM_OP "\t.global\t"
1231 /* Declare an uninitialized external linkage data object. */
1232 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1233 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1235 /* This is how to output an element of a case-vector that is absolute. */
1236 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1237 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
1238 LOCAL_LABEL_PREFIX, VALUE)
1240 /* This is how to output an element of a case-vector that is relative.
1241 This is used for pc-relative code. */
1242 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1244 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
1245 LOCAL_LABEL_PREFIX, (VALUE), \
1246 LOCAL_LABEL_PREFIX, (REL)); \
1249 /* This is how to output an assembler line that says to advance the
1250 location counter to a multiple of 2**LOG bytes. */
1251 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
1254 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
1257 /* Indicate that jump tables go in the text section. This is
1258 necessary when compiling PIC code. */
1259 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1262 /* Define the strings to put out for each section in the object file. */
1263 #define TEXT_SECTION_ASM_OP "\t.text"
1264 #define DATA_SECTION_ASM_OP "\t.data"
1265 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1268 /* Define output to appear before the constant pool. If the function
1269 has been assigned to a specific ELF section, or if it goes into a
1270 unique section, set the name of that section to be the literal
1272 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
1275 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
1276 fnsection = DECL_SECTION_NAME (FUNDECL); \
1277 if (fnsection != NULL_TREE) \
1279 const char *fnsectname = TREE_STRING_POINTER (fnsection); \
1280 fprintf (FILE, "\t.begin\tliteral_prefix %s\n", \
1281 strcmp (fnsectname, ".text") ? fnsectname : ""); \
1285 function_section (FUNDECL); \
1286 fprintf (FILE, "\t.literal_position\n"); \
1291 /* Define code to write out the ".end literal_prefix" directive for a
1292 function in a special section. This is appended to the standard ELF
1293 code for ASM_DECLARE_FUNCTION_SIZE. */
1294 #define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
1295 if (DECL_SECTION_NAME (DECL) != NULL_TREE) \
1296 fprintf (FILE, "\t.end\tliteral_prefix\n")
1298 /* A C statement (with or without semicolon) to output a constant in
1299 the constant pool, if it needs special treatment. */
1300 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1302 xtensa_output_literal (FILE, X, MODE, LABELNO); \
1306 /* How to start an assembler comment. */
1307 #define ASM_COMMENT_START "#"
1309 /* Exception handling TODO!! */
1310 #define DWARF_UNWIND_INFO 0
1312 /* Xtensa constant pool breaks the devices in crtstuff.c to control
1313 section in where code resides. We have to write it as asm code. Use
1314 a MOVI and let the assembler relax it -- for the .init and .fini
1315 sections, the assembler knows to put the literal in the right
1317 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1318 asm (SECTION_OP "\n\
1319 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
1321 TEXT_SECTION_ASM_OP);
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