1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright 2001,2002,2003 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Get Xtensa configuration settings */
23 #include "xtensa-config.h"
25 /* Standard GCC variables that we reference. */
26 extern int current_function_calls_alloca;
27 extern int target_flags;
30 /* External variables defined in xtensa.c. */
34 CMP_SI, /* four byte integers */
35 CMP_DI, /* eight byte integers */
36 CMP_SF, /* single precision floats */
37 CMP_DF, /* double precision floats */
38 CMP_MAX /* max comparison type */
41 extern struct rtx_def * branch_cmp[2]; /* operands for compare */
42 extern enum cmp_type branch_type; /* what type of branch to use */
43 extern unsigned xtensa_current_frame_size;
45 /* Run-time compilation parameters selecting different hardware subsets. */
47 #define MASK_BIG_ENDIAN 0x00000001 /* big or little endian */
48 #define MASK_DENSITY 0x00000002 /* code density option */
49 #define MASK_MAC16 0x00000004 /* MAC16 option */
50 #define MASK_MUL16 0x00000008 /* 16-bit integer multiply */
51 #define MASK_MUL32 0x00000010 /* integer multiply/divide */
52 #define MASK_DIV32 0x00000020 /* integer multiply/divide */
53 #define MASK_NSA 0x00000040 /* nsa instruction option */
54 #define MASK_MINMAX 0x00000080 /* min/max instructions */
55 #define MASK_SEXT 0x00000100 /* sign extend insn option */
56 #define MASK_BOOLEANS 0x00000200 /* boolean register option */
57 #define MASK_HARD_FLOAT 0x00000400 /* floating-point option */
58 #define MASK_HARD_FLOAT_DIV 0x00000800 /* floating-point divide */
59 #define MASK_HARD_FLOAT_RECIP 0x00001000 /* floating-point reciprocal */
60 #define MASK_HARD_FLOAT_SQRT 0x00002000 /* floating-point sqrt */
61 #define MASK_HARD_FLOAT_RSQRT 0x00004000 /* floating-point recip sqrt */
62 #define MASK_NO_FUSED_MADD 0x00008000 /* avoid f-p mul/add */
63 #define MASK_CONST16 0x00010000 /* use CONST16 instruction */
64 #define MASK_ABS 0x00020000 /* use ABS instruction */
65 #define MASK_ADDX 0x00040000 /* use ADDX* and SUBX* */
67 /* Macros used in the machine description to test the flags. */
69 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
70 #define TARGET_DENSITY (target_flags & MASK_DENSITY)
71 #define TARGET_MAC16 (target_flags & MASK_MAC16)
72 #define TARGET_MUL16 (target_flags & MASK_MUL16)
73 #define TARGET_MUL32 (target_flags & MASK_MUL32)
74 #define TARGET_DIV32 (target_flags & MASK_DIV32)
75 #define TARGET_NSA (target_flags & MASK_NSA)
76 #define TARGET_MINMAX (target_flags & MASK_MINMAX)
77 #define TARGET_SEXT (target_flags & MASK_SEXT)
78 #define TARGET_BOOLEANS (target_flags & MASK_BOOLEANS)
79 #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
80 #define TARGET_HARD_FLOAT_DIV (target_flags & MASK_HARD_FLOAT_DIV)
81 #define TARGET_HARD_FLOAT_RECIP (target_flags & MASK_HARD_FLOAT_RECIP)
82 #define TARGET_HARD_FLOAT_SQRT (target_flags & MASK_HARD_FLOAT_SQRT)
83 #define TARGET_HARD_FLOAT_RSQRT (target_flags & MASK_HARD_FLOAT_RSQRT)
84 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
85 #define TARGET_CONST16 (target_flags & MASK_CONST16)
86 #define TARGET_ABS (target_flags & MASK_ABS)
87 #define TARGET_ADDX (target_flags & MASK_ADDX)
89 /* Default target_flags if no switches are specified */
91 #define TARGET_DEFAULT ( \
92 (XCHAL_HAVE_BE ? MASK_BIG_ENDIAN : 0) | \
93 (XCHAL_HAVE_DENSITY ? MASK_DENSITY : 0) | \
94 (XCHAL_HAVE_L32R ? 0 : MASK_CONST16) | \
95 (XCHAL_HAVE_ABS ? MASK_ABS : 0) | \
96 (XCHAL_HAVE_ADDX ? MASK_ADDX : 0) | \
97 (XCHAL_HAVE_MAC16 ? MASK_MAC16 : 0) | \
98 (XCHAL_HAVE_MUL16 ? MASK_MUL16 : 0) | \
99 (XCHAL_HAVE_MUL32 ? MASK_MUL32 : 0) | \
100 (XCHAL_HAVE_DIV32 ? MASK_DIV32 : 0) | \
101 (XCHAL_HAVE_NSA ? MASK_NSA : 0) | \
102 (XCHAL_HAVE_MINMAX ? MASK_MINMAX : 0) | \
103 (XCHAL_HAVE_SEXT ? MASK_SEXT : 0) | \
104 (XCHAL_HAVE_BOOLEANS ? MASK_BOOLEANS : 0) | \
105 (XCHAL_HAVE_FP ? MASK_HARD_FLOAT : 0) | \
106 (XCHAL_HAVE_FP_DIV ? MASK_HARD_FLOAT_DIV : 0) | \
107 (XCHAL_HAVE_FP_RECIP ? MASK_HARD_FLOAT_RECIP : 0) | \
108 (XCHAL_HAVE_FP_SQRT ? MASK_HARD_FLOAT_SQRT : 0) | \
109 (XCHAL_HAVE_FP_RSQRT ? MASK_HARD_FLOAT_RSQRT : 0))
111 /* Macro to define tables used to set the flags. */
113 #define TARGET_SWITCHES \
115 {"big-endian", MASK_BIG_ENDIAN, \
116 N_("Use big-endian byte order")}, \
117 {"little-endian", -MASK_BIG_ENDIAN, \
118 N_("Use little-endian byte order")}, \
119 {"density", MASK_DENSITY, \
120 N_("Use the Xtensa code density option")}, \
121 {"no-density", -MASK_DENSITY, \
122 N_("Do not use the Xtensa code density option")}, \
123 {"const16", MASK_CONST16, \
124 N_("Use CONST16 instruction to load constants")}, \
125 {"no-const16", -MASK_CONST16, \
126 N_("Use PC-relative L32R instruction to load constants")}, \
128 N_("Use the Xtensa ABS instruction")}, \
129 {"no-abs", -MASK_ABS, \
130 N_("Do not use the Xtensa ABS instruction")}, \
131 {"addx", MASK_ADDX, \
132 N_("Use the Xtensa ADDX and SUBX instructions")}, \
133 {"no-addx", -MASK_ADDX, \
134 N_("Do not use the Xtensa ADDX and SUBX instructions")}, \
135 {"mac16", MASK_MAC16, \
136 N_("Use the Xtensa MAC16 option")}, \
137 {"no-mac16", -MASK_MAC16, \
138 N_("Do not use the Xtensa MAC16 option")}, \
139 {"mul16", MASK_MUL16, \
140 N_("Use the Xtensa MUL16 option")}, \
141 {"no-mul16", -MASK_MUL16, \
142 N_("Do not use the Xtensa MUL16 option")}, \
143 {"mul32", MASK_MUL32, \
144 N_("Use the Xtensa MUL32 option")}, \
145 {"no-mul32", -MASK_MUL32, \
146 N_("Do not use the Xtensa MUL32 option")}, \
147 {"div32", MASK_DIV32, \
148 0 /* undocumented */}, \
149 {"no-div32", -MASK_DIV32, \
150 0 /* undocumented */}, \
152 N_("Use the Xtensa NSA option")}, \
153 {"no-nsa", -MASK_NSA, \
154 N_("Do not use the Xtensa NSA option")}, \
155 {"minmax", MASK_MINMAX, \
156 N_("Use the Xtensa MIN/MAX option")}, \
157 {"no-minmax", -MASK_MINMAX, \
158 N_("Do not use the Xtensa MIN/MAX option")}, \
159 {"sext", MASK_SEXT, \
160 N_("Use the Xtensa SEXT option")}, \
161 {"no-sext", -MASK_SEXT, \
162 N_("Do not use the Xtensa SEXT option")}, \
163 {"booleans", MASK_BOOLEANS, \
164 N_("Use the Xtensa boolean register option")}, \
165 {"no-booleans", -MASK_BOOLEANS, \
166 N_("Do not use the Xtensa boolean register option")}, \
167 {"hard-float", MASK_HARD_FLOAT, \
168 N_("Use the Xtensa floating-point unit")}, \
169 {"soft-float", -MASK_HARD_FLOAT, \
170 N_("Do not use the Xtensa floating-point unit")}, \
171 {"hard-float-div", MASK_HARD_FLOAT_DIV, \
172 0 /* undocumented */}, \
173 {"no-hard-float-div", -MASK_HARD_FLOAT_DIV, \
174 0 /* undocumented */}, \
175 {"hard-float-recip", MASK_HARD_FLOAT_RECIP, \
176 0 /* undocumented */}, \
177 {"no-hard-float-recip", -MASK_HARD_FLOAT_RECIP, \
178 0 /* undocumented */}, \
179 {"hard-float-sqrt", MASK_HARD_FLOAT_SQRT, \
180 0 /* undocumented */}, \
181 {"no-hard-float-sqrt", -MASK_HARD_FLOAT_SQRT, \
182 0 /* undocumented */}, \
183 {"hard-float-rsqrt", MASK_HARD_FLOAT_RSQRT, \
184 0 /* undocumented */}, \
185 {"no-hard-float-rsqrt", -MASK_HARD_FLOAT_RSQRT, \
186 0 /* undocumented */}, \
187 {"no-fused-madd", MASK_NO_FUSED_MADD, \
188 N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \
189 {"fused-madd", -MASK_NO_FUSED_MADD, \
190 N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \
191 {"text-section-literals", 0, \
192 N_("Intersperse literal pools with code in the text section")}, \
193 {"no-text-section-literals", 0, \
194 N_("Put literal pools in a separate literal section")}, \
195 {"target-align", 0, \
196 N_("Automatically align branch targets to reduce branch penalties")}, \
197 {"no-target-align", 0, \
198 N_("Do not automatically align branch targets")}, \
200 N_("Use indirect CALLXn instructions for large programs")}, \
201 {"no-longcalls", 0, \
202 N_("Use direct CALLn instructions for fast calls")}, \
203 {"", TARGET_DEFAULT, 0} \
207 #define OVERRIDE_OPTIONS override_options ()
209 /* Target CPU builtins. */
210 #define TARGET_CPU_CPP_BUILTINS() \
212 builtin_assert ("cpu=xtensa"); \
213 builtin_assert ("machine=xtensa"); \
214 builtin_define ("__XTENSA__"); \
215 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
216 if (!TARGET_HARD_FLOAT) \
217 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
220 builtin_define ("__PIC__"); \
221 builtin_define ("__pic__"); \
225 #define CPP_SPEC " %(subtarget_cpp_spec) "
227 #ifndef SUBTARGET_CPP_SPEC
228 #define SUBTARGET_CPP_SPEC ""
231 #define EXTRA_SPECS \
232 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
235 #define LIBGCC2_WORDS_BIG_ENDIAN 1
237 #define LIBGCC2_WORDS_BIG_ENDIAN 0
240 /* Show we can debug even without a frame pointer. */
241 #define CAN_DEBUG_WITHOUT_FP
244 /* Target machine storage layout */
246 /* Define this if most significant bit is lowest numbered
247 in instructions that operate on numbered bit-fields. */
248 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
250 /* Define this if most significant byte of a word is the lowest numbered. */
251 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
253 /* Define this if most significant word of a multiword number is the lowest. */
254 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
256 #define MAX_BITS_PER_WORD 32
258 /* Width of a word, in units (bytes). */
259 #define UNITS_PER_WORD 4
260 #define MIN_UNITS_PER_WORD 4
262 /* Width of a floating point register. */
263 #define UNITS_PER_FPREG 4
265 /* Size in bits of various types on the target machine. */
266 #define INT_TYPE_SIZE 32
267 #define SHORT_TYPE_SIZE 16
268 #define LONG_TYPE_SIZE 32
269 #define MAX_LONG_TYPE_SIZE 32
270 #define LONG_LONG_TYPE_SIZE 64
271 #define FLOAT_TYPE_SIZE 32
272 #define DOUBLE_TYPE_SIZE 64
273 #define LONG_DOUBLE_TYPE_SIZE 64
275 /* Allocation boundary (in *bits*) for storing pointers in memory. */
276 #define POINTER_BOUNDARY 32
278 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
279 #define PARM_BOUNDARY 32
281 /* Allocation boundary (in *bits*) for the code of a function. */
282 #define FUNCTION_BOUNDARY 32
284 /* Alignment of field after 'int : 0' in a structure. */
285 #define EMPTY_FIELD_BOUNDARY 32
287 /* Every structure's size must be a multiple of this. */
288 #define STRUCTURE_SIZE_BOUNDARY 8
290 /* There is no point aligning anything to a rounder boundary than this. */
291 #define BIGGEST_ALIGNMENT 128
293 /* Set this nonzero if move instructions will actually fail to work
294 when given unaligned data. */
295 #define STRICT_ALIGNMENT 1
297 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
298 for QImode, because there is no 8-bit load from memory with sign
299 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
300 loads both with and without sign extension. */
301 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
303 if (GET_MODE_CLASS (MODE) == MODE_INT \
304 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
306 if ((MODE) == QImode) \
312 /* The promotion described by `PROMOTE_MODE' should also be done for
313 outgoing function arguments. */
314 #define PROMOTE_FUNCTION_ARGS
316 /* The promotion described by `PROMOTE_MODE' should also be done for
317 the return value of functions. Note: `FUNCTION_VALUE' must perform
318 the same promotions done by `PROMOTE_MODE'. */
319 #define PROMOTE_FUNCTION_RETURN
321 /* Imitate the way many other C compilers handle alignment of
322 bitfields and the structures that contain them. */
323 #define PCC_BITFIELD_TYPE_MATTERS 1
325 /* Align string constants and constructors to at least a word boundary.
326 The typical use of this macro is to increase alignment for string
327 constants to be word aligned so that 'strcpy' calls that copy
328 constants can be done inline. */
329 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
330 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
331 && (ALIGN) < BITS_PER_WORD \
335 /* Align arrays, unions and records to at least a word boundary.
336 One use of this macro is to increase alignment of medium-size
337 data to make it all fit in fewer cache lines. Another is to
338 cause character arrays to be word-aligned so that 'strcpy' calls
339 that copy constants to character arrays can be done inline. */
340 #undef DATA_ALIGNMENT
341 #define DATA_ALIGNMENT(TYPE, ALIGN) \
342 ((((ALIGN) < BITS_PER_WORD) \
343 && (TREE_CODE (TYPE) == ARRAY_TYPE \
344 || TREE_CODE (TYPE) == UNION_TYPE \
345 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
347 /* An argument declared as 'char' or 'short' in a prototype should
348 actually be passed as an 'int'. */
349 #define PROMOTE_PROTOTYPES 1
351 /* Operations between registers always perform the operation
352 on the full register even if a narrower mode is specified. */
353 #define WORD_REGISTER_OPERATIONS
355 /* Xtensa loads are zero-extended by default. */
356 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
358 /* Standard register usage. */
360 /* Number of actual hardware registers.
361 The hardware registers are assigned numbers for the compiler
362 from 0 to just below FIRST_PSEUDO_REGISTER.
363 All registers that the compiler knows about must be given numbers,
364 even those that are not normally considered general registers.
366 The fake frame pointer and argument pointer will never appear in
367 the generated code, since they will always be eliminated and replaced
368 by either the stack pointer or the hard frame pointer.
370 0 - 15 AR[0] - AR[15]
371 16 FRAME_POINTER (fake = initial sp)
372 17 ARG_POINTER (fake = initial sp + framesize)
373 18 BR[0] for floating-point CC
374 19 - 34 FR[0] - FR[15]
375 35 MAC16 accumulator */
377 #define FIRST_PSEUDO_REGISTER 36
379 /* Return the stabs register number to use for REGNO. */
380 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
382 /* 1 for registers that have pervasive standard uses
383 and are not available for the register allocator. */
384 #define FIXED_REGISTERS \
386 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
388 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
392 /* 1 for registers not available across function calls.
393 These must include the FIXED_REGISTERS and also any
394 registers that can be used without being saved.
395 The latter must include the registers where values are returned
396 and the register where structure-value addresses are passed.
397 Aside from that, you can include as many other registers as you like. */
398 #define CALL_USED_REGISTERS \
400 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
402 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
406 /* For non-leaf procedures on Xtensa processors, the allocation order
407 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
408 want to use the lowest numbered registers first to minimize
409 register window overflows. However, local-alloc is not smart
410 enough to consider conflicts with incoming arguments. If an
411 incoming argument in a2 is live throughout the function and
412 local-alloc decides to use a2, then the incoming argument must
413 either be spilled or copied to another register. To get around
414 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
415 reg_alloc_order for leaf functions such that lowest numbered
416 registers are used first with the exception that the incoming
417 argument registers are not used until after other register choices
418 have been exhausted. */
420 #define REG_ALLOC_ORDER \
421 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
423 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
428 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
430 /* For Xtensa, the only point of this is to prevent GCC from otherwise
431 giving preference to call-used registers. To minimize window
432 overflows for the AR registers, we want to give preference to the
433 lower-numbered AR registers. For other register files, which are
434 not windowed, we still prefer call-used registers, if there are any. */
435 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
436 #define LEAF_REGISTERS xtensa_leaf_regs
438 /* For Xtensa, no remapping is necessary, but this macro must be
439 defined if LEAF_REGISTERS is defined. */
440 #define LEAF_REG_REMAP(REGNO) (REGNO)
442 /* this must be declared if LEAF_REGISTERS is set */
443 extern int leaf_function;
445 /* Internal macros to classify a register number. */
447 /* 16 address registers + fake registers */
448 #define GP_REG_FIRST 0
449 #define GP_REG_LAST 17
450 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
452 /* Coprocessor registers */
453 #define BR_REG_FIRST 18
454 #define BR_REG_LAST 18
455 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
457 /* 16 floating-point registers */
458 #define FP_REG_FIRST 19
459 #define FP_REG_LAST 34
460 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
462 /* MAC16 accumulator */
463 #define ACC_REG_FIRST 35
464 #define ACC_REG_LAST 35
465 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
467 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
468 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
469 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
470 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
472 /* Return number of consecutive hard regs needed starting at reg REGNO
473 to hold something of mode MODE. */
474 #define HARD_REGNO_NREGS(REGNO, MODE) \
475 (FP_REG_P (REGNO) ? \
476 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
477 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
479 /* Value is 1 if hard register REGNO can hold a value of machine-mode
481 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
483 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
484 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
486 /* Value is 1 if it is a good idea to tie two pseudo registers
487 when one has mode MODE1 and one has mode MODE2.
488 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
489 for any hard reg, then this must be 0 for correct output. */
490 #define MODES_TIEABLE_P(MODE1, MODE2) \
491 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
492 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
493 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
494 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
496 /* Register to use for pushing function arguments. */
497 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
499 /* Base register for access to local variables of the function. */
500 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
502 /* The register number of the frame pointer register, which is used to
503 access automatic variables in the stack frame. For Xtensa, this
504 register never appears in the output. It is always eliminated to
505 either the stack pointer or the hard frame pointer. */
506 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
508 /* Value should be nonzero if functions must have frame pointers.
509 Zero means the frame pointer need not be set up (and parms
510 may be accessed via the stack pointer) in functions that seem suitable.
511 This is computed in 'reload', in reload1.c. */
512 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
514 /* Base register for access to arguments of the function. */
515 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
517 /* If the static chain is passed in memory, these macros provide rtx
518 giving 'mem' expressions that denote where they are stored.
519 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
520 seen by the calling and called functions, respectively. */
522 #define STATIC_CHAIN \
523 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
525 #define STATIC_CHAIN_INCOMING \
526 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
528 /* For now we don't try to use the full set of boolean registers. Without
529 software pipelining of FP operations, there's not much to gain and it's
530 a real pain to get them reloaded. */
531 #define FPCC_REGNUM (BR_REG_FIRST + 0)
533 /* Pass structure value address as an "invisible" first argument. */
534 #define STRUCT_VALUE 0
536 /* It is as good or better to call a constant function address than to
537 call an address kept in a register. */
538 #define NO_FUNCTION_CSE 1
540 /* It is as good or better for a function to call itself with an
541 explicit address than to call an address kept in a register. */
542 #define NO_RECURSIVE_FUNCTION_CSE 1
544 /* Xtensa processors have "register windows". GCC does not currently
545 take advantage of the possibility for variable-sized windows; instead,
546 we use a fixed window size of 8. */
548 #define INCOMING_REGNO(OUT) \
549 ((GP_REG_P (OUT) && \
550 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
551 (OUT) - WINDOW_SIZE : (OUT))
553 #define OUTGOING_REGNO(IN) \
555 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
556 (IN) + WINDOW_SIZE : (IN))
559 /* Define the classes of registers for register constraints in the
560 machine description. */
563 NO_REGS, /* no registers in set */
564 BR_REGS, /* coprocessor boolean registers */
565 FP_REGS, /* floating point registers */
566 ACC_REG, /* MAC16 accumulator */
567 SP_REG, /* sp register (aka a1) */
568 RL_REGS, /* preferred reload regs (not sp or fp) */
569 GR_REGS, /* integer registers except sp */
570 AR_REGS, /* all integer registers */
571 ALL_REGS, /* all registers */
572 LIM_REG_CLASSES /* max value + 1 */
575 #define N_REG_CLASSES (int) LIM_REG_CLASSES
577 #define GENERAL_REGS AR_REGS
579 /* An initializer containing the names of the register classes as C
580 string constants. These names are used in writing some of the
582 #define REG_CLASS_NAMES \
595 /* Contents of the register classes. The Nth integer specifies the
596 contents of class N. The way the integer MASK is interpreted is
597 that register R is in the class if 'MASK & (1 << R)' is 1. */
598 #define REG_CLASS_CONTENTS \
600 { 0x00000000, 0x00000000 }, /* no registers */ \
601 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
602 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
603 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
604 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
605 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
606 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
607 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
608 { 0xffffffff, 0x0000000f } /* all registers */ \
611 /* A C expression whose value is a register class containing hard
612 register REGNO. In general there is more that one such class;
613 choose a class which is "minimal", meaning that no smaller class
614 also contains the register. */
615 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
617 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
619 /* Use the Xtensa AR register file for base registers.
620 No index registers. */
621 #define BASE_REG_CLASS AR_REGS
622 #define INDEX_REG_CLASS NO_REGS
624 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
625 16 AR registers may be explicitly used in the RTL, as either
626 incoming or outgoing arguments. */
627 #define SMALL_REGISTER_CLASSES 1
630 /* REGISTER AND CONSTANT CLASSES */
632 /* Get reg_class from a letter such as appears in the machine
635 Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z
637 DEFINED REGISTER CLASSES:
639 'a' general-purpose registers except sp
641 'D' general-purpose registers (only if density option enabled)
642 'd' general-purpose registers, including sp (only if density enabled)
643 'A' MAC16 accumulator (only if MAC16 option enabled)
644 'B' general-purpose registers (only if sext instruction enabled)
645 'C' general-purpose registers (only if mul16 option enabled)
646 'W' general-purpose registers (only if const16 option enabled)
647 'b' coprocessor boolean registers
648 'f' floating-point registers
651 extern enum reg_class xtensa_char_to_class[256];
653 #define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ]
655 /* The letters I, J, K, L, M, N, O, and P in a register constraint
656 string can be used to stand for particular ranges of immediate
657 operands. This macro defines what the ranges are. C is the
658 letter, and VALUE is a constant value. Return 1 if VALUE is
659 in the range specified by C.
663 I = 12-bit signed immediate for movi
664 J = 8-bit signed immediate for addi
665 K = 4-bit value in (b4const U {0})
666 L = 4-bit value in b4constu
667 M = 7-bit value in simm7
668 N = 8-bit unsigned immediate shifted left by 8 bits for addmi
669 O = 4-bit value in ai4const
670 P = valid immediate mask value for extui */
672 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
673 ((C) == 'I' ? (xtensa_simm12b (VALUE)) \
674 : (C) == 'J' ? (xtensa_simm8 (VALUE)) \
675 : (C) == 'K' ? (((VALUE) == 0) || xtensa_b4const (VALUE)) \
676 : (C) == 'L' ? (xtensa_b4constu (VALUE)) \
677 : (C) == 'M' ? (xtensa_simm7 (VALUE)) \
678 : (C) == 'N' ? (xtensa_simm8x256 (VALUE)) \
679 : (C) == 'O' ? (xtensa_ai4const (VALUE)) \
680 : (C) == 'P' ? (xtensa_mask_immediate (VALUE)) \
684 /* Similar, but for floating constants, and defining letters G and H.
685 Here VALUE is the CONST_DOUBLE rtx itself. */
686 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0)
689 /* Other letters can be defined in a machine-dependent fashion to
690 stand for particular classes of registers or other arbitrary
693 R = memory that can be accessed with a 4-bit unsigned offset
694 T = memory in a constant pool (addressable with a pc-relative load)
695 U = memory *NOT* in a constant pool
697 The offset range should not be checked here (except to distinguish
698 denser versions of the instructions for which more general versions
699 are available). Doing so leads to problems in reloading: an
700 argptr-relative address may become invalid when the phony argptr is
701 eliminated in favor of the stack pointer (the offset becomes too
702 large to fit in the instruction's immediate field); a reload is
703 generated to fix this but the RTL is not immediately updated; in
704 the meantime, the constraints are checked and none match. The
705 solution seems to be to simply skip the offset check here. The
706 address will be checked anyway because of the code in
707 GO_IF_LEGITIMATE_ADDRESS. */
709 #define EXTRA_CONSTRAINT(OP, CODE) \
710 ((GET_CODE (OP) != MEM) ? \
711 ((CODE) >= 'R' && (CODE) <= 'U' \
712 && reload_in_progress && GET_CODE (OP) == REG \
713 && REGNO (OP) >= FIRST_PSEUDO_REGISTER) \
714 : ((CODE) == 'R') ? smalloffset_mem_p (OP) \
715 : ((CODE) == 'T') ? !TARGET_CONST16 && constantpool_mem_p (OP) \
716 : ((CODE) == 'U') ? !constantpool_mem_p (OP) \
719 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
720 xtensa_preferred_reload_class (X, CLASS, 0)
722 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
723 xtensa_preferred_reload_class (X, CLASS, 1)
725 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
726 xtensa_secondary_reload_class (CLASS, MODE, X, 0)
728 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
729 xtensa_secondary_reload_class (CLASS, MODE, X, 1)
731 /* Return the maximum number of consecutive registers
732 needed to represent mode MODE in a register of class CLASS. */
733 #define CLASS_UNITS(mode, size) \
734 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
736 #define CLASS_MAX_NREGS(CLASS, MODE) \
737 (CLASS_UNITS (MODE, UNITS_PER_WORD))
740 /* Stack layout; function entry, exit and calling. */
742 #define STACK_GROWS_DOWNWARD
744 /* Offset within stack frame to start allocating local variables at. */
745 #define STARTING_FRAME_OFFSET \
746 current_function_outgoing_args_size
748 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
749 they are eliminated to either the stack pointer or hard frame pointer. */
750 #define ELIMINABLE_REGS \
751 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
752 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
753 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
754 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
756 #define CAN_ELIMINATE(FROM, TO) 1
758 /* Specify the initial difference between the specified pair of registers. */
759 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
761 compute_frame_size (get_frame_size ()); \
762 if ((FROM) == FRAME_POINTER_REGNUM) \
764 else if ((FROM) == ARG_POINTER_REGNUM) \
765 (OFFSET) = xtensa_current_frame_size; \
770 /* If defined, the maximum amount of space required for outgoing
771 arguments will be computed and placed into the variable
772 'current_function_outgoing_args_size'. No space will be pushed
773 onto the stack for each call; instead, the function prologue
774 should increase the stack frame size by this amount. */
775 #define ACCUMULATE_OUTGOING_ARGS 1
777 /* Offset from the argument pointer register to the first argument's
778 address. On some machines it may depend on the data type of the
779 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
780 location above the first argument's address. */
781 #define FIRST_PARM_OFFSET(FNDECL) 0
783 /* Align stack frames on 128 bits for Xtensa. This is necessary for
784 128-bit datatypes defined in TIE (e.g., for Vectra). */
785 #define STACK_BOUNDARY 128
787 /* Functions do not pop arguments off the stack. */
788 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
790 /* Use a fixed register window size of 8. */
791 #define WINDOW_SIZE 8
793 /* Symbolic macros for the registers used to return integer, floating
794 point, and values of coprocessor and user-defined modes. */
795 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
796 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
798 /* Symbolic macros for the first/last argument registers. */
799 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
800 #define GP_ARG_LAST (GP_REG_FIRST + 7)
801 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
802 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
804 #define MAX_ARGS_IN_REGISTERS 6
806 /* Don't worry about compatibility with PCC. */
807 #define DEFAULT_PCC_STRUCT_RETURN 0
809 /* For Xtensa, up to 4 words can be returned in registers. (It would
810 have been nice to allow up to 6 words in registers but GCC cannot
811 support that. The return value must be given one of the standard
812 MODE_INT modes, and there is no 6 word mode. Instead, if we try to
813 return a 6 word structure, GCC selects the next biggest mode
814 (OImode, 8 words) and then the register allocator fails because
815 there is no 8-register group beginning with a10.) */
816 #define RETURN_IN_MEMORY(TYPE) \
817 ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 4 * UNITS_PER_WORD)
819 /* Define how to find the value returned by a library function
820 assuming the value has mode MODE. Because we have defined
821 PROMOTE_FUNCTION_RETURN, we have to perform the same promotions as
823 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
824 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
825 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
827 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
829 #define LIBCALL_VALUE(MODE) \
830 XTENSA_LIBCALL_VALUE ((MODE), 0)
832 #define LIBCALL_OUTGOING_VALUE(MODE) \
833 XTENSA_LIBCALL_VALUE ((MODE), 1)
835 /* Define how to find the value returned by a function.
836 VALTYPE is the data type of the value (as a tree).
837 If the precise function being called is known, FUNC is its FUNCTION_DECL;
838 otherwise, FUNC is 0. */
839 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \
840 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
841 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
842 ? SImode: TYPE_MODE (VALTYPE), \
843 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
845 #define FUNCTION_VALUE(VALTYPE, FUNC) \
846 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
848 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
849 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
851 /* A C expression that is nonzero if REGNO is the number of a hard
852 register in which the values of called function may come back. A
853 register whose use for returning values is limited to serving as
854 the second of a pair (for a value of type 'double', say) need not
855 be recognized by this macro. If the machine has register windows,
856 so that the caller and the called function use different registers
857 for the return value, this macro should recognize only the caller's
859 #define FUNCTION_VALUE_REGNO_P(N) \
862 /* A C expression that is nonzero if REGNO is the number of a hard
863 register in which function arguments are sometimes passed. This
864 does *not* include implicit arguments such as the static chain and
865 the structure-value address. On many machines, no registers can be
866 used for this purpose since all function arguments are pushed on
868 #define FUNCTION_ARG_REGNO_P(N) \
869 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
871 /* Define a data type for recording info about an argument list
872 during the scan of that argument list. This data type should
873 hold all necessary information about the function itself
874 and about the args processed so far, enough to enable macros
875 such as FUNCTION_ARG to determine where the next arg should go. */
876 typedef struct xtensa_args {
877 int arg_words; /* # total words the arguments take */
880 /* Initialize a variable CUM of type CUMULATIVE_ARGS
881 for a call to a function whose data type is FNTYPE.
882 For a library call, FNTYPE is 0. */
883 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
884 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
886 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
887 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
889 /* Update the data in CUM to advance over an argument
890 of mode MODE and data type TYPE.
891 (TYPE is null for libcalls where that information may not be available.) */
892 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
893 function_arg_advance (&CUM, MODE, TYPE)
895 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
896 function_arg (&CUM, MODE, TYPE, FALSE)
898 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
899 function_arg (&CUM, MODE, TYPE, TRUE)
901 /* Arguments are never passed partly in memory and partly in registers. */
902 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
904 /* Specify function argument alignment. */
905 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
907 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
909 : TYPE_ALIGN (TYPE)) \
910 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
912 : GET_MODE_ALIGNMENT (MODE)))
915 /* Nonzero if we do not know how to pass TYPE solely in registers.
916 We cannot do so in the following cases:
918 - if the type has variable size
919 - if the type is marked as addressable (it is required to be constructed
922 This differs from the default in that it does not check if the padding
923 and mode of the type are such that a copy into a register would put it
924 into the wrong part of the register. */
926 #define MUST_PASS_IN_STACK(MODE, TYPE) \
928 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
929 || TREE_ADDRESSABLE (TYPE)))
931 /* Profiling Xtensa code is typically done with the built-in profiling
932 feature of Tensilica's instruction set simulator, which does not
933 require any compiler support. Profiling code on a real (i.e.,
934 non-simulated) Xtensa processor is currently only supported by
935 GNU/Linux with glibc. The glibc version of _mcount doesn't require
936 counter variables. The _mcount function needs the current PC and
937 the current return address to identify an arc in the call graph.
938 Pass the current return address as the first argument; the current
939 PC is available as a0 in _mcount's register window. Both of these
940 values contain window size information in the two most significant
941 bits; we assume that _mcount will mask off those bits. The call to
942 _mcount uses a window size of 8 to make sure that it doesn't clobber
943 any incoming argument values. */
945 #define NO_PROFILE_COUNTERS 1
947 #define FUNCTION_PROFILER(FILE, LABELNO) \
949 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
952 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \
953 fprintf (FILE, "\tcallx8\ta8\n"); \
956 fprintf (FILE, "\tcall8\t_mcount\n"); \
959 /* Stack pointer value doesn't matter at exit. */
960 #define EXIT_IGNORE_STACK 1
962 /* A C statement to output, on the stream FILE, assembler code for a
963 block of data that contains the constant parts of a trampoline.
964 This code should not include a label--the label is taken care of
967 For Xtensa, the trampoline must perform an entry instruction with a
968 minimal stack frame in order to get some free registers. Once the
969 actual call target is known, the proper stack frame size is extracted
970 from the entry instruction at the target and the current frame is
971 adjusted to match. The trampoline then transfers control to the
972 instruction following the entry at the target. Note: this assumes
973 that the target begins with an entry instruction. */
975 /* minimum frame = reg save area (4 words) plus static chain (1 word)
976 and the total number of words must be a multiple of 128 bits */
977 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
979 #define TRAMPOLINE_TEMPLATE(STREAM) \
981 fprintf (STREAM, "\t.begin no-generics\n"); \
982 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \
984 /* save the return address */ \
985 fprintf (STREAM, "\tmov\ta10, a0\n"); \
987 /* Use a CALL0 instruction to skip past the constants and in the \
988 process get the PC into A0. This allows PC-relative access to \
989 the constants without relying on L32R, which may not always be \
992 fprintf (STREAM, "\tcall0\t.Lskipconsts\n"); \
993 fprintf (STREAM, "\t.align\t4\n"); \
994 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \
995 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \
996 fprintf (STREAM, ".Lskipconsts:\n"); \
998 /* store the static chain */ \
999 fprintf (STREAM, "\taddi\ta0, a0, 3\n"); \
1000 fprintf (STREAM, "\tl32i\ta8, a0, 0\n"); \
1001 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", MIN_FRAME_SIZE - 20); \
1003 /* set the proper stack pointer value */ \
1004 fprintf (STREAM, "\tl32i\ta8, a0, 4\n"); \
1005 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \
1006 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \
1007 TARGET_BIG_ENDIAN ? 8 : 12); \
1008 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \
1009 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \
1010 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \
1011 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \
1013 /* restore the return address */ \
1014 fprintf (STREAM, "\tmov\ta0, a10\n"); \
1016 /* jump to the instruction following the entry */ \
1017 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \
1018 fprintf (STREAM, "\tjx\ta8\n"); \
1019 fprintf (STREAM, "\t.end no-generics\n"); \
1022 /* Size in bytes of the trampoline, as an integer. */
1023 #define TRAMPOLINE_SIZE 59
1025 /* Alignment required for trampolines, in bits. */
1026 #define TRAMPOLINE_ALIGNMENT (32)
1028 /* A C statement to initialize the variable parts of a trampoline. */
1029 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
1032 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
1033 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 16)), FUNC); \
1034 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__xtensa_sync_caches"), \
1035 0, VOIDmode, 1, addr, Pmode); \
1038 /* Define the `__builtin_va_list' type for the ABI. */
1039 #define BUILD_VA_LIST_TYPE(VALIST) \
1040 (VALIST) = xtensa_build_va_list ()
1042 /* If defined, is a C expression that produces the machine-specific
1043 code for a call to '__builtin_saveregs'. This code will be moved
1044 to the very beginning of the function, before any parameter access
1045 are made. The return value of this function should be an RTX that
1046 contains the value to use as the return of '__builtin_saveregs'. */
1047 #define EXPAND_BUILTIN_SAVEREGS \
1048 xtensa_builtin_saveregs
1050 /* Implement `va_start' for varargs and stdarg. */
1051 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1052 xtensa_va_start (valist, nextarg)
1054 /* Implement `va_arg'. */
1055 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1056 xtensa_va_arg (valist, type)
1058 /* If defined, a C expression that produces the machine-specific code
1059 to setup the stack so that arbitrary frames can be accessed.
1061 On Xtensa, a stack back-trace must always begin from the stack pointer,
1062 so that the register overflow save area can be located. However, the
1063 stack-walking code in GCC always begins from the hard_frame_pointer
1064 register, not the stack pointer. The frame pointer is usually equal
1065 to the stack pointer, but the __builtin_return_address and
1066 __builtin_frame_address functions will not work if count > 0 and
1067 they are called from a routine that uses alloca. These functions
1068 are not guaranteed to work at all if count > 0 so maybe that is OK.
1070 A nicer solution would be to allow the architecture-specific files to
1071 specify whether to start from the stack pointer or frame pointer. That
1072 would also allow us to skip the machine->accesses_prev_frame stuff that
1073 we currently need to ensure that there is a frame pointer when these
1074 builtin functions are used. */
1076 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
1078 /* A C expression whose value is RTL representing the address in a
1079 stack frame where the pointer to the caller's frame is stored.
1080 Assume that FRAMEADDR is an RTL expression for the address of the
1083 For Xtensa, there is no easy way to get the frame pointer if it is
1084 not equivalent to the stack pointer. Moreover, the result of this
1085 macro is used for continuing to walk back up the stack, so it must
1086 return the stack pointer address. Thus, there is some inconsistency
1087 here in that __builtin_frame_address will return the frame pointer
1088 when count == 0 and the stack pointer when count > 0. */
1090 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1091 gen_rtx (PLUS, Pmode, frame, \
1092 gen_rtx_CONST_INT (VOIDmode, -3 * UNITS_PER_WORD))
1094 /* Define this if the return address of a particular stack frame is
1095 accessed from the frame pointer of the previous stack frame. */
1096 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1098 /* A C expression whose value is RTL representing the value of the
1099 return address for the frame COUNT steps up from the current
1100 frame, after the prologue. */
1101 #define RETURN_ADDR_RTX xtensa_return_addr
1103 /* Addressing modes, and classification of registers for them. */
1105 /* C expressions which are nonzero if register number NUM is suitable
1106 for use as a base or index register in operand addresses. It may
1107 be either a suitable hard register or a pseudo register that has
1108 been allocated such a hard register. The difference between an
1109 index register and a base register is that the index register may
1112 #define REGNO_OK_FOR_BASE_P(NUM) \
1113 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
1115 #define REGNO_OK_FOR_INDEX_P(NUM) 0
1117 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
1118 valid for use as a base or index register. For hard registers, it
1119 should always accept those which the hardware permits and reject
1120 the others. Whether the macro accepts or rejects pseudo registers
1121 must be controlled by `REG_OK_STRICT'. This usually requires two
1122 variant definitions, of which `REG_OK_STRICT' controls the one
1123 actually used. The difference between an index register and a base
1124 register is that the index register may be scaled. */
1126 #ifdef REG_OK_STRICT
1128 #define REG_OK_FOR_INDEX_P(X) 0
1129 #define REG_OK_FOR_BASE_P(X) \
1130 REGNO_OK_FOR_BASE_P (REGNO (X))
1132 #else /* !REG_OK_STRICT */
1134 #define REG_OK_FOR_INDEX_P(X) 0
1135 #define REG_OK_FOR_BASE_P(X) \
1136 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X))))
1138 #endif /* !REG_OK_STRICT */
1140 /* Maximum number of registers that can appear in a valid memory address. */
1141 #define MAX_REGS_PER_ADDRESS 1
1143 /* Identify valid Xtensa addresses. */
1144 #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \
1146 rtx xinsn = (ADDR); \
1148 /* allow constant pool addresses */ \
1149 if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \
1150 && !TARGET_CONST16 && constantpool_address_p (xinsn)) \
1153 while (GET_CODE (xinsn) == SUBREG) \
1154 xinsn = SUBREG_REG (xinsn); \
1156 /* allow base registers */ \
1157 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
1160 /* check for "register + offset" addressing */ \
1161 if (GET_CODE (xinsn) == PLUS) \
1163 rtx xplus0 = XEXP (xinsn, 0); \
1164 rtx xplus1 = XEXP (xinsn, 1); \
1165 enum rtx_code code0; \
1166 enum rtx_code code1; \
1168 while (GET_CODE (xplus0) == SUBREG) \
1169 xplus0 = SUBREG_REG (xplus0); \
1170 code0 = GET_CODE (xplus0); \
1172 while (GET_CODE (xplus1) == SUBREG) \
1173 xplus1 = SUBREG_REG (xplus1); \
1174 code1 = GET_CODE (xplus1); \
1176 /* swap operands if necessary so the register is first */ \
1177 if (code0 != REG && code1 == REG) \
1179 xplus0 = XEXP (xinsn, 1); \
1180 xplus1 = XEXP (xinsn, 0); \
1181 code0 = GET_CODE (xplus0); \
1182 code1 = GET_CODE (xplus1); \
1185 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
1186 && code1 == CONST_INT \
1187 && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \
1194 /* A C expression that is 1 if the RTX X is a constant which is a
1195 valid address. This is defined to be the same as 'CONSTANT_P (X)',
1196 but rejecting CONST_DOUBLE. */
1197 #define CONSTANT_ADDRESS_P(X) \
1198 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1199 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1200 || (GET_CODE (X) == CONST)))
1202 /* Nonzero if the constant value X is a legitimate general operand.
1203 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1204 #define LEGITIMATE_CONSTANT_P(X) 1
1206 /* A C expression that is nonzero if X is a legitimate immediate
1207 operand on the target machine when generating position independent
1209 #define LEGITIMATE_PIC_OPERAND_P(X) \
1210 ((GET_CODE (X) != SYMBOL_REF || SYMBOL_REF_FLAG (X)) \
1211 && GET_CODE (X) != LABEL_REF \
1212 && GET_CODE (X) != CONST)
1214 /* Tell GCC how to use ADDMI to generate addresses. */
1215 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1218 if (GET_CODE (xinsn) == PLUS) \
1220 rtx plus0 = XEXP (xinsn, 0); \
1221 rtx plus1 = XEXP (xinsn, 1); \
1223 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \
1225 plus0 = XEXP (xinsn, 1); \
1226 plus1 = XEXP (xinsn, 0); \
1229 if (GET_CODE (plus0) == REG \
1230 && GET_CODE (plus1) == CONST_INT \
1231 && !xtensa_mem_offset (INTVAL (plus1), MODE) \
1232 && !xtensa_simm8 (INTVAL (plus1)) \
1233 && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \
1234 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \
1236 rtx temp = gen_reg_rtx (Pmode); \
1237 emit_insn (gen_rtx (SET, Pmode, temp, \
1238 gen_rtx (PLUS, Pmode, plus0, \
1239 GEN_INT (INTVAL (plus1) & ~0xff)))); \
1240 (X) = gen_rtx (PLUS, Pmode, temp, \
1241 GEN_INT (INTVAL (plus1) & 0xff)); \
1248 /* Treat constant-pool references as "mode dependent" since they can
1249 only be accessed with SImode loads. This works around a bug in the
1250 combiner where a constant pool reference is temporarily converted
1251 to an HImode load, which is then assumed to zero-extend based on
1252 our definition of LOAD_EXTEND_OP. This is wrong because the high
1253 bits of a 16-bit value in the constant pool are now sign-extended
1256 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1258 if (constantpool_address_p (ADDR)) \
1262 /* Specify the machine mode that this machine uses
1263 for the index in the tablejump instruction. */
1264 #define CASE_VECTOR_MODE (SImode)
1266 /* Define this if the tablejump instruction expects the table
1267 to contain offsets from the address of the table.
1268 Do not define this if the table should contain absolute addresses. */
1269 /* #define CASE_VECTOR_PC_RELATIVE */
1271 /* Define this as 1 if 'char' should by default be signed; else as 0. */
1272 #define DEFAULT_SIGNED_CHAR 0
1274 /* Max number of bytes we can move from memory to memory
1275 in one reasonably fast instruction. */
1277 #define MAX_MOVE_MAX 4
1279 /* Prefer word-sized loads. */
1280 #define SLOW_BYTE_ACCESS 1
1282 /* ??? Xtensa doesn't have any instructions that set integer values
1283 based on the results of comparisons, but the simplification code in
1284 the combiner also uses STORE_FLAG_VALUE. The default value (1) is
1285 fine for us, but (-1) might be better. */
1287 /* Shift instructions ignore all but the low-order few bits. */
1288 #define SHIFT_COUNT_TRUNCATED 1
1290 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1291 is done just by pretending it is already truncated. */
1292 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1294 /* Specify the machine mode that pointers have.
1295 After generation of rtl, the compiler makes no further distinction
1296 between pointers and any other objects of this machine mode. */
1297 #define Pmode SImode
1299 /* A function address in a call instruction is a word address (for
1300 indexing purposes) so give the MEM rtx a words's mode. */
1301 #define FUNCTION_MODE SImode
1303 /* A C expression for the cost of moving data from a register in
1304 class FROM to one in class TO. The classes are expressed using
1305 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
1306 the default; other values are interpreted relative to that. */
1307 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1308 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
1310 : (reg_class_subset_p ((FROM), AR_REGS) \
1311 && reg_class_subset_p ((TO), AR_REGS) \
1313 : (reg_class_subset_p ((FROM), AR_REGS) \
1314 && (TO) == ACC_REG \
1316 : ((FROM) == ACC_REG \
1317 && reg_class_subset_p ((TO), AR_REGS) \
1321 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
1323 #define BRANCH_COST 3
1325 /* Optionally define this if you have added predicates to
1326 'MACHINE.c'. This macro is called within an initializer of an
1327 array of structures. The first field in the structure is the
1328 name of a predicate and the second field is an array of rtl
1329 codes. For each predicate, list all rtl codes that can be in
1330 expressions matched by the predicate. The list should have a
1333 #define PREDICATE_CODES \
1334 {"add_operand", { REG, CONST_INT, SUBREG }}, \
1335 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
1336 {"nonimmed_operand", { REG, SUBREG, MEM }}, \
1337 {"mem_operand", { MEM }}, \
1338 {"mask_operand", { REG, CONST_INT, SUBREG }}, \
1339 {"extui_fldsz_operand", { CONST_INT }}, \
1340 {"sext_fldsz_operand", { CONST_INT }}, \
1341 {"lsbitnum_operand", { CONST_INT }}, \
1342 {"fpmem_offset_operand", { CONST_INT }}, \
1343 {"sext_operand", { REG, SUBREG, MEM }}, \
1344 {"branch_operand", { REG, CONST_INT, SUBREG }}, \
1345 {"ubranch_operand", { REG, CONST_INT, SUBREG }}, \
1346 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG }}, \
1347 {"move_operand", { REG, SUBREG, MEM, CONST_INT, CONST_DOUBLE, \
1348 CONST, SYMBOL_REF, LABEL_REF }}, \
1349 {"const_float_1_operand", { CONST_DOUBLE }}, \
1350 {"branch_operator", { EQ, NE, LT, GE }}, \
1351 {"ubranch_operator", { LTU, GEU }}, \
1352 {"boolean_operator", { EQ, NE }},
1354 /* Control the assembler format that we output. */
1356 /* How to refer to registers in assembler output.
1357 This sequence is indexed by compiler's hard-register-number (see above). */
1358 #define REGISTER_NAMES \
1360 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
1361 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
1362 "fp", "argp", "b0", \
1363 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1364 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
1368 /* If defined, a C initializer for an array of structures containing a
1369 name and a register number. This macro defines additional names
1370 for hard registers, thus allowing the 'asm' option in declarations
1371 to refer to registers using alternate names. */
1372 #define ADDITIONAL_REGISTER_NAMES \
1374 { "a1", 1 + GP_REG_FIRST } \
1377 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1378 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1380 /* Recognize machine-specific patterns that may appear within
1381 constants. Used for PIC-specific UNSPECs. */
1382 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
1384 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
1386 switch (XINT ((X), 1)) \
1389 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
1390 fputs ("@PLT", (STREAM)); \
1401 /* Globalizing directive for a label. */
1402 #define GLOBAL_ASM_OP "\t.global\t"
1404 /* Declare an uninitialized external linkage data object. */
1405 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1406 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1408 /* This is how to output an element of a case-vector that is absolute. */
1409 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1410 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
1411 LOCAL_LABEL_PREFIX, VALUE)
1413 /* This is how to output an element of a case-vector that is relative.
1414 This is used for pc-relative code. */
1415 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1417 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
1418 LOCAL_LABEL_PREFIX, (VALUE), \
1419 LOCAL_LABEL_PREFIX, (REL)); \
1422 /* This is how to output an assembler line that says to advance the
1423 location counter to a multiple of 2**LOG bytes. */
1424 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
1427 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
1430 /* Indicate that jump tables go in the text section. This is
1431 necessary when compiling PIC code. */
1432 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1435 /* Define the strings to put out for each section in the object file. */
1436 #define TEXT_SECTION_ASM_OP "\t.text"
1437 #define DATA_SECTION_ASM_OP "\t.data"
1438 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1441 /* Define output to appear before the constant pool. If the function
1442 has been assigned to a specific ELF section, or if it goes into a
1443 unique section, set the name of that section to be the literal
1445 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
1448 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
1449 fnsection = DECL_SECTION_NAME (FUNDECL); \
1450 if (fnsection != NULL_TREE) \
1452 const char *fnsectname = TREE_STRING_POINTER (fnsection); \
1453 fprintf (FILE, "\t.begin\tliteral_prefix %s\n", \
1454 strcmp (fnsectname, ".text") ? fnsectname : ""); \
1458 function_section (FUNDECL); \
1459 fprintf (FILE, "\t.literal_position\n"); \
1464 /* Define code to write out the ".end literal_prefix" directive for a
1465 function in a special section. This is appended to the standard ELF
1466 code for ASM_DECLARE_FUNCTION_SIZE. */
1467 #define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
1468 if (DECL_SECTION_NAME (DECL) != NULL_TREE) \
1469 fprintf (FILE, "\t.end\tliteral_prefix\n")
1471 /* A C statement (with or without semicolon) to output a constant in
1472 the constant pool, if it needs special treatment. */
1473 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1475 xtensa_output_literal (FILE, X, MODE, LABELNO); \
1479 /* How to start an assembler comment. */
1480 #define ASM_COMMENT_START "#"
1482 /* Exception handling TODO!! */
1483 #define DWARF_UNWIND_INFO 0
1485 /* Xtensa constant pool breaks the devices in crtstuff.c to control
1486 section in where code resides. We have to write it as asm code. Use
1487 a MOVI and let the assembler relax it -- for the .init and .fini
1488 sections, the assembler knows to put the literal in the right
1490 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1491 asm (SECTION_OP "\n\
1492 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
1494 TEXT_SECTION_ASM_OP);
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