1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Get Xtensa configuration settings */
23 #include "xtensa-config.h"
25 /* Standard GCC variables that we reference. */
26 extern int current_function_calls_alloca;
29 /* External variables defined in xtensa.c. */
33 CMP_SI, /* four byte integers */
34 CMP_DI, /* eight byte integers */
35 CMP_SF, /* single precision floats */
36 CMP_DF, /* double precision floats */
37 CMP_MAX /* max comparison type */
40 extern struct rtx_def * branch_cmp[2]; /* operands for compare */
41 extern enum cmp_type branch_type; /* what type of branch to use */
42 extern unsigned xtensa_current_frame_size;
44 /* Macros used in the machine description to select various Xtensa
45 configuration options. */
46 #ifndef XCHAL_HAVE_MUL32_HIGH
47 #define XCHAL_HAVE_MUL32_HIGH 0
49 #ifndef XCHAL_HAVE_RELEASE_SYNC
50 #define XCHAL_HAVE_RELEASE_SYNC 0
52 #ifndef XCHAL_HAVE_S32C1I
53 #define XCHAL_HAVE_S32C1I 0
55 #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE
56 #define TARGET_DENSITY XCHAL_HAVE_DENSITY
57 #define TARGET_MAC16 XCHAL_HAVE_MAC16
58 #define TARGET_MUL16 XCHAL_HAVE_MUL16
59 #define TARGET_MUL32 XCHAL_HAVE_MUL32
60 #define TARGET_MUL32_HIGH XCHAL_HAVE_MUL32_HIGH
61 #define TARGET_DIV32 XCHAL_HAVE_DIV32
62 #define TARGET_NSA XCHAL_HAVE_NSA
63 #define TARGET_MINMAX XCHAL_HAVE_MINMAX
64 #define TARGET_SEXT XCHAL_HAVE_SEXT
65 #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS
66 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP
67 #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV
68 #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP
69 #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT
70 #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT
71 #define TARGET_ABS XCHAL_HAVE_ABS
72 #define TARGET_ADDX XCHAL_HAVE_ADDX
73 #define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC
74 #define TARGET_S32C1I XCHAL_HAVE_S32C1I
76 #define TARGET_DEFAULT ( \
77 (XCHAL_HAVE_L32R ? 0 : MASK_CONST16))
79 #define OVERRIDE_OPTIONS override_options ()
81 /* Reordering blocks for Xtensa is not a good idea unless the compiler
82 understands the range of conditional branches. Currently all branch
83 relaxation for Xtensa is handled in the assembler, so GCC cannot do a
84 good job of reordering blocks. Do not enable reordering unless it is
85 explicitly requested. */
86 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
89 flag_reorder_blocks = 0; \
94 /* Target CPU builtins. */
95 #define TARGET_CPU_CPP_BUILTINS() \
97 builtin_assert ("cpu=xtensa"); \
98 builtin_assert ("machine=xtensa"); \
99 builtin_define ("__xtensa__"); \
100 builtin_define ("__XTENSA__"); \
101 builtin_define ("__XTENSA_WINDOWED_ABI__"); \
102 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
103 if (!TARGET_HARD_FLOAT) \
104 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
107 #define CPP_SPEC " %(subtarget_cpp_spec) "
109 #ifndef SUBTARGET_CPP_SPEC
110 #define SUBTARGET_CPP_SPEC ""
113 #define EXTRA_SPECS \
114 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
117 #define LIBGCC2_WORDS_BIG_ENDIAN 1
119 #define LIBGCC2_WORDS_BIG_ENDIAN 0
122 /* Show we can debug even without a frame pointer. */
123 #define CAN_DEBUG_WITHOUT_FP
126 /* Target machine storage layout */
128 /* Define this if most significant bit is lowest numbered
129 in instructions that operate on numbered bit-fields. */
130 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
132 /* Define this if most significant byte of a word is the lowest numbered. */
133 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
135 /* Define this if most significant word of a multiword number is the lowest. */
136 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
138 #define MAX_BITS_PER_WORD 32
140 /* Width of a word, in units (bytes). */
141 #define UNITS_PER_WORD 4
142 #define MIN_UNITS_PER_WORD 4
144 /* Width of a floating point register. */
145 #define UNITS_PER_FPREG 4
147 /* Size in bits of various types on the target machine. */
148 #define INT_TYPE_SIZE 32
149 #define SHORT_TYPE_SIZE 16
150 #define LONG_TYPE_SIZE 32
151 #define LONG_LONG_TYPE_SIZE 64
152 #define FLOAT_TYPE_SIZE 32
153 #define DOUBLE_TYPE_SIZE 64
154 #define LONG_DOUBLE_TYPE_SIZE 64
156 /* Allocation boundary (in *bits*) for storing pointers in memory. */
157 #define POINTER_BOUNDARY 32
159 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
160 #define PARM_BOUNDARY 32
162 /* Allocation boundary (in *bits*) for the code of a function. */
163 #define FUNCTION_BOUNDARY 32
165 /* Alignment of field after 'int : 0' in a structure. */
166 #define EMPTY_FIELD_BOUNDARY 32
168 /* Every structure's size must be a multiple of this. */
169 #define STRUCTURE_SIZE_BOUNDARY 8
171 /* There is no point aligning anything to a rounder boundary than this. */
172 #define BIGGEST_ALIGNMENT 128
174 /* Set this nonzero if move instructions will actually fail to work
175 when given unaligned data. */
176 #define STRICT_ALIGNMENT 1
178 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
179 for QImode, because there is no 8-bit load from memory with sign
180 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
181 loads both with and without sign extension. */
182 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
184 if (GET_MODE_CLASS (MODE) == MODE_INT \
185 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
187 if ((MODE) == QImode) \
193 /* Imitate the way many other C compilers handle alignment of
194 bitfields and the structures that contain them. */
195 #define PCC_BITFIELD_TYPE_MATTERS 1
197 /* Disable the use of word-sized or smaller complex modes for structures,
198 and for function arguments in particular, where they cause problems with
199 register a7. The xtensa_copy_incoming_a7 function assumes that there is
200 a single reference to an argument in a7, but with small complex modes the
201 real and imaginary components may be extracted separately, leading to two
202 uses of the register, only one of which would be replaced. */
203 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
204 ((MODE) == CQImode || (MODE) == CHImode)
206 /* Align string constants and constructors to at least a word boundary.
207 The typical use of this macro is to increase alignment for string
208 constants to be word aligned so that 'strcpy' calls that copy
209 constants can be done inline. */
210 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
211 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
212 && (ALIGN) < BITS_PER_WORD \
216 /* Align arrays, unions and records to at least a word boundary.
217 One use of this macro is to increase alignment of medium-size
218 data to make it all fit in fewer cache lines. Another is to
219 cause character arrays to be word-aligned so that 'strcpy' calls
220 that copy constants to character arrays can be done inline. */
221 #undef DATA_ALIGNMENT
222 #define DATA_ALIGNMENT(TYPE, ALIGN) \
223 ((((ALIGN) < BITS_PER_WORD) \
224 && (TREE_CODE (TYPE) == ARRAY_TYPE \
225 || TREE_CODE (TYPE) == UNION_TYPE \
226 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
228 /* Operations between registers always perform the operation
229 on the full register even if a narrower mode is specified. */
230 #define WORD_REGISTER_OPERATIONS
232 /* Xtensa loads are zero-extended by default. */
233 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
235 /* Standard register usage. */
237 /* Number of actual hardware registers.
238 The hardware registers are assigned numbers for the compiler
239 from 0 to just below FIRST_PSEUDO_REGISTER.
240 All registers that the compiler knows about must be given numbers,
241 even those that are not normally considered general registers.
243 The fake frame pointer and argument pointer will never appear in
244 the generated code, since they will always be eliminated and replaced
245 by either the stack pointer or the hard frame pointer.
247 0 - 15 AR[0] - AR[15]
248 16 FRAME_POINTER (fake = initial sp)
249 17 ARG_POINTER (fake = initial sp + framesize)
250 18 BR[0] for floating-point CC
251 19 - 34 FR[0] - FR[15]
252 35 MAC16 accumulator */
254 #define FIRST_PSEUDO_REGISTER 36
256 /* Return the stabs register number to use for REGNO. */
257 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
259 /* 1 for registers that have pervasive standard uses
260 and are not available for the register allocator. */
261 #define FIXED_REGISTERS \
263 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
265 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
269 /* 1 for registers not available across function calls.
270 These must include the FIXED_REGISTERS and also any
271 registers that can be used without being saved.
272 The latter must include the registers where values are returned
273 and the register where structure-value addresses are passed.
274 Aside from that, you can include as many other registers as you like. */
275 #define CALL_USED_REGISTERS \
277 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
279 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
283 /* For non-leaf procedures on Xtensa processors, the allocation order
284 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
285 want to use the lowest numbered registers first to minimize
286 register window overflows. However, local-alloc is not smart
287 enough to consider conflicts with incoming arguments. If an
288 incoming argument in a2 is live throughout the function and
289 local-alloc decides to use a2, then the incoming argument must
290 either be spilled or copied to another register. To get around
291 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
292 reg_alloc_order for leaf functions such that lowest numbered
293 registers are used first with the exception that the incoming
294 argument registers are not used until after other register choices
295 have been exhausted. */
297 #define REG_ALLOC_ORDER \
298 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
300 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
305 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
307 /* For Xtensa, the only point of this is to prevent GCC from otherwise
308 giving preference to call-used registers. To minimize window
309 overflows for the AR registers, we want to give preference to the
310 lower-numbered AR registers. For other register files, which are
311 not windowed, we still prefer call-used registers, if there are any. */
312 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
313 #define LEAF_REGISTERS xtensa_leaf_regs
315 /* For Xtensa, no remapping is necessary, but this macro must be
316 defined if LEAF_REGISTERS is defined. */
317 #define LEAF_REG_REMAP(REGNO) (REGNO)
319 /* This must be declared if LEAF_REGISTERS is set. */
320 extern int leaf_function;
322 /* Internal macros to classify a register number. */
324 /* 16 address registers + fake registers */
325 #define GP_REG_FIRST 0
326 #define GP_REG_LAST 17
327 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
329 /* Coprocessor registers */
330 #define BR_REG_FIRST 18
331 #define BR_REG_LAST 18
332 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
334 /* 16 floating-point registers */
335 #define FP_REG_FIRST 19
336 #define FP_REG_LAST 34
337 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
339 /* MAC16 accumulator */
340 #define ACC_REG_FIRST 35
341 #define ACC_REG_LAST 35
342 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
344 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
345 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
346 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
347 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
349 /* Return number of consecutive hard regs needed starting at reg REGNO
350 to hold something of mode MODE. */
351 #define HARD_REGNO_NREGS(REGNO, MODE) \
352 (FP_REG_P (REGNO) ? \
353 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
354 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
356 /* Value is 1 if hard register REGNO can hold a value of machine-mode
358 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
360 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
361 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
363 /* Value is 1 if it is a good idea to tie two pseudo registers
364 when one has mode MODE1 and one has mode MODE2.
365 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
366 for any hard reg, then this must be 0 for correct output. */
367 #define MODES_TIEABLE_P(MODE1, MODE2) \
368 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
369 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
370 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
371 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
373 /* Register to use for pushing function arguments. */
374 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
376 /* Base register for access to local variables of the function. */
377 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
379 /* The register number of the frame pointer register, which is used to
380 access automatic variables in the stack frame. For Xtensa, this
381 register never appears in the output. It is always eliminated to
382 either the stack pointer or the hard frame pointer. */
383 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
385 /* Value should be nonzero if functions must have frame pointers.
386 Zero means the frame pointer need not be set up (and parms
387 may be accessed via the stack pointer) in functions that seem suitable.
388 This is computed in 'reload', in reload1.c. */
389 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
391 /* Base register for access to arguments of the function. */
392 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
394 /* If the static chain is passed in memory, these macros provide rtx
395 giving 'mem' expressions that denote where they are stored.
396 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
397 seen by the calling and called functions, respectively. */
399 #define STATIC_CHAIN \
400 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
402 #define STATIC_CHAIN_INCOMING \
403 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
405 /* For now we don't try to use the full set of boolean registers. Without
406 software pipelining of FP operations, there's not much to gain and it's
407 a real pain to get them reloaded. */
408 #define FPCC_REGNUM (BR_REG_FIRST + 0)
410 /* It is as good or better to call a constant function address than to
411 call an address kept in a register. */
412 #define NO_FUNCTION_CSE 1
414 /* Xtensa processors have "register windows". GCC does not currently
415 take advantage of the possibility for variable-sized windows; instead,
416 we use a fixed window size of 8. */
418 #define INCOMING_REGNO(OUT) \
419 ((GP_REG_P (OUT) && \
420 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
421 (OUT) - WINDOW_SIZE : (OUT))
423 #define OUTGOING_REGNO(IN) \
425 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
426 (IN) + WINDOW_SIZE : (IN))
429 /* Define the classes of registers for register constraints in the
430 machine description. */
433 NO_REGS, /* no registers in set */
434 BR_REGS, /* coprocessor boolean registers */
435 FP_REGS, /* floating point registers */
436 ACC_REG, /* MAC16 accumulator */
437 SP_REG, /* sp register (aka a1) */
438 RL_REGS, /* preferred reload regs (not sp or fp) */
439 GR_REGS, /* integer registers except sp */
440 AR_REGS, /* all integer registers */
441 ALL_REGS, /* all registers */
442 LIM_REG_CLASSES /* max value + 1 */
445 #define N_REG_CLASSES (int) LIM_REG_CLASSES
447 #define GENERAL_REGS AR_REGS
449 /* An initializer containing the names of the register classes as C
450 string constants. These names are used in writing some of the
452 #define REG_CLASS_NAMES \
465 /* Contents of the register classes. The Nth integer specifies the
466 contents of class N. The way the integer MASK is interpreted is
467 that register R is in the class if 'MASK & (1 << R)' is 1. */
468 #define REG_CLASS_CONTENTS \
470 { 0x00000000, 0x00000000 }, /* no registers */ \
471 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
472 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
473 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
474 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
475 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
476 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
477 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
478 { 0xffffffff, 0x0000000f } /* all registers */ \
481 /* A C expression whose value is a register class containing hard
482 register REGNO. In general there is more that one such class;
483 choose a class which is "minimal", meaning that no smaller class
484 also contains the register. */
485 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
487 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
489 /* Use the Xtensa AR register file for base registers.
490 No index registers. */
491 #define BASE_REG_CLASS AR_REGS
492 #define INDEX_REG_CLASS NO_REGS
494 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
495 16 AR registers may be explicitly used in the RTL, as either
496 incoming or outgoing arguments. */
497 #define SMALL_REGISTER_CLASSES 1
499 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
500 xtensa_preferred_reload_class (X, CLASS, 0)
502 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
503 xtensa_preferred_reload_class (X, CLASS, 1)
505 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
506 xtensa_secondary_reload_class (CLASS, MODE, X, 0)
508 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
509 xtensa_secondary_reload_class (CLASS, MODE, X, 1)
511 /* Return the maximum number of consecutive registers
512 needed to represent mode MODE in a register of class CLASS. */
513 #define CLASS_UNITS(mode, size) \
514 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
516 #define CLASS_MAX_NREGS(CLASS, MODE) \
517 (CLASS_UNITS (MODE, UNITS_PER_WORD))
520 /* Stack layout; function entry, exit and calling. */
522 #define STACK_GROWS_DOWNWARD
524 /* Offset within stack frame to start allocating local variables at. */
525 #define STARTING_FRAME_OFFSET \
526 current_function_outgoing_args_size
528 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
529 they are eliminated to either the stack pointer or hard frame pointer. */
530 #define ELIMINABLE_REGS \
531 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
532 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
533 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
534 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
536 #define CAN_ELIMINATE(FROM, TO) 1
538 /* Specify the initial difference between the specified pair of registers. */
539 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
541 compute_frame_size (get_frame_size ()); \
544 case FRAME_POINTER_REGNUM: \
547 case ARG_POINTER_REGNUM: \
548 (OFFSET) = xtensa_current_frame_size; \
551 gcc_unreachable (); \
555 /* If defined, the maximum amount of space required for outgoing
556 arguments will be computed and placed into the variable
557 'current_function_outgoing_args_size'. No space will be pushed
558 onto the stack for each call; instead, the function prologue
559 should increase the stack frame size by this amount. */
560 #define ACCUMULATE_OUTGOING_ARGS 1
562 /* Offset from the argument pointer register to the first argument's
563 address. On some machines it may depend on the data type of the
564 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
565 location above the first argument's address. */
566 #define FIRST_PARM_OFFSET(FNDECL) 0
568 /* Align stack frames on 128 bits for Xtensa. This is necessary for
569 128-bit datatypes defined in TIE (e.g., for Vectra). */
570 #define STACK_BOUNDARY 128
572 /* Functions do not pop arguments off the stack. */
573 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
575 /* Use a fixed register window size of 8. */
576 #define WINDOW_SIZE 8
578 /* Symbolic macros for the registers used to return integer, floating
579 point, and values of coprocessor and user-defined modes. */
580 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
581 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
583 /* Symbolic macros for the first/last argument registers. */
584 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
585 #define GP_ARG_LAST (GP_REG_FIRST + 7)
586 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
587 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
589 #define MAX_ARGS_IN_REGISTERS 6
591 /* Don't worry about compatibility with PCC. */
592 #define DEFAULT_PCC_STRUCT_RETURN 0
594 /* Define how to find the value returned by a library function
595 assuming the value has mode MODE. Because we have defined
596 TARGET_PROMOTE_FUNCTION_RETURN that returns true, we have to
597 perform the same promotions as PROMOTE_MODE. */
598 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
599 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
600 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
602 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
604 #define LIBCALL_VALUE(MODE) \
605 XTENSA_LIBCALL_VALUE ((MODE), 0)
607 #define LIBCALL_OUTGOING_VALUE(MODE) \
608 XTENSA_LIBCALL_VALUE ((MODE), 1)
610 /* Define how to find the value returned by a function.
611 VALTYPE is the data type of the value (as a tree).
612 If the precise function being called is known, FUNC is its FUNCTION_DECL;
613 otherwise, FUNC is 0. */
614 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \
615 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
616 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
617 ? SImode: TYPE_MODE (VALTYPE), \
618 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
620 #define FUNCTION_VALUE(VALTYPE, FUNC) \
621 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
623 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
624 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
626 /* A C expression that is nonzero if REGNO is the number of a hard
627 register in which the values of called function may come back. A
628 register whose use for returning values is limited to serving as
629 the second of a pair (for a value of type 'double', say) need not
630 be recognized by this macro. If the machine has register windows,
631 so that the caller and the called function use different registers
632 for the return value, this macro should recognize only the caller's
634 #define FUNCTION_VALUE_REGNO_P(N) \
637 /* A C expression that is nonzero if REGNO is the number of a hard
638 register in which function arguments are sometimes passed. This
639 does *not* include implicit arguments such as the static chain and
640 the structure-value address. On many machines, no registers can be
641 used for this purpose since all function arguments are pushed on
643 #define FUNCTION_ARG_REGNO_P(N) \
644 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
646 /* Record the number of argument words seen so far, along with a flag to
647 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG
648 is used for both incoming and outgoing args, so a separate flag is
650 typedef struct xtensa_args
656 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
657 init_cumulative_args (&CUM, 0)
659 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
660 init_cumulative_args (&CUM, 1)
662 /* Update the data in CUM to advance over an argument
663 of mode MODE and data type TYPE.
664 (TYPE is null for libcalls where that information may not be available.) */
665 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
666 function_arg_advance (&CUM, MODE, TYPE)
668 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
669 function_arg (&CUM, MODE, TYPE, FALSE)
671 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
672 function_arg (&CUM, MODE, TYPE, TRUE)
674 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
676 /* Profiling Xtensa code is typically done with the built-in profiling
677 feature of Tensilica's instruction set simulator, which does not
678 require any compiler support. Profiling code on a real (i.e.,
679 non-simulated) Xtensa processor is currently only supported by
680 GNU/Linux with glibc. The glibc version of _mcount doesn't require
681 counter variables. The _mcount function needs the current PC and
682 the current return address to identify an arc in the call graph.
683 Pass the current return address as the first argument; the current
684 PC is available as a0 in _mcount's register window. Both of these
685 values contain window size information in the two most significant
686 bits; we assume that _mcount will mask off those bits. The call to
687 _mcount uses a window size of 8 to make sure that it doesn't clobber
688 any incoming argument values. */
690 #define NO_PROFILE_COUNTERS 1
692 #define FUNCTION_PROFILER(FILE, LABELNO) \
694 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
697 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \
698 fprintf (FILE, "\tcallx8\ta8\n"); \
701 fprintf (FILE, "\tcall8\t_mcount\n"); \
704 /* Stack pointer value doesn't matter at exit. */
705 #define EXIT_IGNORE_STACK 1
707 /* A C statement to output, on the stream FILE, assembler code for a
708 block of data that contains the constant parts of a trampoline.
709 This code should not include a label--the label is taken care of
712 For Xtensa, the trampoline must perform an entry instruction with a
713 minimal stack frame in order to get some free registers. Once the
714 actual call target is known, the proper stack frame size is extracted
715 from the entry instruction at the target and the current frame is
716 adjusted to match. The trampoline then transfers control to the
717 instruction following the entry at the target. Note: this assumes
718 that the target begins with an entry instruction. */
720 /* minimum frame = reg save area (4 words) plus static chain (1 word)
721 and the total number of words must be a multiple of 128 bits */
722 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
724 #define TRAMPOLINE_TEMPLATE(STREAM) \
726 fprintf (STREAM, "\t.begin no-transform\n"); \
727 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \
729 /* save the return address */ \
730 fprintf (STREAM, "\tmov\ta10, a0\n"); \
732 /* Use a CALL0 instruction to skip past the constants and in the \
733 process get the PC into A0. This allows PC-relative access to \
734 the constants without relying on L32R, which may not always be \
737 fprintf (STREAM, "\tcall0\t.Lskipconsts\n"); \
738 fprintf (STREAM, "\t.align\t4\n"); \
739 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \
740 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \
741 fprintf (STREAM, ".Lskipconsts:\n"); \
743 /* store the static chain */ \
744 fprintf (STREAM, "\taddi\ta0, a0, 3\n"); \
745 fprintf (STREAM, "\tl32i\ta8, a0, 0\n"); \
746 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", MIN_FRAME_SIZE - 20); \
748 /* set the proper stack pointer value */ \
749 fprintf (STREAM, "\tl32i\ta8, a0, 4\n"); \
750 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \
751 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \
752 TARGET_BIG_ENDIAN ? 8 : 12); \
753 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \
754 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \
755 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \
756 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \
758 /* restore the return address */ \
759 fprintf (STREAM, "\tmov\ta0, a10\n"); \
761 /* jump to the instruction following the entry */ \
762 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \
763 fprintf (STREAM, "\tjx\ta8\n"); \
764 fprintf (STREAM, "\t.byte\t0\n"); \
765 fprintf (STREAM, "\t.end no-transform\n"); \
768 /* Size in bytes of the trampoline, as an integer. Make sure this is
769 a multiple of TRAMPOLINE_ALIGNMENT to avoid -Wpadded warnings. */
770 #define TRAMPOLINE_SIZE 60
772 /* Alignment required for trampolines, in bits. */
773 #define TRAMPOLINE_ALIGNMENT (32)
775 /* A C statement to initialize the variable parts of a trampoline. */
776 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
779 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
780 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 16)), FUNC); \
781 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"), \
782 0, VOIDmode, 1, addr, Pmode); \
785 /* Implement `va_start' for varargs and stdarg. */
786 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
787 xtensa_va_start (valist, nextarg)
789 /* If defined, a C expression that produces the machine-specific code
790 to setup the stack so that arbitrary frames can be accessed.
792 On Xtensa, a stack back-trace must always begin from the stack pointer,
793 so that the register overflow save area can be located. However, the
794 stack-walking code in GCC always begins from the hard_frame_pointer
795 register, not the stack pointer. The frame pointer is usually equal
796 to the stack pointer, but the __builtin_return_address and
797 __builtin_frame_address functions will not work if count > 0 and
798 they are called from a routine that uses alloca. These functions
799 are not guaranteed to work at all if count > 0 so maybe that is OK.
801 A nicer solution would be to allow the architecture-specific files to
802 specify whether to start from the stack pointer or frame pointer. That
803 would also allow us to skip the machine->accesses_prev_frame stuff that
804 we currently need to ensure that there is a frame pointer when these
805 builtin functions are used. */
807 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
809 /* A C expression whose value is RTL representing the address in a
810 stack frame where the pointer to the caller's frame is stored.
811 Assume that FRAMEADDR is an RTL expression for the address of the
814 For Xtensa, there is no easy way to get the frame pointer if it is
815 not equivalent to the stack pointer. Moreover, the result of this
816 macro is used for continuing to walk back up the stack, so it must
817 return the stack pointer address. Thus, there is some inconsistency
818 here in that __builtin_frame_address will return the frame pointer
819 when count == 0 and the stack pointer when count > 0. */
821 #define DYNAMIC_CHAIN_ADDRESS(frame) \
822 gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD))
824 /* Define this if the return address of a particular stack frame is
825 accessed from the frame pointer of the previous stack frame. */
826 #define RETURN_ADDR_IN_PREVIOUS_FRAME
828 /* A C expression whose value is RTL representing the value of the
829 return address for the frame COUNT steps up from the current
830 frame, after the prologue. */
831 #define RETURN_ADDR_RTX xtensa_return_addr
833 /* Addressing modes, and classification of registers for them. */
835 /* C expressions which are nonzero if register number NUM is suitable
836 for use as a base or index register in operand addresses. */
838 #define REGNO_OK_FOR_INDEX_P(NUM) 0
839 #define REGNO_OK_FOR_BASE_P(NUM) \
840 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
842 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
843 valid for use as a base or index register. */
846 #define REG_OK_STRICT_FLAG 1
848 #define REG_OK_STRICT_FLAG 0
851 #define BASE_REG_P(X, STRICT) \
852 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
853 || REGNO_OK_FOR_BASE_P (REGNO (X)))
855 #define REG_OK_FOR_INDEX_P(X) 0
856 #define REG_OK_FOR_BASE_P(X) BASE_REG_P (X, REG_OK_STRICT_FLAG)
858 /* Maximum number of registers that can appear in a valid memory address. */
859 #define MAX_REGS_PER_ADDRESS 1
861 /* Identify valid Xtensa addresses. */
862 #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \
864 if (xtensa_legitimate_address_p (MODE, ADDR, REG_OK_STRICT_FLAG)) \
868 /* A C expression that is 1 if the RTX X is a constant which is a
869 valid address. This is defined to be the same as 'CONSTANT_P (X)',
870 but rejecting CONST_DOUBLE. */
871 #define CONSTANT_ADDRESS_P(X) \
872 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
873 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
874 || (GET_CODE (X) == CONST)))
876 /* Nonzero if the constant value X is a legitimate general operand.
877 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
878 #define LEGITIMATE_CONSTANT_P(X) 1
880 /* A C expression that is nonzero if X is a legitimate immediate
881 operand on the target machine when generating position independent
883 #define LEGITIMATE_PIC_OPERAND_P(X) \
884 ((GET_CODE (X) != SYMBOL_REF \
885 || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \
886 && GET_CODE (X) != LABEL_REF \
887 && GET_CODE (X) != CONST)
889 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
891 rtx new_x = xtensa_legitimize_address (X, OLDX, MODE); \
900 /* Treat constant-pool references as "mode dependent" since they can
901 only be accessed with SImode loads. This works around a bug in the
902 combiner where a constant pool reference is temporarily converted
903 to an HImode load, which is then assumed to zero-extend based on
904 our definition of LOAD_EXTEND_OP. This is wrong because the high
905 bits of a 16-bit value in the constant pool are now sign-extended
908 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
910 if (constantpool_address_p (ADDR)) \
914 /* Specify the machine mode that this machine uses
915 for the index in the tablejump instruction. */
916 #define CASE_VECTOR_MODE (SImode)
918 /* Define this as 1 if 'char' should by default be signed; else as 0. */
919 #define DEFAULT_SIGNED_CHAR 0
921 /* Max number of bytes we can move from memory to memory
922 in one reasonably fast instruction. */
924 #define MAX_MOVE_MAX 4
926 /* Prefer word-sized loads. */
927 #define SLOW_BYTE_ACCESS 1
929 /* Shift instructions ignore all but the low-order few bits. */
930 #define SHIFT_COUNT_TRUNCATED 1
932 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
933 is done just by pretending it is already truncated. */
934 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
936 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
937 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
939 /* Specify the machine mode that pointers have.
940 After generation of rtl, the compiler makes no further distinction
941 between pointers and any other objects of this machine mode. */
944 /* A function address in a call instruction is a word address (for
945 indexing purposes) so give the MEM rtx a words's mode. */
946 #define FUNCTION_MODE SImode
948 /* A C expression for the cost of moving data from a register in
949 class FROM to one in class TO. The classes are expressed using
950 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
951 the default; other values are interpreted relative to that. */
952 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
953 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
955 : (reg_class_subset_p ((FROM), AR_REGS) \
956 && reg_class_subset_p ((TO), AR_REGS) \
958 : (reg_class_subset_p ((FROM), AR_REGS) \
961 : ((FROM) == ACC_REG \
962 && reg_class_subset_p ((TO), AR_REGS) \
966 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
968 #define BRANCH_COST 3
970 /* How to refer to registers in assembler output.
971 This sequence is indexed by compiler's hard-register-number (see above). */
972 #define REGISTER_NAMES \
974 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
975 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
976 "fp", "argp", "b0", \
977 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
978 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
982 /* If defined, a C initializer for an array of structures containing a
983 name and a register number. This macro defines additional names
984 for hard registers, thus allowing the 'asm' option in declarations
985 to refer to registers using alternate names. */
986 #define ADDITIONAL_REGISTER_NAMES \
988 { "a1", 1 + GP_REG_FIRST } \
991 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
992 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
994 /* Recognize machine-specific patterns that may appear within
995 constants. Used for PIC-specific UNSPECs. */
996 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
998 if (xtensa_output_addr_const_extra (STREAM, X) == FALSE) \
1002 /* Globalizing directive for a label. */
1003 #define GLOBAL_ASM_OP "\t.global\t"
1005 /* Declare an uninitialized external linkage data object. */
1006 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1007 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1009 /* This is how to output an element of a case-vector that is absolute. */
1010 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1011 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
1012 LOCAL_LABEL_PREFIX, VALUE)
1014 /* This is how to output an element of a case-vector that is relative.
1015 This is used for pc-relative code. */
1016 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1018 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
1019 LOCAL_LABEL_PREFIX, (VALUE), \
1020 LOCAL_LABEL_PREFIX, (REL)); \
1023 /* This is how to output an assembler line that says to advance the
1024 location counter to a multiple of 2**LOG bytes. */
1025 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
1028 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
1031 /* Indicate that jump tables go in the text section. This is
1032 necessary when compiling PIC code. */
1033 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1036 /* Define the strings to put out for each section in the object file. */
1037 #define TEXT_SECTION_ASM_OP "\t.text"
1038 #define DATA_SECTION_ASM_OP "\t.data"
1039 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1042 /* Define output to appear before the constant pool. */
1043 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
1047 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
1048 switch_to_section (function_section (FUNDECL)); \
1049 fprintf (FILE, "\t.literal_position\n"); \
1054 /* A C statement (with or without semicolon) to output a constant in
1055 the constant pool, if it needs special treatment. */
1056 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1058 xtensa_output_literal (FILE, X, MODE, LABELNO); \
1062 /* How to start an assembler comment. */
1063 #define ASM_COMMENT_START "#"
1065 /* Generate DWARF2 unwind info to get the DW_AT_frame_base set correctly,
1066 even though we don't yet use it for unwinding. */
1067 #define MUST_USE_SJLJ_EXCEPTIONS 1
1068 #define DWARF2_UNWIND_INFO 1
1069 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 0)
1070 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (0)
1072 /* Xtensa constant pool breaks the devices in crtstuff.c to control
1073 section in where code resides. We have to write it as asm code. Use
1074 a MOVI and let the assembler relax it -- for the .init and .fini
1075 sections, the assembler knows to put the literal in the right
1077 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1078 asm (SECTION_OP "\n\
1079 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
1081 TEXT_SECTION_ASM_OP);