1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Get Xtensa configuration settings */
23 #include "xtensa-config.h"
25 /* Standard GCC variables that we reference. */
26 extern int current_function_calls_alloca;
27 extern int target_flags;
30 /* External variables defined in xtensa.c. */
34 CMP_SI, /* four byte integers */
35 CMP_DI, /* eight byte integers */
36 CMP_SF, /* single precision floats */
37 CMP_DF, /* double precision floats */
38 CMP_MAX /* max comparison type */
41 extern struct rtx_def * branch_cmp[2]; /* operands for compare */
42 extern enum cmp_type branch_type; /* what type of branch to use */
43 extern unsigned xtensa_current_frame_size;
45 /* Masks for the -m switches */
46 #define MASK_NO_FUSED_MADD 0x00000001 /* avoid f-p mul/add */
47 #define MASK_CONST16 0x00000002 /* use CONST16 instruction */
49 /* Macros used in the machine description to select various Xtensa
50 configuration options. */
51 #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE
52 #define TARGET_DENSITY XCHAL_HAVE_DENSITY
53 #define TARGET_MAC16 XCHAL_HAVE_MAC16
54 #define TARGET_MUL16 XCHAL_HAVE_MUL16
55 #define TARGET_MUL32 XCHAL_HAVE_MUL32
56 #define TARGET_DIV32 XCHAL_HAVE_DIV32
57 #define TARGET_NSA XCHAL_HAVE_NSA
58 #define TARGET_MINMAX XCHAL_HAVE_MINMAX
59 #define TARGET_SEXT XCHAL_HAVE_SEXT
60 #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS
61 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP
62 #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV
63 #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP
64 #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT
65 #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT
66 #define TARGET_ABS XCHAL_HAVE_ABS
67 #define TARGET_ADDX XCHAL_HAVE_ADDX
69 /* Macros controlled by command-line options. */
70 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
71 #define TARGET_CONST16 (target_flags & MASK_CONST16)
73 #define TARGET_DEFAULT ( \
74 (XCHAL_HAVE_L32R ? 0 : MASK_CONST16))
76 #define TARGET_SWITCHES \
78 {"const16", MASK_CONST16, \
79 N_("Use CONST16 instruction to load constants")}, \
80 {"no-const16", -MASK_CONST16, \
81 N_("Use PC-relative L32R instruction to load constants")}, \
82 {"no-fused-madd", MASK_NO_FUSED_MADD, \
83 N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \
84 {"fused-madd", -MASK_NO_FUSED_MADD, \
85 N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \
86 {"text-section-literals", 0, \
87 N_("Intersperse literal pools with code in the text section")}, \
88 {"no-text-section-literals", 0, \
89 N_("Put literal pools in a separate literal section")}, \
91 N_("Automatically align branch targets to reduce branch penalties")}, \
92 {"no-target-align", 0, \
93 N_("Do not automatically align branch targets")}, \
95 N_("Use indirect CALLXn instructions for large programs")}, \
97 N_("Use direct CALLn instructions for fast calls")}, \
98 {"", TARGET_DEFAULT, 0} \
102 #define OVERRIDE_OPTIONS override_options ()
104 /* Target CPU builtins. */
105 #define TARGET_CPU_CPP_BUILTINS() \
107 builtin_assert ("cpu=xtensa"); \
108 builtin_assert ("machine=xtensa"); \
109 builtin_define ("__xtensa__"); \
110 builtin_define ("__XTENSA__"); \
111 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
112 if (!TARGET_HARD_FLOAT) \
113 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
116 builtin_define ("__PIC__"); \
117 builtin_define ("__pic__"); \
121 #define CPP_SPEC " %(subtarget_cpp_spec) "
123 #ifndef SUBTARGET_CPP_SPEC
124 #define SUBTARGET_CPP_SPEC ""
127 #define EXTRA_SPECS \
128 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
131 #define LIBGCC2_WORDS_BIG_ENDIAN 1
133 #define LIBGCC2_WORDS_BIG_ENDIAN 0
136 /* Show we can debug even without a frame pointer. */
137 #define CAN_DEBUG_WITHOUT_FP
140 /* Target machine storage layout */
142 /* Define this if most significant bit is lowest numbered
143 in instructions that operate on numbered bit-fields. */
144 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
146 /* Define this if most significant byte of a word is the lowest numbered. */
147 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
149 /* Define this if most significant word of a multiword number is the lowest. */
150 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
152 #define MAX_BITS_PER_WORD 32
154 /* Width of a word, in units (bytes). */
155 #define UNITS_PER_WORD 4
156 #define MIN_UNITS_PER_WORD 4
158 /* Width of a floating point register. */
159 #define UNITS_PER_FPREG 4
161 /* Size in bits of various types on the target machine. */
162 #define INT_TYPE_SIZE 32
163 #define SHORT_TYPE_SIZE 16
164 #define LONG_TYPE_SIZE 32
165 #define LONG_LONG_TYPE_SIZE 64
166 #define FLOAT_TYPE_SIZE 32
167 #define DOUBLE_TYPE_SIZE 64
168 #define LONG_DOUBLE_TYPE_SIZE 64
170 /* Allocation boundary (in *bits*) for storing pointers in memory. */
171 #define POINTER_BOUNDARY 32
173 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
174 #define PARM_BOUNDARY 32
176 /* Allocation boundary (in *bits*) for the code of a function. */
177 #define FUNCTION_BOUNDARY 32
179 /* Alignment of field after 'int : 0' in a structure. */
180 #define EMPTY_FIELD_BOUNDARY 32
182 /* Every structure's size must be a multiple of this. */
183 #define STRUCTURE_SIZE_BOUNDARY 8
185 /* There is no point aligning anything to a rounder boundary than this. */
186 #define BIGGEST_ALIGNMENT 128
188 /* Set this nonzero if move instructions will actually fail to work
189 when given unaligned data. */
190 #define STRICT_ALIGNMENT 1
192 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
193 for QImode, because there is no 8-bit load from memory with sign
194 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
195 loads both with and without sign extension. */
196 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
198 if (GET_MODE_CLASS (MODE) == MODE_INT \
199 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
201 if ((MODE) == QImode) \
207 /* Imitate the way many other C compilers handle alignment of
208 bitfields and the structures that contain them. */
209 #define PCC_BITFIELD_TYPE_MATTERS 1
211 /* Align string constants and constructors to at least a word boundary.
212 The typical use of this macro is to increase alignment for string
213 constants to be word aligned so that 'strcpy' calls that copy
214 constants can be done inline. */
215 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
216 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
217 && (ALIGN) < BITS_PER_WORD \
221 /* Align arrays, unions and records to at least a word boundary.
222 One use of this macro is to increase alignment of medium-size
223 data to make it all fit in fewer cache lines. Another is to
224 cause character arrays to be word-aligned so that 'strcpy' calls
225 that copy constants to character arrays can be done inline. */
226 #undef DATA_ALIGNMENT
227 #define DATA_ALIGNMENT(TYPE, ALIGN) \
228 ((((ALIGN) < BITS_PER_WORD) \
229 && (TREE_CODE (TYPE) == ARRAY_TYPE \
230 || TREE_CODE (TYPE) == UNION_TYPE \
231 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
233 /* Operations between registers always perform the operation
234 on the full register even if a narrower mode is specified. */
235 #define WORD_REGISTER_OPERATIONS
237 /* Xtensa loads are zero-extended by default. */
238 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
240 /* Standard register usage. */
242 /* Number of actual hardware registers.
243 The hardware registers are assigned numbers for the compiler
244 from 0 to just below FIRST_PSEUDO_REGISTER.
245 All registers that the compiler knows about must be given numbers,
246 even those that are not normally considered general registers.
248 The fake frame pointer and argument pointer will never appear in
249 the generated code, since they will always be eliminated and replaced
250 by either the stack pointer or the hard frame pointer.
252 0 - 15 AR[0] - AR[15]
253 16 FRAME_POINTER (fake = initial sp)
254 17 ARG_POINTER (fake = initial sp + framesize)
255 18 BR[0] for floating-point CC
256 19 - 34 FR[0] - FR[15]
257 35 MAC16 accumulator */
259 #define FIRST_PSEUDO_REGISTER 36
261 /* Return the stabs register number to use for REGNO. */
262 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
264 /* 1 for registers that have pervasive standard uses
265 and are not available for the register allocator. */
266 #define FIXED_REGISTERS \
268 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
270 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
274 /* 1 for registers not available across function calls.
275 These must include the FIXED_REGISTERS and also any
276 registers that can be used without being saved.
277 The latter must include the registers where values are returned
278 and the register where structure-value addresses are passed.
279 Aside from that, you can include as many other registers as you like. */
280 #define CALL_USED_REGISTERS \
282 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
284 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
288 /* For non-leaf procedures on Xtensa processors, the allocation order
289 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
290 want to use the lowest numbered registers first to minimize
291 register window overflows. However, local-alloc is not smart
292 enough to consider conflicts with incoming arguments. If an
293 incoming argument in a2 is live throughout the function and
294 local-alloc decides to use a2, then the incoming argument must
295 either be spilled or copied to another register. To get around
296 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
297 reg_alloc_order for leaf functions such that lowest numbered
298 registers are used first with the exception that the incoming
299 argument registers are not used until after other register choices
300 have been exhausted. */
302 #define REG_ALLOC_ORDER \
303 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
305 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
310 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
312 /* For Xtensa, the only point of this is to prevent GCC from otherwise
313 giving preference to call-used registers. To minimize window
314 overflows for the AR registers, we want to give preference to the
315 lower-numbered AR registers. For other register files, which are
316 not windowed, we still prefer call-used registers, if there are any. */
317 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
318 #define LEAF_REGISTERS xtensa_leaf_regs
320 /* For Xtensa, no remapping is necessary, but this macro must be
321 defined if LEAF_REGISTERS is defined. */
322 #define LEAF_REG_REMAP(REGNO) (REGNO)
324 /* This must be declared if LEAF_REGISTERS is set. */
325 extern int leaf_function;
327 /* Internal macros to classify a register number. */
329 /* 16 address registers + fake registers */
330 #define GP_REG_FIRST 0
331 #define GP_REG_LAST 17
332 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
334 /* Coprocessor registers */
335 #define BR_REG_FIRST 18
336 #define BR_REG_LAST 18
337 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
339 /* 16 floating-point registers */
340 #define FP_REG_FIRST 19
341 #define FP_REG_LAST 34
342 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
344 /* MAC16 accumulator */
345 #define ACC_REG_FIRST 35
346 #define ACC_REG_LAST 35
347 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
349 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
350 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
351 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
352 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
354 /* Return number of consecutive hard regs needed starting at reg REGNO
355 to hold something of mode MODE. */
356 #define HARD_REGNO_NREGS(REGNO, MODE) \
357 (FP_REG_P (REGNO) ? \
358 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
359 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
361 /* Value is 1 if hard register REGNO can hold a value of machine-mode
363 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
365 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
366 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
368 /* Value is 1 if it is a good idea to tie two pseudo registers
369 when one has mode MODE1 and one has mode MODE2.
370 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
371 for any hard reg, then this must be 0 for correct output. */
372 #define MODES_TIEABLE_P(MODE1, MODE2) \
373 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
374 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
375 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
376 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
378 /* Register to use for pushing function arguments. */
379 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
381 /* Base register for access to local variables of the function. */
382 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
384 /* The register number of the frame pointer register, which is used to
385 access automatic variables in the stack frame. For Xtensa, this
386 register never appears in the output. It is always eliminated to
387 either the stack pointer or the hard frame pointer. */
388 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
390 /* Value should be nonzero if functions must have frame pointers.
391 Zero means the frame pointer need not be set up (and parms
392 may be accessed via the stack pointer) in functions that seem suitable.
393 This is computed in 'reload', in reload1.c. */
394 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
396 /* Base register for access to arguments of the function. */
397 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
399 /* If the static chain is passed in memory, these macros provide rtx
400 giving 'mem' expressions that denote where they are stored.
401 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
402 seen by the calling and called functions, respectively. */
404 #define STATIC_CHAIN \
405 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
407 #define STATIC_CHAIN_INCOMING \
408 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
410 /* For now we don't try to use the full set of boolean registers. Without
411 software pipelining of FP operations, there's not much to gain and it's
412 a real pain to get them reloaded. */
413 #define FPCC_REGNUM (BR_REG_FIRST + 0)
415 /* It is as good or better to call a constant function address than to
416 call an address kept in a register. */
417 #define NO_FUNCTION_CSE 1
419 /* Xtensa processors have "register windows". GCC does not currently
420 take advantage of the possibility for variable-sized windows; instead,
421 we use a fixed window size of 8. */
423 #define INCOMING_REGNO(OUT) \
424 ((GP_REG_P (OUT) && \
425 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
426 (OUT) - WINDOW_SIZE : (OUT))
428 #define OUTGOING_REGNO(IN) \
430 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
431 (IN) + WINDOW_SIZE : (IN))
434 /* Define the classes of registers for register constraints in the
435 machine description. */
438 NO_REGS, /* no registers in set */
439 BR_REGS, /* coprocessor boolean registers */
440 FP_REGS, /* floating point registers */
441 ACC_REG, /* MAC16 accumulator */
442 SP_REG, /* sp register (aka a1) */
443 RL_REGS, /* preferred reload regs (not sp or fp) */
444 GR_REGS, /* integer registers except sp */
445 AR_REGS, /* all integer registers */
446 ALL_REGS, /* all registers */
447 LIM_REG_CLASSES /* max value + 1 */
450 #define N_REG_CLASSES (int) LIM_REG_CLASSES
452 #define GENERAL_REGS AR_REGS
454 /* An initializer containing the names of the register classes as C
455 string constants. These names are used in writing some of the
457 #define REG_CLASS_NAMES \
470 /* Contents of the register classes. The Nth integer specifies the
471 contents of class N. The way the integer MASK is interpreted is
472 that register R is in the class if 'MASK & (1 << R)' is 1. */
473 #define REG_CLASS_CONTENTS \
475 { 0x00000000, 0x00000000 }, /* no registers */ \
476 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
477 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
478 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
479 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
480 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
481 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
482 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
483 { 0xffffffff, 0x0000000f } /* all registers */ \
486 /* A C expression whose value is a register class containing hard
487 register REGNO. In general there is more that one such class;
488 choose a class which is "minimal", meaning that no smaller class
489 also contains the register. */
490 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
492 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
494 /* Use the Xtensa AR register file for base registers.
495 No index registers. */
496 #define BASE_REG_CLASS AR_REGS
497 #define INDEX_REG_CLASS NO_REGS
499 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
500 16 AR registers may be explicitly used in the RTL, as either
501 incoming or outgoing arguments. */
502 #define SMALL_REGISTER_CLASSES 1
505 /* REGISTER AND CONSTANT CLASSES */
507 /* Get reg_class from a letter such as appears in the machine
510 Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z
512 DEFINED REGISTER CLASSES:
514 'a' general-purpose registers except sp
516 'D' general-purpose registers (only if density option enabled)
517 'd' general-purpose registers, including sp (only if density enabled)
518 'A' MAC16 accumulator (only if MAC16 option enabled)
519 'B' general-purpose registers (only if sext instruction enabled)
520 'C' general-purpose registers (only if mul16 option enabled)
521 'W' general-purpose registers (only if const16 option enabled)
522 'b' coprocessor boolean registers
523 'f' floating-point registers
526 extern enum reg_class xtensa_char_to_class[256];
528 #define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ]
530 /* The letters I, J, K, L, M, N, O, and P in a register constraint
531 string can be used to stand for particular ranges of immediate
532 operands. This macro defines what the ranges are. C is the
533 letter, and VALUE is a constant value. Return 1 if VALUE is
534 in the range specified by C.
538 I = 12-bit signed immediate for movi
539 J = 8-bit signed immediate for addi
540 K = 4-bit value in (b4const U {0})
541 L = 4-bit value in b4constu
542 M = 7-bit value in simm7
543 N = 8-bit unsigned immediate shifted left by 8 bits for addmi
544 O = 4-bit value in ai4const
545 P = valid immediate mask value for extui */
547 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
548 ((C) == 'I' ? (xtensa_simm12b (VALUE)) \
549 : (C) == 'J' ? (xtensa_simm8 (VALUE)) \
550 : (C) == 'K' ? (((VALUE) == 0) || xtensa_b4const (VALUE)) \
551 : (C) == 'L' ? (xtensa_b4constu (VALUE)) \
552 : (C) == 'M' ? (xtensa_simm7 (VALUE)) \
553 : (C) == 'N' ? (xtensa_simm8x256 (VALUE)) \
554 : (C) == 'O' ? (xtensa_ai4const (VALUE)) \
555 : (C) == 'P' ? (xtensa_mask_immediate (VALUE)) \
559 /* Similar, but for floating constants, and defining letters G and H.
560 Here VALUE is the CONST_DOUBLE rtx itself. */
561 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0)
564 /* Other letters can be defined in a machine-dependent fashion to
565 stand for particular classes of registers or other arbitrary
568 R = memory that can be accessed with a 4-bit unsigned offset
569 T = memory in a constant pool (addressable with a pc-relative load)
570 U = memory *NOT* in a constant pool
572 The offset range should not be checked here (except to distinguish
573 denser versions of the instructions for which more general versions
574 are available). Doing so leads to problems in reloading: an
575 argptr-relative address may become invalid when the phony argptr is
576 eliminated in favor of the stack pointer (the offset becomes too
577 large to fit in the instruction's immediate field); a reload is
578 generated to fix this but the RTL is not immediately updated; in
579 the meantime, the constraints are checked and none match. The
580 solution seems to be to simply skip the offset check here. The
581 address will be checked anyway because of the code in
582 GO_IF_LEGITIMATE_ADDRESS. */
584 #define EXTRA_CONSTRAINT(OP, CODE) \
585 ((GET_CODE (OP) != MEM) ? \
586 ((CODE) >= 'R' && (CODE) <= 'U' \
587 && reload_in_progress && GET_CODE (OP) == REG \
588 && REGNO (OP) >= FIRST_PSEUDO_REGISTER) \
589 : ((CODE) == 'R') ? smalloffset_mem_p (OP) \
590 : ((CODE) == 'T') ? !TARGET_CONST16 && constantpool_mem_p (OP) \
591 : ((CODE) == 'U') ? !constantpool_mem_p (OP) \
594 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
595 xtensa_preferred_reload_class (X, CLASS, 0)
597 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
598 xtensa_preferred_reload_class (X, CLASS, 1)
600 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
601 xtensa_secondary_reload_class (CLASS, MODE, X, 0)
603 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
604 xtensa_secondary_reload_class (CLASS, MODE, X, 1)
606 /* Return the maximum number of consecutive registers
607 needed to represent mode MODE in a register of class CLASS. */
608 #define CLASS_UNITS(mode, size) \
609 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
611 #define CLASS_MAX_NREGS(CLASS, MODE) \
612 (CLASS_UNITS (MODE, UNITS_PER_WORD))
615 /* Stack layout; function entry, exit and calling. */
617 #define STACK_GROWS_DOWNWARD
619 /* Offset within stack frame to start allocating local variables at. */
620 #define STARTING_FRAME_OFFSET \
621 current_function_outgoing_args_size
623 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
624 they are eliminated to either the stack pointer or hard frame pointer. */
625 #define ELIMINABLE_REGS \
626 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
627 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
628 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
629 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
631 #define CAN_ELIMINATE(FROM, TO) 1
633 /* Specify the initial difference between the specified pair of registers. */
634 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
636 compute_frame_size (get_frame_size ()); \
637 if ((FROM) == FRAME_POINTER_REGNUM) \
639 else if ((FROM) == ARG_POINTER_REGNUM) \
640 (OFFSET) = xtensa_current_frame_size; \
645 /* If defined, the maximum amount of space required for outgoing
646 arguments will be computed and placed into the variable
647 'current_function_outgoing_args_size'. No space will be pushed
648 onto the stack for each call; instead, the function prologue
649 should increase the stack frame size by this amount. */
650 #define ACCUMULATE_OUTGOING_ARGS 1
652 /* Offset from the argument pointer register to the first argument's
653 address. On some machines it may depend on the data type of the
654 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
655 location above the first argument's address. */
656 #define FIRST_PARM_OFFSET(FNDECL) 0
658 /* Align stack frames on 128 bits for Xtensa. This is necessary for
659 128-bit datatypes defined in TIE (e.g., for Vectra). */
660 #define STACK_BOUNDARY 128
662 /* Functions do not pop arguments off the stack. */
663 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
665 /* Use a fixed register window size of 8. */
666 #define WINDOW_SIZE 8
668 /* Symbolic macros for the registers used to return integer, floating
669 point, and values of coprocessor and user-defined modes. */
670 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
671 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
673 /* Symbolic macros for the first/last argument registers. */
674 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
675 #define GP_ARG_LAST (GP_REG_FIRST + 7)
676 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
677 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
679 #define MAX_ARGS_IN_REGISTERS 6
681 /* Don't worry about compatibility with PCC. */
682 #define DEFAULT_PCC_STRUCT_RETURN 0
684 /* Define how to find the value returned by a library function
685 assuming the value has mode MODE. Because we have defined
686 TARGET_PROMOTE_FUNCTION_RETURN that returns true, we have to
687 perform the same promotions as PROMOTE_MODE. */
688 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
689 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
690 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
692 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
694 #define LIBCALL_VALUE(MODE) \
695 XTENSA_LIBCALL_VALUE ((MODE), 0)
697 #define LIBCALL_OUTGOING_VALUE(MODE) \
698 XTENSA_LIBCALL_VALUE ((MODE), 1)
700 /* Define how to find the value returned by a function.
701 VALTYPE is the data type of the value (as a tree).
702 If the precise function being called is known, FUNC is its FUNCTION_DECL;
703 otherwise, FUNC is 0. */
704 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \
705 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
706 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
707 ? SImode: TYPE_MODE (VALTYPE), \
708 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
710 #define FUNCTION_VALUE(VALTYPE, FUNC) \
711 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
713 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
714 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
716 /* A C expression that is nonzero if REGNO is the number of a hard
717 register in which the values of called function may come back. A
718 register whose use for returning values is limited to serving as
719 the second of a pair (for a value of type 'double', say) need not
720 be recognized by this macro. If the machine has register windows,
721 so that the caller and the called function use different registers
722 for the return value, this macro should recognize only the caller's
724 #define FUNCTION_VALUE_REGNO_P(N) \
727 /* A C expression that is nonzero if REGNO is the number of a hard
728 register in which function arguments are sometimes passed. This
729 does *not* include implicit arguments such as the static chain and
730 the structure-value address. On many machines, no registers can be
731 used for this purpose since all function arguments are pushed on
733 #define FUNCTION_ARG_REGNO_P(N) \
734 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
736 /* Record the number of argument words seen so far, along with a flag to
737 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG
738 is used for both incoming and outgoing args, so a separate flag is
740 typedef struct xtensa_args
746 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
747 init_cumulative_args (&CUM, 0)
749 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
750 init_cumulative_args (&CUM, 1)
752 /* Update the data in CUM to advance over an argument
753 of mode MODE and data type TYPE.
754 (TYPE is null for libcalls where that information may not be available.) */
755 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
756 function_arg_advance (&CUM, MODE, TYPE)
758 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
759 function_arg (&CUM, MODE, TYPE, FALSE)
761 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
762 function_arg (&CUM, MODE, TYPE, TRUE)
764 /* Arguments are never passed partly in memory and partly in registers. */
765 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
767 /* Specify function argument alignment. */
768 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
770 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
772 : TYPE_ALIGN (TYPE)) \
773 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
775 : GET_MODE_ALIGNMENT (MODE)))
777 /* Profiling Xtensa code is typically done with the built-in profiling
778 feature of Tensilica's instruction set simulator, which does not
779 require any compiler support. Profiling code on a real (i.e.,
780 non-simulated) Xtensa processor is currently only supported by
781 GNU/Linux with glibc. The glibc version of _mcount doesn't require
782 counter variables. The _mcount function needs the current PC and
783 the current return address to identify an arc in the call graph.
784 Pass the current return address as the first argument; the current
785 PC is available as a0 in _mcount's register window. Both of these
786 values contain window size information in the two most significant
787 bits; we assume that _mcount will mask off those bits. The call to
788 _mcount uses a window size of 8 to make sure that it doesn't clobber
789 any incoming argument values. */
791 #define NO_PROFILE_COUNTERS 1
793 #define FUNCTION_PROFILER(FILE, LABELNO) \
795 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
798 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \
799 fprintf (FILE, "\tcallx8\ta8\n"); \
802 fprintf (FILE, "\tcall8\t_mcount\n"); \
805 /* Stack pointer value doesn't matter at exit. */
806 #define EXIT_IGNORE_STACK 1
808 /* A C statement to output, on the stream FILE, assembler code for a
809 block of data that contains the constant parts of a trampoline.
810 This code should not include a label--the label is taken care of
813 For Xtensa, the trampoline must perform an entry instruction with a
814 minimal stack frame in order to get some free registers. Once the
815 actual call target is known, the proper stack frame size is extracted
816 from the entry instruction at the target and the current frame is
817 adjusted to match. The trampoline then transfers control to the
818 instruction following the entry at the target. Note: this assumes
819 that the target begins with an entry instruction. */
821 /* minimum frame = reg save area (4 words) plus static chain (1 word)
822 and the total number of words must be a multiple of 128 bits */
823 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
825 #define TRAMPOLINE_TEMPLATE(STREAM) \
827 fprintf (STREAM, "\t.begin no-generics\n"); \
828 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \
830 /* save the return address */ \
831 fprintf (STREAM, "\tmov\ta10, a0\n"); \
833 /* Use a CALL0 instruction to skip past the constants and in the \
834 process get the PC into A0. This allows PC-relative access to \
835 the constants without relying on L32R, which may not always be \
838 fprintf (STREAM, "\tcall0\t.Lskipconsts\n"); \
839 fprintf (STREAM, "\t.align\t4\n"); \
840 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \
841 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \
842 fprintf (STREAM, ".Lskipconsts:\n"); \
844 /* store the static chain */ \
845 fprintf (STREAM, "\taddi\ta0, a0, 3\n"); \
846 fprintf (STREAM, "\tl32i\ta8, a0, 0\n"); \
847 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", MIN_FRAME_SIZE - 20); \
849 /* set the proper stack pointer value */ \
850 fprintf (STREAM, "\tl32i\ta8, a0, 4\n"); \
851 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \
852 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \
853 TARGET_BIG_ENDIAN ? 8 : 12); \
854 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \
855 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \
856 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \
857 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \
859 /* restore the return address */ \
860 fprintf (STREAM, "\tmov\ta0, a10\n"); \
862 /* jump to the instruction following the entry */ \
863 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \
864 fprintf (STREAM, "\tjx\ta8\n"); \
865 fprintf (STREAM, "\t.end no-generics\n"); \
868 /* Size in bytes of the trampoline, as an integer. */
869 #define TRAMPOLINE_SIZE 59
871 /* Alignment required for trampolines, in bits. */
872 #define TRAMPOLINE_ALIGNMENT (32)
874 /* A C statement to initialize the variable parts of a trampoline. */
875 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
878 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
879 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 16)), FUNC); \
880 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"), \
881 0, VOIDmode, 1, addr, Pmode); \
884 /* Implement `va_start' for varargs and stdarg. */
885 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
886 xtensa_va_start (valist, nextarg)
888 /* If defined, a C expression that produces the machine-specific code
889 to setup the stack so that arbitrary frames can be accessed.
891 On Xtensa, a stack back-trace must always begin from the stack pointer,
892 so that the register overflow save area can be located. However, the
893 stack-walking code in GCC always begins from the hard_frame_pointer
894 register, not the stack pointer. The frame pointer is usually equal
895 to the stack pointer, but the __builtin_return_address and
896 __builtin_frame_address functions will not work if count > 0 and
897 they are called from a routine that uses alloca. These functions
898 are not guaranteed to work at all if count > 0 so maybe that is OK.
900 A nicer solution would be to allow the architecture-specific files to
901 specify whether to start from the stack pointer or frame pointer. That
902 would also allow us to skip the machine->accesses_prev_frame stuff that
903 we currently need to ensure that there is a frame pointer when these
904 builtin functions are used. */
906 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
908 /* A C expression whose value is RTL representing the address in a
909 stack frame where the pointer to the caller's frame is stored.
910 Assume that FRAMEADDR is an RTL expression for the address of the
913 For Xtensa, there is no easy way to get the frame pointer if it is
914 not equivalent to the stack pointer. Moreover, the result of this
915 macro is used for continuing to walk back up the stack, so it must
916 return the stack pointer address. Thus, there is some inconsistency
917 here in that __builtin_frame_address will return the frame pointer
918 when count == 0 and the stack pointer when count > 0. */
920 #define DYNAMIC_CHAIN_ADDRESS(frame) \
921 gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD))
923 /* Define this if the return address of a particular stack frame is
924 accessed from the frame pointer of the previous stack frame. */
925 #define RETURN_ADDR_IN_PREVIOUS_FRAME
927 /* A C expression whose value is RTL representing the value of the
928 return address for the frame COUNT steps up from the current
929 frame, after the prologue. */
930 #define RETURN_ADDR_RTX xtensa_return_addr
932 /* Addressing modes, and classification of registers for them. */
934 /* C expressions which are nonzero if register number NUM is suitable
935 for use as a base or index register in operand addresses. It may
936 be either a suitable hard register or a pseudo register that has
937 been allocated such a hard register. The difference between an
938 index register and a base register is that the index register may
941 #define REGNO_OK_FOR_BASE_P(NUM) \
942 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
944 #define REGNO_OK_FOR_INDEX_P(NUM) 0
946 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
947 valid for use as a base or index register. For hard registers, it
948 should always accept those which the hardware permits and reject
949 the others. Whether the macro accepts or rejects pseudo registers
950 must be controlled by `REG_OK_STRICT'. This usually requires two
951 variant definitions, of which `REG_OK_STRICT' controls the one
952 actually used. The difference between an index register and a base
953 register is that the index register may be scaled. */
957 #define REG_OK_FOR_INDEX_P(X) 0
958 #define REG_OK_FOR_BASE_P(X) \
959 REGNO_OK_FOR_BASE_P (REGNO (X))
961 #else /* !REG_OK_STRICT */
963 #define REG_OK_FOR_INDEX_P(X) 0
964 #define REG_OK_FOR_BASE_P(X) \
965 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X))))
967 #endif /* !REG_OK_STRICT */
969 /* Maximum number of registers that can appear in a valid memory address. */
970 #define MAX_REGS_PER_ADDRESS 1
972 /* Identify valid Xtensa addresses. */
973 #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \
975 rtx xinsn = (ADDR); \
977 /* allow constant pool addresses */ \
978 if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \
979 && !TARGET_CONST16 && constantpool_address_p (xinsn)) \
982 while (GET_CODE (xinsn) == SUBREG) \
983 xinsn = SUBREG_REG (xinsn); \
985 /* allow base registers */ \
986 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
989 /* check for "register + offset" addressing */ \
990 if (GET_CODE (xinsn) == PLUS) \
992 rtx xplus0 = XEXP (xinsn, 0); \
993 rtx xplus1 = XEXP (xinsn, 1); \
994 enum rtx_code code0; \
995 enum rtx_code code1; \
997 while (GET_CODE (xplus0) == SUBREG) \
998 xplus0 = SUBREG_REG (xplus0); \
999 code0 = GET_CODE (xplus0); \
1001 while (GET_CODE (xplus1) == SUBREG) \
1002 xplus1 = SUBREG_REG (xplus1); \
1003 code1 = GET_CODE (xplus1); \
1005 /* swap operands if necessary so the register is first */ \
1006 if (code0 != REG && code1 == REG) \
1008 xplus0 = XEXP (xinsn, 1); \
1009 xplus1 = XEXP (xinsn, 0); \
1010 code0 = GET_CODE (xplus0); \
1011 code1 = GET_CODE (xplus1); \
1014 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
1015 && code1 == CONST_INT \
1016 && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \
1023 /* A C expression that is 1 if the RTX X is a constant which is a
1024 valid address. This is defined to be the same as 'CONSTANT_P (X)',
1025 but rejecting CONST_DOUBLE. */
1026 #define CONSTANT_ADDRESS_P(X) \
1027 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1028 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1029 || (GET_CODE (X) == CONST)))
1031 /* Nonzero if the constant value X is a legitimate general operand.
1032 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1033 #define LEGITIMATE_CONSTANT_P(X) 1
1035 /* A C expression that is nonzero if X is a legitimate immediate
1036 operand on the target machine when generating position independent
1038 #define LEGITIMATE_PIC_OPERAND_P(X) \
1039 ((GET_CODE (X) != SYMBOL_REF \
1040 || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \
1041 && GET_CODE (X) != LABEL_REF \
1042 && GET_CODE (X) != CONST)
1044 /* Tell GCC how to use ADDMI to generate addresses. */
1045 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1048 if (GET_CODE (xinsn) == PLUS) \
1050 rtx plus0 = XEXP (xinsn, 0); \
1051 rtx plus1 = XEXP (xinsn, 1); \
1053 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \
1055 plus0 = XEXP (xinsn, 1); \
1056 plus1 = XEXP (xinsn, 0); \
1059 if (GET_CODE (plus0) == REG \
1060 && GET_CODE (plus1) == CONST_INT \
1061 && !xtensa_mem_offset (INTVAL (plus1), MODE) \
1062 && !xtensa_simm8 (INTVAL (plus1)) \
1063 && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \
1064 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \
1066 rtx temp = gen_reg_rtx (Pmode); \
1067 emit_insn (gen_rtx_SET (Pmode, temp, \
1068 gen_rtx_PLUS (Pmode, plus0, \
1069 GEN_INT (INTVAL (plus1) & ~0xff)))); \
1070 (X) = gen_rtx_PLUS (Pmode, temp, \
1071 GEN_INT (INTVAL (plus1) & 0xff)); \
1078 /* Treat constant-pool references as "mode dependent" since they can
1079 only be accessed with SImode loads. This works around a bug in the
1080 combiner where a constant pool reference is temporarily converted
1081 to an HImode load, which is then assumed to zero-extend based on
1082 our definition of LOAD_EXTEND_OP. This is wrong because the high
1083 bits of a 16-bit value in the constant pool are now sign-extended
1086 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1088 if (constantpool_address_p (ADDR)) \
1092 /* Specify the machine mode that this machine uses
1093 for the index in the tablejump instruction. */
1094 #define CASE_VECTOR_MODE (SImode)
1096 /* Define this as 1 if 'char' should by default be signed; else as 0. */
1097 #define DEFAULT_SIGNED_CHAR 0
1099 /* Max number of bytes we can move from memory to memory
1100 in one reasonably fast instruction. */
1102 #define MAX_MOVE_MAX 4
1104 /* Prefer word-sized loads. */
1105 #define SLOW_BYTE_ACCESS 1
1107 /* Shift instructions ignore all but the low-order few bits. */
1108 #define SHIFT_COUNT_TRUNCATED 1
1110 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1111 is done just by pretending it is already truncated. */
1112 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1114 /* Specify the machine mode that pointers have.
1115 After generation of rtl, the compiler makes no further distinction
1116 between pointers and any other objects of this machine mode. */
1117 #define Pmode SImode
1119 /* A function address in a call instruction is a word address (for
1120 indexing purposes) so give the MEM rtx a words's mode. */
1121 #define FUNCTION_MODE SImode
1123 /* A C expression for the cost of moving data from a register in
1124 class FROM to one in class TO. The classes are expressed using
1125 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
1126 the default; other values are interpreted relative to that. */
1127 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1128 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
1130 : (reg_class_subset_p ((FROM), AR_REGS) \
1131 && reg_class_subset_p ((TO), AR_REGS) \
1133 : (reg_class_subset_p ((FROM), AR_REGS) \
1134 && (TO) == ACC_REG \
1136 : ((FROM) == ACC_REG \
1137 && reg_class_subset_p ((TO), AR_REGS) \
1141 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
1143 #define BRANCH_COST 3
1145 /* Optionally define this if you have added predicates to
1146 'MACHINE.c'. This macro is called within an initializer of an
1147 array of structures. The first field in the structure is the
1148 name of a predicate and the second field is an array of rtl
1149 codes. For each predicate, list all rtl codes that can be in
1150 expressions matched by the predicate. The list should have a
1153 #define PREDICATE_CODES \
1154 {"add_operand", { REG, CONST_INT, SUBREG }}, \
1155 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
1156 {"nonimmed_operand", { REG, SUBREG, MEM }}, \
1157 {"mem_operand", { MEM }}, \
1158 {"mask_operand", { REG, CONST_INT, SUBREG }}, \
1159 {"extui_fldsz_operand", { CONST_INT }}, \
1160 {"sext_fldsz_operand", { CONST_INT }}, \
1161 {"lsbitnum_operand", { CONST_INT }}, \
1162 {"fpmem_offset_operand", { CONST_INT }}, \
1163 {"sext_operand", { REG, SUBREG, MEM }}, \
1164 {"branch_operand", { REG, CONST_INT, SUBREG }}, \
1165 {"ubranch_operand", { REG, CONST_INT, SUBREG }}, \
1166 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG }}, \
1167 {"move_operand", { REG, SUBREG, MEM, CONST_INT, CONST_DOUBLE, \
1168 CONST, SYMBOL_REF, LABEL_REF }}, \
1169 {"const_float_1_operand", { CONST_DOUBLE }}, \
1170 {"branch_operator", { EQ, NE, LT, GE }}, \
1171 {"ubranch_operator", { LTU, GEU }}, \
1172 {"boolean_operator", { EQ, NE }},
1174 /* Control the assembler format that we output. */
1176 /* How to refer to registers in assembler output.
1177 This sequence is indexed by compiler's hard-register-number (see above). */
1178 #define REGISTER_NAMES \
1180 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
1181 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
1182 "fp", "argp", "b0", \
1183 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1184 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
1188 /* If defined, a C initializer for an array of structures containing a
1189 name and a register number. This macro defines additional names
1190 for hard registers, thus allowing the 'asm' option in declarations
1191 to refer to registers using alternate names. */
1192 #define ADDITIONAL_REGISTER_NAMES \
1194 { "a1", 1 + GP_REG_FIRST } \
1197 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1198 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1200 /* Recognize machine-specific patterns that may appear within
1201 constants. Used for PIC-specific UNSPECs. */
1202 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
1204 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
1206 switch (XINT ((X), 1)) \
1209 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
1210 fputs ("@PLT", (STREAM)); \
1221 /* Globalizing directive for a label. */
1222 #define GLOBAL_ASM_OP "\t.global\t"
1224 /* Declare an uninitialized external linkage data object. */
1225 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1226 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1228 /* This is how to output an element of a case-vector that is absolute. */
1229 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1230 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
1231 LOCAL_LABEL_PREFIX, VALUE)
1233 /* This is how to output an element of a case-vector that is relative.
1234 This is used for pc-relative code. */
1235 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1237 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
1238 LOCAL_LABEL_PREFIX, (VALUE), \
1239 LOCAL_LABEL_PREFIX, (REL)); \
1242 /* This is how to output an assembler line that says to advance the
1243 location counter to a multiple of 2**LOG bytes. */
1244 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
1247 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
1250 /* Indicate that jump tables go in the text section. This is
1251 necessary when compiling PIC code. */
1252 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1255 /* Define the strings to put out for each section in the object file. */
1256 #define TEXT_SECTION_ASM_OP "\t.text"
1257 #define DATA_SECTION_ASM_OP "\t.data"
1258 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1261 /* Define output to appear before the constant pool. If the function
1262 has been assigned to a specific ELF section, or if it goes into a
1263 unique section, set the name of that section to be the literal
1265 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
1268 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
1269 fnsection = DECL_SECTION_NAME (FUNDECL); \
1270 if (fnsection != NULL_TREE) \
1272 const char *fnsectname = TREE_STRING_POINTER (fnsection); \
1273 fprintf (FILE, "\t.begin\tliteral_prefix %s\n", \
1274 strcmp (fnsectname, ".text") ? fnsectname : ""); \
1278 function_section (FUNDECL); \
1279 fprintf (FILE, "\t.literal_position\n"); \
1284 /* Define code to write out the ".end literal_prefix" directive for a
1285 function in a special section. This is appended to the standard ELF
1286 code for ASM_DECLARE_FUNCTION_SIZE. */
1287 #define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
1288 if (DECL_SECTION_NAME (DECL) != NULL_TREE) \
1289 fprintf (FILE, "\t.end\tliteral_prefix\n")
1291 /* A C statement (with or without semicolon) to output a constant in
1292 the constant pool, if it needs special treatment. */
1293 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1295 xtensa_output_literal (FILE, X, MODE, LABELNO); \
1299 /* How to start an assembler comment. */
1300 #define ASM_COMMENT_START "#"
1302 /* Exception handling TODO!! */
1303 #define DWARF_UNWIND_INFO 0
1305 /* Xtensa constant pool breaks the devices in crtstuff.c to control
1306 section in where code resides. We have to write it as asm code. Use
1307 a MOVI and let the assembler relax it -- for the .init and .fini
1308 sections, the assembler knows to put the literal in the right
1310 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1311 asm (SECTION_OP "\n\
1312 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
1314 TEXT_SECTION_ASM_OP);
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