1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright (C) 2001 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Get Xtensa configuration settings */
23 #include "xtensa/xtensa-config.h"
25 /* Standard GCC variables that we reference. */
26 extern int current_function_calls_alloca;
27 extern int target_flags;
30 /* External variables defined in xtensa.c. */
34 CMP_SI, /* four byte integers */
35 CMP_DI, /* eight byte integers */
36 CMP_SF, /* single precision floats */
37 CMP_DF, /* double precision floats */
38 CMP_MAX /* max comparison type */
41 extern struct rtx_def * branch_cmp[2]; /* operands for compare */
42 extern enum cmp_type branch_type; /* what type of branch to use */
43 extern unsigned xtensa_current_frame_size;
45 /* Run-time compilation parameters selecting different hardware subsets. */
47 #define MASK_BIG_ENDIAN 0x00000001 /* big or little endian */
48 #define MASK_DENSITY 0x00000002 /* code density option */
49 #define MASK_MAC16 0x00000004 /* MAC16 option */
50 #define MASK_MUL16 0x00000008 /* 16-bit integer multiply */
51 #define MASK_MUL32 0x00000010 /* integer multiply/divide */
52 #define MASK_DIV32 0x00000020 /* integer multiply/divide */
53 #define MASK_NSA 0x00000040 /* nsa instruction option */
54 #define MASK_MINMAX 0x00000080 /* min/max instructions */
55 #define MASK_SEXT 0x00000100 /* sign extend insn option */
56 #define MASK_BOOLEANS 0x00000200 /* boolean register option */
57 #define MASK_HARD_FLOAT 0x00000400 /* floating-point option */
58 #define MASK_HARD_FLOAT_DIV 0x00000800 /* floating-point divide */
59 #define MASK_HARD_FLOAT_RECIP 0x00001000 /* floating-point reciprocal */
60 #define MASK_HARD_FLOAT_SQRT 0x00002000 /* floating-point sqrt */
61 #define MASK_HARD_FLOAT_RSQRT 0x00004000 /* floating-point recip sqrt */
62 #define MASK_NO_FUSED_MADD 0x00008000 /* avoid f-p mul/add */
63 #define MASK_SERIALIZE_VOLATILE 0x00010000 /* serialize volatile refs */
65 /* Macros used in the machine description to test the flags. */
67 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
68 #define TARGET_DENSITY (target_flags & MASK_DENSITY)
69 #define TARGET_MAC16 (target_flags & MASK_MAC16)
70 #define TARGET_MUL16 (target_flags & MASK_MUL16)
71 #define TARGET_MUL32 (target_flags & MASK_MUL32)
72 #define TARGET_DIV32 (target_flags & MASK_DIV32)
73 #define TARGET_NSA (target_flags & MASK_NSA)
74 #define TARGET_MINMAX (target_flags & MASK_MINMAX)
75 #define TARGET_SEXT (target_flags & MASK_SEXT)
76 #define TARGET_BOOLEANS (target_flags & MASK_BOOLEANS)
77 #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
78 #define TARGET_HARD_FLOAT_DIV (target_flags & MASK_HARD_FLOAT_DIV)
79 #define TARGET_HARD_FLOAT_RECIP (target_flags & MASK_HARD_FLOAT_RECIP)
80 #define TARGET_HARD_FLOAT_SQRT (target_flags & MASK_HARD_FLOAT_SQRT)
81 #define TARGET_HARD_FLOAT_RSQRT (target_flags & MASK_HARD_FLOAT_RSQRT)
82 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
83 #define TARGET_SERIALIZE_VOLATILE (target_flags & MASK_SERIALIZE_VOLATILE)
85 /* Default target_flags if no switches are specified */
87 #define TARGET_DEFAULT ( \
88 (XCHAL_HAVE_BE ? MASK_BIG_ENDIAN : 0) | \
89 (XCHAL_HAVE_DENSITY ? MASK_DENSITY : 0) | \
90 (XCHAL_HAVE_MAC16 ? MASK_MAC16 : 0) | \
91 (XCHAL_HAVE_MUL16 ? MASK_MUL16 : 0) | \
92 (XCHAL_HAVE_MUL32 ? MASK_MUL32 : 0) | \
93 (XCHAL_HAVE_DIV32 ? MASK_DIV32 : 0) | \
94 (XCHAL_HAVE_NSA ? MASK_NSA : 0) | \
95 (XCHAL_HAVE_MINMAX ? MASK_MINMAX : 0) | \
96 (XCHAL_HAVE_SEXT ? MASK_SEXT : 0) | \
97 (XCHAL_HAVE_BOOLEANS ? MASK_BOOLEANS : 0) | \
98 (XCHAL_HAVE_FP ? MASK_HARD_FLOAT : 0) | \
99 (XCHAL_HAVE_FP_DIV ? MASK_HARD_FLOAT_DIV : 0) | \
100 (XCHAL_HAVE_FP_RECIP ? MASK_HARD_FLOAT_RECIP : 0) | \
101 (XCHAL_HAVE_FP_SQRT ? MASK_HARD_FLOAT_SQRT : 0) | \
102 (XCHAL_HAVE_FP_RSQRT ? MASK_HARD_FLOAT_RSQRT : 0) | \
103 MASK_SERIALIZE_VOLATILE)
105 /* Macro to define tables used to set the flags. */
107 #define TARGET_SWITCHES \
109 {"big-endian", MASK_BIG_ENDIAN, \
110 N_("Use big-endian byte order")}, \
111 {"little-endian", -MASK_BIG_ENDIAN, \
112 N_("Use little-endian byte order")}, \
113 {"density", MASK_DENSITY, \
114 N_("Use the Xtensa code density option")}, \
115 {"no-density", -MASK_DENSITY, \
116 N_("Do not use the Xtensa code density option")}, \
117 {"mac16", MASK_MAC16, \
118 N_("Use the Xtensa MAC16 option")}, \
119 {"no-mac16", -MASK_MAC16, \
120 N_("Do not use the Xtensa MAC16 option")}, \
121 {"mul16", MASK_MUL16, \
122 N_("Use the Xtensa MUL16 option")}, \
123 {"no-mul16", -MASK_MUL16, \
124 N_("Do not use the Xtensa MUL16 option")}, \
125 {"mul32", MASK_MUL32, \
126 N_("Use the Xtensa MUL32 option")}, \
127 {"no-mul32", -MASK_MUL32, \
128 N_("Do not use the Xtensa MUL32 option")}, \
129 {"div32", MASK_DIV32, \
130 0 /* undocumented */}, \
131 {"no-div32", -MASK_DIV32, \
132 0 /* undocumented */}, \
134 N_("Use the Xtensa NSA option")}, \
135 {"no-nsa", -MASK_NSA, \
136 N_("Do not use the Xtensa NSA option")}, \
137 {"minmax", MASK_MINMAX, \
138 N_("Use the Xtensa MIN/MAX option")}, \
139 {"no-minmax", -MASK_MINMAX, \
140 N_("Do not use the Xtensa MIN/MAX option")}, \
141 {"sext", MASK_SEXT, \
142 N_("Use the Xtensa SEXT option")}, \
143 {"no-sext", -MASK_SEXT, \
144 N_("Do not use the Xtensa SEXT option")}, \
145 {"booleans", MASK_BOOLEANS, \
146 N_("Use the Xtensa boolean register option")}, \
147 {"no-booleans", -MASK_BOOLEANS, \
148 N_("Do not use the Xtensa boolean register option")}, \
149 {"hard-float", MASK_HARD_FLOAT, \
150 N_("Use the Xtensa floating-point unit")}, \
151 {"soft-float", -MASK_HARD_FLOAT, \
152 N_("Do not use the Xtensa floating-point unit")}, \
153 {"hard-float-div", MASK_HARD_FLOAT_DIV, \
154 0 /* undocumented */}, \
155 {"no-hard-float-div", -MASK_HARD_FLOAT_DIV, \
156 0 /* undocumented */}, \
157 {"hard-float-recip", MASK_HARD_FLOAT_RECIP, \
158 0 /* undocumented */}, \
159 {"no-hard-float-recip", -MASK_HARD_FLOAT_RECIP, \
160 0 /* undocumented */}, \
161 {"hard-float-sqrt", MASK_HARD_FLOAT_SQRT, \
162 0 /* undocumented */}, \
163 {"no-hard-float-sqrt", -MASK_HARD_FLOAT_SQRT, \
164 0 /* undocumented */}, \
165 {"hard-float-rsqrt", MASK_HARD_FLOAT_RSQRT, \
166 0 /* undocumented */}, \
167 {"no-hard-float-rsqrt", -MASK_HARD_FLOAT_RSQRT, \
168 0 /* undocumented */}, \
169 {"no-fused-madd", MASK_NO_FUSED_MADD, \
170 N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \
171 {"fused-madd", -MASK_NO_FUSED_MADD, \
172 N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \
173 {"serialize-volatile", MASK_SERIALIZE_VOLATILE, \
174 N_("Serialize volatile memory references with MEMW instructions")}, \
175 {"no-serialize-volatile", -MASK_SERIALIZE_VOLATILE, \
176 N_("Do not serialize volatile memory references with MEMW instructions")},\
177 {"text-section-literals", 0, \
178 N_("Intersperse literal pools with code in the text section")}, \
179 {"no-text-section-literals", 0, \
180 N_("Put literal pools in a separate literal section")}, \
181 {"target-align", 0, \
182 N_("Automatically align branch targets to reduce branch penalties")}, \
183 {"no-target-align", 0, \
184 N_("Do not automatically align branch targets")}, \
186 N_("Use indirect CALLXn instructions for large programs")}, \
187 {"no-longcalls", 0, \
188 N_("Use direct CALLn instructions for fast calls")}, \
189 {"", TARGET_DEFAULT, 0} \
193 #define OVERRIDE_OPTIONS override_options ()
196 #define CPP_ENDIAN_SPEC "\
197 %{mlittle-endian:-D__XTENSA_EL__} \
198 %{!mlittle-endian:-D__XTENSA_EB__} "
199 #else /* !XCHAL_HAVE_BE */
200 #define CPP_ENDIAN_SPEC "\
201 %{mbig-endian:-D__XTENSA_EB__} \
202 %{!mbig-endian:-D__XTENSA_EL__} "
203 #endif /* !XCHAL_HAVE_BE */
206 #define CPP_FLOAT_SPEC "%{msoft-float:-D__XTENSA_SOFT_FLOAT__}"
208 #define CPP_FLOAT_SPEC "%{!mhard-float:-D__XTENSA_SOFT_FLOAT__}"
212 #define CPP_SPEC CPP_ENDIAN_SPEC CPP_FLOAT_SPEC
214 /* Define this to set the endianness to use in libgcc2.c, which can
215 not depend on target_flags. */
216 #define LIBGCC2_WORDS_BIG_ENDIAN XCHAL_HAVE_BE
218 /* Show we can debug even without a frame pointer. */
219 #define CAN_DEBUG_WITHOUT_FP
222 /* Target machine storage layout */
224 /* Define this if most significant bit is lowest numbered
225 in instructions that operate on numbered bit-fields. */
226 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
228 /* Define this if most significant byte of a word is the lowest numbered. */
229 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
231 /* Define this if most significant word of a multiword number is the lowest. */
232 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
234 #define MAX_BITS_PER_WORD 32
236 /* Width of a word, in units (bytes). */
237 #define UNITS_PER_WORD 4
238 #define MIN_UNITS_PER_WORD 4
240 /* Width of a floating point register. */
241 #define UNITS_PER_FPREG 4
243 /* Size in bits of various types on the target machine. */
244 #define INT_TYPE_SIZE 32
245 #define MAX_INT_TYPE_SIZE 32
246 #define SHORT_TYPE_SIZE 16
247 #define LONG_TYPE_SIZE 32
248 #define MAX_LONG_TYPE_SIZE 32
249 #define LONG_LONG_TYPE_SIZE 64
250 #define FLOAT_TYPE_SIZE 32
251 #define DOUBLE_TYPE_SIZE 64
252 #define LONG_DOUBLE_TYPE_SIZE 64
254 /* Tell the preprocessor the maximum size of wchar_t. */
255 #ifndef MAX_WCHAR_TYPE_SIZE
256 #ifndef WCHAR_TYPE_SIZE
257 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
261 /* Allocation boundary (in *bits*) for storing pointers in memory. */
262 #define POINTER_BOUNDARY 32
264 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
265 #define PARM_BOUNDARY 32
267 /* Allocation boundary (in *bits*) for the code of a function. */
268 #define FUNCTION_BOUNDARY 32
270 /* Alignment of field after 'int : 0' in a structure. */
271 #define EMPTY_FIELD_BOUNDARY 32
273 /* Every structure's size must be a multiple of this. */
274 #define STRUCTURE_SIZE_BOUNDARY 8
276 /* There is no point aligning anything to a rounder boundary than this. */
277 #define BIGGEST_ALIGNMENT 128
279 /* Set this nonzero if move instructions will actually fail to work
280 when given unaligned data. */
281 #define STRICT_ALIGNMENT 1
283 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
284 for QImode, because there is no 8-bit load from memory with sign
285 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
286 loads both with and without sign extension. */
287 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
289 if (GET_MODE_CLASS (MODE) == MODE_INT \
290 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
292 if ((MODE) == QImode) \
298 /* The promotion described by `PROMOTE_MODE' should also be done for
299 outgoing function arguments. */
300 #define PROMOTE_FUNCTION_ARGS
302 /* The promotion described by `PROMOTE_MODE' should also be done for
303 the return value of functions. Note: `FUNCTION_VALUE' must perform
304 the same promotions done by `PROMOTE_MODE'. */
305 #define PROMOTE_FUNCTION_RETURN
307 /* Imitate the way many other C compilers handle alignment of
308 bitfields and the structures that contain them. */
309 #define PCC_BITFIELD_TYPE_MATTERS 1
311 /* Align string constants and constructors to at least a word boundary.
312 The typical use of this macro is to increase alignment for string
313 constants to be word aligned so that 'strcpy' calls that copy
314 constants can be done inline. */
315 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
316 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
317 && (ALIGN) < BITS_PER_WORD \
321 /* Align arrays, unions and records to at least a word boundary.
322 One use of this macro is to increase alignment of medium-size
323 data to make it all fit in fewer cache lines. Another is to
324 cause character arrays to be word-aligned so that 'strcpy' calls
325 that copy constants to character arrays can be done inline. */
326 #undef DATA_ALIGNMENT
327 #define DATA_ALIGNMENT(TYPE, ALIGN) \
328 ((((ALIGN) < BITS_PER_WORD) \
329 && (TREE_CODE (TYPE) == ARRAY_TYPE \
330 || TREE_CODE (TYPE) == UNION_TYPE \
331 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
333 /* An argument declared as 'char' or 'short' in a prototype should
334 actually be passed as an 'int'. */
335 #define PROMOTE_PROTOTYPES 1
337 /* Operations between registers always perform the operation
338 on the full register even if a narrower mode is specified. */
339 #define WORD_REGISTER_OPERATIONS
341 /* Xtensa loads are zero-extended by default. */
342 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
344 /* Standard register usage. */
346 /* Number of actual hardware registers.
347 The hardware registers are assigned numbers for the compiler
348 from 0 to just below FIRST_PSEUDO_REGISTER.
349 All registers that the compiler knows about must be given numbers,
350 even those that are not normally considered general registers.
352 The fake frame pointer and argument pointer will never appear in
353 the generated code, since they will always be eliminated and replaced
354 by either the stack pointer or the hard frame pointer.
356 0 - 15 AR[0] - AR[15]
357 16 FRAME_POINTER (fake = initial sp)
358 17 ARG_POINTER (fake = initial sp + framesize)
359 18 LOOP_COUNT (loop count special register)
360 18 BR[0] for floating-point CC
361 19 - 34 FR[0] - FR[15]
362 35 MAC16 accumulator */
364 #define FIRST_PSEUDO_REGISTER 36
366 /* Return the stabs register number to use for REGNO. */
367 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
369 /* 1 for registers that have pervasive standard uses
370 and are not available for the register allocator. */
371 #define FIXED_REGISTERS \
373 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
375 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
379 /* 1 for registers not available across function calls.
380 These must include the FIXED_REGISTERS and also any
381 registers that can be used without being saved.
382 The latter must include the registers where values are returned
383 and the register where structure-value addresses are passed.
384 Aside from that, you can include as many other registers as you like. */
385 #define CALL_USED_REGISTERS \
387 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
389 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
393 /* For non-leaf procedures on Xtensa processors, the allocation order
394 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
395 want to use the lowest numbered registers first to minimize
396 register window overflows. However, local-alloc is not smart
397 enough to consider conflicts with incoming arguments. If an
398 incoming argument in a2 is live throughout the function and
399 local-alloc decides to use a2, then the incoming argument must
400 either be spilled or copied to another register. To get around
401 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
402 reg_alloc_order for leaf functions such that lowest numbered
403 registers are used first with the exception that the incoming
404 argument registers are not used until after other register choices
405 have been exhausted. */
407 #define REG_ALLOC_ORDER \
408 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, 19, \
409 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, \
414 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
416 /* For Xtensa, the only point of this is to prevent GCC from otherwise
417 giving preference to call-used registers. To minimize window
418 overflows for the AR registers, we want to give preference to the
419 lower-numbered AR registers. For other register files, which are
420 not windowed, we still prefer call-used registers, if there are any. */
421 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
422 #define LEAF_REGISTERS xtensa_leaf_regs
424 /* For Xtensa, no remapping is necessary, but this macro must be
425 defined if LEAF_REGISTERS is defined. */
426 #define LEAF_REG_REMAP(REGNO) (REGNO)
428 /* this must be declared if LEAF_REGISTERS is set */
429 extern int leaf_function;
431 /* Internal macros to classify a register number. */
433 /* 16 address registers + fake registers */
434 #define GP_REG_FIRST 0
435 #define GP_REG_LAST 17
436 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
438 /* Special registers */
439 #define SPEC_REG_FIRST 18
440 #define SPEC_REG_LAST 18
441 #define SPEC_REG_NUM (SPEC_REG_LAST - SPEC_REG_FIRST + 1)
443 /* Coprocessor registers */
444 #define BR_REG_FIRST 18
445 #define BR_REG_LAST 18
446 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
448 /* 16 floating-point registers */
449 #define FP_REG_FIRST 19
450 #define FP_REG_LAST 34
451 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
453 /* MAC16 accumulator */
454 #define ACC_REG_FIRST 35
455 #define ACC_REG_LAST 35
456 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
458 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
459 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
460 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
461 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
463 /* Return number of consecutive hard regs needed starting at reg REGNO
464 to hold something of mode MODE. */
465 #define HARD_REGNO_NREGS(REGNO, MODE) \
466 (FP_REG_P (REGNO) ? \
467 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
468 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
470 /* Value is 1 if hard register REGNO can hold a value of machine-mode
472 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
474 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
475 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
477 /* Value is 1 if it is a good idea to tie two pseudo registers
478 when one has mode MODE1 and one has mode MODE2.
479 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
480 for any hard reg, then this must be 0 for correct output. */
481 #define MODES_TIEABLE_P(MODE1, MODE2) \
482 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
483 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
484 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
485 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
487 /* Register to use for LCOUNT special register. */
488 #define COUNT_REGISTER_REGNUM (SPEC_REG_FIRST + 0)
490 /* Register to use for pushing function arguments. */
491 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
493 /* Base register for access to local variables of the function. */
494 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
496 /* The register number of the frame pointer register, which is used to
497 access automatic variables in the stack frame. For Xtensa, this
498 register never appears in the output. It is always eliminated to
499 either the stack pointer or the hard frame pointer. */
500 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
502 /* Value should be nonzero if functions must have frame pointers.
503 Zero means the frame pointer need not be set up (and parms
504 may be accessed via the stack pointer) in functions that seem suitable.
505 This is computed in 'reload', in reload1.c. */
506 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
508 /* Base register for access to arguments of the function. */
509 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
511 /* If the static chain is passed in memory, these macros provide rtx
512 giving 'mem' expressions that denote where they are stored.
513 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
514 seen by the calling and called functions, respectively. */
516 #define STATIC_CHAIN \
517 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
519 #define STATIC_CHAIN_INCOMING \
520 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
522 /* For now we don't try to use the full set of boolean registers. Without
523 software pipelining of FP operations, there's not much to gain and it's
524 a real pain to get them reloaded. */
525 #define FPCC_REGNUM (BR_REG_FIRST + 0)
527 /* Pass structure value address as an "invisible" first argument. */
528 #define STRUCT_VALUE 0
530 /* It is as good or better to call a constant function address than to
531 call an address kept in a register. */
532 #define NO_FUNCTION_CSE 1
534 /* It is as good or better for a function to call itself with an
535 explicit address than to call an address kept in a register. */
536 #define NO_RECURSIVE_FUNCTION_CSE 1
538 /* Xtensa processors have "register windows". GCC does not currently
539 take advantage of the possibility for variable-sized windows; instead,
540 we use a fixed window size of 8. */
542 #define INCOMING_REGNO(OUT) \
543 ((GP_REG_P (OUT) && \
544 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
545 (OUT) - WINDOW_SIZE : (OUT))
547 #define OUTGOING_REGNO(IN) \
549 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
550 (IN) + WINDOW_SIZE : (IN))
553 /* Define the classes of registers for register constraints in the
554 machine description. */
557 NO_REGS, /* no registers in set */
558 BR_REGS, /* coprocessor boolean registers */
559 FP_REGS, /* floating point registers */
560 ACC_REG, /* MAC16 accumulator */
561 SP_REG, /* sp register (aka a1) */
562 GR_REGS, /* integer registers except sp */
563 AR_REGS, /* all integer registers */
564 ALL_REGS, /* all registers */
565 LIM_REG_CLASSES /* max value + 1 */
568 #define N_REG_CLASSES (int) LIM_REG_CLASSES
570 #define GENERAL_REGS AR_REGS
572 /* An initializer containing the names of the register classes as C
573 string constants. These names are used in writing some of the
575 #define REG_CLASS_NAMES \
587 /* Contents of the register classes. The Nth integer specifies the
588 contents of class N. The way the integer MASK is interpreted is
589 that register R is in the class if 'MASK & (1 << R)' is 1. */
590 #define REG_CLASS_CONTENTS \
592 { 0x00000000, 0x00000000 }, /* no registers */ \
593 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
594 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
595 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
596 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
597 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
598 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
599 { 0xffffffff, 0x0000000f } /* all registers */ \
602 /* A C expression whose value is a register class containing hard
603 register REGNO. In general there is more that one such class;
604 choose a class which is "minimal", meaning that no smaller class
605 also contains the register. */
606 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
608 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
610 /* Use the Xtensa AR register file for base registers.
611 No index registers. */
612 #define BASE_REG_CLASS AR_REGS
613 #define INDEX_REG_CLASS NO_REGS
615 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
616 16 AR registers may be explicitly used in the RTL, as either
617 incoming or outgoing arguments. */
618 #define SMALL_REGISTER_CLASSES 1
621 /* REGISTER AND CONSTANT CLASSES */
623 /* Get reg_class from a letter such as appears in the machine
626 Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z
628 DEFINED REGISTER CLASSES:
630 'a' general-purpose registers except sp
632 'D' general-purpose registers (only if density option enabled)
633 'd' general-purpose registers, including sp (only if density enabled)
634 'A' MAC16 accumulator (only if MAC16 option enabled)
635 'B' general-purpose registers (only if sext instruction enabled)
636 'C' general-purpose registers (only if mul16 option enabled)
637 'b' coprocessor boolean registers
638 'f' floating-point registers
641 extern enum reg_class xtensa_char_to_class[256];
643 #define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ]
645 /* The letters I, J, K, L, M, N, O, and P in a register constraint
646 string can be used to stand for particular ranges of immediate
647 operands. This macro defines what the ranges are. C is the
648 letter, and VALUE is a constant value. Return 1 if VALUE is
649 in the range specified by C.
653 I = 12-bit signed immediate for movi
654 J = 8-bit signed immediate for addi
655 K = 4-bit value in (b4const U {0})
656 L = 4-bit value in b4constu
657 M = 7-bit value in simm7
658 N = 8-bit unsigned immediate shifted left by 8 bits for addmi
659 O = 4-bit value in ai4const
660 P = valid immediate mask value for extui */
662 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
663 ((C) == 'I' ? (xtensa_simm12b (VALUE)) \
664 : (C) == 'J' ? (xtensa_simm8 (VALUE)) \
665 : (C) == 'K' ? (((VALUE) == 0) || xtensa_b4const (VALUE)) \
666 : (C) == 'L' ? (xtensa_b4constu (VALUE)) \
667 : (C) == 'M' ? (xtensa_simm7 (VALUE)) \
668 : (C) == 'N' ? (xtensa_simm8x256 (VALUE)) \
669 : (C) == 'O' ? (xtensa_ai4const (VALUE)) \
670 : (C) == 'P' ? (xtensa_mask_immediate (VALUE)) \
674 /* Similar, but for floating constants, and defining letters G and H.
675 Here VALUE is the CONST_DOUBLE rtx itself. */
676 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0)
679 /* Other letters can be defined in a machine-dependent fashion to
680 stand for particular classes of registers or other arbitrary
683 R = memory that can be accessed with a 4-bit unsigned offset
684 S = memory where the second word can be addressed with a 4-bit offset
685 T = memory in a constant pool (addressable with a pc-relative load)
686 U = memory *NOT* in a constant pool
688 The offset range should not be checked here (except to distinguish
689 denser versions of the instructions for which more general versions
690 are available). Doing so leads to problems in reloading: an
691 argptr-relative address may become invalid when the phony argptr is
692 eliminated in favor of the stack pointer (the offset becomes too
693 large to fit in the instruction's immediate field); a reload is
694 generated to fix this but the RTL is not immediately updated; in
695 the meantime, the constraints are checked and none match. The
696 solution seems to be to simply skip the offset check here. The
697 address will be checked anyway because of the code in
698 GO_IF_LEGITIMATE_ADDRESS. */
700 #define EXTRA_CONSTRAINT(OP, CODE) \
701 ((GET_CODE (OP) != MEM) ? \
702 ((CODE) >= 'R' && (CODE) <= 'U' \
703 && reload_in_progress && GET_CODE (OP) == REG \
704 && REGNO (OP) >= FIRST_PSEUDO_REGISTER) \
705 : ((CODE) == 'R') ? smalloffset_mem_p (OP) \
706 : ((CODE) == 'S') ? smalloffset_double_mem_p (OP) \
707 : ((CODE) == 'T') ? constantpool_mem_p (OP) \
708 : ((CODE) == 'U') ? !constantpool_mem_p (OP) \
711 /* Given an rtx X being reloaded into a reg required to be
712 in class CLASS, return the class of reg to actually use. */
713 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
715 ? (GET_CODE (X) == CONST_DOUBLE) ? NO_REGS : (CLASS) \
718 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
721 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
722 xtensa_secondary_reload_class (CLASS, MODE, X, 0)
724 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
725 xtensa_secondary_reload_class (CLASS, MODE, X, 1)
727 /* Return the maximum number of consecutive registers
728 needed to represent mode MODE in a register of class CLASS. */
729 #define CLASS_UNITS(mode, size) \
730 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
732 #define CLASS_MAX_NREGS(CLASS, MODE) \
733 (CLASS_UNITS (MODE, UNITS_PER_WORD))
736 /* Stack layout; function entry, exit and calling. */
738 #define STACK_GROWS_DOWNWARD
740 /* Offset within stack frame to start allocating local variables at. */
741 #define STARTING_FRAME_OFFSET \
742 current_function_outgoing_args_size
744 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
745 they are eliminated to either the stack pointer or hard frame pointer. */
746 #define ELIMINABLE_REGS \
747 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
748 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
749 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
750 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
752 #define CAN_ELIMINATE(FROM, TO) 1
754 /* Specify the initial difference between the specified pair of registers. */
755 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
757 compute_frame_size (get_frame_size ()); \
758 if ((FROM) == FRAME_POINTER_REGNUM) \
760 else if ((FROM) == ARG_POINTER_REGNUM) \
761 (OFFSET) = xtensa_current_frame_size; \
766 /* If defined, the maximum amount of space required for outgoing
767 arguments will be computed and placed into the variable
768 'current_function_outgoing_args_size'. No space will be pushed
769 onto the stack for each call; instead, the function prologue
770 should increase the stack frame size by this amount. */
771 #define ACCUMULATE_OUTGOING_ARGS 1
773 /* Offset from the argument pointer register to the first argument's
774 address. On some machines it may depend on the data type of the
775 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
776 location above the first argument's address. */
777 #define FIRST_PARM_OFFSET(FNDECL) 0
779 /* Align stack frames on 128 bits for Xtensa. This is necessary for
780 128-bit datatypes defined in TIE (e.g., for Vectra). */
781 #define STACK_BOUNDARY 128
783 /* Functions do not pop arguments off the stack. */
784 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
786 /* Use a fixed register window size of 8. */
787 #define WINDOW_SIZE 8
789 /* Symbolic macros for the registers used to return integer, floating
790 point, and values of coprocessor and user-defined modes. */
791 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
792 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
794 /* Symbolic macros for the first/last argument registers. */
795 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
796 #define GP_ARG_LAST (GP_REG_FIRST + 7)
797 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
798 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
800 #define MAX_ARGS_IN_REGISTERS 6
802 /* Don't worry about compatibility with PCC. */
803 #define DEFAULT_PCC_STRUCT_RETURN 0
805 /* For Xtensa, we would like to be able to return up to 6 words in
806 memory but GCC cannot support that. The return value must be given
807 one of the standard MODE_INT modes, and there is no 6 word mode.
808 Instead, if we try to return a 6 word structure, GCC selects the
809 next biggest mode (OImode, 8 words) and then the register allocator
810 fails because there is no 8-register group beginning with a10. So
811 we have to fall back on the next largest size which is 4 words... */
812 #define RETURN_IN_MEMORY(TYPE) \
813 ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 4 * UNITS_PER_WORD)
815 /* Define how to find the value returned by a library function
816 assuming the value has mode MODE. Because we have defined
817 PROMOTE_FUNCTION_RETURN, we have to perform the same promotions as
819 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
820 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
821 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
823 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
825 #define LIBCALL_VALUE(MODE) \
826 XTENSA_LIBCALL_VALUE ((MODE), 0)
828 #define LIBCALL_OUTGOING_VALUE(MODE) \
829 XTENSA_LIBCALL_VALUE ((MODE), 1)
831 /* Define how to find the value returned by a function.
832 VALTYPE is the data type of the value (as a tree).
833 If the precise function being called is known, FUNC is its FUNCTION_DECL;
834 otherwise, FUNC is 0. */
835 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \
836 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
837 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
838 ? SImode: TYPE_MODE (VALTYPE), \
839 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
841 #define FUNCTION_VALUE(VALTYPE, FUNC) \
842 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
844 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
845 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
847 /* A C expression that is nonzero if REGNO is the number of a hard
848 register in which the values of called function may come back. A
849 register whose use for returning values is limited to serving as
850 the second of a pair (for a value of type 'double', say) need not
851 be recognized by this macro. If the machine has register windows,
852 so that the caller and the called function use different registers
853 for the return value, this macro should recognize only the caller's
855 #define FUNCTION_VALUE_REGNO_P(N) \
858 /* A C expression that is nonzero if REGNO is the number of a hard
859 register in which function arguments are sometimes passed. This
860 does *not* include implicit arguments such as the static chain and
861 the structure-value address. On many machines, no registers can be
862 used for this purpose since all function arguments are pushed on
864 #define FUNCTION_ARG_REGNO_P(N) \
865 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
867 /* Use IEEE floating-point format. */
868 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
870 /* Define a data type for recording info about an argument list
871 during the scan of that argument list. This data type should
872 hold all necessary information about the function itself
873 and about the args processed so far, enough to enable macros
874 such as FUNCTION_ARG to determine where the next arg should go. */
875 typedef struct xtensa_args {
876 int arg_words; /* # total words the arguments take */
879 /* Initialize a variable CUM of type CUMULATIVE_ARGS
880 for a call to a function whose data type is FNTYPE.
881 For a library call, FNTYPE is 0. */
882 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
883 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
885 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
886 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
888 /* Update the data in CUM to advance over an argument
889 of mode MODE and data type TYPE.
890 (TYPE is null for libcalls where that information may not be available.) */
891 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
892 function_arg_advance (&CUM, MODE, TYPE)
894 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
895 function_arg (&CUM, MODE, TYPE, FALSE)
897 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
898 function_arg (&CUM, MODE, TYPE, TRUE)
900 /* Arguments are never passed partly in memory and partly in registers. */
901 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
903 /* Specify function argument alignment. */
904 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
906 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
908 : TYPE_ALIGN (TYPE)) \
909 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
911 : GET_MODE_ALIGNMENT (MODE)))
914 /* Nonzero if we do not know how to pass TYPE solely in registers.
915 We cannot do so in the following cases:
917 - if the type has variable size
918 - if the type is marked as addressable (it is required to be constructed
921 This differs from the default in that it does not check if the padding
922 and mode of the type are such that a copy into a register would put it
923 into the wrong part of the register. */
925 #define MUST_PASS_IN_STACK(MODE, TYPE) \
927 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
928 || TREE_ADDRESSABLE (TYPE)))
930 /* Output assembler code to FILE to increment profiler label LABELNO
931 for profiling a function entry.
933 The mcount code in glibc doesn't seem to use this LABELNO stuff.
934 Some ports (e.g., MIPS) don't even bother to pass the label
935 address, and even those that do (e.g., i386) don't seem to use it.
936 The information needed by mcount() is the current PC and the
937 current return address, so that mcount can identify an arc in the
938 call graph. For Xtensa, we pass the current return address as
939 the first argument to mcount, and the current PC is available as
940 a0 in mcount's register window. Both of these values contain
941 window size information in the two most significant bits; we assume
942 that the mcount code will mask off those bits. The call to mcount
943 uses a window size of 8 to make sure that mcount doesn't clobber
944 any incoming argument values. */
946 #define FUNCTION_PROFILER(FILE, LABELNO) \
948 fprintf (FILE, "\taddi\t%s, %s, 0\t# save current return address\n", \
949 reg_names[GP_REG_FIRST+10], \
950 reg_names[GP_REG_FIRST+0]); \
951 fprintf (FILE, "\tcall8\t_mcount\n"); \
954 /* Stack pointer value doesn't matter at exit. */
955 #define EXIT_IGNORE_STACK 1
957 /* A C statement to output, on the stream FILE, assembler code for a
958 block of data that contains the constant parts of a trampoline.
959 This code should not include a label--the label is taken care of
962 For Xtensa, the trampoline must perform an entry instruction with a
963 minimal stack frame in order to get some free registers. Once the
964 actual call target is known, the proper stack frame size is extracted
965 from the entry instruction at the target and the current frame is
966 adjusted to match. The trampoline then transfers control to the
967 instruction following the entry at the target. Note: this assumes
968 that the target begins with an entry instruction. */
970 /* minimum frame = reg save area (4 words) plus static chain (1 word)
971 and the total number of words must be a multiple of 128 bits */
972 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
974 #define TRAMPOLINE_TEMPLATE(STREAM) \
976 fprintf (STREAM, "\t.begin no-generics\n"); \
977 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \
979 /* GCC isn't prepared to deal with data at the beginning of the \
980 trampoline, and the Xtensa l32r instruction requires that the \
981 constant pool be located before the code. We put the constant \
982 pool in the middle of the trampoline and jump around it. */ \
984 fprintf (STREAM, "\tj\t.Lskipconsts\n"); \
985 fprintf (STREAM, "\t.align\t4\n"); \
986 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \
987 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \
988 fprintf (STREAM, ".Lskipconsts:\n"); \
990 /* store the static chain */ \
991 fprintf (STREAM, "\tl32r\ta8, .Lchainval\n"); \
992 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", \
993 MIN_FRAME_SIZE - (5 * UNITS_PER_WORD)); \
995 /* set the proper stack pointer value */ \
996 fprintf (STREAM, "\tl32r\ta8, .Lfnaddr\n"); \
997 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \
998 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \
999 TARGET_BIG_ENDIAN ? 8 : 12); \
1000 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \
1001 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \
1002 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \
1003 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \
1005 /* jump to the instruction following the entry */ \
1006 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \
1007 fprintf (STREAM, "\tjx\ta8\n"); \
1008 fprintf (STREAM, "\t.end no-generics\n"); \
1011 /* Size in bytes of the trampoline, as an integer. */
1012 #define TRAMPOLINE_SIZE 49
1014 /* Alignment required for trampolines, in bits. */
1015 #define TRAMPOLINE_ALIGNMENT (32)
1017 /* A C statement to initialize the variable parts of a trampoline. */
1018 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
1021 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 8)), FUNC); \
1022 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
1023 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__xtensa_sync_caches"), \
1024 0, VOIDmode, 1, addr, Pmode); \
1027 /* Define the `__builtin_va_list' type for the ABI. */
1028 #define BUILD_VA_LIST_TYPE(VALIST) \
1029 (VALIST) = xtensa_build_va_list ()
1031 /* If defined, is a C expression that produces the machine-specific
1032 code for a call to '__builtin_saveregs'. This code will be moved
1033 to the very beginning of the function, before any parameter access
1034 are made. The return value of this function should be an RTX that
1035 contains the value to use as the return of '__builtin_saveregs'. */
1036 #define EXPAND_BUILTIN_SAVEREGS \
1037 xtensa_builtin_saveregs
1039 /* Implement `va_start' for varargs and stdarg. */
1040 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1041 xtensa_va_start (stdarg, valist, nextarg)
1043 /* Implement `va_arg'. */
1044 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1045 xtensa_va_arg (valist, type)
1047 /* If defined, a C expression that produces the machine-specific code
1048 to setup the stack so that arbitrary frames can be accessed.
1050 On Xtensa, a stack back-trace must always begin from the stack pointer,
1051 so that the register overflow save area can be located. However, the
1052 stack-walking code in GCC always begins from the hard_frame_pointer
1053 register, not the stack pointer. The frame pointer is usually equal
1054 to the stack pointer, but the __builtin_return_address and
1055 __builtin_frame_address functions will not work if count > 0 and
1056 they are called from a routine that uses alloca. These functions
1057 are not guaranteed to work at all if count > 0 so maybe that is OK.
1059 A nicer solution would be to allow the architecture-specific files to
1060 specify whether to start from the stack pointer or frame pointer. That
1061 would also allow us to skip the machine->accesses_prev_frame stuff that
1062 we currently need to ensure that there is a frame pointer when these
1063 builtin functions are used. */
1065 #define SETUP_FRAME_ADDRESSES() \
1066 xtensa_setup_frame_addresses ()
1068 /* A C expression whose value is RTL representing the address in a
1069 stack frame where the pointer to the caller's frame is stored.
1070 Assume that FRAMEADDR is an RTL expression for the address of the
1073 For Xtensa, there is no easy way to get the frame pointer if it is
1074 not equivalent to the stack pointer. Moreover, the result of this
1075 macro is used for continuing to walk back up the stack, so it must
1076 return the stack pointer address. Thus, there is some inconsistency
1077 here in that __builtin_frame_address will return the frame pointer
1078 when count == 0 and the stack pointer when count > 0. */
1080 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1081 gen_rtx (PLUS, Pmode, frame, \
1082 gen_rtx_CONST_INT (VOIDmode, -3 * UNITS_PER_WORD))
1084 /* Define this if the return address of a particular stack frame is
1085 accessed from the frame pointer of the previous stack frame. */
1086 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1088 /* A C expression whose value is RTL representing the value of the
1089 return address for the frame COUNT steps up from the current
1090 frame, after the prologue. FRAMEADDR is the frame pointer of the
1091 COUNT frame, or the frame pointer of the COUNT - 1 frame if
1092 'RETURN_ADDR_IN_PREVIOUS_FRAME' is defined.
1094 The 2 most-significant bits of the return address on Xtensa hold
1095 the register window size. To get the real return address, these bits
1096 must be masked off and replaced with the high bits from the current
1097 PC. Since it is unclear how the __builtin_return_address function
1098 is used, the current code does not do this masking and simply returns
1099 the raw return address from the a0 register. */
1100 #define RETURN_ADDR_RTX(count, frame) \
1102 ? gen_rtx_REG (Pmode, 0) \
1103 : gen_rtx_MEM (Pmode, memory_address \
1104 (Pmode, plus_constant (frame, -4 * UNITS_PER_WORD))))
1107 /* Addressing modes, and classification of registers for them. */
1109 /* C expressions which are nonzero if register number NUM is suitable
1110 for use as a base or index register in operand addresses. It may
1111 be either a suitable hard register or a pseudo register that has
1112 been allocated such a hard register. The difference between an
1113 index register and a base register is that the index register may
1116 #define REGNO_OK_FOR_BASE_P(NUM) \
1117 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
1119 #define REGNO_OK_FOR_INDEX_P(NUM) 0
1121 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
1122 valid for use as a base or index register. For hard registers, it
1123 should always accept those which the hardware permits and reject
1124 the others. Whether the macro accepts or rejects pseudo registers
1125 must be controlled by `REG_OK_STRICT'. This usually requires two
1126 variant definitions, of which `REG_OK_STRICT' controls the one
1127 actually used. The difference between an index register and a base
1128 register is that the index register may be scaled. */
1130 #ifdef REG_OK_STRICT
1132 #define REG_OK_FOR_INDEX_P(X) 0
1133 #define REG_OK_FOR_BASE_P(X) \
1134 REGNO_OK_FOR_BASE_P (REGNO (X))
1136 #else /* !REG_OK_STRICT */
1138 #define REG_OK_FOR_INDEX_P(X) 0
1139 #define REG_OK_FOR_BASE_P(X) \
1140 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X))))
1142 #endif /* !REG_OK_STRICT */
1144 /* Maximum number of registers that can appear in a valid memory address. */
1145 #define MAX_REGS_PER_ADDRESS 1
1147 /* Identify valid Xtensa addresses. */
1148 #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \
1150 rtx xinsn = (ADDR); \
1152 /* allow constant pool addresses */ \
1153 if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \
1154 && constantpool_address_p (xinsn)) \
1157 while (GET_CODE (xinsn) == SUBREG) \
1158 xinsn = SUBREG_REG (xinsn); \
1160 /* allow base registers */ \
1161 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
1164 /* check for "register + offset" addressing */ \
1165 if (GET_CODE (xinsn) == PLUS) \
1167 rtx xplus0 = XEXP (xinsn, 0); \
1168 rtx xplus1 = XEXP (xinsn, 1); \
1169 enum rtx_code code0; \
1170 enum rtx_code code1; \
1172 while (GET_CODE (xplus0) == SUBREG) \
1173 xplus0 = SUBREG_REG (xplus0); \
1174 code0 = GET_CODE (xplus0); \
1176 while (GET_CODE (xplus1) == SUBREG) \
1177 xplus1 = SUBREG_REG (xplus1); \
1178 code1 = GET_CODE (xplus1); \
1180 /* swap operands if necessary so the register is first */ \
1181 if (code0 != REG && code1 == REG) \
1183 xplus0 = XEXP (xinsn, 1); \
1184 xplus1 = XEXP (xinsn, 0); \
1185 code0 = GET_CODE (xplus0); \
1186 code1 = GET_CODE (xplus1); \
1189 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
1190 && code1 == CONST_INT \
1191 && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \
1198 /* A C expression that is 1 if the RTX X is a constant which is a
1199 valid address. This is defined to be the same as 'CONSTANT_P (X)',
1200 but rejecting CONST_DOUBLE. */
1201 #define CONSTANT_ADDRESS_P(X) \
1202 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1203 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1204 || (GET_CODE (X) == CONST)))
1206 /* Nonzero if the constant value X is a legitimate general operand.
1207 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1208 #define LEGITIMATE_CONSTANT_P(X) 1
1210 /* A C expression that is nonzero if X is a legitimate immediate
1211 operand on the target machine when generating position independent
1213 #define LEGITIMATE_PIC_OPERAND_P(X) \
1214 ((GET_CODE (X) != SYMBOL_REF || SYMBOL_REF_FLAG (X)) \
1215 && GET_CODE (X) != LABEL_REF \
1216 && GET_CODE (X) != CONST)
1218 /* Tell GCC how to use ADDMI to generate addresses. */
1219 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1222 if (GET_CODE (xinsn) == PLUS) \
1224 rtx plus0 = XEXP (xinsn, 0); \
1225 rtx plus1 = XEXP (xinsn, 1); \
1227 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \
1229 plus0 = XEXP (xinsn, 1); \
1230 plus1 = XEXP (xinsn, 0); \
1233 if (GET_CODE (plus0) == REG \
1234 && GET_CODE (plus1) == CONST_INT \
1235 && !xtensa_mem_offset (INTVAL (plus1), MODE) \
1236 && !xtensa_simm8 (INTVAL (plus1)) \
1237 && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \
1238 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \
1240 rtx temp = gen_reg_rtx (Pmode); \
1241 emit_insn (gen_rtx (SET, Pmode, temp, \
1242 gen_rtx (PLUS, Pmode, plus0, \
1243 GEN_INT (INTVAL (plus1) & ~0xff)))); \
1244 (X) = gen_rtx (PLUS, Pmode, temp, \
1245 GEN_INT (INTVAL (plus1) & 0xff)); \
1252 /* Treat constant-pool references as "mode dependent" since they can
1253 only be accessed with SImode loads. This works around a bug in the
1254 combiner where a constant pool reference is temporarily converted
1255 to an HImode load, which is then assumed to zero-extend based on
1256 our definition of LOAD_EXTEND_OP. This is wrong because the high
1257 bits of a 16-bit value in the constant pool are now sign-extended
1260 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1262 if (constantpool_address_p (ADDR)) \
1266 /* If we are referencing a function that is static, make the SYMBOL_REF
1267 special so that we can generate direct calls to it even with -fpic. */
1268 #define ENCODE_SECTION_INFO(DECL, FIRST) \
1270 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1271 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
1274 /* Specify the machine mode that this machine uses
1275 for the index in the tablejump instruction. */
1276 #define CASE_VECTOR_MODE (SImode)
1278 /* Define this if the tablejump instruction expects the table
1279 to contain offsets from the address of the table.
1280 Do not define this if the table should contain absolute addresses. */
1281 /* #define CASE_VECTOR_PC_RELATIVE */
1283 /* Specify the tree operation to be used to convert reals to integers. */
1284 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1286 /* This is the kind of divide that is easiest to do in the general case. */
1287 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1289 /* Define this as 1 if 'char' should by default be signed; else as 0. */
1290 #define DEFAULT_SIGNED_CHAR 0
1292 /* Max number of bytes we can move from memory to memory
1293 in one reasonably fast instruction. */
1295 #define MAX_MOVE_MAX 4
1297 /* Prefer word-sized loads. */
1298 #define SLOW_BYTE_ACCESS 1
1300 /* Xtensa doesn't have any instructions that set integer values based on the
1301 results of comparisons, but the simplification code in the combiner also
1302 uses this macro. The value should be either 1 or -1 to enable some
1303 optimizations in the combiner; I'm not sure which is better for us.
1304 Since we've been using 1 for a while, it should probably stay that way for
1306 #define STORE_FLAG_VALUE 1
1308 /* Shift instructions ignore all but the low-order few bits. */
1309 #define SHIFT_COUNT_TRUNCATED 1
1311 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1312 is done just by pretending it is already truncated. */
1313 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1315 /* Specify the machine mode that pointers have.
1316 After generation of rtl, the compiler makes no further distinction
1317 between pointers and any other objects of this machine mode. */
1318 #define Pmode SImode
1320 /* A function address in a call instruction is a word address (for
1321 indexing purposes) so give the MEM rtx a words's mode. */
1322 #define FUNCTION_MODE SImode
1324 /* A C expression that evaluates to true if it is ok to perform a
1325 sibling call to DECL. */
1326 /* TODO: fix this up to allow at least some sibcalls */
1327 #define FUNCTION_OK_FOR_SIBCALL(DECL) 0
1329 /* Xtensa constant costs. */
1330 #define CONST_COSTS(X, CODE, OUTER_CODE) \
1332 switch (OUTER_CODE) \
1335 if (xtensa_simm12b (INTVAL (X))) return 4; \
1338 if (xtensa_simm8 (INTVAL (X))) return 0; \
1339 if (xtensa_simm8x256 (INTVAL (X))) return 0; \
1342 if (xtensa_mask_immediate (INTVAL (X))) return 0; \
1345 if ((INTVAL (X) == 0) || xtensa_b4const (INTVAL (X))) return 0; \
1352 /* no way to tell if X is the 2nd operand so be conservative */ \
1355 if (xtensa_simm12b (INTVAL (X))) return 5; \
1361 case CONST_DOUBLE: \
1364 /* Costs of various Xtensa operations. */
1365 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1369 (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
1370 if (memory_address_p (GET_MODE (X), XEXP ((X), 0))) \
1371 return COSTS_N_INSNS (num_words); \
1373 return COSTS_N_INSNS (2*num_words); \
1377 return COSTS_N_INSNS (TARGET_NSA ? 5 : 50); \
1380 return COSTS_N_INSNS ((GET_MODE (X) == DImode) ? 3 : 2); \
1385 if (GET_MODE (X) == DImode) return COSTS_N_INSNS (2); \
1386 return COSTS_N_INSNS (1); \
1391 if (GET_MODE (X) == DImode) return COSTS_N_INSNS (50); \
1392 return COSTS_N_INSNS (1); \
1396 enum machine_mode xmode = GET_MODE (X); \
1397 if (xmode == SFmode) \
1398 return COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); \
1399 if (xmode == DFmode) \
1400 return COSTS_N_INSNS (50); \
1401 return COSTS_N_INSNS (4); \
1407 enum machine_mode xmode = GET_MODE (X); \
1408 if (xmode == SFmode) \
1409 return COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); \
1410 if (xmode == DFmode || xmode == DImode) \
1411 return COSTS_N_INSNS (50); \
1412 return COSTS_N_INSNS (1); \
1416 return COSTS_N_INSNS ((GET_MODE (X) == DImode) ? 4 : 2); \
1420 enum machine_mode xmode = GET_MODE (X); \
1421 if (xmode == SFmode) \
1422 return COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50); \
1423 if (xmode == DFmode || xmode == DImode) \
1424 return COSTS_N_INSNS (50); \
1426 return COSTS_N_INSNS (4); \
1428 return COSTS_N_INSNS (16); \
1430 return COSTS_N_INSNS (12); \
1431 return COSTS_N_INSNS (50); \
1437 enum machine_mode xmode = GET_MODE (X); \
1438 if (xmode == SFmode) \
1439 return COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50); \
1440 if (xmode == DFmode) \
1441 return COSTS_N_INSNS (50); \
1443 /* fall through */ \
1448 enum machine_mode xmode = GET_MODE (X); \
1449 if (xmode == DImode) \
1450 return COSTS_N_INSNS (50); \
1452 return COSTS_N_INSNS (32); \
1453 return COSTS_N_INSNS (50); \
1457 if (GET_MODE (X) == SFmode) \
1458 return COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50); \
1459 return COSTS_N_INSNS (50); \
1465 return COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50); \
1467 case SIGN_EXTRACT: \
1469 return COSTS_N_INSNS (TARGET_SEXT ? 1 : 2); \
1471 case ZERO_EXTRACT: \
1473 return COSTS_N_INSNS (1);
1476 /* An expression giving the cost of an addressing mode that
1477 contains ADDRESS. */
1478 #define ADDRESS_COST(ADDR) 1
1480 /* A C expression for the cost of moving data from a register in
1481 class FROM to one in class TO. The classes are expressed using
1482 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
1483 the default; other values are interpreted relative to that. */
1484 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1485 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
1487 : (reg_class_subset_p ((FROM), AR_REGS) \
1488 && reg_class_subset_p ((TO), AR_REGS) \
1490 : (reg_class_subset_p ((FROM), AR_REGS) \
1491 && (TO) == ACC_REG \
1493 : ((FROM) == ACC_REG \
1494 && reg_class_subset_p ((TO), AR_REGS) \
1498 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
1500 #define BRANCH_COST 3
1502 /* Optionally define this if you have added predicates to
1503 'MACHINE.c'. This macro is called within an initializer of an
1504 array of structures. The first field in the structure is the
1505 name of a predicate and the second field is an array of rtl
1506 codes. For each predicate, list all rtl codes that can be in
1507 expressions matched by the predicate. The list should have a
1510 #define PREDICATE_CODES \
1511 {"add_operand", { REG, CONST_INT, SUBREG }}, \
1512 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
1513 {"nonimmed_operand", { REG, SUBREG, MEM }}, \
1514 {"non_acc_reg_operand", { REG, SUBREG }}, \
1515 {"mem_operand", { MEM }}, \
1516 {"mask_operand", { REG, CONST_INT, SUBREG }}, \
1517 {"extui_fldsz_operand", { CONST_INT }}, \
1518 {"sext_fldsz_operand", { CONST_INT }}, \
1519 {"lsbitnum_operand", { CONST_INT }}, \
1520 {"fpmem_offset_operand", { CONST_INT }}, \
1521 {"sext_operand", { REG, SUBREG, MEM }}, \
1522 {"branch_operand", { REG, CONST_INT, SUBREG }}, \
1523 {"ubranch_operand", { REG, CONST_INT, SUBREG }}, \
1524 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG }}, \
1525 {"move_operand", { REG, SUBREG, MEM, CONST_INT, CONST_DOUBLE, \
1526 CONST, SYMBOL_REF, LABEL_REF }}, \
1527 {"non_const_move_operand", { REG, SUBREG, MEM }}, \
1528 {"const_float_1_operand", { CONST_DOUBLE }}, \
1529 {"branch_operator", { EQ, NE, LT, GE }}, \
1530 {"ubranch_operator", { LTU, GEU }}, \
1531 {"boolean_operator", { EQ, NE }},
1533 /* Control the assembler format that we output. */
1535 /* How to refer to registers in assembler output.
1536 This sequence is indexed by compiler's hard-register-number (see above). */
1537 #define REGISTER_NAMES \
1539 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
1540 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
1541 "fp", "argp", "b0", \
1542 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1543 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
1547 /* If defined, a C initializer for an array of structures containing a
1548 name and a register number. This macro defines additional names
1549 for hard registers, thus allowing the 'asm' option in declarations
1550 to refer to registers using alternate names. */
1551 #define ADDITIONAL_REGISTER_NAMES \
1553 { "a1", 1 + GP_REG_FIRST } \
1556 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1557 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1559 /* Recognize machine-specific patterns that may appear within
1560 constants. Used for PIC-specific UNSPECs. */
1561 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
1563 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
1565 switch (XINT ((X), 1)) \
1568 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
1569 fputs ("@PLT", (STREAM)); \
1581 /* This is how to output the definition of a user-level label named NAME,
1582 such as the label on a static function or variable NAME. */
1583 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1585 assemble_name (STREAM, NAME); \
1586 fputs (":\n", STREAM); \
1589 /* This is how to output a command to make the user-level label named NAME
1590 defined for reference from other files. */
1591 #define ASM_GLOBALIZE_LABEL(STREAM, NAME) \
1593 fputs ("\t.global\t", STREAM); \
1594 assemble_name (STREAM, NAME); \
1595 fputs ("\n", STREAM); \
1598 /* This says how to define a global common symbol. */
1599 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1600 xtensa_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
1602 /* This says how to define a local common symbol (ie, not visible to
1604 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
1605 xtensa_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
1607 /* This is how to output an element of a case-vector that is absolute. */
1608 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1609 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
1610 LOCAL_LABEL_PREFIX, VALUE)
1612 /* This is how to output an element of a case-vector that is relative.
1613 This is used for pc-relative code. */
1614 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1616 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
1617 LOCAL_LABEL_PREFIX, (VALUE), \
1618 LOCAL_LABEL_PREFIX, (REL)); \
1621 /* This is how to output an assembler line that says to advance the
1622 location counter to a multiple of 2**LOG bytes. */
1623 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
1626 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
1629 /* Indicate that jump tables go in the text section. This is
1630 necessary when compiling PIC code. */
1631 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1634 /* Define this macro for the rare case where the RTL needs some sort of
1635 machine-dependent fixup immediately before register allocation is done.
1637 If the stack frame size is too big to fit in the immediate field of
1638 the ENTRY instruction, we need to store the frame size in the
1639 constant pool. However, the code in xtensa_function_prologue runs too
1640 late to be able to add anything to the constant pool. Since the
1641 final frame size isn't known until reload is complete, this seems
1642 like the best place to do it.
1644 There may also be some fixup required if there is an incoming argument
1645 in a7 and the function requires a frame pointer. */
1647 #define MACHINE_DEPENDENT_REORG(INSN) xtensa_reorg (INSN)
1650 /* Define the strings to put out for each section in the object file. */
1651 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
1652 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
1655 /* Define output to appear before the constant pool. If the function
1656 has been assigned to a specific ELF section, or if it goes into a
1657 unique section, set the name of that section to be the literal
1659 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
1662 resolve_unique_section ((FUNDECL), 0); \
1663 fnsection = DECL_SECTION_NAME (FUNDECL); \
1664 if (fnsection != NULL_TREE) \
1666 const char *fnsectname = TREE_STRING_POINTER (fnsection); \
1667 fprintf (FILE, "\t.begin\tliteral_prefix %s\n", \
1668 strcmp (fnsectname, ".text") ? fnsectname : ""); \
1672 function_section (FUNDECL); \
1673 fprintf (FILE, "\t.literal_position\n"); \
1678 /* Define code to write out the ".end literal_prefix" directive for a
1679 function in a special section. This is appended to the standard ELF
1680 code for ASM_DECLARE_FUNCTION_SIZE. */
1681 #define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
1682 if (DECL_SECTION_NAME (DECL) != NULL_TREE) \
1683 fprintf (FILE, "\t.end\tliteral_prefix\n")
1685 /* A C statement (with or without semicolon) to output a constant in
1686 the constant pool, if it needs special treatment. */
1687 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1689 xtensa_output_literal (FILE, X, MODE, LABELNO); \
1693 /* Store in OUTPUT a string (made with alloca) containing
1694 an assembler-name for a local static variable named NAME.
1695 LABELNO is an integer which is different for each call. */
1696 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1698 (OUTPUT) = (char *) alloca (strlen (NAME) + 10); \
1699 sprintf ((OUTPUT), "%s.%u", (NAME), (LABELNO)); \
1702 /* How to start an assembler comment. */
1703 #define ASM_COMMENT_START "#"
1705 /* Exception handling TODO!! */
1706 #define DWARF_UNWIND_INFO 0
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