1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Define the specific costs for a given cpu */
30 struct processor_costs {
34 /* Integer signed load */
37 /* Integer zeroed load */
43 /* fmov, fneg, fabs */
47 const int float_plusminus;
53 const int float_cmove;
59 const int float_div_sf;
62 const int float_div_df;
65 const int float_sqrt_sf;
68 const int float_sqrt_df;
76 /* integer multiply cost for each bit set past the most
77 significant 3, so the formula for multiply cost becomes:
80 highest_bit = highest_clear_bit(rs1);
82 highest_bit = highest_set_bit(rs1);
85 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
87 A value of zero indicates that the multiply costs is fixed,
89 const int int_mul_bit_factor;
100 /* penalty for shifts, due to scheduling rules etc. */
101 const int shift_penalty;
104 extern const struct processor_costs *sparc_costs;
106 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of
107 Solaris only; otherwise just define __sparc__. Sadly the headers
108 are such a mess there is no Solaris-specific header. */
109 #define TARGET_CPU_CPP_BUILTINS() \
112 builtin_define_std ("sparc"); \
115 builtin_assert ("cpu=sparc64"); \
116 builtin_assert ("machine=sparc64"); \
120 builtin_assert ("cpu=sparc"); \
121 builtin_assert ("machine=sparc"); \
126 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
127 /* #define SPARC_BI_ARCH */
129 /* Macro used later in this file to determine default architecture. */
130 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
132 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
133 architectures to compile for. We allow targets to choose compile time or
134 runtime selection. */
136 #if defined(__sparcv9) || defined(__arch64__)
137 #define TARGET_ARCH32 0
139 #define TARGET_ARCH32 1
143 #define TARGET_ARCH32 (! TARGET_64BIT)
145 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
146 #endif /* SPARC_BI_ARCH */
147 #endif /* IN_LIBGCC2 */
148 #define TARGET_ARCH64 (! TARGET_ARCH32)
150 /* Code model selection in 64-bit environment.
152 The machine mode used for addresses is 32-bit wide:
154 TARGET_CM_32: 32-bit address space.
155 It is the code model used when generating 32-bit code.
157 The machine mode used for addresses is 64-bit wide:
159 TARGET_CM_MEDLOW: 32-bit address space.
160 The executable must be in the low 32 bits of memory.
161 This avoids generating %uhi and %ulo terms. Programs
162 can be statically or dynamically linked.
164 TARGET_CM_MEDMID: 44-bit address space.
165 The executable must be in the low 44 bits of memory,
166 and the %[hml]44 terms are used. The text and data
167 segments have a maximum size of 2GB (31-bit span).
168 The maximum offset from any instruction to the label
169 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
171 TARGET_CM_MEDANY: 64-bit address space.
172 The text and data segments have a maximum size of 2GB
173 (31-bit span) and may be located anywhere in memory.
174 The maximum offset from any instruction to the label
175 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
177 TARGET_CM_EMBMEDANY: 64-bit address space.
178 The text and data segments have a maximum size of 2GB
179 (31-bit span) and may be located anywhere in memory.
180 The global register %g4 contains the start address of
181 the data segment. Programs are statically linked and
182 PIC is not supported.
184 Different code models are not supported in 32-bit environment. */
194 /* Value of -mcmodel specified by user. */
195 extern const char *sparc_cmodel_string;
197 extern enum cmodel sparc_cmodel;
199 /* V9 code model selection. */
200 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
201 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
202 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
203 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
205 #define SPARC_DEFAULT_CMODEL CM_32
207 /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO)
208 which requires the following macro to be true if enabled. Prior to V9,
209 there are no instructions to even talk about memory synchronization.
210 Note that the UltraSPARC III processors don't implement RMO, unlike the
211 UltraSPARC II processors.
213 Default to false; for example, Solaris never enables RMO, only ever uses
214 total memory ordering (TMO). */
215 #define SPARC_RELAXED_ORDERING false
217 /* Do not use the .note.GNU-stack convention by default. */
218 #define NEED_INDICATE_EXEC_STACK 0
220 /* This is call-clobbered in the normal ABI, but is reserved in the
221 home grown (aka upward compatible) embedded ABI. */
222 #define EMBMEDANY_BASE_REG "%g4"
224 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
225 and specified by the user via --with-cpu=foo.
226 This specifies the cpu implementation, not the architecture size. */
227 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
229 #define TARGET_CPU_sparc 0
230 #define TARGET_CPU_v7 0 /* alias for previous */
231 #define TARGET_CPU_sparclet 1
232 #define TARGET_CPU_sparclite 2
233 #define TARGET_CPU_v8 3 /* generic v8 implementation */
234 #define TARGET_CPU_supersparc 4
235 #define TARGET_CPU_hypersparc 5
236 #define TARGET_CPU_sparc86x 6
237 #define TARGET_CPU_sparclite86x 6
238 #define TARGET_CPU_v9 7 /* generic v9 implementation */
239 #define TARGET_CPU_sparcv9 7 /* alias */
240 #define TARGET_CPU_sparc64 7 /* alias */
241 #define TARGET_CPU_ultrasparc 8
242 #define TARGET_CPU_ultrasparc3 9
244 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
245 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
246 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
248 #define CPP_CPU32_DEFAULT_SPEC ""
249 #define ASM_CPU32_DEFAULT_SPEC ""
251 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
252 /* ??? What does Sun's CC pass? */
253 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
254 /* ??? It's not clear how other assemblers will handle this, so by default
255 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
256 is handled in sol2.h. */
257 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
259 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
260 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
261 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
263 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
264 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
265 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
270 #define CPP_CPU64_DEFAULT_SPEC ""
271 #define ASM_CPU64_DEFAULT_SPEC ""
273 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
274 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
275 #define CPP_CPU32_DEFAULT_SPEC ""
276 #define ASM_CPU32_DEFAULT_SPEC ""
279 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
280 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
281 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
284 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
285 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
286 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
289 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
290 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
291 #define ASM_CPU32_DEFAULT_SPEC ""
294 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
295 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
296 #define ASM_CPU32_DEFAULT_SPEC ""
299 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
300 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
301 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
306 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
307 #error Unrecognized value in TARGET_CPU_DEFAULT.
312 #define CPP_CPU_DEFAULT_SPEC \
313 (DEFAULT_ARCH32_P ? "\
314 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
315 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
317 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
318 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
320 #define ASM_CPU_DEFAULT_SPEC \
321 (DEFAULT_ARCH32_P ? "\
322 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
323 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
325 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
326 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
329 #else /* !SPARC_BI_ARCH */
331 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
332 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
334 #endif /* !SPARC_BI_ARCH */
336 /* Define macros to distinguish architectures. */
338 /* Common CPP definitions used by CPP_SPEC amongst the various targets
339 for handling -mcpu=xxx switches. */
340 #define CPP_CPU_SPEC "\
341 %{msoft-float:-D_SOFT_FLOAT} \
343 %{msparclite:-D__sparclite__} \
344 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
345 %{mv8:-D__sparc_v8__} \
346 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
347 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
348 %{mcpu=sparclite:-D__sparclite__} \
349 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
350 %{mcpu=v8:-D__sparc_v8__} \
351 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
352 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
353 %{mcpu=sparclite86x:-D__sparclite86x__} \
354 %{mcpu=v9:-D__sparc_v9__} \
355 %{mcpu=ultrasparc:-D__sparc_v9__} \
356 %{mcpu=ultrasparc3:-D__sparc_v9__} \
357 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
359 #define CPP_ARCH32_SPEC ""
360 #define CPP_ARCH64_SPEC "-D__arch64__"
362 #define CPP_ARCH_DEFAULT_SPEC \
363 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
365 #define CPP_ARCH_SPEC "\
366 %{m32:%(cpp_arch32)} \
367 %{m64:%(cpp_arch64)} \
368 %{!m32:%{!m64:%(cpp_arch_default)}} \
371 /* Macros to distinguish endianness. */
372 #define CPP_ENDIAN_SPEC "\
373 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
374 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
376 /* Macros to distinguish the particular subtarget. */
377 #define CPP_SUBTARGET_SPEC ""
379 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
381 /* Prevent error on `-sun4' and `-target sun4' options. */
382 /* This used to translate -dalign to -malign, but that is no good
383 because it can't turn off the usual meaning of making debugging dumps. */
384 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
385 ??? Delete support for -m<cpu> for 2.9. */
388 %{sun4:} %{target:} \
389 %{mcypress:-mcpu=cypress} \
390 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
391 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
394 /* Override in target specific files. */
395 #define ASM_CPU_SPEC "\
396 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
397 %{msparclite:-Asparclite} \
398 %{mf930:-Asparclite} %{mf934:-Asparclite} \
399 %{mcpu=sparclite:-Asparclite} \
400 %{mcpu=sparclite86x:-Asparclite} \
401 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
402 %{mv8plus:-Av8plus} \
404 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
405 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
406 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
409 /* Word size selection, among other things.
410 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
412 #define ASM_ARCH32_SPEC "-32"
413 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
414 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
416 #define ASM_ARCH64_SPEC "-64"
418 #define ASM_ARCH_DEFAULT_SPEC \
419 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
421 #define ASM_ARCH_SPEC "\
422 %{m32:%(asm_arch32)} \
423 %{m64:%(asm_arch64)} \
424 %{!m32:%{!m64:%(asm_arch_default)}} \
427 #ifdef HAVE_AS_RELAX_OPTION
428 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
430 #define ASM_RELAX_SPEC ""
433 /* Special flags to the Sun-4 assembler when using pipe for input. */
436 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \
437 %(asm_cpu) %(asm_relax)"
439 #define AS_NEEDS_DASH_FOR_PIPED_INPUT
441 /* This macro defines names of additional specifications to put in the specs
442 that can be used in various specifications like CC1_SPEC. Its definition
443 is an initializer with a subgrouping for each command option.
445 Each subgrouping contains a string constant, that defines the
446 specification name, and a string constant that used by the GCC driver
449 Do not define this macro if it does not need to do anything. */
451 #define EXTRA_SPECS \
452 { "cpp_cpu", CPP_CPU_SPEC }, \
453 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
454 { "cpp_arch32", CPP_ARCH32_SPEC }, \
455 { "cpp_arch64", CPP_ARCH64_SPEC }, \
456 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
457 { "cpp_arch", CPP_ARCH_SPEC }, \
458 { "cpp_endian", CPP_ENDIAN_SPEC }, \
459 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
460 { "asm_cpu", ASM_CPU_SPEC }, \
461 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
462 { "asm_arch32", ASM_ARCH32_SPEC }, \
463 { "asm_arch64", ASM_ARCH64_SPEC }, \
464 { "asm_relax", ASM_RELAX_SPEC }, \
465 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
466 { "asm_arch", ASM_ARCH_SPEC }, \
467 SUBTARGET_EXTRA_SPECS
469 #define SUBTARGET_EXTRA_SPECS
471 /* Because libgcc can generate references back to libc (via .umul etc.) we have
472 to list libc again after the second libgcc. */
473 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
476 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
477 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
479 /* ??? This should be 32 bits for v9 but what can we do? */
480 #define WCHAR_TYPE "short unsigned int"
481 #define WCHAR_TYPE_SIZE 16
483 /* Show we can debug even without a frame pointer. */
484 #define CAN_DEBUG_WITHOUT_FP
486 #define OVERRIDE_OPTIONS sparc_override_options ()
488 /* Run-time compilation parameters selecting different hardware subsets. */
490 extern int target_flags;
492 /* Nonzero if we should generate code to use the fpu. */
494 #define TARGET_FPU (target_flags & MASK_FPU)
496 /* Nonzero if we should assume that double pointers might be unaligned.
497 This can happen when linking gcc compiled code with other compilers,
498 because the ABI only guarantees 4 byte alignment. */
499 #define MASK_UNALIGNED_DOUBLES 4
500 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
502 /* Nonzero means that we should generate code for a v8 sparc. */
504 #define TARGET_V8 (target_flags & MASK_V8)
506 /* Nonzero means that we should generate code for a sparclite.
507 This enables the sparclite specific instructions, but does not affect
508 whether FPU instructions are emitted. */
509 #define MASK_SPARCLITE 0x10
510 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
512 /* Nonzero if we're compiling for the sparclet. */
513 #define MASK_SPARCLET 0x20
514 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
516 /* Nonzero if we're compiling for v9 sparc.
517 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
518 the word size is 64. */
520 #define TARGET_V9 (target_flags & MASK_V9)
522 /* Nonzero to generate code that uses the instructions deprecated in
523 the v9 architecture. This option only applies to v9 systems. */
524 /* ??? This isn't user selectable yet. It's used to enable such insns
525 on 32 bit v9 systems and for the moment they're permanently disabled
526 on 64 bit v9 systems. */
527 #define MASK_DEPRECATED_V8_INSNS 0x80
528 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
530 /* Mask of all CPU selection flags. */
532 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
534 /* Nonzero means don't pass `-assert pure-text' to the linker. */
535 #define MASK_IMPURE_TEXT 0x100
536 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
538 /* 0x200 is unused */
540 /* Nonzero means use the registers that the SPARC ABI reserves for
541 application software. This must be the default to coincide with the
542 setting in FIXED_REGISTERS. */
543 #define MASK_APP_REGS 0x400
544 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
546 /* Option to select how quad word floating point is implemented.
547 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
548 Otherwise, we use the SPARC ABI quad library functions. */
549 #define MASK_HARD_QUAD 0x800
550 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
552 /* Nonzero on little-endian machines. */
553 /* ??? Little endian support currently only exists for sparc86x-elf and
554 sparc64-elf configurations. May eventually want to expand the support
555 to all targets, but for now it's kept local to only those two. */
556 #define MASK_LITTLE_ENDIAN 0x1000
557 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
559 /* 0x2000, 0x4000 are unused */
561 /* Nonzero if pointers are 64 bits. */
562 #define MASK_PTR64 0x8000
563 #define TARGET_PTR64 (target_flags & MASK_PTR64)
565 /* Nonzero if generating code to run in a 64 bit environment.
566 This is intended to only be used by TARGET_ARCH{32,64} as they are the
567 mechanism used to control compile time or run time selection. */
568 #define MASK_64BIT 0x10000
569 #define TARGET_64BIT (target_flags & MASK_64BIT)
571 /* 0x20000,0x40000 unused */
573 /* Nonzero means use a stack bias of 2047. Stack offsets are obtained by
574 adding 2047 to %sp. This option is for v9 only and is the default. */
575 #define MASK_STACK_BIAS 0x80000
576 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
578 /* 0x100000,0x200000 unused */
580 /* Nonzero means -m{,no-}fpu was passed on the command line. */
581 #define MASK_FPU_SET 0x400000
582 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
584 /* Use the UltraSPARC Visual Instruction Set extensions. */
585 #define MASK_VIS 0x1000000
586 #define TARGET_VIS (target_flags & MASK_VIS)
588 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
589 the current out and global registers and Linux 2.2+ as well. */
590 #define MASK_V8PLUS 0x2000000
591 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
593 /* Force a the fastest alignment on structures to take advantage of
595 #define MASK_FASTER_STRUCTS 0x4000000
596 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
598 /* Use IEEE quad long double. */
599 #define MASK_LONG_DOUBLE_128 0x8000000
600 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
602 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
603 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
604 to get high 32 bits. False in V8+ or V9 because multiply stores
605 a 64 bit result in a register. */
607 #define TARGET_HARD_MUL32 \
608 ((TARGET_V8 || TARGET_SPARCLITE \
609 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
610 && ! TARGET_V8PLUS && TARGET_ARCH32)
612 #define TARGET_HARD_MUL \
613 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
614 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
617 /* Macro to define tables used to set the flags.
618 This is a list in braces of pairs in braces,
619 each pair being { "NAME", VALUE }
620 where VALUE is the bits to set or minus the bits to clear.
621 An empty string NAME is used to identify the default VALUE. */
623 #define TARGET_SWITCHES \
624 { {"fpu", MASK_FPU | MASK_FPU_SET, \
625 N_("Use hardware fp") }, \
626 {"no-fpu", -MASK_FPU, \
627 N_("Do not use hardware fp") }, \
628 {"no-fpu", MASK_FPU_SET, NULL, }, \
629 {"hard-float", MASK_FPU | MASK_FPU_SET, \
630 N_("Use hardware fp") }, \
631 {"soft-float", -MASK_FPU, \
632 N_("Do not use hardware fp") }, \
633 {"soft-float", MASK_FPU_SET, NULL }, \
634 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
635 N_("Assume possible double misalignment") }, \
636 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
637 N_("Assume all doubles are aligned") }, \
638 {"impure-text", MASK_IMPURE_TEXT, \
639 N_("Pass -assert pure-text to linker") }, \
640 {"no-impure-text", -MASK_IMPURE_TEXT, \
641 N_("Do not pass -assert pure-text to linker") }, \
642 {"app-regs", MASK_APP_REGS, \
643 N_("Use ABI reserved registers") }, \
644 {"no-app-regs", -MASK_APP_REGS, \
645 N_("Do not use ABI reserved registers") }, \
646 {"hard-quad-float", MASK_HARD_QUAD, \
647 N_("Use hardware quad fp instructions") }, \
648 {"soft-quad-float", -MASK_HARD_QUAD, \
649 N_("Do not use hardware quad fp instructions") }, \
650 {"v8plus", MASK_V8PLUS, \
651 N_("Compile for v8plus ABI") }, \
652 {"no-v8plus", -MASK_V8PLUS, \
653 N_("Do not compile for v8plus ABI") }, \
655 N_("Utilize Visual Instruction Set") }, \
656 {"no-vis", -MASK_VIS, \
657 N_("Do not utilize Visual Instruction Set") }, \
658 {"ptr64", MASK_PTR64, \
659 N_("Pointers are 64-bit") }, \
660 {"ptr32", -MASK_PTR64, \
661 N_("Pointers are 32-bit") }, \
662 {"32", -MASK_64BIT, \
663 N_("Use 32-bit ABI") }, \
665 N_("Use 64-bit ABI") }, \
666 {"stack-bias", MASK_STACK_BIAS, \
667 N_("Use stack bias") }, \
668 {"no-stack-bias", -MASK_STACK_BIAS, \
669 N_("Do not use stack bias") }, \
670 {"faster-structs", MASK_FASTER_STRUCTS, \
671 N_("Use structs on stronger alignment for double-word copies") }, \
672 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
673 N_("Do not use structs on stronger alignment for double-word copies") }, \
675 N_("Optimize tail call instructions in assembler and linker") }, \
677 N_("Do not optimize tail call instructions in assembler or linker") }, \
679 { "", TARGET_DEFAULT, ""}}
681 /* MASK_APP_REGS must always be the default because that's what
682 FIXED_REGISTERS is set to and -ffixed- is processed before
683 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
684 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
686 /* This is meant to be redefined in target specific files. */
687 #define SUBTARGET_SWITCHES
690 These must match the values for the cpu attribute in sparc.md. */
691 enum processor_type {
695 PROCESSOR_SUPERSPARC,
699 PROCESSOR_HYPERSPARC,
700 PROCESSOR_SPARCLITE86X,
704 PROCESSOR_ULTRASPARC,
705 PROCESSOR_ULTRASPARC3
708 /* This is set from -m{cpu,tune}=xxx. */
709 extern enum processor_type sparc_cpu;
711 /* Recast the cpu class to be the cpu attribute.
712 Every file includes us, but not every file includes insn-attr.h. */
713 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
715 #define TARGET_OPTIONS \
717 { "cpu=", &sparc_select[1].string, \
718 N_("Use features of and schedule code for given CPU"), 0}, \
719 { "tune=", &sparc_select[2].string, \
720 N_("Schedule code for given CPU"), 0}, \
721 { "cmodel=", &sparc_cmodel_string, \
722 N_("Use given SPARC code model"), 0}, \
726 /* This is meant to be redefined in target specific files. */
727 #define SUBTARGET_OPTIONS
729 /* Support for a compile-time default CPU, et cetera. The rules are:
730 --with-cpu is ignored if -mcpu is specified.
731 --with-tune is ignored if -mtune is specified.
732 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
734 #define OPTION_DEFAULT_SPECS \
735 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
736 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
737 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }
739 /* sparc_select[0] is reserved for the default cpu. */
740 struct sparc_cpu_select
743 const char *const name;
744 const int set_tune_p;
745 const int set_arch_p;
748 extern struct sparc_cpu_select sparc_select[];
750 /* target machine storage layout */
752 /* Define this if most significant bit is lowest numbered
753 in instructions that operate on numbered bit-fields. */
754 #define BITS_BIG_ENDIAN 1
756 /* Define this if most significant byte of a word is the lowest numbered. */
757 #define BYTES_BIG_ENDIAN 1
759 /* Define this if most significant word of a multiword number is the lowest
761 #define WORDS_BIG_ENDIAN 1
763 /* Define this to set the endianness to use in libgcc2.c, which can
764 not depend on target_flags. */
765 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
766 #define LIBGCC2_WORDS_BIG_ENDIAN 0
768 #define LIBGCC2_WORDS_BIG_ENDIAN 1
771 #define MAX_BITS_PER_WORD 64
773 /* Width of a word, in units (bytes). */
774 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
776 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
778 #define MIN_UNITS_PER_WORD 4
781 #define UNITS_PER_SIMD_WORD (TARGET_VIS ? 8 : 0)
783 /* Now define the sizes of the C data types. */
785 #define SHORT_TYPE_SIZE 16
786 #define INT_TYPE_SIZE 32
787 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
788 #define LONG_LONG_TYPE_SIZE 64
789 #define FLOAT_TYPE_SIZE 32
790 #define DOUBLE_TYPE_SIZE 64
791 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
792 SPARC ABI says that it is 128-bit wide. */
793 /* #define LONG_DOUBLE_TYPE_SIZE 128 */
795 /* Width in bits of a pointer.
796 See also the macro `Pmode' defined below. */
797 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
799 /* If we have to extend pointers (only when TARGET_ARCH64 and not
800 TARGET_PTR64), we want to do it unsigned. This macro does nothing
801 if ptr_mode and Pmode are the same. */
802 #define POINTERS_EXTEND_UNSIGNED 1
804 /* For TARGET_ARCH64 we need this, as we don't have instructions
805 for arithmetic operations which do zero/sign extension at the same time,
806 so without this we end up with a srl/sra after every assignment to an
807 user variable, which means very very bad code. */
808 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
810 && GET_MODE_CLASS (MODE) == MODE_INT \
811 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
814 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
815 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
817 /* Boundary (in *bits*) on which stack pointer should be aligned. */
818 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
819 then sp+2047 is 128-bit aligned so sp is really only byte-aligned. */
820 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
821 /* Temporary hack until the FIXME above is fixed. This macro is used
822 only in pad_to_arg_alignment in function.c; see the comment there
823 for details about what it does. */
824 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
826 /* ALIGN FRAMES on double word boundaries */
828 #define SPARC_STACK_ALIGN(LOC) \
829 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
831 /* Allocation boundary (in *bits*) for the code of a function. */
832 #define FUNCTION_BOUNDARY 32
834 /* Alignment of field after `int : 0' in a structure. */
835 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
837 /* Every structure's size must be a multiple of this. */
838 #define STRUCTURE_SIZE_BOUNDARY 8
840 /* A bit-field declared as `int' forces `int' alignment for the struct. */
841 #define PCC_BITFIELD_TYPE_MATTERS 1
843 /* No data type wants to be aligned rounder than this. */
844 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
846 /* The best alignment to use in cases where we have a choice. */
847 #define FASTEST_ALIGNMENT 64
849 /* Define this macro as an expression for the alignment of a structure
850 (given by STRUCT as a tree node) if the alignment computed in the
851 usual way is COMPUTED and the alignment explicitly specified was
854 The default is to use SPECIFIED if it is larger; otherwise, use
855 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
856 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
857 (TARGET_FASTER_STRUCTS ? \
858 ((TREE_CODE (STRUCT) == RECORD_TYPE \
859 || TREE_CODE (STRUCT) == UNION_TYPE \
860 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
861 && TYPE_FIELDS (STRUCT) != 0 \
862 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
863 : MAX ((COMPUTED), (SPECIFIED))) \
864 : MAX ((COMPUTED), (SPECIFIED)))
866 /* Make strings word-aligned so strcpy from constants will be faster. */
867 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
868 ((TREE_CODE (EXP) == STRING_CST \
869 && (ALIGN) < FASTEST_ALIGNMENT) \
870 ? FASTEST_ALIGNMENT : (ALIGN))
872 /* Make arrays of chars word-aligned for the same reasons. */
873 #define DATA_ALIGNMENT(TYPE, ALIGN) \
874 (TREE_CODE (TYPE) == ARRAY_TYPE \
875 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
876 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
878 /* Set this nonzero if move instructions will actually fail to work
879 when given unaligned data. */
880 #define STRICT_ALIGNMENT 1
882 /* Things that must be doubleword aligned cannot go in the text section,
883 because the linker fails to align the text section enough!
884 Put them in the data section. This macro is only used in this file. */
885 #define MAX_TEXT_ALIGN 32
887 /* Standard register usage. */
889 /* Number of actual hardware registers.
890 The hardware registers are assigned numbers for the compiler
891 from 0 to just below FIRST_PSEUDO_REGISTER.
892 All registers that the compiler knows about must be given numbers,
893 even those that are not normally considered general registers.
895 SPARC has 32 integer registers and 32 floating point registers.
896 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
897 accessible. We still account for them to simplify register computations
898 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
900 Register 100 is used as the integer condition code register.
901 Register 101 is used as the soft frame pointer register. */
903 #define FIRST_PSEUDO_REGISTER 102
905 #define SPARC_FIRST_FP_REG 32
906 /* Additional V9 fp regs. */
907 #define SPARC_FIRST_V9_FP_REG 64
908 #define SPARC_LAST_V9_FP_REG 95
909 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
910 #define SPARC_FIRST_V9_FCC_REG 96
911 #define SPARC_LAST_V9_FCC_REG 99
913 #define SPARC_FCC_REG 96
914 /* Integer CC reg. We don't distinguish %icc from %xcc. */
915 #define SPARC_ICC_REG 100
917 /* Nonzero if REGNO is an fp reg. */
918 #define SPARC_FP_REG_P(REGNO) \
919 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
921 /* Argument passing regs. */
922 #define SPARC_OUTGOING_INT_ARG_FIRST 8
923 #define SPARC_INCOMING_INT_ARG_FIRST 24
924 #define SPARC_FP_ARG_FIRST 32
926 /* 1 for registers that have pervasive standard uses
927 and are not available for the register allocator.
930 g1 is free to use as temporary.
931 g2-g4 are reserved for applications. Gcc normally uses them as
932 temporaries, but this can be disabled via the -mno-app-regs option.
933 g5 through g7 are reserved for the operating system.
936 g1,g5 are free to use as temporaries, and are free to use between calls
937 if the call is to an external function via the PLT.
938 g4 is free to use as a temporary in the non-embedded case.
939 g4 is reserved in the embedded case.
940 g2-g3 are reserved for applications. Gcc normally uses them as
941 temporaries, but this can be disabled via the -mno-app-regs option.
942 g6-g7 are reserved for the operating system (or application in
944 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
945 currently be a fixed register until this pattern is rewritten.
946 Register 1 is also used when restoring call-preserved registers in large
949 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
950 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
953 #define FIXED_REGISTERS \
954 {1, 0, 2, 2, 2, 2, 1, 1, \
955 0, 0, 0, 0, 0, 0, 1, 0, \
956 0, 0, 0, 0, 0, 0, 0, 0, \
957 0, 0, 0, 0, 0, 0, 1, 1, \
959 0, 0, 0, 0, 0, 0, 0, 0, \
960 0, 0, 0, 0, 0, 0, 0, 0, \
961 0, 0, 0, 0, 0, 0, 0, 0, \
962 0, 0, 0, 0, 0, 0, 0, 0, \
964 0, 0, 0, 0, 0, 0, 0, 0, \
965 0, 0, 0, 0, 0, 0, 0, 0, \
966 0, 0, 0, 0, 0, 0, 0, 0, \
967 0, 0, 0, 0, 0, 0, 0, 0, \
971 /* 1 for registers not available across function calls.
972 These must include the FIXED_REGISTERS and also any
973 registers that can be used without being saved.
974 The latter must include the registers where values are returned
975 and the register where structure-value addresses are passed.
976 Aside from that, you can include as many other registers as you like. */
978 #define CALL_USED_REGISTERS \
979 {1, 1, 1, 1, 1, 1, 1, 1, \
980 1, 1, 1, 1, 1, 1, 1, 1, \
981 0, 0, 0, 0, 0, 0, 0, 0, \
982 0, 0, 0, 0, 0, 0, 1, 1, \
984 1, 1, 1, 1, 1, 1, 1, 1, \
985 1, 1, 1, 1, 1, 1, 1, 1, \
986 1, 1, 1, 1, 1, 1, 1, 1, \
987 1, 1, 1, 1, 1, 1, 1, 1, \
989 1, 1, 1, 1, 1, 1, 1, 1, \
990 1, 1, 1, 1, 1, 1, 1, 1, \
991 1, 1, 1, 1, 1, 1, 1, 1, \
992 1, 1, 1, 1, 1, 1, 1, 1, \
996 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
997 they won't be allocated. */
999 #define CONDITIONAL_REGISTER_USAGE \
1002 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1004 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1005 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1007 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
1008 /* then honor it. */ \
1009 if (TARGET_ARCH32 && fixed_regs[5]) \
1010 fixed_regs[5] = 1; \
1011 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
1012 fixed_regs[5] = 0; \
1016 for (regno = SPARC_FIRST_V9_FP_REG; \
1017 regno <= SPARC_LAST_V9_FP_REG; \
1019 fixed_regs[regno] = 1; \
1020 /* %fcc0 is used by v8 and v9. */ \
1021 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
1022 regno <= SPARC_LAST_V9_FCC_REG; \
1024 fixed_regs[regno] = 1; \
1029 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
1030 fixed_regs[regno] = 1; \
1032 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
1033 /* then honor it. Likewise with g3 and g4. */ \
1034 if (fixed_regs[2] == 2) \
1035 fixed_regs[2] = ! TARGET_APP_REGS; \
1036 if (fixed_regs[3] == 2) \
1037 fixed_regs[3] = ! TARGET_APP_REGS; \
1038 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
1039 fixed_regs[4] = ! TARGET_APP_REGS; \
1040 else if (TARGET_CM_EMBMEDANY) \
1041 fixed_regs[4] = 1; \
1042 else if (fixed_regs[4] == 2) \
1043 fixed_regs[4] = 0; \
1047 /* Return number of consecutive hard regs needed starting at reg REGNO
1048 to hold something of mode MODE.
1049 This is ordinarily the length in words of a value of mode MODE
1050 but can be less for certain modes in special long registers.
1052 On SPARC, ordinary registers hold 32 bits worth;
1053 this means both integer and floating point registers.
1054 On v9, integer regs hold 64 bits worth; floating point regs hold
1055 32 bits worth (this includes the new fp regs as even the odd ones are
1056 included in the hard register count). */
1058 #define HARD_REGNO_NREGS(REGNO, MODE) \
1060 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
1061 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
1062 : (GET_MODE_SIZE (MODE) + 3) / 4) \
1063 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1065 /* Due to the ARCH64 discrepancy above we must override this next
1067 #define REGMODE_NATURAL_SIZE(MODE) \
1068 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
1070 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1071 See sparc.c for how we initialize this. */
1072 extern const int *hard_regno_mode_classes;
1073 extern int sparc_mode_class[];
1075 /* ??? Because of the funny way we pass parameters we should allow certain
1076 ??? types of float/complex values to be in integer registers during
1077 ??? RTL generation. This only matters on arch32. */
1078 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1079 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1081 /* Value is 1 if it is a good idea to tie two pseudo registers
1082 when one has mode MODE1 and one has mode MODE2.
1083 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1084 for any hard reg, then this must be 0 for correct output.
1086 For V9: SFmode can't be combined with other float modes, because they can't
1087 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1088 registers, but SFmode will. */
1089 #define MODES_TIEABLE_P(MODE1, MODE2) \
1090 ((MODE1) == (MODE2) \
1091 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1093 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1094 || (MODE1 != SFmode && MODE2 != SFmode)))))
1096 /* Specify the registers used for certain standard purposes.
1097 The values of these macros are register numbers. */
1099 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1100 /* #define PC_REGNUM */
1102 /* Register to use for pushing function arguments. */
1103 #define STACK_POINTER_REGNUM 14
1105 /* The stack bias (amount by which the hardware register is offset by). */
1106 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1108 /* Actual top-of-stack address is 92/176 greater than the contents of the
1109 stack pointer register for !v9/v9. That is:
1110 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1111 address, and 6*4 bytes for the 6 register parameters.
1112 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1114 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
1116 /* Base register for access to local variables of the function. */
1117 #define HARD_FRAME_POINTER_REGNUM 30
1119 /* The soft frame pointer does not have the stack bias applied. */
1120 #define FRAME_POINTER_REGNUM 101
1122 /* Given the stack bias, the stack pointer isn't actually aligned. */
1123 #define INIT_EXPANDERS \
1125 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
1127 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
1128 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
1132 /* Value should be nonzero if functions must have frame pointers.
1133 Zero means the frame pointer need not be set up (and parms
1134 may be accessed via the stack pointer) in functions that seem suitable.
1135 Used in flow.c, global.c, ra.c and reload1.c. */
1136 #define FRAME_POINTER_REQUIRED \
1137 (! (leaf_function_p () && only_leaf_regs_used ()))
1139 /* Base register for access to arguments of the function. */
1140 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1142 /* Register in which static-chain is passed to a function. This must
1143 not be a register used by the prologue. */
1144 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1146 /* Register which holds offset table for position-independent
1149 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
1151 /* Pick a default value we can notice from override_options:
1153 v9: Default is off. */
1155 #define DEFAULT_PCC_STRUCT_RETURN -1
1157 /* Functions which return large structures get the address
1158 to place the wanted value at offset 64 from the frame.
1159 Must reserve 64 bytes for the in and local registers.
1160 v9: Functions which return large structures get the address to place the
1161 wanted value from an invisible first argument. */
1162 #define STRUCT_VALUE_OFFSET 64
1164 /* Define the classes of registers for register constraints in the
1165 machine description. Also define ranges of constants.
1167 One of the classes must always be named ALL_REGS and include all hard regs.
1168 If there is more than one class, another class must be named NO_REGS
1169 and contain no registers.
1171 The name GENERAL_REGS must be the name of a class (or an alias for
1172 another name such as ALL_REGS). This is the class of registers
1173 that is allowed by "g" or "r" in a register constraint.
1174 Also, registers outside this class are allocated only when
1175 instructions express preferences for them.
1177 The classes must be numbered in nondecreasing order; that is,
1178 a larger-numbered class must never be contained completely
1179 in a smaller-numbered class.
1181 For any two classes, it is very desirable that there be another
1182 class that represents their union. */
1184 /* The SPARC has various kinds of registers: general, floating point,
1185 and condition codes [well, it has others as well, but none that we
1186 care directly about].
1188 For v9 we must distinguish between the upper and lower floating point
1189 registers because the upper ones can't hold SFmode values.
1190 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1191 satisfying a group need for a class will also satisfy a single need for
1192 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1195 It is important that one class contains all the general and all the standard
1196 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1197 because reg_class_record() will bias the selection in favor of fp regs,
1198 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1199 because FP_REGS > GENERAL_REGS.
1201 It is also important that one class contain all the general and all the
1202 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1203 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1204 allocate_reload_reg() to bypass it causing an abort because the compiler
1205 thinks it doesn't have a spill reg when in fact it does.
1207 v9 also has 4 floating point condition code registers. Since we don't
1208 have a class that is the union of FPCC_REGS with either of the others,
1209 it is important that it appear first. Otherwise the compiler will die
1210 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1213 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1214 may try to use it to hold an SImode value. See register_operand.
1215 ??? Should %fcc[0123] be handled similarly?
1218 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1219 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1220 ALL_REGS, LIM_REG_CLASSES };
1222 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1224 /* Give names of register classes as strings for dump file. */
1226 #define REG_CLASS_NAMES \
1227 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1228 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1231 /* Define which registers fit in which classes.
1232 This is an initializer for a vector of HARD_REG_SET
1233 of length N_REG_CLASSES. */
1235 #define REG_CLASS_CONTENTS \
1236 {{0, 0, 0, 0}, /* NO_REGS */ \
1237 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1238 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1239 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1240 {0, -1, 0, 0}, /* FP_REGS */ \
1241 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1242 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1243 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1244 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1246 /* Defines invalid mode changes. Borrowed from pa64-regs.h.
1248 SImode loads to floating-point registers are not zero-extended.
1249 The definition for LOAD_EXTEND_OP specifies that integer loads
1250 narrower than BITS_PER_WORD will be zero-extended. As a result,
1251 we inhibit changes from SImode unless they are to a mode that is
1252 identical in size. */
1254 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1256 && (FROM) == SImode \
1257 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1258 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
1260 /* The same information, inverted:
1261 Return the class number of the smallest class containing
1262 reg number REGNO. This could be a conditional expression
1263 or could index an array. */
1265 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1267 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1269 /* This is the order in which to allocate registers normally.
1271 We put %f0-%f7 last among the float registers, so as to make it more
1272 likely that a pseudo-register which dies in the float return register
1273 area will get allocated to the float return register, thus saving a move
1274 instruction at the end of the function.
1276 Similarly for integer return value registers.
1278 We know in this case that we will not end up with a leaf function.
1280 The register allocator is given the global and out registers first
1281 because these registers are call clobbered and thus less useful to
1282 global register allocation.
1284 Next we list the local and in registers. They are not call clobbered
1285 and thus very useful for global register allocation. We list the input
1286 registers before the locals so that it is more likely the incoming
1287 arguments received in those registers can just stay there and not be
1290 #define REG_ALLOC_ORDER \
1291 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1292 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1294 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1295 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
1296 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1297 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1298 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1299 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1300 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1301 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1302 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1303 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1304 96, 97, 98, 99, /* %fcc0-3 */ \
1305 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */
1307 /* This is the order in which to allocate registers for
1308 leaf functions. If all registers can fit in the global and
1309 output registers, then we have the possibility of having a leaf
1312 The macro actually mentioned the input registers first,
1313 because they get renumbered into the output registers once
1314 we know really do have a leaf function.
1316 To be more precise, this register allocation order is used
1317 when %o7 is found to not be clobbered right before register
1318 allocation. Normally, the reason %o7 would be clobbered is
1319 due to a call which could not be transformed into a sibling
1322 As a consequence, it is possible to use the leaf register
1323 allocation order and not end up with a leaf function. We will
1324 not get suboptimal register allocation in that case because by
1325 definition of being potentially leaf, there were no function
1326 calls. Therefore, allocation order within the local register
1327 window is not critical like it is when we do have function calls. */
1329 #define REG_LEAF_ALLOC_ORDER \
1330 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1331 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1333 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1334 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1335 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1336 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1337 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1338 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1339 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1340 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1341 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1342 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1343 96, 97, 98, 99, /* %fcc0-3 */ \
1344 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
1346 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1348 extern char sparc_leaf_regs[];
1349 #define LEAF_REGISTERS sparc_leaf_regs
1351 extern char leaf_reg_remap[];
1352 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1354 /* The class value for index registers, and the one for base regs. */
1355 #define INDEX_REG_CLASS GENERAL_REGS
1356 #define BASE_REG_CLASS GENERAL_REGS
1358 /* Local macro to handle the two v9 classes of FP regs. */
1359 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1361 /* Get reg_class from a letter such as appears in the machine description.
1362 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1363 .md file for v8 and v9.
1364 'd' and 'b' are used for single and double precision VIS operations,
1366 'h' is used for V8+ 64 bit global and out registers. */
1368 #define REG_CLASS_FROM_LETTER(C) \
1370 ? ((C) == 'f' ? FP_REGS \
1371 : (C) == 'e' ? EXTRA_FP_REGS \
1372 : (C) == 'c' ? FPCC_REGS \
1373 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1374 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1375 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1377 : ((C) == 'f' ? FP_REGS \
1378 : (C) == 'e' ? FP_REGS \
1379 : (C) == 'c' ? FPCC_REGS \
1382 /* The letters I, J, K, L and M in a register constraint string
1383 can be used to stand for particular ranges of immediate operands.
1384 This macro defines what the ranges are.
1385 C is the letter, and VALUE is a constant value.
1386 Return 1 if VALUE is in the range specified by C.
1388 `I' is used for the range of constants an insn can actually contain.
1389 `J' is used for the range which is just zero (since that is R0).
1390 `K' is used for constants which can be loaded with a single sethi insn.
1391 `L' is used for the range of constants supported by the movcc insns.
1392 `M' is used for the range of constants supported by the movrcc insns.
1393 `N' is like K, but for constants wider than 32 bits.
1394 `O' is used for the range which is just 4096. */
1396 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1397 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1398 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1399 /* 10 and 11 bit immediates are only used for a few specific insns.
1400 SMALL_INT is used throughout the port so we continue to use it. */
1401 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1402 /* 13 bit immediate, considering only the low 32 bits */
1403 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
1404 (INTVAL (X), SImode)))
1405 #define SPARC_SETHI_P(X) \
1406 (((unsigned HOST_WIDE_INT) (X) \
1407 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1408 #define SPARC_SETHI32_P(X) \
1409 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1411 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1412 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1413 : (C) == 'J' ? (VALUE) == 0 \
1414 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1415 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1416 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1417 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1418 : (C) == 'O' ? (VALUE) == 4096 \
1421 /* Similar, but for floating constants, and defining letters G and H.
1422 Here VALUE is the CONST_DOUBLE rtx itself. */
1424 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1425 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1426 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1427 : (C) == 'O' ? arith_double_4096_operand (VALUE, DImode) \
1430 /* Given an rtx X being reloaded into a reg required to be
1431 in class CLASS, return the class of reg to actually use.
1432 In general this is just CLASS; but on some machines
1433 in some cases it is preferable to use a more restrictive class. */
1434 /* - We can't load constants into FP registers.
1435 - We can't load FP constants into integer registers when soft-float,
1436 because there is no soft-float pattern with a r/F constraint.
1437 - We can't load FP constants into integer registers for TFmode unless
1438 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1439 - Try and reload integer constants (symbolic or otherwise) back into
1440 registers directly, rather than having them dumped to memory. */
1442 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1444 ? ((FP_REG_CLASS_P (CLASS) \
1445 || (CLASS) == GENERAL_OR_FP_REGS \
1446 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
1447 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1449 || (GET_MODE (X) == TFmode \
1450 && ! fp_zero_operand (X, TFmode))) \
1452 : (!FP_REG_CLASS_P (CLASS) \
1453 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1458 /* Return the register class of a scratch register needed to load IN into
1459 a register of class CLASS in MODE.
1461 We need a temporary when loading/storing a HImode/QImode value
1462 between memory and the FPU registers. This can happen when combine puts
1463 a paradoxical subreg in a float/fix conversion insn.
1465 We need a temporary when loading/storing a DFmode value between
1466 unaligned memory and the upper FPU registers. */
1468 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1469 ((FP_REG_CLASS_P (CLASS) \
1470 && ((MODE) == HImode || (MODE) == QImode) \
1471 && (GET_CODE (IN) == MEM \
1472 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1473 && true_regnum (IN) == -1))) \
1475 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1476 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1477 && ! mem_min_alignment ((IN), 8)) \
1479 : (((TARGET_CM_MEDANY \
1480 && symbolic_operand ((IN), (MODE))) \
1481 || (TARGET_CM_EMBMEDANY \
1482 && text_segment_operand ((IN), (MODE)))) \
1487 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1488 ((FP_REG_CLASS_P (CLASS) \
1489 && ((MODE) == HImode || (MODE) == QImode) \
1490 && (GET_CODE (IN) == MEM \
1491 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1492 && true_regnum (IN) == -1))) \
1494 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1495 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1496 && ! mem_min_alignment ((IN), 8)) \
1498 : (((TARGET_CM_MEDANY \
1499 && symbolic_operand ((IN), (MODE))) \
1500 || (TARGET_CM_EMBMEDANY \
1501 && text_segment_operand ((IN), (MODE)))) \
1506 /* On SPARC it is not possible to directly move data between
1507 GENERAL_REGS and FP_REGS. */
1508 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1509 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1511 /* Return the stack location to use for secondary memory needed reloads.
1512 We want to use the reserved location just below the frame pointer.
1513 However, we must ensure that there is a frame, so use assign_stack_local
1514 if the frame size is zero. */
1515 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1516 (get_frame_size () == 0 \
1517 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1518 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1519 STARTING_FRAME_OFFSET)))
1521 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1522 because the movsi and movsf patterns don't handle r/f moves.
1523 For v8 we copy the default definition. */
1524 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1526 ? (GET_MODE_BITSIZE (MODE) < 32 \
1527 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1529 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1530 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1533 /* Return the maximum number of consecutive registers
1534 needed to represent mode MODE in a register of class CLASS. */
1535 /* On SPARC, this is the size of MODE in words. */
1536 #define CLASS_MAX_NREGS(CLASS, MODE) \
1537 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1538 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1540 /* Stack layout; function entry, exit and calling. */
1542 /* Define this if pushing a word on the stack
1543 makes the stack pointer a smaller address. */
1544 #define STACK_GROWS_DOWNWARD
1546 /* Define this if the nominal address of the stack frame
1547 is at the high-address end of the local variables;
1548 that is, each additional local variable allocated
1549 goes at a more negative offset in the frame. */
1550 #define FRAME_GROWS_DOWNWARD
1552 /* Offset within stack frame to start allocating local variables at.
1553 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1554 first local allocated. Otherwise, it is the offset to the BEGINNING
1555 of the first local allocated. */
1556 /* This allows space for one TFmode floating point value. */
1557 #define STARTING_FRAME_OFFSET \
1558 (TARGET_ARCH64 ? -16 \
1559 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1561 /* If we generate an insn to push BYTES bytes,
1562 this says how many the stack pointer really advances by.
1563 On SPARC, don't define this because there are no push insns. */
1564 /* #define PUSH_ROUNDING(BYTES) */
1566 /* Offset of first parameter from the argument pointer register value.
1567 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1568 even if this function isn't going to use it.
1569 v9: This is 128 for the ins and locals. */
1570 #define FIRST_PARM_OFFSET(FNDECL) \
1571 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1573 /* Offset from the argument pointer register value to the CFA.
1574 This is different from FIRST_PARM_OFFSET because the register window
1575 comes between the CFA and the arguments. */
1576 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1578 /* When a parameter is passed in a register, stack space is still
1580 !v9: All 6 possible integer registers have backing store allocated.
1581 v9: Only space for the arguments passed is allocated. */
1582 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1583 meaning to the backend. Further, we need to be able to detect if a
1584 varargs/unprototyped function is called, as they may want to spill more
1585 registers than we've provided space. Ugly, ugly. So for now we retain
1586 all 6 slots even for v9. */
1587 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1589 /* Definitions for register elimination. */
1591 #define ELIMINABLE_REGS \
1592 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1593 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1595 /* The way this is structured, we can't eliminate SFP in favor of SP
1596 if the frame pointer is required: we want to use the SFP->HFP elimination
1597 in that case. But the test in update_eliminables doesn't know we are
1598 assuming below that we only do the former elimination. */
1599 #define CAN_ELIMINATE(FROM, TO) \
1600 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1602 /* We always pretend that this is a leaf function because if it's not,
1603 there's no point in trying to eliminate the frame pointer. If it
1604 is a leaf function, we guessed right! */
1605 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1607 if ((TO) == STACK_POINTER_REGNUM) \
1608 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \
1611 (OFFSET) += SPARC_STACK_BIAS; \
1614 /* Keep the stack pointer constant throughout the function.
1615 This is both an optimization and a necessity: longjmp
1616 doesn't behave itself when the stack pointer moves within
1618 #define ACCUMULATE_OUTGOING_ARGS 1
1620 /* Value is the number of bytes of arguments automatically
1621 popped when returning from a subroutine call.
1622 FUNDECL is the declaration node of the function (as a tree),
1623 FUNTYPE is the data type of the function (as a tree),
1624 or for a library call it is an identifier node for the subroutine name.
1625 SIZE is the number of bytes of arguments passed on the stack. */
1627 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1629 /* Define this macro if the target machine has "register windows". This
1630 C expression returns the register number as seen by the called function
1631 corresponding to register number OUT as seen by the calling function.
1632 Return OUT if register number OUT is not an outbound register. */
1634 #define INCOMING_REGNO(OUT) \
1635 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1637 /* Define this macro if the target machine has "register windows". This
1638 C expression returns the register number as seen by the calling function
1639 corresponding to register number IN as seen by the called function.
1640 Return IN if register number IN is not an inbound register. */
1642 #define OUTGOING_REGNO(IN) \
1643 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1645 /* Define this macro if the target machine has register windows. This
1646 C expression returns true if the register is call-saved but is in the
1649 #define LOCAL_REGNO(REGNO) \
1650 ((REGNO) >= 16 && (REGNO) <= 31)
1652 /* Define how to find the value returned by a function.
1653 VALTYPE is the data type of the value (as a tree).
1654 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1655 otherwise, FUNC is 0. */
1657 /* On SPARC the value is found in the first "output" register. */
1659 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1660 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1662 /* But the called function leaves it in the first "input" register. */
1664 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1665 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1667 /* Define how to find the value returned by a library function
1668 assuming the value has mode MODE. */
1670 #define LIBCALL_VALUE(MODE) \
1671 function_value (NULL_TREE, (MODE), 1)
1673 /* 1 if N is a possible register number for a function value
1674 as seen by the caller.
1675 On SPARC, the first "output" reg is used for integer values,
1676 and the first floating point register is used for floating point values. */
1678 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1680 /* Define the size of space to allocate for the return value of an
1683 #define APPLY_RESULT_SIZE 16
1685 /* 1 if N is a possible register number for function argument passing.
1686 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1688 #define FUNCTION_ARG_REGNO_P(N) \
1690 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1691 : ((N) >= 8 && (N) <= 13))
1693 /* Define a data type for recording info about an argument list
1694 during the scan of that argument list. This data type should
1695 hold all necessary information about the function itself
1696 and about the args processed so far, enough to enable macros
1697 such as FUNCTION_ARG to determine where the next arg should go.
1699 On SPARC (!v9), this is a single integer, which is a number of words
1700 of arguments scanned so far (including the invisible argument,
1701 if any, which holds the structure-value-address).
1702 Thus 7 or more means all following args should go on the stack.
1704 For v9, we also need to know whether a prototype is present. */
1707 int words; /* number of words passed so far */
1708 int prototype_p; /* nonzero if a prototype is present */
1709 int libcall_p; /* nonzero if a library call */
1711 #define CUMULATIVE_ARGS struct sparc_args
1713 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1714 for a call to a function whose data type is FNTYPE.
1715 For a library call, FNTYPE is 0. */
1717 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1718 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1720 /* Update the data in CUM to advance over an argument
1721 of mode MODE and data type TYPE.
1722 TYPE is null for libcalls where that information may not be available. */
1724 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1725 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1727 /* Determine where to put an argument to a function.
1728 Value is zero to push the argument on the stack,
1729 or a hard register in which to store the argument.
1731 MODE is the argument's machine mode.
1732 TYPE is the data type of the argument (as a tree).
1733 This is null for libcalls where that information may
1735 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1736 the preceding args and about the function being called.
1737 NAMED is nonzero if this argument is a named parameter
1738 (otherwise it is an extra parameter matching an ellipsis). */
1740 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1741 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1743 /* Define where a function finds its arguments.
1744 This is different from FUNCTION_ARG because of register windows. */
1746 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1747 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1749 /* If defined, a C expression which determines whether, and in which direction,
1750 to pad out an argument with extra space. The value should be of type
1751 `enum direction': either `upward' to pad above the argument,
1752 `downward' to pad below, or `none' to inhibit padding. */
1754 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1755 function_arg_padding ((MODE), (TYPE))
1757 /* If defined, a C expression that gives the alignment boundary, in bits,
1758 of an argument with the specified mode and type. If it is not defined,
1759 PARM_BOUNDARY is used for all arguments.
1760 For sparc64, objects requiring 16 byte alignment are passed that way. */
1762 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1764 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1765 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1766 ? 128 : PARM_BOUNDARY)
1768 /* Define the information needed to generate branch and scc insns. This is
1769 stored from the compare operation. Note that we can't use "rtx" here
1770 since it hasn't been defined! */
1772 extern GTY(()) rtx sparc_compare_op0;
1773 extern GTY(()) rtx sparc_compare_op1;
1776 /* Generate the special assembly code needed to tell the assembler whatever
1777 it might need to know about the return value of a function.
1779 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1780 information to the assembler relating to peephole optimization (done in
1783 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1784 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1786 /* Output the special assembly code needed to tell the assembler some
1787 register is used as global register variable.
1789 SPARC 64bit psABI declares registers %g2 and %g3 as application
1790 registers and %g6 and %g7 as OS registers. Any object using them
1791 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1792 and how they are used (scratch or some global variable).
1793 Linker will then refuse to link together objects which use those
1794 registers incompatibly.
1796 Unless the registers are used for scratch, two different global
1797 registers cannot be declared to the same name, so in the unlikely
1798 case of a global register variable occupying more than one register
1799 we prefix the second and following registers with .gnu.part1. etc. */
1801 extern char sparc_hard_reg_printed[8];
1803 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1804 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1806 if (TARGET_ARCH64) \
1808 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1810 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1811 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1813 if (reg == (REGNO)) \
1814 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1816 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1817 reg, reg - (REGNO), (NAME)); \
1818 sparc_hard_reg_printed[reg] = 1; \
1825 /* Emit rtl for profiling. */
1826 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1828 /* All the work done in PROFILE_HOOK, but still required. */
1829 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1831 /* Set the name of the mcount function for the system. */
1832 #define MCOUNT_FUNCTION "*mcount"
1834 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1835 the stack pointer does not matter. The value is tested only in
1836 functions that have frame pointers.
1837 No definition is equivalent to always zero. */
1839 #define EXIT_IGNORE_STACK \
1840 (get_frame_size () != 0 \
1841 || current_function_calls_alloca || current_function_outgoing_args_size)
1843 /* Define registers used by the epilogue and return instruction. */
1844 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \
1845 || (current_function_calls_eh_return && (REGNO) == 1))
1847 /* Length in units of the trampoline for entering a nested function. */
1849 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1851 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1853 /* Emit RTL insns to initialize the variable parts of a trampoline.
1854 FNADDR is an RTX for the address of the function's pure code.
1855 CXT is an RTX for the static chain value for the function. */
1857 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1858 if (TARGET_ARCH64) \
1859 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1861 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1863 /* Implement `va_start' for varargs and stdarg. */
1864 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1865 sparc_va_start (valist, nextarg)
1867 /* Generate RTL to flush the register windows so as to make arbitrary frames
1869 #define SETUP_FRAME_ADDRESSES() \
1870 emit_insn (gen_flush_register_windows ())
1872 /* Given an rtx for the address of a frame,
1873 return an rtx for the address of the word in the frame
1874 that holds the dynamic chain--the previous frame's address. */
1875 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1876 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1878 /* The return address isn't on the stack, it is in a register, so we can't
1879 access it from the current frame pointer. We can access it from the
1880 previous frame pointer though by reading a value from the register window
1882 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1884 /* This is the offset of the return address to the true next instruction to be
1885 executed for the current function. */
1886 #define RETURN_ADDR_OFFSET \
1887 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1889 /* The current return address is in %i7. The return address of anything
1890 farther back is in the register window save area at [%fp+60]. */
1891 /* ??? This ignores the fact that the actual return address is +8 for normal
1892 returns, and +12 for structure returns. */
1893 #define RETURN_ADDR_RTX(count, frame) \
1895 ? gen_rtx_REG (Pmode, 31) \
1896 : gen_rtx_MEM (Pmode, \
1897 memory_address (Pmode, plus_constant (frame, \
1898 15 * UNITS_PER_WORD \
1899 + SPARC_STACK_BIAS))))
1901 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1902 +12, but always using +8 is close enough for frame unwind purposes.
1903 Actually, just using %o7 is close enough for unwinding, but %o7+8
1904 is something you can return to. */
1905 #define INCOMING_RETURN_ADDR_RTX \
1906 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1907 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1909 /* The offset from the incoming value of %sp to the top of the stack frame
1910 for the current function. On sparc64, we have to account for the stack
1912 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1914 /* Describe how we implement __builtin_eh_return. */
1915 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1916 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1917 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1919 /* Select a format to encode pointers in exception handling data. CODE
1920 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1921 true if the symbol may be affected by dynamic relocations.
1923 If assembler and linker properly support .uaword %r_disp32(foo),
1924 then use PC relative 32-bit relocations instead of absolute relocs
1925 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1926 for binaries, to save memory.
1928 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1929 symbol %r_disp32() is against was not local, but .hidden. In that
1930 case, we have to use DW_EH_PE_absptr for pic personality. */
1931 #ifdef HAVE_AS_SPARC_UA_PCREL
1932 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1933 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1935 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1936 : ((TARGET_ARCH64 && ! GLOBAL) \
1937 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1940 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1942 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1943 : ((TARGET_ARCH64 && ! GLOBAL) \
1944 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1948 /* Emit a PC-relative relocation. */
1949 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1951 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1952 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1953 assemble_name (FILE, LABEL); \
1954 fputc (')', FILE); \
1958 /* Addressing modes, and classification of registers for them. */
1960 /* Macros to check register numbers against specific register classes. */
1962 /* These assume that REGNO is a hard or pseudo reg number.
1963 They give nonzero only if REGNO is a hard reg of the suitable class
1964 or a pseudo reg currently allocated to a suitable hard reg.
1965 Since they use reg_renumber, they are safe only once reg_renumber
1966 has been allocated, which happens in local-alloc.c. */
1968 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1969 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
1970 || (REGNO) == FRAME_POINTER_REGNUM \
1971 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1973 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1975 #define REGNO_OK_FOR_FP_P(REGNO) \
1976 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1977 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1978 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1980 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1981 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1983 /* Now macros that check whether X is a register and also,
1984 strictly, whether it is in a specified class.
1986 These macros are specific to the SPARC, and may be used only
1987 in code for printing assembler insns and in conditions for
1988 define_optimization. */
1990 /* 1 if X is an fp register. */
1992 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1994 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
1995 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
1997 /* Maximum number of registers that can appear in a valid memory address. */
1999 #define MAX_REGS_PER_ADDRESS 2
2001 /* Recognize any constant value that is a valid address.
2002 When PIC, we do not accept an address that would require a scratch reg
2003 to load into a register. */
2005 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
2007 /* Define this, so that when PIC, reload won't try to reload invalid
2008 addresses which require two reload registers. */
2010 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
2012 /* Nonzero if the constant value X is a legitimate general operand.
2013 Anything can be made to work except floating point constants.
2014 If TARGET_VIS, 0.0 can be made to work as well. */
2016 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
2018 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2019 and check its validity for a certain class.
2020 We have two alternate definitions for each of them.
2021 The usual definition accepts all pseudo regs; the other rejects
2022 them unless they have been allocated suitable hard regs.
2023 The symbol REG_OK_STRICT causes the latter definition to be used.
2025 Most source files want to accept pseudo regs in the hope that
2026 they will get allocated to the class that the insn wants them to be in.
2027 Source files for reload pass need to be strict.
2028 After reload, it makes no difference, since pseudo regs have
2029 been eliminated by then. */
2031 /* Optional extra constraints for this machine.
2033 'Q' handles floating point constants which can be moved into
2034 an integer register with a single sethi instruction.
2036 'R' handles floating point constants which can be moved into
2037 an integer register with a single mov instruction.
2039 'S' handles floating point constants which can be moved into
2040 an integer register using a high/lo_sum sequence.
2042 'T' handles memory addresses where the alignment is known to
2043 be at least 8 bytes.
2045 `U' handles all pseudo registers or a hard even numbered
2046 integer register, needed for ldd/std instructions.
2048 'W' handles the memory operand when moving operands in/out
2049 of 'e' constraint floating point registers.
2051 'Y' handles the zero vector constant. */
2053 #ifndef REG_OK_STRICT
2055 /* Nonzero if X is a hard reg that can be used as an index
2056 or if it is a pseudo reg. */
2057 #define REG_OK_FOR_INDEX_P(X) \
2059 || REGNO (X) == FRAME_POINTER_REGNUM \
2060 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2062 /* Nonzero if X is a hard reg that can be used as a base reg
2063 or if it is a pseudo reg. */
2064 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
2066 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
2067 'W' is like 'T' but is assumed true on arch64.
2069 Remember to accept pseudo-registers for memory constraints if reload is
2072 #define EXTRA_CONSTRAINT(OP, C) \
2073 sparc_extra_constraint_check(OP, C, 0)
2077 /* Nonzero if X is a hard reg that can be used as an index. */
2078 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2079 /* Nonzero if X is a hard reg that can be used as a base reg. */
2080 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2082 #define EXTRA_CONSTRAINT(OP, C) \
2083 sparc_extra_constraint_check(OP, C, 1)
2087 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2089 #ifdef HAVE_AS_OFFSETABLE_LO10
2090 #define USE_AS_OFFSETABLE_LO10 1
2092 #define USE_AS_OFFSETABLE_LO10 0
2095 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2096 that is a valid memory address for an instruction.
2097 The MODE argument is the machine mode for the MEM expression
2098 that wants to use this address.
2100 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2101 ordinarily. This changes a bit when generating PIC.
2103 If you change this, execute "rm explow.o recog.o reload.o". */
2105 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
2107 #define RTX_OK_FOR_BASE_P(X) \
2108 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2109 || (GET_CODE (X) == SUBREG \
2110 && GET_CODE (SUBREG_REG (X)) == REG \
2111 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2113 #define RTX_OK_FOR_INDEX_P(X) \
2114 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2115 || (GET_CODE (X) == SUBREG \
2116 && GET_CODE (SUBREG_REG (X)) == REG \
2117 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2119 #define RTX_OK_FOR_OFFSET_P(X) \
2120 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2122 #define RTX_OK_FOR_OLO10_P(X) \
2123 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2125 #ifdef REG_OK_STRICT
2126 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2128 if (legitimate_address_p (MODE, X, 1)) \
2132 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2134 if (legitimate_address_p (MODE, X, 0)) \
2139 /* Go to LABEL if ADDR (a legitimate address expression)
2140 has an effect that depends on the machine mode it is used for.
2146 is not equivalent to
2148 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
2150 because [%l7+a+1] is interpreted as the address of (a+1). */
2152 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2154 if (flag_pic == 1) \
2156 if (GET_CODE (ADDR) == PLUS) \
2158 rtx op0 = XEXP (ADDR, 0); \
2159 rtx op1 = XEXP (ADDR, 1); \
2160 if (op0 == pic_offset_table_rtx \
2161 && SYMBOLIC_CONST (op1)) \
2167 /* Try machine-dependent ways of modifying an illegitimate address
2168 to be legitimate. If we find one, return the new, valid address.
2169 This macro is used in only one place: `memory_address' in explow.c.
2171 OLDX is the address as it was before break_out_memory_refs was called.
2172 In some cases it is useful to look at this to decide what needs to be done.
2174 MODE and WIN are passed so that this macro can use
2175 GO_IF_LEGITIMATE_ADDRESS.
2177 It is always safe for this macro to do nothing. It exists to recognize
2178 opportunities to optimize the output. */
2180 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2181 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2183 (X) = legitimize_address (X, OLDX, MODE); \
2184 if (memory_address_p (MODE, X)) \
2188 /* Try a machine-dependent way of reloading an illegitimate address
2189 operand. If we find one, push the reload and jump to WIN. This
2190 macro is used in only one place: `find_reloads_address' in reload.c.
2192 For SPARC 32, we wish to handle addresses by splitting them into
2193 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2194 This cuts the number of extra insns by one.
2196 Do nothing when generating PIC code and the address is a
2197 symbolic operand or requires a scratch register. */
2199 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2201 /* Decompose SImode constants into hi+lo_sum. We do have to \
2202 rerecognize what we produce, so be careful. */ \
2203 if (CONSTANT_P (X) \
2204 && (MODE != TFmode || TARGET_ARCH64) \
2205 && GET_MODE (X) == SImode \
2206 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2208 && (symbolic_operand (X, Pmode) \
2209 || pic_address_needs_scratch (X))) \
2210 && sparc_cmodel <= CM_MEDLOW) \
2212 X = gen_rtx_LO_SUM (GET_MODE (X), \
2213 gen_rtx_HIGH (GET_MODE (X), X), X); \
2214 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2215 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2219 /* ??? 64-bit reloads. */ \
2222 /* Specify the machine mode that this machine uses
2223 for the index in the tablejump instruction. */
2224 /* If we ever implement any of the full models (such as CM_FULLANY),
2225 this has to be DImode in that case */
2226 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2227 #define CASE_VECTOR_MODE \
2228 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2230 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2231 we have to sign extend which slows things down. */
2232 #define CASE_VECTOR_MODE \
2233 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2236 /* Define this as 1 if `char' should by default be signed; else as 0. */
2237 #define DEFAULT_SIGNED_CHAR 1
2239 /* Max number of bytes we can move from memory to memory
2240 in one reasonably fast instruction. */
2243 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2244 move-instruction pairs, we will do a movmem or libcall instead. */
2246 #define MOVE_RATIO (optimize_size ? 3 : 8)
2248 /* Define if operations between registers always perform the operation
2249 on the full register even if a narrower mode is specified. */
2250 #define WORD_REGISTER_OPERATIONS
2252 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2253 will either zero-extend or sign-extend. The value of this macro should
2254 be the code that says which one of the two operations is implicitly
2255 done, UNKNOWN if none. */
2256 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2258 /* Nonzero if access to memory by bytes is slow and undesirable.
2259 For RISC chips, it means that access to memory by bytes is no
2260 better than access by words when possible, so grab a whole word
2261 and maybe make use of that. */
2262 #define SLOW_BYTE_ACCESS 1
2264 /* Define this to be nonzero if shift instructions ignore all but the low-order
2266 #define SHIFT_COUNT_TRUNCATED 1
2268 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2269 is done just by pretending it is already truncated. */
2270 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2272 /* Specify the machine mode used for addresses. */
2273 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2275 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2276 return the mode to be used for the comparison. For floating-point,
2277 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2278 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2279 processing is needed. */
2280 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2282 /* Return nonzero if MODE implies a floating point inequality can be
2283 reversed. For SPARC this is always true because we have a full
2284 compliment of ordered and unordered comparisons, but until generic
2285 code knows how to reverse it correctly we keep the old definition. */
2286 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2288 /* A function address in a call instruction for indexing purposes. */
2289 #define FUNCTION_MODE Pmode
2291 /* Define this if addresses of constant functions
2292 shouldn't be put through pseudo regs where they can be cse'd.
2293 Desirable on machines where ordinary constants are expensive
2294 but a CALL with constant address is cheap. */
2295 #define NO_FUNCTION_CSE
2297 /* alloca should avoid clobbering the old register save area. */
2298 #define SETJMP_VIA_SAVE_AREA
2300 /* The _Q_* comparison libcalls return booleans. */
2301 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2303 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
2304 that the inputs are fully consumed before the output memory is clobbered. */
2306 #define TARGET_BUGGY_QP_LIB 0
2308 /* Assume by default that we do not have the Solaris-specific conversion
2309 routines nor 64-bit integer multiply and divide routines. */
2311 #define SUN_CONVERSION_LIBFUNCS 0
2312 #define DITF_CONVERSION_LIBFUNCS 0
2313 #define SUN_INTEGER_MULTIPLY_64 0
2315 /* Compute extra cost of moving data between one register class
2317 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2318 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2319 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2320 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2321 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2322 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
2323 || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
2325 /* Provide the cost of a branch. For pre-v9 processors we use
2326 a value of 3 to take into account the potential annulling of
2327 the delay slot (which ends up being a bubble in the pipeline slot)
2328 plus a cycle to take into consideration the instruction cache
2331 On v9 and later, which have branch prediction facilities, we set
2332 it to the depth of the pipeline as that is the cost of a
2333 mispredicted branch. */
2335 #define BRANCH_COST \
2336 ((sparc_cpu == PROCESSOR_V9 \
2337 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2339 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2342 #define PREFETCH_BLOCK \
2343 ((sparc_cpu == PROCESSOR_ULTRASPARC \
2344 || sparc_cpu == PROCESSOR_ULTRASPARC3) \
2347 #define SIMULTANEOUS_PREFETCHES \
2348 ((sparc_cpu == PROCESSOR_ULTRASPARC) \
2350 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2353 /* Control the assembler format that we output. */
2355 /* A C string constant describing how to begin a comment in the target
2356 assembler language. The compiler assumes that the comment will end at
2357 the end of the line. */
2359 #define ASM_COMMENT_START "!"
2361 /* Output to assembler file text saying following lines
2362 may contain character constants, extra white space, comments, etc. */
2364 #define ASM_APP_ON ""
2366 /* Output to assembler file text saying following lines
2367 no longer contain unusual constructs. */
2369 #define ASM_APP_OFF ""
2371 /* How to refer to registers in assembler output.
2372 This sequence is indexed by compiler's hard-register-number (see above). */
2374 #define REGISTER_NAMES \
2375 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2376 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2377 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2378 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2379 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2380 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2381 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2382 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2383 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2384 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2385 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2386 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2387 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2389 /* Define additional names for use in asm clobbers and asm declarations. */
2391 #define ADDITIONAL_REGISTER_NAMES \
2392 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2394 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2395 can run past this up to a continuation point. Once we used 1500, but
2396 a single entry in C++ can run more than 500 bytes, due to the length of
2397 mangled symbol names. dbxout.c should really be fixed to do
2398 continuations when they are actually needed instead of trying to
2400 #define DBX_CONTIN_LENGTH 1000
2402 /* This is how to output a command to make the user-level label named NAME
2403 defined for reference from other files. */
2405 /* Globalizing directive for a label. */
2406 #define GLOBAL_ASM_OP "\t.global "
2408 /* The prefix to add to user-visible assembler symbols. */
2410 #define USER_LABEL_PREFIX "_"
2412 /* This is how to store into the string LABEL
2413 the symbol_ref name of an internal numbered label where
2414 PREFIX is the class of label and NUM is the number within the class.
2415 This is suitable for output with `assemble_name'. */
2417 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2418 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2420 /* This is how we hook in and defer the case-vector until the end of
2422 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2423 sparc_defer_case_vector ((LAB),(VEC), 0)
2425 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2426 sparc_defer_case_vector ((LAB),(VEC), 1)
2428 /* This is how to output an element of a case-vector that is absolute. */
2430 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2433 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2434 if (CASE_VECTOR_MODE == SImode) \
2435 fprintf (FILE, "\t.word\t"); \
2437 fprintf (FILE, "\t.xword\t"); \
2438 assemble_name (FILE, label); \
2439 fputc ('\n', FILE); \
2442 /* This is how to output an element of a case-vector that is relative.
2443 (SPARC uses such vectors only when generating PIC.) */
2445 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2448 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2449 if (CASE_VECTOR_MODE == SImode) \
2450 fprintf (FILE, "\t.word\t"); \
2452 fprintf (FILE, "\t.xword\t"); \
2453 assemble_name (FILE, label); \
2454 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2455 fputc ('-', FILE); \
2456 assemble_name (FILE, label); \
2457 fputc ('\n', FILE); \
2460 /* This is what to output before and after case-vector (both
2461 relative and absolute). If .subsection -1 works, we put case-vectors
2462 at the beginning of the current section. */
2464 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2466 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2467 fprintf(FILE, "\t.subsection\t-1\n")
2469 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2470 fprintf(FILE, "\t.previous\n")
2474 /* This is how to output an assembler line
2475 that says to advance the location counter
2476 to a multiple of 2**LOG bytes. */
2478 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2480 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2482 /* This is how to output an assembler line that says to advance
2483 the location counter to a multiple of 2**LOG bytes using the
2484 "nop" instruction as padding. */
2485 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
2487 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG)))
2489 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2490 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2492 /* This says how to output an assembler line
2493 to define a global common symbol. */
2495 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2496 ( fputs ("\t.common ", (FILE)), \
2497 assemble_name ((FILE), (NAME)), \
2498 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
2500 /* This says how to output an assembler line to define a local common
2503 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2504 ( fputs ("\t.reserve ", (FILE)), \
2505 assemble_name ((FILE), (NAME)), \
2506 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
2507 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2509 /* A C statement (sans semicolon) to output to the stdio stream
2510 FILE the assembler definition of uninitialized global DECL named
2511 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2512 Try to use asm_output_aligned_bss to implement this macro. */
2514 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2516 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2519 #define IDENT_ASM_OP "\t.ident\t"
2521 /* Output #ident as a .ident. */
2523 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2524 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2526 /* Prettify the assembly. */
2528 extern int sparc_indent_opcode;
2530 #define ASM_OUTPUT_OPCODE(FILE, PTR) \
2532 if (sparc_indent_opcode) \
2535 sparc_indent_opcode = 0; \
2539 /* Emit a dtp-relative reference to a TLS variable. */
2542 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
2543 sparc_output_dwarf_dtprel (FILE, SIZE, X)
2546 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2547 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \
2548 || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&')
2550 /* Print operand X (an rtx) in assembler syntax to file FILE.
2551 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2552 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2554 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2556 /* Print a memory address as an operand to reference that memory location. */
2558 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2559 { register rtx base, index = 0; \
2561 register rtx addr = ADDR; \
2562 if (GET_CODE (addr) == REG) \
2563 fputs (reg_names[REGNO (addr)], FILE); \
2564 else if (GET_CODE (addr) == PLUS) \
2566 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2567 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2568 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2569 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2571 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2572 if (GET_CODE (base) == LO_SUM) \
2574 if (! USE_AS_OFFSETABLE_LO10 \
2576 || TARGET_CM_MEDMID) \
2578 output_operand (XEXP (base, 0), 0); \
2579 fputs ("+%lo(", FILE); \
2580 output_address (XEXP (base, 1)); \
2581 fprintf (FILE, ")+%d", offset); \
2585 fputs (reg_names[REGNO (base)], FILE); \
2587 fprintf (FILE, "%+d", offset); \
2588 else if (GET_CODE (index) == REG) \
2589 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2590 else if (GET_CODE (index) == SYMBOL_REF \
2591 || GET_CODE (index) == CONST) \
2592 fputc ('+', FILE), output_addr_const (FILE, index); \
2596 else if (GET_CODE (addr) == MINUS \
2597 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2599 output_addr_const (FILE, XEXP (addr, 0)); \
2600 fputs ("-(", FILE); \
2601 output_addr_const (FILE, XEXP (addr, 1)); \
2602 fputs ("-.)", FILE); \
2604 else if (GET_CODE (addr) == LO_SUM) \
2606 output_operand (XEXP (addr, 0), 0); \
2607 if (TARGET_CM_MEDMID) \
2608 fputs ("+%l44(", FILE); \
2610 fputs ("+%lo(", FILE); \
2611 output_address (XEXP (addr, 1)); \
2612 fputc (')', FILE); \
2614 else if (flag_pic && GET_CODE (addr) == CONST \
2615 && GET_CODE (XEXP (addr, 0)) == MINUS \
2616 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2617 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2618 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2620 addr = XEXP (addr, 0); \
2621 output_addr_const (FILE, XEXP (addr, 0)); \
2622 /* Group the args of the second CONST in parenthesis. */ \
2623 fputs ("-(", FILE); \
2624 /* Skip past the second CONST--it does nothing for us. */\
2625 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2626 /* Close the parenthesis. */ \
2627 fputc (')', FILE); \
2631 output_addr_const (FILE, addr); \
2636 #define TARGET_TLS 1
2638 #define TARGET_TLS 0
2640 #define TARGET_SUN_TLS TARGET_TLS
2641 #define TARGET_GNU_TLS 0
2643 /* Define the codes that are matched by predicates in sparc.c. */
2645 #define PREDICATE_CODES \
2646 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2647 {"const1_operand", {CONST_INT}}, \
2648 {"fp_zero_operand", {CONST_DOUBLE}}, \
2649 {"fp_register_operand", {SUBREG, REG}}, \
2650 {"intreg_operand", {SUBREG, REG}}, \
2651 {"fcc_reg_operand", {REG}}, \
2652 {"fcc0_reg_operand", {REG}}, \
2653 {"icc_or_fcc_reg_operand", {REG}}, \
2654 {"call_operand", {MEM}}, \
2655 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
2656 SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
2657 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2658 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2659 {"label_ref_operand", {LABEL_REF}}, \
2660 {"sp64_medium_pic_operand", {CONST}}, \
2661 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
2662 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
2663 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
2664 {"splittable_symbolic_memory_operand", {MEM}}, \
2665 {"splittable_immediate_memory_operand", {MEM}}, \
2666 {"eq_or_neq", {EQ, NE}}, \
2667 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
2668 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2669 {"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2670 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
2671 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
2672 {"cc_arithop", {AND, IOR, XOR}}, \
2673 {"cc_arithopn", {AND, IOR}}, \
2674 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2675 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
2676 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2677 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
2678 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2679 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2680 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2681 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2682 {"small_int", {CONST_INT}}, \
2683 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
2684 {"uns_small_int", {CONST_INT}}, \
2685 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
2686 {"clobbered_register", {REG}}, \
2687 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
2688 {"compare_operand", {SUBREG, REG, ZERO_EXTRACT}}, \
2689 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
2690 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, \
2691 {"tgd_symbolic_operand", {SYMBOL_REF}}, \
2692 {"tld_symbolic_operand", {SYMBOL_REF}}, \
2693 {"tie_symbolic_operand", {SYMBOL_REF}}, \
2694 {"tle_symbolic_operand", {SYMBOL_REF}},
2696 /* The number of Pmode words for the setjmp buffer. */
2697 #define JMP_BUF_SIZE 12