1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Michael Tiemann (tiemann@cygnus.com).
6 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING3. If not see
23 <http://www.gnu.org/licenses/>. */
25 #include "config/vxworks-dummy.h"
27 /* Note that some other tm.h files include this one and then override
28 whatever definitions are necessary. */
30 /* Define the specific costs for a given cpu */
32 struct processor_costs {
36 /* Integer signed load */
39 /* Integer zeroed load */
45 /* fmov, fneg, fabs */
49 const int float_plusminus;
55 const int float_cmove;
61 const int float_div_sf;
64 const int float_div_df;
67 const int float_sqrt_sf;
70 const int float_sqrt_df;
78 /* integer multiply cost for each bit set past the most
79 significant 3, so the formula for multiply cost becomes:
82 highest_bit = highest_clear_bit(rs1);
84 highest_bit = highest_set_bit(rs1);
87 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
89 A value of zero indicates that the multiply costs is fixed,
91 const int int_mul_bit_factor;
102 /* penalty for shifts, due to scheduling rules etc. */
103 const int shift_penalty;
106 extern const struct processor_costs *sparc_costs;
108 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of
109 Solaris only; otherwise just define __sparc__. Sadly the headers
110 are such a mess there is no Solaris-specific header. */
111 #define TARGET_CPU_CPP_BUILTINS() \
114 builtin_define_std ("sparc"); \
117 builtin_assert ("cpu=sparc64"); \
118 builtin_assert ("machine=sparc64"); \
122 builtin_assert ("cpu=sparc"); \
123 builtin_assert ("machine=sparc"); \
128 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
129 /* #define SPARC_BI_ARCH */
131 /* Macro used later in this file to determine default architecture. */
132 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
134 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
135 architectures to compile for. We allow targets to choose compile time or
136 runtime selection. */
138 #if defined(__sparcv9) || defined(__arch64__)
139 #define TARGET_ARCH32 0
141 #define TARGET_ARCH32 1
145 #define TARGET_ARCH32 (! TARGET_64BIT)
147 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
148 #endif /* SPARC_BI_ARCH */
149 #endif /* IN_LIBGCC2 */
150 #define TARGET_ARCH64 (! TARGET_ARCH32)
152 /* Code model selection in 64-bit environment.
154 The machine mode used for addresses is 32-bit wide:
156 TARGET_CM_32: 32-bit address space.
157 It is the code model used when generating 32-bit code.
159 The machine mode used for addresses is 64-bit wide:
161 TARGET_CM_MEDLOW: 32-bit address space.
162 The executable must be in the low 32 bits of memory.
163 This avoids generating %uhi and %ulo terms. Programs
164 can be statically or dynamically linked.
166 TARGET_CM_MEDMID: 44-bit address space.
167 The executable must be in the low 44 bits of memory,
168 and the %[hml]44 terms are used. The text and data
169 segments have a maximum size of 2GB (31-bit span).
170 The maximum offset from any instruction to the label
171 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
173 TARGET_CM_MEDANY: 64-bit address space.
174 The text and data segments have a maximum size of 2GB
175 (31-bit span) and may be located anywhere in memory.
176 The maximum offset from any instruction to the label
177 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
179 TARGET_CM_EMBMEDANY: 64-bit address space.
180 The text and data segments have a maximum size of 2GB
181 (31-bit span) and may be located anywhere in memory.
182 The global register %g4 contains the start address of
183 the data segment. Programs are statically linked and
184 PIC is not supported.
186 Different code models are not supported in 32-bit environment. */
197 extern enum cmodel sparc_cmodel;
199 /* V9 code model selection. */
200 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
201 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
202 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
203 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
205 #define SPARC_DEFAULT_CMODEL CM_32
207 /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO)
208 which requires the following macro to be true if enabled. Prior to V9,
209 there are no instructions to even talk about memory synchronization.
210 Note that the UltraSPARC III processors don't implement RMO, unlike the
211 UltraSPARC II processors. Niagara and Niagara-2 do not implement RMO
214 Default to false; for example, Solaris never enables RMO, only ever uses
215 total memory ordering (TMO). */
216 #define SPARC_RELAXED_ORDERING false
218 /* Do not use the .note.GNU-stack convention by default. */
219 #define NEED_INDICATE_EXEC_STACK 0
221 /* This is call-clobbered in the normal ABI, but is reserved in the
222 home grown (aka upward compatible) embedded ABI. */
223 #define EMBMEDANY_BASE_REG "%g4"
225 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
226 and specified by the user via --with-cpu=foo.
227 This specifies the cpu implementation, not the architecture size. */
228 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
230 #define TARGET_CPU_sparc 0
231 #define TARGET_CPU_v7 0 /* alias for previous */
232 #define TARGET_CPU_sparclet 1
233 #define TARGET_CPU_sparclite 2
234 #define TARGET_CPU_v8 3 /* generic v8 implementation */
235 #define TARGET_CPU_supersparc 4
236 #define TARGET_CPU_hypersparc 5
237 #define TARGET_CPU_sparc86x 6
238 #define TARGET_CPU_sparclite86x 6
239 #define TARGET_CPU_v9 7 /* generic v9 implementation */
240 #define TARGET_CPU_sparcv9 7 /* alias */
241 #define TARGET_CPU_sparc64 7 /* alias */
242 #define TARGET_CPU_ultrasparc 8
243 #define TARGET_CPU_ultrasparc3 9
244 #define TARGET_CPU_niagara 10
245 #define TARGET_CPU_niagara2 11
247 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
248 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
249 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
250 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \
251 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
253 #define CPP_CPU32_DEFAULT_SPEC ""
254 #define ASM_CPU32_DEFAULT_SPEC ""
256 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
257 /* ??? What does Sun's CC pass? */
258 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
259 /* ??? It's not clear how other assemblers will handle this, so by default
260 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
261 is handled in sol2.h. */
262 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
264 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
265 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
266 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
268 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
269 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
270 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
272 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
273 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
274 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
276 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
277 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
278 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
283 #define CPP_CPU64_DEFAULT_SPEC ""
284 #define ASM_CPU64_DEFAULT_SPEC ""
286 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
287 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
288 #define CPP_CPU32_DEFAULT_SPEC ""
289 #define ASM_CPU32_DEFAULT_SPEC ""
292 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
293 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
294 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
297 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
298 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
299 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
302 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
303 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
304 #define ASM_CPU32_DEFAULT_SPEC ""
307 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
308 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
309 #define ASM_CPU32_DEFAULT_SPEC ""
312 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
313 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
314 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
319 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
320 #error Unrecognized value in TARGET_CPU_DEFAULT.
325 #define CPP_CPU_DEFAULT_SPEC \
326 (DEFAULT_ARCH32_P ? "\
327 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
328 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
330 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
331 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
333 #define ASM_CPU_DEFAULT_SPEC \
334 (DEFAULT_ARCH32_P ? "\
335 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
336 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
338 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
339 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
342 #else /* !SPARC_BI_ARCH */
344 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
345 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
347 #endif /* !SPARC_BI_ARCH */
349 /* Define macros to distinguish architectures. */
351 /* Common CPP definitions used by CPP_SPEC amongst the various targets
352 for handling -mcpu=xxx switches. */
353 #define CPP_CPU_SPEC "\
354 %{msoft-float:-D_SOFT_FLOAT} \
356 %{msparclite:-D__sparclite__} \
357 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
358 %{mv8:-D__sparc_v8__} \
359 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
360 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
361 %{mcpu=sparclite:-D__sparclite__} \
362 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
363 %{mcpu=v8:-D__sparc_v8__} \
364 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
365 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
366 %{mcpu=sparclite86x:-D__sparclite86x__} \
367 %{mcpu=v9:-D__sparc_v9__} \
368 %{mcpu=ultrasparc:-D__sparc_v9__} \
369 %{mcpu=ultrasparc3:-D__sparc_v9__} \
370 %{mcpu=niagara:-D__sparc_v9__} \
371 %{mcpu=niagara2:-D__sparc_v9__} \
372 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
374 #define CPP_ARCH32_SPEC ""
375 #define CPP_ARCH64_SPEC "-D__arch64__"
377 #define CPP_ARCH_DEFAULT_SPEC \
378 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
380 #define CPP_ARCH_SPEC "\
381 %{m32:%(cpp_arch32)} \
382 %{m64:%(cpp_arch64)} \
383 %{!m32:%{!m64:%(cpp_arch_default)}} \
386 /* Macros to distinguish endianness. */
387 #define CPP_ENDIAN_SPEC "\
388 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
389 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
391 /* Macros to distinguish the particular subtarget. */
392 #define CPP_SUBTARGET_SPEC ""
394 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
396 /* Prevent error on `-sun4' and `-target sun4' options. */
397 /* This used to translate -dalign to -malign, but that is no good
398 because it can't turn off the usual meaning of making debugging dumps. */
399 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
400 ??? Delete support for -m<cpu> for 2.9. */
403 %{sun4:} %{target:} \
404 %{mcypress:-mcpu=cypress} \
405 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
406 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
409 /* Override in target specific files. */
410 #define ASM_CPU_SPEC "\
411 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
412 %{msparclite:-Asparclite} \
413 %{mf930:-Asparclite} %{mf934:-Asparclite} \
414 %{mcpu=sparclite:-Asparclite} \
415 %{mcpu=sparclite86x:-Asparclite} \
416 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
417 %{mv8plus:-Av8plus} \
419 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
420 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
421 %{mcpu=niagara:%{!mv8plus:-Av9b}} \
422 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \
423 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
426 /* Word size selection, among other things.
427 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
429 #define ASM_ARCH32_SPEC "-32"
430 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
431 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
433 #define ASM_ARCH64_SPEC "-64"
435 #define ASM_ARCH_DEFAULT_SPEC \
436 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
438 #define ASM_ARCH_SPEC "\
439 %{m32:%(asm_arch32)} \
440 %{m64:%(asm_arch64)} \
441 %{!m32:%{!m64:%(asm_arch_default)}} \
444 #ifdef HAVE_AS_RELAX_OPTION
445 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
447 #define ASM_RELAX_SPEC ""
450 /* Special flags to the Sun-4 assembler when using pipe for input. */
453 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \
454 %(asm_cpu) %(asm_relax)"
456 #define AS_NEEDS_DASH_FOR_PIPED_INPUT
458 /* This macro defines names of additional specifications to put in the specs
459 that can be used in various specifications like CC1_SPEC. Its definition
460 is an initializer with a subgrouping for each command option.
462 Each subgrouping contains a string constant, that defines the
463 specification name, and a string constant that used by the GCC driver
466 Do not define this macro if it does not need to do anything. */
468 #define EXTRA_SPECS \
469 { "cpp_cpu", CPP_CPU_SPEC }, \
470 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
471 { "cpp_arch32", CPP_ARCH32_SPEC }, \
472 { "cpp_arch64", CPP_ARCH64_SPEC }, \
473 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
474 { "cpp_arch", CPP_ARCH_SPEC }, \
475 { "cpp_endian", CPP_ENDIAN_SPEC }, \
476 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
477 { "asm_cpu", ASM_CPU_SPEC }, \
478 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
479 { "asm_arch32", ASM_ARCH32_SPEC }, \
480 { "asm_arch64", ASM_ARCH64_SPEC }, \
481 { "asm_relax", ASM_RELAX_SPEC }, \
482 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
483 { "asm_arch", ASM_ARCH_SPEC }, \
484 SUBTARGET_EXTRA_SPECS
486 #define SUBTARGET_EXTRA_SPECS
488 /* Because libgcc can generate references back to libc (via .umul etc.) we have
489 to list libc again after the second libgcc. */
490 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
493 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
494 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
496 /* ??? This should be 32 bits for v9 but what can we do? */
497 #define WCHAR_TYPE "short unsigned int"
498 #define WCHAR_TYPE_SIZE 16
500 /* Show we can debug even without a frame pointer. */
501 #define CAN_DEBUG_WITHOUT_FP
503 /* Option handling. */
505 #define OVERRIDE_OPTIONS sparc_override_options ()
507 /* Mask of all CPU selection flags. */
509 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
511 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
512 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
513 to get high 32 bits. False in V8+ or V9 because multiply stores
514 a 64-bit result in a register. */
516 #define TARGET_HARD_MUL32 \
517 ((TARGET_V8 || TARGET_SPARCLITE \
518 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
519 && ! TARGET_V8PLUS && TARGET_ARCH32)
521 #define TARGET_HARD_MUL \
522 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
523 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
525 /* MASK_APP_REGS must always be the default because that's what
526 FIXED_REGISTERS is set to and -ffixed- is processed before
527 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
528 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
531 These must match the values for the cpu attribute in sparc.md. */
532 enum processor_type {
536 PROCESSOR_SUPERSPARC,
540 PROCESSOR_HYPERSPARC,
541 PROCESSOR_SPARCLITE86X,
545 PROCESSOR_ULTRASPARC,
546 PROCESSOR_ULTRASPARC3,
551 /* This is set from -m{cpu,tune}=xxx. */
552 extern enum processor_type sparc_cpu;
554 /* Recast the cpu class to be the cpu attribute.
555 Every file includes us, but not every file includes insn-attr.h. */
556 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
558 /* Support for a compile-time default CPU, et cetera. The rules are:
559 --with-cpu is ignored if -mcpu is specified.
560 --with-tune is ignored if -mtune is specified.
561 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
563 #define OPTION_DEFAULT_SPECS \
564 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
565 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
566 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }
568 /* sparc_select[0] is reserved for the default cpu. */
569 struct sparc_cpu_select
572 const char *const name;
573 const int set_tune_p;
574 const int set_arch_p;
577 extern struct sparc_cpu_select sparc_select[];
579 /* target machine storage layout */
581 /* Define this if most significant bit is lowest numbered
582 in instructions that operate on numbered bit-fields. */
583 #define BITS_BIG_ENDIAN 1
585 /* Define this if most significant byte of a word is the lowest numbered. */
586 #define BYTES_BIG_ENDIAN 1
588 /* Define this if most significant word of a multiword number is the lowest
590 #define WORDS_BIG_ENDIAN 1
592 /* Define this to set the endianness to use in libgcc2.c, which can
593 not depend on target_flags. */
594 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
595 #define LIBGCC2_WORDS_BIG_ENDIAN 0
597 #define LIBGCC2_WORDS_BIG_ENDIAN 1
600 #define MAX_BITS_PER_WORD 64
602 /* Width of a word, in units (bytes). */
603 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
605 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
607 #define MIN_UNITS_PER_WORD 4
610 #define UNITS_PER_SIMD_WORD(MODE) (TARGET_VIS ? 8 : UNITS_PER_WORD)
612 /* Now define the sizes of the C data types. */
614 #define SHORT_TYPE_SIZE 16
615 #define INT_TYPE_SIZE 32
616 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
617 #define LONG_LONG_TYPE_SIZE 64
618 #define FLOAT_TYPE_SIZE 32
619 #define DOUBLE_TYPE_SIZE 64
621 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
622 SPARC ABI says that it is 128-bit wide. */
623 /* #define LONG_DOUBLE_TYPE_SIZE 128 */
625 /* The widest floating-point format really supported by the hardware. */
626 #define WIDEST_HARDWARE_FP_SIZE 64
628 /* Width in bits of a pointer. This is the size of ptr_mode. */
629 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
631 /* This is the machine mode used for addresses. */
632 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
634 /* If we have to extend pointers (only when TARGET_ARCH64 and not
635 TARGET_PTR64), we want to do it unsigned. This macro does nothing
636 if ptr_mode and Pmode are the same. */
637 #define POINTERS_EXTEND_UNSIGNED 1
639 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
640 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
642 /* Boundary (in *bits*) on which stack pointer should be aligned. */
643 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
644 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */
645 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
646 /* Temporary hack until the FIXME above is fixed. */
647 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
649 /* ALIGN FRAMES on double word boundaries */
651 #define SPARC_STACK_ALIGN(LOC) \
652 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
654 /* Allocation boundary (in *bits*) for the code of a function. */
655 #define FUNCTION_BOUNDARY 32
657 /* Alignment of field after `int : 0' in a structure. */
658 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
660 /* Every structure's size must be a multiple of this. */
661 #define STRUCTURE_SIZE_BOUNDARY 8
663 /* A bit-field declared as `int' forces `int' alignment for the struct. */
664 #define PCC_BITFIELD_TYPE_MATTERS 1
666 /* No data type wants to be aligned rounder than this. */
667 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
669 /* The best alignment to use in cases where we have a choice. */
670 #define FASTEST_ALIGNMENT 64
672 /* Define this macro as an expression for the alignment of a structure
673 (given by STRUCT as a tree node) if the alignment computed in the
674 usual way is COMPUTED and the alignment explicitly specified was
677 The default is to use SPECIFIED if it is larger; otherwise, use
678 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
679 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
680 (TARGET_FASTER_STRUCTS ? \
681 ((TREE_CODE (STRUCT) == RECORD_TYPE \
682 || TREE_CODE (STRUCT) == UNION_TYPE \
683 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
684 && TYPE_FIELDS (STRUCT) != 0 \
685 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
686 : MAX ((COMPUTED), (SPECIFIED))) \
687 : MAX ((COMPUTED), (SPECIFIED)))
689 /* Make strings word-aligned so strcpy from constants will be faster. */
690 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
691 ((TREE_CODE (EXP) == STRING_CST \
692 && (ALIGN) < FASTEST_ALIGNMENT) \
693 ? FASTEST_ALIGNMENT : (ALIGN))
695 /* Make arrays of chars word-aligned for the same reasons. */
696 #define DATA_ALIGNMENT(TYPE, ALIGN) \
697 (TREE_CODE (TYPE) == ARRAY_TYPE \
698 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
699 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
701 /* Make local arrays of chars word-aligned for the same reasons. */
702 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN)
704 /* Set this nonzero if move instructions will actually fail to work
705 when given unaligned data. */
706 #define STRICT_ALIGNMENT 1
708 /* Things that must be doubleword aligned cannot go in the text section,
709 because the linker fails to align the text section enough!
710 Put them in the data section. This macro is only used in this file. */
711 #define MAX_TEXT_ALIGN 32
713 /* Standard register usage. */
715 /* Number of actual hardware registers.
716 The hardware registers are assigned numbers for the compiler
717 from 0 to just below FIRST_PSEUDO_REGISTER.
718 All registers that the compiler knows about must be given numbers,
719 even those that are not normally considered general registers.
721 SPARC has 32 integer registers and 32 floating point registers.
722 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not
723 accessible. We still account for them to simplify register computations
724 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
726 Register 100 is used as the integer condition code register.
727 Register 101 is used as the soft frame pointer register. */
729 #define FIRST_PSEUDO_REGISTER 102
731 #define SPARC_FIRST_FP_REG 32
732 /* Additional V9 fp regs. */
733 #define SPARC_FIRST_V9_FP_REG 64
734 #define SPARC_LAST_V9_FP_REG 95
735 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
736 #define SPARC_FIRST_V9_FCC_REG 96
737 #define SPARC_LAST_V9_FCC_REG 99
739 #define SPARC_FCC_REG 96
740 /* Integer CC reg. We don't distinguish %icc from %xcc. */
741 #define SPARC_ICC_REG 100
743 /* Nonzero if REGNO is an fp reg. */
744 #define SPARC_FP_REG_P(REGNO) \
745 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
747 /* Argument passing regs. */
748 #define SPARC_OUTGOING_INT_ARG_FIRST 8
749 #define SPARC_INCOMING_INT_ARG_FIRST 24
750 #define SPARC_FP_ARG_FIRST 32
752 /* 1 for registers that have pervasive standard uses
753 and are not available for the register allocator.
756 g1 is free to use as temporary.
757 g2-g4 are reserved for applications. Gcc normally uses them as
758 temporaries, but this can be disabled via the -mno-app-regs option.
759 g5 through g7 are reserved for the operating system.
762 g1,g5 are free to use as temporaries, and are free to use between calls
763 if the call is to an external function via the PLT.
764 g4 is free to use as a temporary in the non-embedded case.
765 g4 is reserved in the embedded case.
766 g2-g3 are reserved for applications. Gcc normally uses them as
767 temporaries, but this can be disabled via the -mno-app-regs option.
768 g6-g7 are reserved for the operating system (or application in
770 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
771 currently be a fixed register until this pattern is rewritten.
772 Register 1 is also used when restoring call-preserved registers in large
775 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
776 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
779 #define FIXED_REGISTERS \
780 {1, 0, 2, 2, 2, 2, 1, 1, \
781 0, 0, 0, 0, 0, 0, 1, 0, \
782 0, 0, 0, 0, 0, 0, 0, 0, \
783 0, 0, 0, 0, 0, 0, 1, 1, \
785 0, 0, 0, 0, 0, 0, 0, 0, \
786 0, 0, 0, 0, 0, 0, 0, 0, \
787 0, 0, 0, 0, 0, 0, 0, 0, \
788 0, 0, 0, 0, 0, 0, 0, 0, \
790 0, 0, 0, 0, 0, 0, 0, 0, \
791 0, 0, 0, 0, 0, 0, 0, 0, \
792 0, 0, 0, 0, 0, 0, 0, 0, \
793 0, 0, 0, 0, 0, 0, 0, 0, \
797 /* 1 for registers not available across function calls.
798 These must include the FIXED_REGISTERS and also any
799 registers that can be used without being saved.
800 The latter must include the registers where values are returned
801 and the register where structure-value addresses are passed.
802 Aside from that, you can include as many other registers as you like. */
804 #define CALL_USED_REGISTERS \
805 {1, 1, 1, 1, 1, 1, 1, 1, \
806 1, 1, 1, 1, 1, 1, 1, 1, \
807 0, 0, 0, 0, 0, 0, 0, 0, \
808 0, 0, 0, 0, 0, 0, 1, 1, \
810 1, 1, 1, 1, 1, 1, 1, 1, \
811 1, 1, 1, 1, 1, 1, 1, 1, \
812 1, 1, 1, 1, 1, 1, 1, 1, \
813 1, 1, 1, 1, 1, 1, 1, 1, \
815 1, 1, 1, 1, 1, 1, 1, 1, \
816 1, 1, 1, 1, 1, 1, 1, 1, \
817 1, 1, 1, 1, 1, 1, 1, 1, \
818 1, 1, 1, 1, 1, 1, 1, 1, \
822 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
823 they won't be allocated. */
825 #define CONDITIONAL_REGISTER_USAGE \
828 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
830 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
831 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
833 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
834 /* then honor it. */ \
835 if (TARGET_ARCH32 && fixed_regs[5]) \
837 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
842 for (regno = SPARC_FIRST_V9_FP_REG; \
843 regno <= SPARC_LAST_V9_FP_REG; \
845 fixed_regs[regno] = 1; \
846 /* %fcc0 is used by v8 and v9. */ \
847 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
848 regno <= SPARC_LAST_V9_FCC_REG; \
850 fixed_regs[regno] = 1; \
855 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
856 fixed_regs[regno] = 1; \
858 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
859 /* then honor it. Likewise with g3 and g4. */ \
860 if (fixed_regs[2] == 2) \
861 fixed_regs[2] = ! TARGET_APP_REGS; \
862 if (fixed_regs[3] == 2) \
863 fixed_regs[3] = ! TARGET_APP_REGS; \
864 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
865 fixed_regs[4] = ! TARGET_APP_REGS; \
866 else if (TARGET_CM_EMBMEDANY) \
868 else if (fixed_regs[4] == 2) \
873 /* Return number of consecutive hard regs needed starting at reg REGNO
874 to hold something of mode MODE.
875 This is ordinarily the length in words of a value of mode MODE
876 but can be less for certain modes in special long registers.
878 On SPARC, ordinary registers hold 32 bits worth;
879 this means both integer and floating point registers.
880 On v9, integer regs hold 64 bits worth; floating point regs hold
881 32 bits worth (this includes the new fp regs as even the odd ones are
882 included in the hard register count). */
884 #define HARD_REGNO_NREGS(REGNO, MODE) \
886 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
887 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
888 : (GET_MODE_SIZE (MODE) + 3) / 4) \
889 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
891 /* Due to the ARCH64 discrepancy above we must override this next
893 #define REGMODE_NATURAL_SIZE(MODE) \
894 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
896 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
897 See sparc.c for how we initialize this. */
898 extern const int *hard_regno_mode_classes;
899 extern int sparc_mode_class[];
901 /* ??? Because of the funny way we pass parameters we should allow certain
902 ??? types of float/complex values to be in integer registers during
903 ??? RTL generation. This only matters on arch32. */
904 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
905 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
907 /* Value is 1 if it is OK to rename a hard register FROM to another hard
908 register TO. We cannot rename %g1 as it may be used before the save
909 register window instruction in the prologue. */
910 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1)
912 /* Value is 1 if it is a good idea to tie two pseudo registers
913 when one has mode MODE1 and one has mode MODE2.
914 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
915 for any hard reg, then this must be 0 for correct output.
917 For V9: SFmode can't be combined with other float modes, because they can't
918 be allocated to the %d registers. Also, DFmode won't fit in odd %f
919 registers, but SFmode will. */
920 #define MODES_TIEABLE_P(MODE1, MODE2) \
921 ((MODE1) == (MODE2) \
922 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
924 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
925 || (MODE1 != SFmode && MODE2 != SFmode)))))
927 /* Specify the registers used for certain standard purposes.
928 The values of these macros are register numbers. */
930 /* Register to use for pushing function arguments. */
931 #define STACK_POINTER_REGNUM 14
933 /* The stack bias (amount by which the hardware register is offset by). */
934 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
936 /* Actual top-of-stack address is 92/176 greater than the contents of the
937 stack pointer register for !v9/v9. That is:
938 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
939 address, and 6*4 bytes for the 6 register parameters.
940 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
942 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
944 /* Base register for access to local variables of the function. */
945 #define HARD_FRAME_POINTER_REGNUM 30
947 /* The soft frame pointer does not have the stack bias applied. */
948 #define FRAME_POINTER_REGNUM 101
950 /* Given the stack bias, the stack pointer isn't actually aligned. */
951 #define INIT_EXPANDERS \
953 if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \
955 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
956 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
960 /* Base register for access to arguments of the function. */
961 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
963 /* Register in which static-chain is passed to a function. This must
964 not be a register used by the prologue. */
965 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
967 /* Register which holds offset table for position-independent
970 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
972 /* Pick a default value we can notice from override_options:
975 Originally it was -1, but later on the container of options changed to
976 unsigned byte, so we decided to pick 127 as default value, which does
977 reflect an undefined default value in case of 0/1. */
979 #define DEFAULT_PCC_STRUCT_RETURN 127
981 /* Functions which return large structures get the address
982 to place the wanted value at offset 64 from the frame.
983 Must reserve 64 bytes for the in and local registers.
984 v9: Functions which return large structures get the address to place the
985 wanted value from an invisible first argument. */
986 #define STRUCT_VALUE_OFFSET 64
988 /* Define the classes of registers for register constraints in the
989 machine description. Also define ranges of constants.
991 One of the classes must always be named ALL_REGS and include all hard regs.
992 If there is more than one class, another class must be named NO_REGS
993 and contain no registers.
995 The name GENERAL_REGS must be the name of a class (or an alias for
996 another name such as ALL_REGS). This is the class of registers
997 that is allowed by "g" or "r" in a register constraint.
998 Also, registers outside this class are allocated only when
999 instructions express preferences for them.
1001 The classes must be numbered in nondecreasing order; that is,
1002 a larger-numbered class must never be contained completely
1003 in a smaller-numbered class.
1005 For any two classes, it is very desirable that there be another
1006 class that represents their union. */
1008 /* The SPARC has various kinds of registers: general, floating point,
1009 and condition codes [well, it has others as well, but none that we
1010 care directly about].
1012 For v9 we must distinguish between the upper and lower floating point
1013 registers because the upper ones can't hold SFmode values.
1014 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1015 satisfying a group need for a class will also satisfy a single need for
1016 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1019 It is important that one class contains all the general and all the standard
1020 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1021 because reg_class_record() will bias the selection in favor of fp regs,
1022 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1023 because FP_REGS > GENERAL_REGS.
1025 It is also important that one class contain all the general and all
1026 the fp regs. Otherwise when spilling a DFmode reg, it may be from
1027 EXTRA_FP_REGS but find_reloads() may use class
1028 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die
1029 because the compiler thinks it doesn't have a spill reg when in
1032 v9 also has 4 floating point condition code registers. Since we don't
1033 have a class that is the union of FPCC_REGS with either of the others,
1034 it is important that it appear first. Otherwise the compiler will die
1035 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1038 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1039 may try to use it to hold an SImode value. See register_operand.
1040 ??? Should %fcc[0123] be handled similarly?
1043 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1044 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1045 ALL_REGS, LIM_REG_CLASSES };
1047 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1049 /* Give names of register classes as strings for dump file. */
1051 #define REG_CLASS_NAMES \
1052 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1053 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1056 /* Define which registers fit in which classes.
1057 This is an initializer for a vector of HARD_REG_SET
1058 of length N_REG_CLASSES. */
1060 #define REG_CLASS_CONTENTS \
1061 {{0, 0, 0, 0}, /* NO_REGS */ \
1062 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1063 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1064 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1065 {0, -1, 0, 0}, /* FP_REGS */ \
1066 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1067 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1068 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1069 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1071 /* The same information, inverted:
1072 Return the class number of the smallest class containing
1073 reg number REGNO. This could be a conditional expression
1074 or could index an array. */
1076 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1078 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1080 /* The following macro defines cover classes for Integrated Register
1081 Allocator. Cover classes is a set of non-intersected register
1082 classes covering all hard registers used for register allocation
1083 purpose. Any move between two registers of a cover class should be
1084 cheaper than load or store of the registers. The macro value is
1085 array of register classes with LIM_REG_CLASSES used as the end
1088 #define IRA_COVER_CLASSES \
1090 GENERAL_REGS, EXTRA_FP_REGS, FPCC_REGS, LIM_REG_CLASSES \
1093 /* Defines invalid mode changes. Borrowed from pa64-regs.h.
1095 SImode loads to floating-point registers are not zero-extended.
1096 The definition for LOAD_EXTEND_OP specifies that integer loads
1097 narrower than BITS_PER_WORD will be zero-extended. As a result,
1098 we inhibit changes from SImode unless they are to a mode that is
1099 identical in size. */
1101 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1103 && (FROM) == SImode \
1104 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1105 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
1107 /* This is the order in which to allocate registers normally.
1109 We put %f0-%f7 last among the float registers, so as to make it more
1110 likely that a pseudo-register which dies in the float return register
1111 area will get allocated to the float return register, thus saving a move
1112 instruction at the end of the function.
1114 Similarly for integer return value registers.
1116 We know in this case that we will not end up with a leaf function.
1118 The register allocator is given the global and out registers first
1119 because these registers are call clobbered and thus less useful to
1120 global register allocation.
1122 Next we list the local and in registers. They are not call clobbered
1123 and thus very useful for global register allocation. We list the input
1124 registers before the locals so that it is more likely the incoming
1125 arguments received in those registers can just stay there and not be
1128 #define REG_ALLOC_ORDER \
1129 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1130 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1132 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1133 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
1134 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1135 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1136 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1137 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1138 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1139 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1140 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1141 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1142 96, 97, 98, 99, /* %fcc0-3 */ \
1143 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */
1145 /* This is the order in which to allocate registers for
1146 leaf functions. If all registers can fit in the global and
1147 output registers, then we have the possibility of having a leaf
1150 The macro actually mentioned the input registers first,
1151 because they get renumbered into the output registers once
1152 we know really do have a leaf function.
1154 To be more precise, this register allocation order is used
1155 when %o7 is found to not be clobbered right before register
1156 allocation. Normally, the reason %o7 would be clobbered is
1157 due to a call which could not be transformed into a sibling
1160 As a consequence, it is possible to use the leaf register
1161 allocation order and not end up with a leaf function. We will
1162 not get suboptimal register allocation in that case because by
1163 definition of being potentially leaf, there were no function
1164 calls. Therefore, allocation order within the local register
1165 window is not critical like it is when we do have function calls. */
1167 #define REG_LEAF_ALLOC_ORDER \
1168 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1169 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1171 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1172 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1173 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1174 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1175 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1176 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1177 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1178 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1179 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1180 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1181 96, 97, 98, 99, /* %fcc0-3 */ \
1182 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
1184 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1186 extern char sparc_leaf_regs[];
1187 #define LEAF_REGISTERS sparc_leaf_regs
1189 extern char leaf_reg_remap[];
1190 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1192 /* The class value for index registers, and the one for base regs. */
1193 #define INDEX_REG_CLASS GENERAL_REGS
1194 #define BASE_REG_CLASS GENERAL_REGS
1196 /* Local macro to handle the two v9 classes of FP regs. */
1197 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1199 /* Predicates for 10-bit, 11-bit and 13-bit signed constants. */
1200 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1201 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1202 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1204 /* 10- and 11-bit immediates are only used for a few specific insns.
1205 SMALL_INT is used throughout the port so we continue to use it. */
1206 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1208 /* Predicate for constants that can be loaded with a sethi instruction.
1209 This is the general, 64-bit aware, bitwise version that ensures that
1210 only constants whose representation fits in the mask
1214 are accepted. It will reject, for example, negative SImode constants
1215 on 64-bit hosts, so correct handling is to mask the value beforehand
1216 according to the mode of the instruction. */
1217 #define SPARC_SETHI_P(X) \
1218 (((unsigned HOST_WIDE_INT) (X) \
1219 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1221 /* Version of the above predicate for SImode constants and below. */
1222 #define SPARC_SETHI32_P(X) \
1223 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1225 /* Given an rtx X being reloaded into a reg required to be
1226 in class CLASS, return the class of reg to actually use.
1227 In general this is just CLASS; but on some machines
1228 in some cases it is preferable to use a more restrictive class. */
1229 /* - We can't load constants into FP registers.
1230 - We can't load FP constants into integer registers when soft-float,
1231 because there is no soft-float pattern with a r/F constraint.
1232 - We can't load FP constants into integer registers for TFmode unless
1233 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1234 - Try and reload integer constants (symbolic or otherwise) back into
1235 registers directly, rather than having them dumped to memory. */
1237 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1239 ? ((FP_REG_CLASS_P (CLASS) \
1240 || (CLASS) == GENERAL_OR_FP_REGS \
1241 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
1242 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1244 || (GET_MODE (X) == TFmode \
1245 && ! const_zero_operand (X, TFmode))) \
1247 : (!FP_REG_CLASS_P (CLASS) \
1248 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1253 /* Return the register class of a scratch register needed to load IN into
1254 a register of class CLASS in MODE.
1256 We need a temporary when loading/storing a HImode/QImode value
1257 between memory and the FPU registers. This can happen when combine puts
1258 a paradoxical subreg in a float/fix conversion insn.
1260 We need a temporary when loading/storing a DFmode value between
1261 unaligned memory and the upper FPU registers. */
1263 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1264 ((FP_REG_CLASS_P (CLASS) \
1265 && ((MODE) == HImode || (MODE) == QImode) \
1266 && (GET_CODE (IN) == MEM \
1267 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1268 && true_regnum (IN) == -1))) \
1270 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1271 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1272 && ! mem_min_alignment ((IN), 8)) \
1274 : (((TARGET_CM_MEDANY \
1275 && symbolic_operand ((IN), (MODE))) \
1276 || (TARGET_CM_EMBMEDANY \
1277 && text_segment_operand ((IN), (MODE)))) \
1282 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1283 ((FP_REG_CLASS_P (CLASS) \
1284 && ((MODE) == HImode || (MODE) == QImode) \
1285 && (GET_CODE (IN) == MEM \
1286 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1287 && true_regnum (IN) == -1))) \
1289 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1290 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1291 && ! mem_min_alignment ((IN), 8)) \
1293 : (((TARGET_CM_MEDANY \
1294 && symbolic_operand ((IN), (MODE))) \
1295 || (TARGET_CM_EMBMEDANY \
1296 && text_segment_operand ((IN), (MODE)))) \
1301 /* On SPARC it is not possible to directly move data between
1302 GENERAL_REGS and FP_REGS. */
1303 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1304 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1306 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1307 because the movsi and movsf patterns don't handle r/f moves.
1308 For v8 we copy the default definition. */
1309 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1311 ? (GET_MODE_BITSIZE (MODE) < 32 \
1312 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1314 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1315 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1318 /* Return the maximum number of consecutive registers
1319 needed to represent mode MODE in a register of class CLASS. */
1320 /* On SPARC, this is the size of MODE in words. */
1321 #define CLASS_MAX_NREGS(CLASS, MODE) \
1322 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1323 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1325 /* Stack layout; function entry, exit and calling. */
1327 /* Define this if pushing a word on the stack
1328 makes the stack pointer a smaller address. */
1329 #define STACK_GROWS_DOWNWARD
1331 /* Define this to nonzero if the nominal address of the stack frame
1332 is at the high-address end of the local variables;
1333 that is, each additional local variable allocated
1334 goes at a more negative offset in the frame. */
1335 #define FRAME_GROWS_DOWNWARD 1
1337 /* Offset within stack frame to start allocating local variables at.
1338 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1339 first local allocated. Otherwise, it is the offset to the BEGINNING
1340 of the first local allocated. */
1341 #define STARTING_FRAME_OFFSET 0
1343 /* Offset of first parameter from the argument pointer register value.
1344 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1345 even if this function isn't going to use it.
1346 v9: This is 128 for the ins and locals. */
1347 #define FIRST_PARM_OFFSET(FNDECL) \
1348 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1350 /* Offset from the argument pointer register value to the CFA.
1351 This is different from FIRST_PARM_OFFSET because the register window
1352 comes between the CFA and the arguments. */
1353 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1355 /* When a parameter is passed in a register, stack space is still
1357 !v9: All 6 possible integer registers have backing store allocated.
1358 v9: Only space for the arguments passed is allocated. */
1359 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1360 meaning to the backend. Further, we need to be able to detect if a
1361 varargs/unprototyped function is called, as they may want to spill more
1362 registers than we've provided space. Ugly, ugly. So for now we retain
1363 all 6 slots even for v9. */
1364 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1366 /* Definitions for register elimination. */
1368 #define ELIMINABLE_REGS \
1369 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1370 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1372 /* We always pretend that this is a leaf function because if it's not,
1373 there's no point in trying to eliminate the frame pointer. If it
1374 is a leaf function, we guessed right! */
1375 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1377 if ((TO) == STACK_POINTER_REGNUM) \
1378 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \
1381 (OFFSET) += SPARC_STACK_BIAS; \
1384 /* Keep the stack pointer constant throughout the function.
1385 This is both an optimization and a necessity: longjmp
1386 doesn't behave itself when the stack pointer moves within
1388 #define ACCUMULATE_OUTGOING_ARGS 1
1390 /* Value is the number of bytes of arguments automatically
1391 popped when returning from a subroutine call.
1392 FUNDECL is the declaration node of the function (as a tree),
1393 FUNTYPE is the data type of the function (as a tree),
1394 or for a library call it is an identifier node for the subroutine name.
1395 SIZE is the number of bytes of arguments passed on the stack. */
1397 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1399 /* Define this macro if the target machine has "register windows". This
1400 C expression returns the register number as seen by the called function
1401 corresponding to register number OUT as seen by the calling function.
1402 Return OUT if register number OUT is not an outbound register. */
1404 #define INCOMING_REGNO(OUT) \
1405 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1407 /* Define this macro if the target machine has "register windows". This
1408 C expression returns the register number as seen by the calling function
1409 corresponding to register number IN as seen by the called function.
1410 Return IN if register number IN is not an inbound register. */
1412 #define OUTGOING_REGNO(IN) \
1413 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1415 /* Define this macro if the target machine has register windows. This
1416 C expression returns true if the register is call-saved but is in the
1419 #define LOCAL_REGNO(REGNO) \
1420 ((REGNO) >= 16 && (REGNO) <= 31)
1422 /* Define how to find the value returned by a function.
1423 VALTYPE is the data type of the value (as a tree).
1424 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1425 otherwise, FUNC is 0. */
1427 /* On SPARC the value is found in the first "output" register. */
1429 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1430 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1432 /* But the called function leaves it in the first "input" register. */
1434 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1435 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1437 /* Define how to find the value returned by a library function
1438 assuming the value has mode MODE. */
1440 #define LIBCALL_VALUE(MODE) \
1441 function_value (NULL_TREE, (MODE), 1)
1443 /* 1 if N is a possible register number for a function value
1444 as seen by the caller.
1445 On SPARC, the first "output" reg is used for integer values,
1446 and the first floating point register is used for floating point values. */
1448 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1450 /* Define the size of space to allocate for the return value of an
1453 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16)
1455 /* 1 if N is a possible register number for function argument passing.
1456 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1458 #define FUNCTION_ARG_REGNO_P(N) \
1460 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1461 : ((N) >= 8 && (N) <= 13))
1463 /* Define a data type for recording info about an argument list
1464 during the scan of that argument list. This data type should
1465 hold all necessary information about the function itself
1466 and about the args processed so far, enough to enable macros
1467 such as FUNCTION_ARG to determine where the next arg should go.
1469 On SPARC (!v9), this is a single integer, which is a number of words
1470 of arguments scanned so far (including the invisible argument,
1471 if any, which holds the structure-value-address).
1472 Thus 7 or more means all following args should go on the stack.
1474 For v9, we also need to know whether a prototype is present. */
1477 int words; /* number of words passed so far */
1478 int prototype_p; /* nonzero if a prototype is present */
1479 int libcall_p; /* nonzero if a library call */
1481 #define CUMULATIVE_ARGS struct sparc_args
1483 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1484 for a call to a function whose data type is FNTYPE.
1485 For a library call, FNTYPE is 0. */
1487 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1488 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1490 /* Update the data in CUM to advance over an argument
1491 of mode MODE and data type TYPE.
1492 TYPE is null for libcalls where that information may not be available. */
1494 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1495 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1497 /* Determine where to put an argument to a function.
1498 Value is zero to push the argument on the stack,
1499 or a hard register in which to store the argument.
1501 MODE is the argument's machine mode.
1502 TYPE is the data type of the argument (as a tree).
1503 This is null for libcalls where that information may
1505 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1506 the preceding args and about the function being called.
1507 NAMED is nonzero if this argument is a named parameter
1508 (otherwise it is an extra parameter matching an ellipsis). */
1510 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1511 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1513 /* Define where a function finds its arguments.
1514 This is different from FUNCTION_ARG because of register windows. */
1516 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1517 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1519 /* If defined, a C expression which determines whether, and in which direction,
1520 to pad out an argument with extra space. The value should be of type
1521 `enum direction': either `upward' to pad above the argument,
1522 `downward' to pad below, or `none' to inhibit padding. */
1524 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1525 function_arg_padding ((MODE), (TYPE))
1527 /* If defined, a C expression that gives the alignment boundary, in bits,
1528 of an argument with the specified mode and type. If it is not defined,
1529 PARM_BOUNDARY is used for all arguments.
1530 For sparc64, objects requiring 16 byte alignment are passed that way. */
1532 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1534 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1535 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1536 ? 128 : PARM_BOUNDARY)
1539 /* Generate the special assembly code needed to tell the assembler whatever
1540 it might need to know about the return value of a function.
1542 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1543 information to the assembler relating to peephole optimization (done in
1546 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1547 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1549 /* Output the special assembly code needed to tell the assembler some
1550 register is used as global register variable.
1552 SPARC 64bit psABI declares registers %g2 and %g3 as application
1553 registers and %g6 and %g7 as OS registers. Any object using them
1554 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1555 and how they are used (scratch or some global variable).
1556 Linker will then refuse to link together objects which use those
1557 registers incompatibly.
1559 Unless the registers are used for scratch, two different global
1560 registers cannot be declared to the same name, so in the unlikely
1561 case of a global register variable occupying more than one register
1562 we prefix the second and following registers with .gnu.part1. etc. */
1564 extern GTY(()) char sparc_hard_reg_printed[8];
1566 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1567 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1569 if (TARGET_ARCH64) \
1571 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1573 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1574 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1576 if (reg == (REGNO)) \
1577 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1579 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1580 reg, reg - (REGNO), (NAME)); \
1581 sparc_hard_reg_printed[reg] = 1; \
1588 /* Emit rtl for profiling. */
1589 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1591 /* All the work done in PROFILE_HOOK, but still required. */
1592 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1594 /* Set the name of the mcount function for the system. */
1595 #define MCOUNT_FUNCTION "*mcount"
1597 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1598 the stack pointer does not matter. The value is tested only in
1599 functions that have frame pointers.
1600 No definition is equivalent to always zero. */
1602 #define EXIT_IGNORE_STACK \
1603 (get_frame_size () != 0 \
1604 || cfun->calls_alloca || crtl->outgoing_args_size)
1606 /* Define registers used by the epilogue and return instruction. */
1607 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \
1608 || (crtl->calls_eh_return && (REGNO) == 1))
1610 /* Length in units of the trampoline for entering a nested function. */
1612 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1614 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1616 /* Generate RTL to flush the register windows so as to make arbitrary frames
1618 #define SETUP_FRAME_ADDRESSES() \
1619 emit_insn (gen_flush_register_windows ())
1621 /* Given an rtx for the address of a frame,
1622 return an rtx for the address of the word in the frame
1623 that holds the dynamic chain--the previous frame's address. */
1624 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1625 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1627 /* Given an rtx for the frame pointer,
1628 return an rtx for the address of the frame. */
1629 #define FRAME_ADDR_RTX(frame) plus_constant (frame, SPARC_STACK_BIAS)
1631 /* The return address isn't on the stack, it is in a register, so we can't
1632 access it from the current frame pointer. We can access it from the
1633 previous frame pointer though by reading a value from the register window
1635 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1637 /* This is the offset of the return address to the true next instruction to be
1638 executed for the current function. */
1639 #define RETURN_ADDR_OFFSET \
1640 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct))
1642 /* The current return address is in %i7. The return address of anything
1643 farther back is in the register window save area at [%fp+60]. */
1644 /* ??? This ignores the fact that the actual return address is +8 for normal
1645 returns, and +12 for structure returns. */
1646 #define RETURN_ADDR_RTX(count, frame) \
1648 ? gen_rtx_REG (Pmode, 31) \
1649 : gen_rtx_MEM (Pmode, \
1650 memory_address (Pmode, plus_constant (frame, \
1651 15 * UNITS_PER_WORD \
1652 + SPARC_STACK_BIAS))))
1654 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1655 +12, but always using +8 is close enough for frame unwind purposes.
1656 Actually, just using %o7 is close enough for unwinding, but %o7+8
1657 is something you can return to. */
1658 #define INCOMING_RETURN_ADDR_RTX \
1659 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1660 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1662 /* The offset from the incoming value of %sp to the top of the stack frame
1663 for the current function. On sparc64, we have to account for the stack
1665 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1667 /* Describe how we implement __builtin_eh_return. */
1668 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1669 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1670 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1672 /* Select a format to encode pointers in exception handling data. CODE
1673 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1674 true if the symbol may be affected by dynamic relocations.
1676 If assembler and linker properly support .uaword %r_disp32(foo),
1677 then use PC relative 32-bit relocations instead of absolute relocs
1678 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1679 for binaries, to save memory.
1681 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1682 symbol %r_disp32() is against was not local, but .hidden. In that
1683 case, we have to use DW_EH_PE_absptr for pic personality. */
1684 #ifdef HAVE_AS_SPARC_UA_PCREL
1685 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1686 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1688 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1689 : ((TARGET_ARCH64 && ! GLOBAL) \
1690 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1693 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1695 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1696 : ((TARGET_ARCH64 && ! GLOBAL) \
1697 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1701 /* Emit a PC-relative relocation. */
1702 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1704 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1705 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1706 assemble_name (FILE, LABEL); \
1707 fputc (')', FILE); \
1711 /* Addressing modes, and classification of registers for them. */
1713 /* Macros to check register numbers against specific register classes. */
1715 /* These assume that REGNO is a hard or pseudo reg number.
1716 They give nonzero only if REGNO is a hard reg of the suitable class
1717 or a pseudo reg currently allocated to a suitable hard reg.
1718 Since they use reg_renumber, they are safe only once reg_renumber
1719 has been allocated, which happens in local-alloc.c. */
1721 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1722 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
1723 || (REGNO) == FRAME_POINTER_REGNUM \
1724 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1726 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1728 #define REGNO_OK_FOR_FP_P(REGNO) \
1729 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1730 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1731 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1733 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1734 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1736 /* Now macros that check whether X is a register and also,
1737 strictly, whether it is in a specified class.
1739 These macros are specific to the SPARC, and may be used only
1740 in code for printing assembler insns and in conditions for
1741 define_optimization. */
1743 /* 1 if X is an fp register. */
1745 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1747 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
1748 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
1750 /* Maximum number of registers that can appear in a valid memory address. */
1752 #define MAX_REGS_PER_ADDRESS 2
1754 /* Recognize any constant value that is a valid address.
1755 When PIC, we do not accept an address that would require a scratch reg
1756 to load into a register. */
1758 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1760 /* Define this, so that when PIC, reload won't try to reload invalid
1761 addresses which require two reload registers. */
1763 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1765 /* Nonzero if the constant value X is a legitimate general operand.
1766 Anything can be made to work except floating point constants.
1767 If TARGET_VIS, 0.0 can be made to work as well. */
1769 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1771 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1772 and check its validity for a certain class.
1773 We have two alternate definitions for each of them.
1774 The usual definition accepts all pseudo regs; the other rejects
1775 them unless they have been allocated suitable hard regs.
1776 The symbol REG_OK_STRICT causes the latter definition to be used.
1778 Most source files want to accept pseudo regs in the hope that
1779 they will get allocated to the class that the insn wants them to be in.
1780 Source files for reload pass need to be strict.
1781 After reload, it makes no difference, since pseudo regs have
1782 been eliminated by then. */
1784 #ifndef REG_OK_STRICT
1786 /* Nonzero if X is a hard reg that can be used as an index
1787 or if it is a pseudo reg. */
1788 #define REG_OK_FOR_INDEX_P(X) \
1790 || REGNO (X) == FRAME_POINTER_REGNUM \
1791 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1793 /* Nonzero if X is a hard reg that can be used as a base reg
1794 or if it is a pseudo reg. */
1795 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
1799 /* Nonzero if X is a hard reg that can be used as an index. */
1800 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1801 /* Nonzero if X is a hard reg that can be used as a base reg. */
1802 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1806 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
1808 #ifdef HAVE_AS_OFFSETABLE_LO10
1809 #define USE_AS_OFFSETABLE_LO10 1
1811 #define USE_AS_OFFSETABLE_LO10 0
1814 /* On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1815 ordinarily. This changes a bit when generating PIC. The details are
1816 in sparc.c's implementation of TARGET_LEGITIMATE_ADDRESS_P. */
1818 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
1820 #define RTX_OK_FOR_BASE_P(X) \
1821 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1822 || (GET_CODE (X) == SUBREG \
1823 && GET_CODE (SUBREG_REG (X)) == REG \
1824 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1826 #define RTX_OK_FOR_INDEX_P(X) \
1827 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1828 || (GET_CODE (X) == SUBREG \
1829 && GET_CODE (SUBREG_REG (X)) == REG \
1830 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1832 #define RTX_OK_FOR_OFFSET_P(X) \
1833 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
1835 #define RTX_OK_FOR_OLO10_P(X) \
1836 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
1838 /* Go to LABEL if ADDR (a legitimate address expression)
1839 has an effect that depends on the machine mode it is used for.
1845 is not equivalent to
1847 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
1849 because [%l7+a+1] is interpreted as the address of (a+1). */
1851 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1853 if (flag_pic == 1) \
1855 if (GET_CODE (ADDR) == PLUS) \
1857 rtx op0 = XEXP (ADDR, 0); \
1858 rtx op1 = XEXP (ADDR, 1); \
1859 if (op0 == pic_offset_table_rtx \
1860 && SYMBOLIC_CONST (op1)) \
1866 /* Try a machine-dependent way of reloading an illegitimate address
1867 operand. If we find one, push the reload and jump to WIN. This
1868 macro is used in only one place: `find_reloads_address' in reload.c.
1870 For SPARC 32, we wish to handle addresses by splitting them into
1871 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
1872 This cuts the number of extra insns by one.
1874 Do nothing when generating PIC code and the address is a
1875 symbolic operand or requires a scratch register. */
1877 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1879 /* Decompose SImode constants into hi+lo_sum. We do have to \
1880 rerecognize what we produce, so be careful. */ \
1881 if (CONSTANT_P (X) \
1882 && (MODE != TFmode || TARGET_ARCH64) \
1883 && GET_MODE (X) == SImode \
1884 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
1886 && (symbolic_operand (X, Pmode) \
1887 || pic_address_needs_scratch (X))) \
1888 && sparc_cmodel <= CM_MEDLOW) \
1890 X = gen_rtx_LO_SUM (GET_MODE (X), \
1891 gen_rtx_HIGH (GET_MODE (X), X), X); \
1892 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1893 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1897 /* ??? 64-bit reloads. */ \
1900 /* Specify the machine mode that this machine uses
1901 for the index in the tablejump instruction. */
1902 /* If we ever implement any of the full models (such as CM_FULLANY),
1903 this has to be DImode in that case */
1904 #ifdef HAVE_GAS_SUBSECTION_ORDERING
1905 #define CASE_VECTOR_MODE \
1906 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
1908 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
1909 we have to sign extend which slows things down. */
1910 #define CASE_VECTOR_MODE \
1911 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
1914 /* Define this as 1 if `char' should by default be signed; else as 0. */
1915 #define DEFAULT_SIGNED_CHAR 1
1917 /* Max number of bytes we can move from memory to memory
1918 in one reasonably fast instruction. */
1921 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1922 move-instruction pairs, we will do a movmem or libcall instead. */
1924 #define MOVE_RATIO(speed) ((speed) ? 8 : 3)
1926 /* Define if operations between registers always perform the operation
1927 on the full register even if a narrower mode is specified. */
1928 #define WORD_REGISTER_OPERATIONS
1930 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1931 will either zero-extend or sign-extend. The value of this macro should
1932 be the code that says which one of the two operations is implicitly
1933 done, UNKNOWN if none. */
1934 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1936 /* Nonzero if access to memory by bytes is slow and undesirable.
1937 For RISC chips, it means that access to memory by bytes is no
1938 better than access by words when possible, so grab a whole word
1939 and maybe make use of that. */
1940 #define SLOW_BYTE_ACCESS 1
1942 /* Define this to be nonzero if shift instructions ignore all but the low-order
1944 #define SHIFT_COUNT_TRUNCATED 1
1946 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1947 is done just by pretending it is already truncated. */
1948 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1950 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1951 return the mode to be used for the comparison. For floating-point,
1952 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
1953 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1954 processing is needed. */
1955 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
1957 /* Return nonzero if MODE implies a floating point inequality can be
1958 reversed. For SPARC this is always true because we have a full
1959 compliment of ordered and unordered comparisons, but until generic
1960 code knows how to reverse it correctly we keep the old definition. */
1961 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
1963 /* A function address in a call instruction for indexing purposes. */
1964 #define FUNCTION_MODE Pmode
1966 /* Define this if addresses of constant functions
1967 shouldn't be put through pseudo regs where they can be cse'd.
1968 Desirable on machines where ordinary constants are expensive
1969 but a CALL with constant address is cheap. */
1970 #define NO_FUNCTION_CSE
1972 /* alloca should avoid clobbering the old register save area. */
1973 #define SETJMP_VIA_SAVE_AREA
1975 /* The _Q_* comparison libcalls return booleans. */
1976 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
1978 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
1979 that the inputs are fully consumed before the output memory is clobbered. */
1981 #define TARGET_BUGGY_QP_LIB 0
1983 /* Assume by default that we do not have the Solaris-specific conversion
1984 routines nor 64-bit integer multiply and divide routines. */
1986 #define SUN_CONVERSION_LIBFUNCS 0
1987 #define DITF_CONVERSION_LIBFUNCS 0
1988 #define SUN_INTEGER_MULTIPLY_64 0
1990 /* Compute extra cost of moving data between one register class
1992 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
1993 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1994 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
1995 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
1996 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
1997 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
1998 || sparc_cpu == PROCESSOR_ULTRASPARC3 \
1999 || sparc_cpu == PROCESSOR_NIAGARA \
2000 || sparc_cpu == PROCESSOR_NIAGARA2) ? 12 : 6) : 2)
2002 /* Provide the cost of a branch. For pre-v9 processors we use
2003 a value of 3 to take into account the potential annulling of
2004 the delay slot (which ends up being a bubble in the pipeline slot)
2005 plus a cycle to take into consideration the instruction cache
2008 On v9 and later, which have branch prediction facilities, we set
2009 it to the depth of the pipeline as that is the cost of a
2010 mispredicted branch.
2012 On Niagara, normal branches insert 3 bubbles into the pipe
2013 and annulled branches insert 4 bubbles.
2015 On Niagara-2, a not-taken branch costs 1 cycle whereas a taken
2016 branch costs 6 cycles. */
2018 #define BRANCH_COST(speed_p, predictable_p) \
2019 ((sparc_cpu == PROCESSOR_V9 \
2020 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2022 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2024 : (sparc_cpu == PROCESSOR_NIAGARA \
2026 : (sparc_cpu == PROCESSOR_NIAGARA2 \
2030 /* Control the assembler format that we output. */
2032 /* A C string constant describing how to begin a comment in the target
2033 assembler language. The compiler assumes that the comment will end at
2034 the end of the line. */
2036 #define ASM_COMMENT_START "!"
2038 /* Output to assembler file text saying following lines
2039 may contain character constants, extra white space, comments, etc. */
2041 #define ASM_APP_ON ""
2043 /* Output to assembler file text saying following lines
2044 no longer contain unusual constructs. */
2046 #define ASM_APP_OFF ""
2048 /* How to refer to registers in assembler output.
2049 This sequence is indexed by compiler's hard-register-number (see above). */
2051 #define REGISTER_NAMES \
2052 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2053 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2054 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2055 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2056 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2057 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2058 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2059 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2060 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2061 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2062 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2063 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2064 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2066 /* Define additional names for use in asm clobbers and asm declarations. */
2068 #define ADDITIONAL_REGISTER_NAMES \
2069 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2071 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2072 can run past this up to a continuation point. Once we used 1500, but
2073 a single entry in C++ can run more than 500 bytes, due to the length of
2074 mangled symbol names. dbxout.c should really be fixed to do
2075 continuations when they are actually needed instead of trying to
2077 #define DBX_CONTIN_LENGTH 1000
2079 /* This is how to output a command to make the user-level label named NAME
2080 defined for reference from other files. */
2082 /* Globalizing directive for a label. */
2083 #define GLOBAL_ASM_OP "\t.global "
2085 /* The prefix to add to user-visible assembler symbols. */
2087 #define USER_LABEL_PREFIX "_"
2089 /* This is how to store into the string LABEL
2090 the symbol_ref name of an internal numbered label where
2091 PREFIX is the class of label and NUM is the number within the class.
2092 This is suitable for output with `assemble_name'. */
2094 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2095 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2097 /* This is how we hook in and defer the case-vector until the end of
2099 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2100 sparc_defer_case_vector ((LAB),(VEC), 0)
2102 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2103 sparc_defer_case_vector ((LAB),(VEC), 1)
2105 /* This is how to output an element of a case-vector that is absolute. */
2107 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2110 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2111 if (CASE_VECTOR_MODE == SImode) \
2112 fprintf (FILE, "\t.word\t"); \
2114 fprintf (FILE, "\t.xword\t"); \
2115 assemble_name (FILE, label); \
2116 fputc ('\n', FILE); \
2119 /* This is how to output an element of a case-vector that is relative.
2120 (SPARC uses such vectors only when generating PIC.) */
2122 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2125 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2126 if (CASE_VECTOR_MODE == SImode) \
2127 fprintf (FILE, "\t.word\t"); \
2129 fprintf (FILE, "\t.xword\t"); \
2130 assemble_name (FILE, label); \
2131 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2132 fputc ('-', FILE); \
2133 assemble_name (FILE, label); \
2134 fputc ('\n', FILE); \
2137 /* This is what to output before and after case-vector (both
2138 relative and absolute). If .subsection -1 works, we put case-vectors
2139 at the beginning of the current section. */
2141 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2143 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2144 fprintf(FILE, "\t.subsection\t-1\n")
2146 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2147 fprintf(FILE, "\t.previous\n")
2151 /* This is how to output an assembler line
2152 that says to advance the location counter
2153 to a multiple of 2**LOG bytes. */
2155 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2157 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2159 /* This is how to output an assembler line that says to advance
2160 the location counter to a multiple of 2**LOG bytes using the
2161 "nop" instruction as padding. */
2162 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
2164 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG)))
2166 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2167 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2169 /* This says how to output an assembler line
2170 to define a global common symbol. */
2172 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2173 ( fputs ("\t.common ", (FILE)), \
2174 assemble_name ((FILE), (NAME)), \
2175 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
2177 /* This says how to output an assembler line to define a local common
2180 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2181 ( fputs ("\t.reserve ", (FILE)), \
2182 assemble_name ((FILE), (NAME)), \
2183 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
2184 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2186 /* A C statement (sans semicolon) to output to the stdio stream
2187 FILE the assembler definition of uninitialized global DECL named
2188 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2189 Try to use asm_output_aligned_bss to implement this macro. */
2191 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2193 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2196 #define IDENT_ASM_OP "\t.ident\t"
2198 /* Output #ident as a .ident. */
2200 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2201 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2203 /* Prettify the assembly. */
2205 extern int sparc_indent_opcode;
2207 #define ASM_OUTPUT_OPCODE(FILE, PTR) \
2209 if (sparc_indent_opcode) \
2212 sparc_indent_opcode = 0; \
2216 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2217 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \
2218 || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&')
2220 /* Print operand X (an rtx) in assembler syntax to file FILE.
2221 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2222 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2224 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2226 /* Print a memory address as an operand to reference that memory location. */
2228 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2229 { register rtx base, index = 0; \
2231 register rtx addr = ADDR; \
2232 if (GET_CODE (addr) == REG) \
2233 fputs (reg_names[REGNO (addr)], FILE); \
2234 else if (GET_CODE (addr) == PLUS) \
2236 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2237 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2238 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2239 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2241 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2242 if (GET_CODE (base) == LO_SUM) \
2244 gcc_assert (USE_AS_OFFSETABLE_LO10 \
2246 && ! TARGET_CM_MEDMID); \
2247 output_operand (XEXP (base, 0), 0); \
2248 fputs ("+%lo(", FILE); \
2249 output_address (XEXP (base, 1)); \
2250 fprintf (FILE, ")+%d", offset); \
2254 fputs (reg_names[REGNO (base)], FILE); \
2256 fprintf (FILE, "%+d", offset); \
2257 else if (GET_CODE (index) == REG) \
2258 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2259 else if (GET_CODE (index) == SYMBOL_REF \
2260 || GET_CODE (index) == LABEL_REF \
2261 || GET_CODE (index) == CONST) \
2262 fputc ('+', FILE), output_addr_const (FILE, index); \
2263 else gcc_unreachable (); \
2266 else if (GET_CODE (addr) == MINUS \
2267 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2269 output_addr_const (FILE, XEXP (addr, 0)); \
2270 fputs ("-(", FILE); \
2271 output_addr_const (FILE, XEXP (addr, 1)); \
2272 fputs ("-.)", FILE); \
2274 else if (GET_CODE (addr) == LO_SUM) \
2276 output_operand (XEXP (addr, 0), 0); \
2277 if (TARGET_CM_MEDMID) \
2278 fputs ("+%l44(", FILE); \
2280 fputs ("+%lo(", FILE); \
2281 output_address (XEXP (addr, 1)); \
2282 fputc (')', FILE); \
2284 else if (flag_pic && GET_CODE (addr) == CONST \
2285 && GET_CODE (XEXP (addr, 0)) == MINUS \
2286 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2287 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2288 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2290 addr = XEXP (addr, 0); \
2291 output_addr_const (FILE, XEXP (addr, 0)); \
2292 /* Group the args of the second CONST in parenthesis. */ \
2293 fputs ("-(", FILE); \
2294 /* Skip past the second CONST--it does nothing for us. */\
2295 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2296 /* Close the parenthesis. */ \
2297 fputc (')', FILE); \
2301 output_addr_const (FILE, addr); \
2305 /* TLS support defaulting to original Sun flavor. GNU extensions
2306 must be activated in separate configuration files. */
2308 #define TARGET_TLS 1
2310 #define TARGET_TLS 0
2313 #define TARGET_SUN_TLS TARGET_TLS
2314 #define TARGET_GNU_TLS 0
2316 /* The number of Pmode words for the setjmp buffer. */
2317 #define JMP_BUF_SIZE 12
2319 /* We use gcc _mcount for profiling. */
2320 #define NO_PROFILE_COUNTERS 0