1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of
29 Solaris only; otherwise just define __sparc__. Sadly the headers
30 are such a mess there is no Solaris-specific header. */
31 #define TARGET_CPU_CPP_BUILTINS() \
34 builtin_define_std ("sparc"); \
37 builtin_assert ("cpu=sparc64"); \
38 builtin_assert ("machine=sparc64"); \
42 builtin_assert ("cpu=sparc"); \
43 builtin_assert ("machine=sparc"); \
48 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
49 /* #define SPARC_BI_ARCH */
51 /* Macro used later in this file to determine default architecture. */
52 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
54 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
55 architectures to compile for. We allow targets to choose compile time or
58 #if defined(__sparcv9) || defined(__arch64__)
59 #define TARGET_ARCH32 0
61 #define TARGET_ARCH32 1
65 #define TARGET_ARCH32 (! TARGET_64BIT)
67 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
68 #endif /* SPARC_BI_ARCH */
69 #endif /* IN_LIBGCC2 */
70 #define TARGET_ARCH64 (! TARGET_ARCH32)
72 /* Code model selection.
73 -mcmodel is used to select the v9 code model.
74 Different code models aren't supported for v7/8 code.
76 TARGET_CM_32: 32 bit address space, top 32 bits = 0,
77 pointers are 32 bits. Note that this isn't intended
80 TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
81 avoid generating %uhi and %ulo terms,
84 TARGET_CM_MEDMID: 64 bit address space.
85 The executable must be in the low 16 TB of memory.
86 This corresponds to the low 44 bits, and the %[hml]44
87 relocs are used. The text segment has a maximum size
90 TARGET_CM_MEDANY: 64 bit address space.
91 The text and data segments have a maximum size of 31
92 bits and may be located anywhere. The maximum offset
93 from any instruction to the label _GLOBAL_OFFSET_TABLE_
96 TARGET_CM_EMBMEDANY: 64 bit address space.
97 The text and data segments have a maximum size of 31 bits
98 and may be located anywhere. Register %g4 contains
99 the start address of the data segment.
110 /* Value of -mcmodel specified by user. */
111 extern const char *sparc_cmodel_string;
113 extern enum cmodel sparc_cmodel;
115 /* V9 code model selection. */
116 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
117 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
118 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
119 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
121 #define SPARC_DEFAULT_CMODEL CM_32
123 /* This is call-clobbered in the normal ABI, but is reserved in the
124 home grown (aka upward compatible) embedded ABI. */
125 #define EMBMEDANY_BASE_REG "%g4"
127 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
128 and specified by the user via --with-cpu=foo.
129 This specifies the cpu implementation, not the architecture size. */
130 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
132 #define TARGET_CPU_sparc 0
133 #define TARGET_CPU_v7 0 /* alias for previous */
134 #define TARGET_CPU_sparclet 1
135 #define TARGET_CPU_sparclite 2
136 #define TARGET_CPU_v8 3 /* generic v8 implementation */
137 #define TARGET_CPU_supersparc 4
138 #define TARGET_CPU_hypersparc 5
139 #define TARGET_CPU_sparc86x 6
140 #define TARGET_CPU_sparclite86x 6
141 #define TARGET_CPU_v9 7 /* generic v9 implementation */
142 #define TARGET_CPU_sparcv9 7 /* alias */
143 #define TARGET_CPU_sparc64 7 /* alias */
144 #define TARGET_CPU_ultrasparc 8
145 #define TARGET_CPU_ultrasparc3 9
147 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
148 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
149 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
151 #define CPP_CPU32_DEFAULT_SPEC ""
152 #define ASM_CPU32_DEFAULT_SPEC ""
154 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
155 /* ??? What does Sun's CC pass? */
156 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
157 /* ??? It's not clear how other assemblers will handle this, so by default
158 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
159 is handled in sol2.h. */
160 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
162 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
163 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
164 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
166 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
167 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
168 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
173 #define CPP_CPU64_DEFAULT_SPEC ""
174 #define ASM_CPU64_DEFAULT_SPEC ""
176 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
177 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
178 #define CPP_CPU32_DEFAULT_SPEC ""
179 #define ASM_CPU32_DEFAULT_SPEC ""
182 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
183 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
184 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
187 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
188 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
189 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
192 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
193 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
194 #define ASM_CPU32_DEFAULT_SPEC ""
197 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
198 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
199 #define ASM_CPU32_DEFAULT_SPEC ""
202 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
203 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
204 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
209 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
210 #error Unrecognized value in TARGET_CPU_DEFAULT.
215 #define CPP_CPU_DEFAULT_SPEC \
216 (DEFAULT_ARCH32_P ? "\
217 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
218 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
220 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
221 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
223 #define ASM_CPU_DEFAULT_SPEC \
224 (DEFAULT_ARCH32_P ? "\
225 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
226 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
228 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
229 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
232 #else /* !SPARC_BI_ARCH */
234 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
235 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
237 #endif /* !SPARC_BI_ARCH */
239 /* Define macros to distinguish architectures. */
241 /* Common CPP definitions used by CPP_SPEC amongst the various targets
242 for handling -mcpu=xxx switches. */
243 #define CPP_CPU_SPEC "\
244 %{msoft-float:-D_SOFT_FLOAT} \
246 %{msparclite:-D__sparclite__} \
247 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
248 %{mv8:-D__sparc_v8__} \
249 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
250 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
251 %{mcpu=sparclite:-D__sparclite__} \
252 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
253 %{mcpu=v8:-D__sparc_v8__} \
254 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
255 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
256 %{mcpu=sparclite86x:-D__sparclite86x__} \
257 %{mcpu=v9:-D__sparc_v9__} \
258 %{mcpu=ultrasparc:-D__sparc_v9__} \
259 %{mcpu=ultrasparc3:-D__sparc_v9__} \
260 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
262 #define CPP_ARCH32_SPEC ""
263 #define CPP_ARCH64_SPEC "-D__arch64__"
265 #define CPP_ARCH_DEFAULT_SPEC \
266 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
268 #define CPP_ARCH_SPEC "\
269 %{m32:%(cpp_arch32)} \
270 %{m64:%(cpp_arch64)} \
271 %{!m32:%{!m64:%(cpp_arch_default)}} \
274 /* Macros to distinguish endianness. */
275 #define CPP_ENDIAN_SPEC "\
276 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
277 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
279 /* Macros to distinguish the particular subtarget. */
280 #define CPP_SUBTARGET_SPEC ""
282 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
284 /* Prevent error on `-sun4' and `-target sun4' options. */
285 /* This used to translate -dalign to -malign, but that is no good
286 because it can't turn off the usual meaning of making debugging dumps. */
287 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
288 ??? Delete support for -m<cpu> for 2.9. */
291 %{sun4:} %{target:} \
292 %{mcypress:-mcpu=cypress} \
293 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
294 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
297 /* Override in target specific files. */
298 #define ASM_CPU_SPEC "\
299 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
300 %{msparclite:-Asparclite} \
301 %{mf930:-Asparclite} %{mf934:-Asparclite} \
302 %{mcpu=sparclite:-Asparclite} \
303 %{mcpu=sparclite86x:-Asparclite} \
304 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
305 %{mv8plus:-Av8plus} \
307 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
308 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
309 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
312 /* Word size selection, among other things.
313 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
315 #define ASM_ARCH32_SPEC "-32"
316 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
317 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
319 #define ASM_ARCH64_SPEC "-64"
321 #define ASM_ARCH_DEFAULT_SPEC \
322 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
324 #define ASM_ARCH_SPEC "\
325 %{m32:%(asm_arch32)} \
326 %{m64:%(asm_arch64)} \
327 %{!m32:%{!m64:%(asm_arch_default)}} \
330 #ifdef HAVE_AS_RELAX_OPTION
331 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
333 #define ASM_RELAX_SPEC ""
336 /* Special flags to the Sun-4 assembler when using pipe for input. */
339 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \
340 %(asm_cpu) %(asm_relax)"
342 #define AS_NEEDS_DASH_FOR_PIPED_INPUT
344 /* This macro defines names of additional specifications to put in the specs
345 that can be used in various specifications like CC1_SPEC. Its definition
346 is an initializer with a subgrouping for each command option.
348 Each subgrouping contains a string constant, that defines the
349 specification name, and a string constant that used by the GCC driver
352 Do not define this macro if it does not need to do anything. */
354 #define EXTRA_SPECS \
355 { "cpp_cpu", CPP_CPU_SPEC }, \
356 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
357 { "cpp_arch32", CPP_ARCH32_SPEC }, \
358 { "cpp_arch64", CPP_ARCH64_SPEC }, \
359 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
360 { "cpp_arch", CPP_ARCH_SPEC }, \
361 { "cpp_endian", CPP_ENDIAN_SPEC }, \
362 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
363 { "asm_cpu", ASM_CPU_SPEC }, \
364 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
365 { "asm_arch32", ASM_ARCH32_SPEC }, \
366 { "asm_arch64", ASM_ARCH64_SPEC }, \
367 { "asm_relax", ASM_RELAX_SPEC }, \
368 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
369 { "asm_arch", ASM_ARCH_SPEC }, \
370 SUBTARGET_EXTRA_SPECS
372 #define SUBTARGET_EXTRA_SPECS
374 /* Because libgcc can generate references back to libc (via .umul etc.) we have
375 to list libc again after the second libgcc. */
376 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
379 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
380 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
382 /* ??? This should be 32 bits for v9 but what can we do? */
383 #define WCHAR_TYPE "short unsigned int"
384 #define WCHAR_TYPE_SIZE 16
386 /* Show we can debug even without a frame pointer. */
387 #define CAN_DEBUG_WITHOUT_FP
389 #define OVERRIDE_OPTIONS sparc_override_options ()
391 /* Generate DBX debugging information. */
393 #define DBX_DEBUGGING_INFO 1
395 /* Run-time compilation parameters selecting different hardware subsets. */
397 extern int target_flags;
399 /* Nonzero if we should generate code to use the fpu. */
401 #define TARGET_FPU (target_flags & MASK_FPU)
403 /* Nonzero if we should assume that double pointers might be unaligned.
404 This can happen when linking gcc compiled code with other compilers,
405 because the ABI only guarantees 4 byte alignment. */
406 #define MASK_UNALIGNED_DOUBLES 4
407 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
409 /* Nonzero means that we should generate code for a v8 sparc. */
411 #define TARGET_V8 (target_flags & MASK_V8)
413 /* Nonzero means that we should generate code for a sparclite.
414 This enables the sparclite specific instructions, but does not affect
415 whether FPU instructions are emitted. */
416 #define MASK_SPARCLITE 0x10
417 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
419 /* Nonzero if we're compiling for the sparclet. */
420 #define MASK_SPARCLET 0x20
421 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
423 /* Nonzero if we're compiling for v9 sparc.
424 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
425 the word size is 64. */
427 #define TARGET_V9 (target_flags & MASK_V9)
429 /* Nonzero to generate code that uses the instructions deprecated in
430 the v9 architecture. This option only applies to v9 systems. */
431 /* ??? This isn't user selectable yet. It's used to enable such insns
432 on 32 bit v9 systems and for the moment they're permanently disabled
433 on 64 bit v9 systems. */
434 #define MASK_DEPRECATED_V8_INSNS 0x80
435 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
437 /* Mask of all CPU selection flags. */
439 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
441 /* Nonzero means don't pass `-assert pure-text' to the linker. */
442 #define MASK_IMPURE_TEXT 0x100
443 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
445 /* 0x200 is unused */
447 /* Nonzero means use the registers that the SPARC ABI reserves for
448 application software. This must be the default to coincide with the
449 setting in FIXED_REGISTERS. */
450 #define MASK_APP_REGS 0x400
451 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
453 /* Option to select how quad word floating point is implemented.
454 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
455 Otherwise, we use the SPARC ABI quad library functions. */
456 #define MASK_HARD_QUAD 0x800
457 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
459 /* Nonzero on little-endian machines. */
460 /* ??? Little endian support currently only exists for sparclet-aout and
461 sparc64-elf configurations. May eventually want to expand the support
462 to all targets, but for now it's kept local to only those two. */
463 #define MASK_LITTLE_ENDIAN 0x1000
464 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
466 /* 0x2000, 0x4000 are unused */
468 /* Nonzero if pointers are 64 bits. */
469 #define MASK_PTR64 0x8000
470 #define TARGET_PTR64 (target_flags & MASK_PTR64)
472 /* Nonzero if generating code to run in a 64 bit environment.
473 This is intended to only be used by TARGET_ARCH{32,64} as they are the
474 mechanism used to control compile time or run time selection. */
475 #define MASK_64BIT 0x10000
476 #define TARGET_64BIT (target_flags & MASK_64BIT)
478 /* 0x20000,0x40000 unused */
480 /* Nonzero means use a stack bias of 2047. Stack offsets are obtained by
481 adding 2047 to %sp. This option is for v9 only and is the default. */
482 #define MASK_STACK_BIAS 0x80000
483 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
485 /* 0x100000,0x200000 unused */
487 /* Nonzero means -m{,no-}fpu was passed on the command line. */
488 #define MASK_FPU_SET 0x400000
489 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
491 /* Use the UltraSPARC Visual Instruction Set extensions. */
492 #define MASK_VIS 0x1000000
493 #define TARGET_VIS (target_flags & MASK_VIS)
495 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
496 the current out and global registers and Linux 2.2+ as well. */
497 #define MASK_V8PLUS 0x2000000
498 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
500 /* Force a the fastest alignment on structures to take advantage of
502 #define MASK_FASTER_STRUCTS 0x4000000
503 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
505 /* Use IEEE quad long double. */
506 #define MASK_LONG_DOUBLE_128 0x8000000
507 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
509 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
510 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
511 to get high 32 bits. False in V8+ or V9 because multiply stores
512 a 64 bit result in a register. */
514 #define TARGET_HARD_MUL32 \
515 ((TARGET_V8 || TARGET_SPARCLITE \
516 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
517 && ! TARGET_V8PLUS && TARGET_ARCH32)
519 #define TARGET_HARD_MUL \
520 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
521 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
524 /* Macro to define tables used to set the flags.
525 This is a list in braces of pairs in braces,
526 each pair being { "NAME", VALUE }
527 where VALUE is the bits to set or minus the bits to clear.
528 An empty string NAME is used to identify the default VALUE. */
530 #define TARGET_SWITCHES \
531 { {"fpu", MASK_FPU | MASK_FPU_SET, \
532 N_("Use hardware fp") }, \
533 {"no-fpu", -MASK_FPU, \
534 N_("Do not use hardware fp") }, \
535 {"no-fpu", MASK_FPU_SET, NULL, }, \
536 {"hard-float", MASK_FPU | MASK_FPU_SET, \
537 N_("Use hardware fp") }, \
538 {"soft-float", -MASK_FPU, \
539 N_("Do not use hardware fp") }, \
540 {"soft-float", MASK_FPU_SET, NULL }, \
541 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
542 N_("Assume possible double misalignment") }, \
543 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
544 N_("Assume all doubles are aligned") }, \
545 {"impure-text", MASK_IMPURE_TEXT, \
546 N_("Pass -assert pure-text to linker") }, \
547 {"no-impure-text", -MASK_IMPURE_TEXT, \
548 N_("Do not pass -assert pure-text to linker") }, \
549 {"app-regs", MASK_APP_REGS, \
550 N_("Use ABI reserved registers") }, \
551 {"no-app-regs", -MASK_APP_REGS, \
552 N_("Do not use ABI reserved registers") }, \
553 {"hard-quad-float", MASK_HARD_QUAD, \
554 N_("Use hardware quad fp instructions") }, \
555 {"soft-quad-float", -MASK_HARD_QUAD, \
556 N_("Do not use hardware quad fp instructions") }, \
557 {"v8plus", MASK_V8PLUS, \
558 N_("Compile for v8plus ABI") }, \
559 {"no-v8plus", -MASK_V8PLUS, \
560 N_("Do not compile for v8plus ABI") }, \
562 N_("Utilize Visual Instruction Set") }, \
563 {"no-vis", -MASK_VIS, \
564 N_("Do not utilize Visual Instruction Set") }, \
565 {"ptr64", MASK_PTR64, \
566 N_("Pointers are 64-bit") }, \
567 {"ptr32", -MASK_PTR64, \
568 N_("Pointers are 32-bit") }, \
569 {"32", -MASK_64BIT, \
570 N_("Use 32-bit ABI") }, \
572 N_("Use 64-bit ABI") }, \
573 {"stack-bias", MASK_STACK_BIAS, \
574 N_("Use stack bias") }, \
575 {"no-stack-bias", -MASK_STACK_BIAS, \
576 N_("Do not use stack bias") }, \
577 {"faster-structs", MASK_FASTER_STRUCTS, \
578 N_("Use structs on stronger alignment for double-word copies") }, \
579 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
580 N_("Do not use structs on stronger alignment for double-word copies") }, \
582 N_("Optimize tail call instructions in assembler and linker") }, \
584 N_("Do not optimize tail call instructions in assembler or linker") }, \
586 { "", TARGET_DEFAULT, ""}}
588 /* MASK_APP_REGS must always be the default because that's what
589 FIXED_REGISTERS is set to and -ffixed- is processed before
590 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
591 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
593 /* This is meant to be redefined in target specific files. */
594 #define SUBTARGET_SWITCHES
597 These must match the values for the cpu attribute in sparc.md. */
598 enum processor_type {
602 PROCESSOR_SUPERSPARC,
606 PROCESSOR_HYPERSPARC,
607 PROCESSOR_SPARCLITE86X,
611 PROCESSOR_ULTRASPARC,
612 PROCESSOR_ULTRASPARC3
615 /* This is set from -m{cpu,tune}=xxx. */
616 extern enum processor_type sparc_cpu;
618 /* Recast the cpu class to be the cpu attribute.
619 Every file includes us, but not every file includes insn-attr.h. */
620 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
622 #define TARGET_OPTIONS \
624 { "cpu=", &sparc_select[1].string, \
625 N_("Use features of and schedule code for given CPU"), 0}, \
626 { "tune=", &sparc_select[2].string, \
627 N_("Schedule code for given CPU"), 0}, \
628 { "cmodel=", &sparc_cmodel_string, \
629 N_("Use given SPARC code model"), 0}, \
633 /* This is meant to be redefined in target specific files. */
634 #define SUBTARGET_OPTIONS
636 /* Support for a compile-time default CPU, et cetera. The rules are:
637 --with-cpu is ignored if -mcpu is specified.
638 --with-tune is ignored if -mtune is specified.
639 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
641 #define OPTION_DEFAULT_SPECS \
642 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
643 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
644 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }
646 /* sparc_select[0] is reserved for the default cpu. */
647 struct sparc_cpu_select
650 const char *const name;
651 const int set_tune_p;
652 const int set_arch_p;
655 extern struct sparc_cpu_select sparc_select[];
657 /* target machine storage layout */
659 /* Define this if most significant bit is lowest numbered
660 in instructions that operate on numbered bit-fields. */
661 #define BITS_BIG_ENDIAN 1
663 /* Define this if most significant byte of a word is the lowest numbered. */
664 #define BYTES_BIG_ENDIAN 1
666 /* Define this if most significant word of a multiword number is the lowest
668 #define WORDS_BIG_ENDIAN 1
670 /* Define this to set the endianness to use in libgcc2.c, which can
671 not depend on target_flags. */
672 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
673 #define LIBGCC2_WORDS_BIG_ENDIAN 0
675 #define LIBGCC2_WORDS_BIG_ENDIAN 1
678 #define MAX_BITS_PER_WORD 64
680 /* Width of a word, in units (bytes). */
681 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
683 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
685 #define MIN_UNITS_PER_WORD 4
688 /* Now define the sizes of the C data types. */
690 #define SHORT_TYPE_SIZE 16
691 #define INT_TYPE_SIZE 32
692 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
693 #define LONG_LONG_TYPE_SIZE 64
694 #define FLOAT_TYPE_SIZE 32
695 #define DOUBLE_TYPE_SIZE 64
698 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
699 Instead, it is enabled in sol2.h, because it does work under Solaris. */
700 /* Define for support of TFmode long double.
701 SPARC ABI says that long double is 4 words. */
702 #define LONG_DOUBLE_TYPE_SIZE 128
705 /* Width in bits of a pointer.
706 See also the macro `Pmode' defined below. */
707 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
709 /* If we have to extend pointers (only when TARGET_ARCH64 and not
710 TARGET_PTR64), we want to do it unsigned. This macro does nothing
711 if ptr_mode and Pmode are the same. */
712 #define POINTERS_EXTEND_UNSIGNED 1
714 /* A macro to update MODE and UNSIGNEDP when an object whose type
715 is TYPE and which has the specified mode and signedness is to be
716 stored in a register. This macro is only called when TYPE is a
718 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
720 && GET_MODE_CLASS (MODE) == MODE_INT \
721 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
724 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
725 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
726 for this value. For TARGET_ARCH64 we need it, as we don't have instructions
727 for arithmetic operations which do zero/sign extension at the same time,
728 so without this we end up with a srl/sra after every assignment to an
729 user variable, which means very very bad code. */
730 #define PROMOTE_FOR_CALL_ONLY
732 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
733 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
735 /* Boundary (in *bits*) on which stack pointer should be aligned. */
736 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
737 then sp+2047 is 128-bit aligned so sp is really only byte-aligned. */
738 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
739 /* Temporary hack until the FIXME above is fixed. This macro is used
740 only in pad_to_arg_alignment in function.c; see the comment there
741 for details about what it does. */
742 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
744 /* ALIGN FRAMES on double word boundaries */
746 #define SPARC_STACK_ALIGN(LOC) \
747 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
749 /* Allocation boundary (in *bits*) for the code of a function. */
750 #define FUNCTION_BOUNDARY 32
752 /* Alignment of field after `int : 0' in a structure. */
753 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
755 /* Every structure's size must be a multiple of this. */
756 #define STRUCTURE_SIZE_BOUNDARY 8
758 /* A bit-field declared as `int' forces `int' alignment for the struct. */
759 #define PCC_BITFIELD_TYPE_MATTERS 1
761 /* No data type wants to be aligned rounder than this. */
762 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
764 /* The best alignment to use in cases where we have a choice. */
765 #define FASTEST_ALIGNMENT 64
767 /* Define this macro as an expression for the alignment of a structure
768 (given by STRUCT as a tree node) if the alignment computed in the
769 usual way is COMPUTED and the alignment explicitly specified was
772 The default is to use SPECIFIED if it is larger; otherwise, use
773 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
774 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
775 (TARGET_FASTER_STRUCTS ? \
776 ((TREE_CODE (STRUCT) == RECORD_TYPE \
777 || TREE_CODE (STRUCT) == UNION_TYPE \
778 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
779 && TYPE_FIELDS (STRUCT) != 0 \
780 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
781 : MAX ((COMPUTED), (SPECIFIED))) \
782 : MAX ((COMPUTED), (SPECIFIED)))
784 /* Make strings word-aligned so strcpy from constants will be faster. */
785 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
786 ((TREE_CODE (EXP) == STRING_CST \
787 && (ALIGN) < FASTEST_ALIGNMENT) \
788 ? FASTEST_ALIGNMENT : (ALIGN))
790 /* Make arrays of chars word-aligned for the same reasons. */
791 #define DATA_ALIGNMENT(TYPE, ALIGN) \
792 (TREE_CODE (TYPE) == ARRAY_TYPE \
793 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
794 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
796 /* Set this nonzero if move instructions will actually fail to work
797 when given unaligned data. */
798 #define STRICT_ALIGNMENT 1
800 /* Things that must be doubleword aligned cannot go in the text section,
801 because the linker fails to align the text section enough!
802 Put them in the data section. This macro is only used in this file. */
803 #define MAX_TEXT_ALIGN 32
805 /* This forces all variables and constants to the data section when PIC.
806 This is because the SunOS 4 shared library scheme thinks everything in
807 text is a function, and patches the address to point to a loader stub. */
808 /* This is defined to zero for every system which doesn't use the a.out object
810 #ifndef SUNOS4_SHARED_LIBRARIES
811 #define SUNOS4_SHARED_LIBRARIES 0
814 /* Standard register usage. */
816 /* Number of actual hardware registers.
817 The hardware registers are assigned numbers for the compiler
818 from 0 to just below FIRST_PSEUDO_REGISTER.
819 All registers that the compiler knows about must be given numbers,
820 even those that are not normally considered general registers.
822 SPARC has 32 integer registers and 32 floating point registers.
823 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
824 accessible. We still account for them to simplify register computations
825 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
827 Register 100 is used as the integer condition code register.
828 Register 101 is used as the soft frame pointer register. */
830 #define FIRST_PSEUDO_REGISTER 102
832 #define SPARC_FIRST_FP_REG 32
833 /* Additional V9 fp regs. */
834 #define SPARC_FIRST_V9_FP_REG 64
835 #define SPARC_LAST_V9_FP_REG 95
836 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
837 #define SPARC_FIRST_V9_FCC_REG 96
838 #define SPARC_LAST_V9_FCC_REG 99
840 #define SPARC_FCC_REG 96
841 /* Integer CC reg. We don't distinguish %icc from %xcc. */
842 #define SPARC_ICC_REG 100
844 /* Nonzero if REGNO is an fp reg. */
845 #define SPARC_FP_REG_P(REGNO) \
846 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
848 /* Argument passing regs. */
849 #define SPARC_OUTGOING_INT_ARG_FIRST 8
850 #define SPARC_INCOMING_INT_ARG_FIRST 24
851 #define SPARC_FP_ARG_FIRST 32
853 /* 1 for registers that have pervasive standard uses
854 and are not available for the register allocator.
857 g1 is free to use as temporary.
858 g2-g4 are reserved for applications. Gcc normally uses them as
859 temporaries, but this can be disabled via the -mno-app-regs option.
860 g5 through g7 are reserved for the operating system.
863 g1,g5 are free to use as temporaries, and are free to use between calls
864 if the call is to an external function via the PLT.
865 g4 is free to use as a temporary in the non-embedded case.
866 g4 is reserved in the embedded case.
867 g2-g3 are reserved for applications. Gcc normally uses them as
868 temporaries, but this can be disabled via the -mno-app-regs option.
869 g6-g7 are reserved for the operating system (or application in
871 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
872 currently be a fixed register until this pattern is rewritten.
873 Register 1 is also used when restoring call-preserved registers in large
876 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
877 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
880 #define FIXED_REGISTERS \
881 {1, 0, 2, 2, 2, 2, 1, 1, \
882 0, 0, 0, 0, 0, 0, 1, 0, \
883 0, 0, 0, 0, 0, 0, 0, 0, \
884 0, 0, 0, 0, 0, 0, 1, 1, \
886 0, 0, 0, 0, 0, 0, 0, 0, \
887 0, 0, 0, 0, 0, 0, 0, 0, \
888 0, 0, 0, 0, 0, 0, 0, 0, \
889 0, 0, 0, 0, 0, 0, 0, 0, \
891 0, 0, 0, 0, 0, 0, 0, 0, \
892 0, 0, 0, 0, 0, 0, 0, 0, \
893 0, 0, 0, 0, 0, 0, 0, 0, \
894 0, 0, 0, 0, 0, 0, 0, 0, \
898 /* 1 for registers not available across function calls.
899 These must include the FIXED_REGISTERS and also any
900 registers that can be used without being saved.
901 The latter must include the registers where values are returned
902 and the register where structure-value addresses are passed.
903 Aside from that, you can include as many other registers as you like. */
905 #define CALL_USED_REGISTERS \
906 {1, 1, 1, 1, 1, 1, 1, 1, \
907 1, 1, 1, 1, 1, 1, 1, 1, \
908 0, 0, 0, 0, 0, 0, 0, 0, \
909 0, 0, 0, 0, 0, 0, 1, 1, \
911 1, 1, 1, 1, 1, 1, 1, 1, \
912 1, 1, 1, 1, 1, 1, 1, 1, \
913 1, 1, 1, 1, 1, 1, 1, 1, \
914 1, 1, 1, 1, 1, 1, 1, 1, \
916 1, 1, 1, 1, 1, 1, 1, 1, \
917 1, 1, 1, 1, 1, 1, 1, 1, \
918 1, 1, 1, 1, 1, 1, 1, 1, \
919 1, 1, 1, 1, 1, 1, 1, 1, \
923 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
924 they won't be allocated. */
926 #define CONDITIONAL_REGISTER_USAGE \
929 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
931 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
932 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
934 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
935 /* then honor it. */ \
936 if (TARGET_ARCH32 && fixed_regs[5]) \
938 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
943 for (regno = SPARC_FIRST_V9_FP_REG; \
944 regno <= SPARC_LAST_V9_FP_REG; \
946 fixed_regs[regno] = 1; \
947 /* %fcc0 is used by v8 and v9. */ \
948 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
949 regno <= SPARC_LAST_V9_FCC_REG; \
951 fixed_regs[regno] = 1; \
956 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
957 fixed_regs[regno] = 1; \
959 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
960 /* then honor it. Likewise with g3 and g4. */ \
961 if (fixed_regs[2] == 2) \
962 fixed_regs[2] = ! TARGET_APP_REGS; \
963 if (fixed_regs[3] == 2) \
964 fixed_regs[3] = ! TARGET_APP_REGS; \
965 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
966 fixed_regs[4] = ! TARGET_APP_REGS; \
967 else if (TARGET_CM_EMBMEDANY) \
969 else if (fixed_regs[4] == 2) \
974 /* Return number of consecutive hard regs needed starting at reg REGNO
975 to hold something of mode MODE.
976 This is ordinarily the length in words of a value of mode MODE
977 but can be less for certain modes in special long registers.
979 On SPARC, ordinary registers hold 32 bits worth;
980 this means both integer and floating point registers.
981 On v9, integer regs hold 64 bits worth; floating point regs hold
982 32 bits worth (this includes the new fp regs as even the odd ones are
983 included in the hard register count). */
985 #define HARD_REGNO_NREGS(REGNO, MODE) \
987 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
988 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
989 : (GET_MODE_SIZE (MODE) + 3) / 4) \
990 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
992 /* Due to the ARCH64 discrepancy above we must override this next
994 #define REGMODE_NATURAL_SIZE(MODE) \
995 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
997 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
998 See sparc.c for how we initialize this. */
999 extern const int *hard_regno_mode_classes;
1000 extern int sparc_mode_class[];
1002 /* ??? Because of the funny way we pass parameters we should allow certain
1003 ??? types of float/complex values to be in integer registers during
1004 ??? RTL generation. This only matters on arch32. */
1005 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1006 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1008 /* Value is 1 if it is a good idea to tie two pseudo registers
1009 when one has mode MODE1 and one has mode MODE2.
1010 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1011 for any hard reg, then this must be 0 for correct output.
1013 For V9: SFmode can't be combined with other float modes, because they can't
1014 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1015 registers, but SFmode will. */
1016 #define MODES_TIEABLE_P(MODE1, MODE2) \
1017 ((MODE1) == (MODE2) \
1018 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1020 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1021 || (MODE1 != SFmode && MODE2 != SFmode)))))
1023 /* Specify the registers used for certain standard purposes.
1024 The values of these macros are register numbers. */
1026 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1027 /* #define PC_REGNUM */
1029 /* Register to use for pushing function arguments. */
1030 #define STACK_POINTER_REGNUM 14
1032 /* The stack bias (amount by which the hardware register is offset by). */
1033 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1035 /* Actual top-of-stack address is 92/176 greater than the contents of the
1036 stack pointer register for !v9/v9. That is:
1037 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1038 address, and 6*4 bytes for the 6 register parameters.
1039 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1041 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
1043 /* Base register for access to local variables of the function. */
1044 #define HARD_FRAME_POINTER_REGNUM 30
1046 /* The soft frame pointer does not have the stack bias applied. */
1047 #define FRAME_POINTER_REGNUM 101
1049 /* Given the stack bias, the stack pointer isn't actually aligned. */
1050 #define INIT_EXPANDERS \
1052 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
1054 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
1055 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
1059 /* Value should be nonzero if functions must have frame pointers.
1060 Zero means the frame pointer need not be set up (and parms
1061 may be accessed via the stack pointer) in functions that seem suitable.
1062 This is computed in `reload', in reload1.c.
1063 Used in flow.c, global.c, and reload1.c. */
1064 #define FRAME_POINTER_REQUIRED \
1065 (! (leaf_function_p () && only_leaf_regs_used ()))
1067 /* Base register for access to arguments of the function. */
1068 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1070 /* Register in which static-chain is passed to a function. This must
1071 not be a register used by the prologue. */
1072 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1074 /* Register which holds offset table for position-independent
1077 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
1079 /* Pick a default value we can notice from override_options:
1081 v9: Default is off. */
1083 #define DEFAULT_PCC_STRUCT_RETURN -1
1085 /* Functions which return large structures get the address
1086 to place the wanted value at offset 64 from the frame.
1087 Must reserve 64 bytes for the in and local registers.
1088 v9: Functions which return large structures get the address to place the
1089 wanted value from an invisible first argument. */
1090 #define STRUCT_VALUE_OFFSET 64
1092 /* Define the classes of registers for register constraints in the
1093 machine description. Also define ranges of constants.
1095 One of the classes must always be named ALL_REGS and include all hard regs.
1096 If there is more than one class, another class must be named NO_REGS
1097 and contain no registers.
1099 The name GENERAL_REGS must be the name of a class (or an alias for
1100 another name such as ALL_REGS). This is the class of registers
1101 that is allowed by "g" or "r" in a register constraint.
1102 Also, registers outside this class are allocated only when
1103 instructions express preferences for them.
1105 The classes must be numbered in nondecreasing order; that is,
1106 a larger-numbered class must never be contained completely
1107 in a smaller-numbered class.
1109 For any two classes, it is very desirable that there be another
1110 class that represents their union. */
1112 /* The SPARC has various kinds of registers: general, floating point,
1113 and condition codes [well, it has others as well, but none that we
1114 care directly about].
1116 For v9 we must distinguish between the upper and lower floating point
1117 registers because the upper ones can't hold SFmode values.
1118 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1119 satisfying a group need for a class will also satisfy a single need for
1120 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1123 It is important that one class contains all the general and all the standard
1124 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1125 because reg_class_record() will bias the selection in favor of fp regs,
1126 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1127 because FP_REGS > GENERAL_REGS.
1129 It is also important that one class contain all the general and all the
1130 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1131 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1132 allocate_reload_reg() to bypass it causing an abort because the compiler
1133 thinks it doesn't have a spill reg when in fact it does.
1135 v9 also has 4 floating point condition code registers. Since we don't
1136 have a class that is the union of FPCC_REGS with either of the others,
1137 it is important that it appear first. Otherwise the compiler will die
1138 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1141 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1142 may try to use it to hold an SImode value. See register_operand.
1143 ??? Should %fcc[0123] be handled similarly?
1146 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1147 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1148 ALL_REGS, LIM_REG_CLASSES };
1150 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1152 /* Give names of register classes as strings for dump file. */
1154 #define REG_CLASS_NAMES \
1155 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1156 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1159 /* Define which registers fit in which classes.
1160 This is an initializer for a vector of HARD_REG_SET
1161 of length N_REG_CLASSES. */
1163 #define REG_CLASS_CONTENTS \
1164 {{0, 0, 0, 0}, /* NO_REGS */ \
1165 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1166 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1167 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1168 {0, -1, 0, 0}, /* FP_REGS */ \
1169 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1170 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1171 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1172 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1174 /* Defines invalid mode changes. Borrowed from pa64-regs.h.
1176 SImode loads to floating-point registers are not zero-extended.
1177 The definition for LOAD_EXTEND_OP specifies that integer loads
1178 narrower than BITS_PER_WORD will be zero-extended. As a result,
1179 we inhibit changes from SImode unless they are to a mode that is
1180 identical in size. */
1182 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1184 && (FROM) == SImode \
1185 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1186 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
1188 /* The same information, inverted:
1189 Return the class number of the smallest class containing
1190 reg number REGNO. This could be a conditional expression
1191 or could index an array. */
1193 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1195 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1197 /* This is the order in which to allocate registers normally.
1199 We put %f0-%f7 last among the float registers, so as to make it more
1200 likely that a pseudo-register which dies in the float return register
1201 area will get allocated to the float return register, thus saving a move
1202 instruction at the end of the function.
1204 Similarly for integer return value registers.
1206 We know in this case that we will not end up with a leaf function.
1208 The register allocator is given the global and out registers first
1209 because these registers are call clobbered and thus less useful to
1210 global register allocation.
1212 Next we list the local and in registers. They are not call clobbered
1213 and thus very useful for global register allocation. We list the input
1214 registers before the locals so that it is more likely the incoming
1215 arguments received in those registers can just stay there and not be
1218 #define REG_ALLOC_ORDER \
1219 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1220 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1222 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1223 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
1224 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1225 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1226 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1227 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1228 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1229 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1230 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1231 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1232 96, 97, 98, 99, /* %fcc0-3 */ \
1233 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */
1235 /* This is the order in which to allocate registers for
1236 leaf functions. If all registers can fit in the global and
1237 output registers, then we have the possibility of having a leaf
1240 The macro actually mentioned the input registers first,
1241 because they get renumbered into the output registers once
1242 we know really do have a leaf function.
1244 To be more precise, this register allocation order is used
1245 when %o7 is found to not be clobbered right before register
1246 allocation. Normally, the reason %o7 would be clobbered is
1247 due to a call which could not be transformed into a sibling
1250 As a consequence, it is possible to use the leaf register
1251 allocation order and not end up with a leaf function. We will
1252 not get suboptimal register allocation in that case because by
1253 definition of being potentially leaf, there were no function
1254 calls. Therefore, allocation order within the local register
1255 window is not critical like it is when we do have function calls. */
1257 #define REG_LEAF_ALLOC_ORDER \
1258 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1259 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1261 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1262 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1263 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1264 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1265 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1266 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1267 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1268 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1269 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1270 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1271 96, 97, 98, 99, /* %fcc0-3 */ \
1272 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
1274 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1276 extern char sparc_leaf_regs[];
1277 #define LEAF_REGISTERS sparc_leaf_regs
1279 extern char leaf_reg_remap[];
1280 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1282 /* The class value for index registers, and the one for base regs. */
1283 #define INDEX_REG_CLASS GENERAL_REGS
1284 #define BASE_REG_CLASS GENERAL_REGS
1286 /* Local macro to handle the two v9 classes of FP regs. */
1287 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1289 /* Get reg_class from a letter such as appears in the machine description.
1290 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1291 .md file for v8 and v9.
1292 'd' and 'b' are used for single and double precision VIS operations,
1294 'h' is used for V8+ 64 bit global and out registers. */
1296 #define REG_CLASS_FROM_LETTER(C) \
1298 ? ((C) == 'f' ? FP_REGS \
1299 : (C) == 'e' ? EXTRA_FP_REGS \
1300 : (C) == 'c' ? FPCC_REGS \
1301 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1302 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1303 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1305 : ((C) == 'f' ? FP_REGS \
1306 : (C) == 'e' ? FP_REGS \
1307 : (C) == 'c' ? FPCC_REGS \
1310 /* The letters I, J, K, L and M in a register constraint string
1311 can be used to stand for particular ranges of immediate operands.
1312 This macro defines what the ranges are.
1313 C is the letter, and VALUE is a constant value.
1314 Return 1 if VALUE is in the range specified by C.
1316 `I' is used for the range of constants an insn can actually contain.
1317 `J' is used for the range which is just zero (since that is R0).
1318 `K' is used for constants which can be loaded with a single sethi insn.
1319 `L' is used for the range of constants supported by the movcc insns.
1320 `M' is used for the range of constants supported by the movrcc insns.
1321 `N' is like K, but for constants wider than 32 bits.
1322 `O' is used for the range which is just 4096. */
1324 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1325 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1326 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1327 /* 10 and 11 bit immediates are only used for a few specific insns.
1328 SMALL_INT is used throughout the port so we continue to use it. */
1329 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1330 /* 13 bit immediate, considering only the low 32 bits */
1331 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
1332 (INTVAL (X), SImode)))
1333 #define SPARC_SETHI_P(X) \
1334 (((unsigned HOST_WIDE_INT) (X) \
1335 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1336 #define SPARC_SETHI32_P(X) \
1337 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1339 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1340 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1341 : (C) == 'J' ? (VALUE) == 0 \
1342 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1343 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1344 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1345 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1346 : (C) == 'O' ? (VALUE) == 4096 \
1349 /* Similar, but for floating constants, and defining letters G and H.
1350 Here VALUE is the CONST_DOUBLE rtx itself. */
1352 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1353 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1354 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1355 : (C) == 'O' ? arith_double_4096_operand (VALUE, DImode) \
1358 /* Given an rtx X being reloaded into a reg required to be
1359 in class CLASS, return the class of reg to actually use.
1360 In general this is just CLASS; but on some machines
1361 in some cases it is preferable to use a more restrictive class. */
1362 /* - We can't load constants into FP registers.
1363 - We can't load FP constants into integer registers when soft-float,
1364 because there is no soft-float pattern with a r/F constraint.
1365 - We can't load FP constants into integer registers for TFmode unless
1366 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1367 - Try and reload integer constants (symbolic or otherwise) back into
1368 registers directly, rather than having them dumped to memory. */
1370 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1372 ? ((FP_REG_CLASS_P (CLASS) \
1373 || (CLASS) == GENERAL_OR_FP_REGS \
1374 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
1375 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1377 || (GET_MODE (X) == TFmode \
1378 && ! fp_zero_operand (X, TFmode))) \
1380 : (!FP_REG_CLASS_P (CLASS) \
1381 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1386 /* Return the register class of a scratch register needed to load IN into
1387 a register of class CLASS in MODE.
1389 We need a temporary when loading/storing a HImode/QImode value
1390 between memory and the FPU registers. This can happen when combine puts
1391 a paradoxical subreg in a float/fix conversion insn.
1393 We need a temporary when loading/storing a DFmode value between
1394 unaligned memory and the upper FPU registers. */
1396 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1397 ((FP_REG_CLASS_P (CLASS) \
1398 && ((MODE) == HImode || (MODE) == QImode) \
1399 && (GET_CODE (IN) == MEM \
1400 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1401 && true_regnum (IN) == -1))) \
1403 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1404 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1405 && ! mem_min_alignment ((IN), 8)) \
1407 : (((TARGET_CM_MEDANY \
1408 && symbolic_operand ((IN), (MODE))) \
1409 || (TARGET_CM_EMBMEDANY \
1410 && text_segment_operand ((IN), (MODE)))) \
1415 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1416 ((FP_REG_CLASS_P (CLASS) \
1417 && ((MODE) == HImode || (MODE) == QImode) \
1418 && (GET_CODE (IN) == MEM \
1419 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1420 && true_regnum (IN) == -1))) \
1422 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1423 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1424 && ! mem_min_alignment ((IN), 8)) \
1426 : (((TARGET_CM_MEDANY \
1427 && symbolic_operand ((IN), (MODE))) \
1428 || (TARGET_CM_EMBMEDANY \
1429 && text_segment_operand ((IN), (MODE)))) \
1434 /* On SPARC it is not possible to directly move data between
1435 GENERAL_REGS and FP_REGS. */
1436 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1437 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1439 /* Return the stack location to use for secondary memory needed reloads.
1440 We want to use the reserved location just below the frame pointer.
1441 However, we must ensure that there is a frame, so use assign_stack_local
1442 if the frame size is zero. */
1443 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1444 (get_frame_size () == 0 \
1445 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1446 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1447 STARTING_FRAME_OFFSET)))
1449 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1450 because the movsi and movsf patterns don't handle r/f moves.
1451 For v8 we copy the default definition. */
1452 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1454 ? (GET_MODE_BITSIZE (MODE) < 32 \
1455 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1457 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1458 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1461 /* Return the maximum number of consecutive registers
1462 needed to represent mode MODE in a register of class CLASS. */
1463 /* On SPARC, this is the size of MODE in words. */
1464 #define CLASS_MAX_NREGS(CLASS, MODE) \
1465 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1466 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1468 /* Stack layout; function entry, exit and calling. */
1470 /* Define the number of register that can hold parameters.
1471 This macro is only used in other macro definitions below and in sparc.c.
1472 MODE is the mode of the argument.
1473 !v9: All args are passed in %o0-%o5.
1474 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
1475 See the description in sparc.c. */
1476 #define NPARM_REGS(MODE) \
1478 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
1481 /* Define this if pushing a word on the stack
1482 makes the stack pointer a smaller address. */
1483 #define STACK_GROWS_DOWNWARD
1485 /* Define this if the nominal address of the stack frame
1486 is at the high-address end of the local variables;
1487 that is, each additional local variable allocated
1488 goes at a more negative offset in the frame. */
1489 #define FRAME_GROWS_DOWNWARD
1491 /* Offset within stack frame to start allocating local variables at.
1492 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1493 first local allocated. Otherwise, it is the offset to the BEGINNING
1494 of the first local allocated. */
1495 /* This allows space for one TFmode floating point value. */
1496 #define STARTING_FRAME_OFFSET \
1497 (TARGET_ARCH64 ? -16 \
1498 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1500 /* If we generate an insn to push BYTES bytes,
1501 this says how many the stack pointer really advances by.
1502 On SPARC, don't define this because there are no push insns. */
1503 /* #define PUSH_ROUNDING(BYTES) */
1505 /* Offset of first parameter from the argument pointer register value.
1506 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1507 even if this function isn't going to use it.
1508 v9: This is 128 for the ins and locals. */
1509 #define FIRST_PARM_OFFSET(FNDECL) \
1510 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1512 /* Offset from the argument pointer register value to the CFA.
1513 This is different from FIRST_PARM_OFFSET because the register window
1514 comes between the CFA and the arguments. */
1515 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1517 /* When a parameter is passed in a register, stack space is still
1519 !v9: All 6 possible integer registers have backing store allocated.
1520 v9: Only space for the arguments passed is allocated. */
1521 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1522 meaning to the backend. Further, we need to be able to detect if a
1523 varargs/unprototyped function is called, as they may want to spill more
1524 registers than we've provided space. Ugly, ugly. So for now we retain
1525 all 6 slots even for v9. */
1526 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1528 /* Definitions for register elimination. */
1530 #define ELIMINABLE_REGS \
1531 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1532 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1534 /* The way this is structured, we can't eliminate SFP in favor of SP
1535 if the frame pointer is required: we want to use the SFP->HFP elimination
1536 in that case. But the test in update_eliminables doesn't know we are
1537 assuming below that we only do the former elimination. */
1538 #define CAN_ELIMINATE(FROM, TO) \
1539 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1541 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1544 if ((TO) == STACK_POINTER_REGNUM) \
1545 /* Note, we always pretend that this is a leaf function \
1546 because if it's not, there's no point in trying to \
1547 eliminate the frame pointer. If it is a leaf \
1548 function, we guessed right! */ \
1549 (OFFSET) = compute_frame_size (get_frame_size (), 1); \
1550 (OFFSET) += SPARC_STACK_BIAS; \
1553 /* Keep the stack pointer constant throughout the function.
1554 This is both an optimization and a necessity: longjmp
1555 doesn't behave itself when the stack pointer moves within
1557 #define ACCUMULATE_OUTGOING_ARGS 1
1559 /* Value is the number of bytes of arguments automatically
1560 popped when returning from a subroutine call.
1561 FUNDECL is the declaration node of the function (as a tree),
1562 FUNTYPE is the data type of the function (as a tree),
1563 or for a library call it is an identifier node for the subroutine name.
1564 SIZE is the number of bytes of arguments passed on the stack. */
1566 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1568 /* Some subroutine macros specific to this machine.
1569 When !TARGET_FPU, put float return values in the general registers,
1570 since we don't have any fp registers. */
1571 #define BASE_RETURN_VALUE_REG(MODE) \
1572 (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8)
1574 #define BASE_OUTGOING_VALUE_REG(MODE) \
1575 (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 24)
1577 #define BASE_PASSING_ARG_REG(MODE) \
1578 (TARGET_ARCH64 && TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8)
1580 /* ??? FIXME -- seems wrong for v9 structure passing... */
1581 #define BASE_INCOMING_ARG_REG(MODE) \
1582 (TARGET_ARCH64 && TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 24)
1584 /* Define this macro if the target machine has "register windows". This
1585 C expression returns the register number as seen by the called function
1586 corresponding to register number OUT as seen by the calling function.
1587 Return OUT if register number OUT is not an outbound register. */
1589 #define INCOMING_REGNO(OUT) \
1590 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1592 /* Define this macro if the target machine has "register windows". This
1593 C expression returns the register number as seen by the calling function
1594 corresponding to register number IN as seen by the called function.
1595 Return IN if register number IN is not an inbound register. */
1597 #define OUTGOING_REGNO(IN) \
1598 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1600 /* Define this macro if the target machine has register windows. This
1601 C expression returns true if the register is call-saved but is in the
1604 #define LOCAL_REGNO(REGNO) \
1605 ((REGNO) >= 16 && (REGNO) <= 31)
1607 /* Define how to find the value returned by a function.
1608 VALTYPE is the data type of the value (as a tree).
1609 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1610 otherwise, FUNC is 0. */
1612 /* On SPARC the value is found in the first "output" register. */
1614 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1615 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1617 /* But the called function leaves it in the first "input" register. */
1619 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1620 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1622 /* Define how to find the value returned by a library function
1623 assuming the value has mode MODE. */
1625 #define LIBCALL_VALUE(MODE) \
1626 function_value (NULL_TREE, (MODE), 1)
1628 /* 1 if N is a possible register number for a function value
1629 as seen by the caller.
1630 On SPARC, the first "output" reg is used for integer values,
1631 and the first floating point register is used for floating point values. */
1633 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1635 /* Define the size of space to allocate for the return value of an
1638 #define APPLY_RESULT_SIZE 16
1640 /* 1 if N is a possible register number for function argument passing.
1641 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1643 #define FUNCTION_ARG_REGNO_P(N) \
1645 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1646 : ((N) >= 8 && (N) <= 13))
1648 /* Define a data type for recording info about an argument list
1649 during the scan of that argument list. This data type should
1650 hold all necessary information about the function itself
1651 and about the args processed so far, enough to enable macros
1652 such as FUNCTION_ARG to determine where the next arg should go.
1654 On SPARC (!v9), this is a single integer, which is a number of words
1655 of arguments scanned so far (including the invisible argument,
1656 if any, which holds the structure-value-address).
1657 Thus 7 or more means all following args should go on the stack.
1659 For v9, we also need to know whether a prototype is present. */
1662 int words; /* number of words passed so far */
1663 int prototype_p; /* nonzero if a prototype is present */
1664 int libcall_p; /* nonzero if a library call */
1666 #define CUMULATIVE_ARGS struct sparc_args
1668 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1669 for a call to a function whose data type is FNTYPE.
1670 For a library call, FNTYPE is 0. */
1672 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1673 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1675 /* Update the data in CUM to advance over an argument
1676 of mode MODE and data type TYPE.
1677 TYPE is null for libcalls where that information may not be available. */
1679 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1680 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1682 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1684 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1686 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1687 || TREE_ADDRESSABLE (TYPE)))
1689 /* Determine where to put an argument to a function.
1690 Value is zero to push the argument on the stack,
1691 or a hard register in which to store the argument.
1693 MODE is the argument's machine mode.
1694 TYPE is the data type of the argument (as a tree).
1695 This is null for libcalls where that information may
1697 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1698 the preceding args and about the function being called.
1699 NAMED is nonzero if this argument is a named parameter
1700 (otherwise it is an extra parameter matching an ellipsis). */
1702 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1703 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1705 /* Define where a function finds its arguments.
1706 This is different from FUNCTION_ARG because of register windows. */
1708 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1709 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1711 /* For an arg passed partly in registers and partly in memory,
1712 this is the number of registers used.
1713 For args passed entirely in registers or entirely in memory, zero. */
1715 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1716 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1718 /* A C expression that indicates when an argument must be passed by reference.
1719 If nonzero for an argument, a copy of that argument is made in memory and a
1720 pointer to the argument is passed instead of the argument itself.
1721 The pointer is passed in whatever way is appropriate for passing a pointer
1724 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1725 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1727 /* If defined, a C expression which determines whether, and in which direction,
1728 to pad out an argument with extra space. The value should be of type
1729 `enum direction': either `upward' to pad above the argument,
1730 `downward' to pad below, or `none' to inhibit padding. */
1732 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1733 function_arg_padding ((MODE), (TYPE))
1735 /* If defined, a C expression that gives the alignment boundary, in bits,
1736 of an argument with the specified mode and type. If it is not defined,
1737 PARM_BOUNDARY is used for all arguments.
1738 For sparc64, objects requiring 16 byte alignment are passed that way. */
1740 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1742 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1743 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1744 ? 128 : PARM_BOUNDARY)
1746 /* Define the information needed to generate branch and scc insns. This is
1747 stored from the compare operation. Note that we can't use "rtx" here
1748 since it hasn't been defined! */
1750 extern GTY(()) rtx sparc_compare_op0;
1751 extern GTY(()) rtx sparc_compare_op1;
1754 /* Generate the special assembly code needed to tell the assembler whatever
1755 it might need to know about the return value of a function.
1757 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1758 information to the assembler relating to peephole optimization (done in
1761 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1762 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1764 /* Output the special assembly code needed to tell the assembler some
1765 register is used as global register variable.
1767 SPARC 64bit psABI declares registers %g2 and %g3 as application
1768 registers and %g6 and %g7 as OS registers. Any object using them
1769 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1770 and how they are used (scratch or some global variable).
1771 Linker will then refuse to link together objects which use those
1772 registers incompatibly.
1774 Unless the registers are used for scratch, two different global
1775 registers cannot be declared to the same name, so in the unlikely
1776 case of a global register variable occupying more than one register
1777 we prefix the second and following registers with .gnu.part1. etc. */
1779 extern char sparc_hard_reg_printed[8];
1781 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1782 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1784 if (TARGET_ARCH64) \
1786 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1788 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1789 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1791 if (reg == (REGNO)) \
1792 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1794 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1795 reg, reg - (REGNO), (NAME)); \
1796 sparc_hard_reg_printed[reg] = 1; \
1803 /* Emit rtl for profiling. */
1804 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1806 /* All the work done in PROFILE_HOOK, but still required. */
1807 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1809 /* Set the name of the mcount function for the system. */
1810 #define MCOUNT_FUNCTION "*mcount"
1812 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1813 the stack pointer does not matter. The value is tested only in
1814 functions that have frame pointers.
1815 No definition is equivalent to always zero. */
1817 #define EXIT_IGNORE_STACK \
1818 (get_frame_size () != 0 \
1819 || current_function_calls_alloca || current_function_outgoing_args_size)
1821 #define DELAY_SLOTS_FOR_EPILOGUE 1
1823 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
1824 eligible_for_epilogue_delay (trial, slots_filled)
1826 /* Define registers used by the epilogue and return instruction. */
1827 #define EPILOGUE_USES(REGNO) (REGNO == 31)
1829 /* Length in units of the trampoline for entering a nested function. */
1831 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1833 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1835 /* Emit RTL insns to initialize the variable parts of a trampoline.
1836 FNADDR is an RTX for the address of the function's pure code.
1837 CXT is an RTX for the static chain value for the function. */
1839 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1840 if (TARGET_ARCH64) \
1841 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1843 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1845 /* Implement `va_start' for varargs and stdarg. */
1846 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1847 sparc_va_start (valist, nextarg)
1849 /* Implement `va_arg'. */
1850 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1851 sparc_va_arg (valist, type)
1853 /* Generate RTL to flush the register windows so as to make arbitrary frames
1855 #define SETUP_FRAME_ADDRESSES() \
1856 emit_insn (gen_flush_register_windows ())
1858 /* Given an rtx for the address of a frame,
1859 return an rtx for the address of the word in the frame
1860 that holds the dynamic chain--the previous frame's address. */
1861 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1862 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1864 /* The return address isn't on the stack, it is in a register, so we can't
1865 access it from the current frame pointer. We can access it from the
1866 previous frame pointer though by reading a value from the register window
1868 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1870 /* This is the offset of the return address to the true next instruction to be
1871 executed for the current function. */
1872 #define RETURN_ADDR_OFFSET \
1873 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1875 /* The current return address is in %i7. The return address of anything
1876 farther back is in the register window save area at [%fp+60]. */
1877 /* ??? This ignores the fact that the actual return address is +8 for normal
1878 returns, and +12 for structure returns. */
1879 #define RETURN_ADDR_RTX(count, frame) \
1881 ? gen_rtx_REG (Pmode, 31) \
1882 : gen_rtx_MEM (Pmode, \
1883 memory_address (Pmode, plus_constant (frame, \
1884 15 * UNITS_PER_WORD \
1885 + SPARC_STACK_BIAS))))
1887 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1888 +12, but always using +8 is close enough for frame unwind purposes.
1889 Actually, just using %o7 is close enough for unwinding, but %o7+8
1890 is something you can return to. */
1891 #define INCOMING_RETURN_ADDR_RTX \
1892 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1893 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1895 /* The offset from the incoming value of %sp to the top of the stack frame
1896 for the current function. On sparc64, we have to account for the stack
1898 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1900 /* Describe how we implement __builtin_eh_return. */
1901 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1902 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1903 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1905 /* Select a format to encode pointers in exception handling data. CODE
1906 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1907 true if the symbol may be affected by dynamic relocations.
1909 If assembler and linker properly support .uaword %r_disp32(foo),
1910 then use PC relative 32-bit relocations instead of absolute relocs
1911 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1912 for binaries, to save memory.
1914 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1915 symbol %r_disp32() is against was not local, but .hidden. In that
1916 case, we have to use DW_EH_PE_absptr for pic personality. */
1917 #ifdef HAVE_AS_SPARC_UA_PCREL
1918 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1919 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1921 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1922 : ((TARGET_ARCH64 && ! GLOBAL) \
1923 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1926 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1928 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1929 : ((TARGET_ARCH64 && ! GLOBAL) \
1930 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1934 /* Emit a PC-relative relocation. */
1935 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1937 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1938 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1939 assemble_name (FILE, LABEL); \
1940 fputc (')', FILE); \
1944 /* Addressing modes, and classification of registers for them. */
1946 /* Macros to check register numbers against specific register classes. */
1948 /* These assume that REGNO is a hard or pseudo reg number.
1949 They give nonzero only if REGNO is a hard reg of the suitable class
1950 or a pseudo reg currently allocated to a suitable hard reg.
1951 Since they use reg_renumber, they are safe only once reg_renumber
1952 has been allocated, which happens in local-alloc.c. */
1954 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1955 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
1956 || (REGNO) == FRAME_POINTER_REGNUM \
1957 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1959 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1961 #define REGNO_OK_FOR_FP_P(REGNO) \
1962 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1963 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1964 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1966 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1967 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1969 /* Now macros that check whether X is a register and also,
1970 strictly, whether it is in a specified class.
1972 These macros are specific to the SPARC, and may be used only
1973 in code for printing assembler insns and in conditions for
1974 define_optimization. */
1976 /* 1 if X is an fp register. */
1978 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1980 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
1981 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
1983 /* Maximum number of registers that can appear in a valid memory address. */
1985 #define MAX_REGS_PER_ADDRESS 2
1987 /* Recognize any constant value that is a valid address.
1988 When PIC, we do not accept an address that would require a scratch reg
1989 to load into a register. */
1991 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1993 /* Define this, so that when PIC, reload won't try to reload invalid
1994 addresses which require two reload registers. */
1996 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1998 /* Nonzero if the constant value X is a legitimate general operand.
1999 Anything can be made to work except floating point constants.
2000 If TARGET_VIS, 0.0 can be made to work as well. */
2002 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
2004 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2005 and check its validity for a certain class.
2006 We have two alternate definitions for each of them.
2007 The usual definition accepts all pseudo regs; the other rejects
2008 them unless they have been allocated suitable hard regs.
2009 The symbol REG_OK_STRICT causes the latter definition to be used.
2011 Most source files want to accept pseudo regs in the hope that
2012 they will get allocated to the class that the insn wants them to be in.
2013 Source files for reload pass need to be strict.
2014 After reload, it makes no difference, since pseudo regs have
2015 been eliminated by then. */
2017 /* Optional extra constraints for this machine.
2019 'Q' handles floating point constants which can be moved into
2020 an integer register with a single sethi instruction.
2022 'R' handles floating point constants which can be moved into
2023 an integer register with a single mov instruction.
2025 'S' handles floating point constants which can be moved into
2026 an integer register using a high/lo_sum sequence.
2028 'T' handles memory addresses where the alignment is known to
2029 be at least 8 bytes.
2031 `U' handles all pseudo registers or a hard even numbered
2032 integer register, needed for ldd/std instructions.
2034 'W' handles the memory operand when moving operands in/out
2035 of 'e' constraint floating point registers. */
2037 #ifndef REG_OK_STRICT
2039 /* Nonzero if X is a hard reg that can be used as an index
2040 or if it is a pseudo reg. */
2041 #define REG_OK_FOR_INDEX_P(X) \
2043 || REGNO (X) == FRAME_POINTER_REGNUM \
2044 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2046 /* Nonzero if X is a hard reg that can be used as a base reg
2047 or if it is a pseudo reg. */
2048 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
2050 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
2051 'W' is like 'T' but is assumed true on arch64.
2053 Remember to accept pseudo-registers for memory constraints if reload is
2056 #define EXTRA_CONSTRAINT(OP, C) \
2057 sparc_extra_constraint_check(OP, C, 0)
2061 /* Nonzero if X is a hard reg that can be used as an index. */
2062 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2063 /* Nonzero if X is a hard reg that can be used as a base reg. */
2064 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2066 #define EXTRA_CONSTRAINT(OP, C) \
2067 sparc_extra_constraint_check(OP, C, 1)
2071 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2073 #ifdef HAVE_AS_OFFSETABLE_LO10
2074 #define USE_AS_OFFSETABLE_LO10 1
2076 #define USE_AS_OFFSETABLE_LO10 0
2079 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2080 that is a valid memory address for an instruction.
2081 The MODE argument is the machine mode for the MEM expression
2082 that wants to use this address.
2084 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2085 ordinarily. This changes a bit when generating PIC.
2087 If you change this, execute "rm explow.o recog.o reload.o". */
2089 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
2091 #define RTX_OK_FOR_BASE_P(X) \
2092 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2093 || (GET_CODE (X) == SUBREG \
2094 && GET_CODE (SUBREG_REG (X)) == REG \
2095 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2097 #define RTX_OK_FOR_INDEX_P(X) \
2098 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2099 || (GET_CODE (X) == SUBREG \
2100 && GET_CODE (SUBREG_REG (X)) == REG \
2101 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2103 #define RTX_OK_FOR_OFFSET_P(X) \
2104 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2106 #define RTX_OK_FOR_OLO10_P(X) \
2107 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2109 #ifdef REG_OK_STRICT
2110 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2112 if (legitimate_address_p (MODE, X, 1)) \
2116 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2118 if (legitimate_address_p (MODE, X, 0)) \
2123 /* Go to LABEL if ADDR (a legitimate address expression)
2124 has an effect that depends on the machine mode it is used for.
2130 is not equivalent to
2132 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
2134 because [%l7+a+1] is interpreted as the address of (a+1). */
2136 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2138 if (flag_pic == 1) \
2140 if (GET_CODE (ADDR) == PLUS) \
2142 rtx op0 = XEXP (ADDR, 0); \
2143 rtx op1 = XEXP (ADDR, 1); \
2144 if (op0 == pic_offset_table_rtx \
2145 && SYMBOLIC_CONST (op1)) \
2151 /* Try machine-dependent ways of modifying an illegitimate address
2152 to be legitimate. If we find one, return the new, valid address.
2153 This macro is used in only one place: `memory_address' in explow.c.
2155 OLDX is the address as it was before break_out_memory_refs was called.
2156 In some cases it is useful to look at this to decide what needs to be done.
2158 MODE and WIN are passed so that this macro can use
2159 GO_IF_LEGITIMATE_ADDRESS.
2161 It is always safe for this macro to do nothing. It exists to recognize
2162 opportunities to optimize the output. */
2164 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2165 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2167 (X) = legitimize_address (X, OLDX, MODE); \
2168 if (memory_address_p (MODE, X)) \
2172 /* Try a machine-dependent way of reloading an illegitimate address
2173 operand. If we find one, push the reload and jump to WIN. This
2174 macro is used in only one place: `find_reloads_address' in reload.c.
2176 For SPARC 32, we wish to handle addresses by splitting them into
2177 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2178 This cuts the number of extra insns by one.
2180 Do nothing when generating PIC code and the address is a
2181 symbolic operand or requires a scratch register. */
2183 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2185 /* Decompose SImode constants into hi+lo_sum. We do have to \
2186 rerecognize what we produce, so be careful. */ \
2187 if (CONSTANT_P (X) \
2188 && (MODE != TFmode || TARGET_ARCH64) \
2189 && GET_MODE (X) == SImode \
2190 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2192 && (symbolic_operand (X, Pmode) \
2193 || pic_address_needs_scratch (X))) \
2194 && sparc_cmodel <= CM_MEDLOW) \
2196 X = gen_rtx_LO_SUM (GET_MODE (X), \
2197 gen_rtx_HIGH (GET_MODE (X), X), X); \
2198 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2199 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2203 /* ??? 64-bit reloads. */ \
2206 /* Specify the machine mode that this machine uses
2207 for the index in the tablejump instruction. */
2208 /* If we ever implement any of the full models (such as CM_FULLANY),
2209 this has to be DImode in that case */
2210 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2211 #define CASE_VECTOR_MODE \
2212 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2214 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2215 we have to sign extend which slows things down. */
2216 #define CASE_VECTOR_MODE \
2217 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2220 /* Define as C expression which evaluates to nonzero if the tablejump
2221 instruction expects the table to contain offsets from the address of the
2223 Do not define this if the table should contain absolute addresses. */
2224 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2226 /* Define this as 1 if `char' should by default be signed; else as 0. */
2227 #define DEFAULT_SIGNED_CHAR 1
2229 /* Max number of bytes we can move from memory to memory
2230 in one reasonably fast instruction. */
2233 #if 0 /* Sun 4 has matherr, so this is no good. */
2234 /* This is the value of the error code EDOM for this machine,
2235 used by the sqrt instruction. */
2236 #define TARGET_EDOM 33
2238 /* This is how to refer to the variable errno. */
2239 #define GEN_ERRNO_RTX \
2240 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno"))
2243 /* Define if operations between registers always perform the operation
2244 on the full register even if a narrower mode is specified. */
2245 #define WORD_REGISTER_OPERATIONS
2247 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2248 will either zero-extend or sign-extend. The value of this macro should
2249 be the code that says which one of the two operations is implicitly
2250 done, NIL if none. */
2251 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2253 /* Nonzero if access to memory by bytes is slow and undesirable.
2254 For RISC chips, it means that access to memory by bytes is no
2255 better than access by words when possible, so grab a whole word
2256 and maybe make use of that. */
2257 #define SLOW_BYTE_ACCESS 1
2259 /* Define this to be nonzero if shift instructions ignore all but the low-order
2261 #define SHIFT_COUNT_TRUNCATED 1
2263 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2264 is done just by pretending it is already truncated. */
2265 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2267 /* Specify the machine mode that pointers have.
2268 After generation of rtl, the compiler makes no further distinction
2269 between pointers and any other objects of this machine mode. */
2270 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2272 /* Generate calls to memcpy, memcmp and memset. */
2273 #define TARGET_MEM_FUNCTIONS
2275 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2276 return the mode to be used for the comparison. For floating-point,
2277 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2278 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2279 processing is needed. */
2280 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2282 /* Return nonzero if MODE implies a floating point inequality can be
2283 reversed. For SPARC this is always true because we have a full
2284 compliment of ordered and unordered comparisons, but until generic
2285 code knows how to reverse it correctly we keep the old definition. */
2286 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2288 /* A function address in a call instruction for indexing purposes. */
2289 #define FUNCTION_MODE Pmode
2291 /* Define this if addresses of constant functions
2292 shouldn't be put through pseudo regs where they can be cse'd.
2293 Desirable on machines where ordinary constants are expensive
2294 but a CALL with constant address is cheap. */
2295 #define NO_FUNCTION_CSE
2297 /* alloca should avoid clobbering the old register save area. */
2298 #define SETJMP_VIA_SAVE_AREA
2300 /* The _Q_* comparison libcalls return booleans. */
2301 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2303 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
2304 that the inputs are fully consumed before the output memory is clobbered. */
2306 #define TARGET_BUGGY_QP_LIB 0
2308 /* Assume by default that we do not have the Solaris-specific conversion
2309 routines nor 64-bit integer multiply and divide routines. */
2311 #define SUN_CONVERSION_LIBFUNCS 0
2312 #define SUN_INTEGER_MULTIPLY_64 0
2314 /* Compute extra cost of moving data between one register class
2316 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2317 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2318 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2319 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2320 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2321 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
2322 || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
2324 /* Provide the cost of a branch. For pre-v9 processors we use
2325 a value of 3 to take into account the potential annulling of
2326 the delay slot (which ends up being a bubble in the pipeline slot)
2327 plus a cycle to take into consideration the instruction cache
2330 On v9 and later, which have branch prediction facilities, we set
2331 it to the depth of the pipeline as that is the cost of a
2332 mispredicted branch. */
2334 #define BRANCH_COST \
2335 ((sparc_cpu == PROCESSOR_V9 \
2336 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2338 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2341 #define PREFETCH_BLOCK \
2342 ((sparc_cpu == PROCESSOR_ULTRASPARC \
2343 || sparc_cpu == PROCESSOR_ULTRASPARC3) \
2346 #define SIMULTANEOUS_PREFETCHES \
2347 ((sparc_cpu == PROCESSOR_ULTRASPARC) \
2349 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2352 /* Control the assembler format that we output. */
2354 /* A C string constant describing how to begin a comment in the target
2355 assembler language. The compiler assumes that the comment will end at
2356 the end of the line. */
2358 #define ASM_COMMENT_START "!"
2360 /* Output to assembler file text saying following lines
2361 may contain character constants, extra white space, comments, etc. */
2363 #define ASM_APP_ON ""
2365 /* Output to assembler file text saying following lines
2366 no longer contain unusual constructs. */
2368 #define ASM_APP_OFF ""
2370 /* ??? Try to make the style consistent here (_OP?). */
2372 #define ASM_FLOAT ".single"
2373 #define ASM_DOUBLE ".double"
2374 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2376 /* How to refer to registers in assembler output.
2377 This sequence is indexed by compiler's hard-register-number (see above). */
2379 #define REGISTER_NAMES \
2380 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2381 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2382 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2383 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2384 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2385 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2386 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2387 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2388 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2389 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2390 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2391 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2392 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2394 /* Define additional names for use in asm clobbers and asm declarations. */
2396 #define ADDITIONAL_REGISTER_NAMES \
2397 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2399 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2400 can run past this up to a continuation point. Once we used 1500, but
2401 a single entry in C++ can run more than 500 bytes, due to the length of
2402 mangled symbol names. dbxout.c should really be fixed to do
2403 continuations when they are actually needed instead of trying to
2405 #define DBX_CONTIN_LENGTH 1000
2407 /* This is how to output a command to make the user-level label named NAME
2408 defined for reference from other files. */
2410 /* Globalizing directive for a label. */
2411 #define GLOBAL_ASM_OP "\t.global "
2413 /* The prefix to add to user-visible assembler symbols. */
2415 #define USER_LABEL_PREFIX "_"
2417 /* This is how to store into the string LABEL
2418 the symbol_ref name of an internal numbered label where
2419 PREFIX is the class of label and NUM is the number within the class.
2420 This is suitable for output with `assemble_name'. */
2422 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2423 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2425 /* This is how we hook in and defer the case-vector until the end of
2427 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2428 sparc_defer_case_vector ((LAB),(VEC), 0)
2430 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2431 sparc_defer_case_vector ((LAB),(VEC), 1)
2433 /* This is how to output an element of a case-vector that is absolute. */
2435 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2438 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2439 if (CASE_VECTOR_MODE == SImode) \
2440 fprintf (FILE, "\t.word\t"); \
2442 fprintf (FILE, "\t.xword\t"); \
2443 assemble_name (FILE, label); \
2444 fputc ('\n', FILE); \
2447 /* This is how to output an element of a case-vector that is relative.
2448 (SPARC uses such vectors only when generating PIC.) */
2450 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2453 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2454 if (CASE_VECTOR_MODE == SImode) \
2455 fprintf (FILE, "\t.word\t"); \
2457 fprintf (FILE, "\t.xword\t"); \
2458 assemble_name (FILE, label); \
2459 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2460 fputc ('-', FILE); \
2461 assemble_name (FILE, label); \
2462 fputc ('\n', FILE); \
2465 /* This is what to output before and after case-vector (both
2466 relative and absolute). If .subsection -1 works, we put case-vectors
2467 at the beginning of the current section. */
2469 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2471 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2472 fprintf(FILE, "\t.subsection\t-1\n")
2474 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2475 fprintf(FILE, "\t.previous\n")
2479 /* This is how to output an assembler line
2480 that says to advance the location counter
2481 to a multiple of 2**LOG bytes. */
2483 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2485 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2487 /* This is how to output an assembler line that says to advance
2488 the location counter to a multiple of 2**LOG bytes using the
2489 "nop" instruction as padding. */
2490 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
2492 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG)))
2494 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2495 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2497 /* This says how to output an assembler line
2498 to define a global common symbol. */
2500 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2501 ( fputs ("\t.common ", (FILE)), \
2502 assemble_name ((FILE), (NAME)), \
2503 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
2505 /* This says how to output an assembler line to define a local common
2508 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2509 ( fputs ("\t.reserve ", (FILE)), \
2510 assemble_name ((FILE), (NAME)), \
2511 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
2512 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2514 /* A C statement (sans semicolon) to output to the stdio stream
2515 FILE the assembler definition of uninitialized global DECL named
2516 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2517 Try to use asm_output_aligned_bss to implement this macro. */
2519 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2521 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2524 #define IDENT_ASM_OP "\t.ident\t"
2526 /* Output #ident as a .ident. */
2528 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2529 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2531 /* Emit a dtp-relative reference to a TLS variable. */
2534 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
2535 sparc_output_dwarf_dtprel (FILE, SIZE, X)
2538 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2539 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' \
2540 || (CHAR) == '(' || (CHAR) == '_' || (CHAR) == '&')
2542 /* Print operand X (an rtx) in assembler syntax to file FILE.
2543 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2544 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2546 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2548 /* Print a memory address as an operand to reference that memory location. */
2550 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2551 { register rtx base, index = 0; \
2553 register rtx addr = ADDR; \
2554 if (GET_CODE (addr) == REG) \
2555 fputs (reg_names[REGNO (addr)], FILE); \
2556 else if (GET_CODE (addr) == PLUS) \
2558 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2559 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2560 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2561 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2563 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2564 if (GET_CODE (base) == LO_SUM) \
2566 if (! USE_AS_OFFSETABLE_LO10 \
2568 || TARGET_CM_MEDMID) \
2570 output_operand (XEXP (base, 0), 0); \
2571 fputs ("+%lo(", FILE); \
2572 output_address (XEXP (base, 1)); \
2573 fprintf (FILE, ")+%d", offset); \
2577 fputs (reg_names[REGNO (base)], FILE); \
2579 fprintf (FILE, "%+d", offset); \
2580 else if (GET_CODE (index) == REG) \
2581 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2582 else if (GET_CODE (index) == SYMBOL_REF \
2583 || GET_CODE (index) == CONST) \
2584 fputc ('+', FILE), output_addr_const (FILE, index); \
2588 else if (GET_CODE (addr) == MINUS \
2589 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2591 output_addr_const (FILE, XEXP (addr, 0)); \
2592 fputs ("-(", FILE); \
2593 output_addr_const (FILE, XEXP (addr, 1)); \
2594 fputs ("-.)", FILE); \
2596 else if (GET_CODE (addr) == LO_SUM) \
2598 output_operand (XEXP (addr, 0), 0); \
2599 if (TARGET_CM_MEDMID) \
2600 fputs ("+%l44(", FILE); \
2602 fputs ("+%lo(", FILE); \
2603 output_address (XEXP (addr, 1)); \
2604 fputc (')', FILE); \
2606 else if (flag_pic && GET_CODE (addr) == CONST \
2607 && GET_CODE (XEXP (addr, 0)) == MINUS \
2608 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2609 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2610 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2612 addr = XEXP (addr, 0); \
2613 output_addr_const (FILE, XEXP (addr, 0)); \
2614 /* Group the args of the second CONST in parenthesis. */ \
2615 fputs ("-(", FILE); \
2616 /* Skip past the second CONST--it does nothing for us. */\
2617 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2618 /* Close the parenthesis. */ \
2619 fputc (')', FILE); \
2623 output_addr_const (FILE, addr); \
2628 #define TARGET_TLS 1
2630 #define TARGET_TLS 0
2632 #define TARGET_SUN_TLS TARGET_TLS
2633 #define TARGET_GNU_TLS 0
2635 /* Define the codes that are matched by predicates in sparc.c. */
2637 #define PREDICATE_CODES \
2638 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2639 {"const1_operand", {CONST_INT}}, \
2640 {"fp_zero_operand", {CONST_DOUBLE}}, \
2641 {"fp_register_operand", {SUBREG, REG}}, \
2642 {"intreg_operand", {SUBREG, REG}}, \
2643 {"fcc_reg_operand", {REG}}, \
2644 {"fcc0_reg_operand", {REG}}, \
2645 {"icc_or_fcc_reg_operand", {REG}}, \
2646 {"restore_operand", {REG}}, \
2647 {"call_operand", {MEM}}, \
2648 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
2649 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
2650 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2651 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2652 {"label_ref_operand", {LABEL_REF}}, \
2653 {"sp64_medium_pic_operand", {CONST}}, \
2654 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
2655 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
2656 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
2657 {"splittable_symbolic_memory_operand", {MEM}}, \
2658 {"splittable_immediate_memory_operand", {MEM}}, \
2659 {"eq_or_neq", {EQ, NE}}, \
2660 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
2661 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2662 {"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2663 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
2664 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
2665 {"cc_arithop", {AND, IOR, XOR}}, \
2666 {"cc_arithopn", {AND, IOR}}, \
2667 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2668 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
2669 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2670 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
2671 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2672 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2673 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2674 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2675 {"small_int", {CONST_INT}}, \
2676 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
2677 {"uns_small_int", {CONST_INT}}, \
2678 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
2679 {"clobbered_register", {REG}}, \
2680 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
2681 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
2682 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, \
2683 {"tgd_symbolic_operand", {SYMBOL_REF}}, \
2684 {"tld_symbolic_operand", {SYMBOL_REF}}, \
2685 {"tie_symbolic_operand", {SYMBOL_REF}}, \
2686 {"tle_symbolic_operand", {SYMBOL_REF}},
2688 /* The number of Pmode words for the setjmp buffer. */
2689 #define JMP_BUF_SIZE 12
2691 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)
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