1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
29 /* #define SPARC_BI_ARCH */
31 /* Macro used later in this file to determine default architecture. */
32 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
34 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
35 architectures to compile for. We allow targets to choose compile time or
38 #if defined(__sparcv9) || defined(__arch64__)
39 #define TARGET_ARCH32 0
41 #define TARGET_ARCH32 1
45 #define TARGET_ARCH32 (! TARGET_64BIT)
47 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
48 #endif /* SPARC_BI_ARCH */
49 #endif /* IN_LIBGCC2 */
50 #define TARGET_ARCH64 (! TARGET_ARCH32)
52 /* Code model selection.
53 -mcmodel is used to select the v9 code model.
54 Different code models aren't supported for v7/8 code.
56 TARGET_CM_32: 32 bit address space, top 32 bits = 0,
57 pointers are 32 bits. Note that this isn't intended
60 TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
61 avoid generating %uhi and %ulo terms,
64 TARGET_CM_MEDMID: 64 bit address space.
65 The executable must be in the low 16 TB of memory.
66 This corresponds to the low 44 bits, and the %[hml]44
67 relocs are used. The text segment has a maximum size
70 TARGET_CM_MEDANY: 64 bit address space.
71 The text and data segments have a maximum size of 31
72 bits and may be located anywhere. The maximum offset
73 from any instruction to the label _GLOBAL_OFFSET_TABLE_
76 TARGET_CM_EMBMEDANY: 64 bit address space.
77 The text and data segments have a maximum size of 31 bits
78 and may be located anywhere. Register %g4 contains
79 the start address of the data segment.
90 /* Value of -mcmodel specified by user. */
91 extern const char *sparc_cmodel_string;
93 extern enum cmodel sparc_cmodel;
95 /* V9 code model selection. */
96 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
97 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
98 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
99 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
101 #define SPARC_DEFAULT_CMODEL CM_32
103 /* This is call-clobbered in the normal ABI, but is reserved in the
104 home grown (aka upward compatible) embedded ABI. */
105 #define EMBMEDANY_BASE_REG "%g4"
107 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
108 and specified by the user via --with-cpu=foo.
109 This specifies the cpu implementation, not the architecture size. */
110 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
112 #define TARGET_CPU_sparc 0
113 #define TARGET_CPU_v7 0 /* alias for previous */
114 #define TARGET_CPU_sparclet 1
115 #define TARGET_CPU_sparclite 2
116 #define TARGET_CPU_v8 3 /* generic v8 implementation */
117 #define TARGET_CPU_supersparc 4
118 #define TARGET_CPU_hypersparc 5
119 #define TARGET_CPU_sparc86x 6
120 #define TARGET_CPU_sparclite86x 6
121 #define TARGET_CPU_v9 7 /* generic v9 implementation */
122 #define TARGET_CPU_sparcv9 7 /* alias */
123 #define TARGET_CPU_sparc64 7 /* alias */
124 #define TARGET_CPU_ultrasparc 8
126 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
127 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
129 #define CPP_CPU32_DEFAULT_SPEC ""
130 #define ASM_CPU32_DEFAULT_SPEC ""
132 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
133 /* ??? What does Sun's CC pass? */
134 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
135 /* ??? It's not clear how other assemblers will handle this, so by default
136 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
137 is handled in sol2.h. */
138 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
140 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
141 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
142 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
147 #define CPP_CPU64_DEFAULT_SPEC ""
148 #define ASM_CPU64_DEFAULT_SPEC ""
150 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
151 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
152 #define CPP_CPU32_DEFAULT_SPEC ""
153 #define ASM_CPU32_DEFAULT_SPEC ""
156 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
157 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
158 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
161 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
162 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
163 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
166 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
167 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
168 #define ASM_CPU32_DEFAULT_SPEC ""
171 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
172 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
173 #define ASM_CPU32_DEFAULT_SPEC ""
176 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
177 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
178 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
183 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
184 Unrecognized value in TARGET_CPU_DEFAULT.
189 #define CPP_CPU_DEFAULT_SPEC \
190 (DEFAULT_ARCH32_P ? "\
191 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
192 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
194 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
195 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
197 #define ASM_CPU_DEFAULT_SPEC \
198 (DEFAULT_ARCH32_P ? "\
199 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
200 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
202 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
203 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
206 #else /* !SPARC_BI_ARCH */
208 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
209 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
211 #endif /* !SPARC_BI_ARCH */
213 /* Define macros to distinguish architectures. */
215 /* Common CPP definitions used by CPP_SPEC amongst the various targets
216 for handling -mcpu=xxx switches. */
217 #define CPP_CPU_SPEC "\
218 %{msoft-float:-D_SOFT_FLOAT} \
220 %{msparclite:-D__sparclite__} \
221 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
222 %{mv8:-D__sparc_v8__} \
223 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
224 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
225 %{mcpu=sparclite:-D__sparclite__} \
226 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
227 %{mcpu=v8:-D__sparc_v8__} \
228 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
229 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
230 %{mcpu=sparclite86x:-D__sparclite86x__} \
231 %{mcpu=v9:-D__sparc_v9__} \
232 %{mcpu=ultrasparc:-D__sparc_v9__} \
233 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
236 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
237 the right varags.h file when bootstrapping. */
238 /* ??? It's not clear what value we want to use for -Acpu/machine for
239 sparc64 in 32 bit environments, so for now we only use `sparc64' in
240 64 bit environments. */
244 #define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \
245 -D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
246 #define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
247 -D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
251 #define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
252 #define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
256 #define CPP_ARCH_DEFAULT_SPEC \
257 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
259 #define CPP_ARCH_SPEC "\
260 %{m32:%(cpp_arch32)} \
261 %{m64:%(cpp_arch64)} \
262 %{!m32:%{!m64:%(cpp_arch_default)}} \
265 /* Macros to distinguish endianness. */
266 #define CPP_ENDIAN_SPEC "\
267 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
268 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
270 /* Macros to distinguish the particular subtarget. */
271 #define CPP_SUBTARGET_SPEC ""
273 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
275 /* Prevent error on `-sun4' and `-target sun4' options. */
276 /* This used to translate -dalign to -malign, but that is no good
277 because it can't turn off the usual meaning of making debugging dumps. */
278 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
279 ??? Delete support for -m<cpu> for 2.9. */
282 %{sun4:} %{target:} \
283 %{mcypress:-mcpu=cypress} \
284 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
285 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
288 /* Override in target specific files. */
289 #define ASM_CPU_SPEC "\
290 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
291 %{msparclite:-Asparclite} \
292 %{mf930:-Asparclite} %{mf934:-Asparclite} \
293 %{mcpu=sparclite:-Asparclite} \
294 %{mcpu=sparclite86x:-Asparclite} \
295 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
296 %{mv8plus:-Av8plus} \
298 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
299 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
302 /* Word size selection, among other things.
303 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
305 #define ASM_ARCH32_SPEC "-32"
306 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
307 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
309 #define ASM_ARCH64_SPEC "-64"
311 #define ASM_ARCH_DEFAULT_SPEC \
312 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
314 #define ASM_ARCH_SPEC "\
315 %{m32:%(asm_arch32)} \
316 %{m64:%(asm_arch64)} \
317 %{!m32:%{!m64:%(asm_arch_default)}} \
320 #ifdef HAVE_AS_RELAX_OPTION
321 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
323 #define ASM_RELAX_SPEC ""
326 /* Special flags to the Sun-4 assembler when using pipe for input. */
329 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
330 %(asm_cpu) %(asm_relax)"
332 /* This macro defines names of additional specifications to put in the specs
333 that can be used in various specifications like CC1_SPEC. Its definition
334 is an initializer with a subgrouping for each command option.
336 Each subgrouping contains a string constant, that defines the
337 specification name, and a string constant that used by the GNU CC driver
340 Do not define this macro if it does not need to do anything. */
342 #define EXTRA_SPECS \
343 { "cpp_cpu", CPP_CPU_SPEC }, \
344 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
345 { "cpp_arch32", CPP_ARCH32_SPEC }, \
346 { "cpp_arch64", CPP_ARCH64_SPEC }, \
347 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
348 { "cpp_arch", CPP_ARCH_SPEC }, \
349 { "cpp_endian", CPP_ENDIAN_SPEC }, \
350 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
351 { "asm_cpu", ASM_CPU_SPEC }, \
352 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
353 { "asm_arch32", ASM_ARCH32_SPEC }, \
354 { "asm_arch64", ASM_ARCH64_SPEC }, \
355 { "asm_relax", ASM_RELAX_SPEC }, \
356 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
357 { "asm_arch", ASM_ARCH_SPEC }, \
358 SUBTARGET_EXTRA_SPECS
360 #define SUBTARGET_EXTRA_SPECS
363 #define NO_BUILTIN_PTRDIFF_TYPE
364 #define NO_BUILTIN_SIZE_TYPE
366 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
367 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
369 /* ??? This should be 32 bits for v9 but what can we do? */
370 #define WCHAR_TYPE "short unsigned int"
371 #define WCHAR_TYPE_SIZE 16
372 #define MAX_WCHAR_TYPE_SIZE 16
374 /* Show we can debug even without a frame pointer. */
375 #define CAN_DEBUG_WITHOUT_FP
377 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
378 code into the rtl. Also, if we are profiling, we cannot eliminate
379 the frame pointer (because the return address will get smashed). */
381 #define OVERRIDE_OPTIONS \
383 if (profile_flag || profile_arc_flag) \
387 const char *const pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC";\
388 warning ("%s and profiling conflict: disabling %s", \
389 pic_string, pic_string); \
392 flag_omit_frame_pointer = 0; \
394 sparc_override_options (); \
395 SUBTARGET_OVERRIDE_OPTIONS; \
398 /* This is meant to be redefined in the host dependent files. */
399 #define SUBTARGET_OVERRIDE_OPTIONS
401 /* Generate DBX debugging information. */
403 #define DBX_DEBUGGING_INFO
405 /* Run-time compilation parameters selecting different hardware subsets. */
407 extern int target_flags;
409 /* Nonzero if we should generate code to use the fpu. */
411 #define TARGET_FPU (target_flags & MASK_FPU)
413 /* Nonzero if we should use function_epilogue(). Otherwise, we
414 use fast return insns, but lose some generality. */
415 #define MASK_EPILOGUE 2
416 #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
418 /* Nonzero if we should assume that double pointers might be unaligned.
419 This can happen when linking gcc compiled code with other compilers,
420 because the ABI only guarantees 4 byte alignment. */
421 #define MASK_UNALIGNED_DOUBLES 4
422 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
424 /* Nonzero means that we should generate code for a v8 sparc. */
426 #define TARGET_V8 (target_flags & MASK_V8)
428 /* Nonzero means that we should generate code for a sparclite.
429 This enables the sparclite specific instructions, but does not affect
430 whether FPU instructions are emitted. */
431 #define MASK_SPARCLITE 0x10
432 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
434 /* Nonzero if we're compiling for the sparclet. */
435 #define MASK_SPARCLET 0x20
436 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
438 /* Nonzero if we're compiling for v9 sparc.
439 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
440 the word size is 64. */
442 #define TARGET_V9 (target_flags & MASK_V9)
444 /* Non-zero to generate code that uses the instructions deprecated in
445 the v9 architecture. This option only applies to v9 systems. */
446 /* ??? This isn't user selectable yet. It's used to enable such insns
447 on 32 bit v9 systems and for the moment they're permanently disabled
448 on 64 bit v9 systems. */
449 #define MASK_DEPRECATED_V8_INSNS 0x80
450 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
452 /* Mask of all CPU selection flags. */
454 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
456 /* Non-zero means don't pass `-assert pure-text' to the linker. */
457 #define MASK_IMPURE_TEXT 0x100
458 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
460 /* Nonzero means that we should generate code using a flat register window
461 model, i.e. no save/restore instructions are generated, which is
462 compatible with normal sparc code.
463 The frame pointer is %i7 instead of %fp. */
464 #define MASK_FLAT 0x200
465 #define TARGET_FLAT (target_flags & MASK_FLAT)
467 /* Nonzero means use the registers that the Sparc ABI reserves for
468 application software. This must be the default to coincide with the
469 setting in FIXED_REGISTERS. */
470 #define MASK_APP_REGS 0x400
471 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
473 /* Option to select how quad word floating point is implemented.
474 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
475 Otherwise, we use the SPARC ABI quad library functions. */
476 #define MASK_HARD_QUAD 0x800
477 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
479 /* Non-zero on little-endian machines. */
480 /* ??? Little endian support currently only exists for sparclet-aout and
481 sparc64-elf configurations. May eventually want to expand the support
482 to all targets, but for now it's kept local to only those two. */
483 #define MASK_LITTLE_ENDIAN 0x1000
484 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
486 /* 0x2000, 0x4000 are unused */
488 /* Nonzero if pointers are 64 bits. */
489 #define MASK_PTR64 0x8000
490 #define TARGET_PTR64 (target_flags & MASK_PTR64)
492 /* Nonzero if generating code to run in a 64 bit environment.
493 This is intended to only be used by TARGET_ARCH{32,64} as they are the
494 mechanism used to control compile time or run time selection. */
495 #define MASK_64BIT 0x10000
496 #define TARGET_64BIT (target_flags & MASK_64BIT)
498 /* 0x20000,0x40000 unused */
500 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
501 adding 2047 to %sp. This option is for v9 only and is the default. */
502 #define MASK_STACK_BIAS 0x80000
503 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
505 /* 0x100000,0x200000 unused */
507 /* Non-zero means -m{,no-}fpu was passed on the command line. */
508 #define MASK_FPU_SET 0x400000
509 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
511 /* Use the UltraSPARC Visual Instruction Set extensions. */
512 #define MASK_VIS 0x1000000
513 #define TARGET_VIS (target_flags & MASK_VIS)
515 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
516 the current out and global registers and Linux 2.2+ as well. */
517 #define MASK_V8PLUS 0x2000000
518 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
520 /* Force a the fastest alignment on structures to take advantage of
522 #define MASK_FASTER_STRUCTS 0x4000000
523 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
525 /* Use IEEE quad long double. */
526 #define MASK_LONG_DOUBLE_128 0x8000000
527 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
529 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
530 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
531 to get high 32 bits. False in V8+ or V9 because multiply stores
532 a 64 bit result in a register. */
534 #define TARGET_HARD_MUL32 \
535 ((TARGET_V8 || TARGET_SPARCLITE \
536 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
537 && ! TARGET_V8PLUS && TARGET_ARCH32)
539 #define TARGET_HARD_MUL \
540 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
541 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
544 /* Macro to define tables used to set the flags.
545 This is a list in braces of pairs in braces,
546 each pair being { "NAME", VALUE }
547 where VALUE is the bits to set or minus the bits to clear.
548 An empty string NAME is used to identify the default VALUE. */
550 #define TARGET_SWITCHES \
551 { {"fpu", MASK_FPU | MASK_FPU_SET, \
552 N_("Use hardware fp") }, \
553 {"no-fpu", -MASK_FPU, \
554 N_("Do not use hardware fp") }, \
555 {"no-fpu", MASK_FPU_SET, NULL, }, \
556 {"hard-float", MASK_FPU | MASK_FPU_SET, \
557 N_("Use hardware fp") }, \
558 {"soft-float", -MASK_FPU, \
559 N_("Do not use hardware fp") }, \
560 {"soft-float", MASK_FPU_SET, NULL }, \
561 {"epilogue", MASK_EPILOGUE, \
562 N_("Use function_epilogue()") }, \
563 {"no-epilogue", -MASK_EPILOGUE, \
564 N_("Do not use function_epilogue()") }, \
565 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
566 N_("Assume possible double misalignment") }, \
567 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
568 N_("Assume all doubles are aligned") }, \
569 {"impure-text", MASK_IMPURE_TEXT, \
570 N_("Pass -assert pure-text to linker") }, \
571 {"no-impure-text", -MASK_IMPURE_TEXT, \
572 N_("Do not pass -assert pure-text to linker") }, \
573 {"flat", MASK_FLAT, \
574 N_("Use flat register window model") }, \
575 {"no-flat", -MASK_FLAT, \
576 N_("Do not use flat register window model") }, \
577 {"app-regs", MASK_APP_REGS, \
578 N_("Use ABI reserved registers") }, \
579 {"no-app-regs", -MASK_APP_REGS, \
580 N_("Do not use ABI reserved registers") }, \
581 {"hard-quad-float", MASK_HARD_QUAD, \
582 N_("Use hardware quad fp instructions") }, \
583 {"soft-quad-float", -MASK_HARD_QUAD, \
584 N_("Do not use hardware quad fp instructions") }, \
585 {"v8plus", MASK_V8PLUS, \
586 N_("Compile for v8plus ABI") }, \
587 {"no-v8plus", -MASK_V8PLUS, \
588 N_("Do not compile for v8plus ABI") }, \
590 N_("Utilize Visual Instruction Set") }, \
591 {"no-vis", -MASK_VIS, \
592 N_("Do not utilize Visual Instruction Set") }, \
593 /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
595 N_("Optimize for Cypress processors") }, \
597 N_("Optimize for SparcLite processors") }, \
599 N_("Optimize for F930 processors") }, \
601 N_("Optimize for F934 processors") }, \
603 N_("Use V8 Sparc ISA") }, \
605 N_("Optimize for SuperSparc processors") }, \
606 /* End of deprecated options. */ \
607 {"ptr64", MASK_PTR64, \
608 N_("Pointers are 64-bit") }, \
609 {"ptr32", -MASK_PTR64, \
610 N_("Pointers are 32-bit") }, \
611 {"32", -MASK_64BIT, \
612 N_("Use 32-bit ABI") }, \
614 N_("Use 64-bit ABI") }, \
615 {"stack-bias", MASK_STACK_BIAS, \
616 N_("Use stack bias") }, \
617 {"no-stack-bias", -MASK_STACK_BIAS, \
618 N_("Do not use stack bias") }, \
619 {"faster-structs", MASK_FASTER_STRUCTS, \
620 N_("Use structs on stronger alignment for double-word copies") }, \
621 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
622 N_("Do not use structs on stronger alignment for double-word copies") }, \
624 N_("Optimize tail call instructions in assembler and linker") }, \
626 N_("Do not optimize tail call instructions in assembler or linker") }, \
628 { "", TARGET_DEFAULT, ""}}
630 /* MASK_APP_REGS must always be the default because that's what
631 FIXED_REGISTERS is set to and -ffixed- is processed before
632 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
633 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
635 /* This is meant to be redefined in target specific files. */
636 #define SUBTARGET_SWITCHES
639 These must match the values for the cpu attribute in sparc.md. */
640 enum processor_type {
644 PROCESSOR_SUPERSPARC,
648 PROCESSOR_HYPERSPARC,
649 PROCESSOR_SPARCLITE86X,
656 /* This is set from -m{cpu,tune}=xxx. */
657 extern enum processor_type sparc_cpu;
659 /* Recast the cpu class to be the cpu attribute.
660 Every file includes us, but not every file includes insn-attr.h. */
661 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
663 #define TARGET_OPTIONS \
665 { "cpu=", &sparc_select[1].string, \
666 N_("Use features of and schedule code for given CPU") }, \
667 { "tune=", &sparc_select[2].string, \
668 N_("Schedule code for given CPU") }, \
669 { "cmodel=", &sparc_cmodel_string, \
670 N_("Use given Sparc code model") }, \
674 /* This is meant to be redefined in target specific files. */
675 #define SUBTARGET_OPTIONS
677 /* sparc_select[0] is reserved for the default cpu. */
678 struct sparc_cpu_select
681 const char *const name;
682 const int set_tune_p;
683 const int set_arch_p;
686 extern struct sparc_cpu_select sparc_select[];
688 /* target machine storage layout */
690 /* Define for cross-compilation to a sparc target with no TFmode from a host
691 with a different float format (e.g. VAX). */
692 #define REAL_ARITHMETIC
694 /* Define this if most significant bit is lowest numbered
695 in instructions that operate on numbered bit-fields. */
696 #define BITS_BIG_ENDIAN 1
698 /* Define this if most significant byte of a word is the lowest numbered. */
699 #define BYTES_BIG_ENDIAN 1
701 /* Define this if most significant word of a multiword number is the lowest
703 #define WORDS_BIG_ENDIAN 1
705 /* Define this to set the endianness to use in libgcc2.c, which can
706 not depend on target_flags. */
707 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
708 #define LIBGCC2_WORDS_BIG_ENDIAN 0
710 #define LIBGCC2_WORDS_BIG_ENDIAN 1
713 /* number of bits in an addressable storage unit */
714 #define BITS_PER_UNIT 8
716 /* Width in bits of a "word", which is the contents of a machine register.
717 Note that this is not necessarily the width of data type `int';
718 if using 16-bit ints on a 68000, this would still be 32.
719 But on a machine with 16-bit registers, this would be 16. */
720 #define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32)
721 #define MAX_BITS_PER_WORD 64
723 /* Width of a word, in units (bytes). */
724 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
725 #define MIN_UNITS_PER_WORD 4
727 /* Now define the sizes of the C data types. */
729 #define SHORT_TYPE_SIZE 16
730 #define INT_TYPE_SIZE 32
731 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
732 #define LONG_LONG_TYPE_SIZE 64
733 #define FLOAT_TYPE_SIZE 32
734 #define DOUBLE_TYPE_SIZE 64
737 #define MAX_LONG_TYPE_SIZE 64
741 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
742 Instead, it is enabled in sol2.h, because it does work under Solaris. */
743 /* Define for support of TFmode long double and REAL_ARITHMETIC.
744 Sparc ABI says that long double is 4 words. */
745 #define LONG_DOUBLE_TYPE_SIZE 128
748 /* Width in bits of a pointer.
749 See also the macro `Pmode' defined below. */
750 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
752 /* If we have to extend pointers (only when TARGET_ARCH64 and not
753 TARGET_PTR64), we want to do it unsigned. This macro does nothing
754 if ptr_mode and Pmode are the same. */
755 #define POINTERS_EXTEND_UNSIGNED 1
757 /* A macro to update MODE and UNSIGNEDP when an object whose type
758 is TYPE and which has the specified mode and signedness is to be
759 stored in a register. This macro is only called when TYPE is a
761 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
763 && GET_MODE_CLASS (MODE) == MODE_INT \
764 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
767 /* Define this macro if the promotion described by PROMOTE_MODE
768 should also be done for outgoing function arguments. */
769 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
770 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
772 #define PROMOTE_FUNCTION_ARGS
774 /* Define this macro if the promotion described by PROMOTE_MODE
775 should also be done for the return value of functions.
776 If this macro is defined, FUNCTION_VALUE must perform the same
777 promotions done by PROMOTE_MODE. */
778 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
779 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
781 #define PROMOTE_FUNCTION_RETURN
783 /* Define this macro if the promotion described by PROMOTE_MODE
784 should _only_ be performed for outgoing function arguments or
785 function return values, as specified by PROMOTE_FUNCTION_ARGS
786 and PROMOTE_FUNCTION_RETURN, respectively. */
787 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
788 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
789 for this value. For TARGET_ARCH64 we need it, as we don't have instructions
790 for arithmetic operations which do zero/sign extension at the same time,
791 so without this we end up with a srl/sra after every assignment to an
792 user variable, which means very very bad code. */
793 #define PROMOTE_FOR_CALL_ONLY
795 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
796 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
798 /* Boundary (in *bits*) on which stack pointer should be aligned. */
799 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
801 /* ALIGN FRAMES on double word boundaries */
803 #define SPARC_STACK_ALIGN(LOC) \
804 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
806 /* Allocation boundary (in *bits*) for the code of a function. */
807 #define FUNCTION_BOUNDARY 32
809 /* Alignment of field after `int : 0' in a structure. */
810 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
812 /* Every structure's size must be a multiple of this. */
813 #define STRUCTURE_SIZE_BOUNDARY 8
815 /* A bitfield declared as `int' forces `int' alignment for the struct. */
816 #define PCC_BITFIELD_TYPE_MATTERS 1
818 /* No data type wants to be aligned rounder than this. */
819 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
821 /* The best alignment to use in cases where we have a choice. */
822 #define FASTEST_ALIGNMENT 64
824 /* Define this macro as an expression for the alignment of a structure
825 (given by STRUCT as a tree node) if the alignment computed in the
826 usual way is COMPUTED and the alignment explicitly specified was
829 The default is to use SPECIFIED if it is larger; otherwise, use
830 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
831 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
832 (TARGET_FASTER_STRUCTS ? \
833 ((TREE_CODE (STRUCT) == RECORD_TYPE \
834 || TREE_CODE (STRUCT) == UNION_TYPE \
835 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
836 && TYPE_FIELDS (STRUCT) != 0 \
837 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
838 : MAX ((COMPUTED), (SPECIFIED))) \
839 : MAX ((COMPUTED), (SPECIFIED)))
841 /* Make strings word-aligned so strcpy from constants will be faster. */
842 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
843 ((TREE_CODE (EXP) == STRING_CST \
844 && (ALIGN) < FASTEST_ALIGNMENT) \
845 ? FASTEST_ALIGNMENT : (ALIGN))
847 /* Make arrays of chars word-aligned for the same reasons. */
848 #define DATA_ALIGNMENT(TYPE, ALIGN) \
849 (TREE_CODE (TYPE) == ARRAY_TYPE \
850 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
851 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
853 /* Set this nonzero if move instructions will actually fail to work
854 when given unaligned data. */
855 #define STRICT_ALIGNMENT 1
857 /* Things that must be doubleword aligned cannot go in the text section,
858 because the linker fails to align the text section enough!
859 Put them in the data section. This macro is only used in this file. */
860 #define MAX_TEXT_ALIGN 32
862 /* This forces all variables and constants to the data section when PIC.
863 This is because the SunOS 4 shared library scheme thinks everything in
864 text is a function, and patches the address to point to a loader stub. */
865 /* This is defined to zero for every system which doesn't use the a.out object
867 #ifndef SUNOS4_SHARED_LIBRARIES
868 #define SUNOS4_SHARED_LIBRARIES 0
872 /* Use text section for a constant
873 unless we need more alignment than that offers. */
874 /* This is defined differently for v9 in a cover file. */
875 #define SELECT_RTX_SECTION(MODE, X, ALIGN) \
877 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
878 && ! (flag_pic && (symbolic_operand ((X), (MODE)) || SUNOS4_SHARED_LIBRARIES))) \
884 /* Standard register usage. */
886 /* Number of actual hardware registers.
887 The hardware registers are assigned numbers for the compiler
888 from 0 to just below FIRST_PSEUDO_REGISTER.
889 All registers that the compiler knows about must be given numbers,
890 even those that are not normally considered general registers.
892 SPARC has 32 integer registers and 32 floating point registers.
893 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
894 accessible. We still account for them to simplify register computations
895 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
897 Register 100 is used as the integer condition code register.
898 Register 101 is used as the soft frame pointer register. */
900 #define FIRST_PSEUDO_REGISTER 102
902 #define SPARC_FIRST_FP_REG 32
903 /* Additional V9 fp regs. */
904 #define SPARC_FIRST_V9_FP_REG 64
905 #define SPARC_LAST_V9_FP_REG 95
906 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
907 #define SPARC_FIRST_V9_FCC_REG 96
908 #define SPARC_LAST_V9_FCC_REG 99
910 #define SPARC_FCC_REG 96
911 /* Integer CC reg. We don't distinguish %icc from %xcc. */
912 #define SPARC_ICC_REG 100
914 /* Nonzero if REGNO is an fp reg. */
915 #define SPARC_FP_REG_P(REGNO) \
916 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
918 /* Argument passing regs. */
919 #define SPARC_OUTGOING_INT_ARG_FIRST 8
920 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
921 #define SPARC_FP_ARG_FIRST 32
923 /* 1 for registers that have pervasive standard uses
924 and are not available for the register allocator.
927 g1 is free to use as temporary.
928 g2-g4 are reserved for applications. Gcc normally uses them as
929 temporaries, but this can be disabled via the -mno-app-regs option.
930 g5 through g7 are reserved for the operating system.
933 g1,g5 are free to use as temporaries, and are free to use between calls
934 if the call is to an external function via the PLT.
935 g4 is free to use as a temporary in the non-embedded case.
936 g4 is reserved in the embedded case.
937 g2-g3 are reserved for applications. Gcc normally uses them as
938 temporaries, but this can be disabled via the -mno-app-regs option.
939 g6-g7 are reserved for the operating system (or application in
941 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
942 currently be a fixed register until this pattern is rewritten.
943 Register 1 is also used when restoring call-preserved registers in large
946 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
947 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
950 #define FIXED_REGISTERS \
951 {1, 0, 2, 2, 2, 2, 1, 1, \
952 0, 0, 0, 0, 0, 0, 1, 0, \
953 0, 0, 0, 0, 0, 0, 0, 0, \
954 0, 0, 0, 0, 0, 0, 1, 1, \
956 0, 0, 0, 0, 0, 0, 0, 0, \
957 0, 0, 0, 0, 0, 0, 0, 0, \
958 0, 0, 0, 0, 0, 0, 0, 0, \
959 0, 0, 0, 0, 0, 0, 0, 0, \
961 0, 0, 0, 0, 0, 0, 0, 0, \
962 0, 0, 0, 0, 0, 0, 0, 0, \
963 0, 0, 0, 0, 0, 0, 0, 0, \
964 0, 0, 0, 0, 0, 0, 0, 0, \
968 /* 1 for registers not available across function calls.
969 These must include the FIXED_REGISTERS and also any
970 registers that can be used without being saved.
971 The latter must include the registers where values are returned
972 and the register where structure-value addresses are passed.
973 Aside from that, you can include as many other registers as you like. */
975 #define CALL_USED_REGISTERS \
976 {1, 1, 1, 1, 1, 1, 1, 1, \
977 1, 1, 1, 1, 1, 1, 1, 1, \
978 0, 0, 0, 0, 0, 0, 0, 0, \
979 0, 0, 0, 0, 0, 0, 1, 1, \
981 1, 1, 1, 1, 1, 1, 1, 1, \
982 1, 1, 1, 1, 1, 1, 1, 1, \
983 1, 1, 1, 1, 1, 1, 1, 1, \
984 1, 1, 1, 1, 1, 1, 1, 1, \
986 1, 1, 1, 1, 1, 1, 1, 1, \
987 1, 1, 1, 1, 1, 1, 1, 1, \
988 1, 1, 1, 1, 1, 1, 1, 1, \
989 1, 1, 1, 1, 1, 1, 1, 1, \
993 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
994 they won't be allocated. */
996 #define CONDITIONAL_REGISTER_USAGE \
1001 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1002 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1004 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
1005 /* then honour it. */ \
1006 if (TARGET_ARCH32 && fixed_regs[5]) \
1007 fixed_regs[5] = 1; \
1008 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
1009 fixed_regs[5] = 0; \
1013 for (regno = SPARC_FIRST_V9_FP_REG; \
1014 regno <= SPARC_LAST_V9_FP_REG; \
1016 fixed_regs[regno] = 1; \
1017 /* %fcc0 is used by v8 and v9. */ \
1018 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
1019 regno <= SPARC_LAST_V9_FCC_REG; \
1021 fixed_regs[regno] = 1; \
1026 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
1027 fixed_regs[regno] = 1; \
1029 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
1030 /* then honour it. Likewise with g3 and g4. */ \
1031 if (fixed_regs[2] == 2) \
1032 fixed_regs[2] = ! TARGET_APP_REGS; \
1033 if (fixed_regs[3] == 2) \
1034 fixed_regs[3] = ! TARGET_APP_REGS; \
1035 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
1036 fixed_regs[4] = ! TARGET_APP_REGS; \
1037 else if (TARGET_CM_EMBMEDANY) \
1038 fixed_regs[4] = 1; \
1039 else if (fixed_regs[4] == 2) \
1040 fixed_regs[4] = 0; \
1043 /* Let the compiler believe the frame pointer is still \
1044 %fp, but output it as %i7. */ \
1045 fixed_regs[31] = 1; \
1046 reg_names[HARD_FRAME_POINTER_REGNUM] = "%i7"; \
1047 /* Disable leaf functions */ \
1048 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \
1053 /* Return number of consecutive hard regs needed starting at reg REGNO
1054 to hold something of mode MODE.
1055 This is ordinarily the length in words of a value of mode MODE
1056 but can be less for certain modes in special long registers.
1058 On SPARC, ordinary registers hold 32 bits worth;
1059 this means both integer and floating point registers.
1060 On v9, integer regs hold 64 bits worth; floating point regs hold
1061 32 bits worth (this includes the new fp regs as even the odd ones are
1062 included in the hard register count). */
1064 #define HARD_REGNO_NREGS(REGNO, MODE) \
1066 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
1067 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
1068 : (GET_MODE_SIZE (MODE) + 3) / 4) \
1069 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1071 /* Due to the ARCH64 descrepancy above we must override this next
1073 #define REGMODE_NATURAL_SIZE(MODE) \
1074 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
1076 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1077 See sparc.c for how we initialize this. */
1078 extern const int *hard_regno_mode_classes;
1079 extern int sparc_mode_class[];
1081 /* ??? Because of the funny way we pass parameters we should allow certain
1082 ??? types of float/complex values to be in integer registers during
1083 ??? RTL generation. This only matters on arch32. */
1084 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1085 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1087 /* Value is 1 if it is a good idea to tie two pseudo registers
1088 when one has mode MODE1 and one has mode MODE2.
1089 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1090 for any hard reg, then this must be 0 for correct output.
1092 For V9: SFmode can't be combined with other float modes, because they can't
1093 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1094 registers, but SFmode will. */
1095 #define MODES_TIEABLE_P(MODE1, MODE2) \
1096 ((MODE1) == (MODE2) \
1097 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1099 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1100 || (MODE1 != SFmode && MODE2 != SFmode)))))
1102 /* Specify the registers used for certain standard purposes.
1103 The values of these macros are register numbers. */
1105 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1106 /* #define PC_REGNUM */
1108 /* Register to use for pushing function arguments. */
1109 #define STACK_POINTER_REGNUM 14
1111 /* The stack bias (amount by which the hardware register is offset by). */
1112 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1114 /* Actual top-of-stack address is 92/176 greater than the contents of the
1115 stack pointer register for !v9/v9. That is:
1116 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1117 address, and 6*4 bytes for the 6 register parameters.
1118 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1120 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
1122 /* Base register for access to local variables of the function. */
1123 #define HARD_FRAME_POINTER_REGNUM 30
1125 /* The soft frame pointer does not have the stack bias applied. */
1126 #define FRAME_POINTER_REGNUM 101
1128 /* Given the stack bias, the stack pointer isn't actually aligned. */
1129 #define INIT_EXPANDERS \
1131 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
1133 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
1134 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
1138 /* Value should be nonzero if functions must have frame pointers.
1139 Zero means the frame pointer need not be set up (and parms
1140 may be accessed via the stack pointer) in functions that seem suitable.
1141 This is computed in `reload', in reload1.c.
1142 Used in flow.c, global.c, and reload1.c.
1144 Being a non-leaf function does not mean a frame pointer is needed in the
1145 flat window model. However, the debugger won't be able to backtrace through
1147 #define FRAME_POINTER_REQUIRED \
1149 ? (current_function_calls_alloca \
1150 || current_function_varargs \
1151 || !leaf_function_p ()) \
1152 : ! (leaf_function_p () && only_leaf_regs_used ()))
1154 /* C statement to store the difference between the frame pointer
1155 and the stack pointer values immediately after the function prologue.
1157 Note, we always pretend that this is a leaf function because if
1158 it's not, there's no point in trying to eliminate the
1159 frame pointer. If it is a leaf function, we guessed right! */
1160 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
1161 ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \
1162 : compute_frame_size (get_frame_size (), 1)))
1164 /* Base register for access to arguments of the function. */
1165 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1167 /* Register in which static-chain is passed to a function. This must
1168 not be a register used by the prologue. */
1169 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1171 /* Register which holds offset table for position-independent
1174 #define PIC_OFFSET_TABLE_REGNUM 23
1176 /* Pick a default value we can notice from override_options:
1178 v9: Default is off. */
1180 #define DEFAULT_PCC_STRUCT_RETURN -1
1182 /* Sparc ABI says that quad-precision floats and all structures are returned
1184 For v9: unions <= 32 bytes in size are returned in int regs,
1185 structures up to 32 bytes are returned in int and fp regs. */
1187 #define RETURN_IN_MEMORY(TYPE) \
1189 ? (TYPE_MODE (TYPE) == BLKmode \
1190 || TYPE_MODE (TYPE) == TFmode \
1191 || TYPE_MODE (TYPE) == TCmode) \
1192 : (TYPE_MODE (TYPE) == BLKmode \
1193 && (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 32))
1195 /* Functions which return large structures get the address
1196 to place the wanted value at offset 64 from the frame.
1197 Must reserve 64 bytes for the in and local registers.
1198 v9: Functions which return large structures get the address to place the
1199 wanted value from an invisible first argument. */
1200 /* Used only in other #defines in this file. */
1201 #define STRUCT_VALUE_OFFSET 64
1203 #define STRUCT_VALUE \
1206 : gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1207 STRUCT_VALUE_OFFSET)))
1209 #define STRUCT_VALUE_INCOMING \
1212 : gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, \
1213 STRUCT_VALUE_OFFSET)))
1215 /* Define the classes of registers for register constraints in the
1216 machine description. Also define ranges of constants.
1218 One of the classes must always be named ALL_REGS and include all hard regs.
1219 If there is more than one class, another class must be named NO_REGS
1220 and contain no registers.
1222 The name GENERAL_REGS must be the name of a class (or an alias for
1223 another name such as ALL_REGS). This is the class of registers
1224 that is allowed by "g" or "r" in a register constraint.
1225 Also, registers outside this class are allocated only when
1226 instructions express preferences for them.
1228 The classes must be numbered in nondecreasing order; that is,
1229 a larger-numbered class must never be contained completely
1230 in a smaller-numbered class.
1232 For any two classes, it is very desirable that there be another
1233 class that represents their union. */
1235 /* The SPARC has various kinds of registers: general, floating point,
1236 and condition codes [well, it has others as well, but none that we
1237 care directly about].
1239 For v9 we must distinguish between the upper and lower floating point
1240 registers because the upper ones can't hold SFmode values.
1241 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1242 satisfying a group need for a class will also satisfy a single need for
1243 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1246 It is important that one class contains all the general and all the standard
1247 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1248 because reg_class_record() will bias the selection in favor of fp regs,
1249 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1250 because FP_REGS > GENERAL_REGS.
1252 It is also important that one class contain all the general and all the
1253 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1254 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1255 allocate_reload_reg() to bypass it causing an abort because the compiler
1256 thinks it doesn't have a spill reg when in fact it does.
1258 v9 also has 4 floating point condition code registers. Since we don't
1259 have a class that is the union of FPCC_REGS with either of the others,
1260 it is important that it appear first. Otherwise the compiler will die
1261 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1264 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1265 may try to use it to hold an SImode value. See register_operand.
1266 ??? Should %fcc[0123] be handled similarly?
1269 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1270 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1271 ALL_REGS, LIM_REG_CLASSES };
1273 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1275 /* Give names of register classes as strings for dump file. */
1277 #define REG_CLASS_NAMES \
1278 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1279 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1282 /* Define which registers fit in which classes.
1283 This is an initializer for a vector of HARD_REG_SET
1284 of length N_REG_CLASSES. */
1286 #define REG_CLASS_CONTENTS \
1287 {{0, 0, 0, 0}, /* NO_REGS */ \
1288 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1289 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1290 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1291 {0, -1, 0, 0}, /* FP_REGS */ \
1292 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1293 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1294 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1295 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1297 /* The same information, inverted:
1298 Return the class number of the smallest class containing
1299 reg number REGNO. This could be a conditional expression
1300 or could index an array. */
1302 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1304 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1306 /* This is the order in which to allocate registers normally.
1308 We put %f0/%f1 last among the float registers, so as to make it more
1309 likely that a pseudo-register which dies in the float return register
1310 will get allocated to the float return register, thus saving a move
1311 instruction at the end of the function. */
1313 #define REG_ALLOC_ORDER \
1314 { 8, 9, 10, 11, 12, 13, 2, 3, \
1315 15, 16, 17, 18, 19, 20, 21, 22, \
1316 23, 24, 25, 26, 27, 28, 29, 31, \
1317 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
1318 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1319 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1320 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1321 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1322 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1323 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1324 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1325 32, 33, /* %f0,%f1 */ \
1326 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
1327 1, 4, 5, 6, 7, 0, 14, 30, 101}
1329 /* This is the order in which to allocate registers for
1330 leaf functions. If all registers can fit in the "gi" registers,
1331 then we have the possibility of having a leaf function. */
1333 #define REG_LEAF_ALLOC_ORDER \
1334 { 2, 3, 24, 25, 26, 27, 28, 29, \
1336 15, 8, 9, 10, 11, 12, 13, \
1337 16, 17, 18, 19, 20, 21, 22, 23, \
1338 34, 35, 36, 37, 38, 39, \
1339 40, 41, 42, 43, 44, 45, 46, 47, \
1340 48, 49, 50, 51, 52, 53, 54, 55, \
1341 56, 57, 58, 59, 60, 61, 62, 63, \
1342 64, 65, 66, 67, 68, 69, 70, 71, \
1343 72, 73, 74, 75, 76, 77, 78, 79, \
1344 80, 81, 82, 83, 84, 85, 86, 87, \
1345 88, 89, 90, 91, 92, 93, 94, 95, \
1347 96, 97, 98, 99, 100, \
1350 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1352 extern char sparc_leaf_regs[];
1353 #define LEAF_REGISTERS sparc_leaf_regs
1355 extern const char leaf_reg_remap[];
1356 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1358 /* The class value for index registers, and the one for base regs. */
1359 #define INDEX_REG_CLASS GENERAL_REGS
1360 #define BASE_REG_CLASS GENERAL_REGS
1362 /* Local macro to handle the two v9 classes of FP regs. */
1363 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1365 /* Get reg_class from a letter such as appears in the machine description.
1366 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1367 .md file for v8 and v9.
1368 'd' and 'b' are used for single and double precision VIS operations,
1370 'h' is used for V8+ 64 bit global and out registers. */
1372 #define REG_CLASS_FROM_LETTER(C) \
1374 ? ((C) == 'f' ? FP_REGS \
1375 : (C) == 'e' ? EXTRA_FP_REGS \
1376 : (C) == 'c' ? FPCC_REGS \
1377 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1378 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1379 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1381 : ((C) == 'f' ? FP_REGS \
1382 : (C) == 'e' ? FP_REGS \
1383 : (C) == 'c' ? FPCC_REGS \
1386 /* The letters I, J, K, L and M in a register constraint string
1387 can be used to stand for particular ranges of immediate operands.
1388 This macro defines what the ranges are.
1389 C is the letter, and VALUE is a constant value.
1390 Return 1 if VALUE is in the range specified by C.
1392 `I' is used for the range of constants an insn can actually contain.
1393 `J' is used for the range which is just zero (since that is R0).
1394 `K' is used for constants which can be loaded with a single sethi insn.
1395 `L' is used for the range of constants supported by the movcc insns.
1396 `M' is used for the range of constants supported by the movrcc insns.
1397 `N' is like K, but for constants wider than 32 bits. */
1399 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1400 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1401 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1402 /* 10 and 11 bit immediates are only used for a few specific insns.
1403 SMALL_INT is used throughout the port so we continue to use it. */
1404 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1405 /* 13 bit immediate, considering only the low 32 bits */
1406 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
1407 (INTVAL (X), SImode)))
1408 #define SPARC_SETHI_P(X) \
1409 (((unsigned HOST_WIDE_INT) (X) \
1410 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1411 #define SPARC_SETHI32_P(X) \
1412 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1414 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1415 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1416 : (C) == 'J' ? (VALUE) == 0 \
1417 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1418 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1419 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1420 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1423 /* Similar, but for floating constants, and defining letters G and H.
1424 Here VALUE is the CONST_DOUBLE rtx itself. */
1426 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1427 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1428 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1431 /* Given an rtx X being reloaded into a reg required to be
1432 in class CLASS, return the class of reg to actually use.
1433 In general this is just CLASS; but on some machines
1434 in some cases it is preferable to use a more restrictive class. */
1435 /* - We can't load constants into FP registers.
1436 - We can't load FP constants into integer registers when soft-float,
1437 because there is no soft-float pattern with a r/F constraint.
1438 - We can't load FP constants into integer registers for TFmode unless
1439 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1440 - Try and reload integer constants (symbolic or otherwise) back into
1441 registers directly, rather than having them dumped to memory. */
1443 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1445 ? ((FP_REG_CLASS_P (CLASS) \
1446 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1448 || (GET_MODE (X) == TFmode \
1449 && ! fp_zero_operand (X, TFmode))) \
1451 : (!FP_REG_CLASS_P (CLASS) \
1452 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1457 /* Return the register class of a scratch register needed to load IN into
1458 a register of class CLASS in MODE.
1460 We need a temporary when loading/storing a HImode/QImode value
1461 between memory and the FPU registers. This can happen when combine puts
1462 a paradoxical subreg in a float/fix conversion insn. */
1464 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1465 ((FP_REG_CLASS_P (CLASS) \
1466 && ((MODE) == HImode || (MODE) == QImode) \
1467 && (GET_CODE (IN) == MEM \
1468 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1469 && true_regnum (IN) == -1))) \
1471 : (((TARGET_CM_MEDANY \
1472 && symbolic_operand ((IN), (MODE))) \
1473 || (TARGET_CM_EMBMEDANY \
1474 && text_segment_operand ((IN), (MODE)))) \
1479 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1480 ((FP_REG_CLASS_P (CLASS) \
1481 && ((MODE) == HImode || (MODE) == QImode) \
1482 && (GET_CODE (IN) == MEM \
1483 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1484 && true_regnum (IN) == -1))) \
1486 : (((TARGET_CM_MEDANY \
1487 && symbolic_operand ((IN), (MODE))) \
1488 || (TARGET_CM_EMBMEDANY \
1489 && text_segment_operand ((IN), (MODE)))) \
1494 /* On SPARC it is not possible to directly move data between
1495 GENERAL_REGS and FP_REGS. */
1496 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1497 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1499 /* Return the stack location to use for secondary memory needed reloads.
1500 We want to use the reserved location just below the frame pointer.
1501 However, we must ensure that there is a frame, so use assign_stack_local
1502 if the frame size is zero. */
1503 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1504 (get_frame_size () == 0 \
1505 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1506 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1507 STARTING_FRAME_OFFSET)))
1509 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1510 because the movsi and movsf patterns don't handle r/f moves.
1511 For v8 we copy the default definition. */
1512 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1514 ? (GET_MODE_BITSIZE (MODE) < 32 \
1515 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1517 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1518 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1521 /* Return the maximum number of consecutive registers
1522 needed to represent mode MODE in a register of class CLASS. */
1523 /* On SPARC, this is the size of MODE in words. */
1524 #define CLASS_MAX_NREGS(CLASS, MODE) \
1525 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1526 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1528 /* Stack layout; function entry, exit and calling. */
1530 /* Define the number of register that can hold parameters.
1531 This macro is only used in other macro definitions below and in sparc.c.
1532 MODE is the mode of the argument.
1533 !v9: All args are passed in %o0-%o5.
1534 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
1535 See the description in sparc.c. */
1536 #define NPARM_REGS(MODE) \
1538 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
1541 /* Define this if pushing a word on the stack
1542 makes the stack pointer a smaller address. */
1543 #define STACK_GROWS_DOWNWARD
1545 /* Define this if the nominal address of the stack frame
1546 is at the high-address end of the local variables;
1547 that is, each additional local variable allocated
1548 goes at a more negative offset in the frame. */
1549 #define FRAME_GROWS_DOWNWARD
1551 /* Offset within stack frame to start allocating local variables at.
1552 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1553 first local allocated. Otherwise, it is the offset to the BEGINNING
1554 of the first local allocated. */
1555 /* This allows space for one TFmode floating point value. */
1556 #define STARTING_FRAME_OFFSET \
1557 (TARGET_ARCH64 ? -16 \
1558 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1560 /* If we generate an insn to push BYTES bytes,
1561 this says how many the stack pointer really advances by.
1562 On SPARC, don't define this because there are no push insns. */
1563 /* #define PUSH_ROUNDING(BYTES) */
1565 /* Offset of first parameter from the argument pointer register value.
1566 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1567 even if this function isn't going to use it.
1568 v9: This is 128 for the ins and locals. */
1569 #define FIRST_PARM_OFFSET(FNDECL) \
1570 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1572 /* Offset from the argument pointer register value to the CFA.
1573 This is different from FIRST_PARM_OFFSET because the register window
1574 comes between the CFA and the arguments. */
1575 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1577 /* When a parameter is passed in a register, stack space is still
1579 !v9: All 6 possible integer registers have backing store allocated.
1580 v9: Only space for the arguments passed is allocated. */
1581 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1582 meaning to the backend. Further, we need to be able to detect if a
1583 varargs/unprototyped function is called, as they may want to spill more
1584 registers than we've provided space. Ugly, ugly. So for now we retain
1585 all 6 slots even for v9. */
1586 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1588 /* Definitions for register elimination. */
1589 /* ??? In TARGET_FLAT mode we needn't have a hard frame pointer. */
1591 #define ELIMINABLE_REGS \
1592 {{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
1594 #define CAN_ELIMINATE(FROM, TO) 1
1596 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1597 ((OFFSET) = SPARC_STACK_BIAS)
1599 /* Keep the stack pointer constant throughout the function.
1600 This is both an optimization and a necessity: longjmp
1601 doesn't behave itself when the stack pointer moves within
1603 #define ACCUMULATE_OUTGOING_ARGS 1
1605 /* Value is the number of bytes of arguments automatically
1606 popped when returning from a subroutine call.
1607 FUNDECL is the declaration node of the function (as a tree),
1608 FUNTYPE is the data type of the function (as a tree),
1609 or for a library call it is an identifier node for the subroutine name.
1610 SIZE is the number of bytes of arguments passed on the stack. */
1612 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1614 /* Some subroutine macros specific to this machine.
1615 When !TARGET_FPU, put float return values in the general registers,
1616 since we don't have any fp registers. */
1617 #define BASE_RETURN_VALUE_REG(MODE) \
1619 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1620 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1622 #define BASE_OUTGOING_VALUE_REG(MODE) \
1624 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1625 : TARGET_FLAT ? 8 : 24) \
1626 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1627 : (TARGET_FLAT ? 8 : 24)))
1629 #define BASE_PASSING_ARG_REG(MODE) \
1631 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1634 /* ??? FIXME -- seems wrong for v9 structure passing... */
1635 #define BASE_INCOMING_ARG_REG(MODE) \
1637 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1638 : TARGET_FLAT ? 8 : 24) \
1639 : (TARGET_FLAT ? 8 : 24))
1641 /* Define this macro if the target machine has "register windows". This
1642 C expression returns the register number as seen by the called function
1643 corresponding to register number OUT as seen by the calling function.
1644 Return OUT if register number OUT is not an outbound register. */
1646 #define INCOMING_REGNO(OUT) \
1647 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1649 /* Define this macro if the target machine has "register windows". This
1650 C expression returns the register number as seen by the calling function
1651 corresponding to register number IN as seen by the called function.
1652 Return IN if register number IN is not an inbound register. */
1654 #define OUTGOING_REGNO(IN) \
1655 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1657 /* Define this macro if the target machine has register windows. This
1658 C expression returns true if the register is call-saved but is in the
1661 #define LOCAL_REGNO(REGNO) \
1662 (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31)
1664 /* Define how to find the value returned by a function.
1665 VALTYPE is the data type of the value (as a tree).
1666 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1667 otherwise, FUNC is 0. */
1669 /* On SPARC the value is found in the first "output" register. */
1671 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1672 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1674 /* But the called function leaves it in the first "input" register. */
1676 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1677 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1679 /* Define how to find the value returned by a library function
1680 assuming the value has mode MODE. */
1682 #define LIBCALL_VALUE(MODE) \
1683 function_value (NULL_TREE, (MODE), 1)
1685 /* 1 if N is a possible register number for a function value
1686 as seen by the caller.
1687 On SPARC, the first "output" reg is used for integer values,
1688 and the first floating point register is used for floating point values. */
1690 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1692 /* Define the size of space to allocate for the return value of an
1695 #define APPLY_RESULT_SIZE 16
1697 /* 1 if N is a possible register number for function argument passing.
1698 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1700 #define FUNCTION_ARG_REGNO_P(N) \
1702 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1703 : ((N) >= 8 && (N) <= 13))
1705 /* Define a data type for recording info about an argument list
1706 during the scan of that argument list. This data type should
1707 hold all necessary information about the function itself
1708 and about the args processed so far, enough to enable macros
1709 such as FUNCTION_ARG to determine where the next arg should go.
1711 On SPARC (!v9), this is a single integer, which is a number of words
1712 of arguments scanned so far (including the invisible argument,
1713 if any, which holds the structure-value-address).
1714 Thus 7 or more means all following args should go on the stack.
1716 For v9, we also need to know whether a prototype is present. */
1719 int words; /* number of words passed so far */
1720 int prototype_p; /* non-zero if a prototype is present */
1721 int libcall_p; /* non-zero if a library call */
1723 #define CUMULATIVE_ARGS struct sparc_args
1725 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1726 for a call to a function whose data type is FNTYPE.
1727 For a library call, FNTYPE is 0. */
1729 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1730 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT));
1732 /* Update the data in CUM to advance over an argument
1733 of mode MODE and data type TYPE.
1734 TYPE is null for libcalls where that information may not be available. */
1736 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1737 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1739 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1741 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1743 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1744 || TREE_ADDRESSABLE (TYPE)))
1746 /* Determine where to put an argument to a function.
1747 Value is zero to push the argument on the stack,
1748 or a hard register in which to store the argument.
1750 MODE is the argument's machine mode.
1751 TYPE is the data type of the argument (as a tree).
1752 This is null for libcalls where that information may
1754 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1755 the preceding args and about the function being called.
1756 NAMED is nonzero if this argument is a named parameter
1757 (otherwise it is an extra parameter matching an ellipsis). */
1759 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1760 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1762 /* Define where a function finds its arguments.
1763 This is different from FUNCTION_ARG because of register windows. */
1765 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1766 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1768 /* For an arg passed partly in registers and partly in memory,
1769 this is the number of registers used.
1770 For args passed entirely in registers or entirely in memory, zero. */
1772 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1773 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1775 /* A C expression that indicates when an argument must be passed by reference.
1776 If nonzero for an argument, a copy of that argument is made in memory and a
1777 pointer to the argument is passed instead of the argument itself.
1778 The pointer is passed in whatever way is appropriate for passing a pointer
1781 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1782 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1784 /* If defined, a C expression which determines whether, and in which direction,
1785 to pad out an argument with extra space. The value should be of type
1786 `enum direction': either `upward' to pad above the argument,
1787 `downward' to pad below, or `none' to inhibit padding. */
1789 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1790 function_arg_padding ((MODE), (TYPE))
1792 /* If defined, a C expression that gives the alignment boundary, in bits,
1793 of an argument with the specified mode and type. If it is not defined,
1794 PARM_BOUNDARY is used for all arguments.
1795 For sparc64, objects requiring 16 byte alignment are passed that way. */
1797 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1799 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1800 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1801 ? 128 : PARM_BOUNDARY)
1803 /* Define the information needed to generate branch and scc insns. This is
1804 stored from the compare operation. Note that we can't use "rtx" here
1805 since it hasn't been defined! */
1807 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1810 /* Generate the special assembly code needed to tell the assembler whatever
1811 it might need to know about the return value of a function.
1813 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1814 information to the assembler relating to peephole optimization (done in
1817 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1818 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1820 /* Output the special assembly code needed to tell the assembler some
1821 register is used as global register variable.
1823 SPARC 64bit psABI declares registers %g2 and %g3 as application
1824 registers and %g6 and %g7 as OS registers. Any object using them
1825 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1826 and how they are used (scratch or some global variable).
1827 Linker will then refuse to link together objects which use those
1828 registers incompatibly.
1830 Unless the registers are used for scratch, two different global
1831 registers cannot be declared to the same name, so in the unlikely
1832 case of a global register variable occupying more than one register
1833 we prefix the second and following registers with .gnu.part1. etc. */
1835 extern char sparc_hard_reg_printed[8];
1837 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1838 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1840 if (TARGET_ARCH64) \
1842 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1844 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1845 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1847 if (reg == (REGNO)) \
1848 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1850 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1851 reg, reg - (REGNO), (NAME)); \
1852 sparc_hard_reg_printed[reg] = 1; \
1859 /* Output assembler code to FILE to increment profiler label # LABELNO
1860 for profiling a function entry. */
1862 #define FUNCTION_PROFILER(FILE, LABELNO) \
1863 sparc_function_profiler(FILE, LABELNO)
1865 /* Set the name of the mcount function for the system. */
1867 #define MCOUNT_FUNCTION "*mcount"
1869 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1870 the stack pointer does not matter. The value is tested only in
1871 functions that have frame pointers.
1872 No definition is equivalent to always zero. */
1874 #define EXIT_IGNORE_STACK \
1875 (get_frame_size () != 0 \
1876 || current_function_calls_alloca || current_function_outgoing_args_size)
1878 #define DELAY_SLOTS_FOR_EPILOGUE \
1879 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
1880 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
1881 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
1882 : eligible_for_epilogue_delay (trial, slots_filled))
1884 /* Define registers used by the epilogue and return instruction. */
1885 #define EPILOGUE_USES(REGNO) \
1886 (!TARGET_FLAT && REGNO == 31)
1888 /* Length in units of the trampoline for entering a nested function. */
1890 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1892 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1894 /* Emit RTL insns to initialize the variable parts of a trampoline.
1895 FNADDR is an RTX for the address of the function's pure code.
1896 CXT is an RTX for the static chain value for the function. */
1898 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1899 if (TARGET_ARCH64) \
1900 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1902 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1904 /* Generate necessary RTL for __builtin_saveregs(). */
1906 #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs ()
1908 /* Implement `va_start' for varargs and stdarg. */
1909 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1910 sparc_va_start (stdarg, valist, nextarg)
1912 /* Implement `va_arg'. */
1913 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1914 sparc_va_arg (valist, type)
1916 /* Define this macro if the location where a function argument is passed
1917 depends on whether or not it is a named argument.
1919 This macro controls how the NAMED argument to FUNCTION_ARG
1920 is set for varargs and stdarg functions. With this macro defined,
1921 the NAMED argument is always true for named arguments, and false for
1922 unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS
1923 is defined, then all arguments are treated as named. Otherwise, all named
1924 arguments except the last are treated as named.
1925 For the v9 we want NAMED to mean what it says it means. */
1927 #define STRICT_ARGUMENT_NAMING TARGET_V9
1929 /* We do not allow sibling calls if -mflat, nor
1930 we do not allow indirect calls to be optimized into sibling calls. */
1931 #define FUNCTION_OK_FOR_SIBCALL(DECL) (DECL && ! TARGET_FLAT)
1933 /* Generate RTL to flush the register windows so as to make arbitrary frames
1935 #define SETUP_FRAME_ADDRESSES() \
1936 emit_insn (gen_flush_register_windows ())
1938 /* Given an rtx for the address of a frame,
1939 return an rtx for the address of the word in the frame
1940 that holds the dynamic chain--the previous frame's address.
1941 ??? -mflat support? */
1942 #define DYNAMIC_CHAIN_ADDRESS(frame) plus_constant (frame, 14 * UNITS_PER_WORD)
1944 /* The return address isn't on the stack, it is in a register, so we can't
1945 access it from the current frame pointer. We can access it from the
1946 previous frame pointer though by reading a value from the register window
1948 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1950 /* This is the offset of the return address to the true next instruction to be
1951 executed for the current function. */
1952 #define RETURN_ADDR_OFFSET \
1953 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1955 /* The current return address is in %i7. The return address of anything
1956 farther back is in the register window save area at [%fp+60]. */
1957 /* ??? This ignores the fact that the actual return address is +8 for normal
1958 returns, and +12 for structure returns. */
1959 #define RETURN_ADDR_RTX(count, frame) \
1961 ? gen_rtx_REG (Pmode, 31) \
1962 : gen_rtx_MEM (Pmode, \
1963 memory_address (Pmode, plus_constant (frame, \
1964 15 * UNITS_PER_WORD))))
1966 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1967 +12, but always using +8 is close enough for frame unwind purposes.
1968 Actually, just using %o7 is close enough for unwinding, but %o7+8
1969 is something you can return to. */
1970 #define INCOMING_RETURN_ADDR_RTX \
1971 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1972 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1974 /* The offset from the incoming value of %sp to the top of the stack frame
1975 for the current function. On sparc64, we have to account for the stack
1977 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1979 /* Describe how we implement __builtin_eh_return. */
1980 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1981 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1982 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1984 /* Select a format to encode pointers in exception handling data. CODE
1985 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1986 true if the symbol may be affected by dynamic relocations.
1988 If assembler and linker properly support .uaword %r_disp32(foo),
1989 then use PC relative 32-bit relocations instead of absolute relocs
1990 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1991 for binaries, to save memory. */
1992 #ifdef HAVE_AS_SPARC_UA_PCREL
1993 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1995 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1996 : ((TARGET_ARCH64 && ! GLOBAL) \
1997 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
2000 /* Emit a PC-relative relocation. */
2001 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2003 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2004 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
2005 assemble_name (FILE, LABEL); \
2006 fputc (')', FILE); \
2010 /* Addressing modes, and classification of registers for them. */
2012 /* #define HAVE_POST_INCREMENT 0 */
2013 /* #define HAVE_POST_DECREMENT 0 */
2015 /* #define HAVE_PRE_DECREMENT 0 */
2016 /* #define HAVE_PRE_INCREMENT 0 */
2018 /* Macros to check register numbers against specific register classes. */
2020 /* These assume that REGNO is a hard or pseudo reg number.
2021 They give nonzero only if REGNO is a hard reg of the suitable class
2022 or a pseudo reg currently allocated to a suitable hard reg.
2023 Since they use reg_renumber, they are safe only once reg_renumber
2024 has been allocated, which happens in local-alloc.c. */
2026 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2027 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
2028 || (REGNO) == FRAME_POINTER_REGNUM \
2029 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
2031 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
2033 #define REGNO_OK_FOR_FP_P(REGNO) \
2034 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
2035 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
2036 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2038 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
2039 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
2041 /* Now macros that check whether X is a register and also,
2042 strictly, whether it is in a specified class.
2044 These macros are specific to the SPARC, and may be used only
2045 in code for printing assembler insns and in conditions for
2046 define_optimization. */
2048 /* 1 if X is an fp register. */
2050 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2052 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
2053 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
2055 /* Maximum number of registers that can appear in a valid memory address. */
2057 #define MAX_REGS_PER_ADDRESS 2
2059 /* Recognize any constant value that is a valid address.
2060 When PIC, we do not accept an address that would require a scratch reg
2061 to load into a register. */
2063 #define CONSTANT_ADDRESS_P(X) \
2064 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2065 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2066 || (GET_CODE (X) == CONST \
2067 && ! (flag_pic && pic_address_needs_scratch (X))))
2069 /* Define this, so that when PIC, reload won't try to reload invalid
2070 addresses which require two reload registers. */
2072 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2074 /* Nonzero if the constant value X is a legitimate general operand.
2075 Anything can be made to work except floating point constants.
2076 If TARGET_VIS, 0.0 can be made to work as well. */
2078 #define LEGITIMATE_CONSTANT_P(X) \
2079 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \
2081 (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode || \
2082 GET_MODE (X) == TFmode) && \
2083 fp_zero_operand (X, GET_MODE (X))))
2085 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2086 and check its validity for a certain class.
2087 We have two alternate definitions for each of them.
2088 The usual definition accepts all pseudo regs; the other rejects
2089 them unless they have been allocated suitable hard regs.
2090 The symbol REG_OK_STRICT causes the latter definition to be used.
2092 Most source files want to accept pseudo regs in the hope that
2093 they will get allocated to the class that the insn wants them to be in.
2094 Source files for reload pass need to be strict.
2095 After reload, it makes no difference, since pseudo regs have
2096 been eliminated by then. */
2098 /* Optional extra constraints for this machine.
2100 'Q' handles floating point constants which can be moved into
2101 an integer register with a single sethi instruction.
2103 'R' handles floating point constants which can be moved into
2104 an integer register with a single mov instruction.
2106 'S' handles floating point constants which can be moved into
2107 an integer register using a high/lo_sum sequence.
2109 'T' handles memory addresses where the alignment is known to
2110 be at least 8 bytes.
2112 `U' handles all pseudo registers or a hard even numbered
2113 integer register, needed for ldd/std instructions. */
2115 #define EXTRA_CONSTRAINT_BASE(OP, C) \
2116 ((C) == 'Q' ? fp_sethi_p(OP) \
2117 : (C) == 'R' ? fp_mov_p(OP) \
2118 : (C) == 'S' ? fp_high_losum_p(OP) \
2121 #ifndef REG_OK_STRICT
2123 /* Nonzero if X is a hard reg that can be used as an index
2124 or if it is a pseudo reg. */
2125 #define REG_OK_FOR_INDEX_P(X) \
2127 || REGNO (X) == FRAME_POINTER_REGNUM \
2128 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2130 /* Nonzero if X is a hard reg that can be used as a base reg
2131 or if it is a pseudo reg. */
2132 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
2134 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64. */
2136 #define EXTRA_CONSTRAINT(OP, C) \
2137 (EXTRA_CONSTRAINT_BASE(OP, C) \
2138 || ((! TARGET_ARCH64 && (C) == 'T') \
2139 ? (mem_min_alignment (OP, 8)) \
2140 : ((! TARGET_ARCH64 && (C) == 'U') \
2141 ? (register_ok_for_ldd (OP)) \
2146 /* Nonzero if X is a hard reg that can be used as an index. */
2147 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2148 /* Nonzero if X is a hard reg that can be used as a base reg. */
2149 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2151 #define EXTRA_CONSTRAINT(OP, C) \
2152 (EXTRA_CONSTRAINT_BASE(OP, C) \
2153 || ((! TARGET_ARCH64 && (C) == 'T') \
2154 ? mem_min_alignment (OP, 8) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
2155 : ((! TARGET_ARCH64 && (C) == 'U') \
2156 ? (GET_CODE (OP) == REG \
2157 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
2158 || reg_renumber[REGNO (OP)] >= 0) \
2159 && register_ok_for_ldd (OP)) \
2164 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2166 #ifdef HAVE_AS_OFFSETABLE_LO10
2167 #define USE_AS_OFFSETABLE_LO10 1
2169 #define USE_AS_OFFSETABLE_LO10 0
2172 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2173 that is a valid memory address for an instruction.
2174 The MODE argument is the machine mode for the MEM expression
2175 that wants to use this address.
2177 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2178 ordinarily. This changes a bit when generating PIC.
2180 If you change this, execute "rm explow.o recog.o reload.o". */
2182 #define RTX_OK_FOR_BASE_P(X) \
2183 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2184 || (GET_CODE (X) == SUBREG \
2185 && GET_CODE (SUBREG_REG (X)) == REG \
2186 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2188 #define RTX_OK_FOR_INDEX_P(X) \
2189 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2190 || (GET_CODE (X) == SUBREG \
2191 && GET_CODE (SUBREG_REG (X)) == REG \
2192 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2194 #define RTX_OK_FOR_OFFSET_P(X) \
2195 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2197 #define RTX_OK_FOR_OLO10_P(X) \
2198 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2200 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2201 { if (RTX_OK_FOR_BASE_P (X)) \
2203 else if (GET_CODE (X) == PLUS) \
2205 register rtx op0 = XEXP (X, 0); \
2206 register rtx op1 = XEXP (X, 1); \
2207 if (flag_pic && op0 == pic_offset_table_rtx) \
2209 if (RTX_OK_FOR_BASE_P (op1)) \
2211 else if (flag_pic == 1 \
2212 && GET_CODE (op1) != REG \
2213 && GET_CODE (op1) != LO_SUM \
2214 && GET_CODE (op1) != MEM \
2215 && (GET_CODE (op1) != CONST_INT \
2216 || SMALL_INT (op1))) \
2219 else if (RTX_OK_FOR_BASE_P (op0)) \
2221 if ((RTX_OK_FOR_INDEX_P (op1) \
2222 /* We prohibit REG + REG for TFmode when \
2223 there are no instructions which accept \
2224 REG+REG instructions. We do this \
2225 because REG+REG is not an offsetable \
2226 address. If we get the situation \
2227 in reload where source and destination \
2228 of a movtf pattern are both MEMs with \
2229 REG+REG address, then only one of them \
2230 gets converted to an offsetable \
2232 && (MODE != TFmode \
2233 || (TARGET_FPU && TARGET_ARCH64 \
2235 && TARGET_HARD_QUAD)) \
2236 /* We prohibit REG + REG on ARCH32 if \
2237 not optimizing for DFmode/DImode \
2238 because then mem_min_alignment is \
2239 likely to be zero after reload and the \
2240 forced split would lack a matching \
2241 splitter pattern. */ \
2242 && (TARGET_ARCH64 || optimize \
2243 || (MODE != DFmode \
2244 && MODE != DImode))) \
2245 || RTX_OK_FOR_OFFSET_P (op1)) \
2248 else if (RTX_OK_FOR_BASE_P (op1)) \
2250 if ((RTX_OK_FOR_INDEX_P (op0) \
2251 /* See the previous comment. */ \
2252 && (MODE != TFmode \
2253 || (TARGET_FPU && TARGET_ARCH64 \
2255 && TARGET_HARD_QUAD)) \
2256 && (TARGET_ARCH64 || optimize \
2257 || (MODE != DFmode \
2258 && MODE != DImode))) \
2259 || RTX_OK_FOR_OFFSET_P (op0)) \
2262 else if (USE_AS_OFFSETABLE_LO10 \
2263 && GET_CODE (op0) == LO_SUM \
2265 && ! TARGET_CM_MEDMID \
2266 && RTX_OK_FOR_OLO10_P (op1)) \
2268 register rtx op00 = XEXP (op0, 0); \
2269 register rtx op01 = XEXP (op0, 1); \
2270 if (RTX_OK_FOR_BASE_P (op00) \
2271 && CONSTANT_P (op01)) \
2274 else if (USE_AS_OFFSETABLE_LO10 \
2275 && GET_CODE (op1) == LO_SUM \
2277 && ! TARGET_CM_MEDMID \
2278 && RTX_OK_FOR_OLO10_P (op0)) \
2280 register rtx op10 = XEXP (op1, 0); \
2281 register rtx op11 = XEXP (op1, 1); \
2282 if (RTX_OK_FOR_BASE_P (op10) \
2283 && CONSTANT_P (op11)) \
2287 else if (GET_CODE (X) == LO_SUM) \
2289 register rtx op0 = XEXP (X, 0); \
2290 register rtx op1 = XEXP (X, 1); \
2291 if (RTX_OK_FOR_BASE_P (op0) \
2292 && CONSTANT_P (op1) \
2293 /* We can't allow TFmode, because an offset \
2294 greater than or equal to the alignment (8) \
2295 may cause the LO_SUM to overflow if !v9. */\
2296 && (MODE != TFmode || TARGET_V9)) \
2299 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2303 /* Try machine-dependent ways of modifying an illegitimate address
2304 to be legitimate. If we find one, return the new, valid address.
2305 This macro is used in only one place: `memory_address' in explow.c.
2307 OLDX is the address as it was before break_out_memory_refs was called.
2308 In some cases it is useful to look at this to decide what needs to be done.
2310 MODE and WIN are passed so that this macro can use
2311 GO_IF_LEGITIMATE_ADDRESS.
2313 It is always safe for this macro to do nothing. It exists to recognize
2314 opportunities to optimize the output. */
2316 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2317 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2318 { rtx sparc_x = (X); \
2319 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2320 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2321 force_operand (XEXP (X, 0), NULL_RTX)); \
2322 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2323 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2324 force_operand (XEXP (X, 1), NULL_RTX)); \
2325 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2326 (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2328 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2329 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2330 force_operand (XEXP (X, 1), NULL_RTX)); \
2331 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2333 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2334 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2335 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2336 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2337 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2338 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2339 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2340 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2341 || GET_CODE (X) == LABEL_REF) \
2342 (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); \
2343 if (memory_address_p (MODE, X)) \
2346 /* Try a machine-dependent way of reloading an illegitimate address
2347 operand. If we find one, push the reload and jump to WIN. This
2348 macro is used in only one place: `find_reloads_address' in reload.c.
2350 For Sparc 32, we wish to handle addresses by splitting them into
2351 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2352 This cuts the number of extra insns by one.
2354 Do nothing when generating PIC code and the address is a
2355 symbolic operand or requires a scratch register. */
2357 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2359 /* Decompose SImode constants into hi+lo_sum. We do have to \
2360 rerecognize what we produce, so be careful. */ \
2361 if (CONSTANT_P (X) \
2362 && (MODE != TFmode || TARGET_V9) \
2363 && GET_MODE (X) == SImode \
2364 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2366 && (symbolic_operand (X, Pmode) \
2367 || pic_address_needs_scratch (X)))) \
2369 X = gen_rtx_LO_SUM (GET_MODE (X), \
2370 gen_rtx_HIGH (GET_MODE (X), X), X); \
2371 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2372 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2376 /* ??? 64-bit reloads. */ \
2379 /* Go to LABEL if ADDR (a legitimate address expression)
2380 has an effect that depends on the machine mode it is used for.
2381 On the SPARC this is never true. */
2383 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2385 /* If we are referencing a function make the SYMBOL_REF special.
2386 In the Embedded Medium/Anywhere code model, %g4 points to the data segment
2387 so we must not add it to function addresses. */
2389 #define ENCODE_SECTION_INFO(DECL) \
2391 if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2392 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2395 /* Specify the machine mode that this machine uses
2396 for the index in the tablejump instruction. */
2397 /* If we ever implement any of the full models (such as CM_FULLANY),
2398 this has to be DImode in that case */
2399 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2400 #define CASE_VECTOR_MODE \
2401 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2403 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2404 we have to sign extend which slows things down. */
2405 #define CASE_VECTOR_MODE \
2406 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2409 /* Define as C expression which evaluates to nonzero if the tablejump
2410 instruction expects the table to contain offsets from the address of the
2412 Do not define this if the table should contain absolute addresses. */
2413 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2415 /* Define this as 1 if `char' should by default be signed; else as 0. */
2416 #define DEFAULT_SIGNED_CHAR 1
2418 /* Max number of bytes we can move from memory to memory
2419 in one reasonably fast instruction. */
2422 #if 0 /* Sun 4 has matherr, so this is no good. */
2423 /* This is the value of the error code EDOM for this machine,
2424 used by the sqrt instruction. */
2425 #define TARGET_EDOM 33
2427 /* This is how to refer to the variable errno. */
2428 #define GEN_ERRNO_RTX \
2429 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno"))
2432 /* Define if operations between registers always perform the operation
2433 on the full register even if a narrower mode is specified. */
2434 #define WORD_REGISTER_OPERATIONS
2436 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2437 will either zero-extend or sign-extend. The value of this macro should
2438 be the code that says which one of the two operations is implicitly
2439 done, NIL if none. */
2440 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2442 /* Nonzero if access to memory by bytes is slow and undesirable.
2443 For RISC chips, it means that access to memory by bytes is no
2444 better than access by words when possible, so grab a whole word
2445 and maybe make use of that. */
2446 #define SLOW_BYTE_ACCESS 1
2448 /* We assume that the store-condition-codes instructions store 0 for false
2449 and some other value for true. This is the value stored for true. */
2451 #define STORE_FLAG_VALUE 1
2453 /* When a prototype says `char' or `short', really pass an `int'. */
2454 #define PROMOTE_PROTOTYPES (TARGET_ARCH32)
2456 /* Define this to be nonzero if shift instructions ignore all but the low-order
2458 #define SHIFT_COUNT_TRUNCATED 1
2460 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2461 is done just by pretending it is already truncated. */
2462 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2464 /* Specify the machine mode that pointers have.
2465 After generation of rtl, the compiler makes no further distinction
2466 between pointers and any other objects of this machine mode. */
2467 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2469 /* Generate calls to memcpy, memcmp and memset. */
2470 #define TARGET_MEM_FUNCTIONS
2472 /* Add any extra modes needed to represent the condition code.
2474 On the Sparc, we have a "no-overflow" mode which is used when an add or
2475 subtract insn is used to set the condition code. Different branches are
2476 used in this case for some operations.
2478 We also have two modes to indicate that the relevant condition code is
2479 in the floating-point condition code register. One for comparisons which
2480 will generate an exception if the result is unordered (CCFPEmode) and
2481 one for comparisons which will never trap (CCFPmode).
2483 CCXmode and CCX_NOOVmode are only used by v9. */
2485 #define EXTRA_CC_MODES \
2486 CC(CCXmode, "CCX") \
2487 CC(CC_NOOVmode, "CC_NOOV") \
2488 CC(CCX_NOOVmode, "CCX_NOOV") \
2489 CC(CCFPmode, "CCFP") \
2490 CC(CCFPEmode, "CCFPE")
2492 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2493 return the mode to be used for the comparison. For floating-point,
2494 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2495 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2496 processing is needed. */
2497 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2499 /* Return non-zero if MODE implies a floating point inequality can be
2500 reversed. For Sparc this is always true because we have a full
2501 compliment of ordered and unordered comparisons, but until generic
2502 code knows how to reverse it correctly we keep the old definition. */
2503 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2505 /* A function address in a call instruction for indexing purposes. */
2506 #define FUNCTION_MODE Pmode
2508 /* Define this if addresses of constant functions
2509 shouldn't be put through pseudo regs where they can be cse'd.
2510 Desirable on machines where ordinary constants are expensive
2511 but a CALL with constant address is cheap. */
2512 #define NO_FUNCTION_CSE
2514 /* alloca should avoid clobbering the old register save area. */
2515 #define SETJMP_VIA_SAVE_AREA
2517 /* Define subroutines to call to handle multiply and divide.
2518 Use the subroutines that Sun's library provides.
2519 The `*' prevents an underscore from being prepended by the compiler. */
2521 #define DIVSI3_LIBCALL "*.div"
2522 #define UDIVSI3_LIBCALL "*.udiv"
2523 #define MODSI3_LIBCALL "*.rem"
2524 #define UMODSI3_LIBCALL "*.urem"
2525 /* .umul is a little faster than .mul. */
2526 #define MULSI3_LIBCALL "*.umul"
2528 /* Define library calls for quad FP operations. These are all part of the
2530 #define ADDTF3_LIBCALL "_Q_add"
2531 #define SUBTF3_LIBCALL "_Q_sub"
2532 #define NEGTF2_LIBCALL "_Q_neg"
2533 #define MULTF3_LIBCALL "_Q_mul"
2534 #define DIVTF3_LIBCALL "_Q_div"
2535 #define FLOATSITF2_LIBCALL "_Q_itoq"
2536 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2537 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2538 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2539 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2540 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2541 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2542 #define EQTF2_LIBCALL "_Q_feq"
2543 #define NETF2_LIBCALL "_Q_fne"
2544 #define GTTF2_LIBCALL "_Q_fgt"
2545 #define GETF2_LIBCALL "_Q_fge"
2546 #define LTTF2_LIBCALL "_Q_flt"
2547 #define LETF2_LIBCALL "_Q_fle"
2549 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2550 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2551 and the compiler will notice and try to use the TFmode sqrt instruction
2552 for calls to the builtin function sqrt, but this fails. */
2553 #define INIT_TARGET_OPTABS \
2555 if (TARGET_ARCH32) \
2557 add_optab->handlers[(int) TFmode].libfunc \
2558 = init_one_libfunc (ADDTF3_LIBCALL); \
2559 sub_optab->handlers[(int) TFmode].libfunc \
2560 = init_one_libfunc (SUBTF3_LIBCALL); \
2561 neg_optab->handlers[(int) TFmode].libfunc \
2562 = init_one_libfunc (NEGTF2_LIBCALL); \
2563 smul_optab->handlers[(int) TFmode].libfunc \
2564 = init_one_libfunc (MULTF3_LIBCALL); \
2565 sdiv_optab->handlers[(int) TFmode].libfunc \
2566 = init_one_libfunc (DIVTF3_LIBCALL); \
2567 eqtf2_libfunc = init_one_libfunc (EQTF2_LIBCALL); \
2568 netf2_libfunc = init_one_libfunc (NETF2_LIBCALL); \
2569 gttf2_libfunc = init_one_libfunc (GTTF2_LIBCALL); \
2570 getf2_libfunc = init_one_libfunc (GETF2_LIBCALL); \
2571 lttf2_libfunc = init_one_libfunc (LTTF2_LIBCALL); \
2572 letf2_libfunc = init_one_libfunc (LETF2_LIBCALL); \
2573 trunctfsf2_libfunc = init_one_libfunc (TRUNCTFSF2_LIBCALL); \
2574 trunctfdf2_libfunc = init_one_libfunc (TRUNCTFDF2_LIBCALL); \
2575 extendsftf2_libfunc = init_one_libfunc (EXTENDSFTF2_LIBCALL); \
2576 extenddftf2_libfunc = init_one_libfunc (EXTENDDFTF2_LIBCALL); \
2577 floatsitf_libfunc = init_one_libfunc (FLOATSITF2_LIBCALL); \
2578 fixtfsi_libfunc = init_one_libfunc (FIX_TRUNCTFSI2_LIBCALL); \
2579 fixunstfsi_libfunc \
2580 = init_one_libfunc (FIXUNS_TRUNCTFSI2_LIBCALL); \
2582 sqrt_optab->handlers[(int) TFmode].libfunc \
2583 = init_one_libfunc ("_Q_sqrt"); \
2585 INIT_SUBTARGET_OPTABS; \
2588 /* This is meant to be redefined in the host dependent files */
2589 #define INIT_SUBTARGET_OPTABS
2591 /* Nonzero if a floating point comparison library call for
2592 mode MODE that will return a boolean value. Zero if one
2593 of the libgcc2 functions is used. */
2594 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2596 /* Compute the cost of computing a constant rtl expression RTX
2597 whose rtx-code is CODE. The body of this macro is a portion
2598 of a switch statement. If the code is computed here,
2599 return it with a return statement. Otherwise, break from the switch. */
2601 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2603 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2611 case CONST_DOUBLE: \
2612 if (GET_MODE (RTX) == DImode) \
2613 if ((XINT (RTX, 3) == 0 \
2614 && (unsigned) XINT (RTX, 2) < 0x1000) \
2615 || (XINT (RTX, 3) == -1 \
2616 && XINT (RTX, 2) < 0 \
2617 && XINT (RTX, 2) >= -0x1000)) \
2621 #define ADDRESS_COST(RTX) 1
2623 /* Compute extra cost of moving data between one register class
2625 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2626 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2627 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2628 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2629 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2630 ? (sparc_cpu == PROCESSOR_ULTRASPARC ? 12 : 6) : 2)
2632 /* Provide the costs of a rtl expression. This is in the body of a
2633 switch on CODE. The purpose for the cost of MULT is to encourage
2634 `synth_mult' to find a synthetic multiply when reasonable.
2636 If we need more than 12 insns to do a multiply, then go out-of-line,
2637 since the call overhead will be < 10% of the cost of the multiply. */
2639 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2641 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2642 return (GET_MODE (X) == DImode ? \
2643 COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \
2644 return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2649 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2650 return (GET_MODE (X) == DImode ? \
2651 COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \
2652 return COSTS_N_INSNS (25); \
2653 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2654 so that cse will favor the latter. */ \
2659 /* Conditional branches with empty delay slots have a length of two. */
2660 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2662 if (GET_CODE (INSN) == CALL_INSN \
2663 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
2667 /* Control the assembler format that we output. */
2669 /* Output at beginning of assembler file. */
2671 #define ASM_FILE_START(file)
2673 /* A C string constant describing how to begin a comment in the target
2674 assembler language. The compiler assumes that the comment will end at
2675 the end of the line. */
2677 #define ASM_COMMENT_START "!"
2679 /* Output to assembler file text saying following lines
2680 may contain character constants, extra white space, comments, etc. */
2682 #define ASM_APP_ON ""
2684 /* Output to assembler file text saying following lines
2685 no longer contain unusual constructs. */
2687 #define ASM_APP_OFF ""
2689 /* ??? Try to make the style consistent here (_OP?). */
2691 #define ASM_FLOAT ".single"
2692 #define ASM_DOUBLE ".double"
2693 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2695 /* How to refer to registers in assembler output.
2696 This sequence is indexed by compiler's hard-register-number (see above). */
2698 #define REGISTER_NAMES \
2699 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2700 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2701 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2702 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2703 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2704 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2705 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2706 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2707 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2708 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2709 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2710 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2711 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2713 /* Define additional names for use in asm clobbers and asm declarations. */
2715 #define ADDITIONAL_REGISTER_NAMES \
2716 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2718 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2719 can run past this up to a continuation point. Once we used 1500, but
2720 a single entry in C++ can run more than 500 bytes, due to the length of
2721 mangled symbol names. dbxout.c should really be fixed to do
2722 continuations when they are actually needed instead of trying to
2724 #define DBX_CONTIN_LENGTH 1000
2726 /* This is how to output the definition of a user-level label named NAME,
2727 such as the label on a static function or variable NAME. */
2729 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2730 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2732 /* This is how to output a command to make the user-level label named NAME
2733 defined for reference from other files. */
2735 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2736 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2738 /* The prefix to add to user-visible assembler symbols. */
2740 #define USER_LABEL_PREFIX "_"
2742 /* This is how to output a definition of an internal numbered label where
2743 PREFIX is the class of label and NUM is the number within the class. */
2745 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2746 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2748 /* This is how to store into the string LABEL
2749 the symbol_ref name of an internal numbered label where
2750 PREFIX is the class of label and NUM is the number within the class.
2751 This is suitable for output with `assemble_name'. */
2753 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2754 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2756 /* This is how we hook in and defer the case-vector until the end of
2758 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2759 sparc_defer_case_vector ((LAB),(VEC), 0)
2761 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2762 sparc_defer_case_vector ((LAB),(VEC), 1)
2764 /* This is how to output an element of a case-vector that is absolute. */
2766 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2769 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2770 if (CASE_VECTOR_MODE == SImode) \
2771 fprintf (FILE, "\t.word\t"); \
2773 fprintf (FILE, "\t.xword\t"); \
2774 assemble_name (FILE, label); \
2775 fputc ('\n', FILE); \
2778 /* This is how to output an element of a case-vector that is relative.
2779 (SPARC uses such vectors only when generating PIC.) */
2781 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2784 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2785 if (CASE_VECTOR_MODE == SImode) \
2786 fprintf (FILE, "\t.word\t"); \
2788 fprintf (FILE, "\t.xword\t"); \
2789 assemble_name (FILE, label); \
2790 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2791 fputc ('-', FILE); \
2792 assemble_name (FILE, label); \
2793 fputc ('\n', FILE); \
2796 /* This is what to output before and after case-vector (both
2797 relative and absolute). If .subsection -1 works, we put case-vectors
2798 at the beginning of the current section. */
2800 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2802 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2803 fprintf(FILE, "\t.subsection\t-1\n")
2805 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2806 fprintf(FILE, "\t.previous\n")
2810 /* This is how to output an assembler line
2811 that says to advance the location counter
2812 to a multiple of 2**LOG bytes. */
2814 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2816 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2818 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2819 fprintf (FILE, "\t.skip %u\n", (SIZE))
2821 /* This says how to output an assembler line
2822 to define a global common symbol. */
2824 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2825 ( fputs ("\t.common ", (FILE)), \
2826 assemble_name ((FILE), (NAME)), \
2827 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
2829 /* This says how to output an assembler line to define a local common
2832 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2833 ( fputs ("\t.reserve ", (FILE)), \
2834 assemble_name ((FILE), (NAME)), \
2835 fprintf ((FILE), ",%u,\"bss\",%u\n", \
2836 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2838 /* A C statement (sans semicolon) to output to the stdio stream
2839 FILE the assembler definition of uninitialized global DECL named
2840 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2841 Try to use asm_output_aligned_bss to implement this macro. */
2843 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2845 fputs (".globl ", (FILE)); \
2846 assemble_name ((FILE), (NAME)); \
2847 fputs ("\n", (FILE)); \
2848 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2851 /* Store in OUTPUT a string (made with alloca) containing
2852 an assembler-name for a local static variable named NAME.
2853 LABELNO is an integer which is different for each call. */
2855 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2856 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2857 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2859 #define IDENT_ASM_OP "\t.ident\t"
2861 /* Output #ident as a .ident. */
2863 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2864 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2866 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2867 Used for C++ multiple inheritance. */
2868 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2873 && aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION)))) \
2875 if ((DELTA) >= 4096 || (DELTA) < -4096) \
2876 fprintf (FILE, "\tset\t%d, %%g1\n\tadd\t%%o%d, %%g1, %%o%d\n", \
2877 (int)(DELTA), reg, reg); \
2879 fprintf (FILE, "\tadd\t%%o%d, %d, %%o%d\n", reg, (int)(DELTA), reg);\
2880 fprintf (FILE, "\tor\t%%o7, %%g0, %%g1\n"); \
2881 fprintf (FILE, "\tcall\t"); \
2882 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2883 fprintf (FILE, ", 0\n"); \
2884 fprintf (FILE, "\t or\t%%g1, %%g0, %%o7\n"); \
2887 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2888 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
2890 /* Print operand X (an rtx) in assembler syntax to file FILE.
2891 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2892 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2894 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2896 /* Print a memory address as an operand to reference that memory location. */
2898 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2899 { register rtx base, index = 0; \
2901 register rtx addr = ADDR; \
2902 if (GET_CODE (addr) == REG) \
2903 fputs (reg_names[REGNO (addr)], FILE); \
2904 else if (GET_CODE (addr) == PLUS) \
2906 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2907 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2908 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2909 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2911 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2912 if (GET_CODE (base) == LO_SUM) \
2914 if (! USE_AS_OFFSETABLE_LO10 \
2916 || TARGET_CM_MEDMID) \
2918 output_operand (XEXP (base, 0), 0); \
2919 fputs ("+%lo(", FILE); \
2920 output_address (XEXP (base, 1)); \
2921 fprintf (FILE, ")+%d", offset); \
2925 fputs (reg_names[REGNO (base)], FILE); \
2927 fprintf (FILE, "%+d", offset); \
2928 else if (GET_CODE (index) == REG) \
2929 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2930 else if (GET_CODE (index) == SYMBOL_REF \
2931 || GET_CODE (index) == CONST) \
2932 fputc ('+', FILE), output_addr_const (FILE, index); \
2936 else if (GET_CODE (addr) == MINUS \
2937 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2939 output_addr_const (FILE, XEXP (addr, 0)); \
2940 fputs ("-(", FILE); \
2941 output_addr_const (FILE, XEXP (addr, 1)); \
2942 fputs ("-.)", FILE); \
2944 else if (GET_CODE (addr) == LO_SUM) \
2946 output_operand (XEXP (addr, 0), 0); \
2947 if (TARGET_CM_MEDMID) \
2948 fputs ("+%l44(", FILE); \
2950 fputs ("+%lo(", FILE); \
2951 output_address (XEXP (addr, 1)); \
2952 fputc (')', FILE); \
2954 else if (flag_pic && GET_CODE (addr) == CONST \
2955 && GET_CODE (XEXP (addr, 0)) == MINUS \
2956 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2957 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2958 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2960 addr = XEXP (addr, 0); \
2961 output_addr_const (FILE, XEXP (addr, 0)); \
2962 /* Group the args of the second CONST in parenthesis. */ \
2963 fputs ("-(", FILE); \
2964 /* Skip past the second CONST--it does nothing for us. */\
2965 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2966 /* Close the parenthesis. */ \
2967 fputc (')', FILE); \
2971 output_addr_const (FILE, addr); \
2975 /* Define the codes that are matched by predicates in sparc.c. */
2977 #define PREDICATE_CODES \
2978 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2979 {"fp_zero_operand", {CONST_DOUBLE}}, \
2980 {"intreg_operand", {SUBREG, REG}}, \
2981 {"fcc_reg_operand", {REG}}, \
2982 {"icc_or_fcc_reg_operand", {REG}}, \
2983 {"restore_operand", {REG}}, \
2984 {"call_operand", {MEM}}, \
2985 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
2986 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
2987 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2988 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2989 {"label_ref_operand", {LABEL_REF}}, \
2990 {"sp64_medium_pic_operand", {CONST}}, \
2991 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
2992 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
2993 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
2994 {"splittable_symbolic_memory_operand", {MEM}}, \
2995 {"splittable_immediate_memory_operand", {MEM}}, \
2996 {"eq_or_neq", {EQ, NE}}, \
2997 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
2998 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2999 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
3000 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
3001 {"cc_arithop", {AND, IOR, XOR}}, \
3002 {"cc_arithopn", {AND, IOR}}, \
3003 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3004 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
3005 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
3006 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
3007 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3008 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3009 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3010 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3011 {"small_int", {CONST_INT}}, \
3012 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
3013 {"uns_small_int", {CONST_INT}}, \
3014 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
3015 {"clobbered_register", {REG}}, \
3016 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
3017 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
3018 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
3020 /* The number of Pmode words for the setjmp buffer. */
3021 #define JMP_BUF_SIZE 12
3023 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)