1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
50 #include "tree-gimple.h"
54 struct processor_costs cypress_costs = {
55 COSTS_N_INSNS (2), /* int load */
56 COSTS_N_INSNS (2), /* int signed load */
57 COSTS_N_INSNS (2), /* int zeroed load */
58 COSTS_N_INSNS (2), /* float load */
59 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
60 COSTS_N_INSNS (5), /* fadd, fsub */
61 COSTS_N_INSNS (1), /* fcmp */
62 COSTS_N_INSNS (1), /* fmov, fmovr */
63 COSTS_N_INSNS (7), /* fmul */
64 COSTS_N_INSNS (37), /* fdivs */
65 COSTS_N_INSNS (37), /* fdivd */
66 COSTS_N_INSNS (63), /* fsqrts */
67 COSTS_N_INSNS (63), /* fsqrtd */
68 COSTS_N_INSNS (1), /* imul */
69 COSTS_N_INSNS (1), /* imulX */
70 0, /* imul bit factor */
71 COSTS_N_INSNS (1), /* idiv */
72 COSTS_N_INSNS (1), /* idivX */
73 COSTS_N_INSNS (1), /* movcc/movr */
74 0, /* shift penalty */
78 struct processor_costs supersparc_costs = {
79 COSTS_N_INSNS (1), /* int load */
80 COSTS_N_INSNS (1), /* int signed load */
81 COSTS_N_INSNS (1), /* int zeroed load */
82 COSTS_N_INSNS (0), /* float load */
83 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
84 COSTS_N_INSNS (3), /* fadd, fsub */
85 COSTS_N_INSNS (3), /* fcmp */
86 COSTS_N_INSNS (1), /* fmov, fmovr */
87 COSTS_N_INSNS (3), /* fmul */
88 COSTS_N_INSNS (6), /* fdivs */
89 COSTS_N_INSNS (9), /* fdivd */
90 COSTS_N_INSNS (12), /* fsqrts */
91 COSTS_N_INSNS (12), /* fsqrtd */
92 COSTS_N_INSNS (4), /* imul */
93 COSTS_N_INSNS (4), /* imulX */
94 0, /* imul bit factor */
95 COSTS_N_INSNS (4), /* idiv */
96 COSTS_N_INSNS (4), /* idivX */
97 COSTS_N_INSNS (1), /* movcc/movr */
98 1, /* shift penalty */
102 struct processor_costs hypersparc_costs = {
103 COSTS_N_INSNS (1), /* int load */
104 COSTS_N_INSNS (1), /* int signed load */
105 COSTS_N_INSNS (1), /* int zeroed load */
106 COSTS_N_INSNS (1), /* float load */
107 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
108 COSTS_N_INSNS (1), /* fadd, fsub */
109 COSTS_N_INSNS (1), /* fcmp */
110 COSTS_N_INSNS (1), /* fmov, fmovr */
111 COSTS_N_INSNS (1), /* fmul */
112 COSTS_N_INSNS (8), /* fdivs */
113 COSTS_N_INSNS (12), /* fdivd */
114 COSTS_N_INSNS (17), /* fsqrts */
115 COSTS_N_INSNS (17), /* fsqrtd */
116 COSTS_N_INSNS (17), /* imul */
117 COSTS_N_INSNS (17), /* imulX */
118 0, /* imul bit factor */
119 COSTS_N_INSNS (17), /* idiv */
120 COSTS_N_INSNS (17), /* idivX */
121 COSTS_N_INSNS (1), /* movcc/movr */
122 0, /* shift penalty */
126 struct processor_costs sparclet_costs = {
127 COSTS_N_INSNS (3), /* int load */
128 COSTS_N_INSNS (3), /* int signed load */
129 COSTS_N_INSNS (1), /* int zeroed load */
130 COSTS_N_INSNS (1), /* float load */
131 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
132 COSTS_N_INSNS (1), /* fadd, fsub */
133 COSTS_N_INSNS (1), /* fcmp */
134 COSTS_N_INSNS (1), /* fmov, fmovr */
135 COSTS_N_INSNS (1), /* fmul */
136 COSTS_N_INSNS (1), /* fdivs */
137 COSTS_N_INSNS (1), /* fdivd */
138 COSTS_N_INSNS (1), /* fsqrts */
139 COSTS_N_INSNS (1), /* fsqrtd */
140 COSTS_N_INSNS (5), /* imul */
141 COSTS_N_INSNS (5), /* imulX */
142 0, /* imul bit factor */
143 COSTS_N_INSNS (5), /* idiv */
144 COSTS_N_INSNS (5), /* idivX */
145 COSTS_N_INSNS (1), /* movcc/movr */
146 0, /* shift penalty */
150 struct processor_costs ultrasparc_costs = {
151 COSTS_N_INSNS (2), /* int load */
152 COSTS_N_INSNS (3), /* int signed load */
153 COSTS_N_INSNS (2), /* int zeroed load */
154 COSTS_N_INSNS (2), /* float load */
155 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
156 COSTS_N_INSNS (4), /* fadd, fsub */
157 COSTS_N_INSNS (1), /* fcmp */
158 COSTS_N_INSNS (2), /* fmov, fmovr */
159 COSTS_N_INSNS (4), /* fmul */
160 COSTS_N_INSNS (13), /* fdivs */
161 COSTS_N_INSNS (23), /* fdivd */
162 COSTS_N_INSNS (13), /* fsqrts */
163 COSTS_N_INSNS (23), /* fsqrtd */
164 COSTS_N_INSNS (4), /* imul */
165 COSTS_N_INSNS (4), /* imulX */
166 2, /* imul bit factor */
167 COSTS_N_INSNS (37), /* idiv */
168 COSTS_N_INSNS (68), /* idivX */
169 COSTS_N_INSNS (2), /* movcc/movr */
170 2, /* shift penalty */
174 struct processor_costs ultrasparc3_costs = {
175 COSTS_N_INSNS (2), /* int load */
176 COSTS_N_INSNS (3), /* int signed load */
177 COSTS_N_INSNS (3), /* int zeroed load */
178 COSTS_N_INSNS (2), /* float load */
179 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
180 COSTS_N_INSNS (4), /* fadd, fsub */
181 COSTS_N_INSNS (5), /* fcmp */
182 COSTS_N_INSNS (3), /* fmov, fmovr */
183 COSTS_N_INSNS (4), /* fmul */
184 COSTS_N_INSNS (17), /* fdivs */
185 COSTS_N_INSNS (20), /* fdivd */
186 COSTS_N_INSNS (20), /* fsqrts */
187 COSTS_N_INSNS (29), /* fsqrtd */
188 COSTS_N_INSNS (6), /* imul */
189 COSTS_N_INSNS (6), /* imulX */
190 0, /* imul bit factor */
191 COSTS_N_INSNS (40), /* idiv */
192 COSTS_N_INSNS (71), /* idivX */
193 COSTS_N_INSNS (2), /* movcc/movr */
194 0, /* shift penalty */
197 const struct processor_costs *sparc_costs = &cypress_costs;
199 #ifdef HAVE_AS_RELAX_OPTION
200 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
201 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
202 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
203 somebody does not branch between the sethi and jmp. */
204 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
206 #define LEAF_SIBCALL_SLOT_RESERVED_P \
207 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
210 /* Global variables for machine-dependent things. */
212 /* Size of frame. Need to know this to emit return insns from leaf procedures.
213 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
214 reload pass. This is important as the value is later used for scheduling
215 (to see what can go in a delay slot).
216 APPARENT_FSIZE is the size of the stack less the register save area and less
217 the outgoing argument area. It is used when saving call preserved regs. */
218 static HOST_WIDE_INT apparent_fsize;
219 static HOST_WIDE_INT actual_fsize;
221 /* Number of live general or floating point registers needed to be
222 saved (as 4-byte quantities). */
223 static int num_gfregs;
225 /* The alias set for prologue/epilogue register save/restore. */
226 static GTY(()) int sparc_sr_alias_set;
228 /* Save the operands last given to a compare for use when we
229 generate a scc or bcc insn. */
230 rtx sparc_compare_op0, sparc_compare_op1;
232 /* Vector to say how input registers are mapped to output registers.
233 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
234 eliminate it. You must use -fomit-frame-pointer to get that. */
235 char leaf_reg_remap[] =
236 { 0, 1, 2, 3, 4, 5, 6, 7,
237 -1, -1, -1, -1, -1, -1, 14, -1,
238 -1, -1, -1, -1, -1, -1, -1, -1,
239 8, 9, 10, 11, 12, 13, -1, 15,
241 32, 33, 34, 35, 36, 37, 38, 39,
242 40, 41, 42, 43, 44, 45, 46, 47,
243 48, 49, 50, 51, 52, 53, 54, 55,
244 56, 57, 58, 59, 60, 61, 62, 63,
245 64, 65, 66, 67, 68, 69, 70, 71,
246 72, 73, 74, 75, 76, 77, 78, 79,
247 80, 81, 82, 83, 84, 85, 86, 87,
248 88, 89, 90, 91, 92, 93, 94, 95,
249 96, 97, 98, 99, 100};
251 /* Vector, indexed by hard register number, which contains 1
252 for a register that is allowable in a candidate for leaf
253 function treatment. */
254 char sparc_leaf_regs[] =
255 { 1, 1, 1, 1, 1, 1, 1, 1,
256 0, 0, 0, 0, 0, 0, 1, 0,
257 0, 0, 0, 0, 0, 0, 0, 0,
258 1, 1, 1, 1, 1, 1, 0, 1,
259 1, 1, 1, 1, 1, 1, 1, 1,
260 1, 1, 1, 1, 1, 1, 1, 1,
261 1, 1, 1, 1, 1, 1, 1, 1,
262 1, 1, 1, 1, 1, 1, 1, 1,
263 1, 1, 1, 1, 1, 1, 1, 1,
264 1, 1, 1, 1, 1, 1, 1, 1,
265 1, 1, 1, 1, 1, 1, 1, 1,
266 1, 1, 1, 1, 1, 1, 1, 1,
269 struct machine_function GTY(())
271 /* Some local-dynamic TLS symbol name. */
272 const char *some_ld_name;
275 /* Register we pretend to think the frame pointer is allocated to.
276 Normally, this is %fp, but if we are in a leaf procedure, this
277 is %sp+"something". We record "something" separately as it may
278 be too big for reg+constant addressing. */
280 static rtx frame_base_reg;
281 static HOST_WIDE_INT frame_base_offset;
283 static void sparc_init_modes (void);
284 static void scan_record_type (tree, int *, int *, int *);
285 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
286 tree, int, int, int *, int *);
288 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
289 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
291 static void sparc_output_addr_vec (rtx);
292 static void sparc_output_addr_diff_vec (rtx);
293 static void sparc_output_deferred_case_vectors (void);
294 static rtx sparc_builtin_saveregs (void);
295 static int epilogue_renumber (rtx *, int);
296 static bool sparc_assemble_integer (rtx, unsigned int, int);
297 static int set_extends (rtx);
298 static void load_pic_register (void);
299 static int save_or_restore_regs (int, int, rtx, int, int);
300 static void emit_save_regs (void);
301 static void emit_restore_regs (void);
302 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
303 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
304 #ifdef OBJECT_FORMAT_ELF
305 static void sparc_elf_asm_named_section (const char *, unsigned int);
308 static int sparc_adjust_cost (rtx, rtx, rtx, int);
309 static int sparc_issue_rate (void);
310 static void sparc_sched_init (FILE *, int, int);
311 static int sparc_use_sched_lookahead (void);
313 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
314 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
315 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
316 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
317 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
319 static bool sparc_function_ok_for_sibcall (tree, tree);
320 static void sparc_init_libfuncs (void);
321 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
322 HOST_WIDE_INT, tree);
323 static struct machine_function * sparc_init_machine_status (void);
324 static bool sparc_cannot_force_const_mem (rtx);
325 static rtx sparc_tls_get_addr (void);
326 static rtx sparc_tls_got (void);
327 static const char *get_some_local_dynamic_name (void);
328 static int get_some_local_dynamic_name_1 (rtx *, void *);
329 static bool sparc_rtx_costs (rtx, int, int, int *);
330 static bool sparc_promote_prototypes (tree);
331 static rtx sparc_struct_value_rtx (tree, int);
332 static bool sparc_return_in_memory (tree, tree);
333 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
334 static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
335 static bool sparc_pass_by_reference (CUMULATIVE_ARGS *,
336 enum machine_mode, tree, bool);
337 #ifdef SUBTARGET_ATTRIBUTE_TABLE
338 const struct attribute_spec sparc_attribute_table[];
341 /* Option handling. */
343 /* Code model option as passed by user. */
344 const char *sparc_cmodel_string;
346 enum cmodel sparc_cmodel;
348 char sparc_hard_reg_printed[8];
350 struct sparc_cpu_select sparc_select[] =
352 /* switch name, tune arch */
353 { (char *)0, "default", 1, 1 },
354 { (char *)0, "-mcpu=", 1, 1 },
355 { (char *)0, "-mtune=", 1, 0 },
359 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
360 enum processor_type sparc_cpu;
362 /* Initialize the GCC target structure. */
364 /* The sparc default is to use .half rather than .short for aligned
365 HI objects. Use .word instead of .long on non-ELF systems. */
366 #undef TARGET_ASM_ALIGNED_HI_OP
367 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
368 #ifndef OBJECT_FORMAT_ELF
369 #undef TARGET_ASM_ALIGNED_SI_OP
370 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
373 #undef TARGET_ASM_UNALIGNED_HI_OP
374 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
375 #undef TARGET_ASM_UNALIGNED_SI_OP
376 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
377 #undef TARGET_ASM_UNALIGNED_DI_OP
378 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
380 /* The target hook has to handle DI-mode values. */
381 #undef TARGET_ASM_INTEGER
382 #define TARGET_ASM_INTEGER sparc_assemble_integer
384 #undef TARGET_ASM_FUNCTION_PROLOGUE
385 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
386 #undef TARGET_ASM_FUNCTION_EPILOGUE
387 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
389 #undef TARGET_SCHED_ADJUST_COST
390 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
391 #undef TARGET_SCHED_ISSUE_RATE
392 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
393 #undef TARGET_SCHED_INIT
394 #define TARGET_SCHED_INIT sparc_sched_init
395 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
396 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
398 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
399 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
401 #undef TARGET_INIT_LIBFUNCS
402 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
405 #undef TARGET_HAVE_TLS
406 #define TARGET_HAVE_TLS true
408 #undef TARGET_CANNOT_FORCE_CONST_MEM
409 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
411 #undef TARGET_ASM_OUTPUT_MI_THUNK
412 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
413 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
414 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
416 #undef TARGET_RTX_COSTS
417 #define TARGET_RTX_COSTS sparc_rtx_costs
418 #undef TARGET_ADDRESS_COST
419 #define TARGET_ADDRESS_COST hook_int_rtx_0
421 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
422 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
423 test for this value. */
424 #undef TARGET_PROMOTE_FUNCTION_ARGS
425 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
427 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
428 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
429 test for this value. */
430 #undef TARGET_PROMOTE_FUNCTION_RETURN
431 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
433 #undef TARGET_PROMOTE_PROTOTYPES
434 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
436 #undef TARGET_STRUCT_VALUE_RTX
437 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
438 #undef TARGET_RETURN_IN_MEMORY
439 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
440 #undef TARGET_MUST_PASS_IN_STACK
441 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
442 #undef TARGET_PASS_BY_REFERENCE
443 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
445 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
446 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
447 #undef TARGET_STRICT_ARGUMENT_NAMING
448 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
450 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
451 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
453 #undef TARGET_LATE_RTL_PROLOGUE_EPILOGUE
454 #define TARGET_LATE_RTL_PROLOGUE_EPILOGUE true
456 #ifdef SUBTARGET_INSERT_ATTRIBUTES
457 #undef TARGET_INSERT_ATTRIBUTES
458 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
461 #ifdef SUBTARGET_ATTRIBUTE_TABLE
462 #undef TARGET_ATTRIBUTE_TABLE
463 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
466 struct gcc_target targetm = TARGET_INITIALIZER;
468 /* Validate and override various options, and do some machine dependent
472 sparc_override_options (void)
474 static struct code_model {
475 const char *const name;
477 } const cmodels[] = {
479 { "medlow", CM_MEDLOW },
480 { "medmid", CM_MEDMID },
481 { "medany", CM_MEDANY },
482 { "embmedany", CM_EMBMEDANY },
485 const struct code_model *cmodel;
486 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
487 static struct cpu_default {
489 const char *const name;
490 } const cpu_default[] = {
491 /* There must be one entry here for each TARGET_CPU value. */
492 { TARGET_CPU_sparc, "cypress" },
493 { TARGET_CPU_sparclet, "tsc701" },
494 { TARGET_CPU_sparclite, "f930" },
495 { TARGET_CPU_v8, "v8" },
496 { TARGET_CPU_hypersparc, "hypersparc" },
497 { TARGET_CPU_sparclite86x, "sparclite86x" },
498 { TARGET_CPU_supersparc, "supersparc" },
499 { TARGET_CPU_v9, "v9" },
500 { TARGET_CPU_ultrasparc, "ultrasparc" },
501 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
504 const struct cpu_default *def;
505 /* Table of values for -m{cpu,tune}=. */
506 static struct cpu_table {
507 const char *const name;
508 const enum processor_type processor;
511 } const cpu_table[] = {
512 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
513 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
514 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
515 /* TI TMS390Z55 supersparc */
516 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
517 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
518 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
519 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
520 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
521 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
522 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
523 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
525 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
527 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
528 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
529 /* TI ultrasparc I, II, IIi */
530 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
531 /* Although insns using %y are deprecated, it is a clear win on current
533 |MASK_DEPRECATED_V8_INSNS},
534 /* TI ultrasparc III */
535 /* ??? Check if %y issue still holds true in ultra3. */
536 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
539 const struct cpu_table *cpu;
540 const struct sparc_cpu_select *sel;
543 #ifndef SPARC_BI_ARCH
544 /* Check for unsupported architecture size. */
545 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
546 error ("%s is not supported by this configuration",
547 DEFAULT_ARCH32_P ? "-m64" : "-m32");
550 /* We force all 64bit archs to use 128 bit long double */
551 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
553 error ("-mlong-double-64 not allowed with -m64");
554 target_flags |= MASK_LONG_DOUBLE_128;
557 /* Code model selection. */
558 sparc_cmodel = SPARC_DEFAULT_CMODEL;
562 sparc_cmodel = CM_32;
565 if (sparc_cmodel_string != NULL)
569 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
570 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
572 if (cmodel->name == NULL)
573 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
575 sparc_cmodel = cmodel->value;
578 error ("-mcmodel= is not supported on 32 bit systems");
581 fpu = TARGET_FPU; /* save current -mfpu status */
583 /* Set the default CPU. */
584 for (def = &cpu_default[0]; def->name; ++def)
585 if (def->cpu == TARGET_CPU_DEFAULT)
589 sparc_select[0].string = def->name;
591 for (sel = &sparc_select[0]; sel->name; ++sel)
595 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
596 if (! strcmp (sel->string, cpu->name))
599 sparc_cpu = cpu->processor;
603 target_flags &= ~cpu->disable;
604 target_flags |= cpu->enable;
610 error ("bad value (%s) for %s switch", sel->string, sel->name);
614 /* If -mfpu or -mno-fpu was explicitly used, don't override with
615 the processor default. Clear MASK_FPU_SET to avoid confusing
616 the reverse mapping from switch values to names. */
619 target_flags = (target_flags & ~MASK_FPU) | fpu;
620 target_flags &= ~MASK_FPU_SET;
623 /* Don't allow -mvis if FPU is disabled. */
625 target_flags &= ~MASK_VIS;
627 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
629 -m64 also implies v9. */
630 if (TARGET_VIS || TARGET_ARCH64)
632 target_flags |= MASK_V9;
633 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
636 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
637 if (TARGET_V9 && TARGET_ARCH32)
638 target_flags |= MASK_DEPRECATED_V8_INSNS;
640 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
641 if (! TARGET_V9 || TARGET_ARCH64)
642 target_flags &= ~MASK_V8PLUS;
644 /* Don't use stack biasing in 32 bit mode. */
646 target_flags &= ~MASK_STACK_BIAS;
648 /* Supply a default value for align_functions. */
649 if (align_functions == 0
650 && (sparc_cpu == PROCESSOR_ULTRASPARC
651 || sparc_cpu == PROCESSOR_ULTRASPARC3))
652 align_functions = 32;
654 /* Validate PCC_STRUCT_RETURN. */
655 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
656 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
658 /* Only use .uaxword when compiling for a 64-bit target. */
660 targetm.asm_out.unaligned_op.di = NULL;
662 /* Do various machine dependent initializations. */
665 /* Acquire a unique set number for our register saves and restores. */
666 sparc_sr_alias_set = new_alias_set ();
668 /* Set up function hooks. */
669 init_machine_status = sparc_init_machine_status;
674 case PROCESSOR_CYPRESS:
675 sparc_costs = &cypress_costs;
678 case PROCESSOR_SPARCLITE:
679 case PROCESSOR_SUPERSPARC:
680 sparc_costs = &supersparc_costs;
684 case PROCESSOR_HYPERSPARC:
685 case PROCESSOR_SPARCLITE86X:
686 sparc_costs = &hypersparc_costs;
688 case PROCESSOR_SPARCLET:
689 case PROCESSOR_TSC701:
690 sparc_costs = &sparclet_costs;
693 case PROCESSOR_ULTRASPARC:
694 sparc_costs = &ultrasparc_costs;
696 case PROCESSOR_ULTRASPARC3:
697 sparc_costs = &ultrasparc3_costs;
702 #ifdef SUBTARGET_ATTRIBUTE_TABLE
703 /* Table of valid machine attributes. */
704 const struct attribute_spec sparc_attribute_table[] =
706 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
707 SUBTARGET_ATTRIBUTE_TABLE,
708 { NULL, 0, 0, false, false, false, NULL }
712 /* Miscellaneous utilities. */
714 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
715 or branch on register contents instructions. */
718 v9_regcmp_p (enum rtx_code code)
720 return (code == EQ || code == NE || code == GE || code == LT
721 || code == LE || code == GT);
725 /* Operand constraints. */
727 /* Return nonzero only if OP is a register of mode MODE,
731 reg_or_0_operand (rtx op, enum machine_mode mode)
733 if (register_operand (op, mode))
735 if (op == const0_rtx)
737 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
738 && CONST_DOUBLE_HIGH (op) == 0
739 && CONST_DOUBLE_LOW (op) == 0)
741 if (fp_zero_operand (op, mode))
746 /* Return nonzero only if OP is const1_rtx. */
749 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
751 return op == const1_rtx;
754 /* Nonzero if OP is a floating point value with value 0.0. */
757 fp_zero_operand (rtx op, enum machine_mode mode)
759 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
761 return op == CONST0_RTX (mode);
764 /* Nonzero if OP is a register operand in floating point register. */
767 fp_register_operand (rtx op, enum machine_mode mode)
769 if (! register_operand (op, mode))
771 if (GET_CODE (op) == SUBREG)
772 op = SUBREG_REG (op);
773 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
776 /* Nonzero if OP is a floating point constant which can
777 be loaded into an integer register using a single
778 sethi instruction. */
783 if (GET_CODE (op) == CONST_DOUBLE)
788 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
789 if (REAL_VALUES_EQUAL (r, dconst0) &&
790 ! REAL_VALUE_MINUS_ZERO (r))
792 REAL_VALUE_TO_TARGET_SINGLE (r, i);
793 if (SPARC_SETHI_P (i))
800 /* Nonzero if OP is a floating point constant which can
801 be loaded into an integer register using a single
807 if (GET_CODE (op) == CONST_DOUBLE)
812 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
813 if (REAL_VALUES_EQUAL (r, dconst0) &&
814 ! REAL_VALUE_MINUS_ZERO (r))
816 REAL_VALUE_TO_TARGET_SINGLE (r, i);
817 if (SPARC_SIMM13_P (i))
824 /* Nonzero if OP is a floating point constant which can
825 be loaded into an integer register using a high/losum
826 instruction sequence. */
829 fp_high_losum_p (rtx op)
831 /* The constraints calling this should only be in
832 SFmode move insns, so any constant which cannot
833 be moved using a single insn will do. */
834 if (GET_CODE (op) == CONST_DOUBLE)
839 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
840 if (REAL_VALUES_EQUAL (r, dconst0) &&
841 ! REAL_VALUE_MINUS_ZERO (r))
843 REAL_VALUE_TO_TARGET_SINGLE (r, i);
844 if (! SPARC_SETHI_P (i)
845 && ! SPARC_SIMM13_P (i))
852 /* Nonzero if OP is an integer register. */
855 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
857 return (register_operand (op, SImode)
858 || (TARGET_ARCH64 && register_operand (op, DImode)));
861 /* Nonzero if OP is a floating point condition code register. */
864 fcc_reg_operand (rtx op, enum machine_mode mode)
866 /* This can happen when recog is called from combine. Op may be a MEM.
867 Fail instead of calling abort in this case. */
868 if (GET_CODE (op) != REG)
871 if (mode != VOIDmode && mode != GET_MODE (op))
874 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
877 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
878 if (reg_renumber == 0)
879 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
880 return REGNO_OK_FOR_CCFP_P (REGNO (op));
882 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
886 /* Nonzero if OP is a floating point condition code fcc0 register. */
889 fcc0_reg_operand (rtx op, enum machine_mode mode)
891 /* This can happen when recog is called from combine. Op may be a MEM.
892 Fail instead of calling abort in this case. */
893 if (GET_CODE (op) != REG)
896 if (mode != VOIDmode && mode != GET_MODE (op))
899 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
902 return REGNO (op) == SPARC_FCC_REG;
905 /* Nonzero if OP is an integer or floating point condition code register. */
908 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
910 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
912 if (mode != VOIDmode && mode != GET_MODE (op))
915 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
920 return fcc_reg_operand (op, mode);
923 /* Call insn on SPARC can take a PC-relative constant address, or any regular
927 call_operand (rtx op, enum machine_mode mode)
929 if (GET_CODE (op) != MEM)
932 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
936 call_operand_address (rtx op, enum machine_mode mode)
938 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
941 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
942 otherwise return 0. */
945 tls_symbolic_operand (rtx op)
947 if (GET_CODE (op) != SYMBOL_REF)
949 return SYMBOL_REF_TLS_MODEL (op);
953 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
955 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
959 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
961 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
965 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
967 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
971 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
973 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
976 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
977 reference and a constant. */
980 symbolic_operand (register rtx op, enum machine_mode mode)
982 enum machine_mode omode = GET_MODE (op);
984 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
987 switch (GET_CODE (op))
990 return !SYMBOL_REF_TLS_MODEL (op);
997 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
998 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
999 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1000 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1007 /* Return truth value of statement that OP is a symbolic memory
1008 operand of mode MODE. */
1011 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1013 if (GET_CODE (op) == SUBREG)
1014 op = SUBREG_REG (op);
1015 if (GET_CODE (op) != MEM)
1018 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
1019 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
1020 || GET_CODE (op) == LABEL_REF);
1023 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
1026 label_ref_operand (rtx op, enum machine_mode mode)
1028 if (GET_CODE (op) != LABEL_REF)
1030 if (GET_MODE (op) != mode)
1035 /* Return 1 if the operand is an argument used in generating pic references
1036 in either the medium/low or medium/anywhere code models of sparc64. */
1039 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1041 /* Check for (const (minus (symbol_ref:GOT)
1042 (const (minus (label) (pc))))). */
1043 if (GET_CODE (op) != CONST)
1046 if (GET_CODE (op) != MINUS)
1048 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
1050 /* ??? Ensure symbol is GOT. */
1051 if (GET_CODE (XEXP (op, 1)) != CONST)
1053 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
1058 /* Return 1 if the operand is a data segment reference. This includes
1059 the readonly data segment, or in other words anything but the text segment.
1060 This is needed in the medium/anywhere code model on v9. These values
1061 are accessed with EMBMEDANY_BASE_REG. */
1064 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1066 switch (GET_CODE (op))
1069 return ! SYMBOL_REF_FUNCTION_P (op);
1071 /* Assume canonical format of symbol + constant.
1074 return data_segment_operand (XEXP (op, 0), VOIDmode);
1080 /* Return 1 if the operand is a text segment reference.
1081 This is needed in the medium/anywhere code model on v9. */
1084 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1086 switch (GET_CODE (op))
1091 return SYMBOL_REF_FUNCTION_P (op);
1093 /* Assume canonical format of symbol + constant.
1096 return text_segment_operand (XEXP (op, 0), VOIDmode);
1102 /* Return 1 if the operand is either a register or a memory operand that is
1106 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
1108 if (register_operand (op, mode))
1111 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
1118 splittable_symbolic_memory_operand (rtx op,
1119 enum machine_mode mode ATTRIBUTE_UNUSED)
1121 if (GET_CODE (op) != MEM)
1123 if (! symbolic_operand (XEXP (op, 0), Pmode))
1129 splittable_immediate_memory_operand (rtx op,
1130 enum machine_mode mode ATTRIBUTE_UNUSED)
1132 if (GET_CODE (op) != MEM)
1134 if (! immediate_operand (XEXP (op, 0), Pmode))
1139 /* Return truth value of whether OP is EQ or NE. */
1142 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1144 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
1147 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
1148 or LTU for non-floating-point. We handle those specially. */
1151 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1155 if (!COMPARISON_P (op))
1158 if (GET_MODE (XEXP (op, 0)) == CCFPmode
1159 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
1162 code = GET_CODE (op);
1163 return (code != NE && code != EQ && code != GEU && code != LTU);
1166 /* Return 1 if this is a comparison operator. This allows the use of
1167 MATCH_OPERATOR to recognize all the branch insns. */
1170 noov_compare_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1174 if (!COMPARISON_P (op))
1177 code = GET_CODE (op);
1178 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
1179 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1180 /* These are the only branches which work with CC_NOOVmode. */
1181 return (code == EQ || code == NE || code == GE || code == LT);
1185 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
1186 MATCH_OPERATOR to recognize all the branch insns. */
1189 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1196 if (!COMPARISON_P (op))
1199 code = GET_CODE (op);
1200 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1201 /* These are the only branches which work with CCX_NOOVmode. */
1202 return (code == EQ || code == NE || code == GE || code == LT);
1203 return (GET_MODE (XEXP (op, 0)) == CCXmode);
1206 /* Nonzero if OP is a comparison operator suitable for use in v9
1207 conditional move or branch on register contents instructions. */
1210 v9_regcmp_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1214 if (!COMPARISON_P (op))
1217 code = GET_CODE (op);
1218 return v9_regcmp_p (code);
1221 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1224 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1226 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1229 /* Return nonzero if OP is an operator of mode MODE which can set
1230 the condition codes explicitly. We do not include PLUS and MINUS
1231 because these require CC_NOOVmode, which we handle explicitly. */
1234 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1236 if (GET_CODE (op) == AND
1237 || GET_CODE (op) == IOR
1238 || GET_CODE (op) == XOR)
1244 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1245 complement its second operand and set the condition codes explicitly. */
1248 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1250 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1251 and (xor ... (not ...)) to (not (xor ...)). */
1252 return (GET_CODE (op) == AND
1253 || GET_CODE (op) == IOR);
1256 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1257 signed 13 bit immediate field. This is an acceptable SImode operand for
1258 most 3 address instructions. */
1261 arith_operand (rtx op, enum machine_mode mode)
1263 if (register_operand (op, mode))
1265 if (GET_CODE (op) != CONST_INT)
1267 return SMALL_INT32 (op);
1270 /* Return true if OP is a constant 4096 */
1273 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1275 if (GET_CODE (op) != CONST_INT)
1278 return INTVAL (op) == 4096;
1281 /* Return true if OP is suitable as second operand for add/sub */
1284 arith_add_operand (rtx op, enum machine_mode mode)
1286 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1289 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1290 immediate field of OR and XOR instructions. Used for 64-bit
1291 constant formation patterns. */
1293 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1295 return ((GET_CODE (op) == CONST_INT
1296 && SPARC_SIMM13_P (INTVAL (op)))
1297 #if HOST_BITS_PER_WIDE_INT != 64
1298 || (GET_CODE (op) == CONST_DOUBLE
1299 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1300 && (CONST_DOUBLE_HIGH (op) ==
1301 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1302 (HOST_WIDE_INT)-1 : 0)))
1307 /* The same, but only for sethi instructions. */
1309 const64_high_operand (rtx op, enum machine_mode mode)
1311 return ((GET_CODE (op) == CONST_INT
1312 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1313 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1315 || (GET_CODE (op) == CONST_DOUBLE
1316 && CONST_DOUBLE_HIGH (op) == 0
1317 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1318 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1321 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1322 signed 11 bit immediate field. This is an acceptable SImode operand for
1323 the movcc instructions. */
1326 arith11_operand (rtx op, enum machine_mode mode)
1328 return (register_operand (op, mode)
1329 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1332 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1333 signed 10 bit immediate field. This is an acceptable SImode operand for
1334 the movrcc instructions. */
1337 arith10_operand (rtx op, enum machine_mode mode)
1339 return (register_operand (op, mode)
1340 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1343 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1344 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1346 ARCH64: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1347 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1348 for most 3 address instructions. */
1351 arith_double_operand (rtx op, enum machine_mode mode)
1353 return (register_operand (op, mode)
1354 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1356 && GET_CODE (op) == CONST_DOUBLE
1357 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1358 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1360 && GET_CODE (op) == CONST_DOUBLE
1361 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1362 && ((CONST_DOUBLE_HIGH (op) == -1
1363 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1364 || (CONST_DOUBLE_HIGH (op) == 0
1365 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1368 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1371 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1373 return (TARGET_ARCH64 &&
1374 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1375 (GET_CODE (op) == CONST_DOUBLE &&
1376 CONST_DOUBLE_LOW (op) == 4096 &&
1377 CONST_DOUBLE_HIGH (op) == 0)));
1380 /* Return true if OP is suitable as second operand for add/sub in DImode */
1383 arith_double_add_operand (rtx op, enum machine_mode mode)
1385 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1388 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1389 can fit in an 11 bit immediate field. This is an acceptable DImode
1390 operand for the movcc instructions. */
1391 /* ??? Replace with arith11_operand? */
1394 arith11_double_operand (rtx op, enum machine_mode mode)
1396 return (register_operand (op, mode)
1397 || (GET_CODE (op) == CONST_DOUBLE
1398 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1399 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1400 && ((CONST_DOUBLE_HIGH (op) == -1
1401 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1402 || (CONST_DOUBLE_HIGH (op) == 0
1403 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1404 || (GET_CODE (op) == CONST_INT
1405 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1406 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1409 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1410 can fit in an 10 bit immediate field. This is an acceptable DImode
1411 operand for the movrcc instructions. */
1412 /* ??? Replace with arith10_operand? */
1415 arith10_double_operand (rtx op, enum machine_mode mode)
1417 return (register_operand (op, mode)
1418 || (GET_CODE (op) == CONST_DOUBLE
1419 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1420 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1421 && ((CONST_DOUBLE_HIGH (op) == -1
1422 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1423 || (CONST_DOUBLE_HIGH (op) == 0
1424 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1425 || (GET_CODE (op) == CONST_INT
1426 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1427 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1430 /* Return truth value of whether OP is an integer which fits the
1431 range constraining immediate operands in most three-address insns,
1432 which have a 13 bit immediate field. */
1435 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1437 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1441 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1443 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1444 || (GET_CODE (op) == CONST_DOUBLE
1445 && CONST_DOUBLE_HIGH (op) == 0
1446 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1449 /* Recognize operand values for the umul instruction. That instruction sign
1450 extends immediate values just like all other sparc instructions, but
1451 interprets the extended result as an unsigned number. */
1454 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1456 #if HOST_BITS_PER_WIDE_INT > 32
1457 /* All allowed constants will fit a CONST_INT. */
1458 return (GET_CODE (op) == CONST_INT
1459 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1460 || (INTVAL (op) >= 0xFFFFF000
1461 && INTVAL (op) <= 0xFFFFFFFF)));
1463 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1464 || (GET_CODE (op) == CONST_DOUBLE
1465 && CONST_DOUBLE_HIGH (op) == 0
1466 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1471 uns_arith_operand (rtx op, enum machine_mode mode)
1473 return register_operand (op, mode) || uns_small_int (op, mode);
1476 /* Return truth value of statement that OP is a call-clobbered register. */
1478 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1480 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1483 /* Return 1 if OP is a valid operand for the source of a move insn. */
1486 input_operand (rtx op, enum machine_mode mode)
1488 /* If both modes are non-void they must be the same. */
1489 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1492 /* Allow any one instruction integer constant, and all CONST_INT
1493 variants when we are working in DImode and !arch64. */
1494 if (GET_MODE_CLASS (mode) == MODE_INT
1495 && ((GET_CODE (op) == CONST_INT
1496 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1497 || SPARC_SIMM13_P (INTVAL (op))
1499 && ! TARGET_ARCH64)))
1501 && GET_CODE (op) == CONST_DOUBLE
1502 && ((CONST_DOUBLE_HIGH (op) == 0
1503 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1505 #if HOST_BITS_PER_WIDE_INT == 64
1506 (CONST_DOUBLE_HIGH (op) == 0
1507 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1509 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1510 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1511 && CONST_DOUBLE_HIGH (op) == 0)
1512 || (CONST_DOUBLE_HIGH (op) == -1
1513 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1518 /* If !arch64 and this is a DImode const, allow it so that
1519 the splits can be generated. */
1522 && GET_CODE (op) == CONST_DOUBLE)
1525 if (register_operand (op, mode))
1528 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1529 && GET_CODE (op) == CONST_DOUBLE)
1532 /* If this is a SUBREG, look inside so that we handle
1533 paradoxical ones. */
1534 if (GET_CODE (op) == SUBREG)
1535 op = SUBREG_REG (op);
1537 /* Check for valid MEM forms. */
1538 if (GET_CODE (op) == MEM)
1540 rtx inside = XEXP (op, 0);
1542 if (GET_CODE (inside) == LO_SUM)
1544 /* We can't allow these because all of the splits
1545 (eventually as they trickle down into DFmode
1546 splits) require offsettable memory references. */
1548 && GET_MODE (op) == TFmode)
1551 return (register_operand (XEXP (inside, 0), Pmode)
1552 && CONSTANT_P (XEXP (inside, 1)));
1554 return memory_address_p (mode, inside);
1560 /* Return 1 if OP is valid for the lhs of a compare insn. */
1563 compare_operand (rtx op, enum machine_mode mode)
1565 if (GET_CODE (op) == ZERO_EXTRACT)
1566 return (register_operand (XEXP (op, 0), mode)
1567 && small_int_or_double (XEXP (op, 1), mode)
1568 && small_int_or_double (XEXP (op, 2), mode)
1569 /* This matches cmp_zero_extract. */
1571 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1572 && INTVAL (XEXP (op, 2)) > 19)
1573 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1574 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19)))
1575 /* This matches cmp_zero_extract_sp64. */
1578 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1579 && INTVAL (XEXP (op, 2)) > 51)
1580 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1581 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51)))));
1583 return register_operand (op, mode);
1587 /* We know it can't be done in one insn when we get here,
1588 the movsi expander guarantees this. */
1590 sparc_emit_set_const32 (rtx op0, rtx op1)
1592 enum machine_mode mode = GET_MODE (op0);
1595 if (GET_CODE (op1) == CONST_INT)
1597 HOST_WIDE_INT value = INTVAL (op1);
1599 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1600 || SPARC_SIMM13_P (value))
1604 /* Full 2-insn decomposition is needed. */
1605 if (reload_in_progress || reload_completed)
1608 temp = gen_reg_rtx (mode);
1610 if (GET_CODE (op1) == CONST_INT)
1612 /* Emit them as real moves instead of a HIGH/LO_SUM,
1613 this way CSE can see everything and reuse intermediate
1614 values if it wants. */
1616 && HOST_BITS_PER_WIDE_INT != 64
1617 && (INTVAL (op1) & 0x80000000) != 0)
1618 emit_insn (gen_rtx_SET
1620 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1623 emit_insn (gen_rtx_SET (VOIDmode, temp,
1624 GEN_INT (INTVAL (op1)
1625 & ~(HOST_WIDE_INT)0x3ff)));
1627 emit_insn (gen_rtx_SET (VOIDmode,
1629 gen_rtx_IOR (mode, temp,
1630 GEN_INT (INTVAL (op1) & 0x3ff))));
1634 /* A symbol, emit in the traditional way. */
1635 emit_insn (gen_rtx_SET (VOIDmode, temp,
1636 gen_rtx_HIGH (mode, op1)));
1637 emit_insn (gen_rtx_SET (VOIDmode,
1638 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1644 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1645 If TEMP is non-zero, we are forbidden to use any other scratch
1646 registers. Otherwise, we are allowed to generate them as needed.
1648 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1649 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1651 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1653 rtx temp1, temp2, temp3, temp4, temp5;
1656 if (temp && GET_MODE (temp) == TImode)
1659 temp = gen_rtx_REG (DImode, REGNO (temp));
1662 /* SPARC-V9 code-model support. */
1663 switch (sparc_cmodel)
1666 /* The range spanned by all instructions in the object is less
1667 than 2^31 bytes (2GB) and the distance from any instruction
1668 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1669 than 2^31 bytes (2GB).
1671 The executable must be in the low 4TB of the virtual address
1674 sethi %hi(symbol), %temp1
1675 or %temp1, %lo(symbol), %reg */
1677 temp1 = temp; /* op0 is allowed. */
1679 temp1 = gen_reg_rtx (DImode);
1681 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1682 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1686 /* The range spanned by all instructions in the object is less
1687 than 2^31 bytes (2GB) and the distance from any instruction
1688 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1689 than 2^31 bytes (2GB).
1691 The executable must be in the low 16TB of the virtual address
1694 sethi %h44(symbol), %temp1
1695 or %temp1, %m44(symbol), %temp2
1696 sllx %temp2, 12, %temp3
1697 or %temp3, %l44(symbol), %reg */
1702 temp3 = temp; /* op0 is allowed. */
1706 temp1 = gen_reg_rtx (DImode);
1707 temp2 = gen_reg_rtx (DImode);
1708 temp3 = gen_reg_rtx (DImode);
1711 emit_insn (gen_seth44 (temp1, op1));
1712 emit_insn (gen_setm44 (temp2, temp1, op1));
1713 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1714 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1715 emit_insn (gen_setl44 (op0, temp3, op1));
1719 /* The range spanned by all instructions in the object is less
1720 than 2^31 bytes (2GB) and the distance from any instruction
1721 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1722 than 2^31 bytes (2GB).
1724 The executable can be placed anywhere in the virtual address
1727 sethi %hh(symbol), %temp1
1728 sethi %lm(symbol), %temp2
1729 or %temp1, %hm(symbol), %temp3
1730 sllx %temp3, 32, %temp4
1731 or %temp4, %temp2, %temp5
1732 or %temp5, %lo(symbol), %reg */
1735 /* It is possible that one of the registers we got for operands[2]
1736 might coincide with that of operands[0] (which is why we made
1737 it TImode). Pick the other one to use as our scratch. */
1738 if (rtx_equal_p (temp, op0))
1741 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1746 temp2 = temp; /* op0 is _not_ allowed, see above. */
1753 temp1 = gen_reg_rtx (DImode);
1754 temp2 = gen_reg_rtx (DImode);
1755 temp3 = gen_reg_rtx (DImode);
1756 temp4 = gen_reg_rtx (DImode);
1757 temp5 = gen_reg_rtx (DImode);
1760 emit_insn (gen_sethh (temp1, op1));
1761 emit_insn (gen_setlm (temp2, op1));
1762 emit_insn (gen_sethm (temp3, temp1, op1));
1763 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1764 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1765 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1766 gen_rtx_PLUS (DImode, temp4, temp2)));
1767 emit_insn (gen_setlo (op0, temp5, op1));
1771 /* Old old old backwards compatibility kruft here.
1772 Essentially it is MEDLOW with a fixed 64-bit
1773 virtual base added to all data segment addresses.
1774 Text-segment stuff is computed like MEDANY, we can't
1775 reuse the code above because the relocation knobs
1778 Data segment: sethi %hi(symbol), %temp1
1779 add %temp1, EMBMEDANY_BASE_REG, %temp2
1780 or %temp2, %lo(symbol), %reg */
1781 if (data_segment_operand (op1, GET_MODE (op1)))
1785 temp1 = temp; /* op0 is allowed. */
1790 temp1 = gen_reg_rtx (DImode);
1791 temp2 = gen_reg_rtx (DImode);
1794 emit_insn (gen_embmedany_sethi (temp1, op1));
1795 emit_insn (gen_embmedany_brsum (temp2, temp1));
1796 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1799 /* Text segment: sethi %uhi(symbol), %temp1
1800 sethi %hi(symbol), %temp2
1801 or %temp1, %ulo(symbol), %temp3
1802 sllx %temp3, 32, %temp4
1803 or %temp4, %temp2, %temp5
1804 or %temp5, %lo(symbol), %reg */
1809 /* It is possible that one of the registers we got for operands[2]
1810 might coincide with that of operands[0] (which is why we made
1811 it TImode). Pick the other one to use as our scratch. */
1812 if (rtx_equal_p (temp, op0))
1815 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1820 temp2 = temp; /* op0 is _not_ allowed, see above. */
1827 temp1 = gen_reg_rtx (DImode);
1828 temp2 = gen_reg_rtx (DImode);
1829 temp3 = gen_reg_rtx (DImode);
1830 temp4 = gen_reg_rtx (DImode);
1831 temp5 = gen_reg_rtx (DImode);
1834 emit_insn (gen_embmedany_textuhi (temp1, op1));
1835 emit_insn (gen_embmedany_texthi (temp2, op1));
1836 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1837 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1838 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1839 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1840 gen_rtx_PLUS (DImode, temp4, temp2)));
1841 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1850 /* These avoid problems when cross compiling. If we do not
1851 go through all this hair then the optimizer will see
1852 invalid REG_EQUAL notes or in some cases none at all. */
1853 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1854 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1855 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1856 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1858 #if HOST_BITS_PER_WIDE_INT == 64
1859 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1860 #define GEN_INT64(__x) GEN_INT (__x)
1862 #define GEN_HIGHINT64(__x) \
1863 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1864 #define GEN_INT64(__x) \
1865 immed_double_const ((__x) & 0xffffffff, \
1866 ((__x) & 0x80000000 ? -1 : 0), DImode)
1869 /* The optimizer is not to assume anything about exactly
1870 which bits are set for a HIGH, they are unspecified.
1871 Unfortunately this leads to many missed optimizations
1872 during CSE. We mask out the non-HIGH bits, and matches
1873 a plain movdi, to alleviate this problem. */
1875 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1877 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1881 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1883 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1887 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1889 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1893 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1895 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1898 /* Worker routines for 64-bit constant formation on arch64.
1899 One of the key things to be doing in these emissions is
1900 to create as many temp REGs as possible. This makes it
1901 possible for half-built constants to be used later when
1902 such values are similar to something required later on.
1903 Without doing this, the optimizer cannot see such
1906 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1907 unsigned HOST_WIDE_INT, int);
1910 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1911 unsigned HOST_WIDE_INT low_bits, int is_neg)
1913 unsigned HOST_WIDE_INT high_bits;
1916 high_bits = (~low_bits) & 0xffffffff;
1918 high_bits = low_bits;
1920 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1923 emit_insn (gen_rtx_SET (VOIDmode, op0,
1924 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1928 /* If we are XOR'ing with -1, then we should emit a one's complement
1929 instead. This way the combiner will notice logical operations
1930 such as ANDN later on and substitute. */
1931 if ((low_bits & 0x3ff) == 0x3ff)
1933 emit_insn (gen_rtx_SET (VOIDmode, op0,
1934 gen_rtx_NOT (DImode, temp)));
1938 emit_insn (gen_rtx_SET (VOIDmode, op0,
1939 gen_safe_XOR64 (temp,
1940 (-(HOST_WIDE_INT)0x400
1941 | (low_bits & 0x3ff)))));
1946 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1947 unsigned HOST_WIDE_INT, int);
1950 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1951 unsigned HOST_WIDE_INT high_bits,
1952 unsigned HOST_WIDE_INT low_immediate,
1957 if ((high_bits & 0xfffffc00) != 0)
1959 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1960 if ((high_bits & ~0xfffffc00) != 0)
1961 emit_insn (gen_rtx_SET (VOIDmode, op0,
1962 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1968 emit_insn (gen_safe_SET64 (temp, high_bits));
1972 /* Now shift it up into place. */
1973 emit_insn (gen_rtx_SET (VOIDmode, op0,
1974 gen_rtx_ASHIFT (DImode, temp2,
1975 GEN_INT (shift_count))));
1977 /* If there is a low immediate part piece, finish up by
1978 putting that in as well. */
1979 if (low_immediate != 0)
1980 emit_insn (gen_rtx_SET (VOIDmode, op0,
1981 gen_safe_OR64 (op0, low_immediate)));
1984 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1985 unsigned HOST_WIDE_INT);
1987 /* Full 64-bit constant decomposition. Even though this is the
1988 'worst' case, we still optimize a few things away. */
1990 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1991 unsigned HOST_WIDE_INT high_bits,
1992 unsigned HOST_WIDE_INT low_bits)
1996 if (reload_in_progress || reload_completed)
1999 sub_temp = gen_reg_rtx (DImode);
2001 if ((high_bits & 0xfffffc00) != 0)
2003 sparc_emit_set_safe_HIGH64 (temp, high_bits);
2004 if ((high_bits & ~0xfffffc00) != 0)
2005 emit_insn (gen_rtx_SET (VOIDmode,
2007 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
2013 emit_insn (gen_safe_SET64 (temp, high_bits));
2017 if (!reload_in_progress && !reload_completed)
2019 rtx temp2 = gen_reg_rtx (DImode);
2020 rtx temp3 = gen_reg_rtx (DImode);
2021 rtx temp4 = gen_reg_rtx (DImode);
2023 emit_insn (gen_rtx_SET (VOIDmode, temp4,
2024 gen_rtx_ASHIFT (DImode, sub_temp,
2027 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
2028 if ((low_bits & ~0xfffffc00) != 0)
2030 emit_insn (gen_rtx_SET (VOIDmode, temp3,
2031 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
2032 emit_insn (gen_rtx_SET (VOIDmode, op0,
2033 gen_rtx_PLUS (DImode, temp4, temp3)));
2037 emit_insn (gen_rtx_SET (VOIDmode, op0,
2038 gen_rtx_PLUS (DImode, temp4, temp2)));
2043 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
2044 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
2045 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
2048 /* We are in the middle of reload, so this is really
2049 painful. However we do still make an attempt to
2050 avoid emitting truly stupid code. */
2051 if (low1 != const0_rtx)
2053 emit_insn (gen_rtx_SET (VOIDmode, op0,
2054 gen_rtx_ASHIFT (DImode, sub_temp,
2055 GEN_INT (to_shift))));
2056 emit_insn (gen_rtx_SET (VOIDmode, op0,
2057 gen_rtx_IOR (DImode, op0, low1)));
2065 if (low2 != const0_rtx)
2067 emit_insn (gen_rtx_SET (VOIDmode, op0,
2068 gen_rtx_ASHIFT (DImode, sub_temp,
2069 GEN_INT (to_shift))));
2070 emit_insn (gen_rtx_SET (VOIDmode, op0,
2071 gen_rtx_IOR (DImode, op0, low2)));
2079 emit_insn (gen_rtx_SET (VOIDmode, op0,
2080 gen_rtx_ASHIFT (DImode, sub_temp,
2081 GEN_INT (to_shift))));
2082 if (low3 != const0_rtx)
2083 emit_insn (gen_rtx_SET (VOIDmode, op0,
2084 gen_rtx_IOR (DImode, op0, low3)));
2089 /* Analyze a 64-bit constant for certain properties. */
2090 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
2091 unsigned HOST_WIDE_INT,
2092 int *, int *, int *);
2095 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
2096 unsigned HOST_WIDE_INT low_bits,
2097 int *hbsp, int *lbsp, int *abbasp)
2099 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
2102 lowest_bit_set = highest_bit_set = -1;
2106 if ((lowest_bit_set == -1)
2107 && ((low_bits >> i) & 1))
2109 if ((highest_bit_set == -1)
2110 && ((high_bits >> (32 - i - 1)) & 1))
2111 highest_bit_set = (64 - i - 1);
2114 && ((highest_bit_set == -1)
2115 || (lowest_bit_set == -1)));
2121 if ((lowest_bit_set == -1)
2122 && ((high_bits >> i) & 1))
2123 lowest_bit_set = i + 32;
2124 if ((highest_bit_set == -1)
2125 && ((low_bits >> (32 - i - 1)) & 1))
2126 highest_bit_set = 32 - i - 1;
2129 && ((highest_bit_set == -1)
2130 || (lowest_bit_set == -1)));
2132 /* If there are no bits set this should have gone out
2133 as one instruction! */
2134 if (lowest_bit_set == -1
2135 || highest_bit_set == -1)
2137 all_bits_between_are_set = 1;
2138 for (i = lowest_bit_set; i <= highest_bit_set; i++)
2142 if ((low_bits & (1 << i)) != 0)
2147 if ((high_bits & (1 << (i - 32))) != 0)
2150 all_bits_between_are_set = 0;
2153 *hbsp = highest_bit_set;
2154 *lbsp = lowest_bit_set;
2155 *abbasp = all_bits_between_are_set;
2158 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
2161 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
2162 unsigned HOST_WIDE_INT low_bits)
2164 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
2167 || high_bits == 0xffffffff)
2170 analyze_64bit_constant (high_bits, low_bits,
2171 &highest_bit_set, &lowest_bit_set,
2172 &all_bits_between_are_set);
2174 if ((highest_bit_set == 63
2175 || lowest_bit_set == 0)
2176 && all_bits_between_are_set != 0)
2179 if ((highest_bit_set - lowest_bit_set) < 21)
2185 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
2186 unsigned HOST_WIDE_INT,
2189 static unsigned HOST_WIDE_INT
2190 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
2191 unsigned HOST_WIDE_INT low_bits,
2192 int lowest_bit_set, int shift)
2194 HOST_WIDE_INT hi, lo;
2196 if (lowest_bit_set < 32)
2198 lo = (low_bits >> lowest_bit_set) << shift;
2199 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
2204 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
2211 /* Here we are sure to be arch64 and this is an integer constant
2212 being loaded into a register. Emit the most efficient
2213 insn sequence possible. Detection of all the 1-insn cases
2214 has been done already. */
2216 sparc_emit_set_const64 (rtx op0, rtx op1)
2218 unsigned HOST_WIDE_INT high_bits, low_bits;
2219 int lowest_bit_set, highest_bit_set;
2220 int all_bits_between_are_set;
2223 /* Sanity check that we know what we are working with. */
2224 if (! TARGET_ARCH64)
2227 if (GET_CODE (op0) != SUBREG)
2229 if (GET_CODE (op0) != REG
2230 || (REGNO (op0) >= SPARC_FIRST_FP_REG
2231 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
2235 if (reload_in_progress || reload_completed)
2238 if (GET_CODE (op1) != CONST_DOUBLE
2239 && GET_CODE (op1) != CONST_INT)
2241 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2246 temp = gen_reg_rtx (DImode);
2248 if (GET_CODE (op1) == CONST_DOUBLE)
2250 #if HOST_BITS_PER_WIDE_INT == 64
2251 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
2252 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
2254 high_bits = CONST_DOUBLE_HIGH (op1);
2255 low_bits = CONST_DOUBLE_LOW (op1);
2260 #if HOST_BITS_PER_WIDE_INT == 64
2261 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2262 low_bits = (INTVAL (op1) & 0xffffffff);
2264 high_bits = ((INTVAL (op1) < 0) ?
2267 low_bits = INTVAL (op1);
2271 /* low_bits bits 0 --> 31
2272 high_bits bits 32 --> 63 */
2274 analyze_64bit_constant (high_bits, low_bits,
2275 &highest_bit_set, &lowest_bit_set,
2276 &all_bits_between_are_set);
2278 /* First try for a 2-insn sequence. */
2280 /* These situations are preferred because the optimizer can
2281 * do more things with them:
2283 * sllx %reg, shift, %reg
2285 * srlx %reg, shift, %reg
2286 * 3) mov some_small_const, %reg
2287 * sllx %reg, shift, %reg
2289 if (((highest_bit_set == 63
2290 || lowest_bit_set == 0)
2291 && all_bits_between_are_set != 0)
2292 || ((highest_bit_set - lowest_bit_set) < 12))
2294 HOST_WIDE_INT the_const = -1;
2295 int shift = lowest_bit_set;
2297 if ((highest_bit_set != 63
2298 && lowest_bit_set != 0)
2299 || all_bits_between_are_set == 0)
2302 create_simple_focus_bits (high_bits, low_bits,
2305 else if (lowest_bit_set == 0)
2306 shift = -(63 - highest_bit_set);
2308 if (! SPARC_SIMM13_P (the_const))
2311 emit_insn (gen_safe_SET64 (temp, the_const));
2313 emit_insn (gen_rtx_SET (VOIDmode,
2315 gen_rtx_ASHIFT (DImode,
2319 emit_insn (gen_rtx_SET (VOIDmode,
2321 gen_rtx_LSHIFTRT (DImode,
2323 GEN_INT (-shift))));
2329 /* Now a range of 22 or less bits set somewhere.
2330 * 1) sethi %hi(focus_bits), %reg
2331 * sllx %reg, shift, %reg
2332 * 2) sethi %hi(focus_bits), %reg
2333 * srlx %reg, shift, %reg
2335 if ((highest_bit_set - lowest_bit_set) < 21)
2337 unsigned HOST_WIDE_INT focus_bits =
2338 create_simple_focus_bits (high_bits, low_bits,
2339 lowest_bit_set, 10);
2341 if (! SPARC_SETHI_P (focus_bits))
2344 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2346 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2347 if (lowest_bit_set < 10)
2348 emit_insn (gen_rtx_SET (VOIDmode,
2350 gen_rtx_LSHIFTRT (DImode, temp,
2351 GEN_INT (10 - lowest_bit_set))));
2352 else if (lowest_bit_set > 10)
2353 emit_insn (gen_rtx_SET (VOIDmode,
2355 gen_rtx_ASHIFT (DImode, temp,
2356 GEN_INT (lowest_bit_set - 10))));
2362 /* 1) sethi %hi(low_bits), %reg
2363 * or %reg, %lo(low_bits), %reg
2364 * 2) sethi %hi(~low_bits), %reg
2365 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2368 || high_bits == 0xffffffff)
2370 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2371 (high_bits == 0xffffffff));
2375 /* Now, try 3-insn sequences. */
2377 /* 1) sethi %hi(high_bits), %reg
2378 * or %reg, %lo(high_bits), %reg
2379 * sllx %reg, 32, %reg
2383 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2387 /* We may be able to do something quick
2388 when the constant is negated, so try that. */
2389 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2390 (~low_bits) & 0xfffffc00))
2392 /* NOTE: The trailing bits get XOR'd so we need the
2393 non-negated bits, not the negated ones. */
2394 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2396 if ((((~high_bits) & 0xffffffff) == 0
2397 && ((~low_bits) & 0x80000000) == 0)
2398 || (((~high_bits) & 0xffffffff) == 0xffffffff
2399 && ((~low_bits) & 0x80000000) != 0))
2401 int fast_int = (~low_bits & 0xffffffff);
2403 if ((SPARC_SETHI_P (fast_int)
2404 && (~high_bits & 0xffffffff) == 0)
2405 || SPARC_SIMM13_P (fast_int))
2406 emit_insn (gen_safe_SET64 (temp, fast_int));
2408 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2413 #if HOST_BITS_PER_WIDE_INT == 64
2414 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2415 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2417 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2418 (~high_bits) & 0xffffffff,
2421 sparc_emit_set_const64 (temp, negated_const);
2424 /* If we are XOR'ing with -1, then we should emit a one's complement
2425 instead. This way the combiner will notice logical operations
2426 such as ANDN later on and substitute. */
2427 if (trailing_bits == 0x3ff)
2429 emit_insn (gen_rtx_SET (VOIDmode, op0,
2430 gen_rtx_NOT (DImode, temp)));
2434 emit_insn (gen_rtx_SET (VOIDmode,
2436 gen_safe_XOR64 (temp,
2437 (-0x400 | trailing_bits))));
2442 /* 1) sethi %hi(xxx), %reg
2443 * or %reg, %lo(xxx), %reg
2444 * sllx %reg, yyy, %reg
2446 * ??? This is just a generalized version of the low_bits==0
2447 * thing above, FIXME...
2449 if ((highest_bit_set - lowest_bit_set) < 32)
2451 unsigned HOST_WIDE_INT focus_bits =
2452 create_simple_focus_bits (high_bits, low_bits,
2455 /* We can't get here in this state. */
2456 if (highest_bit_set < 32
2457 || lowest_bit_set >= 32)
2460 /* So what we know is that the set bits straddle the
2461 middle of the 64-bit word. */
2462 sparc_emit_set_const64_quick2 (op0, temp,
2468 /* 1) sethi %hi(high_bits), %reg
2469 * or %reg, %lo(high_bits), %reg
2470 * sllx %reg, 32, %reg
2471 * or %reg, low_bits, %reg
2473 if (SPARC_SIMM13_P(low_bits)
2474 && ((int)low_bits > 0))
2476 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2480 /* The easiest way when all else fails, is full decomposition. */
2482 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2483 high_bits, low_bits, ~high_bits, ~low_bits);
2485 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2488 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2489 return the mode to be used for the comparison. For floating-point,
2490 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2491 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2492 processing is needed. */
2495 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2497 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2523 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2524 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2526 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2527 return CCX_NOOVmode;
2533 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2540 /* X and Y are two things to compare using CODE. Emit the compare insn and
2541 return the rtx for the cc reg in the proper mode. */
2544 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2546 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2549 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2550 fcc regs (cse can't tell they're really call clobbered regs and will
2551 remove a duplicate comparison even if there is an intervening function
2552 call - it will then try to reload the cc reg via an int reg which is why
2553 we need the movcc patterns). It is possible to provide the movcc
2554 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2555 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2556 to tell cse that CCFPE mode registers (even pseudos) are call
2559 /* ??? This is an experiment. Rather than making changes to cse which may
2560 or may not be easy/clean, we do our own cse. This is possible because
2561 we will generate hard registers. Cse knows they're call clobbered (it
2562 doesn't know the same thing about pseudos). If we guess wrong, no big
2563 deal, but if we win, great! */
2565 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2566 #if 1 /* experiment */
2569 /* We cycle through the registers to ensure they're all exercised. */
2570 static int next_fcc_reg = 0;
2571 /* Previous x,y for each fcc reg. */
2572 static rtx prev_args[4][2];
2574 /* Scan prev_args for x,y. */
2575 for (reg = 0; reg < 4; reg++)
2576 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2581 prev_args[reg][0] = x;
2582 prev_args[reg][1] = y;
2583 next_fcc_reg = (next_fcc_reg + 1) & 3;
2585 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2588 cc_reg = gen_reg_rtx (mode);
2589 #endif /* ! experiment */
2590 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2591 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2593 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2595 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2596 gen_rtx_COMPARE (mode, x, y)));
2601 /* This function is used for v9 only.
2602 CODE is the code for an Scc's comparison.
2603 OPERANDS[0] is the target of the Scc insn.
2604 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2605 been generated yet).
2607 This function is needed to turn
2610 (gt (reg:CCX 100 %icc)
2614 (gt:DI (reg:CCX 100 %icc)
2617 IE: The instruction recognizer needs to see the mode of the comparison to
2618 find the right instruction. We could use "gt:DI" right in the
2619 define_expand, but leaving it out allows us to handle DI, SI, etc.
2621 We refer to the global sparc compare operands sparc_compare_op0 and
2622 sparc_compare_op1. */
2625 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2630 && (GET_MODE (sparc_compare_op0) == DImode
2631 || GET_MODE (operands[0]) == DImode))
2634 op0 = sparc_compare_op0;
2635 op1 = sparc_compare_op1;
2637 /* Try to use the movrCC insns. */
2639 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2640 && op1 == const0_rtx
2641 && v9_regcmp_p (compare_code))
2643 /* Special case for op0 != 0. This can be done with one instruction if
2644 operands[0] == sparc_compare_op0. */
2646 if (compare_code == NE
2647 && GET_MODE (operands[0]) == DImode
2648 && rtx_equal_p (op0, operands[0]))
2650 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2651 gen_rtx_IF_THEN_ELSE (DImode,
2652 gen_rtx_fmt_ee (compare_code, DImode,
2659 if (reg_overlap_mentioned_p (operands[0], op0))
2661 /* Handle the case where operands[0] == sparc_compare_op0.
2662 We "early clobber" the result. */
2663 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2664 emit_move_insn (op0, sparc_compare_op0);
2667 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2668 if (GET_MODE (op0) != DImode)
2670 temp = gen_reg_rtx (DImode);
2671 convert_move (temp, op0, 0);
2675 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2676 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2677 gen_rtx_fmt_ee (compare_code, DImode,
2685 operands[1] = gen_compare_reg (compare_code, op0, op1);
2687 switch (GET_MODE (operands[1]))
2697 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2698 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2699 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2700 gen_rtx_fmt_ee (compare_code,
2701 GET_MODE (operands[1]),
2702 operands[1], const0_rtx),
2703 const1_rtx, operands[0])));
2708 /* Emit a conditional jump insn for the v9 architecture using comparison code
2709 CODE and jump target LABEL.
2710 This function exists to take advantage of the v9 brxx insns. */
2713 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2715 emit_jump_insn (gen_rtx_SET (VOIDmode,
2717 gen_rtx_IF_THEN_ELSE (VOIDmode,
2718 gen_rtx_fmt_ee (code, GET_MODE (op0),
2720 gen_rtx_LABEL_REF (VOIDmode, label),
2724 /* Generate a DFmode part of a hard TFmode register.
2725 REG is the TFmode hard register, LOW is 1 for the
2726 low 64bit of the register and 0 otherwise.
2729 gen_df_reg (rtx reg, int low)
2731 int regno = REGNO (reg);
2733 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2734 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2735 return gen_rtx_REG (DFmode, regno);
2738 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2739 Unlike normal calls, TFmode operands are passed by reference. It is
2740 assumed that no more than 3 operands are required. */
2743 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2745 rtx ret_slot = NULL, arg[3], func_sym;
2748 /* We only expect to be called for conversions, unary, and binary ops. */
2749 if (nargs < 2 || nargs > 3)
2752 for (i = 0; i < nargs; ++i)
2754 rtx this_arg = operands[i];
2757 /* TFmode arguments and return values are passed by reference. */
2758 if (GET_MODE (this_arg) == TFmode)
2760 int force_stack_temp;
2762 force_stack_temp = 0;
2763 if (TARGET_BUGGY_QP_LIB && i == 0)
2764 force_stack_temp = 1;
2766 if (GET_CODE (this_arg) == MEM
2767 && ! force_stack_temp)
2768 this_arg = XEXP (this_arg, 0);
2769 else if (CONSTANT_P (this_arg)
2770 && ! force_stack_temp)
2772 this_slot = force_const_mem (TFmode, this_arg);
2773 this_arg = XEXP (this_slot, 0);
2777 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2779 /* Operand 0 is the return value. We'll copy it out later. */
2781 emit_move_insn (this_slot, this_arg);
2783 ret_slot = this_slot;
2785 this_arg = XEXP (this_slot, 0);
2792 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2794 if (GET_MODE (operands[0]) == TFmode)
2797 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2798 arg[0], GET_MODE (arg[0]),
2799 arg[1], GET_MODE (arg[1]));
2801 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2802 arg[0], GET_MODE (arg[0]),
2803 arg[1], GET_MODE (arg[1]),
2804 arg[2], GET_MODE (arg[2]));
2807 emit_move_insn (operands[0], ret_slot);
2816 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2817 GET_MODE (operands[0]), 1,
2818 arg[1], GET_MODE (arg[1]));
2820 if (ret != operands[0])
2821 emit_move_insn (operands[0], ret);
2825 /* Expand soft-float TFmode calls to sparc abi routines. */
2828 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2850 emit_soft_tfmode_libcall (func, 3, operands);
2854 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2867 emit_soft_tfmode_libcall (func, 2, operands);
2871 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2878 switch (GET_MODE (operands[1]))
2891 case FLOAT_TRUNCATE:
2892 switch (GET_MODE (operands[0]))
2906 switch (GET_MODE (operands[1]))
2919 case UNSIGNED_FLOAT:
2920 switch (GET_MODE (operands[1]))
2934 switch (GET_MODE (operands[0]))
2948 switch (GET_MODE (operands[0]))
2965 emit_soft_tfmode_libcall (func, 2, operands);
2968 /* Expand a hard-float tfmode operation. All arguments must be in
2972 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2976 if (GET_RTX_CLASS (code) == RTX_UNARY)
2978 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2979 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2983 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2984 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2985 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2986 operands[1], operands[2]);
2989 if (register_operand (operands[0], VOIDmode))
2992 dest = gen_reg_rtx (GET_MODE (operands[0]));
2994 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2996 if (dest != operands[0])
2997 emit_move_insn (operands[0], dest);
3001 emit_tfmode_binop (enum rtx_code code, rtx *operands)
3003 if (TARGET_HARD_QUAD)
3004 emit_hard_tfmode_operation (code, operands);
3006 emit_soft_tfmode_binop (code, operands);
3010 emit_tfmode_unop (enum rtx_code code, rtx *operands)
3012 if (TARGET_HARD_QUAD)
3013 emit_hard_tfmode_operation (code, operands);
3015 emit_soft_tfmode_unop (code, operands);
3019 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
3021 if (TARGET_HARD_QUAD)
3022 emit_hard_tfmode_operation (code, operands);
3024 emit_soft_tfmode_cvt (code, operands);
3027 /* Return nonzero if a branch/jump/call instruction will be emitting
3028 nop into its delay slot. */
3031 empty_delay_slot (rtx insn)
3035 /* If no previous instruction (should not happen), return true. */
3036 if (PREV_INSN (insn) == NULL)
3039 seq = NEXT_INSN (PREV_INSN (insn));
3040 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
3046 /* Return nonzero if TRIAL can go into the call delay slot. */
3049 tls_call_delay (rtx trial)
3054 call __tls_get_addr, %tgd_call (foo)
3055 add %l7, %o0, %o0, %tgd_add (foo)
3056 while Sun as/ld does not. */
3057 if (TARGET_GNU_TLS || !TARGET_TLS)
3060 pat = PATTERN (trial);
3061 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
3064 unspec = XEXP (SET_DEST (pat), 1);
3065 if (GET_CODE (unspec) != UNSPEC
3066 || (XINT (unspec, 1) != UNSPEC_TLSGD
3067 && XINT (unspec, 1) != UNSPEC_TLSLDM))
3073 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3074 instruction. RETURN_P is true if the v9 variant 'return' is to be
3075 considered in the test too.
3077 TRIAL must be a SET whose destination is a REG appropriate for the
3078 'restore' instruction or, if RETURN_P is true, for the 'return'
3082 eligible_for_restore_insn (rtx trial, bool return_p)
3084 rtx pat = PATTERN (trial);
3085 rtx src = SET_SRC (pat);
3087 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3088 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3089 && arith_operand (src, GET_MODE (src)))
3092 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3094 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3097 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3098 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3099 && arith_double_operand (src, GET_MODE (src)))
3100 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3102 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3103 else if (! TARGET_FPU && register_operand (src, SFmode))
3106 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3107 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
3110 /* If we have the 'return' instruction, anything that does not use
3111 local or output registers and can go into a delay slot wins. */
3112 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
3113 && (get_attr_in_uncond_branch_delay (trial)
3114 == IN_UNCOND_BRANCH_DELAY_TRUE))
3117 /* The 'restore src1,src2,dest' pattern for SImode. */
3118 else if (GET_CODE (src) == PLUS
3119 && register_operand (XEXP (src, 0), SImode)
3120 && arith_operand (XEXP (src, 1), SImode))
3123 /* The 'restore src1,src2,dest' pattern for DImode. */
3124 else if (GET_CODE (src) == PLUS
3125 && register_operand (XEXP (src, 0), DImode)
3126 && arith_double_operand (XEXP (src, 1), DImode))
3129 /* The 'restore src1,%lo(src2),dest' pattern. */
3130 else if (GET_CODE (src) == LO_SUM
3131 && ! TARGET_CM_MEDMID
3132 && ((register_operand (XEXP (src, 0), SImode)
3133 && immediate_operand (XEXP (src, 1), SImode))
3135 && register_operand (XEXP (src, 0), DImode)
3136 && immediate_operand (XEXP (src, 1), DImode))))
3139 /* The 'restore src,src,dest' pattern. */
3140 else if (GET_CODE (src) == ASHIFT
3141 && (register_operand (XEXP (src, 0), SImode)
3142 || register_operand (XEXP (src, 0), DImode))
3143 && XEXP (src, 1) == const1_rtx)
3149 /* Return nonzero if TRIAL can go into the function return's
3153 eligible_for_return_delay (rtx trial)
3155 int leaf_function_p = current_function_uses_only_leaf_regs;
3158 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3161 if (get_attr_length (trial) != 1)
3164 /* If there are any call-saved registers, we should scan TRIAL if it
3165 does not reference them. For now just make it easy. */
3169 /* If the function uses __builtin_eh_return, the eh_return machinery
3170 occupies the delay slot. */
3171 if (current_function_calls_eh_return)
3174 /* In the case of a true leaf function, anything can go into the slot. */
3175 if (leaf_function_p)
3176 return get_attr_in_uncond_branch_delay (trial)
3177 == IN_UNCOND_BRANCH_DELAY_TRUE;
3179 pat = PATTERN (trial);
3181 /* Otherwise, only operations which can be done in tandem with
3182 a `restore' or `return' insn can go into the delay slot. */
3183 if (GET_CODE (SET_DEST (pat)) != REG
3184 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
3187 /* If this instruction sets up floating point register and we have a return
3188 instruction, it can probably go in. But restore will not work
3190 if (REGNO (SET_DEST (pat)) >= 32)
3192 && ! epilogue_renumber (&pat, 1)
3193 && (get_attr_in_uncond_branch_delay (trial)
3194 == IN_UNCOND_BRANCH_DELAY_TRUE));
3196 return eligible_for_restore_insn (trial, true);
3199 /* Return nonzero if TRIAL can go into the sibling call's
3203 eligible_for_sibcall_delay (rtx trial)
3205 int leaf_function_p = current_function_uses_only_leaf_regs;
3208 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3211 if (get_attr_length (trial) != 1)
3214 pat = PATTERN (trial);
3216 if (leaf_function_p)
3218 /* If the tail call is done using the call instruction,
3219 we have to restore %o7 in the delay slot. */
3220 if (LEAF_SIBCALL_SLOT_RESERVED_P)
3223 /* %g1 is used to build the function address */
3224 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3230 /* Otherwise, only operations which can be done in tandem with
3231 a `restore' insn can go into the delay slot. */
3232 if (GET_CODE (SET_DEST (pat)) != REG
3233 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
3234 || REGNO (SET_DEST (pat)) >= 32)
3237 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3239 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3242 return eligible_for_restore_insn (trial, false);
3246 short_branch (int uid1, int uid2)
3248 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3250 /* Leave a few words of "slop". */
3251 if (delta >= -1023 && delta <= 1022)
3257 /* Return nonzero if REG is not used after INSN.
3258 We assume REG is a reload reg, and therefore does
3259 not live past labels or calls or jumps. */
3261 reg_unused_after (rtx reg, rtx insn)
3263 enum rtx_code code, prev_code = UNKNOWN;
3265 while ((insn = NEXT_INSN (insn)))
3267 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3270 code = GET_CODE (insn);
3271 if (GET_CODE (insn) == CODE_LABEL)
3276 rtx set = single_set (insn);
3277 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3280 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3282 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3290 /* Determine if it's legal to put X into the constant pool. This
3291 is not possible if X contains the address of a symbol that is
3292 not constant (TLS) or not known at final link time (PIC). */
3295 sparc_cannot_force_const_mem (rtx x)
3297 switch (GET_CODE (x))
3301 /* Accept all non-symbolic constants. */
3305 /* Labels are OK iff we are non-PIC. */
3306 return flag_pic != 0;
3309 /* 'Naked' TLS symbol references are never OK,
3310 non-TLS symbols are OK iff we are non-PIC. */
3311 if (SYMBOL_REF_TLS_MODEL (x))
3314 return flag_pic != 0;
3317 return sparc_cannot_force_const_mem (XEXP (x, 0));
3320 return sparc_cannot_force_const_mem (XEXP (x, 0))
3321 || sparc_cannot_force_const_mem (XEXP (x, 1));
3329 /* The table we use to reference PIC data. */
3330 static GTY(()) rtx global_offset_table;
3332 /* The function we use to get at it. */
3333 static GTY(()) rtx add_pc_to_pic_symbol;
3334 static GTY(()) char add_pc_to_pic_symbol_name[256];
3336 /* Ensure that we are not using patterns that are not OK with PIC. */
3344 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3345 || (GET_CODE (recog_data.operand[i]) == CONST
3346 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3347 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3348 == global_offset_table)
3349 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3358 /* Return true if X is an address which needs a temporary register when
3359 reloaded while generating PIC code. */
3362 pic_address_needs_scratch (rtx x)
3364 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3365 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3366 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3367 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3368 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3374 /* Determine if a given RTX is a valid constant. We already know this
3375 satisfies CONSTANT_P. */
3378 legitimate_constant_p (rtx x)
3382 switch (GET_CODE (x))
3385 /* TLS symbols are not constant. */
3386 if (SYMBOL_REF_TLS_MODEL (x))
3391 inner = XEXP (x, 0);
3393 /* Offsets of TLS symbols are never valid.
3394 Discourage CSE from creating them. */
3395 if (GET_CODE (inner) == PLUS
3396 && tls_symbolic_operand (XEXP (inner, 0)))
3401 if (GET_MODE (x) == VOIDmode)
3404 /* Floating point constants are generally not ok.
3405 The only exception is 0.0 in VIS. */
3407 && (GET_MODE (x) == SFmode
3408 || GET_MODE (x) == DFmode
3409 || GET_MODE (x) == TFmode)
3410 && fp_zero_operand (x, GET_MODE (x)))
3422 /* Determine if a given RTX is a valid constant address. */
3425 constant_address_p (rtx x)
3427 switch (GET_CODE (x))
3435 if (flag_pic && pic_address_needs_scratch (x))
3437 return legitimate_constant_p (x);
3440 return !flag_pic && legitimate_constant_p (x);
3447 /* Nonzero if the constant value X is a legitimate general operand
3448 when generating PIC code. It is given that flag_pic is on and
3449 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3452 legitimate_pic_operand_p (rtx x)
3454 if (pic_address_needs_scratch (x))
3456 if (tls_symbolic_operand (x)
3457 || (GET_CODE (x) == CONST
3458 && GET_CODE (XEXP (x, 0)) == PLUS
3459 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3464 /* Return nonzero if ADDR is a valid memory address.
3465 STRICT specifies whether strict register checking applies. */
3468 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3470 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3472 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3474 else if (GET_CODE (addr) == PLUS)
3476 rs1 = XEXP (addr, 0);
3477 rs2 = XEXP (addr, 1);
3479 /* Canonicalize. REG comes first, if there are no regs,
3480 LO_SUM comes first. */
3482 && GET_CODE (rs1) != SUBREG
3484 || GET_CODE (rs2) == SUBREG
3485 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3487 rs1 = XEXP (addr, 1);
3488 rs2 = XEXP (addr, 0);
3492 && rs1 == pic_offset_table_rtx
3494 && GET_CODE (rs2) != SUBREG
3495 && GET_CODE (rs2) != LO_SUM
3496 && GET_CODE (rs2) != MEM
3497 && !tls_symbolic_operand (rs2)
3498 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3499 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3501 || GET_CODE (rs1) == SUBREG)
3502 && RTX_OK_FOR_OFFSET_P (rs2)))
3507 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3508 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3510 /* We prohibit REG + REG for TFmode when there are no instructions
3511 which accept REG+REG instructions. We do this because REG+REG
3512 is not an offsetable address. If we get the situation in reload
3513 where source and destination of a movtf pattern are both MEMs with
3514 REG+REG address, then only one of them gets converted to an
3515 offsetable address. */
3517 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3518 && TARGET_HARD_QUAD))
3521 /* We prohibit REG + REG on ARCH32 if not optimizing for
3522 DFmode/DImode because then mem_min_alignment is likely to be zero
3523 after reload and the forced split would lack a matching splitter
3525 if (TARGET_ARCH32 && !optimize
3526 && (mode == DFmode || mode == DImode))
3529 else if (USE_AS_OFFSETABLE_LO10
3530 && GET_CODE (rs1) == LO_SUM
3532 && ! TARGET_CM_MEDMID
3533 && RTX_OK_FOR_OLO10_P (rs2))
3537 imm1 = XEXP (rs1, 1);
3538 rs1 = XEXP (rs1, 0);
3539 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3543 else if (GET_CODE (addr) == LO_SUM)
3545 rs1 = XEXP (addr, 0);
3546 imm1 = XEXP (addr, 1);
3548 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3551 /* We can't allow TFmode, because an offset greater than or equal to the
3552 alignment (8) may cause the LO_SUM to overflow if !v9. */
3553 if (mode == TFmode && !TARGET_V9)
3556 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3561 if (GET_CODE (rs1) == SUBREG)
3562 rs1 = SUBREG_REG (rs1);
3568 if (GET_CODE (rs2) == SUBREG)
3569 rs2 = SUBREG_REG (rs2);
3576 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3577 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3582 if ((REGNO (rs1) >= 32
3583 && REGNO (rs1) != FRAME_POINTER_REGNUM
3584 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3586 && (REGNO (rs2) >= 32
3587 && REGNO (rs2) != FRAME_POINTER_REGNUM
3588 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3594 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3596 static GTY(()) rtx sparc_tls_symbol;
3598 sparc_tls_get_addr (void)
3600 if (!sparc_tls_symbol)
3601 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3603 return sparc_tls_symbol;
3607 sparc_tls_got (void)
3612 current_function_uses_pic_offset_table = 1;
3613 return pic_offset_table_rtx;
3616 if (!global_offset_table)
3617 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3618 temp = gen_reg_rtx (Pmode);
3619 emit_move_insn (temp, global_offset_table);
3624 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3625 this (thread-local) address. */
3628 legitimize_tls_address (rtx addr)
3630 rtx temp1, temp2, temp3, ret, o0, got, insn;
3635 if (GET_CODE (addr) == SYMBOL_REF)
3636 switch (SYMBOL_REF_TLS_MODEL (addr))
3638 case TLS_MODEL_GLOBAL_DYNAMIC:
3640 temp1 = gen_reg_rtx (SImode);
3641 temp2 = gen_reg_rtx (SImode);
3642 ret = gen_reg_rtx (Pmode);
3643 o0 = gen_rtx_REG (Pmode, 8);
3644 got = sparc_tls_got ();
3645 emit_insn (gen_tgd_hi22 (temp1, addr));
3646 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3649 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3650 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3655 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3656 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3659 CALL_INSN_FUNCTION_USAGE (insn)
3660 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3661 CALL_INSN_FUNCTION_USAGE (insn));
3662 insn = get_insns ();
3664 emit_libcall_block (insn, ret, o0, addr);
3667 case TLS_MODEL_LOCAL_DYNAMIC:
3669 temp1 = gen_reg_rtx (SImode);
3670 temp2 = gen_reg_rtx (SImode);
3671 temp3 = gen_reg_rtx (Pmode);
3672 ret = gen_reg_rtx (Pmode);
3673 o0 = gen_rtx_REG (Pmode, 8);
3674 got = sparc_tls_got ();
3675 emit_insn (gen_tldm_hi22 (temp1));
3676 emit_insn (gen_tldm_lo10 (temp2, temp1));
3679 emit_insn (gen_tldm_add32 (o0, got, temp2));
3680 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3685 emit_insn (gen_tldm_add64 (o0, got, temp2));
3686 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3689 CALL_INSN_FUNCTION_USAGE (insn)
3690 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3691 CALL_INSN_FUNCTION_USAGE (insn));
3692 insn = get_insns ();
3694 emit_libcall_block (insn, temp3, o0,
3695 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3696 UNSPEC_TLSLD_BASE));
3697 temp1 = gen_reg_rtx (SImode);
3698 temp2 = gen_reg_rtx (SImode);
3699 emit_insn (gen_tldo_hix22 (temp1, addr));
3700 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3702 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3704 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3707 case TLS_MODEL_INITIAL_EXEC:
3708 temp1 = gen_reg_rtx (SImode);
3709 temp2 = gen_reg_rtx (SImode);
3710 temp3 = gen_reg_rtx (Pmode);
3711 got = sparc_tls_got ();
3712 emit_insn (gen_tie_hi22 (temp1, addr));
3713 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3715 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3717 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3720 ret = gen_reg_rtx (Pmode);
3722 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3725 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3729 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3732 case TLS_MODEL_LOCAL_EXEC:
3733 temp1 = gen_reg_rtx (Pmode);
3734 temp2 = gen_reg_rtx (Pmode);
3737 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3738 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3742 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3743 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3745 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3753 abort (); /* for now ... */
3759 /* Legitimize PIC addresses. If the address is already position-independent,
3760 we return ORIG. Newly generated position-independent addresses go into a
3761 reg. This is REG if nonzero, otherwise we allocate register(s) as
3765 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3768 if (GET_CODE (orig) == SYMBOL_REF)
3770 rtx pic_ref, address;
3775 if (reload_in_progress || reload_completed)
3778 reg = gen_reg_rtx (Pmode);
3783 /* If not during reload, allocate another temp reg here for loading
3784 in the address, so that these instructions can be optimized
3786 rtx temp_reg = ((reload_in_progress || reload_completed)
3787 ? reg : gen_reg_rtx (Pmode));
3789 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3790 won't get confused into thinking that these two instructions
3791 are loading in the true address of the symbol. If in the
3792 future a PIC rtx exists, that should be used instead. */
3793 if (Pmode == SImode)
3795 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3796 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3800 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3801 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3808 pic_ref = gen_const_mem (Pmode,
3809 gen_rtx_PLUS (Pmode,
3810 pic_offset_table_rtx, address));
3811 current_function_uses_pic_offset_table = 1;
3812 insn = emit_move_insn (reg, pic_ref);
3813 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3815 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3819 else if (GET_CODE (orig) == CONST)
3823 if (GET_CODE (XEXP (orig, 0)) == PLUS
3824 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3829 if (reload_in_progress || reload_completed)
3832 reg = gen_reg_rtx (Pmode);
3835 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3837 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3838 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3839 base == reg ? 0 : reg);
3844 if (GET_CODE (offset) == CONST_INT)
3846 if (SMALL_INT (offset))
3847 return plus_constant (base, INTVAL (offset));
3848 else if (! reload_in_progress && ! reload_completed)
3849 offset = force_reg (Pmode, offset);
3851 /* If we reach here, then something is seriously wrong. */
3854 return gen_rtx_PLUS (Pmode, base, offset);
3856 else if (GET_CODE (orig) == LABEL_REF)
3857 /* ??? Why do we do this? */
3858 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3859 the register is live instead, in case it is eliminated. */
3860 current_function_uses_pic_offset_table = 1;
3865 /* Try machine-dependent ways of modifying an illegitimate address X
3866 to be legitimate. If we find one, return the new, valid address.
3868 OLDX is the address as it was before break_out_memory_refs was called.
3869 In some cases it is useful to look at this to decide what needs to be done.
3871 MODE is the mode of the operand pointed to by X. */
3874 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3878 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3879 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3880 force_operand (XEXP (x, 0), NULL_RTX));
3881 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3882 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3883 force_operand (XEXP (x, 1), NULL_RTX));
3884 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3885 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3887 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3888 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3889 force_operand (XEXP (x, 1), NULL_RTX));
3891 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3894 if (tls_symbolic_operand (x))
3895 x = legitimize_tls_address (x);
3897 x = legitimize_pic_address (x, mode, 0);
3898 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3899 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3900 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3901 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3902 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3903 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3904 else if (GET_CODE (x) == SYMBOL_REF
3905 || GET_CODE (x) == CONST
3906 || GET_CODE (x) == LABEL_REF)
3907 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3911 /* Emit the special PIC prologue. */
3914 load_pic_register (void)
3916 int orig_flag_pic = flag_pic;
3918 /* If we haven't emitted the special helper function, do so now. */
3919 if (add_pc_to_pic_symbol_name[0] == 0)
3921 const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)];
3924 ASM_GENERATE_INTERNAL_LABEL (add_pc_to_pic_symbol_name, "LADDPC", 0);
3927 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3929 ASM_OUTPUT_ALIGN (asm_out_file, align);
3930 ASM_OUTPUT_LABEL (asm_out_file, add_pc_to_pic_symbol_name);
3931 if (flag_delayed_branch)
3932 fprintf (asm_out_file, "\tjmp %%o7+8\n\t add\t%%o7, %s, %s\n",
3933 pic_name, pic_name);
3935 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp %%o7+8\n\t nop\n",
3936 pic_name, pic_name);
3939 /* Initialize every time through, since we can't easily
3940 know this to be permanent. */
3941 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3942 add_pc_to_pic_symbol = gen_rtx_SYMBOL_REF (Pmode, add_pc_to_pic_symbol_name);
3945 emit_insn (gen_load_pcrel_sym (pic_offset_table_rtx, global_offset_table,
3946 add_pc_to_pic_symbol));
3947 flag_pic = orig_flag_pic;
3949 /* Need to emit this whether or not we obey regdecls,
3950 since setjmp/longjmp can cause life info to screw up.
3951 ??? In the case where we don't obey regdecls, this is not sufficient
3952 since we may not fall out the bottom. */
3953 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3956 /* Return 1 if RTX is a MEM which is known to be aligned to at
3957 least a DESIRED byte boundary. */
3960 mem_min_alignment (rtx mem, int desired)
3962 rtx addr, base, offset;
3964 /* If it's not a MEM we can't accept it. */
3965 if (GET_CODE (mem) != MEM)
3968 addr = XEXP (mem, 0);
3969 base = offset = NULL_RTX;
3970 if (GET_CODE (addr) == PLUS)
3972 if (GET_CODE (XEXP (addr, 0)) == REG)
3974 base = XEXP (addr, 0);
3976 /* What we are saying here is that if the base
3977 REG is aligned properly, the compiler will make
3978 sure any REG based index upon it will be so
3980 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3981 offset = XEXP (addr, 1);
3983 offset = const0_rtx;
3986 else if (GET_CODE (addr) == REG)
3989 offset = const0_rtx;
3992 if (base != NULL_RTX)
3994 int regno = REGNO (base);
3996 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3998 /* Check if the compiler has recorded some information
3999 about the alignment of the base REG. If reload has
4000 completed, we already matched with proper alignments.
4001 If not running global_alloc, reload might give us
4002 unaligned pointer to local stack though. */
4004 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
4005 || (optimize && reload_completed))
4006 && (INTVAL (offset) & (desired - 1)) == 0)
4011 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
4015 else if (! TARGET_UNALIGNED_DOUBLES
4016 || CONSTANT_P (addr)
4017 || GET_CODE (addr) == LO_SUM)
4019 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4020 is true, in which case we can only assume that an access is aligned if
4021 it is to a constant address, or the address involves a LO_SUM. */
4025 /* An obviously unaligned address. */
4030 /* Vectors to keep interesting information about registers where it can easily
4031 be got. We used to use the actual mode value as the bit number, but there
4032 are more than 32 modes now. Instead we use two tables: one indexed by
4033 hard register number, and one indexed by mode. */
4035 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4036 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
4037 mapped into one sparc_mode_class mode. */
4039 enum sparc_mode_class {
4040 S_MODE, D_MODE, T_MODE, O_MODE,
4041 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
4045 /* Modes for single-word and smaller quantities. */
4046 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4048 /* Modes for double-word and smaller quantities. */
4049 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4051 /* Modes for quad-word and smaller quantities. */
4052 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4054 /* Modes for 8-word and smaller quantities. */
4055 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4057 /* Modes for single-float quantities. We must allow any single word or
4058 smaller quantity. This is because the fix/float conversion instructions
4059 take integer inputs/outputs from the float registers. */
4060 #define SF_MODES (S_MODES)
4062 /* Modes for double-float and smaller quantities. */
4063 #define DF_MODES (S_MODES | D_MODES)
4065 /* Modes for double-float only quantities. */
4066 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4068 /* Modes for quad-float only quantities. */
4069 #define TF_ONLY_MODES (1 << (int) TF_MODE)
4071 /* Modes for quad-float and smaller quantities. */
4072 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
4074 /* Modes for quad-float and double-float quantities. */
4075 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
4077 /* Modes for quad-float pair only quantities. */
4078 #define OF_ONLY_MODES (1 << (int) OF_MODE)
4080 /* Modes for quad-float pairs and smaller quantities. */
4081 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
4083 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
4085 /* Modes for condition codes. */
4086 #define CC_MODES (1 << (int) CC_MODE)
4087 #define CCFP_MODES (1 << (int) CCFP_MODE)
4089 /* Value is 1 if register/mode pair is acceptable on sparc.
4090 The funny mixture of D and T modes is because integer operations
4091 do not specially operate on tetra quantities, so non-quad-aligned
4092 registers can hold quadword quantities (except %o4 and %i4 because
4093 they cross fixed registers). */
4095 /* This points to either the 32 bit or the 64 bit version. */
4096 const int *hard_regno_mode_classes;
4098 static const int hard_32bit_mode_classes[] = {
4099 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4100 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4101 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4102 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4104 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4105 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4106 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4107 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4109 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4110 and none can hold SFmode/SImode values. */
4111 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4112 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4113 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4114 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4117 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4123 static const int hard_64bit_mode_classes[] = {
4124 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4125 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4126 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4127 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4129 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4130 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4131 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4132 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4134 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4135 and none can hold SFmode/SImode values. */
4136 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4137 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4138 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4139 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4142 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4148 int sparc_mode_class [NUM_MACHINE_MODES];
4150 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4153 sparc_init_modes (void)
4157 for (i = 0; i < NUM_MACHINE_MODES; i++)
4159 switch (GET_MODE_CLASS (i))
4162 case MODE_PARTIAL_INT:
4163 case MODE_COMPLEX_INT:
4164 if (GET_MODE_SIZE (i) <= 4)
4165 sparc_mode_class[i] = 1 << (int) S_MODE;
4166 else if (GET_MODE_SIZE (i) == 8)
4167 sparc_mode_class[i] = 1 << (int) D_MODE;
4168 else if (GET_MODE_SIZE (i) == 16)
4169 sparc_mode_class[i] = 1 << (int) T_MODE;
4170 else if (GET_MODE_SIZE (i) == 32)
4171 sparc_mode_class[i] = 1 << (int) O_MODE;
4173 sparc_mode_class[i] = 0;
4176 case MODE_COMPLEX_FLOAT:
4177 if (GET_MODE_SIZE (i) <= 4)
4178 sparc_mode_class[i] = 1 << (int) SF_MODE;
4179 else if (GET_MODE_SIZE (i) == 8)
4180 sparc_mode_class[i] = 1 << (int) DF_MODE;
4181 else if (GET_MODE_SIZE (i) == 16)
4182 sparc_mode_class[i] = 1 << (int) TF_MODE;
4183 else if (GET_MODE_SIZE (i) == 32)
4184 sparc_mode_class[i] = 1 << (int) OF_MODE;
4186 sparc_mode_class[i] = 0;
4189 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4190 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4192 sparc_mode_class[i] = 1 << (int) CC_MODE;
4195 sparc_mode_class[i] = 0;
4201 hard_regno_mode_classes = hard_64bit_mode_classes;
4203 hard_regno_mode_classes = hard_32bit_mode_classes;
4205 /* Initialize the array used by REGNO_REG_CLASS. */
4206 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4208 if (i < 16 && TARGET_V8PLUS)
4209 sparc_regno_reg_class[i] = I64_REGS;
4210 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4211 sparc_regno_reg_class[i] = GENERAL_REGS;
4213 sparc_regno_reg_class[i] = FP_REGS;
4215 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4217 sparc_regno_reg_class[i] = FPCC_REGS;
4219 sparc_regno_reg_class[i] = NO_REGS;
4223 /* Compute the frame size required by the function. This function is called
4224 during the reload pass and also by sparc_expand_prologue. */
4227 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
4229 int outgoing_args_size = (current_function_outgoing_args_size
4230 + REG_PARM_STACK_SPACE (current_function_decl));
4231 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */
4236 for (i = 0; i < 8; i++)
4237 if (regs_ever_live[i] && ! call_used_regs[i])
4242 for (i = 0; i < 8; i += 2)
4243 if ((regs_ever_live[i] && ! call_used_regs[i])
4244 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4248 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4249 if ((regs_ever_live[i] && ! call_used_regs[i])
4250 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4253 /* Set up values for use in prologue and epilogue. */
4254 num_gfregs = n_regs;
4259 && current_function_outgoing_args_size == 0)
4260 actual_fsize = apparent_fsize = 0;
4263 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4264 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4265 apparent_fsize += n_regs * 4;
4266 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4269 /* Make sure nothing can clobber our register windows.
4270 If a SAVE must be done, or there is a stack-local variable,
4271 the register window area must be allocated.
4272 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4273 if (! leaf_function_p || size > 0)
4274 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4276 return SPARC_STACK_ALIGN (actual_fsize);
4279 /* Output any necessary .register pseudo-ops. */
4282 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4284 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4290 /* Check if %g[2367] were used without
4291 .register being printed for them already. */
4292 for (i = 2; i < 8; i++)
4294 if (regs_ever_live [i]
4295 && ! sparc_hard_reg_printed [i])
4297 sparc_hard_reg_printed [i] = 1;
4298 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4305 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
4306 as needed. LOW should be double-word aligned for 32-bit registers.
4307 Return the new OFFSET. */
4310 #define SORR_RESTORE 1
4313 save_or_restore_regs (int low, int high, rtx base, int offset, int action)
4318 if (TARGET_ARCH64 && high <= 32)
4320 for (i = low; i < high; i++)
4322 if (regs_ever_live[i] && ! call_used_regs[i])
4324 mem = gen_rtx_MEM (DImode, plus_constant (base, offset));
4325 set_mem_alias_set (mem, sparc_sr_alias_set);
4326 if (action == SORR_SAVE)
4328 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4329 RTX_FRAME_RELATED_P (insn) = 1;
4331 else /* action == SORR_RESTORE */
4332 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4339 for (i = low; i < high; i += 2)
4341 bool reg0 = regs_ever_live[i] && ! call_used_regs[i];
4342 bool reg1 = regs_ever_live[i+1] && ! call_used_regs[i+1];
4343 enum machine_mode mode;
4348 mode = i < 32 ? DImode : DFmode;
4353 mode = i < 32 ? SImode : SFmode;
4358 mode = i < 32 ? SImode : SFmode;
4365 mem = gen_rtx_MEM (mode, plus_constant (base, offset));
4366 set_mem_alias_set (mem, sparc_sr_alias_set);
4367 if (action == SORR_SAVE)
4369 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4370 RTX_FRAME_RELATED_P (insn) = 1;
4372 else /* action == SORR_RESTORE */
4373 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4375 /* Always preserve double-word alignment. */
4376 offset = (offset + 7) & -8;
4383 /* Emit code to save call-saved registers. */
4386 emit_save_regs (void)
4388 HOST_WIDE_INT offset;
4391 offset = frame_base_offset - apparent_fsize;
4393 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4395 /* ??? This might be optimized a little as %g1 might already have a
4396 value close enough that a single add insn will do. */
4397 /* ??? Although, all of this is probably only a temporary fix
4398 because if %g1 can hold a function result, then
4399 sparc_expand_epilogue will lose (the result will be
4401 base = gen_rtx_REG (Pmode, 1);
4402 emit_move_insn (base, GEN_INT (offset));
4403 emit_insn (gen_rtx_SET (VOIDmode,
4405 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4409 base = frame_base_reg;
4411 offset = save_or_restore_regs (0, 8, base, offset, SORR_SAVE);
4412 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_SAVE);
4415 /* Emit code to restore call-saved registers. */
4418 emit_restore_regs (void)
4420 HOST_WIDE_INT offset;
4423 offset = frame_base_offset - apparent_fsize;
4425 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4427 base = gen_rtx_REG (Pmode, 1);
4428 emit_move_insn (base, GEN_INT (offset));
4429 emit_insn (gen_rtx_SET (VOIDmode,
4431 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4435 base = frame_base_reg;
4437 offset = save_or_restore_regs (0, 8, base, offset, SORR_RESTORE);
4438 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_RESTORE);
4441 /* Emit an increment for the stack pointer. */
4444 emit_stack_pointer_increment (rtx increment)
4447 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4449 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4452 /* Emit a decrement for the stack pointer. */
4455 emit_stack_pointer_decrement (rtx decrement)
4458 emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4460 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4463 /* Expand the function prologue. The prologue is responsible for reserving
4464 storage for the frame, saving the call-saved registers and loading the
4465 PIC register if needed. */
4468 sparc_expand_prologue (void)
4470 int leaf_function_p = current_function_uses_only_leaf_regs;
4472 /* Need to use actual_fsize, since we are also allocating
4473 space for our callee (and our own register save area). */
4474 actual_fsize = sparc_compute_frame_size (get_frame_size(), leaf_function_p);
4476 if (leaf_function_p)
4478 frame_base_reg = stack_pointer_rtx;
4479 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4483 frame_base_reg = hard_frame_pointer_rtx;
4484 frame_base_offset = SPARC_STACK_BIAS;
4487 if (actual_fsize == 0)
4489 else if (leaf_function_p)
4491 if (actual_fsize <= 4096)
4492 emit_stack_pointer_increment (GEN_INT (- actual_fsize));
4493 else if (actual_fsize <= 8192)
4495 emit_stack_pointer_increment (GEN_INT (-4096));
4496 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4500 rtx reg = gen_rtx_REG (Pmode, 1);
4501 emit_move_insn (reg, GEN_INT (-actual_fsize));
4502 emit_stack_pointer_increment (reg);
4507 if (actual_fsize <= 4096)
4508 emit_insn (gen_save_register_window (GEN_INT (-actual_fsize)));
4509 else if (actual_fsize <= 8192)
4511 emit_insn (gen_save_register_window (GEN_INT (-4096)));
4512 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4516 rtx reg = gen_rtx_REG (Pmode, 1);
4517 emit_move_insn (reg, GEN_INT (-actual_fsize));
4518 emit_insn (gen_save_register_window (reg));
4522 /* Call-saved registers are saved just above the outgoing argument area. */
4526 /* Load the PIC register if needed. */
4527 if (flag_pic && current_function_uses_pic_offset_table)
4528 load_pic_register ();
4531 /* This function generates the assembly code for function entry, which boils
4532 down to emitting the necessary .register directives. It also informs the
4533 DWARF-2 back-end on the layout of the frame.
4535 ??? Historical cruft: "On SPARC, move-double insns between fpu and cpu need
4536 an 8-byte block of memory. If any fpu reg is used in the function, we
4537 allocate such a block here, at the bottom of the frame, just in case it's
4538 needed." Could this explain the -8 in emit_restore_regs? */
4541 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4543 int leaf_function_p = current_function_uses_only_leaf_regs;
4545 sparc_output_scratch_registers (file);
4547 if (dwarf2out_do_frame () && actual_fsize)
4549 char *label = dwarf2out_cfi_label ();
4551 /* The canonical frame address refers to the top of the frame. */
4552 dwarf2out_def_cfa (label,
4554 ? STACK_POINTER_REGNUM
4555 : HARD_FRAME_POINTER_REGNUM,
4558 if (! leaf_function_p)
4560 /* Note the register window save. This tells the unwinder that
4561 it needs to restore the window registers from the previous
4562 frame's window save area at 0(cfa). */
4563 dwarf2out_window_save (label);
4565 /* The return address (-8) is now in %i7. */
4566 dwarf2out_return_reg (label, 31);
4571 /* Expand the function epilogue, either normal or part of a sibcall.
4572 We emit all the instructions except the return or the call. */
4575 sparc_expand_epilogue (void)
4577 int leaf_function_p = current_function_uses_only_leaf_regs;
4580 emit_restore_regs ();
4582 if (actual_fsize == 0)
4584 else if (leaf_function_p)
4586 if (actual_fsize <= 4096)
4587 emit_stack_pointer_decrement (GEN_INT (- actual_fsize));
4588 else if (actual_fsize <= 8192)
4590 emit_stack_pointer_decrement (GEN_INT (-4096));
4591 emit_stack_pointer_decrement (GEN_INT (4096 - actual_fsize));
4595 rtx reg = gen_rtx_REG (Pmode, 1);
4596 emit_move_insn (reg, GEN_INT (-actual_fsize));
4597 emit_stack_pointer_decrement (reg);
4602 /* This function generates the assembly code for function exit. */
4605 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4607 /* If code does not drop into the epilogue, we have to still output
4608 a dummy nop for the sake of sane backtraces. Otherwise, if the
4609 last two instructions of a function were "call foo; dslot;" this
4610 can make the return PC of foo (ie. address of call instruction
4611 plus 8) point to the first instruction in the next function. */
4613 rtx insn, last_real_insn;
4615 insn = get_last_insn ();
4617 last_real_insn = prev_real_insn (insn);
4619 && GET_CODE (last_real_insn) == INSN
4620 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4621 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4623 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4624 fputs("\tnop\n", file);
4626 sparc_output_deferred_case_vectors ();
4629 /* Output a 'restore' instruction. */
4632 output_restore (rtx pat)
4638 fputs ("\t restore\n", asm_out_file);
4642 if (GET_CODE (pat) != SET)
4645 operands[0] = SET_DEST (pat);
4646 pat = SET_SRC (pat);
4648 switch (GET_CODE (pat))
4651 operands[1] = XEXP (pat, 0);
4652 operands[2] = XEXP (pat, 1);
4653 output_asm_insn (" restore %r1, %2, %Y0", operands);
4656 operands[1] = XEXP (pat, 0);
4657 operands[2] = XEXP (pat, 1);
4658 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4661 operands[1] = XEXP (pat, 0);
4662 if (XEXP (pat, 1) != const1_rtx)
4664 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4668 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4673 /* Output a return. */
4676 output_return (rtx insn)
4678 int leaf_function_p = current_function_uses_only_leaf_regs;
4679 bool delay_slot_filled_p = dbr_sequence_length () > 0;
4680 /* True if the caller has placed an "unimp" insn immediately after the call.
4681 This insn is used in the 32-bit ABI when calling a function that returns
4682 a non zero-sized structure. The 64-bit ABI doesn't have it. Be careful
4683 to have this test be the same as that used on the call. */
4684 bool sparc_skip_caller_unimp
4686 && current_function_returns_struct
4687 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
4689 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl)));
4691 if (leaf_function_p)
4693 /* This is a leaf function so we don't have to bother restoring the
4694 register window, which frees us from dealing with the convoluted
4695 semantics of restore/return. We simply output the jump to the
4696 return address and the insn in the delay slot, which usually is
4697 the substraction restoring the stack pointer %sp. */
4699 if (current_function_calls_eh_return)
4702 fprintf (asm_out_file, "\tjmp\t%%o7+%d\n", sparc_skip_caller_unimp ? 12 : 8);
4704 if (delay_slot_filled_p)
4706 rtx delay = NEXT_INSN (insn);
4710 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4711 PATTERN (delay) = gen_blockage ();
4712 INSN_CODE (delay) = -1;
4715 fputs ("\t nop\n", asm_out_file);
4719 /* This is a regular function so we have to restore the register window.
4720 We may have a pending insn for the delay slot, which will be either
4721 combined with the 'restore' instruction or put in the delay slot of
4722 the 'return' instruction. */
4724 if (current_function_calls_eh_return)
4726 /* If the function uses __builtin_eh_return, the eh_return
4727 machinery occupies the delay slot. */
4728 if (delay_slot_filled_p || sparc_skip_caller_unimp)
4731 if (! flag_delayed_branch)
4732 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
4735 fputs ("\treturn\t%i7+8\n", asm_out_file);
4737 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
4739 if (flag_delayed_branch)
4740 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
4742 fputs ("\t nop\n", asm_out_file);
4744 else if (delay_slot_filled_p)
4748 delay = NEXT_INSN (insn);
4752 pat = PATTERN (delay);
4754 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
4756 epilogue_renumber (&pat, 0);
4757 fprintf (asm_out_file, "\treturn\t%%i7+%d\n",
4758 sparc_skip_caller_unimp ? 12 : 8);
4759 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4763 fprintf (asm_out_file, "\tjmp\t%%i7+%d\n",
4764 sparc_skip_caller_unimp ? 12 : 8);
4765 output_restore (pat);
4768 PATTERN (delay) = gen_blockage ();
4769 INSN_CODE (delay) = -1;
4773 /* The delay slot is empty. */
4775 fprintf (asm_out_file, "\treturn\t%%i7+%d\n\t nop\n",
4776 sparc_skip_caller_unimp ? 12 : 8);
4777 else if (flag_delayed_branch)
4778 fprintf (asm_out_file, "\tjmp\t%%i7+%d\n\t restore\n",
4779 sparc_skip_caller_unimp ? 12 : 8);
4781 fprintf (asm_out_file, "\trestore\n\tjmp\t%%o7+%d\n\t nop\n",
4782 sparc_skip_caller_unimp ? 12 : 8);
4789 /* Output a sibling call. */
4792 output_sibcall (rtx insn, rtx call_operand)
4794 int leaf_function_p = current_function_uses_only_leaf_regs;
4795 bool delay_slot_filled_p = dbr_sequence_length () > 0;
4798 if (! flag_delayed_branch)
4801 operands[0] = call_operand;
4803 if (leaf_function_p)
4805 /* This is a leaf function so we don't have to bother restoring the
4806 register window. We simply output the jump to the function and
4807 the insn in the delay slot (if any). */
4809 if (LEAF_SIBCALL_SLOT_RESERVED_P && delay_slot_filled_p)
4812 if (delay_slot_filled_p)
4814 rtx delay = NEXT_INSN (insn);
4818 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4819 output_asm_insn ("jmp\t%%g1 + %%lo(%a0)", operands);
4820 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4822 PATTERN (delay) = gen_blockage ();
4823 INSN_CODE (delay) = -1;
4827 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4828 it into branch if possible. */
4829 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4830 output_asm_insn ("call\t%a0, 0", operands);
4831 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4836 /* This is a regular function so we have to restore the register window.
4837 We may have a pending insn for the delay slot, which will be combined
4838 with the 'restore' instruction. */
4840 output_asm_insn ("call\t%a0, 0", operands);
4842 if (delay_slot_filled_p)
4844 rtx delay = NEXT_INSN (insn);
4848 output_restore (PATTERN (delay));
4850 PATTERN (delay) = gen_blockage ();
4851 INSN_CODE (delay) = -1;
4854 output_restore (NULL_RTX);
4860 /* Functions for handling argument passing.
4862 For 32-bit, the first 6 args are normally in registers and the rest are
4863 pushed. Any arg that starts within the first 6 words is at least
4864 partially passed in a register unless its data type forbids.
4866 For 64-bit, the argument registers are laid out as an array of 16 elements
4867 and arguments are added sequentially. The first 6 int args and up to the
4868 first 16 fp args (depending on size) are passed in regs.
4870 Slot Stack Integral Float Float in structure Double Long Double
4871 ---- ----- -------- ----- ------------------ ------ -----------
4872 15 [SP+248] %f31 %f30,%f31 %d30
4873 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4874 13 [SP+232] %f27 %f26,%f27 %d26
4875 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4876 11 [SP+216] %f23 %f22,%f23 %d22
4877 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4878 9 [SP+200] %f19 %f18,%f19 %d18
4879 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4880 7 [SP+184] %f15 %f14,%f15 %d14
4881 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4882 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4883 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4884 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4885 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4886 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4887 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4889 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4891 Integral arguments are always passed as 64-bit quantities appropriately
4894 Passing of floating point values is handled as follows.
4895 If a prototype is in scope:
4896 If the value is in a named argument (i.e. not a stdarg function or a
4897 value not part of the `...') then the value is passed in the appropriate
4899 If the value is part of the `...' and is passed in one of the first 6
4900 slots then the value is passed in the appropriate int reg.
4901 If the value is part of the `...' and is not passed in one of the first 6
4902 slots then the value is passed in memory.
4903 If a prototype is not in scope:
4904 If the value is one of the first 6 arguments the value is passed in the
4905 appropriate integer reg and the appropriate fp reg.
4906 If the value is not one of the first 6 arguments the value is passed in
4907 the appropriate fp reg and in memory.
4910 Summary of the calling conventions implemented by GCC on SPARC:
4913 size argument return value
4915 small integer <4 int. reg. int. reg.
4916 word 4 int. reg. int. reg.
4917 double word 8 int. reg. int. reg.
4919 _Complex small integer <8 int. reg. int. reg.
4920 _Complex word 8 int. reg. int. reg.
4921 _Complex double word 16 memory int. reg.
4923 vector integer <=8 int. reg. FP reg.
4924 vector integer >8 memory memory
4926 float 4 int. reg. FP reg.
4927 double 8 int. reg. FP reg.
4928 long double 16 memory memory
4930 _Complex float 8 memory FP reg.
4931 _Complex double 16 memory FP reg.
4932 _Complex long double 32 memory FP reg.
4934 vector float <=32 memory FP reg.
4935 vector float >32 memory memory
4937 aggregate any memory memory
4942 size argument return value
4944 small integer <8 int. reg. int. reg.
4945 word 8 int. reg. int. reg.
4946 double word 16 int. reg. int. reg.
4948 _Complex small integer <16 int. reg. int. reg.
4949 _Complex word 16 int. reg. int. reg.
4950 _Complex double word 32 memory int. reg.
4952 vector integer <=16 FP reg. FP reg.
4953 vector integer 16<s<=32 memory FP reg.
4954 vector integer >32 memory memory
4956 float 4 FP reg. FP reg.
4957 double 8 FP reg. FP reg.
4958 long double 16 FP reg. FP reg.
4960 _Complex float 8 FP reg. FP reg.
4961 _Complex double 16 FP reg. FP reg.
4962 _Complex long double 32 memory FP reg.
4964 vector float <=16 FP reg. FP reg.
4965 vector float 16<s<=32 memory FP reg.
4966 vector float >32 memory memory
4968 aggregate <=16 reg. reg.
4969 aggregate 16<s<=32 memory reg.
4970 aggregate >32 memory memory
4974 Note #1: complex floating-point types follow the extended SPARC ABIs as
4975 implemented by the Sun compiler.
4977 Note #2: integral vector types follow the scalar floating-point types
4978 conventions to match what is implemented by the Sun VIS SDK.
4980 Note #3: floating-point vector types follow the complex floating-point
4981 types conventions. */
4984 /* Maximum number of int regs for args. */
4985 #define SPARC_INT_ARG_MAX 6
4986 /* Maximum number of fp regs for args. */
4987 #define SPARC_FP_ARG_MAX 16
4989 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4991 /* Handle the INIT_CUMULATIVE_ARGS macro.
4992 Initialize a variable CUM of type CUMULATIVE_ARGS
4993 for a call to a function whose data type is FNTYPE.
4994 For a library call, FNTYPE is 0. */
4997 init_cumulative_args (struct sparc_args *cum, tree fntype,
4998 rtx libname ATTRIBUTE_UNUSED,
4999 tree fndecl ATTRIBUTE_UNUSED)
5002 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
5003 cum->libcall_p = fntype == 0;
5006 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
5007 When a prototype says `char' or `short', really pass an `int'. */
5010 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
5012 return TARGET_ARCH32 ? true : false;
5015 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5018 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
5020 return TARGET_ARCH64 ? true : false;
5023 /* Scan the record type TYPE and return the following predicates:
5024 - INTREGS_P: the record contains at least one field or sub-field
5025 that is eligible for promotion in integer registers.
5026 - FP_REGS_P: the record contains at least one field or sub-field
5027 that is eligible for promotion in floating-point registers.
5028 - PACKED_P: the record contains at least one field that is packed.
5030 Sub-fields are not taken into account for the PACKED_P predicate. */
5033 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
5037 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5039 if (TREE_CODE (field) == FIELD_DECL)
5041 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5042 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
5043 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU)
5048 if (packed_p && DECL_PACKED (field))
5054 /* Compute the slot number to pass an argument in.
5055 Return the slot number or -1 if passing on the stack.
5057 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5058 the preceding args and about the function being called.
5059 MODE is the argument's machine mode.
5060 TYPE is the data type of the argument (as a tree).
5061 This is null for libcalls where that information may
5063 NAMED is nonzero if this argument is a named parameter
5064 (otherwise it is an extra parameter matching an ellipsis).
5065 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5066 *PREGNO records the register number to use if scalar type.
5067 *PPADDING records the amount of padding needed in words. */
5070 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5071 tree type, int named, int incoming_p,
5072 int *pregno, int *ppadding)
5074 int regbase = (incoming_p
5075 ? SPARC_INCOMING_INT_ARG_FIRST
5076 : SPARC_OUTGOING_INT_ARG_FIRST);
5077 int slotno = cum->words;
5082 if (type && TREE_ADDRESSABLE (type))
5088 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5091 /* For SPARC64, objects requiring 16-byte alignment get it. */
5093 && GET_MODE_ALIGNMENT (mode) >= 2 * BITS_PER_WORD
5094 && (slotno & 1) != 0)
5095 slotno++, *ppadding = 1;
5097 switch (GET_MODE_CLASS (mode))
5100 case MODE_COMPLEX_FLOAT:
5101 case MODE_VECTOR_INT:
5102 case MODE_VECTOR_FLOAT:
5103 if (TARGET_ARCH64 && TARGET_FPU && named)
5105 if (slotno >= SPARC_FP_ARG_MAX)
5107 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5108 /* Arguments filling only one single FP register are
5109 right-justified in the outer double FP register. */
5110 if (GET_MODE_SIZE (mode) <= 4)
5117 case MODE_COMPLEX_INT:
5118 if (slotno >= SPARC_INT_ARG_MAX)
5120 regno = regbase + slotno;
5124 if (mode == VOIDmode)
5125 /* MODE is VOIDmode when generating the actual call. */
5128 if (mode != BLKmode)
5131 /* For SPARC64, objects requiring 16-byte alignment get it. */
5134 && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5135 && (slotno & 1) != 0)
5136 slotno++, *ppadding = 1;
5138 if (TARGET_ARCH32 || (type && TREE_CODE (type) == UNION_TYPE))
5140 if (slotno >= SPARC_INT_ARG_MAX)
5142 regno = regbase + slotno;
5144 else /* TARGET_ARCH64 && type && TREE_CODE (type) == RECORD_TYPE */
5146 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5148 /* First see what kinds of registers we would need. */
5149 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5151 /* The ABI obviously doesn't specify how packed structures
5152 are passed. These are defined to be passed in int regs
5153 if possible, otherwise memory. */
5154 if (packed_p || !named)
5155 fpregs_p = 0, intregs_p = 1;
5157 /* If all arg slots are filled, then must pass on stack. */
5158 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5161 /* If there are only int args and all int arg slots are filled,
5162 then must pass on stack. */
5163 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5166 /* Note that even if all int arg slots are filled, fp members may
5167 still be passed in regs if such regs are available.
5168 *PREGNO isn't set because there may be more than one, it's up
5169 to the caller to compute them. */
5182 /* Handle recursive register counting for structure field layout. */
5184 struct function_arg_record_value_parms
5186 rtx ret; /* return expression being built. */
5187 int slotno; /* slot number of the argument. */
5188 int named; /* whether the argument is named. */
5189 int regbase; /* regno of the base register. */
5190 int stack; /* 1 if part of the argument is on the stack. */
5191 int intoffset; /* offset of the first pending integer field. */
5192 unsigned int nregs; /* number of words passed in registers. */
5195 static void function_arg_record_value_3
5196 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5197 static void function_arg_record_value_2
5198 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5199 static void function_arg_record_value_1
5200 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5201 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5202 static rtx function_arg_union_value (int, enum machine_mode, int);
5204 /* A subroutine of function_arg_record_value. Traverse the structure
5205 recursively and determine how many registers will be required. */
5208 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5209 struct function_arg_record_value_parms *parms,
5214 /* We need to compute how many registers are needed so we can
5215 allocate the PARALLEL but before we can do that we need to know
5216 whether there are any packed fields. The ABI obviously doesn't
5217 specify how structures are passed in this case, so they are
5218 defined to be passed in int regs if possible, otherwise memory,
5219 regardless of whether there are fp values present. */
5222 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5224 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5231 /* Compute how many registers we need. */
5232 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5234 if (TREE_CODE (field) == FIELD_DECL)
5236 HOST_WIDE_INT bitpos = startbitpos;
5238 if (DECL_SIZE (field) != 0
5239 && host_integerp (bit_position (field), 1))
5240 bitpos += int_bit_position (field);
5242 /* ??? FIXME: else assume zero offset. */
5244 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5245 function_arg_record_value_1 (TREE_TYPE (field),
5249 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5250 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5255 if (parms->intoffset != -1)
5257 unsigned int startbit, endbit;
5258 int intslots, this_slotno;
5260 startbit = parms->intoffset & -BITS_PER_WORD;
5261 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5263 intslots = (endbit - startbit) / BITS_PER_WORD;
5264 this_slotno = parms->slotno + parms->intoffset
5267 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5269 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5270 /* We need to pass this field on the stack. */
5274 parms->nregs += intslots;
5275 parms->intoffset = -1;
5278 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5279 If it wasn't true we wouldn't be here. */
5281 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5286 if (parms->intoffset == -1)
5287 parms->intoffset = bitpos;
5293 /* A subroutine of function_arg_record_value. Assign the bits of the
5294 structure between parms->intoffset and bitpos to integer registers. */
5297 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5298 struct function_arg_record_value_parms *parms)
5300 enum machine_mode mode;
5302 unsigned int startbit, endbit;
5303 int this_slotno, intslots, intoffset;
5306 if (parms->intoffset == -1)
5309 intoffset = parms->intoffset;
5310 parms->intoffset = -1;
5312 startbit = intoffset & -BITS_PER_WORD;
5313 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5314 intslots = (endbit - startbit) / BITS_PER_WORD;
5315 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5317 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5321 /* If this is the trailing part of a word, only load that much into
5322 the register. Otherwise load the whole register. Note that in
5323 the latter case we may pick up unwanted bits. It's not a problem
5324 at the moment but may wish to revisit. */
5326 if (intoffset % BITS_PER_WORD != 0)
5327 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5332 intoffset /= BITS_PER_UNIT;
5335 regno = parms->regbase + this_slotno;
5336 reg = gen_rtx_REG (mode, regno);
5337 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5338 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5341 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5346 while (intslots > 0);
5349 /* A subroutine of function_arg_record_value. Traverse the structure
5350 recursively and assign bits to floating point registers. Track which
5351 bits in between need integer registers; invoke function_arg_record_value_3
5352 to make that happen. */
5355 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5356 struct function_arg_record_value_parms *parms,
5362 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5364 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5371 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5373 if (TREE_CODE (field) == FIELD_DECL)
5375 HOST_WIDE_INT bitpos = startbitpos;
5377 if (DECL_SIZE (field) != 0
5378 && host_integerp (bit_position (field), 1))
5379 bitpos += int_bit_position (field);
5381 /* ??? FIXME: else assume zero offset. */
5383 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5384 function_arg_record_value_2 (TREE_TYPE (field),
5388 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5389 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5394 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5396 enum machine_mode mode = DECL_MODE (field);
5399 function_arg_record_value_3 (bitpos, parms);
5402 case SCmode: mode = SFmode; break;
5403 case DCmode: mode = DFmode; break;
5404 case TCmode: mode = TFmode; break;
5407 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5408 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5410 reg = gen_rtx_REG (mode, regno);
5411 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5412 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5413 GEN_INT (bitpos / BITS_PER_UNIT));
5415 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5417 regno += GET_MODE_SIZE (mode) / 4;
5418 reg = gen_rtx_REG (mode, regno);
5419 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5420 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5421 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5428 if (parms->intoffset == -1)
5429 parms->intoffset = bitpos;
5435 /* Used by function_arg and function_value to implement the complex
5436 conventions of the 64-bit ABI for passing and returning structures.
5437 Return an expression valid as a return value for the two macros
5438 FUNCTION_ARG and FUNCTION_VALUE.
5440 TYPE is the data type of the argument (as a tree).
5441 This is null for libcalls where that information may
5443 MODE is the argument's machine mode.
5444 SLOTNO is the index number of the argument's slot in the parameter array.
5445 NAMED is nonzero if this argument is a named parameter
5446 (otherwise it is an extra parameter matching an ellipsis).
5447 REGBASE is the regno of the base register for the parameter array. */
5450 function_arg_record_value (tree type, enum machine_mode mode,
5451 int slotno, int named, int regbase)
5453 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5454 struct function_arg_record_value_parms parms;
5457 parms.ret = NULL_RTX;
5458 parms.slotno = slotno;
5459 parms.named = named;
5460 parms.regbase = regbase;
5463 /* Compute how many registers we need. */
5465 parms.intoffset = 0;
5466 function_arg_record_value_1 (type, 0, &parms, false);
5468 /* Take into account pending integer fields. */
5469 if (parms.intoffset != -1)
5471 unsigned int startbit, endbit;
5472 int intslots, this_slotno;
5474 startbit = parms.intoffset & -BITS_PER_WORD;
5475 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5476 intslots = (endbit - startbit) / BITS_PER_WORD;
5477 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5479 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5481 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5482 /* We need to pass this field on the stack. */
5486 parms.nregs += intslots;
5488 nregs = parms.nregs;
5490 /* Allocate the vector and handle some annoying special cases. */
5493 /* ??? Empty structure has no value? Duh? */
5496 /* Though there's nothing really to store, return a word register
5497 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5498 leads to breakage due to the fact that there are zero bytes to
5500 return gen_rtx_REG (mode, regbase);
5504 /* ??? C++ has structures with no fields, and yet a size. Give up
5505 for now and pass everything back in integer registers. */
5506 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5508 if (nregs + slotno > SPARC_INT_ARG_MAX)
5509 nregs = SPARC_INT_ARG_MAX - slotno;
5514 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5516 /* If at least one field must be passed on the stack, generate
5517 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5518 also be passed on the stack. We can't do much better because the
5519 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5520 of structures for which the fields passed exclusively in registers
5521 are not at the beginning of the structure. */
5523 XVECEXP (parms.ret, 0, 0)
5524 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5526 /* Fill in the entries. */
5528 parms.intoffset = 0;
5529 function_arg_record_value_2 (type, 0, &parms, false);
5530 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5532 if (parms.nregs != nregs)
5538 /* Used by function_arg and function_value to implement the conventions
5539 of the 64-bit ABI for passing and returning unions.
5540 Return an expression valid as a return value for the two macros
5541 FUNCTION_ARG and FUNCTION_VALUE.
5543 SIZE is the size in bytes of the union.
5544 MODE is the argument's machine mode.
5545 REGNO is the hard register the union will be passed in. */
5548 function_arg_union_value (int size, enum machine_mode mode, int regno)
5550 int nwords = ROUND_ADVANCE (size), i;
5553 /* Unions are passed left-justified. */
5554 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5556 for (i = 0; i < nwords; i++)
5557 XVECEXP (regs, 0, i)
5558 = gen_rtx_EXPR_LIST (VOIDmode,
5559 gen_rtx_REG (word_mode, regno + i),
5560 GEN_INT (UNITS_PER_WORD * i));
5565 /* Handle the FUNCTION_ARG macro.
5566 Determine where to put an argument to a function.
5567 Value is zero to push the argument on the stack,
5568 or a hard register in which to store the argument.
5570 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5571 the preceding args and about the function being called.
5572 MODE is the argument's machine mode.
5573 TYPE is the data type of the argument (as a tree).
5574 This is null for libcalls where that information may
5576 NAMED is nonzero if this argument is a named parameter
5577 (otherwise it is an extra parameter matching an ellipsis).
5578 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5581 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5582 tree type, int named, int incoming_p)
5584 int regbase = (incoming_p
5585 ? SPARC_INCOMING_INT_ARG_FIRST
5586 : SPARC_OUTGOING_INT_ARG_FIRST);
5587 int slotno, regno, padding;
5590 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5598 reg = gen_rtx_REG (mode, regno);
5602 if (type && TREE_CODE (type) == RECORD_TYPE)
5604 /* Structures up to 16 bytes in size are passed in arg slots on the
5605 stack and are promoted to registers where possible. */
5607 if (int_size_in_bytes (type) > 16)
5608 abort (); /* shouldn't get here */
5610 return function_arg_record_value (type, mode, slotno, named, regbase);
5612 else if (type && TREE_CODE (type) == UNION_TYPE)
5614 HOST_WIDE_INT size = int_size_in_bytes (type);
5617 abort (); /* shouldn't get here */
5619 return function_arg_union_value (size, mode, regno);
5621 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5622 but also have the slot allocated for them.
5623 If no prototype is in scope fp values in register slots get passed
5624 in two places, either fp regs and int regs or fp regs and memory. */
5625 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5626 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5627 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
5628 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
5629 && SPARC_FP_REG_P (regno))
5631 reg = gen_rtx_REG (mode, regno);
5632 if (cum->prototype_p || cum->libcall_p)
5634 /* "* 2" because fp reg numbers are recorded in 4 byte
5637 /* ??? This will cause the value to be passed in the fp reg and
5638 in the stack. When a prototype exists we want to pass the
5639 value in the reg but reserve space on the stack. That's an
5640 optimization, and is deferred [for a bit]. */
5641 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5642 return gen_rtx_PARALLEL (mode,
5644 gen_rtx_EXPR_LIST (VOIDmode,
5645 NULL_RTX, const0_rtx),
5646 gen_rtx_EXPR_LIST (VOIDmode,
5650 /* ??? It seems that passing back a register even when past
5651 the area declared by REG_PARM_STACK_SPACE will allocate
5652 space appropriately, and will not copy the data onto the
5653 stack, exactly as we desire.
5655 This is due to locate_and_pad_parm being called in
5656 expand_call whenever reg_parm_stack_space > 0, which
5657 while beneficial to our example here, would seem to be
5658 in error from what had been intended. Ho hum... -- r~ */
5666 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5670 /* On incoming, we don't need to know that the value
5671 is passed in %f0 and %i0, and it confuses other parts
5672 causing needless spillage even on the simplest cases. */
5676 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5677 + (regno - SPARC_FP_ARG_FIRST) / 2);
5679 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5680 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5682 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5686 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5687 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5688 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5694 /* Scalar or complex int. */
5695 reg = gen_rtx_REG (mode, regno);
5701 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5702 For an arg passed partly in registers and partly in memory,
5703 this is the number of registers used.
5704 For args passed entirely in registers or entirely in memory, zero.
5706 Any arg that starts in the first 6 regs but won't entirely fit in them
5707 needs partial registers on v8. On v9, structures with integer
5708 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5709 values that begin in the last fp reg [where "last fp reg" varies with the
5710 mode] will be split between that reg and memory. */
5713 function_arg_partial_nregs (const struct sparc_args *cum,
5714 enum machine_mode mode, tree type, int named)
5716 int slotno, regno, padding;
5718 /* We pass 0 for incoming_p here, it doesn't matter. */
5719 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5726 if ((slotno + (mode == BLKmode
5727 ? ROUND_ADVANCE (int_size_in_bytes (type))
5728 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5729 > SPARC_INT_ARG_MAX)
5730 return SPARC_INT_ARG_MAX - slotno;
5734 /* We are guaranteed by pass_by_reference that the size of the
5735 argument is not greater than 16 bytes, so we only need to
5736 return 1 if the argument is partially passed in registers. */
5738 if (type && AGGREGATE_TYPE_P (type))
5740 int size = int_size_in_bytes (type);
5742 if (size > UNITS_PER_WORD
5743 && slotno == SPARC_INT_ARG_MAX - 1)
5746 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5747 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5748 && ! (TARGET_FPU && named)))
5750 /* The complex types are passed as packed types. */
5751 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5752 && slotno == SPARC_INT_ARG_MAX - 1)
5755 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5757 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5766 /* Return true if the argument should be passed by reference.
5767 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5768 quad-precision floats by invisible reference.
5769 v9: Aggregates greater than 16 bytes are passed by reference.
5770 For Pascal, also pass arrays by reference. */
5773 sparc_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5774 enum machine_mode mode, tree type,
5775 bool named ATTRIBUTE_UNUSED)
5779 return ((type && AGGREGATE_TYPE_P (type))
5780 /* Extended ABI (as implemented by the Sun compiler) says
5781 that all complex floats are passed in memory. */
5783 /* Enforce the 2-word cap for passing arguments in registers.
5784 This affects CDImode, TFmode, DCmode, TCmode and large
5786 || GET_MODE_SIZE (mode) > 8);
5790 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5792 && AGGREGATE_TYPE_P (type)
5793 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5794 /* Enforce the 2-word cap for passing arguments in registers.
5795 This affects CTImode, TCmode and large vector modes. */
5796 || GET_MODE_SIZE (mode) > 16);
5800 /* Handle the FUNCTION_ARG_ADVANCE macro.
5801 Update the data in CUM to advance over an argument
5802 of mode MODE and data type TYPE.
5803 TYPE is null for libcalls where that information may not be available. */
5806 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5807 tree type, int named)
5809 int slotno, regno, padding;
5811 /* We pass 0 for incoming_p here, it doesn't matter. */
5812 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5814 /* If register required leading padding, add it. */
5816 cum->words += padding;
5820 cum->words += (mode != BLKmode
5821 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5822 : ROUND_ADVANCE (int_size_in_bytes (type)));
5826 if (type && AGGREGATE_TYPE_P (type))
5828 int size = int_size_in_bytes (type);
5832 else if (size <= 16)
5834 else /* passed by reference */
5839 cum->words += (mode != BLKmode
5840 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5841 : ROUND_ADVANCE (int_size_in_bytes (type)));
5846 /* Handle the FUNCTION_ARG_PADDING macro.
5847 For the 64 bit ABI structs are always stored left shifted in their
5851 function_arg_padding (enum machine_mode mode, tree type)
5853 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5856 /* Fall back to the default. */
5857 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5860 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5861 Specify whether to return the return value in memory. */
5864 sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
5867 /* Original SPARC 32-bit ABI says that quad-precision floats
5868 and all structures are returned in memory. Extended ABI
5869 (as implemented by the Sun compiler) says that all complex
5870 floats are returned in registers (8 FP registers at most
5871 for '_Complex long double'). Return all complex integers
5872 in registers (4 at most for '_Complex long long'). */
5873 return (TYPE_MODE (type) == BLKmode
5874 || TYPE_MODE (type) == TFmode
5875 /* Integral vector types follow the scalar FP types conventions. */
5876 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_INT
5877 && GET_MODE_SIZE (TYPE_MODE (type)) > 8)
5878 /* FP vector types follow the complex FP types conventions. */
5879 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_FLOAT
5880 && GET_MODE_SIZE (TYPE_MODE (type)) > 32));
5882 /* Original SPARC 64-bit ABI says that structures and unions
5883 smaller than 32 bytes are returned in registers. Extended
5884 ABI (as implemented by the Sun compiler) says that all complex
5885 floats are returned in registers (8 FP registers at most
5886 for '_Complex long double'). Return all complex integers
5887 in registers (4 at most for '_Complex TItype'). */
5888 return ((TYPE_MODE (type) == BLKmode
5889 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32)
5890 || GET_MODE_SIZE (TYPE_MODE (type)) > 32);
5893 /* Handle the TARGET_STRUCT_VALUE target hook.
5894 Return where to find the structure return value address. */
5897 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, int incoming)
5904 return gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
5905 STRUCT_VALUE_OFFSET));
5907 return gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
5908 STRUCT_VALUE_OFFSET));
5912 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5913 For v9, function return values are subject to the same rules as arguments,
5914 except that up to 32 bytes may be returned in registers. */
5917 function_value (tree type, enum machine_mode mode, int incoming_p)
5919 /* Beware that the two values are swapped here wrt function_arg. */
5920 int regbase = (incoming_p
5921 ? SPARC_OUTGOING_INT_ARG_FIRST
5922 : SPARC_INCOMING_INT_ARG_FIRST);
5925 if (TARGET_ARCH64 && type)
5927 if (TREE_CODE (type) == RECORD_TYPE)
5929 /* Structures up to 32 bytes in size are passed in registers,
5930 promoted to fp registers where possible. */
5932 if (int_size_in_bytes (type) > 32)
5933 abort (); /* shouldn't get here */
5935 return function_arg_record_value (type, mode, 0, 1, regbase);
5937 else if (TREE_CODE (type) == UNION_TYPE)
5939 HOST_WIDE_INT size = int_size_in_bytes (type);
5942 abort (); /* shouldn't get here */
5944 return function_arg_union_value (size, mode, regbase);
5946 else if (AGGREGATE_TYPE_P (type))
5948 /* All other aggregate types are passed in an integer register
5949 in a mode corresponding to the size of the type. */
5950 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5953 abort (); /* shouldn't get here */
5955 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5957 /* ??? We probably should have made the same ABI change in
5958 3.4.0 as the one we made for unions. The latter was
5959 required by the SCD though, while the former is not
5960 specified, so we favored compatibility and efficiency.
5962 Now we're stuck for aggregates larger than 16 bytes,
5963 because OImode vanished in the meantime. Let's not
5964 try to be unduly clever, and simply follow the ABI
5965 for unions in that case. */
5966 if (mode == BLKmode)
5967 return function_arg_union_value (bytes, mode, regbase);
5969 else if (GET_MODE_CLASS (mode) == MODE_INT
5970 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5974 if (TARGET_FPU && (FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)))
5975 regno = SPARC_FP_ARG_FIRST;
5979 return gen_rtx_REG (mode, regno);
5982 /* Do what is necessary for `va_start'. We look at the current function
5983 to determine if stdarg or varargs is used and return the address of
5984 the first unnamed parameter. */
5987 sparc_builtin_saveregs (void)
5989 int first_reg = current_function_args_info.words;
5993 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
5994 emit_move_insn (gen_rtx_MEM (word_mode,
5995 gen_rtx_PLUS (Pmode,
5997 GEN_INT (FIRST_PARM_OFFSET (0)
6000 gen_rtx_REG (word_mode,
6001 SPARC_INCOMING_INT_ARG_FIRST + regno));
6003 address = gen_rtx_PLUS (Pmode,
6005 GEN_INT (FIRST_PARM_OFFSET (0)
6006 + UNITS_PER_WORD * first_reg));
6011 /* Implement `va_start' for stdarg. */
6014 sparc_va_start (tree valist, rtx nextarg)
6016 nextarg = expand_builtin_saveregs ();
6017 std_expand_builtin_va_start (valist, nextarg);
6020 /* Implement `va_arg' for stdarg. */
6023 sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6025 HOST_WIDE_INT size, rsize, align;
6028 tree ptrtype = build_pointer_type (type);
6030 if (pass_by_reference (NULL, TYPE_MODE (type), type, 0))
6033 size = rsize = UNITS_PER_WORD;
6039 size = int_size_in_bytes (type);
6040 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6045 /* For SPARC64, objects requiring 16-byte alignment get it. */
6046 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6047 align = 2 * UNITS_PER_WORD;
6049 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6050 are given whole slots as needed. */
6051 if (AGGREGATE_TYPE_P (type))
6054 size = rsize = UNITS_PER_WORD;
6064 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6065 ssize_int (align - 1)));
6066 incr = fold (build2 (BIT_AND_EXPR, ptr_type_node, incr,
6067 ssize_int (-align)));
6070 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6073 if (BYTES_BIG_ENDIAN && size < rsize)
6074 addr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6075 ssize_int (rsize - size)));
6079 addr = fold_convert (build_pointer_type (ptrtype), addr);
6080 addr = build_fold_indirect_ref (addr);
6082 /* If the address isn't aligned properly for the type,
6083 we may need to copy to a temporary.
6084 FIXME: This is inefficient. Usually we can do this
6087 && TYPE_ALIGN (type) > BITS_PER_WORD)
6089 tree tmp = create_tmp_var (type, "va_arg_tmp");
6090 tree dest_addr = build_fold_addr_expr (tmp);
6092 tree copy = build_function_call_expr
6093 (implicit_built_in_decls[BUILT_IN_MEMCPY],
6094 tree_cons (NULL_TREE, dest_addr,
6095 tree_cons (NULL_TREE, addr,
6096 tree_cons (NULL_TREE, size_int (rsize),
6099 gimplify_and_add (copy, pre_p);
6103 addr = fold_convert (ptrtype, addr);
6105 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, ssize_int (rsize)));
6106 incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr);
6107 gimplify_and_add (incr, post_p);
6109 return build_fold_indirect_ref (addr);
6112 /* Return the string to output an unconditional branch to LABEL, which is
6113 the operand number of the label.
6115 DEST is the destination insn (i.e. the label), INSN is the source. */
6118 output_ubranch (rtx dest, int label, rtx insn)
6120 static char string[64];
6124 /* TurboSPARC is reported to have problems with
6127 i.e. an empty loop with the annul bit set. The workaround is to use
6131 if (! TARGET_V9 && flag_delayed_branch
6132 && (INSN_ADDRESSES (INSN_UID (dest))
6133 == INSN_ADDRESSES (INSN_UID (insn))))
6135 strcpy (string, "b\t");
6140 bool v9_form = false;
6142 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
6144 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6145 - INSN_ADDRESSES (INSN_UID (insn)));
6146 /* Leave some instructions for "slop". */
6147 if (delta >= -260000 && delta < 260000)
6152 strcpy (string, "ba%*,pt\t%%xcc, ");
6154 strcpy (string, "b%*\t");
6157 p = strchr (string, '\0');
6171 /* Return the string to output a conditional branch to LABEL, which is
6172 the operand number of the label. OP is the conditional expression.
6173 XEXP (OP, 0) is assumed to be a condition code register (integer or
6174 floating point) and its mode specifies what kind of comparison we made.
6176 DEST is the destination insn (i.e. the label), INSN is the source.
6178 REVERSED is nonzero if we should reverse the sense of the comparison.
6180 ANNUL is nonzero if we should generate an annulling branch.
6182 NOOP is nonzero if we have to follow this branch by a noop. */
6185 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6188 static char string[64];
6189 enum rtx_code code = GET_CODE (op);
6190 rtx cc_reg = XEXP (op, 0);
6191 enum machine_mode mode = GET_MODE (cc_reg);
6192 const char *labelno, *branch;
6193 int spaces = 8, far;
6196 /* v9 branches are limited to +-1MB. If it is too far away,
6209 fbne,a,pn %fcc2, .LC29
6217 far = TARGET_V9 && (get_attr_length (insn) >= 3);
6220 /* Reversal of FP compares takes care -- an ordered compare
6221 becomes an unordered compare and vice versa. */
6222 if (mode == CCFPmode || mode == CCFPEmode)
6223 code = reverse_condition_maybe_unordered (code);
6225 code = reverse_condition (code);
6228 /* Start by writing the branch condition. */
6229 if (mode == CCFPmode || mode == CCFPEmode)
6280 /* ??? !v9: FP branches cannot be preceded by another floating point
6281 insn. Because there is currently no concept of pre-delay slots,
6282 we can fix this only by always emitting a nop before a floating
6287 strcpy (string, "nop\n\t");
6288 strcat (string, branch);
6301 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6313 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6334 strcpy (string, branch);
6336 spaces -= strlen (branch);
6337 p = strchr (string, '\0');
6339 /* Now add the annulling, the label, and a possible noop. */
6352 if (! far && insn && INSN_ADDRESSES_SET_P ())
6354 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6355 - INSN_ADDRESSES (INSN_UID (insn)));
6356 /* Leave some instructions for "slop". */
6357 if (delta < -260000 || delta >= 260000)
6361 if (mode == CCFPmode || mode == CCFPEmode)
6363 static char v9_fcc_labelno[] = "%%fccX, ";
6364 /* Set the char indicating the number of the fcc reg to use. */
6365 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6366 labelno = v9_fcc_labelno;
6369 if (REGNO (cc_reg) == SPARC_FCC_REG)
6375 else if (mode == CCXmode || mode == CCX_NOOVmode)
6377 labelno = "%%xcc, ";
6383 labelno = "%%icc, ";
6388 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6391 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6404 strcpy (p, labelno);
6405 p = strchr (p, '\0');
6408 strcpy (p, ".+12\n\t nop\n\tb\t");
6415 /* Set the char indicating the number of the operand containing the
6420 strcpy (p, "\n\t nop");
6425 /* Emit a library call comparison between floating point X and Y.
6426 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6427 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6428 values as arguments instead of the TFmode registers themselves,
6429 that's why we cannot call emit_float_lib_cmp. */
6431 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6434 rtx slot0, slot1, result, tem, tem2;
6435 enum machine_mode mode;
6440 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6444 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6448 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6452 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6456 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6460 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6471 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6481 if (GET_CODE (x) != MEM)
6483 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6484 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6489 if (GET_CODE (y) != MEM)
6491 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6492 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6497 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6499 XEXP (slot0, 0), Pmode,
6500 XEXP (slot1, 0), Pmode);
6506 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6508 x, TFmode, y, TFmode);
6514 /* Immediately move the result of the libcall into a pseudo
6515 register so reload doesn't clobber the value if it needs
6516 the return register for a spill reg. */
6517 result = gen_reg_rtx (mode);
6518 emit_move_insn (result, hard_libcall_value (mode));
6523 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6527 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6532 emit_cmp_insn (result, const1_rtx,
6533 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6536 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6539 tem = gen_reg_rtx (mode);
6541 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6543 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6544 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6548 tem = gen_reg_rtx (mode);
6550 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6552 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6553 tem2 = gen_reg_rtx (mode);
6555 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6557 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6558 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6564 /* Generate an unsigned DImode to FP conversion. This is the same code
6565 optabs would emit if we didn't have TFmode patterns. */
6568 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
6570 rtx neglab, donelab, i0, i1, f0, in, out;
6573 in = force_reg (DImode, operands[1]);
6574 neglab = gen_label_rtx ();
6575 donelab = gen_label_rtx ();
6576 i0 = gen_reg_rtx (DImode);
6577 i1 = gen_reg_rtx (DImode);
6578 f0 = gen_reg_rtx (mode);
6580 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6582 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6583 emit_jump_insn (gen_jump (donelab));
6586 emit_label (neglab);
6588 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6589 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6590 emit_insn (gen_iordi3 (i0, i0, i1));
6591 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6592 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6594 emit_label (donelab);
6597 /* Generate an FP to unsigned DImode conversion. This is the same code
6598 optabs would emit if we didn't have TFmode patterns. */
6601 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6603 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6606 in = force_reg (mode, operands[1]);
6607 neglab = gen_label_rtx ();
6608 donelab = gen_label_rtx ();
6609 i0 = gen_reg_rtx (DImode);
6610 i1 = gen_reg_rtx (DImode);
6611 limit = gen_reg_rtx (mode);
6612 f0 = gen_reg_rtx (mode);
6614 emit_move_insn (limit,
6615 CONST_DOUBLE_FROM_REAL_VALUE (
6616 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6617 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6619 emit_insn (gen_rtx_SET (VOIDmode,
6621 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6622 emit_jump_insn (gen_jump (donelab));
6625 emit_label (neglab);
6627 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6628 emit_insn (gen_rtx_SET (VOIDmode,
6630 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6631 emit_insn (gen_movdi (i1, const1_rtx));
6632 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6633 emit_insn (gen_xordi3 (out, i0, i1));
6635 emit_label (donelab);
6638 /* Return the string to output a conditional branch to LABEL, testing
6639 register REG. LABEL is the operand number of the label; REG is the
6640 operand number of the reg. OP is the conditional expression. The mode
6641 of REG says what kind of comparison we made.
6643 DEST is the destination insn (i.e. the label), INSN is the source.
6645 REVERSED is nonzero if we should reverse the sense of the comparison.
6647 ANNUL is nonzero if we should generate an annulling branch.
6649 NOOP is nonzero if we have to follow this branch by a noop. */
6652 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6653 int annul, int noop, rtx insn)
6655 static char string[64];
6656 enum rtx_code code = GET_CODE (op);
6657 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6662 /* branch on register are limited to +-128KB. If it is too far away,
6675 brgez,a,pn %o1, .LC29
6681 ba,pt %xcc, .LC29 */
6683 far = get_attr_length (insn) >= 3;
6685 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6687 code = reverse_condition (code);
6689 /* Only 64 bit versions of these instructions exist. */
6693 /* Start by writing the branch condition. */
6698 strcpy (string, "brnz");
6702 strcpy (string, "brz");
6706 strcpy (string, "brgez");
6710 strcpy (string, "brlz");
6714 strcpy (string, "brlez");
6718 strcpy (string, "brgz");
6725 p = strchr (string, '\0');
6727 /* Now add the annulling, reg, label, and nop. */
6734 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6737 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6742 *p = p < string + 8 ? '\t' : ' ';
6750 int veryfar = 1, delta;
6752 if (INSN_ADDRESSES_SET_P ())
6754 delta = (INSN_ADDRESSES (INSN_UID (dest))
6755 - INSN_ADDRESSES (INSN_UID (insn)));
6756 /* Leave some instructions for "slop". */
6757 if (delta >= -260000 && delta < 260000)
6761 strcpy (p, ".+12\n\t nop\n\t");
6772 strcpy (p, "ba,pt\t%%xcc, ");
6782 strcpy (p, "\n\t nop");
6787 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6788 Such instructions cannot be used in the delay slot of return insn on v9.
6789 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6793 epilogue_renumber (register rtx *where, int test)
6795 register const char *fmt;
6797 register enum rtx_code code;
6802 code = GET_CODE (*where);
6807 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6809 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6810 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6818 /* Do not replace the frame pointer with the stack pointer because
6819 it can cause the delayed instruction to load below the stack.
6820 This occurs when instructions like:
6822 (set (reg/i:SI 24 %i0)
6823 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6824 (const_int -20 [0xffffffec])) 0))
6826 are in the return delayed slot. */
6828 if (GET_CODE (XEXP (*where, 0)) == REG
6829 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6830 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6831 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6836 if (SPARC_STACK_BIAS
6837 && GET_CODE (XEXP (*where, 0)) == REG
6838 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6846 fmt = GET_RTX_FORMAT (code);
6848 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6853 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6854 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6857 else if (fmt[i] == 'e'
6858 && epilogue_renumber (&(XEXP (*where, i)), test))
6864 /* Leaf functions and non-leaf functions have different needs. */
6867 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6870 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6872 static const int *const reg_alloc_orders[] = {
6873 reg_leaf_alloc_order,
6874 reg_nonleaf_alloc_order};
6877 order_regs_for_local_alloc (void)
6879 static int last_order_nonleaf = 1;
6881 if (regs_ever_live[15] != last_order_nonleaf)
6883 last_order_nonleaf = !last_order_nonleaf;
6884 memcpy ((char *) reg_alloc_order,
6885 (const char *) reg_alloc_orders[last_order_nonleaf],
6886 FIRST_PSEUDO_REGISTER * sizeof (int));
6890 /* Return 1 if REG and MEM are legitimate enough to allow the various
6891 mem<-->reg splits to be run. */
6894 sparc_splitdi_legitimate (rtx reg, rtx mem)
6896 /* Punt if we are here by mistake. */
6897 if (! reload_completed)
6900 /* We must have an offsettable memory reference. */
6901 if (! offsettable_memref_p (mem))
6904 /* If we have legitimate args for ldd/std, we do not want
6905 the split to happen. */
6906 if ((REGNO (reg) % 2) == 0
6907 && mem_min_alignment (mem, 8))
6914 /* Return 1 if x and y are some kind of REG and they refer to
6915 different hard registers. This test is guaranteed to be
6916 run after reload. */
6919 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6921 if (GET_CODE (x) != REG)
6923 if (GET_CODE (y) != REG)
6925 if (REGNO (x) == REGNO (y))
6930 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6931 This makes them candidates for using ldd and std insns.
6933 Note reg1 and reg2 *must* be hard registers. */
6936 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6938 /* We might have been passed a SUBREG. */
6939 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6942 if (REGNO (reg1) % 2 != 0)
6945 /* Integer ldd is deprecated in SPARC V9 */
6946 if (TARGET_V9 && REGNO (reg1) < 32)
6949 return (REGNO (reg1) == REGNO (reg2) - 1);
6952 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6955 This can only happen when addr1 and addr2, the addresses in mem1
6956 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6957 addr1 must also be aligned on a 64-bit boundary.
6959 Also iff dependent_reg_rtx is not null it should not be used to
6960 compute the address for mem1, i.e. we cannot optimize a sequence
6972 But, note that the transformation from:
6977 is perfectly fine. Thus, the peephole2 patterns always pass us
6978 the destination register of the first load, never the second one.
6980 For stores we don't have a similar problem, so dependent_reg_rtx is
6984 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6988 HOST_WIDE_INT offset1;
6990 /* The mems cannot be volatile. */
6991 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6994 /* MEM1 should be aligned on a 64-bit boundary. */
6995 if (MEM_ALIGN (mem1) < 64)
6998 addr1 = XEXP (mem1, 0);
6999 addr2 = XEXP (mem2, 0);
7001 /* Extract a register number and offset (if used) from the first addr. */
7002 if (GET_CODE (addr1) == PLUS)
7004 /* If not a REG, return zero. */
7005 if (GET_CODE (XEXP (addr1, 0)) != REG)
7009 reg1 = REGNO (XEXP (addr1, 0));
7010 /* The offset must be constant! */
7011 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
7013 offset1 = INTVAL (XEXP (addr1, 1));
7016 else if (GET_CODE (addr1) != REG)
7020 reg1 = REGNO (addr1);
7021 /* This was a simple (mem (reg)) expression. Offset is 0. */
7025 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7026 if (GET_CODE (addr2) != PLUS)
7029 if (GET_CODE (XEXP (addr2, 0)) != REG
7030 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
7033 if (reg1 != REGNO (XEXP (addr2, 0)))
7036 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
7039 /* The first offset must be evenly divisible by 8 to ensure the
7040 address is 64 bit aligned. */
7041 if (offset1 % 8 != 0)
7044 /* The offset for the second addr must be 4 more than the first addr. */
7045 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
7048 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7053 /* Return 1 if reg is a pseudo, or is the first register in
7054 a hard register pair. This makes it a candidate for use in
7055 ldd and std insns. */
7058 register_ok_for_ldd (rtx reg)
7060 /* We might have been passed a SUBREG. */
7061 if (GET_CODE (reg) != REG)
7064 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
7065 return (REGNO (reg) % 2 == 0);
7070 /* Print operand X (an rtx) in assembler syntax to file FILE.
7071 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7072 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7075 print_operand (FILE *file, rtx x, int code)
7080 /* Output a 'nop' if there's nothing for the delay slot. */
7081 if (dbr_sequence_length () == 0)
7082 fputs ("\n\t nop", file);
7085 /* Output an annul flag if there's nothing for the delay slot and we
7086 are optimizing. This is always used with '(' below. */
7087 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7088 this is a dbx bug. So, we only do this when optimizing. */
7089 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7090 Always emit a nop in case the next instruction is a branch. */
7091 if (dbr_sequence_length () == 0
7092 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
7096 /* Output a 'nop' if there's nothing for the delay slot and we are
7097 not optimizing. This is always used with '*' above. */
7098 if (dbr_sequence_length () == 0
7099 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
7100 fputs ("\n\t nop", file);
7103 /* Output the Embedded Medium/Anywhere code model base register. */
7104 fputs (EMBMEDANY_BASE_REG, file);
7107 /* Print out what we are using as the frame pointer. This might
7108 be %fp, or might be %sp+offset. */
7109 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
7110 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC,
7111 reg_names[REGNO (frame_base_reg)], frame_base_offset);
7114 /* Print some local dynamic TLS name. */
7115 assemble_name (file, get_some_local_dynamic_name ());
7118 /* Adjust the operand to take into account a RESTORE operation. */
7119 if (GET_CODE (x) == CONST_INT)
7121 else if (GET_CODE (x) != REG)
7122 output_operand_lossage ("invalid %%Y operand");
7123 else if (REGNO (x) < 8)
7124 fputs (reg_names[REGNO (x)], file);
7125 else if (REGNO (x) >= 24 && REGNO (x) < 32)
7126 fputs (reg_names[REGNO (x)-16], file);
7128 output_operand_lossage ("invalid %%Y operand");
7131 /* Print out the low order register name of a register pair. */
7132 if (WORDS_BIG_ENDIAN)
7133 fputs (reg_names[REGNO (x)+1], file);
7135 fputs (reg_names[REGNO (x)], file);
7138 /* Print out the high order register name of a register pair. */
7139 if (WORDS_BIG_ENDIAN)
7140 fputs (reg_names[REGNO (x)], file);
7142 fputs (reg_names[REGNO (x)+1], file);
7145 /* Print out the second register name of a register pair or quad.
7146 I.e., R (%o0) => %o1. */
7147 fputs (reg_names[REGNO (x)+1], file);
7150 /* Print out the third register name of a register quad.
7151 I.e., S (%o0) => %o2. */
7152 fputs (reg_names[REGNO (x)+2], file);
7155 /* Print out the fourth register name of a register quad.
7156 I.e., T (%o0) => %o3. */
7157 fputs (reg_names[REGNO (x)+3], file);
7160 /* Print a condition code register. */
7161 if (REGNO (x) == SPARC_ICC_REG)
7163 /* We don't handle CC[X]_NOOVmode because they're not supposed
7165 if (GET_MODE (x) == CCmode)
7166 fputs ("%icc", file);
7167 else if (GET_MODE (x) == CCXmode)
7168 fputs ("%xcc", file);
7173 /* %fccN register */
7174 fputs (reg_names[REGNO (x)], file);
7177 /* Print the operand's address only. */
7178 output_address (XEXP (x, 0));
7181 /* In this case we need a register. Use %g0 if the
7182 operand is const0_rtx. */
7184 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7186 fputs ("%g0", file);
7193 switch (GET_CODE (x))
7195 case IOR: fputs ("or", file); break;
7196 case AND: fputs ("and", file); break;
7197 case XOR: fputs ("xor", file); break;
7198 default: output_operand_lossage ("invalid %%A operand");
7203 switch (GET_CODE (x))
7205 case IOR: fputs ("orn", file); break;
7206 case AND: fputs ("andn", file); break;
7207 case XOR: fputs ("xnor", file); break;
7208 default: output_operand_lossage ("invalid %%B operand");
7212 /* These are used by the conditional move instructions. */
7216 enum rtx_code rc = GET_CODE (x);
7220 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7221 if (mode == CCFPmode || mode == CCFPEmode)
7222 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7224 rc = reverse_condition (GET_CODE (x));
7228 case NE: fputs ("ne", file); break;
7229 case EQ: fputs ("e", file); break;
7230 case GE: fputs ("ge", file); break;
7231 case GT: fputs ("g", file); break;
7232 case LE: fputs ("le", file); break;
7233 case LT: fputs ("l", file); break;
7234 case GEU: fputs ("geu", file); break;
7235 case GTU: fputs ("gu", file); break;
7236 case LEU: fputs ("leu", file); break;
7237 case LTU: fputs ("lu", file); break;
7238 case LTGT: fputs ("lg", file); break;
7239 case UNORDERED: fputs ("u", file); break;
7240 case ORDERED: fputs ("o", file); break;
7241 case UNLT: fputs ("ul", file); break;
7242 case UNLE: fputs ("ule", file); break;
7243 case UNGT: fputs ("ug", file); break;
7244 case UNGE: fputs ("uge", file); break;
7245 case UNEQ: fputs ("ue", file); break;
7246 default: output_operand_lossage (code == 'c'
7247 ? "invalid %%c operand"
7248 : "invalid %%C operand");
7253 /* These are used by the movr instruction pattern. */
7257 enum rtx_code rc = (code == 'd'
7258 ? reverse_condition (GET_CODE (x))
7262 case NE: fputs ("ne", file); break;
7263 case EQ: fputs ("e", file); break;
7264 case GE: fputs ("gez", file); break;
7265 case LT: fputs ("lz", file); break;
7266 case LE: fputs ("lez", file); break;
7267 case GT: fputs ("gz", file); break;
7268 default: output_operand_lossage (code == 'd'
7269 ? "invalid %%d operand"
7270 : "invalid %%D operand");
7277 /* Print a sign-extended character. */
7278 int i = trunc_int_for_mode (INTVAL (x), QImode);
7279 fprintf (file, "%d", i);
7284 /* Operand must be a MEM; write its address. */
7285 if (GET_CODE (x) != MEM)
7286 output_operand_lossage ("invalid %%f operand");
7287 output_address (XEXP (x, 0));
7292 /* Print a sign-extended 32-bit value. */
7294 if (GET_CODE(x) == CONST_INT)
7296 else if (GET_CODE(x) == CONST_DOUBLE)
7297 i = CONST_DOUBLE_LOW (x);
7300 output_operand_lossage ("invalid %%s operand");
7303 i = trunc_int_for_mode (i, SImode);
7304 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7309 /* Do nothing special. */
7313 /* Undocumented flag. */
7314 output_operand_lossage ("invalid operand output code");
7317 if (GET_CODE (x) == REG)
7318 fputs (reg_names[REGNO (x)], file);
7319 else if (GET_CODE (x) == MEM)
7322 /* Poor Sun assembler doesn't understand absolute addressing. */
7323 if (CONSTANT_P (XEXP (x, 0)))
7324 fputs ("%g0+", file);
7325 output_address (XEXP (x, 0));
7328 else if (GET_CODE (x) == HIGH)
7330 fputs ("%hi(", file);
7331 output_addr_const (file, XEXP (x, 0));
7334 else if (GET_CODE (x) == LO_SUM)
7336 print_operand (file, XEXP (x, 0), 0);
7337 if (TARGET_CM_MEDMID)
7338 fputs ("+%l44(", file);
7340 fputs ("+%lo(", file);
7341 output_addr_const (file, XEXP (x, 1));
7344 else if (GET_CODE (x) == CONST_DOUBLE
7345 && (GET_MODE (x) == VOIDmode
7346 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7348 if (CONST_DOUBLE_HIGH (x) == 0)
7349 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7350 else if (CONST_DOUBLE_HIGH (x) == -1
7351 && CONST_DOUBLE_LOW (x) < 0)
7352 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7354 output_operand_lossage ("long long constant not a valid immediate operand");
7356 else if (GET_CODE (x) == CONST_DOUBLE)
7357 output_operand_lossage ("floating point constant not a valid immediate operand");
7358 else { output_addr_const (file, x); }
7361 /* Target hook for assembling integer objects. The sparc version has
7362 special handling for aligned DI-mode objects. */
7365 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7367 /* ??? We only output .xword's for symbols and only then in environments
7368 where the assembler can handle them. */
7369 if (aligned_p && size == 8
7370 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7374 assemble_integer_with_op ("\t.xword\t", x);
7379 assemble_aligned_integer (4, const0_rtx);
7380 assemble_aligned_integer (4, x);
7384 return default_assemble_integer (x, size, aligned_p);
7387 /* Return the value of a code used in the .proc pseudo-op that says
7388 what kind of result this function returns. For non-C types, we pick
7389 the closest C type. */
7391 #ifndef SHORT_TYPE_SIZE
7392 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7395 #ifndef INT_TYPE_SIZE
7396 #define INT_TYPE_SIZE BITS_PER_WORD
7399 #ifndef LONG_TYPE_SIZE
7400 #define LONG_TYPE_SIZE BITS_PER_WORD
7403 #ifndef LONG_LONG_TYPE_SIZE
7404 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7407 #ifndef FLOAT_TYPE_SIZE
7408 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7411 #ifndef DOUBLE_TYPE_SIZE
7412 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7415 #ifndef LONG_DOUBLE_TYPE_SIZE
7416 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7420 sparc_type_code (register tree type)
7422 register unsigned long qualifiers = 0;
7423 register unsigned shift;
7425 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7426 setting more, since some assemblers will give an error for this. Also,
7427 we must be careful to avoid shifts of 32 bits or more to avoid getting
7428 unpredictable results. */
7430 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7432 switch (TREE_CODE (type))
7438 qualifiers |= (3 << shift);
7443 qualifiers |= (2 << shift);
7447 case REFERENCE_TYPE:
7449 qualifiers |= (1 << shift);
7453 return (qualifiers | 8);
7456 case QUAL_UNION_TYPE:
7457 return (qualifiers | 9);
7460 return (qualifiers | 10);
7463 return (qualifiers | 16);
7466 /* If this is a range type, consider it to be the underlying
7468 if (TREE_TYPE (type) != 0)
7471 /* Carefully distinguish all the standard types of C,
7472 without messing up if the language is not C. We do this by
7473 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
7474 look at both the names and the above fields, but that's redundant.
7475 Any type whose size is between two C types will be considered
7476 to be the wider of the two types. Also, we do not have a
7477 special code to use for "long long", so anything wider than
7478 long is treated the same. Note that we can't distinguish
7479 between "int" and "long" in this code if they are the same
7480 size, but that's fine, since neither can the assembler. */
7482 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7483 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
7485 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7486 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
7488 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7489 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
7492 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
7495 /* If this is a range type, consider it to be the underlying
7497 if (TREE_TYPE (type) != 0)
7500 /* Carefully distinguish all the standard types of C,
7501 without messing up if the language is not C. */
7503 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7504 return (qualifiers | 6);
7507 return (qualifiers | 7);
7509 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7510 /* ??? We need to distinguish between double and float complex types,
7511 but I don't know how yet because I can't reach this code from
7512 existing front-ends. */
7513 return (qualifiers | 7); /* Who knows? */
7516 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7517 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7518 case FILE_TYPE: /* GNU Pascal FILE type. */
7519 case SET_TYPE: /* GNU Pascal SET type. */
7520 case LANG_TYPE: /* ? */
7524 abort (); /* Not a type! */
7531 /* Nested function support. */
7533 /* Emit RTL insns to initialize the variable parts of a trampoline.
7534 FNADDR is an RTX for the address of the function's pure code.
7535 CXT is an RTX for the static chain value for the function.
7537 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7538 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7539 (to store insns). This is a bit excessive. Perhaps a different
7540 mechanism would be better here.
7542 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7545 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7547 /* SPARC 32-bit trampoline:
7550 sethi %hi(static), %g2
7552 or %g2, %lo(static), %g2
7554 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7555 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7559 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7560 expand_binop (SImode, ior_optab,
7561 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7562 size_int (10), 0, 1),
7563 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7564 NULL_RTX, 1, OPTAB_DIRECT));
7567 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7568 expand_binop (SImode, ior_optab,
7569 expand_shift (RSHIFT_EXPR, SImode, cxt,
7570 size_int (10), 0, 1),
7571 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7572 NULL_RTX, 1, OPTAB_DIRECT));
7575 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7576 expand_binop (SImode, ior_optab,
7577 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7578 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7579 NULL_RTX, 1, OPTAB_DIRECT));
7582 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7583 expand_binop (SImode, ior_optab,
7584 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7585 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7586 NULL_RTX, 1, OPTAB_DIRECT));
7588 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7589 aligned on a 16 byte boundary so one flush clears it all. */
7590 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7591 if (sparc_cpu != PROCESSOR_ULTRASPARC
7592 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7593 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7594 plus_constant (tramp, 8)))));
7596 /* Call __enable_execute_stack after writing onto the stack to make sure
7597 the stack address is accessible. */
7598 #ifdef ENABLE_EXECUTE_STACK
7599 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7600 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7605 /* The 64-bit version is simpler because it makes more sense to load the
7606 values as "immediate" data out of the trampoline. It's also easier since
7607 we can read the PC without clobbering a register. */
7610 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7612 /* SPARC 64-bit trampoline:
7621 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7622 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7623 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7624 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7625 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7626 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7627 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7628 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7629 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7630 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7631 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7633 if (sparc_cpu != PROCESSOR_ULTRASPARC
7634 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7635 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7637 /* Call __enable_execute_stack after writing onto the stack to make sure
7638 the stack address is accessible. */
7639 #ifdef ENABLE_EXECUTE_STACK
7640 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7641 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7645 /* Adjust the cost of a scheduling dependency. Return the new cost of
7646 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7649 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7651 enum attr_type insn_type;
7653 if (! recog_memoized (insn))
7656 insn_type = get_attr_type (insn);
7658 if (REG_NOTE_KIND (link) == 0)
7660 /* Data dependency; DEP_INSN writes a register that INSN reads some
7663 /* if a load, then the dependence must be on the memory address;
7664 add an extra "cycle". Note that the cost could be two cycles
7665 if the reg was written late in an instruction group; we ca not tell
7667 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7670 /* Get the delay only if the address of the store is the dependence. */
7671 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7673 rtx pat = PATTERN(insn);
7674 rtx dep_pat = PATTERN (dep_insn);
7676 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7677 return cost; /* This should not happen! */
7679 /* The dependency between the two instructions was on the data that
7680 is being stored. Assume that this implies that the address of the
7681 store is not dependent. */
7682 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7685 return cost + 3; /* An approximation. */
7688 /* A shift instruction cannot receive its data from an instruction
7689 in the same cycle; add a one cycle penalty. */
7690 if (insn_type == TYPE_SHIFT)
7691 return cost + 3; /* Split before cascade into shift. */
7695 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7696 INSN writes some cycles later. */
7698 /* These are only significant for the fpu unit; writing a fp reg before
7699 the fpu has finished with it stalls the processor. */
7701 /* Reusing an integer register causes no problems. */
7702 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7710 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7712 enum attr_type insn_type, dep_type;
7713 rtx pat = PATTERN(insn);
7714 rtx dep_pat = PATTERN (dep_insn);
7716 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7719 insn_type = get_attr_type (insn);
7720 dep_type = get_attr_type (dep_insn);
7722 switch (REG_NOTE_KIND (link))
7725 /* Data dependency; DEP_INSN writes a register that INSN reads some
7732 /* Get the delay iff the address of the store is the dependence. */
7733 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7736 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7743 /* If a load, then the dependence must be on the memory address. If
7744 the addresses aren't equal, then it might be a false dependency */
7745 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7747 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7748 || GET_CODE (SET_DEST (dep_pat)) != MEM
7749 || GET_CODE (SET_SRC (pat)) != MEM
7750 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7751 XEXP (SET_SRC (pat), 0)))
7759 /* Compare to branch latency is 0. There is no benefit from
7760 separating compare and branch. */
7761 if (dep_type == TYPE_COMPARE)
7763 /* Floating point compare to branch latency is less than
7764 compare to conditional move. */
7765 if (dep_type == TYPE_FPCMP)
7774 /* Anti-dependencies only penalize the fpu unit. */
7775 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7787 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
7791 case PROCESSOR_SUPERSPARC:
7792 cost = supersparc_adjust_cost (insn, link, dep, cost);
7794 case PROCESSOR_HYPERSPARC:
7795 case PROCESSOR_SPARCLITE86X:
7796 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7805 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7806 int sched_verbose ATTRIBUTE_UNUSED,
7807 int max_ready ATTRIBUTE_UNUSED)
7812 sparc_use_sched_lookahead (void)
7814 if (sparc_cpu == PROCESSOR_ULTRASPARC
7815 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7817 if ((1 << sparc_cpu) &
7818 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7819 (1 << PROCESSOR_SPARCLITE86X)))
7825 sparc_issue_rate (void)
7832 /* Assume V9 processors are capable of at least dual-issue. */
7834 case PROCESSOR_SUPERSPARC:
7836 case PROCESSOR_HYPERSPARC:
7837 case PROCESSOR_SPARCLITE86X:
7839 case PROCESSOR_ULTRASPARC:
7840 case PROCESSOR_ULTRASPARC3:
7846 set_extends (rtx insn)
7848 register rtx pat = PATTERN (insn);
7850 switch (GET_CODE (SET_SRC (pat)))
7852 /* Load and some shift instructions zero extend. */
7855 /* sethi clears the high bits */
7857 /* LO_SUM is used with sethi. sethi cleared the high
7858 bits and the values used with lo_sum are positive */
7860 /* Store flag stores 0 or 1 */
7870 rtx op0 = XEXP (SET_SRC (pat), 0);
7871 rtx op1 = XEXP (SET_SRC (pat), 1);
7872 if (GET_CODE (op1) == CONST_INT)
7873 return INTVAL (op1) >= 0;
7874 if (GET_CODE (op0) != REG)
7876 if (sparc_check_64 (op0, insn) == 1)
7878 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7883 rtx op0 = XEXP (SET_SRC (pat), 0);
7884 rtx op1 = XEXP (SET_SRC (pat), 1);
7885 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7887 if (GET_CODE (op1) == CONST_INT)
7888 return INTVAL (op1) >= 0;
7889 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7892 return GET_MODE (SET_SRC (pat)) == SImode;
7893 /* Positive integers leave the high bits zero. */
7895 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7897 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7900 return - (GET_MODE (SET_SRC (pat)) == SImode);
7902 return sparc_check_64 (SET_SRC (pat), insn);
7908 /* We _ought_ to have only one kind per function, but... */
7909 static GTY(()) rtx sparc_addr_diff_list;
7910 static GTY(()) rtx sparc_addr_list;
7913 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
7915 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7917 sparc_addr_diff_list
7918 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7920 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7924 sparc_output_addr_vec (rtx vec)
7926 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7927 int idx, vlen = XVECLEN (body, 0);
7929 #ifdef ASM_OUTPUT_ADDR_VEC_START
7930 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7933 #ifdef ASM_OUTPUT_CASE_LABEL
7934 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7937 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7940 for (idx = 0; idx < vlen; idx++)
7942 ASM_OUTPUT_ADDR_VEC_ELT
7943 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7946 #ifdef ASM_OUTPUT_ADDR_VEC_END
7947 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7952 sparc_output_addr_diff_vec (rtx vec)
7954 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7955 rtx base = XEXP (XEXP (body, 0), 0);
7956 int idx, vlen = XVECLEN (body, 1);
7958 #ifdef ASM_OUTPUT_ADDR_VEC_START
7959 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7962 #ifdef ASM_OUTPUT_CASE_LABEL
7963 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7966 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7969 for (idx = 0; idx < vlen; idx++)
7971 ASM_OUTPUT_ADDR_DIFF_ELT
7974 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7975 CODE_LABEL_NUMBER (base));
7978 #ifdef ASM_OUTPUT_ADDR_VEC_END
7979 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7984 sparc_output_deferred_case_vectors (void)
7989 if (sparc_addr_list == NULL_RTX
7990 && sparc_addr_diff_list == NULL_RTX)
7993 /* Align to cache line in the function's code section. */
7994 function_section (current_function_decl);
7996 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7998 ASM_OUTPUT_ALIGN (asm_out_file, align);
8000 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8001 sparc_output_addr_vec (XEXP (t, 0));
8002 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8003 sparc_output_addr_diff_vec (XEXP (t, 0));
8005 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8008 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8009 unknown. Return 1 if the high bits are zero, -1 if the register is
8012 sparc_check_64 (rtx x, rtx insn)
8014 /* If a register is set only once it is safe to ignore insns this
8015 code does not know how to handle. The loop will either recognize
8016 the single set and return the correct value or fail to recognize
8021 if (GET_CODE (x) != REG)
8024 if (GET_MODE (x) == DImode)
8025 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8027 if (flag_expensive_optimizations
8028 && REG_N_SETS (REGNO (y)) == 1)
8034 insn = get_last_insn_anywhere ();
8039 while ((insn = PREV_INSN (insn)))
8041 switch (GET_CODE (insn))
8054 rtx pat = PATTERN (insn);
8055 if (GET_CODE (pat) != SET)
8057 if (rtx_equal_p (x, SET_DEST (pat)))
8058 return set_extends (insn);
8059 if (y && rtx_equal_p (y, SET_DEST (pat)))
8060 return set_extends (insn);
8061 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8069 /* Returns assembly code to perform a DImode shift using
8070 a 64-bit global or out register on SPARC-V8+. */
8072 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8074 static char asm_code[60];
8076 /* The scratch register is only required when the destination
8077 register is not a 64-bit global or out register. */
8078 if (which_alternative != 2)
8079 operands[3] = operands[0];
8081 /* We can only shift by constants <= 63. */
8082 if (GET_CODE (operands[2]) == CONST_INT)
8083 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8085 if (GET_CODE (operands[1]) == CONST_INT)
8087 output_asm_insn ("mov\t%1, %3", operands);
8091 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8092 if (sparc_check_64 (operands[1], insn) <= 0)
8093 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8094 output_asm_insn ("or\t%L1, %3, %3", operands);
8097 strcpy(asm_code, opcode);
8099 if (which_alternative != 2)
8100 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8102 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8105 /* Output rtl to increment the profiler label LABELNO
8106 for profiling a function entry. */
8109 sparc_profile_hook (int labelno)
8114 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8115 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8116 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8118 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8121 #ifdef OBJECT_FORMAT_ELF
8123 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8125 if (flags & SECTION_MERGE)
8127 /* entsize cannot be expressed in this section attributes
8129 default_elf_asm_named_section (name, flags);
8133 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8135 if (!(flags & SECTION_DEBUG))
8136 fputs (",#alloc", asm_out_file);
8137 if (flags & SECTION_WRITE)
8138 fputs (",#write", asm_out_file);
8139 if (flags & SECTION_TLS)
8140 fputs (",#tls", asm_out_file);
8141 if (flags & SECTION_CODE)
8142 fputs (",#execinstr", asm_out_file);
8144 /* ??? Handle SECTION_BSS. */
8146 fputc ('\n', asm_out_file);
8148 #endif /* OBJECT_FORMAT_ELF */
8150 /* We do not allow indirect calls to be optimized into sibling calls.
8152 We cannot use sibling calls when delayed branches are disabled
8153 because they will likely require the call delay slot to be filled.
8155 Also, on SPARC 32-bit we cannot emit a sibling call when the
8156 current function returns a structure. This is because the "unimp
8157 after call" convention would cause the callee to return to the
8158 wrong place. The generic code already disallows cases where the
8159 function being called returns a structure.
8161 It may seem strange how this last case could occur. Usually there
8162 is code after the call which jumps to epilogue code which dumps the
8163 return value into the struct return area. That ought to invalidate
8164 the sibling call right? Well, in the C++ case we can end up passing
8165 the pointer to the struct return area to a constructor (which returns
8166 void) and then nothing else happens. Such a sibling call would look
8167 valid without the added check here. */
8169 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8172 && flag_delayed_branch
8173 && (TARGET_ARCH64 || ! current_function_returns_struct));
8176 /* libfunc renaming. */
8177 #include "config/gofast.h"
8180 sparc_init_libfuncs (void)
8184 /* Use the subroutines that Sun's library provides for integer
8185 multiply and divide. The `*' prevents an underscore from
8186 being prepended by the compiler. .umul is a little faster
8188 set_optab_libfunc (smul_optab, SImode, "*.umul");
8189 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8190 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8191 set_optab_libfunc (smod_optab, SImode, "*.rem");
8192 set_optab_libfunc (umod_optab, SImode, "*.urem");
8194 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8195 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8196 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8197 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8198 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8199 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8201 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8202 is because with soft-float, the SFmode and DFmode sqrt
8203 instructions will be absent, and the compiler will notice and
8204 try to use the TFmode sqrt instruction for calls to the
8205 builtin function sqrt, but this fails. */
8207 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8209 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8210 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8211 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8212 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8213 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8214 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8216 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8217 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8218 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8219 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8221 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8222 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8223 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8225 if (DITF_CONVERSION_LIBFUNCS)
8227 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8228 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8229 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
8232 if (SUN_CONVERSION_LIBFUNCS)
8234 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8235 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8236 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8237 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8242 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8243 do not exist in the library. Make sure the compiler does not
8244 emit calls to them by accident. (It should always use the
8245 hardware instructions.) */
8246 set_optab_libfunc (smul_optab, SImode, 0);
8247 set_optab_libfunc (sdiv_optab, SImode, 0);
8248 set_optab_libfunc (udiv_optab, SImode, 0);
8249 set_optab_libfunc (smod_optab, SImode, 0);
8250 set_optab_libfunc (umod_optab, SImode, 0);
8252 if (SUN_INTEGER_MULTIPLY_64)
8254 set_optab_libfunc (smul_optab, DImode, "__mul64");
8255 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8256 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8257 set_optab_libfunc (smod_optab, DImode, "__rem64");
8258 set_optab_libfunc (umod_optab, DImode, "__urem64");
8261 if (SUN_CONVERSION_LIBFUNCS)
8263 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8264 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8265 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8266 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8270 gofast_maybe_init_libfuncs ();
8274 sparc_extra_constraint_check (rtx op, int c, int strict)
8279 && (c == 'T' || c == 'U'))
8285 return fp_sethi_p (op);
8288 return fp_mov_p (op);
8291 return fp_high_losum_p (op);
8295 || (GET_CODE (op) == REG
8296 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8297 || reg_renumber[REGNO (op)] >= 0)))
8298 return register_ok_for_ldd (op);
8310 /* Our memory extra constraints have to emulate the
8311 behavior of 'm' and 'o' in order for reload to work
8313 if (GET_CODE (op) == MEM)
8316 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8318 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8323 reload_ok_mem = (reload_in_progress
8324 && GET_CODE (op) == REG
8325 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8326 && reg_renumber [REGNO (op)] < 0);
8329 return reload_ok_mem;
8332 /* ??? This duplicates information provided to the compiler by the
8333 ??? scheduler description. Some day, teach genautomata to output
8334 ??? the latencies and then CSE will just use that. */
8337 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8339 enum machine_mode mode = GET_MODE (x);
8340 bool float_mode_p = FLOAT_MODE_P (mode);
8345 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8363 if (GET_MODE (x) == DImode
8364 && ((XINT (x, 3) == 0
8365 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8366 || (XINT (x, 3) == -1
8368 && XINT (x, 2) >= -0x1000)))
8375 /* If outer-code was a sign or zero extension, a cost
8376 of COSTS_N_INSNS (1) was already added in. This is
8377 why we are subtracting it back out. */
8378 if (outer_code == ZERO_EXTEND)
8380 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
8382 else if (outer_code == SIGN_EXTEND)
8384 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
8386 else if (float_mode_p)
8388 *total = sparc_costs->float_load;
8392 *total = sparc_costs->int_load;
8400 *total = sparc_costs->float_plusminus;
8402 *total = COSTS_N_INSNS (1);
8407 *total = sparc_costs->float_mul;
8408 else if (! TARGET_HARD_MUL)
8409 *total = COSTS_N_INSNS (25);
8415 if (sparc_costs->int_mul_bit_factor)
8419 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8421 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
8422 for (nbits = 0; value != 0; value &= value - 1)
8425 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
8426 && GET_MODE (XEXP (x, 1)) == DImode)
8428 rtx x1 = XEXP (x, 1);
8429 unsigned HOST_WIDE_INT value1 = XINT (x1, 2);
8430 unsigned HOST_WIDE_INT value2 = XINT (x1, 3);
8432 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
8434 for (; value2 != 0; value2 &= value2 - 1)
8442 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
8443 bit_cost = COSTS_N_INSNS (bit_cost);
8447 *total = sparc_costs->int_mulX + bit_cost;
8449 *total = sparc_costs->int_mul + bit_cost;
8456 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
8466 *total = sparc_costs->float_div_df;
8468 *total = sparc_costs->float_div_sf;
8473 *total = sparc_costs->int_divX;
8475 *total = sparc_costs->int_div;
8482 *total = COSTS_N_INSNS (1);
8489 case UNSIGNED_FLOAT:
8493 case FLOAT_TRUNCATE:
8494 *total = sparc_costs->float_move;
8499 *total = sparc_costs->float_sqrt_df;
8501 *total = sparc_costs->float_sqrt_sf;
8506 *total = sparc_costs->float_cmp;
8508 *total = COSTS_N_INSNS (1);
8513 *total = sparc_costs->float_cmove;
8515 *total = sparc_costs->int_cmove;
8523 /* Emit the sequence of insns SEQ while preserving the register REG. */
8526 emit_and_preserve (rtx seq, rtx reg)
8528 rtx slot = gen_rtx_MEM (word_mode,
8529 plus_constant (stack_pointer_rtx, SPARC_STACK_BIAS));
8531 emit_stack_pointer_decrement (GEN_INT (UNITS_PER_WORD));
8532 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
8534 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
8535 emit_stack_pointer_increment (GEN_INT (UNITS_PER_WORD));
8538 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8539 Used for C++ multiple inheritance. */
8542 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8543 HOST_WIDE_INT delta,
8544 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8547 rtx this, insn, funexp, delta_rtx;
8548 unsigned int int_arg_first;
8550 reload_completed = 1;
8551 epilogue_completed = 1;
8553 reset_block_changes ();
8555 emit_note (NOTE_INSN_PROLOGUE_END);
8557 if (flag_delayed_branch)
8559 /* We will emit a regular sibcall below, so we need to instruct
8560 output_sibcall that we are in a leaf function. */
8561 current_function_uses_only_leaf_regs = 1;
8563 /* This will cause final.c to invoke leaf_renumber_regs so we
8564 must behave as if we were in a not-yet-leafified function. */
8565 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
8569 /* We will emit the sibcall manually below, so we will need to
8570 manually spill non-leaf registers. */
8571 current_function_uses_only_leaf_regs = 0;
8573 /* We really are in a leaf function. */
8574 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
8577 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8578 returns a structure, the structure return pointer is there instead. */
8579 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8580 this = gen_rtx_REG (Pmode, int_arg_first + 1);
8582 this = gen_rtx_REG (Pmode, int_arg_first);
8584 /* Add DELTA. When possible use a plain add, otherwise load it into
8585 a register first. */
8586 delta_rtx = GEN_INT (delta);
8587 if (!SPARC_SIMM13_P (delta))
8589 rtx scratch = gen_rtx_REG (Pmode, 1);
8591 if (input_operand (delta_rtx, GET_MODE (scratch)))
8592 emit_insn (gen_rtx_SET (VOIDmode, scratch, delta_rtx));
8596 sparc_emit_set_const64 (scratch, delta_rtx);
8598 sparc_emit_set_const32 (scratch, delta_rtx);
8601 delta_rtx = scratch;
8604 emit_insn (gen_rtx_SET (VOIDmode,
8606 gen_rtx_PLUS (Pmode, this, delta_rtx)));
8608 /* Generate a tail call to the target function. */
8609 if (! TREE_USED (function))
8611 assemble_external (function);
8612 TREE_USED (function) = 1;
8614 funexp = XEXP (DECL_RTL (function), 0);
8616 if (flag_delayed_branch)
8618 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8619 insn = emit_call_insn (gen_sibcall (funexp));
8620 SIBLING_CALL_P (insn) = 1;
8624 /* The hoops we have to jump through in order to generate a sibcall
8625 without using delay slots... */
8626 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
8630 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
8632 load_pic_register (); /* clobbers %o7 */
8633 scratch = legitimize_pic_address (funexp, Pmode, scratch);
8636 emit_and_preserve (seq, spill_reg);
8638 else if (TARGET_ARCH32)
8640 emit_insn (gen_rtx_SET (VOIDmode,
8642 gen_rtx_HIGH (SImode, funexp)));
8643 emit_insn (gen_rtx_SET (VOIDmode,
8645 gen_rtx_LO_SUM (SImode, scratch, funexp)));
8647 else /* TARGET_ARCH64 */
8649 switch (sparc_cmodel)
8653 /* The destination can serve as a temporary. */
8654 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
8659 /* The destination cannot serve as a temporary. */
8660 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
8662 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
8665 emit_and_preserve (seq, spill_reg);
8673 emit_jump_insn (gen_indirect_jump (scratch));
8678 /* Run just enough of rest_of_compilation to get the insns emitted.
8679 There's not really enough bulk here to make other passes such as
8680 instruction scheduling worth while. Note that use_thunk calls
8681 assemble_start_function and assemble_end_function. */
8682 insn = get_insns ();
8683 insn_locators_initialize ();
8684 shorten_branches (insn);
8685 final_start_function (insn, file, 1);
8686 final (insn, file, 1, 0);
8687 final_end_function ();
8689 reload_completed = 0;
8690 epilogue_completed = 0;
8694 /* How to allocate a 'struct machine_function'. */
8696 static struct machine_function *
8697 sparc_init_machine_status (void)
8699 return ggc_alloc_cleared (sizeof (struct machine_function));
8702 /* Locate some local-dynamic symbol still in use by this function
8703 so that we can print its name in local-dynamic base patterns. */
8706 get_some_local_dynamic_name (void)
8710 if (cfun->machine->some_ld_name)
8711 return cfun->machine->some_ld_name;
8713 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8715 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8716 return cfun->machine->some_ld_name;
8722 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8727 && GET_CODE (x) == SYMBOL_REF
8728 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8730 cfun->machine->some_ld_name = XSTR (x, 0);
8737 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
8738 We need to emit DTP-relative relocations. */
8741 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
8746 fputs ("\t.word\t%r_tls_dtpoff32(", file);
8749 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
8754 output_addr_const (file, x);
8758 #include "gt-sparc.h"