1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92-96, 1997 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
40 /* 1 if the caller has placed an "unimp" insn immediately after the call.
41 This is used in v8 code when calling a function that returns a structure.
42 v9 doesn't have this. Be careful to have this test be the same as that
45 #define SKIP_CALLERS_UNIMP_P \
46 (!TARGET_ARCH64 && current_function_returns_struct \
47 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
48 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
51 /* Global variables for machine-dependent things. */
53 /* Size of frame. Need to know this to emit return insns from leaf procedures.
54 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
55 reload pass. This is important as the value is later used in insn
56 scheduling (to see what can go in a delay slot).
57 APPARENT_FSIZE is the size of the stack less the register save area and less
58 the outgoing argument area. It is used when saving call preserved regs. */
59 static int apparent_fsize;
60 static int actual_fsize;
62 /* Save the operands last given to a compare for use when we
63 generate a scc or bcc insn. */
65 rtx sparc_compare_op0, sparc_compare_op1;
67 /* Count of named arguments (v9 only).
68 ??? INIT_CUMULATIVE_ARGS initializes these, and FUNCTION_ARG_ADVANCE
69 increments SPARC_ARG_COUNT. They are then used by
70 FUNCTION_ARG_CALLEE_COPIES to determine if the argument is really a named
71 argument or not. This hack is necessary because the NAMED argument to the
72 FUNCTION_ARG_XXX macros is not what it says it is: it does not include the
73 last named argument. */
76 int sparc_n_named_args;
78 /* We may need an epilogue if we spill too many registers.
79 If this is non-zero, then we branch here for the epilogue. */
80 static rtx leaf_label;
84 /* Vector to say how input registers are mapped to output
85 registers. FRAME_POINTER_REGNUM cannot be remapped by
86 this function to eliminate it. You must use -fomit-frame-pointer
88 char leaf_reg_remap[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
106 /* Name of where we pretend to think the frame pointer points.
107 Normally, this is "%fp", but if we are in a leaf procedure,
108 this is "%sp+something". We record "something" separately as it may be
109 too big for reg+constant addressing. */
111 static char *frame_base_name;
112 static int frame_base_offset;
114 static rtx find_addr_reg ();
115 static void sparc_init_modes ();
117 /* Option handling. */
119 struct sparc_cpu_select sparc_select[] =
121 /* switch name, tune arch */
122 { (char *)0, "default", 1, 1 },
123 { (char *)0, "-mcpu=", 1, 1 },
124 { (char *)0, "-mtune=", 1, 0 },
128 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
129 enum processor_type sparc_cpu;
131 /* Validate and override various options, and do some machine dependent
135 sparc_override_options ()
137 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
138 static struct cpu_default {
142 { TARGET_CPU_sparc, "cypress" },
143 { TARGET_CPU_v8, "v8" },
144 { TARGET_CPU_supersparc, "supersparc" },
145 { TARGET_CPU_sparclet, "tsc701" },
146 { TARGET_CPU_sparclite, "f930" },
147 { TARGET_CPU_ultrasparc, "ultrasparc" },
150 struct cpu_default *def;
151 /* Table of values for -m{cpu,tune}=. */
152 static struct cpu_table {
154 enum processor_type processor;
158 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
159 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
160 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
161 /* TI TMS390Z55 supersparc */
162 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
163 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
164 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
165 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
166 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
167 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
168 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
170 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
171 /* "v9" is used to specify a true 64 bit architecture.
172 "v8plus" is what Sun calls Solaris2 running on UltraSPARC's. */
173 { "v8plus", PROCESSOR_V8PLUS, MASK_ISA, MASK_V9 },
175 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
178 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 },
181 struct cpu_table *cpu;
182 struct sparc_cpu_select *sel;
184 int fpu = TARGET_FPU; /* save current -mfpu status */
186 /* Set the default. */
187 for (def = &cpu_default[0]; def->name; ++def)
188 if (def->cpu == TARGET_CPU_DEFAULT)
192 sparc_select[0].string = def->name;
194 for (sel = &sparc_select[0]; sel->name; ++sel)
198 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
199 if (! strcmp (sel->string, cpu->name))
202 sparc_cpu = cpu->processor;
206 target_flags &= ~cpu->disable;
207 target_flags |= cpu->enable;
213 error ("bad value (%s) for %s switch", sel->string, sel->name);
217 /* If -mfpu or -mno-fpu was explicitly used, don't override with
218 the processor default. */
220 target_flags = (target_flags & ~MASK_FPU) | fpu;
222 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
223 if (TARGET_V9 && TARGET_ARCH32)
224 target_flags |= MASK_DEPRECATED_V8_INSNS;
226 /* Do various machine dependent initializations. */
230 /* Float conversions (v9 only).
232 The floating point registers cannot hold DImode values because SUBREG's
233 on them get the wrong register. "(subreg:SI (reg:DI M int-reg) 0)" is the
234 same as "(subreg:SI (reg:DI N float-reg) 1)", but gcc doesn't know how to
235 turn the "0" to a "1". Therefore, we must explicitly do the conversions
236 to/from int/fp regs. `sparc64_fpconv_stack_slot' is the address of an
237 8 byte stack slot used during the transfer.
238 ??? I could have used [%fp-16] but I didn't want to add yet another
239 dependence on this. */
240 /* ??? Can we use assign_stack_temp here? */
242 static rtx fpconv_stack_temp;
244 /* Called once for each function. */
247 sparc64_init_expanders ()
249 fpconv_stack_temp = NULL_RTX;
252 /* Assign a stack temp for fp/int DImode conversions. */
255 sparc64_fpconv_stack_temp ()
257 if (fpconv_stack_temp == NULL_RTX)
259 assign_stack_local (DImode, GET_MODE_SIZE (DImode), 0);
261 return fpconv_stack_temp;
264 /* Miscellaneous utilities. */
266 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
267 or branch on register contents instructions. */
273 return (code == EQ || code == NE || code == GE || code == LT
274 || code == LE || code == GT);
277 /* Operand constraints. */
279 /* Return non-zero only if OP is a register of mode MODE,
280 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
281 %g0 may contain anything. */
284 reg_or_0_operand (op, mode)
286 enum machine_mode mode;
288 if (register_operand (op, mode))
292 if (op == const0_rtx)
294 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
295 && CONST_DOUBLE_HIGH (op) == 0
296 && CONST_DOUBLE_LOW (op) == 0)
298 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
299 && GET_CODE (op) == CONST_DOUBLE
300 && fp_zero_operand (op))
305 /* Nonzero if OP is a floating point value with value 0.0. */
313 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
314 return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r));
317 /* Nonzero if OP is an integer register. */
320 intreg_operand (op, mode)
322 enum machine_mode mode;
324 return (register_operand (op, SImode)
325 || (TARGET_ARCH64 && register_operand (op, DImode)));
328 /* Nonzero if OP is a floating point condition code register. */
331 fcc_reg_operand (op, mode)
333 enum machine_mode mode;
335 /* This can happen when recog is called from combine. Op may be a MEM.
336 Fail instead of calling abort in this case. */
337 if (GET_CODE (op) != REG)
340 if (mode != VOIDmode && mode != GET_MODE (op))
343 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
346 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
347 if (reg_renumber == 0)
348 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
349 return REGNO_OK_FOR_CCFP_P (REGNO (op));
351 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
355 /* Nonzero if OP is an integer or floating point condition code register. */
358 icc_or_fcc_reg_operand (op, mode)
360 enum machine_mode mode;
362 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
364 if (mode != VOIDmode && mode != GET_MODE (op))
367 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
372 return fcc_reg_operand (op, mode);
375 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
377 restore_operand (op, mode)
379 enum machine_mode mode;
381 return (GET_CODE (op) == REG && GET_MODE (op) == mode
382 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
385 /* Call insn on SPARC can take a PC-relative constant address, or any regular
389 call_operand (op, mode)
391 enum machine_mode mode;
393 if (GET_CODE (op) != MEM)
396 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
400 call_operand_address (op, mode)
402 enum machine_mode mode;
404 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
407 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
408 reference and a constant. */
411 symbolic_operand (op, mode)
413 enum machine_mode mode;
415 switch (GET_CODE (op))
423 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
424 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
425 && GET_CODE (XEXP (op, 1)) == CONST_INT);
427 /* ??? This clause seems to be irrelevant. */
429 return GET_MODE (op) == mode;
436 /* Return truth value of statement that OP is a symbolic memory
437 operand of mode MODE. */
440 symbolic_memory_operand (op, mode)
442 enum machine_mode mode;
444 if (GET_CODE (op) == SUBREG)
445 op = SUBREG_REG (op);
446 if (GET_CODE (op) != MEM)
449 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
450 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
453 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
456 label_ref_operand (op, mode)
458 enum machine_mode mode;
460 if (GET_CODE (op) != LABEL_REF)
462 if (GET_MODE (op) != mode)
467 /* Return 1 if the operand is an argument used in generating pic references
468 in either the medium/low or medium/anywhere code models of sparc64. */
471 sp64_medium_pic_operand (op, mode)
473 enum machine_mode mode;
475 /* Check for (const (minus (symbol_ref:GOT)
476 (const (minus (label) (pc))))). */
477 if (GET_CODE (op) != CONST)
480 if (GET_CODE (op) != MINUS)
482 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
484 /* ??? Ensure symbol is GOT. */
485 if (GET_CODE (XEXP (op, 1)) != CONST)
487 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
492 /* Return 1 if the operand is a data segment reference. This includes
493 the readonly data segment, or in other words anything but the text segment.
494 This is needed in the medium/anywhere code model on v9. These values
495 are accessed with MEDANY_BASE_REG. */
498 data_segment_operand (op, mode)
500 enum machine_mode mode;
502 switch (GET_CODE (op))
505 return ! SYMBOL_REF_FLAG (op);
507 /* Assume canonical format of symbol + constant.
510 return data_segment_operand (XEXP (op, 0));
516 /* Return 1 if the operand is a text segment reference.
517 This is needed in the medium/anywhere code model on v9. */
520 text_segment_operand (op, mode)
522 enum machine_mode mode;
524 switch (GET_CODE (op))
529 return SYMBOL_REF_FLAG (op);
531 /* Assume canonical format of symbol + constant.
534 return text_segment_operand (XEXP (op, 0));
540 /* Return 1 if the operand is either a register or a memory operand that is
544 reg_or_nonsymb_mem_operand (op, mode)
546 enum machine_mode mode;
548 if (register_operand (op, mode))
551 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
558 sparc_operand (op, mode)
560 enum machine_mode mode;
562 if (register_operand (op, mode))
564 if (GET_CODE (op) == CONST_INT)
565 return SMALL_INT (op);
566 if (GET_MODE (op) != mode)
568 if (GET_CODE (op) == SUBREG)
569 op = SUBREG_REG (op);
570 if (GET_CODE (op) != MEM)
574 if (GET_CODE (op) == LO_SUM)
575 return (GET_CODE (XEXP (op, 0)) == REG
576 && symbolic_operand (XEXP (op, 1), Pmode));
577 return memory_address_p (mode, op);
581 move_operand (op, mode)
583 enum machine_mode mode;
585 if (mode == DImode && arith_double_operand (op, mode))
587 if (register_operand (op, mode))
589 if (GET_CODE (op) == CONST_INT)
590 return (SMALL_INT (op) || (INTVAL (op) & 0x3ff) == 0);
592 if (GET_MODE (op) != mode)
594 if (GET_CODE (op) == SUBREG)
595 op = SUBREG_REG (op);
596 if (GET_CODE (op) != MEM)
599 if (GET_CODE (op) == LO_SUM)
600 return (register_operand (XEXP (op, 0), Pmode)
601 && CONSTANT_P (XEXP (op, 1)));
602 return memory_address_p (mode, op);
606 splittable_symbolic_memory_operand (op, mode)
608 enum machine_mode mode;
610 if (GET_CODE (op) != MEM)
612 if (! symbolic_operand (XEXP (op, 0), Pmode))
618 splittable_immediate_memory_operand (op, mode)
620 enum machine_mode mode;
622 if (GET_CODE (op) != MEM)
624 if (! immediate_operand (XEXP (op, 0), Pmode))
629 /* Return truth value of whether OP is EQ or NE. */
634 enum machine_mode mode;
636 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
639 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
640 or LTU for non-floating-point. We handle those specially. */
643 normal_comp_operator (op, mode)
645 enum machine_mode mode;
647 enum rtx_code code = GET_CODE (op);
649 if (GET_RTX_CLASS (code) != '<')
652 if (GET_MODE (XEXP (op, 0)) == CCFPmode
653 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
656 return (code != NE && code != EQ && code != GEU && code != LTU);
659 /* Return 1 if this is a comparison operator. This allows the use of
660 MATCH_OPERATOR to recognize all the branch insns. */
663 noov_compare_op (op, mode)
665 enum machine_mode mode;
667 enum rtx_code code = GET_CODE (op);
669 if (GET_RTX_CLASS (code) != '<')
672 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
673 /* These are the only branches which work with CC_NOOVmode. */
674 return (code == EQ || code == NE || code == GE || code == LT);
678 /* Nonzero if OP is a comparison operator suitable for use in v9
679 conditional move or branch on register contents instructions. */
682 v9_regcmp_op (op, mode)
684 enum machine_mode mode;
686 enum rtx_code code = GET_CODE (op);
688 if (GET_RTX_CLASS (code) != '<')
691 return v9_regcmp_p (code);
694 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
699 enum machine_mode mode;
701 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
704 /* Return nonzero if OP is an operator of mode MODE which can set
705 the condition codes explicitly. We do not include PLUS and MINUS
706 because these require CC_NOOVmode, which we handle explicitly. */
709 cc_arithop (op, mode)
711 enum machine_mode mode;
713 if (GET_CODE (op) == AND
714 || GET_CODE (op) == IOR
715 || GET_CODE (op) == XOR)
721 /* Return nonzero if OP is an operator of mode MODE which can bitwise
722 complement its second operand and set the condition codes explicitly. */
725 cc_arithopn (op, mode)
727 enum machine_mode mode;
729 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
730 and (xor ... (not ...)) to (not (xor ...)). */
731 return (GET_CODE (op) == AND
732 || GET_CODE (op) == IOR);
735 /* Return true if OP is a register, or is a CONST_INT that can fit in a
736 signed 13 bit immediate field. This is an acceptable SImode operand for
737 most 3 address instructions. */
740 arith_operand (op, mode)
742 enum machine_mode mode;
744 return (register_operand (op, mode)
745 || (GET_CODE (op) == CONST_INT && SMALL_INT (op)));
748 /* Return true if OP is a register, or is a CONST_INT that can fit in a
749 signed 11 bit immediate field. This is an acceptable SImode operand for
750 the movcc instructions. */
753 arith11_operand (op, mode)
755 enum machine_mode mode;
757 return (register_operand (op, mode)
758 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
761 /* Return true if OP is a register, or is a CONST_INT that can fit in a
762 signed 10 bit immediate field. This is an acceptable SImode operand for
763 the movrcc instructions. */
766 arith10_operand (op, mode)
768 enum machine_mode mode;
770 return (register_operand (op, mode)
771 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
774 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
775 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
777 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
778 can fit in a 13 bit immediate field. This is an acceptable DImode operand
779 for most 3 address instructions. */
782 arith_double_operand (op, mode)
784 enum machine_mode mode;
786 return (register_operand (op, mode)
787 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
789 && GET_CODE (op) == CONST_DOUBLE
790 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
791 && (unsigned) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
793 && GET_CODE (op) == CONST_DOUBLE
794 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
795 && ((CONST_DOUBLE_HIGH (op) == -1
796 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
797 || (CONST_DOUBLE_HIGH (op) == 0
798 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
801 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
802 can fit in an 11 bit immediate field. This is an acceptable DImode
803 operand for the movcc instructions. */
804 /* ??? Replace with arith11_operand? */
807 arith11_double_operand (op, mode)
809 enum machine_mode mode;
811 return (register_operand (op, mode)
812 || (GET_CODE (op) == CONST_DOUBLE
813 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
814 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
815 && ((CONST_DOUBLE_HIGH (op) == -1
816 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
817 || (CONST_DOUBLE_HIGH (op) == 0
818 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
819 || (GET_CODE (op) == CONST_INT
820 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
821 && (unsigned) (INTVAL (op) + 0x400) < 0x800));
824 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
825 can fit in an 10 bit immediate field. This is an acceptable DImode
826 operand for the movrcc instructions. */
827 /* ??? Replace with arith10_operand? */
830 arith10_double_operand (op, mode)
832 enum machine_mode mode;
834 return (register_operand (op, mode)
835 || (GET_CODE (op) == CONST_DOUBLE
836 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
837 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
838 && ((CONST_DOUBLE_HIGH (op) == -1
839 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
840 || (CONST_DOUBLE_HIGH (op) == 0
841 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
842 || (GET_CODE (op) == CONST_INT
843 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
844 && (unsigned) (INTVAL (op) + 0x200) < 0x400));
847 /* Return truth value of whether OP is a integer which fits the
848 range constraining immediate operands in most three-address insns,
849 which have a 13 bit immediate field. */
854 enum machine_mode mode;
856 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
859 /* Recognize operand values for the umul instruction. That instruction sign
860 extends immediate values just like all other sparc instructions, but
861 interprets the extended result as an unsigned number. */
864 uns_small_int (op, mode)
866 enum machine_mode mode;
868 #if HOST_BITS_PER_WIDE_INT > 32
869 /* All allowed constants will fit a CONST_INT. */
870 return (GET_CODE (op) == CONST_INT
871 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
872 || (INTVAL (op) >= 0xFFFFF000 && INTVAL (op) < 0x100000000L)));
874 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
875 || (GET_CODE (op) == CONST_DOUBLE
876 && CONST_DOUBLE_HIGH (op) == 0
877 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
882 uns_arith_operand (op, mode)
884 enum machine_mode mode;
886 return register_operand (op, mode) || uns_small_int (op, mode);
889 /* Return truth value of statement that OP is a call-clobbered register. */
891 clobbered_register (op, mode)
893 enum machine_mode mode;
895 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
898 /* X and Y are two things to compare using CODE. Emit the compare insn and
899 return the rtx for the cc reg in the proper mode. */
902 gen_compare_reg (code, x, y)
906 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
909 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
910 fcc regs (cse can't tell they're really call clobbered regs and will
911 remove a duplicate comparison even if there is an intervening function
912 call - it will then try to reload the cc reg via an int reg which is why
913 we need the movcc patterns). It is possible to provide the movcc
914 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
915 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
916 to tell cse that CCFPE mode registers (even pseudos) are call
919 /* ??? This is an experiment. Rather than making changes to cse which may
920 or may not be easy/clean, we do our own cse. This is possible because
921 we will generate hard registers. Cse knows they're call clobbered (it
922 doesn't know the same thing about pseudos). If we guess wrong, no big
923 deal, but if we win, great! */
925 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
926 #if 1 /* experiment */
929 /* We cycle through the registers to ensure they're all exercised. */
930 static int next_fcc_reg = 0;
931 /* Previous x,y for each fcc reg. */
932 static rtx prev_args[4][2];
934 /* Scan prev_args for x,y. */
935 for (reg = 0; reg < 4; reg++)
936 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
941 prev_args[reg][0] = x;
942 prev_args[reg][1] = y;
943 next_fcc_reg = (next_fcc_reg + 1) & 3;
945 cc_reg = gen_rtx (REG, mode, reg + SPARC_FIRST_V9_FCC_REG);
948 cc_reg = gen_reg_rtx (mode);
949 #endif /* ! experiment */
950 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
951 cc_reg = gen_rtx (REG, mode, SPARC_FCC_REG);
953 cc_reg = gen_rtx (REG, mode, SPARC_ICC_REG);
955 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
956 gen_rtx (COMPARE, mode, x, y)));
961 /* This function is used for v9 only.
962 CODE is the code for an Scc's comparison.
963 OPERANDS[0] is the target of the Scc insn.
964 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
967 This function is needed to turn
974 (gt:DI (reg:CCX 0 %g0)
977 IE: The instruction recognizer needs to see the mode of the comparison to
978 find the right instruction. We could use "gt:DI" right in the
979 define_expand, but leaving it out allows us to handle DI, SI, etc.
981 We refer to the global sparc compare operands sparc_compare_op0 and
984 ??? Some of this is outdated as the scc insns set the mode of the
987 ??? We optimize for the case where op1 is 0 and the comparison allows us to
988 use the "movrCC" insns. This reduces the generated code from three to two
989 insns. This way seems too brute force though. Is there a more elegant way
990 to achieve the same effect?
994 gen_v9_scc (compare_code, operands)
995 enum rtx_code compare_code;
996 register rtx *operands;
1000 /* It might be that we'll never be called if this is true,
1001 but keep this here for documentation at least. */
1003 && (GET_MODE (sparc_compare_op0) == DImode
1004 || GET_MODE (operands[0]) == DImode))
1007 /* Try to use the movrCC insns. */
1009 && GET_MODE_CLASS (GET_MODE (sparc_compare_op0)) == MODE_INT
1010 && sparc_compare_op1 == const0_rtx
1011 && v9_regcmp_p (compare_code))
1013 /* Special case for op0 != 0. This can be done with one instruction if
1014 op0 can be clobbered. We store to a temp, and then clobber the temp,
1015 but the combiner will remove the first insn. */
1017 if (compare_code == NE
1018 && GET_MODE (operands[0]) == DImode
1019 && GET_MODE (sparc_compare_op0) == DImode)
1021 emit_insn (gen_rtx (SET, VOIDmode, operands[0], sparc_compare_op0));
1022 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1023 gen_rtx (IF_THEN_ELSE, DImode,
1024 gen_rtx (compare_code, DImode,
1025 sparc_compare_op0, const0_rtx),
1031 emit_insn (gen_rtx (SET, VOIDmode, operands[0], const0_rtx));
1032 if (GET_MODE (sparc_compare_op0) != DImode)
1034 temp = gen_reg_rtx (DImode);
1035 convert_move (temp, sparc_compare_op0, 0);
1039 temp = sparc_compare_op0;
1041 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1042 gen_rtx (IF_THEN_ELSE, GET_MODE (operands[0]),
1043 gen_rtx (compare_code, DImode,
1051 operands[1] = gen_compare_reg (compare_code,
1052 sparc_compare_op0, sparc_compare_op1);
1054 switch (GET_MODE (operands[1]))
1064 emit_insn (gen_rtx (SET, VOIDmode, operands[0], const0_rtx));
1065 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1066 gen_rtx (IF_THEN_ELSE, GET_MODE (operands[0]),
1067 gen_rtx (compare_code,
1068 GET_MODE (operands[1]),
1069 operands[1], const0_rtx),
1070 const1_rtx, operands[0])));
1075 /* Emit a conditional jump insn for the v9 architecture using comparison code
1076 CODE and jump target LABEL.
1077 This function exists to take advantage of the v9 brxx insns. */
1080 emit_v9_brxx_insn (code, op0, label)
1084 emit_jump_insn (gen_rtx (SET, VOIDmode,
1086 gen_rtx (IF_THEN_ELSE, VOIDmode,
1087 gen_rtx (code, GET_MODE (op0),
1089 gen_rtx (LABEL_REF, VOIDmode, label),
1093 /* Return nonzero if a return peephole merging return with
1094 setting of output register is ok. */
1096 leaf_return_peephole_ok ()
1098 return (actual_fsize == 0);
1101 /* Return nonzero if TRIAL can go into the function epilogue's
1102 delay slot. SLOT is the slot we are trying to fill. */
1105 eligible_for_epilogue_delay (trial, slot)
1114 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
1117 if (get_attr_length (trial) != 1)
1120 /* If %g0 is live, there are lots of things we can't handle.
1121 Rather than trying to find them all now, let's punt and only
1122 optimize things as necessary. */
1126 /* In the case of a true leaf function, anything can go into the delay slot.
1127 A delay slot only exists however if the frame size is zero, otherwise
1128 we will put an insn to adjust the stack after the return. */
1131 if (leaf_return_peephole_ok ())
1132 return ((get_attr_in_uncond_branch_delay (trial)
1133 == IN_BRANCH_DELAY_TRUE));
1137 /* If only trivial `restore' insns work, nothing can go in the
1139 else if (TARGET_BROKEN_SAVERESTORE)
1142 pat = PATTERN (trial);
1144 /* Otherwise, only operations which can be done in tandem with
1145 a `restore' insn can go into the delay slot. */
1146 if (GET_CODE (SET_DEST (pat)) != REG
1147 || REGNO (SET_DEST (pat)) >= 32
1148 || REGNO (SET_DEST (pat)) < 24)
1151 /* The set of insns matched here must agree precisely with the set of
1152 patterns paired with a RETURN in sparc.md. */
1154 src = SET_SRC (pat);
1156 /* This matches "*return_[qhs]". */
1157 if (arith_operand (src, GET_MODE (src)))
1158 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
1160 /* This matches "*return_di". */
1161 else if (arith_double_operand (src, GET_MODE (src)))
1162 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
1164 /* This matches "*return_sf_no_fpu". */
1165 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
1166 && register_operand (src, SFmode))
1169 /* This matches "*return_addsi". */
1170 else if (GET_CODE (src) == PLUS
1171 && arith_operand (XEXP (src, 0), SImode)
1172 && arith_operand (XEXP (src, 1), SImode)
1173 && (register_operand (XEXP (src, 0), SImode)
1174 || register_operand (XEXP (src, 1), SImode)))
1177 /* This matches "*return_adddi". */
1178 else if (GET_CODE (src) == PLUS
1179 && arith_double_operand (XEXP (src, 0), DImode)
1180 && arith_double_operand (XEXP (src, 1), DImode)
1181 && (register_operand (XEXP (src, 0), DImode)
1182 || register_operand (XEXP (src, 1), DImode)))
1185 /* This matches "*return_subsi". */
1186 else if (GET_CODE (src) == MINUS
1187 && register_operand (XEXP (src, 0), SImode)
1188 && small_int (XEXP (src, 1), VOIDmode)
1189 && INTVAL (XEXP (src, 1)) != -4096)
1196 short_branch (uid1, uid2)
1199 unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
1200 if (delta + 1024 < 2048)
1202 /* warning ("long branch, distance %d", delta); */
1206 /* Return non-zero if REG is not used after INSN.
1207 We assume REG is a reload reg, and therefore does
1208 not live past labels or calls or jumps. */
1210 reg_unused_after (reg, insn)
1214 enum rtx_code code, prev_code = UNKNOWN;
1216 while (insn = NEXT_INSN (insn))
1218 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
1221 code = GET_CODE (insn);
1222 if (GET_CODE (insn) == CODE_LABEL)
1225 if (GET_RTX_CLASS (code) == 'i')
1227 rtx set = single_set (insn);
1228 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
1231 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1233 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
1241 /* The rtx for the global offset table which is a special form
1242 that *is* a position independent symbolic constant. */
1243 static rtx pic_pc_rtx;
1245 /* Ensure that we are not using patterns that are not OK with PIC. */
1254 if (GET_CODE (recog_operand[i]) == SYMBOL_REF
1255 || (GET_CODE (recog_operand[i]) == CONST
1256 && ! rtx_equal_p (pic_pc_rtx, recog_operand[i])))
1264 /* Return true if X is an address which needs a temporary register when
1265 reloaded while generating PIC code. */
1268 pic_address_needs_scratch (x)
1271 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1272 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
1273 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1274 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1275 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
1281 /* Legitimize PIC addresses. If the address is already position-independent,
1282 we return ORIG. Newly generated position-independent addresses go into a
1283 reg. This is REG if non zero, otherwise we allocate register(s) as
1287 legitimize_pic_address (orig, mode, reg)
1289 enum machine_mode mode;
1292 if (GET_CODE (orig) == SYMBOL_REF)
1294 rtx pic_ref, address;
1299 if (reload_in_progress || reload_completed)
1302 reg = gen_reg_rtx (Pmode);
1307 /* If not during reload, allocate another temp reg here for loading
1308 in the address, so that these instructions can be optimized
1310 rtx temp_reg = ((reload_in_progress || reload_completed)
1311 ? reg : gen_reg_rtx (Pmode));
1313 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
1314 won't get confused into thinking that these two instructions
1315 are loading in the true address of the symbol. If in the
1316 future a PIC rtx exists, that should be used instead. */
1317 emit_insn (gen_pic_sethi_si (temp_reg, orig));
1318 emit_insn (gen_pic_lo_sum_si (temp_reg, temp_reg, orig));
1325 pic_ref = gen_rtx (MEM, Pmode,
1326 gen_rtx (PLUS, Pmode,
1327 pic_offset_table_rtx, address));
1328 current_function_uses_pic_offset_table = 1;
1329 RTX_UNCHANGING_P (pic_ref) = 1;
1330 insn = emit_move_insn (reg, pic_ref);
1331 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1333 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig,
1337 else if (GET_CODE (orig) == CONST)
1341 if (GET_CODE (XEXP (orig, 0)) == PLUS
1342 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1347 if (reload_in_progress || reload_completed)
1350 reg = gen_reg_rtx (Pmode);
1353 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1355 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1356 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1357 base == reg ? 0 : reg);
1362 if (GET_CODE (offset) == CONST_INT)
1364 if (SMALL_INT (offset))
1365 return plus_constant_for_output (base, INTVAL (offset));
1366 else if (! reload_in_progress && ! reload_completed)
1367 offset = force_reg (Pmode, offset);
1369 /* If we reach here, then something is seriously wrong. */
1372 return gen_rtx (PLUS, Pmode, base, offset);
1374 else if (GET_CODE (orig) == LABEL_REF)
1375 /* ??? Why do we do this? */
1376 current_function_uses_pic_offset_table = 1;
1381 /* Set up PIC-specific rtl. This should not cause any insns
1389 /* Emit special PIC prologues and epilogues. */
1394 /* The table we use to reference PIC data. */
1395 rtx global_offset_table;
1396 /* Labels to get the PC in the prologue of this function. */
1399 int orig_flag_pic = flag_pic;
1401 if (current_function_uses_pic_offset_table == 0)
1409 /* ??? sparc64 pic currently under construction. */
1413 l1 = gen_label_rtx ();
1415 /* Initialize every time through, since we can't easily
1416 know this to be permanent. */
1417 global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_");
1418 pic_pc_rtx = gen_rtx (CONST, Pmode,
1419 gen_rtx (MINUS, Pmode,
1420 global_offset_table,
1421 gen_rtx (CONST, Pmode,
1422 gen_rtx (MINUS, Pmode,
1423 gen_rtx (LABEL_REF, VOIDmode, l1),
1426 if (! TARGET_ARCH64)
1428 l2 = gen_label_rtx ();
1430 /* Note that we pun calls and jumps here! */
1431 emit_jump_insn (gen_get_pc_sp32 (l2));
1434 emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx,
1435 gen_rtx (HIGH, Pmode, pic_pc_rtx)));
1437 emit_insn (gen_rtx (SET, VOIDmode,
1438 pic_offset_table_rtx,
1439 gen_rtx (LO_SUM, Pmode,
1440 pic_offset_table_rtx, pic_pc_rtx)));
1441 emit_insn (gen_rtx (SET, VOIDmode,
1442 pic_offset_table_rtx,
1443 gen_rtx (PLUS, Pmode,
1444 pic_offset_table_rtx,
1445 gen_rtx (REG, Pmode, 15))));
1447 /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */
1448 LABEL_PRESERVE_P (l1) = 1;
1449 LABEL_PRESERVE_P (l2) = 1;
1453 /* ??? This definately isn't right for -mfullany. */
1454 /* ??? And it doesn't quite seem right for the others either. */
1456 emit_insn (gen_get_pc_sp64 (gen_rtx (REG, Pmode, 1)));
1458 /* Don't let the scheduler separate the previous insn from `l1'. */
1459 emit_insn (gen_blockage ());
1461 emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx,
1462 gen_rtx (HIGH, Pmode, pic_pc_rtx)));
1464 emit_insn (gen_rtx (SET, VOIDmode,
1465 pic_offset_table_rtx,
1466 gen_rtx (LO_SUM, Pmode,
1467 pic_offset_table_rtx, pic_pc_rtx)));
1468 emit_insn (gen_rtx (SET, VOIDmode,
1469 pic_offset_table_rtx,
1470 gen_rtx (PLUS, Pmode,
1471 pic_offset_table_rtx, gen_rtx (REG, Pmode, 1))));
1473 /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */
1474 LABEL_PRESERVE_P (l1) = 1;
1477 flag_pic = orig_flag_pic;
1479 seq = gen_sequence ();
1481 emit_insn_after (seq, get_insns ());
1483 /* Need to emit this whether or not we obey regdecls,
1484 since setjmp/longjmp can cause life info to screw up. */
1485 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
1488 /* Emit insns to move operands[1] into operands[0].
1490 Return 1 if we have written out everything that needs to be done to
1491 do the move. Otherwise, return 0 and the caller will emit the move
1495 emit_move_sequence (operands, mode)
1497 enum machine_mode mode;
1499 register rtx operand0 = operands[0];
1500 register rtx operand1 = operands[1];
1502 if (CONSTANT_P (operand1) && flag_pic
1503 && pic_address_needs_scratch (operand1))
1504 operands[1] = operand1 = legitimize_pic_address (operand1, mode, 0);
1506 /* Handle most common case first: storing into a register. */
1507 if (register_operand (operand0, mode))
1509 if (register_operand (operand1, mode)
1510 || (GET_CODE (operand1) == CONST_INT && SMALL_INT (operand1))
1511 || (GET_CODE (operand1) == CONST_DOUBLE
1512 && arith_double_operand (operand1, DImode))
1513 || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) != DImode)
1514 /* Only `general_operands' can come here, so MEM is ok. */
1515 || GET_CODE (operand1) == MEM)
1517 /* Run this case quickly. */
1518 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
1522 else if (GET_CODE (operand0) == MEM)
1524 if (register_operand (operand1, mode)
1525 || (operand1 == const0_rtx && ! TARGET_LIVE_G0))
1527 /* Run this case quickly. */
1528 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
1531 if (! reload_in_progress)
1533 operands[0] = validize_mem (operand0);
1534 operands[1] = operand1 = force_reg (mode, operand1);
1538 if (GET_CODE (operand1) == LABEL_REF
1539 && mode == SImode && flag_pic)
1543 emit_insn (gen_move_pic_label_si (operand0, operand1));
1546 /* Non-pic LABEL_REF's in sparc64 are expensive to do the normal way,
1547 so always use special code. */
1548 else if (GET_CODE (operand1) == LABEL_REF
1551 if (! TARGET_ARCH64)
1553 emit_insn (gen_move_label_di (operand0, operand1));
1556 /* DImode HIGH values in sparc64 need a clobber added. */
1557 else if (TARGET_ARCH64
1558 && GET_CODE (operand1) == HIGH && GET_MODE (operand1) == DImode)
1560 emit_insn (gen_sethi_di_sp64 (operand0, XEXP (operand1, 0)));
1563 /* Simplify the source if we need to. */
1564 else if (GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1566 if (flag_pic && symbolic_operand (operand1, mode))
1568 rtx temp_reg = reload_in_progress ? operand0 : 0;
1570 operands[1] = legitimize_pic_address (operand1, mode, temp_reg);
1572 else if (GET_CODE (operand1) == CONST_INT
1573 ? (! SMALL_INT (operand1)
1574 && (INTVAL (operand1) & 0x3ff) != 0)
1575 : (GET_CODE (operand1) == CONST_DOUBLE
1576 ? ! arith_double_operand (operand1, DImode)
1579 /* For DImode values, temp must be operand0 because of the way
1580 HI and LO_SUM work. The LO_SUM operator only copies half of
1581 the LSW from the dest of the HI operator. If the LO_SUM dest is
1582 not the same as the HI dest, then the MSW of the LO_SUM dest will
1585 ??? The real problem here is that the ...(HI:DImode pattern emits
1586 multiple instructions, and the ...(LO_SUM:DImode pattern emits
1587 one instruction. This fails, because the compiler assumes that
1588 LO_SUM copies all bits of the first operand to its dest. Better
1589 would be to have the HI pattern emit one instruction and the
1590 LO_SUM pattern multiple instructions. Even better would be
1591 to use four rtl insns. */
1592 rtx temp = ((reload_in_progress || mode == DImode)
1593 ? operand0 : gen_reg_rtx (mode));
1595 if (TARGET_ARCH64 && mode == DImode)
1596 emit_insn (gen_sethi_di_sp64 (temp, operand1));
1598 emit_insn (gen_rtx (SET, VOIDmode, temp,
1599 gen_rtx (HIGH, mode, operand1)));
1601 operands[1] = gen_rtx (LO_SUM, mode, temp, operand1);
1605 /* Now have insn-emit do whatever it normally does. */
1609 /* Return the best assembler insn template
1610 for moving operands[1] into operands[0] as a fullword. */
1613 singlemove_string (operands)
1616 if (GET_CODE (operands[0]) == MEM)
1618 if (GET_CODE (operands[1]) != MEM)
1623 else if (GET_CODE (operands[1]) == MEM)
1625 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1630 /* Must be SFmode, otherwise this doesn't make sense. */
1631 if (GET_MODE (operands[1]) != SFmode)
1634 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1635 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1636 operands[1] = gen_rtx (CONST_INT, VOIDmode, i);
1638 if (CONST_OK_FOR_LETTER_P (i, 'I'))
1640 else if ((i & 0x000003FF) != 0)
1641 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
1643 return "sethi %%hi(%a1),%0";
1645 else if (GET_CODE (operands[1]) == CONST_INT
1646 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'I'))
1648 int i = INTVAL (operands[1]);
1650 /* If all low order 10 bits are clear, then we only need a single
1651 sethi insn to load the constant. */
1652 if ((i & 0x000003FF) != 0)
1653 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
1655 return "sethi %%hi(%a1),%0";
1657 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
1661 /* Return non-zero if it is OK to assume that the given memory operand is
1662 aligned at least to a 8-byte boundary. This should only be called
1663 for memory accesses whose size is 8 bytes or larger. */
1671 register rtx offset;
1673 if (GET_CODE (mem) != MEM)
1674 return 0; /* It's gotta be a MEM! */
1676 addr = XEXP (mem, 0);
1678 /* Now that all misaligned double parms are copied on function entry,
1679 we can assume any 64-bit object is 64-bit aligned except those which
1680 are at unaligned offsets from the stack or frame pointer. If the
1681 TARGET_UNALIGNED_DOUBLES switch is given, we do not make this
1684 /* See what register we use in the address. */
1686 if (GET_CODE (addr) == PLUS)
1688 if (GET_CODE (XEXP (addr, 0)) == REG
1689 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
1691 base = XEXP (addr, 0);
1692 offset = XEXP (addr, 1);
1695 else if (GET_CODE (addr) == REG)
1698 offset = const0_rtx;
1701 /* If it's the stack or frame pointer, check offset alignment.
1702 We can have improper alignment in the function entry code. */
1704 && (REGNO (base) == FRAME_POINTER_REGNUM
1705 || REGNO (base) == STACK_POINTER_REGNUM))
1707 if (((INTVAL (offset) - SPARC_STACK_BIAS) & 0x7) == 0)
1710 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
1711 is true, in which case we can only assume that an access is aligned if
1712 it is to a constant address, or the address involves a LO_SUM.
1714 We used to assume an address was aligned if MEM_IN_STRUCT_P was true.
1715 That assumption was deleted so that gcc generated code can be used with
1716 memory allocators that only guarantee 4 byte alignment. */
1717 else if (! TARGET_UNALIGNED_DOUBLES || CONSTANT_P (addr)
1718 || GET_CODE (addr) == LO_SUM)
1721 /* An obviously unaligned address. */
1725 enum optype { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP };
1727 /* Output assembler code to perform a doubleword move insn
1728 with operands OPERANDS. This is very similar to the following
1729 output_move_quad function. */
1732 output_move_double (operands)
1735 register rtx op0 = operands[0];
1736 register rtx op1 = operands[1];
1737 register enum optype optype0;
1738 register enum optype optype1;
1742 int highest_first = 0;
1743 int no_addreg1_decrement = 0;
1745 /* First classify both operands. */
1749 else if (offsettable_memref_p (op0))
1751 else if (GET_CODE (op0) == MEM)
1758 else if (CONSTANT_P (op1))
1760 else if (offsettable_memref_p (op1))
1762 else if (GET_CODE (op1) == MEM)
1767 /* Check for the cases that the operand constraints are not
1768 supposed to allow to happen. Abort if we get one,
1769 because generating code for these cases is painful. */
1771 if (optype0 == RNDOP || optype1 == RNDOP
1772 || (optype0 == MEM && optype1 == MEM))
1775 /* If an operand is an unoffsettable memory ref, find a register
1776 we can increment temporarily to make it refer to the second word. */
1778 if (optype0 == MEMOP)
1779 addreg0 = find_addr_reg (XEXP (op0, 0));
1781 if (optype1 == MEMOP)
1782 addreg1 = find_addr_reg (XEXP (op1, 0));
1784 /* Ok, we can do one word at a time.
1785 Set up in LATEHALF the operands to use for the
1786 high-numbered (least significant) word and in some cases alter the
1787 operands in OPERANDS to be suitable for the low-numbered word. */
1789 if (optype0 == REGOP)
1790 latehalf[0] = gen_rtx (REG, SImode, REGNO (op0) + 1);
1791 else if (optype0 == OFFSOP)
1792 latehalf[0] = adj_offsettable_operand (op0, 4);
1796 if (optype1 == REGOP)
1797 latehalf[1] = gen_rtx (REG, SImode, REGNO (op1) + 1);
1798 else if (optype1 == OFFSOP)
1799 latehalf[1] = adj_offsettable_operand (op1, 4);
1800 else if (optype1 == CNSTOP)
1804 if (arith_double_operand (op1, DImode))
1806 operands[1] = gen_rtx (CONST_INT, VOIDmode,
1807 CONST_DOUBLE_LOW (op1));
1812 /* The only way to handle CONST_DOUBLEs or other 64 bit
1813 constants here is to use a temporary, such as is done
1814 for the V9 DImode sethi insn pattern. This is not
1815 a practical solution, so abort if we reach here.
1816 The md file should always force such constants to
1822 split_double (op1, &operands[1], &latehalf[1]);
1827 /* Easy case: try moving both words at once. Check for moving between
1828 an even/odd register pair and a memory location. */
1829 if ((optype0 == REGOP && optype1 != REGOP && optype1 != CNSTOP
1830 && (TARGET_ARCH64 || (REGNO (op0) & 1) == 0))
1831 || (optype0 != REGOP && optype0 != CNSTOP && optype1 == REGOP
1832 && (TARGET_ARCH64 || (REGNO (op1) & 1) == 0)))
1834 register rtx mem,reg;
1836 if (optype0 == REGOP)
1837 mem = op1, reg = op0;
1839 mem = op0, reg = op1;
1841 /* In v9, ldd can be used for word aligned addresses, so technically
1842 some of this logic is unneeded. We still avoid ldd if the address
1843 is obviously unaligned though. */
1845 if (mem_aligned_8 (mem)
1846 /* If this is a floating point register higher than %f31,
1847 then we *must* use an aligned load, since `ld' will not accept
1848 the register number. */
1849 || (TARGET_V9 && REGNO (reg) >= 64))
1851 if (FP_REG_P (reg) || ! TARGET_ARCH64)
1852 return (mem == op1 ? "ldd %1,%0" : "std %1,%0");
1854 return (mem == op1 ? "ldx %1,%0" : "stx %1,%0");
1860 if (optype0 == REGOP && optype1 == REGOP)
1863 return "fmovd %1,%0";
1869 /* If the first move would clobber the source of the second one,
1870 do them in the other order. */
1872 /* Overlapping registers. */
1873 if (optype0 == REGOP && optype1 == REGOP
1874 && REGNO (op0) == REGNO (latehalf[1]))
1877 output_asm_insn (singlemove_string (latehalf), latehalf);
1878 /* Do low-numbered word. */
1879 return singlemove_string (operands);
1881 /* Loading into a register which overlaps a register used in the address. */
1882 else if (optype0 == REGOP && optype1 != REGOP
1883 && reg_overlap_mentioned_p (op0, op1))
1885 /* If both halves of dest are used in the src memory address,
1886 add the two regs and put them in the low reg (op0).
1887 Then it works to load latehalf first. */
1888 if (reg_mentioned_p (op0, XEXP (op1, 0))
1889 && reg_mentioned_p (latehalf[0], XEXP (op1, 0)))
1892 xops[0] = latehalf[0];
1894 output_asm_insn ("add %1,%0,%1", xops);
1895 operands[1] = gen_rtx (MEM, DImode, op0);
1896 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1900 /* Only one register in the dest is used in the src memory address,
1901 and this is the first register of the dest, so we want to do
1902 the late half first here also. */
1903 else if (! reg_mentioned_p (latehalf[0], XEXP (op1, 0)))
1905 /* Only one register in the dest is used in the src memory address,
1906 and this is the second register of the dest, so we want to do
1907 the late half last. If addreg1 is set, and addreg1 is the same
1908 register as latehalf, then we must suppress the trailing decrement,
1909 because it would clobber the value just loaded. */
1910 else if (addreg1 && reg_mentioned_p (addreg1, latehalf[0]))
1911 no_addreg1_decrement = 1;
1914 /* Normal case: do the two words, low-numbered first.
1915 Overlap case (highest_first set): do high-numbered word first. */
1917 if (! highest_first)
1918 output_asm_insn (singlemove_string (operands), operands);
1920 /* Make any unoffsettable addresses point at high-numbered word. */
1922 output_asm_insn ("add %0,0x4,%0", &addreg0);
1924 output_asm_insn ("add %0,0x4,%0", &addreg1);
1927 output_asm_insn (singlemove_string (latehalf), latehalf);
1929 /* Undo the adds we just did. */
1931 output_asm_insn ("add %0,-0x4,%0", &addreg0);
1932 if (addreg1 && ! no_addreg1_decrement)
1933 output_asm_insn ("add %0,-0x4,%0", &addreg1);
1936 output_asm_insn (singlemove_string (operands), operands);
1941 /* Output assembler code to perform a quadword move insn
1942 with operands OPERANDS. This is very similar to the preceding
1943 output_move_double function. */
1946 output_move_quad (operands)
1949 register rtx op0 = operands[0];
1950 register rtx op1 = operands[1];
1951 register enum optype optype0;
1952 register enum optype optype1;
1957 /* First classify both operands. */
1961 else if (offsettable_memref_p (op0))
1963 else if (GET_CODE (op0) == MEM)
1970 else if (CONSTANT_P (op1))
1972 else if (offsettable_memref_p (op1))
1974 else if (GET_CODE (op1) == MEM)
1979 /* Check for the cases that the operand constraints are not
1980 supposed to allow to happen. Abort if we get one,
1981 because generating code for these cases is painful. */
1983 if (optype0 == RNDOP || optype1 == RNDOP
1984 || (optype0 == MEM && optype1 == MEM))
1987 /* If an operand is an unoffsettable memory ref, find a register
1988 we can increment temporarily to make it refer to the later words. */
1990 if (optype0 == MEMOP)
1991 addreg0 = find_addr_reg (XEXP (op0, 0));
1993 if (optype1 == MEMOP)
1994 addreg1 = find_addr_reg (XEXP (op1, 0));
1996 /* Ok, we can do one word at a time.
1997 Set up in wordpart the operands to use for each word of the arguments. */
1999 if (optype0 == REGOP)
2001 wordpart[0][0] = gen_rtx (REG, SImode, REGNO (op0) + 0);
2002 wordpart[1][0] = gen_rtx (REG, SImode, REGNO (op0) + 1);
2003 wordpart[2][0] = gen_rtx (REG, SImode, REGNO (op0) + 2);
2004 wordpart[3][0] = gen_rtx (REG, SImode, REGNO (op0) + 3);
2006 else if (optype0 == OFFSOP)
2008 wordpart[0][0] = adj_offsettable_operand (op0, 0);
2009 wordpart[1][0] = adj_offsettable_operand (op0, 4);
2010 wordpart[2][0] = adj_offsettable_operand (op0, 8);
2011 wordpart[3][0] = adj_offsettable_operand (op0, 12);
2015 wordpart[0][0] = op0;
2016 wordpart[1][0] = op0;
2017 wordpart[2][0] = op0;
2018 wordpart[3][0] = op0;
2021 if (optype1 == REGOP)
2023 wordpart[0][1] = gen_rtx (REG, SImode, REGNO (op1) + 0);
2024 wordpart[1][1] = gen_rtx (REG, SImode, REGNO (op1) + 1);
2025 wordpart[2][1] = gen_rtx (REG, SImode, REGNO (op1) + 2);
2026 wordpart[3][1] = gen_rtx (REG, SImode, REGNO (op1) + 3);
2028 else if (optype1 == OFFSOP)
2030 wordpart[0][1] = adj_offsettable_operand (op1, 0);
2031 wordpart[1][1] = adj_offsettable_operand (op1, 4);
2032 wordpart[2][1] = adj_offsettable_operand (op1, 8);
2033 wordpart[3][1] = adj_offsettable_operand (op1, 12);
2035 else if (optype1 == CNSTOP)
2040 /* This only works for TFmode floating point constants. */
2041 if (GET_CODE (op1) != CONST_DOUBLE || GET_MODE (op1) != TFmode)
2044 REAL_VALUE_FROM_CONST_DOUBLE (r, op1);
2045 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
2047 wordpart[0][1] = GEN_INT (l[0]);
2048 wordpart[1][1] = GEN_INT (l[1]);
2049 wordpart[2][1] = GEN_INT (l[2]);
2050 wordpart[3][1] = GEN_INT (l[3]);
2054 wordpart[0][1] = op1;
2055 wordpart[1][1] = op1;
2056 wordpart[2][1] = op1;
2057 wordpart[3][1] = op1;
2060 /* Easy case: try moving the quad as two pairs. Check for moving between
2061 an even/odd register pair and a memory location.
2062 Also handle new v9 fp regs here. */
2063 /* ??? Should also handle the case of non-offsettable addresses here.
2064 We can at least do the first pair as a ldd/std, and then do the third
2065 and fourth words individually. */
2066 if ((optype0 == REGOP && optype1 == OFFSOP && (REGNO (op0) & 1) == 0)
2067 || (optype0 == OFFSOP && optype1 == REGOP && (REGNO (op1) & 1) == 0))
2071 if (optype0 == REGOP)
2072 mem = op1, reg = op0;
2074 mem = op0, reg = op1;
2076 if (mem_aligned_8 (mem)
2077 /* If this is a floating point register higher than %f31,
2078 then we *must* use an aligned load, since `ld' will not accept
2079 the register number. */
2080 || (TARGET_V9 && REGNO (reg) >= 64))
2082 if (TARGET_V9 && FP_REG_P (reg) && TARGET_HARD_QUAD)
2084 if ((REGNO (reg) & 3) != 0)
2086 return (mem == op1 ? "ldq %1,%0" : "stq %1,%0");
2088 operands[2] = adj_offsettable_operand (mem, 8);
2089 /* ??? In arch64 case, shouldn't we use ldd/std for fp regs. */
2091 return TARGET_ARCH64 ? "ldx %1,%0;ldx %2,%R0" : "ldd %1,%0;ldd %2,%S0";
2093 return TARGET_ARCH64 ? "stx %1,%0;stx %R1,%2" : "std %1,%0;std %S1,%2";
2097 /* If the first move would clobber the source of the second one,
2098 do them in the other order. */
2100 /* Overlapping registers. */
2101 if (optype0 == REGOP && optype1 == REGOP
2102 && (REGNO (op0) == REGNO (wordpart[1][3])
2103 || REGNO (op0) == REGNO (wordpart[1][2])
2104 || REGNO (op0) == REGNO (wordpart[1][1])))
2106 /* Do fourth word. */
2107 output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]);
2108 /* Do the third word. */
2109 output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]);
2110 /* Do the second word. */
2111 output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]);
2112 /* Do lowest-numbered word. */
2113 return singlemove_string (wordpart[0]);
2115 /* Loading into a register which overlaps a register used in the address. */
2116 if (optype0 == REGOP && optype1 != REGOP
2117 && reg_overlap_mentioned_p (op0, op1))
2119 /* ??? Not implemented yet. This is a bit complicated, because we
2120 must load which ever part overlaps the address last. If the address
2121 is a double-reg address, then there are two parts which need to
2122 be done last, which is impossible. We would need a scratch register
2127 /* Normal case: move the four words in lowest to highest address order. */
2129 output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]);
2131 /* Make any unoffsettable addresses point at the second word. */
2133 output_asm_insn ("add %0,0x4,%0", &addreg0);
2135 output_asm_insn ("add %0,0x4,%0", &addreg1);
2137 /* Do the second word. */
2138 output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]);
2140 /* Make any unoffsettable addresses point at the third word. */
2142 output_asm_insn ("add %0,0x4,%0", &addreg0);
2144 output_asm_insn ("add %0,0x4,%0", &addreg1);
2146 /* Do the third word. */
2147 output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]);
2149 /* Make any unoffsettable addresses point at the fourth word. */
2151 output_asm_insn ("add %0,0x4,%0", &addreg0);
2153 output_asm_insn ("add %0,0x4,%0", &addreg1);
2155 /* Do the fourth word. */
2156 output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]);
2158 /* Undo the adds we just did. */
2160 output_asm_insn ("add %0,-0xc,%0", &addreg0);
2162 output_asm_insn ("add %0,-0xc,%0", &addreg1);
2167 /* Output assembler code to perform a doubleword move insn with operands
2168 OPERANDS, one of which must be a floating point register. */
2171 output_fp_move_double (operands)
2174 if (FP_REG_P (operands[0]))
2176 if (FP_REG_P (operands[1]))
2179 return "fmovd %1,%0";
2181 return "fmovs %1,%0\n\tfmovs %R1,%R0";
2183 else if (GET_CODE (operands[1]) == REG)
2186 return output_move_double (operands);
2188 else if (FP_REG_P (operands[1]))
2190 if (GET_CODE (operands[0]) == REG)
2193 return output_move_double (operands);
2198 /* Output assembler code to perform a quadword move insn with operands
2199 OPERANDS, one of which must be a floating point register. */
2202 output_fp_move_quad (operands)
2205 register rtx op0 = operands[0];
2206 register rtx op1 = operands[1];
2213 return "fmovq %1,%0";
2215 return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0";
2217 else if (GET_CODE (op1) == REG)
2220 return output_move_quad (operands);
2222 else if (FP_REG_P (op1))
2224 if (GET_CODE (op0) == REG)
2227 return output_move_quad (operands);
2233 /* Return a REG that occurs in ADDR with coefficient 1.
2234 ADDR can be effectively incremented by incrementing REG. */
2237 find_addr_reg (addr)
2240 while (GET_CODE (addr) == PLUS)
2242 /* We absolutely can not fudge the frame pointer here, because the
2243 frame pointer must always be 8 byte aligned. It also confuses
2245 if (GET_CODE (XEXP (addr, 0)) == REG
2246 && REGNO (XEXP (addr, 0)) != FRAME_POINTER_REGNUM)
2247 addr = XEXP (addr, 0);
2248 else if (GET_CODE (XEXP (addr, 1)) == REG
2249 && REGNO (XEXP (addr, 1)) != FRAME_POINTER_REGNUM)
2250 addr = XEXP (addr, 1);
2251 else if (CONSTANT_P (XEXP (addr, 0)))
2252 addr = XEXP (addr, 1);
2253 else if (CONSTANT_P (XEXP (addr, 1)))
2254 addr = XEXP (addr, 0);
2258 if (GET_CODE (addr) == REG)
2263 #if 0 /* not currently used */
2266 output_sized_memop (opname, mode, signedp)
2268 enum machine_mode mode;
2271 static char *ld_size_suffix_u[] = { "ub", "uh", "", "?", "d" };
2272 static char *ld_size_suffix_s[] = { "sb", "sh", "", "?", "d" };
2273 static char *st_size_suffix[] = { "b", "h", "", "?", "d" };
2274 char **opnametab, *modename;
2276 if (opname[0] == 'l')
2278 opnametab = ld_size_suffix_s;
2280 opnametab = ld_size_suffix_u;
2282 opnametab = st_size_suffix;
2283 modename = opnametab[GET_MODE_SIZE (mode) >> 1];
2285 fprintf (asm_out_file, "\t%s%s", opname, modename);
2289 output_move_with_extension (operands)
2292 if (GET_MODE (operands[2]) == HImode)
2293 output_asm_insn ("sll %2,0x10,%0", operands);
2294 else if (GET_MODE (operands[2]) == QImode)
2295 output_asm_insn ("sll %2,0x18,%0", operands);
2299 #endif /* not currently used */
2302 /* ??? These are only used by the movstrsi pattern, but we get better code
2303 in general without that, because emit_block_move can do just as good a
2304 job as this function does when alignment and size are known. When they
2305 aren't known, a call to strcpy may be faster anyways, because it is
2306 likely to be carefully crafted assembly language code, and below we just
2307 do a byte-wise copy.
2309 Also, emit_block_move expands into multiple read/write RTL insns, which
2310 can then be optimized, whereas our movstrsi pattern can not be optimized
2313 /* Load the address specified by OPERANDS[3] into the register
2314 specified by OPERANDS[0].
2316 OPERANDS[3] may be the result of a sum, hence it could either be:
2321 (3) REG + REG + CONST_INT
2322 (4) REG + REG (special case of 3).
2324 Note that (3) is not a legitimate address.
2325 All cases are handled here. */
2328 output_load_address (operands)
2333 if (CONSTANT_P (operands[3]))
2335 output_asm_insn ("set %3,%0", operands);
2339 if (REG_P (operands[3]))
2341 if (REGNO (operands[0]) != REGNO (operands[3]))
2342 output_asm_insn ("mov %3,%0", operands);
2346 if (GET_CODE (operands[3]) != PLUS)
2349 base = XEXP (operands[3], 0);
2350 offset = XEXP (operands[3], 1);
2352 if (GET_CODE (base) == CONST_INT)
2359 if (GET_CODE (offset) != CONST_INT)
2361 /* Operand is (PLUS (REG) (REG)). */
2363 offset = const0_rtx;
2369 operands[7] = offset;
2370 if (SMALL_INT (offset))
2371 output_asm_insn ("add %6,%7,%0", operands);
2373 output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands);
2375 else if (GET_CODE (base) == PLUS)
2377 operands[6] = XEXP (base, 0);
2378 operands[7] = XEXP (base, 1);
2379 operands[8] = offset;
2381 if (SMALL_INT (offset))
2382 output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands);
2384 output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands);
2390 /* Output code to place a size count SIZE in register REG.
2391 ALIGN is the size of the unit of transfer.
2393 Because block moves are pipelined, we don't include the
2394 first element in the transfer of SIZE to REG. */
2397 output_size_for_block_move (size, reg, align)
2404 xoperands[1] = size;
2405 xoperands[2] = align;
2406 if (GET_CODE (size) == REG)
2407 output_asm_insn ("sub %1,%2,%0", xoperands);
2411 = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align));
2412 output_asm_insn ("set %1,%0", xoperands);
2416 /* Emit code to perform a block move.
2418 OPERANDS[0] is the destination.
2419 OPERANDS[1] is the source.
2420 OPERANDS[2] is the size.
2421 OPERANDS[3] is the alignment safe to use.
2422 OPERANDS[4] is a register we can safely clobber as a temp. */
2425 output_block_move (operands)
2428 /* A vector for our computed operands. Note that load_output_address
2429 makes use of (and can clobber) up to the 8th element of this vector. */
2432 static int movstrsi_label = 0;
2434 rtx temp1 = operands[4];
2435 rtx sizertx = operands[2];
2436 rtx alignrtx = operands[3];
2437 int align = INTVAL (alignrtx);
2438 char label3[30], label5[30];
2440 xoperands[0] = operands[0];
2441 xoperands[1] = operands[1];
2442 xoperands[2] = temp1;
2444 /* We can't move more than this many bytes at a time because we have only
2445 one register, %g1, to move them through. */
2446 if (align > UNITS_PER_WORD)
2448 align = UNITS_PER_WORD;
2449 alignrtx = gen_rtx (CONST_INT, VOIDmode, UNITS_PER_WORD);
2452 /* We consider 8 ld/st pairs, for a total of 16 inline insns to be
2453 reasonable here. (Actually will emit a maximum of 18 inline insns for
2454 the case of size == 31 and align == 4). */
2456 if (GET_CODE (sizertx) == CONST_INT && (INTVAL (sizertx) / align) <= 8
2457 && memory_address_p (QImode, plus_constant_for_output (xoperands[0],
2459 && memory_address_p (QImode, plus_constant_for_output (xoperands[1],
2462 int size = INTVAL (sizertx);
2465 /* We will store different integers into this particular RTX. */
2466 xoperands[2] = rtx_alloc (CONST_INT);
2467 PUT_MODE (xoperands[2], VOIDmode);
2469 /* This case is currently not handled. Abort instead of generating
2471 if (align > UNITS_PER_WORD)
2474 if (TARGET_ARCH64 && align >= 8)
2476 for (i = (size >> 3) - 1; i >= 0; i--)
2478 INTVAL (xoperands[2]) = (i << 3) + offset;
2479 output_asm_insn ("ldx [%a1+%2],%%g1\n\tstx %%g1,[%a0+%2]",
2482 offset += (size & ~0x7);
2490 for (i = (size >> 2) - 1; i >= 0; i--)
2492 INTVAL (xoperands[2]) = (i << 2) + offset;
2493 output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]",
2496 offset += (size & ~0x3);
2504 for (i = (size >> 1) - 1; i >= 0; i--)
2506 INTVAL (xoperands[2]) = (i << 1) + offset;
2507 output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]",
2510 offset += (size & ~0x1);
2518 for (i = size - 1; i >= 0; i--)
2520 INTVAL (xoperands[2]) = i + offset;
2521 output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]",
2527 /* We should never reach here. */
2531 /* If the size isn't known to be a multiple of the alignment,
2532 we have to do it in smaller pieces. If we could determine that
2533 the size was a multiple of 2 (or whatever), we could be smarter
2535 if (GET_CODE (sizertx) != CONST_INT)
2539 int size = INTVAL (sizertx);
2540 while (size % align)
2544 if (align != INTVAL (alignrtx))
2545 alignrtx = gen_rtx (CONST_INT, VOIDmode, align);
2547 xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
2548 xoperands[4] = gen_rtx (CONST_INT, VOIDmode, align);
2549 xoperands[5] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
2551 ASM_GENERATE_INTERNAL_LABEL (label3, "Lm", INTVAL (xoperands[3]));
2552 ASM_GENERATE_INTERNAL_LABEL (label5, "Lm", INTVAL (xoperands[5]));
2554 /* This is the size of the transfer. Emit code to decrement the size
2555 value by ALIGN, and store the result in the temp1 register. */
2556 output_size_for_block_move (sizertx, temp1, alignrtx);
2558 /* Must handle the case when the size is zero or negative, so the first thing
2559 we do is compare the size against zero, and only copy bytes if it is
2560 zero or greater. Note that we have already subtracted off the alignment
2561 once, so we must copy 1 alignment worth of bytes if the size is zero
2564 The SUN assembler complains about labels in branch delay slots, so we
2565 do this before outputting the load address, so that there will always
2566 be a harmless insn between the branch here and the next label emitted
2572 sprintf (pattern, "cmp %%2,0\n\tbl %s", &label5[1]);
2573 output_asm_insn (pattern, xoperands);
2576 zoperands[0] = operands[0];
2577 zoperands[3] = plus_constant_for_output (operands[0], align);
2578 output_load_address (zoperands);
2580 /* ??? This might be much faster if the loops below were preconditioned
2583 That is, at run time, copy enough bytes one at a time to ensure that the
2584 target and source addresses are aligned to the the largest possible
2585 alignment. Then use a preconditioned unrolled loop to copy say 16
2586 bytes at a time. Then copy bytes one at a time until finish the rest. */
2588 /* Output the first label separately, so that it is spaced properly. */
2590 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "Lm", INTVAL (xoperands[3]));
2594 register char *ld_suffix = ((align == 1) ? "ub" : (align == 2) ? "uh"
2595 : (align == 8 && TARGET_ARCH64) ? "x" : "");
2596 register char *st_suffix = ((align == 1) ? "b" : (align == 2) ? "h"
2597 : (align == 8 && TARGET_ARCH64) ? "x" : "");
2599 sprintf (pattern, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix, &label3[1], st_suffix, &label5[1]);
2600 output_asm_insn (pattern, xoperands);
2607 /* Output reasonable peephole for set-on-condition-code insns.
2608 Note that these insns assume a particular way of defining
2609 labels. Therefore, *both* sparc.h and this function must
2610 be changed if a new syntax is needed. */
2613 output_scc_insn (operands, insn)
2617 static char string[100];
2618 rtx label = 0, next = insn;
2621 /* Try doing a jump optimization which jump.c can't do for us
2622 because we did not expose that setcc works by using branches.
2624 If this scc insn is followed by an unconditional branch, then have
2625 the jump insn emitted here jump to that location, instead of to
2626 the end of the scc sequence as usual. */
2630 if (GET_CODE (next) == CODE_LABEL)
2632 next = NEXT_INSN (next);
2636 while (GET_CODE (next) == NOTE || GET_CODE (next) == CODE_LABEL);
2638 /* If we are in a sequence, and the following insn is a sequence also,
2639 then just following the current insn's next field will take us to the
2640 first insn of the next sequence, which is the wrong place. We don't
2641 want to optimize with a branch that has had its delay slot filled.
2642 Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next
2643 which fails only if NEXT is such a branch. */
2645 if (next && GET_CODE (next) == JUMP_INSN && simplejump_p (next)
2646 && (! final_sequence || NEXT_INSN (PREV_INSN (next)) == next))
2647 label = JUMP_LABEL (next);
2648 /* If not optimizing, jump label fields are not set. To be safe, always
2649 check here to whether label is still zero. */
2652 label = gen_label_rtx ();
2656 LABEL_NUSES (label) += 1;
2658 /* operands[3] is an unused slot. */
2659 operands[3] = label;
2661 /* If we are in a delay slot, assume it is the delay slot of an fpcc
2662 insn since our type isn't allowed anywhere else. */
2664 /* ??? Fpcc instructions no longer have delay slots, so this code is
2665 probably obsolete. */
2667 /* The fastest way to emit code for this is an annulled branch followed
2668 by two move insns. This will take two cycles if the branch is taken,
2669 and three cycles if the branch is not taken.
2671 However, if we are in the delay slot of another branch, this won't work,
2672 because we can't put a branch in the delay slot of another branch.
2673 The above sequence would effectively take 3 or 4 cycles respectively
2674 since a no op would have be inserted between the two branches.
2675 In this case, we want to emit a move, annulled branch, and then the
2676 second move. This sequence always takes 3 cycles, and hence is faster
2677 when we are in a branch delay slot. */
2681 strcpy (string, "mov 0,%0\n\t");
2682 strcat (string, output_cbranch (operands[2], 3, 0, 1, 0));
2683 strcat (string, "\n\tmov 1,%0");
2687 strcpy (string, output_cbranch (operands[2], 3, 0, 1, 0));
2688 strcat (string, "\n\tmov 1,%0\n\tmov 0,%0");
2692 strcat (string, "\n%l3:");
2697 /* Vectors to keep interesting information about registers where it can easily
2698 be got. We use to use the actual mode value as the bit number, but there
2699 are more than 32 modes now. Instead we use two tables: one indexed by
2700 hard register number, and one indexed by mode. */
2702 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2703 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2704 mapped into one sparc_mode_class mode. */
2706 enum sparc_mode_class {
2707 S_MODE, D_MODE, T_MODE, O_MODE,
2708 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2712 /* Modes for single-word and smaller quantities. */
2713 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2715 /* Modes for double-word and smaller quantities. */
2716 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2718 /* Modes for quad-word and smaller quantities. */
2719 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2721 /* Modes for single-float quantities. We must allow any single word or
2722 smaller quantity. This is because the fix/float conversion instructions
2723 take integer inputs/outputs from the float registers. */
2724 #define SF_MODES (S_MODES)
2726 /* Modes for double-float and smaller quantities. */
2727 #define DF_MODES (S_MODES | D_MODES)
2729 /* ??? Sparc64 fp regs cannot hold DImode values. */
2730 #define DF_MODES64 (SF_MODES | DF_MODE /* | D_MODE*/)
2732 /* Modes for double-float only quantities. */
2733 /* ??? Sparc64 fp regs cannot hold DImode values.
2734 See fix_truncsfdi2. */
2735 #define DF_ONLY_MODES ((1 << (int) DF_MODE) /*| (1 << (int) D_MODE)*/)
2737 /* Modes for double-float and larger quantities. */
2738 #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
2740 /* Modes for quad-float only quantities. */
2741 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2743 /* Modes for quad-float and smaller quantities. */
2744 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2746 /* ??? Sparc64 fp regs cannot hold DImode values.
2747 See fix_truncsfdi2. */
2748 #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
2750 /* Modes for condition codes. */
2751 #define CC_MODES (1 << (int) CC_MODE)
2752 #define CCFP_MODES (1 << (int) CCFP_MODE)
2754 /* Value is 1 if register/mode pair is acceptable on sparc.
2755 The funny mixture of D and T modes is because integer operations
2756 do not specially operate on tetra quantities, so non-quad-aligned
2757 registers can hold quadword quantities (except %o4 and %i4 because
2758 they cross fixed registers). */
2760 /* This points to either the 32 bit or the 64 bit version. */
2761 int *hard_regno_mode_classes;
2763 static int hard_32bit_mode_classes[] = {
2764 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2765 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2766 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2767 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2769 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2770 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2771 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2772 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2774 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2775 and none can hold SFmode/SImode values. */
2776 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2777 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2778 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2779 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2782 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2788 static int hard_64bit_mode_classes[] = {
2789 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2790 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2791 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2792 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2794 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2795 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2796 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2797 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2799 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2800 and none can hold SFmode/SImode values. */
2801 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2802 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2803 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2804 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2807 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2813 int sparc_mode_class [NUM_MACHINE_MODES];
2815 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
2822 for (i = 0; i < NUM_MACHINE_MODES; i++)
2824 switch (GET_MODE_CLASS (i))
2827 case MODE_PARTIAL_INT:
2828 case MODE_COMPLEX_INT:
2829 if (GET_MODE_SIZE (i) <= 4)
2830 sparc_mode_class[i] = 1 << (int) S_MODE;
2831 else if (GET_MODE_SIZE (i) == 8)
2832 sparc_mode_class[i] = 1 << (int) D_MODE;
2833 else if (GET_MODE_SIZE (i) == 16)
2834 sparc_mode_class[i] = 1 << (int) T_MODE;
2835 else if (GET_MODE_SIZE (i) == 32)
2836 sparc_mode_class[i] = 1 << (int) O_MODE;
2838 sparc_mode_class[i] = 0;
2841 case MODE_COMPLEX_FLOAT:
2842 if (GET_MODE_SIZE (i) <= 4)
2843 sparc_mode_class[i] = 1 << (int) SF_MODE;
2844 else if (GET_MODE_SIZE (i) == 8)
2845 sparc_mode_class[i] = 1 << (int) DF_MODE;
2846 else if (GET_MODE_SIZE (i) == 16)
2847 sparc_mode_class[i] = 1 << (int) TF_MODE;
2848 else if (GET_MODE_SIZE (i) == 32)
2849 sparc_mode_class[i] = 1 << (int) OF_MODE;
2851 sparc_mode_class[i] = 0;
2855 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
2856 we must explicitly check for them here. */
2857 if (i == (int) CCFPmode || i == (int) CCFPEmode)
2858 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
2859 else if (i == (int) CCmode || i == (int) CC_NOOVmode
2860 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
2861 sparc_mode_class[i] = 1 << (int) CC_MODE;
2863 sparc_mode_class[i] = 0;
2869 hard_regno_mode_classes = hard_64bit_mode_classes;
2871 hard_regno_mode_classes = hard_32bit_mode_classes;
2873 /* Initialize the array used by REGNO_REG_CLASS. */
2874 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2877 sparc_regno_reg_class[i] = GENERAL_REGS;
2879 sparc_regno_reg_class[i] = FP_REGS;
2881 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
2883 sparc_regno_reg_class[i] = FPCC_REGS;
2885 sparc_regno_reg_class[i] = NO_REGS;
2889 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
2890 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2891 v9 int regs as it simplifies the code. */
2897 save_regs (file, low, high, base, offset, n_regs)
2906 if (TARGET_ARCH64 && high <= 32)
2908 for (i = low; i < high; i++)
2910 if (regs_ever_live[i] && ! call_used_regs[i])
2911 fprintf (file, "\tstx %s,[%s+%d]\n",
2912 reg_names[i], base, offset + 4 * n_regs),
2918 for (i = low; i < high; i += 2)
2920 if (regs_ever_live[i] && ! call_used_regs[i])
2921 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2922 fprintf (file, "\tstd %s,[%s+%d]\n",
2923 reg_names[i], base, offset + 4 * n_regs),
2926 fprintf (file, "\tst %s,[%s+%d]\n",
2927 reg_names[i], base, offset + 4 * n_regs),
2929 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2930 fprintf (file, "\tst %s,[%s+%d]\n",
2931 reg_names[i+1], base, offset + 4 * n_regs + 4),
2938 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
2940 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2941 v9 int regs as it simplifies the code. */
2947 restore_regs (file, low, high, base, offset, n_regs)
2956 if (TARGET_ARCH64 && high <= 32)
2958 for (i = low; i < high; i++)
2960 if (regs_ever_live[i] && ! call_used_regs[i])
2961 fprintf (file, "\tldx [%s+%d], %s\n",
2962 base, offset + 4 * n_regs, reg_names[i]),
2968 for (i = low; i < high; i += 2)
2970 if (regs_ever_live[i] && ! call_used_regs[i])
2971 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2972 fprintf (file, "\tldd [%s+%d], %s\n",
2973 base, offset + 4 * n_regs, reg_names[i]),
2976 fprintf (file, "\tld [%s+%d],%s\n",
2977 base, offset + 4 * n_regs, reg_names[i]),
2979 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2980 fprintf (file, "\tld [%s+%d],%s\n",
2981 base, offset + 4 * n_regs + 4, reg_names[i+1]),
2988 /* Static variables we want to share between prologue and epilogue. */
2990 /* Number of live general or floating point registers needed to be saved
2991 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
2992 static int num_gfregs;
2994 /* Compute the frame size required by the function. This function is called
2995 during the reload pass and also by output_function_prologue(). */
2998 compute_frame_size (size, leaf_function)
3003 int outgoing_args_size = (current_function_outgoing_args_size
3005 + REG_PARM_STACK_SPACE (current_function_decl)
3009 if (TARGET_EPILOGUE)
3011 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3012 even to v9 int regs to be consistent with save_regs/restore_regs. */
3016 for (i = 0; i < 8; i++)
3017 if (regs_ever_live[i] && ! call_used_regs[i])
3022 for (i = 0; i < 8; i += 2)
3023 if ((regs_ever_live[i] && ! call_used_regs[i])
3024 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3028 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3029 if ((regs_ever_live[i] && ! call_used_regs[i])
3030 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3034 /* Set up values for use in `function_epilogue'. */
3035 num_gfregs = n_regs;
3037 if (leaf_function && n_regs == 0
3038 && size == 0 && current_function_outgoing_args_size == 0)
3040 actual_fsize = apparent_fsize = 0;
3044 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3045 The stack bias (if any) is taken out to undo its effects. */
3046 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
3047 apparent_fsize += n_regs * 4;
3048 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3051 /* Make sure nothing can clobber our register windows.
3052 If a SAVE must be done, or there is a stack-local variable,
3053 the register window area must be allocated.
3054 ??? For v9 we need an additional 8 bytes of reserved space, apparently
3055 it's needed by v8 as well. */
3056 if (leaf_function == 0 || size > 0)
3057 actual_fsize += (16 * UNITS_PER_WORD) + 8;
3059 return SPARC_STACK_ALIGN (actual_fsize);
3062 /* Build a (32 bit) big number in a register. */
3063 /* ??? We may be able to use the set macro here too. */
3066 build_big_number (file, num, reg)
3071 if (num >= 0 || ! TARGET_ARCH64)
3073 fprintf (file, "\tsethi %%hi(%d),%s\n", num, reg);
3074 if ((num & 0x3ff) != 0)
3075 fprintf (file, "\tor %s,%%lo(%d),%s\n", reg, num, reg);
3077 else /* num < 0 && TARGET_ARCH64 */
3079 /* Sethi does not sign extend, so we must use a little trickery
3080 to use it for negative numbers. Invert the constant before
3081 loading it in, then use xor immediate to invert the loaded bits
3082 (along with the upper 32 bits) to the desired constant. This
3083 works because the sethi and immediate fields overlap. */
3086 int low = -0x400 + (asize & 0x3FF);
3088 fprintf (file, "\tsethi %%hi(%d),%s\n\txor %s,%d,%s\n",
3089 inv, reg, reg, low, reg);
3093 /* Output code for the function prologue. */
3096 output_function_prologue (file, size, leaf_function)
3101 /* Need to use actual_fsize, since we are also allocating
3102 space for our callee (and our own register save area). */
3103 actual_fsize = compute_frame_size (size, leaf_function);
3107 frame_base_name = "%sp";
3108 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3112 frame_base_name = "%fp";
3113 frame_base_offset = SPARC_STACK_BIAS;
3116 /* This is only for the human reader. */
3117 fprintf (file, "\t!#PROLOGUE# 0\n");
3119 if (actual_fsize == 0)
3121 else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
3123 if (actual_fsize <= 4096)
3124 fprintf (file, "\tsave %%sp,-%d,%%sp\n", actual_fsize);
3125 else if (actual_fsize <= 8192)
3127 fprintf (file, "\tsave %%sp,-4096,%%sp\n");
3128 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096);
3132 build_big_number (file, -actual_fsize, "%g1");
3133 fprintf (file, "\tsave %%sp,%%g1,%%sp\n");
3136 else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
3138 /* We assume the environment will properly handle or otherwise avoid
3139 trouble associated with an interrupt occuring after the `save' or
3140 trap occuring during it. */
3141 fprintf (file, "\tsave\n");
3143 if (actual_fsize <= 4096)
3144 fprintf (file, "\tadd %%fp,-%d,%%sp\n", actual_fsize);
3145 else if (actual_fsize <= 8192)
3147 fprintf (file, "\tadd %%fp,-4096,%%sp\n");
3148 fprintf (file, "\tadd %%fp,-%d,%%sp\n", actual_fsize - 4096);
3152 build_big_number (file, -actual_fsize, "%g1");
3153 fprintf (file, "\tadd %%fp,%%g1,%%sp\n");
3156 else /* leaf function */
3158 if (actual_fsize <= 4096)
3159 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize);
3160 else if (actual_fsize <= 8192)
3162 fprintf (file, "\tadd %%sp,-4096,%%sp\n");
3163 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096);
3167 build_big_number (file, -actual_fsize, "%g1");
3168 fprintf (file, "\tadd %%sp,%%g1,%%sp\n");
3172 /* If doing anything with PIC, do it now. */
3174 fprintf (file, "\t!#PROLOGUE# 1\n");
3176 /* Call saved registers are saved just above the outgoing argument area. */
3182 offset = -apparent_fsize + frame_base_offset;
3183 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3185 /* ??? This might be optimized a little as %g1 might already have a
3186 value close enough that a single add insn will do. */
3187 /* ??? Although, all of this is probably only a temporary fix
3188 because if %g1 can hold a function result, then
3189 output_function_epilogue will lose (the result will get
3191 build_big_number (file, offset, "%g1");
3192 fprintf (file, "\tadd %s,%%g1,%%g1\n", frame_base_name);
3198 base = frame_base_name;
3201 if (TARGET_EPILOGUE && ! leaf_function)
3202 /* ??? Originally saved regs 0-15 here. */
3203 n_regs = save_regs (file, 0, 8, base, offset, 0);
3204 else if (leaf_function)
3205 /* ??? Originally saved regs 0-31 here. */
3206 n_regs = save_regs (file, 0, 8, base, offset, 0);
3207 if (TARGET_EPILOGUE)
3208 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3212 if (leaf_function && actual_fsize != 0)
3214 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3215 if (! TARGET_EPILOGUE)
3216 leaf_label = gen_label_rtx ();
3220 /* Output code for the function epilogue. */
3223 output_function_epilogue (file, size, leaf_function)
3232 emit_label_after (leaf_label, get_last_insn ());
3233 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3236 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3237 else if (profile_block_flag == 2)
3239 FUNCTION_BLOCK_PROFILER_EXIT(file);
3243 /* Restore any call saved registers. */
3249 offset = -apparent_fsize + frame_base_offset;
3250 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3252 build_big_number (file, offset, "%g1");
3253 fprintf (file, "\tadd %s,%%g1,%%g1\n", frame_base_name);
3259 base = frame_base_name;
3262 if (TARGET_EPILOGUE && ! leaf_function)
3263 /* ??? Originally saved regs 0-15 here. */
3264 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3265 else if (leaf_function)
3266 /* ??? Originally saved regs 0-31 here. */
3267 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3268 if (TARGET_EPILOGUE)
3269 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3272 /* Work out how to skip the caller's unimp instruction if required. */
3274 ret = (SKIP_CALLERS_UNIMP_P ? "jmp %o7+12" : "retl");
3276 ret = (SKIP_CALLERS_UNIMP_P ? "jmp %i7+12" : "ret");
3278 if (TARGET_EPILOGUE || leaf_label)
3280 int old_target_epilogue = TARGET_EPILOGUE;
3281 target_flags &= ~old_target_epilogue;
3283 if (! leaf_function)
3285 /* If we wound up with things in our delay slot, flush them here. */
3286 if (current_function_epilogue_delay_list)
3288 rtx insn = emit_jump_insn_after (gen_rtx (RETURN, VOIDmode),
3290 PATTERN (insn) = gen_rtx (PARALLEL, VOIDmode,
3292 PATTERN (XEXP (current_function_epilogue_delay_list, 0)),
3294 final_scan_insn (insn, file, 1, 0, 1);
3297 fprintf (file, "\t%s\n\trestore\n", ret);
3299 /* All of the following cases are for leaf functions. */
3300 else if (current_function_epilogue_delay_list)
3302 /* eligible_for_epilogue_delay_slot ensures that if this is a
3303 leaf function, then we will only have insn in the delay slot
3304 if the frame size is zero, thus no adjust for the stack is
3306 if (actual_fsize != 0)
3308 fprintf (file, "\t%s\n", ret);
3309 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3312 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3313 avoid generating confusing assembly language output. */
3314 else if (actual_fsize == 0)
3315 fprintf (file, "\t%s\n\tnop\n", ret);
3316 else if (actual_fsize <= 4096)
3317 fprintf (file, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret, actual_fsize);
3318 else if (actual_fsize <= 8192)
3319 fprintf (file, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n",
3320 ret, actual_fsize - 4096);
3321 else if ((actual_fsize & 0x3ff) == 0)
3322 fprintf (file, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
3325 fprintf (file, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
3326 actual_fsize, actual_fsize, ret);
3327 target_flags |= old_target_epilogue;
3331 /* Do what is necessary for `va_start'. The argument is ignored.
3332 !v9: We look at the current function to determine if stdarg or varargs
3333 is used and return the address of the first unnamed parameter.
3334 v9: We save the argument integer and floating point regs in a buffer, and
3335 return the address of this buffer. The rest is handled in va-sparc.h. */
3336 /* ??? This is currently conditioned on SPARC_ARCH64 because
3337 current_function_args_info is different in each compiler. */
3342 sparc_builtin_saveregs (arglist)
3345 tree fntype = TREE_TYPE (current_function_decl);
3346 /* First unnamed integer register. */
3347 int first_intreg = current_function_args_info.arg_count[(int) SPARC_ARG_INT];
3348 /* Number of integer registers we need to save. */
3349 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
3350 /* First unnamed SFmode float reg (no, you can't pass SFmode floats as
3351 unnamed arguments, we just number them that way). We must round up to
3352 the next double word float reg - that is the first one to save. */
3353 int first_floatreg = current_function_args_info.arg_count[(int) SPARC_ARG_FLOAT] + 1 & ~1;
3354 /* Number of SFmode float regs to save. */
3355 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
3356 int ptrsize = GET_MODE_SIZE (Pmode);
3357 rtx valist, regbuf, fpregs;
3358 int bufsize, adjust, regno;
3360 /* Allocate block of memory for the regs.
3361 We only allocate as much as we need, but we must ensure quadword float
3362 regs are stored with the appropriate alignment. */
3363 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
3364 Or can assign_stack_local accept a 0 SIZE argument? */
3366 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * (UNITS_PER_WORD / 2));
3367 /* Add space in front of the int regs to ensure proper alignment of quadword
3368 fp regs. We must add the space in front because va_start assumes this. */
3369 if (n_floatregs >= 4)
3370 adjust = ((n_intregs + first_floatreg / 2) % 2) * UNITS_PER_WORD;
3374 regbuf = assign_stack_local (BLKmode, bufsize + adjust,
3375 GET_MODE_BITSIZE (TFmode));
3376 regbuf = gen_rtx (MEM, BLKmode, plus_constant (XEXP (regbuf, 0), adjust));
3377 MEM_IN_STRUCT_P (regbuf) = 1;
3380 This is optimized to only save the regs that are necessary. Explicitly
3381 named args need not be saved. */
3384 move_block_from_reg (BASE_INCOMING_ARG_REG (SImode) + first_intreg,
3385 regbuf, n_intregs, n_intregs * UNITS_PER_WORD);
3388 This is optimized to only save the regs that are necessary. Explicitly
3389 named args need not be saved.
3390 We explicitly build a pointer to the buffer because it halves the insn
3391 count when not optimizing (otherwise the pointer is built for each reg
3394 fpregs = gen_reg_rtx (Pmode);
3395 emit_move_insn (fpregs, plus_constant (XEXP (regbuf, 0),
3396 n_intregs * UNITS_PER_WORD));
3397 for (regno = first_floatreg; regno < NPARM_REGS (SFmode); regno += 2)
3398 emit_move_insn (gen_rtx (MEM, DFmode,
3399 plus_constant (fpregs,
3400 GET_MODE_SIZE (SFmode)
3401 * (regno - first_floatreg))),
3402 gen_rtx (REG, DFmode,
3403 BASE_INCOMING_ARG_REG (DFmode) + regno));
3405 /* Return the address of the regbuf. */
3407 return XEXP (regbuf, 0);
3410 #else /* ! SPARC_ARCH64 */
3413 sparc_builtin_saveregs (arglist)
3416 tree fntype = TREE_TYPE (current_function_decl);
3417 int stdarg = (TYPE_ARG_TYPES (fntype) != 0
3418 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3419 != void_type_node));
3420 int first_reg = current_function_args_info;
3424 #if 0 /* This code seemed to have no effect except to make
3425 varargs not work right when va_list wasn't the first arg. */
3430 for (regno = first_reg; regno < NPARM_REGS (SImode); regno++)
3431 emit_move_insn (gen_rtx (MEM, word_mode,
3432 gen_rtx (PLUS, Pmode,
3434 GEN_INT (STACK_POINTER_OFFSET
3435 + UNITS_PER_WORD * regno))),
3436 gen_rtx (REG, word_mode, BASE_INCOMING_ARG_REG (word_mode)
3439 address = gen_rtx (PLUS, Pmode,
3441 GEN_INT (STACK_POINTER_OFFSET
3442 + UNITS_PER_WORD * first_reg));
3447 #endif /* ! SPARC_ARCH64 */
3449 /* Return the string to output a conditional branch to LABEL, which is
3450 the operand number of the label. OP is the conditional expression.
3451 XEXP (OP, 0) is assumed to be a condition code register (integer or
3452 floating point) and its mode specifies what kind of comparison we made.
3454 REVERSED is non-zero if we should reverse the sense of the comparison.
3456 ANNUL is non-zero if we should generate an annulling branch.
3458 NOOP is non-zero if we have to follow this branch by a noop. */
3461 output_cbranch (op, label, reversed, annul, noop)
3464 int reversed, annul, noop;
3466 static char string[20];
3467 enum rtx_code code = GET_CODE (op);
3468 rtx cc_reg = XEXP (op, 0);
3469 enum machine_mode mode = GET_MODE (cc_reg);
3470 static char v8_labelno[] = " %lX";
3471 static char v9_icc_labelno[] = " %%icc,%lX";
3472 static char v9_xcc_labelno[] = " %%xcc,%lX";
3473 static char v9_fcc_labelno[] = " %%fccX,%lY";
3477 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
3478 Because there is currently no concept of pre-delay slots, we can fix
3479 this only by always emitting a nop before a floating point branch. */
3481 if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9)
3482 strcpy (string, "nop\n\t");
3486 /* If not floating-point or if EQ or NE, we can just reverse the code. */
3488 && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE))
3489 code = reverse_condition (code), reversed = 0;
3491 /* Start by writing the branch condition. */
3495 if (mode == CCFPmode || mode == CCFPEmode)
3496 strcat (string, "fbne");
3498 strcpy (string, "bne");
3502 if (mode == CCFPmode || mode == CCFPEmode)
3503 strcat (string, "fbe");
3505 strcpy (string, "be");
3509 if (mode == CCFPmode || mode == CCFPEmode)
3512 strcat (string, "fbul");
3514 strcat (string, "fbge");
3516 else if (mode == CC_NOOVmode)
3517 strcpy (string, "bpos");
3519 strcpy (string, "bge");
3523 if (mode == CCFPmode || mode == CCFPEmode)
3526 strcat (string, "fbule");
3528 strcat (string, "fbg");
3531 strcpy (string, "bg");
3535 if (mode == CCFPmode || mode == CCFPEmode)
3538 strcat (string, "fbug");
3540 strcat (string, "fble");
3543 strcpy (string, "ble");
3547 if (mode == CCFPmode || mode == CCFPEmode)
3550 strcat (string, "fbuge");
3552 strcat (string, "fbl");
3554 else if (mode == CC_NOOVmode)
3555 strcpy (string, "bneg");
3557 strcpy (string, "bl");
3561 strcpy (string, "bgeu");
3565 strcpy (string, "bgu");
3569 strcpy (string, "bleu");
3573 strcpy (string, "blu");
3577 /* Now add the annulling, the label, and a possible noop. */
3579 strcat (string, ",a");
3581 /* ??? If v9, optional prediction bit ",pt" or ",pf" goes here. */
3586 labelno = v8_labelno;
3591 if (mode == CCFPmode || mode == CCFPEmode)
3594 labelno = v9_fcc_labelno;
3595 /* Set the char indicating the number of the fcc reg to use. */
3596 labelno[6] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
3598 else if (mode == CCXmode || mode == CCX_NOOVmode)
3599 labelno = v9_xcc_labelno;
3601 labelno = v9_icc_labelno;
3603 /* Set the char indicating the number of the operand containing the
3605 labelno[labeloff] = label + '0';
3606 strcat (string, labelno);
3609 strcat (string, "\n\tnop");
3614 /* Return the string to output a conditional branch to LABEL, testing
3615 register REG. LABEL is the operand number of the label; REG is the
3616 operand number of the reg. OP is the conditional expression. The mode
3617 of REG says what kind of comparison we made.
3619 REVERSED is non-zero if we should reverse the sense of the comparison.
3621 ANNUL is non-zero if we should generate an annulling branch.
3623 NOOP is non-zero if we have to follow this branch by a noop. */
3626 output_v9branch (op, reg, label, reversed, annul, noop)
3629 int reversed, annul, noop;
3631 static char string[20];
3632 enum rtx_code code = GET_CODE (op);
3633 enum machine_mode mode = GET_MODE (XEXP (op, 0));
3634 static char labelno[] = " %X,%lX";
3636 /* If not floating-point or if EQ or NE, we can just reverse the code. */
3638 code = reverse_condition (code), reversed = 0;
3640 /* Only 64 bit versions of these instructions exist. */
3644 /* Start by writing the branch condition. */
3649 strcpy (string, "brnz");
3653 strcpy (string, "brz");
3657 strcpy (string, "brgez");
3661 strcpy (string, "brlz");
3665 strcpy (string, "brlez");
3669 strcpy (string, "brgz");
3676 /* Now add the annulling, reg, label, and nop. */
3678 strcat (string, ",a");
3680 /* ??? Optional prediction bit ",pt" or ",pf" goes here. */
3682 labelno[2] = reg + '0';
3683 labelno[6] = label + '0';
3684 strcat (string, labelno);
3687 strcat (string, "\n\tnop");
3692 /* Output assembler code to return from a function. */
3694 /* ??? v9: Update to use the new `return' instruction. Also, add patterns to
3695 md file for the `return' instruction. */
3698 output_return (operands)
3703 operands[0] = leaf_label;
3706 else if (leaf_function)
3708 /* If we didn't allocate a frame pointer for the current function,
3709 the stack pointer might have been adjusted. Output code to
3712 operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize);
3714 /* Use sub of negated value in first two cases instead of add to
3715 allow actual_fsize == 4096. */
3717 if (actual_fsize <= 4096)
3719 if (SKIP_CALLERS_UNIMP_P)
3720 return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp";
3722 return "retl\n\tsub %%sp,-%0,%%sp";
3724 else if (actual_fsize <= 8192)
3726 operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize - 4096);
3727 if (SKIP_CALLERS_UNIMP_P)
3728 return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp";
3730 return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp";
3732 else if (SKIP_CALLERS_UNIMP_P)
3734 if ((actual_fsize & 0x3ff) != 0)
3735 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
3737 return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
3741 if ((actual_fsize & 0x3ff) != 0)
3742 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
3744 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
3749 if (SKIP_CALLERS_UNIMP_P)
3750 return "jmp %%i7+12\n\trestore";
3752 return "ret\n\trestore";
3756 /* Leaf functions and non-leaf functions have different needs. */
3759 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
3762 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
3764 static int *reg_alloc_orders[] = {
3765 reg_leaf_alloc_order,
3766 reg_nonleaf_alloc_order};
3769 order_regs_for_local_alloc ()
3771 static int last_order_nonleaf = 1;
3773 if (regs_ever_live[15] != last_order_nonleaf)
3775 last_order_nonleaf = !last_order_nonleaf;
3776 bcopy ((char *) reg_alloc_orders[last_order_nonleaf],
3777 (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int));
3781 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
3782 This makes them candidates for using ldd and std insns.
3784 Note reg1 and reg2 *must* be hard registers. To be sure we will
3785 abort if we are passed pseudo registers. */
3788 registers_ok_for_ldd_peep (reg1, reg2)
3791 /* We might have been passed a SUBREG. */
3792 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
3795 if (REGNO (reg1) % 2 != 0)
3798 return (REGNO (reg1) == REGNO (reg2) - 1);
3801 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
3804 This can only happen when addr1 and addr2 are consecutive memory
3805 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
3806 64 bit boundary (addr1 % 8 == 0).
3808 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
3809 registers are assumed to *never* be properly aligned and are
3812 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
3813 need only check that the offset for addr1 % 8 == 0. */
3816 addrs_ok_for_ldd_peep (addr1, addr2)
3821 /* Extract a register number and offset (if used) from the first addr. */
3822 if (GET_CODE (addr1) == PLUS)
3824 /* If not a REG, return zero. */
3825 if (GET_CODE (XEXP (addr1, 0)) != REG)
3829 reg1 = REGNO (XEXP (addr1, 0));
3830 /* The offset must be constant! */
3831 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
3833 offset1 = INTVAL (XEXP (addr1, 1));
3836 else if (GET_CODE (addr1) != REG)
3840 reg1 = REGNO (addr1);
3841 /* This was a simple (mem (reg)) expression. Offset is 0. */
3845 /* Make sure the second address is a (mem (plus (reg) (const_int). */
3846 if (GET_CODE (addr2) != PLUS)
3849 if (GET_CODE (XEXP (addr2, 0)) != REG
3850 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
3853 /* Only %fp and %sp are allowed. Additionally both addresses must
3854 use the same register. */
3855 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
3858 if (reg1 != REGNO (XEXP (addr2, 0)))
3861 /* The first offset must be evenly divisible by 8 to ensure the
3862 address is 64 bit aligned. */
3863 if (offset1 % 8 != 0)
3866 /* The offset for the second addr must be 4 more than the first addr. */
3867 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
3870 /* All the tests passed. addr1 and addr2 are valid for ldd and std
3875 /* Return 1 if reg is a pseudo, or is the first register in
3876 a hard register pair. This makes it a candidate for use in
3877 ldd and std insns. */
3880 register_ok_for_ldd (reg)
3883 /* We might have been passed a SUBREG. */
3884 if (GET_CODE (reg) != REG)
3887 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
3888 return (REGNO (reg) % 2 == 0);
3893 /* Print operand X (an rtx) in assembler syntax to file FILE.
3894 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3895 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3898 print_operand (file, x, code)
3906 /* Output a 'nop' if there's nothing for the delay slot. */
3907 if (dbr_sequence_length () == 0)
3908 fputs ("\n\tnop", file);
3911 /* Output an annul flag if there's nothing for the delay slot and we
3912 are optimizing. This is always used with '(' below. */
3913 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
3914 this is a dbx bug. So, we only do this when optimizing. */
3915 if (dbr_sequence_length () == 0 && optimize)
3919 /* Output a 'nop' if there's nothing for the delay slot and we are
3920 not optimizing. This is always used with '*' above. */
3921 if (dbr_sequence_length () == 0 && ! optimize)
3922 fputs ("\n\tnop", file);
3925 /* Output the Medium/Anywhere code model base register. */
3926 fputs (MEDANY_BASE_REG, file);
3929 /* Print out what we are using as the frame pointer. This might
3930 be %fp, or might be %sp+offset. */
3931 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
3932 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
3935 /* Adjust the operand to take into account a RESTORE operation. */
3936 if (GET_CODE (x) != REG)
3937 output_operand_lossage ("Invalid %%Y operand");
3938 else if (REGNO (x) < 8)
3939 fputs (reg_names[REGNO (x)], file);
3940 else if (REGNO (x) >= 24 && REGNO (x) < 32)
3941 fputs (reg_names[REGNO (x)-16], file);
3943 output_operand_lossage ("Invalid %%Y operand");
3946 /* Print out the low order register name of a register pair. */
3947 if (WORDS_BIG_ENDIAN)
3948 fputs (reg_names[REGNO (x)+1], file);
3950 fputs (reg_names[REGNO (x)], file);
3953 /* Print out the high order register name of a register pair. */
3954 if (WORDS_BIG_ENDIAN)
3955 fputs (reg_names[REGNO (x)], file);
3957 fputs (reg_names[REGNO (x)+1], file);
3960 /* Print out the second register name of a register pair or quad.
3961 I.e., R (%o0) => %o1. */
3962 fputs (reg_names[REGNO (x)+1], file);
3965 /* Print out the third register name of a register quad.
3966 I.e., S (%o0) => %o2. */
3967 fputs (reg_names[REGNO (x)+2], file);
3970 /* Print out the fourth register name of a register quad.
3971 I.e., T (%o0) => %o3. */
3972 fputs (reg_names[REGNO (x)+3], file);
3975 /* Print a condition code register. */
3976 if (REGNO (x) == SPARC_ICC_REG)
3978 /* We don't handle CC[X]_NOOVmode because they're not supposed
3980 if (GET_MODE (x) == CCmode)
3981 fputs ("%icc", file);
3982 else if (GET_MODE (x) == CCXmode)
3983 fputs ("%xcc", file);
3988 /* %fccN register */
3989 fputs (reg_names[REGNO (x)], file);
3992 /* Print the operand's address only. */
3993 output_address (XEXP (x, 0));
3996 /* In this case we need a register. Use %g0 if the
3997 operand is const0_rtx. */
3999 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
4001 fputs ("%g0", file);
4008 switch (GET_CODE (x))
4010 case IOR: fputs ("or", file); break;
4011 case AND: fputs ("and", file); break;
4012 case XOR: fputs ("xor", file); break;
4013 default: output_operand_lossage ("Invalid %%A operand");
4018 switch (GET_CODE (x))
4020 case IOR: fputs ("orn", file); break;
4021 case AND: fputs ("andn", file); break;
4022 case XOR: fputs ("xnor", file); break;
4023 default: output_operand_lossage ("Invalid %%B operand");
4027 /* These are used by the conditional move instructions. */
4031 enum rtx_code rc = (code == 'c'
4032 ? reverse_condition (GET_CODE (x))
4036 case NE: fputs ("ne", file); break;
4037 case EQ: fputs ("e", file); break;
4038 case GE: fputs ("ge", file); break;
4039 case GT: fputs ("g", file); break;
4040 case LE: fputs ("le", file); break;
4041 case LT: fputs ("l", file); break;
4042 case GEU: fputs ("geu", file); break;
4043 case GTU: fputs ("gu", file); break;
4044 case LEU: fputs ("leu", file); break;
4045 case LTU: fputs ("lu", file); break;
4046 default: output_operand_lossage (code == 'c'
4047 ? "Invalid %%c operand"
4048 : "Invalid %%C operand");
4053 /* These are used by the movr instruction pattern. */
4057 enum rtx_code rc = (code == 'd'
4058 ? reverse_condition (GET_CODE (x))
4062 case NE: fputs ("ne", file); break;
4063 case EQ: fputs ("e", file); break;
4064 case GE: fputs ("gez", file); break;
4065 case LT: fputs ("lz", file); break;
4066 case LE: fputs ("lez", file); break;
4067 case GT: fputs ("gz", file); break;
4068 default: output_operand_lossage (code == 'd'
4069 ? "Invalid %%d operand"
4070 : "Invalid %%D operand");
4077 /* Print a sign-extended character. */
4078 int i = INTVAL (x) & 0xff;
4081 fprintf (file, "%d", i);
4086 /* Operand must be a MEM; write its address. */
4087 if (GET_CODE (x) != MEM)
4088 output_operand_lossage ("Invalid %%f operand");
4089 output_address (XEXP (x, 0));
4093 /* Do nothing special. */
4097 /* Undocumented flag. */
4098 output_operand_lossage ("invalid operand output code");
4101 if (GET_CODE (x) == REG)
4102 fputs (reg_names[REGNO (x)], file);
4103 else if (GET_CODE (x) == MEM)
4106 /* Poor Sun assembler doesn't understand absolute addressing. */
4107 if (CONSTANT_P (XEXP (x, 0))
4108 && ! TARGET_LIVE_G0)
4109 fputs ("%g0+", file);
4110 output_address (XEXP (x, 0));
4113 else if (GET_CODE (x) == HIGH)
4115 fputs ("%hi(", file);
4116 output_addr_const (file, XEXP (x, 0));
4119 else if (GET_CODE (x) == LO_SUM)
4121 print_operand (file, XEXP (x, 0), 0);
4122 fputs ("+%lo(", file);
4123 output_addr_const (file, XEXP (x, 1));
4126 else if (GET_CODE (x) == CONST_DOUBLE
4127 && (GET_MODE (x) == VOIDmode
4128 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
4130 if (CONST_DOUBLE_HIGH (x) == 0)
4131 fprintf (file, "%u", CONST_DOUBLE_LOW (x));
4132 else if (CONST_DOUBLE_HIGH (x) == -1
4133 && CONST_DOUBLE_LOW (x) < 0)
4134 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
4136 output_operand_lossage ("long long constant not a valid immediate operand");
4138 else if (GET_CODE (x) == CONST_DOUBLE)
4139 output_operand_lossage ("floating point constant not a valid immediate operand");
4140 else { output_addr_const (file, x); }
4143 /* This function outputs assembler code for VALUE to FILE, where VALUE is
4144 a 64 bit (DImode) value. */
4146 /* ??? If there is a 64 bit counterpart to .word that the assembler
4147 understands, then using that would simply this code greatly. */
4148 /* ??? We only output .xword's for symbols and only then in environments
4149 where the assembler can handle them. */
4152 output_double_int (file, value)
4156 if (GET_CODE (value) == CONST_INT)
4158 if (INTVAL (value) < 0)
4159 ASM_OUTPUT_INT (file, constm1_rtx);
4161 ASM_OUTPUT_INT (file, const0_rtx);
4162 ASM_OUTPUT_INT (file, value);
4164 else if (GET_CODE (value) == CONST_DOUBLE)
4166 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode,
4167 CONST_DOUBLE_HIGH (value)));
4168 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode,
4169 CONST_DOUBLE_LOW (value)));
4171 else if (GET_CODE (value) == SYMBOL_REF
4172 || GET_CODE (value) == CONST
4173 || GET_CODE (value) == PLUS
4174 || (TARGET_ARCH64 &&
4175 (GET_CODE (value) == LABEL_REF
4176 || GET_CODE (value) == CODE_LABEL
4177 || GET_CODE (value) == MINUS)))
4179 if (!TARGET_V9 || TARGET_MEDLOW)
4181 ASM_OUTPUT_INT (file, const0_rtx);
4182 ASM_OUTPUT_INT (file, value);
4186 fprintf (file, "\t%s\t", ASM_LONGLONG);
4187 output_addr_const (file, value);
4188 fprintf (file, "\n");
4195 /* Return the value of a code used in the .proc pseudo-op that says
4196 what kind of result this function returns. For non-C types, we pick
4197 the closest C type. */
4199 #ifndef CHAR_TYPE_SIZE
4200 #define CHAR_TYPE_SIZE BITS_PER_UNIT
4203 #ifndef SHORT_TYPE_SIZE
4204 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
4207 #ifndef INT_TYPE_SIZE
4208 #define INT_TYPE_SIZE BITS_PER_WORD
4211 #ifndef LONG_TYPE_SIZE
4212 #define LONG_TYPE_SIZE BITS_PER_WORD
4215 #ifndef LONG_LONG_TYPE_SIZE
4216 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
4219 #ifndef FLOAT_TYPE_SIZE
4220 #define FLOAT_TYPE_SIZE BITS_PER_WORD
4223 #ifndef DOUBLE_TYPE_SIZE
4224 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
4227 #ifndef LONG_DOUBLE_TYPE_SIZE
4228 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
4232 sparc_type_code (type)
4235 register unsigned long qualifiers = 0;
4236 register unsigned shift = 6;
4238 /* Only the first 30 bits of the qualifier are valid. We must refrain from
4239 setting more, since some assemblers will give an error for this. Also,
4240 we must be careful to avoid shifts of 32 bits or more to avoid getting
4241 unpredictable results. */
4245 switch (TREE_CODE (type))
4252 qualifiers |= (3 << shift);
4254 type = TREE_TYPE (type);
4260 qualifiers |= (2 << shift);
4262 type = TREE_TYPE (type);
4266 case REFERENCE_TYPE:
4269 qualifiers |= (1 << shift);
4271 type = TREE_TYPE (type);
4275 return (qualifiers | 8);
4278 case QUAL_UNION_TYPE:
4279 return (qualifiers | 9);
4282 return (qualifiers | 10);
4285 return (qualifiers | 16);
4288 /* If this is a range type, consider it to be the underlying
4290 if (TREE_TYPE (type) != 0)
4292 type = TREE_TYPE (type);
4296 /* Carefully distinguish all the standard types of C,
4297 without messing up if the language is not C. We do this by
4298 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
4299 look at both the names and the above fields, but that's redundant.
4300 Any type whose size is between two C types will be considered
4301 to be the wider of the two types. Also, we do not have a
4302 special code to use for "long long", so anything wider than
4303 long is treated the same. Note that we can't distinguish
4304 between "int" and "long" in this code if they are the same
4305 size, but that's fine, since neither can the assembler. */
4307 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
4308 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
4310 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
4311 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
4313 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
4314 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
4317 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
4320 /* Carefully distinguish all the standard types of C,
4321 without messing up if the language is not C. */
4323 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
4324 return (qualifiers | 6);
4327 return (qualifiers | 7);
4329 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
4330 /* ??? We need to distinguish between double and float complex types,
4331 but I don't know how yet because I can't reach this code from
4332 existing front-ends. */
4333 return (qualifiers | 7); /* Who knows? */
4335 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
4336 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
4337 case FILE_TYPE: /* GNU Pascal FILE type. */
4338 case SET_TYPE: /* GNU Pascal SET type. */
4339 case LANG_TYPE: /* ? */
4343 abort (); /* Not a type! */
4348 /* Nested function support. */
4350 /* Emit RTL insns to initialize the variable parts of a trampoline.
4351 FNADDR is an RTX for the address of the function's pure code.
4352 CXT is an RTX for the static chain value for the function.
4354 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
4355 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
4356 (to store insns). This is a bit excessive. Perhaps a different
4357 mechanism would be better here.
4359 Emit enough FLUSH insns to synchronize the data and instruction caches. */
4362 sparc_initialize_trampoline (tramp, fnaddr, cxt)
4363 rtx tramp, fnaddr, cxt;
4365 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt,
4366 size_int (10), 0, 1);
4367 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, fnaddr,
4368 size_int (10), 0, 1);
4369 rtx low_cxt = expand_and (cxt, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0);
4370 rtx low_fn = expand_and (fnaddr, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0);
4371 rtx g1_sethi = gen_rtx (HIGH, SImode,
4372 gen_rtx (CONST_INT, VOIDmode, 0x03000000));
4373 rtx g2_sethi = gen_rtx (HIGH, SImode,
4374 gen_rtx (CONST_INT, VOIDmode, 0x05000000));
4375 rtx g1_ori = gen_rtx (HIGH, SImode,
4376 gen_rtx (CONST_INT, VOIDmode, 0x82106000));
4377 rtx g2_ori = gen_rtx (HIGH, SImode,
4378 gen_rtx (CONST_INT, VOIDmode, 0x8410A000));
4379 rtx tem = gen_reg_rtx (SImode);
4380 emit_move_insn (tem, g1_sethi);
4381 emit_insn (gen_iorsi3 (high_fn, high_fn, tem));
4382 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 0)), high_fn);
4383 emit_move_insn (tem, g1_ori);
4384 emit_insn (gen_iorsi3 (low_fn, low_fn, tem));
4385 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 4)), low_fn);
4386 emit_move_insn (tem, g2_sethi);
4387 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem));
4388 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 8)), high_cxt);
4389 emit_move_insn (tem, g2_ori);
4390 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem));
4391 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 16)), low_cxt);
4392 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode, tramp))));
4393 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode,
4394 plus_constant (tramp, 8)))));
4395 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode,
4396 plus_constant (tramp, 16)))));
4399 /* The 64 bit version is simpler because it makes more sense to load the
4400 values as "immediate" data out of the trampoline. It's also easier since
4401 we can read the PC without clobbering a register. */
4404 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
4405 rtx tramp, fnaddr, cxt;
4407 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (tramp, 24)), cxt);
4408 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (tramp, 32)), fnaddr);
4409 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode, tramp))));
4410 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode,
4411 plus_constant (tramp, 8)))));
4412 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode,
4413 plus_constant (tramp, 16)))));
4414 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode,
4415 plus_constant (tramp, 24)))));
4416 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode,
4417 plus_constant (tramp, 32)))));
4420 /* Subroutines to support a flat (single) register window calling
4423 /* Single-register window sparc stack frames look like:
4425 Before call After call
4426 +-----------------------+ +-----------------------+
4428 mem | caller's temps. | | caller's temps. |
4430 +-----------------------+ +-----------------------+
4432 | arguments on stack. | | arguments on stack. |
4434 +-----------------------+FP+92->+-----------------------+
4435 | 6 words to save | | 6 words to save |
4436 | arguments passed | | arguments passed |
4437 | in registers, even | | in registers, even |
4438 | if not passed. | | if not passed. |
4439 SP+68->+-----------------------+FP+68->+-----------------------+
4440 | 1 word struct addr | | 1 word struct addr |
4441 +-----------------------+FP+64->+-----------------------+
4443 | 16 word reg save area | | 16 word reg save area |
4445 SP->+-----------------------+ FP->+-----------------------+
4447 | fp/alu reg moves |
4448 FP-16->+-----------------------+
4452 +-----------------------+
4454 | fp register save |
4456 +-----------------------+
4458 | gp register save |
4460 +-----------------------+
4462 | alloca allocations |
4464 +-----------------------+
4466 | arguments on stack |
4468 SP+92->+-----------------------+
4470 | arguments passed |
4471 | in registers, even |
4472 low | if not passed. |
4473 memory SP+68->+-----------------------+
4474 | 1 word struct addr |
4475 SP+64->+-----------------------+
4477 I 16 word reg save area |
4479 SP->+-----------------------+ */
4481 /* Structure to be filled in by sparc_flat_compute_frame_size with register
4482 save masks, and offsets for the current function. */
4484 struct sparc_frame_info
4486 unsigned long total_size; /* # bytes that the entire frame takes up. */
4487 unsigned long var_size; /* # bytes that variables take up. */
4488 unsigned long args_size; /* # bytes that outgoing arguments take up. */
4489 unsigned long extra_size; /* # bytes of extra gunk. */
4490 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
4491 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
4492 unsigned long gmask; /* Mask of saved gp registers. */
4493 unsigned long fmask; /* Mask of saved fp registers. */
4494 unsigned long reg_offset; /* Offset from new sp to store regs. */
4495 int initialized; /* Nonzero if frame size already calculated. */
4498 /* Current frame information calculated by sparc_flat_compute_frame_size. */
4499 struct sparc_frame_info current_frame_info;
4501 /* Zero structure to initialize current_frame_info. */
4502 struct sparc_frame_info zero_frame_info;
4504 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
4506 #define RETURN_ADDR_REGNUM 15
4507 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
4508 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
4510 #define MUST_SAVE_REGISTER(regno) \
4511 ((regs_ever_live[regno] && !call_used_regs[regno]) \
4512 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
4513 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
4515 /* Return the bytes needed to compute the frame pointer from the current
4519 sparc_flat_compute_frame_size (size)
4520 int size; /* # of var. bytes allocated. */
4523 unsigned long total_size; /* # bytes that the entire frame takes up. */
4524 unsigned long var_size; /* # bytes that variables take up. */
4525 unsigned long args_size; /* # bytes that outgoing arguments take up. */
4526 unsigned long extra_size; /* # extra bytes. */
4527 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
4528 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
4529 unsigned long gmask; /* Mask of saved gp registers. */
4530 unsigned long fmask; /* Mask of saved fp registers. */
4531 unsigned long reg_offset; /* Offset to register save area. */
4532 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
4534 /* This is the size of the 16 word reg save area, 1 word struct addr
4535 area, and 4 word fp/alu register copy area. */
4536 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
4538 /* Also include the size needed for the 6 parameter registers. */
4539 args_size = current_function_outgoing_args_size + 24;
4540 total_size = var_size + args_size + extra_size;
4548 /* Calculate space needed for gp registers. */
4549 for (regno = 1; regno <= 31; regno++)
4551 if (MUST_SAVE_REGISTER (regno))
4553 /* If we need to save two regs in a row, ensure there's room to bump
4554 up the address to align it to a doubleword boundary. */
4555 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
4557 if (gp_reg_size % 8 != 0)
4559 gp_reg_size += 2 * UNITS_PER_WORD;
4560 gmask |= 3 << regno;
4566 gp_reg_size += UNITS_PER_WORD;
4567 gmask |= 1 << regno;
4572 /* Calculate space needed for fp registers. */
4573 for (regno = 32; regno <= 63; regno++)
4575 if (regs_ever_live[regno] && !call_used_regs[regno])
4577 fp_reg_size += UNITS_PER_WORD;
4578 fmask |= 1 << (regno - 32);
4585 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
4586 /* Ensure save area is 8 byte aligned if we need it. */
4588 if (need_aligned_p && n != 0)
4590 total_size += 8 - n;
4591 reg_offset += 8 - n;
4593 total_size += gp_reg_size + fp_reg_size;
4596 /* ??? This looks a little suspicious. Clarify. */
4597 if (total_size == extra_size)
4598 total_size = extra_size = 0;
4600 total_size = SPARC_STACK_ALIGN (total_size);
4602 /* Save other computed information. */
4603 current_frame_info.total_size = total_size;
4604 current_frame_info.var_size = var_size;
4605 current_frame_info.args_size = args_size;
4606 current_frame_info.extra_size = extra_size;
4607 current_frame_info.gp_reg_size = gp_reg_size;
4608 current_frame_info.fp_reg_size = fp_reg_size;
4609 current_frame_info.gmask = gmask;
4610 current_frame_info.fmask = fmask;
4611 current_frame_info.reg_offset = reg_offset;
4612 current_frame_info.initialized = reload_completed;
4614 /* Ok, we're done. */
4618 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
4621 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
4622 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
4623 [BASE_REG+OFFSET] will always be a valid address.
4625 WORD_OP is either "st" for save, "ld" for restore.
4626 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
4629 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, doubleword_op)
4632 unsigned int offset;
4633 unsigned long gmask;
4634 unsigned long fmask;
4636 char *doubleword_op;
4640 if (gmask == 0 && fmask == 0)
4643 /* Save registers starting from high to low. We've already saved the
4644 previous frame pointer and previous return address for the debugger's
4645 sake. The debugger allows us to not need a nop in the epilog if at least
4646 one register is reloaded in addition to return address. */
4650 for (regno = 1; regno <= 31; regno++)
4652 if ((gmask & (1L << regno)) != 0)
4654 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
4656 /* We can save two registers in a row. If we're not at a
4657 double word boundary, move to one.
4658 sparc_flat_compute_frame_size ensures there's room to do
4660 if (offset % 8 != 0)
4661 offset += UNITS_PER_WORD;
4663 if (word_op[0] == 's')
4664 fprintf (file, "\t%s %s,[%s+%d]\n",
4665 doubleword_op, reg_names[regno],
4668 fprintf (file, "\t%s [%s+%d],%s\n",
4669 doubleword_op, base_reg, offset,
4672 offset += 2 * UNITS_PER_WORD;
4677 if (word_op[0] == 's')
4678 fprintf (file, "\t%s %s,[%s+%d]\n",
4679 word_op, reg_names[regno],
4682 fprintf (file, "\t%s [%s+%d],%s\n",
4683 word_op, base_reg, offset, reg_names[regno]);
4685 offset += UNITS_PER_WORD;
4693 for (regno = 32; regno <= 63; regno++)
4695 if ((fmask & (1L << (regno - 32))) != 0)
4697 if (word_op[0] == 's')
4698 fprintf (file, "\t%s %s,[%s+%d]\n",
4699 word_op, reg_names[regno],
4702 fprintf (file, "\t%s [%s+%d],%s\n",
4703 word_op, base_reg, offset, reg_names[regno]);
4705 offset += UNITS_PER_WORD;
4711 /* Set up the stack and frame (if desired) for the function. */
4714 sparc_flat_output_function_prologue (file, size)
4718 char *sp_str = reg_names[STACK_POINTER_REGNUM];
4719 unsigned long gmask = current_frame_info.gmask;
4721 /* This is only for the human reader. */
4722 fprintf (file, "\t!#PROLOGUE# 0\n");
4723 fprintf (file, "\t!# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
4724 current_frame_info.var_size,
4725 current_frame_info.gp_reg_size / 4,
4726 current_frame_info.fp_reg_size / 4,
4727 current_function_outgoing_args_size,
4728 current_frame_info.extra_size);
4730 size = SPARC_STACK_ALIGN (size);
4731 size = (! current_frame_info.initialized
4732 ? sparc_flat_compute_frame_size (size)
4733 : current_frame_info.total_size);
4735 /* These cases shouldn't happen. Catch them now. */
4736 if (size == 0 && (gmask || current_frame_info.fmask))
4739 /* Allocate our stack frame by decrementing %sp.
4740 At present, the only algorithm gdb can use to determine if this is a
4741 flat frame is if we always set %i7 if we set %sp. This can be optimized
4742 in the future by putting in some sort of debugging information that says
4743 this is a `flat' function. However, there is still the case of debugging
4744 code without such debugging information (including cases where most fns
4745 have such info, but there is one that doesn't). So, always do this now
4746 so we don't get a lot of code out there that gdb can't handle.
4747 If the frame pointer isn't needn't then that's ok - gdb won't be able to
4748 distinguish us from a non-flat function but there won't (and shouldn't)
4749 be any differences anyway. The return pc is saved (if necessary) right
4750 after %i7 so gdb won't have to look too far to find it. */
4753 unsigned int reg_offset = current_frame_info.reg_offset;
4754 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
4755 char *t1_str = "%g1";
4757 /* Things get a little tricky if local variables take up more than ~4096
4758 bytes and outgoing arguments take up more than ~4096 bytes. When that
4759 happens, the register save area can't be accessed from either end of
4760 the frame. Handle this by decrementing %sp to the start of the gp
4761 register save area, save the regs, update %i7, and then set %sp to its
4762 final value. Given that we only have one scratch register to play
4763 with it is the cheapest solution, and it helps gdb out as it won't
4764 slow down recognition of flat functions.
4765 Don't change the order of insns emitted here without checking with
4766 the gdb folk first. */
4768 /* Is the entire register save area offsettable from %sp? */
4769 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
4773 fprintf (file, "\tadd %s,%d,%s\n",
4774 sp_str, -size, sp_str);
4775 if (gmask & FRAME_POINTER_MASK)
4777 fprintf (file, "\tst %s,[%s+%d]\n",
4778 fp_str, sp_str, reg_offset);
4779 fprintf (file, "\tsub %s,%d,%s\t!# set up frame pointer\n",
4780 sp_str, -size, fp_str);
4786 fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n",
4787 size, t1_str, sp_str, t1_str, sp_str);
4788 if (gmask & FRAME_POINTER_MASK)
4790 fprintf (file, "\tst %s,[%s+%d]\n",
4791 fp_str, sp_str, reg_offset);
4792 fprintf (file, "\tadd %s,%s,%s\t!# set up frame pointer\n",
4793 sp_str, t1_str, fp_str);
4797 if (gmask & RETURN_ADDR_MASK)
4799 fprintf (file, "\tst %s,[%s+%d]\n",
4800 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
4803 sparc_flat_save_restore (file, sp_str, reg_offset,
4804 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
4805 current_frame_info.fmask,
4810 /* Subtract %sp in two steps, but make sure there is always a
4811 64 byte register save area, and %sp is properly aligned. */
4812 /* Amount to decrement %sp by, the first time. */
4813 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
4814 /* Offset to register save area from %sp. */
4815 unsigned int offset = size1 - (size - reg_offset);
4819 fprintf (file, "\tadd %s,%d,%s\n",
4820 sp_str, -size1, sp_str);
4821 if (gmask & FRAME_POINTER_MASK)
4823 fprintf (file, "\tst %s,[%s+%d]\n\tsub %s,%d,%s\t!# set up frame pointer\n",
4824 fp_str, sp_str, offset, sp_str, -size1, fp_str);
4830 fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n",
4831 size1, t1_str, sp_str, t1_str, sp_str);
4832 if (gmask & FRAME_POINTER_MASK)
4834 fprintf (file, "\tst %s,[%s+%d]\n\tadd %s,%s,%s\t!# set up frame pointer\n",
4835 fp_str, sp_str, offset, sp_str, t1_str, fp_str);
4839 if (gmask & RETURN_ADDR_MASK)
4841 fprintf (file, "\tst %s,[%s+%d]\n",
4842 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
4845 sparc_flat_save_restore (file, sp_str, offset,
4846 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
4847 current_frame_info.fmask,
4849 fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n",
4850 size - size1, t1_str, sp_str, t1_str, sp_str);
4854 fprintf (file, "\t!#PROLOGUE# 1\n");
4857 /* Do any necessary cleanup after a function to restore stack, frame,
4861 sparc_flat_output_function_epilogue (file, size)
4865 rtx epilogue_delay = current_function_epilogue_delay_list;
4866 int noepilogue = FALSE;
4868 /* This is only for the human reader. */
4869 fprintf (file, "\t!#EPILOGUE#\n");
4871 /* The epilogue does not depend on any registers, but the stack
4872 registers, so we assume that if we have 1 pending nop, it can be
4873 ignored, and 2 it must be filled (2 nops occur for integer
4874 multiply and divide). */
4876 size = SPARC_STACK_ALIGN (size);
4877 size = (!current_frame_info.initialized
4878 ? sparc_flat_compute_frame_size (size)
4879 : current_frame_info.total_size);
4881 if (size == 0 && epilogue_delay == 0)
4883 rtx insn = get_last_insn ();
4885 /* If the last insn was a BARRIER, we don't have to write any code
4886 because a jump (aka return) was put there. */
4887 if (GET_CODE (insn) == NOTE)
4888 insn = prev_nonnote_insn (insn);
4889 if (insn && GET_CODE (insn) == BARRIER)
4895 unsigned int reg_offset = current_frame_info.reg_offset;
4897 char *sp_str = reg_names[STACK_POINTER_REGNUM];
4898 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
4899 char *t1_str = "%g1";
4901 /* In the reload sequence, we don't need to fill the load delay
4902 slots for most of the loads, also see if we can fill the final
4903 delay slot if not otherwise filled by the reload sequence. */
4906 fprintf (file, "\tset %d,%s\n", size, t1_str);
4908 if (frame_pointer_needed)
4911 fprintf (file,"\tsub %s,%s,%s\t\t!# sp not trusted here\n",
4912 fp_str, t1_str, sp_str);
4914 fprintf (file,"\tsub %s,%d,%s\t\t!# sp not trusted here\n",
4915 fp_str, size, sp_str);
4918 /* Is the entire register save area offsettable from %sp? */
4919 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
4925 /* Restore %sp in two steps, but make sure there is always a
4926 64 byte register save area, and %sp is properly aligned. */
4927 /* Amount to increment %sp by, the first time. */
4928 size1 = ((reg_offset - 64 - 16) + 15) & -16;
4929 /* Offset to register save area from %sp. */
4930 reg_offset = size1 - reg_offset;
4932 fprintf (file, "\tset %d,%s\n\tadd %s,%s,%s\n",
4933 size1, t1_str, sp_str, t1_str, sp_str);
4936 /* We must restore the frame pointer and return address reg first
4937 because they are treated specially by the prologue output code. */
4938 if (current_frame_info.gmask & FRAME_POINTER_MASK)
4940 fprintf (file, "\tld [%s+%d],%s\n",
4941 sp_str, reg_offset, fp_str);
4944 if (current_frame_info.gmask & RETURN_ADDR_MASK)
4946 fprintf (file, "\tld [%s+%d],%s\n",
4947 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
4951 /* Restore any remaining saved registers. */
4952 sparc_flat_save_restore (file, sp_str, reg_offset,
4953 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
4954 current_frame_info.fmask,
4957 /* If we had to increment %sp in two steps, record it so the second
4958 restoration in the epilogue finishes up. */
4963 fprintf (file, "\tset %d,%s\n",
4967 if (current_function_returns_struct)
4968 fprintf (file, "\tjmp %%o7+12\n");
4970 fprintf (file, "\tretl\n");
4972 /* If the only register saved is the return address, we need a
4973 nop, unless we have an instruction to put into it. Otherwise
4974 we don't since reloading multiple registers doesn't reference
4975 the register being loaded. */
4981 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
4984 else if (size > 4095)
4985 fprintf (file, "\tadd %s,%s,%s\n", sp_str, t1_str, sp_str);
4988 fprintf (file, "\tadd %s,%d,%s\n", sp_str, size, sp_str);
4991 fprintf (file, "\tnop\n");
4994 /* Reset state info for each function. */
4995 current_frame_info = zero_frame_info;
4998 /* Define the number of delay slots needed for the function epilogue.
5000 On the sparc, we need a slot if either no stack has been allocated,
5001 or the only register saved is the return register. */
5004 sparc_flat_epilogue_delay_slots ()
5006 if (!current_frame_info.initialized)
5007 (void) sparc_flat_compute_frame_size (get_frame_size ());
5009 if (current_frame_info.total_size == 0)
5015 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
5016 Any single length instruction which doesn't reference the stack or frame
5020 sparc_flat_eligible_for_epilogue_delay (trial, slot)
5024 rtx pat = PATTERN (trial);
5026 if (get_attr_length (trial) != 1)
5029 /* If %g0 is live, there are lots of things we can't handle.
5030 Rather than trying to find them all now, let's punt and only
5031 optimize things as necessary. */
5035 if (! reg_mentioned_p (stack_pointer_rtx, pat)
5036 && ! reg_mentioned_p (frame_pointer_rtx, pat))
5042 /* Adjust the cost of a scheduling dependency. Return the new cost of
5043 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5046 supersparc_adjust_cost (insn, link, dep_insn, cost)
5052 enum attr_type insn_type;
5054 if (! recog_memoized (insn))
5057 insn_type = get_attr_type (insn);
5059 if (REG_NOTE_KIND (link) == 0)
5061 /* Data dependency; DEP_INSN writes a register that INSN reads some
5064 /* if a load, then the dependence must be on the memory address;
5065 add an extra 'cycle'. Note that the cost could be two cycles
5066 if the reg was written late in an instruction group; we can't tell
5068 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
5071 /* Get the delay only if the address of the store is the dependence. */
5072 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
5074 rtx pat = PATTERN(insn);
5075 rtx dep_pat = PATTERN (dep_insn);
5077 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
5078 return cost; /* This shouldn't happen! */
5080 /* The dependency between the two instructions was on the data that
5081 is being stored. Assume that this implies that the address of the
5082 store is not dependent. */
5083 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
5086 return cost + 3; /* An approximation. */
5089 /* A shift instruction cannot receive its data from an instruction
5090 in the same cycle; add a one cycle penalty. */
5091 if (insn_type == TYPE_SHIFT)
5092 return cost + 3; /* Split before cascade into shift. */
5096 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
5097 INSN writes some cycles later. */
5099 /* These are only significant for the fpu unit; writing a fp reg before
5100 the fpu has finished with it stalls the processor. */
5102 /* Reusing an integer register causes no problems. */
5103 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)