1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
41 /* 1 if the caller has placed an "unimp" insn immediately after the call.
42 This is used in v8 code when calling a function that returns a structure.
43 v9 doesn't have this. Be careful to have this test be the same as that
46 #define SKIP_CALLERS_UNIMP_P \
47 (!TARGET_ARCH64 && current_function_returns_struct \
48 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
49 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
52 /* Global variables for machine-dependent things. */
54 /* Size of frame. Need to know this to emit return insns from leaf procedures.
55 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
56 reload pass. This is important as the value is later used in insn
57 scheduling (to see what can go in a delay slot).
58 APPARENT_FSIZE is the size of the stack less the register save area and less
59 the outgoing argument area. It is used when saving call preserved regs. */
60 static int apparent_fsize;
61 static int actual_fsize;
63 /* Save the operands last given to a compare for use when we
64 generate a scc or bcc insn. */
66 rtx sparc_compare_op0, sparc_compare_op1;
68 /* We may need an epilogue if we spill too many registers.
69 If this is non-zero, then we branch here for the epilogue. */
70 static rtx leaf_label;
74 /* Vector to say how input registers are mapped to output
75 registers. FRAME_POINTER_REGNUM cannot be remapped by
76 this function to eliminate it. You must use -fomit-frame-pointer
78 char leaf_reg_remap[] =
79 { 0, 1, 2, 3, 4, 5, 6, 7,
80 -1, -1, -1, -1, -1, -1, 14, -1,
81 -1, -1, -1, -1, -1, -1, -1, -1,
82 8, 9, 10, 11, 12, 13, -1, 15,
84 32, 33, 34, 35, 36, 37, 38, 39,
85 40, 41, 42, 43, 44, 45, 46, 47,
86 48, 49, 50, 51, 52, 53, 54, 55,
87 56, 57, 58, 59, 60, 61, 62, 63,
88 64, 65, 66, 67, 68, 69, 70, 71,
89 72, 73, 74, 75, 76, 77, 78, 79,
90 80, 81, 82, 83, 84, 85, 86, 87,
91 88, 89, 90, 91, 92, 93, 94, 95,
96 /* Name of where we pretend to think the frame pointer points.
97 Normally, this is "%fp", but if we are in a leaf procedure,
98 this is "%sp+something". We record "something" separately as it may be
99 too big for reg+constant addressing. */
101 static char *frame_base_name;
102 static int frame_base_offset;
104 static rtx pic_setup_code PROTO((void));
105 static rtx find_addr_reg PROTO((rtx));
106 static void sparc_init_modes PROTO((void));
107 static int save_regs PROTO((FILE *, int, int, char *,
109 static int restore_regs PROTO((FILE *, int, int, char *, int, int));
110 static void build_big_number PROTO((FILE *, int, char *));
111 static int function_arg_slotno PROTO((const CUMULATIVE_ARGS *,
112 enum machine_mode, tree, int, int,
114 static void sparc_output_addr_vec PROTO((rtx));
115 static void sparc_output_addr_diff_vec PROTO((rtx));
116 static void sparc_output_deferred_case_vectors PROTO((void));
119 #ifdef DWARF2_DEBUGGING_INFO
120 extern char *dwarf2out_cfi_label ();
123 /* Option handling. */
125 /* Code model option as passed by user. */
126 char *sparc_cmodel_string;
128 enum cmodel sparc_cmodel;
130 /* Record alignment options as passed by user. */
131 char *sparc_align_loops_string;
132 char *sparc_align_jumps_string;
133 char *sparc_align_funcs_string;
135 /* Parsed values, as a power of two. */
136 int sparc_align_loops;
137 int sparc_align_jumps;
138 int sparc_align_funcs;
140 struct sparc_cpu_select sparc_select[] =
142 /* switch name, tune arch */
143 { (char *)0, "default", 1, 1 },
144 { (char *)0, "-mcpu=", 1, 1 },
145 { (char *)0, "-mtune=", 1, 0 },
149 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
150 enum processor_type sparc_cpu;
152 /* Validate and override various options, and do some machine dependent
156 sparc_override_options ()
158 static struct code_model {
163 { "medlow", CM_MEDLOW },
164 { "medmid", CM_MEDMID },
165 { "medany", CM_MEDANY },
166 { "embmedany", CM_EMBMEDANY },
169 struct code_model *cmodel;
170 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
171 static struct cpu_default {
175 /* There must be one entry here for each TARGET_CPU value. */
176 { TARGET_CPU_sparc, "cypress" },
177 { TARGET_CPU_sparclet, "tsc701" },
178 { TARGET_CPU_sparclite, "f930" },
179 { TARGET_CPU_v8, "v8" },
180 { TARGET_CPU_supersparc, "supersparc" },
181 { TARGET_CPU_v9, "v9" },
182 { TARGET_CPU_ultrasparc, "ultrasparc" },
185 struct cpu_default *def;
186 /* Table of values for -m{cpu,tune}=. */
187 static struct cpu_table {
189 enum processor_type processor;
193 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
194 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
195 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
196 /* TI TMS390Z55 supersparc */
197 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
198 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
199 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
200 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
201 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
202 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
203 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
205 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
206 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
208 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 },
211 struct cpu_table *cpu;
212 struct sparc_cpu_select *sel;
215 #ifndef SPARC_BI_ARCH
216 /* Check for unsupported architecture size. */
217 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
219 error ("%s is not supported by this configuration",
220 DEFAULT_ARCH32_P ? "-m64" : "-m32");
224 /* Code model selection. */
225 sparc_cmodel = SPARC_DEFAULT_CMODEL;
226 if (sparc_cmodel_string != NULL)
230 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
231 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
233 if (cmodel->name == NULL)
234 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
236 sparc_cmodel = cmodel->value;
239 error ("-mcmodel= is not supported on 32 bit systems");
242 fpu = TARGET_FPU; /* save current -mfpu status */
244 /* Set the default CPU. */
245 for (def = &cpu_default[0]; def->name; ++def)
246 if (def->cpu == TARGET_CPU_DEFAULT)
250 sparc_select[0].string = def->name;
252 for (sel = &sparc_select[0]; sel->name; ++sel)
256 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
257 if (! strcmp (sel->string, cpu->name))
260 sparc_cpu = cpu->processor;
264 target_flags &= ~cpu->disable;
265 target_flags |= cpu->enable;
271 error ("bad value (%s) for %s switch", sel->string, sel->name);
275 /* If -mfpu or -mno-fpu was explicitly used, don't override with
276 the processor default. */
278 target_flags = (target_flags & ~MASK_FPU) | fpu;
280 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
281 if (TARGET_V9 && TARGET_ARCH32)
282 target_flags |= MASK_DEPRECATED_V8_INSNS;
284 /* V8PLUS requires V9 */
286 target_flags &= ~MASK_V8PLUS;
288 /* Don't use stack biasing in 32 bit mode. */
290 target_flags &= ~MASK_STACK_BIAS;
292 /* Validate -malign-loops= value, or provide default. */
293 if (sparc_align_loops_string)
295 sparc_align_loops = exact_log2 (atoi (sparc_align_loops_string));
296 if (sparc_align_loops < 2 || sparc_align_loops > 7)
297 fatal ("-malign-loops=%s is not between 4 and 128 or is not a power of two",
298 sparc_align_loops_string);
302 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
303 its 0. This sounds a bit kludgey. */
304 sparc_align_loops = 0;
307 /* Validate -malign-jumps= value, or provide default. */
308 if (sparc_align_jumps_string)
310 sparc_align_jumps = exact_log2 (atoi (sparc_align_jumps_string));
311 if (sparc_align_jumps < 2 || sparc_align_loops > 7)
312 fatal ("-malign-jumps=%s is not between 4 and 128 or is not a power of two",
313 sparc_align_jumps_string);
317 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
318 its 0. This sounds a bit kludgey. */
319 sparc_align_jumps = 0;
322 /* Validate -malign-functions= value, or provide default. */
323 if (sparc_align_funcs_string)
325 sparc_align_funcs = exact_log2 (atoi (sparc_align_funcs_string));
326 if (sparc_align_funcs < 2 || sparc_align_loops > 7)
327 fatal ("-malign-functions=%s is not between 4 and 128 or is not a power of two",
328 sparc_align_funcs_string);
331 sparc_align_funcs = DEFAULT_SPARC_ALIGN_FUNCS;
333 /* Validate PCC_STRUCT_RETURN. */
334 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
335 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
337 /* Do various machine dependent initializations. */
341 /* Miscellaneous utilities. */
343 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
344 or branch on register contents instructions. */
350 return (code == EQ || code == NE || code == GE || code == LT
351 || code == LE || code == GT);
355 /* Operand constraints. */
357 /* Return non-zero only if OP is a register of mode MODE,
358 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
359 %g0 may contain anything. */
362 reg_or_0_operand (op, mode)
364 enum machine_mode mode;
366 if (register_operand (op, mode))
370 if (op == const0_rtx)
372 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
373 && CONST_DOUBLE_HIGH (op) == 0
374 && CONST_DOUBLE_LOW (op) == 0)
376 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
377 && GET_CODE (op) == CONST_DOUBLE
378 && fp_zero_operand (op))
383 /* Nonzero if OP is a floating point value with value 0.0. */
391 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
392 return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r));
395 /* Nonzero if OP is an integer register. */
398 intreg_operand (op, mode)
400 enum machine_mode mode ATTRIBUTE_UNUSED;
402 return (register_operand (op, SImode)
403 || (TARGET_ARCH64 && register_operand (op, DImode)));
406 /* Nonzero if OP is a floating point condition code register. */
409 fcc_reg_operand (op, mode)
411 enum machine_mode mode;
413 /* This can happen when recog is called from combine. Op may be a MEM.
414 Fail instead of calling abort in this case. */
415 if (GET_CODE (op) != REG)
418 if (mode != VOIDmode && mode != GET_MODE (op))
421 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
424 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
425 if (reg_renumber == 0)
426 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
427 return REGNO_OK_FOR_CCFP_P (REGNO (op));
429 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
433 /* Nonzero if OP is an integer or floating point condition code register. */
436 icc_or_fcc_reg_operand (op, mode)
438 enum machine_mode mode;
440 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
442 if (mode != VOIDmode && mode != GET_MODE (op))
445 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
450 return fcc_reg_operand (op, mode);
453 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
455 restore_operand (op, mode)
457 enum machine_mode mode;
459 return (GET_CODE (op) == REG && GET_MODE (op) == mode
460 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
463 /* Call insn on SPARC can take a PC-relative constant address, or any regular
467 call_operand (op, mode)
469 enum machine_mode mode;
471 if (GET_CODE (op) != MEM)
474 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
478 call_operand_address (op, mode)
480 enum machine_mode mode;
482 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
485 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
486 reference and a constant. */
489 symbolic_operand (op, mode)
491 enum machine_mode mode;
493 switch (GET_CODE (op))
501 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
502 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
503 && GET_CODE (XEXP (op, 1)) == CONST_INT);
505 /* ??? This clause seems to be irrelevant. */
507 return GET_MODE (op) == mode;
514 /* Return truth value of statement that OP is a symbolic memory
515 operand of mode MODE. */
518 symbolic_memory_operand (op, mode)
520 enum machine_mode mode ATTRIBUTE_UNUSED;
522 if (GET_CODE (op) == SUBREG)
523 op = SUBREG_REG (op);
524 if (GET_CODE (op) != MEM)
527 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
528 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
531 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
534 label_ref_operand (op, mode)
536 enum machine_mode mode;
538 if (GET_CODE (op) != LABEL_REF)
540 if (GET_MODE (op) != mode)
545 /* Return 1 if the operand is an argument used in generating pic references
546 in either the medium/low or medium/anywhere code models of sparc64. */
549 sp64_medium_pic_operand (op, mode)
551 enum machine_mode mode ATTRIBUTE_UNUSED;
553 /* Check for (const (minus (symbol_ref:GOT)
554 (const (minus (label) (pc))))). */
555 if (GET_CODE (op) != CONST)
558 if (GET_CODE (op) != MINUS)
560 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
562 /* ??? Ensure symbol is GOT. */
563 if (GET_CODE (XEXP (op, 1)) != CONST)
565 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
570 /* Return 1 if the operand is a data segment reference. This includes
571 the readonly data segment, or in other words anything but the text segment.
572 This is needed in the medium/anywhere code model on v9. These values
573 are accessed with EMBMEDANY_BASE_REG. */
576 data_segment_operand (op, mode)
578 enum machine_mode mode ATTRIBUTE_UNUSED;
580 switch (GET_CODE (op))
583 return ! SYMBOL_REF_FLAG (op);
585 /* Assume canonical format of symbol + constant.
588 return data_segment_operand (XEXP (op, 0));
594 /* Return 1 if the operand is a text segment reference.
595 This is needed in the medium/anywhere code model on v9. */
598 text_segment_operand (op, mode)
600 enum machine_mode mode ATTRIBUTE_UNUSED;
602 switch (GET_CODE (op))
607 return SYMBOL_REF_FLAG (op);
609 /* Assume canonical format of symbol + constant.
612 return text_segment_operand (XEXP (op, 0));
618 /* Return 1 if the operand is either a register or a memory operand that is
622 reg_or_nonsymb_mem_operand (op, mode)
624 enum machine_mode mode;
626 if (register_operand (op, mode))
629 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
636 splittable_symbolic_memory_operand (op, mode)
638 enum machine_mode mode ATTRIBUTE_UNUSED;
640 if (GET_CODE (op) != MEM)
642 if (! symbolic_operand (XEXP (op, 0), Pmode))
648 splittable_immediate_memory_operand (op, mode)
650 enum machine_mode mode ATTRIBUTE_UNUSED;
652 if (GET_CODE (op) != MEM)
654 if (! immediate_operand (XEXP (op, 0), Pmode))
659 /* Return truth value of whether OP is EQ or NE. */
664 enum machine_mode mode ATTRIBUTE_UNUSED;
666 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
669 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
670 or LTU for non-floating-point. We handle those specially. */
673 normal_comp_operator (op, mode)
675 enum machine_mode mode ATTRIBUTE_UNUSED;
677 enum rtx_code code = GET_CODE (op);
679 if (GET_RTX_CLASS (code) != '<')
682 if (GET_MODE (XEXP (op, 0)) == CCFPmode
683 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
686 return (code != NE && code != EQ && code != GEU && code != LTU);
689 /* Return 1 if this is a comparison operator. This allows the use of
690 MATCH_OPERATOR to recognize all the branch insns. */
693 noov_compare_op (op, mode)
695 enum machine_mode mode ATTRIBUTE_UNUSED;
697 enum rtx_code code = GET_CODE (op);
699 if (GET_RTX_CLASS (code) != '<')
702 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
703 /* These are the only branches which work with CC_NOOVmode. */
704 return (code == EQ || code == NE || code == GE || code == LT);
708 /* Nonzero if OP is a comparison operator suitable for use in v9
709 conditional move or branch on register contents instructions. */
712 v9_regcmp_op (op, mode)
714 enum machine_mode mode ATTRIBUTE_UNUSED;
716 enum rtx_code code = GET_CODE (op);
718 if (GET_RTX_CLASS (code) != '<')
721 return v9_regcmp_p (code);
724 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
729 enum machine_mode mode ATTRIBUTE_UNUSED;
731 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
734 /* Return nonzero if OP is an operator of mode MODE which can set
735 the condition codes explicitly. We do not include PLUS and MINUS
736 because these require CC_NOOVmode, which we handle explicitly. */
739 cc_arithop (op, mode)
741 enum machine_mode mode ATTRIBUTE_UNUSED;
743 if (GET_CODE (op) == AND
744 || GET_CODE (op) == IOR
745 || GET_CODE (op) == XOR)
751 /* Return nonzero if OP is an operator of mode MODE which can bitwise
752 complement its second operand and set the condition codes explicitly. */
755 cc_arithopn (op, mode)
757 enum machine_mode mode ATTRIBUTE_UNUSED;
759 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
760 and (xor ... (not ...)) to (not (xor ...)). */
761 return (GET_CODE (op) == AND
762 || GET_CODE (op) == IOR);
765 /* Return true if OP is a register, or is a CONST_INT that can fit in a
766 signed 13 bit immediate field. This is an acceptable SImode operand for
767 most 3 address instructions. */
770 arith_operand (op, mode)
772 enum machine_mode mode;
775 if (register_operand (op, mode)
776 || GET_CODE (op) == CONSTANT_P_RTX)
778 if (GET_CODE (op) != CONST_INT)
780 val = INTVAL (op) & 0xffffffff;
781 return SPARC_SIMM13_P (val);
784 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
785 immediate field of OR and XOR instructions. Used for 64-bit
786 constant formation patterns. */
788 const64_operand (op, mode)
790 enum machine_mode mode;
792 return ((GET_CODE (op) == CONST_INT
793 && SPARC_SIMM13_P (INTVAL (op)))
794 #if HOST_BITS_PER_WIDE_INT != 64
795 || (GET_CODE (op) == CONST_DOUBLE
796 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
797 && (CONST_DOUBLE_HIGH (op) ==
798 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
801 || GET_CODE (op) == CONSTANT_P_RTX);
804 /* The same, but only for sethi instructions. */
806 const64_high_operand (op, mode)
808 enum machine_mode mode;
810 return ((GET_CODE (op) == CONST_INT
811 && (INTVAL (op) & 0xfffffc00) != 0
812 && SPARC_SETHI_P (INTVAL (op))
813 #if HOST_BITS_PER_WIDE_INT != 64
814 /* Must be positive on non-64bit host else the
815 optimizer is fooled into thinking that sethi
816 sign extends, even though it does not. */
820 || (GET_CODE (op) == CONST_DOUBLE
821 && CONST_DOUBLE_HIGH (op) == 0
822 && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
823 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
824 || GET_CODE (op) == CONSTANT_P_RTX);
827 /* Return true if OP is a register, or is a CONST_INT that can fit in a
828 signed 11 bit immediate field. This is an acceptable SImode operand for
829 the movcc instructions. */
832 arith11_operand (op, mode)
834 enum machine_mode mode;
836 return (register_operand (op, mode)
837 || GET_CODE (op) == CONSTANT_P_RTX
838 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
841 /* Return true if OP is a register, or is a CONST_INT that can fit in a
842 signed 10 bit immediate field. This is an acceptable SImode operand for
843 the movrcc instructions. */
846 arith10_operand (op, mode)
848 enum machine_mode mode;
850 return (register_operand (op, mode)
851 || GET_CODE (op) == CONSTANT_P_RTX
852 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
855 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
856 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
858 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
859 can fit in a 13 bit immediate field. This is an acceptable DImode operand
860 for most 3 address instructions. */
863 arith_double_operand (op, mode)
865 enum machine_mode mode;
867 return (register_operand (op, mode)
868 || GET_CODE (op) == CONSTANT_P_RTX
869 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
871 && GET_CODE (op) == CONST_DOUBLE
872 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
873 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
875 && GET_CODE (op) == CONST_DOUBLE
876 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
877 && ((CONST_DOUBLE_HIGH (op) == -1
878 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
879 || (CONST_DOUBLE_HIGH (op) == 0
880 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
883 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
884 can fit in an 11 bit immediate field. This is an acceptable DImode
885 operand for the movcc instructions. */
886 /* ??? Replace with arith11_operand? */
889 arith11_double_operand (op, mode)
891 enum machine_mode mode;
893 return (register_operand (op, mode)
894 || GET_CODE (op) == CONSTANT_P_RTX
895 || (GET_CODE (op) == CONST_DOUBLE
896 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
897 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
898 && ((CONST_DOUBLE_HIGH (op) == -1
899 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
900 || (CONST_DOUBLE_HIGH (op) == 0
901 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
902 || (GET_CODE (op) == CONST_INT
903 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
904 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
907 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
908 can fit in an 10 bit immediate field. This is an acceptable DImode
909 operand for the movrcc instructions. */
910 /* ??? Replace with arith10_operand? */
913 arith10_double_operand (op, mode)
915 enum machine_mode mode;
917 return (register_operand (op, mode)
918 || GET_CODE (op) == CONSTANT_P_RTX
919 || (GET_CODE (op) == CONST_DOUBLE
920 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
921 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
922 && ((CONST_DOUBLE_HIGH (op) == -1
923 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
924 || (CONST_DOUBLE_HIGH (op) == 0
925 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
926 || (GET_CODE (op) == CONST_INT
927 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
928 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
931 /* Return truth value of whether OP is a integer which fits the
932 range constraining immediate operands in most three-address insns,
933 which have a 13 bit immediate field. */
938 enum machine_mode mode ATTRIBUTE_UNUSED;
940 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
941 || GET_CODE (op) == CONSTANT_P_RTX);
945 small_int_or_double (op, mode)
947 enum machine_mode mode ATTRIBUTE_UNUSED;
949 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
950 || (GET_CODE (op) == CONST_DOUBLE
951 && CONST_DOUBLE_HIGH (op) == 0
952 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
953 || GET_CODE (op) == CONSTANT_P_RTX);
956 /* Recognize operand values for the umul instruction. That instruction sign
957 extends immediate values just like all other sparc instructions, but
958 interprets the extended result as an unsigned number. */
961 uns_small_int (op, mode)
963 enum machine_mode mode ATTRIBUTE_UNUSED;
965 #if HOST_BITS_PER_WIDE_INT > 32
966 /* All allowed constants will fit a CONST_INT. */
967 return ((GET_CODE (op) == CONST_INT
968 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
969 || (INTVAL (op) >= 0xFFFFF000
970 && INTVAL (op) < 0x100000000)))
971 || GET_CODE (op) == CONSTANT_P_RTX);
973 return (((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
974 || (GET_CODE (op) == CONST_DOUBLE
975 && CONST_DOUBLE_HIGH (op) == 0
976 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000))
977 || GET_CODE (op) == CONSTANT_P_RTX);
982 uns_arith_operand (op, mode)
984 enum machine_mode mode;
986 return register_operand (op, mode) || uns_small_int (op, mode);
989 /* Return truth value of statement that OP is a call-clobbered register. */
991 clobbered_register (op, mode)
993 enum machine_mode mode ATTRIBUTE_UNUSED;
995 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
998 /* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */
1001 zero_operand (op, mode)
1003 enum machine_mode mode ATTRIBUTE_UNUSED;
1005 return (op == const0_rtx || GET_CODE (op) == CONSTANT_P_RTX);
1008 /* Return 1 if OP is a valid operand for the source of a move insn. */
1011 input_operand (op, mode)
1013 enum machine_mode mode;
1015 /* If both modes are non-void they must be the same. */
1016 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1019 /* Allow any one instruction integer constant, and all CONST_INT
1020 variants when we are working in DImode and !arch64. */
1021 if (GET_MODE_CLASS (mode) == MODE_INT
1022 && ((GET_CODE (op) == CONST_INT
1023 && ((SPARC_SETHI_P (INTVAL (op))
1025 || (INTVAL (op) >= 0)
1027 || SPARC_SIMM13_P (INTVAL (op))
1029 && ! TARGET_ARCH64)))
1031 && GET_CODE (op) == CONST_DOUBLE
1032 && ((CONST_DOUBLE_HIGH (op) == 0
1033 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1035 #if HOST_BITS_PER_WIDE_INT == 64
1036 (CONST_DOUBLE_HIGH (op) == 0
1037 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1039 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1040 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1041 && CONST_DOUBLE_HIGH (op) == 0)
1042 || (CONST_DOUBLE_HIGH (op) == -1)))
1047 /* Always match this. */
1048 if (GET_CODE (op) == CONSTANT_P_RTX)
1051 /* If !arch64 and this is a DImode const, allow it so that
1052 the splits can be generated. */
1055 && GET_CODE (op) == CONST_DOUBLE)
1058 if (register_operand (op, mode))
1061 /* If this is a SUBREG, look inside so that we handle
1062 paradoxical ones. */
1063 if (GET_CODE (op) == SUBREG)
1064 op = SUBREG_REG (op);
1066 /* Check for valid MEM forms. */
1067 if (GET_CODE (op) == MEM)
1069 rtx inside = XEXP (op, 0);
1071 if (GET_CODE (inside) == LO_SUM)
1073 /* We can't allow these because all of the splits
1074 (eventually as they trickle down into DFmode
1075 splits) require offsettable memory references. */
1077 && GET_MODE (op) == TFmode)
1080 return (register_operand (XEXP (inside, 0), Pmode)
1081 && CONSTANT_P (XEXP (inside, 1)));
1083 return memory_address_p (mode, inside);
1090 /* We know it can't be done in one insn when we get here,
1091 the movsi expander guarentees this. */
1093 sparc_emit_set_const32 (op0, op1)
1097 enum machine_mode mode = GET_MODE (op0);
1100 if (GET_CODE (op1) == CONST_INT)
1102 HOST_WIDE_INT value = INTVAL (op1);
1104 if (SPARC_SETHI_P (value)
1105 || SPARC_SIMM13_P (value))
1109 /* Full 2-insn decomposition is needed. */
1110 if (reload_in_progress || reload_completed)
1113 temp = gen_reg_rtx (mode);
1115 emit_insn (gen_rtx_SET (VOIDmode,
1119 emit_insn (gen_rtx_SET (VOIDmode,
1121 gen_rtx_LO_SUM (mode,
1127 /* Sparc-v9 code-model support. */
1129 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1134 switch (sparc_cmodel)
1137 /* The range spanned by all instructions in the object is less
1138 than 2^31 bytes (2GB) and the distance from any instruction
1139 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1140 than 2^31 bytes (2GB).
1142 The executable must be in the low 4TB of the virtual address
1145 sethi %hi(symbol), %temp
1146 or %temp, %lo(symbol), %reg */
1147 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1148 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1152 /* The range spanned by all instructions in the object is less
1153 than 2^31 bytes (2GB) and the distance from any instruction
1154 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1155 than 2^31 bytes (2GB).
1157 The executable must be in the low 16TB of the virtual address
1160 sethi %h44(symbol), %temp1
1161 or %temp1, %m44(symbol), %temp2
1162 sllx %temp2, 12, %temp3
1163 or %temp3, %l44(symbol), %reg */
1164 emit_insn (gen_seth44 (op0, op1));
1165 emit_insn (gen_setm44 (op0, op0, op1));
1166 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1167 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1168 emit_insn (gen_setl44 (op0, temp1, op1));
1172 /* The range spanned by all instructions in the object is less
1173 than 2^31 bytes (2GB) and the distance from any instruction
1174 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1175 than 2^31 bytes (2GB).
1177 The executable can be placed anywhere in the virtual address
1180 sethi %hh(symbol), %temp1
1181 sethi %lm(symbol), %temp2
1182 or %temp1, %hm(symbol), %temp3
1183 or %temp2, %lo(symbol), %temp4
1184 sllx %temp3, 32, %temp5
1185 or %temp4, %temp5, %reg */
1187 /* Getting this right wrt. reloading is really tricky.
1188 We _MUST_ have a seperate temporary at this point,
1189 if we don't barf immediately instead of generating
1194 emit_insn (gen_sethh (op0, op1));
1195 emit_insn (gen_setlm (temp1, op1));
1196 emit_insn (gen_sethm (op0, op0, op1));
1197 emit_insn (gen_rtx_SET (VOIDmode, op0,
1198 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1199 emit_insn (gen_rtx_SET (VOIDmode, op0,
1200 gen_rtx_PLUS (DImode, op0, temp1)));
1201 emit_insn (gen_setlo (op0, op0, op1));
1205 /* Old old old backwards compatibility kruft here.
1206 Essentially it is MEDLOW with a fixed 64-bit
1207 virtual base added to all data segment addresses.
1208 Text-segment stuff is computed like MEDANY, we can't
1209 reuse the code above because the relocation knobs
1212 Data segment: sethi %hi(symbol), %temp1
1213 or %temp1, %lo(symbol), %temp2
1214 add %temp2, EMBMEDANY_BASE_REG, %reg
1216 Text segment: sethi %uhi(symbol), %temp1
1217 sethi %hi(symbol), %temp2
1218 or %temp1, %ulo(symbol), %temp3
1219 or %temp2, %lo(symbol), %temp4
1220 sllx %temp3, 32, %temp5
1221 or %temp4, %temp5, %reg */
1222 if (data_segment_operand (op1, GET_MODE (op1)))
1224 emit_insn (gen_embmedany_sethi (temp1, op1));
1225 emit_insn (gen_embmedany_brsum (op0, temp1));
1226 emit_insn (gen_embmedany_losum (op0, op0, op1));
1230 /* Getting this right wrt. reloading is really tricky.
1231 We _MUST_ have a seperate temporary at this point,
1232 so we barf immediately instead of generating
1237 emit_insn (gen_embmedany_textuhi (op0, op1));
1238 emit_insn (gen_embmedany_texthi (temp1, op1));
1239 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1240 emit_insn (gen_rtx_SET (VOIDmode, op0,
1241 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1242 emit_insn (gen_rtx_SET (VOIDmode, op0,
1243 gen_rtx_PLUS (DImode, op0, temp1)));
1244 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1253 /* These avoid problems when cross compiling. If we do not
1254 go through all this hair then the optimizer will see
1255 invalid REG_EQUAL notes or in some cases none at all. */
1256 static void sparc_emit_set_safe_HIGH64 PROTO ((rtx, HOST_WIDE_INT));
1257 static rtx gen_safe_SET64 PROTO ((rtx, HOST_WIDE_INT));
1258 static rtx gen_safe_OR64 PROTO ((rtx, HOST_WIDE_INT));
1259 static rtx gen_safe_XOR64 PROTO ((rtx, HOST_WIDE_INT));
1261 #if HOST_BITS_PER_WIDE_INT == 64
1262 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
1263 #define GEN_INT64(__x) GEN_INT (__x)
1265 #define GEN_HIGHINT64(__x) \
1266 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1267 (__x) & 0xfffffc00, 0)
1268 #define GEN_INT64(__x) \
1269 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1270 (__x) & 0xffffffff, \
1271 ((__x) & 0x80000000 \
1275 /* The optimizer is not to assume anything about exactly
1276 which bits are set for a HIGH, they are unspecified.
1277 Unfortunately this leads to many missed optimizations
1278 during CSE. We mask out the non-HIGH bits, and matches
1279 a plain movdi, to alleviate this problem. */
1281 sparc_emit_set_safe_HIGH64 (dest, val)
1285 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1289 gen_safe_SET64 (dest, val)
1293 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1297 gen_safe_OR64 (src, val)
1301 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1305 gen_safe_XOR64 (src, val)
1309 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1312 /* Worker routines for 64-bit constant formation on arch64.
1313 One of the key things to be doing in these emissions is
1314 to create as many temp REGs as possible. This makes it
1315 possible for half-built constants to be used later when
1316 such values are similar to something required later on.
1317 Without doing this, the optimizer cannot see such
1320 static void sparc_emit_set_const64_quick1
1321 PROTO((rtx, rtx, unsigned HOST_WIDE_INT, int));
1324 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1327 unsigned HOST_WIDE_INT low_bits;
1330 unsigned HOST_WIDE_INT high_bits;
1333 high_bits = (~low_bits) & 0xffffffff;
1335 high_bits = low_bits;
1337 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1339 emit_insn (gen_rtx_SET (VOIDmode, op0,
1340 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1342 emit_insn (gen_rtx_SET (VOIDmode, op0,
1343 gen_safe_XOR64 (temp,
1344 (-0x400 | (low_bits & 0x3ff)))));
1347 static void sparc_emit_set_const64_quick2
1348 PROTO((rtx, rtx, unsigned HOST_WIDE_INT,
1349 unsigned HOST_WIDE_INT, int));
1352 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1355 unsigned HOST_WIDE_INT high_bits;
1356 unsigned HOST_WIDE_INT low_immediate;
1361 if ((high_bits & 0xfffffc00) != 0)
1363 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1364 if ((high_bits & ~0xfffffc00) != 0)
1365 emit_insn (gen_rtx_SET (VOIDmode, op0,
1366 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1372 emit_insn (gen_safe_SET64 (temp, high_bits));
1376 /* Now shift it up into place. */
1377 emit_insn (gen_rtx_SET (VOIDmode, op0,
1378 gen_rtx_ASHIFT (DImode, temp2,
1379 GEN_INT (shift_count))));
1381 /* If there is a low immediate part piece, finish up by
1382 putting that in as well. */
1383 if (low_immediate != 0)
1384 emit_insn (gen_rtx_SET (VOIDmode, op0,
1385 gen_safe_OR64 (op0, low_immediate)));
1388 static void sparc_emit_set_const64_longway
1389 PROTO((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1391 /* Full 64-bit constant decomposition. Even though this is the
1392 'worst' case, we still optimize a few things away. */
1394 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1397 unsigned HOST_WIDE_INT high_bits;
1398 unsigned HOST_WIDE_INT low_bits;
1402 if (reload_in_progress || reload_completed)
1405 sub_temp = gen_reg_rtx (DImode);
1407 if ((high_bits & 0xfffffc00) != 0)
1409 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1410 if ((high_bits & ~0xfffffc00) != 0)
1411 emit_insn (gen_rtx_SET (VOIDmode,
1413 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1419 emit_insn (gen_safe_SET64 (temp, high_bits));
1423 if (!reload_in_progress && !reload_completed)
1425 rtx temp2 = gen_reg_rtx (DImode);
1426 rtx temp3 = gen_reg_rtx (DImode);
1427 rtx temp4 = gen_reg_rtx (DImode);
1429 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1430 gen_rtx_ASHIFT (DImode, sub_temp,
1433 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1434 if ((low_bits & ~0xfffffc00) != 0)
1436 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1437 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1438 emit_insn (gen_rtx_SET (VOIDmode, op0,
1439 gen_rtx_PLUS (DImode, temp4, temp3)));
1443 emit_insn (gen_rtx_SET (VOIDmode, op0,
1444 gen_rtx_PLUS (DImode, temp4, temp2)));
1449 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1450 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1451 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1454 /* We are in the middle of reload, so this is really
1455 painful. However we do still make an attempt to
1456 avoid emmitting truly stupid code. */
1457 if (low1 != const0_rtx)
1459 emit_insn (gen_rtx_SET (VOIDmode, op0,
1460 gen_rtx_ASHIFT (DImode, sub_temp,
1461 GEN_INT (to_shift))));
1462 emit_insn (gen_rtx_SET (VOIDmode, op0,
1463 gen_rtx_IOR (DImode, op0, low1)));
1471 if (low2 != const0_rtx)
1473 emit_insn (gen_rtx_SET (VOIDmode, op0,
1474 gen_rtx_ASHIFT (DImode, sub_temp,
1475 GEN_INT (to_shift))));
1476 emit_insn (gen_rtx_SET (VOIDmode, op0,
1477 gen_rtx_IOR (DImode, op0, low2)));
1485 emit_insn (gen_rtx_SET (VOIDmode, op0,
1486 gen_rtx_ASHIFT (DImode, sub_temp,
1487 GEN_INT (to_shift))));
1488 if (low3 != const0_rtx)
1489 emit_insn (gen_rtx_SET (VOIDmode, op0,
1490 gen_rtx_IOR (DImode, op0, low3)));
1495 /* Analyze a 64-bit constant for certain properties. */
1496 static void analyze_64bit_constant
1497 PROTO((unsigned HOST_WIDE_INT,
1498 unsigned HOST_WIDE_INT,
1499 int *, int *, int *));
1502 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1503 unsigned HOST_WIDE_INT high_bits, low_bits;
1504 int *hbsp, *lbsp, *abbasp;
1506 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1509 lowest_bit_set = highest_bit_set = -1;
1513 if ((lowest_bit_set == -1)
1514 && ((low_bits >> i) & 1))
1516 if ((highest_bit_set == -1)
1517 && ((high_bits >> (32 - i - 1)) & 1))
1518 highest_bit_set = (64 - i - 1);
1521 && ((highest_bit_set == -1)
1522 || (lowest_bit_set == -1)));
1528 if ((lowest_bit_set == -1)
1529 && ((high_bits >> i) & 1))
1530 lowest_bit_set = i + 32;
1531 if ((highest_bit_set == -1)
1532 && ((low_bits >> (32 - i - 1)) & 1))
1533 highest_bit_set = 32 - i - 1;
1536 && ((highest_bit_set == -1)
1537 || (lowest_bit_set == -1)));
1539 /* If there are no bits set this should have gone out
1540 as one instruction! */
1541 if (lowest_bit_set == -1
1542 || highest_bit_set == -1)
1544 all_bits_between_are_set = 1;
1545 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1549 if ((low_bits & (1 << i)) != 0)
1554 if ((high_bits & (1 << (i - 32))) != 0)
1557 all_bits_between_are_set = 0;
1560 *hbsp = highest_bit_set;
1561 *lbsp = lowest_bit_set;
1562 *abbasp = all_bits_between_are_set;
1565 static int const64_is_2insns
1566 PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1569 const64_is_2insns (high_bits, low_bits)
1570 unsigned HOST_WIDE_INT high_bits, low_bits;
1572 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1575 || high_bits == 0xffffffff)
1578 analyze_64bit_constant (high_bits, low_bits,
1579 &highest_bit_set, &lowest_bit_set,
1580 &all_bits_between_are_set);
1582 if ((highest_bit_set == 63
1583 || lowest_bit_set == 0)
1584 && all_bits_between_are_set != 0)
1587 if ((highest_bit_set - lowest_bit_set) < 21)
1593 static unsigned HOST_WIDE_INT create_simple_focus_bits
1594 PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
1597 static unsigned HOST_WIDE_INT
1598 create_simple_focus_bits (high_bits, low_bits, highest_bit_set, lowest_bit_set, shift)
1599 unsigned HOST_WIDE_INT high_bits, low_bits;
1600 int highest_bit_set, lowest_bit_set, shift;
1602 HOST_WIDE_INT hi, lo;
1604 if (lowest_bit_set < 32)
1606 lo = (low_bits >> lowest_bit_set) << shift;
1607 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1612 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1619 /* Here we are sure to be arch64 and this is an integer constant
1620 being loaded into a register. Emit the most efficient
1621 insn sequence possible. Detection of all the 1-insn cases
1622 has been done already. */
1624 sparc_emit_set_const64 (op0, op1)
1628 unsigned HOST_WIDE_INT high_bits, low_bits;
1629 int lowest_bit_set, highest_bit_set;
1630 int all_bits_between_are_set;
1634 /* Sanity check that we know what we are working with. */
1636 || GET_CODE (op0) != REG
1637 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1638 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1641 if (reload_in_progress || reload_completed)
1644 temp = gen_reg_rtx (DImode);
1646 if (GET_CODE (op1) != CONST_DOUBLE
1647 && GET_CODE (op1) != CONST_INT)
1649 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1653 if (GET_CODE (op1) == CONST_DOUBLE)
1655 #if HOST_BITS_PER_WIDE_INT == 64
1656 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1657 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1659 high_bits = CONST_DOUBLE_HIGH (op1);
1660 low_bits = CONST_DOUBLE_LOW (op1);
1665 #if HOST_BITS_PER_WIDE_INT == 64
1666 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1667 low_bits = (INTVAL (op1) & 0xffffffff);
1669 high_bits = ((INTVAL (op1) < 0) ?
1672 low_bits = INTVAL (op1);
1676 /* low_bits bits 0 --> 31
1677 high_bits bits 32 --> 63 */
1679 analyze_64bit_constant (high_bits, low_bits,
1680 &highest_bit_set, &lowest_bit_set,
1681 &all_bits_between_are_set);
1683 /* First try for a 2-insn sequence. */
1685 /* These situations are preferred because the optimizer can
1686 * do more things with them:
1688 * sllx %reg, shift, %reg
1690 * srlx %reg, shift, %reg
1691 * 3) mov some_small_const, %reg
1692 * sllx %reg, shift, %reg
1694 if (((highest_bit_set == 63
1695 || lowest_bit_set == 0)
1696 && all_bits_between_are_set != 0)
1697 || ((highest_bit_set - lowest_bit_set) < 12))
1699 HOST_WIDE_INT the_const = -1;
1700 int shift = lowest_bit_set;
1702 if ((highest_bit_set != 63
1703 && lowest_bit_set != 0)
1704 || all_bits_between_are_set == 0)
1707 create_simple_focus_bits (high_bits, low_bits,
1711 else if (lowest_bit_set == 0)
1712 shift = -(63 - highest_bit_set);
1714 if (! SPARC_SIMM13_P (the_const))
1717 emit_insn (gen_safe_SET64 (temp, the_const));
1719 emit_insn (gen_rtx_SET (VOIDmode,
1721 gen_rtx_ASHIFT (DImode,
1725 emit_insn (gen_rtx_SET (VOIDmode,
1727 gen_rtx_LSHIFTRT (DImode,
1729 GEN_INT (-shift))));
1735 /* Now a range of 22 or less bits set somewhere.
1736 * 1) sethi %hi(focus_bits), %reg
1737 * sllx %reg, shift, %reg
1738 * 2) sethi %hi(focus_bits), %reg
1739 * srlx %reg, shift, %reg
1741 if ((highest_bit_set - lowest_bit_set) < 21)
1743 unsigned HOST_WIDE_INT focus_bits =
1744 create_simple_focus_bits (high_bits, low_bits,
1745 highest_bit_set, lowest_bit_set, 10);
1747 if (! SPARC_SETHI_P (focus_bits))
1750 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
1752 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1753 if (lowest_bit_set < 10)
1754 emit_insn (gen_rtx_SET (VOIDmode,
1756 gen_rtx_LSHIFTRT (DImode, temp,
1757 GEN_INT (10 - lowest_bit_set))));
1758 else if (lowest_bit_set > 10)
1759 emit_insn (gen_rtx_SET (VOIDmode,
1761 gen_rtx_ASHIFT (DImode, temp,
1762 GEN_INT (lowest_bit_set - 10))));
1768 /* 1) sethi %hi(low_bits), %reg
1769 * or %reg, %lo(low_bits), %reg
1770 * 2) sethi %hi(~low_bits), %reg
1771 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1774 || high_bits == 0xffffffff)
1776 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1777 (high_bits == 0xffffffff));
1781 /* Now, try 3-insn sequences. */
1783 /* 1) sethi %hi(high_bits), %reg
1784 * or %reg, %lo(high_bits), %reg
1785 * sllx %reg, 32, %reg
1789 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
1793 /* We may be able to do something quick
1794 when the constant is negated, so try that. */
1795 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1796 (~low_bits) & 0xfffffc00))
1798 unsigned HOST_WIDE_INT trailing_bits = (~low_bits) & 0x3ff;
1800 if ((((~high_bits) & 0xffffffff) == 0
1801 && ((~low_bits) & 0x80000000) == 0)
1802 || (((~high_bits) & 0xffffffff) == 0xffffffff
1803 && ((~low_bits) & 0x80000000) != 0))
1805 HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
1807 if (SPARC_SETHI_P (fast_int)
1808 || SPARC_SIMM13_P (((int)fast_int)))
1809 emit_insn (gen_safe_SET64 (temp, fast_int));
1811 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
1816 #if HOST_BITS_PER_WIDE_INT == 64
1817 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
1818 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
1820 negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx,
1821 (~low_bits) & 0xfffffc00,
1822 (~high_bits) & 0xffffffff);
1824 sparc_emit_set_const64 (temp, negated_const);
1826 emit_insn (gen_rtx_SET (VOIDmode,
1828 gen_safe_XOR64 (temp,
1829 (-0x400 | trailing_bits))));
1833 /* 1) sethi %hi(xxx), %reg
1834 * or %reg, %lo(xxx), %reg
1835 * sllx %reg, yyy, %reg
1837 * ??? This is just a generalized version of the low_bits==0
1838 * thing above, FIXME...
1840 if ((highest_bit_set - lowest_bit_set) < 32)
1842 unsigned HOST_WIDE_INT focus_bits =
1843 create_simple_focus_bits (high_bits, low_bits,
1844 highest_bit_set, lowest_bit_set, 0);
1846 /* We can't get here in this state. */
1847 if (highest_bit_set < 32
1848 || lowest_bit_set >= 32)
1851 /* So what we know is that the set bits straddle the
1852 middle of the 64-bit word. */
1853 sparc_emit_set_const64_quick2 (op0, temp,
1859 /* 1) sethi %hi(high_bits), %reg
1860 * or %reg, %lo(high_bits), %reg
1861 * sllx %reg, 32, %reg
1862 * or %reg, low_bits, %reg
1864 if (SPARC_SIMM13_P(low_bits)
1865 && ((int)low_bits > 0))
1867 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
1871 /* The easiest way when all else fails, is full decomposition. */
1873 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1874 high_bits, low_bits, ~high_bits, ~low_bits);
1876 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
1879 /* X and Y are two things to compare using CODE. Emit the compare insn and
1880 return the rtx for the cc reg in the proper mode. */
1883 gen_compare_reg (code, x, y)
1887 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1890 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
1891 fcc regs (cse can't tell they're really call clobbered regs and will
1892 remove a duplicate comparison even if there is an intervening function
1893 call - it will then try to reload the cc reg via an int reg which is why
1894 we need the movcc patterns). It is possible to provide the movcc
1895 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
1896 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
1897 to tell cse that CCFPE mode registers (even pseudos) are call
1900 /* ??? This is an experiment. Rather than making changes to cse which may
1901 or may not be easy/clean, we do our own cse. This is possible because
1902 we will generate hard registers. Cse knows they're call clobbered (it
1903 doesn't know the same thing about pseudos). If we guess wrong, no big
1904 deal, but if we win, great! */
1906 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1907 #if 1 /* experiment */
1910 /* We cycle through the registers to ensure they're all exercised. */
1911 static int next_fcc_reg = 0;
1912 /* Previous x,y for each fcc reg. */
1913 static rtx prev_args[4][2];
1915 /* Scan prev_args for x,y. */
1916 for (reg = 0; reg < 4; reg++)
1917 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
1922 prev_args[reg][0] = x;
1923 prev_args[reg][1] = y;
1924 next_fcc_reg = (next_fcc_reg + 1) & 3;
1926 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
1929 cc_reg = gen_reg_rtx (mode);
1930 #endif /* ! experiment */
1931 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1932 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
1934 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
1936 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
1937 gen_rtx_COMPARE (mode, x, y)));
1942 /* This function is used for v9 only.
1943 CODE is the code for an Scc's comparison.
1944 OPERANDS[0] is the target of the Scc insn.
1945 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
1946 been generated yet).
1948 This function is needed to turn
1951 (gt (reg:CCX 100 %icc)
1955 (gt:DI (reg:CCX 100 %icc)
1958 IE: The instruction recognizer needs to see the mode of the comparison to
1959 find the right instruction. We could use "gt:DI" right in the
1960 define_expand, but leaving it out allows us to handle DI, SI, etc.
1962 We refer to the global sparc compare operands sparc_compare_op0 and
1963 sparc_compare_op1. */
1966 gen_v9_scc (compare_code, operands)
1967 enum rtx_code compare_code;
1968 register rtx *operands;
1973 && (GET_MODE (sparc_compare_op0) == DImode
1974 || GET_MODE (operands[0]) == DImode))
1977 /* Handle the case where operands[0] == sparc_compare_op0.
1978 We "early clobber" the result. */
1979 if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
1981 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
1982 emit_move_insn (op0, sparc_compare_op0);
1985 op0 = sparc_compare_op0;
1986 /* For consistency in the following. */
1987 op1 = sparc_compare_op1;
1989 /* Try to use the movrCC insns. */
1991 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
1992 && op1 == const0_rtx
1993 && v9_regcmp_p (compare_code))
1995 /* Special case for op0 != 0. This can be done with one instruction if
1996 operands[0] == sparc_compare_op0. We don't assume they are equal
1999 if (compare_code == NE
2000 && GET_MODE (operands[0]) == DImode
2001 && GET_MODE (op0) == DImode)
2003 emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0));
2004 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2005 gen_rtx_IF_THEN_ELSE (DImode,
2006 gen_rtx_fmt_ee (compare_code, DImode,
2013 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2014 if (GET_MODE (op0) != DImode)
2016 temp = gen_reg_rtx (DImode);
2017 convert_move (temp, op0, 0);
2021 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2022 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2023 gen_rtx_fmt_ee (compare_code, DImode,
2031 operands[1] = gen_compare_reg (compare_code, op0, op1);
2033 switch (GET_MODE (operands[1]))
2043 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2044 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2045 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2046 gen_rtx_fmt_ee (compare_code,
2047 GET_MODE (operands[1]),
2048 operands[1], const0_rtx),
2049 const1_rtx, operands[0])));
2054 /* Emit a conditional jump insn for the v9 architecture using comparison code
2055 CODE and jump target LABEL.
2056 This function exists to take advantage of the v9 brxx insns. */
2059 emit_v9_brxx_insn (code, op0, label)
2063 emit_jump_insn (gen_rtx_SET (VOIDmode,
2065 gen_rtx_IF_THEN_ELSE (VOIDmode,
2066 gen_rtx_fmt_ee (code, GET_MODE (op0),
2068 gen_rtx_LABEL_REF (VOIDmode, label),
2072 /* Return nonzero if a return peephole merging return with
2073 setting of output register is ok. */
2075 leaf_return_peephole_ok ()
2077 return (actual_fsize == 0);
2080 /* Return nonzero if TRIAL can go into the function epilogue's
2081 delay slot. SLOT is the slot we are trying to fill. */
2084 eligible_for_epilogue_delay (trial, slot)
2093 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2096 if (get_attr_length (trial) != 1)
2099 /* If %g0 is live, there are lots of things we can't handle.
2100 Rather than trying to find them all now, let's punt and only
2101 optimize things as necessary. */
2105 /* In the case of a true leaf function, anything can go into the delay slot.
2106 A delay slot only exists however if the frame size is zero, otherwise
2107 we will put an insn to adjust the stack after the return. */
2110 if (leaf_return_peephole_ok ())
2111 return ((get_attr_in_uncond_branch_delay (trial)
2112 == IN_BRANCH_DELAY_TRUE));
2116 /* If only trivial `restore' insns work, nothing can go in the
2118 else if (TARGET_BROKEN_SAVERESTORE)
2121 pat = PATTERN (trial);
2123 /* Otherwise, only operations which can be done in tandem with
2124 a `restore' insn can go into the delay slot. */
2125 if (GET_CODE (SET_DEST (pat)) != REG
2126 || REGNO (SET_DEST (pat)) >= 32
2127 || REGNO (SET_DEST (pat)) < 24)
2130 /* The set of insns matched here must agree precisely with the set of
2131 patterns paired with a RETURN in sparc.md. */
2133 src = SET_SRC (pat);
2135 /* This matches "*return_[qhs]i". */
2136 if (arith_operand (src, GET_MODE (src)))
2137 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2139 /* This matches "*return_di". */
2140 else if (arith_double_operand (src, GET_MODE (src)))
2141 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2143 /* This matches "*return_sf_no_fpu". */
2144 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2145 && register_operand (src, SFmode))
2148 /* This matches "*return_addsi". */
2149 else if (GET_CODE (src) == PLUS
2150 && arith_operand (XEXP (src, 0), SImode)
2151 && arith_operand (XEXP (src, 1), SImode)
2152 && (register_operand (XEXP (src, 0), SImode)
2153 || register_operand (XEXP (src, 1), SImode)))
2156 /* This matches "*return_adddi". */
2157 else if (GET_CODE (src) == PLUS
2158 && arith_double_operand (XEXP (src, 0), DImode)
2159 && arith_double_operand (XEXP (src, 1), DImode)
2160 && (register_operand (XEXP (src, 0), DImode)
2161 || register_operand (XEXP (src, 1), DImode)))
2168 check_return_regs (x)
2171 switch (GET_CODE (x))
2174 return IN_OR_GLOBAL_P (x);
2189 if (check_return_regs (XEXP (x, 1)) == 0)
2194 return check_return_regs (XEXP (x, 0));
2202 /* Return 1 if TRIAL references only in and global registers. */
2204 eligible_for_return_delay (trial)
2207 if (GET_CODE (PATTERN (trial)) != SET)
2210 return check_return_regs (PATTERN (trial));
2214 short_branch (uid1, uid2)
2217 unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
2218 if (delta + 1024 < 2048)
2220 /* warning ("long branch, distance %d", delta); */
2224 /* Return non-zero if REG is not used after INSN.
2225 We assume REG is a reload reg, and therefore does
2226 not live past labels or calls or jumps. */
2228 reg_unused_after (reg, insn)
2232 enum rtx_code code, prev_code = UNKNOWN;
2234 while ((insn = NEXT_INSN (insn)))
2236 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2239 code = GET_CODE (insn);
2240 if (GET_CODE (insn) == CODE_LABEL)
2243 if (GET_RTX_CLASS (code) == 'i')
2245 rtx set = single_set (insn);
2246 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2249 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2251 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2259 /* The table we use to reference PIC data. */
2260 static rtx global_offset_table;
2262 /* The function we use to get at it. */
2263 static rtx get_pc_symbol;
2264 static char get_pc_symbol_name[256];
2266 /* Ensure that we are not using patterns that are not OK with PIC. */
2275 if (GET_CODE (recog_operand[i]) == SYMBOL_REF
2276 || (GET_CODE (recog_operand[i]) == CONST
2277 && ! (GET_CODE (XEXP (recog_operand[i], 0)) == MINUS
2278 && (XEXP (XEXP (recog_operand[i], 0), 0)
2279 == global_offset_table)
2280 && (GET_CODE (XEXP (XEXP (recog_operand[i], 0), 1))
2289 /* Return true if X is an address which needs a temporary register when
2290 reloaded while generating PIC code. */
2293 pic_address_needs_scratch (x)
2296 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2297 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2298 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2299 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2300 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2306 /* Legitimize PIC addresses. If the address is already position-independent,
2307 we return ORIG. Newly generated position-independent addresses go into a
2308 reg. This is REG if non zero, otherwise we allocate register(s) as
2312 legitimize_pic_address (orig, mode, reg)
2314 enum machine_mode mode ATTRIBUTE_UNUSED;
2317 if (GET_CODE (orig) == SYMBOL_REF)
2319 rtx pic_ref, address;
2324 if (reload_in_progress || reload_completed)
2327 reg = gen_reg_rtx (Pmode);
2332 /* If not during reload, allocate another temp reg here for loading
2333 in the address, so that these instructions can be optimized
2335 rtx temp_reg = ((reload_in_progress || reload_completed)
2336 ? reg : gen_reg_rtx (Pmode));
2338 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
2339 won't get confused into thinking that these two instructions
2340 are loading in the true address of the symbol. If in the
2341 future a PIC rtx exists, that should be used instead. */
2342 emit_insn (gen_movsi_high_pic (temp_reg, orig));
2343 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
2349 pic_ref = gen_rtx_MEM (Pmode,
2350 gen_rtx_PLUS (Pmode,
2351 pic_offset_table_rtx, address));
2352 current_function_uses_pic_offset_table = 1;
2353 RTX_UNCHANGING_P (pic_ref) = 1;
2354 insn = emit_move_insn (reg, pic_ref);
2355 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2357 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2361 else if (GET_CODE (orig) == CONST)
2365 if (GET_CODE (XEXP (orig, 0)) == PLUS
2366 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2371 if (reload_in_progress || reload_completed)
2374 reg = gen_reg_rtx (Pmode);
2377 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2379 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2380 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2381 base == reg ? 0 : reg);
2386 if (GET_CODE (offset) == CONST_INT)
2388 if (SMALL_INT (offset))
2389 return plus_constant_for_output (base, INTVAL (offset));
2390 else if (! reload_in_progress && ! reload_completed)
2391 offset = force_reg (Pmode, offset);
2393 /* If we reach here, then something is seriously wrong. */
2396 return gen_rtx_PLUS (Pmode, base, offset);
2398 else if (GET_CODE (orig) == LABEL_REF)
2399 /* ??? Why do we do this? */
2400 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
2401 the register is live instead, in case it is eliminated. */
2402 current_function_uses_pic_offset_table = 1;
2407 /* Set up PIC-specific rtl. This should not cause any insns
2415 /* Return the RTX for insns to set the PIC register. */
2423 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
2425 seq = gen_sequence ();
2431 /* Emit special PIC prologues and epilogues. */
2436 /* Labels to get the PC in the prologue of this function. */
2437 int orig_flag_pic = flag_pic;
2440 if (current_function_uses_pic_offset_table == 0)
2446 /* If we havn't emitted the special get_pc helper function, do so now. */
2447 if (get_pc_symbol_name[0] == 0)
2449 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
2452 ASM_OUTPUT_ALIGN (asm_out_file, 3);
2453 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
2454 fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file);
2457 /* Initialize every time through, since we can't easily
2458 know this to be permanent. */
2459 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2460 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
2463 emit_insn_after (pic_setup_code (), get_insns ());
2465 /* Insert the code in each nonlocal goto receiver. */
2466 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2467 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
2468 && XINT (PATTERN (insn), 1) == 4)
2469 emit_insn_after (pic_setup_code (), insn);
2471 flag_pic = orig_flag_pic;
2473 /* Need to emit this whether or not we obey regdecls,
2474 since setjmp/longjmp can cause life info to screw up.
2475 ??? In the case where we don't obey regdecls, this is not sufficient
2476 since we may not fall out the bottom. */
2477 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2480 /* Return 1 if RTX is a MEM which is known to be aligned to at
2481 least an 8 byte boundary. */
2484 mem_min_alignment (mem, desired)
2488 rtx addr, base, offset;
2490 /* If it's not a MEM we can't accept it. */
2491 if (GET_CODE (mem) != MEM)
2494 addr = XEXP (mem, 0);
2495 base = offset = NULL_RTX;
2496 if (GET_CODE (addr) == PLUS)
2498 if (GET_CODE (XEXP (addr, 0)) == REG)
2500 base = XEXP (addr, 0);
2502 /* What we are saying here is that if the base
2503 REG is aligned properly, the compiler will make
2504 sure any REG based index upon it will be so
2506 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2507 offset = XEXP (addr, 1);
2509 offset = const0_rtx;
2512 else if (GET_CODE (addr) == REG)
2515 offset = const0_rtx;
2518 if (base != NULL_RTX)
2520 int regno = REGNO (base);
2522 if (regno != FRAME_POINTER_REGNUM
2523 && regno != STACK_POINTER_REGNUM)
2525 /* Check if the compiler has recorded some information
2526 about the alignment of the base REG. If reload has
2527 completed, we already matched with proper alignments. */
2528 if (((regno_pointer_align != NULL
2529 && REGNO_POINTER_ALIGN (regno) >= desired)
2530 || reload_completed)
2531 && ((INTVAL (offset) & (desired - 1)) == 0))
2536 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
2540 else if (! TARGET_UNALIGNED_DOUBLES
2541 || CONSTANT_P (addr)
2542 || GET_CODE (addr) == LO_SUM)
2544 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
2545 is true, in which case we can only assume that an access is aligned if
2546 it is to a constant address, or the address involves a LO_SUM. */
2550 /* An obviously unaligned address. */
2555 /* Return a REG that occurs in ADDR with coefficient 1.
2556 ADDR can be effectively incremented by incrementing REG. */
2559 find_addr_reg (addr)
2562 while (GET_CODE (addr) == PLUS)
2564 /* We absolutely can not fudge the frame pointer here, because the
2565 frame pointer must always be 8 byte aligned. It also confuses
2567 if (GET_CODE (XEXP (addr, 0)) == REG
2568 && REGNO (XEXP (addr, 0)) != FRAME_POINTER_REGNUM)
2569 addr = XEXP (addr, 0);
2570 else if (GET_CODE (XEXP (addr, 1)) == REG
2571 && REGNO (XEXP (addr, 1)) != FRAME_POINTER_REGNUM)
2572 addr = XEXP (addr, 1);
2573 else if (CONSTANT_P (XEXP (addr, 0)))
2574 addr = XEXP (addr, 1);
2575 else if (CONSTANT_P (XEXP (addr, 1)))
2576 addr = XEXP (addr, 0);
2580 if (GET_CODE (addr) == REG)
2585 /* Vectors to keep interesting information about registers where it can easily
2586 be got. We use to use the actual mode value as the bit number, but there
2587 are more than 32 modes now. Instead we use two tables: one indexed by
2588 hard register number, and one indexed by mode. */
2590 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2591 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2592 mapped into one sparc_mode_class mode. */
2594 enum sparc_mode_class {
2595 S_MODE, D_MODE, T_MODE, O_MODE,
2596 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2600 /* Modes for single-word and smaller quantities. */
2601 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2603 /* Modes for double-word and smaller quantities. */
2604 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2606 /* Modes for quad-word and smaller quantities. */
2607 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2609 /* Modes for single-float quantities. We must allow any single word or
2610 smaller quantity. This is because the fix/float conversion instructions
2611 take integer inputs/outputs from the float registers. */
2612 #define SF_MODES (S_MODES)
2614 /* Modes for double-float and smaller quantities. */
2615 #define DF_MODES (S_MODES | D_MODES)
2617 #define DF_MODES64 DF_MODES
2619 /* Modes for double-float only quantities. */
2620 #define DF_ONLY_MODES ((1 << (int) DF_MODE) | (1 << (int) D_MODE))
2622 /* Modes for double-float and larger quantities. */
2623 #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
2625 /* Modes for quad-float only quantities. */
2626 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2628 /* Modes for quad-float and smaller quantities. */
2629 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2631 #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
2633 /* Modes for condition codes. */
2634 #define CC_MODES (1 << (int) CC_MODE)
2635 #define CCFP_MODES (1 << (int) CCFP_MODE)
2637 /* Value is 1 if register/mode pair is acceptable on sparc.
2638 The funny mixture of D and T modes is because integer operations
2639 do not specially operate on tetra quantities, so non-quad-aligned
2640 registers can hold quadword quantities (except %o4 and %i4 because
2641 they cross fixed registers). */
2643 /* This points to either the 32 bit or the 64 bit version. */
2644 int *hard_regno_mode_classes;
2646 static int hard_32bit_mode_classes[] = {
2647 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2648 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2649 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2650 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2652 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2653 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2654 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2655 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2657 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2658 and none can hold SFmode/SImode values. */
2659 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2660 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2661 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2662 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2665 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2671 static int hard_64bit_mode_classes[] = {
2672 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2673 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2674 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2675 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2677 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2678 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2679 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2680 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2682 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2683 and none can hold SFmode/SImode values. */
2684 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2685 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2686 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2687 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2690 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2696 int sparc_mode_class [NUM_MACHINE_MODES];
2698 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
2705 for (i = 0; i < NUM_MACHINE_MODES; i++)
2707 switch (GET_MODE_CLASS (i))
2710 case MODE_PARTIAL_INT:
2711 case MODE_COMPLEX_INT:
2712 if (GET_MODE_SIZE (i) <= 4)
2713 sparc_mode_class[i] = 1 << (int) S_MODE;
2714 else if (GET_MODE_SIZE (i) == 8)
2715 sparc_mode_class[i] = 1 << (int) D_MODE;
2716 else if (GET_MODE_SIZE (i) == 16)
2717 sparc_mode_class[i] = 1 << (int) T_MODE;
2718 else if (GET_MODE_SIZE (i) == 32)
2719 sparc_mode_class[i] = 1 << (int) O_MODE;
2721 sparc_mode_class[i] = 0;
2724 case MODE_COMPLEX_FLOAT:
2725 if (GET_MODE_SIZE (i) <= 4)
2726 sparc_mode_class[i] = 1 << (int) SF_MODE;
2727 else if (GET_MODE_SIZE (i) == 8)
2728 sparc_mode_class[i] = 1 << (int) DF_MODE;
2729 else if (GET_MODE_SIZE (i) == 16)
2730 sparc_mode_class[i] = 1 << (int) TF_MODE;
2731 else if (GET_MODE_SIZE (i) == 32)
2732 sparc_mode_class[i] = 1 << (int) OF_MODE;
2734 sparc_mode_class[i] = 0;
2738 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
2739 we must explicitly check for them here. */
2740 if (i == (int) CCFPmode || i == (int) CCFPEmode)
2741 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
2742 else if (i == (int) CCmode || i == (int) CC_NOOVmode
2743 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
2744 sparc_mode_class[i] = 1 << (int) CC_MODE;
2746 sparc_mode_class[i] = 0;
2752 hard_regno_mode_classes = hard_64bit_mode_classes;
2754 hard_regno_mode_classes = hard_32bit_mode_classes;
2756 /* Initialize the array used by REGNO_REG_CLASS. */
2757 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2759 if (i < 16 && TARGET_V8PLUS)
2760 sparc_regno_reg_class[i] = I64_REGS;
2762 sparc_regno_reg_class[i] = GENERAL_REGS;
2764 sparc_regno_reg_class[i] = FP_REGS;
2766 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
2768 sparc_regno_reg_class[i] = FPCC_REGS;
2770 sparc_regno_reg_class[i] = NO_REGS;
2774 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
2775 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2776 v9 int regs as it simplifies the code. */
2779 save_regs (file, low, high, base, offset, n_regs, real_offset)
2789 if (TARGET_ARCH64 && high <= 32)
2791 for (i = low; i < high; i++)
2793 if (regs_ever_live[i] && ! call_used_regs[i])
2795 fprintf (file, "\tstx\t%s, [%s+%d]\n",
2796 reg_names[i], base, offset + 4 * n_regs);
2797 if (dwarf2out_do_frame ())
2798 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
2805 for (i = low; i < high; i += 2)
2807 if (regs_ever_live[i] && ! call_used_regs[i])
2809 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2811 fprintf (file, "\tstd\t%s, [%s+%d]\n",
2812 reg_names[i], base, offset + 4 * n_regs);
2813 if (dwarf2out_do_frame ())
2815 char *l = dwarf2out_cfi_label ();
2816 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
2817 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
2823 fprintf (file, "\tst\t%s, [%s+%d]\n",
2824 reg_names[i], base, offset + 4 * n_regs);
2825 if (dwarf2out_do_frame ())
2826 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
2832 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2834 fprintf (file, "\tst\t%s, [%s+%d]\n",
2835 reg_names[i+1], base, offset + 4 * n_regs + 4);
2836 if (dwarf2out_do_frame ())
2837 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
2846 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
2848 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2849 v9 int regs as it simplifies the code. */
2852 restore_regs (file, low, high, base, offset, n_regs)
2861 if (TARGET_ARCH64 && high <= 32)
2863 for (i = low; i < high; i++)
2865 if (regs_ever_live[i] && ! call_used_regs[i])
2866 fprintf (file, "\tldx\t[%s+%d], %s\n",
2867 base, offset + 4 * n_regs, reg_names[i]),
2873 for (i = low; i < high; i += 2)
2875 if (regs_ever_live[i] && ! call_used_regs[i])
2876 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2877 fprintf (file, "\tldd\t[%s+%d], %s\n",
2878 base, offset + 4 * n_regs, reg_names[i]),
2881 fprintf (file, "\tld\t[%s+%d],%s\n",
2882 base, offset + 4 * n_regs, reg_names[i]),
2884 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2885 fprintf (file, "\tld\t[%s+%d],%s\n",
2886 base, offset + 4 * n_regs + 4, reg_names[i+1]),
2893 /* Static variables we want to share between prologue and epilogue. */
2895 /* Number of live general or floating point registers needed to be saved
2896 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
2897 static int num_gfregs;
2899 /* Compute the frame size required by the function. This function is called
2900 during the reload pass and also by output_function_prologue(). */
2903 compute_frame_size (size, leaf_function)
2908 int outgoing_args_size = (current_function_outgoing_args_size
2909 + REG_PARM_STACK_SPACE (current_function_decl));
2911 if (TARGET_EPILOGUE)
2913 /* N_REGS is the number of 4-byte regs saved thus far. This applies
2914 even to v9 int regs to be consistent with save_regs/restore_regs. */
2918 for (i = 0; i < 8; i++)
2919 if (regs_ever_live[i] && ! call_used_regs[i])
2924 for (i = 0; i < 8; i += 2)
2925 if ((regs_ever_live[i] && ! call_used_regs[i])
2926 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
2930 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
2931 if ((regs_ever_live[i] && ! call_used_regs[i])
2932 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
2936 /* Set up values for use in `function_epilogue'. */
2937 num_gfregs = n_regs;
2939 if (leaf_function && n_regs == 0
2940 && size == 0 && current_function_outgoing_args_size == 0)
2942 actual_fsize = apparent_fsize = 0;
2946 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
2947 The stack bias (if any) is taken out to undo its effects. */
2948 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
2949 apparent_fsize += n_regs * 4;
2950 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
2953 /* Make sure nothing can clobber our register windows.
2954 If a SAVE must be done, or there is a stack-local variable,
2955 the register window area must be allocated.
2956 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
2957 if (leaf_function == 0 || size > 0)
2958 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
2960 return SPARC_STACK_ALIGN (actual_fsize);
2963 /* Build a (32 bit) big number in a register. */
2964 /* ??? We may be able to use the set macro here too. */
2967 build_big_number (file, num, reg)
2972 if (num >= 0 || ! TARGET_ARCH64)
2974 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
2975 if ((num & 0x3ff) != 0)
2976 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
2978 else /* num < 0 && TARGET_ARCH64 */
2980 /* Sethi does not sign extend, so we must use a little trickery
2981 to use it for negative numbers. Invert the constant before
2982 loading it in, then use xor immediate to invert the loaded bits
2983 (along with the upper 32 bits) to the desired constant. This
2984 works because the sethi and immediate fields overlap. */
2987 int low = -0x400 + (asize & 0x3FF);
2989 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
2990 inv, reg, reg, low, reg);
2994 /* Output code for the function prologue. */
2997 output_function_prologue (file, size, leaf_function)
3002 /* Need to use actual_fsize, since we are also allocating
3003 space for our callee (and our own register save area). */
3004 actual_fsize = compute_frame_size (size, leaf_function);
3008 frame_base_name = "%sp";
3009 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3013 frame_base_name = "%fp";
3014 frame_base_offset = SPARC_STACK_BIAS;
3017 /* This is only for the human reader. */
3018 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3020 if (actual_fsize == 0)
3022 else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
3024 if (actual_fsize <= 4096)
3025 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3026 else if (actual_fsize <= 8192)
3028 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3029 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3033 build_big_number (file, -actual_fsize, "%g1");
3034 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3037 else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
3039 /* We assume the environment will properly handle or otherwise avoid
3040 trouble associated with an interrupt occurring after the `save' or
3041 trap occurring during it. */
3042 fprintf (file, "\tsave\n");
3044 if (actual_fsize <= 4096)
3045 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize);
3046 else if (actual_fsize <= 8192)
3048 fprintf (file, "\tadd\t%%fp, -4096, %%sp\n");
3049 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096);
3053 build_big_number (file, -actual_fsize, "%g1");
3054 fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n");
3057 else /* leaf function */
3059 if (actual_fsize <= 4096)
3060 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3061 else if (actual_fsize <= 8192)
3063 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3064 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3068 build_big_number (file, -actual_fsize, "%g1");
3069 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3073 if (dwarf2out_do_frame () && actual_fsize)
3075 char *label = dwarf2out_cfi_label ();
3077 /* The canonical frame address refers to the top of the frame. */
3078 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3079 : FRAME_POINTER_REGNUM),
3082 if (! leaf_function)
3084 /* Note the register window save. This tells the unwinder that
3085 it needs to restore the window registers from the previous
3086 frame's window save area at 0(cfa). */
3087 dwarf2out_window_save (label);
3089 /* The return address (-8) is now in %i7. */
3090 dwarf2out_return_reg (label, 31);
3094 /* If doing anything with PIC, do it now. */
3096 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3098 /* Call saved registers are saved just above the outgoing argument area. */
3101 int offset, real_offset, n_regs;
3104 real_offset = -apparent_fsize;
3105 offset = -apparent_fsize + frame_base_offset;
3106 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3108 /* ??? This might be optimized a little as %g1 might already have a
3109 value close enough that a single add insn will do. */
3110 /* ??? Although, all of this is probably only a temporary fix
3111 because if %g1 can hold a function result, then
3112 output_function_epilogue will lose (the result will get
3114 build_big_number (file, offset, "%g1");
3115 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3121 base = frame_base_name;
3125 if (TARGET_EPILOGUE && ! leaf_function)
3126 /* ??? Originally saved regs 0-15 here. */
3127 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3128 else if (leaf_function)
3129 /* ??? Originally saved regs 0-31 here. */
3130 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3131 if (TARGET_EPILOGUE)
3132 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3137 if (leaf_function && actual_fsize != 0)
3139 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3140 if (! TARGET_EPILOGUE)
3141 leaf_label = gen_label_rtx ();
3145 /* Output code for the function epilogue. */
3148 output_function_epilogue (file, size, leaf_function)
3150 int size ATTRIBUTE_UNUSED;
3157 emit_label_after (leaf_label, get_last_insn ());
3158 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3161 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3162 else if (profile_block_flag == 2)
3164 FUNCTION_BLOCK_PROFILER_EXIT(file);
3168 else if (current_function_epilogue_delay_list == 0)
3170 /* If code does not drop into the epilogue, we need
3171 do nothing except output pending case vectors. */
3172 rtx insn = get_last_insn ();
3173 if (GET_CODE (insn) == NOTE)
3174 insn = prev_nonnote_insn (insn);
3175 if (insn && GET_CODE (insn) == BARRIER)
3176 goto output_vectors;
3179 /* Restore any call saved registers. */
3185 offset = -apparent_fsize + frame_base_offset;
3186 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3188 build_big_number (file, offset, "%g1");
3189 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3195 base = frame_base_name;
3199 if (TARGET_EPILOGUE && ! leaf_function)
3200 /* ??? Originally saved regs 0-15 here. */
3201 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3202 else if (leaf_function)
3203 /* ??? Originally saved regs 0-31 here. */
3204 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3205 if (TARGET_EPILOGUE)
3206 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3209 /* Work out how to skip the caller's unimp instruction if required. */
3211 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
3213 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
3215 if (TARGET_EPILOGUE || leaf_label)
3217 int old_target_epilogue = TARGET_EPILOGUE;
3218 target_flags &= ~old_target_epilogue;
3220 if (! leaf_function)
3222 /* If we wound up with things in our delay slot, flush them here. */
3223 if (current_function_epilogue_delay_list)
3225 rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
3227 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
3229 PATTERN (XEXP (current_function_epilogue_delay_list, 0)),
3231 final_scan_insn (insn, file, 1, 0, 1);
3233 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
3234 fputs ("\treturn\t%i7+8\n\tnop\n", file);
3236 fprintf (file, "\t%s\n\trestore\n", ret);
3238 /* All of the following cases are for leaf functions. */
3239 else if (current_function_epilogue_delay_list)
3241 /* eligible_for_epilogue_delay_slot ensures that if this is a
3242 leaf function, then we will only have insn in the delay slot
3243 if the frame size is zero, thus no adjust for the stack is
3245 if (actual_fsize != 0)
3247 fprintf (file, "\t%s\n", ret);
3248 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3251 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3252 avoid generating confusing assembly language output. */
3253 else if (actual_fsize == 0)
3254 fprintf (file, "\t%s\n\tnop\n", ret);
3255 else if (actual_fsize <= 4096)
3256 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
3257 else if (actual_fsize <= 8192)
3258 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
3259 ret, actual_fsize - 4096);
3260 else if ((actual_fsize & 0x3ff) == 0)
3261 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3264 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3265 actual_fsize, actual_fsize, ret);
3266 target_flags |= old_target_epilogue;
3270 sparc_output_deferred_case_vectors ();
3273 /* Functions for handling argument passing.
3275 For v8 the first six args are normally in registers and the rest are
3276 pushed. Any arg that starts within the first 6 words is at least
3277 partially passed in a register unless its data type forbids.
3279 For v9, the argument registers are laid out as an array of 16 elements
3280 and arguments are added sequentially. The first 6 int args and up to the
3281 first 16 fp args (depending on size) are passed in regs.
3283 Slot Stack Integral Float Float in structure Double Long Double
3284 ---- ----- -------- ----- ------------------ ------ -----------
3285 15 [SP+248] %f31 %f30,%f31 %d30
3286 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3287 13 [SP+232] %f27 %f26,%f27 %d26
3288 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3289 11 [SP+216] %f23 %f22,%f23 %d22
3290 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3291 9 [SP+200] %f19 %f18,%f19 %d18
3292 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3293 7 [SP+184] %f15 %f14,%f15 %d14
3294 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3295 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3296 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3297 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3298 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3299 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3300 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3302 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3304 Integral arguments are always passed as 64 bit quantities appropriately
3307 Passing of floating point values is handled as follows.
3308 If a prototype is in scope:
3309 If the value is in a named argument (i.e. not a stdarg function or a
3310 value not part of the `...') then the value is passed in the appropriate
3312 If the value is part of the `...' and is passed in one of the first 6
3313 slots then the value is passed in the appropriate int reg.
3314 If the value is part of the `...' and is not passed in one of the first 6
3315 slots then the value is passed in memory.
3316 If a prototype is not in scope:
3317 If the value is one of the first 6 arguments the value is passed in the
3318 appropriate integer reg and the appropriate fp reg.
3319 If the value is not one of the first 6 arguments the value is passed in
3320 the appropriate fp reg and in memory.
3323 /* Maximum number of int regs for args. */
3324 #define SPARC_INT_ARG_MAX 6
3325 /* Maximum number of fp regs for args. */
3326 #define SPARC_FP_ARG_MAX 16
3328 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3330 /* Handle the INIT_CUMULATIVE_ARGS macro.
3331 Initialize a variable CUM of type CUMULATIVE_ARGS
3332 for a call to a function whose data type is FNTYPE.
3333 For a library call, FNTYPE is 0. */
3336 init_cumulative_args (cum, fntype, libname, indirect)
3337 CUMULATIVE_ARGS *cum;
3339 tree libname ATTRIBUTE_UNUSED;
3340 int indirect ATTRIBUTE_UNUSED;
3343 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
3344 cum->libcall_p = fntype == 0;
3347 /* Compute the slot number to pass an argument in.
3348 Returns the slot number or -1 if passing on the stack.
3350 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3351 the preceding args and about the function being called.
3352 MODE is the argument's machine mode.
3353 TYPE is the data type of the argument (as a tree).
3354 This is null for libcalls where that information may
3356 NAMED is nonzero if this argument is a named parameter
3357 (otherwise it is an extra parameter matching an ellipsis).
3358 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3359 *PREGNO records the register number to use if scalar type.
3360 *PPADDING records the amount of padding needed in words. */
3363 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
3364 const CUMULATIVE_ARGS *cum;
3365 enum machine_mode mode;
3372 int regbase = (incoming_p
3373 ? SPARC_INCOMING_INT_ARG_FIRST
3374 : SPARC_OUTGOING_INT_ARG_FIRST);
3375 int slotno = cum->words;
3380 if (type != 0 && TREE_ADDRESSABLE (type))
3383 && type != 0 && mode == BLKmode
3384 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
3390 /* MODE is VOIDmode when generating the actual call.
3394 case QImode : case CQImode :
3395 case HImode : case CHImode :
3396 case SImode : case CSImode :
3397 case DImode : case CDImode :
3398 if (slotno >= SPARC_INT_ARG_MAX)
3400 regno = regbase + slotno;
3403 case SFmode : case SCmode :
3404 case DFmode : case DCmode :
3405 case TFmode : case TCmode :
3408 if (slotno >= SPARC_INT_ARG_MAX)
3410 regno = regbase + slotno;
3414 if ((mode == TFmode || mode == TCmode)
3415 && (slotno & 1) != 0)
3416 slotno++, *ppadding = 1;
3417 if (TARGET_FPU && named)
3419 if (slotno >= SPARC_FP_ARG_MAX)
3421 regno = SPARC_FP_ARG_FIRST + slotno * 2;
3427 if (slotno >= SPARC_INT_ARG_MAX)
3429 regno = regbase + slotno;
3435 /* For sparc64, objects requiring 16 byte alignment get it. */
3438 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
3439 slotno++, *ppadding = 1;
3443 || (type && TREE_CODE (type) == UNION_TYPE))
3445 if (slotno >= SPARC_INT_ARG_MAX)
3447 regno = regbase + slotno;
3452 int intregs_p = 0, fpregs_p = 0;
3453 /* The ABI obviously doesn't specify how packed
3454 structures are passed. These are defined to be passed
3455 in int regs if possible, otherwise memory. */
3458 /* First see what kinds of registers we need. */
3459 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3461 if (TREE_CODE (field) == FIELD_DECL)
3463 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3468 if (DECL_PACKED (field))
3472 if (packed_p || !named)
3473 fpregs_p = 0, intregs_p = 1;
3475 /* If all arg slots are filled, then must pass on stack. */
3476 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
3478 /* If there are only int args and all int arg slots are filled,
3479 then must pass on stack. */
3480 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
3482 /* Note that even if all int arg slots are filled, fp members may
3483 still be passed in regs if such regs are available.
3484 *PREGNO isn't set because there may be more than one, it's up
3485 to the caller to compute them. */
3498 /* Handle recursive register counting for structure field layout. */
3500 struct function_arg_record_value_parms
3503 int slotno, named, regbase;
3504 int nregs, intoffset;
3507 static void function_arg_record_value_3
3508 PROTO((int, struct function_arg_record_value_parms *));
3509 static void function_arg_record_value_2
3510 PROTO((tree, int, struct function_arg_record_value_parms *));
3511 static rtx function_arg_record_value
3512 PROTO((tree, enum machine_mode, int, int, int));
3515 function_arg_record_value_1 (type, startbitpos, parms)
3518 struct function_arg_record_value_parms *parms;
3522 /* The ABI obviously doesn't specify how packed structures are
3523 passed. These are defined to be passed in int regs if possible,
3524 otherwise memory. */
3527 /* We need to compute how many registers are needed so we can
3528 allocate the PARALLEL but before we can do that we need to know
3529 whether there are any packed fields. If there are, int regs are
3530 used regardless of whether there are fp values present. */
3531 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3533 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3540 /* Compute how many registers we need. */
3541 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3543 if (TREE_CODE (field) == FIELD_DECL)
3545 int bitpos = startbitpos;
3546 if (DECL_FIELD_BITPOS (field))
3547 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3548 /* ??? FIXME: else assume zero offset. */
3550 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3552 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
3554 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3559 if (parms->intoffset != -1)
3561 int intslots, this_slotno;
3563 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
3565 this_slotno = parms->slotno + parms->intoffset
3568 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3569 intslots = MAX (intslots, 0);
3570 parms->nregs += intslots;
3571 parms->intoffset = -1;
3574 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
3575 If it wasn't true we wouldn't be here. */
3580 if (parms->intoffset == -1)
3581 parms->intoffset = bitpos;
3587 /* Handle recursive structure field register assignment. */
3590 function_arg_record_value_3 (bitpos, parms)
3592 struct function_arg_record_value_parms *parms;
3594 enum machine_mode mode;
3595 int regno, this_slotno, intslots, intoffset;
3598 if (parms->intoffset == -1)
3600 intoffset = parms->intoffset;
3601 parms->intoffset = -1;
3603 intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD;
3604 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
3606 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3610 /* If this is the trailing part of a word, only load that much into
3611 the register. Otherwise load the whole register. Note that in
3612 the latter case we may pick up unwanted bits. It's not a problem
3613 at the moment but may wish to revisit. */
3615 if (intoffset % BITS_PER_WORD != 0)
3617 mode = mode_for_size (BITS_PER_WORD - intoffset%BITS_PER_WORD,
3623 intoffset /= BITS_PER_UNIT;
3626 regno = parms->regbase + this_slotno;
3627 reg = gen_rtx_REG (mode, regno);
3628 XVECEXP (parms->ret, 0, parms->nregs)
3629 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
3632 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
3636 while (intslots > 0);
3640 function_arg_record_value_2 (type, startbitpos, parms)
3643 struct function_arg_record_value_parms *parms;
3648 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3650 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3657 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3659 if (TREE_CODE (field) == FIELD_DECL)
3661 int bitpos = startbitpos;
3662 if (DECL_FIELD_BITPOS (field))
3663 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3664 /* ??? FIXME: else assume zero offset. */
3666 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3668 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
3670 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3675 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
3678 function_arg_record_value_3 (bitpos, parms);
3680 reg = gen_rtx_REG (DECL_MODE (field),
3681 (SPARC_FP_ARG_FIRST + this_slotno * 2
3682 + (DECL_MODE (field) == SFmode
3683 && (bitpos & 32) != 0)));
3684 XVECEXP (parms->ret, 0, parms->nregs)
3685 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3686 GEN_INT (bitpos / BITS_PER_UNIT));
3691 if (parms->intoffset == -1)
3692 parms->intoffset = bitpos;
3699 function_arg_record_value (type, mode, slotno, named, regbase)
3701 enum machine_mode mode;
3702 int slotno, named, regbase;
3704 HOST_WIDE_INT typesize = int_size_in_bytes (type);
3705 struct function_arg_record_value_parms parms;
3708 parms.ret = NULL_RTX;
3709 parms.slotno = slotno;
3710 parms.named = named;
3711 parms.regbase = regbase;
3713 /* Compute how many registers we need. */
3715 parms.intoffset = 0;
3716 function_arg_record_value_1 (type, 0, &parms);
3718 if (parms.intoffset != -1)
3720 int intslots, this_slotno;
3722 intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1)
3724 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
3726 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3727 intslots = MAX (intslots, 0);
3729 parms.nregs += intslots;
3731 nregs = parms.nregs;
3733 /* Allocate the vector and handle some annoying special cases. */
3736 /* ??? Empty structure has no value? Duh? */
3739 /* Though there's nothing really to store, return a word register
3740 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
3741 leads to breakage due to the fact that there are zero bytes to
3743 return gen_rtx_REG (mode, regbase);
3747 /* ??? C++ has structures with no fields, and yet a size. Give up
3748 for now and pass everything back in integer registers. */
3749 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3751 if (nregs + slotno > SPARC_INT_ARG_MAX)
3752 nregs = SPARC_INT_ARG_MAX - slotno;
3757 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
3759 /* Fill in the entries. */
3761 parms.intoffset = 0;
3762 function_arg_record_value_2 (type, 0, &parms);
3763 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
3765 if (parms.nregs != nregs)
3771 /* Handle the FUNCTION_ARG macro.
3772 Determine where to put an argument to a function.
3773 Value is zero to push the argument on the stack,
3774 or a hard register in which to store the argument.
3776 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3777 the preceding args and about the function being called.
3778 MODE is the argument's machine mode.
3779 TYPE is the data type of the argument (as a tree).
3780 This is null for libcalls where that information may
3782 NAMED is nonzero if this argument is a named parameter
3783 (otherwise it is an extra parameter matching an ellipsis).
3784 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
3787 function_arg (cum, mode, type, named, incoming_p)
3788 const CUMULATIVE_ARGS *cum;
3789 enum machine_mode mode;
3794 int regbase = (incoming_p
3795 ? SPARC_INCOMING_INT_ARG_FIRST
3796 : SPARC_OUTGOING_INT_ARG_FIRST);
3797 int slotno, regno, padding;
3800 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
3808 reg = gen_rtx_REG (mode, regno);
3812 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
3813 but also have the slot allocated for them.
3814 If no prototype is in scope fp values in register slots get passed
3815 in two places, either fp regs and int regs or fp regs and memory. */
3816 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
3817 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3818 && SPARC_FP_REG_P (regno))
3820 reg = gen_rtx_REG (mode, regno);
3821 if (cum->prototype_p || cum->libcall_p)
3823 /* "* 2" because fp reg numbers are recorded in 4 byte
3826 /* ??? This will cause the value to be passed in the fp reg and
3827 in the stack. When a prototype exists we want to pass the
3828 value in the reg but reserve space on the stack. That's an
3829 optimization, and is deferred [for a bit]. */
3830 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
3831 return gen_rtx_PARALLEL (mode,
3833 gen_rtx_EXPR_LIST (VOIDmode,
3834 NULL_RTX, const0_rtx),
3835 gen_rtx_EXPR_LIST (VOIDmode,
3839 /* ??? It seems that passing back a register even when past
3840 the area declared by REG_PARM_STACK_SPACE will allocate
3841 space appropriately, and will not copy the data onto the
3842 stack, exactly as we desire.
3844 This is due to locate_and_pad_parm being called in
3845 expand_call whenever reg_parm_stack_space > 0, which
3846 while benefical to our example here, would seem to be
3847 in error from what had been intended. Ho hum... -- r~ */
3855 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
3859 /* On incoming, we don't need to know that the value
3860 is passed in %f0 and %i0, and it confuses other parts
3861 causing needless spillage even on the simplest cases. */
3865 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
3866 + (regno - SPARC_FP_ARG_FIRST) / 2);
3868 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
3869 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
3871 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
3875 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
3876 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
3877 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
3881 else if (type && TREE_CODE (type) == RECORD_TYPE)
3883 /* Structures up to 16 bytes in size are passed in arg slots on the
3884 stack and are promoted to registers where possible. */
3886 if (int_size_in_bytes (type) > 16)
3887 abort (); /* shouldn't get here */
3889 return function_arg_record_value (type, mode, slotno, named, regbase);
3891 else if (type && TREE_CODE (type) == UNION_TYPE)
3893 enum machine_mode mode;
3894 int bytes = int_size_in_bytes (type);
3899 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
3900 reg = gen_rtx_REG (mode, regno);
3904 /* Scalar or complex int. */
3905 reg = gen_rtx_REG (mode, regno);
3911 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
3912 For an arg passed partly in registers and partly in memory,
3913 this is the number of registers used.
3914 For args passed entirely in registers or entirely in memory, zero.
3916 Any arg that starts in the first 6 regs but won't entirely fit in them
3917 needs partial registers on v8. On v9, structures with integer
3918 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
3919 values that begin in the last fp reg [where "last fp reg" varies with the
3920 mode] will be split between that reg and memory. */
3923 function_arg_partial_nregs (cum, mode, type, named)
3924 const CUMULATIVE_ARGS *cum;
3925 enum machine_mode mode;
3929 int slotno, regno, padding;
3931 /* We pass 0 for incoming_p here, it doesn't matter. */
3932 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
3939 if ((slotno + (mode == BLKmode
3940 ? ROUND_ADVANCE (int_size_in_bytes (type))
3941 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
3942 > NPARM_REGS (SImode))
3943 return NPARM_REGS (SImode) - slotno;
3948 if (type && AGGREGATE_TYPE_P (type))
3950 int size = int_size_in_bytes (type);
3951 int align = TYPE_ALIGN (type);
3954 slotno += slotno & 1;
3955 if (size > 8 && size <= 16
3956 && slotno == SPARC_INT_ARG_MAX - 1)
3959 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
3960 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3963 if (GET_MODE_ALIGNMENT (mode) == 128)
3965 slotno += slotno & 1;
3966 if (slotno == SPARC_INT_ARG_MAX - 2)
3971 if (slotno == SPARC_INT_ARG_MAX - 1)
3975 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3977 if (GET_MODE_ALIGNMENT (mode) == 128)
3978 slotno += slotno & 1;
3979 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
3987 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
3988 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
3989 quad-precision floats by invisible reference.
3990 v9: Aggregates greater than 16 bytes are passed by reference.
3991 For Pascal, also pass arrays by reference. */
3994 function_arg_pass_by_reference (cum, mode, type, named)
3995 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3996 enum machine_mode mode;
3998 int named ATTRIBUTE_UNUSED;
4002 return ((type && AGGREGATE_TYPE_P (type))
4003 || mode == TFmode || mode == TCmode);
4007 return ((type && TREE_CODE (type) == ARRAY_TYPE)
4008 /* Consider complex values as aggregates, so care for TCmode. */
4009 || GET_MODE_SIZE (mode) > 16
4010 || (type && AGGREGATE_TYPE_P (type)
4011 && int_size_in_bytes (type) > 16));
4015 /* Handle the FUNCTION_ARG_ADVANCE macro.
4016 Update the data in CUM to advance over an argument
4017 of mode MODE and data type TYPE.
4018 TYPE is null for libcalls where that information may not be available. */
4021 function_arg_advance (cum, mode, type, named)
4022 CUMULATIVE_ARGS *cum;
4023 enum machine_mode mode;
4027 int slotno, regno, padding;
4029 /* We pass 0 for incoming_p here, it doesn't matter. */
4030 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4032 /* If register required leading padding, add it. */
4034 cum->words += padding;
4038 cum->words += (mode != BLKmode
4039 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4040 : ROUND_ADVANCE (int_size_in_bytes (type)));
4044 if (type && AGGREGATE_TYPE_P (type))
4046 int size = int_size_in_bytes (type);
4050 else if (size <= 16)
4052 else /* passed by reference */
4055 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
4059 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4061 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
4065 cum->words += (mode != BLKmode
4066 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4067 : ROUND_ADVANCE (int_size_in_bytes (type)));
4072 /* Handle the FUNCTION_ARG_PADDING macro.
4073 For the 64 bit ABI structs are always stored left shifted in their
4077 function_arg_padding (mode, type)
4078 enum machine_mode mode;
4081 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
4084 /* This is the default definition. */
4085 return (! BYTES_BIG_ENDIAN
4088 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
4089 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
4090 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
4091 ? downward : upward));
4094 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
4095 For v9, function return values are subject to the same rules as arguments,
4096 except that up to 32-bytes may be returned in registers. */
4099 function_value (type, mode, incoming_p)
4101 enum machine_mode mode;
4105 int regbase = (incoming_p
4106 ? SPARC_OUTGOING_INT_ARG_FIRST
4107 : SPARC_INCOMING_INT_ARG_FIRST);
4109 if (TARGET_ARCH64 && type)
4111 if (TREE_CODE (type) == RECORD_TYPE)
4113 /* Structures up to 32 bytes in size are passed in registers,
4114 promoted to fp registers where possible. */
4116 if (int_size_in_bytes (type) > 32)
4117 abort (); /* shouldn't get here */
4119 return function_arg_record_value (type, mode, 0, 1, regbase);
4121 else if (TREE_CODE (type) == UNION_TYPE)
4123 int bytes = int_size_in_bytes (type);
4128 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4133 regno = BASE_RETURN_VALUE_REG (mode);
4135 regno = BASE_OUTGOING_VALUE_REG (mode);
4137 return gen_rtx_REG (mode, regno);
4140 /* Do what is necessary for `va_start'. The argument is ignored.
4142 We look at the current function to determine if stdarg or varargs
4143 is used and return the address of the first unnamed parameter. */
4146 sparc_builtin_saveregs (arglist)
4147 tree arglist ATTRIBUTE_UNUSED;
4149 int first_reg = current_function_args_info.words;
4153 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
4154 emit_move_insn (gen_rtx_MEM (word_mode,
4155 gen_rtx_PLUS (Pmode,
4157 GEN_INT (STACK_POINTER_OFFSET
4158 + UNITS_PER_WORD * regno))),
4159 gen_rtx_REG (word_mode,
4160 BASE_INCOMING_ARG_REG (word_mode) + regno));
4162 address = gen_rtx_PLUS (Pmode,
4164 GEN_INT (STACK_POINTER_OFFSET
4165 + UNITS_PER_WORD * first_reg));
4167 if (flag_check_memory_usage
4168 && first_reg < NPARM_REGS (word_mode))
4169 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4171 GEN_INT (UNITS_PER_WORD
4172 * (NPARM_REGS (word_mode) - first_reg)),
4173 TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW),
4174 TYPE_MODE (integer_type_node));
4179 /* Return the string to output a conditional branch to LABEL, which is
4180 the operand number of the label. OP is the conditional expression.
4181 XEXP (OP, 0) is assumed to be a condition code register (integer or
4182 floating point) and its mode specifies what kind of comparison we made.
4184 REVERSED is non-zero if we should reverse the sense of the comparison.
4186 ANNUL is non-zero if we should generate an annulling branch.
4188 NOOP is non-zero if we have to follow this branch by a noop.
4190 INSN, if set, is the insn. */
4193 output_cbranch (op, label, reversed, annul, noop, insn)
4196 int reversed, annul, noop;
4199 static char string[32];
4200 enum rtx_code code = GET_CODE (op);
4201 rtx cc_reg = XEXP (op, 0);
4202 enum machine_mode mode = GET_MODE (cc_reg);
4203 static char v8_labelno[] = "%lX";
4204 static char v9_icc_labelno[] = "%%icc, %lX";
4205 static char v9_xcc_labelno[] = "%%xcc, %lX";
4206 static char v9_fcc_labelno[] = "%%fccX, %lY";
4208 int labeloff, spaces = 8;
4210 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
4211 Because there is currently no concept of pre-delay slots, we can fix
4212 this only by always emitting a nop before a floating point branch. */
4214 if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9)
4215 strcpy (string, "nop\n\t");
4219 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4221 && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE))
4222 code = reverse_condition (code), reversed = 0;
4224 /* Start by writing the branch condition. */
4228 if (mode == CCFPmode || mode == CCFPEmode)
4230 strcat (string, "fbne");
4235 strcpy (string, "bne");
4241 if (mode == CCFPmode || mode == CCFPEmode)
4243 strcat (string, "fbe");
4248 strcpy (string, "be");
4254 if (mode == CCFPmode || mode == CCFPEmode)
4257 strcat (string, "fbul");
4259 strcat (string, "fbge");
4262 else if (mode == CC_NOOVmode)
4264 strcpy (string, "bpos");
4269 strcpy (string, "bge");
4275 if (mode == CCFPmode || mode == CCFPEmode)
4279 strcat (string, "fbule");
4284 strcat (string, "fbg");
4290 strcpy (string, "bg");
4296 if (mode == CCFPmode || mode == CCFPEmode)
4299 strcat (string, "fbug");
4301 strcat (string, "fble");
4306 strcpy (string, "ble");
4312 if (mode == CCFPmode || mode == CCFPEmode)
4316 strcat (string, "fbuge");
4321 strcat (string, "fbl");
4325 else if (mode == CC_NOOVmode)
4327 strcpy (string, "bneg");
4332 strcpy (string, "bl");
4338 strcpy (string, "bgeu");
4343 strcpy (string, "bgu");
4348 strcpy (string, "bleu");
4353 strcpy (string, "blu");
4361 /* Now add the annulling, the label, and a possible noop. */
4364 strcat (string, ",a");
4371 labelno = v8_labelno;
4377 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
4380 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4385 if (mode == CCFPmode || mode == CCFPEmode)
4388 labelno = v9_fcc_labelno;
4389 /* Set the char indicating the number of the fcc reg to use. */
4390 labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
4392 else if (mode == CCXmode || mode == CCX_NOOVmode)
4393 labelno = v9_xcc_labelno;
4395 labelno = v9_icc_labelno;
4397 /* Set the char indicating the number of the operand containing the
4399 labelno[labeloff] = label + '0';
4401 strcat (string, "\t");
4403 strcat (string, " ");
4404 strcat (string, labelno);
4407 strcat (string, "\n\tnop");
4412 /* Return the string to output a conditional branch to LABEL, testing
4413 register REG. LABEL is the operand number of the label; REG is the
4414 operand number of the reg. OP is the conditional expression. The mode
4415 of REG says what kind of comparison we made.
4417 REVERSED is non-zero if we should reverse the sense of the comparison.
4419 ANNUL is non-zero if we should generate an annulling branch.
4421 NOOP is non-zero if we have to follow this branch by a noop. */
4424 output_v9branch (op, reg, label, reversed, annul, noop, insn)
4427 int reversed, annul, noop;
4430 static char string[20];
4431 enum rtx_code code = GET_CODE (op);
4432 enum machine_mode mode = GET_MODE (XEXP (op, 0));
4433 static char labelno[] = "%X, %lX";
4437 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4439 code = reverse_condition (code), reversed = 0;
4441 /* Only 64 bit versions of these instructions exist. */
4445 /* Start by writing the branch condition. */
4450 strcpy (string, "brnz");
4455 strcpy (string, "brz");
4460 strcpy (string, "brgez");
4465 strcpy (string, "brlz");
4470 strcpy (string, "brlez");
4475 strcpy (string, "brgz");
4483 /* Now add the annulling, reg, label, and nop. */
4486 strcat (string, ",a");
4490 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
4493 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4497 labelno[1] = reg + '0';
4498 labelno[6] = label + '0';
4500 strcat (string, "\t");
4502 strcat (string, " ");
4503 strcat (string, labelno);
4506 strcat (string, "\n\tnop");
4511 /* Renumber registers in delay slot. Replace registers instead of
4512 renumbering because they may be shared.
4514 This does not handle instructions other than move. */
4517 epilogue_renumber (where)
4521 enum rtx_code code = GET_CODE (x);
4526 *where = x = copy_rtx (x);
4527 epilogue_renumber (&XEXP (x, 0));
4532 int regno = REGNO (x);
4533 if (regno > 8 && regno < 24)
4535 if (regno >= 24 && regno < 32)
4536 *where = gen_rtx_REG (GET_MODE (x), regno - 16);
4551 epilogue_renumber (&XEXP (x, 1));
4554 epilogue_renumber (&XEXP (x, 0));
4563 /* Output assembler code to return from a function. */
4566 output_return (operands)
4569 rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
4573 operands[0] = leaf_label;
4576 else if (leaf_function)
4578 /* No delay slot in a leaf function. */
4582 /* If we didn't allocate a frame pointer for the current function,
4583 the stack pointer might have been adjusted. Output code to
4586 operands[0] = GEN_INT (actual_fsize);
4588 /* Use sub of negated value in first two cases instead of add to
4589 allow actual_fsize == 4096. */
4591 if (actual_fsize <= 4096)
4593 if (SKIP_CALLERS_UNIMP_P)
4594 return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
4596 return "retl\n\tsub\t%%sp, -%0, %%sp";
4598 else if (actual_fsize <= 8192)
4600 operands[0] = GEN_INT (actual_fsize - 4096);
4601 if (SKIP_CALLERS_UNIMP_P)
4602 return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
4604 return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
4606 else if (SKIP_CALLERS_UNIMP_P)
4608 if ((actual_fsize & 0x3ff) != 0)
4609 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
4611 return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
4615 if ((actual_fsize & 0x3ff) != 0)
4616 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4618 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4625 epilogue_renumber (&SET_DEST (PATTERN (delay)));
4626 epilogue_renumber (&SET_SRC (PATTERN (delay)));
4628 if (SKIP_CALLERS_UNIMP_P)
4629 return "return\t%%i7+12%#";
4631 return "return\t%%i7+8%#";
4637 if (SKIP_CALLERS_UNIMP_P)
4638 return "jmp\t%%i7+12\n\trestore";
4640 return "ret\n\trestore";
4644 /* Leaf functions and non-leaf functions have different needs. */
4647 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
4650 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
4652 static int *reg_alloc_orders[] = {
4653 reg_leaf_alloc_order,
4654 reg_nonleaf_alloc_order};
4657 order_regs_for_local_alloc ()
4659 static int last_order_nonleaf = 1;
4661 if (regs_ever_live[15] != last_order_nonleaf)
4663 last_order_nonleaf = !last_order_nonleaf;
4664 bcopy ((char *) reg_alloc_orders[last_order_nonleaf],
4665 (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int));
4669 /* Return 1 if REG and MEM are legitimate enough to allow the various
4670 mem<-->reg splits to be run. */
4673 sparc_splitdi_legitimate(reg, mem)
4677 rtx addr_part = XEXP (mem, 0);
4679 /* Punt if we are here by mistake. */
4680 if (! reload_completed)
4683 /* We must have an offsettable memory reference. */
4684 if (! offsettable_memref_p (mem))
4687 /* If we have legitimate args for ldd/std, we do not want
4688 the split to happen. */
4689 if ((REGNO (reg) % 2) == 0
4690 && mem_min_alignment (mem, 8))
4697 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4698 This makes them candidates for using ldd and std insns.
4700 Note reg1 and reg2 *must* be hard registers. */
4703 registers_ok_for_ldd_peep (reg1, reg2)
4706 /* We might have been passed a SUBREG. */
4707 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
4710 if (REGNO (reg1) % 2 != 0)
4713 /* Integer ldd is deprecated in SPARC V9 */
4714 if (TARGET_V9 && REGNO (reg1) < 32)
4717 return (REGNO (reg1) == REGNO (reg2) - 1);
4720 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
4723 This can only happen when addr1 and addr2 are consecutive memory
4724 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
4725 64 bit boundary (addr1 % 8 == 0).
4727 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
4728 registers are assumed to *never* be properly aligned and are
4731 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
4732 need only check that the offset for addr1 % 8 == 0. */
4735 addrs_ok_for_ldd_peep (addr1, addr2)
4740 /* Extract a register number and offset (if used) from the first addr. */
4741 if (GET_CODE (addr1) == PLUS)
4743 /* If not a REG, return zero. */
4744 if (GET_CODE (XEXP (addr1, 0)) != REG)
4748 reg1 = REGNO (XEXP (addr1, 0));
4749 /* The offset must be constant! */
4750 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
4752 offset1 = INTVAL (XEXP (addr1, 1));
4755 else if (GET_CODE (addr1) != REG)
4759 reg1 = REGNO (addr1);
4760 /* This was a simple (mem (reg)) expression. Offset is 0. */
4764 /* Make sure the second address is a (mem (plus (reg) (const_int). */
4765 if (GET_CODE (addr2) != PLUS)
4768 if (GET_CODE (XEXP (addr2, 0)) != REG
4769 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
4772 /* Only %fp and %sp are allowed. Additionally both addresses must
4773 use the same register. */
4774 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
4777 if (reg1 != REGNO (XEXP (addr2, 0)))
4780 /* The first offset must be evenly divisible by 8 to ensure the
4781 address is 64 bit aligned. */
4782 if (offset1 % 8 != 0)
4785 /* The offset for the second addr must be 4 more than the first addr. */
4786 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
4789 /* All the tests passed. addr1 and addr2 are valid for ldd and std
4794 /* Return 1 if reg is a pseudo, or is the first register in
4795 a hard register pair. This makes it a candidate for use in
4796 ldd and std insns. */
4799 register_ok_for_ldd (reg)
4802 /* We might have been passed a SUBREG. */
4803 if (GET_CODE (reg) != REG)
4806 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
4807 return (REGNO (reg) % 2 == 0);
4812 /* Print operand X (an rtx) in assembler syntax to file FILE.
4813 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4814 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4817 print_operand (file, x, code)
4825 /* Output a 'nop' if there's nothing for the delay slot. */
4826 if (dbr_sequence_length () == 0)
4827 fputs ("\n\t nop", file);
4830 /* Output an annul flag if there's nothing for the delay slot and we
4831 are optimizing. This is always used with '(' below. */
4832 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
4833 this is a dbx bug. So, we only do this when optimizing. */
4834 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
4835 Always emit a nop in case the next instruction is a branch. */
4836 if (dbr_sequence_length () == 0
4837 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
4841 /* Output a 'nop' if there's nothing for the delay slot and we are
4842 not optimizing. This is always used with '*' above. */
4843 if (dbr_sequence_length () == 0
4844 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
4845 fputs ("\n\t nop", file);
4848 /* Output the Embedded Medium/Anywhere code model base register. */
4849 fputs (EMBMEDANY_BASE_REG, file);
4852 /* Print out what we are using as the frame pointer. This might
4853 be %fp, or might be %sp+offset. */
4854 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
4855 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
4858 /* Adjust the operand to take into account a RESTORE operation. */
4859 if (GET_CODE (x) == CONST_INT)
4861 else if (GET_CODE (x) != REG)
4862 output_operand_lossage ("Invalid %%Y operand");
4863 else if (REGNO (x) < 8)
4864 fputs (reg_names[REGNO (x)], file);
4865 else if (REGNO (x) >= 24 && REGNO (x) < 32)
4866 fputs (reg_names[REGNO (x)-16], file);
4868 output_operand_lossage ("Invalid %%Y operand");
4871 /* Print out the low order register name of a register pair. */
4872 if (WORDS_BIG_ENDIAN)
4873 fputs (reg_names[REGNO (x)+1], file);
4875 fputs (reg_names[REGNO (x)], file);
4878 /* Print out the high order register name of a register pair. */
4879 if (WORDS_BIG_ENDIAN)
4880 fputs (reg_names[REGNO (x)], file);
4882 fputs (reg_names[REGNO (x)+1], file);
4885 /* Print out the second register name of a register pair or quad.
4886 I.e., R (%o0) => %o1. */
4887 fputs (reg_names[REGNO (x)+1], file);
4890 /* Print out the third register name of a register quad.
4891 I.e., S (%o0) => %o2. */
4892 fputs (reg_names[REGNO (x)+2], file);
4895 /* Print out the fourth register name of a register quad.
4896 I.e., T (%o0) => %o3. */
4897 fputs (reg_names[REGNO (x)+3], file);
4900 /* Print a condition code register. */
4901 if (REGNO (x) == SPARC_ICC_REG)
4903 /* We don't handle CC[X]_NOOVmode because they're not supposed
4905 if (GET_MODE (x) == CCmode)
4906 fputs ("%icc", file);
4907 else if (GET_MODE (x) == CCXmode)
4908 fputs ("%xcc", file);
4913 /* %fccN register */
4914 fputs (reg_names[REGNO (x)], file);
4917 /* Print the operand's address only. */
4918 output_address (XEXP (x, 0));
4921 /* In this case we need a register. Use %g0 if the
4922 operand is const0_rtx. */
4924 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
4926 fputs ("%g0", file);
4933 switch (GET_CODE (x))
4935 case IOR: fputs ("or", file); break;
4936 case AND: fputs ("and", file); break;
4937 case XOR: fputs ("xor", file); break;
4938 default: output_operand_lossage ("Invalid %%A operand");
4943 switch (GET_CODE (x))
4945 case IOR: fputs ("orn", file); break;
4946 case AND: fputs ("andn", file); break;
4947 case XOR: fputs ("xnor", file); break;
4948 default: output_operand_lossage ("Invalid %%B operand");
4952 /* These are used by the conditional move instructions. */
4956 enum rtx_code rc = (code == 'c'
4957 ? reverse_condition (GET_CODE (x))
4961 case NE: fputs ("ne", file); break;
4962 case EQ: fputs ("e", file); break;
4963 case GE: fputs ("ge", file); break;
4964 case GT: fputs ("g", file); break;
4965 case LE: fputs ("le", file); break;
4966 case LT: fputs ("l", file); break;
4967 case GEU: fputs ("geu", file); break;
4968 case GTU: fputs ("gu", file); break;
4969 case LEU: fputs ("leu", file); break;
4970 case LTU: fputs ("lu", file); break;
4971 default: output_operand_lossage (code == 'c'
4972 ? "Invalid %%c operand"
4973 : "Invalid %%C operand");
4978 /* These are used by the movr instruction pattern. */
4982 enum rtx_code rc = (code == 'd'
4983 ? reverse_condition (GET_CODE (x))
4987 case NE: fputs ("ne", file); break;
4988 case EQ: fputs ("e", file); break;
4989 case GE: fputs ("gez", file); break;
4990 case LT: fputs ("lz", file); break;
4991 case LE: fputs ("lez", file); break;
4992 case GT: fputs ("gz", file); break;
4993 default: output_operand_lossage (code == 'd'
4994 ? "Invalid %%d operand"
4995 : "Invalid %%D operand");
5002 /* Print a sign-extended character. */
5003 int i = INTVAL (x) & 0xff;
5006 fprintf (file, "%d", i);
5011 /* Operand must be a MEM; write its address. */
5012 if (GET_CODE (x) != MEM)
5013 output_operand_lossage ("Invalid %%f operand");
5014 output_address (XEXP (x, 0));
5018 /* Do nothing special. */
5022 /* Undocumented flag. */
5023 output_operand_lossage ("invalid operand output code");
5026 if (GET_CODE (x) == REG)
5027 fputs (reg_names[REGNO (x)], file);
5028 else if (GET_CODE (x) == MEM)
5031 /* Poor Sun assembler doesn't understand absolute addressing. */
5032 if (CONSTANT_P (XEXP (x, 0))
5033 && ! TARGET_LIVE_G0)
5034 fputs ("%g0+", file);
5035 output_address (XEXP (x, 0));
5038 else if (GET_CODE (x) == HIGH)
5040 fputs ("%hi(", file);
5041 output_addr_const (file, XEXP (x, 0));
5044 else if (GET_CODE (x) == LO_SUM)
5046 print_operand (file, XEXP (x, 0), 0);
5047 if (TARGET_CM_MEDMID)
5048 fputs ("+%l44(", file);
5050 fputs ("+%lo(", file);
5051 output_addr_const (file, XEXP (x, 1));
5054 else if (GET_CODE (x) == CONST_DOUBLE
5055 && (GET_MODE (x) == VOIDmode
5056 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
5058 if (CONST_DOUBLE_HIGH (x) == 0)
5059 fprintf (file, "%u", CONST_DOUBLE_LOW (x));
5060 else if (CONST_DOUBLE_HIGH (x) == -1
5061 && CONST_DOUBLE_LOW (x) < 0)
5062 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
5064 output_operand_lossage ("long long constant not a valid immediate operand");
5066 else if (GET_CODE (x) == CONST_DOUBLE)
5067 output_operand_lossage ("floating point constant not a valid immediate operand");
5068 else { output_addr_const (file, x); }
5071 /* This function outputs assembler code for VALUE to FILE, where VALUE is
5072 a 64 bit (DImode) value. */
5074 /* ??? If there is a 64 bit counterpart to .word that the assembler
5075 understands, then using that would simply this code greatly. */
5076 /* ??? We only output .xword's for symbols and only then in environments
5077 where the assembler can handle them. */
5080 output_double_int (file, value)
5084 if (GET_CODE (value) == CONST_INT)
5086 /* ??? This has endianness issues. */
5087 #if HOST_BITS_PER_WIDE_INT == 64
5088 HOST_WIDE_INT xword = INTVAL (value);
5089 HOST_WIDE_INT high, low;
5091 high = (xword >> 32) & 0xffffffff;
5092 low = xword & 0xffffffff;
5093 ASM_OUTPUT_INT (file, GEN_INT (high));
5094 ASM_OUTPUT_INT (file, GEN_INT (low));
5096 if (INTVAL (value) < 0)
5097 ASM_OUTPUT_INT (file, constm1_rtx);
5099 ASM_OUTPUT_INT (file, const0_rtx);
5100 ASM_OUTPUT_INT (file, value);
5103 else if (GET_CODE (value) == CONST_DOUBLE)
5105 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value)));
5106 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value)));
5108 else if (GET_CODE (value) == SYMBOL_REF
5109 || GET_CODE (value) == CONST
5110 || GET_CODE (value) == PLUS
5111 || (TARGET_ARCH64 &&
5112 (GET_CODE (value) == LABEL_REF
5113 || GET_CODE (value) == CODE_LABEL
5114 || GET_CODE (value) == MINUS)))
5116 if (!TARGET_V9 || TARGET_CM_MEDLOW)
5118 ASM_OUTPUT_INT (file, const0_rtx);
5119 ASM_OUTPUT_INT (file, value);
5123 fprintf (file, "\t%s\t", ASM_LONGLONG);
5124 output_addr_const (file, value);
5125 fprintf (file, "\n");
5132 /* Return the value of a code used in the .proc pseudo-op that says
5133 what kind of result this function returns. For non-C types, we pick
5134 the closest C type. */
5136 #ifndef CHAR_TYPE_SIZE
5137 #define CHAR_TYPE_SIZE BITS_PER_UNIT
5140 #ifndef SHORT_TYPE_SIZE
5141 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5144 #ifndef INT_TYPE_SIZE
5145 #define INT_TYPE_SIZE BITS_PER_WORD
5148 #ifndef LONG_TYPE_SIZE
5149 #define LONG_TYPE_SIZE BITS_PER_WORD
5152 #ifndef LONG_LONG_TYPE_SIZE
5153 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5156 #ifndef FLOAT_TYPE_SIZE
5157 #define FLOAT_TYPE_SIZE BITS_PER_WORD
5160 #ifndef DOUBLE_TYPE_SIZE
5161 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5164 #ifndef LONG_DOUBLE_TYPE_SIZE
5165 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5169 sparc_type_code (type)
5172 register unsigned long qualifiers = 0;
5173 register unsigned shift;
5175 /* Only the first 30 bits of the qualifier are valid. We must refrain from
5176 setting more, since some assemblers will give an error for this. Also,
5177 we must be careful to avoid shifts of 32 bits or more to avoid getting
5178 unpredictable results. */
5180 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
5182 switch (TREE_CODE (type))
5188 qualifiers |= (3 << shift);
5193 qualifiers |= (2 << shift);
5197 case REFERENCE_TYPE:
5199 qualifiers |= (1 << shift);
5203 return (qualifiers | 8);
5206 case QUAL_UNION_TYPE:
5207 return (qualifiers | 9);
5210 return (qualifiers | 10);
5213 return (qualifiers | 16);
5216 /* If this is a range type, consider it to be the underlying
5218 if (TREE_TYPE (type) != 0)
5221 /* Carefully distinguish all the standard types of C,
5222 without messing up if the language is not C. We do this by
5223 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
5224 look at both the names and the above fields, but that's redundant.
5225 Any type whose size is between two C types will be considered
5226 to be the wider of the two types. Also, we do not have a
5227 special code to use for "long long", so anything wider than
5228 long is treated the same. Note that we can't distinguish
5229 between "int" and "long" in this code if they are the same
5230 size, but that's fine, since neither can the assembler. */
5232 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
5233 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
5235 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
5236 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
5238 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
5239 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
5242 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
5245 /* If this is a range type, consider it to be the underlying
5247 if (TREE_TYPE (type) != 0)
5250 /* Carefully distinguish all the standard types of C,
5251 without messing up if the language is not C. */
5253 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
5254 return (qualifiers | 6);
5257 return (qualifiers | 7);
5259 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
5260 /* ??? We need to distinguish between double and float complex types,
5261 but I don't know how yet because I can't reach this code from
5262 existing front-ends. */
5263 return (qualifiers | 7); /* Who knows? */
5265 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
5266 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
5267 case FILE_TYPE: /* GNU Pascal FILE type. */
5268 case SET_TYPE: /* GNU Pascal SET type. */
5269 case LANG_TYPE: /* ? */
5273 abort (); /* Not a type! */
5280 /* Nested function support. */
5282 /* Emit RTL insns to initialize the variable parts of a trampoline.
5283 FNADDR is an RTX for the address of the function's pure code.
5284 CXT is an RTX for the static chain value for the function.
5286 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
5287 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
5288 (to store insns). This is a bit excessive. Perhaps a different
5289 mechanism would be better here.
5291 Emit enough FLUSH insns to synchronize the data and instruction caches. */
5294 sparc_initialize_trampoline (tramp, fnaddr, cxt)
5295 rtx tramp, fnaddr, cxt;
5297 /* SPARC 32 bit trampoline:
5300 sethi %hi(static), %g2
5302 or %g2, %lo(static), %g2
5304 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
5305 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
5308 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
5309 expand_binop (SImode, ior_optab,
5310 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
5311 size_int (10), 0, 1),
5312 GEN_INT (0x03000000),
5313 NULL_RTX, 1, OPTAB_DIRECT));
5315 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5316 expand_binop (SImode, ior_optab,
5317 expand_shift (RSHIFT_EXPR, SImode, cxt,
5318 size_int (10), 0, 1),
5319 GEN_INT (0x05000000),
5320 NULL_RTX, 1, OPTAB_DIRECT));
5322 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5323 expand_binop (SImode, ior_optab,
5324 expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX),
5325 GEN_INT (0x81c06000),
5326 NULL_RTX, 1, OPTAB_DIRECT));
5328 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5329 expand_binop (SImode, ior_optab,
5330 expand_and (cxt, GEN_INT (0x3ff), NULL_RTX),
5331 GEN_INT (0x8410a000),
5332 NULL_RTX, 1, OPTAB_DIRECT));
5334 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
5335 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
5336 aligned on a 16 byte boundary so one flush clears it all. */
5337 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5338 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
5339 plus_constant (tramp, 8)))));
5342 /* The 64 bit version is simpler because it makes more sense to load the
5343 values as "immediate" data out of the trampoline. It's also easier since
5344 we can read the PC without clobbering a register. */
5347 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
5348 rtx tramp, fnaddr, cxt;
5358 emit_move_insn (gen_rtx_MEM (SImode, tramp),
5359 GEN_INT (0x83414000));
5360 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5361 GEN_INT (0xca586018));
5362 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5363 GEN_INT (0x81c04000));
5364 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5365 GEN_INT (0xca586010));
5366 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
5367 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 20)), fnaddr);
5368 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, tramp))));
5369 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5370 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
5373 /* Subroutines to support a flat (single) register window calling
5376 /* Single-register window sparc stack frames look like:
5378 Before call After call
5379 +-----------------------+ +-----------------------+
5381 mem | caller's temps. | | caller's temps. |
5383 +-----------------------+ +-----------------------+
5385 | arguments on stack. | | arguments on stack. |
5387 +-----------------------+FP+92->+-----------------------+
5388 | 6 words to save | | 6 words to save |
5389 | arguments passed | | arguments passed |
5390 | in registers, even | | in registers, even |
5391 | if not passed. | | if not passed. |
5392 SP+68->+-----------------------+FP+68->+-----------------------+
5393 | 1 word struct addr | | 1 word struct addr |
5394 +-----------------------+FP+64->+-----------------------+
5396 | 16 word reg save area | | 16 word reg save area |
5398 SP->+-----------------------+ FP->+-----------------------+
5400 | fp/alu reg moves |
5401 FP-16->+-----------------------+
5405 +-----------------------+
5407 | fp register save |
5409 +-----------------------+
5411 | gp register save |
5413 +-----------------------+
5415 | alloca allocations |
5417 +-----------------------+
5419 | arguments on stack |
5421 SP+92->+-----------------------+
5423 | arguments passed |
5424 | in registers, even |
5425 low | if not passed. |
5426 memory SP+68->+-----------------------+
5427 | 1 word struct addr |
5428 SP+64->+-----------------------+
5430 I 16 word reg save area |
5432 SP->+-----------------------+ */
5434 /* Structure to be filled in by sparc_flat_compute_frame_size with register
5435 save masks, and offsets for the current function. */
5437 struct sparc_frame_info
5439 unsigned long total_size; /* # bytes that the entire frame takes up. */
5440 unsigned long var_size; /* # bytes that variables take up. */
5441 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5442 unsigned long extra_size; /* # bytes of extra gunk. */
5443 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5444 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5445 unsigned long gmask; /* Mask of saved gp registers. */
5446 unsigned long fmask; /* Mask of saved fp registers. */
5447 unsigned long reg_offset; /* Offset from new sp to store regs. */
5448 int initialized; /* Nonzero if frame size already calculated. */
5451 /* Current frame information calculated by sparc_flat_compute_frame_size. */
5452 struct sparc_frame_info current_frame_info;
5454 /* Zero structure to initialize current_frame_info. */
5455 struct sparc_frame_info zero_frame_info;
5457 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
5459 #define RETURN_ADDR_REGNUM 15
5460 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
5461 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
5463 #define MUST_SAVE_REGISTER(regno) \
5464 ((regs_ever_live[regno] && !call_used_regs[regno]) \
5465 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
5466 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
5468 /* Return the bytes needed to compute the frame pointer from the current
5472 sparc_flat_compute_frame_size (size)
5473 int size; /* # of var. bytes allocated. */
5476 unsigned long total_size; /* # bytes that the entire frame takes up. */
5477 unsigned long var_size; /* # bytes that variables take up. */
5478 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5479 unsigned long extra_size; /* # extra bytes. */
5480 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5481 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5482 unsigned long gmask; /* Mask of saved gp registers. */
5483 unsigned long fmask; /* Mask of saved fp registers. */
5484 unsigned long reg_offset; /* Offset to register save area. */
5485 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
5487 /* This is the size of the 16 word reg save area, 1 word struct addr
5488 area, and 4 word fp/alu register copy area. */
5489 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
5491 /* Also include the size needed for the 6 parameter registers. */
5492 args_size = current_function_outgoing_args_size + 24;
5493 total_size = var_size + args_size + extra_size;
5501 /* Calculate space needed for gp registers. */
5502 for (regno = 1; regno <= 31; regno++)
5504 if (MUST_SAVE_REGISTER (regno))
5506 /* If we need to save two regs in a row, ensure there's room to bump
5507 up the address to align it to a doubleword boundary. */
5508 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
5510 if (gp_reg_size % 8 != 0)
5512 gp_reg_size += 2 * UNITS_PER_WORD;
5513 gmask |= 3 << regno;
5519 gp_reg_size += UNITS_PER_WORD;
5520 gmask |= 1 << regno;
5525 /* Calculate space needed for fp registers. */
5526 for (regno = 32; regno <= 63; regno++)
5528 if (regs_ever_live[regno] && !call_used_regs[regno])
5530 fp_reg_size += UNITS_PER_WORD;
5531 fmask |= 1 << (regno - 32);
5538 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
5539 /* Ensure save area is 8 byte aligned if we need it. */
5541 if (need_aligned_p && n != 0)
5543 total_size += 8 - n;
5544 reg_offset += 8 - n;
5546 total_size += gp_reg_size + fp_reg_size;
5549 /* ??? This looks a little suspicious. Clarify. */
5550 if (total_size == extra_size)
5551 total_size = extra_size = 0;
5553 total_size = SPARC_STACK_ALIGN (total_size);
5555 /* Save other computed information. */
5556 current_frame_info.total_size = total_size;
5557 current_frame_info.var_size = var_size;
5558 current_frame_info.args_size = args_size;
5559 current_frame_info.extra_size = extra_size;
5560 current_frame_info.gp_reg_size = gp_reg_size;
5561 current_frame_info.fp_reg_size = fp_reg_size;
5562 current_frame_info.gmask = gmask;
5563 current_frame_info.fmask = fmask;
5564 current_frame_info.reg_offset = reg_offset;
5565 current_frame_info.initialized = reload_completed;
5567 /* Ok, we're done. */
5571 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
5574 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
5575 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
5576 [BASE_REG+OFFSET] will always be a valid address.
5578 WORD_OP is either "st" for save, "ld" for restore.
5579 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
5582 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
5583 doubleword_op, base_offset)
5586 unsigned int offset;
5587 unsigned long gmask;
5588 unsigned long fmask;
5590 char *doubleword_op;
5591 unsigned long base_offset;
5595 if (gmask == 0 && fmask == 0)
5598 /* Save registers starting from high to low. We've already saved the
5599 previous frame pointer and previous return address for the debugger's
5600 sake. The debugger allows us to not need a nop in the epilog if at least
5601 one register is reloaded in addition to return address. */
5605 for (regno = 1; regno <= 31; regno++)
5607 if ((gmask & (1L << regno)) != 0)
5609 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
5611 /* We can save two registers in a row. If we're not at a
5612 double word boundary, move to one.
5613 sparc_flat_compute_frame_size ensures there's room to do
5615 if (offset % 8 != 0)
5616 offset += UNITS_PER_WORD;
5618 if (word_op[0] == 's')
5620 fprintf (file, "\t%s\t%s, [%s+%d]\n",
5621 doubleword_op, reg_names[regno],
5623 if (dwarf2out_do_frame ())
5625 char *l = dwarf2out_cfi_label ();
5626 dwarf2out_reg_save (l, regno, offset + base_offset);
5628 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
5632 fprintf (file, "\t%s\t[%s+%d], %s\n",
5633 doubleword_op, base_reg, offset,
5636 offset += 2 * UNITS_PER_WORD;
5641 if (word_op[0] == 's')
5643 fprintf (file, "\t%s\t%s, [%s+%d]\n",
5644 word_op, reg_names[regno],
5646 if (dwarf2out_do_frame ())
5647 dwarf2out_reg_save ("", regno, offset + base_offset);
5650 fprintf (file, "\t%s\t[%s+%d], %s\n",
5651 word_op, base_reg, offset, reg_names[regno]);
5653 offset += UNITS_PER_WORD;
5661 for (regno = 32; regno <= 63; regno++)
5663 if ((fmask & (1L << (regno - 32))) != 0)
5665 if (word_op[0] == 's')
5667 fprintf (file, "\t%s\t%s, [%s+%d]\n",
5668 word_op, reg_names[regno],
5670 if (dwarf2out_do_frame ())
5671 dwarf2out_reg_save ("", regno, offset + base_offset);
5674 fprintf (file, "\t%s\t[%s+%d], %s\n",
5675 word_op, base_reg, offset, reg_names[regno]);
5677 offset += UNITS_PER_WORD;
5683 /* Set up the stack and frame (if desired) for the function. */
5686 sparc_flat_output_function_prologue (file, size)
5690 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5691 unsigned long gmask = current_frame_info.gmask;
5693 /* This is only for the human reader. */
5694 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
5695 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
5697 current_frame_info.var_size,
5698 current_frame_info.gp_reg_size / 4,
5699 current_frame_info.fp_reg_size / 4,
5700 current_function_outgoing_args_size,
5701 current_frame_info.extra_size);
5703 size = SPARC_STACK_ALIGN (size);
5704 size = (! current_frame_info.initialized
5705 ? sparc_flat_compute_frame_size (size)
5706 : current_frame_info.total_size);
5708 /* These cases shouldn't happen. Catch them now. */
5709 if (size == 0 && (gmask || current_frame_info.fmask))
5712 /* Allocate our stack frame by decrementing %sp.
5713 At present, the only algorithm gdb can use to determine if this is a
5714 flat frame is if we always set %i7 if we set %sp. This can be optimized
5715 in the future by putting in some sort of debugging information that says
5716 this is a `flat' function. However, there is still the case of debugging
5717 code without such debugging information (including cases where most fns
5718 have such info, but there is one that doesn't). So, always do this now
5719 so we don't get a lot of code out there that gdb can't handle.
5720 If the frame pointer isn't needn't then that's ok - gdb won't be able to
5721 distinguish us from a non-flat function but there won't (and shouldn't)
5722 be any differences anyway. The return pc is saved (if necessary) right
5723 after %i7 so gdb won't have to look too far to find it. */
5726 unsigned int reg_offset = current_frame_info.reg_offset;
5727 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
5728 char *t1_str = "%g1";
5730 /* Things get a little tricky if local variables take up more than ~4096
5731 bytes and outgoing arguments take up more than ~4096 bytes. When that
5732 happens, the register save area can't be accessed from either end of
5733 the frame. Handle this by decrementing %sp to the start of the gp
5734 register save area, save the regs, update %i7, and then set %sp to its
5735 final value. Given that we only have one scratch register to play
5736 with it is the cheapest solution, and it helps gdb out as it won't
5737 slow down recognition of flat functions.
5738 Don't change the order of insns emitted here without checking with
5739 the gdb folk first. */
5741 /* Is the entire register save area offsettable from %sp? */
5742 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
5746 fprintf (file, "\tadd\t%s, %d, %s\n",
5747 sp_str, -size, sp_str);
5748 if (gmask & FRAME_POINTER_MASK)
5750 fprintf (file, "\tst\t%s, [%s+%d]\n",
5751 fp_str, sp_str, reg_offset);
5752 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
5753 sp_str, -size, fp_str, ASM_COMMENT_START);
5759 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
5760 size, t1_str, sp_str, t1_str, sp_str);
5761 if (gmask & FRAME_POINTER_MASK)
5763 fprintf (file, "\tst\t%s, [%s+%d]\n",
5764 fp_str, sp_str, reg_offset);
5765 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
5766 sp_str, t1_str, fp_str, ASM_COMMENT_START);
5770 if (dwarf2out_do_frame ())
5772 char *l = dwarf2out_cfi_label ();
5773 if (gmask & FRAME_POINTER_MASK)
5775 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5776 reg_offset - 4 - size);
5777 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5780 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
5782 if (gmask & RETURN_ADDR_MASK)
5784 fprintf (file, "\tst\t%s, [%s+%d]\n",
5785 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
5786 if (dwarf2out_do_frame ())
5787 dwarf2out_return_save ("", reg_offset - size);
5790 sparc_flat_save_restore (file, sp_str, reg_offset,
5791 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5792 current_frame_info.fmask,
5793 "st", "std", -size);
5797 /* Subtract %sp in two steps, but make sure there is always a
5798 64 byte register save area, and %sp is properly aligned. */
5799 /* Amount to decrement %sp by, the first time. */
5800 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
5801 /* Offset to register save area from %sp. */
5802 unsigned int offset = size1 - (size - reg_offset);
5806 fprintf (file, "\tadd\t%s, %d, %s\n",
5807 sp_str, -size1, sp_str);
5808 if (gmask & FRAME_POINTER_MASK)
5810 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
5811 fp_str, sp_str, offset, sp_str, -size1, fp_str,
5818 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
5819 size1, t1_str, sp_str, t1_str, sp_str);
5820 if (gmask & FRAME_POINTER_MASK)
5822 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
5823 fp_str, sp_str, offset, sp_str, t1_str, fp_str,
5828 if (dwarf2out_do_frame ())
5830 char *l = dwarf2out_cfi_label ();
5831 if (gmask & FRAME_POINTER_MASK)
5833 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5834 offset - 4 - size1);
5835 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5838 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
5840 if (gmask & RETURN_ADDR_MASK)
5842 fprintf (file, "\tst\t%s, [%s+%d]\n",
5843 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
5844 if (dwarf2out_do_frame ())
5845 /* offset - size1 == reg_offset - size
5846 if reg_offset were updated above like offset. */
5847 dwarf2out_return_save ("", offset - size1);
5850 sparc_flat_save_restore (file, sp_str, offset,
5851 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5852 current_frame_info.fmask,
5853 "st", "std", -size1);
5854 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
5855 size - size1, t1_str, sp_str, t1_str, sp_str);
5856 if (dwarf2out_do_frame ())
5857 if (! (gmask & FRAME_POINTER_MASK))
5858 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
5862 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
5865 /* Do any necessary cleanup after a function to restore stack, frame,
5869 sparc_flat_output_function_epilogue (file, size)
5873 rtx epilogue_delay = current_function_epilogue_delay_list;
5874 int noepilogue = FALSE;
5876 /* This is only for the human reader. */
5877 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
5879 /* The epilogue does not depend on any registers, but the stack
5880 registers, so we assume that if we have 1 pending nop, it can be
5881 ignored, and 2 it must be filled (2 nops occur for integer
5882 multiply and divide). */
5884 size = SPARC_STACK_ALIGN (size);
5885 size = (!current_frame_info.initialized
5886 ? sparc_flat_compute_frame_size (size)
5887 : current_frame_info.total_size);
5889 if (size == 0 && epilogue_delay == 0)
5891 rtx insn = get_last_insn ();
5893 /* If the last insn was a BARRIER, we don't have to write any code
5894 because a jump (aka return) was put there. */
5895 if (GET_CODE (insn) == NOTE)
5896 insn = prev_nonnote_insn (insn);
5897 if (insn && GET_CODE (insn) == BARRIER)
5903 unsigned int reg_offset = current_frame_info.reg_offset;
5905 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5906 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
5907 char *t1_str = "%g1";
5909 /* In the reload sequence, we don't need to fill the load delay
5910 slots for most of the loads, also see if we can fill the final
5911 delay slot if not otherwise filled by the reload sequence. */
5914 fprintf (file, "\tset\t%d, %s\n", size, t1_str);
5916 if (frame_pointer_needed)
5919 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
5920 fp_str, t1_str, sp_str, ASM_COMMENT_START);
5922 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
5923 fp_str, size, sp_str, ASM_COMMENT_START);
5926 /* Is the entire register save area offsettable from %sp? */
5927 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
5933 /* Restore %sp in two steps, but make sure there is always a
5934 64 byte register save area, and %sp is properly aligned. */
5935 /* Amount to increment %sp by, the first time. */
5936 size1 = ((reg_offset - 64 - 16) + 15) & -16;
5937 /* Offset to register save area from %sp. */
5938 reg_offset = size1 - reg_offset;
5940 fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
5941 size1, t1_str, sp_str, t1_str, sp_str);
5944 /* We must restore the frame pointer and return address reg first
5945 because they are treated specially by the prologue output code. */
5946 if (current_frame_info.gmask & FRAME_POINTER_MASK)
5948 fprintf (file, "\tld\t[%s+%d], %s\n",
5949 sp_str, reg_offset, fp_str);
5952 if (current_frame_info.gmask & RETURN_ADDR_MASK)
5954 fprintf (file, "\tld\t[%s+%d], %s\n",
5955 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
5959 /* Restore any remaining saved registers. */
5960 sparc_flat_save_restore (file, sp_str, reg_offset,
5961 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5962 current_frame_info.fmask,
5965 /* If we had to increment %sp in two steps, record it so the second
5966 restoration in the epilogue finishes up. */
5971 fprintf (file, "\tset\t%d, %s\n",
5975 if (current_function_returns_struct)
5976 fprintf (file, "\tjmp\t%%o7+12\n");
5978 fprintf (file, "\tretl\n");
5980 /* If the only register saved is the return address, we need a
5981 nop, unless we have an instruction to put into it. Otherwise
5982 we don't since reloading multiple registers doesn't reference
5983 the register being loaded. */
5989 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
5992 else if (size > 4095)
5993 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
5996 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str);
5999 fprintf (file, "\tnop\n");
6002 /* Reset state info for each function. */
6003 current_frame_info = zero_frame_info;
6005 sparc_output_deferred_case_vectors ();
6008 /* Define the number of delay slots needed for the function epilogue.
6010 On the sparc, we need a slot if either no stack has been allocated,
6011 or the only register saved is the return register. */
6014 sparc_flat_epilogue_delay_slots ()
6016 if (!current_frame_info.initialized)
6017 (void) sparc_flat_compute_frame_size (get_frame_size ());
6019 if (current_frame_info.total_size == 0)
6025 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
6026 Any single length instruction which doesn't reference the stack or frame
6030 sparc_flat_eligible_for_epilogue_delay (trial, slot)
6032 int slot ATTRIBUTE_UNUSED;
6034 rtx pat = PATTERN (trial);
6036 if (get_attr_length (trial) != 1)
6039 /* If %g0 is live, there are lots of things we can't handle.
6040 Rather than trying to find them all now, let's punt and only
6041 optimize things as necessary. */
6045 if (! reg_mentioned_p (stack_pointer_rtx, pat)
6046 && ! reg_mentioned_p (frame_pointer_rtx, pat))
6052 /* Adjust the cost of a scheduling dependency. Return the new cost of
6053 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6056 supersparc_adjust_cost (insn, link, dep_insn, cost)
6062 enum attr_type insn_type;
6064 if (! recog_memoized (insn))
6067 insn_type = get_attr_type (insn);
6069 if (REG_NOTE_KIND (link) == 0)
6071 /* Data dependency; DEP_INSN writes a register that INSN reads some
6074 /* if a load, then the dependence must be on the memory address;
6075 add an extra 'cycle'. Note that the cost could be two cycles
6076 if the reg was written late in an instruction group; we can't tell
6078 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
6081 /* Get the delay only if the address of the store is the dependence. */
6082 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
6084 rtx pat = PATTERN(insn);
6085 rtx dep_pat = PATTERN (dep_insn);
6087 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6088 return cost; /* This shouldn't happen! */
6090 /* The dependency between the two instructions was on the data that
6091 is being stored. Assume that this implies that the address of the
6092 store is not dependent. */
6093 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6096 return cost + 3; /* An approximation. */
6099 /* A shift instruction cannot receive its data from an instruction
6100 in the same cycle; add a one cycle penalty. */
6101 if (insn_type == TYPE_SHIFT)
6102 return cost + 3; /* Split before cascade into shift. */
6106 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
6107 INSN writes some cycles later. */
6109 /* These are only significant for the fpu unit; writing a fp reg before
6110 the fpu has finished with it stalls the processor. */
6112 /* Reusing an integer register causes no problems. */
6113 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
6121 ultrasparc_adjust_cost (insn, link, dep_insn, cost)
6127 enum attr_type insn_type, dep_type;
6128 rtx pat = PATTERN(insn);
6129 rtx dep_pat = PATTERN (dep_insn);
6131 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
6134 insn_type = get_attr_type (insn);
6135 dep_type = get_attr_type (dep_insn);
6137 #define SLOW_FP(dep_type) \
6138 (dep_type == TYPE_FPSQRT || dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
6140 switch (REG_NOTE_KIND (link))
6143 /* Data dependency; DEP_INSN writes a register that INSN reads some
6148 /* UltraSPARC can dual issue a store and an instruction setting
6149 the value stored, except for divide and square root. */
6151 if (! SLOW_FP (dep_type))
6156 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6159 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6160 /* The dependency between the two instructions is on the data
6161 that is being stored. Assume that the address of the store
6162 is not also dependent. */
6169 /* A load does not return data until at least 11 cycles after
6170 a store to the same location. 3 cycles are accounted for
6171 in the load latency; add the other 8 here. */
6172 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
6174 /* If the addresses are not equal this may be a false
6175 dependency because pointer aliasing could not be
6176 determined. Add only 2 cycles in that case. 2 is
6177 an arbitrary compromise between 8, which would cause
6178 the scheduler to generate worse code elsewhere to
6179 compensate for a dependency which might not really
6181 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
6182 || GET_CODE (SET_SRC (pat)) != MEM
6183 || GET_CODE (SET_DEST (dep_pat)) != MEM
6184 || ! rtx_equal_p (XEXP (SET_SRC (pat), 0),
6185 XEXP (SET_DEST (dep_pat), 0)))
6193 /* Compare to branch latency is 0. There is no benefit from
6194 separating compare and branch. */
6195 if (dep_type == TYPE_COMPARE)
6197 /* Floating point compare to branch latency is less than
6198 compare to conditional move. */
6199 if (dep_type == TYPE_FPCMP)
6204 /* FMOVR class instructions can not issue in the same cycle
6205 or the cycle after an instruction which writes any
6206 integer register. Model this as cost 2 for dependent
6208 if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY
6209 || dep_type == TYPE_BINARY)
6212 /* Otherwise check as for integer conditional moves. */
6215 /* Conditional moves involving integer registers wait until
6216 3 cycles after loads return data. The interlock applies
6217 to all loads, not just dependent loads, but that is hard
6219 if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD)
6229 /* Divide and square root lock destination registers for full latency. */
6230 if (! SLOW_FP (dep_type))
6238 /* Other costs not accounted for:
6239 - Multiply should be modeled as having no latency because there is
6240 nothing the scheduler can do about it.
6241 - Single precision floating point loads lock the other half of
6242 the even/odd register pair.
6243 - Several hazards associated with ldd/std are ignored because these
6244 instructions are rarely generated for V9.
6245 - A shift following an integer instruction which does not set the
6246 condition codes can not issue in the same cycle.
6247 - The floating point pipeline can not have both a single and double
6248 precision operation active at the same time. Format conversions
6249 and graphics instructions are given honorary double precision status.
6250 - call and jmpl are always the first instruction in a group. */
6263 /* Assume V9 processors are capable of at least dual-issue. */
6265 case PROCESSOR_SUPERSPARC:
6267 case PROCESSOR_ULTRASPARC:
6273 set_extends(x, insn)
6276 register rtx pat = PATTERN (insn);
6278 switch (GET_CODE (SET_SRC (pat)))
6280 /* Load and some shift instructions zero extend. */
6283 /* sethi clears the high bits */
6285 /* LO_SUM is used with sethi. sethi cleared the high
6286 bits and the values used with lo_sum are positive */
6288 /* Store flag stores 0 or 1 */
6298 rtx op1 = XEXP (SET_SRC (pat), 1);
6299 if (GET_CODE (op1) == CONST_INT)
6300 return INTVAL (op1) >= 0;
6301 if (GET_CODE (XEXP (SET_SRC (pat), 0)) == REG
6302 && sparc_check_64 (XEXP (SET_SRC (pat), 0), insn) == 1)
6304 if (GET_CODE (op1) == REG
6305 && sparc_check_64 ((op1), insn) == 1)
6310 return GET_MODE (SET_SRC (pat)) == SImode;
6311 /* Positive integers leave the high bits zero. */
6313 return ! (CONST_DOUBLE_LOW (x) & 0x80000000);
6315 return ! (INTVAL (x) & 0x80000000);
6318 return - (GET_MODE (SET_SRC (pat)) == SImode);
6324 /* We _ought_ to have only one kind per function, but... */
6325 static rtx sparc_addr_diff_list;
6326 static rtx sparc_addr_list;
6329 sparc_defer_case_vector (lab, vec, diff)
6333 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
6335 sparc_addr_diff_list
6336 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
6338 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
6342 sparc_output_addr_vec (vec)
6345 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
6346 int idx, vlen = XVECLEN (body, 0);
6348 #ifdef ASM_OUTPUT_CASE_LABEL
6349 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
6352 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
6355 for (idx = 0; idx < vlen; idx++)
6357 ASM_OUTPUT_ADDR_VEC_ELT
6358 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
6363 sparc_output_addr_diff_vec (vec)
6366 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
6367 rtx base = XEXP (XEXP (body, 0), 0);
6368 int idx, vlen = XVECLEN (body, 1);
6370 #ifdef ASM_OUTPUT_CASE_LABEL
6371 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
6374 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
6377 for (idx = 0; idx < vlen; idx++)
6379 ASM_OUTPUT_ADDR_DIFF_ELT
6382 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
6383 CODE_LABEL_NUMBER (base));
6388 sparc_output_deferred_case_vectors ()
6392 /* Align to cache line in the function's code section. */
6393 function_section (current_function_decl);
6394 ASM_OUTPUT_ALIGN (asm_out_file, 5);
6396 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
6397 sparc_output_addr_vec (XEXP (t, 0));
6398 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
6399 sparc_output_addr_diff_vec (XEXP (t, 0));
6401 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
6404 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
6405 unknown. Return 1 if the high bits are zero, -1 if the register is
6408 sparc_check_64 (x, insn)
6411 /* If a register is set only once it is safe to ignore insns this
6412 code does not know how to handle. The loop will either recognize
6413 the single set and return the correct value or fail to recognize
6417 if (GET_CODE (x) == REG
6418 && flag_expensive_optimizations
6419 && REG_N_SETS (REGNO (x)) == 1)
6425 insn = get_last_insn_anywhere ();
6430 while ((insn = PREV_INSN (insn)))
6432 switch (GET_CODE (insn))
6445 rtx pat = PATTERN (insn);
6446 if (GET_CODE (pat) != SET)
6448 if (rtx_equal_p (x, SET_DEST (pat)))
6449 return set_extends (x, insn);
6450 if (reg_overlap_mentioned_p (SET_DEST (pat), x))
6459 sparc_v8plus_shift (operands, insn, opcode)
6464 static char asm_code[60];
6466 if (GET_CODE (operands[3]) == SCRATCH)
6467 operands[3] = operands[0];
6468 if (GET_CODE (operands[1]) == CONST_INT)
6470 output_asm_insn ("mov %1,%3", operands);
6474 output_asm_insn ("sllx %H1,32,%3", operands);
6475 if (sparc_check_64 (operands[1], insn) <= 0)
6476 output_asm_insn ("srl %L1,0,%L1", operands);
6477 output_asm_insn ("or %L1,%3,%3", operands);
6480 strcpy(asm_code, opcode);
6481 if (which_alternative != 2)
6482 return strcat (asm_code, " %0,%2,%L0\n\tsrlx %L0,32,%H0");
6484 return strcat (asm_code, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0");
6488 /* Return 1 if DEST and SRC reference only global and in registers. */
6491 sparc_return_peephole_ok (dest, src)
6498 if (GET_CODE (src) != CONST_INT
6499 && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
6501 return IN_OR_GLOBAL_P (dest);