1 ;; DFA scheduling description for ST40-300.
2 ;; Copyright (C) 2004, 2006 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19 ;; Boston, MA 02110-1301, USA.
21 ;; Load and store instructions save a cycle if they are aligned on a
22 ;; four byte boundary. Using a function unit for stores encourages
23 ;; gcc to separate load and store instructions by one instruction,
24 ;; which makes it more likely that the linker will be able to word
25 ;; align them when relaxing.
27 ;; The following description models the ST40-300 pipeline using the DFA based
30 ;; Two automata are defined to reduce number of states
31 ;; which a single large automaton will have. (Factoring)
33 (define_automaton "sh4_300_inst_pipeline,sh4_300_fpu_pipe")
35 ;; This unit is basically the decode unit of the processor.
36 ;; Since SH4 is a dual issue machine,it is as if there are two
37 ;; units so that any insn can be processed by either one
38 ;; of the decoding unit.
40 (define_cpu_unit "sh4_300_pipe_01,sh4_300_pipe_02" "sh4_300_inst_pipeline")
42 ;; The floating point units.
44 (define_cpu_unit "sh4_300_fpt,sh4_300_fpu,sh4_300_fds" "sh4_300_fpu_pipe")
46 ;; integer multiplier unit
48 (define_cpu_unit "sh4_300_mul" "sh4_300_inst_pipeline")
52 (define_cpu_unit "sh4_300_ls" "sh4_300_inst_pipeline")
54 ;; The address calculator used for branch instructions.
55 ;; This will be reserved after "issue" of branch instructions
56 ;; and this is to make sure that no two branch instructions
57 ;; can be issued in parallel.
59 (define_cpu_unit "sh4_300_br" "sh4_300_inst_pipeline")
61 ;; ----------------------------------------------------
62 ;; This reservation is to simplify the dual issue description.
64 (define_reservation "sh4_300_issue" "sh4_300_pipe_01|sh4_300_pipe_02")
66 (define_reservation "all" "sh4_300_pipe_01+sh4_300_pipe_02")
68 ;;(define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing")
70 ;; MOV RM,RN / MOV #imm8,RN / STS PR,RN
71 (define_insn_reservation "sh4_300_mov" 0
72 (and (eq_attr "pipe_model" "sh4_300")
73 (eq_attr "type" "move,movi8,prget"))
76 ;; Fixed STS from MACL / MACH
77 (define_insn_reservation "sh4_300_mac_gp" 0
78 (and (eq_attr "pipe_model" "sh4_300")
79 (eq_attr "type" "mac_gp"))
80 "sh4_300_issue+sh4_300_mul")
82 ;; Fixed LDS to MACL / MACH
83 (define_insn_reservation "sh4_300_gp_mac" 1
84 (and (eq_attr "pipe_model" "sh4_300")
85 (eq_attr "type" "gp_mac"))
86 "sh4_300_issue+sh4_300_mul")
88 ;; Instructions without specific resource requirements with latency 1.
90 (define_insn_reservation "sh4_300_simple_arith" 1
91 (and (eq_attr "pipe_model" "sh4_300")
92 (eq_attr "type" "mt_group,arith,dyn_shift,prset"))
95 ;; Load and store instructions have no alignment peculiarities for the ST40-300,
96 ;; but they use the load-store unit, which they share with the fmove type
97 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
98 ;; Loads have a latency of three.
100 ;; Load Store instructions.
101 (define_insn_reservation "sh4_300_load" 3
102 (and (eq_attr "pipe_model" "sh4_300")
103 (eq_attr "type" "load,pcload,load_si,pcload_si,pload"))
104 "sh4_300_issue+sh4_300_ls")
106 (define_insn_reservation "sh4_300_mac_load" 3
107 (and (eq_attr "pipe_model" "sh4_300")
108 (eq_attr "type" "mem_mac"))
109 "sh4_300_issue+sh4_300_ls+sh4_300_mul")
111 (define_insn_reservation "sh4_300_fload" 4
112 (and (eq_attr "pipe_model" "sh4_300")
113 (eq_attr "type" "fload,pcfload"))
114 "sh4_300_issue+sh4_300_ls+sh4_300_fpt")
116 ;; sh_adjust_cost describes the reduced latency of the feeding insns of a store.
117 ;; The latency of an auto-increment register is 1; the latency of the memory
118 ;; output is not actually considered here anyway.
119 (define_insn_reservation "sh4_300_store" 1
120 (and (eq_attr "pipe_model" "sh4_300")
121 (eq_attr "type" "store,pstore"))
122 "sh4_300_issue+sh4_300_ls")
124 (define_insn_reservation "sh4_300_fstore" 1
125 (and (eq_attr "pipe_model" "sh4_300")
126 (eq_attr "type" "fstore"))
127 "sh4_300_issue+sh4_300_ls+sh4_300_fpt")
129 ;; Fixed STS.L from MACL / MACH
130 (define_insn_reservation "sh4_300_mac_store" 1
131 (and (eq_attr "pipe_model" "sh4_300")
132 (eq_attr "type" "mac_mem"))
133 "sh4_300_issue+sh4_300_mul+sh4_300_ls")
135 (define_insn_reservation "sh4_300_gp_fpul" 2
136 (and (eq_attr "pipe_model" "sh4_300")
137 (eq_attr "type" "gp_fpul"))
138 "sh4_300_issue+sh4_300_fpt")
140 (define_insn_reservation "sh4_300_fpul_gp" 1
141 (and (eq_attr "pipe_model" "sh4_300")
142 (eq_attr "type" "fpul_gp"))
143 "sh4_300_issue+sh4_300_fpt")
145 ;; Branch (BF,BF/S,BT,BT/S,BRA)
146 ;; Branch Far (JMP,RTS,BRAF)
148 ;; When displacement is 0 for BF / BT, we have effectively conditional
149 ;; execution of one instruction, without pipeline disruption.
150 ;; Otherwise, the latency depends on prediction success.
151 ;; We can't really do much with the latency, even if we could express it,
152 ;; but the pairing restrictions are useful to take into account.
153 ;; ??? If the branch is likely, and not paired with a preceding insn,
154 ;; or likely and likely not predicted, we might want to fill the delay slot.
155 ;; However, there appears to be no machinery to make the compiler
156 ;; recognize these scenarios.
158 (define_insn_reservation "sh4_300_branch" 1
159 (and (eq_attr "pipe_model" "sh4_300")
160 (eq_attr "type" "cbranch,jump,return,jump_ind"))
161 "sh4_300_issue+sh4_300_br")
164 (define_insn_reservation "sh4_300_return_from_exp" 9
165 (and (eq_attr "pipe_model" "sh4_300")
166 (eq_attr "type" "rte"))
167 "sh4_300_pipe_01+sh4_300_pipe_02*9")
174 ;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2
175 ;; This description is likely inexact, but this pattern should not actually
176 ;; appear when compiling for sh4-300; we should use isbi instead.
177 ;; If a -mtune option is added later, we should use the icache array
178 ;; dispatch method instead.
179 (define_insn_reservation "sh4_300_ocbwb" 3
180 (and (eq_attr "pipe_model" "sh4_300")
181 (eq_attr "type" "cwb"))
185 ;; Calls have a mandatory delay slot, which we'd like to fill with an insn
186 ;; that can be paired with the call itself.
187 ;; Scheduling runs before reorg, so we approximate this by saying that we
188 ;; want the call to be paired with a preceding insn.
189 ;; In most cases, the insn that loads the address of the call should have
190 ;; a nonzero latency (mov rn,rm doesn't make sense since we could use rn
191 ;; for the address then). Thus, a preceding insn that can be paired with
192 ;; a call should be eligible for the delay slot.
194 ;; calls introduce a longisch delay that is likely to flush the pipelines
195 ;; of the caller's instructions. Ordinary functions tend to end with a
196 ;; load to restore a register (in the delay slot of rts), while sfuncs
197 ;; tend to end with an EX or MT insn. But that is not actually relevant,
198 ;; since there are no instructions that contend for memory access early.
199 ;; We could, of course, provide exact scheduling information for specific
200 ;; sfuncs, if that should prove useful.
202 (define_insn_reservation "sh4_300_call" 16
203 (and (eq_attr "pipe_model" "sh4_300")
204 (eq_attr "type" "call,sfunc"))
205 "sh4_300_issue+sh4_300_br,all*15")
208 (define_insn_reservation "sh4_300_fmov" 1
209 (and (eq_attr "pipe_model" "sh4_300")
210 (eq_attr "type" "fmove"))
211 "sh4_300_issue+sh4_300_fpt")
214 (define_insn_reservation "sh4_300_fpscr_load" 8
215 (and (eq_attr "pipe_model" "sh4_300")
216 (eq_attr "type" "gp_fpscr"))
217 "sh4_300_issue+sh4_300_fpu+sh4_300_fpt")
220 (define_insn_reservation "sh4_300_fpscr_load_mem" 8
221 (and (eq_attr "pipe_model" "sh4_300")
222 (eq_attr "type" "mem_fpscr"))
223 "sh4_300_issue+sh4_300_fpu+sh4_300_fpt+sh4_300_ls")
226 ;; Fixed point multiplication (DMULS.L DMULU.L MUL.L MULS.W,MULU.W)
227 (define_insn_reservation "multi" 2
228 (and (eq_attr "pipe_model" "sh4_300")
229 (eq_attr "type" "smpy,dmpy"))
230 "sh4_300_issue+sh4_300_mul")
232 ;; FPCHG, FRCHG, FSCHG
233 (define_insn_reservation "fpscr_toggle" 1
234 (and (eq_attr "pipe_model" "sh4_300")
235 (eq_attr "type" "fpscr_toggle"))
236 "sh4_300_issue+sh4_300_fpu+sh4_300_fpt")
239 (define_insn_reservation "fp_cmp" 3
240 (and (eq_attr "pipe_model" "sh4_300")
241 (eq_attr "type" "fp_cmp,dfp_cmp"))
242 "sh4_300_issue+sh4_300_fpu")
244 ;; Single precision floating point (FADD,FLOAT,FMAC,FMUL,FSUB,FTRC)
245 ;; Double-precision floating-point (FADD,FCNVDS,FCNVSD,FLOAT,FSUB,FTRC)
246 (define_insn_reservation "fp_arith" 6
247 (and (eq_attr "pipe_model" "sh4_300")
248 (eq_attr "type" "fp,ftrc_s,dfp_arith,dfp_conv"))
249 "sh4_300_issue+sh4_300_fpu")
251 ;; Single Precision FDIV/SQRT
252 (define_insn_reservation "fp_div" 19
253 (and (eq_attr "pipe_model" "sh4_300")
254 (eq_attr "type" "fdiv"))
255 "sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*15")
257 ;; Double-precision floating-point FMUL
258 (define_insn_reservation "dfp_mul" 9
259 (and (eq_attr "pipe_model" "sh4_300")
260 (eq_attr "type" "dfp_mul"))
261 "sh4_300_issue+sh4_300_fpu,sh4_300_fpu*3")
263 ;; Double precision FDIV/SQRT
264 (define_insn_reservation "dp_div" 35
265 (and (eq_attr "pipe_model" "sh4_300")
266 (eq_attr "type" "dfdiv"))
267 "sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*31")
270 ;; ??? We don't really want these for sh4-300.
271 ;; this pattern itself is likely to finish in 3 cycles, but also
272 ;; to disrupt branch prediction for taken branches for the following
274 (define_insn_reservation "sh4_300_arith3" 5
275 (and (eq_attr "pipe_model" "sh4_300")
276 (eq_attr "type" "arith3"))
277 "sh4_300_issue,all*4")
279 ;; arith3b insns without brach redirection make use of the 0-offset 0-latency
280 ;; branch feature, and thus schedule the same no matter if the branch is taken
281 ;; or not. If the branch is redirected, the taken branch might take longer,
282 ;; but then, we don't have to take the next branch.
283 ;; ??? should we suppress branch redirection for sh4-300 to improve branch
285 (define_insn_reservation "arith3b" 2
286 (and (eq_attr "pipe_model" "sh4")
287 (eq_attr "type" "arith3"))