1 ; Options for the SH port of the compiler.
3 ; Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc.
5 ; This file is part of GCC.
7 ; GCC is free software; you can redistribute it and/or modify it under
8 ; the terms of the GNU General Public License as published by the Free
9 ; Software Foundation; either version 3, or (at your option) any later
12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ; You should have received a copy of the GNU General Public License
18 ; along with GCC; see the file COPYING3. If not see
19 ; <http://www.gnu.org/licenses/>.
21 ;; Used for various architecture options.
24 ;; Set if the default precision of th FPU is single.
27 ;; Set if we should generate code using type 2A insns.
30 ;; Set if we should generate code using type 2A DF insns.
31 Mask(HARD_SH2A_DOUBLE)
33 ;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
36 ;; Set if we should generate code for a SH5 CPU (either ISA).
39 ;; Set if we should save all target registers.
40 Mask(SAVE_ALL_TARGET_REGS)
43 Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
47 Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2)
51 Target RejectNegative Condition(SUPPORT_SH2A)
55 Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
56 Generate SH2a FPU-less code
59 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE)
60 Generate default single-precision SH2a code
63 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY)
64 Generate only single-precision SH2a code
67 Target RejectNegative Condition(SUPPORT_SH2E)
71 Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
75 Target RejectNegative Condition(SUPPORT_SH3E)
79 Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4)
83 Target RejectNegative Condition(SUPPORT_SH4)
87 Target RejectNegative Condition(SUPPORT_SH4)
90 ;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and
91 ;; pipeline - irrespective of ABI.
93 Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300)
97 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
98 Generate SH4 FPU-less code
101 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
102 Generate SH4-100 FPU-less code
105 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
106 Generate SH4-200 FPU-less code
109 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
110 Generate SH4-300 FPU-less code
113 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
114 Generate code for SH4 340 series (MMU/FPU-less)
115 ;; passes -isa=sh4-nommu-nofpu to the assembler.
118 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
119 Generate code for SH4 400 series (MMU/FPU-less)
120 ;; passes -isa=sh4-nommu-nofpu to the assembler.
123 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
124 Generate code for SH4 500 series (FPU-less).
125 ;; passes -isa=sh4-nofpu to the assembler.
128 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
129 Generate default single-precision SH4 code
132 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
133 Generate default single-precision SH4-100 code
136 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
137 Generate default single-precision SH4-200 code
140 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) VarExists
141 Generate default single-precision SH4-300 code
144 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
145 Generate only single-precision SH4 code
148 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
149 Generate only single-precision SH4-100 code
152 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
153 Generate only single-precision SH4-200 code
156 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) VarExists
157 Generate only single-precision SH4-300 code
160 Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
164 Target RejectNegative Condition(SUPPORT_SH4A_NOFPU)
165 Generate SH4a FPU-less code
168 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE)
169 Generate default single-precision SH4a code
172 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY)
173 Generate only single-precision SH4a code
176 Target RejectNegative Condition(SUPPORT_SH4AL)
177 Generate SH4al-dsp code
180 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
181 Generate 32-bit SHmedia code
184 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
185 Generate 32-bit FPU-less SHmedia code
188 Target RejectNegative Condition(SUPPORT_SH5_64MEDIA)
189 Generate 64-bit SHmedia code
192 Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU)
193 Generate 64-bit FPU-less SHmedia code
196 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
197 Generate SHcompact code
200 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
201 Generate FPU-less SHcompact code
204 Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5)
205 Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this
208 Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
209 Generate code in big endian mode
212 Target Report RejectNegative Mask(BIGTABLE)
213 Generate 32-bit offsets in switch tables
216 Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
217 Cost to assume for a branch insn
220 Target Var(TARGET_CBRANCHDI4)
221 Enable cbranchdi4 pattern
224 Target Var(TARGET_EXPAND_CBRANCHDI4)
225 Expand cbranchdi4 pattern early into separate comparisons and branches.
228 Target Var(TARGET_CMPEQDI_T)
229 Emit cmpeqdi_t pattern even when -mcbranchdi and -mexpand-cbranchdi are in effect.
232 Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND)
233 Enable SH5 cut2 workaround
236 Target Report RejectNegative Mask(ALIGN_DOUBLE)
237 Align doubles at 64-bit boundaries
240 Target RejectNegative Joined Var(sh_div_str) Init("")
241 Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table
244 Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
245 Specify name for 32 bit signed division function
248 Target RejectNegative Mask(FMOVD) Undocumented
251 Target Var(TARGET_FMAC)
252 Enable the use of the fused floating point multiply-accumulate operation
255 Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1)
256 Cost to assume for gettr insn
259 Target Report RejectNegative Mask(HITACHI)
260 Follow Renesas (formerly Hitachi) / SuperH calling conventions
263 Target Report Mask(IEEE)
264 Increase the IEEE compliance for floating-point code
267 Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA)
268 Enable the use of the indexed addressing mode for SHmedia32/SHcompact
270 minline-ic_invalidate
271 Target Report Var(TARGET_INLINE_IC_INVALIDATE)
272 inline code to invalidate instruction cache entries after setting up nested function trampolines
275 Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5)
276 Assume symbols might be invalid
279 Target Report RejectNegative Mask(DUMPISIZE)
280 Annotate assembler instructions with estimated addresses
283 Target Report RejectNegative Mask(LITTLE_ENDIAN)
284 Generate code in little endian mode
287 Target Report RejectNegative Mask(NOMACSAVE)
288 Mark MAC register as call-clobbered
290 ;; ??? This option is not useful, but is retained in case there are people
291 ;; who are still relying on it. It may be deleted in the future.
293 Target Report RejectNegative Mask(PADSTRUCT)
294 Make structs a multiple of 4 bytes (warning: ABI altered)
297 Target Report RejectNegative Mask(PREFERGOT)
298 Emit function-calls using global offset table when generating PIC
301 Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5)
302 Assume pt* instructions won't trap
305 Target Report RejectNegative Mask(RELAX)
306 Shorten address references during linking
309 Target Mask(HITACHI) MaskExists
310 Follow Renesas (formerly Hitachi) / SuperH calling conventions
313 Target Report RejectNegative Mask(SMALLCODE)
314 Deprecated. Use -Os instead
317 Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)
318 Cost to assume for a multiply insn
321 Target Report RejectNegative Mask(USERMODE)
322 Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode.
324 ;; We might want to enable this by default for TARGET_HARD_SH4, because
325 ;; zero-offset branches have zero latency. Needs some benchmarking.
327 Target Var(TARGET_PRETEND_CMOVE)
328 Pretend a branch-around-a-move is a conditional move.