1 /* Definitions of target machine for GNU compiler for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because hconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
35 /* Generate SDB debugging information. */
37 #define SDB_DEBUGGING_INFO
39 /* Output DBX (stabs) debugging information if doing -gstabs. */
46 %{m5-64media|m5-64media-nofpu|m5-32media|m5-32media-nofpu:-D__SHMEDIA__=1} \
47 %{m5-compact|m5-compact-nofpu:-D__SHMEDIA__=0} \
48 %{m5-64media|m5-64media-nofpu:-D__SH5__=64 -D__LONG_MAX__=9223372036854775807L} \
49 %{m5-32media|m5-32media-nofpu|m5-compact|m5-compact-nofpu:-D__SH5__=32} \
50 %{m5-64media-nofpu|m5-32media-nofpu|m5-compact-nofpu:-D__SH4_NOFPU__} \
55 %{m4-single-only:-D__SH4_SINGLE_ONLY__} \
56 %{m4-single:-D__SH4_SINGLE__} \
57 %{m4-nofpu:-D__sh3__ -D__SH4_NOFPU__} \
59 %{m1|m2|m3*|m4*:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
60 %{m5*:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
61 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(cpp_default_cpu_spec)}}}}} \
62 %{mhitachi:-D__HITACHI__} \
63 %(subtarget_cpp_spec) \
64 %(subtarget_cpp_endian_spec) "
66 #ifndef SUBTARGET_CPP_ENDIAN_SPEC
67 #define SUBTARGET_CPP_ENDIAN_SPEC "%{ml:-D__LITTLE_ENDIAN__}"
70 #ifndef SUBTARGET_CPP_SPEC
71 #define SUBTARGET_CPP_SPEC ""
74 #ifndef CPP_DEFAULT_CPU_SPEC
75 #define CPP_DEFAULT_CPU_SPEC \
76 "-D__sh1__ -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
81 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
82 { "subtarget_cpp_endian_spec", SUBTARGET_CPP_ENDIAN_SPEC }, \
83 { "cpp_default_cpu_spec", CPP_DEFAULT_CPU_SPEC }, \
84 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC },
86 #define CPP_PREDEFINES "-D__sh__ -Acpu=sh -Amachine=sh"
88 #define ASM_SPEC "%(subtarget_asm_endian_spec) %{mrelax:-relax}"
90 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
91 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little}"
94 #define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}"
96 /* We can not debug without a frame pointer. */
97 /* #define CAN_DEBUG_WITHOUT_FP */
99 #define CONDITIONAL_REGISTER_USAGE do \
102 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
103 if (! VALID_REGISTER_P (regno)) \
104 fixed_regs[regno] = call_used_regs[regno] = 1; \
105 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
107 call_used_regs[FIRST_GENERAL_REG + 8] \
108 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
109 if (TARGET_SHMEDIA) \
111 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
112 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
113 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
116 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
117 /* Hitachi saves and restores mac registers on call. */ \
118 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
120 call_used_regs[MACH_REG] = 0; \
121 call_used_regs[MACL_REG] = 0; \
123 if (TARGET_SHMEDIA) \
125 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
126 if (! fixed_regs[regno] && call_used_regs[regno]) \
127 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
130 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
131 if (! fixed_regs[regno] && call_used_regs[regno]) \
132 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
135 /* ??? Need to write documentation for all SH options and add it to the
138 /* Run-time compilation parameters selecting different hardware subsets. */
140 extern int target_flags;
141 #define ISIZE_BIT (1<<1)
142 #define DALIGN_BIT (1<<6)
143 #define SH1_BIT (1<<8)
144 #define SH2_BIT (1<<9)
145 #define SH3_BIT (1<<10)
146 #define SH3E_BIT (1<<11)
147 #define HARD_SH4_BIT (1<<5)
148 #define FPU_SINGLE_BIT (1<<7)
149 #define SH4_BIT (1<<12)
150 #define FMOVD_BIT (1<<4)
151 #define SH5_BIT (1<<0)
152 #define SPACE_BIT (1<<13)
153 #define BIGTABLE_BIT (1<<14)
154 #define RELAX_BIT (1<<15)
155 #define USERMODE_BIT (1<<16)
156 #define HITACHI_BIT (1<<22)
157 #define NOMACSAVE_BIT (1<<23)
158 #define PREFERGOT_BIT (1<<24)
159 #define PADSTRUCT_BIT (1<<28)
160 #define LITTLE_ENDIAN_BIT (1<<29)
161 #define IEEE_BIT (1<<30)
163 /* Nonzero if we should dump out instruction size info. */
164 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
166 /* Nonzero to align doubles on 64 bit boundaries. */
167 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
169 /* Nonzero if we should generate code using type 1 insns. */
170 #define TARGET_SH1 (target_flags & SH1_BIT)
172 /* Nonzero if we should generate code using type 2 insns. */
173 #define TARGET_SH2 (target_flags & SH2_BIT)
175 /* Nonzero if we should generate code using type 3 insns. */
176 #define TARGET_SH3 (target_flags & SH3_BIT)
178 /* Nonzero if we should generate code using type 3E insns. */
179 #define TARGET_SH3E ((target_flags & SH3E_BIT) && (target_flags & SH1_BIT))
181 /* Nonzero if the cache line size is 32. */
182 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
184 /* Nonzero if we schedule for a superscalar implementation. */
185 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
187 /* Nonzero if the target has separate instruction and data caches. */
188 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
190 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
191 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
193 /* Nonzero if the default precision of th FPU is single */
194 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
196 /* Nonzero if a double-precision FPU is available. */
197 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
199 /* Nonzero if an FPU is available. */
200 #define TARGET_FPU_ANY (TARGET_SH3E || TARGET_FPU_DOUBLE)
202 /* Nonzero if we should generate code using type 4 insns. */
203 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
205 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
206 #define TARGET_SH5 (target_flags & SH5_BIT)
208 /* Nonzero if we should generate code using the SHcompact instruction
209 set and 32-bit ABI. */
210 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
212 /* Nonzero if we should generate code using the SHmedia instruction
214 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
216 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
218 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
219 && (target_flags & SH3E_BIT))
221 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
223 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
224 && ! (target_flags & SH3E_BIT))
226 /* Nonzero if we should generate code using SHmedia FPU instructions. */
227 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
228 /* Nonzero if we should generate fmovd. */
229 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
231 /* Nonzero if we respect NANs. */
232 #define TARGET_IEEE (target_flags & IEEE_BIT)
234 /* Nonzero if we should generate smaller code rather than faster code. */
235 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
237 /* Nonzero to use long jump tables. */
238 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
240 /* Nonzero to generate pseudo-ops needed by the assembler and linker
241 to do function call relaxing. */
242 #define TARGET_RELAX (target_flags & RELAX_BIT)
244 /* Nonzero if using Hitachi's calling convention. */
245 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
247 /* Nonzero if not saving macl/mach when using -mhitachi */
248 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
250 /* Nonzero if padding structures to a multiple of 4 bytes. This is
251 incompatible with Hitachi's compiler, and gives unusual structure layouts
252 which confuse programmers.
253 ??? This option is not useful, but is retained in case there are people
254 who are still relying on it. It may be deleted in the future. */
255 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
257 /* Nonzero if generating code for a little endian SH. */
258 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
260 /* Nonzero if we should do everything in userland. */
261 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
263 /* Nonzero if we should prefer @GOT calls when generating PIC. */
264 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
266 /* Reset all target-selection flags. */
267 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \
268 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
270 #define TARGET_SWITCHES \
271 { {"1", TARGET_NONE, "" }, \
272 {"1", SH1_BIT, "" }, \
273 {"2", TARGET_NONE, "" }, \
274 {"2", SH2_BIT|SH1_BIT, "" }, \
275 {"3", TARGET_NONE, "" }, \
276 {"3", SH3_BIT|SH2_BIT|SH1_BIT, "" }, \
277 {"3e", TARGET_NONE, "" }, \
278 {"3e", SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|FPU_SINGLE_BIT, "" }, \
279 {"4-single-only", TARGET_NONE, "" }, \
280 {"4-single-only", SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT, "" }, \
281 {"4-single", TARGET_NONE, "" }, \
282 {"4-single", SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT, "" },\
283 {"4-nofpu", TARGET_NONE, "" }, \
284 {"4-nofpu", SH3_BIT|SH2_BIT|SH1_BIT|HARD_SH4_BIT, "" },\
285 {"4", TARGET_NONE, "" }, \
286 {"4", SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|HARD_SH4_BIT, "" }, \
287 {"5-64media", TARGET_NONE, "" }, \
288 {"5-64media", SH5_BIT|SH4_BIT, "Generate 64-bit SHmedia code" }, \
289 {"5-64media-nofpu", TARGET_NONE, "" }, \
290 {"5-64media-nofpu", SH5_BIT, "Generate 64-bit FPU-less SHmedia code" }, \
291 {"5-32media", TARGET_NONE, "" }, \
292 {"5-32media", SH5_BIT|SH4_BIT|SH3E_BIT, "Generate 32-bit SHmedia code" }, \
293 {"5-32media-nofpu", TARGET_NONE, "" }, \
294 {"5-32media-nofpu", SH5_BIT|SH3E_BIT, "Generate 32-bit FPU-less SHmedia code" }, \
295 {"5-compact", TARGET_NONE, "" }, \
296 {"5-compact", SH5_BIT|SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|FPU_SINGLE_BIT, "Generate SHcompact code" }, \
297 {"5-compact-nofpu", TARGET_NONE, "" }, \
298 {"5-compact-nofpu", SH5_BIT|SH3_BIT|SH2_BIT|SH1_BIT, "Generate FPU-less SHcompact code" }, \
299 {"b", -LITTLE_ENDIAN_BIT, "" }, \
300 {"bigtable", BIGTABLE_BIT, "" }, \
301 {"dalign", DALIGN_BIT, "" }, \
302 {"fmovd", FMOVD_BIT, "" }, \
303 {"hitachi", HITACHI_BIT, "" }, \
304 {"nomacsave", NOMACSAVE_BIT, "" }, \
305 {"ieee", IEEE_BIT, "" }, \
306 {"isize", ISIZE_BIT, "" }, \
307 {"l", LITTLE_ENDIAN_BIT, "" }, \
308 {"no-ieee", -IEEE_BIT, "" }, \
309 {"padstruct", PADSTRUCT_BIT, "" }, \
310 {"prefergot", PREFERGOT_BIT, "" }, \
311 {"relax", RELAX_BIT, "" }, \
312 {"space", SPACE_BIT, "" }, \
313 {"usermode", USERMODE_BIT, "" }, \
315 {"", TARGET_DEFAULT, "" } \
318 /* This are meant to be redefined in the host dependent files */
319 #define SUBTARGET_SWITCHES
321 #define TARGET_DEFAULT (SH1_BIT)
323 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
326 flag_omit_frame_pointer = -1; \
328 target_flags |= SPACE_BIT; \
331 #define ASSEMBLER_DIALECT assembler_dialect
333 extern int assembler_dialect;
335 #define OVERRIDE_OPTIONS \
340 assembler_dialect = 0; \
349 assembler_dialect = 1; \
355 target_flags |= DALIGN_BIT; \
356 if (TARGET_FPU_ANY) \
357 target_flags |= FMOVD_BIT; \
358 if (TARGET_SHMEDIA) \
360 /* There are no delay slots on SHmedia. */ \
361 flag_delayed_branch = 0; \
362 /* Relaxation isn't yet supported for SHmedia */ \
363 target_flags &= ~RELAX_BIT; \
365 if (profile_flag || profile_arc_flag) \
367 warning ("Profiling is not supported on this target."); \
368 profile_flag = profile_arc_flag = 0; \
373 /* Only the sh64-elf assembler fully supports .quad properly. */\
374 targetm.asm_out.aligned_op.di = NULL; \
375 targetm.asm_out.unaligned_op.di = NULL; \
378 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
379 if (! VALID_REGISTER_P (regno)) \
380 sh_register_names[regno][0] = '\0'; \
382 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
383 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
384 sh_additional_register_names[regno][0] = '\0'; \
386 if (flag_omit_frame_pointer < 0) \
388 /* The debugging information is sufficient, \
389 but gdb doesn't implement this yet */ \
391 flag_omit_frame_pointer \
392 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
393 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
395 flag_omit_frame_pointer = 0; \
398 if (flag_pic && ! TARGET_PREFERGOT) \
399 flag_no_function_cse = 1; \
401 /* Never run scheduling before reload, since that can \
402 break global alloc, and generates slower code anyway due \
403 to the pressure on R0. */ \
404 flag_schedule_insns = 0; \
407 /* Target machine storage layout. */
409 /* Define this if most significant bit is lowest numbered
410 in instructions that operate on numbered bit-fields. */
412 #define BITS_BIG_ENDIAN 0
414 /* Define this if most significant byte of a word is the lowest numbered. */
415 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
417 /* Define this if most significant word of a multiword number is the lowest
419 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
421 /* Define this to set the endianness to use in libgcc2.c, which can
422 not depend on target_flags. */
423 #if defined(__LITTLE_ENDIAN__)
424 #define LIBGCC2_WORDS_BIG_ENDIAN 0
426 #define LIBGCC2_WORDS_BIG_ENDIAN 1
429 #define MAX_BITS_PER_WORD 64
431 #define MAX_LONG_TYPE_SIZE MAX_BITS_PER_WORD
433 /* Width in bits of an `int'. We want just 32-bits, even if words are
435 #define INT_TYPE_SIZE 32
437 /* Width in bits of a `long'. */
438 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
440 /* Width in bits of a `long long'. */
441 #define LONG_LONG_TYPE_SIZE 64
443 /* Width in bits of a `long double'. */
444 #define LONG_DOUBLE_TYPE_SIZE 64
446 /* Width of a word, in units (bytes). */
447 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
448 #define MIN_UNITS_PER_WORD 4
450 /* Width in bits of a pointer.
451 See also the macro `Pmode' defined below. */
452 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
454 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
455 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
457 /* Boundary (in *bits*) on which stack pointer should be aligned. */
458 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
460 /* The log (base 2) of the cache line size, in bytes. Processors prior to
461 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
462 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
463 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
465 /* Allocation boundary (in *bits*) for the code of a function.
466 32 bit alignment is faster, because instructions are always fetched as a
467 pair from a longword boundary. */
468 #define FUNCTION_BOUNDARY \
469 (TARGET_SMALLCODE ? 16 << TARGET_SHMEDIA : (1 << CACHE_LOG) * 8)
471 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
472 the vbit must go into the delta field of
473 pointers-to-member-functions. */
474 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
475 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
477 /* Alignment of field after `int : 0' in a structure. */
478 #define EMPTY_FIELD_BOUNDARY 32
480 /* No data type wants to be aligned rounder than this. */
481 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
483 /* The best alignment to use in cases where we have a choice. */
484 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
486 /* Make strings word-aligned so strcpy from constants will be faster. */
487 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
488 ((TREE_CODE (EXP) == STRING_CST \
489 && (ALIGN) < FASTEST_ALIGNMENT) \
490 ? FASTEST_ALIGNMENT : (ALIGN))
492 #ifndef MAX_OFILE_ALIGNMENT
493 #define MAX_OFILE_ALIGNMENT 128
496 /* Make arrays of chars word-aligned for the same reasons. */
497 #define DATA_ALIGNMENT(TYPE, ALIGN) \
498 (TREE_CODE (TYPE) == ARRAY_TYPE \
499 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
500 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
502 /* Number of bits which any structure or union's size must be a
503 multiple of. Each structure or union's size is rounded up to a
505 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
507 /* Set this nonzero if move instructions will actually fail to work
508 when given unaligned data. */
509 #define STRICT_ALIGNMENT 1
511 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
512 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
513 barrier_align (LABEL_AFTER_BARRIER)
515 #define LOOP_ALIGN(A_LABEL) \
516 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
517 ? 0 : sh_loop_align (A_LABEL))
519 #define LABEL_ALIGN(A_LABEL) \
521 (PREV_INSN (A_LABEL) \
522 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
523 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
524 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
525 /* explicit alignment insn in constant tables. */ \
526 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
529 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
530 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
532 /* The base two logarithm of the known minimum alignment of an insn length. */
533 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
534 (GET_CODE (A_INSN) == INSN \
535 ? 1 << TARGET_SHMEDIA \
536 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
537 ? 1 << TARGET_SHMEDIA \
540 /* Standard register usage. */
542 /* Register allocation for the Hitachi calling convention:
548 r14 frame pointer/call saved
550 ap arg pointer (doesn't really exist, always eliminated)
551 pr subroutine return address
553 mach multiply/accumulate result, high part
554 macl multiply/accumulate result, low part.
555 fpul fp/int communication register
556 rap return address pointer register
558 fr1..fr3 scratch floating point registers
560 fr12..fr15 call saved floating point registers */
562 #define MAX_REGISTER_NAME_LENGTH 5
563 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
565 #define SH_REGISTER_NAMES_INITIALIZER \
567 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
568 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
569 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
570 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
571 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
572 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
573 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
574 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
575 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
576 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
577 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
578 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
579 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
580 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
581 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
582 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
583 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
584 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
585 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
589 #define DEBUG_REGISTER_NAMES SH_REGISTER_NAMES_INITIALIZER
591 #define REGNAMES_ARR_INDEX_1(index) \
592 (sh_register_names[index])
593 #define REGNAMES_ARR_INDEX_2(index) \
594 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
595 #define REGNAMES_ARR_INDEX_4(index) \
596 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
597 #define REGNAMES_ARR_INDEX_8(index) \
598 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
599 #define REGNAMES_ARR_INDEX_16(index) \
600 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
601 #define REGNAMES_ARR_INDEX_32(index) \
602 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
603 #define REGNAMES_ARR_INDEX_64(index) \
604 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
606 #define REGISTER_NAMES \
608 REGNAMES_ARR_INDEX_64 (0), \
609 REGNAMES_ARR_INDEX_64 (64), \
610 REGNAMES_ARR_INDEX_8 (128), \
611 REGNAMES_ARR_INDEX_8 (136), \
612 REGNAMES_ARR_INDEX_8 (144), \
613 REGNAMES_ARR_INDEX_1 (152) \
616 #define ADDREGNAMES_SIZE 32
617 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
618 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
619 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
621 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
623 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
624 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
625 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
626 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
629 #define ADDREGNAMES_REGNO(index) \
630 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
633 #define ADDREGNAMES_ARR_INDEX_1(index) \
634 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
635 #define ADDREGNAMES_ARR_INDEX_2(index) \
636 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
637 #define ADDREGNAMES_ARR_INDEX_4(index) \
638 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
639 #define ADDREGNAMES_ARR_INDEX_8(index) \
640 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
641 #define ADDREGNAMES_ARR_INDEX_16(index) \
642 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
643 #define ADDREGNAMES_ARR_INDEX_32(index) \
644 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
646 #define ADDITIONAL_REGISTER_NAMES \
648 ADDREGNAMES_ARR_INDEX_32 (0) \
651 /* Number of actual hardware registers.
652 The hardware registers are assigned numbers for the compiler
653 from 0 to just below FIRST_PSEUDO_REGISTER.
654 All registers that the compiler knows about must be given numbers,
655 even those that are not normally considered general registers. */
657 /* There are many other relevant definitions in sh.md's md_constants. */
659 #define FIRST_GENERAL_REG R0_REG
660 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
661 #define FIRST_FP_REG DR0_REG
662 #define LAST_FP_REG (FIRST_FP_REG + \
663 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH3E ? 15 : -1))
664 #define FIRST_XD_REG XD0_REG
665 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
666 #define FIRST_TARGET_REG TR0_REG
667 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
669 #define GENERAL_REGISTER_P(REGNO) \
670 IN_RANGE ((REGNO), FIRST_GENERAL_REG, LAST_GENERAL_REG)
672 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
673 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
675 #define FP_REGISTER_P(REGNO) \
676 ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
678 #define XD_REGISTER_P(REGNO) \
679 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
681 #define FP_OR_XD_REGISTER_P(REGNO) \
682 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
684 #define FP_ANY_REGISTER_P(REGNO) \
685 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
687 #define SPECIAL_REGISTER_P(REGNO) \
688 ((REGNO) == GBR_REG || (REGNO) == T_REG \
689 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
691 #define TARGET_REGISTER_P(REGNO) \
692 ((REGNO) >= FIRST_TARGET_REG && (REGNO) <= LAST_TARGET_REG)
694 #define SHMEDIA_REGISTER_P(REGNO) \
695 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
696 || TARGET_REGISTER_P (REGNO))
698 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
699 that should be fixed. */
700 #define VALID_REGISTER_P(REGNO) \
701 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
702 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
703 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
704 || (TARGET_SH3E && (REGNO) == FPUL_REG))
706 /* The mode that should be generally used to store a register by
707 itself in the stack, or to load it back. */
708 #define REGISTER_NATURAL_MODE(REGNO) \
709 (FP_REGISTER_P (REGNO) ? SFmode \
710 : XD_REGISTER_P (REGNO) ? DFmode \
711 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
715 #define FIRST_PSEUDO_REGISTER 153
717 /* 1 for registers that have pervasive standard uses
718 and are not available for the register allocator.
720 Mach register is fixed 'cause it's only 10 bits wide for SH1.
721 It is 32 bits wide for SH2. */
723 #define FIXED_REGISTERS \
725 /* Regular registers. */ \
726 0, 0, 0, 0, 0, 0, 0, 0, \
727 0, 0, 0, 0, 0, 0, 0, 1, \
728 /* r16 is reserved, r18 is the former pr. */ \
729 1, 0, 0, 0, 0, 0, 0, 0, \
730 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
731 /* r26 is a global variable data pointer; r27 is for constants. */ \
732 1, 1, 1, 1, 0, 0, 0, 0, \
733 0, 0, 0, 0, 0, 0, 0, 0, \
734 0, 0, 0, 0, 0, 0, 0, 0, \
735 0, 0, 0, 0, 0, 0, 0, 0, \
736 0, 0, 0, 0, 0, 0, 0, 1, \
737 /* FP registers. */ \
738 0, 0, 0, 0, 0, 0, 0, 0, \
739 0, 0, 0, 0, 0, 0, 0, 0, \
740 0, 0, 0, 0, 0, 0, 0, 0, \
741 0, 0, 0, 0, 0, 0, 0, 0, \
742 0, 0, 0, 0, 0, 0, 0, 0, \
743 0, 0, 0, 0, 0, 0, 0, 0, \
744 0, 0, 0, 0, 0, 0, 0, 0, \
745 0, 0, 0, 0, 0, 0, 0, 0, \
746 /* Branch target registers. */ \
747 0, 0, 0, 0, 0, 0, 0, 0, \
748 /* XD registers. */ \
749 0, 0, 0, 0, 0, 0, 0, 0, \
750 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
751 1, 1, 1, 1, 1, 1, 0, 1, \
756 /* 1 for registers not available across function calls.
757 These must include the FIXED_REGISTERS and also any
758 registers that can be used without being saved.
759 The latter must include the registers where values are returned
760 and the register where structure-value addresses are passed.
761 Aside from that, you can include as many other registers as you like. */
763 #define CALL_USED_REGISTERS \
765 /* Regular registers. */ \
766 1, 1, 1, 1, 1, 1, 1, 1, \
767 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
768 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
769 across SH5 function calls. */ \
770 0, 0, 0, 0, 0, 0, 0, 1, \
771 1, 1, 0, 1, 1, 1, 1, 1, \
772 1, 1, 1, 1, 0, 0, 0, 0, \
773 0, 0, 0, 0, 1, 1, 1, 1, \
774 1, 1, 1, 1, 0, 0, 0, 0, \
775 0, 0, 0, 0, 0, 0, 0, 0, \
776 0, 0, 0, 0, 1, 1, 1, 1, \
777 /* FP registers. */ \
778 1, 1, 1, 1, 1, 1, 1, 1, \
779 1, 1, 1, 1, 0, 0, 0, 0, \
780 1, 1, 1, 1, 1, 1, 1, 1, \
781 1, 1, 1, 1, 1, 1, 1, 1, \
782 1, 1, 1, 1, 0, 0, 0, 0, \
783 0, 0, 0, 0, 0, 0, 0, 0, \
784 0, 0, 0, 0, 0, 0, 0, 0, \
785 0, 0, 0, 0, 0, 0, 0, 0, \
786 /* Branch target registers. */ \
787 1, 1, 1, 1, 1, 0, 0, 0, \
788 /* XD registers. */ \
789 1, 1, 1, 1, 1, 1, 0, 0, \
790 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
791 1, 1, 0, 1, 1, 1, 1, 1, \
796 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
797 across SHcompact function calls. We can't tell whether a called
798 function is SHmedia or SHcompact, so we assume it may be when
799 compiling SHmedia code with the 32-bit ABI, since that's the only
800 ABI that can be linked with SHcompact code. */
801 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
803 && GET_MODE_SIZE (MODE) > 4 \
804 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
805 && (REGNO) <= FIRST_GENERAL_REG + 14) \
806 || (REGNO) == PR_MEDIA_REG))
808 /* Return number of consecutive hard regs needed starting at reg REGNO
809 to hold something of mode MODE.
810 This is ordinarily the length in words of a value of mode MODE
811 but can be less for certain modes in special long registers.
813 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
815 #define HARD_REGNO_NREGS(REGNO, MODE) \
816 (XD_REGISTER_P (REGNO) \
817 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
818 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
819 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
820 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
822 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
823 We can allow any mode in any general register. The special registers
824 only allow SImode. Don't allow any mode in the PR. */
826 /* We cannot hold DCmode values in the XD registers because alter_reg
827 handles subregs of them incorrectly. We could work around this by
828 spacing the XD registers like the DR registers, but this would require
829 additional memory in every compilation to hold larger register vectors.
830 We could hold SFmode / SCmode values in XD registers, but that
831 would require a tertiary reload when reloading from / to memory,
832 and a secondary reload to reload from / to general regs; that
833 seems to be a loosing proposition. */
834 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
835 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
836 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
837 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
839 : (MODE) == V2SFmode \
840 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
841 : (MODE) == V4SFmode \
842 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
843 : (MODE) == V16SFmode \
845 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
846 : (REGNO) == FIRST_XD_REG) \
847 : FP_REGISTER_P (REGNO) \
848 ? ((MODE) == SFmode \
849 || (TARGET_SHMEDIA && (MODE) == SImode) \
850 || ((TARGET_SH3E || TARGET_SHMEDIA) && (MODE) == SCmode) \
851 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
852 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
853 || (MODE) == V2SFmode))) \
854 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
855 : XD_REGISTER_P (REGNO) \
857 : TARGET_REGISTER_P (REGNO) \
858 ? ((MODE) == DImode || (MODE) == SImode) \
859 : (REGNO) == PR_REG ? 0 \
860 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
863 /* Value is 1 if MODE is a supported vector mode. */
864 #define VECTOR_MODE_SUPPORTED_P(MODE) \
866 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode))
868 /* Value is 1 if it is a good idea to tie two pseudo registers
869 when one has mode MODE1 and one has mode MODE2.
870 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
871 for any hard reg, then this must be 0 for correct output.
872 That's the case for xd registers: we don't hold SFmode values in
873 them, so we can't tie an SFmode pseudos with one in another
874 floating-point mode. */
876 #define MODES_TIEABLE_P(MODE1, MODE2) \
877 ((MODE1) == (MODE2) \
878 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
879 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
880 && (GET_MODE_SIZE (MODE2) <= 4)) \
881 : ((MODE1) != SFmode && (MODE2) != SFmode))))
883 /* Specify the registers used for certain standard purposes.
884 The values of these macros are register numbers. */
886 /* Define this if the program counter is overloaded on a register. */
887 /* #define PC_REGNUM 15*/
889 /* Register to use for pushing function arguments. */
890 #define STACK_POINTER_REGNUM SP_REG
892 /* Base register for access to local variables of the function. */
893 #define FRAME_POINTER_REGNUM FP_REG
895 /* Fake register that holds the address on the stack of the
896 current function's return address. */
897 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
899 /* Register to hold the addressing base for position independent
900 code access to data items. */
901 #define PIC_OFFSET_TABLE_REGNUM PIC_REG
903 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
905 /* Value should be nonzero if functions must have frame pointers.
906 Zero means the frame pointer need not be set up (and parms may be accessed
907 via the stack pointer) in functions that seem suitable. */
909 #define FRAME_POINTER_REQUIRED 0
911 /* Definitions for register eliminations.
913 We have three registers that can be eliminated on the SH. First, the
914 frame pointer register can often be eliminated in favor of the stack
915 pointer register. Secondly, the argument pointer register can always be
916 eliminated; it is replaced with either the stack or frame pointer.
917 Third, there is the return address pointer, which can also be replaced
918 with either the stack or the frame pointer. */
920 /* This is an array of structures. Each structure initializes one pair
921 of eliminable registers. The "from" register number is given first,
922 followed by "to". Eliminations of the same "from" register are listed
923 in order of preference. */
925 /* If you add any registers here that are not actually hard registers,
926 and that have any alternative of elimination that doesn't always
927 apply, you need to amend calc_live_regs to exclude it, because
928 reload spills all eliminable registers where it sees an
929 can_eliminate == 0 entry, thus making them 'live' .
930 If you add any hard registers that can be eliminated in different
931 ways, you have to patch reload to spill them only when all alternatives
932 of elimination fail. */
934 #define ELIMINABLE_REGS \
935 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
936 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
937 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
938 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
939 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
941 /* Given FROM and TO register numbers, say whether this elimination
943 #define CAN_ELIMINATE(FROM, TO) \
944 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
946 /* Define the offset between two registers, one to be eliminated, and the other
947 its replacement, at the start of a routine. */
949 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
950 OFFSET = initial_elimination_offset ((FROM), (TO))
952 /* Base register for access to arguments of the function. */
953 #define ARG_POINTER_REGNUM AP_REG
955 /* Register in which the static-chain is passed to a function. */
956 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
958 /* The register in which a struct value address is passed. */
960 #define STRUCT_VALUE_REGNUM 2
962 /* If the structure value address is not passed in a register, define
963 `STRUCT_VALUE' as an expression returning an RTX for the place
964 where the address is passed. If it returns 0, the address is
965 passed as an "invisible" first argument. */
967 /* The Hitachi calling convention doesn't quite fit into this scheme since
968 the address is passed like an invisible argument, but one that is always
970 #define STRUCT_VALUE \
971 (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM))
973 #define RETURN_IN_MEMORY(TYPE) \
975 ? ((TYPE_MODE (TYPE) == BLKmode \
976 ? (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
977 : GET_MODE_SIZE (TYPE_MODE (TYPE))) > 8) \
978 : (TYPE_MODE (TYPE) == BLKmode \
979 || TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE))
981 /* Don't default to pcc-struct-return, because we have already specified
982 exactly how to return structures in the RETURN_IN_MEMORY macro. */
984 #define DEFAULT_PCC_STRUCT_RETURN 0
986 #define SHMEDIA_REGS_STACK_ADJUST() \
987 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
988 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
989 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
993 /* Define the classes of registers for register constraints in the
994 machine description. Also define ranges of constants.
996 One of the classes must always be named ALL_REGS and include all hard regs.
997 If there is more than one class, another class must be named NO_REGS
998 and contain no registers.
1000 The name GENERAL_REGS must be the name of a class (or an alias for
1001 another name such as ALL_REGS). This is the class of registers
1002 that is allowed by "g" or "r" in a register constraint.
1003 Also, registers outside this class are allocated only when
1004 instructions express preferences for them.
1006 The classes must be numbered in nondecreasing order; that is,
1007 a larger-numbered class must never be contained completely
1008 in a smaller-numbered class.
1010 For any two classes, it is very desirable that there be another
1011 class that represents their union. */
1013 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1014 be used as the destination of some of the arithmetic ops. There are
1015 also some special purpose registers; the T bit register, the
1016 Procedure Return Register and the Multiply Accumulate Registers. */
1017 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1018 reg_class_subunion. We don't want to have an actual union class
1019 of these, because it would only be used when both classes are calculated
1020 to give the same cost, but there is only one FPUL register.
1021 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1022 applying to the actual instruction alternative considered. E.g., the
1023 y/r alternative of movsi_ie is considered to have no more cost that
1024 the r/r alternative, which is patently untrue. */
1046 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1048 /* Give names of register classes as strings for dump file. */
1049 #define REG_CLASS_NAMES \
1063 "GENERAL_FP_REGS", \
1068 /* Define which registers fit in which classes.
1069 This is an initializer for a vector of HARD_REG_SET
1070 of length N_REG_CLASSES. */
1072 #define REG_CLASS_CONTENTS \
1075 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1077 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1079 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1081 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1083 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1085 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1086 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1087 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1088 /* GENERAL_REGS: */ \
1089 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1091 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1093 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1095 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1097 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1098 /* GENERAL_FP_REGS: */ \
1099 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1100 /* TARGET_REGS: */ \
1101 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1103 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1106 /* The same information, inverted:
1107 Return the class number of the smallest class containing
1108 reg number REGNO. This could be a conditional expression
1109 or could index an array. */
1111 extern int regno_reg_class[FIRST_PSEUDO_REGISTER];
1112 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1114 /* When defined, the compiler allows registers explicitly used in the
1115 rtl to be used as spill registers but prevents the compiler from
1116 extending the lifetime of these registers. */
1118 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1120 /* The order in which register should be allocated. */
1121 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1122 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1123 spilled or used otherwise, we better have the FP_REGS allocated first. */
1124 #define REG_ALLOC_ORDER \
1125 { 65, 66, 67, 68, 69, 70, 71, 64, \
1126 72, 73, 74, 75, 76, 77, 78, 79, \
1127 136,137,138,139,140,141,142,143, \
1128 80, 81, 82, 83, 84, 85, 86, 87, \
1129 88, 89, 90, 91, 92, 93, 94, 95, \
1130 96, 97, 98, 99,100,101,102,103, \
1131 104,105,106,107,108,109,110,111, \
1132 112,113,114,115,116,117,118,119, \
1133 120,121,122,123,124,125,126,127, \
1134 151, 1, 2, 3, 7, 6, 5, 4, \
1135 0, 8, 9, 10, 11, 12, 13, 14, \
1136 16, 17, 18, 19, 20, 21, 22, 23, \
1137 24, 25, 26, 27, 28, 29, 30, 31, \
1138 32, 33, 34, 35, 36, 37, 38, 39, \
1139 40, 41, 42, 43, 44, 45, 46, 47, \
1140 48, 49, 50, 51, 52, 53, 54, 55, \
1141 56, 57, 58, 59, 60, 61, 62, 63, \
1142 150, 15,145,146,147,144,148,149, \
1143 128,129,130,131,132,133,134,135, \
1146 /* The class value for index registers, and the one for base regs. */
1147 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1148 #define BASE_REG_CLASS GENERAL_REGS
1150 /* Get reg_class from a letter such as appears in the machine
1152 extern const enum reg_class reg_class_from_letter[];
1154 #define REG_CLASS_FROM_LETTER(C) \
1155 ( ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1157 /* The letters I, J, K, L and M in a register constraint string
1158 can be used to stand for particular ranges of immediate operands.
1159 This macro defines what the ranges are.
1160 C is the letter, and VALUE is a constant value.
1161 Return 1 if VALUE is in the range specified by C.
1162 I: arithmetic operand -127..128, as used in add, sub, etc
1163 J: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1164 K: shift operand 1,2,8 or 16
1165 L: logical operand 0..255, as used in and, or, etc.
1168 O: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1169 P: arithmetic operand -512..511, as used in SHmedia andi, ori
1172 #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1173 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1174 #define CONST_OK_FOR_J(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1175 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1176 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1177 #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1178 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1179 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1180 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1181 #define CONST_OK_FOR_O(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1182 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1183 #define CONST_OK_FOR_P(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1184 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1185 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1186 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
1187 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
1188 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
1189 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
1190 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1191 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1192 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
1193 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
1196 /* Similar, but for floating constants, and defining letters G and H.
1197 Here VALUE is the CONST_DOUBLE rtx itself. */
1199 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1200 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1201 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1204 /* Given an rtx X being reloaded into a reg required to be
1205 in class CLASS, return the class of reg to actually use.
1206 In general this is just CLASS; but on some machines
1207 in some cases it is preferable to use a more restrictive class. */
1209 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1210 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1211 && (GET_CODE (X) == CONST_DOUBLE \
1212 || GET_CODE (X) == SYMBOL_REF) \
1216 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1217 ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \
1218 || (CLASS) == DF_REGS) \
1219 && (GET_CODE (X) == REG && GENERAL_OR_AP_REGISTER_P (REGNO (X)))) \
1220 || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
1221 && GET_CODE (X) == REG \
1222 && FP_REGISTER_P (REGNO (X)))) \
1223 && ! TARGET_SHMEDIA \
1224 && MODE == SFmode) \
1226 : ((CLASS) == FPUL_REGS \
1227 && (GET_CODE (X) == MEM \
1228 || (GET_CODE (X) == REG \
1229 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1230 || REGNO (X) == T_REG \
1231 || system_reg_operand (X, VOIDmode))))) \
1233 : (((CLASS) == FP_REGS || (CLASS) == DF_REGS) && TARGET_SHMEDIA \
1234 && immediate_operand ((X), (MODE))) \
1236 : ((CLASS) == TARGET_REGS \
1237 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1238 ? ((target_operand ((X), (MODE)) \
1239 && ! target_reg_operand ((X), (MODE))) \
1240 ? NO_REGS : GENERAL_REGS) \
1241 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1242 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1243 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1244 ? GENERAL_REGS : NO_REGS)
1246 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1247 ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS) \
1248 && ! TARGET_SHMEDIA \
1249 && immediate_operand ((X), (MODE)) \
1250 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1251 && (MODE) == SFmode && fldi_ok ())) \
1253 : (CLASS == FPUL_REGS \
1254 && ((GET_CODE (X) == REG \
1255 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1256 || REGNO (X) == T_REG)))) \
1258 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1259 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \
1262 : (CLASS == FPSCR_REGS \
1263 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1264 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1266 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1268 /* Return the maximum number of consecutive registers
1269 needed to represent mode MODE in a register of class CLASS.
1271 On SH this is the size of MODE in words. */
1272 #define CLASS_MAX_NREGS(CLASS, MODE) \
1273 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1275 /* If defined, gives a class of registers that cannot be used as the
1276 operand of a SUBREG that changes the mode of the object illegally. */
1278 #define CLASS_CANNOT_CHANGE_MODE DF_REGS
1280 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1282 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1283 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1285 /* Stack layout; function entry, exit and calling. */
1287 /* Define the number of registers that can hold parameters.
1288 These macros are used only in other macro definitions below. */
1290 #define NPARM_REGS(MODE) \
1291 (TARGET_FPU_ANY && (MODE) == SFmode \
1292 ? (TARGET_SH5 ? 12 : 8) \
1293 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1294 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1295 ? (TARGET_SH5 ? 12 : 8) \
1296 : (TARGET_SH5 ? 8 : 4))
1298 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1299 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1301 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1302 #define FIRST_FP_RET_REG FIRST_FP_REG
1304 /* Define this if pushing a word on the stack
1305 makes the stack pointer a smaller address. */
1306 #define STACK_GROWS_DOWNWARD
1308 /* Define this macro if the addresses of local variable slots are at
1309 negative offsets from the frame pointer.
1311 The SH only has positive indexes, so grow the frame up. */
1312 /* #define FRAME_GROWS_DOWNWARD */
1314 /* Offset from the frame pointer to the first local variable slot to
1316 #define STARTING_FRAME_OFFSET 0
1318 /* If we generate an insn to push BYTES bytes,
1319 this says how many the stack pointer really advances by. */
1320 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1321 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1322 do correct alignment. */
1324 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1327 /* Offset of first parameter from the argument pointer register value. */
1328 #define FIRST_PARM_OFFSET(FNDECL) 0
1330 /* Value is the number of byte of arguments automatically
1331 popped when returning from a subroutine call.
1332 FUNDECL is the declaration node of the function (as a tree),
1333 FUNTYPE is the data type of the function (as a tree),
1334 or for a library call it is an identifier node for the subroutine name.
1335 SIZE is the number of bytes of arguments passed on the stack.
1337 On the SH, the caller does not pop any of its arguments that were passed
1339 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1341 /* Value is the number of bytes of arguments automatically popped when
1342 calling a subroutine.
1343 CUM is the accumulated argument list.
1345 On SHcompact, the call trampoline pops arguments off the stack. */
1346 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1348 /* Nonzero if we do not know how to pass TYPE solely in registers.
1349 Values that come in registers with inconvenient padding are stored
1350 to memory at the function start. */
1352 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1354 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1355 || TREE_ADDRESSABLE (TYPE)))
1356 /* Some subroutine macros specific to this machine. */
1358 #define BASE_RETURN_VALUE_REG(MODE) \
1359 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1360 ? FIRST_FP_RET_REG \
1361 : TARGET_FPU_ANY && (MODE) == SCmode \
1362 ? FIRST_FP_RET_REG \
1363 : (TARGET_FPU_DOUBLE \
1364 && ((MODE) == DFmode || (MODE) == SFmode \
1365 || (MODE) == DCmode || (MODE) == SCmode )) \
1366 ? FIRST_FP_RET_REG \
1369 #define BASE_ARG_REG(MODE) \
1370 ((TARGET_SH3E && ((MODE) == SFmode)) \
1371 ? FIRST_FP_PARM_REG \
1372 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1373 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1374 ? FIRST_FP_PARM_REG \
1377 /* Define how to find the value returned by a function.
1378 VALTYPE is the data type of the value (as a tree).
1379 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1380 otherwise, FUNC is 0.
1381 For the SH, this is like LIBCALL_VALUE, except that we must change the
1382 mode like PROMOTE_MODE does.
1383 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1384 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1386 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1388 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1389 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1390 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1391 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1392 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1393 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1394 || TREE_CODE (VALTYPE) == REAL_TYPE \
1395 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1396 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1397 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1399 /* Define how to find the value returned by a library function
1400 assuming the value has mode MODE. */
1401 #define LIBCALL_VALUE(MODE) \
1402 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1404 /* 1 if N is a possible register number for a function value. */
1405 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1406 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG) \
1407 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1409 /* 1 if N is a possible register number for function argument passing. */
1410 #define FUNCTION_ARG_REGNO_P(REGNO) \
1411 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG \
1412 + NPARM_REGS (SImode))) \
1413 || (TARGET_FPU_ANY \
1414 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG \
1415 + NPARM_REGS (SFmode))))
1417 /* Define a data type for recording info about an argument list
1418 during the scan of that argument list. This data type should
1419 hold all necessary information about the function itself
1420 and about the args processed so far, enough to enable macros
1421 such as FUNCTION_ARG to determine where the next arg should go.
1423 On SH, this is a single integer, which is a number of words
1424 of arguments scanned so far (including the invisible argument,
1425 if any, which holds the structure-value-address).
1426 Thus NARGREGS or more means all following args should go on the stack. */
1428 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1432 /* Non-zero if a prototype is available for the function. */
1434 /* The number of an odd floating-point register, that should be used
1435 for the next argument of type float. */
1436 int free_single_fp_reg;
1437 /* Whether we're processing an outgoing function call. */
1439 /* The number of general-purpose registers that should have been
1440 used to pass partial arguments, that are passed totally on the
1441 stack. On SHcompact, a call trampoline will pop them off the
1442 stack before calling the actual function, and, if the called
1443 function is implemented in SHcompact mode, the incoming arguments
1444 decoder will push such arguments back onto the stack. For
1445 incoming arguments, STACK_REGS also takes into account other
1446 arguments passed by reference, that the decoder will also push
1449 /* The number of general-purpose registers that should have been
1450 used to pass arguments, if the arguments didn't have to be passed
1453 /* Set by SHCOMPACT_BYREF if the current argument is to be passed by
1457 /* call_cookie is a bitmask used by call expanders, as well as
1458 function prologue and epilogues, to allow SHcompact to comply
1459 with the SH5 32-bit ABI, that requires 64-bit registers to be
1460 used even though only the lower 32-bit half is visible in
1461 SHcompact mode. The strategy is to call SHmedia trampolines.
1463 The alternatives for each of the argument-passing registers are
1464 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1465 contents from the address in it; (d) add 8 to it, storing the
1466 result in the next register, then (c); (e) copy it from some
1467 floating-point register,
1469 Regarding copies from floating-point registers, r2 may only be
1470 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1471 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1472 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1473 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1476 The bit mask is structured as follows:
1478 - 1 bit to tell whether to set up a return trampoline.
1480 - 3 bits to count the number consecutive registers to pop off the
1483 - 4 bits for each of r9, r8, r7 and r6.
1485 - 3 bits for each of r5, r4, r3 and r2.
1487 - 3 bits set to 0 (the most significant ones)
1490 1098 7654 3210 9876 5432 1098 7654 3210
1491 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1492 2223 3344 4555 6666 7777 8888 9999 SSS-
1494 - If F is set, the register must be copied from an FP register,
1495 whose number is encoded in the remaining bits.
1497 - Else, if L is set, the register must be loaded from the address
1498 contained in it. If the P bit is *not* set, the address of the
1499 following dword should be computed first, and stored in the
1502 - Else, if P is set, the register alone should be popped off the
1505 - After all this processing, the number of registers represented
1506 in SSS will be popped off the stack. This is an optimization
1507 for pushing/popping consecutive registers, typically used for
1508 varargs and large arguments partially passed in registers.
1510 - If T is set, a return trampoline will be set up for 64-bit
1511 return values to be split into 2 32-bit registers. */
1512 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1513 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1514 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1515 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1516 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1517 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1518 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1519 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1520 #define CALL_COOKIE_INT_REG(REG, VAL) \
1521 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1522 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1523 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1527 #define CUMULATIVE_ARGS struct sh_args
1529 #define GET_SH_ARG_CLASS(MODE) \
1530 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1532 /* There's no mention of complex float types in the SH5 ABI, so we
1533 should presumably handle them as aggregate types. */ \
1534 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1536 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1537 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1538 ? SH_ARG_FLOAT : SH_ARG_INT)
1540 #define ROUND_ADVANCE(SIZE) \
1541 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1543 /* Round a register number up to a proper boundary for an arg of mode
1546 The SH doesn't care about double alignment, so we only
1547 round doubles to even regs when asked to explicitly. */
1549 #define ROUND_REG(CUM, MODE) \
1550 (((TARGET_ALIGN_DOUBLE \
1551 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1552 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1553 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1554 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1555 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1556 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1558 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1559 for a call to a function whose data type is FNTYPE.
1560 For a library call, FNTYPE is 0.
1562 On SH, the offset always starts at 0: the first parm reg is always
1563 the same reg for a given argument class.
1565 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1567 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1569 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1570 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1572 = (TARGET_HITACHI && FNTYPE \
1573 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1574 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
1575 (CUM).arg_count[(int) SH_ARG_INT] \
1576 = (TARGET_SH5 && (FNTYPE) \
1577 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1578 (CUM).free_single_fp_reg = 0; \
1579 (CUM).outgoing = 1; \
1580 (CUM).stack_regs = 0; \
1581 (CUM).byref_regs = 0; \
1584 = (CALL_COOKIE_RET_TRAMP \
1585 (TARGET_SHCOMPACT && (FNTYPE) \
1586 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
1587 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
1588 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
1589 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
1590 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
1592 == FIRST_RET_REG))); \
1595 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1597 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0); \
1599 = (CALL_COOKIE_RET_TRAMP \
1600 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
1601 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
1604 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1606 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0); \
1607 (CUM).outgoing = 0; \
1610 /* FIXME: This is overly conservative. A SHcompact function that
1611 receives arguments ``by reference'' will have them stored in its
1612 own stack frame, so it must not pass pointers or references to
1613 these arguments to other functions by means of sibling calls. */
1614 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1615 (! TARGET_SHCOMPACT || current_function_args_info.stack_regs == 0)
1617 /* Update the data in CUM to advance over an argument
1618 of mode MODE and data type TYPE.
1619 (TYPE is null for libcalls where that information may not be
1622 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1623 if ((CUM).force_mem) \
1624 (CUM).force_mem = 0; \
1625 else if (TARGET_SH5) \
1627 tree TYPE_ = ((CUM).byref && (TYPE) \
1628 ? TREE_TYPE (TYPE) \
1630 enum machine_mode MODE_ = ((CUM).byref && (TYPE) \
1631 ? TYPE_MODE (TYPE_) \
1633 int dwords = (((CUM).byref \
1635 : (MODE_) == BLKmode \
1636 ? int_size_in_bytes (TYPE_) \
1637 : GET_MODE_SIZE (MODE_)) + 7) / 8; \
1638 int numregs = MIN (dwords, NPARM_REGS (SImode) \
1639 - (CUM).arg_count[(int) SH_ARG_INT]); \
1643 (CUM).arg_count[(int) SH_ARG_INT] += numregs; \
1644 if (TARGET_SHCOMPACT \
1645 && SHCOMPACT_FORCE_ON_STACK (MODE_, TYPE_)) \
1647 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1649 else if ((CUM).byref) \
1651 if (! (CUM).outgoing) \
1652 (CUM).stack_regs += numregs; \
1653 (CUM).byref_regs += numregs; \
1657 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1659 while (--numregs); \
1661 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1664 else if (dwords > numregs) \
1666 int pushregs = numregs; \
1668 if (TARGET_SHCOMPACT) \
1669 (CUM).stack_regs += numregs; \
1670 while (pushregs < NPARM_REGS (SImode) - 1 \
1671 && (CALL_COOKIE_INT_REG_GET \
1672 ((CUM).call_cookie, \
1673 NPARM_REGS (SImode) - pushregs) \
1677 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) \
1681 if (numregs == NPARM_REGS (SImode)) \
1683 |= CALL_COOKIE_INT_REG (0, 1) \
1684 | CALL_COOKIE_STACKSEQ (numregs - 1); \
1687 |= CALL_COOKIE_STACKSEQ (numregs); \
1690 if (GET_SH_ARG_CLASS (MODE_) == SH_ARG_FLOAT \
1691 && ((NAMED) || ! (CUM).prototype_p)) \
1693 if ((MODE_) == SFmode && (CUM).free_single_fp_reg) \
1694 (CUM).free_single_fp_reg = 0; \
1695 else if ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1696 < NPARM_REGS (SFmode)) \
1699 = MIN ((GET_MODE_SIZE (MODE_) + 7) / 8 * 2, \
1700 NPARM_REGS (SFmode) \
1701 - (CUM).arg_count[(int) SH_ARG_FLOAT]); \
1703 (CUM).arg_count[(int) SH_ARG_FLOAT] += numfpregs; \
1705 if (TARGET_SHCOMPACT && ! (CUM).prototype_p) \
1707 if ((CUM).outgoing && numregs > 0) \
1711 |= (CALL_COOKIE_INT_REG \
1712 ((CUM).arg_count[(int) SH_ARG_INT] \
1713 - numregs + ((numfpregs - 2) / 2), \
1714 4 + ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1715 - numfpregs) / 2)); \
1717 while (numfpregs -= 2); \
1719 else if ((MODE_) == SFmode && (NAMED) \
1720 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1721 < NPARM_REGS (SFmode))) \
1722 (CUM).free_single_fp_reg \
1723 = FIRST_FP_PARM_REG - numfpregs \
1724 + (CUM).arg_count[(int) SH_ARG_FLOAT] + 1; \
1728 else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
1729 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1730 = (ROUND_REG ((CUM), (MODE)) \
1731 + ((MODE) == BLKmode \
1732 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1733 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
1735 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1736 This macro is only used in this file. */
1738 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1740 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1741 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
1742 && ! (CUM).force_mem \
1744 ? ((MODE) == BLKmode \
1745 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1746 + int_size_in_bytes (TYPE)) \
1747 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1748 : ((ROUND_REG((CUM), (MODE)) \
1749 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1750 <= NPARM_REGS (MODE))) \
1751 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1753 /* Define where to put the arguments to a function.
1754 Value is zero to push the argument on the stack,
1755 or a hard register in which to store the argument.
1757 MODE is the argument's machine mode.
1758 TYPE is the data type of the argument (as a tree).
1759 This is null for libcalls where that information may
1761 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1762 the preceding args and about the function being called.
1763 NAMED is nonzero if this argument is a named parameter
1764 (otherwise it is an extra parameter matching an ellipsis).
1766 On SH the first args are normally in registers
1767 and the rest are pushed. Any arg that starts within the first
1768 NPARM_REGS words is at least partially passed in a register unless
1769 its data type forbids. */
1771 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1773 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1775 || (! TARGET_HITACHI && (TARGET_SH3E || ! current_function_varargs)))) \
1776 ? gen_rtx_REG ((MODE), \
1777 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
1778 ^ ((MODE) == SFmode && TARGET_SH4 \
1779 && TARGET_LITTLE_ENDIAN != 0))) \
1781 ? ((MODE) == VOIDmode && TARGET_SHCOMPACT \
1782 ? GEN_INT ((CUM).call_cookie) \
1783 /* The following test assumes unnamed arguments are promoted to \
1785 : (MODE) == SFmode && (CUM).free_single_fp_reg \
1786 ? SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), (CUM).free_single_fp_reg) \
1787 : (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1788 && ((NAMED) || ! (CUM).prototype_p) \
1789 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode)) \
1790 ? ((! (CUM).prototype_p && TARGET_SHMEDIA) \
1791 ? SH5_PROTOTYPELESS_FLOAT_ARG ((CUM), (MODE)) \
1792 : SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), \
1794 + (CUM).arg_count[(int) SH_ARG_FLOAT])) \
1795 : ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1796 && (! TARGET_SHCOMPACT \
1797 || (! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1798 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1799 (TYPE), (NAMED))))) \
1800 ? gen_rtx_REG ((MODE), (FIRST_PARM_REG \
1801 + (CUM).arg_count[(int) SH_ARG_INT])) \
1805 /* Whether an argument must be passed by reference. On SHcompact, we
1806 pretend arguments wider than 32-bits that would have been passed in
1807 registers are passed by reference, so that an SHmedia trampoline
1808 loads them into the full 64-bits registers. */
1809 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) \
1810 (MUST_PASS_IN_STACK ((MODE), (TYPE)) \
1811 || SHCOMPACT_BYREF ((CUM), (MODE), (TYPE), (NAMED)))
1813 #define SHCOMPACT_BYREF(CUM, MODE, TYPE, NAMED) \
1815 = (TARGET_SHCOMPACT \
1816 && (CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1817 && (! (NAMED) || GET_SH_ARG_CLASS (MODE) == SH_ARG_INT \
1818 || (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1819 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1820 >= NPARM_REGS (SFmode)))) \
1821 && ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1822 : GET_MODE_SIZE (MODE)) > 4 \
1823 && ! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1824 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1826 ? ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1827 : GET_MODE_SIZE (MODE)) \
1830 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1831 register in SHcompact mode, it must be padded in the most
1832 significant end. This means that passing it by reference wouldn't
1833 pad properly on a big-endian machine. In this particular case, we
1834 pass this argument on the stack, in a way that the call trampoline
1835 will load its value into the appropriate register. */
1836 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1837 ((MODE) == BLKmode \
1838 && TARGET_SHCOMPACT \
1839 && ! TARGET_LITTLE_ENDIAN \
1840 && int_size_in_bytes (TYPE) > 4 \
1841 && int_size_in_bytes (TYPE) < 8)
1843 /* Minimum alignment for an argument to be passed by callee-copy
1844 reference. We need such arguments to be aligned to 8 byte
1845 boundaries, because they'll be loaded using quad loads. */
1846 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1848 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
1850 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
1851 : GET_MODE_ALIGNMENT (MODE)) \
1852 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
1854 /* The SH5 ABI requires floating-point arguments to be passed to
1855 functions without a prototype in both an FP register and a regular
1856 register or the stack. When passing the argument in both FP and
1857 general-purpose registers, list the FP register first. */
1858 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1864 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1865 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1866 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1871 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1872 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1873 + (CUM).arg_count[(int) SH_ARG_INT]) \
1874 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1875 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1878 /* The SH5 ABI requires regular registers or stack slots to be
1879 reserved for floating-point arguments. Registers are taken care of
1880 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1881 Unfortunately, there's no way to just reserve a stack slot, so
1882 we'll end up needlessly storing a copy of the argument in the
1883 stack. For incoming arguments, however, the PARALLEL will be
1884 optimized to the register-only form, and the value in the stack
1885 slot won't be used at all. */
1886 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1887 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1888 ? gen_rtx_REG ((MODE), (REG)) \
1889 : gen_rtx_PARALLEL ((MODE), \
1892 (VOIDmode, NULL_RTX, \
1895 (VOIDmode, gen_rtx_REG ((MODE), \
1899 #define STRICT_ARGUMENT_NAMING TARGET_SH5
1901 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI && ! TARGET_SH5)
1903 /* For an arg passed partly in registers and partly in memory,
1904 this is the number of registers used.
1905 For args passed entirely in registers or entirely in memory, zero.
1907 We sometimes split args. */
1909 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1911 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1913 && (ROUND_REG ((CUM), (MODE)) \
1914 + ((MODE) != BLKmode \
1915 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
1916 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
1917 > NPARM_REGS (MODE))) \
1918 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
1919 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
1920 && ! TARGET_SHCOMPACT) \
1921 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
1924 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1925 (TARGET_SH5 && (MODE) == BLKmode \
1926 && ((CUM).arg_count[(int) SH_ARG_INT] \
1927 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
1929 /* Perform any needed actions needed for a function that is receiving a
1930 variable number of arguments. */
1932 /* We actually emit the code in sh_expand_prologue. We used to use
1933 a static variable to flag that we need to emit this code, but that
1934 doesn't when inlining, when functions are deferred and then emitted
1935 later. Fortunately, we already have two flags that are part of struct
1936 function that tell if a function uses varargs or stdarg. */
1937 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) do \
1938 if (! current_function_varargs && ! current_function_stdarg) \
1942 /* Define the `__builtin_va_list' type for the ABI. */
1943 #define BUILD_VA_LIST_TYPE(VALIST) \
1944 (VALIST) = sh_build_va_list ()
1946 /* Implement `va_start' for varargs and stdarg. */
1947 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1948 sh_va_start (stdarg, valist, nextarg)
1950 /* Implement `va_arg'. */
1951 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1952 sh_va_arg (valist, type)
1954 /* Call the function profiler with a given profile label.
1955 We use two .aligns, so as to make sure that both the .long is aligned
1956 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1957 from the trapa instruction. */
1959 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1961 fprintf((STREAM), "\t.align\t2\n"); \
1962 fprintf((STREAM), "\ttrapa\t#33\n"); \
1963 fprintf((STREAM), "\t.align\t2\n"); \
1964 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1967 /* Define this macro if the code for function profiling should come
1968 before the function prologue. Normally, the profiling code comes
1971 #define PROFILE_BEFORE_PROLOGUE
1973 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1974 the stack pointer does not matter. The value is tested only in
1975 functions that have frame pointers.
1976 No definition is equivalent to always zero. */
1978 #define EXIT_IGNORE_STACK 1
1981 On the SH, the trampoline looks like
1982 2 0002 D202 mov.l l2,r2
1983 1 0000 D301 mov.l l1,r3
1986 5 0008 00000000 l1: .long area
1987 6 000c 00000000 l2: .long function */
1989 /* Length in units of the trampoline for entering a nested function. */
1990 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 32 : 16)
1992 /* Alignment required for a trampoline in bits . */
1993 #define TRAMPOLINE_ALIGNMENT \
1994 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 : 64)
1996 /* Emit RTL insns to initialize the variable parts of a trampoline.
1997 FNADDR is an RTX for the address of the function's pure code.
1998 CXT is an RTX for the static chain value for the function. */
2000 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) do \
2004 rtx tramp_templ = gen_rtx_SYMBOL_REF (Pmode, \
2005 "__GCC_nested_trampoline"); \
2006 int fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode); \
2008 tramp_templ = gen_datalabel_ref (tramp_templ); \
2009 emit_block_move (gen_rtx_MEM (BLKmode, (TRAMP)), \
2010 gen_rtx_MEM (BLKmode, tramp_templ), \
2011 GEN_INT (fixed_len)); \
2012 emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), \
2015 emit_move_insn (gen_rtx_MEM (Pmode, \
2016 plus_constant ((TRAMP), \
2018 + GET_MODE_SIZE (Pmode))), \
2020 emit_insn (gen_ic_invalidate_line (TRAMP)); \
2023 emit_move_insn (gen_rtx_MEM (SImode, (TRAMP)), \
2024 GEN_INT (trunc_int_for_mode \
2025 (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,\
2027 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 4)), \
2028 GEN_INT (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009));\
2029 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
2031 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
2033 if (TARGET_HARVARD) \
2035 if (TARGET_USERMODE) \
2036 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__ic_invalidate"),\
2037 0, VOIDmode, 1, (TRAMP), SImode); \
2039 emit_insn (gen_ic_invalidate_line (TRAMP)); \
2043 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2045 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2048 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), GEN_INT (1), \
2049 gen_reg_rtx (Pmode), 0, \
2053 /* A C expression whose value is RTL representing the value of the return
2054 address for the frame COUNT steps up from the current frame.
2055 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2056 can ignore COUNT. */
2058 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2060 ? get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
2063 /* Generate necessary RTL for __builtin_saveregs(). */
2064 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
2066 /* Addressing modes, and classification of registers for them. */
2067 #define HAVE_POST_INCREMENT TARGET_SH1
2068 /*#define HAVE_PRE_INCREMENT 1*/
2069 /*#define HAVE_POST_DECREMENT 1*/
2070 #define HAVE_PRE_DECREMENT TARGET_SH1
2072 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2074 #define USE_LOAD_PRE_DECREMENT(mode) 0
2075 #define USE_STORE_POST_INCREMENT(mode) 0
2076 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2079 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2080 < (TARGET_SMALLCODE ? 2 : \
2081 ((ALIGN >= 32) ? 16 : 2)))
2083 /* Macros to check register numbers against specific register classes. */
2085 /* These assume that REGNO is a hard or pseudo reg number.
2086 They give nonzero only if REGNO is a hard reg of the suitable class
2087 or a pseudo reg currently allocated to a suitable hard reg.
2088 Since they use reg_renumber, they are safe only once reg_renumber
2089 has been allocated, which happens in local-alloc.c. */
2091 #define REGNO_OK_FOR_BASE_P(REGNO) \
2092 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2093 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2094 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2096 ? (GENERAL_REGISTER_P (REGNO) \
2097 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2098 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2100 /* Maximum number of registers that can appear in a valid memory
2103 #define MAX_REGS_PER_ADDRESS 2
2105 /* Recognize any constant value that is a valid address. */
2107 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2109 /* Nonzero if the constant value X is a legitimate general operand. */
2111 #define LEGITIMATE_CONSTANT_P(X) \
2113 ? (GET_MODE (X) != DFmode \
2114 || (X) == CONST0_RTX (GET_MODE (X)) \
2115 || ! TARGET_SHMEDIA_FPU \
2116 || TARGET_SHMEDIA64) \
2117 : (GET_CODE (X) != CONST_DOUBLE \
2118 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2119 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X)))))
2121 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2122 and check its validity for a certain class.
2123 We have two alternate definitions for each of them.
2124 The usual definition accepts all pseudo regs; the other rejects
2125 them unless they have been allocated suitable hard regs.
2126 The symbol REG_OK_STRICT causes the latter definition to be used. */
2128 #ifndef REG_OK_STRICT
2130 /* Nonzero if X is a hard reg that can be used as a base reg
2131 or if it is a pseudo reg. */
2132 #define REG_OK_FOR_BASE_P(X) \
2133 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2135 /* Nonzero if X is a hard reg that can be used as an index
2136 or if it is a pseudo reg. */
2137 #define REG_OK_FOR_INDEX_P(X) \
2138 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2139 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2141 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2142 or if X is a pseudo reg. */
2143 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2144 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2145 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2149 /* Nonzero if X is a hard reg that can be used as a base reg. */
2150 #define REG_OK_FOR_BASE_P(X) \
2151 REGNO_OK_FOR_BASE_P (REGNO (X))
2153 /* Nonzero if X is a hard reg that can be used as an index. */
2154 #define REG_OK_FOR_INDEX_P(X) \
2155 REGNO_OK_FOR_INDEX_P (REGNO (X))
2157 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2158 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2159 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2163 /* The 'Q' constraint is a pc relative load operand. */
2164 #define EXTRA_CONSTRAINT_Q(OP) \
2165 (GET_CODE (OP) == MEM \
2166 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2167 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2168 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2169 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2170 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2172 /* The `S' constraint is a 16-bit constant, literal or symbolic. */
2173 #define EXTRA_CONSTRAINT_S(OP) \
2174 (GET_CODE (OP) == CONST \
2175 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2176 && GET_MODE (XEXP ((OP), 0)) == DImode \
2177 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2178 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2179 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2180 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2181 && (MOVI_SHORI_BASE_OPERAND_P \
2182 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2183 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2186 /* Check whether OP is a datalabel unspec. */
2187 #define DATALABEL_REF_NO_CONST_P(OP) \
2188 (GET_CODE (OP) == UNSPEC \
2189 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2190 && XVECLEN ((OP), 0) == 1 \
2191 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2192 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2194 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2196 #define DATALABEL_REF_P(OP) \
2197 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2198 || DATALABEL_REF_NO_CONST_P (OP))
2200 #define GOT_ENTRY_P(OP) \
2201 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2202 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2204 #define GOTPLT_ENTRY_P(OP) \
2205 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2206 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2208 #define GOTOFF_P(OP) \
2209 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2210 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTOFF)
2212 #define PIC_ADDR_P(OP) \
2213 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2214 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2216 #define NON_PIC_REFERENCE_P(OP) \
2217 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2218 || DATALABEL_REF_P (OP) \
2219 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2220 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2221 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2222 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2224 #define PIC_REFERENCE_P(OP) \
2225 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2226 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2228 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2229 (flag_pic ? PIC_REFERENCE_P (OP) : NON_PIC_REFERENCE_P (OP))
2231 /* The `T' constraint is a label or a symbol. */
2232 #define EXTRA_CONSTRAINT_T(OP) \
2233 (NON_PIC_REFERENCE_P (OP))
2235 #define EXTRA_CONSTRAINT(OP, C) \
2236 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2237 : (C) == 'S' ? EXTRA_CONSTRAINT_S (OP) \
2238 : (C) == 'T' ? EXTRA_CONSTRAINT_T (OP) \
2241 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2242 that is a valid memory address for an instruction.
2243 The MODE argument is the machine mode for the MEM expression
2244 that wants to use this address. */
2246 #define MODE_DISP_OK_4(X,MODE) \
2247 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2248 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
2250 #define MODE_DISP_OK_8(X,MODE) \
2251 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2252 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2254 #define BASE_REGISTER_RTX_P(X) \
2255 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2256 || (GET_CODE (X) == SUBREG \
2257 && GET_CODE (SUBREG_REG (X)) == REG \
2258 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2260 /* Since this must be r0, which is a single register class, we must check
2261 SUBREGs more carefully, to be sure that we don't accept one that extends
2262 outside the class. */
2263 #define INDEX_REGISTER_RTX_P(X) \
2264 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2265 || (GET_CODE (X) == SUBREG \
2266 && GET_CODE (SUBREG_REG (X)) == REG \
2267 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2269 /* Jump to LABEL if X is a valid address RTX. This must also take
2270 REG_OK_STRICT into account when deciding about valid registers, but it uses
2271 the above macros so we are in luck.
2279 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
2280 into the FRx registers. We implement this by setting the maximum offset
2281 to zero when the value is SFmode. This also restricts loading of SFmode
2282 values into the integer registers, but that can't be helped. */
2284 /* The SH allows a displacement in a QI or HI amode, but only when the
2285 other operand is R0. GCC doesn't handle this very well, so we forgo
2288 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2289 DI can be any number 0..60. */
2291 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2293 if (GET_CODE (OP) == CONST_INT) \
2295 if (TARGET_SHMEDIA) \
2297 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2298 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2299 && INTVAL (OP) >= -512 * MODE_SIZE \
2300 && INTVAL (OP) < 512 * MODE_SIZE) \
2305 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2306 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2310 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2312 if (BASE_REGISTER_RTX_P (X)) \
2314 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2315 && ! TARGET_SHMEDIA \
2316 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2318 else if (GET_CODE (X) == PLUS \
2319 && ((MODE) != PSImode || reload_completed)) \
2321 rtx xop0 = XEXP ((X), 0); \
2322 rtx xop1 = XEXP ((X), 1); \
2323 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2324 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2325 if (GET_MODE_SIZE (MODE) <= 4 \
2326 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2327 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
2329 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2331 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2337 /* Try machine-dependent ways of modifying an illegitimate address
2338 to be legitimate. If we find one, return the new, valid address.
2339 This macro is used in only one place: `memory_address' in explow.c.
2341 OLDX is the address as it was before break_out_memory_refs was called.
2342 In some cases it is useful to look at this to decide what needs to be done.
2344 MODE and WIN are passed so that this macro can use
2345 GO_IF_LEGITIMATE_ADDRESS.
2347 It is always safe for this macro to do nothing. It exists to recognize
2348 opportunities to optimize the output.
2350 For the SH, if X is almost suitable for indexing, but the offset is
2351 out of range, convert it into a normal form so that cse has a chance
2352 of reducing the number of address registers used. */
2354 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2357 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2358 if (GET_CODE (X) == PLUS \
2359 && (GET_MODE_SIZE (MODE) == 4 \
2360 || GET_MODE_SIZE (MODE) == 8) \
2361 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2362 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2363 && ! TARGET_SHMEDIA \
2364 && ! (TARGET_SH4 && (MODE) == DFmode) \
2365 && ! (TARGET_SH3E && (MODE) == SFmode)) \
2367 rtx index_rtx = XEXP ((X), 1); \
2368 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2371 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2372 /* On rare occasions, we might get an unaligned pointer \
2373 that is indexed in a way to give an aligned address. \
2374 Therefore, keep the lower two bits in offset_base. */ \
2375 /* Instead of offset_base 128..131 use 124..127, so that \
2376 simple add suffices. */ \
2379 offset_base = ((offset + 4) & ~60) - 4; \
2382 offset_base = offset & ~60; \
2383 /* Sometimes the normal form does not suit DImode. We \
2384 could avoid that by using smaller ranges, but that \
2385 would give less optimized code when SImode is \
2387 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2389 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2390 GEN_INT (offset_base), NULL_RTX, 0, \
2393 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2399 /* A C compound statement that attempts to replace X, which is an address
2400 that needs reloading, with a valid memory address for an operand of
2401 mode MODE. WIN is a C statement label elsewhere in the code.
2403 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2404 of the address. That will allow inheritance of the address reloads. */
2406 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2408 if (GET_CODE (X) == PLUS \
2409 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2410 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2411 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2412 && ! TARGET_SHMEDIA \
2413 && ! (TARGET_SH4 && (MODE) == DFmode) \
2414 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2416 rtx index_rtx = XEXP (X, 1); \
2417 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2420 if (TARGET_SH3E && MODE == SFmode) \
2423 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2424 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2428 /* Instead of offset_base 128..131 use 124..127, so that \
2429 simple add suffices. */ \
2432 offset_base = ((offset + 4) & ~60) - 4; \
2435 offset_base = offset & ~60; \
2436 /* Sometimes the normal form does not suit DImode. We \
2437 could avoid that by using smaller ranges, but that \
2438 would give less optimized code when SImode is \
2440 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2442 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2443 GEN_INT (offset_base)); \
2444 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
2445 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2446 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2451 /* We must re-recognize what we created before. */ \
2452 else if (GET_CODE (X) == PLUS \
2453 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2454 && GET_CODE (XEXP (X, 0)) == PLUS \
2455 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2456 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2457 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2458 && ! TARGET_SHMEDIA \
2459 && ! (TARGET_SH3E && MODE == SFmode)) \
2461 /* Because this address is so complex, we know it must have \
2462 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2463 it is already unshared, and needs no further unsharing. */ \
2464 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2465 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2470 /* Go to LABEL if ADDR (a legitimate address expression)
2471 has an effect that depends on the machine mode it is used for.
2473 ??? Strictly speaking, we should also include all indexed addressing,
2474 because the index scale factor is the length of the operand.
2475 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2476 high if we did that. So we rely on reload to fix things up. */
2478 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2480 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2484 /* Specify the machine mode that this machine uses
2485 for the index in the tablejump instruction. */
2486 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
2488 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2489 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2490 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2491 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2492 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2493 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2496 /* Define as C expression which evaluates to nonzero if the tablejump
2497 instruction expects the table to contain offsets from the address of the
2499 Do not define this if the table should contain absolute addresses. */
2500 #define CASE_VECTOR_PC_RELATIVE 1
2502 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2503 #define FLOAT_TYPE_SIZE 32
2505 /* Since the SH3e has only `float' support, it is desirable to make all
2506 floating point types equivalent to `float'. */
2507 #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
2509 /* 'char' is signed by default. */
2510 #define DEFAULT_SIGNED_CHAR 1
2512 /* We -Define SIZE_TYPE in CPP_SPEC. */
2513 #define NO_BUILTIN_SIZE_TYPE 1
2515 /* The type of size_t unsigned int. */
2516 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2518 #define NO_BUILTIN_PTRDIFF_TYPE 1
2521 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2523 #define WCHAR_TYPE "short unsigned int"
2524 #define WCHAR_TYPE_SIZE 16
2525 #define WCHAR_UNSIGNED 1
2527 #define SH_ELF_WCHAR_TYPE "long int"
2529 /* Don't cse the address of the function being compiled. */
2530 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
2532 /* Max number of bytes we can move from memory to memory
2533 in one reasonably fast instruction. */
2534 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2536 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2537 MOVE_MAX is not a compile-time constant. */
2538 #define MAX_MOVE_MAX 8
2540 /* Max number of bytes we want move_by_pieces to be able to copy
2542 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2544 /* Define if operations between registers always perform the operation
2545 on the full register even if a narrower mode is specified. */
2546 #define WORD_REGISTER_OPERATIONS
2548 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2549 will either zero-extend or sign-extend. The value of this macro should
2550 be the code that says which one of the two operations is implicitly
2551 done, NIL if none. */
2552 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
2554 /* Define if loading short immediate values into registers sign extends. */
2555 #define SHORT_IMMEDIATES_SIGN_EXTEND
2557 /* Nonzero if access to memory by bytes is no faster than for words. */
2558 #define SLOW_BYTE_ACCESS 1
2560 /* We assume that the store-condition-codes instructions store 0 for false
2561 and some other value for true. This is the value stored for true. */
2563 #define STORE_FLAG_VALUE 1
2565 /* Immediate shift counts are truncated by the output routines (or was it
2566 the assembler?). Shift counts in a register are truncated by SH. Note
2567 that the native compiler puts too large (> 32) immediate shift counts
2568 into a register and shifts by the register, letting the SH decide what
2569 to do instead of doing that itself. */
2570 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2571 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2572 expects - the sign bit is significant - so it appears that we need to
2573 leave this zero for correct SH3 code. */
2574 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
2576 /* All integers have the same format so truncation is easy. */
2577 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2579 /* Define this if addresses of constant functions
2580 shouldn't be put through pseudo regs where they can be cse'd.
2581 Desirable on machines where ordinary constants are expensive
2582 but a CALL with constant address is cheap. */
2583 /*#define NO_FUNCTION_CSE 1*/
2585 /* Chars and shorts should be passed as ints. */
2586 #define PROMOTE_PROTOTYPES 1
2588 /* The machine modes of pointers and functions. */
2589 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2590 #define FUNCTION_MODE Pmode
2592 /* The relative costs of various types of constants. */
2594 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2596 if (TARGET_SHMEDIA) \
2598 if (CONST_OK_FOR_J (INTVAL (RTX))) \
2599 return COSTS_N_INSNS (1); \
2600 else if (CONST_OK_FOR_J (INTVAL (RTX) >> 16)) \
2601 return COSTS_N_INSNS (2); \
2602 else if (CONST_OK_FOR_J ((INTVAL (RTX) >> 16) >> 16)) \
2603 return COSTS_N_INSNS (3); \
2605 return COSTS_N_INSNS (4); \
2607 if (CONST_OK_FOR_I (INTVAL (RTX))) \
2609 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \
2610 && CONST_OK_FOR_L (INTVAL (RTX))) \
2617 if (TARGET_SHMEDIA64) \
2618 return COSTS_N_INSNS (4); \
2619 if (TARGET_SHMEDIA32) \
2620 return COSTS_N_INSNS (2); \
2622 case CONST_DOUBLE: \
2623 if (TARGET_SHMEDIA) \
2624 return COSTS_N_INSNS (4); \
2628 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2630 return COSTS_N_INSNS (addsubcosts (X)); \
2632 return COSTS_N_INSNS (andcosts (X)); \
2634 return COSTS_N_INSNS (multcosts (X)); \
2638 return COSTS_N_INSNS (shiftcosts (X)); \
2643 return COSTS_N_INSNS (20); \
2648 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2649 are actually function calls with some special constraints on arguments
2652 These macros tell reorg that the references to arguments and
2653 register clobbers for insns of type sfunc do not appear to happen
2654 until after the millicode call. This allows reorg to put insns
2655 which set the argument registers into the delay slot of the millicode
2656 call -- thus they act more like traditional CALL_INSNs.
2658 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2659 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2662 #define INSN_SETS_ARE_DELAYED(X) \
2663 ((GET_CODE (X) == INSN \
2664 && GET_CODE (PATTERN (X)) != SEQUENCE \
2665 && GET_CODE (PATTERN (X)) != USE \
2666 && GET_CODE (PATTERN (X)) != CLOBBER \
2667 && get_attr_is_sfunc (X)))
2669 #define INSN_REFERENCES_ARE_DELAYED(X) \
2670 ((GET_CODE (X) == INSN \
2671 && GET_CODE (PATTERN (X)) != SEQUENCE \
2672 && GET_CODE (PATTERN (X)) != USE \
2673 && GET_CODE (PATTERN (X)) != CLOBBER \
2674 && get_attr_is_sfunc (X)))
2677 /* Position Independent Code. */
2678 /* Define this macro if references to a symbol must be treated
2679 differently depending on something about the variable or function
2680 named by the symbol (such as what section it is in).
2682 On SH, if using PIC, mark a SYMBOL_REF for a non-global symbol
2683 so that we may access it using GOTOFF instead of GOT. */
2685 #define ENCODE_SECTION_INFO(DECL, FIRST) \
2692 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2693 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2695 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = \
2696 (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2697 || ! TREE_PUBLIC (DECL)); \
2701 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2702 ? TREE_CST_RTL (DECL) \
2703 : TREE_CODE (DECL) != VAR_DECL \
2705 : DECL_RTL (DECL)); \
2707 if (rtl && GET_CODE (rtl) == MEM \
2708 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF) \
2709 XEXP (rtl, 0) = gen_datalabel_ref (XEXP (rtl, 0)); \
2714 /* The prefix used to mark SYMBOL_REFs that refer to data symbols. */
2715 #define SH_DATALABEL_ENCODING "#"
2717 /* Return true if SYM_NAME starts with SH_DATALABEL_ENCODING. */
2718 #define DATALABEL_SYMNAME_P(SYM_NAME) \
2719 (SH_DATALABEL_ENCODING[1] ? (abort (), 0) : \
2720 (SYM_NAME)[0] == SH_DATALABEL_ENCODING[0])
2722 /* Skip an optional SH_DATALABEL_ENCODING in the beginning of
2723 SYM_NAME. Then, remove a leading *, like the default definition in
2725 #define STRIP_DATALABEL_ENCODING(VAR, SYM_NAME) \
2726 (VAR) = (SYM_NAME) + (DATALABEL_SYMNAME_P (SYM_NAME) \
2727 ? strlen (SH_DATALABEL_ENCODING) : 0)
2728 #define STRIP_NAME_ENCODING(VAR, SYM_NAME) \
2729 STRIP_DATALABEL_ENCODING((VAR), (SYM_NAME)), \
2730 (VAR) += (*(VAR) == '*')
2732 /* We can't directly access anything that contains a symbol,
2733 nor can we indirect via the constant pool. */
2734 #define LEGITIMATE_PIC_OPERAND_P(X) \
2735 (! nonpic_symbol_mentioned_p (X) \
2736 && (! CONSTANT_POOL_ADDRESS_P (X) \
2737 || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))
2739 #define SYMBOLIC_CONST_P(X) \
2740 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2741 && nonpic_symbol_mentioned_p (X))
2743 /* Compute the cost of an address. For the SH, all valid addresses are
2744 the same cost. Use a slightly higher cost for reg + reg addressing,
2745 since it increases pressure on r0. */
2747 #define ADDRESS_COST(X) (GET_CODE (X) == PLUS && ! CONSTANT_P (XEXP (X, 1)) \
2748 && ! TARGET_SHMEDIA \
2751 /* Compute extra cost of moving data between one register class
2754 /* Regclass always uses 2 for moves in the same register class;
2755 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
2756 it uses this information. Hence, the general register <-> floating point
2757 register information here is not used for SFmode. */
2758 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2759 (((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
2760 : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS || (DSTCLASS) == DF_REGS) \
2761 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
2762 || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \
2763 && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
2764 || (SRCCLASS) == DF_REGS))) \
2765 ? (TARGET_SHMEDIA ? 2 \
2766 : TARGET_FMOVD ? 8 : 12) \
2767 : (((DSTCLASS) == FPUL_REGS \
2768 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
2769 || (SRCCLASS == FPUL_REGS \
2770 && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \
2772 : (((DSTCLASS) == FPUL_REGS \
2773 && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
2774 || (SRCCLASS) == T_REGS)) \
2775 || ((SRCCLASS) == FPUL_REGS \
2776 && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
2778 : (((SRCCLASS) == TARGET_REGS && (DSTCLASS) != GENERAL_REGS) \
2779 || ((DSTCLASS) == TARGET_REGS && (SRCCLASS) != GENERAL_REGS)) \
2781 : (((SRCCLASS) == FPSCR_REGS && (DSTCLASS) != GENERAL_REGS) \
2782 || ((DSTCLASS) == FPSCR_REGS && (SRCCLASS) != GENERAL_REGS)) \
2784 : 2) * ((MODE) == V16SFmode ? 8 : (MODE) == V4SFmode ? 2 : 1))
2786 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2787 would be so that people with slow memory systems could generate
2788 different code that does fewer memory accesses. */
2790 /* A C expression for the cost of a branch instruction. A value of 1
2791 is the default; other values are interpreted relative to that.
2792 The SH1 does not have delay slots, hence we get a pipeline stall
2793 at every branch. The SH4 is superscalar, so the single delay slot
2794 is not sufficient to keep both pipelines filled. */
2795 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2797 /* Assembler output control. */
2799 /* A C string constant describing how to begin a comment in the target
2800 assembler language. The compiler assumes that the comment will end at
2801 the end of the line. */
2802 #define ASM_COMMENT_START "!"
2804 /* The text to go at the start of the assembler file. */
2805 #define ASM_FILE_START(STREAM) \
2806 output_file_start (STREAM)
2808 #define ASM_FILE_END(STREAM)
2810 #define ASM_APP_ON ""
2811 #define ASM_APP_OFF ""
2812 #define FILE_ASM_OP "\t.file\n"
2813 #define IDENT_ASM_OP "\t.ident\t"
2814 #define SET_ASM_OP "\t.set\t"
2816 /* How to change between sections. */
2818 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2819 #define DATA_SECTION_ASM_OP "\t.data"
2821 #if defined CRT_BEGIN || defined CRT_END
2822 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2823 # undef TEXT_SECTION_ASM_OP
2824 # if __SHMEDIA__ == 1 && __SH5__ == 32
2825 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2827 # define TEXT_SECTION_ASM_OP "\t.text"
2832 /* If defined, a C expression whose value is a string containing the
2833 assembler operation to identify the following data as
2834 uninitialized global data. If not defined, and neither
2835 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2836 uninitialized global data will be output in the data section if
2837 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2839 #ifndef BSS_SECTION_ASM_OP
2840 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2843 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2844 separate, explicit argument. If you define this macro, it is used
2845 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2846 handling the required alignment of the variable. The alignment is
2847 specified as the number of bits.
2849 Try to use function `asm_output_aligned_bss' defined in file
2850 `varasm.c' when defining this macro. */
2851 #ifndef ASM_OUTPUT_ALIGNED_BSS
2852 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2853 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2856 /* Define this so that jump tables go in same section as the current function,
2857 which could be text or it could be a user defined section. */
2858 #define JUMP_TABLES_IN_TEXT_SECTION 1
2860 /* Switch into a generic section. */
2861 #define TARGET_ASM_NAMED_SECTION sh_asm_named_section
2863 #undef DO_GLOBAL_CTORS_BODY
2864 #define DO_GLOBAL_CTORS_BODY \
2866 typedef (*pfunc)(); \
2867 extern pfunc __ctors[]; \
2868 extern pfunc __ctors_end[]; \
2870 for (p = __ctors_end; p > __ctors; ) \
2876 #undef DO_GLOBAL_DTORS_BODY
2877 #define DO_GLOBAL_DTORS_BODY \
2879 typedef (*pfunc)(); \
2880 extern pfunc __dtors[]; \
2881 extern pfunc __dtors_end[]; \
2883 for (p = __dtors; p < __dtors_end; p++) \
2889 #define ASM_OUTPUT_REG_PUSH(file, v) \
2890 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
2892 #define ASM_OUTPUT_REG_POP(file, v) \
2893 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
2895 /* DBX register number for a given compiler register number. */
2896 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2898 /* svr4.h undefines this macro, yet we really want to use the same numbers
2899 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2900 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2902 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2903 (GENERAL_REGISTER_P (REGNO) \
2904 ? ((REGNO) - FIRST_GENERAL_REG) \
2905 : FP_REGISTER_P (REGNO) \
2906 ? ((REGNO) - FIRST_FP_REG + (TARGET_SH5 ? (TARGET_SHCOMPACT ? 245 \
2908 : XD_REGISTER_P (REGNO) \
2909 ? ((REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2910 : TARGET_REGISTER_P (REGNO) \
2911 ? ((REGNO) - FIRST_TARGET_REG + 68) \
2912 : (REGNO) == PR_REG \
2913 ? (TARGET_SH5 ? 241 : 17) \
2914 : (REGNO) == T_REG \
2915 ? (TARGET_SH5 ? 242 : 18) \
2916 : (REGNO) == GBR_REG \
2917 ? (TARGET_SH5 ? 238 : 19) \
2918 : (REGNO) == MACH_REG \
2919 ? (TARGET_SH5 ? 239 : 20) \
2920 : (REGNO) == MACL_REG \
2921 ? (TARGET_SH5 ? 240 : 21) \
2922 : (REGNO) == FPUL_REG \
2923 ? (TARGET_SH5 ? 244 : 23) \
2926 /* This is how to output a reference to a user-level label named NAME. */
2927 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2932 STRIP_DATALABEL_ENCODING (lname, (NAME)); \
2933 if (lname[0] == '*') \
2934 fputs (lname + 1, (FILE)); \
2936 asm_fprintf ((FILE), "%U%s", lname); \
2940 /* This is how to output a reference to a symbol_ref. On SH5,
2941 references to non-code symbols must be preceded by `datalabel'. */
2942 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2946 && (DATALABEL_SYMNAME_P (XSTR ((SYM), 0)) \
2947 || CONSTANT_POOL_ADDRESS_P (SYM))) \
2948 fputs ("datalabel ", (FILE)); \
2949 assemble_name ((FILE), XSTR ((SYM), 0)); \
2953 /* Output a label definition. */
2954 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2955 do { assemble_name ((FILE), (NAME)); fputs (":\n", (FILE)); } while (0)
2957 /* This is how to output an assembler line
2958 that says to advance the location counter
2959 to a multiple of 2**LOG bytes. */
2961 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2963 fprintf ((FILE), "\t.align %d\n", (LOG))
2965 /* Output a function label definition. */
2966 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
2967 ASM_OUTPUT_LABEL((STREAM), (NAME))
2969 /* Output a globalising directive for a label. */
2970 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
2971 (fprintf ((STREAM), "\t.global\t"), \
2972 assemble_name ((STREAM), (NAME)), \
2973 fputc ('\n', (STREAM)))
2975 /* The prefix to add to user-visible assembler symbols. */
2977 #define USER_LABEL_PREFIX "_"
2979 /* The prefix to add to an internally generated label. */
2981 #define LOCAL_LABEL_PREFIX ""
2983 /* Make an internal label into a string. */
2984 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
2985 sprintf ((STRING), "*%s%s%ld", LOCAL_LABEL_PREFIX, (PREFIX), (long)(NUM))
2987 /* Output an internal label definition. */
2988 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2989 asm_fprintf ((FILE), "%L%s%d:\n", (PREFIX), (NUM))
2991 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2993 /* Construct a private name. */
2994 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
2995 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
2996 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
2998 /* Output a relative address table. */
3000 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3001 switch (GET_MODE (BODY)) \
3006 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3010 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3015 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3019 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3024 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3028 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3034 /* Output an absolute table element. */
3036 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3037 if (TARGET_BIGTABLE) \
3038 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3040 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); \
3042 /* Output various types of constants. */
3044 /* Loop alignment is now done in machine_dependent_reorg, so that
3045 branch shortening can know about it. */
3047 /* This is how to output an assembler line
3048 that says to advance the location counter by SIZE bytes. */
3050 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
3051 fprintf ((FILE), "\t.space %d\n", (SIZE))
3053 /* This says how to output an assembler line
3054 to define a global common symbol. */
3056 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
3057 ( fputs ("\t.comm ", (FILE)), \
3058 assemble_name ((FILE), (NAME)), \
3059 fprintf ((FILE), ",%d\n", (SIZE)))
3061 /* This says how to output an assembler line
3062 to define a local common symbol. */
3064 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
3065 ( fputs ("\t.lcomm ", (FILE)), \
3066 assemble_name ((FILE), (NAME)), \
3067 fprintf ((FILE), ",%d\n", (SIZE)))
3069 /* A C statement to be executed just prior to the output of
3070 assembler code for INSN, to modify the extracted operands so
3071 they will be output differently.
3073 Here the argument OPVEC is the vector containing the operands
3074 extracted from INSN, and NOPERANDS is the number of elements of
3075 the vector which contain meaningful data for this insn.
3076 The contents of this vector are what will be used to convert the insn
3077 template into assembler code, so you can change the assembler output
3078 by changing the contents of the vector. */
3080 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3081 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3083 /* Print operand X (an rtx) in assembler syntax to file FILE.
3084 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3085 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3087 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3089 /* Print a memory address as an operand to reference that memory location. */
3091 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3093 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3094 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3097 /* Recognize machine-specific patterns that may appear within
3098 constants. Used for PIC-specific UNSPECs. */
3099 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3101 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3103 switch (XINT ((X), 1)) \
3105 case UNSPEC_DATALABEL: \
3106 fputs ("datalabel ", (STREAM)); \
3107 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3110 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3111 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3114 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3115 fputs ("@GOT", (STREAM)); \
3117 case UNSPEC_GOTOFF: \
3118 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3119 fputs ("@GOTOFF", (STREAM)); \
3122 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3123 fputs ("@PLT", (STREAM)); \
3125 case UNSPEC_GOTPLT: \
3126 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3127 fputs ("@GOTPLT", (STREAM)); \
3129 case UNSPEC_CALLER: \
3132 /* LPCS stands for Label for PIC Call Site. */ \
3133 ASM_GENERATE_INTERNAL_LABEL \
3134 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3135 assemble_name ((STREAM), name); \
3148 extern struct rtx_def *sh_compare_op0;
3149 extern struct rtx_def *sh_compare_op1;
3151 /* Which processor to schedule for. The elements of the enumeration must
3152 match exactly the cpu attribute in the sh.md file. */
3154 enum processor_type {
3163 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3164 extern enum processor_type sh_cpu;
3166 extern int optimize; /* needed for gen_casesi. */
3168 enum mdep_reorg_phase_e
3170 SH_BEFORE_MDEP_REORG,
3171 SH_INSERT_USES_LABELS,
3172 SH_SHORTEN_BRANCHES0,
3174 SH_SHORTEN_BRANCHES1,
3178 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3180 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
3182 /* Generate calls to memcpy, memcmp and memset. */
3184 #define TARGET_MEM_FUNCTIONS
3186 /* Handle Hitachi compiler's pragmas. */
3187 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
3188 cpp_register_pragma (PFILE, 0, "interrupt", sh_pr_interrupt); \
3189 cpp_register_pragma (PFILE, 0, "trapa", sh_pr_trapa); \
3190 cpp_register_pragma (PFILE, 0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3193 /* Set when processing a function with pragma interrupt turned on. */
3195 extern int pragma_interrupt;
3197 /* Set when processing a function with interrupt attribute. */
3199 extern int current_function_interrupt;
3201 /* Set to an RTX containing the address of the stack to switch to
3202 for interrupt functions. */
3203 extern struct rtx_def *sp_switch;
3205 extern int rtx_equal_function_value_matters;
3206 extern struct rtx_def *fpscr_rtx;
3209 /* Instructions with unfilled delay slots take up an
3210 extra two bytes for the nop in the delay slot.
3211 sh-dsp parallel processing insns are four bytes long. */
3213 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3214 (LENGTH) += sh_insn_length_adjustment (X);
3216 /* Define the codes that are matched by predicates in sh.c. */
3217 #define PREDICATE_CODES \
3218 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3219 {"arith_reg_operand", {SUBREG, REG}}, \
3220 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
3221 {"binary_float_operator", {PLUS, MULT}}, \
3222 {"commutative_float_operator", {PLUS, MULT}}, \
3223 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3224 {"fpscr_operand", {REG}}, \
3225 {"fpul_operand", {REG}}, \
3226 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3227 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3228 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3229 {"noncommutative_float_operator", {MINUS, DIV}}, \
3230 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3231 {"target_reg_operand", {SUBREG, REG}}, \
3232 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF}}, \
3233 {"register_operand", {SUBREG, REG}}, \
3234 {"symbol_ref_operand", {SYMBOL_REF}},
3236 /* Define this macro if it is advisable to hold scalars in registers
3237 in a wider mode than that declared by the program. In such cases,
3238 the value is constrained to be within the bounds of the declared
3239 type, but kept valid in the wider mode. The signedness of the
3240 extension may differ from that of the type.
3242 Leaving the unsignedp unchanged gives better code than always setting it
3243 to 0. This is despite the fact that we have only signed char and short
3244 load instructions. */
3245 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3246 if (GET_MODE_CLASS (MODE) == MODE_INT \
3247 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3248 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3249 (MODE) = (TARGET_SH1 ? SImode : DImode);
3251 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
3252 extensions applied to char/short functions arguments. Defining
3253 PROMOTE_FUNCTION_RETURN does the same for function returns. */
3255 #define PROMOTE_FUNCTION_ARGS
3256 #define PROMOTE_FUNCTION_RETURN
3258 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3259 and poping arguments. However, we do have push/pop instructions, and
3260 rather limited offsets (4 bits) in load/store instructions, so it isn't
3261 clear if this would give better code. If implemented, should check for
3262 compatibility problems. */
3264 #define SH_DYNAMIC_SHIFT_COST \
3265 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3268 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3270 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3272 #define NORMAL_MODE(ENTITY) \
3273 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3275 #define EPILOGUE_USES(REGNO) ((TARGET_SH3E || TARGET_SH4) \
3276 && (REGNO) == FPSCR_REG)
3278 #define MODE_NEEDED(ENTITY, INSN) \
3279 (recog_memoized (INSN) >= 0 \
3280 ? get_attr_fp_mode (INSN) \
3283 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3284 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3286 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3287 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3289 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3290 sh_can_redirect_branch ((INSN), (SEQ))
3292 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3293 /* SH constant pool breaks the devices in crtstuff.c to control section
3294 in where code resides. We have to write it as asm code. */
3295 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3296 asm (SECTION_OP "\n\
3302 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3303 2:\n" TEXT_SECTION_ASM_OP);
3304 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3306 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3307 (REGNO (hard_reg) == (TARGET_SH5 ? PR_MEDIA_REG : PR_REG) \
3308 ? (current_function_is_leaf && ! sh_pr_n_sets () \
3310 : gen_rtx_MEM (Pmode, TARGET_SH5 \
3311 ? (plus_constant (arg_pointer_rtx, \
3312 TARGET_SHMEDIA64 ? -8 : -4)) \
3313 : frame_pointer_rtx)) \
3316 #endif /* ! GCC_SH_H */
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