1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
35 #define TARGET_CPU_CPP_BUILTINS() \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
43 builtin_define ("__sh1__"); \
46 builtin_define ("__sh2__"); \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
52 builtin_define ("__sh3__"); \
53 builtin_define ("__SH3__"); \
54 if (TARGET_HARD_SH4) \
55 builtin_define ("__SH4_NOFPU__"); \
57 case PROCESSOR_SH3E: \
58 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
61 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
65 builtin_define_with_value ("__SH5__", \
66 TARGET_SHMEDIA64 ? "64" : "32", 0); \
67 builtin_define_with_value ("__SHMEDIA__", \
68 TARGET_SHMEDIA ? "1" : "0", 0); \
69 if (! TARGET_FPU_DOUBLE) \
70 builtin_define ("__SH4_NOFPU__"); \
74 builtin_define ("__HITACHI__"); \
75 builtin_define (TARGET_LITTLE_ENDIAN \
76 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
79 builtin_define ("__pic__"); \
80 builtin_define ("__PIC__"); \
84 /* We can not debug without a frame pointer. */
85 /* #define CAN_DEBUG_WITHOUT_FP */
87 #define CONDITIONAL_REGISTER_USAGE do \
90 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
91 if (! VALID_REGISTER_P (regno)) \
92 fixed_regs[regno] = call_used_regs[regno] = 1; \
93 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
95 call_used_regs[FIRST_GENERAL_REG + 8] \
96 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
99 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
100 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
101 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
104 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
105 /* Renesas saves and restores mac registers on call. */ \
106 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
108 call_used_regs[MACH_REG] = 0; \
109 call_used_regs[MACL_REG] = 0; \
111 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
112 regno <= LAST_FP_REG; regno += 2) \
113 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
114 if (TARGET_SHMEDIA) \
116 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
117 if (! fixed_regs[regno] && call_used_regs[regno]) \
118 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
121 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
122 if (! fixed_regs[regno] && call_used_regs[regno]) \
123 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
126 /* ??? Need to write documentation for all SH options and add it to the
129 /* Run-time compilation parameters selecting different hardware subsets. */
131 extern int target_flags;
132 #define ISIZE_BIT (1<<1)
133 #define DALIGN_BIT (1<<6)
134 #define SH1_BIT (1<<8)
135 #define SH2_BIT (1<<9)
136 #define SH3_BIT (1<<10)
137 #define SH_E_BIT (1<<11)
138 #define HARD_SH4_BIT (1<<5)
139 #define FPU_SINGLE_BIT (1<<7)
140 #define SH4_BIT (1<<12)
141 #define FMOVD_BIT (1<<4)
142 #define SH5_BIT (1<<0)
143 #define SPACE_BIT (1<<13)
144 #define BIGTABLE_BIT (1<<14)
145 #define RELAX_BIT (1<<15)
146 #define USERMODE_BIT (1<<16)
147 #define HITACHI_BIT (1<<22)
148 #define NOMACSAVE_BIT (1<<23)
149 #define PREFERGOT_BIT (1<<24)
150 #define PADSTRUCT_BIT (1<<28)
151 #define LITTLE_ENDIAN_BIT (1<<29)
152 #define IEEE_BIT (1<<30)
153 #define SAVE_ALL_TR_BIT (1<<2)
155 /* Nonzero if this is an ELF target - compile time only */
158 /* Nonzero if we should dump out instruction size info. */
159 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
161 /* Nonzero to align doubles on 64 bit boundaries. */
162 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
164 /* Nonzero if we should generate code using type 1 insns. */
165 #define TARGET_SH1 (target_flags & SH1_BIT)
167 /* Nonzero if we should generate code using type 2 insns. */
168 #define TARGET_SH2 (target_flags & SH2_BIT)
170 /* Nonzero if we should generate code using type 2E insns. */
171 #define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
173 /* Nonzero if we should generate code using type 3 insns. */
174 #define TARGET_SH3 (target_flags & SH3_BIT)
176 /* Nonzero if we should generate code using type 3E insns. */
177 #define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
179 /* Nonzero if the cache line size is 32. */
180 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
182 /* Nonzero if we schedule for a superscalar implementation. */
183 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
185 /* Nonzero if the target has separate instruction and data caches. */
186 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
188 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
189 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
191 /* Nonzero if the default precision of th FPU is single */
192 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
194 /* Nonzero if a double-precision FPU is available. */
195 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
197 /* Nonzero if an FPU is available. */
198 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
200 /* Nonzero if we should generate code using type 4 insns. */
201 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
203 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
204 #define TARGET_SH5 (target_flags & SH5_BIT)
206 /* Nonzero if we should generate code using the SHcompact instruction
207 set and 32-bit ABI. */
208 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
210 /* Nonzero if we should generate code using the SHmedia instruction
212 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
214 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
216 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
217 && (target_flags & SH_E_BIT))
219 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
221 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
222 && ! (target_flags & SH_E_BIT))
224 /* Nonzero if we should generate code using SHmedia FPU instructions. */
225 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
226 /* Nonzero if we should generate fmovd. */
227 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
229 /* Nonzero if we respect NANs. */
230 #define TARGET_IEEE (target_flags & IEEE_BIT)
232 /* Nonzero if we should generate smaller code rather than faster code. */
233 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
235 /* Nonzero to use long jump tables. */
236 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
238 /* Nonzero to generate pseudo-ops needed by the assembler and linker
239 to do function call relaxing. */
240 #define TARGET_RELAX (target_flags & RELAX_BIT)
242 /* Nonzero if using Renesas's calling convention. */
243 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
245 /* Nonzero if not saving macl/mach when using -mhitachi */
246 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
248 /* Nonzero if padding structures to a multiple of 4 bytes. This is
249 incompatible with Renesas's compiler, and gives unusual structure layouts
250 which confuse programmers.
251 ??? This option is not useful, but is retained in case there are people
252 who are still relying on it. It may be deleted in the future. */
253 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
255 /* Nonzero if generating code for a little endian SH. */
256 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
258 /* Nonzero if we should do everything in userland. */
259 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
261 /* Nonzero if we should prefer @GOT calls when generating PIC. */
262 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
264 #define TARGET_SAVE_ALL_TARGET_REGS (target_flags & SAVE_ALL_TR_BIT)
266 #define SELECT_SH1 (SH1_BIT)
267 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
268 #define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
269 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
270 #define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
271 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
272 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
273 #define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
274 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
275 #define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
276 #define SELECT_SH5_64_NOFPU (SH5_BIT)
277 #define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH_E_BIT)
278 #define SELECT_SH5_32_NOFPU (SH5_BIT | SH_E_BIT)
279 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
280 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
282 /* Reset all target-selection flags. */
283 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
284 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
286 #define TARGET_SWITCHES \
287 { {"1", TARGET_NONE, "" }, \
288 {"1", SELECT_SH1, "Generate SH1 code" }, \
289 {"2", TARGET_NONE, "" }, \
290 {"2", SELECT_SH2, "Generate SH2 code" }, \
291 {"2e", TARGET_NONE, "" }, \
292 {"2e", SELECT_SH2E, "Generate SH2e code" }, \
293 {"3", TARGET_NONE, "" }, \
294 {"3", SELECT_SH3, "Generate SH3 code" }, \
295 {"3e", TARGET_NONE, "" }, \
296 {"3e", SELECT_SH3E, "Generate SH3e code" }, \
297 {"4-single-only", TARGET_NONE, "" }, \
298 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" }, \
299 {"4-single", TARGET_NONE, "" }, \
300 {"4-single", SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" }, \
301 {"4-nofpu", TARGET_NONE, "" }, \
302 {"4-nofpu", SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" }, \
303 {"4", TARGET_NONE, "" }, \
304 {"4", SELECT_SH4, "Generate SH4 code" }, \
305 {"5-64media", TARGET_NONE, "" }, \
306 {"5-64media", SELECT_SH5_64, "Generate 64-bit SHmedia code" }, \
307 {"5-64media-nofpu", TARGET_NONE, "" }, \
308 {"5-64media-nofpu", SELECT_SH5_64_NOFPU, "Generate 64-bit FPU-less SHmedia code" }, \
309 {"5-32media", TARGET_NONE, "" }, \
310 {"5-32media", SELECT_SH5_32, "Generate 32-bit SHmedia code" }, \
311 {"5-32media-nofpu", TARGET_NONE, "" }, \
312 {"5-32media-nofpu", SELECT_SH5_32_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
313 {"5-compact", TARGET_NONE, "" }, \
314 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" }, \
315 {"5-compact-nofpu", TARGET_NONE, "" }, \
316 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" }, \
317 {"b", -LITTLE_ENDIAN_BIT, "Generate code in big endian mode" }, \
318 {"bigtable", BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" }, \
319 {"dalign", DALIGN_BIT, "Aligns doubles at 64-bit boundaries" }, \
320 {"fmovd", FMOVD_BIT, "" }, \
321 {"hitachi", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
322 {"renesas", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
323 {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" }, \
324 {"ieee", IEEE_BIT, "Increase the IEEE compliance for floating-point code" }, \
325 {"isize", ISIZE_BIT, "" }, \
326 {"l", LITTLE_ENDIAN_BIT, "Generate code in little endian mode" }, \
327 {"no-ieee", -IEEE_BIT, "" }, \
328 {"padstruct", PADSTRUCT_BIT, "" }, \
329 {"prefergot", PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" }, \
330 {"relax", RELAX_BIT, "Shorten address references during linking" }, \
331 {"space", SPACE_BIT, "Deprecated. Use -Os instead" }, \
332 {"usermode", USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" }, \
334 {"", TARGET_DEFAULT, "" } \
337 /* This are meant to be redefined in the host dependent files */
338 #define SUBTARGET_SWITCHES
340 /* This defaults us to big-endian. */
341 #ifndef TARGET_ENDIAN_DEFAULT
342 #define TARGET_ENDIAN_DEFAULT 0
345 #ifndef TARGET_CPU_DEFAULT
346 #define TARGET_CPU_DEFAULT SELECT_SH1
349 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
351 #define CPP_SPEC " %(subtarget_cpp_spec) "
353 #ifndef SUBTARGET_CPP_SPEC
354 #define SUBTARGET_CPP_SPEC ""
357 #ifndef SUBTARGET_EXTRA_SPECS
358 #define SUBTARGET_EXTRA_SPECS
361 #define EXTRA_SPECS \
362 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
363 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
364 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
365 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
366 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
367 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
368 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
369 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
370 SUBTARGET_EXTRA_SPECS
372 #if TARGET_CPU_DEFAULT & HARD_SH4_BIT
373 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
375 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
378 #define SH_ASM_SPEC \
379 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
380 %(subtarget_asm_isa_spec)"
382 #define ASM_SPEC SH_ASM_SPEC
384 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
385 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
386 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
388 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
392 #define SUBTARGET_ASM_ISA_SPEC ""
394 #define LINK_EMUL_PREFIX "sh%{ml:l}"
396 #if TARGET_CPU_DEFAULT & SH5_BIT
397 #if TARGET_CPU_DEFAULT & SH_E_BIT
398 #define LINK_DEFAULT_CPU_EMUL "32"
400 #define LINK_DEFAULT_CPU_EMUL "64"
401 #endif /* SH_E_BIT */
403 #define LINK_DEFAULT_CPU_EMUL ""
406 #define SUBTARGET_LINK_EMUL_SUFFIX ""
407 #define SUBTARGET_LINK_SPEC ""
409 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
410 so that we can undo the damage without code replication. */
411 #define LINK_SPEC SH_LINK_SPEC
413 #define SH_LINK_SPEC "\
414 -m %(link_emul_prefix)\
415 %{m5-compact*|m5-32media*:32}\
417 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
418 %(subtarget_link_emul_suffix) \
419 %{mrelax:-relax} %(subtarget_link_spec)"
421 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
424 flag_omit_frame_pointer = -1; \
426 target_flags |= SPACE_BIT; \
427 if (TARGET_SHMEDIA && LEVEL > 1) \
429 flag_branch_target_load_optimize = 1; \
431 target_flags |= SAVE_ALL_TR_BIT; \
435 #define ASSEMBLER_DIALECT assembler_dialect
437 extern int assembler_dialect;
439 #define OVERRIDE_OPTIONS \
444 assembler_dialect = 0; \
455 assembler_dialect = 1; \
461 target_flags |= DALIGN_BIT; \
463 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
464 target_flags |= FMOVD_BIT; \
465 if (TARGET_SHMEDIA) \
467 /* There are no delay slots on SHmedia. */ \
468 flag_delayed_branch = 0; \
469 /* Relaxation isn't yet supported for SHmedia */ \
470 target_flags &= ~RELAX_BIT; \
472 /* -fprofile-arcs needs a working libgcov . In unified tree \
473 configurations with newlib, this requires to configure with \
474 --with-newlib --with-headers. But there is no way to check \
475 here we have a working libgcov, so just assume that we have. */\
478 warning ("Profiling is not supported on this target."); \
479 profile_flag = profile_arc_flag = 0; \
484 /* Only the sh64-elf assembler fully supports .quad properly. */\
485 targetm.asm_out.aligned_op.di = NULL; \
486 targetm.asm_out.unaligned_op.di = NULL; \
489 reg_class_from_letter['e' - 'a'] = NO_REGS; \
491 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
492 if (! VALID_REGISTER_P (regno)) \
493 sh_register_names[regno][0] = '\0'; \
495 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
496 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
497 sh_additional_register_names[regno][0] = '\0'; \
499 if (flag_omit_frame_pointer < 0) \
501 /* The debugging information is sufficient, \
502 but gdb doesn't implement this yet */ \
504 flag_omit_frame_pointer \
505 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
506 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
508 flag_omit_frame_pointer = 0; \
511 if (flag_pic && ! TARGET_PREFERGOT) \
512 flag_no_function_cse = 1; \
514 if (SMALL_REGISTER_CLASSES) \
516 /* Never run scheduling before reload, since that can \
517 break global alloc, and generates slower code anyway due \
518 to the pressure on R0. */ \
519 flag_schedule_insns = 0; \
522 if (align_loops == 0) \
523 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
524 if (align_jumps == 0) \
525 align_jumps = 1 << CACHE_LOG; \
526 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
527 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
529 /* Allocation boundary (in *bytes*) for the code of a function. \
530 SH1: 32 bit alignment is faster, because instructions are always \
531 fetched as a pair from a longword boundary. \
532 SH2 .. SH5 : align to cache line start. */ \
533 if (align_functions == 0) \
535 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
536 /* The linker relaxation code breaks when a function contains \
537 alignments that are larger than that at the start of a \
538 compilation unit. */ \
542 = align_loops > align_jumps ? align_loops : align_jumps; \
544 /* Also take possible .long constants / mova tables int account. */\
547 if (align_functions < min_align) \
548 align_functions = min_align; \
552 /* Target machine storage layout. */
554 /* Define this if most significant bit is lowest numbered
555 in instructions that operate on numbered bit-fields. */
557 #define BITS_BIG_ENDIAN 0
559 /* Define this if most significant byte of a word is the lowest numbered. */
560 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
562 /* Define this if most significant word of a multiword number is the lowest
564 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
566 /* Define this to set the endianness to use in libgcc2.c, which can
567 not depend on target_flags. */
568 #if defined(__LITTLE_ENDIAN__)
569 #define LIBGCC2_WORDS_BIG_ENDIAN 0
571 #define LIBGCC2_WORDS_BIG_ENDIAN 1
574 #define MAX_BITS_PER_WORD 64
576 #define MAX_LONG_TYPE_SIZE MAX_BITS_PER_WORD
578 /* Width in bits of an `int'. We want just 32-bits, even if words are
580 #define INT_TYPE_SIZE 32
582 /* Width in bits of a `long'. */
583 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
585 /* Width in bits of a `long long'. */
586 #define LONG_LONG_TYPE_SIZE 64
588 /* Width in bits of a `long double'. */
589 #define LONG_DOUBLE_TYPE_SIZE 64
591 /* Width of a word, in units (bytes). */
592 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
593 #define MIN_UNITS_PER_WORD 4
595 /* Scaling factor for Dwarf data offsets for CFI information.
596 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
597 SHmedia; however, since we do partial register saves for the registers
598 visible to SHcompact, and for target registers for SHMEDIA32, we have
599 to allow saves that are only 4-byte aligned. */
600 #define DWARF_CIE_DATA_ALIGNMENT -4
602 /* Width in bits of a pointer.
603 See also the macro `Pmode' defined below. */
604 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
606 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
607 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
609 /* Boundary (in *bits*) on which stack pointer should be aligned. */
610 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
612 /* The log (base 2) of the cache line size, in bytes. Processors prior to
613 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
614 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
615 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
617 /* ABI given & required minimum allocation boundary (in *bits*) for the
618 code of a function. */
619 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
621 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
622 the vbit must go into the delta field of
623 pointers-to-member-functions. */
624 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
625 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
627 /* Alignment of field after `int : 0' in a structure. */
628 #define EMPTY_FIELD_BOUNDARY 32
630 /* No data type wants to be aligned rounder than this. */
631 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
633 /* The best alignment to use in cases where we have a choice. */
634 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
636 /* Make strings word-aligned so strcpy from constants will be faster. */
637 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
638 ((TREE_CODE (EXP) == STRING_CST \
639 && (ALIGN) < FASTEST_ALIGNMENT) \
640 ? FASTEST_ALIGNMENT : (ALIGN))
642 /* get_mode_alignment assumes complex values are always held in multiple
643 registers, but that is not the case on the SH; CQImode and CHImode are
644 held in a single integer register. SH5 also holds CSImode and SCmode
645 values in integer registers. This is relevant for argument passing on
646 SHcompact as we use a stack temp in order to pass CSImode by reference. */
647 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
648 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
649 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
650 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
653 /* Make arrays of chars word-aligned for the same reasons. */
654 #define DATA_ALIGNMENT(TYPE, ALIGN) \
655 (TREE_CODE (TYPE) == ARRAY_TYPE \
656 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
657 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
659 /* Number of bits which any structure or union's size must be a
660 multiple of. Each structure or union's size is rounded up to a
662 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
664 /* Set this nonzero if move instructions will actually fail to work
665 when given unaligned data. */
666 #define STRICT_ALIGNMENT 1
668 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
669 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
670 barrier_align (LABEL_AFTER_BARRIER)
672 #define LOOP_ALIGN(A_LABEL) \
673 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
674 ? 0 : sh_loop_align (A_LABEL))
676 #define LABEL_ALIGN(A_LABEL) \
678 (PREV_INSN (A_LABEL) \
679 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
680 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
681 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
682 /* explicit alignment insn in constant tables. */ \
683 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
686 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
687 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
689 /* The base two logarithm of the known minimum alignment of an insn length. */
690 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
691 (GET_CODE (A_INSN) == INSN \
692 ? 1 << TARGET_SHMEDIA \
693 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
694 ? 1 << TARGET_SHMEDIA \
697 /* Standard register usage. */
699 /* Register allocation for the Renesas calling convention:
705 r14 frame pointer/call saved
707 ap arg pointer (doesn't really exist, always eliminated)
708 pr subroutine return address
710 mach multiply/accumulate result, high part
711 macl multiply/accumulate result, low part.
712 fpul fp/int communication register
713 rap return address pointer register
715 fr1..fr3 scratch floating point registers
717 fr12..fr15 call saved floating point registers */
719 #define MAX_REGISTER_NAME_LENGTH 5
720 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
722 #define SH_REGISTER_NAMES_INITIALIZER \
724 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
725 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
726 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
727 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
728 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
729 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
730 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
731 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
732 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
733 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
734 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
735 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
736 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
737 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
738 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
739 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
740 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
741 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
742 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
746 #define REGNAMES_ARR_INDEX_1(index) \
747 (sh_register_names[index])
748 #define REGNAMES_ARR_INDEX_2(index) \
749 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
750 #define REGNAMES_ARR_INDEX_4(index) \
751 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
752 #define REGNAMES_ARR_INDEX_8(index) \
753 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
754 #define REGNAMES_ARR_INDEX_16(index) \
755 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
756 #define REGNAMES_ARR_INDEX_32(index) \
757 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
758 #define REGNAMES_ARR_INDEX_64(index) \
759 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
761 #define REGISTER_NAMES \
763 REGNAMES_ARR_INDEX_64 (0), \
764 REGNAMES_ARR_INDEX_64 (64), \
765 REGNAMES_ARR_INDEX_8 (128), \
766 REGNAMES_ARR_INDEX_8 (136), \
767 REGNAMES_ARR_INDEX_8 (144), \
768 REGNAMES_ARR_INDEX_1 (152) \
771 #define ADDREGNAMES_SIZE 32
772 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
773 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
774 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
776 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
778 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
779 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
780 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
781 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
784 #define ADDREGNAMES_REGNO(index) \
785 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
788 #define ADDREGNAMES_ARR_INDEX_1(index) \
789 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
790 #define ADDREGNAMES_ARR_INDEX_2(index) \
791 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
792 #define ADDREGNAMES_ARR_INDEX_4(index) \
793 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
794 #define ADDREGNAMES_ARR_INDEX_8(index) \
795 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
796 #define ADDREGNAMES_ARR_INDEX_16(index) \
797 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
798 #define ADDREGNAMES_ARR_INDEX_32(index) \
799 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
801 #define ADDITIONAL_REGISTER_NAMES \
803 ADDREGNAMES_ARR_INDEX_32 (0) \
806 /* Number of actual hardware registers.
807 The hardware registers are assigned numbers for the compiler
808 from 0 to just below FIRST_PSEUDO_REGISTER.
809 All registers that the compiler knows about must be given numbers,
810 even those that are not normally considered general registers. */
812 /* There are many other relevant definitions in sh.md's md_constants. */
814 #define FIRST_GENERAL_REG R0_REG
815 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
816 #define FIRST_FP_REG DR0_REG
817 #define LAST_FP_REG (FIRST_FP_REG + \
818 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
819 #define FIRST_XD_REG XD0_REG
820 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
821 #define FIRST_TARGET_REG TR0_REG
822 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
824 #define GENERAL_REGISTER_P(REGNO) \
826 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
827 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
829 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
830 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
832 #define FP_REGISTER_P(REGNO) \
833 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
835 #define XD_REGISTER_P(REGNO) \
836 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
838 #define FP_OR_XD_REGISTER_P(REGNO) \
839 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
841 #define FP_ANY_REGISTER_P(REGNO) \
842 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
844 #define SPECIAL_REGISTER_P(REGNO) \
845 ((REGNO) == GBR_REG || (REGNO) == T_REG \
846 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
848 #define TARGET_REGISTER_P(REGNO) \
849 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
851 #define SHMEDIA_REGISTER_P(REGNO) \
852 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
853 || TARGET_REGISTER_P (REGNO))
855 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
856 that should be fixed. */
857 #define VALID_REGISTER_P(REGNO) \
858 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
859 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
860 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
861 || (TARGET_SH2E && (REGNO) == FPUL_REG))
863 /* The mode that should be generally used to store a register by
864 itself in the stack, or to load it back. */
865 #define REGISTER_NATURAL_MODE(REGNO) \
866 (FP_REGISTER_P (REGNO) ? SFmode \
867 : XD_REGISTER_P (REGNO) ? DFmode \
868 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
872 #define FIRST_PSEUDO_REGISTER 153
874 /* 1 for registers that have pervasive standard uses
875 and are not available for the register allocator.
877 Mach register is fixed 'cause it's only 10 bits wide for SH1.
878 It is 32 bits wide for SH2. */
880 #define FIXED_REGISTERS \
882 /* Regular registers. */ \
883 0, 0, 0, 0, 0, 0, 0, 0, \
884 0, 0, 0, 0, 0, 0, 0, 1, \
885 /* r16 is reserved, r18 is the former pr. */ \
886 1, 0, 0, 0, 0, 0, 0, 0, \
887 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
888 /* r26 is a global variable data pointer; r27 is for constants. */ \
889 1, 1, 1, 1, 0, 0, 0, 0, \
890 0, 0, 0, 0, 0, 0, 0, 0, \
891 0, 0, 0, 0, 0, 0, 0, 0, \
892 0, 0, 0, 0, 0, 0, 0, 0, \
893 0, 0, 0, 0, 0, 0, 0, 1, \
894 /* FP registers. */ \
895 0, 0, 0, 0, 0, 0, 0, 0, \
896 0, 0, 0, 0, 0, 0, 0, 0, \
897 0, 0, 0, 0, 0, 0, 0, 0, \
898 0, 0, 0, 0, 0, 0, 0, 0, \
899 0, 0, 0, 0, 0, 0, 0, 0, \
900 0, 0, 0, 0, 0, 0, 0, 0, \
901 0, 0, 0, 0, 0, 0, 0, 0, \
902 0, 0, 0, 0, 0, 0, 0, 0, \
903 /* Branch target registers. */ \
904 0, 0, 0, 0, 0, 0, 0, 0, \
905 /* XD registers. */ \
906 0, 0, 0, 0, 0, 0, 0, 0, \
907 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
908 1, 1, 1, 1, 1, 1, 0, 1, \
913 /* 1 for registers not available across function calls.
914 These must include the FIXED_REGISTERS and also any
915 registers that can be used without being saved.
916 The latter must include the registers where values are returned
917 and the register where structure-value addresses are passed.
918 Aside from that, you can include as many other registers as you like. */
920 #define CALL_USED_REGISTERS \
922 /* Regular registers. */ \
923 1, 1, 1, 1, 1, 1, 1, 1, \
924 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
925 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
926 across SH5 function calls. */ \
927 0, 0, 0, 0, 0, 0, 0, 1, \
928 1, 1, 1, 1, 1, 1, 1, 1, \
929 1, 1, 1, 1, 0, 0, 0, 0, \
930 0, 0, 0, 0, 1, 1, 1, 1, \
931 1, 1, 1, 1, 0, 0, 0, 0, \
932 0, 0, 0, 0, 0, 0, 0, 0, \
933 0, 0, 0, 0, 1, 1, 1, 1, \
934 /* FP registers. */ \
935 1, 1, 1, 1, 1, 1, 1, 1, \
936 1, 1, 1, 1, 0, 0, 0, 0, \
937 1, 1, 1, 1, 1, 1, 1, 1, \
938 1, 1, 1, 1, 1, 1, 1, 1, \
939 1, 1, 1, 1, 0, 0, 0, 0, \
940 0, 0, 0, 0, 0, 0, 0, 0, \
941 0, 0, 0, 0, 0, 0, 0, 0, \
942 0, 0, 0, 0, 0, 0, 0, 0, \
943 /* Branch target registers. */ \
944 1, 1, 1, 1, 1, 0, 0, 0, \
945 /* XD registers. */ \
946 1, 1, 1, 1, 1, 1, 0, 0, \
947 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
948 1, 1, 1, 1, 1, 1, 1, 1, \
953 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
954 across SHcompact function calls. We can't tell whether a called
955 function is SHmedia or SHcompact, so we assume it may be when
956 compiling SHmedia code with the 32-bit ABI, since that's the only
957 ABI that can be linked with SHcompact code. */
958 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
960 && GET_MODE_SIZE (MODE) > 4 \
961 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
962 && (REGNO) <= FIRST_GENERAL_REG + 15) \
963 || TARGET_REGISTER_P (REGNO) \
964 || (REGNO) == PR_MEDIA_REG))
966 /* Return number of consecutive hard regs needed starting at reg REGNO
967 to hold something of mode MODE.
968 This is ordinarily the length in words of a value of mode MODE
969 but can be less for certain modes in special long registers.
971 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
973 #define HARD_REGNO_NREGS(REGNO, MODE) \
974 (XD_REGISTER_P (REGNO) \
975 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
976 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
977 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
978 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
980 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
981 We can allow any mode in any general register. The special registers
982 only allow SImode. Don't allow any mode in the PR. */
984 /* We cannot hold DCmode values in the XD registers because alter_reg
985 handles subregs of them incorrectly. We could work around this by
986 spacing the XD registers like the DR registers, but this would require
987 additional memory in every compilation to hold larger register vectors.
988 We could hold SFmode / SCmode values in XD registers, but that
989 would require a tertiary reload when reloading from / to memory,
990 and a secondary reload to reload from / to general regs; that
991 seems to be a loosing proposition. */
992 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
993 it won't be ferried through GP registers first. */
994 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
995 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
996 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
997 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
999 : (MODE) == V2SFmode \
1000 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1001 || GENERAL_REGISTER_P (REGNO)) \
1002 : (MODE) == V4SFmode \
1003 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1004 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
1005 : (MODE) == V16SFmode \
1007 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1008 : (REGNO) == FIRST_XD_REG) \
1009 : FP_REGISTER_P (REGNO) \
1010 ? ((MODE) == SFmode || (MODE) == SImode \
1011 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1012 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
1013 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1014 || (MODE) == V2SFmode || (MODE) == TImode))) \
1015 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
1016 : XD_REGISTER_P (REGNO) \
1017 ? (MODE) == DFmode \
1018 : TARGET_REGISTER_P (REGNO) \
1019 ? ((MODE) == DImode || (MODE) == SImode) \
1020 : (REGNO) == PR_REG ? (MODE) == SImode \
1021 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1024 /* Value is 1 if MODE is a supported vector mode. */
1025 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1027 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
1028 || (TARGET_SHMEDIA \
1029 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
1030 || (MODE) == V2SImode)))
1032 /* Value is 1 if it is a good idea to tie two pseudo registers
1033 when one has mode MODE1 and one has mode MODE2.
1034 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1035 for any hard reg, then this must be 0 for correct output.
1036 That's the case for xd registers: we don't hold SFmode values in
1037 them, so we can't tie an SFmode pseudos with one in another
1038 floating-point mode. */
1040 #define MODES_TIEABLE_P(MODE1, MODE2) \
1041 ((MODE1) == (MODE2) \
1042 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1043 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1044 && (GET_MODE_SIZE (MODE2) <= 4)) \
1045 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1047 /* A C expression that is nonzero if hard register NEW_REG can be
1048 considered for use as a rename register for OLD_REG register */
1050 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1051 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1053 /* Specify the registers used for certain standard purposes.
1054 The values of these macros are register numbers. */
1056 /* Define this if the program counter is overloaded on a register. */
1057 /* #define PC_REGNUM 15*/
1059 /* Register to use for pushing function arguments. */
1060 #define STACK_POINTER_REGNUM SP_REG
1062 /* Base register for access to local variables of the function. */
1063 #define FRAME_POINTER_REGNUM FP_REG
1065 /* Fake register that holds the address on the stack of the
1066 current function's return address. */
1067 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1069 /* Register to hold the addressing base for position independent
1070 code access to data items. */
1071 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1073 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1075 /* Value should be nonzero if functions must have frame pointers.
1076 Zero means the frame pointer need not be set up (and parms may be accessed
1077 via the stack pointer) in functions that seem suitable. */
1079 #define FRAME_POINTER_REQUIRED 0
1081 /* Definitions for register eliminations.
1083 We have three registers that can be eliminated on the SH. First, the
1084 frame pointer register can often be eliminated in favor of the stack
1085 pointer register. Secondly, the argument pointer register can always be
1086 eliminated; it is replaced with either the stack or frame pointer.
1087 Third, there is the return address pointer, which can also be replaced
1088 with either the stack or the frame pointer. */
1090 /* This is an array of structures. Each structure initializes one pair
1091 of eliminable registers. The "from" register number is given first,
1092 followed by "to". Eliminations of the same "from" register are listed
1093 in order of preference. */
1095 /* If you add any registers here that are not actually hard registers,
1096 and that have any alternative of elimination that doesn't always
1097 apply, you need to amend calc_live_regs to exclude it, because
1098 reload spills all eliminable registers where it sees an
1099 can_eliminate == 0 entry, thus making them 'live' .
1100 If you add any hard registers that can be eliminated in different
1101 ways, you have to patch reload to spill them only when all alternatives
1102 of elimination fail. */
1104 #define ELIMINABLE_REGS \
1105 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1106 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1107 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1108 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1109 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1111 /* Given FROM and TO register numbers, say whether this elimination
1113 #define CAN_ELIMINATE(FROM, TO) \
1114 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1116 /* Define the offset between two registers, one to be eliminated, and the other
1117 its replacement, at the start of a routine. */
1119 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1120 OFFSET = initial_elimination_offset ((FROM), (TO))
1122 /* Base register for access to arguments of the function. */
1123 #define ARG_POINTER_REGNUM AP_REG
1125 /* Register in which the static-chain is passed to a function. */
1126 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1128 /* Don't default to pcc-struct-return, because we have already specified
1129 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1132 #define DEFAULT_PCC_STRUCT_RETURN 0
1134 #define SHMEDIA_REGS_STACK_ADJUST() \
1135 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1136 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1137 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1141 /* Define the classes of registers for register constraints in the
1142 machine description. Also define ranges of constants.
1144 One of the classes must always be named ALL_REGS and include all hard regs.
1145 If there is more than one class, another class must be named NO_REGS
1146 and contain no registers.
1148 The name GENERAL_REGS must be the name of a class (or an alias for
1149 another name such as ALL_REGS). This is the class of registers
1150 that is allowed by "g" or "r" in a register constraint.
1151 Also, registers outside this class are allocated only when
1152 instructions express preferences for them.
1154 The classes must be numbered in nondecreasing order; that is,
1155 a larger-numbered class must never be contained completely
1156 in a smaller-numbered class.
1158 For any two classes, it is very desirable that there be another
1159 class that represents their union. */
1161 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1162 be used as the destination of some of the arithmetic ops. There are
1163 also some special purpose registers; the T bit register, the
1164 Procedure Return Register and the Multiply Accumulate Registers. */
1165 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1166 reg_class_subunion. We don't want to have an actual union class
1167 of these, because it would only be used when both classes are calculated
1168 to give the same cost, but there is only one FPUL register.
1169 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1170 applying to the actual instruction alternative considered. E.g., the
1171 y/r alternative of movsi_ie is considered to have no more cost that
1172 the r/r alternative, which is patently untrue. */
1195 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1197 /* Give names of register classes as strings for dump file. */
1198 #define REG_CLASS_NAMES \
1213 "GENERAL_FP_REGS", \
1218 /* Define which registers fit in which classes.
1219 This is an initializer for a vector of HARD_REG_SET
1220 of length N_REG_CLASSES. */
1222 #define REG_CLASS_CONTENTS \
1225 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1227 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1229 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1231 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1233 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1235 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1236 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1237 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1238 /* GENERAL_REGS: */ \
1239 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1241 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1243 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1244 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1245 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1247 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1249 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1250 /* GENERAL_FP_REGS: */ \
1251 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1252 /* TARGET_REGS: */ \
1253 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1255 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1258 /* The same information, inverted:
1259 Return the class number of the smallest class containing
1260 reg number REGNO. This could be a conditional expression
1261 or could index an array. */
1263 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1264 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1266 /* When defined, the compiler allows registers explicitly used in the
1267 rtl to be used as spill registers but prevents the compiler from
1268 extending the lifetime of these registers. */
1270 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1272 /* The order in which register should be allocated. */
1273 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1274 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1275 spilled or used otherwise, we better have the FP_REGS allocated first. */
1276 #define REG_ALLOC_ORDER \
1277 {/* Caller-saved FPRs */ \
1278 65, 66, 67, 68, 69, 70, 71, 64, \
1279 72, 73, 74, 75, 80, 81, 82, 83, \
1280 84, 85, 86, 87, 88, 89, 90, 91, \
1281 92, 93, 94, 95, 96, 97, 98, 99, \
1282 /* Callee-saved FPRs */ \
1283 76, 77, 78, 79,100,101,102,103, \
1284 104,105,106,107,108,109,110,111, \
1285 112,113,114,115,116,117,118,119, \
1286 120,121,122,123,124,125,126,127, \
1287 136,137,138,139,140,141,142,143, \
1289 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1290 1, 2, 3, 7, 6, 5, 4, 0, \
1291 8, 9, 17, 19, 20, 21, 22, 23, \
1292 36, 37, 38, 39, 40, 41, 42, 43, \
1294 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1295 10, 11, 12, 13, 14, 18, \
1296 /* SH5 callee-saved GPRs */ \
1297 28, 29, 30, 31, 32, 33, 34, 35, \
1298 44, 45, 46, 47, 48, 49, 50, 51, \
1299 52, 53, 54, 55, 56, 57, 58, 59, \
1301 /* SH5 branch target registers */ \
1302 128,129,130,131,132,133,134,135, \
1303 /* Fixed registers */ \
1304 15, 16, 24, 25, 26, 27, 63,144, \
1305 145,146,147,148,149,152 }
1307 /* The class value for index registers, and the one for base regs. */
1308 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1309 #define BASE_REG_CLASS GENERAL_REGS
1311 /* Get reg_class from a letter such as appears in the machine
1313 extern enum reg_class reg_class_from_letter[];
1315 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1316 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1317 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1319 /* Overview of uppercase letter constraints:
1320 A: Addresses (constraint len == 3)
1321 Ac4: sh4 cache operations
1322 Ac5: sh5 cache operations
1323 Bxx: miscellaneous constraints
1324 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1326 C: Constants other than only CONST_INT (constraint len == 3)
1327 C16: 16 bit constant, literal or symbolic
1328 Csy: label or symbol
1329 Cpg: non-explicit constants that can be directly loaded into a general
1330 purpose register in PIC code. like 's' except we don't allow
1332 IJKLMNOP: CONT_INT constants
1334 J16: 0xffffffff00000000 | 0x00000000ffffffff
1335 Kxx: unsigned xx bit
1339 Q: pc relative load operand
1340 Rxx: reserved for exotic register classes.
1341 S: extra memory (storage) constraints (constraint len == 3)
1342 Sua: unaligned memory operations
1346 unused CONST_INT constraint letters: LO
1347 unused EXTRA_CONSTRAINT letters: D T U Y */
1349 #if 1 /* check that the transition went well. */
1350 #define CONSTRAINT_LEN(C,STR) \
1351 (((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
1354 && (((STR)[1] != '0' && (STR)[1] != '1') \
1355 || (STR)[2] < '0' || (STR)[2] > '9')) \
1356 || ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
1357 || ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
1358 || ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
1359 || ((C) == 'P' && ((STR)[1] != '2' || (STR)[2] != '7'))) \
1361 : ((C) == 'A' || (C) == 'B' || (C) == 'C' \
1362 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1363 || (C) == 'R' || (C) == 'S') \
1365 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1367 #define CONSTRAINT_LEN(C,STR) \
1368 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1369 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1370 || (C) == 'R' || (C) == 'S') \
1371 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1374 /* The letters I, J, K, L and M in a register constraint string
1375 can be used to stand for particular ranges of immediate operands.
1376 This macro defines what the ranges are.
1377 C is the letter, and VALUE is a constant value.
1378 Return 1 if VALUE is in the range specified by C.
1379 I08: arithmetic operand -127..128, as used in add, sub, etc
1380 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1381 P27: shift operand 1,2,8 or 16
1382 K08: logical operand 0..255, as used in and, or, etc.
1385 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1386 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1389 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1390 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1391 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1392 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1393 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1394 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1395 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1396 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1397 #define CONST_OK_FOR_I(VALUE, STR) \
1398 ((STR)[1] == '0' && (STR)[2] == 6 ? CONST_OK_FOR_I06 (VALUE) \
1399 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1400 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1401 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1404 #define CONST_OK_FOR_J16(VALUE) \
1405 (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff \
1406 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1407 #define CONST_OK_FOR_J(VALUE, STR) \
1408 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1411 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1412 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1413 #define CONST_OK_FOR_K(VALUE, STR) \
1414 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1416 #define CONST_OK_FOR_P27(VALUE) \
1417 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1418 #define CONST_OK_FOR_P(VALUE, STR) \
1419 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1421 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1422 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1423 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1424 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1425 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1426 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1427 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1428 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1429 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1432 /* Similar, but for floating constants, and defining letters G and H.
1433 Here VALUE is the CONST_DOUBLE rtx itself. */
1435 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1436 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1437 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1440 /* Given an rtx X being reloaded into a reg required to be
1441 in class CLASS, return the class of reg to actually use.
1442 In general this is just CLASS; but on some machines
1443 in some cases it is preferable to use a more restrictive class. */
1445 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1446 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1447 && (GET_CODE (X) == CONST_DOUBLE \
1448 || GET_CODE (X) == SYMBOL_REF) \
1452 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1453 ((((REGCLASS_HAS_FP_REG (CLASS) \
1454 && (GET_CODE (X) == REG \
1455 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1456 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1457 && TARGET_FMOVD)))) \
1458 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1459 && GET_CODE (X) == REG \
1460 && FP_REGISTER_P (REGNO (X)))) \
1461 && ! TARGET_SHMEDIA \
1462 && ((MODE) == SFmode || (MODE) == SImode)) \
1464 : (((CLASS) == FPUL_REGS \
1465 || (REGCLASS_HAS_FP_REG (CLASS) \
1466 && ! TARGET_SHMEDIA && MODE == SImode)) \
1467 && (GET_CODE (X) == MEM \
1468 || (GET_CODE (X) == REG \
1469 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1470 || REGNO (X) == T_REG \
1471 || system_reg_operand (X, VOIDmode))))) \
1473 : ((CLASS) == TARGET_REGS \
1474 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1475 ? ((target_operand ((X), (MODE)) \
1476 && ! target_reg_operand ((X), (MODE))) \
1477 ? NO_REGS : GENERAL_REGS) \
1478 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1479 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1480 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1482 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1483 && TARGET_REGISTER_P (REGNO (X))) \
1484 ? GENERAL_REGS : NO_REGS)
1486 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1487 ((REGCLASS_HAS_FP_REG (CLASS) \
1488 && ! TARGET_SHMEDIA \
1489 && immediate_operand ((X), (MODE)) \
1490 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1491 && (MODE) == SFmode && fldi_ok ())) \
1493 : (CLASS == FPUL_REGS \
1494 && ((GET_CODE (X) == REG \
1495 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1496 || REGNO (X) == T_REG)) \
1497 || GET_CODE (X) == PLUS)) \
1499 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1500 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1503 : (CLASS == FPSCR_REGS \
1504 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1505 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1507 : (REGCLASS_HAS_FP_REG (CLASS) \
1509 && immediate_operand ((X), (MODE)) \
1510 && (X) != CONST0_RTX (GET_MODE (X)) \
1511 && GET_MODE (X) != V4SFmode) \
1513 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1515 /* Return the maximum number of consecutive registers
1516 needed to represent mode MODE in a register of class CLASS.
1518 If TARGET_SHMEDIA, we need two FP registers per word.
1519 Otherwise we will need at most one register per word. */
1520 #define CLASS_MAX_NREGS(CLASS, MODE) \
1522 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1523 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1524 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1526 /* If defined, gives a class of registers that cannot be used as the
1527 operand of a SUBREG that changes the mode of the object illegally. */
1528 /* ??? We need to renumber the internal numbers for the frnn registers
1529 when in little endian in order to allow mode size changes. */
1531 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1532 sh_cannot_change_mode_class (FROM, TO, CLASS)
1534 /* Stack layout; function entry, exit and calling. */
1536 /* Define the number of registers that can hold parameters.
1537 These macros are used only in other macro definitions below. */
1539 #define NPARM_REGS(MODE) \
1540 (TARGET_FPU_ANY && (MODE) == SFmode \
1541 ? (TARGET_SH5 ? 12 : 8) \
1542 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1543 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1544 ? (TARGET_SH5 ? 12 : 8) \
1545 : (TARGET_SH5 ? 8 : 4))
1547 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1548 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1550 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1551 #define FIRST_FP_RET_REG FIRST_FP_REG
1553 /* Define this if pushing a word on the stack
1554 makes the stack pointer a smaller address. */
1555 #define STACK_GROWS_DOWNWARD
1557 /* Define this macro if the addresses of local variable slots are at
1558 negative offsets from the frame pointer.
1560 The SH only has positive indexes, so grow the frame up. */
1561 /* #define FRAME_GROWS_DOWNWARD */
1563 /* Offset from the frame pointer to the first local variable slot to
1565 #define STARTING_FRAME_OFFSET 0
1567 /* If we generate an insn to push BYTES bytes,
1568 this says how many the stack pointer really advances by. */
1569 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1570 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1571 do correct alignment. */
1573 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1576 /* Offset of first parameter from the argument pointer register value. */
1577 #define FIRST_PARM_OFFSET(FNDECL) 0
1579 /* Value is the number of byte of arguments automatically
1580 popped when returning from a subroutine call.
1581 FUNDECL is the declaration node of the function (as a tree),
1582 FUNTYPE is the data type of the function (as a tree),
1583 or for a library call it is an identifier node for the subroutine name.
1584 SIZE is the number of bytes of arguments passed on the stack.
1586 On the SH, the caller does not pop any of its arguments that were passed
1588 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1590 /* Value is the number of bytes of arguments automatically popped when
1591 calling a subroutine.
1592 CUM is the accumulated argument list.
1594 On SHcompact, the call trampoline pops arguments off the stack. */
1595 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1597 /* Nonzero if we do not know how to pass TYPE solely in registers.
1598 Values that come in registers with inconvenient padding are stored
1599 to memory at the function start. */
1601 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1603 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1604 || TREE_ADDRESSABLE (TYPE)))
1605 /* Some subroutine macros specific to this machine. */
1607 #define BASE_RETURN_VALUE_REG(MODE) \
1608 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1609 ? FIRST_FP_RET_REG \
1610 : TARGET_FPU_ANY && (MODE) == SCmode \
1611 ? FIRST_FP_RET_REG \
1612 : (TARGET_FPU_DOUBLE \
1613 && ((MODE) == DFmode || (MODE) == SFmode \
1614 || (MODE) == DCmode || (MODE) == SCmode )) \
1615 ? FIRST_FP_RET_REG \
1618 #define BASE_ARG_REG(MODE) \
1619 ((TARGET_SH2E && ((MODE) == SFmode)) \
1620 ? FIRST_FP_PARM_REG \
1621 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1622 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1623 ? FIRST_FP_PARM_REG \
1626 /* Define how to find the value returned by a function.
1627 VALTYPE is the data type of the value (as a tree).
1628 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1629 otherwise, FUNC is 0.
1630 For the SH, this is like LIBCALL_VALUE, except that we must change the
1631 mode like PROMOTE_MODE does.
1632 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1633 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1635 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1637 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1638 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1639 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1640 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1641 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1642 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1643 || TREE_CODE (VALTYPE) == REAL_TYPE \
1644 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1645 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1646 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1648 /* Define how to find the value returned by a library function
1649 assuming the value has mode MODE. */
1650 #define LIBCALL_VALUE(MODE) \
1651 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1653 /* 1 if N is a possible register number for a function value. */
1654 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1655 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1656 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1658 /* 1 if N is a possible register number for function argument passing. */
1659 /* ??? There are some callers that pass REGNO as int, and others that pass
1660 it as unsigned. We get warnings unless we do casts everywhere. */
1661 #define FUNCTION_ARG_REGNO_P(REGNO) \
1662 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1663 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1664 || (TARGET_FPU_ANY \
1665 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1666 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1667 + NPARM_REGS (SFmode))))
1669 /* Define a data type for recording info about an argument list
1670 during the scan of that argument list. This data type should
1671 hold all necessary information about the function itself
1672 and about the args processed so far, enough to enable macros
1673 such as FUNCTION_ARG to determine where the next arg should go.
1675 On SH, this is a single integer, which is a number of words
1676 of arguments scanned so far (including the invisible argument,
1677 if any, which holds the structure-value-address).
1678 Thus NARGREGS or more means all following args should go on the stack. */
1680 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1684 /* Nonzero if a prototype is available for the function. */
1686 /* The number of an odd floating-point register, that should be used
1687 for the next argument of type float. */
1688 int free_single_fp_reg;
1689 /* Whether we're processing an outgoing function call. */
1691 /* The number of general-purpose registers that should have been
1692 used to pass partial arguments, that are passed totally on the
1693 stack. On SHcompact, a call trampoline will pop them off the
1694 stack before calling the actual function, and, if the called
1695 function is implemented in SHcompact mode, the incoming arguments
1696 decoder will push such arguments back onto the stack. For
1697 incoming arguments, STACK_REGS also takes into account other
1698 arguments passed by reference, that the decoder will also push
1701 /* The number of general-purpose registers that should have been
1702 used to pass arguments, if the arguments didn't have to be passed
1705 /* Set by SHCOMPACT_BYREF if the current argument is to be passed by
1709 /* call_cookie is a bitmask used by call expanders, as well as
1710 function prologue and epilogues, to allow SHcompact to comply
1711 with the SH5 32-bit ABI, that requires 64-bit registers to be
1712 used even though only the lower 32-bit half is visible in
1713 SHcompact mode. The strategy is to call SHmedia trampolines.
1715 The alternatives for each of the argument-passing registers are
1716 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1717 contents from the address in it; (d) add 8 to it, storing the
1718 result in the next register, then (c); (e) copy it from some
1719 floating-point register,
1721 Regarding copies from floating-point registers, r2 may only be
1722 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1723 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1724 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1725 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1728 The bit mask is structured as follows:
1730 - 1 bit to tell whether to set up a return trampoline.
1732 - 3 bits to count the number consecutive registers to pop off the
1735 - 4 bits for each of r9, r8, r7 and r6.
1737 - 3 bits for each of r5, r4, r3 and r2.
1739 - 3 bits set to 0 (the most significant ones)
1742 1098 7654 3210 9876 5432 1098 7654 3210
1743 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1744 2223 3344 4555 6666 7777 8888 9999 SSS-
1746 - If F is set, the register must be copied from an FP register,
1747 whose number is encoded in the remaining bits.
1749 - Else, if L is set, the register must be loaded from the address
1750 contained in it. If the P bit is *not* set, the address of the
1751 following dword should be computed first, and stored in the
1754 - Else, if P is set, the register alone should be popped off the
1757 - After all this processing, the number of registers represented
1758 in SSS will be popped off the stack. This is an optimization
1759 for pushing/popping consecutive registers, typically used for
1760 varargs and large arguments partially passed in registers.
1762 - If T is set, a return trampoline will be set up for 64-bit
1763 return values to be split into 2 32-bit registers. */
1764 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1765 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1766 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1767 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1768 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1769 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1770 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1771 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1772 #define CALL_COOKIE_INT_REG(REG, VAL) \
1773 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1774 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1775 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1778 /* This is set to nonzero when the call in question must use the Renesas ABI,
1779 even without the -mrenesas option. */
1783 #define CUMULATIVE_ARGS struct sh_args
1785 #define GET_SH_ARG_CLASS(MODE) \
1786 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1788 /* There's no mention of complex float types in the SH5 ABI, so we
1789 should presumably handle them as aggregate types. */ \
1790 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1792 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1793 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1794 ? SH_ARG_FLOAT : SH_ARG_INT)
1796 #define ROUND_ADVANCE(SIZE) \
1797 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1799 /* Round a register number up to a proper boundary for an arg of mode
1802 The SH doesn't care about double alignment, so we only
1803 round doubles to even regs when asked to explicitly. */
1805 #define ROUND_REG(CUM, MODE) \
1806 (((TARGET_ALIGN_DOUBLE \
1807 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1808 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1809 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1810 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1811 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1812 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1814 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1815 for a call to a function whose data type is FNTYPE.
1816 For a library call, FNTYPE is 0.
1818 On SH, the offset always starts at 0: the first parm reg is always
1819 the same reg for a given argument class.
1821 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1823 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
1825 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1826 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1827 (CUM).renesas_abi = sh_attr_renesas_p (FNTYPE) ? 1 : 0; \
1829 = ((TARGET_HITACHI || (CUM).renesas_abi) && (FNTYPE) \
1830 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
1831 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
1832 (CUM).arg_count[(int) SH_ARG_INT] \
1833 = (TARGET_SH5 && (FNTYPE) \
1834 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
1835 (CUM).free_single_fp_reg = 0; \
1836 (CUM).outgoing = 1; \
1837 (CUM).stack_regs = 0; \
1838 (CUM).byref_regs = 0; \
1841 = (CALL_COOKIE_RET_TRAMP \
1842 (TARGET_SHCOMPACT && (FNTYPE) \
1843 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
1844 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
1845 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
1846 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
1847 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
1849 == FIRST_RET_REG))); \
1852 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1854 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0); \
1856 = (CALL_COOKIE_RET_TRAMP \
1857 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
1858 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
1861 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1863 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0); \
1864 (CUM).outgoing = 0; \
1867 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1868 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1869 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1870 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1872 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1873 This macro is only used in this file. */
1875 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1877 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1878 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1879 || ! (AGGREGATE_TYPE_P (TYPE) \
1880 || (!TARGET_FPU_ANY \
1881 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1882 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1883 && ! (CUM).force_mem \
1885 ? ((MODE) == BLKmode \
1886 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1887 + int_size_in_bytes (TYPE)) \
1888 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1889 : ((ROUND_REG((CUM), (MODE)) \
1890 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1891 <= NPARM_REGS (MODE))) \
1892 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1894 /* By accident we got stuck with passing SCmode on SH4 little endian
1895 in two registers that are nominally successive - which is different from
1896 two single SFmode values, where we take endianness translation into
1897 account. That does not work at all if an odd number of registers is
1898 already in use, so that got fixed, but library functions are still more
1899 likely to use complex numbers without mixing them with SFmode arguments
1900 (which in C would have to be structures), so for the sake of ABI
1901 compatibility the way SCmode values are passed when an even number of
1902 FP registers is in use remains different from a pair of SFmode values for
1905 foo (double); a: fr5,fr4
1906 foo (float a, float b); a: fr5 b: fr4
1907 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1908 this should be the other way round...
1909 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1910 #define FUNCTION_ARG_SCmode_WART 1
1912 /* Whether an argument must be passed by reference. On SHcompact, we
1913 pretend arguments wider than 32-bits that would have been passed in
1914 registers are passed by reference, so that an SHmedia trampoline
1915 loads them into the full 64-bits registers. */
1916 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) \
1917 (MUST_PASS_IN_STACK ((MODE), (TYPE)) \
1918 || SHCOMPACT_BYREF ((CUM), (MODE), (TYPE), (NAMED)))
1920 #define SHCOMPACT_BYREF(CUM, MODE, TYPE, NAMED) \
1922 = (TARGET_SHCOMPACT \
1923 && (CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1924 && (! (NAMED) || GET_SH_ARG_CLASS (MODE) == SH_ARG_INT \
1925 || (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1926 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1927 >= NPARM_REGS (SFmode)))) \
1928 && ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1929 : GET_MODE_SIZE (MODE)) > 4 \
1930 && ! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1931 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1933 ? ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1934 : GET_MODE_SIZE (MODE)) \
1937 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1938 register in SHcompact mode, it must be padded in the most
1939 significant end. This means that passing it by reference wouldn't
1940 pad properly on a big-endian machine. In this particular case, we
1941 pass this argument on the stack, in a way that the call trampoline
1942 will load its value into the appropriate register. */
1943 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1944 ((MODE) == BLKmode \
1945 && TARGET_SHCOMPACT \
1946 && ! TARGET_LITTLE_ENDIAN \
1947 && int_size_in_bytes (TYPE) > 4 \
1948 && int_size_in_bytes (TYPE) < 8)
1950 /* Minimum alignment for an argument to be passed by callee-copy
1951 reference. We need such arguments to be aligned to 8 byte
1952 boundaries, because they'll be loaded using quad loads. */
1953 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1955 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
1957 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
1958 : GET_MODE_ALIGNMENT (MODE)) \
1959 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
1961 /* The SH5 ABI requires floating-point arguments to be passed to
1962 functions without a prototype in both an FP register and a regular
1963 register or the stack. When passing the argument in both FP and
1964 general-purpose registers, list the FP register first. */
1965 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1971 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1972 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1973 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1978 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1979 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1980 + (CUM).arg_count[(int) SH_ARG_INT]) \
1981 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1982 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1985 /* The SH5 ABI requires regular registers or stack slots to be
1986 reserved for floating-point arguments. Registers are taken care of
1987 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1988 Unfortunately, there's no way to just reserve a stack slot, so
1989 we'll end up needlessly storing a copy of the argument in the
1990 stack. For incoming arguments, however, the PARALLEL will be
1991 optimized to the register-only form, and the value in the stack
1992 slot won't be used at all. */
1993 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1994 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1995 ? gen_rtx_REG ((MODE), (REG)) \
1996 : gen_rtx_PARALLEL ((MODE), \
1999 (VOIDmode, NULL_RTX, \
2002 (VOIDmode, gen_rtx_REG ((MODE), \
2006 /* For an arg passed partly in registers and partly in memory,
2007 this is the number of registers used.
2008 For args passed entirely in registers or entirely in memory, zero.
2010 We sometimes split args. */
2012 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2014 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2016 && (ROUND_REG ((CUM), (MODE)) \
2017 + ((MODE) != BLKmode \
2018 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2019 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2020 > NPARM_REGS (MODE))) \
2021 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2022 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2023 && ! TARGET_SHCOMPACT) \
2024 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2027 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2029 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2030 || (MODE) == DCmode) \
2031 && ((CUM).arg_count[(int) SH_ARG_INT] \
2032 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2034 /* Perform any needed actions needed for a function that is receiving a
2035 variable number of arguments. */
2037 /* Implement `va_start' for varargs and stdarg. */
2038 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2039 sh_va_start (valist, nextarg)
2041 /* Implement `va_arg'. */
2042 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2043 sh_va_arg (valist, type)
2045 /* Call the function profiler with a given profile label.
2046 We use two .aligns, so as to make sure that both the .long is aligned
2047 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2048 from the trapa instruction. */
2050 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2052 fprintf((STREAM), "\t.align\t2\n"); \
2053 fprintf((STREAM), "\ttrapa\t#33\n"); \
2054 fprintf((STREAM), "\t.align\t2\n"); \
2055 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2058 /* Define this macro if the code for function profiling should come
2059 before the function prologue. Normally, the profiling code comes
2062 #define PROFILE_BEFORE_PROLOGUE
2064 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2065 the stack pointer does not matter. The value is tested only in
2066 functions that have frame pointers.
2067 No definition is equivalent to always zero. */
2069 #define EXIT_IGNORE_STACK 1
2072 On the SH, the trampoline looks like
2073 2 0002 D202 mov.l l2,r2
2074 1 0000 D301 mov.l l1,r3
2077 5 0008 00000000 l1: .long area
2078 6 000c 00000000 l2: .long function */
2080 /* Length in units of the trampoline for entering a nested function. */
2081 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2083 /* Alignment required for a trampoline in bits . */
2084 #define TRAMPOLINE_ALIGNMENT \
2085 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2086 : TARGET_SHMEDIA ? 256 : 64)
2088 /* Emit RTL insns to initialize the variable parts of a trampoline.
2089 FNADDR is an RTX for the address of the function's pure code.
2090 CXT is an RTX for the static chain value for the function. */
2092 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2093 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2095 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2097 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2099 if (TARGET_SHMEDIA) \
2100 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), GEN_INT (1), \
2101 gen_reg_rtx (Pmode), 0, \
2105 /* A C expression whose value is RTL representing the value of the return
2106 address for the frame COUNT steps up from the current frame.
2107 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2108 can ignore COUNT. */
2110 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2111 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2113 /* A C expression whose value is RTL representing the location of the
2114 incoming return address at the beginning of any function, before the
2115 prologue. This RTL is either a REG, indicating that the return
2116 value is saved in REG, or a MEM representing a location in
2118 #define INCOMING_RETURN_ADDR_RTX \
2119 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2121 /* Addressing modes, and classification of registers for them. */
2122 #define HAVE_POST_INCREMENT TARGET_SH1
2123 #define HAVE_PRE_DECREMENT TARGET_SH1
2125 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2127 #define USE_LOAD_PRE_DECREMENT(mode) 0
2128 #define USE_STORE_POST_INCREMENT(mode) 0
2129 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2132 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2133 < (TARGET_SMALLCODE ? 2 : \
2134 ((ALIGN >= 32) ? 16 : 2)))
2136 /* Macros to check register numbers against specific register classes. */
2138 /* These assume that REGNO is a hard or pseudo reg number.
2139 They give nonzero only if REGNO is a hard reg of the suitable class
2140 or a pseudo reg currently allocated to a suitable hard reg.
2141 Since they use reg_renumber, they are safe only once reg_renumber
2142 has been allocated, which happens in local-alloc.c. */
2144 #define REGNO_OK_FOR_BASE_P(REGNO) \
2145 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2146 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2147 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2149 ? (GENERAL_REGISTER_P (REGNO) \
2150 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2151 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2153 /* Maximum number of registers that can appear in a valid memory
2156 #define MAX_REGS_PER_ADDRESS 2
2158 /* Recognize any constant value that is a valid address. */
2160 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2162 /* Nonzero if the constant value X is a legitimate general operand. */
2164 #define LEGITIMATE_CONSTANT_P(X) \
2166 ? ((GET_MODE (X) != DFmode \
2167 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2168 || (X) == CONST0_RTX (GET_MODE (X)) \
2169 || ! TARGET_SHMEDIA_FPU \
2170 || TARGET_SHMEDIA64) \
2171 : (GET_CODE (X) != CONST_DOUBLE \
2172 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2173 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2175 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2176 and check its validity for a certain class.
2177 We have two alternate definitions for each of them.
2178 The usual definition accepts all pseudo regs; the other rejects
2179 them unless they have been allocated suitable hard regs.
2180 The symbol REG_OK_STRICT causes the latter definition to be used. */
2182 #ifndef REG_OK_STRICT
2184 /* Nonzero if X is a hard reg that can be used as a base reg
2185 or if it is a pseudo reg. */
2186 #define REG_OK_FOR_BASE_P(X) \
2187 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2189 /* Nonzero if X is a hard reg that can be used as an index
2190 or if it is a pseudo reg. */
2191 #define REG_OK_FOR_INDEX_P(X) \
2192 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2193 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2195 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2196 or if X is a pseudo reg. */
2197 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2198 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2199 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2203 /* Nonzero if X is a hard reg that can be used as a base reg. */
2204 #define REG_OK_FOR_BASE_P(X) \
2205 REGNO_OK_FOR_BASE_P (REGNO (X))
2207 /* Nonzero if X is a hard reg that can be used as an index. */
2208 #define REG_OK_FOR_INDEX_P(X) \
2209 REGNO_OK_FOR_INDEX_P (REGNO (X))
2211 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2212 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2213 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2217 /* The 'Q' constraint is a pc relative load operand. */
2218 #define EXTRA_CONSTRAINT_Q(OP) \
2219 (GET_CODE (OP) == MEM \
2220 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2221 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2222 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2223 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2224 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2226 /* Extra address constraints. */
2227 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2229 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2230 operand is not SCRATCH (i.e. REG) then R0 is probably being
2231 used, hence mova is being used, hence do not select this pattern */
2232 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2233 #define EXTRA_CONSTRAINT_B(OP, STR) \
2234 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2237 /* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2238 #define EXTRA_CONSTRAINT_C16(OP) \
2239 (GET_CODE (OP) == CONST \
2240 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2241 && GET_MODE (XEXP ((OP), 0)) == DImode \
2242 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2243 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2244 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2245 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2246 && (MOVI_SHORI_BASE_OPERAND_P \
2247 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2248 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2251 /* Check whether OP is a datalabel unspec. */
2252 #define DATALABEL_REF_NO_CONST_P(OP) \
2253 (GET_CODE (OP) == UNSPEC \
2254 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2255 && XVECLEN ((OP), 0) == 1 \
2256 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2257 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2259 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2261 #define DATALABEL_REF_P(OP) \
2262 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2263 || DATALABEL_REF_NO_CONST_P (OP))
2265 #define GOT_ENTRY_P(OP) \
2266 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2267 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2269 #define GOTPLT_ENTRY_P(OP) \
2270 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2271 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2273 #define UNSPEC_GOTOFF_P(OP) \
2274 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2276 #define GOTOFF_P(OP) \
2277 (GET_CODE (OP) == CONST \
2278 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2279 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2280 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2281 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2283 #define PIC_ADDR_P(OP) \
2284 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2285 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2287 #define PIC_OFFSET_P(OP) \
2289 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2290 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2292 #define PIC_DIRECT_ADDR_P(OP) \
2293 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2295 #define NON_PIC_REFERENCE_P(OP) \
2296 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2297 || DATALABEL_REF_P (OP) \
2298 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2299 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2300 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2301 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2303 #define PIC_REFERENCE_P(OP) \
2304 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2305 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2307 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2309 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2310 || PIC_OFFSET_P (OP)) \
2311 : NON_PIC_REFERENCE_P (OP))
2313 /* The `Csy' constraint is a label or a symbol. */
2314 #define EXTRA_CONSTRAINT_Csy(OP) \
2315 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2317 /* A zero in any shape or form. */
2318 #define EXTRA_CONSTRAINT_Z(OP) \
2319 ((OP) == CONST0_RTX (GET_MODE (OP)))
2321 /* Any vector constant we can handle. */
2322 #define EXTRA_CONSTRAINT_W(OP) \
2323 (GET_CODE (OP) == CONST_VECTOR \
2324 && (sh_rep_vec ((OP), VOIDmode) \
2325 || (HOST_BITS_PER_WIDE_INT >= 64 \
2326 ? sh_const_vec ((OP), VOIDmode) \
2327 : sh_1el_vec ((OP), VOIDmode))))
2329 /* A non-explicit constant that can be loaded directly into a general purpose
2330 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2331 #define EXTRA_CONSTRAINT_Cpg(OP) \
2333 && GET_CODE (OP) != CONST_INT \
2334 && GET_CODE (OP) != CONST_DOUBLE \
2336 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2337 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2338 && GET_CODE (OP) != LABEL_REF)))
2339 #define EXTRA_CONSTRAINT_C(OP, STR) \
2340 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2341 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2342 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2345 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2346 #define EXTRA_CONSTRAINT_Sr0(OP) \
2347 (memory_operand((OP), GET_MODE (OP)) \
2348 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2349 #define EXTRA_CONSTRAINT_S(OP, STR) \
2350 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2353 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2354 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2355 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2356 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2357 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2358 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2359 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2360 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2363 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2364 that is a valid memory address for an instruction.
2365 The MODE argument is the machine mode for the MEM expression
2366 that wants to use this address. */
2368 #define MODE_DISP_OK_4(X,MODE) \
2369 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2370 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2372 #define MODE_DISP_OK_8(X,MODE) \
2373 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2374 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2376 #define BASE_REGISTER_RTX_P(X) \
2377 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2378 || (GET_CODE (X) == SUBREG \
2379 && GET_CODE (SUBREG_REG (X)) == REG \
2380 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2382 /* Since this must be r0, which is a single register class, we must check
2383 SUBREGs more carefully, to be sure that we don't accept one that extends
2384 outside the class. */
2385 #define INDEX_REGISTER_RTX_P(X) \
2386 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2387 || (GET_CODE (X) == SUBREG \
2388 && GET_CODE (SUBREG_REG (X)) == REG \
2389 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2391 /* Jump to LABEL if X is a valid address RTX. This must also take
2392 REG_OK_STRICT into account when deciding about valid registers, but it uses
2393 the above macros so we are in luck.
2401 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2402 into the FRx registers. We implement this by setting the maximum offset
2403 to zero when the value is SFmode. This also restricts loading of SFmode
2404 values into the integer registers, but that can't be helped. */
2406 /* The SH allows a displacement in a QI or HI amode, but only when the
2407 other operand is R0. GCC doesn't handle this very well, so we forgo
2410 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2411 DI can be any number 0..60. */
2413 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2415 if (GET_CODE (OP) == CONST_INT) \
2417 if (TARGET_SHMEDIA) \
2419 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2420 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2421 && INTVAL (OP) >= -512 * MODE_SIZE \
2422 && INTVAL (OP) < 512 * MODE_SIZE) \
2427 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2428 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2432 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2434 if (BASE_REGISTER_RTX_P (X)) \
2436 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2437 && ! TARGET_SHMEDIA \
2438 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2440 else if (GET_CODE (X) == PLUS \
2441 && ((MODE) != PSImode || reload_completed)) \
2443 rtx xop0 = XEXP ((X), 0); \
2444 rtx xop1 = XEXP ((X), 1); \
2445 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2446 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2447 if (GET_MODE_SIZE (MODE) <= 4 \
2448 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2449 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
2451 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2453 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2459 /* Try machine-dependent ways of modifying an illegitimate address
2460 to be legitimate. If we find one, return the new, valid address.
2461 This macro is used in only one place: `memory_address' in explow.c.
2463 OLDX is the address as it was before break_out_memory_refs was called.
2464 In some cases it is useful to look at this to decide what needs to be done.
2466 MODE and WIN are passed so that this macro can use
2467 GO_IF_LEGITIMATE_ADDRESS.
2469 It is always safe for this macro to do nothing. It exists to recognize
2470 opportunities to optimize the output.
2472 For the SH, if X is almost suitable for indexing, but the offset is
2473 out of range, convert it into a normal form so that cse has a chance
2474 of reducing the number of address registers used. */
2476 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2479 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2480 if (GET_CODE (X) == PLUS \
2481 && (GET_MODE_SIZE (MODE) == 4 \
2482 || GET_MODE_SIZE (MODE) == 8) \
2483 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2484 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2485 && ! TARGET_SHMEDIA \
2486 && ! (TARGET_SH4 && (MODE) == DFmode) \
2487 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2489 rtx index_rtx = XEXP ((X), 1); \
2490 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2493 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2494 /* On rare occasions, we might get an unaligned pointer \
2495 that is indexed in a way to give an aligned address. \
2496 Therefore, keep the lower two bits in offset_base. */ \
2497 /* Instead of offset_base 128..131 use 124..127, so that \
2498 simple add suffices. */ \
2501 offset_base = ((offset + 4) & ~60) - 4; \
2504 offset_base = offset & ~60; \
2505 /* Sometimes the normal form does not suit DImode. We \
2506 could avoid that by using smaller ranges, but that \
2507 would give less optimized code when SImode is \
2509 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2511 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2512 GEN_INT (offset_base), NULL_RTX, 0, \
2515 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2521 /* A C compound statement that attempts to replace X, which is an address
2522 that needs reloading, with a valid memory address for an operand of
2523 mode MODE. WIN is a C statement label elsewhere in the code.
2525 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2526 of the address. That will allow inheritance of the address reloads. */
2528 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2530 if (GET_CODE (X) == PLUS \
2531 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2532 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2533 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2534 && ! TARGET_SHMEDIA \
2535 && ! (TARGET_SH4 && (MODE) == DFmode) \
2536 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2538 rtx index_rtx = XEXP (X, 1); \
2539 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2542 if (TARGET_SH2E && MODE == SFmode) \
2545 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2546 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2550 /* Instead of offset_base 128..131 use 124..127, so that \
2551 simple add suffices. */ \
2554 offset_base = ((offset + 4) & ~60) - 4; \
2557 offset_base = offset & ~60; \
2558 /* Sometimes the normal form does not suit DImode. We \
2559 could avoid that by using smaller ranges, but that \
2560 would give less optimized code when SImode is \
2562 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2564 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2565 GEN_INT (offset_base)); \
2566 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2567 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2568 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2573 /* We must re-recognize what we created before. */ \
2574 else if (GET_CODE (X) == PLUS \
2575 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2576 && GET_CODE (XEXP (X, 0)) == PLUS \
2577 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2578 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2579 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2580 && ! TARGET_SHMEDIA \
2581 && ! (TARGET_SH2E && MODE == SFmode)) \
2583 /* Because this address is so complex, we know it must have \
2584 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2585 it is already unshared, and needs no further unsharing. */ \
2586 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2587 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2592 /* Go to LABEL if ADDR (a legitimate address expression)
2593 has an effect that depends on the machine mode it is used for.
2595 ??? Strictly speaking, we should also include all indexed addressing,
2596 because the index scale factor is the length of the operand.
2597 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2598 high if we did that. So we rely on reload to fix things up. */
2600 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2602 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2606 /* Specify the machine mode that this machine uses
2607 for the index in the tablejump instruction. */
2608 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2610 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2611 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2612 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2613 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2614 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2615 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2618 /* Define as C expression which evaluates to nonzero if the tablejump
2619 instruction expects the table to contain offsets from the address of the
2621 Do not define this if the table should contain absolute addresses. */
2622 #define CASE_VECTOR_PC_RELATIVE 1
2624 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2625 #define FLOAT_TYPE_SIZE 32
2627 /* Since the SH2e has only `float' support, it is desirable to make all
2628 floating point types equivalent to `float'. */
2629 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4) ? 32 : 64)
2631 /* 'char' is signed by default. */
2632 #define DEFAULT_SIGNED_CHAR 1
2634 /* The type of size_t unsigned int. */
2635 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2638 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2640 #define WCHAR_TYPE "short unsigned int"
2641 #define WCHAR_TYPE_SIZE 16
2643 #define SH_ELF_WCHAR_TYPE "long int"
2645 /* Don't cse the address of the function being compiled. */
2646 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
2648 /* Max number of bytes we can move from memory to memory
2649 in one reasonably fast instruction. */
2650 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2652 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2653 MOVE_MAX is not a compile-time constant. */
2654 #define MAX_MOVE_MAX 8
2656 /* Max number of bytes we want move_by_pieces to be able to copy
2658 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2660 /* Define if operations between registers always perform the operation
2661 on the full register even if a narrower mode is specified. */
2662 #define WORD_REGISTER_OPERATIONS
2664 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2665 will either zero-extend or sign-extend. The value of this macro should
2666 be the code that says which one of the two operations is implicitly
2667 done, NIL if none. */
2668 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2669 /* FP registers can load SImode values, but don't implicitly sign-extend
2671 #define LOAD_EXTEND_OP(MODE) \
2672 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2673 : (MODE) != SImode ? SIGN_EXTEND : NIL)
2675 /* Define if loading short immediate values into registers sign extends. */
2676 #define SHORT_IMMEDIATES_SIGN_EXTEND
2678 /* Nonzero if access to memory by bytes is no faster than for words. */
2679 #define SLOW_BYTE_ACCESS 1
2681 /* Immediate shift counts are truncated by the output routines (or was it
2682 the assembler?). Shift counts in a register are truncated by SH. Note
2683 that the native compiler puts too large (> 32) immediate shift counts
2684 into a register and shifts by the register, letting the SH decide what
2685 to do instead of doing that itself. */
2686 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2687 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2688 expects - the sign bit is significant - so it appears that we need to
2689 leave this zero for correct SH3 code. */
2690 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
2692 /* All integers have the same format so truncation is easy. */
2693 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2695 /* Define this if addresses of constant functions
2696 shouldn't be put through pseudo regs where they can be cse'd.
2697 Desirable on machines where ordinary constants are expensive
2698 but a CALL with constant address is cheap. */
2699 /*#define NO_FUNCTION_CSE 1*/
2701 /* The machine modes of pointers and functions. */
2702 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2703 #define FUNCTION_MODE Pmode
2705 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2706 are actually function calls with some special constraints on arguments
2709 These macros tell reorg that the references to arguments and
2710 register clobbers for insns of type sfunc do not appear to happen
2711 until after the millicode call. This allows reorg to put insns
2712 which set the argument registers into the delay slot of the millicode
2713 call -- thus they act more like traditional CALL_INSNs.
2715 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2716 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2719 #define INSN_SETS_ARE_DELAYED(X) \
2720 ((GET_CODE (X) == INSN \
2721 && GET_CODE (PATTERN (X)) != SEQUENCE \
2722 && GET_CODE (PATTERN (X)) != USE \
2723 && GET_CODE (PATTERN (X)) != CLOBBER \
2724 && get_attr_is_sfunc (X)))
2726 #define INSN_REFERENCES_ARE_DELAYED(X) \
2727 ((GET_CODE (X) == INSN \
2728 && GET_CODE (PATTERN (X)) != SEQUENCE \
2729 && GET_CODE (PATTERN (X)) != USE \
2730 && GET_CODE (PATTERN (X)) != CLOBBER \
2731 && get_attr_is_sfunc (X)))
2734 /* Position Independent Code. */
2736 /* We can't directly access anything that contains a symbol,
2737 nor can we indirect via the constant pool. */
2738 #define LEGITIMATE_PIC_OPERAND_P(X) \
2739 ((! nonpic_symbol_mentioned_p (X) \
2740 && (GET_CODE (X) != SYMBOL_REF \
2741 || ! CONSTANT_POOL_ADDRESS_P (X) \
2742 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2743 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2745 #define SYMBOLIC_CONST_P(X) \
2746 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2747 && nonpic_symbol_mentioned_p (X))
2749 /* Compute extra cost of moving data between one register class
2752 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2753 uses this information. Hence, the general register <-> floating point
2754 register information here is not used for SFmode. */
2756 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2757 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2758 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2760 #define REGCLASS_HAS_FP_REG(CLASS) \
2761 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2762 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2764 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2765 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2767 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2768 would be so that people with slow memory systems could generate
2769 different code that does fewer memory accesses. */
2771 /* A C expression for the cost of a branch instruction. A value of 1
2772 is the default; other values are interpreted relative to that.
2773 The SH1 does not have delay slots, hence we get a pipeline stall
2774 at every branch. The SH4 is superscalar, so the single delay slot
2775 is not sufficient to keep both pipelines filled. */
2776 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2778 /* Assembler output control. */
2780 /* A C string constant describing how to begin a comment in the target
2781 assembler language. The compiler assumes that the comment will end at
2782 the end of the line. */
2783 #define ASM_COMMENT_START "!"
2785 #define ASM_APP_ON ""
2786 #define ASM_APP_OFF ""
2787 #define FILE_ASM_OP "\t.file\n"
2788 #define SET_ASM_OP "\t.set\t"
2790 /* How to change between sections. */
2792 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2793 #define DATA_SECTION_ASM_OP "\t.data"
2795 #if defined CRT_BEGIN || defined CRT_END
2796 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2797 # undef TEXT_SECTION_ASM_OP
2798 # if __SHMEDIA__ == 1 && __SH5__ == 32
2799 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2801 # define TEXT_SECTION_ASM_OP "\t.text"
2806 /* If defined, a C expression whose value is a string containing the
2807 assembler operation to identify the following data as
2808 uninitialized global data. If not defined, and neither
2809 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2810 uninitialized global data will be output in the data section if
2811 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2813 #ifndef BSS_SECTION_ASM_OP
2814 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2817 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2818 separate, explicit argument. If you define this macro, it is used
2819 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2820 handling the required alignment of the variable. The alignment is
2821 specified as the number of bits.
2823 Try to use function `asm_output_aligned_bss' defined in file
2824 `varasm.c' when defining this macro. */
2825 #ifndef ASM_OUTPUT_ALIGNED_BSS
2826 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2827 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2830 /* Define this so that jump tables go in same section as the current function,
2831 which could be text or it could be a user defined section. */
2832 #define JUMP_TABLES_IN_TEXT_SECTION 1
2834 #undef DO_GLOBAL_CTORS_BODY
2835 #define DO_GLOBAL_CTORS_BODY \
2837 typedef (*pfunc)(); \
2838 extern pfunc __ctors[]; \
2839 extern pfunc __ctors_end[]; \
2841 for (p = __ctors_end; p > __ctors; ) \
2847 #undef DO_GLOBAL_DTORS_BODY
2848 #define DO_GLOBAL_DTORS_BODY \
2850 typedef (*pfunc)(); \
2851 extern pfunc __dtors[]; \
2852 extern pfunc __dtors_end[]; \
2854 for (p = __dtors; p < __dtors_end; p++) \
2860 #define ASM_OUTPUT_REG_PUSH(file, v) \
2861 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
2863 #define ASM_OUTPUT_REG_POP(file, v) \
2864 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
2866 /* DBX register number for a given compiler register number. */
2867 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2869 /* svr4.h undefines this macro, yet we really want to use the same numbers
2870 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2871 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2872 register exists, so we should return -1 for invalid register numbers. */
2873 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2875 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2876 used to use the encodings 245..260, but that doesn't make sense:
2877 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2878 the FP registers stay the same when switching between compact and media
2879 mode. Hence, we also need to use the same dwarf frame columns.
2880 Likewise, we need to support unwind information for SHmedia registers
2881 even in compact code. */
2882 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2883 (IN_RANGE ((REGNO), \
2884 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2885 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2886 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2887 : ((int) (REGNO) >= FIRST_FP_REG \
2889 <= (FIRST_FP_REG + \
2890 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2891 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2892 + (TARGET_SH5 ? 77 : 25)) \
2893 : XD_REGISTER_P (REGNO) \
2894 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2895 : TARGET_REGISTER_P (REGNO) \
2896 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2897 : (REGNO) == PR_REG \
2898 ? (TARGET_SH5 ? 18 : 17) \
2899 : (REGNO) == PR_MEDIA_REG \
2900 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2901 : (REGNO) == T_REG \
2902 ? (TARGET_SH5 ? 242 : 18) \
2903 : (REGNO) == GBR_REG \
2904 ? (TARGET_SH5 ? 238 : 19) \
2905 : (REGNO) == MACH_REG \
2906 ? (TARGET_SH5 ? 239 : 20) \
2907 : (REGNO) == MACL_REG \
2908 ? (TARGET_SH5 ? 240 : 21) \
2909 : (REGNO) == FPUL_REG \
2910 ? (TARGET_SH5 ? 244 : 23) \
2913 /* This is how to output a reference to a symbol_ref. On SH5,
2914 references to non-code symbols must be preceded by `datalabel'. */
2915 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2918 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2919 fputs ("datalabel ", (FILE)); \
2920 assemble_name ((FILE), XSTR ((SYM), 0)); \
2924 /* This is how to output an assembler line
2925 that says to advance the location counter
2926 to a multiple of 2**LOG bytes. */
2928 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2930 fprintf ((FILE), "\t.align %d\n", (LOG))
2932 /* Globalizing directive for a label. */
2933 #define GLOBAL_ASM_OP "\t.global\t"
2935 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2937 /* Output a relative address table. */
2939 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2940 switch (GET_MODE (BODY)) \
2945 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2949 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2954 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2958 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2963 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2967 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2973 /* Output an absolute table element. */
2975 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2976 if (! optimize || TARGET_BIGTABLE) \
2977 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2979 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2982 /* A C statement to be executed just prior to the output of
2983 assembler code for INSN, to modify the extracted operands so
2984 they will be output differently.
2986 Here the argument OPVEC is the vector containing the operands
2987 extracted from INSN, and NOPERANDS is the number of elements of
2988 the vector which contain meaningful data for this insn.
2989 The contents of this vector are what will be used to convert the insn
2990 template into assembler code, so you can change the assembler output
2991 by changing the contents of the vector. */
2993 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2994 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2996 /* Print operand X (an rtx) in assembler syntax to file FILE.
2997 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2998 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3000 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3002 /* Print a memory address as an operand to reference that memory location. */
3004 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3006 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3007 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3008 || (CHAR) == '$'|| (CHAR) == '\'')
3010 /* Recognize machine-specific patterns that may appear within
3011 constants. Used for PIC-specific UNSPECs. */
3012 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3014 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3016 switch (XINT ((X), 1)) \
3018 case UNSPEC_DATALABEL: \
3019 fputs ("datalabel ", (STREAM)); \
3020 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3023 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3024 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3027 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3028 fputs ("@GOT", (STREAM)); \
3030 case UNSPEC_GOTOFF: \
3031 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3032 fputs ("@GOTOFF", (STREAM)); \
3035 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3036 fputs ("@PLT", (STREAM)); \
3038 case UNSPEC_GOTPLT: \
3039 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3040 fputs ("@GOTPLT", (STREAM)); \
3042 case UNSPEC_DTPOFF: \
3043 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3044 fputs ("@DTPOFF", (STREAM)); \
3046 case UNSPEC_GOTTPOFF: \
3047 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3048 fputs ("@GOTTPOFF", (STREAM)); \
3050 case UNSPEC_TPOFF: \
3051 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3052 fputs ("@TPOFF", (STREAM)); \
3054 case UNSPEC_CALLER: \
3057 /* LPCS stands for Label for PIC Call Site. */ \
3058 ASM_GENERATE_INTERNAL_LABEL \
3059 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3060 assemble_name ((STREAM), name); \
3073 extern struct rtx_def *sh_compare_op0;
3074 extern struct rtx_def *sh_compare_op1;
3076 /* Which processor to schedule for. The elements of the enumeration must
3077 match exactly the cpu attribute in the sh.md file. */
3079 enum processor_type {
3089 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3090 extern enum processor_type sh_cpu;
3092 extern int optimize; /* needed for gen_casesi. */
3094 enum mdep_reorg_phase_e
3096 SH_BEFORE_MDEP_REORG,
3097 SH_INSERT_USES_LABELS,
3098 SH_SHORTEN_BRANCHES0,
3100 SH_SHORTEN_BRANCHES1,
3104 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3106 /* Generate calls to memcpy, memcmp and memset. */
3108 #define TARGET_MEM_FUNCTIONS
3110 /* Handle Renesas compiler's pragmas. */
3111 #define REGISTER_TARGET_PRAGMAS() do { \
3112 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3113 c_register_pragma (0, "trapa", sh_pr_trapa); \
3114 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3117 /* Set when processing a function with pragma interrupt turned on. */
3119 extern int pragma_interrupt;
3121 /* Set when processing a function with interrupt attribute. */
3123 extern int current_function_interrupt;
3125 /* Set to an RTX containing the address of the stack to switch to
3126 for interrupt functions. */
3127 extern struct rtx_def *sp_switch;
3129 extern int rtx_equal_function_value_matters;
3132 /* Instructions with unfilled delay slots take up an
3133 extra two bytes for the nop in the delay slot.
3134 sh-dsp parallel processing insns are four bytes long. */
3136 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3137 (LENGTH) += sh_insn_length_adjustment (X);
3139 /* Define the codes that are matched by predicates in sh.c. */
3140 #define PREDICATE_CODES \
3141 {"and_operand", {SUBREG, REG, CONST_INT}}, \
3142 {"any_register_operand", {SUBREG, REG}}, \
3143 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3144 {"arith_reg_dest", {SUBREG, REG}}, \
3145 {"arith_reg_operand", {SUBREG, REG}}, \
3146 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
3147 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
3148 {"binary_logical_operator", {AND, IOR, XOR}}, \
3149 {"cmpsi_operand", {SUBREG, REG, CONST_INT}}, \
3150 {"commutative_float_operator", {PLUS, MULT}}, \
3151 {"equality_comparison_operator", {EQ,NE}}, \
3152 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
3153 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
3154 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3155 {"fpscr_operand", {REG}}, \
3156 {"fpul_operand", {REG}}, \
3157 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
3158 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3159 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3160 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
3161 {"int_gpr_dest", {SUBREG, REG}}, \
3162 {"inqhi_operand", {TRUNCATE}}, \
3163 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
3164 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3165 {"mextr_bit_offset", {CONST_INT}}, \
3166 {"noncommutative_float_operator", {MINUS, DIV}}, \
3167 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3168 {"sh_register_operand", {REG, SUBREG, CONST_INT}}, \
3169 {"target_reg_operand", {SUBREG, REG}}, \
3170 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
3171 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
3172 {"register_operand", {SUBREG, REG}}, \
3173 {"sh_const_vec", {CONST_VECTOR}}, \
3174 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
3175 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
3176 {"symbol_ref_operand", {SYMBOL_REF}}, \
3177 {"unary_float_operator", {ABS, NEG, SQRT}}, \
3179 #define SPECIAL_MODE_PREDICATES \
3180 "any_register_operand", \
3182 "trunc_hi_operand", \
3183 /* This line intentionally left blank. */
3185 #define any_register_operand register_operand
3187 /* Define this macro if it is advisable to hold scalars in registers
3188 in a wider mode than that declared by the program. In such cases,
3189 the value is constrained to be within the bounds of the declared
3190 type, but kept valid in the wider mode. The signedness of the
3191 extension may differ from that of the type.
3193 Leaving the unsignedp unchanged gives better code than always setting it
3194 to 0. This is despite the fact that we have only signed char and short
3195 load instructions. */
3196 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3197 if (GET_MODE_CLASS (MODE) == MODE_INT \
3198 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3199 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3200 (MODE) = (TARGET_SH1 ? SImode : DImode);
3202 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3204 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3205 and popping arguments. However, we do have push/pop instructions, and
3206 rather limited offsets (4 bits) in load/store instructions, so it isn't
3207 clear if this would give better code. If implemented, should check for
3208 compatibility problems. */
3210 #define SH_DYNAMIC_SHIFT_COST \
3211 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3214 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3216 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3218 #define ACTUAL_NORMAL_MODE(ENTITY) \
3219 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3221 #define NORMAL_MODE(ENTITY) \
3222 (sh_cfun_interrupt_handler_p () \
3223 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3224 : ACTUAL_NORMAL_MODE (ENTITY))
3226 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3228 #define MODE_EXIT(ENTITY) \
3229 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3231 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3232 && (REGNO) == FPSCR_REG)
3234 #define MODE_NEEDED(ENTITY, INSN) \
3235 (recog_memoized (INSN) >= 0 \
3236 ? get_attr_fp_mode (INSN) \
3239 #define MODE_AFTER(MODE, INSN) \
3241 && recog_memoized (INSN) >= 0 \
3242 && get_attr_fp_set (INSN) != FP_SET_NONE \
3243 ? get_attr_fp_set (INSN) \
3246 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3247 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3249 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3250 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3252 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3253 sh_can_redirect_branch ((INSN), (SEQ))
3255 #define DWARF_FRAME_RETURN_COLUMN \
3256 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3258 #define EH_RETURN_DATA_REGNO(N) \
3259 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3261 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3262 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3264 /* We have to distinguish between code and data, so that we apply
3265 datalabel where and only where appropriate. Use textrel for code. */
3266 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3267 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3268 | ((CODE) ? DW_EH_PE_textrel : flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))
3270 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3271 indirect are handled automatically. */
3272 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3274 if (((ENCODING) & 0x70) == DW_EH_PE_textrel) \
3276 encoding &= ~DW_EH_PE_textrel; \
3277 encoding |= flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr; \
3278 if (GET_CODE (ADDR) != SYMBOL_REF) \
3280 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3285 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3286 /* SH constant pool breaks the devices in crtstuff.c to control section
3287 in where code resides. We have to write it as asm code. */
3288 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3289 asm (SECTION_OP "\n\
3295 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3296 2:\n" TEXT_SECTION_ASM_OP);
3297 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3299 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3300 (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
3301 ? (current_function_is_leaf \
3302 && ! sh_pr_n_sets () \
3303 && ! (TARGET_SHCOMPACT \
3304 && ((current_function_args_info.call_cookie \
3305 & ~ CALL_COOKIE_RET_TRAMP (1)) \
3306 || current_function_has_nonlocal_label)) \
3308 : gen_rtx_MEM (Pmode, TARGET_SH5 \
3309 ? (plus_constant (arg_pointer_rtx, \
3310 TARGET_SHMEDIA64 ? -8 : -4)) \
3311 : frame_pointer_rtx)) \
3314 #endif /* ! GCC_SH_H */
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