1 /* Definitions of target machine for GNU compiler for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because hconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
35 #define TARGET_CPU_CPP_BUILTINS() \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
43 builtin_define ("__sh1__"); \
46 builtin_define ("__sh2__"); \
49 builtin_define ("__sh3__"); \
50 builtin_define ("__SH3__"); \
51 if (TARGET_HARD_SH4) \
52 builtin_define ("__SH4_NOFPU__"); \
54 case PROCESSOR_SH3E: \
55 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
58 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
62 builtin_define_with_value ("__SH5__", \
63 TARGET_SHMEDIA64 ? "64" : "32", 0); \
64 builtin_define_with_value ("__SHMEDIA__", \
65 TARGET_SHMEDIA ? "1" : "0", 0); \
66 if (! TARGET_FPU_DOUBLE) \
67 builtin_define ("__SH4_NOFPU__"); \
71 builtin_define ("__HITACHI__"); \
72 builtin_define (TARGET_LITTLE_ENDIAN \
73 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
76 builtin_define ("__pic__"); \
77 builtin_define ("__PIC__"); \
79 TARGET_OBJFMT_CPP_BUILTINS (); \
82 /* We can not debug without a frame pointer. */
83 /* #define CAN_DEBUG_WITHOUT_FP */
85 #define CONDITIONAL_REGISTER_USAGE do \
88 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
89 if (! VALID_REGISTER_P (regno)) \
90 fixed_regs[regno] = call_used_regs[regno] = 1; \
91 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
93 call_used_regs[FIRST_GENERAL_REG + 8] \
94 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
97 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
98 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
99 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
102 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
103 /* Hitachi saves and restores mac registers on call. */ \
104 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
106 call_used_regs[MACH_REG] = 0; \
107 call_used_regs[MACL_REG] = 0; \
109 if (TARGET_SHMEDIA) \
111 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
112 if (! fixed_regs[regno] && call_used_regs[regno]) \
113 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
116 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
117 if (! fixed_regs[regno] && call_used_regs[regno]) \
118 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
121 /* ??? Need to write documentation for all SH options and add it to the
124 /* Run-time compilation parameters selecting different hardware subsets. */
126 extern int target_flags;
127 #define ISIZE_BIT (1<<1)
128 #define DALIGN_BIT (1<<6)
129 #define SH1_BIT (1<<8)
130 #define SH2_BIT (1<<9)
131 #define SH3_BIT (1<<10)
132 #define SH3E_BIT (1<<11)
133 #define HARD_SH4_BIT (1<<5)
134 #define FPU_SINGLE_BIT (1<<7)
135 #define SH4_BIT (1<<12)
136 #define FMOVD_BIT (1<<4)
137 #define SH5_BIT (1<<0)
138 #define SPACE_BIT (1<<13)
139 #define BIGTABLE_BIT (1<<14)
140 #define RELAX_BIT (1<<15)
141 #define USERMODE_BIT (1<<16)
142 #define HITACHI_BIT (1<<22)
143 #define NOMACSAVE_BIT (1<<23)
144 #define PREFERGOT_BIT (1<<24)
145 #define PADSTRUCT_BIT (1<<28)
146 #define LITTLE_ENDIAN_BIT (1<<29)
147 #define IEEE_BIT (1<<30)
149 /* Nonzero if we should dump out instruction size info. */
150 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
152 /* Nonzero to align doubles on 64 bit boundaries. */
153 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
155 /* Nonzero if we should generate code using type 1 insns. */
156 #define TARGET_SH1 (target_flags & SH1_BIT)
158 /* Nonzero if we should generate code using type 2 insns. */
159 #define TARGET_SH2 (target_flags & SH2_BIT)
161 /* Nonzero if we should generate code using type 3 insns. */
162 #define TARGET_SH3 (target_flags & SH3_BIT)
164 /* Nonzero if we should generate code using type 3E insns. */
165 #define TARGET_SH3E ((target_flags & SH3E_BIT) && (target_flags & SH1_BIT))
167 /* Nonzero if the cache line size is 32. */
168 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
170 /* Nonzero if we schedule for a superscalar implementation. */
171 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
173 /* Nonzero if the target has separate instruction and data caches. */
174 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
176 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
177 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
179 /* Nonzero if the default precision of th FPU is single */
180 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
182 /* Nonzero if a double-precision FPU is available. */
183 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
185 /* Nonzero if an FPU is available. */
186 #define TARGET_FPU_ANY (TARGET_SH3E || TARGET_FPU_DOUBLE)
188 /* Nonzero if we should generate code using type 4 insns. */
189 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
191 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
192 #define TARGET_SH5 (target_flags & SH5_BIT)
194 /* Nonzero if we should generate code using the SHcompact instruction
195 set and 32-bit ABI. */
196 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
198 /* Nonzero if we should generate code using the SHmedia instruction
200 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
202 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
204 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
205 && (target_flags & SH3E_BIT))
207 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
209 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
210 && ! (target_flags & SH3E_BIT))
212 /* Nonzero if we should generate code using SHmedia FPU instructions. */
213 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
214 /* Nonzero if we should generate fmovd. */
215 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
217 /* Nonzero if we respect NANs. */
218 #define TARGET_IEEE (target_flags & IEEE_BIT)
220 /* Nonzero if we should generate smaller code rather than faster code. */
221 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
223 /* Nonzero to use long jump tables. */
224 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
226 /* Nonzero to generate pseudo-ops needed by the assembler and linker
227 to do function call relaxing. */
228 #define TARGET_RELAX (target_flags & RELAX_BIT)
230 /* Nonzero if using Hitachi's calling convention. */
231 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
233 /* Nonzero if not saving macl/mach when using -mhitachi */
234 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
236 /* Nonzero if padding structures to a multiple of 4 bytes. This is
237 incompatible with Hitachi's compiler, and gives unusual structure layouts
238 which confuse programmers.
239 ??? This option is not useful, but is retained in case there are people
240 who are still relying on it. It may be deleted in the future. */
241 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
243 /* Nonzero if generating code for a little endian SH. */
244 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
246 /* Nonzero if we should do everything in userland. */
247 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
249 /* Nonzero if we should prefer @GOT calls when generating PIC. */
250 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
252 #define SELECT_SH1 (SH1_BIT)
253 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
254 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
255 #define SELECT_SH3E (SH3E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
256 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
257 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
258 #define SELECT_SH4 (SH4_BIT|SH3E_BIT|HARD_SH4_BIT | SELECT_SH3)
259 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
260 #define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
261 #define SELECT_SH5_64_NOFPU (SH5_BIT)
262 #define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH3E_BIT)
263 #define SELECT_SH5_32_NOFPU (SH5_BIT | SH3E_BIT)
264 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
265 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
267 /* Reset all target-selection flags. */
268 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \
269 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
271 #define TARGET_SWITCHES \
272 { {"1", TARGET_NONE, "" }, \
273 {"1", SELECT_SH1, "" }, \
274 {"2", TARGET_NONE, "" }, \
275 {"2", SELECT_SH2, "" }, \
276 {"3", TARGET_NONE, "" }, \
277 {"3", SELECT_SH3, "" }, \
278 {"3e", TARGET_NONE, "" }, \
279 {"3e", SELECT_SH3E, "" }, \
280 {"4-single-only", TARGET_NONE, "" }, \
281 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "" }, \
282 {"4-single", TARGET_NONE, "" }, \
283 {"4-single", SELECT_SH4_SINGLE, "" },\
284 {"4-nofpu", TARGET_NONE, "" }, \
285 {"4-nofpu", SELECT_SH4_NOFPU, "" },\
286 {"4", TARGET_NONE, "" }, \
287 {"4", SELECT_SH4, "" }, \
288 {"5-64media", TARGET_NONE, "" }, \
289 {"5-64media", SELECT_SH5_64, "Generate 64-bit SHmedia code" }, \
290 {"5-64media-nofpu", TARGET_NONE, "" }, \
291 {"5-64media-nofpu", SELECT_SH5_64_NOFPU, "Generate 64-bit FPU-less SHmedia code" }, \
292 {"5-32media", TARGET_NONE, "" }, \
293 {"5-32media", SELECT_SH5_32, "Generate 32-bit SHmedia code" }, \
294 {"5-32media-nofpu", TARGET_NONE, "" }, \
295 {"5-32media-nofpu", SELECT_SH5_32_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
296 {"5-compact", TARGET_NONE, "" }, \
297 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" }, \
298 {"5-compact-nofpu", TARGET_NONE, "" }, \
299 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" }, \
300 {"b", -LITTLE_ENDIAN_BIT, "" }, \
301 {"bigtable", BIGTABLE_BIT, "" }, \
302 {"dalign", DALIGN_BIT, "" }, \
303 {"fmovd", FMOVD_BIT, "" }, \
304 {"hitachi", HITACHI_BIT, "" }, \
305 {"nomacsave", NOMACSAVE_BIT, "" }, \
306 {"ieee", IEEE_BIT, "" }, \
307 {"isize", ISIZE_BIT, "" }, \
308 {"l", LITTLE_ENDIAN_BIT, "" }, \
309 {"no-ieee", -IEEE_BIT, "" }, \
310 {"padstruct", PADSTRUCT_BIT, "" }, \
311 {"prefergot", PREFERGOT_BIT, "" }, \
312 {"relax", RELAX_BIT, "" }, \
313 {"space", SPACE_BIT, "" }, \
314 {"usermode", USERMODE_BIT, "" }, \
316 {"", TARGET_DEFAULT, "" } \
319 /* This are meant to be redefined in the host dependent files */
320 #define SUBTARGET_SWITCHES
322 /* This defaults us to big-endian. */
323 #ifndef TARGET_ENDIAN_DEFAULT
324 #define TARGET_ENDIAN_DEFAULT 0
327 #ifndef TARGET_CPU_DEFAULT
328 #define TARGET_CPU_DEFAULT SELECT_SH1
331 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
333 #define CPP_SPEC " %(subtarget_cpp_spec) "
335 #ifndef SUBTARGET_CPP_SPEC
336 #define SUBTARGET_CPP_SPEC ""
339 #ifndef SUBTARGET_EXTRA_SPECS
340 #define SUBTARGET_EXTRA_SPECS
343 #define EXTRA_SPECS \
344 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
345 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
346 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
347 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
348 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
349 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
350 SUBTARGET_EXTRA_SPECS
352 #define ASM_SPEC "%(subtarget_asm_endian_spec) %{mrelax:-relax}"
354 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
355 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
356 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
358 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
362 #define LINK_EMUL_PREFIX "sh%{ml:l}"
364 #if TARGET_CPU_DEFAULT & SH5_BIT
365 #if TARGET_CPU_DEFAULT & SH3E_BIT
366 #define LINK_DEFAULT_CPU_EMUL "32"
368 #define LINK_DEFAULT_CPU_EMUL "64"
369 #endif /* SH3E_BIT */
371 #define LINK_DEFAULT_CPU_EMUL ""
374 #define SUBTARGET_LINK_EMUL_SUFFIX ""
375 #define SUBTARGET_LINK_SPEC ""
377 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
378 so that we can undo the damage without code replication. */
379 #define LINK_SPEC SH_LINK_SPEC
381 #define SH_LINK_SPEC "\
382 -m %(link_emul_prefix)\
383 %{m5-compact*|m5-32media*:32}\
385 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
386 %(subtarget_link_emul_suffix) \
387 %{mrelax:-relax} %(subtarget_link_spec)"
389 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
392 flag_omit_frame_pointer = -1; \
394 target_flags |= SPACE_BIT; \
397 #define ASSEMBLER_DIALECT assembler_dialect
399 extern int assembler_dialect;
401 #define OVERRIDE_OPTIONS \
406 assembler_dialect = 0; \
415 assembler_dialect = 1; \
421 target_flags |= DALIGN_BIT; \
422 if (TARGET_FPU_ANY) \
423 target_flags |= FMOVD_BIT; \
424 if (TARGET_SHMEDIA) \
426 /* There are no delay slots on SHmedia. */ \
427 flag_delayed_branch = 0; \
428 /* Relaxation isn't yet supported for SHmedia */ \
429 target_flags &= ~RELAX_BIT; \
431 if (profile_flag || profile_arc_flag) \
433 warning ("Profiling is not supported on this target."); \
434 profile_flag = profile_arc_flag = 0; \
439 /* Only the sh64-elf assembler fully supports .quad properly. */\
440 targetm.asm_out.aligned_op.di = NULL; \
441 targetm.asm_out.unaligned_op.di = NULL; \
444 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
445 if (! VALID_REGISTER_P (regno)) \
446 sh_register_names[regno][0] = '\0'; \
448 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
449 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
450 sh_additional_register_names[regno][0] = '\0'; \
452 if (flag_omit_frame_pointer < 0) \
454 /* The debugging information is sufficient, \
455 but gdb doesn't implement this yet */ \
457 flag_omit_frame_pointer \
458 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
459 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
461 flag_omit_frame_pointer = 0; \
464 if (flag_pic && ! TARGET_PREFERGOT) \
465 flag_no_function_cse = 1; \
467 /* Never run scheduling before reload, since that can \
468 break global alloc, and generates slower code anyway due \
469 to the pressure on R0. */ \
470 flag_schedule_insns = 0; \
473 /* Target machine storage layout. */
475 /* Define this if most significant bit is lowest numbered
476 in instructions that operate on numbered bit-fields. */
478 #define BITS_BIG_ENDIAN 0
480 /* Define this if most significant byte of a word is the lowest numbered. */
481 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
483 /* Define this if most significant word of a multiword number is the lowest
485 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
487 /* Define this to set the endianness to use in libgcc2.c, which can
488 not depend on target_flags. */
489 #if defined(__LITTLE_ENDIAN__)
490 #define LIBGCC2_WORDS_BIG_ENDIAN 0
492 #define LIBGCC2_WORDS_BIG_ENDIAN 1
495 #define MAX_BITS_PER_WORD 64
497 #define MAX_LONG_TYPE_SIZE MAX_BITS_PER_WORD
499 /* Width in bits of an `int'. We want just 32-bits, even if words are
501 #define INT_TYPE_SIZE 32
503 /* Width in bits of a `long'. */
504 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
506 /* Width in bits of a `long long'. */
507 #define LONG_LONG_TYPE_SIZE 64
509 /* Width in bits of a `long double'. */
510 #define LONG_DOUBLE_TYPE_SIZE 64
512 /* Width of a word, in units (bytes). */
513 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
514 #define MIN_UNITS_PER_WORD 4
516 /* Width in bits of a pointer.
517 See also the macro `Pmode' defined below. */
518 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
520 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
521 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
523 /* Boundary (in *bits*) on which stack pointer should be aligned. */
524 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
526 /* The log (base 2) of the cache line size, in bytes. Processors prior to
527 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
528 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
529 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
531 /* Allocation boundary (in *bits*) for the code of a function.
532 32 bit alignment is faster, because instructions are always fetched as a
533 pair from a longword boundary. */
534 #define FUNCTION_BOUNDARY \
535 (TARGET_SMALLCODE ? 16 << TARGET_SHMEDIA : (1 << CACHE_LOG) * 8)
537 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
538 the vbit must go into the delta field of
539 pointers-to-member-functions. */
540 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
541 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
543 /* Alignment of field after `int : 0' in a structure. */
544 #define EMPTY_FIELD_BOUNDARY 32
546 /* No data type wants to be aligned rounder than this. */
547 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
549 /* The best alignment to use in cases where we have a choice. */
550 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
552 /* Make strings word-aligned so strcpy from constants will be faster. */
553 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
554 ((TREE_CODE (EXP) == STRING_CST \
555 && (ALIGN) < FASTEST_ALIGNMENT) \
556 ? FASTEST_ALIGNMENT : (ALIGN))
558 /* Make arrays of chars word-aligned for the same reasons. */
559 #define DATA_ALIGNMENT(TYPE, ALIGN) \
560 (TREE_CODE (TYPE) == ARRAY_TYPE \
561 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
562 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
564 /* Number of bits which any structure or union's size must be a
565 multiple of. Each structure or union's size is rounded up to a
567 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
569 /* Set this nonzero if move instructions will actually fail to work
570 when given unaligned data. */
571 #define STRICT_ALIGNMENT 1
573 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
574 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
575 barrier_align (LABEL_AFTER_BARRIER)
577 #define LOOP_ALIGN(A_LABEL) \
578 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
579 ? 0 : sh_loop_align (A_LABEL))
581 #define LABEL_ALIGN(A_LABEL) \
583 (PREV_INSN (A_LABEL) \
584 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
585 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
586 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
587 /* explicit alignment insn in constant tables. */ \
588 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
591 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
592 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
594 /* The base two logarithm of the known minimum alignment of an insn length. */
595 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
596 (GET_CODE (A_INSN) == INSN \
597 ? 1 << TARGET_SHMEDIA \
598 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
599 ? 1 << TARGET_SHMEDIA \
602 /* Standard register usage. */
604 /* Register allocation for the Hitachi calling convention:
610 r14 frame pointer/call saved
612 ap arg pointer (doesn't really exist, always eliminated)
613 pr subroutine return address
615 mach multiply/accumulate result, high part
616 macl multiply/accumulate result, low part.
617 fpul fp/int communication register
618 rap return address pointer register
620 fr1..fr3 scratch floating point registers
622 fr12..fr15 call saved floating point registers */
624 #define MAX_REGISTER_NAME_LENGTH 5
625 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
627 #define SH_REGISTER_NAMES_INITIALIZER \
629 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
630 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
631 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
632 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
633 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
634 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
635 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
636 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
637 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
638 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
639 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
640 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
641 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
642 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
643 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
644 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
645 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
646 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
647 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
651 #define DEBUG_REGISTER_NAMES SH_REGISTER_NAMES_INITIALIZER
653 #define REGNAMES_ARR_INDEX_1(index) \
654 (sh_register_names[index])
655 #define REGNAMES_ARR_INDEX_2(index) \
656 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
657 #define REGNAMES_ARR_INDEX_4(index) \
658 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
659 #define REGNAMES_ARR_INDEX_8(index) \
660 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
661 #define REGNAMES_ARR_INDEX_16(index) \
662 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
663 #define REGNAMES_ARR_INDEX_32(index) \
664 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
665 #define REGNAMES_ARR_INDEX_64(index) \
666 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
668 #define REGISTER_NAMES \
670 REGNAMES_ARR_INDEX_64 (0), \
671 REGNAMES_ARR_INDEX_64 (64), \
672 REGNAMES_ARR_INDEX_8 (128), \
673 REGNAMES_ARR_INDEX_8 (136), \
674 REGNAMES_ARR_INDEX_8 (144), \
675 REGNAMES_ARR_INDEX_1 (152) \
678 #define ADDREGNAMES_SIZE 32
679 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
680 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
681 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
683 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
685 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
686 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
687 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
688 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
691 #define ADDREGNAMES_REGNO(index) \
692 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
695 #define ADDREGNAMES_ARR_INDEX_1(index) \
696 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
697 #define ADDREGNAMES_ARR_INDEX_2(index) \
698 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
699 #define ADDREGNAMES_ARR_INDEX_4(index) \
700 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
701 #define ADDREGNAMES_ARR_INDEX_8(index) \
702 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
703 #define ADDREGNAMES_ARR_INDEX_16(index) \
704 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
705 #define ADDREGNAMES_ARR_INDEX_32(index) \
706 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
708 #define ADDITIONAL_REGISTER_NAMES \
710 ADDREGNAMES_ARR_INDEX_32 (0) \
713 /* Number of actual hardware registers.
714 The hardware registers are assigned numbers for the compiler
715 from 0 to just below FIRST_PSEUDO_REGISTER.
716 All registers that the compiler knows about must be given numbers,
717 even those that are not normally considered general registers. */
719 /* There are many other relevant definitions in sh.md's md_constants. */
721 #define FIRST_GENERAL_REG R0_REG
722 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
723 #define FIRST_FP_REG DR0_REG
724 #define LAST_FP_REG (FIRST_FP_REG + \
725 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH3E ? 15 : -1))
726 #define FIRST_XD_REG XD0_REG
727 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
728 #define FIRST_TARGET_REG TR0_REG
729 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
731 #define GENERAL_REGISTER_P(REGNO) \
732 IN_RANGE ((REGNO), FIRST_GENERAL_REG, LAST_GENERAL_REG)
734 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
735 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
737 #define FP_REGISTER_P(REGNO) \
738 ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
740 #define XD_REGISTER_P(REGNO) \
741 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
743 #define FP_OR_XD_REGISTER_P(REGNO) \
744 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
746 #define FP_ANY_REGISTER_P(REGNO) \
747 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
749 #define SPECIAL_REGISTER_P(REGNO) \
750 ((REGNO) == GBR_REG || (REGNO) == T_REG \
751 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
753 #define TARGET_REGISTER_P(REGNO) \
754 ((REGNO) >= FIRST_TARGET_REG && (REGNO) <= LAST_TARGET_REG)
756 #define SHMEDIA_REGISTER_P(REGNO) \
757 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
758 || TARGET_REGISTER_P (REGNO))
760 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
761 that should be fixed. */
762 #define VALID_REGISTER_P(REGNO) \
763 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
764 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
765 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
766 || (TARGET_SH3E && (REGNO) == FPUL_REG))
768 /* The mode that should be generally used to store a register by
769 itself in the stack, or to load it back. */
770 #define REGISTER_NATURAL_MODE(REGNO) \
771 (FP_REGISTER_P (REGNO) ? SFmode \
772 : XD_REGISTER_P (REGNO) ? DFmode \
773 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
777 #define FIRST_PSEUDO_REGISTER 153
779 /* 1 for registers that have pervasive standard uses
780 and are not available for the register allocator.
782 Mach register is fixed 'cause it's only 10 bits wide for SH1.
783 It is 32 bits wide for SH2. */
785 #define FIXED_REGISTERS \
787 /* Regular registers. */ \
788 0, 0, 0, 0, 0, 0, 0, 0, \
789 0, 0, 0, 0, 0, 0, 0, 1, \
790 /* r16 is reserved, r18 is the former pr. */ \
791 1, 0, 0, 0, 0, 0, 0, 0, \
792 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
793 /* r26 is a global variable data pointer; r27 is for constants. */ \
794 1, 1, 1, 1, 0, 0, 0, 0, \
795 0, 0, 0, 0, 0, 0, 0, 0, \
796 0, 0, 0, 0, 0, 0, 0, 0, \
797 0, 0, 0, 0, 0, 0, 0, 0, \
798 0, 0, 0, 0, 0, 0, 0, 1, \
799 /* FP registers. */ \
800 0, 0, 0, 0, 0, 0, 0, 0, \
801 0, 0, 0, 0, 0, 0, 0, 0, \
802 0, 0, 0, 0, 0, 0, 0, 0, \
803 0, 0, 0, 0, 0, 0, 0, 0, \
804 0, 0, 0, 0, 0, 0, 0, 0, \
805 0, 0, 0, 0, 0, 0, 0, 0, \
806 0, 0, 0, 0, 0, 0, 0, 0, \
807 0, 0, 0, 0, 0, 0, 0, 0, \
808 /* Branch target registers. */ \
809 0, 0, 0, 0, 0, 0, 0, 0, \
810 /* XD registers. */ \
811 0, 0, 0, 0, 0, 0, 0, 0, \
812 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
813 1, 1, 1, 1, 1, 1, 0, 1, \
818 /* 1 for registers not available across function calls.
819 These must include the FIXED_REGISTERS and also any
820 registers that can be used without being saved.
821 The latter must include the registers where values are returned
822 and the register where structure-value addresses are passed.
823 Aside from that, you can include as many other registers as you like. */
825 #define CALL_USED_REGISTERS \
827 /* Regular registers. */ \
828 1, 1, 1, 1, 1, 1, 1, 1, \
829 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
830 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
831 across SH5 function calls. */ \
832 0, 0, 0, 0, 0, 0, 0, 1, \
833 1, 1, 0, 1, 1, 1, 1, 1, \
834 1, 1, 1, 1, 0, 0, 0, 0, \
835 0, 0, 0, 0, 1, 1, 1, 1, \
836 1, 1, 1, 1, 0, 0, 0, 0, \
837 0, 0, 0, 0, 0, 0, 0, 0, \
838 0, 0, 0, 0, 1, 1, 1, 1, \
839 /* FP registers. */ \
840 1, 1, 1, 1, 1, 1, 1, 1, \
841 1, 1, 1, 1, 0, 0, 0, 0, \
842 1, 1, 1, 1, 1, 1, 1, 1, \
843 1, 1, 1, 1, 1, 1, 1, 1, \
844 1, 1, 1, 1, 0, 0, 0, 0, \
845 0, 0, 0, 0, 0, 0, 0, 0, \
846 0, 0, 0, 0, 0, 0, 0, 0, \
847 0, 0, 0, 0, 0, 0, 0, 0, \
848 /* Branch target registers. */ \
849 1, 1, 1, 1, 1, 0, 0, 0, \
850 /* XD registers. */ \
851 1, 1, 1, 1, 1, 1, 0, 0, \
852 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
853 1, 1, 0, 1, 1, 1, 1, 1, \
858 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
859 across SHcompact function calls. We can't tell whether a called
860 function is SHmedia or SHcompact, so we assume it may be when
861 compiling SHmedia code with the 32-bit ABI, since that's the only
862 ABI that can be linked with SHcompact code. */
863 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
865 && GET_MODE_SIZE (MODE) > 4 \
866 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
867 && (REGNO) <= FIRST_GENERAL_REG + 14) \
868 || (REGNO) == PR_MEDIA_REG))
870 /* Return number of consecutive hard regs needed starting at reg REGNO
871 to hold something of mode MODE.
872 This is ordinarily the length in words of a value of mode MODE
873 but can be less for certain modes in special long registers.
875 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
877 #define HARD_REGNO_NREGS(REGNO, MODE) \
878 (XD_REGISTER_P (REGNO) \
879 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
880 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
881 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
882 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
884 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
885 We can allow any mode in any general register. The special registers
886 only allow SImode. Don't allow any mode in the PR. */
888 /* We cannot hold DCmode values in the XD registers because alter_reg
889 handles subregs of them incorrectly. We could work around this by
890 spacing the XD registers like the DR registers, but this would require
891 additional memory in every compilation to hold larger register vectors.
892 We could hold SFmode / SCmode values in XD registers, but that
893 would require a tertiary reload when reloading from / to memory,
894 and a secondary reload to reload from / to general regs; that
895 seems to be a loosing proposition. */
896 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
897 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
898 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
899 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
901 : (MODE) == V2SFmode \
902 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
903 : (MODE) == V4SFmode \
904 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
905 : (MODE) == V16SFmode \
907 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
908 : (REGNO) == FIRST_XD_REG) \
909 : FP_REGISTER_P (REGNO) \
910 ? ((MODE) == SFmode \
911 || (TARGET_SHMEDIA && (MODE) == SImode) \
912 || ((TARGET_SH3E || TARGET_SHMEDIA) && (MODE) == SCmode) \
913 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
914 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
915 || (MODE) == V2SFmode))) \
916 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
917 : XD_REGISTER_P (REGNO) \
919 : TARGET_REGISTER_P (REGNO) \
920 ? ((MODE) == DImode || (MODE) == SImode) \
921 : (REGNO) == PR_REG ? 0 \
922 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
925 /* Value is 1 if MODE is a supported vector mode. */
926 #define VECTOR_MODE_SUPPORTED_P(MODE) \
928 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode))
930 /* Value is 1 if it is a good idea to tie two pseudo registers
931 when one has mode MODE1 and one has mode MODE2.
932 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
933 for any hard reg, then this must be 0 for correct output.
934 That's the case for xd registers: we don't hold SFmode values in
935 them, so we can't tie an SFmode pseudos with one in another
936 floating-point mode. */
938 #define MODES_TIEABLE_P(MODE1, MODE2) \
939 ((MODE1) == (MODE2) \
940 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
941 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
942 && (GET_MODE_SIZE (MODE2) <= 4)) \
943 : ((MODE1) != SFmode && (MODE2) != SFmode))))
945 /* Specify the registers used for certain standard purposes.
946 The values of these macros are register numbers. */
948 /* Define this if the program counter is overloaded on a register. */
949 /* #define PC_REGNUM 15*/
951 /* Register to use for pushing function arguments. */
952 #define STACK_POINTER_REGNUM SP_REG
954 /* Base register for access to local variables of the function. */
955 #define FRAME_POINTER_REGNUM FP_REG
957 /* Fake register that holds the address on the stack of the
958 current function's return address. */
959 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
961 /* Register to hold the addressing base for position independent
962 code access to data items. */
963 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
965 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
967 /* Value should be nonzero if functions must have frame pointers.
968 Zero means the frame pointer need not be set up (and parms may be accessed
969 via the stack pointer) in functions that seem suitable. */
971 #define FRAME_POINTER_REQUIRED 0
973 /* Definitions for register eliminations.
975 We have three registers that can be eliminated on the SH. First, the
976 frame pointer register can often be eliminated in favor of the stack
977 pointer register. Secondly, the argument pointer register can always be
978 eliminated; it is replaced with either the stack or frame pointer.
979 Third, there is the return address pointer, which can also be replaced
980 with either the stack or the frame pointer. */
982 /* This is an array of structures. Each structure initializes one pair
983 of eliminable registers. The "from" register number is given first,
984 followed by "to". Eliminations of the same "from" register are listed
985 in order of preference. */
987 /* If you add any registers here that are not actually hard registers,
988 and that have any alternative of elimination that doesn't always
989 apply, you need to amend calc_live_regs to exclude it, because
990 reload spills all eliminable registers where it sees an
991 can_eliminate == 0 entry, thus making them 'live' .
992 If you add any hard registers that can be eliminated in different
993 ways, you have to patch reload to spill them only when all alternatives
994 of elimination fail. */
996 #define ELIMINABLE_REGS \
997 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
998 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
999 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1000 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1001 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1003 /* Given FROM and TO register numbers, say whether this elimination
1005 #define CAN_ELIMINATE(FROM, TO) \
1006 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1008 /* Define the offset between two registers, one to be eliminated, and the other
1009 its replacement, at the start of a routine. */
1011 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1012 OFFSET = initial_elimination_offset ((FROM), (TO))
1014 /* Base register for access to arguments of the function. */
1015 #define ARG_POINTER_REGNUM AP_REG
1017 /* Register in which the static-chain is passed to a function. */
1018 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1020 /* The register in which a struct value address is passed. */
1022 #define STRUCT_VALUE_REGNUM 2
1024 /* If the structure value address is not passed in a register, define
1025 `STRUCT_VALUE' as an expression returning an RTX for the place
1026 where the address is passed. If it returns 0, the address is
1027 passed as an "invisible" first argument. */
1029 /* The Hitachi calling convention doesn't quite fit into this scheme since
1030 the address is passed like an invisible argument, but one that is always
1031 passed in memory. */
1032 #define STRUCT_VALUE \
1033 (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM))
1035 #define RETURN_IN_MEMORY(TYPE) \
1037 ? ((TYPE_MODE (TYPE) == BLKmode \
1038 ? (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1039 : GET_MODE_SIZE (TYPE_MODE (TYPE))) > 8) \
1040 : (TYPE_MODE (TYPE) == BLKmode \
1041 || TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE))
1043 /* Don't default to pcc-struct-return, because we have already specified
1044 exactly how to return structures in the RETURN_IN_MEMORY macro. */
1046 #define DEFAULT_PCC_STRUCT_RETURN 0
1048 #define SHMEDIA_REGS_STACK_ADJUST() \
1049 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1050 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1051 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1055 /* Define the classes of registers for register constraints in the
1056 machine description. Also define ranges of constants.
1058 One of the classes must always be named ALL_REGS and include all hard regs.
1059 If there is more than one class, another class must be named NO_REGS
1060 and contain no registers.
1062 The name GENERAL_REGS must be the name of a class (or an alias for
1063 another name such as ALL_REGS). This is the class of registers
1064 that is allowed by "g" or "r" in a register constraint.
1065 Also, registers outside this class are allocated only when
1066 instructions express preferences for them.
1068 The classes must be numbered in nondecreasing order; that is,
1069 a larger-numbered class must never be contained completely
1070 in a smaller-numbered class.
1072 For any two classes, it is very desirable that there be another
1073 class that represents their union. */
1075 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1076 be used as the destination of some of the arithmetic ops. There are
1077 also some special purpose registers; the T bit register, the
1078 Procedure Return Register and the Multiply Accumulate Registers. */
1079 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1080 reg_class_subunion. We don't want to have an actual union class
1081 of these, because it would only be used when both classes are calculated
1082 to give the same cost, but there is only one FPUL register.
1083 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1084 applying to the actual instruction alternative considered. E.g., the
1085 y/r alternative of movsi_ie is considered to have no more cost that
1086 the r/r alternative, which is patently untrue. */
1108 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1110 /* Give names of register classes as strings for dump file. */
1111 #define REG_CLASS_NAMES \
1125 "GENERAL_FP_REGS", \
1130 /* Define which registers fit in which classes.
1131 This is an initializer for a vector of HARD_REG_SET
1132 of length N_REG_CLASSES. */
1134 #define REG_CLASS_CONTENTS \
1137 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1139 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1141 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1143 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1145 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1147 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1148 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1149 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1150 /* GENERAL_REGS: */ \
1151 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1153 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1155 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1157 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1159 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1160 /* GENERAL_FP_REGS: */ \
1161 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1162 /* TARGET_REGS: */ \
1163 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1165 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1168 /* The same information, inverted:
1169 Return the class number of the smallest class containing
1170 reg number REGNO. This could be a conditional expression
1171 or could index an array. */
1173 extern int regno_reg_class[FIRST_PSEUDO_REGISTER];
1174 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1176 /* When defined, the compiler allows registers explicitly used in the
1177 rtl to be used as spill registers but prevents the compiler from
1178 extending the lifetime of these registers. */
1180 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1182 /* The order in which register should be allocated. */
1183 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1184 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1185 spilled or used otherwise, we better have the FP_REGS allocated first. */
1186 #define REG_ALLOC_ORDER \
1187 { 65, 66, 67, 68, 69, 70, 71, 64, \
1188 72, 73, 74, 75, 76, 77, 78, 79, \
1189 136,137,138,139,140,141,142,143, \
1190 80, 81, 82, 83, 84, 85, 86, 87, \
1191 88, 89, 90, 91, 92, 93, 94, 95, \
1192 96, 97, 98, 99,100,101,102,103, \
1193 104,105,106,107,108,109,110,111, \
1194 112,113,114,115,116,117,118,119, \
1195 120,121,122,123,124,125,126,127, \
1196 151, 1, 2, 3, 7, 6, 5, 4, \
1197 0, 8, 9, 10, 11, 12, 13, 14, \
1198 16, 17, 18, 19, 20, 21, 22, 23, \
1199 24, 25, 26, 27, 28, 29, 30, 31, \
1200 32, 33, 34, 35, 36, 37, 38, 39, \
1201 40, 41, 42, 43, 44, 45, 46, 47, \
1202 48, 49, 50, 51, 52, 53, 54, 55, \
1203 56, 57, 58, 59, 60, 61, 62, 63, \
1204 150, 15,145,146,147,144,148,149, \
1205 128,129,130,131,132,133,134,135, \
1208 /* The class value for index registers, and the one for base regs. */
1209 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1210 #define BASE_REG_CLASS GENERAL_REGS
1212 /* Get reg_class from a letter such as appears in the machine
1214 extern const enum reg_class reg_class_from_letter[];
1216 #define REG_CLASS_FROM_LETTER(C) \
1217 ( ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1219 /* The letters I, J, K, L and M in a register constraint string
1220 can be used to stand for particular ranges of immediate operands.
1221 This macro defines what the ranges are.
1222 C is the letter, and VALUE is a constant value.
1223 Return 1 if VALUE is in the range specified by C.
1224 I: arithmetic operand -127..128, as used in add, sub, etc
1225 J: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1226 K: shift operand 1,2,8 or 16
1227 L: logical operand 0..255, as used in and, or, etc.
1230 O: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1231 P: arithmetic operand -512..511, as used in SHmedia andi, ori
1234 #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1235 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1236 #define CONST_OK_FOR_J(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1237 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1238 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1239 #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1240 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1241 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1242 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1243 #define CONST_OK_FOR_O(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1244 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1245 #define CONST_OK_FOR_P(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1246 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1247 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1248 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
1249 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
1250 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
1251 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
1252 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1253 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1254 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
1255 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
1258 /* Similar, but for floating constants, and defining letters G and H.
1259 Here VALUE is the CONST_DOUBLE rtx itself. */
1261 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1262 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1263 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1266 /* Given an rtx X being reloaded into a reg required to be
1267 in class CLASS, return the class of reg to actually use.
1268 In general this is just CLASS; but on some machines
1269 in some cases it is preferable to use a more restrictive class. */
1271 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1272 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1273 && (GET_CODE (X) == CONST_DOUBLE \
1274 || GET_CODE (X) == SYMBOL_REF) \
1278 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1279 ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \
1280 || (CLASS) == DF_REGS) \
1281 && (GET_CODE (X) == REG && GENERAL_OR_AP_REGISTER_P (REGNO (X)))) \
1282 || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
1283 && GET_CODE (X) == REG \
1284 && FP_REGISTER_P (REGNO (X)))) \
1285 && ! TARGET_SHMEDIA \
1286 && MODE == SFmode) \
1288 : ((CLASS) == FPUL_REGS \
1289 && (GET_CODE (X) == MEM \
1290 || (GET_CODE (X) == REG \
1291 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1292 || REGNO (X) == T_REG \
1293 || system_reg_operand (X, VOIDmode))))) \
1295 : (((CLASS) == FP_REGS || (CLASS) == DF_REGS) && TARGET_SHMEDIA \
1296 && immediate_operand ((X), (MODE))) \
1298 : ((CLASS) == TARGET_REGS \
1299 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1300 ? ((target_operand ((X), (MODE)) \
1301 && ! target_reg_operand ((X), (MODE))) \
1302 ? NO_REGS : GENERAL_REGS) \
1303 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1304 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1305 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1306 ? GENERAL_REGS : NO_REGS)
1308 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1309 ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS) \
1310 && ! TARGET_SHMEDIA \
1311 && immediate_operand ((X), (MODE)) \
1312 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1313 && (MODE) == SFmode && fldi_ok ())) \
1315 : (CLASS == FPUL_REGS \
1316 && ((GET_CODE (X) == REG \
1317 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1318 || REGNO (X) == T_REG)))) \
1320 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1321 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \
1324 : (CLASS == FPSCR_REGS \
1325 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1326 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1328 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1330 /* Return the maximum number of consecutive registers
1331 needed to represent mode MODE in a register of class CLASS.
1333 On SH this is the size of MODE in words. */
1334 #define CLASS_MAX_NREGS(CLASS, MODE) \
1335 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1337 /* If defined, gives a class of registers that cannot be used as the
1338 operand of a SUBREG that changes the mode of the object illegally. */
1340 #define CLASS_CANNOT_CHANGE_MODE DF_REGS
1342 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1344 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1345 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1347 /* Stack layout; function entry, exit and calling. */
1349 /* Define the number of registers that can hold parameters.
1350 These macros are used only in other macro definitions below. */
1352 #define NPARM_REGS(MODE) \
1353 (TARGET_FPU_ANY && (MODE) == SFmode \
1354 ? (TARGET_SH5 ? 12 : 8) \
1355 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1356 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1357 ? (TARGET_SH5 ? 12 : 8) \
1358 : (TARGET_SH5 ? 8 : 4))
1360 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1361 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1363 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1364 #define FIRST_FP_RET_REG FIRST_FP_REG
1366 /* Define this if pushing a word on the stack
1367 makes the stack pointer a smaller address. */
1368 #define STACK_GROWS_DOWNWARD
1370 /* Define this macro if the addresses of local variable slots are at
1371 negative offsets from the frame pointer.
1373 The SH only has positive indexes, so grow the frame up. */
1374 /* #define FRAME_GROWS_DOWNWARD */
1376 /* Offset from the frame pointer to the first local variable slot to
1378 #define STARTING_FRAME_OFFSET 0
1380 /* If we generate an insn to push BYTES bytes,
1381 this says how many the stack pointer really advances by. */
1382 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1383 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1384 do correct alignment. */
1386 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1389 /* Offset of first parameter from the argument pointer register value. */
1390 #define FIRST_PARM_OFFSET(FNDECL) 0
1392 /* Value is the number of byte of arguments automatically
1393 popped when returning from a subroutine call.
1394 FUNDECL is the declaration node of the function (as a tree),
1395 FUNTYPE is the data type of the function (as a tree),
1396 or for a library call it is an identifier node for the subroutine name.
1397 SIZE is the number of bytes of arguments passed on the stack.
1399 On the SH, the caller does not pop any of its arguments that were passed
1401 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1403 /* Value is the number of bytes of arguments automatically popped when
1404 calling a subroutine.
1405 CUM is the accumulated argument list.
1407 On SHcompact, the call trampoline pops arguments off the stack. */
1408 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1410 /* Nonzero if we do not know how to pass TYPE solely in registers.
1411 Values that come in registers with inconvenient padding are stored
1412 to memory at the function start. */
1414 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1416 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1417 || TREE_ADDRESSABLE (TYPE)))
1418 /* Some subroutine macros specific to this machine. */
1420 #define BASE_RETURN_VALUE_REG(MODE) \
1421 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1422 ? FIRST_FP_RET_REG \
1423 : TARGET_FPU_ANY && (MODE) == SCmode \
1424 ? FIRST_FP_RET_REG \
1425 : (TARGET_FPU_DOUBLE \
1426 && ((MODE) == DFmode || (MODE) == SFmode \
1427 || (MODE) == DCmode || (MODE) == SCmode )) \
1428 ? FIRST_FP_RET_REG \
1431 #define BASE_ARG_REG(MODE) \
1432 ((TARGET_SH3E && ((MODE) == SFmode)) \
1433 ? FIRST_FP_PARM_REG \
1434 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1435 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1436 ? FIRST_FP_PARM_REG \
1439 /* Define how to find the value returned by a function.
1440 VALTYPE is the data type of the value (as a tree).
1441 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1442 otherwise, FUNC is 0.
1443 For the SH, this is like LIBCALL_VALUE, except that we must change the
1444 mode like PROMOTE_MODE does.
1445 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1446 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1448 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1450 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1451 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1452 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1453 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1454 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1455 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1456 || TREE_CODE (VALTYPE) == REAL_TYPE \
1457 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1458 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1459 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1461 /* Define how to find the value returned by a library function
1462 assuming the value has mode MODE. */
1463 #define LIBCALL_VALUE(MODE) \
1464 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1466 /* 1 if N is a possible register number for a function value. */
1467 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1468 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG) \
1469 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1471 /* 1 if N is a possible register number for function argument passing. */
1472 #define FUNCTION_ARG_REGNO_P(REGNO) \
1473 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG \
1474 + NPARM_REGS (SImode))) \
1475 || (TARGET_FPU_ANY \
1476 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG \
1477 + NPARM_REGS (SFmode))))
1479 /* Define a data type for recording info about an argument list
1480 during the scan of that argument list. This data type should
1481 hold all necessary information about the function itself
1482 and about the args processed so far, enough to enable macros
1483 such as FUNCTION_ARG to determine where the next arg should go.
1485 On SH, this is a single integer, which is a number of words
1486 of arguments scanned so far (including the invisible argument,
1487 if any, which holds the structure-value-address).
1488 Thus NARGREGS or more means all following args should go on the stack. */
1490 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1494 /* Non-zero if a prototype is available for the function. */
1496 /* The number of an odd floating-point register, that should be used
1497 for the next argument of type float. */
1498 int free_single_fp_reg;
1499 /* Whether we're processing an outgoing function call. */
1501 /* The number of general-purpose registers that should have been
1502 used to pass partial arguments, that are passed totally on the
1503 stack. On SHcompact, a call trampoline will pop them off the
1504 stack before calling the actual function, and, if the called
1505 function is implemented in SHcompact mode, the incoming arguments
1506 decoder will push such arguments back onto the stack. For
1507 incoming arguments, STACK_REGS also takes into account other
1508 arguments passed by reference, that the decoder will also push
1511 /* The number of general-purpose registers that should have been
1512 used to pass arguments, if the arguments didn't have to be passed
1515 /* Set by SHCOMPACT_BYREF if the current argument is to be passed by
1519 /* call_cookie is a bitmask used by call expanders, as well as
1520 function prologue and epilogues, to allow SHcompact to comply
1521 with the SH5 32-bit ABI, that requires 64-bit registers to be
1522 used even though only the lower 32-bit half is visible in
1523 SHcompact mode. The strategy is to call SHmedia trampolines.
1525 The alternatives for each of the argument-passing registers are
1526 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1527 contents from the address in it; (d) add 8 to it, storing the
1528 result in the next register, then (c); (e) copy it from some
1529 floating-point register,
1531 Regarding copies from floating-point registers, r2 may only be
1532 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1533 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1534 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1535 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1538 The bit mask is structured as follows:
1540 - 1 bit to tell whether to set up a return trampoline.
1542 - 3 bits to count the number consecutive registers to pop off the
1545 - 4 bits for each of r9, r8, r7 and r6.
1547 - 3 bits for each of r5, r4, r3 and r2.
1549 - 3 bits set to 0 (the most significant ones)
1552 1098 7654 3210 9876 5432 1098 7654 3210
1553 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1554 2223 3344 4555 6666 7777 8888 9999 SSS-
1556 - If F is set, the register must be copied from an FP register,
1557 whose number is encoded in the remaining bits.
1559 - Else, if L is set, the register must be loaded from the address
1560 contained in it. If the P bit is *not* set, the address of the
1561 following dword should be computed first, and stored in the
1564 - Else, if P is set, the register alone should be popped off the
1567 - After all this processing, the number of registers represented
1568 in SSS will be popped off the stack. This is an optimization
1569 for pushing/popping consecutive registers, typically used for
1570 varargs and large arguments partially passed in registers.
1572 - If T is set, a return trampoline will be set up for 64-bit
1573 return values to be split into 2 32-bit registers. */
1574 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1575 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1576 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1577 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1578 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1579 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1580 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1581 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1582 #define CALL_COOKIE_INT_REG(REG, VAL) \
1583 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1584 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1585 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1589 #define CUMULATIVE_ARGS struct sh_args
1591 #define GET_SH_ARG_CLASS(MODE) \
1592 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1594 /* There's no mention of complex float types in the SH5 ABI, so we
1595 should presumably handle them as aggregate types. */ \
1596 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1598 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1599 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1600 ? SH_ARG_FLOAT : SH_ARG_INT)
1602 #define ROUND_ADVANCE(SIZE) \
1603 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1605 /* Round a register number up to a proper boundary for an arg of mode
1608 The SH doesn't care about double alignment, so we only
1609 round doubles to even regs when asked to explicitly. */
1611 #define ROUND_REG(CUM, MODE) \
1612 (((TARGET_ALIGN_DOUBLE \
1613 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1614 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1615 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1616 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1617 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1618 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1620 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1621 for a call to a function whose data type is FNTYPE.
1622 For a library call, FNTYPE is 0.
1624 On SH, the offset always starts at 0: the first parm reg is always
1625 the same reg for a given argument class.
1627 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1629 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1631 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1632 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1634 = (TARGET_HITACHI && FNTYPE \
1635 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1636 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
1637 (CUM).arg_count[(int) SH_ARG_INT] \
1638 = (TARGET_SH5 && (FNTYPE) \
1639 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1640 (CUM).free_single_fp_reg = 0; \
1641 (CUM).outgoing = 1; \
1642 (CUM).stack_regs = 0; \
1643 (CUM).byref_regs = 0; \
1646 = (CALL_COOKIE_RET_TRAMP \
1647 (TARGET_SHCOMPACT && (FNTYPE) \
1648 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
1649 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
1650 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
1651 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
1652 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
1654 == FIRST_RET_REG))); \
1657 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1659 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0); \
1661 = (CALL_COOKIE_RET_TRAMP \
1662 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
1663 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
1666 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1668 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0); \
1669 (CUM).outgoing = 0; \
1672 /* FIXME: This is overly conservative. A SHcompact function that
1673 receives arguments ``by reference'' will have them stored in its
1674 own stack frame, so it must not pass pointers or references to
1675 these arguments to other functions by means of sibling calls. */
1676 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1677 (! TARGET_SHCOMPACT || current_function_args_info.stack_regs == 0)
1679 /* Update the data in CUM to advance over an argument
1680 of mode MODE and data type TYPE.
1681 (TYPE is null for libcalls where that information may not be
1684 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1685 if ((CUM).force_mem) \
1686 (CUM).force_mem = 0; \
1687 else if (TARGET_SH5) \
1689 tree TYPE_ = ((CUM).byref && (TYPE) \
1690 ? TREE_TYPE (TYPE) \
1692 enum machine_mode MODE_ = ((CUM).byref && (TYPE) \
1693 ? TYPE_MODE (TYPE_) \
1695 int dwords = (((CUM).byref \
1697 : (MODE_) == BLKmode \
1698 ? int_size_in_bytes (TYPE_) \
1699 : GET_MODE_SIZE (MODE_)) + 7) / 8; \
1700 int numregs = MIN (dwords, NPARM_REGS (SImode) \
1701 - (CUM).arg_count[(int) SH_ARG_INT]); \
1705 (CUM).arg_count[(int) SH_ARG_INT] += numregs; \
1706 if (TARGET_SHCOMPACT \
1707 && SHCOMPACT_FORCE_ON_STACK (MODE_, TYPE_)) \
1709 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1711 else if ((CUM).byref) \
1713 if (! (CUM).outgoing) \
1714 (CUM).stack_regs += numregs; \
1715 (CUM).byref_regs += numregs; \
1719 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1721 while (--numregs); \
1723 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1726 else if (dwords > numregs) \
1728 int pushregs = numregs; \
1730 if (TARGET_SHCOMPACT) \
1731 (CUM).stack_regs += numregs; \
1732 while (pushregs < NPARM_REGS (SImode) - 1 \
1733 && (CALL_COOKIE_INT_REG_GET \
1734 ((CUM).call_cookie, \
1735 NPARM_REGS (SImode) - pushregs) \
1739 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) \
1743 if (numregs == NPARM_REGS (SImode)) \
1745 |= CALL_COOKIE_INT_REG (0, 1) \
1746 | CALL_COOKIE_STACKSEQ (numregs - 1); \
1749 |= CALL_COOKIE_STACKSEQ (numregs); \
1752 if (GET_SH_ARG_CLASS (MODE_) == SH_ARG_FLOAT \
1753 && ((NAMED) || ! (CUM).prototype_p)) \
1755 if ((MODE_) == SFmode && (CUM).free_single_fp_reg) \
1756 (CUM).free_single_fp_reg = 0; \
1757 else if ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1758 < NPARM_REGS (SFmode)) \
1761 = MIN ((GET_MODE_SIZE (MODE_) + 7) / 8 * 2, \
1762 NPARM_REGS (SFmode) \
1763 - (CUM).arg_count[(int) SH_ARG_FLOAT]); \
1765 (CUM).arg_count[(int) SH_ARG_FLOAT] += numfpregs; \
1767 if (TARGET_SHCOMPACT && ! (CUM).prototype_p) \
1769 if ((CUM).outgoing && numregs > 0) \
1773 |= (CALL_COOKIE_INT_REG \
1774 ((CUM).arg_count[(int) SH_ARG_INT] \
1775 - numregs + ((numfpregs - 2) / 2), \
1776 4 + ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1777 - numfpregs) / 2)); \
1779 while (numfpregs -= 2); \
1781 else if ((MODE_) == SFmode && (NAMED) \
1782 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1783 < NPARM_REGS (SFmode))) \
1784 (CUM).free_single_fp_reg \
1785 = FIRST_FP_PARM_REG - numfpregs \
1786 + (CUM).arg_count[(int) SH_ARG_FLOAT] + 1; \
1790 else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
1791 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1792 = (ROUND_REG ((CUM), (MODE)) \
1793 + ((MODE) == BLKmode \
1794 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1795 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
1797 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1798 This macro is only used in this file. */
1800 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1802 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1803 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
1804 && ! (CUM).force_mem \
1806 ? ((MODE) == BLKmode \
1807 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1808 + int_size_in_bytes (TYPE)) \
1809 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1810 : ((ROUND_REG((CUM), (MODE)) \
1811 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1812 <= NPARM_REGS (MODE))) \
1813 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1815 /* Define where to put the arguments to a function.
1816 Value is zero to push the argument on the stack,
1817 or a hard register in which to store the argument.
1819 MODE is the argument's machine mode.
1820 TYPE is the data type of the argument (as a tree).
1821 This is null for libcalls where that information may
1823 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1824 the preceding args and about the function being called.
1825 NAMED is nonzero if this argument is a named parameter
1826 (otherwise it is an extra parameter matching an ellipsis).
1828 On SH the first args are normally in registers
1829 and the rest are pushed. Any arg that starts within the first
1830 NPARM_REGS words is at least partially passed in a register unless
1831 its data type forbids. */
1833 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1835 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1837 || (! TARGET_HITACHI && (TARGET_SH3E || ! current_function_varargs)))) \
1838 ? gen_rtx_REG ((MODE), \
1839 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
1840 ^ ((MODE) == SFmode && TARGET_SH4 \
1841 && TARGET_LITTLE_ENDIAN != 0))) \
1843 ? ((MODE) == VOIDmode && TARGET_SHCOMPACT \
1844 ? GEN_INT ((CUM).call_cookie) \
1845 /* The following test assumes unnamed arguments are promoted to \
1847 : (MODE) == SFmode && (CUM).free_single_fp_reg \
1848 ? SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), (CUM).free_single_fp_reg) \
1849 : (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1850 && ((NAMED) || ! (CUM).prototype_p) \
1851 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode)) \
1852 ? ((! (CUM).prototype_p && TARGET_SHMEDIA) \
1853 ? SH5_PROTOTYPELESS_FLOAT_ARG ((CUM), (MODE)) \
1854 : SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), \
1856 + (CUM).arg_count[(int) SH_ARG_FLOAT])) \
1857 : ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1858 && (! TARGET_SHCOMPACT \
1859 || (! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1860 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1861 (TYPE), (NAMED))))) \
1862 ? gen_rtx_REG ((MODE), (FIRST_PARM_REG \
1863 + (CUM).arg_count[(int) SH_ARG_INT])) \
1867 /* Whether an argument must be passed by reference. On SHcompact, we
1868 pretend arguments wider than 32-bits that would have been passed in
1869 registers are passed by reference, so that an SHmedia trampoline
1870 loads them into the full 64-bits registers. */
1871 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) \
1872 (MUST_PASS_IN_STACK ((MODE), (TYPE)) \
1873 || SHCOMPACT_BYREF ((CUM), (MODE), (TYPE), (NAMED)))
1875 #define SHCOMPACT_BYREF(CUM, MODE, TYPE, NAMED) \
1877 = (TARGET_SHCOMPACT \
1878 && (CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1879 && (! (NAMED) || GET_SH_ARG_CLASS (MODE) == SH_ARG_INT \
1880 || (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1881 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1882 >= NPARM_REGS (SFmode)))) \
1883 && ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1884 : GET_MODE_SIZE (MODE)) > 4 \
1885 && ! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1886 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1888 ? ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1889 : GET_MODE_SIZE (MODE)) \
1892 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1893 register in SHcompact mode, it must be padded in the most
1894 significant end. This means that passing it by reference wouldn't
1895 pad properly on a big-endian machine. In this particular case, we
1896 pass this argument on the stack, in a way that the call trampoline
1897 will load its value into the appropriate register. */
1898 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1899 ((MODE) == BLKmode \
1900 && TARGET_SHCOMPACT \
1901 && ! TARGET_LITTLE_ENDIAN \
1902 && int_size_in_bytes (TYPE) > 4 \
1903 && int_size_in_bytes (TYPE) < 8)
1905 /* Minimum alignment for an argument to be passed by callee-copy
1906 reference. We need such arguments to be aligned to 8 byte
1907 boundaries, because they'll be loaded using quad loads. */
1908 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1910 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
1912 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
1913 : GET_MODE_ALIGNMENT (MODE)) \
1914 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
1916 /* The SH5 ABI requires floating-point arguments to be passed to
1917 functions without a prototype in both an FP register and a regular
1918 register or the stack. When passing the argument in both FP and
1919 general-purpose registers, list the FP register first. */
1920 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1926 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1927 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1928 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1933 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1934 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1935 + (CUM).arg_count[(int) SH_ARG_INT]) \
1936 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1937 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1940 /* The SH5 ABI requires regular registers or stack slots to be
1941 reserved for floating-point arguments. Registers are taken care of
1942 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1943 Unfortunately, there's no way to just reserve a stack slot, so
1944 we'll end up needlessly storing a copy of the argument in the
1945 stack. For incoming arguments, however, the PARALLEL will be
1946 optimized to the register-only form, and the value in the stack
1947 slot won't be used at all. */
1948 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1949 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1950 ? gen_rtx_REG ((MODE), (REG)) \
1951 : gen_rtx_PARALLEL ((MODE), \
1954 (VOIDmode, NULL_RTX, \
1957 (VOIDmode, gen_rtx_REG ((MODE), \
1961 #define STRICT_ARGUMENT_NAMING TARGET_SH5
1963 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI && ! TARGET_SH5)
1965 /* For an arg passed partly in registers and partly in memory,
1966 this is the number of registers used.
1967 For args passed entirely in registers or entirely in memory, zero.
1969 We sometimes split args. */
1971 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1973 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1975 && (ROUND_REG ((CUM), (MODE)) \
1976 + ((MODE) != BLKmode \
1977 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
1978 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
1979 > NPARM_REGS (MODE))) \
1980 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
1981 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
1982 && ! TARGET_SHCOMPACT) \
1983 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
1986 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1987 (TARGET_SH5 && (MODE) == BLKmode \
1988 && ((CUM).arg_count[(int) SH_ARG_INT] \
1989 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
1991 /* Perform any needed actions needed for a function that is receiving a
1992 variable number of arguments. */
1994 /* We actually emit the code in sh_expand_prologue. We used to use
1995 a static variable to flag that we need to emit this code, but that
1996 doesn't when inlining, when functions are deferred and then emitted
1997 later. Fortunately, we already have two flags that are part of struct
1998 function that tell if a function uses varargs or stdarg. */
1999 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) do \
2000 if (! current_function_varargs && ! current_function_stdarg) \
2004 /* Define the `__builtin_va_list' type for the ABI. */
2005 #define BUILD_VA_LIST_TYPE(VALIST) \
2006 (VALIST) = sh_build_va_list ()
2008 /* Implement `va_start' for varargs and stdarg. */
2009 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2010 sh_va_start (stdarg, valist, nextarg)
2012 /* Implement `va_arg'. */
2013 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2014 sh_va_arg (valist, type)
2016 /* Call the function profiler with a given profile label.
2017 We use two .aligns, so as to make sure that both the .long is aligned
2018 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2019 from the trapa instruction. */
2021 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2023 fprintf((STREAM), "\t.align\t2\n"); \
2024 fprintf((STREAM), "\ttrapa\t#33\n"); \
2025 fprintf((STREAM), "\t.align\t2\n"); \
2026 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2029 /* Define this macro if the code for function profiling should come
2030 before the function prologue. Normally, the profiling code comes
2033 #define PROFILE_BEFORE_PROLOGUE
2035 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2036 the stack pointer does not matter. The value is tested only in
2037 functions that have frame pointers.
2038 No definition is equivalent to always zero. */
2040 #define EXIT_IGNORE_STACK 1
2043 On the SH, the trampoline looks like
2044 2 0002 D202 mov.l l2,r2
2045 1 0000 D301 mov.l l1,r3
2048 5 0008 00000000 l1: .long area
2049 6 000c 00000000 l2: .long function */
2051 /* Length in units of the trampoline for entering a nested function. */
2052 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 32 : 16)
2054 /* Alignment required for a trampoline in bits . */
2055 #define TRAMPOLINE_ALIGNMENT \
2056 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 : 64)
2058 /* Emit RTL insns to initialize the variable parts of a trampoline.
2059 FNADDR is an RTX for the address of the function's pure code.
2060 CXT is an RTX for the static chain value for the function. */
2062 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) do \
2066 rtx tramp_templ = gen_rtx_SYMBOL_REF (Pmode, \
2067 "__GCC_nested_trampoline"); \
2068 int fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode); \
2070 tramp_templ = gen_datalabel_ref (tramp_templ); \
2071 emit_block_move (gen_rtx_MEM (BLKmode, (TRAMP)), \
2072 gen_rtx_MEM (BLKmode, tramp_templ), \
2073 GEN_INT (fixed_len)); \
2074 emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), \
2077 emit_move_insn (gen_rtx_MEM (Pmode, \
2078 plus_constant ((TRAMP), \
2080 + GET_MODE_SIZE (Pmode))), \
2082 emit_insn (gen_ic_invalidate_line (TRAMP)); \
2085 emit_move_insn (gen_rtx_MEM (SImode, (TRAMP)), \
2086 GEN_INT (trunc_int_for_mode \
2087 (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,\
2089 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 4)), \
2090 GEN_INT (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009));\
2091 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
2093 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
2095 if (TARGET_HARVARD) \
2097 if (TARGET_USERMODE) \
2098 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__ic_invalidate"),\
2099 0, VOIDmode, 1, (TRAMP), SImode); \
2101 emit_insn (gen_ic_invalidate_line (TRAMP)); \
2105 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2107 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2110 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), GEN_INT (1), \
2111 gen_reg_rtx (Pmode), 0, \
2115 /* A C expression whose value is RTL representing the value of the return
2116 address for the frame COUNT steps up from the current frame.
2117 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2118 can ignore COUNT. */
2120 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2122 ? get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
2125 /* A C expression whose value is RTL representing the location of the
2126 incoming return address at the beginning of any function, before the
2127 prologue. This RTL is either a REG, indicating that the return
2128 value is saved in REG, or a MEM representing a location in
2130 #define INCOMING_RETURN_ADDR_RTX \
2131 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2133 /* Generate necessary RTL for __builtin_saveregs(). */
2134 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
2136 /* Addressing modes, and classification of registers for them. */
2137 #define HAVE_POST_INCREMENT TARGET_SH1
2138 /*#define HAVE_PRE_INCREMENT 1*/
2139 /*#define HAVE_POST_DECREMENT 1*/
2140 #define HAVE_PRE_DECREMENT TARGET_SH1
2142 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2144 #define USE_LOAD_PRE_DECREMENT(mode) 0
2145 #define USE_STORE_POST_INCREMENT(mode) 0
2146 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2149 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2150 < (TARGET_SMALLCODE ? 2 : \
2151 ((ALIGN >= 32) ? 16 : 2)))
2153 /* Macros to check register numbers against specific register classes. */
2155 /* These assume that REGNO is a hard or pseudo reg number.
2156 They give nonzero only if REGNO is a hard reg of the suitable class
2157 or a pseudo reg currently allocated to a suitable hard reg.
2158 Since they use reg_renumber, they are safe only once reg_renumber
2159 has been allocated, which happens in local-alloc.c. */
2161 #define REGNO_OK_FOR_BASE_P(REGNO) \
2162 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2163 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2164 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2166 ? (GENERAL_REGISTER_P (REGNO) \
2167 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2168 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2170 /* Maximum number of registers that can appear in a valid memory
2173 #define MAX_REGS_PER_ADDRESS 2
2175 /* Recognize any constant value that is a valid address. */
2177 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2179 /* Nonzero if the constant value X is a legitimate general operand. */
2181 #define LEGITIMATE_CONSTANT_P(X) \
2183 ? (GET_MODE (X) != DFmode \
2184 || (X) == CONST0_RTX (GET_MODE (X)) \
2185 || ! TARGET_SHMEDIA_FPU \
2186 || TARGET_SHMEDIA64) \
2187 : (GET_CODE (X) != CONST_DOUBLE \
2188 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2189 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X)))))
2191 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2192 and check its validity for a certain class.
2193 We have two alternate definitions for each of them.
2194 The usual definition accepts all pseudo regs; the other rejects
2195 them unless they have been allocated suitable hard regs.
2196 The symbol REG_OK_STRICT causes the latter definition to be used. */
2198 #ifndef REG_OK_STRICT
2200 /* Nonzero if X is a hard reg that can be used as a base reg
2201 or if it is a pseudo reg. */
2202 #define REG_OK_FOR_BASE_P(X) \
2203 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2205 /* Nonzero if X is a hard reg that can be used as an index
2206 or if it is a pseudo reg. */
2207 #define REG_OK_FOR_INDEX_P(X) \
2208 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2209 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2211 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2212 or if X is a pseudo reg. */
2213 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2214 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2215 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2219 /* Nonzero if X is a hard reg that can be used as a base reg. */
2220 #define REG_OK_FOR_BASE_P(X) \
2221 REGNO_OK_FOR_BASE_P (REGNO (X))
2223 /* Nonzero if X is a hard reg that can be used as an index. */
2224 #define REG_OK_FOR_INDEX_P(X) \
2225 REGNO_OK_FOR_INDEX_P (REGNO (X))
2227 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2228 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2229 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2233 /* The 'Q' constraint is a pc relative load operand. */
2234 #define EXTRA_CONSTRAINT_Q(OP) \
2235 (GET_CODE (OP) == MEM \
2236 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2237 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2238 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2239 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2240 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2242 /* The `S' constraint is a 16-bit constant, literal or symbolic. */
2243 #define EXTRA_CONSTRAINT_S(OP) \
2244 (GET_CODE (OP) == CONST \
2245 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2246 && GET_MODE (XEXP ((OP), 0)) == DImode \
2247 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2248 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2249 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2250 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2251 && (MOVI_SHORI_BASE_OPERAND_P \
2252 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2253 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2256 /* Check whether OP is a datalabel unspec. */
2257 #define DATALABEL_REF_NO_CONST_P(OP) \
2258 (GET_CODE (OP) == UNSPEC \
2259 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2260 && XVECLEN ((OP), 0) == 1 \
2261 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2262 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2264 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2266 #define DATALABEL_REF_P(OP) \
2267 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2268 || DATALABEL_REF_NO_CONST_P (OP))
2270 #define GOT_ENTRY_P(OP) \
2271 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2272 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2274 #define GOTPLT_ENTRY_P(OP) \
2275 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2276 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2278 #define GOTOFF_P(OP) \
2279 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2280 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTOFF)
2282 #define PIC_ADDR_P(OP) \
2283 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2284 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2286 #define NON_PIC_REFERENCE_P(OP) \
2287 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2288 || DATALABEL_REF_P (OP) \
2289 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2290 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2291 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2292 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2294 #define PIC_REFERENCE_P(OP) \
2295 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2296 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2298 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2299 (flag_pic ? PIC_REFERENCE_P (OP) : NON_PIC_REFERENCE_P (OP))
2301 /* The `T' constraint is a label or a symbol. */
2302 #define EXTRA_CONSTRAINT_T(OP) \
2303 (NON_PIC_REFERENCE_P (OP))
2305 #define EXTRA_CONSTRAINT(OP, C) \
2306 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2307 : (C) == 'S' ? EXTRA_CONSTRAINT_S (OP) \
2308 : (C) == 'T' ? EXTRA_CONSTRAINT_T (OP) \
2311 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2312 that is a valid memory address for an instruction.
2313 The MODE argument is the machine mode for the MEM expression
2314 that wants to use this address. */
2316 #define MODE_DISP_OK_4(X,MODE) \
2317 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2318 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
2320 #define MODE_DISP_OK_8(X,MODE) \
2321 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2322 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2324 #define BASE_REGISTER_RTX_P(X) \
2325 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2326 || (GET_CODE (X) == SUBREG \
2327 && GET_CODE (SUBREG_REG (X)) == REG \
2328 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2330 /* Since this must be r0, which is a single register class, we must check
2331 SUBREGs more carefully, to be sure that we don't accept one that extends
2332 outside the class. */
2333 #define INDEX_REGISTER_RTX_P(X) \
2334 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2335 || (GET_CODE (X) == SUBREG \
2336 && GET_CODE (SUBREG_REG (X)) == REG \
2337 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2339 /* Jump to LABEL if X is a valid address RTX. This must also take
2340 REG_OK_STRICT into account when deciding about valid registers, but it uses
2341 the above macros so we are in luck.
2349 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
2350 into the FRx registers. We implement this by setting the maximum offset
2351 to zero when the value is SFmode. This also restricts loading of SFmode
2352 values into the integer registers, but that can't be helped. */
2354 /* The SH allows a displacement in a QI or HI amode, but only when the
2355 other operand is R0. GCC doesn't handle this very well, so we forgo
2358 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2359 DI can be any number 0..60. */
2361 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2363 if (GET_CODE (OP) == CONST_INT) \
2365 if (TARGET_SHMEDIA) \
2367 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2368 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2369 && INTVAL (OP) >= -512 * MODE_SIZE \
2370 && INTVAL (OP) < 512 * MODE_SIZE) \
2375 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2376 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2380 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2382 if (BASE_REGISTER_RTX_P (X)) \
2384 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2385 && ! TARGET_SHMEDIA \
2386 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2388 else if (GET_CODE (X) == PLUS \
2389 && ((MODE) != PSImode || reload_completed)) \
2391 rtx xop0 = XEXP ((X), 0); \
2392 rtx xop1 = XEXP ((X), 1); \
2393 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2394 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2395 if (GET_MODE_SIZE (MODE) <= 4 \
2396 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2397 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
2399 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2401 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2407 /* Try machine-dependent ways of modifying an illegitimate address
2408 to be legitimate. If we find one, return the new, valid address.
2409 This macro is used in only one place: `memory_address' in explow.c.
2411 OLDX is the address as it was before break_out_memory_refs was called.
2412 In some cases it is useful to look at this to decide what needs to be done.
2414 MODE and WIN are passed so that this macro can use
2415 GO_IF_LEGITIMATE_ADDRESS.
2417 It is always safe for this macro to do nothing. It exists to recognize
2418 opportunities to optimize the output.
2420 For the SH, if X is almost suitable for indexing, but the offset is
2421 out of range, convert it into a normal form so that cse has a chance
2422 of reducing the number of address registers used. */
2424 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2427 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2428 if (GET_CODE (X) == PLUS \
2429 && (GET_MODE_SIZE (MODE) == 4 \
2430 || GET_MODE_SIZE (MODE) == 8) \
2431 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2432 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2433 && ! TARGET_SHMEDIA \
2434 && ! (TARGET_SH4 && (MODE) == DFmode) \
2435 && ! (TARGET_SH3E && (MODE) == SFmode)) \
2437 rtx index_rtx = XEXP ((X), 1); \
2438 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2441 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2442 /* On rare occasions, we might get an unaligned pointer \
2443 that is indexed in a way to give an aligned address. \
2444 Therefore, keep the lower two bits in offset_base. */ \
2445 /* Instead of offset_base 128..131 use 124..127, so that \
2446 simple add suffices. */ \
2449 offset_base = ((offset + 4) & ~60) - 4; \
2452 offset_base = offset & ~60; \
2453 /* Sometimes the normal form does not suit DImode. We \
2454 could avoid that by using smaller ranges, but that \
2455 would give less optimized code when SImode is \
2457 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2459 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2460 GEN_INT (offset_base), NULL_RTX, 0, \
2463 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2469 /* A C compound statement that attempts to replace X, which is an address
2470 that needs reloading, with a valid memory address for an operand of
2471 mode MODE. WIN is a C statement label elsewhere in the code.
2473 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2474 of the address. That will allow inheritance of the address reloads. */
2476 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2478 if (GET_CODE (X) == PLUS \
2479 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2480 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2481 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2482 && ! TARGET_SHMEDIA \
2483 && ! (TARGET_SH4 && (MODE) == DFmode) \
2484 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2486 rtx index_rtx = XEXP (X, 1); \
2487 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2490 if (TARGET_SH3E && MODE == SFmode) \
2493 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2494 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2498 /* Instead of offset_base 128..131 use 124..127, so that \
2499 simple add suffices. */ \
2502 offset_base = ((offset + 4) & ~60) - 4; \
2505 offset_base = offset & ~60; \
2506 /* Sometimes the normal form does not suit DImode. We \
2507 could avoid that by using smaller ranges, but that \
2508 would give less optimized code when SImode is \
2510 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2512 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2513 GEN_INT (offset_base)); \
2514 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
2515 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2516 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2521 /* We must re-recognize what we created before. */ \
2522 else if (GET_CODE (X) == PLUS \
2523 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2524 && GET_CODE (XEXP (X, 0)) == PLUS \
2525 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2526 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2527 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2528 && ! TARGET_SHMEDIA \
2529 && ! (TARGET_SH3E && MODE == SFmode)) \
2531 /* Because this address is so complex, we know it must have \
2532 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2533 it is already unshared, and needs no further unsharing. */ \
2534 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2535 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2540 /* Go to LABEL if ADDR (a legitimate address expression)
2541 has an effect that depends on the machine mode it is used for.
2543 ??? Strictly speaking, we should also include all indexed addressing,
2544 because the index scale factor is the length of the operand.
2545 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2546 high if we did that. So we rely on reload to fix things up. */
2548 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2550 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2554 /* Specify the machine mode that this machine uses
2555 for the index in the tablejump instruction. */
2556 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
2558 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2559 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2560 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2561 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2562 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2563 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2566 /* Define as C expression which evaluates to nonzero if the tablejump
2567 instruction expects the table to contain offsets from the address of the
2569 Do not define this if the table should contain absolute addresses. */
2570 #define CASE_VECTOR_PC_RELATIVE 1
2572 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2573 #define FLOAT_TYPE_SIZE 32
2575 /* Since the SH3e has only `float' support, it is desirable to make all
2576 floating point types equivalent to `float'. */
2577 #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
2579 /* 'char' is signed by default. */
2580 #define DEFAULT_SIGNED_CHAR 1
2582 /* The type of size_t unsigned int. */
2583 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2586 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2588 #define WCHAR_TYPE "short unsigned int"
2589 #define WCHAR_TYPE_SIZE 16
2591 #define SH_ELF_WCHAR_TYPE "long int"
2593 /* Don't cse the address of the function being compiled. */
2594 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
2596 /* Max number of bytes we can move from memory to memory
2597 in one reasonably fast instruction. */
2598 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2600 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2601 MOVE_MAX is not a compile-time constant. */
2602 #define MAX_MOVE_MAX 8
2604 /* Max number of bytes we want move_by_pieces to be able to copy
2606 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2608 /* Define if operations between registers always perform the operation
2609 on the full register even if a narrower mode is specified. */
2610 #define WORD_REGISTER_OPERATIONS
2612 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2613 will either zero-extend or sign-extend. The value of this macro should
2614 be the code that says which one of the two operations is implicitly
2615 done, NIL if none. */
2616 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
2618 /* Define if loading short immediate values into registers sign extends. */
2619 #define SHORT_IMMEDIATES_SIGN_EXTEND
2621 /* Nonzero if access to memory by bytes is no faster than for words. */
2622 #define SLOW_BYTE_ACCESS 1
2624 /* We assume that the store-condition-codes instructions store 0 for false
2625 and some other value for true. This is the value stored for true. */
2627 #define STORE_FLAG_VALUE 1
2629 /* Immediate shift counts are truncated by the output routines (or was it
2630 the assembler?). Shift counts in a register are truncated by SH. Note
2631 that the native compiler puts too large (> 32) immediate shift counts
2632 into a register and shifts by the register, letting the SH decide what
2633 to do instead of doing that itself. */
2634 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2635 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2636 expects - the sign bit is significant - so it appears that we need to
2637 leave this zero for correct SH3 code. */
2638 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
2640 /* All integers have the same format so truncation is easy. */
2641 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2643 /* Define this if addresses of constant functions
2644 shouldn't be put through pseudo regs where they can be cse'd.
2645 Desirable on machines where ordinary constants are expensive
2646 but a CALL with constant address is cheap. */
2647 /*#define NO_FUNCTION_CSE 1*/
2649 /* Chars and shorts should be passed as ints. */
2650 #define PROMOTE_PROTOTYPES 1
2652 /* The machine modes of pointers and functions. */
2653 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2654 #define FUNCTION_MODE Pmode
2656 /* The relative costs of various types of constants. */
2658 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2660 if (TARGET_SHMEDIA) \
2662 if (CONST_OK_FOR_J (INTVAL (RTX))) \
2663 return COSTS_N_INSNS (1); \
2664 else if (CONST_OK_FOR_J (INTVAL (RTX) >> 16)) \
2665 return COSTS_N_INSNS (2); \
2666 else if (CONST_OK_FOR_J ((INTVAL (RTX) >> 16) >> 16)) \
2667 return COSTS_N_INSNS (3); \
2669 return COSTS_N_INSNS (4); \
2671 if (CONST_OK_FOR_I (INTVAL (RTX))) \
2673 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \
2674 && CONST_OK_FOR_L (INTVAL (RTX))) \
2681 if (TARGET_SHMEDIA64) \
2682 return COSTS_N_INSNS (4); \
2683 if (TARGET_SHMEDIA32) \
2684 return COSTS_N_INSNS (2); \
2686 case CONST_DOUBLE: \
2687 if (TARGET_SHMEDIA) \
2688 return COSTS_N_INSNS (4); \
2692 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2694 return COSTS_N_INSNS (addsubcosts (X)); \
2696 return COSTS_N_INSNS (andcosts (X)); \
2698 return COSTS_N_INSNS (multcosts (X)); \
2702 return COSTS_N_INSNS (shiftcosts (X)); \
2707 return COSTS_N_INSNS (20); \
2712 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2713 are actually function calls with some special constraints on arguments
2716 These macros tell reorg that the references to arguments and
2717 register clobbers for insns of type sfunc do not appear to happen
2718 until after the millicode call. This allows reorg to put insns
2719 which set the argument registers into the delay slot of the millicode
2720 call -- thus they act more like traditional CALL_INSNs.
2722 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2723 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2726 #define INSN_SETS_ARE_DELAYED(X) \
2727 ((GET_CODE (X) == INSN \
2728 && GET_CODE (PATTERN (X)) != SEQUENCE \
2729 && GET_CODE (PATTERN (X)) != USE \
2730 && GET_CODE (PATTERN (X)) != CLOBBER \
2731 && get_attr_is_sfunc (X)))
2733 #define INSN_REFERENCES_ARE_DELAYED(X) \
2734 ((GET_CODE (X) == INSN \
2735 && GET_CODE (PATTERN (X)) != SEQUENCE \
2736 && GET_CODE (PATTERN (X)) != USE \
2737 && GET_CODE (PATTERN (X)) != CLOBBER \
2738 && get_attr_is_sfunc (X)))
2741 /* Position Independent Code. */
2743 /* The prefix used to mark SYMBOL_REFs that refer to data symbols. */
2744 #define SH_DATALABEL_ENCODING "#"
2746 /* Return true if SYM_NAME starts with SH_DATALABEL_ENCODING. */
2747 #define DATALABEL_SYMNAME_P(SYM_NAME) \
2748 (SH_DATALABEL_ENCODING[1] ? (abort (), 0) : \
2749 (SYM_NAME)[0] == SH_DATALABEL_ENCODING[0])
2751 /* Skip an optional SH_DATALABEL_ENCODING in the beginning of
2752 SYM_NAME. Then, remove a leading *, like the default definition in
2754 #define STRIP_DATALABEL_ENCODING(VAR, SYM_NAME) \
2755 (VAR) = (SYM_NAME) + (DATALABEL_SYMNAME_P (SYM_NAME) \
2756 ? strlen (SH_DATALABEL_ENCODING) : 0)
2758 /* We can't directly access anything that contains a symbol,
2759 nor can we indirect via the constant pool. */
2760 #define LEGITIMATE_PIC_OPERAND_P(X) \
2761 (! nonpic_symbol_mentioned_p (X) \
2762 && (GET_CODE (X) != SYMBOL_REF \
2763 || ! CONSTANT_POOL_ADDRESS_P (X) \
2764 || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))
2766 #define SYMBOLIC_CONST_P(X) \
2767 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2768 && nonpic_symbol_mentioned_p (X))
2770 /* Compute the cost of an address. For the SH, all valid addresses are
2771 the same cost. Use a slightly higher cost for reg + reg addressing,
2772 since it increases pressure on r0. */
2774 #define ADDRESS_COST(X) (GET_CODE (X) == PLUS && ! CONSTANT_P (XEXP (X, 1)) \
2775 && ! TARGET_SHMEDIA \
2778 /* Compute extra cost of moving data between one register class
2781 /* Regclass always uses 2 for moves in the same register class;
2782 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
2783 it uses this information. Hence, the general register <-> floating point
2784 register information here is not used for SFmode. */
2785 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2786 (((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
2787 : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS || (DSTCLASS) == DF_REGS) \
2788 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
2789 || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \
2790 && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
2791 || (SRCCLASS) == DF_REGS))) \
2792 ? (TARGET_SHMEDIA ? 2 \
2793 : TARGET_FMOVD ? 8 : 12) \
2794 : (((DSTCLASS) == FPUL_REGS \
2795 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
2796 || (SRCCLASS == FPUL_REGS \
2797 && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \
2799 : (((DSTCLASS) == FPUL_REGS \
2800 && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
2801 || (SRCCLASS) == T_REGS)) \
2802 || ((SRCCLASS) == FPUL_REGS \
2803 && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
2805 : (((SRCCLASS) == TARGET_REGS && (DSTCLASS) != GENERAL_REGS) \
2806 || ((DSTCLASS) == TARGET_REGS && (SRCCLASS) != GENERAL_REGS)) \
2808 : (((SRCCLASS) == FPSCR_REGS && (DSTCLASS) != GENERAL_REGS) \
2809 || ((DSTCLASS) == FPSCR_REGS && (SRCCLASS) != GENERAL_REGS)) \
2811 : 2) * ((MODE) == V16SFmode ? 8 : (MODE) == V4SFmode ? 2 : 1))
2813 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2814 would be so that people with slow memory systems could generate
2815 different code that does fewer memory accesses. */
2817 /* A C expression for the cost of a branch instruction. A value of 1
2818 is the default; other values are interpreted relative to that.
2819 The SH1 does not have delay slots, hence we get a pipeline stall
2820 at every branch. The SH4 is superscalar, so the single delay slot
2821 is not sufficient to keep both pipelines filled. */
2822 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2824 /* Assembler output control. */
2826 /* A C string constant describing how to begin a comment in the target
2827 assembler language. The compiler assumes that the comment will end at
2828 the end of the line. */
2829 #define ASM_COMMENT_START "!"
2831 /* The text to go at the start of the assembler file. */
2832 #define ASM_FILE_START(STREAM) \
2833 output_file_start (STREAM)
2835 #define ASM_APP_ON ""
2836 #define ASM_APP_OFF ""
2837 #define FILE_ASM_OP "\t.file\n"
2838 #define SET_ASM_OP "\t.set\t"
2840 /* How to change between sections. */
2842 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2843 #define DATA_SECTION_ASM_OP "\t.data"
2845 #if defined CRT_BEGIN || defined CRT_END
2846 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2847 # undef TEXT_SECTION_ASM_OP
2848 # if __SHMEDIA__ == 1 && __SH5__ == 32
2849 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2851 # define TEXT_SECTION_ASM_OP "\t.text"
2856 /* If defined, a C expression whose value is a string containing the
2857 assembler operation to identify the following data as
2858 uninitialized global data. If not defined, and neither
2859 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2860 uninitialized global data will be output in the data section if
2861 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2863 #ifndef BSS_SECTION_ASM_OP
2864 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2867 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2868 separate, explicit argument. If you define this macro, it is used
2869 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2870 handling the required alignment of the variable. The alignment is
2871 specified as the number of bits.
2873 Try to use function `asm_output_aligned_bss' defined in file
2874 `varasm.c' when defining this macro. */
2875 #ifndef ASM_OUTPUT_ALIGNED_BSS
2876 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2877 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2880 /* Define this so that jump tables go in same section as the current function,
2881 which could be text or it could be a user defined section. */
2882 #define JUMP_TABLES_IN_TEXT_SECTION 1
2884 #undef DO_GLOBAL_CTORS_BODY
2885 #define DO_GLOBAL_CTORS_BODY \
2887 typedef (*pfunc)(); \
2888 extern pfunc __ctors[]; \
2889 extern pfunc __ctors_end[]; \
2891 for (p = __ctors_end; p > __ctors; ) \
2897 #undef DO_GLOBAL_DTORS_BODY
2898 #define DO_GLOBAL_DTORS_BODY \
2900 typedef (*pfunc)(); \
2901 extern pfunc __dtors[]; \
2902 extern pfunc __dtors_end[]; \
2904 for (p = __dtors; p < __dtors_end; p++) \
2910 #define ASM_OUTPUT_REG_PUSH(file, v) \
2911 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
2913 #define ASM_OUTPUT_REG_POP(file, v) \
2914 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
2916 /* DBX register number for a given compiler register number. */
2917 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2919 /* svr4.h undefines this macro, yet we really want to use the same numbers
2920 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2921 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2923 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2924 (GENERAL_REGISTER_P (REGNO) \
2925 ? ((REGNO) - FIRST_GENERAL_REG) \
2926 : FP_REGISTER_P (REGNO) \
2927 ? ((REGNO) - FIRST_FP_REG + (TARGET_SH5 ? (TARGET_SHCOMPACT ? 245 \
2929 : XD_REGISTER_P (REGNO) \
2930 ? ((REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2931 : TARGET_REGISTER_P (REGNO) \
2932 ? ((REGNO) - FIRST_TARGET_REG + 68) \
2933 : (REGNO) == PR_REG \
2934 ? (TARGET_SH5 ? 241 : 17) \
2935 : (REGNO) == T_REG \
2936 ? (TARGET_SH5 ? 242 : 18) \
2937 : (REGNO) == GBR_REG \
2938 ? (TARGET_SH5 ? 238 : 19) \
2939 : (REGNO) == MACH_REG \
2940 ? (TARGET_SH5 ? 239 : 20) \
2941 : (REGNO) == MACL_REG \
2942 ? (TARGET_SH5 ? 240 : 21) \
2943 : (REGNO) == FPUL_REG \
2944 ? (TARGET_SH5 ? 244 : 23) \
2947 /* This is how to output a reference to a user-level label named NAME. */
2948 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2953 STRIP_DATALABEL_ENCODING (lname, (NAME)); \
2954 if (lname[0] == '*') \
2955 fputs (lname + 1, (FILE)); \
2957 asm_fprintf ((FILE), "%U%s", lname); \
2961 /* This is how to output a reference to a symbol_ref. On SH5,
2962 references to non-code symbols must be preceded by `datalabel'. */
2963 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2967 && (DATALABEL_SYMNAME_P (XSTR ((SYM), 0)) \
2968 || CONSTANT_POOL_ADDRESS_P (SYM))) \
2969 fputs ("datalabel ", (FILE)); \
2970 assemble_name ((FILE), XSTR ((SYM), 0)); \
2974 /* Output a label definition. */
2975 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2976 do { assemble_name ((FILE), (NAME)); fputs (":\n", (FILE)); } while (0)
2978 /* This is how to output an assembler line
2979 that says to advance the location counter
2980 to a multiple of 2**LOG bytes. */
2982 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2984 fprintf ((FILE), "\t.align %d\n", (LOG))
2986 /* Output a globalising directive for a label. */
2987 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
2988 (fprintf ((STREAM), "\t.global\t"), \
2989 assemble_name ((STREAM), (NAME)), \
2990 fputc ('\n', (STREAM)))
2992 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2994 /* Construct a private name. */
2995 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
2996 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
2997 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
2999 /* Output a relative address table. */
3001 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3002 switch (GET_MODE (BODY)) \
3007 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3011 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3016 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3020 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3025 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3029 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3035 /* Output an absolute table element. */
3037 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3038 if (TARGET_BIGTABLE) \
3039 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3041 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3044 /* A C statement to be executed just prior to the output of
3045 assembler code for INSN, to modify the extracted operands so
3046 they will be output differently.
3048 Here the argument OPVEC is the vector containing the operands
3049 extracted from INSN, and NOPERANDS is the number of elements of
3050 the vector which contain meaningful data for this insn.
3051 The contents of this vector are what will be used to convert the insn
3052 template into assembler code, so you can change the assembler output
3053 by changing the contents of the vector. */
3055 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3056 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3058 /* Print operand X (an rtx) in assembler syntax to file FILE.
3059 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3060 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3062 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3064 /* Print a memory address as an operand to reference that memory location. */
3066 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3068 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3069 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3072 /* Recognize machine-specific patterns that may appear within
3073 constants. Used for PIC-specific UNSPECs. */
3074 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3076 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3078 switch (XINT ((X), 1)) \
3080 case UNSPEC_DATALABEL: \
3081 fputs ("datalabel ", (STREAM)); \
3082 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3085 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3086 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3089 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3090 fputs ("@GOT", (STREAM)); \
3092 case UNSPEC_GOTOFF: \
3093 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3094 fputs ("@GOTOFF", (STREAM)); \
3097 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3098 fputs ("@PLT", (STREAM)); \
3100 case UNSPEC_GOTPLT: \
3101 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3102 fputs ("@GOTPLT", (STREAM)); \
3104 case UNSPEC_CALLER: \
3107 /* LPCS stands for Label for PIC Call Site. */ \
3108 ASM_GENERATE_INTERNAL_LABEL \
3109 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3110 assemble_name ((STREAM), name); \
3123 extern struct rtx_def *sh_compare_op0;
3124 extern struct rtx_def *sh_compare_op1;
3126 /* Which processor to schedule for. The elements of the enumeration must
3127 match exactly the cpu attribute in the sh.md file. */
3129 enum processor_type {
3138 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3139 extern enum processor_type sh_cpu;
3141 extern int optimize; /* needed for gen_casesi. */
3143 enum mdep_reorg_phase_e
3145 SH_BEFORE_MDEP_REORG,
3146 SH_INSERT_USES_LABELS,
3147 SH_SHORTEN_BRANCHES0,
3149 SH_SHORTEN_BRANCHES1,
3153 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3155 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
3157 /* Generate calls to memcpy, memcmp and memset. */
3159 #define TARGET_MEM_FUNCTIONS
3161 /* Handle Hitachi compiler's pragmas. */
3162 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
3163 cpp_register_pragma (PFILE, 0, "interrupt", sh_pr_interrupt); \
3164 cpp_register_pragma (PFILE, 0, "trapa", sh_pr_trapa); \
3165 cpp_register_pragma (PFILE, 0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3168 /* Set when processing a function with pragma interrupt turned on. */
3170 extern int pragma_interrupt;
3172 /* Set when processing a function with interrupt attribute. */
3174 extern int current_function_interrupt;
3176 /* Set to an RTX containing the address of the stack to switch to
3177 for interrupt functions. */
3178 extern struct rtx_def *sp_switch;
3180 extern int rtx_equal_function_value_matters;
3181 extern struct rtx_def *fpscr_rtx;
3184 /* Instructions with unfilled delay slots take up an
3185 extra two bytes for the nop in the delay slot.
3186 sh-dsp parallel processing insns are four bytes long. */
3188 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3189 (LENGTH) += sh_insn_length_adjustment (X);
3191 /* Define the codes that are matched by predicates in sh.c. */
3192 #define PREDICATE_CODES \
3193 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3194 {"arith_reg_operand", {SUBREG, REG}}, \
3195 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
3196 {"binary_float_operator", {PLUS, MULT}}, \
3197 {"commutative_float_operator", {PLUS, MULT}}, \
3198 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3199 {"fpscr_operand", {REG}}, \
3200 {"fpul_operand", {REG}}, \
3201 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3202 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3203 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3204 {"noncommutative_float_operator", {MINUS, DIV}}, \
3205 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3206 {"target_reg_operand", {SUBREG, REG}}, \
3207 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF}}, \
3208 {"register_operand", {SUBREG, REG}}, \
3209 {"symbol_ref_operand", {SYMBOL_REF}},
3211 /* Define this macro if it is advisable to hold scalars in registers
3212 in a wider mode than that declared by the program. In such cases,
3213 the value is constrained to be within the bounds of the declared
3214 type, but kept valid in the wider mode. The signedness of the
3215 extension may differ from that of the type.
3217 Leaving the unsignedp unchanged gives better code than always setting it
3218 to 0. This is despite the fact that we have only signed char and short
3219 load instructions. */
3220 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3221 if (GET_MODE_CLASS (MODE) == MODE_INT \
3222 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3223 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3224 (MODE) = (TARGET_SH1 ? SImode : DImode);
3226 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
3227 extensions applied to char/short functions arguments. Defining
3228 PROMOTE_FUNCTION_RETURN does the same for function returns. */
3230 #define PROMOTE_FUNCTION_ARGS
3231 #define PROMOTE_FUNCTION_RETURN
3233 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3234 and poping arguments. However, we do have push/pop instructions, and
3235 rather limited offsets (4 bits) in load/store instructions, so it isn't
3236 clear if this would give better code. If implemented, should check for
3237 compatibility problems. */
3239 #define SH_DYNAMIC_SHIFT_COST \
3240 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3243 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3245 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3247 #define NORMAL_MODE(ENTITY) \
3248 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3250 #define EPILOGUE_USES(REGNO) ((TARGET_SH3E || TARGET_SH4) \
3251 && (REGNO) == FPSCR_REG)
3253 #define MODE_NEEDED(ENTITY, INSN) \
3254 (recog_memoized (INSN) >= 0 \
3255 ? get_attr_fp_mode (INSN) \
3258 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3259 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3261 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3262 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3264 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3265 sh_can_redirect_branch ((INSN), (SEQ))
3267 #define DWARF_FRAME_RETURN_COLUMN (TARGET_SH5 ? PR_MEDIA_REG : PR_REG)
3269 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3270 /* SH constant pool breaks the devices in crtstuff.c to control section
3271 in where code resides. We have to write it as asm code. */
3272 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3273 asm (SECTION_OP "\n\
3279 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3280 2:\n" TEXT_SECTION_ASM_OP);
3281 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3283 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3284 (REGNO (hard_reg) == (TARGET_SH5 ? PR_MEDIA_REG : PR_REG) \
3285 ? (current_function_is_leaf && ! sh_pr_n_sets () \
3287 : gen_rtx_MEM (Pmode, TARGET_SH5 \
3288 ? (plus_constant (arg_pointer_rtx, \
3289 TARGET_SHMEDIA64 ? -8 : -4)) \
3290 : frame_pointer_rtx)) \
3293 #endif /* ! GCC_SH_H */
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