1 /* Definitions of target machine for GNU compiler for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
25 #define TARGET_VERSION \
26 fputs (" (Hitachi SH)", stderr);
28 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
29 include it here, because hconfig.h is also included by gencodes.c . */
30 extern int code_for_indirect_jump_scratch;
32 /* Generate SDB debugging information. */
34 #define SDB_DEBUGGING_INFO
36 /* Output DBX (stabs) debugging information if doing -gstabs. */
42 #define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__} \
47 %{m4-single-only:-D__SH4_SINGLE_ONLY__} \
48 %{m4-single:-D__SH4_SINGLE__} \
50 %{!m1:%{!m2:%{!m3:%{!m3e:%{!m4:%{!m4-single:%{!m4-single-only:-D__sh1__}}}}}}} \
51 %{mhitachi:-D__HITACHI__}"
53 #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
55 #define ASM_SPEC "%{ml:-little} %{mrelax:-relax}"
57 #define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}"
59 /* We can not debug without a frame pointer. */
60 /* #define CAN_DEBUG_WITHOUT_FP */
62 #define CONDITIONAL_REGISTER_USAGE \
63 if (! TARGET_SH4 || ! TARGET_FMOVD) \
66 for (regno = FIRST_XD_REG; regno <= LAST_XD_REG; regno++) \
67 fixed_regs[regno] = call_used_regs[regno] = 1; \
73 for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
74 fixed_regs[regno] = call_used_regs[regno] = 1; \
75 fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1; \
79 /* Hitachi saves and restores mac registers on call. */ \
82 call_used_regs[MACH_REG] = 0; \
83 call_used_regs[MACL_REG] = 0; \
86 /* ??? Need to write documentation for all SH options and add it to the
89 /* Run-time compilation parameters selecting different hardware subsets. */
91 extern int target_flags;
92 #define ISIZE_BIT (1<<1)
93 #define DALIGN_BIT (1<<6)
94 #define SH1_BIT (1<<8)
95 #define SH2_BIT (1<<9)
96 #define SH3_BIT (1<<10)
97 #define SH3E_BIT (1<<11)
98 #define HARD_SH4_BIT (1<<5)
99 #define FPU_SINGLE_BIT (1<<7)
100 #define SH4_BIT (1<<12)
101 #define FMOVD_BIT (1<<4)
102 #define SPACE_BIT (1<<13)
103 #define BIGTABLE_BIT (1<<14)
104 #define RELAX_BIT (1<<15)
105 #define HITACHI_BIT (1<<22)
106 #define PADSTRUCT_BIT (1<<28)
107 #define LITTLE_ENDIAN_BIT (1<<29)
108 #define IEEE_BIT (1<<30)
110 /* Nonzero if we should dump out instruction size info. */
111 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
113 /* Nonzero to align doubles on 64 bit boundaries. */
114 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
116 /* Nonzero if we should generate code using type 1 insns. */
117 #define TARGET_SH1 (target_flags & SH1_BIT)
119 /* Nonzero if we should generate code using type 2 insns. */
120 #define TARGET_SH2 (target_flags & SH2_BIT)
122 /* Nonzero if we should generate code using type 3 insns. */
123 #define TARGET_SH3 (target_flags & SH3_BIT)
125 /* Nonzero if we should generate code using type 3E insns. */
126 #define TARGET_SH3E (target_flags & SH3E_BIT)
128 /* Nonzero if the cache line size is 32. */
129 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT)
131 /* Nonzero if we schedule for a superscalar implementation. */
132 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
134 /* Nonzero if the target has separate instruction and data caches. */
135 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
137 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
138 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
140 /* Nonzero if the default precision of th FPU is single */
141 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
143 /* Nonzero if we should generate code using type 4 insns. */
144 #define TARGET_SH4 (target_flags & SH4_BIT)
146 /* Nonzero if we should generate fmovd. */
147 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
149 /* Nonzero if we respect NANs. */
150 #define TARGET_IEEE (target_flags & IEEE_BIT)
152 /* Nonzero if we should generate smaller code rather than faster code. */
153 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
155 /* Nonzero to use long jump tables. */
156 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
158 /* Nonzero to generate pseudo-ops needed by the assembler and linker
159 to do function call relaxing. */
160 #define TARGET_RELAX (target_flags & RELAX_BIT)
162 /* Nonzero if using Hitachi's calling convention. */
163 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
165 /* Nonzero if padding structures to a multiple of 4 bytes. This is
166 incompatible with Hitachi's compiler, and gives unusual structure layouts
167 which confuse programmers.
168 ??? This option is not useful, but is retained in case there are people
169 who are still relying on it. It may be deleted in the future. */
170 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
172 /* Nonzero if generating code for a little endian SH. */
173 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
175 #define TARGET_SWITCHES \
178 {"3", SH3_BIT|SH2_BIT}, \
179 {"3e", SH3E_BIT|SH3_BIT|SH2_BIT|FPU_SINGLE_BIT}, \
180 {"4-single-only", SH3E_BIT|SH3_BIT|SH2_BIT|SH3E_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT}, \
181 {"4-single", SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT},\
182 {"4", SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT}, \
183 {"b", -LITTLE_ENDIAN_BIT}, \
184 {"bigtable", BIGTABLE_BIT}, \
185 {"dalign", DALIGN_BIT}, \
186 {"fmovd", FMOVD_BIT}, \
187 {"hitachi", HITACHI_BIT}, \
188 {"ieee", IEEE_BIT}, \
189 {"isize", ISIZE_BIT}, \
190 {"l", LITTLE_ENDIAN_BIT}, \
191 {"no-ieee", -IEEE_BIT}, \
192 {"padstruct", PADSTRUCT_BIT}, \
193 {"relax", RELAX_BIT}, \
194 {"space", SPACE_BIT}, \
196 {"", TARGET_DEFAULT} \
199 /* This are meant to be redefined in the host dependent files */
200 #define SUBTARGET_SWITCHES
202 #define TARGET_DEFAULT (0)
204 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
207 flag_omit_frame_pointer = -1; \
209 target_flags |= SPACE_BIT; \
212 #define ASSEMBLER_DIALECT assembler_dialect
214 extern int assembler_dialect;
216 #define OVERRIDE_OPTIONS \
219 assembler_dialect = 0; \
228 assembler_dialect = 1; \
231 if (! TARGET_SH4 || ! TARGET_FMOVD) \
233 /* Prevent usage of explicit register names for variables \
234 for registers not present / not addressable in the \
235 target architecture. */ \
237 for (regno = (TARGET_SH3E) ? 17 : 0; \
238 regno <= 24; regno++) \
239 fp_reg_names[regno][0] = 0; \
241 if (flag_omit_frame_pointer < 0) \
242 /* The debugging information is sufficient, \
243 but gdb doesn't implement this yet */ \
245 flag_omit_frame_pointer \
246 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
247 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
249 flag_omit_frame_pointer = 0; \
251 /* Never run scheduling before reload, since that can \
252 break global alloc, and generates slower code anyway due \
253 to the pressure on R0. */ \
254 flag_schedule_insns = 0; \
257 /* Target machine storage layout. */
259 /* Define to use software floating point emulator for REAL_ARITHMETIC and
260 decimal <-> binary conversion. */
261 #define REAL_ARITHMETIC
263 /* Define this if most significant bit is lowest numbered
264 in instructions that operate on numbered bit-fields. */
266 #define BITS_BIG_ENDIAN 0
268 /* Define this if most significant byte of a word is the lowest numbered. */
269 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
271 /* Define this if most significant word of a multiword number is the lowest
273 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
275 /* Define this to set the endianness to use in libgcc2.c, which can
276 not depend on target_flags. */
277 #if defined(__LITTLE_ENDIAN__)
278 #define LIBGCC2_WORDS_BIG_ENDIAN 0
280 #define LIBGCC2_WORDS_BIG_ENDIAN 1
283 /* Number of bits in an addressable storage unit. */
284 #define BITS_PER_UNIT 8
286 /* Width in bits of a "word", which is the contents of a machine register.
287 Note that this is not necessarily the width of data type `int';
288 if using 16-bit ints on a 68000, this would still be 32.
289 But on a machine with 16-bit registers, this would be 16. */
290 #define BITS_PER_WORD 32
291 #define MAX_BITS_PER_WORD 32
293 /* Width of a word, in units (bytes). */
294 #define UNITS_PER_WORD 4
296 /* Width in bits of a pointer.
297 See also the macro `Pmode' defined below. */
298 #define POINTER_SIZE 32
300 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
301 #define PARM_BOUNDARY 32
303 /* Boundary (in *bits*) on which stack pointer should be aligned. */
304 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
306 /* The log (base 2) of the cache line size, in bytes. Processors prior to
307 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
308 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
309 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
311 /* Allocation boundary (in *bits*) for the code of a function.
312 32 bit alignment is faster, because instructions are always fetched as a
313 pair from a longword boundary. */
314 #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : (1 << CACHE_LOG) * 8)
316 /* Alignment of field after `int : 0' in a structure. */
317 #define EMPTY_FIELD_BOUNDARY 32
319 /* No data type wants to be aligned rounder than this. */
320 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
322 /* The best alignment to use in cases where we have a choice. */
323 #define FASTEST_ALIGNMENT 32
325 /* Make strings word-aligned so strcpy from constants will be faster. */
326 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
327 ((TREE_CODE (EXP) == STRING_CST \
328 && (ALIGN) < FASTEST_ALIGNMENT) \
329 ? FASTEST_ALIGNMENT : (ALIGN))
331 #ifndef MAX_OFILE_ALIGNMENT
332 #define MAX_OFILE_ALIGNMENT 128
335 /* Make arrays of chars word-aligned for the same reasons. */
336 #define DATA_ALIGNMENT(TYPE, ALIGN) \
337 (TREE_CODE (TYPE) == ARRAY_TYPE \
338 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
339 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
341 /* Number of bits which any structure or union's size must be a
342 multiple of. Each structure or union's size is rounded up to a
344 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
346 /* Set this nonzero if move instructions will actually fail to work
347 when given unaligned data. */
348 #define STRICT_ALIGNMENT 1
350 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
351 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
352 barrier_align (LABEL_AFTER_BARRIER)
354 #define LOOP_ALIGN(A_LABEL) \
355 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
356 ? 0 : sh_loop_align (A_LABEL))
358 #define LABEL_ALIGN(A_LABEL) \
360 (PREV_INSN (A_LABEL) \
361 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
362 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
363 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == 1) \
364 /* explicit alignment insn in constant tables. */ \
365 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
368 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
369 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
371 /* The base two logarithm of the known minimum alignment of an insn length. */
372 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
373 (GET_CODE (A_INSN) == INSN \
375 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
379 /* Standard register usage. */
381 /* Register allocation for the Hitachi calling convention:
387 r14 frame pointer/call saved
389 ap arg pointer (doesn't really exist, always eliminated)
390 pr subroutine return address
392 mach multiply/accumulate result, high part
393 macl multiply/accumulate result, low part.
394 fpul fp/int communication register
395 rap return address pointer register
397 fr1..fr3 scratch floating point registers
399 fr12..fr15 call saved floating point registers */
401 /* Number of actual hardware registers.
402 The hardware registers are assigned numbers for the compiler
403 from 0 to just below FIRST_PSEUDO_REGISTER.
404 All registers that the compiler knows about must be given numbers,
405 even those that are not normally considered general registers. */
413 #define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
416 #define FIRST_FP_REG 24
417 #define LAST_FP_REG 39
418 #define FIRST_XD_REG 40
419 #define LAST_XD_REG 47
422 #define FIRST_PSEUDO_REGISTER 49
424 /* 1 for registers that have pervasive standard uses
425 and are not available for the register allocator.
427 Mach register is fixed 'cause it's only 10 bits wide for SH1.
428 It is 32 bits wide for SH2. */
430 #define FIXED_REGISTERS \
446 /* 1 for registers not available across function calls.
447 These must include the FIXED_REGISTERS and also any
448 registers that can be used without being saved.
449 The latter must include the registers where values are returned
450 and the register where structure-value addresses are passed.
451 Aside from that, you can include as many other registers as you like. */
453 #define CALL_USED_REGISTERS \
469 /* Return number of consecutive hard regs needed starting at reg REGNO
470 to hold something of mode MODE.
471 This is ordinarily the length in words of a value of mode MODE
472 but can be less for certain modes in special long registers.
474 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
476 #define HARD_REGNO_NREGS(REGNO, MODE) \
477 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \
478 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
479 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
481 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
482 We can allow any mode in any general register. The special registers
483 only allow SImode. Don't allow any mode in the PR. */
485 /* We cannot hold DCmode values in the XD registers because alter_reg
486 handles subregs of them incorrectly. We could work around this by
487 spacing the XD registers like the DR registers, but this would require
488 additional memory in every compilation to hold larger register vectors.
489 We could hold SFmode / SCmode values in XD registers, but that
490 would require a tertiary reload when reloading from / to memory,
491 and a secondary reload to reload from / to general regs; that
492 seems to be a loosing proposition. */
493 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
494 (SPECIAL_REG (REGNO) ? (MODE) == SImode \
495 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
496 : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG && (MODE) == SFmode \
498 : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG \
499 ? ((MODE) == SFmode \
500 || (TARGET_SH3E && (MODE) == SCmode) \
501 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode) \
502 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
503 : (REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \
505 : (REGNO) == PR_REG ? 0 \
506 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
509 /* Value is 1 if it is a good idea to tie two pseudo registers
510 when one has mode MODE1 and one has mode MODE2.
511 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
512 for any hard reg, then this must be 0 for correct output. */
514 #define MODES_TIEABLE_P(MODE1, MODE2) \
515 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
517 /* Specify the registers used for certain standard purposes.
518 The values of these macros are register numbers. */
520 /* Define this if the program counter is overloaded on a register. */
521 /* #define PC_REGNUM 15*/
523 /* Register to use for pushing function arguments. */
524 #define STACK_POINTER_REGNUM 15
526 /* Base register for access to local variables of the function. */
527 #define FRAME_POINTER_REGNUM 14
529 /* Fake register that holds the address on the stack of the
530 current function's return address. */
531 #define RETURN_ADDRESS_POINTER_REGNUM 23
533 /* Value should be nonzero if functions must have frame pointers.
534 Zero means the frame pointer need not be set up (and parms may be accessed
535 via the stack pointer) in functions that seem suitable. */
537 #define FRAME_POINTER_REQUIRED 0
539 /* Definitions for register eliminations.
541 We have three registers that can be eliminated on the SH. First, the
542 frame pointer register can often be eliminated in favor of the stack
543 pointer register. Secondly, the argument pointer register can always be
544 eliminated; it is replaced with either the stack or frame pointer.
545 Third, there is the return address pointer, which can also be replaced
546 with either the stack or the frame pointer. */
548 /* This is an array of structures. Each structure initializes one pair
549 of eliminable registers. The "from" register number is given first,
550 followed by "to". Eliminations of the same "from" register are listed
551 in order of preference. */
553 /* If you add any registers here that are not actually hard registers,
554 and that have any alternative of elimination that doesn't always
555 apply, you need to amend calc_live_regs to exclude it, because
556 reload spills all eliminable registers where it sees an
557 can_eliminate == 0 entry, thus making them 'live' .
558 If you add any hard registers that can be eliminated in different
559 ways, you have to patch reload to spill them only when all alternatives
560 of elimination fail. */
562 #define ELIMINABLE_REGS \
563 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
564 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
565 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
566 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
567 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
569 /* Given FROM and TO register numbers, say whether this elimination
571 #define CAN_ELIMINATE(FROM, TO) \
572 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
574 /* Define the offset between two registers, one to be eliminated, and the other
575 its replacement, at the start of a routine. */
577 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
578 OFFSET = initial_elimination_offset ((FROM), (TO))
580 /* Base register for access to arguments of the function. */
581 #define ARG_POINTER_REGNUM 16
583 /* Register in which the static-chain is passed to a function. */
584 #define STATIC_CHAIN_REGNUM 13
586 /* The register in which a struct value address is passed. */
588 #define STRUCT_VALUE_REGNUM 2
590 /* If the structure value address is not passed in a register, define
591 `STRUCT_VALUE' as an expression returning an RTX for the place
592 where the address is passed. If it returns 0, the address is
593 passed as an "invisible" first argument. */
595 /*#define STRUCT_VALUE ((rtx)0)*/
597 /* Don't default to pcc-struct-return, because we have already specified
598 exactly how to return structures in the RETURN_IN_MEMORY macro. */
600 #define DEFAULT_PCC_STRUCT_RETURN 0
602 /* Define the classes of registers for register constraints in the
603 machine description. Also define ranges of constants.
605 One of the classes must always be named ALL_REGS and include all hard regs.
606 If there is more than one class, another class must be named NO_REGS
607 and contain no registers.
609 The name GENERAL_REGS must be the name of a class (or an alias for
610 another name such as ALL_REGS). This is the class of registers
611 that is allowed by "g" or "r" in a register constraint.
612 Also, registers outside this class are allocated only when
613 instructions express preferences for them.
615 The classes must be numbered in nondecreasing order; that is,
616 a larger-numbered class must never be contained completely
617 in a smaller-numbered class.
619 For any two classes, it is very desirable that there be another
620 class that represents their union. */
622 /* The SH has two sorts of general registers, R0 and the rest. R0 can
623 be used as the destination of some of the arithmetic ops. There are
624 also some special purpose registers; the T bit register, the
625 Procedure Return Register and the Multiply Accumulate Registers. */
626 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
627 reg_class_subunion. We don't want to have an actual union class
628 of these, because it would only be used when both classes are calculated
629 to give the same cost, but there is only one FPUL register.
630 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
631 applying to the actual instruction alternative considered. E.g., the
632 y/r alternative of movsi_ie is considered to have no more cost that
633 the r/r alternative, which is patently untrue. */
653 #define N_REG_CLASSES (int) LIM_REG_CLASSES
655 /* Give names of register classes as strings for dump file. */
656 #define REG_CLASS_NAMES \
673 /* Define which registers fit in which classes.
674 This is an initializer for a vector of HARD_REG_SET
675 of length N_REG_CLASSES. */
677 #define REG_CLASS_CONTENTS \
679 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
680 { 0x00000001, 0x00000000 }, /* R0_REGS */ \
681 { 0x00020000, 0x00000000 }, /* PR_REGS */ \
682 { 0x00040000, 0x00000000 }, /* T_REGS */ \
683 { 0x00300000, 0x00000000 }, /* MAC_REGS */ \
684 { 0x00400000, 0x00000000 }, /* FPUL_REGS */ \
685 { 0x0081FFFF, 0x00000000 }, /* GENERAL_REGS */ \
686 { 0x01000000, 0x00000000 }, /* FP0_REGS */ \
687 { 0xFF000000, 0x000000FF }, /* FP_REGS */ \
688 { 0xFF000000, 0x0000FFFF }, /* DF_REGS */ \
689 { 0x00000000, 0x00010000 }, /* FPSCR_REGS */ \
690 { 0xFF81FFFF, 0x0000FFFF }, /* GENERAL_FP_REGS */ \
691 { 0xFFFFFFFF, 0x0001FFFF }, /* ALL_REGS */ \
694 /* The same information, inverted:
695 Return the class number of the smallest class containing
696 reg number REGNO. This could be a conditional expression
697 or could index an array. */
699 extern int regno_reg_class[];
700 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
702 /* When defined, the compiler allows registers explicitly used in the
703 rtl to be used as spill registers but prevents the compiler from
704 extending the lifetime of these registers. */
706 #define SMALL_REGISTER_CLASSES 1
708 /* The order in which register should be allocated. */
709 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
710 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
711 spilled or used otherwise, we better have the FP_REGS allocated first. */
712 #define REG_ALLOC_ORDER \
713 { 25,26,27,28,29,30,31,24,32,33,34,35,36,37,38,39, \
714 40,41,42,43,44,45,46,47,48, \
715 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \
716 22,15,16,17,18,19,20,21,23 }
718 /* The class value for index registers, and the one for base regs. */
719 #define INDEX_REG_CLASS R0_REGS
720 #define BASE_REG_CLASS GENERAL_REGS
722 /* Get reg_class from a letter such as appears in the machine
724 extern enum reg_class reg_class_from_letter[];
726 #define REG_CLASS_FROM_LETTER(C) \
727 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
729 /* The letters I, J, K, L and M in a register constraint string
730 can be used to stand for particular ranges of immediate operands.
731 This macro defines what the ranges are.
732 C is the letter, and VALUE is a constant value.
733 Return 1 if VALUE is in the range specified by C.
734 I: arithmetic operand -127..128, as used in add, sub, etc
735 K: shift operand 1,2,8 or 16
736 L: logical operand 0..255, as used in and, or, etc.
740 #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
741 && ((HOST_WIDE_INT)(VALUE)) <= 127)
742 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
743 #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
744 && ((HOST_WIDE_INT)(VALUE)) <= 255)
745 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
746 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
747 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
748 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
749 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
750 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
751 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
752 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
755 /* Similar, but for floating constants, and defining letters G and H.
756 Here VALUE is the CONST_DOUBLE rtx itself. */
758 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
759 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
760 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
763 /* Given an rtx X being reloaded into a reg required to be
764 in class CLASS, return the class of reg to actually use.
765 In general this is just CLASS; but on some machines
766 in some cases it is preferable to use a more restrictive class. */
768 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
770 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
771 ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \
772 || (CLASS) == DF_REGS) \
773 && (GET_CODE (X) == REG && REGNO (X) <= AP_REG)) \
774 || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
775 && GET_CODE (X) == REG \
776 && REGNO (X) >= FIRST_FP_REG && REGNO (X) <= LAST_FP_REG)) \
779 : ((CLASS) == FPUL_REGS \
780 && (GET_CODE (X) == MEM \
781 || (GET_CODE (X) == REG \
782 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
783 || system_reg_operand (X, VOIDmode))))) \
785 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
786 && GET_CODE (X) == REG && REGNO (X) > 15 \
787 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
788 ? GENERAL_REGS : NO_REGS)
790 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
791 ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS) \
792 && immediate_operand ((X), (MODE)) \
793 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
794 && (MODE) == SFmode && fldi_ok ())) \
796 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
797 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \
800 : (CLASS == FPSCR_REGS \
801 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
802 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
804 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
806 /* Return the maximum number of consecutive registers
807 needed to represent mode MODE in a register of class CLASS.
809 On SH this is the size of MODE in words. */
810 #define CLASS_MAX_NREGS(CLASS, MODE) \
811 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
813 /* If defined, gives a class of registers that cannot be used as the
814 operand of a SUBREG that changes the size of the object. */
816 #define CLASS_CANNOT_CHANGE_SIZE DF_REGS
818 /* Stack layout; function entry, exit and calling. */
820 /* Define the number of registers that can hold parameters.
821 These macros are used only in other macro definitions below. */
823 #define NPARM_REGS(MODE) \
824 (TARGET_SH3E && (MODE) == SFmode \
826 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
827 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
831 #define FIRST_PARM_REG 4
832 #define FIRST_RET_REG 0
834 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
835 #define FIRST_FP_RET_REG FIRST_FP_REG
837 /* Define this if pushing a word on the stack
838 makes the stack pointer a smaller address. */
839 #define STACK_GROWS_DOWNWARD
841 /* Define this macro if the addresses of local variable slots are at
842 negative offsets from the frame pointer.
844 The SH only has positive indexes, so grow the frame up. */
845 /* #define FRAME_GROWS_DOWNWARD */
847 /* Offset from the frame pointer to the first local variable slot to
849 #define STARTING_FRAME_OFFSET 0
851 /* If we generate an insn to push BYTES bytes,
852 this says how many the stack pointer really advances by. */
853 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
854 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
855 do correct alignment. */
857 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
860 /* Offset of first parameter from the argument pointer register value. */
861 #define FIRST_PARM_OFFSET(FNDECL) 0
863 /* Value is the number of byte of arguments automatically
864 popped when returning from a subroutine call.
865 FUNDECL is the declaration node of the function (as a tree),
866 FUNTYPE is the data type of the function (as a tree),
867 or for a library call it is an identifier node for the subroutine name.
868 SIZE is the number of bytes of arguments passed on the stack.
870 On the SH, the caller does not pop any of its arguments that were passed
872 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
874 /* Nonzero if we do not know how to pass TYPE solely in registers.
875 Values that come in registers with inconvenient padding are stored
876 to memory at the function start. */
878 #define MUST_PASS_IN_STACK(MODE,TYPE) \
880 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
881 || TREE_ADDRESSABLE (TYPE)))
882 /* Some subroutine macros specific to this machine. */
884 #define BASE_RETURN_VALUE_REG(MODE) \
885 ((TARGET_SH3E && ((MODE) == SFmode)) \
887 : TARGET_SH3E && (MODE) == SCmode \
890 && ((MODE) == DFmode || (MODE) == SFmode \
891 || (MODE) == DCmode || (MODE) == SCmode )) \
895 #define BASE_ARG_REG(MODE) \
896 ((TARGET_SH3E && ((MODE) == SFmode)) \
897 ? FIRST_FP_PARM_REG \
898 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
899 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
900 ? FIRST_FP_PARM_REG \
903 /* Define how to find the value returned by a function.
904 VALTYPE is the data type of the value (as a tree).
905 If the precise function being called is known, FUNC is its FUNCTION_DECL;
906 otherwise, FUNC is 0.
907 For the SH, this is like LIBCALL_VALUE, except that we must change the
908 mode like PROMOTE_MODE does.
909 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
910 tested here has to be kept in sync with the one in explow.c:promote_mode. */
912 #define FUNCTION_VALUE(VALTYPE, FUNC) \
914 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
915 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
916 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
917 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
918 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
919 || TREE_CODE (VALTYPE) == CHAR_TYPE \
920 || TREE_CODE (VALTYPE) == REAL_TYPE \
921 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
922 ? SImode : TYPE_MODE (VALTYPE)), \
923 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
925 /* Define how to find the value returned by a library function
926 assuming the value has mode MODE. */
927 #define LIBCALL_VALUE(MODE) \
928 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
930 /* 1 if N is a possible register number for a function value. */
931 #define FUNCTION_VALUE_REGNO_P(REGNO) \
932 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
934 /* 1 if N is a possible register number for function argument passing. */
935 #define FUNCTION_ARG_REGNO_P(REGNO) \
936 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \
938 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8)))
940 /* Define a data type for recording info about an argument list
941 during the scan of that argument list. This data type should
942 hold all necessary information about the function itself
943 and about the args processed so far, enough to enable macros
944 such as FUNCTION_ARG to determine where the next arg should go.
946 On SH, this is a single integer, which is a number of words
947 of arguments scanned so far (including the invisible argument,
948 if any, which holds the structure-value-address).
949 Thus NARGREGS or more means all following args should go on the stack. */
951 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
956 #define CUMULATIVE_ARGS struct sh_args
958 #define GET_SH_ARG_CLASS(MODE) \
959 ((TARGET_SH3E && (MODE) == SFmode) \
961 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
962 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
963 ? SH_ARG_FLOAT : SH_ARG_INT)
965 #define ROUND_ADVANCE(SIZE) \
966 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
968 /* Round a register number up to a proper boundary for an arg of mode
971 The SH doesn't care about double alignment, so we only
972 round doubles to even regs when asked to explicitly. */
974 #define ROUND_REG(CUM, MODE) \
975 (((TARGET_ALIGN_DOUBLE \
976 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
977 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
978 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
979 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
980 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
981 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
983 /* Initialize a variable CUM of type CUMULATIVE_ARGS
984 for a call to a function whose data type is FNTYPE.
985 For a library call, FNTYPE is 0.
987 On SH, the offset always starts at 0: the first parm reg is always
988 the same reg for a given argument class. */
990 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
992 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
993 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
996 /* Update the data in CUM to advance over an argument
997 of mode MODE and data type TYPE.
998 (TYPE is null for libcalls where that information may not be
1001 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1002 if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
1003 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1004 = (ROUND_REG ((CUM), (MODE)) \
1005 + ((MODE) == BLKmode \
1006 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1007 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
1009 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1010 This macro is only used in this file. */
1012 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1014 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1015 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
1017 ? ((MODE) == BLKmode \
1018 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1019 + int_size_in_bytes (TYPE)) \
1020 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1021 : ((ROUND_REG((CUM), (MODE)) \
1022 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1023 <= NPARM_REGS (MODE))) \
1024 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1026 /* Define where to put the arguments to a function.
1027 Value is zero to push the argument on the stack,
1028 or a hard register in which to store the argument.
1030 MODE is the argument's machine mode.
1031 TYPE is the data type of the argument (as a tree).
1032 This is null for libcalls where that information may
1034 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1035 the preceding args and about the function being called.
1036 NAMED is nonzero if this argument is a named parameter
1037 (otherwise it is an extra parameter matching an ellipsis).
1039 On SH the first args are normally in registers
1040 and the rest are pushed. Any arg that starts within the first
1041 NPARM_REGS words is at least partially passed in a register unless
1042 its data type forbids. */
1044 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1045 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1047 || (! TARGET_HITACHI && (TARGET_SH3E || ! current_function_varargs)))) \
1048 ? gen_rtx_REG ((MODE), \
1049 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
1050 ^ ((MODE) == SFmode && TARGET_SH4 \
1051 && TARGET_LITTLE_ENDIAN != 0))) \
1054 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI)
1056 /* For an arg passed partly in registers and partly in memory,
1057 this is the number of registers used.
1058 For args passed entirely in registers or entirely in memory, zero.
1060 We sometimes split args. */
1062 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1063 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1065 && (ROUND_REG ((CUM), (MODE)) \
1066 + ((MODE) != BLKmode \
1067 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
1068 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
1069 - NPARM_REGS (MODE) > 0)) \
1070 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
1073 extern int current_function_anonymous_args;
1075 /* Perform any needed actions needed for a function that is receiving a
1076 variable number of arguments. */
1078 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
1079 current_function_anonymous_args = 1;
1081 /* Define the `__builtin_va_list' type for the ABI. */
1082 #define BUILD_VA_LIST_TYPE(VALIST) \
1083 (VALIST) = sh_build_va_list ()
1085 /* Implement `va_start' for varargs and stdarg. */
1086 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1087 sh_va_start (stdarg, valist, nextarg)
1089 /* Implement `va_arg'. */
1090 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1091 sh_va_arg (valist, type)
1093 /* Call the function profiler with a given profile label.
1094 We use two .aligns, so as to make sure that both the .long is aligned
1095 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1096 from the trapa instruction. */
1098 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1100 fprintf((STREAM), "\t.align\t2\n"); \
1101 fprintf((STREAM), "\ttrapa\t#33\n"); \
1102 fprintf((STREAM), "\t.align\t2\n"); \
1103 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1106 /* Define this macro if the code for function profiling should come
1107 before the function prologue. Normally, the profiling code comes
1110 #define PROFILE_BEFORE_PROLOGUE
1112 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1113 the stack pointer does not matter. The value is tested only in
1114 functions that have frame pointers.
1115 No definition is equivalent to always zero. */
1117 #define EXIT_IGNORE_STACK 1
1119 /* Generate the assembly code for function exit
1120 Just dump out any accumulated constant table. */
1122 #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue ((STREAM), (SIZE))
1125 On the SH, the trampoline looks like
1126 2 0002 DD02 mov.l l2,r13
1127 1 0000 D301 mov.l l1,r3
1128 3 0004 4D2B jmp @r13
1130 5 0008 00000000 l1: .long function
1131 6 000c 00000000 l2: .long area */
1133 /* Length in units of the trampoline for entering a nested function. */
1134 #define TRAMPOLINE_SIZE 16
1136 /* Alignment required for a trampoline in bits . */
1137 #define TRAMPOLINE_ALIGNMENT \
1138 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 : 64)
1140 /* Emit RTL insns to initialize the variable parts of a trampoline.
1141 FNADDR is an RTX for the address of the function's pure code.
1142 CXT is an RTX for the static chain value for the function. */
1144 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1146 emit_move_insn (gen_rtx_MEM (SImode, (TRAMP)), \
1147 GEN_INT (TARGET_LITTLE_ENDIAN ? 0xd301dd02 : 0xdd02d301));\
1148 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 4)), \
1149 GEN_INT (TARGET_LITTLE_ENDIAN ? 0x00094d2b : 0x4d2b0009));\
1150 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1152 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1154 if (TARGET_HARVARD) \
1155 emit_insn (gen_ic_invalidate_line (TRAMP)); \
1158 /* A C expression whose value is RTL representing the value of the return
1159 address for the frame COUNT steps up from the current frame.
1160 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1161 can ignore COUNT. */
1163 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1165 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)) \
1168 /* Generate necessary RTL for __builtin_saveregs(). */
1169 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
1171 /* Addressing modes, and classification of registers for them. */
1172 #define HAVE_POST_INCREMENT 1
1173 /*#define HAVE_PRE_INCREMENT 1*/
1174 /*#define HAVE_POST_DECREMENT 1*/
1175 #define HAVE_PRE_DECREMENT 1
1177 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1179 #define USE_LOAD_PRE_DECREMENT(mode) 0
1180 #define USE_STORE_POST_INCREMENT(mode) 0
1181 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1184 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
1185 < (TARGET_SMALLCODE ? 2 : \
1186 ((ALIGN >= 4) ? 16 : 2)))
1188 /* Macros to check register numbers against specific register classes. */
1190 /* These assume that REGNO is a hard or pseudo reg number.
1191 They give nonzero only if REGNO is a hard reg of the suitable class
1192 or a pseudo reg currently allocated to a suitable hard reg.
1193 Since they use reg_renumber, they are safe only once reg_renumber
1194 has been allocated, which happens in local-alloc.c. */
1196 #define REGNO_OK_FOR_BASE_P(REGNO) \
1197 ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
1198 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1199 ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
1201 /* Maximum number of registers that can appear in a valid memory
1204 #define MAX_REGS_PER_ADDRESS 2
1206 /* Recognize any constant value that is a valid address. */
1208 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1210 /* Nonzero if the constant value X is a legitimate general operand. */
1212 #define LEGITIMATE_CONSTANT_P(X) \
1213 (GET_CODE (X) != CONST_DOUBLE \
1214 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
1215 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))
1217 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1218 and check its validity for a certain class.
1219 We have two alternate definitions for each of them.
1220 The usual definition accepts all pseudo regs; the other rejects
1221 them unless they have been allocated suitable hard regs.
1222 The symbol REG_OK_STRICT causes the latter definition to be used. */
1224 #ifndef REG_OK_STRICT
1226 /* Nonzero if X is a hard reg that can be used as a base reg
1227 or if it is a pseudo reg. */
1228 #define REG_OK_FOR_BASE_P(X) \
1229 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1231 /* Nonzero if X is a hard reg that can be used as an index
1232 or if it is a pseudo reg. */
1233 #define REG_OK_FOR_INDEX_P(X) \
1234 (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1236 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
1237 or if X is a pseudo reg. */
1238 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
1239 ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1243 /* Nonzero if X is a hard reg that can be used as a base reg. */
1244 #define REG_OK_FOR_BASE_P(X) \
1245 REGNO_OK_FOR_BASE_P (REGNO (X))
1247 /* Nonzero if X is a hard reg that can be used as an index. */
1248 #define REG_OK_FOR_INDEX_P(X) \
1249 REGNO_OK_FOR_INDEX_P (REGNO (X))
1251 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
1252 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
1253 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
1257 /* The 'Q' constraint is a pc relative load operand. */
1258 #define EXTRA_CONSTRAINT_Q(OP) \
1259 (GET_CODE (OP) == MEM && \
1260 ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
1261 || (GET_CODE (XEXP ((OP), 0)) == CONST \
1262 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
1263 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
1264 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
1266 #define EXTRA_CONSTRAINT(OP, C) \
1267 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
1270 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1271 that is a valid memory address for an instruction.
1272 The MODE argument is the machine mode for the MEM expression
1273 that wants to use this address. */
1275 #define MODE_DISP_OK_4(X,MODE) \
1276 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
1277 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
1279 #define MODE_DISP_OK_8(X,MODE) \
1280 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
1281 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
1283 #define BASE_REGISTER_RTX_P(X) \
1284 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1285 || (GET_CODE (X) == SUBREG \
1286 && GET_CODE (SUBREG_REG (X)) == REG \
1287 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1289 /* Since this must be r0, which is a single register class, we must check
1290 SUBREGs more carefully, to be sure that we don't accept one that extends
1291 outside the class. */
1292 #define INDEX_REGISTER_RTX_P(X) \
1293 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1294 || (GET_CODE (X) == SUBREG \
1295 && GET_CODE (SUBREG_REG (X)) == REG \
1296 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X))))
1298 /* Jump to LABEL if X is a valid address RTX. This must also take
1299 REG_OK_STRICT into account when deciding about valid registers, but it uses
1300 the above macros so we are in luck.
1308 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
1309 into the FRx registers. We implement this by setting the maximum offset
1310 to zero when the value is SFmode. This also restricts loading of SFmode
1311 values into the integer registers, but that can't be helped. */
1313 /* The SH allows a displacement in a QI or HI amode, but only when the
1314 other operand is R0. GCC doesn't handle this very well, so we forgo
1317 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
1318 DI can be any number 0..60. */
1320 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
1322 if (GET_CODE (OP) == CONST_INT) \
1324 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
1325 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
1329 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1331 if (BASE_REGISTER_RTX_P (X)) \
1333 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1334 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
1336 else if (GET_CODE (X) == PLUS \
1337 && ((MODE) != PSImode || reload_completed)) \
1339 rtx xop0 = XEXP ((X), 0); \
1340 rtx xop1 = XEXP ((X), 1); \
1341 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
1342 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
1343 if (GET_MODE_SIZE (MODE) <= 4 \
1344 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
1346 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
1348 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
1354 /* Try machine-dependent ways of modifying an illegitimate address
1355 to be legitimate. If we find one, return the new, valid address.
1356 This macro is used in only one place: `memory_address' in explow.c.
1358 OLDX is the address as it was before break_out_memory_refs was called.
1359 In some cases it is useful to look at this to decide what needs to be done.
1361 MODE and WIN are passed so that this macro can use
1362 GO_IF_LEGITIMATE_ADDRESS.
1364 It is always safe for this macro to do nothing. It exists to recognize
1365 opportunities to optimize the output.
1367 For the SH, if X is almost suitable for indexing, but the offset is
1368 out of range, convert it into a normal form so that cse has a chance
1369 of reducing the number of address registers used. */
1371 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1373 if (GET_CODE (X) == PLUS \
1374 && (GET_MODE_SIZE (MODE) == 4 \
1375 || GET_MODE_SIZE (MODE) == 8) \
1376 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
1377 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
1378 && ! (TARGET_SH4 && (MODE) == DFmode) \
1379 && ! (TARGET_SH3E && (MODE) == SFmode)) \
1381 rtx index_rtx = XEXP ((X), 1); \
1382 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1385 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
1386 /* On rare occasions, we might get an unaligned pointer \
1387 that is indexed in a way to give an aligned address. \
1388 Therefore, keep the lower two bits in offset_base. */ \
1389 /* Instead of offset_base 128..131 use 124..127, so that \
1390 simple add suffices. */ \
1393 offset_base = ((offset + 4) & ~60) - 4; \
1396 offset_base = offset & ~60; \
1397 /* Sometimes the normal form does not suit DImode. We \
1398 could avoid that by using smaller ranges, but that \
1399 would give less optimized code when SImode is \
1401 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1403 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
1404 GEN_INT (offset_base), NULL_RTX, 0, \
1407 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
1413 /* A C compound statement that attempts to replace X, which is an address
1414 that needs reloading, with a valid memory address for an operand of
1415 mode MODE. WIN is a C statement label elsewhere in the code.
1417 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
1418 of the address. That will allow inheritance of the address reloads. */
1420 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1422 if (GET_CODE (X) == PLUS \
1423 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
1424 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1425 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1426 && ! (TARGET_SH4 && (MODE) == DFmode) \
1427 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
1429 rtx index_rtx = XEXP (X, 1); \
1430 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1433 if (TARGET_SH3E && MODE == SFmode) \
1436 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL_PTR, \
1437 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
1441 /* Instead of offset_base 128..131 use 124..127, so that \
1442 simple add suffices. */ \
1445 offset_base = ((offset + 4) & ~60) - 4; \
1448 offset_base = offset & ~60; \
1449 /* Sometimes the normal form does not suit DImode. We \
1450 could avoid that by using smaller ranges, but that \
1451 would give less optimized code when SImode is \
1453 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1455 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1456 GEN_INT (offset_base)); \
1457 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
1458 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1459 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
1464 /* We must re-recognize what we created before. */ \
1465 else if (GET_CODE (X) == PLUS \
1466 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
1467 && GET_CODE (XEXP (X, 0)) == PLUS \
1468 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1469 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
1470 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1471 && ! (TARGET_SH3E && MODE == SFmode)) \
1473 /* Because this address is so complex, we know it must have \
1474 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
1475 it is already unshared, and needs no further unsharing. */ \
1476 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL_PTR, \
1477 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
1482 /* Go to LABEL if ADDR (a legitimate address expression)
1483 has an effect that depends on the machine mode it is used for.
1485 ??? Strictly speaking, we should also include all indexed addressing,
1486 because the index scale factor is the length of the operand.
1487 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
1488 high if we did that. So we rely on reload to fix things up. */
1490 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1492 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
1496 /* Specify the machine mode that this machine uses
1497 for the index in the tablejump instruction. */
1498 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
1500 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1501 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1502 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1503 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1504 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1505 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1508 /* Define as C expression which evaluates to nonzero if the tablejump
1509 instruction expects the table to contain offsets from the address of the
1511 Do not define this if the table should contain absolute addresses. */
1512 #define CASE_VECTOR_PC_RELATIVE 1
1514 /* Specify the tree operation to be used to convert reals to integers. */
1515 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1517 /* This is the kind of divide that is easiest to do in the general case. */
1518 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1520 /* Since the SH3e has only `float' support, it is desirable to make all
1521 floating point types equivalent to `float'. */
1522 #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
1524 /* 'char' is signed by default. */
1525 #define DEFAULT_SIGNED_CHAR 1
1527 /* The type of size_t unsigned int. */
1528 #define SIZE_TYPE "unsigned int"
1530 #define WCHAR_TYPE "short unsigned int"
1531 #define WCHAR_TYPE_SIZE 16
1533 /* Don't cse the address of the function being compiled. */
1534 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
1536 /* Max number of bytes we can move from memory to memory
1537 in one reasonably fast instruction. */
1540 /* Max number of bytes we want move_by_pieces to be able to copy
1542 #define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4)
1544 /* Define if operations between registers always perform the operation
1545 on the full register even if a narrower mode is specified. */
1546 #define WORD_REGISTER_OPERATIONS
1548 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1549 will either zero-extend or sign-extend. The value of this macro should
1550 be the code that says which one of the two operations is implicitly
1551 done, NIL if none. */
1552 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1554 /* Define if loading short immediate values into registers sign extends. */
1555 #define SHORT_IMMEDIATES_SIGN_EXTEND
1557 /* Define this if zero-extension is slow (more than one real instruction).
1558 On the SH, it's only one instruction. */
1559 /* #define SLOW_ZERO_EXTEND */
1561 /* Nonzero if access to memory by bytes is no faster than for words. */
1562 #define SLOW_BYTE_ACCESS 1
1564 /* Force sizeof(bool) == 1 to maintain binary compatibility; otherwise, the
1565 change in SLOW_BYTE_ACCESS would have changed it to 4. */
1567 /* This used to use INT_TYPE_SIZE / CHAR_TYPE_SIZE, but these are
1568 not guaranteed to be defined when BOOL_TYPE_SIZE is used. */
1569 #define BOOL_TYPE_SIZE (flag_new_abi ? BITS_PER_WORD : BITS_PER_UNIT)
1571 /* We assume that the store-condition-codes instructions store 0 for false
1572 and some other value for true. This is the value stored for true. */
1574 #define STORE_FLAG_VALUE 1
1576 /* Immediate shift counts are truncated by the output routines (or was it
1577 the assembler?). Shift counts in a register are truncated by SH. Note
1578 that the native compiler puts too large (> 32) immediate shift counts
1579 into a register and shifts by the register, letting the SH decide what
1580 to do instead of doing that itself. */
1581 /* ??? The library routines in lib1funcs.asm truncate the shift count.
1582 However, the SH3 has hardware shifts that do not truncate exactly as gcc
1583 expects - the sign bit is significant - so it appears that we need to
1584 leave this zero for correct SH3 code. */
1585 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
1587 /* All integers have the same format so truncation is easy. */
1588 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1590 /* Define this if addresses of constant functions
1591 shouldn't be put through pseudo regs where they can be cse'd.
1592 Desirable on machines where ordinary constants are expensive
1593 but a CALL with constant address is cheap. */
1594 /*#define NO_FUNCTION_CSE 1*/
1596 /* Chars and shorts should be passed as ints. */
1597 #define PROMOTE_PROTOTYPES 1
1599 /* The machine modes of pointers and functions. */
1600 #define Pmode SImode
1601 #define FUNCTION_MODE Pmode
1603 /* The relative costs of various types of constants. Note that cse.c defines
1604 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1606 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1608 if (INTVAL (RTX) == 0) \
1610 else if (CONST_OK_FOR_I (INTVAL (RTX))) \
1612 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \
1613 && CONST_OK_FOR_L (INTVAL (RTX))) \
1621 case CONST_DOUBLE: \
1624 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1626 return (COSTS_N_INSNS (1) \
1627 + rtx_cost (XEXP ((X), 0), PLUS) \
1628 + (rtx_equal_p (XEXP ((X), 0), XEXP ((X), 1))\
1629 ? 0 : rtx_cost (XEXP ((X), 1), PLUS)));\
1631 return COSTS_N_INSNS (andcosts (X)); \
1633 return COSTS_N_INSNS (multcosts (X)); \
1637 /* Add one extra unit for the matching constraint. \
1638 Otherwise loop strength reduction would think that\
1639 a shift with different sourc and destination is \
1640 as cheap as adding a constant to a register. */ \
1641 return (COSTS_N_INSNS (shiftcosts (X)) \
1642 + rtx_cost (XEXP ((X), 0), (CODE)) \
1648 return COSTS_N_INSNS (20); \
1653 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1654 are actually function calls with some special constraints on arguments
1657 These macros tell reorg that the references to arguments and
1658 register clobbers for insns of type sfunc do not appear to happen
1659 until after the millicode call. This allows reorg to put insns
1660 which set the argument registers into the delay slot of the millicode
1661 call -- thus they act more like traditional CALL_INSNs.
1663 get_attr_is_sfunc will try to recognize the given insn, so make sure to
1664 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1667 #define INSN_SETS_ARE_DELAYED(X) \
1668 ((GET_CODE (X) == INSN \
1669 && GET_CODE (PATTERN (X)) != SEQUENCE \
1670 && GET_CODE (PATTERN (X)) != USE \
1671 && GET_CODE (PATTERN (X)) != CLOBBER \
1672 && get_attr_is_sfunc (X)))
1674 #define INSN_REFERENCES_ARE_DELAYED(X) \
1675 ((GET_CODE (X) == INSN \
1676 && GET_CODE (PATTERN (X)) != SEQUENCE \
1677 && GET_CODE (PATTERN (X)) != USE \
1678 && GET_CODE (PATTERN (X)) != CLOBBER \
1679 && get_attr_is_sfunc (X)))
1681 /* Compute the cost of an address. For the SH, all valid addresses are
1683 /* ??? Perhaps we should make reg+reg addresses have higher cost because
1684 they add to register pressure on r0. */
1686 #define ADDRESS_COST(RTX) 1
1688 /* Compute extra cost of moving data between one register class
1691 /* Regclass always uses 2 for moves in the same register class;
1692 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
1693 it uses this information. Hence, the general register <-> floating point
1694 register information here is not used for SFmode. */
1695 #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
1696 ((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
1697 : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS || (DSTCLASS) == DF_REGS) \
1698 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
1699 || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \
1700 && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
1701 || (SRCCLASS) == DF_REGS))) \
1702 ? TARGET_FMOVD ? 8 : 12 \
1703 : (((DSTCLASS) == FPUL_REGS \
1704 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
1705 || (SRCCLASS == FPUL_REGS \
1706 && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \
1708 : (((DSTCLASS) == FPUL_REGS \
1709 && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
1710 || (SRCCLASS) == T_REGS)) \
1711 || ((SRCCLASS) == FPUL_REGS \
1712 && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
1716 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1717 would be so that people with slow memory systems could generate
1718 different code that does fewer memory accesses. */
1720 /* A C expression for the cost of a branch instruction. A value of 1
1721 is the default; other values are interpreted relative to that.
1722 The SH1 does not have delay slots, hence we get a pipeline stall
1723 at every branch. The SH4 is superscalar, so the single delay slot
1724 is not sufficient to keep both pipelines filled. */
1725 #define BRANCH_COST (! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
1727 /* Assembler output control. */
1729 /* A C string constant describing how to begin a comment in the target
1730 assembler language. The compiler assumes that the comment will end at
1731 the end of the line. */
1732 #define ASM_COMMENT_START "!"
1734 /* The text to go at the start of the assembler file. */
1735 #define ASM_FILE_START(STREAM) \
1736 output_file_start (STREAM)
1738 #define ASM_FILE_END(STREAM)
1740 #define ASM_APP_ON ""
1741 #define ASM_APP_OFF ""
1742 #define FILE_ASM_OP "\t.file\n"
1743 #define IDENT_ASM_OP "\t.ident\n"
1744 #define SET_ASM_OP ".set"
1746 /* How to change between sections. */
1748 #define TEXT_SECTION_ASM_OP "\t.text"
1749 #define DATA_SECTION_ASM_OP "\t.data"
1750 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
1751 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
1752 #define EXTRA_SECTIONS in_ctors, in_dtors
1753 #define EXTRA_SECTION_FUNCTIONS \
1757 if (in_section != in_ctors) \
1759 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1760 in_section = in_ctors; \
1766 if (in_section != in_dtors) \
1768 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1769 in_section = in_dtors; \
1773 /* If defined, a C expression whose value is a string containing the
1774 assembler operation to identify the following data as
1775 uninitialized global data. If not defined, and neither
1776 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
1777 uninitialized global data will be output in the data section if
1778 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
1780 #ifndef BSS_SECTION_ASM_OP
1781 #define BSS_SECTION_ASM_OP ".section\t.bss"
1784 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
1785 separate, explicit argument. If you define this macro, it is used
1786 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
1787 handling the required alignment of the variable. The alignment is
1788 specified as the number of bits.
1790 Try to use function `asm_output_aligned_bss' defined in file
1791 `varasm.c' when defining this macro. */
1792 #ifndef ASM_OUTPUT_ALIGNED_BSS
1793 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1794 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1797 /* Define this so that jump tables go in same section as the current function,
1798 which could be text or it could be a user defined section. */
1799 #define JUMP_TABLES_IN_TEXT_SECTION 1
1801 /* A C statement to output something to the assembler file to switch to section
1802 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
1803 NULL_TREE. Some target formats do not support arbitrary sections. Do not
1804 define this macro in such cases. */
1806 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
1807 do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
1809 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1810 do { ctors_section(); asm_fprintf((FILE),"\t.long\t%U%s\n", (NAME)); } while (0)
1812 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1813 do { dtors_section(); asm_fprintf((FILE),"\t.long\t%U%s\n", (NAME)); } while (0)
1815 #undef DO_GLOBAL_CTORS_BODY
1817 #define DO_GLOBAL_CTORS_BODY \
1819 typedef (*pfunc)(); \
1820 extern pfunc __ctors[]; \
1821 extern pfunc __ctors_end[]; \
1823 for (p = __ctors_end; p > __ctors; ) \
1829 #undef DO_GLOBAL_DTORS_BODY
1830 #define DO_GLOBAL_DTORS_BODY \
1832 typedef (*pfunc)(); \
1833 extern pfunc __dtors[]; \
1834 extern pfunc __dtors_end[]; \
1836 for (p = __dtors; p < __dtors_end; p++) \
1842 #define ASM_OUTPUT_REG_PUSH(file, v) \
1843 fprintf ((file), "\tmov.l\tr%d,-@r15\n", (v));
1845 #define ASM_OUTPUT_REG_POP(file, v) \
1846 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
1848 /* The assembler's names for the registers. RFP need not always be used as
1849 the Real framepointer; it can also be used as a normal general register.
1850 Note that the name `fp' is horribly misleading since `fp' is in fact only
1851 the argument-and-return-context pointer. */
1853 extern char fp_reg_names[][5];
1855 #define REGISTER_NAMES \
1857 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1858 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1859 "ap", "pr", "t", "gbr", "mach","macl", fp_reg_names[16], "rap", \
1860 fp_reg_names[0], fp_reg_names[1] , fp_reg_names[2], fp_reg_names[3], \
1861 fp_reg_names[4], fp_reg_names[5], fp_reg_names[6], fp_reg_names[7], \
1862 fp_reg_names[8], fp_reg_names[9], fp_reg_names[10], fp_reg_names[11], \
1863 fp_reg_names[12], fp_reg_names[13], fp_reg_names[14], fp_reg_names[15], \
1864 fp_reg_names[17], fp_reg_names[18], fp_reg_names[19], fp_reg_names[20], \
1865 fp_reg_names[21], fp_reg_names[22], fp_reg_names[23], fp_reg_names[24], \
1869 #define DEBUG_REGISTER_NAMES \
1871 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1872 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1873 "ap", "pr", "t", "gbr", "mach","macl", "fpul","rap", \
1874 "fr0","fr1","fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1875 "fr8","fr9","fr10","fr11","fr12","fr13","fr14","fr15",\
1876 "xd0","xd2","xd4", "xd6", "xd8", "xd10","xd12","xd14", \
1880 /* DBX register number for a given compiler register number. */
1881 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
1883 #define DBX_REGISTER_NUMBER(REGNO) \
1884 (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO))
1886 /* Output a label definition. */
1887 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1888 do { assemble_name ((FILE), (NAME)); fputs (":\n", (FILE)); } while (0)
1890 /* This is how to output an assembler line
1891 that says to advance the location counter
1892 to a multiple of 2**LOG bytes. */
1894 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1896 fprintf ((FILE), "\t.align %d\n", (LOG))
1898 /* Output a function label definition. */
1899 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1900 ASM_OUTPUT_LABEL((STREAM), (NAME))
1902 /* Output a globalising directive for a label. */
1903 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1904 (fprintf ((STREAM), "\t.global\t"), \
1905 assemble_name ((STREAM), (NAME)), \
1906 fputc ('\n', (STREAM)))
1908 /* The prefix to add to user-visible assembler symbols. */
1910 #define USER_LABEL_PREFIX "_"
1912 /* The prefix to add to an internally generated label. */
1914 #define LOCAL_LABEL_PREFIX ""
1916 /* Make an internal label into a string. */
1917 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1918 sprintf ((STRING), "*%s%s%ld", LOCAL_LABEL_PREFIX, (PREFIX), (long)(NUM))
1920 /* Output an internal label definition. */
1921 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1922 asm_fprintf ((FILE), "%L%s%d:\n", (PREFIX), (NUM))
1924 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1926 /* Construct a private name. */
1927 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1928 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1929 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1931 /* Output a relative address table. */
1933 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1934 switch (GET_MODE (BODY)) \
1937 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1940 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1943 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1949 /* Output an absolute table element. */
1951 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1952 if (TARGET_BIGTABLE) \
1953 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
1955 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); \
1957 /* Output various types of constants. */
1959 /* This is how to output an assembler line defining a `double'. */
1961 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1962 do { char dstr[30]; \
1963 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1964 fprintf ((FILE), "\t.double %s\n", dstr); \
1967 /* This is how to output an assembler line defining a `float' constant. */
1968 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1969 do { char dstr[30]; \
1970 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1971 fprintf ((FILE), "\t.float %s\n", dstr); \
1974 #define ASM_OUTPUT_INT(STREAM, EXP) \
1975 (fprintf ((STREAM), "\t.long\t"), \
1976 output_addr_const ((STREAM), (EXP)), \
1977 fputc ('\n', (STREAM)))
1979 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1980 (fprintf ((STREAM), "\t.short\t"), \
1981 output_addr_const ((STREAM), (EXP)), \
1982 fputc ('\n', (STREAM)))
1984 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1985 (fprintf ((STREAM), "\t.byte\t"), \
1986 output_addr_const ((STREAM), (EXP)), \
1987 fputc ('\n', (STREAM)))
1989 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1990 fprintf ((STREAM), "\t.byte\t%d\n", (VALUE)) \
1992 /* The next two are used for debug info when compiling with -gdwarf. */
1993 #define UNALIGNED_SHORT_ASM_OP ".uaword"
1994 #define UNALIGNED_INT_ASM_OP ".ualong"
1996 /* Loop alignment is now done in machine_dependent_reorg, so that
1997 branch shortening can know about it. */
1999 /* This is how to output an assembler line
2000 that says to advance the location counter by SIZE bytes. */
2002 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2003 fprintf ((FILE), "\t.space %d\n", (SIZE))
2005 /* This says how to output an assembler line
2006 to define a global common symbol. */
2008 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2009 ( fputs ("\t.comm ", (FILE)), \
2010 assemble_name ((FILE), (NAME)), \
2011 fprintf ((FILE), ",%d\n", (SIZE)))
2013 /* This says how to output an assembler line
2014 to define a local common symbol. */
2016 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2017 ( fputs ("\t.lcomm ", (FILE)), \
2018 assemble_name ((FILE), (NAME)), \
2019 fprintf ((FILE), ",%d\n", (SIZE)))
2021 /* The assembler's parentheses characters. */
2022 #define ASM_OPEN_PAREN "("
2023 #define ASM_CLOSE_PAREN ")"
2025 /* Target characters. */
2026 #define TARGET_BELL 007
2027 #define TARGET_BS 010
2028 #define TARGET_TAB 011
2029 #define TARGET_NEWLINE 012
2030 #define TARGET_VT 013
2031 #define TARGET_FF 014
2032 #define TARGET_CR 015
2034 /* A C statement to be executed just prior to the output of
2035 assembler code for INSN, to modify the extracted operands so
2036 they will be output differently.
2038 Here the argument OPVEC is the vector containing the operands
2039 extracted from INSN, and NOPERANDS is the number of elements of
2040 the vector which contain meaningful data for this insn.
2041 The contents of this vector are what will be used to convert the insn
2042 template into assembler code, so you can change the assembler output
2043 by changing the contents of the vector. */
2045 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2046 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2048 /* Print operand X (an rtx) in assembler syntax to file FILE.
2049 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2050 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2052 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
2054 /* Print a memory address as an operand to reference that memory location. */
2056 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
2058 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2059 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
2062 extern struct rtx_def *sh_compare_op0;
2063 extern struct rtx_def *sh_compare_op1;
2065 /* Which processor to schedule for. The elements of the enumeration must
2066 match exactly the cpu attribute in the sh.md file. */
2068 enum processor_type {
2076 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2077 extern enum processor_type sh_cpu;
2079 extern int optimize; /* needed for gen_casesi. */
2081 enum mdep_reorg_phase_e
2083 SH_BEFORE_MDEP_REORG,
2084 SH_INSERT_USES_LABELS,
2085 SH_SHORTEN_BRANCHES0,
2087 SH_SHORTEN_BRANCHES1,
2091 extern enum mdep_reorg_phase_e mdep_reorg_phase;
2093 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
2095 /* Generate calls to memcpy, memcmp and memset. */
2097 #define TARGET_MEM_FUNCTIONS
2099 /* Define this macro if you want to implement any pragmas. If defined, it
2100 is a C expression whose value is 1 if the pragma was handled by the
2101 macro, zero otherwise. */
2102 #define HANDLE_PRAGMA(GETC, UNGETC, NODE) sh_handle_pragma (GETC, UNGETC, NODE)
2104 /* Set when processing a function with pragma interrupt turned on. */
2106 extern int pragma_interrupt;
2108 /* Set to an RTX containing the address of the stack to switch to
2109 for interrupt functions. */
2110 extern struct rtx_def *sp_switch;
2112 /* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
2113 is a valid machine specific attribute for DECL.
2114 The attributes in ATTRIBUTES have previously been assigned to DECL. */
2115 #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
2116 sh_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
2118 #define PRAGMA_INSERT_ATTRIBUTES(node, pattr, prefix_attr) \
2119 sh_pragma_insert_attributes (node, pattr, prefix_attr)
2121 extern int rtx_equal_function_value_matters;
2122 extern struct rtx_def *fpscr_rtx;
2125 /* Instructions with unfilled delay slots take up an extra two bytes for
2126 the nop in the delay slot. */
2128 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2129 if (((GET_CODE (X) == INSN \
2130 && GET_CODE (PATTERN (X)) != USE \
2131 && GET_CODE (PATTERN (X)) != CLOBBER) \
2132 || GET_CODE (X) == CALL_INSN \
2133 || (GET_CODE (X) == JUMP_INSN \
2134 && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \
2135 && GET_CODE (PATTERN (X)) != ADDR_VEC)) \
2136 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (X)))) != SEQUENCE \
2137 && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \
2140 /* Define the codes that are matched by predicates in sh.c. */
2141 #define PREDICATE_CODES \
2142 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2143 {"arith_reg_operand", {SUBREG, REG}}, \
2144 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2145 {"binary_float_operator", {PLUS, MULT}}, \
2146 {"commutative_float_operator", {PLUS, MULT}}, \
2147 {"fp_arith_reg_operand", {SUBREG, REG}}, \
2148 {"fp_extended_operand", {SUBREG, REG, FLOAT_EXTEND}}, \
2149 {"fpscr_operand", {REG}}, \
2150 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2151 {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2152 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
2153 {"noncommutative_float_operator", {MINUS, DIV}}, \
2154 {"register_operand", {SUBREG, REG}},
2156 /* Define this macro if it is advisable to hold scalars in registers
2157 in a wider mode than that declared by the program. In such cases,
2158 the value is constrained to be within the bounds of the declared
2159 type, but kept valid in the wider mode. The signedness of the
2160 extension may differ from that of the type.
2162 Leaving the unsignedp unchanged gives better code than always setting it
2163 to 0. This is despite the fact that we have only signed char and short
2164 load instructions. */
2165 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2166 if (GET_MODE_CLASS (MODE) == MODE_INT \
2167 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
2170 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
2171 extensions applied to char/short functions arguments. Defining
2172 PROMOTE_FUNCTION_RETURN does the same for function returns. */
2174 #define PROMOTE_FUNCTION_ARGS
2175 #define PROMOTE_FUNCTION_RETURN
2177 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
2178 and poping arguments. However, we do have push/pop instructions, and
2179 rather limited offsets (4 bits) in load/store instructions, so it isn't
2180 clear if this would give better code. If implemented, should check for
2181 compatibility problems. */
2183 /* A C statement (sans semicolon) to update the integer variable COST
2184 based on the relationship between INSN that is dependent on
2185 DEP_INSN through the dependence LINK. The default is to make no
2186 adjustment to COST. This can be used for example to specify to
2187 the scheduler that an output- or anti-dependence does not incur
2188 the same cost as a data-dependence. */
2190 #define ADJUST_COST(insn,link,dep_insn,cost) \
2194 if (GET_CODE(insn) == CALL_INSN) \
2196 /* The only input for a call that is timing-critical is the \
2197 function's address. */ \
2198 rtx call = PATTERN (insn); \
2200 if (GET_CODE (call) == PARALLEL) \
2201 call = XVECEXP (call, 0 ,0); \
2202 if (GET_CODE (call) == SET) \
2203 call = SET_SRC (call); \
2204 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM \
2205 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)) \
2208 /* All sfunc calls are parallels with at least four components. \
2209 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */ \
2210 else if (GET_CODE (PATTERN (insn)) == PARALLEL \
2211 && XVECLEN (PATTERN (insn), 0) >= 4 \
2212 && (reg = sfunc_uses_reg (insn))) \
2214 /* Likewise, the most timing critical input for an sfuncs call \
2215 is the function address. However, sfuncs typically start \
2216 using their arguments pretty quickly. \
2217 Assume a four cycle delay before they are needed. */ \
2218 if (! reg_set_p (reg, dep_insn)) \
2219 cost -= TARGET_SUPERSCALAR ? 40 : 4; \
2221 /* Adjust load_si / pcload_si type insns latency. Use the known \
2222 nominal latency and form of the insn to speed up the check. */ \
2223 else if (cost == 3 \
2224 && GET_CODE (PATTERN (dep_insn)) == SET \
2225 /* Latency for dmpy type insns is also 3, so check the that \
2226 it's actually a move insn. */ \
2227 && general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode))\
2229 else if (cost == 30 \
2230 && GET_CODE (PATTERN (dep_insn)) == SET \
2231 && GET_MODE (SET_SRC (PATTERN (dep_insn))) == SImode) \
2235 #define SH_DYNAMIC_SHIFT_COST \
2236 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
2239 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2241 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
2243 #define MODE_USES_IN_EXIT_BLOCK gen_rtx_USE (VOIDmode, get_fpscr_rtx ())
2245 #define MODE_NEEDED(ENTITY, INSN) \
2246 (recog_memoized (INSN) >= 0 \
2247 ? get_attr_fp_mode (INSN) \
2248 : (GET_CODE (PATTERN (INSN)) == USE \
2249 && rtx_equal_p (XEXP (PATTERN (INSN), 0), get_fpscr_rtx ())) \
2250 ? (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE) \
2253 #define MODE_AT_ENTRY(ENTITY) \
2254 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2256 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2257 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2259 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2260 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2262 #define DWARF_LINE_MIN_INSTR_LENGTH 2
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