1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
26 #include "config/vxworks-dummy.h"
28 #define TARGET_VERSION \
29 fputs (" (Hitachi SH)", stderr);
31 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
32 include it here, because bconfig.h is also included by gencodes.c . */
33 /* ??? No longer true. */
34 extern int code_for_indirect_jump_scratch;
36 #define TARGET_CPU_CPP_BUILTINS() \
38 builtin_define ("__sh__"); \
39 builtin_assert ("cpu=sh"); \
40 builtin_assert ("machine=sh"); \
41 switch ((int) sh_cpu) \
44 builtin_define ("__sh1__"); \
47 builtin_define ("__sh2__"); \
49 case PROCESSOR_SH2E: \
50 builtin_define ("__SH2E__"); \
52 case PROCESSOR_SH2A: \
53 builtin_define ("__SH2A__"); \
54 builtin_define (TARGET_SH2A_DOUBLE \
55 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
56 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
57 : "__SH2A_NOFPU__"); \
60 builtin_define ("__sh3__"); \
61 builtin_define ("__SH3__"); \
62 if (TARGET_HARD_SH4) \
63 builtin_define ("__SH4_NOFPU__"); \
65 case PROCESSOR_SH3E: \
66 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
69 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
71 case PROCESSOR_SH4A: \
72 builtin_define ("__SH4A__"); \
73 builtin_define (TARGET_SH4 \
74 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
75 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
80 builtin_define_with_value ("__SH5__", \
81 TARGET_SHMEDIA64 ? "64" : "32", 0); \
82 builtin_define_with_value ("__SHMEDIA__", \
83 TARGET_SHMEDIA ? "1" : "0", 0); \
84 if (! TARGET_FPU_DOUBLE) \
85 builtin_define ("__SH4_NOFPU__"); \
89 builtin_define ("__SH_FPU_ANY__"); \
90 if (TARGET_FPU_DOUBLE) \
91 builtin_define ("__SH_FPU_DOUBLE__"); \
93 builtin_define ("__HITACHI__"); \
94 builtin_define (TARGET_LITTLE_ENDIAN \
95 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
98 /* We can not debug without a frame pointer. */
99 /* #define CAN_DEBUG_WITHOUT_FP */
101 #define CONDITIONAL_REGISTER_USAGE do \
104 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
105 if (! VALID_REGISTER_P (regno)) \
106 fixed_regs[regno] = call_used_regs[regno] = 1; \
107 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
110 call_used_regs[FIRST_GENERAL_REG + 8] \
111 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
112 call_really_used_regs[FIRST_GENERAL_REG + 8] \
113 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
115 if (TARGET_SHMEDIA) \
117 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
118 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
119 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
123 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
124 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
126 /* Renesas saves and restores mac registers on call. */ \
127 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
129 call_really_used_regs[MACH_REG] = 0; \
130 call_really_used_regs[MACL_REG] = 0; \
132 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
133 regno <= LAST_FP_REG; regno += 2) \
134 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
135 if (TARGET_SHMEDIA) \
137 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
138 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
139 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
142 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
143 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
144 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
147 /* Nonzero if this is an ELF target - compile time only */
150 /* Nonzero if we should generate code using type 2E insns. */
151 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
153 /* Nonzero if we should generate code using type 2A insns. */
154 #define TARGET_SH2A TARGET_HARD_SH2A
155 /* Nonzero if we should generate code using type 2A SF insns. */
156 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
157 /* Nonzero if we should generate code using type 2A DF insns. */
158 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
160 /* Nonzero if we should generate code using type 3E insns. */
161 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
163 /* Nonzero if the cache line size is 32. */
164 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
166 /* Nonzero if we schedule for a superscalar implementation. */
167 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
169 /* Nonzero if the target has separate instruction and data caches. */
170 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
172 /* Nonzero if a double-precision FPU is available. */
173 #define TARGET_FPU_DOUBLE \
174 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
176 /* Nonzero if an FPU is available. */
177 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
179 /* Nonzero if we should generate code using type 4 insns. */
181 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
183 /* Nonzero if we're generating code for the common subset of
184 instructions present on both SH4a and SH4al-dsp. */
185 #define TARGET_SH4A_ARCH TARGET_SH4A
187 /* Nonzero if we're generating code for SH4a, unless the use of the
188 FPU is disabled (which makes it compatible with SH4al-dsp). */
189 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
191 /* Nonzero if we should generate code using the SHcompact instruction
192 set and 32-bit ABI. */
193 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
195 /* Nonzero if we should generate code using the SHmedia instruction
197 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
199 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
201 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
203 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
205 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
207 /* Nonzero if we should generate code using SHmedia FPU instructions. */
208 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
210 /* This is not used by the SH2E calling convention */
211 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
212 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
213 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
215 #ifndef TARGET_CPU_DEFAULT
216 #define TARGET_CPU_DEFAULT SELECT_SH1
217 #define SUPPORT_SH1 1
218 #define SUPPORT_SH2E 1
219 #define SUPPORT_SH4 1
220 #define SUPPORT_SH4_SINGLE 1
221 #define SUPPORT_SH2A 1
222 #define SUPPORT_SH2A_SINGLE 1
225 #define TARGET_DIVIDE_INV \
226 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
227 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
228 || sh_div_strategy == SH_DIV_INV_CALL \
229 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
230 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
231 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
232 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
233 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
234 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
235 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
236 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
237 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
238 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
239 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
240 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
242 #define SELECT_SH1 (MASK_SH1)
243 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
244 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
246 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
247 | MASK_HARD_SH2A_DOUBLE \
248 | MASK_SH2 | MASK_SH1)
249 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
250 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
251 | MASK_SH1 | MASK_FPU_SINGLE)
252 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
253 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
254 | MASK_SH2 | MASK_SH1)
255 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
256 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
257 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
258 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
259 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
261 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
262 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
263 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
264 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
265 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
266 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
267 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
268 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
269 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
270 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
271 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
274 #define SUPPORT_SH2 1
277 #define SUPPORT_SH3 1
278 #define SUPPORT_SH2A_NOFPU 1
281 #define SUPPORT_SH4_NOFPU 1
283 #if SUPPORT_SH4_NOFPU
284 #define SUPPORT_SH4A_NOFPU 1
285 #define SUPPORT_SH4AL 1
289 #define SUPPORT_SH3E 1
290 #define SUPPORT_SH2A_SINGLE_ONLY 1
293 #define SUPPORT_SH4_SINGLE_ONLY 1
295 #if SUPPORT_SH4_SINGLE_ONLY
296 #define SUPPORT_SH4A_SINGLE_ONLY 1
300 #define SUPPORT_SH4A 1
303 #if SUPPORT_SH4_SINGLE
304 #define SUPPORT_SH4A_SINGLE 1
307 #if SUPPORT_SH5_COMPAT
308 #define SUPPORT_SH5_32MEDIA 1
311 #if SUPPORT_SH5_COMPACT_NOFPU
312 #define SUPPORT_SH5_32MEDIA_NOFPU 1
315 #define SUPPORT_ANY_SH5_32MEDIA \
316 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
317 #define SUPPORT_ANY_SH5_64MEDIA \
318 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
319 #define SUPPORT_ANY_SH5 \
320 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
322 /* Reset all target-selection flags. */
323 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
324 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
325 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
327 /* This defaults us to big-endian. */
328 #ifndef TARGET_ENDIAN_DEFAULT
329 #define TARGET_ENDIAN_DEFAULT 0
332 #ifndef TARGET_OPT_DEFAULT
333 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
336 #define TARGET_DEFAULT \
337 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
339 #ifndef SH_MULTILIB_CPU_DEFAULT
340 #define SH_MULTILIB_CPU_DEFAULT "m1"
343 #if TARGET_ENDIAN_DEFAULT
344 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
346 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
349 #define CPP_SPEC " %(subtarget_cpp_spec) "
351 #ifndef SUBTARGET_CPP_SPEC
352 #define SUBTARGET_CPP_SPEC ""
355 #ifndef SUBTARGET_EXTRA_SPECS
356 #define SUBTARGET_EXTRA_SPECS
359 #define EXTRA_SPECS \
360 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
361 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
362 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
363 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
364 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
365 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
366 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
367 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
368 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
369 SUBTARGET_EXTRA_SPECS
371 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
372 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
374 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
377 #define SH_ASM_SPEC \
378 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
379 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
381 %{m2a-single:--isa=sh2a} \
382 %{m2a-single-only:--isa=sh2a} \
383 %{m2a-nofpu:--isa=sh2a-nofpu} \
384 %{m5-compact*:--isa=SHcompact} \
385 %{m5-32media*:--isa=SHmedia --abi=32} \
386 %{m5-64media*:--isa=SHmedia --abi=64} \
387 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
389 #define ASM_SPEC SH_ASM_SPEC
391 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
392 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
393 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
395 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
399 #if STRICT_NOFPU == 1
400 /* Strict nofpu means that the compiler should tell the assembler
401 to reject FPU instructions. E.g. from ASM inserts. */
402 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
403 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
405 /* If there were an -isa option for sh5-nofpu then it would also go here. */
406 #define SUBTARGET_ASM_ISA_SPEC \
407 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
409 #else /* ! STRICT_NOFPU */
410 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
413 #ifndef SUBTARGET_ASM_SPEC
414 #define SUBTARGET_ASM_SPEC ""
417 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
418 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
420 #define LINK_EMUL_PREFIX "sh%{ml:l}"
423 #if TARGET_CPU_DEFAULT & MASK_SH5
424 #if TARGET_CPU_DEFAULT & MASK_SH_E
425 #define LINK_DEFAULT_CPU_EMUL "32"
426 #if TARGET_CPU_DEFAULT & MASK_SH1
427 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
429 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
430 #endif /* MASK_SH1 */
431 #else /* !MASK_SH_E */
432 #define LINK_DEFAULT_CPU_EMUL "64"
433 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
434 #endif /* MASK_SH_E */
435 #define ASM_ISA_DEFAULT_SPEC \
436 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
437 #else /* !MASK_SH5 */
438 #define LINK_DEFAULT_CPU_EMUL ""
439 #define ASM_ISA_DEFAULT_SPEC ""
440 #endif /* MASK_SH5 */
442 #define SUBTARGET_LINK_EMUL_SUFFIX ""
443 #define SUBTARGET_LINK_SPEC ""
445 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
446 so that we can undo the damage without code replication. */
447 #define LINK_SPEC SH_LINK_SPEC
449 #define SH_LINK_SPEC "\
450 -m %(link_emul_prefix)\
451 %{m5-compact*|m5-32media*:32}\
453 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
454 %(subtarget_link_emul_suffix) \
455 %{mrelax:-relax} %(subtarget_link_spec)"
457 #ifndef SH_DIV_STR_FOR_SIZE
458 #define SH_DIV_STR_FOR_SIZE "call"
461 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
462 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
466 flag_omit_frame_pointer = 2; \
468 sh_div_str = "inv:minlat"; \
472 target_flags |= MASK_SMALLCODE; \
473 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
477 TARGET_CBRANCHDI4 = 1; \
478 TARGET_EXPAND_CBRANCHDI4 = 1; \
480 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
481 haven't been parsed yet, hence we'd read only the default. \
482 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
483 it's OK to always set flag_branch_target_load_optimize. */ \
486 flag_branch_target_load_optimize = 1; \
488 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
490 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
491 here, so leave it to OVERRIDE_OPTIONS to set \
492 flag_finite_math_only. We set it to 2 here so we know if the user \
493 explicitly requested this to be on or off. */ \
494 flag_finite_math_only = 2; \
495 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \
496 the user explicitly requested this to be on or off. */ \
497 if (flag_schedule_insns > 0) \
498 flag_schedule_insns = 2; \
500 set_param_value ("simultaneous-prefetches", 2); \
503 #define ASSEMBLER_DIALECT assembler_dialect
505 extern int assembler_dialect;
507 enum sh_divide_strategy_e {
508 /* SH5 strategies. */
511 SH_DIV_FP, /* We could do this also for SH4. */
519 /* SH1 .. SH4 strategies. Because of the small number of registers
520 available, the compiler uses knowledge of the actual set of registers
521 being clobbered by the different functions called. */
522 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
523 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
524 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
528 extern enum sh_divide_strategy_e sh_div_strategy;
530 #ifndef SH_DIV_STRATEGY_DEFAULT
531 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
534 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
536 extern const char *sh_fixed_range_str;
538 #define OVERRIDE_OPTIONS \
542 SUBTARGET_OVERRIDE_OPTIONS; \
543 if (flag_finite_math_only == 2) \
544 flag_finite_math_only \
545 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
546 if (TARGET_SH2E && !flag_finite_math_only) \
547 target_flags |= MASK_IEEE; \
548 sh_cpu = PROCESSOR_SH1; \
549 assembler_dialect = 0; \
551 sh_cpu = PROCESSOR_SH2; \
553 sh_cpu = PROCESSOR_SH2E; \
556 sh_cpu = PROCESSOR_SH2A; \
557 if (TARGET_SH2A_DOUBLE) \
558 target_flags |= MASK_FMOVD; \
561 sh_cpu = PROCESSOR_SH3; \
563 sh_cpu = PROCESSOR_SH3E; \
566 assembler_dialect = 1; \
567 sh_cpu = PROCESSOR_SH4; \
569 if (TARGET_SH4A_ARCH) \
571 assembler_dialect = 1; \
572 sh_cpu = PROCESSOR_SH4A; \
576 sh_cpu = PROCESSOR_SH5; \
577 target_flags |= MASK_ALIGN_DOUBLE; \
578 if (TARGET_SHMEDIA_FPU) \
579 target_flags |= MASK_FMOVD; \
580 if (TARGET_SHMEDIA) \
582 /* There are no delay slots on SHmedia. */ \
583 flag_delayed_branch = 0; \
584 /* Relaxation isn't yet supported for SHmedia */ \
585 target_flags &= ~MASK_RELAX; \
586 /* After reload, if conversion does little good but can cause \
588 - find_if_block doesn't do anything for SH because we don't\
589 have conditional execution patterns. (We use conditional\
590 move patterns, which are handled differently, and only \
592 - find_cond_trap doesn't do anything for the SH because we \
593 don't have conditional traps. \
594 - find_if_case_1 uses redirect_edge_and_branch_force in \
595 the only path that does an optimization, and this causes \
596 an ICE when branch targets are in registers. \
597 - find_if_case_2 doesn't do anything for the SHmedia after \
598 reload except when it can redirect a tablejump - and \
599 that's rather rare. */ \
600 flag_if_conversion2 = 0; \
601 if (! strcmp (sh_div_str, "call")) \
602 sh_div_strategy = SH_DIV_CALL; \
603 else if (! strcmp (sh_div_str, "call2")) \
604 sh_div_strategy = SH_DIV_CALL2; \
605 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
606 sh_div_strategy = SH_DIV_FP; \
607 else if (! strcmp (sh_div_str, "inv")) \
608 sh_div_strategy = SH_DIV_INV; \
609 else if (! strcmp (sh_div_str, "inv:minlat")) \
610 sh_div_strategy = SH_DIV_INV_MINLAT; \
611 else if (! strcmp (sh_div_str, "inv20u")) \
612 sh_div_strategy = SH_DIV_INV20U; \
613 else if (! strcmp (sh_div_str, "inv20l")) \
614 sh_div_strategy = SH_DIV_INV20L; \
615 else if (! strcmp (sh_div_str, "inv:call2")) \
616 sh_div_strategy = SH_DIV_INV_CALL2; \
617 else if (! strcmp (sh_div_str, "inv:call")) \
618 sh_div_strategy = SH_DIV_INV_CALL; \
619 else if (! strcmp (sh_div_str, "inv:fp")) \
621 if (TARGET_FPU_ANY) \
622 sh_div_strategy = SH_DIV_INV_FP; \
624 sh_div_strategy = SH_DIV_INV; \
626 TARGET_CBRANCHDI4 = 0; \
627 /* Assembler CFI isn't yet fully supported for SHmedia. */ \
628 flag_dwarf2_cfi_asm = 0; \
633 /* Only the sh64-elf assembler fully supports .quad properly. */\
634 targetm.asm_out.aligned_op.di = NULL; \
635 targetm.asm_out.unaligned_op.di = NULL; \
639 if (! strcmp (sh_div_str, "call-div1")) \
640 sh_div_strategy = SH_DIV_CALL_DIV1; \
641 else if (! strcmp (sh_div_str, "call-fp") \
642 && (TARGET_FPU_DOUBLE \
643 || (TARGET_HARD_SH4 && TARGET_SH2E) \
644 || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) \
645 sh_div_strategy = SH_DIV_CALL_FP; \
646 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2) \
647 sh_div_strategy = SH_DIV_CALL_TABLE; \
649 /* Pick one that makes most sense for the target in general. \
650 It is not much good to use different functions depending \
651 on -Os, since then we'll end up with two different functions \
652 when some of the code is compiled for size, and some for \
655 /* SH4 tends to emphasize speed. */ \
656 if (TARGET_HARD_SH4) \
657 sh_div_strategy = SH_DIV_CALL_TABLE; \
658 /* These have their own way of doing things. */ \
659 else if (TARGET_SH2A) \
660 sh_div_strategy = SH_DIV_INTRINSIC; \
661 /* ??? Should we use the integer SHmedia function instead? */ \
662 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
663 sh_div_strategy = SH_DIV_CALL_FP; \
664 /* SH1 .. SH3 cores often go into small-footprint systems, so \
665 default to the smallest implementation available. */ \
666 else if (TARGET_SH2) /* ??? EXPERIMENTAL */ \
667 sh_div_strategy = SH_DIV_CALL_TABLE; \
669 sh_div_strategy = SH_DIV_CALL_DIV1; \
672 TARGET_PRETEND_CMOVE = 0; \
673 if (sh_divsi3_libfunc[0]) \
674 ; /* User supplied - leave it alone. */ \
675 else if (TARGET_DIVIDE_CALL_FP) \
676 sh_divsi3_libfunc = "__sdivsi3_i4"; \
677 else if (TARGET_DIVIDE_CALL_TABLE) \
678 sh_divsi3_libfunc = "__sdivsi3_i4i"; \
679 else if (TARGET_SH5) \
680 sh_divsi3_libfunc = "__sdivsi3_1"; \
682 sh_divsi3_libfunc = "__sdivsi3"; \
683 if (sh_branch_cost == -1) \
685 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1; \
687 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
688 if (! VALID_REGISTER_P (regno)) \
689 sh_register_names[regno][0] = '\0'; \
691 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
692 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
693 sh_additional_register_names[regno][0] = '\0'; \
695 if (flag_omit_frame_pointer == 2) \
697 /* The debugging information is sufficient, \
698 but gdb doesn't implement this yet */ \
700 flag_omit_frame_pointer \
701 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
703 flag_omit_frame_pointer = 0; \
706 if ((flag_pic && ! TARGET_PREFERGOT) \
707 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
708 flag_no_function_cse = 1; \
710 if (SMALL_REGISTER_CLASSES) \
712 /* Never run scheduling before reload, since that can \
713 break global alloc, and generates slower code anyway due \
714 to the pressure on R0. */ \
715 /* Enable sched1 for SH4; ready queue will be reordered by \
716 the target hooks when pressure is high. We can not do this for \
717 PIC, SH3 and lower as they give spill failures for R0. */ \
718 if (!TARGET_HARD_SH4 || flag_pic) \
719 flag_schedule_insns = 0; \
720 /* ??? Current exception handling places basic block boundaries \
721 after call_insns. It causes the high pressure on R0 and gives \
722 spill failures for R0 in reload. See PR 22553 and the thread \
724 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
725 else if (flag_exceptions) \
727 if (flag_schedule_insns == 1) \
728 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
729 flag_schedule_insns = 0; \
733 if (align_loops == 0) \
734 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
735 if (align_jumps == 0) \
736 align_jumps = 1 << CACHE_LOG; \
737 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
738 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
740 /* Allocation boundary (in *bytes*) for the code of a function. \
741 SH1: 32 bit alignment is faster, because instructions are always \
742 fetched as a pair from a longword boundary. \
743 SH2 .. SH5 : align to cache line start. */ \
744 if (align_functions == 0) \
746 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
747 /* The linker relaxation code breaks when a function contains \
748 alignments that are larger than that at the start of a \
749 compilation unit. */ \
753 = align_loops > align_jumps ? align_loops : align_jumps; \
755 /* Also take possible .long constants / mova tables int account. */\
758 if (align_functions < min_align) \
759 align_functions = min_align; \
762 if (sh_fixed_range_str) \
763 sh_fix_range (sh_fixed_range_str); \
766 /* Target machine storage layout. */
768 /* Define this if most significant bit is lowest numbered
769 in instructions that operate on numbered bit-fields. */
771 #define BITS_BIG_ENDIAN 0
773 /* Define this if most significant byte of a word is the lowest numbered. */
774 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
776 /* Define this if most significant word of a multiword number is the lowest
778 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
780 /* Define this to set the endianness to use in libgcc2.c, which can
781 not depend on target_flags. */
782 #if defined(__LITTLE_ENDIAN__)
783 #define LIBGCC2_WORDS_BIG_ENDIAN 0
785 #define LIBGCC2_WORDS_BIG_ENDIAN 1
788 #define MAX_BITS_PER_WORD 64
790 /* Width in bits of an `int'. We want just 32-bits, even if words are
792 #define INT_TYPE_SIZE 32
794 /* Width in bits of a `long'. */
795 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
797 /* Width in bits of a `long long'. */
798 #define LONG_LONG_TYPE_SIZE 64
800 /* Width in bits of a `long double'. */
801 #define LONG_DOUBLE_TYPE_SIZE 64
803 /* Width of a word, in units (bytes). */
804 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
805 #define MIN_UNITS_PER_WORD 4
807 /* Scaling factor for Dwarf data offsets for CFI information.
808 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
809 SHmedia; however, since we do partial register saves for the registers
810 visible to SHcompact, and for target registers for SHMEDIA32, we have
811 to allow saves that are only 4-byte aligned. */
812 #define DWARF_CIE_DATA_ALIGNMENT -4
814 /* Width in bits of a pointer.
815 See also the macro `Pmode' defined below. */
816 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
818 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
819 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
821 /* Boundary (in *bits*) on which stack pointer should be aligned. */
822 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
824 /* The log (base 2) of the cache line size, in bytes. Processors prior to
825 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
826 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
827 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
829 /* ABI given & required minimum allocation boundary (in *bits*) for the
830 code of a function. */
831 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
833 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
834 the vbit must go into the delta field of
835 pointers-to-member-functions. */
836 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
837 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
839 /* Alignment of field after `int : 0' in a structure. */
840 #define EMPTY_FIELD_BOUNDARY 32
842 /* No data type wants to be aligned rounder than this. */
843 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
845 /* The best alignment to use in cases where we have a choice. */
846 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
848 /* Make strings word-aligned so strcpy from constants will be faster. */
849 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
850 ((TREE_CODE (EXP) == STRING_CST \
851 && (ALIGN) < FASTEST_ALIGNMENT) \
852 ? FASTEST_ALIGNMENT : (ALIGN))
854 /* get_mode_alignment assumes complex values are always held in multiple
855 registers, but that is not the case on the SH; CQImode and CHImode are
856 held in a single integer register. SH5 also holds CSImode and SCmode
857 values in integer registers. This is relevant for argument passing on
858 SHcompact as we use a stack temp in order to pass CSImode by reference. */
859 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
860 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
861 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
862 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
863 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
865 /* Make arrays of chars word-aligned for the same reasons. */
866 #define DATA_ALIGNMENT(TYPE, ALIGN) \
867 (TREE_CODE (TYPE) == ARRAY_TYPE \
868 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
869 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
871 /* Number of bits which any structure or union's size must be a
872 multiple of. Each structure or union's size is rounded up to a
874 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
876 /* Set this nonzero if move instructions will actually fail to work
877 when given unaligned data. */
878 #define STRICT_ALIGNMENT 1
880 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
881 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
882 barrier_align (LABEL_AFTER_BARRIER)
884 #define LOOP_ALIGN(A_LABEL) \
885 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
886 ? 0 : sh_loop_align (A_LABEL))
888 #define LABEL_ALIGN(A_LABEL) \
890 (PREV_INSN (A_LABEL) \
891 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
892 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
893 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
894 /* explicit alignment insn in constant tables. */ \
895 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
898 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
899 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
901 /* The base two logarithm of the known minimum alignment of an insn length. */
902 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
903 (GET_CODE (A_INSN) == INSN \
904 ? 1 << TARGET_SHMEDIA \
905 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
906 ? 1 << TARGET_SHMEDIA \
909 /* Standard register usage. */
911 /* Register allocation for the Renesas calling convention:
917 r14 frame pointer/call saved
919 ap arg pointer (doesn't really exist, always eliminated)
920 pr subroutine return address
922 mach multiply/accumulate result, high part
923 macl multiply/accumulate result, low part.
924 fpul fp/int communication register
925 rap return address pointer register
927 fr1..fr3 scratch floating point registers
929 fr12..fr15 call saved floating point registers */
931 #define MAX_REGISTER_NAME_LENGTH 5
932 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
934 #define SH_REGISTER_NAMES_INITIALIZER \
936 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
937 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
938 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
939 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
940 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
941 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
942 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
943 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
944 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
945 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
946 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
947 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
948 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
949 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
950 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
951 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
952 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
953 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
954 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
958 #define REGNAMES_ARR_INDEX_1(index) \
959 (sh_register_names[index])
960 #define REGNAMES_ARR_INDEX_2(index) \
961 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
962 #define REGNAMES_ARR_INDEX_4(index) \
963 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
964 #define REGNAMES_ARR_INDEX_8(index) \
965 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
966 #define REGNAMES_ARR_INDEX_16(index) \
967 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
968 #define REGNAMES_ARR_INDEX_32(index) \
969 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
970 #define REGNAMES_ARR_INDEX_64(index) \
971 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
973 #define REGISTER_NAMES \
975 REGNAMES_ARR_INDEX_64 (0), \
976 REGNAMES_ARR_INDEX_64 (64), \
977 REGNAMES_ARR_INDEX_8 (128), \
978 REGNAMES_ARR_INDEX_8 (136), \
979 REGNAMES_ARR_INDEX_8 (144), \
980 REGNAMES_ARR_INDEX_2 (152) \
983 #define ADDREGNAMES_SIZE 32
984 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
985 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
986 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
988 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
990 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
991 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
992 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
993 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
996 #define ADDREGNAMES_REGNO(index) \
997 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
1000 #define ADDREGNAMES_ARR_INDEX_1(index) \
1001 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
1002 #define ADDREGNAMES_ARR_INDEX_2(index) \
1003 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
1004 #define ADDREGNAMES_ARR_INDEX_4(index) \
1005 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
1006 #define ADDREGNAMES_ARR_INDEX_8(index) \
1007 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
1008 #define ADDREGNAMES_ARR_INDEX_16(index) \
1009 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
1010 #define ADDREGNAMES_ARR_INDEX_32(index) \
1011 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1013 #define ADDITIONAL_REGISTER_NAMES \
1015 ADDREGNAMES_ARR_INDEX_32 (0) \
1018 /* Number of actual hardware registers.
1019 The hardware registers are assigned numbers for the compiler
1020 from 0 to just below FIRST_PSEUDO_REGISTER.
1021 All registers that the compiler knows about must be given numbers,
1022 even those that are not normally considered general registers. */
1024 /* There are many other relevant definitions in sh.md's md_constants. */
1026 #define FIRST_GENERAL_REG R0_REG
1027 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1028 #define FIRST_FP_REG DR0_REG
1029 #define LAST_FP_REG (FIRST_FP_REG + \
1030 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1031 #define FIRST_XD_REG XD0_REG
1032 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1033 #define FIRST_TARGET_REG TR0_REG
1034 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1036 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
1038 #define FIRST_BANKED_REG R0_REG
1039 #define LAST_BANKED_REG R7_REG
1041 #define BANKED_REGISTER_P(REGNO) \
1042 IN_RANGE ((REGNO), \
1043 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
1044 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
1046 #define GENERAL_REGISTER_P(REGNO) \
1047 IN_RANGE ((REGNO), \
1048 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1049 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1051 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1052 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
1053 || ((REGNO) == FRAME_POINTER_REGNUM))
1055 #define FP_REGISTER_P(REGNO) \
1056 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1058 #define XD_REGISTER_P(REGNO) \
1059 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1061 #define FP_OR_XD_REGISTER_P(REGNO) \
1062 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1064 #define FP_ANY_REGISTER_P(REGNO) \
1065 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1067 #define SPECIAL_REGISTER_P(REGNO) \
1068 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1069 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1071 #define TARGET_REGISTER_P(REGNO) \
1072 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1074 #define SHMEDIA_REGISTER_P(REGNO) \
1075 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1076 || TARGET_REGISTER_P (REGNO))
1078 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1079 that should be fixed. */
1080 #define VALID_REGISTER_P(REGNO) \
1081 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1082 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1083 || (REGNO) == FRAME_POINTER_REGNUM \
1084 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1085 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1087 /* The mode that should be generally used to store a register by
1088 itself in the stack, or to load it back. */
1089 #define REGISTER_NATURAL_MODE(REGNO) \
1090 (FP_REGISTER_P (REGNO) ? SFmode \
1091 : XD_REGISTER_P (REGNO) ? DFmode \
1092 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1096 #define FIRST_PSEUDO_REGISTER 154
1098 /* Don't count soft frame pointer. */
1099 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1101 /* 1 for registers that have pervasive standard uses
1102 and are not available for the register allocator.
1104 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1105 It is 32 bits wide for SH2. */
1107 #define FIXED_REGISTERS \
1109 /* Regular registers. */ \
1110 0, 0, 0, 0, 0, 0, 0, 0, \
1111 0, 0, 0, 0, 0, 0, 0, 1, \
1112 /* r16 is reserved, r18 is the former pr. */ \
1113 1, 0, 0, 0, 0, 0, 0, 0, \
1114 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1115 /* r26 is a global variable data pointer; r27 is for constants. */ \
1116 1, 1, 1, 1, 0, 0, 0, 0, \
1117 0, 0, 0, 0, 0, 0, 0, 0, \
1118 0, 0, 0, 0, 0, 0, 0, 0, \
1119 0, 0, 0, 0, 0, 0, 0, 0, \
1120 0, 0, 0, 0, 0, 0, 0, 1, \
1121 /* FP registers. */ \
1122 0, 0, 0, 0, 0, 0, 0, 0, \
1123 0, 0, 0, 0, 0, 0, 0, 0, \
1124 0, 0, 0, 0, 0, 0, 0, 0, \
1125 0, 0, 0, 0, 0, 0, 0, 0, \
1126 0, 0, 0, 0, 0, 0, 0, 0, \
1127 0, 0, 0, 0, 0, 0, 0, 0, \
1128 0, 0, 0, 0, 0, 0, 0, 0, \
1129 0, 0, 0, 0, 0, 0, 0, 0, \
1130 /* Branch target registers. */ \
1131 0, 0, 0, 0, 0, 0, 0, 0, \
1132 /* XD registers. */ \
1133 0, 0, 0, 0, 0, 0, 0, 0, \
1134 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1135 1, 1, 1, 1, 1, 1, 0, 1, \
1140 /* 1 for registers not available across function calls.
1141 These must include the FIXED_REGISTERS and also any
1142 registers that can be used without being saved.
1143 The latter must include the registers where values are returned
1144 and the register where structure-value addresses are passed.
1145 Aside from that, you can include as many other registers as you like. */
1147 #define CALL_USED_REGISTERS \
1149 /* Regular registers. */ \
1150 1, 1, 1, 1, 1, 1, 1, 1, \
1151 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1152 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1153 across SH5 function calls. */ \
1154 0, 0, 0, 0, 0, 0, 0, 1, \
1155 1, 1, 1, 1, 1, 1, 1, 1, \
1156 1, 1, 1, 1, 0, 0, 0, 0, \
1157 0, 0, 0, 0, 1, 1, 1, 1, \
1158 1, 1, 1, 1, 0, 0, 0, 0, \
1159 0, 0, 0, 0, 0, 0, 0, 0, \
1160 0, 0, 0, 0, 1, 1, 1, 1, \
1161 /* FP registers. */ \
1162 1, 1, 1, 1, 1, 1, 1, 1, \
1163 1, 1, 1, 1, 0, 0, 0, 0, \
1164 1, 1, 1, 1, 1, 1, 1, 1, \
1165 1, 1, 1, 1, 1, 1, 1, 1, \
1166 1, 1, 1, 1, 0, 0, 0, 0, \
1167 0, 0, 0, 0, 0, 0, 0, 0, \
1168 0, 0, 0, 0, 0, 0, 0, 0, \
1169 0, 0, 0, 0, 0, 0, 0, 0, \
1170 /* Branch target registers. */ \
1171 1, 1, 1, 1, 1, 0, 0, 0, \
1172 /* XD registers. */ \
1173 1, 1, 1, 1, 1, 1, 0, 0, \
1174 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1175 1, 1, 1, 1, 1, 1, 1, 1, \
1180 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1181 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1182 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1184 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1185 across SHcompact function calls. We can't tell whether a called
1186 function is SHmedia or SHcompact, so we assume it may be when
1187 compiling SHmedia code with the 32-bit ABI, since that's the only
1188 ABI that can be linked with SHcompact code. */
1189 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1191 && GET_MODE_SIZE (MODE) > 4 \
1192 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1193 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1194 || TARGET_REGISTER_P (REGNO) \
1195 || (REGNO) == PR_MEDIA_REG))
1197 /* Return number of consecutive hard regs needed starting at reg REGNO
1198 to hold something of mode MODE.
1199 This is ordinarily the length in words of a value of mode MODE
1200 but can be less for certain modes in special long registers.
1202 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1204 #define HARD_REGNO_NREGS(REGNO, MODE) \
1205 (XD_REGISTER_P (REGNO) \
1206 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1207 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1208 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1209 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1211 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1213 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1214 sh_hard_regno_mode_ok ((REGNO), (MODE))
1216 /* Value is 1 if it is a good idea to tie two pseudo registers
1217 when one has mode MODE1 and one has mode MODE2.
1218 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1219 for any hard reg, then this must be 0 for correct output.
1220 That's the case for xd registers: we don't hold SFmode values in
1221 them, so we can't tie an SFmode pseudos with one in another
1222 floating-point mode. */
1224 #define MODES_TIEABLE_P(MODE1, MODE2) \
1225 ((MODE1) == (MODE2) \
1226 || (TARGET_SHMEDIA \
1227 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1228 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1229 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1230 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1231 && (GET_MODE_SIZE (MODE2) <= 4)) \
1232 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1234 /* A C expression that is nonzero if hard register NEW_REG can be
1235 considered for use as a rename register for OLD_REG register */
1237 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1238 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1240 /* Specify the registers used for certain standard purposes.
1241 The values of these macros are register numbers. */
1243 /* Define this if the program counter is overloaded on a register. */
1244 /* #define PC_REGNUM 15*/
1246 /* Register to use for pushing function arguments. */
1247 #define STACK_POINTER_REGNUM SP_REG
1249 /* Base register for access to local variables of the function. */
1250 #define HARD_FRAME_POINTER_REGNUM FP_REG
1252 /* Base register for access to local variables of the function. */
1253 #define FRAME_POINTER_REGNUM 153
1255 /* Fake register that holds the address on the stack of the
1256 current function's return address. */
1257 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1259 /* Register to hold the addressing base for position independent
1260 code access to data items. */
1261 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1263 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1265 /* Definitions for register eliminations.
1267 We have three registers that can be eliminated on the SH. First, the
1268 frame pointer register can often be eliminated in favor of the stack
1269 pointer register. Secondly, the argument pointer register can always be
1270 eliminated; it is replaced with either the stack or frame pointer.
1271 Third, there is the return address pointer, which can also be replaced
1272 with either the stack or the frame pointer. */
1274 /* This is an array of structures. Each structure initializes one pair
1275 of eliminable registers. The "from" register number is given first,
1276 followed by "to". Eliminations of the same "from" register are listed
1277 in order of preference. */
1279 /* If you add any registers here that are not actually hard registers,
1280 and that have any alternative of elimination that doesn't always
1281 apply, you need to amend calc_live_regs to exclude it, because
1282 reload spills all eliminable registers where it sees an
1283 can_eliminate == 0 entry, thus making them 'live' .
1284 If you add any hard registers that can be eliminated in different
1285 ways, you have to patch reload to spill them only when all alternatives
1286 of elimination fail. */
1288 #define ELIMINABLE_REGS \
1289 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1290 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1291 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1292 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1293 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1294 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1295 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1297 /* Given FROM and TO register numbers, say whether this elimination
1299 #define CAN_ELIMINATE(FROM, TO) \
1300 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1302 /* Define the offset between two registers, one to be eliminated, and the other
1303 its replacement, at the start of a routine. */
1305 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1306 OFFSET = initial_elimination_offset ((FROM), (TO))
1308 /* Base register for access to arguments of the function. */
1309 #define ARG_POINTER_REGNUM AP_REG
1311 /* Register in which the static-chain is passed to a function. */
1312 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1314 /* Don't default to pcc-struct-return, because we have already specified
1315 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1318 #define DEFAULT_PCC_STRUCT_RETURN 0
1320 #define SHMEDIA_REGS_STACK_ADJUST() \
1321 (TARGET_SHCOMPACT && crtl->saves_all_registers \
1322 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1323 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1327 /* Define the classes of registers for register constraints in the
1328 machine description. Also define ranges of constants.
1330 One of the classes must always be named ALL_REGS and include all hard regs.
1331 If there is more than one class, another class must be named NO_REGS
1332 and contain no registers.
1334 The name GENERAL_REGS must be the name of a class (or an alias for
1335 another name such as ALL_REGS). This is the class of registers
1336 that is allowed by "g" or "r" in a register constraint.
1337 Also, registers outside this class are allocated only when
1338 instructions express preferences for them.
1340 The classes must be numbered in nondecreasing order; that is,
1341 a larger-numbered class must never be contained completely
1342 in a smaller-numbered class.
1344 For any two classes, it is very desirable that there be another
1345 class that represents their union. */
1347 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1348 be used as the destination of some of the arithmetic ops. There are
1349 also some special purpose registers; the T bit register, the
1350 Procedure Return Register and the Multiply Accumulate Registers. */
1351 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1352 reg_class_subunion. We don't want to have an actual union class
1353 of these, because it would only be used when both classes are calculated
1354 to give the same cost, but there is only one FPUL register.
1355 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1356 applying to the actual instruction alternative considered. E.g., the
1357 y/r alternative of movsi_ie is considered to have no more cost that
1358 the r/r alternative, which is patently untrue. */
1382 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1384 /* Give names of register classes as strings for dump file. */
1385 #define REG_CLASS_NAMES \
1400 "GENERAL_FP_REGS", \
1401 "GENERAL_DF_REGS", \
1406 /* Define which registers fit in which classes.
1407 This is an initializer for a vector of HARD_REG_SET
1408 of length N_REG_CLASSES. */
1410 #define REG_CLASS_CONTENTS \
1413 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1415 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1417 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1419 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1421 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1423 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1424 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1425 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1426 /* GENERAL_REGS: */ \
1427 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1429 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1431 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1432 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1433 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1435 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1437 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1438 /* GENERAL_FP_REGS: */ \
1439 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1440 /* GENERAL_DF_REGS: */ \
1441 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1442 /* TARGET_REGS: */ \
1443 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1445 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1448 /* The same information, inverted:
1449 Return the class number of the smallest class containing
1450 reg number REGNO. This could be a conditional expression
1451 or could index an array. */
1453 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1454 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1456 /* The following macro defines cover classes for Integrated Register
1457 Allocator. Cover classes is a set of non-intersected register
1458 classes covering all hard registers used for register allocation
1459 purpose. Any move between two registers of a cover class should be
1460 cheaper than load or store of the registers. The macro value is
1461 array of register classes with LIM_REG_CLASSES used as the end
1464 #define IRA_COVER_CLASSES \
1466 GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \
1467 FPUL_REGS, LIM_REG_CLASSES \
1470 /* When defined, the compiler allows registers explicitly used in the
1471 rtl to be used as spill registers but prevents the compiler from
1472 extending the lifetime of these registers. */
1474 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1476 /* The order in which register should be allocated. */
1477 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1478 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1479 spilled or used otherwise, we better have the FP_REGS allocated first. */
1480 #define REG_ALLOC_ORDER \
1481 {/* Caller-saved FPRs */ \
1482 65, 66, 67, 68, 69, 70, 71, 64, \
1483 72, 73, 74, 75, 80, 81, 82, 83, \
1484 84, 85, 86, 87, 88, 89, 90, 91, \
1485 92, 93, 94, 95, 96, 97, 98, 99, \
1486 /* Callee-saved FPRs */ \
1487 76, 77, 78, 79,100,101,102,103, \
1488 104,105,106,107,108,109,110,111, \
1489 112,113,114,115,116,117,118,119, \
1490 120,121,122,123,124,125,126,127, \
1491 136,137,138,139,140,141,142,143, \
1493 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1494 1, 2, 3, 7, 6, 5, 4, 0, \
1495 8, 9, 17, 19, 20, 21, 22, 23, \
1496 36, 37, 38, 39, 40, 41, 42, 43, \
1498 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1499 10, 11, 12, 13, 14, 18, \
1500 /* SH5 callee-saved GPRs */ \
1501 28, 29, 30, 31, 32, 33, 34, 35, \
1502 44, 45, 46, 47, 48, 49, 50, 51, \
1503 52, 53, 54, 55, 56, 57, 58, 59, \
1505 /* SH5 branch target registers */ \
1506 128,129,130,131,132,133,134,135, \
1507 /* Fixed registers */ \
1508 15, 16, 24, 25, 26, 27, 63,144, \
1509 145,146,147,148,149,152,153 }
1511 /* The class value for index registers, and the one for base regs. */
1512 #define INDEX_REG_CLASS \
1513 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1514 #define BASE_REG_CLASS GENERAL_REGS
1516 /* Defines for sh.md and constraints.md. */
1518 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1519 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1520 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1521 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1522 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1523 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1524 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1525 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1527 #define CONST_OK_FOR_J16(VALUE) \
1528 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1529 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1531 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1532 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1534 /* Given an rtx X being reloaded into a reg required to be
1535 in class CLASS, return the class of reg to actually use.
1536 In general this is just CLASS; but on some machines
1537 in some cases it is preferable to use a more restrictive class. */
1539 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1540 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1541 && (GET_CODE (X) == CONST_DOUBLE \
1542 || GET_CODE (X) == SYMBOL_REF \
1543 || PIC_ADDR_P (X)) \
1548 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1549 ((((REGCLASS_HAS_FP_REG (CLASS) \
1550 && (GET_CODE (X) == REG \
1551 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1552 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1553 && TARGET_FMOVD)))) \
1554 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1555 && GET_CODE (X) == REG \
1556 && FP_REGISTER_P (REGNO (X)))) \
1557 && ! TARGET_SHMEDIA \
1558 && ((MODE) == SFmode || (MODE) == SImode)) \
1560 : (((CLASS) == FPUL_REGS \
1561 || (REGCLASS_HAS_FP_REG (CLASS) \
1562 && ! TARGET_SHMEDIA && MODE == SImode)) \
1563 && (GET_CODE (X) == MEM \
1564 || (GET_CODE (X) == REG \
1565 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1566 || REGNO (X) == T_REG \
1567 || system_reg_operand (X, VOIDmode))))) \
1569 : (((CLASS) == TARGET_REGS \
1570 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1571 && !satisfies_constraint_Csy (X) \
1572 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
1574 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1575 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1576 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1578 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1579 && TARGET_REGISTER_P (REGNO (X))) \
1580 ? GENERAL_REGS : (ELSE))
1582 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1583 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1585 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1586 ((REGCLASS_HAS_FP_REG (CLASS) \
1587 && ! TARGET_SHMEDIA \
1588 && immediate_operand ((X), (MODE)) \
1589 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1590 && (MODE) == SFmode && fldi_ok ())) \
1592 : ((CLASS) == FPUL_REGS \
1593 && ((GET_CODE (X) == REG \
1594 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1595 || REGNO (X) == T_REG)) \
1596 || GET_CODE (X) == PLUS)) \
1598 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1599 ? (satisfies_constraint_I08 (X) \
1602 : ((CLASS) == FPSCR_REGS \
1603 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1604 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1606 : (REGCLASS_HAS_FP_REG (CLASS) \
1608 && immediate_operand ((X), (MODE)) \
1609 && (X) != CONST0_RTX (GET_MODE (X)) \
1610 && GET_MODE (X) != V4SFmode) \
1612 : (((MODE) == QImode || (MODE) == HImode) \
1613 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1615 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1616 && (GET_CODE (X) == LABEL_REF || PIC_ADDR_P (X))) \
1618 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1621 /* Return the maximum number of consecutive registers
1622 needed to represent mode MODE in a register of class CLASS.
1624 If TARGET_SHMEDIA, we need two FP registers per word.
1625 Otherwise we will need at most one register per word. */
1626 #define CLASS_MAX_NREGS(CLASS, MODE) \
1628 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1629 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1630 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1632 /* If defined, gives a class of registers that cannot be used as the
1633 operand of a SUBREG that changes the mode of the object illegally. */
1634 /* ??? We need to renumber the internal numbers for the frnn registers
1635 when in little endian in order to allow mode size changes. */
1637 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1638 sh_cannot_change_mode_class (FROM, TO, CLASS)
1640 /* Stack layout; function entry, exit and calling. */
1642 /* Define the number of registers that can hold parameters.
1643 These macros are used only in other macro definitions below. */
1645 #define NPARM_REGS(MODE) \
1646 (TARGET_FPU_ANY && (MODE) == SFmode \
1647 ? (TARGET_SH5 ? 12 : 8) \
1648 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1649 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1650 ? (TARGET_SH5 ? 12 : 8) \
1651 : (TARGET_SH5 ? 8 : 4))
1653 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1654 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1656 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1657 #define FIRST_FP_RET_REG FIRST_FP_REG
1659 /* Define this if pushing a word on the stack
1660 makes the stack pointer a smaller address. */
1661 #define STACK_GROWS_DOWNWARD
1663 /* Define this macro to nonzero if the addresses of local variable slots
1664 are at negative offsets from the frame pointer. */
1665 #define FRAME_GROWS_DOWNWARD 1
1667 /* Offset from the frame pointer to the first local variable slot to
1669 #define STARTING_FRAME_OFFSET 0
1671 /* If we generate an insn to push BYTES bytes,
1672 this says how many the stack pointer really advances by. */
1673 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1674 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1675 do correct alignment. */
1677 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1680 /* Offset of first parameter from the argument pointer register value. */
1681 #define FIRST_PARM_OFFSET(FNDECL) 0
1683 /* Value is the number of byte of arguments automatically
1684 popped when returning from a subroutine call.
1685 FUNDECL is the declaration node of the function (as a tree),
1686 FUNTYPE is the data type of the function (as a tree),
1687 or for a library call it is an identifier node for the subroutine name.
1688 SIZE is the number of bytes of arguments passed on the stack.
1690 On the SH, the caller does not pop any of its arguments that were passed
1692 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1694 /* Value is the number of bytes of arguments automatically popped when
1695 calling a subroutine.
1696 CUM is the accumulated argument list.
1698 On SHcompact, the call trampoline pops arguments off the stack. */
1699 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1701 /* Some subroutine macros specific to this machine. */
1703 #define BASE_RETURN_VALUE_REG(MODE) \
1704 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1705 ? FIRST_FP_RET_REG \
1706 : TARGET_FPU_ANY && (MODE) == SCmode \
1707 ? FIRST_FP_RET_REG \
1708 : (TARGET_FPU_DOUBLE \
1709 && ((MODE) == DFmode || (MODE) == SFmode \
1710 || (MODE) == DCmode || (MODE) == SCmode )) \
1711 ? FIRST_FP_RET_REG \
1714 #define BASE_ARG_REG(MODE) \
1715 ((TARGET_SH2E && ((MODE) == SFmode)) \
1716 ? FIRST_FP_PARM_REG \
1717 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1718 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1719 ? FIRST_FP_PARM_REG \
1722 /* Define how to find the value returned by a function.
1723 VALTYPE is the data type of the value (as a tree).
1724 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1725 otherwise, FUNC is 0.
1726 For the SH, this is like LIBCALL_VALUE, except that we must change the
1727 mode like PROMOTE_MODE does.
1728 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1729 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1731 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1733 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1734 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1735 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1736 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1737 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1738 || TREE_CODE (VALTYPE) == REAL_TYPE \
1739 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1740 && sh_promote_prototypes (FUNC) \
1741 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1742 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1744 /* Define how to find the value returned by a library function
1745 assuming the value has mode MODE. */
1746 #define LIBCALL_VALUE(MODE) \
1747 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1749 /* 1 if N is a possible register number for a function value. */
1750 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1751 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1752 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1754 /* 1 if N is a possible register number for function argument passing. */
1755 /* ??? There are some callers that pass REGNO as int, and others that pass
1756 it as unsigned. We get warnings unless we do casts everywhere. */
1757 #define FUNCTION_ARG_REGNO_P(REGNO) \
1758 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1759 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1760 || (TARGET_FPU_ANY \
1761 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1762 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1763 + NPARM_REGS (SFmode))))
1765 /* Define a data type for recording info about an argument list
1766 during the scan of that argument list. This data type should
1767 hold all necessary information about the function itself
1768 and about the args processed so far, enough to enable macros
1769 such as FUNCTION_ARG to determine where the next arg should go.
1771 On SH, this is a single integer, which is a number of words
1772 of arguments scanned so far (including the invisible argument,
1773 if any, which holds the structure-value-address).
1774 Thus NARGREGS or more means all following args should go on the stack. */
1776 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1780 /* Nonzero if a prototype is available for the function. */
1782 /* The number of an odd floating-point register, that should be used
1783 for the next argument of type float. */
1784 int free_single_fp_reg;
1785 /* Whether we're processing an outgoing function call. */
1787 /* The number of general-purpose registers that should have been
1788 used to pass partial arguments, that are passed totally on the
1789 stack. On SHcompact, a call trampoline will pop them off the
1790 stack before calling the actual function, and, if the called
1791 function is implemented in SHcompact mode, the incoming arguments
1792 decoder will push such arguments back onto the stack. For
1793 incoming arguments, STACK_REGS also takes into account other
1794 arguments passed by reference, that the decoder will also push
1797 /* The number of general-purpose registers that should have been
1798 used to pass arguments, if the arguments didn't have to be passed
1801 /* Set as by shcompact_byref if the current argument is to be passed
1805 /* call_cookie is a bitmask used by call expanders, as well as
1806 function prologue and epilogues, to allow SHcompact to comply
1807 with the SH5 32-bit ABI, that requires 64-bit registers to be
1808 used even though only the lower 32-bit half is visible in
1809 SHcompact mode. The strategy is to call SHmedia trampolines.
1811 The alternatives for each of the argument-passing registers are
1812 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1813 contents from the address in it; (d) add 8 to it, storing the
1814 result in the next register, then (c); (e) copy it from some
1815 floating-point register,
1817 Regarding copies from floating-point registers, r2 may only be
1818 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1819 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1820 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1821 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1824 The bit mask is structured as follows:
1826 - 1 bit to tell whether to set up a return trampoline.
1828 - 3 bits to count the number consecutive registers to pop off the
1831 - 4 bits for each of r9, r8, r7 and r6.
1833 - 3 bits for each of r5, r4, r3 and r2.
1835 - 3 bits set to 0 (the most significant ones)
1838 1098 7654 3210 9876 5432 1098 7654 3210
1839 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1840 2223 3344 4555 6666 7777 8888 9999 SSS-
1842 - If F is set, the register must be copied from an FP register,
1843 whose number is encoded in the remaining bits.
1845 - Else, if L is set, the register must be loaded from the address
1846 contained in it. If the P bit is *not* set, the address of the
1847 following dword should be computed first, and stored in the
1850 - Else, if P is set, the register alone should be popped off the
1853 - After all this processing, the number of registers represented
1854 in SSS will be popped off the stack. This is an optimization
1855 for pushing/popping consecutive registers, typically used for
1856 varargs and large arguments partially passed in registers.
1858 - If T is set, a return trampoline will be set up for 64-bit
1859 return values to be split into 2 32-bit registers. */
1862 /* This is set to nonzero when the call in question must use the Renesas ABI,
1863 even without the -mrenesas option. */
1867 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1868 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1869 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1870 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1871 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1872 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1873 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1874 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1875 #define CALL_COOKIE_INT_REG(REG, VAL) \
1876 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1877 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1878 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1880 #define CUMULATIVE_ARGS struct sh_args
1882 #define GET_SH_ARG_CLASS(MODE) \
1883 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1885 /* There's no mention of complex float types in the SH5 ABI, so we
1886 should presumably handle them as aggregate types. */ \
1887 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1889 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1890 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1891 ? SH_ARG_FLOAT : SH_ARG_INT)
1893 #define ROUND_ADVANCE(SIZE) \
1894 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1896 /* Round a register number up to a proper boundary for an arg of mode
1899 The SH doesn't care about double alignment, so we only
1900 round doubles to even regs when asked to explicitly. */
1902 #define ROUND_REG(CUM, MODE) \
1903 (((TARGET_ALIGN_DOUBLE \
1904 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1905 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1906 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1907 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1908 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1909 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1911 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1912 for a call to a function whose data type is FNTYPE.
1913 For a library call, FNTYPE is 0.
1915 On SH, the offset always starts at 0: the first parm reg is always
1916 the same reg for a given argument class.
1918 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1920 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1921 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1923 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1924 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1926 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1927 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1928 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1929 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1931 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1932 This macro is only used in this file. */
1934 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1936 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1937 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1938 || ! (AGGREGATE_TYPE_P (TYPE) \
1939 || (!TARGET_FPU_ANY \
1940 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1941 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1942 && ! (CUM).force_mem \
1944 ? ((MODE) == BLKmode \
1945 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1946 + int_size_in_bytes (TYPE)) \
1947 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1948 : ((ROUND_REG((CUM), (MODE)) \
1949 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1950 <= NPARM_REGS (MODE))) \
1951 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1953 /* By accident we got stuck with passing SCmode on SH4 little endian
1954 in two registers that are nominally successive - which is different from
1955 two single SFmode values, where we take endianness translation into
1956 account. That does not work at all if an odd number of registers is
1957 already in use, so that got fixed, but library functions are still more
1958 likely to use complex numbers without mixing them with SFmode arguments
1959 (which in C would have to be structures), so for the sake of ABI
1960 compatibility the way SCmode values are passed when an even number of
1961 FP registers is in use remains different from a pair of SFmode values for
1964 foo (double); a: fr5,fr4
1965 foo (float a, float b); a: fr5 b: fr4
1966 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1967 this should be the other way round...
1968 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1969 #define FUNCTION_ARG_SCmode_WART 1
1971 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1972 register in SHcompact mode, it must be padded in the most
1973 significant end. This means that passing it by reference wouldn't
1974 pad properly on a big-endian machine. In this particular case, we
1975 pass this argument on the stack, in a way that the call trampoline
1976 will load its value into the appropriate register. */
1977 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1978 ((MODE) == BLKmode \
1979 && TARGET_SHCOMPACT \
1980 && ! TARGET_LITTLE_ENDIAN \
1981 && int_size_in_bytes (TYPE) > 4 \
1982 && int_size_in_bytes (TYPE) < 8)
1984 /* Minimum alignment for an argument to be passed by callee-copy
1985 reference. We need such arguments to be aligned to 8 byte
1986 boundaries, because they'll be loaded using quad loads. */
1987 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1989 /* The SH5 ABI requires floating-point arguments to be passed to
1990 functions without a prototype in both an FP register and a regular
1991 register or the stack. When passing the argument in both FP and
1992 general-purpose registers, list the FP register first. */
1993 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1999 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2000 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2001 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2006 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2007 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2008 + (CUM).arg_count[(int) SH_ARG_INT]) \
2009 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2010 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2013 /* The SH5 ABI requires regular registers or stack slots to be
2014 reserved for floating-point arguments. Registers are taken care of
2015 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2016 Unfortunately, there's no way to just reserve a stack slot, so
2017 we'll end up needlessly storing a copy of the argument in the
2018 stack. For incoming arguments, however, the PARALLEL will be
2019 optimized to the register-only form, and the value in the stack
2020 slot won't be used at all. */
2021 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2022 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2023 ? gen_rtx_REG ((MODE), (REG)) \
2024 : gen_rtx_PARALLEL ((MODE), \
2027 (VOIDmode, NULL_RTX, \
2030 (VOIDmode, gen_rtx_REG ((MODE), \
2034 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2036 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2037 || (MODE) == DCmode) \
2038 && ((CUM).arg_count[(int) SH_ARG_INT] \
2039 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2040 : GET_MODE_SIZE (MODE)) \
2041 + 7) / 8) > NPARM_REGS (SImode))
2043 /* Perform any needed actions needed for a function that is receiving a
2044 variable number of arguments. */
2046 /* Call the function profiler with a given profile label.
2047 We use two .aligns, so as to make sure that both the .long is aligned
2048 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2049 from the trapa instruction. */
2051 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2053 if (TARGET_SHMEDIA) \
2055 fprintf((STREAM), "\tmovi\t33,r0\n"); \
2056 fprintf((STREAM), "\ttrapa\tr0\n"); \
2057 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2061 fprintf((STREAM), "\t.align\t2\n"); \
2062 fprintf((STREAM), "\ttrapa\t#33\n"); \
2063 fprintf((STREAM), "\t.align\t2\n"); \
2064 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2068 /* Define this macro if the code for function profiling should come
2069 before the function prologue. Normally, the profiling code comes
2072 #define PROFILE_BEFORE_PROLOGUE
2074 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2075 the stack pointer does not matter. The value is tested only in
2076 functions that have frame pointers.
2077 No definition is equivalent to always zero. */
2079 #define EXIT_IGNORE_STACK 1
2082 On the SH, the trampoline looks like
2083 2 0002 D202 mov.l l2,r2
2084 1 0000 D301 mov.l l1,r3
2087 5 0008 00000000 l1: .long area
2088 6 000c 00000000 l2: .long function */
2090 /* Length in units of the trampoline for entering a nested function. */
2091 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2093 /* Alignment required for a trampoline in bits . */
2094 #define TRAMPOLINE_ALIGNMENT \
2095 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2096 : TARGET_SHMEDIA ? 256 : 64)
2098 /* Emit RTL insns to initialize the variable parts of a trampoline.
2099 FNADDR is an RTX for the address of the function's pure code.
2100 CXT is an RTX for the static chain value for the function. */
2102 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2103 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2105 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2107 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2109 if (TARGET_SHMEDIA) \
2110 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2111 gen_reg_rtx (Pmode), 0, \
2115 /* A C expression whose value is RTL representing the value of the return
2116 address for the frame COUNT steps up from the current frame.
2117 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2118 can ignore COUNT. */
2120 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2121 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2123 /* A C expression whose value is RTL representing the location of the
2124 incoming return address at the beginning of any function, before the
2125 prologue. This RTL is either a REG, indicating that the return
2126 value is saved in REG, or a MEM representing a location in
2128 #define INCOMING_RETURN_ADDR_RTX \
2129 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2131 /* Addressing modes, and classification of registers for them. */
2132 #define HAVE_POST_INCREMENT TARGET_SH1
2133 #define HAVE_PRE_DECREMENT TARGET_SH1
2135 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2137 #define USE_LOAD_PRE_DECREMENT(mode) 0
2138 #define USE_STORE_POST_INCREMENT(mode) 0
2139 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2142 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2143 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2144 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2146 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2147 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2148 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2150 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
2152 /* Macros to check register numbers against specific register classes. */
2154 /* These assume that REGNO is a hard or pseudo reg number.
2155 They give nonzero only if REGNO is a hard reg of the suitable class
2156 or a pseudo reg currently allocated to a suitable hard reg.
2157 Since they use reg_renumber, they are safe only once reg_renumber
2158 has been allocated, which happens in local-alloc.c. */
2160 #define REGNO_OK_FOR_BASE_P(REGNO) \
2161 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2162 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2163 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2165 ? (GENERAL_REGISTER_P (REGNO) \
2166 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2167 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2169 /* Maximum number of registers that can appear in a valid memory
2172 #define MAX_REGS_PER_ADDRESS 2
2174 /* Recognize any constant value that is a valid address. */
2176 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2178 /* Nonzero if the constant value X is a legitimate general operand. */
2179 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
2181 #define LEGITIMATE_CONSTANT_P(X) \
2183 ? ((GET_MODE (X) != DFmode \
2184 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2185 || (X) == CONST0_RTX (GET_MODE (X)) \
2186 || ! TARGET_SHMEDIA_FPU \
2187 || TARGET_SHMEDIA64) \
2188 : (GET_CODE (X) != CONST_DOUBLE \
2189 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2190 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
2192 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2193 and check its validity for a certain class.
2194 We have two alternate definitions for each of them.
2195 The usual definition accepts all pseudo regs; the other rejects
2196 them unless they have been allocated suitable hard regs.
2197 The symbol REG_OK_STRICT causes the latter definition to be used. */
2199 #ifndef REG_OK_STRICT
2201 /* Nonzero if X is a hard reg that can be used as a base reg
2202 or if it is a pseudo reg. */
2203 #define REG_OK_FOR_BASE_P(X) \
2204 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2206 /* Nonzero if X is a hard reg that can be used as an index
2207 or if it is a pseudo reg. */
2208 #define REG_OK_FOR_INDEX_P(X) \
2209 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2210 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2212 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2213 or if X is a pseudo reg. */
2214 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2215 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2216 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2220 /* Nonzero if X is a hard reg that can be used as a base reg. */
2221 #define REG_OK_FOR_BASE_P(X) \
2222 REGNO_OK_FOR_BASE_P (REGNO (X))
2224 /* Nonzero if X is a hard reg that can be used as an index. */
2225 #define REG_OK_FOR_INDEX_P(X) \
2226 REGNO_OK_FOR_INDEX_P (REGNO (X))
2228 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2229 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2230 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2234 /* Macros for extra constraints. */
2236 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
2237 ((GET_CODE ((OP)) == LABEL_REF) \
2238 || (GET_CODE ((OP)) == CONST \
2239 && GET_CODE (XEXP ((OP), 0)) == PLUS \
2240 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2241 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2243 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
2245 && GET_CODE (OP) != CONST_INT \
2246 && GET_CODE (OP) != CONST_DOUBLE \
2248 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2249 && !PIC_ADDR_P (OP) \
2250 && GET_CODE (OP) != LABEL_REF)))
2252 /* Check whether OP is a datalabel unspec. */
2253 #define DATALABEL_REF_NO_CONST_P(OP) \
2254 (GET_CODE (OP) == UNSPEC \
2255 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2256 && XVECLEN ((OP), 0) == 1 \
2257 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2259 #define GOT_ENTRY_P(OP) \
2260 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2261 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2263 #define GOTPLT_ENTRY_P(OP) \
2264 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2265 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2267 #define UNSPEC_GOTOFF_P(OP) \
2268 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2270 #define GOTOFF_P(OP) \
2271 (GET_CODE (OP) == CONST \
2272 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2273 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2274 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2275 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2277 #define PIC_ADDR_P(OP) \
2278 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2279 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2281 #define PCREL_SYMOFF_P(OP) \
2282 (GET_CODE (OP) == CONST \
2283 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2284 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
2286 #define NON_PIC_REFERENCE_P(OP) \
2287 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2288 || (GET_CODE (OP) == CONST \
2289 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2290 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2291 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2292 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2293 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2294 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2295 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2296 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2298 #define PIC_REFERENCE_P(OP) \
2299 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2300 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2302 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2304 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2305 || PCREL_SYMOFF_P (OP)) \
2306 : NON_PIC_REFERENCE_P (OP))
2308 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2309 that is a valid memory address for an instruction.
2310 The MODE argument is the machine mode for the MEM expression
2311 that wants to use this address. */
2313 #define MODE_DISP_OK_4(X,MODE) \
2314 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2315 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2317 #define MODE_DISP_OK_8(X,MODE) \
2318 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2319 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2321 #undef MODE_DISP_OK_4
2322 #define MODE_DISP_OK_4(X,MODE) \
2323 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2324 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2325 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2326 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2328 #undef MODE_DISP_OK_8
2329 #define MODE_DISP_OK_8(X,MODE) \
2330 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2331 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2332 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2333 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2335 #define BASE_REGISTER_RTX_P(X) \
2336 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2337 || (GET_CODE (X) == SUBREG \
2338 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2339 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2340 && GET_CODE (SUBREG_REG (X)) == REG \
2341 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2343 /* Since this must be r0, which is a single register class, we must check
2344 SUBREGs more carefully, to be sure that we don't accept one that extends
2345 outside the class. */
2346 #define INDEX_REGISTER_RTX_P(X) \
2347 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2348 || (GET_CODE (X) == SUBREG \
2349 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2350 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2351 && GET_CODE (SUBREG_REG (X)) == REG \
2352 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2354 /* Jump to LABEL if X is a valid address RTX. This must also take
2355 REG_OK_STRICT into account when deciding about valid registers, but it uses
2356 the above macros so we are in luck.
2364 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2365 into the FRx registers. We implement this by setting the maximum offset
2366 to zero when the value is SFmode. This also restricts loading of SFmode
2367 values into the integer registers, but that can't be helped. */
2369 /* The SH allows a displacement in a QI or HI amode, but only when the
2370 other operand is R0. GCC doesn't handle this very well, so we forgo
2373 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2374 DI can be any number 0..60. */
2376 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2378 if (GET_CODE (OP) == CONST_INT) \
2380 if (TARGET_SHMEDIA) \
2383 /* Check if this the address of an unaligned load / store. */\
2384 if ((MODE) == VOIDmode) \
2386 if (CONST_OK_FOR_I06 (INTVAL (OP))) \
2390 MODE_SIZE = GET_MODE_SIZE (MODE); \
2391 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2392 && INTVAL (OP) >= -512 * MODE_SIZE \
2393 && INTVAL (OP) < 512 * MODE_SIZE) \
2400 if (GET_MODE_SIZE (MODE) == 1 \
2401 && (unsigned) INTVAL (OP) < 4096) \
2404 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2405 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2409 #define ALLOW_INDEXED_ADDRESS \
2410 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2412 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2414 if (BASE_REGISTER_RTX_P (X)) \
2416 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2417 && ! TARGET_SHMEDIA \
2418 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2420 else if (GET_CODE (X) == PLUS \
2421 && ((MODE) != PSImode || reload_completed)) \
2423 rtx xop0 = XEXP ((X), 0); \
2424 rtx xop1 = XEXP ((X), 1); \
2425 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2426 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2427 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
2428 || ((xop0 == stack_pointer_rtx \
2429 || xop0 == hard_frame_pointer_rtx) \
2430 && REG_P (xop1) && REGNO (xop1) == R0_REG) \
2431 || ((xop1 == stack_pointer_rtx \
2432 || xop1 == hard_frame_pointer_rtx) \
2433 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \
2434 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
2435 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2436 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2437 && TARGET_FMOVD && MODE == DFmode))) \
2439 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2441 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2447 /* A C compound statement that attempts to replace X, which is an address
2448 that needs reloading, with a valid memory address for an operand of
2449 mode MODE. WIN is a C statement label elsewhere in the code.
2451 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2452 of the address. That will allow inheritance of the address reloads. */
2454 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2456 if (GET_CODE (X) == PLUS \
2457 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2458 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2459 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2460 && ! TARGET_SHMEDIA \
2461 && ! (TARGET_SH4 && (MODE) == DFmode) \
2462 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2463 && (ALLOW_INDEXED_ADDRESS \
2464 || XEXP ((X), 0) == stack_pointer_rtx \
2465 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2467 rtx index_rtx = XEXP (X, 1); \
2468 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2471 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2473 push_reload (X, NULL_RTX, &X, NULL, \
2474 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2478 if (TARGET_SH2E && MODE == SFmode) \
2481 push_reload (X, NULL_RTX, &X, NULL, \
2482 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2486 /* Instead of offset_base 128..131 use 124..127, so that \
2487 simple add suffices. */ \
2490 offset_base = ((offset + 4) & ~60) - 4; \
2493 offset_base = offset & ~60; \
2494 /* Sometimes the normal form does not suit DImode. We \
2495 could avoid that by using smaller ranges, but that \
2496 would give less optimized code when SImode is \
2498 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2500 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2501 GEN_INT (offset_base)); \
2502 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2503 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2504 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2509 /* We must re-recognize what we created before. */ \
2510 else if (GET_CODE (X) == PLUS \
2511 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2512 && GET_CODE (XEXP (X, 0)) == PLUS \
2513 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2514 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2515 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2516 && ! TARGET_SHMEDIA \
2517 && ! (TARGET_SH2E && MODE == SFmode)) \
2519 /* Because this address is so complex, we know it must have \
2520 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2521 it is already unshared, and needs no further unsharing. */ \
2522 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2523 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2528 /* Specify the machine mode that this machine uses
2529 for the index in the tablejump instruction. */
2530 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2532 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2533 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2534 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2535 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2536 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2537 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2540 /* Define as C expression which evaluates to nonzero if the tablejump
2541 instruction expects the table to contain offsets from the address of the
2543 Do not define this if the table should contain absolute addresses. */
2544 #define CASE_VECTOR_PC_RELATIVE 1
2546 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2547 #define FLOAT_TYPE_SIZE 32
2549 /* Since the SH2e has only `float' support, it is desirable to make all
2550 floating point types equivalent to `float'. */
2551 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2553 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH2A_SINGLE_ONLY__) || defined( __SH4_SINGLE_ONLY__)
2554 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2556 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2559 /* 'char' is signed by default. */
2560 #define DEFAULT_SIGNED_CHAR 1
2562 /* The type of size_t unsigned int. */
2563 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2566 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2568 #define WCHAR_TYPE "short unsigned int"
2569 #define WCHAR_TYPE_SIZE 16
2571 #define SH_ELF_WCHAR_TYPE "long int"
2573 /* Max number of bytes we can move from memory to memory
2574 in one reasonably fast instruction. */
2575 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2577 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2578 MOVE_MAX is not a compile-time constant. */
2579 #define MAX_MOVE_MAX 8
2581 /* Max number of bytes we want move_by_pieces to be able to copy
2583 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2585 /* Define if operations between registers always perform the operation
2586 on the full register even if a narrower mode is specified. */
2587 #define WORD_REGISTER_OPERATIONS
2589 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2590 will either zero-extend or sign-extend. The value of this macro should
2591 be the code that says which one of the two operations is implicitly
2592 done, UNKNOWN if none. */
2593 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2594 /* FP registers can load SImode values, but don't implicitly sign-extend
2596 #define LOAD_EXTEND_OP(MODE) \
2597 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2598 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2600 /* Define if loading short immediate values into registers sign extends. */
2601 #define SHORT_IMMEDIATES_SIGN_EXTEND
2603 /* Nonzero if access to memory by bytes is no faster than for words. */
2604 #define SLOW_BYTE_ACCESS 1
2606 /* Immediate shift counts are truncated by the output routines (or was it
2607 the assembler?). Shift counts in a register are truncated by SH. Note
2608 that the native compiler puts too large (> 32) immediate shift counts
2609 into a register and shifts by the register, letting the SH decide what
2610 to do instead of doing that itself. */
2611 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2612 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2613 expects - the sign bit is significant - so it appears that we need to
2614 leave this zero for correct SH3 code. */
2615 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2617 /* All integers have the same format so truncation is easy. */
2618 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2619 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2620 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2622 /* Define this if addresses of constant functions
2623 shouldn't be put through pseudo regs where they can be cse'd.
2624 Desirable on machines where ordinary constants are expensive
2625 but a CALL with constant address is cheap. */
2626 /*#define NO_FUNCTION_CSE 1*/
2628 /* The machine modes of pointers and functions. */
2629 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2630 #define FUNCTION_MODE Pmode
2632 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2633 are actually function calls with some special constraints on arguments
2636 These macros tell reorg that the references to arguments and
2637 register clobbers for insns of type sfunc do not appear to happen
2638 until after the millicode call. This allows reorg to put insns
2639 which set the argument registers into the delay slot of the millicode
2640 call -- thus they act more like traditional CALL_INSNs.
2642 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2643 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2646 #define INSN_SETS_ARE_DELAYED(X) \
2647 ((GET_CODE (X) == INSN \
2648 && GET_CODE (PATTERN (X)) != SEQUENCE \
2649 && GET_CODE (PATTERN (X)) != USE \
2650 && GET_CODE (PATTERN (X)) != CLOBBER \
2651 && get_attr_is_sfunc (X)))
2653 #define INSN_REFERENCES_ARE_DELAYED(X) \
2654 ((GET_CODE (X) == INSN \
2655 && GET_CODE (PATTERN (X)) != SEQUENCE \
2656 && GET_CODE (PATTERN (X)) != USE \
2657 && GET_CODE (PATTERN (X)) != CLOBBER \
2658 && get_attr_is_sfunc (X)))
2661 /* Position Independent Code. */
2663 /* We can't directly access anything that contains a symbol,
2664 nor can we indirect via the constant pool. */
2665 #define LEGITIMATE_PIC_OPERAND_P(X) \
2666 ((! nonpic_symbol_mentioned_p (X) \
2667 && (GET_CODE (X) != SYMBOL_REF \
2668 || ! CONSTANT_POOL_ADDRESS_P (X) \
2669 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2670 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2672 #define SYMBOLIC_CONST_P(X) \
2673 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2674 && nonpic_symbol_mentioned_p (X))
2676 /* Compute extra cost of moving data between one register class
2679 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2680 uses this information. Hence, the general register <-> floating point
2681 register information here is not used for SFmode. */
2683 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2684 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2685 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2687 #define REGCLASS_HAS_FP_REG(CLASS) \
2688 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2689 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2691 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2692 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2694 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2695 would be so that people with slow memory systems could generate
2696 different code that does fewer memory accesses. */
2698 /* A C expression for the cost of a branch instruction. A value of 1
2699 is the default; other values are interpreted relative to that.
2700 The SH1 does not have delay slots, hence we get a pipeline stall
2701 at every branch. The SH4 is superscalar, so the single delay slot
2702 is not sufficient to keep both pipelines filled. */
2703 #define BRANCH_COST(speed_p, predictable_p) \
2704 (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2706 /* Assembler output control. */
2708 /* A C string constant describing how to begin a comment in the target
2709 assembler language. The compiler assumes that the comment will end at
2710 the end of the line. */
2711 #define ASM_COMMENT_START "!"
2713 #define ASM_APP_ON ""
2714 #define ASM_APP_OFF ""
2715 #define FILE_ASM_OP "\t.file\n"
2716 #define SET_ASM_OP "\t.set\t"
2718 /* How to change between sections. */
2720 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2721 #define DATA_SECTION_ASM_OP "\t.data"
2723 #if defined CRT_BEGIN || defined CRT_END
2724 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2725 # undef TEXT_SECTION_ASM_OP
2726 # if __SHMEDIA__ == 1 && __SH5__ == 32
2727 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2729 # define TEXT_SECTION_ASM_OP "\t.text"
2734 /* If defined, a C expression whose value is a string containing the
2735 assembler operation to identify the following data as
2736 uninitialized global data. If not defined, and neither
2737 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2738 uninitialized global data will be output in the data section if
2739 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2741 #ifndef BSS_SECTION_ASM_OP
2742 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2745 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2746 separate, explicit argument. If you define this macro, it is used
2747 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2748 handling the required alignment of the variable. The alignment is
2749 specified as the number of bits.
2751 Try to use function `asm_output_aligned_bss' defined in file
2752 `varasm.c' when defining this macro. */
2753 #ifndef ASM_OUTPUT_ALIGNED_BSS
2754 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2755 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2758 /* Define this so that jump tables go in same section as the current function,
2759 which could be text or it could be a user defined section. */
2760 #define JUMP_TABLES_IN_TEXT_SECTION 1
2762 #undef DO_GLOBAL_CTORS_BODY
2763 #define DO_GLOBAL_CTORS_BODY \
2765 typedef void (*pfunc) (void); \
2766 extern pfunc __ctors[]; \
2767 extern pfunc __ctors_end[]; \
2769 for (p = __ctors_end; p > __ctors; ) \
2775 #undef DO_GLOBAL_DTORS_BODY
2776 #define DO_GLOBAL_DTORS_BODY \
2778 typedef void (*pfunc) (void); \
2779 extern pfunc __dtors[]; \
2780 extern pfunc __dtors_end[]; \
2782 for (p = __dtors; p < __dtors_end; p++) \
2788 #define ASM_OUTPUT_REG_PUSH(file, v) \
2790 if (TARGET_SHMEDIA) \
2792 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2793 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2796 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2799 #define ASM_OUTPUT_REG_POP(file, v) \
2801 if (TARGET_SHMEDIA) \
2803 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2804 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2807 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2810 /* DBX register number for a given compiler register number. */
2811 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2813 /* svr4.h undefines this macro, yet we really want to use the same numbers
2814 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2815 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2816 register exists, so we should return -1 for invalid register numbers. */
2817 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2819 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2820 used to use the encodings 245..260, but that doesn't make sense:
2821 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2822 the FP registers stay the same when switching between compact and media
2823 mode. Hence, we also need to use the same dwarf frame columns.
2824 Likewise, we need to support unwind information for SHmedia registers
2825 even in compact code. */
2826 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2827 (IN_RANGE ((REGNO), \
2828 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2829 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2830 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2831 : ((int) (REGNO) >= FIRST_FP_REG \
2833 <= (FIRST_FP_REG + \
2834 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2835 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2836 + (TARGET_SH5 ? 77 : 25)) \
2837 : XD_REGISTER_P (REGNO) \
2838 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2839 : TARGET_REGISTER_P (REGNO) \
2840 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2841 : (REGNO) == PR_REG \
2842 ? (TARGET_SH5 ? 18 : 17) \
2843 : (REGNO) == PR_MEDIA_REG \
2844 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2845 : (REGNO) == GBR_REG \
2846 ? (TARGET_SH5 ? 238 : 18) \
2847 : (REGNO) == MACH_REG \
2848 ? (TARGET_SH5 ? 239 : 20) \
2849 : (REGNO) == MACL_REG \
2850 ? (TARGET_SH5 ? 240 : 21) \
2851 : (REGNO) == T_REG \
2852 ? (TARGET_SH5 ? 242 : 22) \
2853 : (REGNO) == FPUL_REG \
2854 ? (TARGET_SH5 ? 244 : 23) \
2855 : (REGNO) == FPSCR_REG \
2856 ? (TARGET_SH5 ? 243 : 24) \
2859 /* This is how to output a reference to a symbol_ref. On SH5,
2860 references to non-code symbols must be preceded by `datalabel'. */
2861 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2864 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2865 fputs ("datalabel ", (FILE)); \
2866 assemble_name ((FILE), XSTR ((SYM), 0)); \
2870 /* This is how to output an assembler line
2871 that says to advance the location counter
2872 to a multiple of 2**LOG bytes. */
2874 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2876 fprintf ((FILE), "\t.align %d\n", (LOG))
2878 /* Globalizing directive for a label. */
2879 #define GLOBAL_ASM_OP "\t.global\t"
2881 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2883 /* Output a relative address table. */
2885 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2886 switch (GET_MODE (BODY)) \
2891 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2895 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2900 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2904 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2909 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2913 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2919 /* Output an absolute table element. */
2921 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2922 if (! optimize || TARGET_BIGTABLE) \
2923 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2925 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2928 /* A C statement to be executed just prior to the output of
2929 assembler code for INSN, to modify the extracted operands so
2930 they will be output differently.
2932 Here the argument OPVEC is the vector containing the operands
2933 extracted from INSN, and NOPERANDS is the number of elements of
2934 the vector which contain meaningful data for this insn.
2935 The contents of this vector are what will be used to convert the insn
2936 template into assembler code, so you can change the assembler output
2937 by changing the contents of the vector. */
2939 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2940 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2942 /* Print operand X (an rtx) in assembler syntax to file FILE.
2943 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2944 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2946 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
2948 /* Print a memory address as an operand to reference that memory location. */
2950 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
2952 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2953 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
2954 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
2956 /* Recognize machine-specific patterns that may appear within
2957 constants. Used for PIC-specific UNSPECs. */
2958 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2960 if (GET_CODE (X) == UNSPEC) \
2962 switch (XINT ((X), 1)) \
2964 case UNSPEC_DATALABEL: \
2965 fputs ("datalabel ", (STREAM)); \
2966 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2969 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
2970 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2973 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2974 fputs ("@GOT", (STREAM)); \
2976 case UNSPEC_GOTOFF: \
2977 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2978 fputs ("@GOTOFF", (STREAM)); \
2981 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2982 fputs ("@PLT", (STREAM)); \
2984 case UNSPEC_GOTPLT: \
2985 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2986 fputs ("@GOTPLT", (STREAM)); \
2988 case UNSPEC_DTPOFF: \
2989 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2990 fputs ("@DTPOFF", (STREAM)); \
2992 case UNSPEC_GOTTPOFF: \
2993 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2994 fputs ("@GOTTPOFF", (STREAM)); \
2996 case UNSPEC_TPOFF: \
2997 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2998 fputs ("@TPOFF", (STREAM)); \
3000 case UNSPEC_CALLER: \
3003 /* LPCS stands for Label for PIC Call Site. */ \
3004 ASM_GENERATE_INTERNAL_LABEL \
3005 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3006 assemble_name ((STREAM), name); \
3009 case UNSPEC_EXTRACT_S16: \
3010 case UNSPEC_EXTRACT_U16: \
3014 val = XVECEXP (X, 0, 0); \
3015 shift = XVECEXP (X, 0, 1); \
3016 fputc ('(', STREAM); \
3017 if (shift != const0_rtx) \
3018 fputc ('(', STREAM); \
3019 if (GET_CODE (val) == CONST \
3020 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ) \
3022 fputc ('(', STREAM); \
3023 output_addr_const (STREAM, val); \
3024 fputc (')', STREAM); \
3027 output_addr_const (STREAM, val); \
3028 if (shift != const0_rtx) \
3030 fputs (" >> ", STREAM); \
3031 output_addr_const (STREAM, shift); \
3032 fputc (')', STREAM); \
3034 fputs (" & 65535)", STREAM); \
3037 case UNSPEC_SYMOFF: \
3038 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
3039 fputc ('-', STREAM); \
3040 if (GET_CODE (XVECEXP (X, 0, 1)) == CONST) \
3042 fputc ('(', STREAM); \
3043 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
3044 fputc (')', STREAM); \
3047 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
3049 case UNSPEC_PCREL_SYMOFF: \
3050 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
3051 fputs ("-(", STREAM); \
3052 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
3053 fputs ("-.)", STREAM); \
3065 extern struct rtx_def *sh_compare_op0;
3066 extern struct rtx_def *sh_compare_op1;
3068 /* Which processor to schedule for. The elements of the enumeration must
3069 match exactly the cpu attribute in the sh.md file. */
3071 enum processor_type {
3083 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3084 extern enum processor_type sh_cpu;
3086 extern int optimize; /* needed for gen_casesi. */
3088 enum mdep_reorg_phase_e
3090 SH_BEFORE_MDEP_REORG,
3091 SH_INSERT_USES_LABELS,
3092 SH_SHORTEN_BRANCHES0,
3094 SH_SHORTEN_BRANCHES1,
3098 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3100 /* Handle Renesas compiler's pragmas. */
3101 #define REGISTER_TARGET_PRAGMAS() do { \
3102 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3103 c_register_pragma (0, "trapa", sh_pr_trapa); \
3104 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3107 extern tree sh_deferred_function_attributes;
3108 extern tree *sh_deferred_function_attributes_tail;
3110 /* Set when processing a function with interrupt attribute. */
3112 extern int current_function_interrupt;
3115 /* Instructions with unfilled delay slots take up an
3116 extra two bytes for the nop in the delay slot.
3117 sh-dsp parallel processing insns are four bytes long. */
3119 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3120 (LENGTH) += sh_insn_length_adjustment (X);
3122 /* Define this macro if it is advisable to hold scalars in registers
3123 in a wider mode than that declared by the program. In such cases,
3124 the value is constrained to be within the bounds of the declared
3125 type, but kept valid in the wider mode. The signedness of the
3126 extension may differ from that of the type.
3128 Leaving the unsignedp unchanged gives better code than always setting it
3129 to 0. This is despite the fact that we have only signed char and short
3130 load instructions. */
3131 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3132 if (GET_MODE_CLASS (MODE) == MODE_INT \
3133 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3134 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3135 (MODE) = (TARGET_SH1 ? SImode \
3136 : TARGET_SHMEDIA32 ? SImode : DImode);
3138 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3140 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3142 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3143 and popping arguments. However, we do have push/pop instructions, and
3144 rather limited offsets (4 bits) in load/store instructions, so it isn't
3145 clear if this would give better code. If implemented, should check for
3146 compatibility problems. */
3148 #define SH_DYNAMIC_SHIFT_COST \
3149 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3152 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3154 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3156 #define ACTUAL_NORMAL_MODE(ENTITY) \
3157 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3159 #define NORMAL_MODE(ENTITY) \
3160 (sh_cfun_interrupt_handler_p () \
3161 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3162 : ACTUAL_NORMAL_MODE (ENTITY))
3164 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3166 #define MODE_EXIT(ENTITY) \
3167 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3169 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3170 && (REGNO) == FPSCR_REG)
3172 #define MODE_NEEDED(ENTITY, INSN) \
3173 (recog_memoized (INSN) >= 0 \
3174 ? get_attr_fp_mode (INSN) \
3177 #define MODE_AFTER(MODE, INSN) \
3179 && recog_memoized (INSN) >= 0 \
3180 && get_attr_fp_set (INSN) != FP_SET_NONE \
3181 ? (int) get_attr_fp_set (INSN) \
3184 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3185 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3187 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3188 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3190 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3191 sh_can_redirect_branch ((INSN), (SEQ))
3193 #define DWARF_FRAME_RETURN_COLUMN \
3194 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3196 #define EH_RETURN_DATA_REGNO(N) \
3197 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3199 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3200 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3202 /* We have to distinguish between code and data, so that we apply
3203 datalabel where and only where appropriate. Use sdataN for data. */
3204 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3205 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3206 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3207 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3209 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3210 indirect are handled automatically. */
3211 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3213 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3214 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3216 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3217 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3222 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3223 /* SH constant pool breaks the devices in crtstuff.c to control section
3224 in where code resides. We have to write it as asm code. */
3225 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3226 asm (SECTION_OP "\n\
3232 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3233 2:\n" TEXT_SECTION_ASM_OP);
3234 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3236 /* FIXME: middle-end support for highpart optimizations is missing. */
3237 #define high_life_started reload_in_progress
3239 #endif /* ! GCC_SH_H */
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