1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
27 #include "config/vxworks-dummy.h"
29 #define TARGET_VERSION \
30 fputs (" (Hitachi SH)", stderr);
32 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
33 include it here, because bconfig.h is also included by gencodes.c . */
34 /* ??? No longer true. */
35 extern int code_for_indirect_jump_scratch;
37 #define TARGET_CPU_CPP_BUILTINS() \
39 builtin_define ("__sh__"); \
40 builtin_assert ("cpu=sh"); \
41 builtin_assert ("machine=sh"); \
42 switch ((int) sh_cpu) \
45 builtin_define ("__sh1__"); \
48 builtin_define ("__sh2__"); \
50 case PROCESSOR_SH2E: \
51 builtin_define ("__SH2E__"); \
53 case PROCESSOR_SH2A: \
54 builtin_define ("__SH2A__"); \
55 builtin_define (TARGET_SH2A_DOUBLE \
56 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
57 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
58 : "__SH2A_NOFPU__"); \
61 builtin_define ("__sh3__"); \
62 builtin_define ("__SH3__"); \
63 if (TARGET_HARD_SH4) \
64 builtin_define ("__SH4_NOFPU__"); \
66 case PROCESSOR_SH3E: \
67 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
70 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
72 case PROCESSOR_SH4A: \
73 builtin_define ("__SH4A__"); \
74 builtin_define (TARGET_SH4 \
75 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
76 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
81 builtin_define_with_value ("__SH5__", \
82 TARGET_SHMEDIA64 ? "64" : "32", 0); \
83 builtin_define_with_value ("__SHMEDIA__", \
84 TARGET_SHMEDIA ? "1" : "0", 0); \
85 if (! TARGET_FPU_DOUBLE) \
86 builtin_define ("__SH4_NOFPU__"); \
90 builtin_define ("__SH_FPU_ANY__"); \
91 if (TARGET_FPU_DOUBLE) \
92 builtin_define ("__SH_FPU_DOUBLE__"); \
94 builtin_define ("__HITACHI__"); \
96 builtin_define ("__FMOVD_ENABLED__"); \
97 builtin_define (TARGET_LITTLE_ENDIAN \
98 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
101 /* Value should be nonzero if functions must have frame pointers.
102 Zero means the frame pointer need not be set up (and parms may be accessed
103 via the stack pointer) in functions that seem suitable. */
105 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
106 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
110 /* Nonzero if this is an ELF target - compile time only */
113 /* Nonzero if we should generate code using type 2E insns. */
114 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
116 /* Nonzero if we should generate code using type 2A insns. */
117 #define TARGET_SH2A TARGET_HARD_SH2A
118 /* Nonzero if we should generate code using type 2A SF insns. */
119 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
120 /* Nonzero if we should generate code using type 2A DF insns. */
121 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
123 /* Nonzero if we should generate code using type 3E insns. */
124 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
126 /* Nonzero if the cache line size is 32. */
127 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
129 /* Nonzero if we schedule for a superscalar implementation. */
130 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
132 /* Nonzero if the target has separate instruction and data caches. */
133 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
135 /* Nonzero if a double-precision FPU is available. */
136 #define TARGET_FPU_DOUBLE \
137 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
139 /* Nonzero if an FPU is available. */
140 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
142 /* Nonzero if we should generate code using type 4 insns. */
144 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
146 /* Nonzero if we're generating code for the common subset of
147 instructions present on both SH4a and SH4al-dsp. */
148 #define TARGET_SH4A_ARCH TARGET_SH4A
150 /* Nonzero if we're generating code for SH4a, unless the use of the
151 FPU is disabled (which makes it compatible with SH4al-dsp). */
152 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
154 /* Nonzero if we should generate code using the SHcompact instruction
155 set and 32-bit ABI. */
156 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
158 /* Nonzero if we should generate code using the SHmedia instruction
160 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
162 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
164 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
166 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
168 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
170 /* Nonzero if we should generate code using SHmedia FPU instructions. */
171 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
173 /* This is not used by the SH2E calling convention */
174 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
175 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
176 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
178 #ifndef TARGET_CPU_DEFAULT
179 #define TARGET_CPU_DEFAULT SELECT_SH1
180 #define SUPPORT_SH1 1
181 #define SUPPORT_SH2E 1
182 #define SUPPORT_SH4 1
183 #define SUPPORT_SH4_SINGLE 1
184 #define SUPPORT_SH2A 1
185 #define SUPPORT_SH2A_SINGLE 1
188 #define TARGET_DIVIDE_INV \
189 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
190 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
191 || sh_div_strategy == SH_DIV_INV_CALL \
192 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
193 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
194 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
195 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
196 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
197 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
198 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
199 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
200 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
201 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
202 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
203 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
205 #define SELECT_SH1 (MASK_SH1)
206 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
207 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
209 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
210 | MASK_HARD_SH2A_DOUBLE \
211 | MASK_SH2 | MASK_SH1)
212 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
213 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
214 | MASK_SH1 | MASK_FPU_SINGLE)
215 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
216 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
217 | MASK_SH2 | MASK_SH1)
218 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
219 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
220 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
221 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
222 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
224 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
225 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
226 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
227 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
228 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
229 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
230 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
231 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
232 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
233 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
234 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
237 #define SUPPORT_SH2 1
240 #define SUPPORT_SH3 1
241 #define SUPPORT_SH2A_NOFPU 1
244 #define SUPPORT_SH4_NOFPU 1
246 #if SUPPORT_SH4_NOFPU
247 #define SUPPORT_SH4A_NOFPU 1
248 #define SUPPORT_SH4AL 1
252 #define SUPPORT_SH3E 1
253 #define SUPPORT_SH2A_SINGLE_ONLY 1
256 #define SUPPORT_SH4_SINGLE_ONLY 1
258 #if SUPPORT_SH4_SINGLE_ONLY
259 #define SUPPORT_SH4A_SINGLE_ONLY 1
263 #define SUPPORT_SH4A 1
266 #if SUPPORT_SH4_SINGLE
267 #define SUPPORT_SH4A_SINGLE 1
270 #if SUPPORT_SH5_COMPAT
271 #define SUPPORT_SH5_32MEDIA 1
274 #if SUPPORT_SH5_COMPACT_NOFPU
275 #define SUPPORT_SH5_32MEDIA_NOFPU 1
278 #define SUPPORT_ANY_SH5_32MEDIA \
279 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
280 #define SUPPORT_ANY_SH5_64MEDIA \
281 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
282 #define SUPPORT_ANY_SH5 \
283 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
285 /* Reset all target-selection flags. */
286 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
287 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
288 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
290 /* This defaults us to big-endian. */
291 #ifndef TARGET_ENDIAN_DEFAULT
292 #define TARGET_ENDIAN_DEFAULT 0
295 #ifndef TARGET_OPT_DEFAULT
296 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
299 #define TARGET_DEFAULT \
300 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
302 #ifndef SH_MULTILIB_CPU_DEFAULT
303 #define SH_MULTILIB_CPU_DEFAULT "m1"
306 #if TARGET_ENDIAN_DEFAULT
307 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
309 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
312 #define CPP_SPEC " %(subtarget_cpp_spec) "
314 #ifndef SUBTARGET_CPP_SPEC
315 #define SUBTARGET_CPP_SPEC ""
318 #ifndef SUBTARGET_EXTRA_SPECS
319 #define SUBTARGET_EXTRA_SPECS
322 #define EXTRA_SPECS \
323 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
324 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
325 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
326 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
327 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
328 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
329 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
330 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
331 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
332 SUBTARGET_EXTRA_SPECS
334 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
335 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
337 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
340 #define SH_ASM_SPEC \
341 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
342 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
344 %{m2a-single:--isa=sh2a} \
345 %{m2a-single-only:--isa=sh2a} \
346 %{m2a-nofpu:--isa=sh2a-nofpu} \
347 %{m5-compact*:--isa=SHcompact} \
348 %{m5-32media*:--isa=SHmedia --abi=32} \
349 %{m5-64media*:--isa=SHmedia --abi=64} \
350 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
352 #define ASM_SPEC SH_ASM_SPEC
354 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
355 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
356 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
358 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
362 #if STRICT_NOFPU == 1
363 /* Strict nofpu means that the compiler should tell the assembler
364 to reject FPU instructions. E.g. from ASM inserts. */
365 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
366 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
368 /* If there were an -isa option for sh5-nofpu then it would also go here. */
369 #define SUBTARGET_ASM_ISA_SPEC \
370 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
372 #else /* ! STRICT_NOFPU */
373 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
376 #ifndef SUBTARGET_ASM_SPEC
377 #define SUBTARGET_ASM_SPEC ""
380 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
381 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
383 #define LINK_EMUL_PREFIX "sh%{ml:l}"
386 #if TARGET_CPU_DEFAULT & MASK_SH5
387 #if TARGET_CPU_DEFAULT & MASK_SH_E
388 #define LINK_DEFAULT_CPU_EMUL "32"
389 #if TARGET_CPU_DEFAULT & MASK_SH1
390 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
392 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
393 #endif /* MASK_SH1 */
394 #else /* !MASK_SH_E */
395 #define LINK_DEFAULT_CPU_EMUL "64"
396 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
397 #endif /* MASK_SH_E */
398 #define ASM_ISA_DEFAULT_SPEC \
399 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
400 #else /* !MASK_SH5 */
401 #define LINK_DEFAULT_CPU_EMUL ""
402 #define ASM_ISA_DEFAULT_SPEC ""
403 #endif /* MASK_SH5 */
405 #define SUBTARGET_LINK_EMUL_SUFFIX ""
406 #define SUBTARGET_LINK_SPEC ""
408 /* Go via SH_LINK_SPEC to avoid code replication. */
409 #define LINK_SPEC SH_LINK_SPEC
411 #define SH_LINK_SPEC "\
412 -m %(link_emul_prefix)\
413 %{m5-compact*|m5-32media*:32}\
415 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
416 %(subtarget_link_emul_suffix) \
417 %{mrelax:-relax} %(subtarget_link_spec)"
419 #ifndef SH_DIV_STR_FOR_SIZE
420 #define SH_DIV_STR_FOR_SIZE "call"
423 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
425 #define ASSEMBLER_DIALECT assembler_dialect
427 extern int assembler_dialect;
429 enum sh_divide_strategy_e {
430 /* SH5 strategies. */
433 SH_DIV_FP, /* We could do this also for SH4. */
441 /* SH1 .. SH4 strategies. Because of the small number of registers
442 available, the compiler uses knowledge of the actual set of registers
443 being clobbered by the different functions called. */
444 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
445 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
446 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
450 extern enum sh_divide_strategy_e sh_div_strategy;
452 #ifndef SH_DIV_STRATEGY_DEFAULT
453 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
456 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
459 /* Target machine storage layout. */
461 /* Define this if most significant bit is lowest numbered
462 in instructions that operate on numbered bit-fields. */
464 #define BITS_BIG_ENDIAN 0
466 /* Define this if most significant byte of a word is the lowest numbered. */
467 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
469 /* Define this if most significant word of a multiword number is the lowest
471 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
473 #define MAX_BITS_PER_WORD 64
475 /* Width in bits of an `int'. We want just 32-bits, even if words are
477 #define INT_TYPE_SIZE 32
479 /* Width in bits of a `long'. */
480 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
482 /* Width in bits of a `long long'. */
483 #define LONG_LONG_TYPE_SIZE 64
485 /* Width in bits of a `long double'. */
486 #define LONG_DOUBLE_TYPE_SIZE 64
488 /* Width of a word, in units (bytes). */
489 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
490 #define MIN_UNITS_PER_WORD 4
492 /* Scaling factor for Dwarf data offsets for CFI information.
493 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
494 SHmedia; however, since we do partial register saves for the registers
495 visible to SHcompact, and for target registers for SHMEDIA32, we have
496 to allow saves that are only 4-byte aligned. */
497 #define DWARF_CIE_DATA_ALIGNMENT -4
499 /* Width in bits of a pointer.
500 See also the macro `Pmode' defined below. */
501 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
503 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
504 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
506 /* Boundary (in *bits*) on which stack pointer should be aligned. */
507 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
509 /* The log (base 2) of the cache line size, in bytes. Processors prior to
510 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
511 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
512 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
514 /* ABI given & required minimum allocation boundary (in *bits*) for the
515 code of a function. */
516 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
518 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
519 the vbit must go into the delta field of
520 pointers-to-member-functions. */
521 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
522 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
524 /* Alignment of field after `int : 0' in a structure. */
525 #define EMPTY_FIELD_BOUNDARY 32
527 /* No data type wants to be aligned rounder than this. */
528 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
530 /* The best alignment to use in cases where we have a choice. */
531 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
533 /* Make strings word-aligned so strcpy from constants will be faster. */
534 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
535 ((TREE_CODE (EXP) == STRING_CST \
536 && (ALIGN) < FASTEST_ALIGNMENT) \
537 ? FASTEST_ALIGNMENT : (ALIGN))
539 /* get_mode_alignment assumes complex values are always held in multiple
540 registers, but that is not the case on the SH; CQImode and CHImode are
541 held in a single integer register. SH5 also holds CSImode and SCmode
542 values in integer registers. This is relevant for argument passing on
543 SHcompact as we use a stack temp in order to pass CSImode by reference. */
544 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
545 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
546 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
547 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
548 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
550 /* Make arrays of chars word-aligned for the same reasons. */
551 #define DATA_ALIGNMENT(TYPE, ALIGN) \
552 (TREE_CODE (TYPE) == ARRAY_TYPE \
553 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
554 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
556 /* Number of bits which any structure or union's size must be a
557 multiple of. Each structure or union's size is rounded up to a
559 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
561 /* Set this nonzero if move instructions will actually fail to work
562 when given unaligned data. */
563 #define STRICT_ALIGNMENT 1
565 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
566 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
567 barrier_align (LABEL_AFTER_BARRIER)
569 #define LOOP_ALIGN(A_LABEL) \
570 ((! optimize || TARGET_HARD_SH4 || optimize_size) \
571 ? 0 : sh_loop_align (A_LABEL))
573 #define LABEL_ALIGN(A_LABEL) \
575 (PREV_INSN (A_LABEL) \
576 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
577 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
578 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
579 /* explicit alignment insn in constant tables. */ \
580 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
583 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
584 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
586 /* The base two logarithm of the known minimum alignment of an insn length. */
587 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
588 (NONJUMP_INSN_P (A_INSN) \
589 ? 1 << TARGET_SHMEDIA \
590 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
591 ? 1 << TARGET_SHMEDIA \
594 /* Standard register usage. */
596 /* Register allocation for the Renesas calling convention:
602 r14 frame pointer/call saved
604 ap arg pointer (doesn't really exist, always eliminated)
605 pr subroutine return address
607 mach multiply/accumulate result, high part
608 macl multiply/accumulate result, low part.
609 fpul fp/int communication register
610 rap return address pointer register
612 fr1..fr3 scratch floating point registers
614 fr12..fr15 call saved floating point registers */
616 #define MAX_REGISTER_NAME_LENGTH 5
617 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
619 #define SH_REGISTER_NAMES_INITIALIZER \
621 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
622 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
623 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
624 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
625 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
626 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
627 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
628 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
629 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
630 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
631 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
632 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
633 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
634 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
635 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
636 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
637 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
638 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
639 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
643 #define REGNAMES_ARR_INDEX_1(index) \
644 (sh_register_names[index])
645 #define REGNAMES_ARR_INDEX_2(index) \
646 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
647 #define REGNAMES_ARR_INDEX_4(index) \
648 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
649 #define REGNAMES_ARR_INDEX_8(index) \
650 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
651 #define REGNAMES_ARR_INDEX_16(index) \
652 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
653 #define REGNAMES_ARR_INDEX_32(index) \
654 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
655 #define REGNAMES_ARR_INDEX_64(index) \
656 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
658 #define REGISTER_NAMES \
660 REGNAMES_ARR_INDEX_64 (0), \
661 REGNAMES_ARR_INDEX_64 (64), \
662 REGNAMES_ARR_INDEX_8 (128), \
663 REGNAMES_ARR_INDEX_8 (136), \
664 REGNAMES_ARR_INDEX_8 (144), \
665 REGNAMES_ARR_INDEX_2 (152) \
668 #define ADDREGNAMES_SIZE 32
669 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
670 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
671 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
673 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
675 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
676 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
677 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
678 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
681 #define ADDREGNAMES_REGNO(index) \
682 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
685 #define ADDREGNAMES_ARR_INDEX_1(index) \
686 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
687 #define ADDREGNAMES_ARR_INDEX_2(index) \
688 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
689 #define ADDREGNAMES_ARR_INDEX_4(index) \
690 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
691 #define ADDREGNAMES_ARR_INDEX_8(index) \
692 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
693 #define ADDREGNAMES_ARR_INDEX_16(index) \
694 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
695 #define ADDREGNAMES_ARR_INDEX_32(index) \
696 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
698 #define ADDITIONAL_REGISTER_NAMES \
700 ADDREGNAMES_ARR_INDEX_32 (0) \
703 /* Number of actual hardware registers.
704 The hardware registers are assigned numbers for the compiler
705 from 0 to just below FIRST_PSEUDO_REGISTER.
706 All registers that the compiler knows about must be given numbers,
707 even those that are not normally considered general registers. */
709 /* There are many other relevant definitions in sh.md's md_constants. */
711 #define FIRST_GENERAL_REG R0_REG
712 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
713 #define FIRST_FP_REG DR0_REG
714 #define LAST_FP_REG (FIRST_FP_REG + \
715 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
716 #define FIRST_XD_REG XD0_REG
717 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
718 #define FIRST_TARGET_REG TR0_REG
719 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
721 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
723 #define FIRST_BANKED_REG R0_REG
724 #define LAST_BANKED_REG R7_REG
726 #define BANKED_REGISTER_P(REGNO) \
728 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
729 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
731 #define GENERAL_REGISTER_P(REGNO) \
733 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
734 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
736 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
737 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
738 || ((REGNO) == FRAME_POINTER_REGNUM))
740 #define FP_REGISTER_P(REGNO) \
741 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
743 #define XD_REGISTER_P(REGNO) \
744 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
746 #define FP_OR_XD_REGISTER_P(REGNO) \
747 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
749 #define FP_ANY_REGISTER_P(REGNO) \
750 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
752 #define SPECIAL_REGISTER_P(REGNO) \
753 ((REGNO) == GBR_REG || (REGNO) == T_REG \
754 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
756 #define TARGET_REGISTER_P(REGNO) \
757 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
759 #define SHMEDIA_REGISTER_P(REGNO) \
760 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
761 || TARGET_REGISTER_P (REGNO))
763 /* This is to be used in TARGET_CONDITIONAL_REGISTER_USAGE, to mark
764 registers that should be fixed. */
765 #define VALID_REGISTER_P(REGNO) \
766 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
767 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
768 || (REGNO) == FRAME_POINTER_REGNUM \
769 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
770 || (TARGET_SH2E && (REGNO) == FPUL_REG))
772 /* The mode that should be generally used to store a register by
773 itself in the stack, or to load it back. */
774 #define REGISTER_NATURAL_MODE(REGNO) \
775 (FP_REGISTER_P (REGNO) ? SFmode \
776 : XD_REGISTER_P (REGNO) ? DFmode \
777 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
781 #define FIRST_PSEUDO_REGISTER 154
783 /* Don't count soft frame pointer. */
784 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
786 /* 1 for registers that have pervasive standard uses
787 and are not available for the register allocator.
789 Mach register is fixed 'cause it's only 10 bits wide for SH1.
790 It is 32 bits wide for SH2. */
792 #define FIXED_REGISTERS \
794 /* Regular registers. */ \
795 0, 0, 0, 0, 0, 0, 0, 0, \
796 0, 0, 0, 0, 0, 0, 0, 1, \
797 /* r16 is reserved, r18 is the former pr. */ \
798 1, 0, 0, 0, 0, 0, 0, 0, \
799 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
800 /* r26 is a global variable data pointer; r27 is for constants. */ \
801 1, 1, 1, 1, 0, 0, 0, 0, \
802 0, 0, 0, 0, 0, 0, 0, 0, \
803 0, 0, 0, 0, 0, 0, 0, 0, \
804 0, 0, 0, 0, 0, 0, 0, 0, \
805 0, 0, 0, 0, 0, 0, 0, 1, \
806 /* FP registers. */ \
807 0, 0, 0, 0, 0, 0, 0, 0, \
808 0, 0, 0, 0, 0, 0, 0, 0, \
809 0, 0, 0, 0, 0, 0, 0, 0, \
810 0, 0, 0, 0, 0, 0, 0, 0, \
811 0, 0, 0, 0, 0, 0, 0, 0, \
812 0, 0, 0, 0, 0, 0, 0, 0, \
813 0, 0, 0, 0, 0, 0, 0, 0, \
814 0, 0, 0, 0, 0, 0, 0, 0, \
815 /* Branch target registers. */ \
816 0, 0, 0, 0, 0, 0, 0, 0, \
817 /* XD registers. */ \
818 0, 0, 0, 0, 0, 0, 0, 0, \
819 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
820 1, 1, 1, 1, 1, 1, 0, 1, \
825 /* 1 for registers not available across function calls.
826 These must include the FIXED_REGISTERS and also any
827 registers that can be used without being saved.
828 The latter must include the registers where values are returned
829 and the register where structure-value addresses are passed.
830 Aside from that, you can include as many other registers as you like. */
832 #define CALL_USED_REGISTERS \
834 /* Regular registers. */ \
835 1, 1, 1, 1, 1, 1, 1, 1, \
836 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
837 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
838 across SH5 function calls. */ \
839 0, 0, 0, 0, 0, 0, 0, 1, \
840 1, 1, 1, 1, 1, 1, 1, 1, \
841 1, 1, 1, 1, 0, 0, 0, 0, \
842 0, 0, 0, 0, 1, 1, 1, 1, \
843 1, 1, 1, 1, 0, 0, 0, 0, \
844 0, 0, 0, 0, 0, 0, 0, 0, \
845 0, 0, 0, 0, 1, 1, 1, 1, \
846 /* FP registers. */ \
847 1, 1, 1, 1, 1, 1, 1, 1, \
848 1, 1, 1, 1, 0, 0, 0, 0, \
849 1, 1, 1, 1, 1, 1, 1, 1, \
850 1, 1, 1, 1, 1, 1, 1, 1, \
851 1, 1, 1, 1, 0, 0, 0, 0, \
852 0, 0, 0, 0, 0, 0, 0, 0, \
853 0, 0, 0, 0, 0, 0, 0, 0, \
854 0, 0, 0, 0, 0, 0, 0, 0, \
855 /* Branch target registers. */ \
856 1, 1, 1, 1, 1, 0, 0, 0, \
857 /* XD registers. */ \
858 1, 1, 1, 1, 1, 1, 0, 0, \
859 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
860 1, 1, 1, 1, 1, 1, 1, 1, \
865 /* TARGET_CONDITIONAL_REGISTER_USAGE might want to make a register
866 call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */
867 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
869 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
870 across SHcompact function calls. We can't tell whether a called
871 function is SHmedia or SHcompact, so we assume it may be when
872 compiling SHmedia code with the 32-bit ABI, since that's the only
873 ABI that can be linked with SHcompact code. */
874 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
876 && GET_MODE_SIZE (MODE) > 4 \
877 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
878 && (REGNO) <= FIRST_GENERAL_REG + 15) \
879 || TARGET_REGISTER_P (REGNO) \
880 || (REGNO) == PR_MEDIA_REG))
882 /* Return number of consecutive hard regs needed starting at reg REGNO
883 to hold something of mode MODE.
884 This is ordinarily the length in words of a value of mode MODE
885 but can be less for certain modes in special long registers.
887 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
889 #define HARD_REGNO_NREGS(REGNO, MODE) \
890 (XD_REGISTER_P (REGNO) \
891 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
892 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
893 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
894 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
896 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
898 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
899 sh_hard_regno_mode_ok ((REGNO), (MODE))
901 /* Value is 1 if it is a good idea to tie two pseudo registers
902 when one has mode MODE1 and one has mode MODE2.
903 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
904 for any hard reg, then this must be 0 for correct output.
905 That's the case for xd registers: we don't hold SFmode values in
906 them, so we can't tie an SFmode pseudos with one in another
907 floating-point mode. */
909 #define MODES_TIEABLE_P(MODE1, MODE2) \
910 ((MODE1) == (MODE2) \
912 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
913 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
914 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
915 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
916 && (GET_MODE_SIZE (MODE2) <= 4)) \
917 : ((MODE1) != SFmode && (MODE2) != SFmode))))
919 /* A C expression that is nonzero if hard register NEW_REG can be
920 considered for use as a rename register for OLD_REG register */
922 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
923 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
925 /* Specify the registers used for certain standard purposes.
926 The values of these macros are register numbers. */
928 /* Define this if the program counter is overloaded on a register. */
929 /* #define PC_REGNUM 15*/
931 /* Register to use for pushing function arguments. */
932 #define STACK_POINTER_REGNUM SP_REG
934 /* Base register for access to local variables of the function. */
935 #define HARD_FRAME_POINTER_REGNUM FP_REG
937 /* Base register for access to local variables of the function. */
938 #define FRAME_POINTER_REGNUM 153
940 /* Fake register that holds the address on the stack of the
941 current function's return address. */
942 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
944 /* Register to hold the addressing base for position independent
945 code access to data items. */
946 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
948 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
950 /* Definitions for register eliminations.
952 We have three registers that can be eliminated on the SH. First, the
953 frame pointer register can often be eliminated in favor of the stack
954 pointer register. Secondly, the argument pointer register can always be
955 eliminated; it is replaced with either the stack or frame pointer.
956 Third, there is the return address pointer, which can also be replaced
957 with either the stack or the frame pointer. */
959 /* This is an array of structures. Each structure initializes one pair
960 of eliminable registers. The "from" register number is given first,
961 followed by "to". Eliminations of the same "from" register are listed
962 in order of preference. */
964 /* If you add any registers here that are not actually hard registers,
965 and that have any alternative of elimination that doesn't always
966 apply, you need to amend calc_live_regs to exclude it, because
967 reload spills all eliminable registers where it sees an
968 can_eliminate == 0 entry, thus making them 'live' .
969 If you add any hard registers that can be eliminated in different
970 ways, you have to patch reload to spill them only when all alternatives
971 of elimination fail. */
973 #define ELIMINABLE_REGS \
974 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
975 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
976 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
977 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
978 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
979 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
980 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
982 /* Define the offset between two registers, one to be eliminated, and the other
983 its replacement, at the start of a routine. */
985 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
986 OFFSET = initial_elimination_offset ((FROM), (TO))
988 /* Base register for access to arguments of the function. */
989 #define ARG_POINTER_REGNUM AP_REG
991 /* Register in which the static-chain is passed to a function. */
992 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
994 /* Don't default to pcc-struct-return, because we have already specified
995 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
998 #define DEFAULT_PCC_STRUCT_RETURN 0
1000 #define SHMEDIA_REGS_STACK_ADJUST() \
1001 (TARGET_SHCOMPACT && crtl->saves_all_registers \
1002 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1003 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1007 /* Define the classes of registers for register constraints in the
1008 machine description. Also define ranges of constants.
1010 One of the classes must always be named ALL_REGS and include all hard regs.
1011 If there is more than one class, another class must be named NO_REGS
1012 and contain no registers.
1014 The name GENERAL_REGS must be the name of a class (or an alias for
1015 another name such as ALL_REGS). This is the class of registers
1016 that is allowed by "g" or "r" in a register constraint.
1017 Also, registers outside this class are allocated only when
1018 instructions express preferences for them.
1020 The classes must be numbered in nondecreasing order; that is,
1021 a larger-numbered class must never be contained completely
1022 in a smaller-numbered class.
1024 For any two classes, it is very desirable that there be another
1025 class that represents their union. */
1027 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1028 be used as the destination of some of the arithmetic ops. There are
1029 also some special purpose registers; the T bit register, the
1030 Procedure Return Register and the Multiply Accumulate Registers. */
1031 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1032 reg_class_subunion. We don't want to have an actual union class
1033 of these, because it would only be used when both classes are calculated
1034 to give the same cost, but there is only one FPUL register.
1035 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1036 applying to the actual instruction alternative considered. E.g., the
1037 y/r alternative of movsi_ie is considered to have no more cost that
1038 the r/r alternative, which is patently untrue. */
1062 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1064 /* Give names of register classes as strings for dump file. */
1065 #define REG_CLASS_NAMES \
1080 "GENERAL_FP_REGS", \
1081 "GENERAL_DF_REGS", \
1086 /* Define which registers fit in which classes.
1087 This is an initializer for a vector of HARD_REG_SET
1088 of length N_REG_CLASSES. */
1090 #define REG_CLASS_CONTENTS \
1093 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1095 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1097 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1099 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1101 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1103 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1104 /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1105 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1106 /* GENERAL_REGS: */ \
1107 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1109 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1111 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1112 /* DF_HI_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1113 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1115 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1117 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1118 /* GENERAL_FP_REGS: */ \
1119 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1120 /* GENERAL_DF_REGS: */ \
1121 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1122 /* TARGET_REGS: */ \
1123 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1125 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1128 /* The same information, inverted:
1129 Return the class number of the smallest class containing
1130 reg number REGNO. This could be a conditional expression
1131 or could index an array. */
1133 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1134 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1136 /* The following macro defines cover classes for Integrated Register
1137 Allocator. Cover classes is a set of non-intersected register
1138 classes covering all hard registers used for register allocation
1139 purpose. Any move between two registers of a cover class should be
1140 cheaper than load or store of the registers. The macro value is
1141 array of register classes with LIM_REG_CLASSES used as the end
1144 #define IRA_COVER_CLASSES \
1146 GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \
1147 FPUL_REGS, LIM_REG_CLASSES \
1150 /* When this hook returns true for MODE, the compiler allows
1151 registers explicitly used in the rtl to be used as spill registers
1152 but prevents the compiler from extending the lifetime of these
1154 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1155 sh_small_register_classes_for_mode_p
1157 /* The order in which register should be allocated. */
1158 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1159 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1160 spilled or used otherwise, we better have the FP_REGS allocated first. */
1161 #define REG_ALLOC_ORDER \
1162 {/* Caller-saved FPRs */ \
1163 65, 66, 67, 68, 69, 70, 71, 64, \
1164 72, 73, 74, 75, 80, 81, 82, 83, \
1165 84, 85, 86, 87, 88, 89, 90, 91, \
1166 92, 93, 94, 95, 96, 97, 98, 99, \
1167 /* Callee-saved FPRs */ \
1168 76, 77, 78, 79,100,101,102,103, \
1169 104,105,106,107,108,109,110,111, \
1170 112,113,114,115,116,117,118,119, \
1171 120,121,122,123,124,125,126,127, \
1172 136,137,138,139,140,141,142,143, \
1174 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1175 1, 2, 3, 7, 6, 5, 4, 0, \
1176 8, 9, 17, 19, 20, 21, 22, 23, \
1177 36, 37, 38, 39, 40, 41, 42, 43, \
1179 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1180 10, 11, 12, 13, 14, 18, \
1181 /* SH5 callee-saved GPRs */ \
1182 28, 29, 30, 31, 32, 33, 34, 35, \
1183 44, 45, 46, 47, 48, 49, 50, 51, \
1184 52, 53, 54, 55, 56, 57, 58, 59, \
1186 /* SH5 branch target registers */ \
1187 128,129,130,131,132,133,134,135, \
1188 /* Fixed registers */ \
1189 15, 16, 24, 25, 26, 27, 63,144, \
1190 145,146,147,148,149,152,153 }
1192 /* The class value for index registers, and the one for base regs. */
1193 #define INDEX_REG_CLASS \
1194 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1195 #define BASE_REG_CLASS GENERAL_REGS
1197 /* Defines for sh.md and constraints.md. */
1199 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1200 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1201 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1202 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1203 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1204 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1205 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1206 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1208 #define CONST_OK_FOR_J16(VALUE) \
1209 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1210 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1212 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1213 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1216 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1217 ((((REGCLASS_HAS_FP_REG (CLASS) \
1219 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1220 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1221 && TARGET_FMOVD)))) \
1222 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1224 && FP_REGISTER_P (REGNO (X)))) \
1225 && ! TARGET_SHMEDIA \
1226 && ((MODE) == SFmode || (MODE) == SImode)) \
1228 : (((CLASS) == FPUL_REGS \
1229 || (REGCLASS_HAS_FP_REG (CLASS) \
1230 && ! TARGET_SHMEDIA && MODE == SImode)) \
1233 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1234 || REGNO (X) == T_REG \
1235 || system_reg_operand (X, VOIDmode))))) \
1237 : (((CLASS) == TARGET_REGS \
1238 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1239 && !satisfies_constraint_Csy (X) \
1240 && (!REG_P (X) || ! GENERAL_REGISTER_P (REGNO (X)))) \
1242 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1243 && REG_P (X) && ! GENERAL_REGISTER_P (REGNO (X)) \
1244 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1246 : ((CLASS) != GENERAL_REGS && REG_P (X) \
1247 && TARGET_REGISTER_P (REGNO (X))) \
1248 ? GENERAL_REGS : (ELSE))
1250 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1251 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1253 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1254 ((REGCLASS_HAS_FP_REG (CLASS) \
1255 && ! TARGET_SHMEDIA \
1256 && immediate_operand ((X), (MODE)) \
1257 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1258 && (MODE) == SFmode && fldi_ok ())) \
1260 : ((CLASS) == FPUL_REGS \
1262 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1263 || REGNO (X) == T_REG)) \
1264 || GET_CODE (X) == PLUS)) \
1266 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1267 ? (satisfies_constraint_I08 (X) \
1270 : ((CLASS) == FPSCR_REGS \
1271 && ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1272 || (MEM_P (X) && GET_CODE (XEXP ((X), 0)) == PLUS))) \
1274 : (REGCLASS_HAS_FP_REG (CLASS) \
1276 && immediate_operand ((X), (MODE)) \
1277 && (X) != CONST0_RTX (GET_MODE (X)) \
1278 && GET_MODE (X) != V4SFmode) \
1280 : (((MODE) == QImode || (MODE) == HImode) \
1281 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1283 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1284 && (GET_CODE (X) == LABEL_REF || PIC_ADDR_P (X))) \
1286 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1289 /* Return the maximum number of consecutive registers
1290 needed to represent mode MODE in a register of class CLASS.
1292 If TARGET_SHMEDIA, we need two FP registers per word.
1293 Otherwise we will need at most one register per word. */
1294 #define CLASS_MAX_NREGS(CLASS, MODE) \
1296 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1297 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1298 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1300 /* If defined, gives a class of registers that cannot be used as the
1301 operand of a SUBREG that changes the mode of the object illegally. */
1302 /* ??? We need to renumber the internal numbers for the frnn registers
1303 when in little endian in order to allow mode size changes. */
1305 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1306 sh_cannot_change_mode_class (FROM, TO, CLASS)
1308 /* Stack layout; function entry, exit and calling. */
1310 /* Define the number of registers that can hold parameters.
1311 These macros are used only in other macro definitions below. */
1313 #define NPARM_REGS(MODE) \
1314 (TARGET_FPU_ANY && (MODE) == SFmode \
1315 ? (TARGET_SH5 ? 12 : 8) \
1316 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1317 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1318 ? (TARGET_SH5 ? 12 : 8) \
1319 : (TARGET_SH5 ? 8 : 4))
1321 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1322 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1324 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1325 #define FIRST_FP_RET_REG FIRST_FP_REG
1327 /* Define this if pushing a word on the stack
1328 makes the stack pointer a smaller address. */
1329 #define STACK_GROWS_DOWNWARD
1331 /* Define this macro to nonzero if the addresses of local variable slots
1332 are at negative offsets from the frame pointer. */
1333 #define FRAME_GROWS_DOWNWARD 1
1335 /* Offset from the frame pointer to the first local variable slot to
1337 #define STARTING_FRAME_OFFSET 0
1339 /* If we generate an insn to push BYTES bytes,
1340 this says how many the stack pointer really advances by. */
1341 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1342 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1343 do correct alignment. */
1345 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1348 /* Offset of first parameter from the argument pointer register value. */
1349 #define FIRST_PARM_OFFSET(FNDECL) 0
1351 /* Value is the number of bytes of arguments automatically popped when
1352 calling a subroutine.
1353 CUM is the accumulated argument list.
1355 On SHcompact, the call trampoline pops arguments off the stack. */
1356 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1358 /* Some subroutine macros specific to this machine. */
1360 #define BASE_RETURN_VALUE_REG(MODE) \
1361 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1362 ? FIRST_FP_RET_REG \
1363 : TARGET_FPU_ANY && (MODE) == SCmode \
1364 ? FIRST_FP_RET_REG \
1365 : (TARGET_FPU_DOUBLE \
1366 && ((MODE) == DFmode || (MODE) == SFmode \
1367 || (MODE) == DCmode || (MODE) == SCmode )) \
1368 ? FIRST_FP_RET_REG \
1371 #define BASE_ARG_REG(MODE) \
1372 ((TARGET_SH2E && ((MODE) == SFmode)) \
1373 ? FIRST_FP_PARM_REG \
1374 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1375 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1376 ? FIRST_FP_PARM_REG \
1379 /* 1 if N is a possible register number for function argument passing. */
1380 /* ??? There are some callers that pass REGNO as int, and others that pass
1381 it as unsigned. We get warnings unless we do casts everywhere. */
1382 #define FUNCTION_ARG_REGNO_P(REGNO) \
1383 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1384 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1385 || (TARGET_FPU_ANY \
1386 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1387 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1388 + NPARM_REGS (SFmode))))
1390 /* Define a data type for recording info about an argument list
1391 during the scan of that argument list. This data type should
1392 hold all necessary information about the function itself
1393 and about the args processed so far, enough to enable macros
1394 such as FUNCTION_ARG to determine where the next arg should go.
1396 On SH, this is a single integer, which is a number of words
1397 of arguments scanned so far (including the invisible argument,
1398 if any, which holds the structure-value-address).
1399 Thus NARGREGS or more means all following args should go on the stack. */
1401 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1405 /* Nonzero if a prototype is available for the function. */
1407 /* The number of an odd floating-point register, that should be used
1408 for the next argument of type float. */
1409 int free_single_fp_reg;
1410 /* Whether we're processing an outgoing function call. */
1412 /* The number of general-purpose registers that should have been
1413 used to pass partial arguments, that are passed totally on the
1414 stack. On SHcompact, a call trampoline will pop them off the
1415 stack before calling the actual function, and, if the called
1416 function is implemented in SHcompact mode, the incoming arguments
1417 decoder will push such arguments back onto the stack. For
1418 incoming arguments, STACK_REGS also takes into account other
1419 arguments passed by reference, that the decoder will also push
1422 /* The number of general-purpose registers that should have been
1423 used to pass arguments, if the arguments didn't have to be passed
1426 /* Set as by shcompact_byref if the current argument is to be passed
1430 /* call_cookie is a bitmask used by call expanders, as well as
1431 function prologue and epilogues, to allow SHcompact to comply
1432 with the SH5 32-bit ABI, that requires 64-bit registers to be
1433 used even though only the lower 32-bit half is visible in
1434 SHcompact mode. The strategy is to call SHmedia trampolines.
1436 The alternatives for each of the argument-passing registers are
1437 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1438 contents from the address in it; (d) add 8 to it, storing the
1439 result in the next register, then (c); (e) copy it from some
1440 floating-point register,
1442 Regarding copies from floating-point registers, r2 may only be
1443 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1444 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1445 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1446 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1449 The bit mask is structured as follows:
1451 - 1 bit to tell whether to set up a return trampoline.
1453 - 3 bits to count the number consecutive registers to pop off the
1456 - 4 bits for each of r9, r8, r7 and r6.
1458 - 3 bits for each of r5, r4, r3 and r2.
1460 - 3 bits set to 0 (the most significant ones)
1463 1098 7654 3210 9876 5432 1098 7654 3210
1464 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1465 2223 3344 4555 6666 7777 8888 9999 SSS-
1467 - If F is set, the register must be copied from an FP register,
1468 whose number is encoded in the remaining bits.
1470 - Else, if L is set, the register must be loaded from the address
1471 contained in it. If the P bit is *not* set, the address of the
1472 following dword should be computed first, and stored in the
1475 - Else, if P is set, the register alone should be popped off the
1478 - After all this processing, the number of registers represented
1479 in SSS will be popped off the stack. This is an optimization
1480 for pushing/popping consecutive registers, typically used for
1481 varargs and large arguments partially passed in registers.
1483 - If T is set, a return trampoline will be set up for 64-bit
1484 return values to be split into 2 32-bit registers. */
1487 /* This is set to nonzero when the call in question must use the Renesas ABI,
1488 even without the -mrenesas option. */
1492 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1493 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1494 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1495 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1496 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1497 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1498 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1499 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1500 #define CALL_COOKIE_INT_REG(REG, VAL) \
1501 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1502 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1503 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1505 #define CUMULATIVE_ARGS struct sh_args
1507 #define GET_SH_ARG_CLASS(MODE) \
1508 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1510 /* There's no mention of complex float types in the SH5 ABI, so we
1511 should presumably handle them as aggregate types. */ \
1512 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1514 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1515 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1516 ? SH_ARG_FLOAT : SH_ARG_INT)
1518 #define ROUND_ADVANCE(SIZE) \
1519 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1521 /* Round a register number up to a proper boundary for an arg of mode
1524 The SH doesn't care about double alignment, so we only
1525 round doubles to even regs when asked to explicitly. */
1527 #define ROUND_REG(CUM, MODE) \
1528 (((TARGET_ALIGN_DOUBLE \
1529 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1530 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1531 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1532 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1533 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1534 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1536 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1537 for a call to a function whose data type is FNTYPE.
1538 For a library call, FNTYPE is 0.
1540 On SH, the offset always starts at 0: the first parm reg is always
1541 the same reg for a given argument class.
1543 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1545 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1546 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1548 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1549 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1551 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1552 This macro is only used in this file. */
1554 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1556 || (! TREE_ADDRESSABLE ((TYPE)) \
1557 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1558 || ! (AGGREGATE_TYPE_P (TYPE) \
1559 || (!TARGET_FPU_ANY \
1560 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1561 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1562 && ! (CUM).force_mem \
1564 ? ((MODE) == BLKmode \
1565 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1566 + int_size_in_bytes (TYPE)) \
1567 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1568 : ((ROUND_REG((CUM), (MODE)) \
1569 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1570 <= NPARM_REGS (MODE))) \
1571 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1573 /* By accident we got stuck with passing SCmode on SH4 little endian
1574 in two registers that are nominally successive - which is different from
1575 two single SFmode values, where we take endianness translation into
1576 account. That does not work at all if an odd number of registers is
1577 already in use, so that got fixed, but library functions are still more
1578 likely to use complex numbers without mixing them with SFmode arguments
1579 (which in C would have to be structures), so for the sake of ABI
1580 compatibility the way SCmode values are passed when an even number of
1581 FP registers is in use remains different from a pair of SFmode values for
1584 foo (double); a: fr5,fr4
1585 foo (float a, float b); a: fr5 b: fr4
1586 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1587 this should be the other way round...
1588 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1589 #define FUNCTION_ARG_SCmode_WART 1
1591 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1592 register in SHcompact mode, it must be padded in the most
1593 significant end. This means that passing it by reference wouldn't
1594 pad properly on a big-endian machine. In this particular case, we
1595 pass this argument on the stack, in a way that the call trampoline
1596 will load its value into the appropriate register. */
1597 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1598 ((MODE) == BLKmode \
1599 && TARGET_SHCOMPACT \
1600 && ! TARGET_LITTLE_ENDIAN \
1601 && int_size_in_bytes (TYPE) > 4 \
1602 && int_size_in_bytes (TYPE) < 8)
1604 /* Minimum alignment for an argument to be passed by callee-copy
1605 reference. We need such arguments to be aligned to 8 byte
1606 boundaries, because they'll be loaded using quad loads. */
1607 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1609 /* The SH5 ABI requires floating-point arguments to be passed to
1610 functions without a prototype in both an FP register and a regular
1611 register or the stack. When passing the argument in both FP and
1612 general-purpose registers, list the FP register first. */
1613 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1619 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1620 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1621 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1626 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1627 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1628 + (CUM).arg_count[(int) SH_ARG_INT]) \
1629 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1630 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1633 /* The SH5 ABI requires regular registers or stack slots to be
1634 reserved for floating-point arguments. Registers are taken care of
1635 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1636 Unfortunately, there's no way to just reserve a stack slot, so
1637 we'll end up needlessly storing a copy of the argument in the
1638 stack. For incoming arguments, however, the PARALLEL will be
1639 optimized to the register-only form, and the value in the stack
1640 slot won't be used at all. */
1641 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1642 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1643 ? gen_rtx_REG ((MODE), (REG)) \
1644 : gen_rtx_PARALLEL ((MODE), \
1647 (VOIDmode, NULL_RTX, \
1650 (VOIDmode, gen_rtx_REG ((MODE), \
1654 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1656 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
1657 || (MODE) == DCmode) \
1658 && ((CUM).arg_count[(int) SH_ARG_INT] \
1659 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1660 : GET_MODE_SIZE (MODE)) \
1661 + 7) / 8) > NPARM_REGS (SImode))
1663 /* Perform any needed actions needed for a function that is receiving a
1664 variable number of arguments. */
1666 /* Call the function profiler with a given profile label.
1667 We use two .aligns, so as to make sure that both the .long is aligned
1668 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1669 from the trapa instruction. */
1671 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1673 if (TARGET_SHMEDIA) \
1675 fprintf((STREAM), "\tmovi\t33,r0\n"); \
1676 fprintf((STREAM), "\ttrapa\tr0\n"); \
1677 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1681 fprintf((STREAM), "\t.align\t2\n"); \
1682 fprintf((STREAM), "\ttrapa\t#33\n"); \
1683 fprintf((STREAM), "\t.align\t2\n"); \
1684 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1688 /* Define this macro if the code for function profiling should come
1689 before the function prologue. Normally, the profiling code comes
1692 #define PROFILE_BEFORE_PROLOGUE
1694 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1695 the stack pointer does not matter. The value is tested only in
1696 functions that have frame pointers.
1697 No definition is equivalent to always zero. */
1699 #define EXIT_IGNORE_STACK 1
1702 On the SH, the trampoline looks like
1703 2 0002 D202 mov.l l2,r2
1704 1 0000 D301 mov.l l1,r3
1707 5 0008 00000000 l1: .long area
1708 6 000c 00000000 l2: .long function */
1710 /* Length in units of the trampoline for entering a nested function. */
1711 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
1713 /* Alignment required for a trampoline in bits . */
1714 #define TRAMPOLINE_ALIGNMENT \
1715 ((CACHE_LOG < 3 || (optimize_size && ! TARGET_HARVARD)) ? 32 \
1716 : TARGET_SHMEDIA ? 256 : 64)
1718 /* A C expression whose value is RTL representing the value of the return
1719 address for the frame COUNT steps up from the current frame.
1720 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1721 can ignore COUNT. */
1723 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1724 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
1726 /* A C expression whose value is RTL representing the location of the
1727 incoming return address at the beginning of any function, before the
1728 prologue. This RTL is either a REG, indicating that the return
1729 value is saved in REG, or a MEM representing a location in
1731 #define INCOMING_RETURN_ADDR_RTX \
1732 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
1734 /* Addressing modes, and classification of registers for them. */
1735 #define HAVE_POST_INCREMENT TARGET_SH1
1736 #define HAVE_PRE_DECREMENT TARGET_SH1
1738 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1740 #define USE_LOAD_PRE_DECREMENT(mode) 0
1741 #define USE_STORE_POST_INCREMENT(mode) 0
1742 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1745 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
1746 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
1747 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1749 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
1750 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
1751 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1753 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
1755 /* Macros to check register numbers against specific register classes. */
1757 /* These assume that REGNO is a hard or pseudo reg number.
1758 They give nonzero only if REGNO is a hard reg of the suitable class
1759 or a pseudo reg currently allocated to a suitable hard reg.
1760 Since they use reg_renumber, they are safe only once reg_renumber
1761 has been allocated, which happens in local-alloc.c. */
1763 #define REGNO_OK_FOR_BASE_P(REGNO) \
1764 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1765 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1766 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1768 ? (GENERAL_REGISTER_P (REGNO) \
1769 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
1770 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1772 /* Maximum number of registers that can appear in a valid memory
1775 #define MAX_REGS_PER_ADDRESS 2
1777 /* Recognize any constant value that is a valid address. */
1779 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1781 /* Nonzero if the constant value X is a legitimate general operand. */
1782 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
1784 #define LEGITIMATE_CONSTANT_P(X) \
1786 ? ((GET_MODE (X) != DFmode \
1787 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
1788 || (X) == CONST0_RTX (GET_MODE (X)) \
1789 || ! TARGET_SHMEDIA_FPU \
1790 || TARGET_SHMEDIA64) \
1791 : (GET_CODE (X) != CONST_DOUBLE \
1792 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
1793 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
1795 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1796 and check its validity for a certain class.
1797 The suitable hard regs are always accepted and all pseudo regs
1798 are also accepted if STRICT is not set. */
1800 /* Nonzero if X is a reg that can be used as a base reg. */
1801 #define REG_OK_FOR_BASE_P(X, STRICT) \
1802 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1803 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1805 /* Nonzero if X is a reg that can be used as an index. */
1806 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1807 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1808 : REGNO (X) == R0_REG) \
1809 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1811 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1812 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1813 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1814 : REGNO (X) == R0_REG && OFFSET == 0) \
1815 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1817 /* Macros for extra constraints. */
1819 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1820 ((GET_CODE ((OP)) == LABEL_REF) \
1821 || (GET_CODE ((OP)) == CONST \
1822 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1823 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1824 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1826 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1828 && !CONST_INT_P (OP) \
1829 && GET_CODE (OP) != CONST_DOUBLE \
1831 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1832 && !PIC_ADDR_P (OP) \
1833 && GET_CODE (OP) != LABEL_REF)))
1835 /* Check whether OP is a datalabel unspec. */
1836 #define DATALABEL_REF_NO_CONST_P(OP) \
1837 (GET_CODE (OP) == UNSPEC \
1838 && XINT ((OP), 1) == UNSPEC_DATALABEL \
1839 && XVECLEN ((OP), 0) == 1 \
1840 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
1842 #define GOT_ENTRY_P(OP) \
1843 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1844 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1846 #define GOTPLT_ENTRY_P(OP) \
1847 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1848 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1850 #define UNSPEC_GOTOFF_P(OP) \
1851 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1853 #define GOTOFF_P(OP) \
1854 (GET_CODE (OP) == CONST \
1855 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1856 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1857 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1858 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1860 #define PIC_ADDR_P(OP) \
1861 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1862 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1864 #define PCREL_SYMOFF_P(OP) \
1865 (GET_CODE (OP) == CONST \
1866 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1867 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1869 #define NON_PIC_REFERENCE_P(OP) \
1870 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1871 || (GET_CODE (OP) == CONST \
1872 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1873 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
1874 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
1875 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1876 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1877 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1878 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
1879 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1881 #define PIC_REFERENCE_P(OP) \
1882 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1883 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1885 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
1887 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
1888 || PCREL_SYMOFF_P (OP)) \
1889 : NON_PIC_REFERENCE_P (OP))
1891 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1892 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1893 || (GET_CODE (X) == SUBREG \
1894 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1895 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1896 && REG_P (SUBREG_REG (X)) \
1897 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1899 /* Since this must be r0, which is a single register class, we must check
1900 SUBREGs more carefully, to be sure that we don't accept one that extends
1901 outside the class. */
1902 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1903 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1904 || (GET_CODE (X) == SUBREG \
1905 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1906 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1907 && REG_P (SUBREG_REG (X)) \
1908 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1910 #ifdef REG_OK_STRICT
1911 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1912 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1914 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
1915 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
1918 #define ALLOW_INDEXED_ADDRESS \
1919 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
1921 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, WIN) \
1923 if (sh_legitimate_index_p ((MODE), (OP))) \
1927 /* A C compound statement that attempts to replace X, which is an address
1928 that needs reloading, with a valid memory address for an operand of
1929 mode MODE. WIN is a C statement label elsewhere in the code. */
1931 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1933 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
1937 /* Specify the machine mode that this machine uses
1938 for the index in the tablejump instruction. */
1939 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
1941 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1942 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1943 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1944 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1945 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1946 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1949 /* Define as C expression which evaluates to nonzero if the tablejump
1950 instruction expects the table to contain offsets from the address of the
1952 Do not define this if the table should contain absolute addresses. */
1953 #define CASE_VECTOR_PC_RELATIVE 1
1955 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
1956 #define FLOAT_TYPE_SIZE 32
1958 /* Since the SH2e has only `float' support, it is desirable to make all
1959 floating point types equivalent to `float'. */
1960 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
1962 /* 'char' is signed by default. */
1963 #define DEFAULT_SIGNED_CHAR 1
1965 /* The type of size_t unsigned int. */
1966 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
1969 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
1971 #define WCHAR_TYPE "short unsigned int"
1972 #define WCHAR_TYPE_SIZE 16
1974 #define SH_ELF_WCHAR_TYPE "long int"
1976 /* Max number of bytes we can move from memory to memory
1977 in one reasonably fast instruction. */
1978 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
1980 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
1981 MOVE_MAX is not a compile-time constant. */
1982 #define MAX_MOVE_MAX 8
1984 /* Max number of bytes we want move_by_pieces to be able to copy
1986 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
1988 /* Define if operations between registers always perform the operation
1989 on the full register even if a narrower mode is specified. */
1990 #define WORD_REGISTER_OPERATIONS
1992 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1993 will either zero-extend or sign-extend. The value of this macro should
1994 be the code that says which one of the two operations is implicitly
1995 done, UNKNOWN if none. */
1996 /* For SHmedia, we can truncate to QImode easier using zero extension. */
1997 /* FP registers can load SImode values, but don't implicitly sign-extend
1999 #define LOAD_EXTEND_OP(MODE) \
2000 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2001 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2003 /* Define if loading short immediate values into registers sign extends. */
2004 #define SHORT_IMMEDIATES_SIGN_EXTEND
2006 /* Nonzero if access to memory by bytes is no faster than for words. */
2007 #define SLOW_BYTE_ACCESS 1
2009 /* Immediate shift counts are truncated by the output routines (or was it
2010 the assembler?). Shift counts in a register are truncated by SH. Note
2011 that the native compiler puts too large (> 32) immediate shift counts
2012 into a register and shifts by the register, letting the SH decide what
2013 to do instead of doing that itself. */
2014 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2015 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2016 expects - the sign bit is significant - so it appears that we need to
2017 leave this zero for correct SH3 code. */
2018 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2020 /* All integers have the same format so truncation is easy. */
2021 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2022 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2023 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2025 /* Define this if addresses of constant functions
2026 shouldn't be put through pseudo regs where they can be cse'd.
2027 Desirable on machines where ordinary constants are expensive
2028 but a CALL with constant address is cheap. */
2029 /*#define NO_FUNCTION_CSE 1*/
2031 /* The machine modes of pointers and functions. */
2032 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2033 #define FUNCTION_MODE Pmode
2035 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2036 are actually function calls with some special constraints on arguments
2039 These macros tell reorg that the references to arguments and
2040 register clobbers for insns of type sfunc do not appear to happen
2041 until after the millicode call. This allows reorg to put insns
2042 which set the argument registers into the delay slot of the millicode
2043 call -- thus they act more like traditional CALL_INSNs.
2045 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2046 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2049 #define INSN_SETS_ARE_DELAYED(X) \
2050 ((NONJUMP_INSN_P (X) \
2051 && GET_CODE (PATTERN (X)) != SEQUENCE \
2052 && GET_CODE (PATTERN (X)) != USE \
2053 && GET_CODE (PATTERN (X)) != CLOBBER \
2054 && get_attr_is_sfunc (X)))
2056 #define INSN_REFERENCES_ARE_DELAYED(X) \
2057 ((NONJUMP_INSN_P (X) \
2058 && GET_CODE (PATTERN (X)) != SEQUENCE \
2059 && GET_CODE (PATTERN (X)) != USE \
2060 && GET_CODE (PATTERN (X)) != CLOBBER \
2061 && get_attr_is_sfunc (X)))
2064 /* Position Independent Code. */
2066 /* We can't directly access anything that contains a symbol,
2067 nor can we indirect via the constant pool. */
2068 #define LEGITIMATE_PIC_OPERAND_P(X) \
2069 ((! nonpic_symbol_mentioned_p (X) \
2070 && (GET_CODE (X) != SYMBOL_REF \
2071 || ! CONSTANT_POOL_ADDRESS_P (X) \
2072 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2073 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2075 #define SYMBOLIC_CONST_P(X) \
2076 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2077 && nonpic_symbol_mentioned_p (X))
2079 /* Compute extra cost of moving data between one register class
2082 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2083 uses this information. Hence, the general register <-> floating point
2084 register information here is not used for SFmode. */
2086 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2087 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2088 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2090 #define REGCLASS_HAS_FP_REG(CLASS) \
2091 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2092 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2094 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2095 would be so that people with slow memory systems could generate
2096 different code that does fewer memory accesses. */
2098 /* A C expression for the cost of a branch instruction. A value of 1
2099 is the default; other values are interpreted relative to that.
2100 The SH1 does not have delay slots, hence we get a pipeline stall
2101 at every branch. The SH4 is superscalar, so the single delay slot
2102 is not sufficient to keep both pipelines filled. */
2103 #define BRANCH_COST(speed_p, predictable_p) \
2104 (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2106 /* Assembler output control. */
2108 /* A C string constant describing how to begin a comment in the target
2109 assembler language. The compiler assumes that the comment will end at
2110 the end of the line. */
2111 #define ASM_COMMENT_START "!"
2113 #define ASM_APP_ON ""
2114 #define ASM_APP_OFF ""
2115 #define FILE_ASM_OP "\t.file\n"
2116 #define SET_ASM_OP "\t.set\t"
2118 /* How to change between sections. */
2120 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2121 #define DATA_SECTION_ASM_OP "\t.data"
2123 #if defined CRT_BEGIN || defined CRT_END
2124 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2125 # undef TEXT_SECTION_ASM_OP
2126 # if __SHMEDIA__ == 1 && __SH5__ == 32
2127 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2129 # define TEXT_SECTION_ASM_OP "\t.text"
2134 /* If defined, a C expression whose value is a string containing the
2135 assembler operation to identify the following data as
2136 uninitialized global data. If not defined, and neither
2137 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2138 uninitialized global data will be output in the data section if
2139 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2141 #ifndef BSS_SECTION_ASM_OP
2142 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2145 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2146 separate, explicit argument. If you define this macro, it is used
2147 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2148 handling the required alignment of the variable. The alignment is
2149 specified as the number of bits.
2151 Try to use function `asm_output_aligned_bss' defined in file
2152 `varasm.c' when defining this macro. */
2153 #ifndef ASM_OUTPUT_ALIGNED_BSS
2154 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2155 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2158 /* Define this so that jump tables go in same section as the current function,
2159 which could be text or it could be a user defined section. */
2160 #define JUMP_TABLES_IN_TEXT_SECTION 1
2162 #undef DO_GLOBAL_CTORS_BODY
2163 #define DO_GLOBAL_CTORS_BODY \
2165 typedef void (*pfunc) (void); \
2166 extern pfunc __ctors[]; \
2167 extern pfunc __ctors_end[]; \
2169 for (p = __ctors_end; p > __ctors; ) \
2175 #undef DO_GLOBAL_DTORS_BODY
2176 #define DO_GLOBAL_DTORS_BODY \
2178 typedef void (*pfunc) (void); \
2179 extern pfunc __dtors[]; \
2180 extern pfunc __dtors_end[]; \
2182 for (p = __dtors; p < __dtors_end; p++) \
2188 #define ASM_OUTPUT_REG_PUSH(file, v) \
2190 if (TARGET_SHMEDIA) \
2192 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2193 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2196 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2199 #define ASM_OUTPUT_REG_POP(file, v) \
2201 if (TARGET_SHMEDIA) \
2203 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2204 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2207 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2210 /* DBX register number for a given compiler register number. */
2211 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2213 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2214 register exists, so we should return -1 for invalid register numbers. */
2215 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2217 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2218 used to use the encodings 245..260, but that doesn't make sense:
2219 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2220 the FP registers stay the same when switching between compact and media
2221 mode. Hence, we also need to use the same dwarf frame columns.
2222 Likewise, we need to support unwind information for SHmedia registers
2223 even in compact code. */
2224 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2225 (IN_RANGE ((REGNO), \
2226 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2227 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2228 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2229 : ((int) (REGNO) >= FIRST_FP_REG \
2231 <= (FIRST_FP_REG + \
2232 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2233 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2234 + (TARGET_SH5 ? 77 : 25)) \
2235 : XD_REGISTER_P (REGNO) \
2236 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2237 : TARGET_REGISTER_P (REGNO) \
2238 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2239 : (REGNO) == PR_REG \
2240 ? (TARGET_SH5 ? 18 : 17) \
2241 : (REGNO) == PR_MEDIA_REG \
2242 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2243 : (REGNO) == GBR_REG \
2244 ? (TARGET_SH5 ? 238 : 18) \
2245 : (REGNO) == MACH_REG \
2246 ? (TARGET_SH5 ? 239 : 20) \
2247 : (REGNO) == MACL_REG \
2248 ? (TARGET_SH5 ? 240 : 21) \
2249 : (REGNO) == T_REG \
2250 ? (TARGET_SH5 ? 242 : 22) \
2251 : (REGNO) == FPUL_REG \
2252 ? (TARGET_SH5 ? 244 : 23) \
2253 : (REGNO) == FPSCR_REG \
2254 ? (TARGET_SH5 ? 243 : 24) \
2257 /* This is how to output a reference to a symbol_ref. On SH5,
2258 references to non-code symbols must be preceded by `datalabel'. */
2259 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2262 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2263 fputs ("datalabel ", (FILE)); \
2264 assemble_name ((FILE), XSTR ((SYM), 0)); \
2268 /* This is how to output an assembler line
2269 that says to advance the location counter
2270 to a multiple of 2**LOG bytes. */
2272 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2274 fprintf ((FILE), "\t.align %d\n", (LOG))
2276 /* Globalizing directive for a label. */
2277 #define GLOBAL_ASM_OP "\t.global\t"
2279 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2281 /* Output a relative address table. */
2283 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2284 switch (GET_MODE (BODY)) \
2289 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2293 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2298 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2302 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2307 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2311 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2317 /* Output an absolute table element. */
2319 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2320 if (! optimize || TARGET_BIGTABLE) \
2321 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2323 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2326 /* A C statement to be executed just prior to the output of
2327 assembler code for INSN, to modify the extracted operands so
2328 they will be output differently.
2330 Here the argument OPVEC is the vector containing the operands
2331 extracted from INSN, and NOPERANDS is the number of elements of
2332 the vector which contain meaningful data for this insn.
2333 The contents of this vector are what will be used to convert the insn
2334 template into assembler code, so you can change the assembler output
2335 by changing the contents of the vector. */
2337 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2338 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2341 extern struct rtx_def *sh_compare_op0;
2342 extern struct rtx_def *sh_compare_op1;
2344 /* Which processor to schedule for. The elements of the enumeration must
2345 match exactly the cpu attribute in the sh.md file. */
2347 enum processor_type {
2359 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2360 extern enum processor_type sh_cpu;
2362 enum mdep_reorg_phase_e
2364 SH_BEFORE_MDEP_REORG,
2365 SH_INSERT_USES_LABELS,
2366 SH_SHORTEN_BRANCHES0,
2368 SH_SHORTEN_BRANCHES1,
2372 extern enum mdep_reorg_phase_e mdep_reorg_phase;
2374 /* Handle Renesas compiler's pragmas. */
2375 #define REGISTER_TARGET_PRAGMAS() do { \
2376 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
2377 c_register_pragma (0, "trapa", sh_pr_trapa); \
2378 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
2381 extern tree sh_deferred_function_attributes;
2382 extern tree *sh_deferred_function_attributes_tail;
2384 /* Set when processing a function with interrupt attribute. */
2386 extern int current_function_interrupt;
2389 /* Instructions with unfilled delay slots take up an
2390 extra two bytes for the nop in the delay slot.
2391 sh-dsp parallel processing insns are four bytes long. */
2393 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2394 (LENGTH) += sh_insn_length_adjustment (X);
2396 /* Define this macro if it is advisable to hold scalars in registers
2397 in a wider mode than that declared by the program. In such cases,
2398 the value is constrained to be within the bounds of the declared
2399 type, but kept valid in the wider mode. The signedness of the
2400 extension may differ from that of the type.
2402 Leaving the unsignedp unchanged gives better code than always setting it
2403 to 0. This is despite the fact that we have only signed char and short
2404 load instructions. */
2405 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2406 if (GET_MODE_CLASS (MODE) == MODE_INT \
2407 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
2408 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
2409 (MODE) = (TARGET_SH1 ? SImode \
2410 : TARGET_SHMEDIA32 ? SImode : DImode);
2412 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
2414 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
2416 /* Better to allocate once the maximum space for outgoing args in the
2417 prologue rather than duplicate around each call. */
2418 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
2420 #define SH_DYNAMIC_SHIFT_COST \
2421 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (optimize_size ? 1 : 2) : 20)
2424 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2426 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
2428 #define ACTUAL_NORMAL_MODE(ENTITY) \
2429 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2431 #define NORMAL_MODE(ENTITY) \
2432 (sh_cfun_interrupt_handler_p () \
2433 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
2434 : ACTUAL_NORMAL_MODE (ENTITY))
2436 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
2438 #define MODE_EXIT(ENTITY) \
2439 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
2441 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
2442 && (REGNO) == FPSCR_REG)
2444 #define MODE_NEEDED(ENTITY, INSN) \
2445 (recog_memoized (INSN) >= 0 \
2446 ? get_attr_fp_mode (INSN) \
2449 #define MODE_AFTER(MODE, INSN) \
2451 && recog_memoized (INSN) >= 0 \
2452 && get_attr_fp_set (INSN) != FP_SET_NONE \
2453 ? (int) get_attr_fp_set (INSN) \
2456 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2457 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2459 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2460 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2462 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
2463 sh_can_redirect_branch ((INSN), (SEQ))
2465 #define DWARF_FRAME_RETURN_COLUMN \
2466 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
2468 #define EH_RETURN_DATA_REGNO(N) \
2469 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
2471 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
2472 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
2474 /* We have to distinguish between code and data, so that we apply
2475 datalabel where and only where appropriate. Use sdataN for data. */
2476 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2477 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
2478 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
2479 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
2481 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2482 indirect are handled automatically. */
2483 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2485 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
2486 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
2488 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
2489 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
2494 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
2495 /* SH constant pool breaks the devices in crtstuff.c to control section
2496 in where code resides. We have to write it as asm code. */
2497 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2498 asm (SECTION_OP "\n\
2504 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
2505 2:\n" TEXT_SECTION_ASM_OP);
2506 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
2508 /* FIXME: middle-end support for highpart optimizations is missing. */
2509 #define high_life_started reload_in_progress
2511 #endif /* ! GCC_SH_H */
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