1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
28 #include "insn-config.h"
36 #include "hard-reg-set.h"
38 #include "insn-attr.h"
42 #include "integrate.h"
45 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
54 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
55 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
57 /* These are some macros to abstract register modes. */
58 #define CONST_OK_FOR_ADD(size) \
59 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
60 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
61 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
62 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
64 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
65 int current_function_interrupt;
67 /* ??? The pragma interrupt support will not work for SH3. */
68 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
69 output code for the next function appropriate for an interrupt handler. */
72 /* This is set by the trap_exit attribute for functions. It specifies
73 a trap number to be used in a trapa instruction at function exit
74 (instead of an rte instruction). */
77 /* This is used by the sp_switch attribute for functions. It specifies
78 a variable holding the address of the stack the interrupt function
79 should switch to/from at entry/exit. */
82 /* This is set by #pragma trapa, and is similar to the above, except that
83 the compiler doesn't emit code to preserve all registers. */
84 static int pragma_trapa;
86 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
87 which has a separate set of low regs for User and Supervisor modes.
88 This should only be used for the lowest level of interrupts. Higher levels
89 of interrupts must save the registers in case they themselves are
91 int pragma_nosave_low_regs;
93 /* This is used for communication between SETUP_INCOMING_VARARGS and
94 sh_expand_prologue. */
95 int current_function_anonymous_args;
97 /* Global variables for machine-dependent things. */
99 /* Which cpu are we scheduling for. */
100 enum processor_type sh_cpu;
102 /* Saved operands from the last compare to use when we generate an scc
108 /* Provides the class number of the smallest class containing
111 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
113 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
114 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
130 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
146 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
147 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
148 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
149 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
150 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
154 char sh_register_names[FIRST_PSEUDO_REGISTER] \
155 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
157 char sh_additional_register_names[ADDREGNAMES_SIZE] \
158 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
159 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
161 /* Provide reg_class from a letter such as appears in the machine
162 description. *: target independently reserved letter.
163 reg_class_from_letter['e' - 'a'] is set to NO_REGS for TARGET_FMOVD. */
165 enum reg_class reg_class_from_letter[] =
167 /* a */ ALL_REGS, /* b */ TARGET_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
168 /* e */ FP_REGS, /* f */ FP_REGS, /* g **/ NO_REGS, /* h */ NO_REGS,
169 /* i **/ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
170 /* m **/ NO_REGS, /* n **/ NO_REGS, /* o **/ NO_REGS, /* p **/ NO_REGS,
171 /* q */ NO_REGS, /* r **/ NO_REGS, /* s **/ NO_REGS, /* t */ T_REGS,
172 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
173 /* y */ FPUL_REGS, /* z */ R0_REGS
176 int assembler_dialect;
178 static bool shmedia_space_reserved_for_target_registers;
180 static void split_branches PARAMS ((rtx));
181 static int branch_dest PARAMS ((rtx));
182 static void force_into PARAMS ((rtx, rtx));
183 static void print_slot PARAMS ((rtx));
184 static rtx add_constant PARAMS ((rtx, enum machine_mode, rtx));
185 static void dump_table PARAMS ((rtx));
186 static int hi_const PARAMS ((rtx));
187 static int broken_move PARAMS ((rtx));
188 static int mova_p PARAMS ((rtx));
189 static rtx find_barrier PARAMS ((int, rtx, rtx));
190 static int noncall_uses_reg PARAMS ((rtx, rtx, rtx *));
191 static rtx gen_block_redirect PARAMS ((rtx, int, int));
192 static void sh_reorg PARAMS ((void));
193 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
194 static rtx frame_insn PARAMS ((rtx));
195 static rtx push PARAMS ((int));
196 static void pop PARAMS ((int));
197 static void push_regs PARAMS ((HARD_REG_SET *, int));
198 static int calc_live_regs PARAMS ((HARD_REG_SET *));
199 static void mark_use PARAMS ((rtx, rtx *));
200 static HOST_WIDE_INT rounded_frame_size PARAMS ((int));
201 static rtx mark_constant_pool_use PARAMS ((rtx));
202 const struct attribute_spec sh_attribute_table[];
203 static tree sh_handle_interrupt_handler_attribute PARAMS ((tree *, tree, tree, int, bool *));
204 static tree sh_handle_sp_switch_attribute PARAMS ((tree *, tree, tree, int, bool *));
205 static tree sh_handle_trap_exit_attribute PARAMS ((tree *, tree, tree, int, bool *));
206 static void sh_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
207 static void sh_insert_attributes PARAMS ((tree, tree *));
208 static int sh_adjust_cost PARAMS ((rtx, rtx, rtx, int));
209 static int sh_use_dfa_interface PARAMS ((void));
210 static int sh_issue_rate PARAMS ((void));
211 static bool sh_function_ok_for_sibcall PARAMS ((tree, tree));
213 static bool sh_cannot_modify_jumps_p PARAMS ((void));
214 static int sh_target_reg_class (void);
215 static bool sh_optimize_target_register_callee_saved (bool);
216 static bool sh_ms_bitfield_layout_p PARAMS ((tree));
218 static void sh_init_builtins PARAMS ((void));
219 static void sh_media_init_builtins PARAMS ((void));
220 static rtx sh_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
221 static void sh_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
222 HOST_WIDE_INT, tree));
223 static void sh_file_start PARAMS ((void));
224 static int flow_dependent_p PARAMS ((rtx, rtx));
225 static void flow_dependent_p_1 PARAMS ((rtx, rtx, void *));
226 static int shiftcosts PARAMS ((rtx));
227 static int andcosts PARAMS ((rtx));
228 static int addsubcosts PARAMS ((rtx));
229 static int multcosts PARAMS ((rtx));
230 static bool unspec_caller_rtx_p PARAMS ((rtx));
231 static bool sh_cannot_copy_insn_p PARAMS ((rtx));
232 static bool sh_rtx_costs PARAMS ((rtx, int, int, int *));
233 static int sh_address_cost PARAMS ((rtx));
234 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
235 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
236 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
237 static int scavenge_reg (HARD_REG_SET *s);
238 struct save_schedule_s;
239 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
240 struct save_schedule_s *, int);
242 /* Initialize the GCC target structure. */
243 #undef TARGET_ATTRIBUTE_TABLE
244 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
246 /* The next two are used for debug info when compiling with -gdwarf. */
247 #undef TARGET_ASM_UNALIGNED_HI_OP
248 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
249 #undef TARGET_ASM_UNALIGNED_SI_OP
250 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
252 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
253 #undef TARGET_ASM_UNALIGNED_DI_OP
254 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
255 #undef TARGET_ASM_ALIGNED_DI_OP
256 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
258 #undef TARGET_ASM_FUNCTION_EPILOGUE
259 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
261 #undef TARGET_ASM_OUTPUT_MI_THUNK
262 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
264 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
265 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
267 #undef TARGET_ASM_FILE_START
268 #define TARGET_ASM_FILE_START sh_file_start
269 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
270 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
272 #undef TARGET_INSERT_ATTRIBUTES
273 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
275 #undef TARGET_SCHED_ADJUST_COST
276 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
278 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
279 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
281 #undef TARGET_SCHED_ISSUE_RATE
282 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
284 #undef TARGET_CANNOT_MODIFY_JUMPS_P
285 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
286 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
287 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
288 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
289 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
290 sh_optimize_target_register_callee_saved
292 #undef TARGET_MS_BITFIELD_LAYOUT_P
293 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
295 #undef TARGET_INIT_BUILTINS
296 #define TARGET_INIT_BUILTINS sh_init_builtins
297 #undef TARGET_EXPAND_BUILTIN
298 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
300 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
301 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
303 #undef TARGET_CANNOT_COPY_INSN_P
304 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
305 #undef TARGET_RTX_COSTS
306 #define TARGET_RTX_COSTS sh_rtx_costs
307 #undef TARGET_ADDRESS_COST
308 #define TARGET_ADDRESS_COST sh_address_cost
310 #undef TARGET_MACHINE_DEPENDENT_REORG
311 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
314 #undef TARGET_HAVE_TLS
315 #define TARGET_HAVE_TLS true
318 struct gcc_target targetm = TARGET_INITIALIZER;
320 /* Print the operand address in x to the stream. */
323 print_operand_address (stream, x)
327 switch (GET_CODE (x))
331 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
336 rtx base = XEXP (x, 0);
337 rtx index = XEXP (x, 1);
339 switch (GET_CODE (index))
342 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
343 reg_names[true_regnum (base)]);
349 int base_num = true_regnum (base);
350 int index_num = true_regnum (index);
352 fprintf (stream, "@(r0,%s)",
353 reg_names[MAX (base_num, index_num)]);
365 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
369 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
373 x = mark_constant_pool_use (x);
374 output_addr_const (stream, x);
379 /* Print operand x (an rtx) in assembler syntax to file stream
380 according to modifier code.
382 '.' print a .s if insn needs delay slot
383 ',' print LOCAL_LABEL_PREFIX
384 '@' print trap, rte or rts depending upon pragma interruptness
385 '#' output a nop if there is nothing to put in the delay slot
386 ''' print likelihood suffix (/u for unlikely).
387 'O' print a constant without the #
388 'R' print the LSW of a dp value - changes if in little endian
389 'S' print the MSW of a dp value - changes if in little endian
390 'T' print the next word of a dp value - same as 'R' in big endian mode.
391 'M' print an `x' if `m' will print `base,index'.
392 'N' print 'r63' if the operand is (const_int 0).
393 'm' print a pair `base,offset' or `base,index', for LD and ST.
394 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
395 'o' output an operator. */
398 print_operand (stream, x, code)
407 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
408 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
409 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
412 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
416 fprintf (stream, "trapa #%d", trap_exit);
417 else if (sh_cfun_interrupt_handler_p ())
418 fprintf (stream, "rte");
420 fprintf (stream, "rts");
423 /* Output a nop if there's nothing in the delay slot. */
424 if (dbr_sequence_length () == 0)
425 fprintf (stream, "\n\tnop");
429 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
431 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
432 fputs ("/u", stream);
436 x = mark_constant_pool_use (x);
437 output_addr_const (stream, x);
440 fputs (reg_names[REGNO (x) + LSW], (stream));
443 fputs (reg_names[REGNO (x) + MSW], (stream));
446 /* Next word of a double. */
447 switch (GET_CODE (x))
450 fputs (reg_names[REGNO (x) + 1], (stream));
453 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
454 && GET_CODE (XEXP (x, 0)) != POST_INC)
455 x = adjust_address (x, SImode, 4);
456 print_operand_address (stream, XEXP (x, 0));
463 switch (GET_CODE (x))
465 case PLUS: fputs ("add", stream); break;
466 case MINUS: fputs ("sub", stream); break;
467 case MULT: fputs ("mul", stream); break;
468 case DIV: fputs ("div", stream); break;
469 case EQ: fputs ("eq", stream); break;
470 case NE: fputs ("ne", stream); break;
471 case GT: case LT: fputs ("gt", stream); break;
472 case GE: case LE: fputs ("ge", stream); break;
473 case GTU: case LTU: fputs ("gtu", stream); break;
474 case GEU: case LEU: fputs ("geu", stream); break;
480 if (GET_CODE (x) == MEM
481 && GET_CODE (XEXP (x, 0)) == PLUS
482 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
483 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
488 if (GET_CODE (x) != MEM)
491 switch (GET_CODE (x))
495 print_operand (stream, x, 0);
496 fputs (", 0", stream);
500 print_operand (stream, XEXP (x, 0), 0);
501 fputs (", ", stream);
502 print_operand (stream, XEXP (x, 1), 0);
511 if (x == CONST0_RTX (GET_MODE (x)))
513 fprintf ((stream), "r63");
518 if (GET_CODE (x) == CONST_INT)
520 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
527 switch (GET_CODE (x))
529 /* FIXME: We need this on SHmedia32 because reload generates
530 some sign-extended HI or QI loads into DImode registers
531 but, because Pmode is SImode, the address ends up with a
532 subreg:SI of the DImode register. Maybe reload should be
533 fixed so as to apply alter_subreg to such loads? */
535 if (SUBREG_BYTE (x) != 0
536 || GET_CODE (SUBREG_REG (x)) != REG)
543 if (FP_REGISTER_P (REGNO (x))
544 && GET_MODE (x) == V16SFmode)
545 fprintf ((stream), "mtrx%s", reg_names[REGNO (x)] + 2);
546 else if (FP_REGISTER_P (REGNO (x))
547 && GET_MODE (x) == V4SFmode)
548 fprintf ((stream), "fv%s", reg_names[REGNO (x)] + 2);
549 else if (GET_CODE (x) == REG
550 && GET_MODE (x) == V2SFmode)
551 fprintf ((stream), "fp%s", reg_names[REGNO (x)] + 2);
552 else if (FP_REGISTER_P (REGNO (x))
553 && GET_MODE_SIZE (GET_MODE (x)) > 4)
554 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
556 fputs (reg_names[REGNO (x)], (stream));
560 output_address (XEXP (x, 0));
565 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
566 && GET_MODE (XEXP (x, 0)) == DImode
567 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
568 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
570 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
573 if (GET_CODE (val) == ASHIFTRT)
576 if (GET_CODE (XEXP (val, 0)) == CONST)
578 output_addr_const (stream, XEXP (val, 0));
579 if (GET_CODE (XEXP (val, 0)) == CONST)
581 fputs (" >> ", stream);
582 output_addr_const (stream, XEXP (val, 1));
587 if (GET_CODE (val) == CONST)
589 output_addr_const (stream, val);
590 if (GET_CODE (val) == CONST)
593 fputs (" & 65535)", stream);
601 output_addr_const (stream, x);
608 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
610 force_into (value, target)
613 value = force_operand (value, target);
614 if (! rtx_equal_p (value, target))
615 emit_insn (gen_move_insn (target, value));
618 /* Emit code to perform a block move. Choose the best method.
620 OPERANDS[0] is the destination.
621 OPERANDS[1] is the source.
622 OPERANDS[2] is the size.
623 OPERANDS[3] is the alignment safe to use. */
626 expand_block_move (operands)
629 int align = INTVAL (operands[3]);
630 int constp = (GET_CODE (operands[2]) == CONST_INT);
631 int bytes = (constp ? INTVAL (operands[2]) : 0);
633 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
634 alignment, or if it isn't a multiple of 4 bytes, then fail. */
635 if (! constp || align < 4 || (bytes % 4 != 0))
642 else if (bytes == 12)
647 rtx r4 = gen_rtx (REG, SImode, 4);
648 rtx r5 = gen_rtx (REG, SImode, 5);
650 entry_name = get_identifier ("__movstrSI12_i4");
652 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
653 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
654 force_into (XEXP (operands[0], 0), r4);
655 force_into (XEXP (operands[1], 0), r5);
656 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
659 else if (! TARGET_SMALLCODE)
665 rtx r4 = gen_rtx (REG, SImode, 4);
666 rtx r5 = gen_rtx (REG, SImode, 5);
667 rtx r6 = gen_rtx (REG, SImode, 6);
669 entry_name = get_identifier (bytes & 4
671 : "__movstr_i4_even");
672 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
673 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
674 force_into (XEXP (operands[0], 0), r4);
675 force_into (XEXP (operands[1], 0), r5);
678 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
679 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
691 rtx r4 = gen_rtx_REG (SImode, 4);
692 rtx r5 = gen_rtx_REG (SImode, 5);
694 sprintf (entry, "__movstrSI%d", bytes);
695 entry_name = get_identifier (entry);
696 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
697 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
698 force_into (XEXP (operands[0], 0), r4);
699 force_into (XEXP (operands[1], 0), r5);
700 emit_insn (gen_block_move_real (func_addr_rtx));
704 /* This is the same number of bytes as a memcpy call, but to a different
705 less common function name, so this will occasionally use more space. */
706 if (! TARGET_SMALLCODE)
711 int final_switch, while_loop;
712 rtx r4 = gen_rtx_REG (SImode, 4);
713 rtx r5 = gen_rtx_REG (SImode, 5);
714 rtx r6 = gen_rtx_REG (SImode, 6);
716 entry_name = get_identifier ("__movstr");
717 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
718 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
719 force_into (XEXP (operands[0], 0), r4);
720 force_into (XEXP (operands[1], 0), r5);
722 /* r6 controls the size of the move. 16 is decremented from it
723 for each 64 bytes moved. Then the negative bit left over is used
724 as an index into a list of move instructions. e.g., a 72 byte move
725 would be set up with size(r6) = 14, for one iteration through the
726 big while loop, and a switch of -2 for the last part. */
728 final_switch = 16 - ((bytes / 4) % 16);
729 while_loop = ((bytes / 4) / 16 - 1) * 16;
730 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
731 emit_insn (gen_block_lump_real (func_addr_rtx));
738 /* Prepare operands for a move define_expand; specifically, one of the
739 operands must be in a register. */
742 prepare_move_operands (operands, mode)
744 enum machine_mode mode;
746 if ((mode == SImode || mode == DImode)
748 && ! ((mode == Pmode || mode == ptr_mode)
749 && tls_symbolic_operand (operands[1], Pmode) != 0))
752 if (SYMBOLIC_CONST_P (operands[1]))
754 if (GET_CODE (operands[0]) == MEM)
755 operands[1] = force_reg (Pmode, operands[1]);
756 else if (TARGET_SHMEDIA
757 && GET_CODE (operands[1]) == LABEL_REF
758 && target_reg_operand (operands[0], mode))
762 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
763 operands[1] = legitimize_pic_address (operands[1], mode, temp);
766 else if (GET_CODE (operands[1]) == CONST
767 && GET_CODE (XEXP (operands[1], 0)) == PLUS
768 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
770 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
771 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
773 operands[1] = expand_binop (mode, add_optab, temp,
774 XEXP (XEXP (operands[1], 0), 1),
775 no_new_pseudos ? temp
776 : gen_reg_rtx (Pmode),
781 if (! reload_in_progress && ! reload_completed)
783 /* Copy the source to a register if both operands aren't registers. */
784 if (! register_operand (operands[0], mode)
785 && ! sh_register_operand (operands[1], mode))
786 operands[1] = copy_to_mode_reg (mode, operands[1]);
788 if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode))
790 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
791 except that we can't use that function because it is static. */
792 rtx new = change_address (operands[0], mode, 0);
793 MEM_COPY_ATTRIBUTES (new, operands[0]);
797 /* This case can happen while generating code to move the result
798 of a library call to the target. Reject `st r0,@(rX,rY)' because
799 reload will fail to find a spill register for rX, since r0 is already
800 being used for the source. */
801 else if (refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
802 && GET_CODE (operands[0]) == MEM
803 && GET_CODE (XEXP (operands[0], 0)) == PLUS
804 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
805 operands[1] = copy_to_mode_reg (mode, operands[1]);
808 if (mode == Pmode || mode == ptr_mode)
811 enum tls_model tls_kind;
815 if ((tls_kind = tls_symbolic_operand (op1, Pmode)))
817 rtx tga_op1, tga_ret, tmp, tmp2;
822 case TLS_MODEL_GLOBAL_DYNAMIC:
823 tga_ret = gen_rtx_REG (Pmode, R0_REG);
824 emit_insn (gen_tls_global_dynamic (tga_ret, op1));
828 case TLS_MODEL_LOCAL_DYNAMIC:
829 tga_ret = gen_rtx_REG (Pmode, R0_REG);
830 emit_insn (gen_tls_local_dynamic (tga_ret, op1));
832 tmp = gen_reg_rtx (Pmode);
833 emit_move_insn (tmp, tga_ret);
835 if (register_operand (op0, Pmode))
838 tmp2 = gen_reg_rtx (Pmode);
840 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
844 case TLS_MODEL_INITIAL_EXEC:
846 emit_insn (gen_GOTaddr2picreg ());
847 tga_op1 = gen_reg_rtx (Pmode);
848 tmp = gen_sym2GOTTPOFF (op1);
849 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
853 case TLS_MODEL_LOCAL_EXEC:
854 tmp2 = gen_reg_rtx (Pmode);
855 emit_insn (gen_load_gbr (tmp2));
856 tmp = gen_reg_rtx (Pmode);
857 emit_insn (gen_symTPOFF2reg (tmp, op1));
858 RTX_UNCHANGING_P (tmp) = 1;
860 if (register_operand (op0, Pmode))
863 op1 = gen_reg_rtx (Pmode);
865 emit_insn (gen_addsi3 (op1, tmp, tmp2));
878 /* Prepare the operands for an scc instruction; make sure that the
879 compare has been done. */
881 prepare_scc_operands (code)
884 rtx t_reg = gen_rtx_REG (SImode, T_REG);
885 enum rtx_code oldcode = code;
886 enum machine_mode mode;
888 /* First need a compare insn. */
892 /* It isn't possible to handle this case. */
911 rtx tmp = sh_compare_op0;
912 sh_compare_op0 = sh_compare_op1;
913 sh_compare_op1 = tmp;
916 mode = GET_MODE (sh_compare_op0);
917 if (mode == VOIDmode)
918 mode = GET_MODE (sh_compare_op1);
920 sh_compare_op0 = force_reg (mode, sh_compare_op0);
921 if ((code != EQ && code != NE
922 && (sh_compare_op1 != const0_rtx
923 || code == GTU || code == GEU || code == LTU || code == LEU))
924 || (mode == DImode && sh_compare_op1 != const0_rtx)
925 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
926 sh_compare_op1 = force_reg (mode, sh_compare_op1);
928 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
929 (mode == SFmode ? emit_sf_insn : emit_df_insn)
930 (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
931 gen_rtx (SET, VOIDmode, t_reg,
932 gen_rtx (code, SImode,
933 sh_compare_op0, sh_compare_op1)),
934 gen_rtx (USE, VOIDmode, get_fpscr_rtx ()))));
936 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
937 gen_rtx (code, SImode, sh_compare_op0,
943 /* Called from the md file, set up the operands of a compare instruction. */
946 from_compare (operands, code)
950 enum machine_mode mode = GET_MODE (sh_compare_op0);
952 if (mode == VOIDmode)
953 mode = GET_MODE (sh_compare_op1);
956 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
958 /* Force args into regs, since we can't use constants here. */
959 sh_compare_op0 = force_reg (mode, sh_compare_op0);
960 if (sh_compare_op1 != const0_rtx
961 || code == GTU || code == GEU
962 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
963 sh_compare_op1 = force_reg (mode, sh_compare_op1);
965 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
967 from_compare (operands, GT);
968 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
971 insn = gen_rtx_SET (VOIDmode,
972 gen_rtx_REG (SImode, T_REG),
973 gen_rtx (code, SImode, sh_compare_op0,
975 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
977 insn = gen_rtx (PARALLEL, VOIDmode,
979 gen_rtx (USE, VOIDmode, get_fpscr_rtx ())));
980 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
986 /* Functions to output assembly code. */
988 /* Return a sequence of instructions to perform DI or DF move.
990 Since the SH cannot move a DI or DF in one instruction, we have
991 to take care when we see overlapping source and dest registers. */
994 output_movedouble (insn, operands, mode)
995 rtx insn ATTRIBUTE_UNUSED;
997 enum machine_mode mode;
999 rtx dst = operands[0];
1000 rtx src = operands[1];
1002 if (GET_CODE (dst) == MEM
1003 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
1004 return "mov.l %T1,%0\n\tmov.l %1,%0";
1006 if (register_operand (dst, mode)
1007 && register_operand (src, mode))
1009 if (REGNO (src) == MACH_REG)
1010 return "sts mach,%S0\n\tsts macl,%R0";
1012 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1013 when mov.d r1,r0 do r1->r0 then r2->r1. */
1015 if (REGNO (src) + 1 == REGNO (dst))
1016 return "mov %T1,%T0\n\tmov %1,%0";
1018 return "mov %1,%0\n\tmov %T1,%T0";
1020 else if (GET_CODE (src) == CONST_INT)
1022 if (INTVAL (src) < 0)
1023 output_asm_insn ("mov #-1,%S0", operands);
1025 output_asm_insn ("mov #0,%S0", operands);
1027 return "mov %1,%R0";
1029 else if (GET_CODE (src) == MEM)
1032 int dreg = REGNO (dst);
1033 rtx inside = XEXP (src, 0);
1035 if (GET_CODE (inside) == REG)
1036 ptrreg = REGNO (inside);
1037 else if (GET_CODE (inside) == SUBREG)
1038 ptrreg = subreg_regno (inside);
1039 else if (GET_CODE (inside) == PLUS)
1041 ptrreg = REGNO (XEXP (inside, 0));
1042 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1043 an offsettable address. Unfortunately, offsettable addresses use
1044 QImode to check the offset, and a QImode offsettable address
1045 requires r0 for the other operand, which is not currently
1046 supported, so we can't use the 'o' constraint.
1047 Thus we must check for and handle r0+REG addresses here.
1048 We punt for now, since this is likely very rare. */
1049 if (GET_CODE (XEXP (inside, 1)) == REG)
1052 else if (GET_CODE (inside) == LABEL_REF)
1053 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1054 else if (GET_CODE (inside) == POST_INC)
1055 return "mov.l %1,%0\n\tmov.l %1,%T0";
1059 /* Work out the safe way to copy. Copy into the second half first. */
1061 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1064 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1067 /* Print an instruction which would have gone into a delay slot after
1068 another instruction, but couldn't because the other instruction expanded
1069 into a sequence where putting the slot insn at the end wouldn't work. */
1075 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
1077 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1081 output_far_jump (insn, op)
1085 struct { rtx lab, reg, op; } this;
1086 rtx braf_base_lab = NULL_RTX;
1089 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
1092 this.lab = gen_label_rtx ();
1096 && offset - get_attr_length (insn) <= 32766)
1099 jump = "mov.w %O0,%1; braf %1";
1107 jump = "mov.l %O0,%1; braf %1";
1109 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1112 jump = "mov.l %O0,%1; jmp @%1";
1114 /* If we have a scratch register available, use it. */
1115 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
1116 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1118 this.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
1119 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1120 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1121 output_asm_insn (jump, &this.lab);
1122 if (dbr_sequence_length ())
1123 print_slot (final_sequence);
1125 output_asm_insn ("nop", 0);
1129 /* Output the delay slot insn first if any. */
1130 if (dbr_sequence_length ())
1131 print_slot (final_sequence);
1133 this.reg = gen_rtx_REG (SImode, 13);
1134 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1135 Fortunately, MACL is fixed and call-clobbered, and we never
1136 need its value across jumps, so save r13 in it instead of in
1139 output_asm_insn ("lds r13, macl", 0);
1141 output_asm_insn ("mov.l r13,@-r15", 0);
1142 output_asm_insn (jump, &this.lab);
1144 output_asm_insn ("sts macl, r13", 0);
1146 output_asm_insn ("mov.l @r15+,r13", 0);
1148 if (far && flag_pic && TARGET_SH2)
1150 braf_base_lab = gen_label_rtx ();
1151 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1152 CODE_LABEL_NUMBER (braf_base_lab));
1155 output_asm_insn (".align 2", 0);
1156 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
1158 if (far && flag_pic)
1161 this.lab = braf_base_lab;
1162 output_asm_insn (".long %O2-%O0", &this.lab);
1165 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
1169 /* Local label counter, used for constants in the pool and inside
1170 pattern branches. */
1172 static int lf = 100;
1174 /* Output code for ordinary branches. */
1177 output_branch (logic, insn, operands)
1182 switch (get_attr_length (insn))
1185 /* This can happen if filling the delay slot has caused a forward
1186 branch to exceed its range (we could reverse it, but only
1187 when we know we won't overextend other branches; this should
1188 best be handled by relaxation).
1189 It can also happen when other condbranches hoist delay slot insn
1190 from their destination, thus leading to code size increase.
1191 But the branch will still be in the range -4092..+4098 bytes. */
1196 /* The call to print_slot will clobber the operands. */
1197 rtx op0 = operands[0];
1199 /* If the instruction in the delay slot is annulled (true), then
1200 there is no delay slot where we can put it now. The only safe
1201 place for it is after the label. final will do that by default. */
1204 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1206 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
1207 ASSEMBLER_DIALECT ? "/" : ".", label);
1208 print_slot (final_sequence);
1211 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
1213 output_asm_insn ("bra\t%l0", &op0);
1214 fprintf (asm_out_file, "\tnop\n");
1215 (*targetm.asm_out.internal_label)(asm_out_file, "LF", label);
1219 /* When relaxing, handle this like a short branch. The linker
1220 will fix it up if it still doesn't fit after relaxation. */
1222 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
1224 /* These are for SH2e, in which we have to account for the
1225 extra nop because of the hardware bug in annulled branches. */
1232 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1234 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
1236 ASSEMBLER_DIALECT ? "/" : ".", label);
1237 fprintf (asm_out_file, "\tnop\n");
1238 output_asm_insn ("bra\t%l0", operands);
1239 fprintf (asm_out_file, "\tnop\n");
1240 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
1244 /* When relaxing, fall through. */
1249 sprintf (buffer, "b%s%ss\t%%l0",
1251 ASSEMBLER_DIALECT ? "/" : ".");
1252 output_asm_insn (buffer, &operands[0]);
1257 /* There should be no longer branches now - that would
1258 indicate that something has destroyed the branches set
1259 up in machine_dependent_reorg. */
1265 output_branchy_insn (code, template, insn, operands)
1267 const char *template;
1271 rtx next_insn = NEXT_INSN (insn);
1273 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
1275 rtx src = SET_SRC (PATTERN (next_insn));
1276 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
1278 /* Following branch not taken */
1279 operands[9] = gen_label_rtx ();
1280 emit_label_after (operands[9], next_insn);
1281 INSN_ADDRESSES_NEW (operands[9],
1282 INSN_ADDRESSES (INSN_UID (next_insn))
1283 + get_attr_length (next_insn));
1288 int offset = (branch_dest (next_insn)
1289 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
1290 if (offset >= -252 && offset <= 258)
1292 if (GET_CODE (src) == IF_THEN_ELSE)
1294 src = XEXP (src, 1);
1300 operands[9] = gen_label_rtx ();
1301 emit_label_after (operands[9], insn);
1302 INSN_ADDRESSES_NEW (operands[9],
1303 INSN_ADDRESSES (INSN_UID (insn))
1304 + get_attr_length (insn));
1309 output_ieee_ccmpeq (insn, operands)
1310 rtx insn, *operands;
1312 return output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
1315 /* Output the start of the assembler file. */
1320 default_file_start ();
1323 /* We need to show the text section with the proper
1324 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
1325 emits it without attributes in TEXT_SECTION, else GAS
1326 will complain. We can teach GAS specifically about the
1327 default attributes for our choice of text section, but
1328 then we would have to change GAS again if/when we change
1329 the text section name. */
1330 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
1332 /* Switch to the data section so that the coffsem symbol
1333 isn't in the text section. */
1336 if (TARGET_LITTLE_ENDIAN)
1337 fputs ("\t.little\n", asm_out_file);
1341 if (TARGET_SHCOMPACT)
1342 fputs ("\t.mode\tSHcompact\n", asm_out_file);
1343 else if (TARGET_SHMEDIA)
1344 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1345 TARGET_SHMEDIA64 ? 64 : 32);
1349 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
1352 unspec_caller_rtx_p (pat)
1355 switch (GET_CODE (pat))
1358 return unspec_caller_rtx_p (XEXP (pat, 0));
1361 if (unspec_caller_rtx_p (XEXP (pat, 0)))
1363 return unspec_caller_rtx_p (XEXP (pat, 1));
1365 if (XINT (pat, 1) == UNSPEC_CALLER)
1374 /* Indicate that INSN cannot be duplicated. This is true for insn
1375 that generates an unique label. */
1378 sh_cannot_copy_insn_p (insn)
1383 if (!reload_completed || !flag_pic)
1386 if (GET_CODE (insn) != INSN)
1388 if (asm_noperands (insn) >= 0)
1391 pat = PATTERN (insn);
1392 if (GET_CODE (pat) != SET)
1394 pat = SET_SRC (pat);
1396 if (unspec_caller_rtx_p (pat))
1402 /* Actual number of instructions used to make a shift by N. */
1403 static const char ashiftrt_insns[] =
1404 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1406 /* Left shift and logical right shift are the same. */
1407 static const char shift_insns[] =
1408 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1410 /* Individual shift amounts needed to get the above length sequences.
1411 One bit right shifts clobber the T bit, so when possible, put one bit
1412 shifts in the middle of the sequence, so the ends are eligible for
1413 branch delay slots. */
1414 static const short shift_amounts[32][5] = {
1415 {0}, {1}, {2}, {2, 1},
1416 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1417 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1418 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1419 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1420 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1421 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1422 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1424 /* Likewise, but for shift amounts < 16, up to three highmost bits
1425 might be clobbered. This is typically used when combined with some
1426 kind of sign or zero extension. */
1428 static const char ext_shift_insns[] =
1429 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1431 static const short ext_shift_amounts[32][4] = {
1432 {0}, {1}, {2}, {2, 1},
1433 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1434 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1435 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1436 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1437 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1438 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1439 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1441 /* Assuming we have a value that has been sign-extended by at least one bit,
1442 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1443 to shift it by N without data loss, and quicker than by other means? */
1444 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1446 /* This is used in length attributes in sh.md to help compute the length
1447 of arbitrary constant shift instructions. */
1450 shift_insns_rtx (insn)
1453 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1454 int shift_count = INTVAL (XEXP (set_src, 1));
1455 enum rtx_code shift_code = GET_CODE (set_src);
1460 return ashiftrt_insns[shift_count];
1463 return shift_insns[shift_count];
1469 /* Return the cost of a shift. */
1480 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
1482 if (GET_MODE (x) == DImode
1483 && GET_CODE (XEXP (x, 1)) == CONST_INT
1484 && INTVAL (XEXP (x, 1)) == 1)
1487 /* Everything else is invalid, because there is no pattern for it. */
1490 /* If shift by a non constant, then this will be expensive. */
1491 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1492 return SH_DYNAMIC_SHIFT_COST;
1494 value = INTVAL (XEXP (x, 1));
1496 /* Otherwise, return the true cost in instructions. */
1497 if (GET_CODE (x) == ASHIFTRT)
1499 int cost = ashiftrt_insns[value];
1500 /* If SH3, then we put the constant in a reg and use shad. */
1501 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
1502 cost = 1 + SH_DYNAMIC_SHIFT_COST;
1506 return shift_insns[value];
1509 /* Return the cost of an AND operation. */
1517 /* Anding with a register is a single cycle and instruction. */
1518 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1521 i = INTVAL (XEXP (x, 1));
1525 if ((GET_CODE (XEXP (x, 1)) == CONST_INT
1526 && CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
1527 || EXTRA_CONSTRAINT_C16 (XEXP (x, 1)))
1533 /* These constants are single cycle extu.[bw] instructions. */
1534 if (i == 0xff || i == 0xffff)
1536 /* Constants that can be used in an and immediate instruction in a single
1537 cycle, but this requires r0, so make it a little more expensive. */
1538 if (CONST_OK_FOR_K08 (i))
1540 /* Constants that can be loaded with a mov immediate and an and.
1541 This case is probably unnecessary. */
1542 if (CONST_OK_FOR_I08 (i))
1544 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1545 This case is probably unnecessary. */
1549 /* Return the cost of an addition or a subtraction. */
1555 /* Adding a register is a single cycle insn. */
1556 if (GET_CODE (XEXP (x, 1)) == REG
1557 || GET_CODE (XEXP (x, 1)) == SUBREG)
1560 /* Likewise for small constants. */
1561 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1562 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
1566 switch (GET_CODE (XEXP (x, 1)))
1571 return TARGET_SHMEDIA64 ? 5 : 3;
1574 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
1576 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
1578 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
1586 /* Any other constant requires a 2 cycle pc-relative load plus an
1591 /* Return the cost of a multiply. */
1594 rtx x ATTRIBUTE_UNUSED;
1601 /* We have a mul insn, so we can never take more than the mul and the
1602 read of the mac reg, but count more because of the latency and extra
1604 if (TARGET_SMALLCODE)
1609 /* If we're aiming at small code, then just count the number of
1610 insns in a multiply call sequence. */
1611 if (TARGET_SMALLCODE)
1614 /* Otherwise count all the insns in the routine we'd be calling too. */
1618 /* Compute a (partial) cost for rtx X. Return true if the complete
1619 cost has been computed, and false if subexpressions should be
1620 scanned. In either case, *TOTAL contains the cost result. */
1623 sh_rtx_costs (x, code, outer_code, total)
1625 int code, outer_code, *total;
1632 if (INTVAL (x) == 0)
1634 else if (outer_code == AND && and_operand ((x), DImode))
1636 else if ((outer_code == IOR || outer_code == XOR
1637 || outer_code == PLUS)
1638 && CONST_OK_FOR_I10 (INTVAL (x)))
1640 else if (CONST_OK_FOR_I16 (INTVAL (x)))
1641 *total = COSTS_N_INSNS (outer_code != SET);
1642 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
1643 *total = COSTS_N_INSNS (2);
1644 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
1645 *total = COSTS_N_INSNS (3);
1647 *total = COSTS_N_INSNS (4);
1650 if (CONST_OK_FOR_I08 (INTVAL (x)))
1652 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
1653 && CONST_OK_FOR_K08 (INTVAL (x)))
1662 if (TARGET_SHMEDIA64)
1663 *total = COSTS_N_INSNS (4);
1664 else if (TARGET_SHMEDIA32)
1665 *total = COSTS_N_INSNS (2);
1672 *total = COSTS_N_INSNS (4);
1678 *total = COSTS_N_INSNS (addsubcosts (x));
1682 *total = COSTS_N_INSNS (andcosts (x));
1686 *total = COSTS_N_INSNS (multcosts (x));
1692 *total = COSTS_N_INSNS (shiftcosts (x));
1699 *total = COSTS_N_INSNS (20);
1712 /* Compute the cost of an address. For the SH, all valid addresses are
1713 the same cost. Use a slightly higher cost for reg + reg addressing,
1714 since it increases pressure on r0. */
1720 return (GET_CODE (X) == PLUS
1721 && ! CONSTANT_P (XEXP (X, 1))
1722 && ! TARGET_SHMEDIA ? 1 : 0);
1725 /* Code to expand a shift. */
1728 gen_ashift (type, n, reg)
1733 /* Negative values here come from the shift_amounts array. */
1746 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
1750 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
1752 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
1755 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
1760 /* Same for HImode */
1763 gen_ashift_hi (type, n, reg)
1768 /* Negative values here come from the shift_amounts array. */
1782 /* We don't have HImode right shift operations because using the
1783 ordinary 32 bit shift instructions for that doesn't generate proper
1784 zero/sign extension.
1785 gen_ashift_hi is only called in contexts where we know that the
1786 sign extension works out correctly. */
1789 if (GET_CODE (reg) == SUBREG)
1791 offset = SUBREG_BYTE (reg);
1792 reg = SUBREG_REG (reg);
1794 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
1798 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
1803 /* Output RTL to split a constant shift into its component SH constant
1804 shift instructions. */
1807 gen_shifty_op (code, operands)
1811 int value = INTVAL (operands[2]);
1814 /* Truncate the shift count in case it is out of bounds. */
1815 value = value & 0x1f;
1819 if (code == LSHIFTRT)
1821 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1822 emit_insn (gen_movt (operands[0]));
1825 else if (code == ASHIFT)
1827 /* There is a two instruction sequence for 31 bit left shifts,
1828 but it requires r0. */
1829 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
1831 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
1832 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1837 else if (value == 0)
1839 /* This can happen when not optimizing. We must output something here
1840 to prevent the compiler from aborting in final.c after the try_split
1842 emit_insn (gen_nop ());
1846 max = shift_insns[value];
1847 for (i = 0; i < max; i++)
1848 gen_ashift (code, shift_amounts[value][i], operands[0]);
1851 /* Same as above, but optimized for values where the topmost bits don't
1855 gen_shifty_hi_op (code, operands)
1859 int value = INTVAL (operands[2]);
1861 void (*gen_fun) PARAMS ((int, int, rtx));
1863 /* This operation is used by and_shl for SImode values with a few
1864 high bits known to be cleared. */
1868 emit_insn (gen_nop ());
1872 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
1875 max = ext_shift_insns[value];
1876 for (i = 0; i < max; i++)
1877 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1880 /* When shifting right, emit the shifts in reverse order, so that
1881 solitary negative values come first. */
1882 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
1883 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1886 /* Output RTL for an arithmetic right shift. */
1888 /* ??? Rewrite to use super-optimizer sequences. */
1891 expand_ashiftrt (operands)
1902 if (GET_CODE (operands[2]) != CONST_INT)
1904 rtx count = copy_to_mode_reg (SImode, operands[2]);
1905 emit_insn (gen_negsi2 (count, count));
1906 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1909 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
1910 > 1 + SH_DYNAMIC_SHIFT_COST)
1913 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
1914 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1918 if (GET_CODE (operands[2]) != CONST_INT)
1921 value = INTVAL (operands[2]) & 31;
1925 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
1928 else if (value >= 16 && value <= 19)
1930 wrk = gen_reg_rtx (SImode);
1931 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
1934 gen_ashift (ASHIFTRT, 1, wrk);
1935 emit_move_insn (operands[0], wrk);
1938 /* Expand a short sequence inline, longer call a magic routine. */
1939 else if (value <= 5)
1941 wrk = gen_reg_rtx (SImode);
1942 emit_move_insn (wrk, operands[1]);
1944 gen_ashift (ASHIFTRT, 1, wrk);
1945 emit_move_insn (operands[0], wrk);
1949 wrk = gen_reg_rtx (Pmode);
1951 /* Load the value into an arg reg and call a helper. */
1952 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1953 sprintf (func, "__ashiftrt_r4_%d", value);
1954 func_name = get_identifier (func);
1955 sym = function_symbol (IDENTIFIER_POINTER (func_name));
1956 emit_move_insn (wrk, sym);
1957 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1958 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
1963 sh_dynamicalize_shift_p (count)
1966 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
1969 /* Try to find a good way to implement the combiner pattern
1970 [(set (match_operand:SI 0 "register_operand" "r")
1971 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1972 (match_operand:SI 2 "const_int_operand" "n"))
1973 (match_operand:SI 3 "const_int_operand" "n"))) .
1974 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1975 return 0 for simple right / left or left/right shift combination.
1976 return 1 for a combination of shifts with zero_extend.
1977 return 2 for a combination of shifts with an AND that needs r0.
1978 return 3 for a combination of shifts with an AND that needs an extra
1979 scratch register, when the three highmost bits of the AND mask are clear.
1980 return 4 for a combination of shifts with an AND that needs an extra
1981 scratch register, when any of the three highmost bits of the AND mask
1983 If ATTRP is set, store an initial right shift width in ATTRP[0],
1984 and the instruction length in ATTRP[1] . These values are not valid
1986 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1987 shift_amounts for the last shift value that is to be used before the
1990 shl_and_kind (left_rtx, mask_rtx, attrp)
1991 rtx left_rtx, mask_rtx;
1994 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
1995 int left = INTVAL (left_rtx), right;
1997 int cost, best_cost = 10000;
1998 int best_right = 0, best_len = 0;
2002 if (left < 0 || left > 31)
2004 if (GET_CODE (mask_rtx) == CONST_INT)
2005 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
2007 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
2008 /* Can this be expressed as a right shift / left shift pair ? */
2009 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
2010 right = exact_log2 (lsb);
2011 mask2 = ~(mask + lsb - 1);
2012 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
2013 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
2015 best_cost = shift_insns[right] + shift_insns[right + left];
2016 /* mask has no trailing zeroes <==> ! right */
2017 else if (! right && mask2 == ~(lsb2 - 1))
2019 int late_right = exact_log2 (lsb2);
2020 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
2022 /* Try to use zero extend */
2023 if (mask2 == ~(lsb2 - 1))
2027 for (width = 8; width <= 16; width += 8)
2029 /* Can we zero-extend right away? */
2030 if (lsb2 == (unsigned HOST_WIDE_INT)1 << width)
2033 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
2034 if (cost < best_cost)
2045 /* ??? Could try to put zero extend into initial right shift,
2046 or even shift a bit left before the right shift. */
2047 /* Determine value of first part of left shift, to get to the
2048 zero extend cut-off point. */
2049 first = width - exact_log2 (lsb2) + right;
2050 if (first >= 0 && right + left - first >= 0)
2052 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
2053 + ext_shift_insns[right + left - first];
2054 if (cost < best_cost)
2066 /* Try to use r0 AND pattern */
2067 for (i = 0; i <= 2; i++)
2071 if (! CONST_OK_FOR_K08 (mask >> i))
2073 cost = (i != 0) + 2 + ext_shift_insns[left + i];
2074 if (cost < best_cost)
2079 best_len = cost - 1;
2082 /* Try to use a scratch register to hold the AND operand. */
2083 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT)3 << 30)) == 0;
2084 for (i = 0; i <= 2; i++)
2088 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
2089 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
2090 if (cost < best_cost)
2095 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
2101 attrp[0] = best_right;
2102 attrp[1] = best_len;
2107 /* This is used in length attributes of the unnamed instructions
2108 corresponding to shl_and_kind return values of 1 and 2. */
2110 shl_and_length (insn)
2113 rtx set_src, left_rtx, mask_rtx;
2116 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2117 left_rtx = XEXP (XEXP (set_src, 0), 1);
2118 mask_rtx = XEXP (set_src, 1);
2119 shl_and_kind (left_rtx, mask_rtx, attributes);
2120 return attributes[1];
2123 /* This is used in length attribute of the and_shl_scratch instruction. */
2126 shl_and_scr_length (insn)
2129 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2130 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
2131 rtx op = XEXP (set_src, 0);
2132 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
2133 op = XEXP (XEXP (op, 0), 0);
2134 return len + shift_insns[INTVAL (XEXP (op, 1))];
2137 /* Generating rtl? */
2138 extern int rtx_equal_function_value_matters;
2140 /* Generate rtl for instructions for which shl_and_kind advised a particular
2141 method of generating them, i.e. returned zero. */
2144 gen_shl_and (dest, left_rtx, mask_rtx, source)
2145 rtx dest, left_rtx, mask_rtx, source;
2148 unsigned HOST_WIDE_INT mask;
2149 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
2150 int right, total_shift;
2151 void (*shift_gen_fun) PARAMS ((int, rtx*)) = gen_shifty_hi_op;
2153 right = attributes[0];
2154 total_shift = INTVAL (left_rtx) + right;
2155 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
2162 int first = attributes[2];
2167 emit_insn ((mask << right) <= 0xff
2168 ? gen_zero_extendqisi2(dest,
2169 gen_lowpart (QImode, source))
2170 : gen_zero_extendhisi2(dest,
2171 gen_lowpart (HImode, source)));
2175 emit_insn (gen_movsi (dest, source));
2179 operands[2] = GEN_INT (right);
2180 gen_shifty_hi_op (LSHIFTRT, operands);
2184 operands[2] = GEN_INT (first);
2185 gen_shifty_hi_op (ASHIFT, operands);
2186 total_shift -= first;
2190 emit_insn (mask <= 0xff
2191 ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
2192 : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
2193 if (total_shift > 0)
2195 operands[2] = GEN_INT (total_shift);
2196 gen_shifty_hi_op (ASHIFT, operands);
2201 shift_gen_fun = gen_shifty_op;
2203 /* If the topmost bit that matters is set, set the topmost bits
2204 that don't matter. This way, we might be able to get a shorter
2206 if (mask & ((HOST_WIDE_INT)1 << (31 - total_shift)))
2207 mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
2209 /* Don't expand fine-grained when combining, because that will
2210 make the pattern fail. */
2211 if (rtx_equal_function_value_matters
2212 || reload_in_progress || reload_completed)
2216 /* Cases 3 and 4 should be handled by this split
2217 only while combining */
2222 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
2225 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
2230 operands[2] = GEN_INT (total_shift);
2231 shift_gen_fun (ASHIFT, operands);
2238 if (kind != 4 && total_shift < 16)
2240 neg = -ext_shift_amounts[total_shift][1];
2242 neg -= ext_shift_amounts[total_shift][2];
2246 emit_insn (gen_and_shl_scratch (dest, source,
2249 GEN_INT (total_shift + neg),
2251 emit_insn (gen_movsi (dest, dest));
2258 /* Try to find a good way to implement the combiner pattern
2259 [(set (match_operand:SI 0 "register_operand" "=r")
2260 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2261 (match_operand:SI 2 "const_int_operand" "n")
2262 (match_operand:SI 3 "const_int_operand" "n")
2264 (clobber (reg:SI T_REG))]
2265 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
2266 return 0 for simple left / right shift combination.
2267 return 1 for left shift / 8 bit sign extend / left shift.
2268 return 2 for left shift / 16 bit sign extend / left shift.
2269 return 3 for left shift / 8 bit sign extend / shift / sign extend.
2270 return 4 for left shift / 16 bit sign extend / shift / sign extend.
2271 return 5 for left shift / 16 bit sign extend / right shift
2272 return 6 for < 8 bit sign extend / left shift.
2273 return 7 for < 8 bit sign extend / left shift / single right shift.
2274 If COSTP is nonzero, assign the calculated cost to *COSTP. */
2277 shl_sext_kind (left_rtx, size_rtx, costp)
2278 rtx left_rtx, size_rtx;
2281 int left, size, insize, ext;
2282 int cost = 0, best_cost;
2285 left = INTVAL (left_rtx);
2286 size = INTVAL (size_rtx);
2287 insize = size - left;
2290 /* Default to left / right shift. */
2292 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
2295 /* 16 bit shift / sign extend / 16 bit shift */
2296 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
2297 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
2298 below, by alternative 3 or something even better. */
2299 if (cost < best_cost)
2305 /* Try a plain sign extend between two shifts. */
2306 for (ext = 16; ext >= insize; ext -= 8)
2310 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
2311 if (cost < best_cost)
2313 kind = ext / (unsigned) 8;
2317 /* Check if we can do a sloppy shift with a final signed shift
2318 restoring the sign. */
2319 if (EXT_SHIFT_SIGNED (size - ext))
2320 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
2321 /* If not, maybe it's still cheaper to do the second shift sloppy,
2322 and do a final sign extend? */
2323 else if (size <= 16)
2324 cost = ext_shift_insns[ext - insize] + 1
2325 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
2328 if (cost < best_cost)
2330 kind = ext / (unsigned) 8 + 2;
2334 /* Check if we can sign extend in r0 */
2337 cost = 3 + shift_insns[left];
2338 if (cost < best_cost)
2343 /* Try the same with a final signed shift. */
2346 cost = 3 + ext_shift_insns[left + 1] + 1;
2347 if (cost < best_cost)
2356 /* Try to use a dynamic shift. */
2357 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
2358 if (cost < best_cost)
2369 /* Function to be used in the length attribute of the instructions
2370 implementing this pattern. */
2373 shl_sext_length (insn)
2376 rtx set_src, left_rtx, size_rtx;
2379 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2380 left_rtx = XEXP (XEXP (set_src, 0), 1);
2381 size_rtx = XEXP (set_src, 1);
2382 shl_sext_kind (left_rtx, size_rtx, &cost);
2386 /* Generate rtl for this pattern */
2389 gen_shl_sext (dest, left_rtx, size_rtx, source)
2390 rtx dest, left_rtx, size_rtx, source;
2393 int left, size, insize, cost;
2396 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
2397 left = INTVAL (left_rtx);
2398 size = INTVAL (size_rtx);
2399 insize = size - left;
2407 int ext = kind & 1 ? 8 : 16;
2408 int shift2 = size - ext;
2410 /* Don't expand fine-grained when combining, because that will
2411 make the pattern fail. */
2412 if (! rtx_equal_function_value_matters
2413 && ! reload_in_progress && ! reload_completed)
2415 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2416 emit_insn (gen_movsi (dest, source));
2420 emit_insn (gen_movsi (dest, source));
2424 operands[2] = GEN_INT (ext - insize);
2425 gen_shifty_hi_op (ASHIFT, operands);
2428 ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
2429 : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
2434 operands[2] = GEN_INT (shift2);
2435 gen_shifty_op (ASHIFT, operands);
2442 if (EXT_SHIFT_SIGNED (shift2))
2444 operands[2] = GEN_INT (shift2 + 1);
2445 gen_shifty_op (ASHIFT, operands);
2446 operands[2] = GEN_INT (1);
2447 gen_shifty_op (ASHIFTRT, operands);
2450 operands[2] = GEN_INT (shift2);
2451 gen_shifty_hi_op (ASHIFT, operands);
2455 operands[2] = GEN_INT (-shift2);
2456 gen_shifty_hi_op (LSHIFTRT, operands);
2458 emit_insn (size <= 8
2459 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
2460 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2467 if (! rtx_equal_function_value_matters
2468 && ! reload_in_progress && ! reload_completed)
2469 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2473 operands[2] = GEN_INT (16 - insize);
2474 gen_shifty_hi_op (ASHIFT, operands);
2475 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2477 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2479 gen_ashift (ASHIFTRT, 1, dest);
2484 /* Don't expand fine-grained when combining, because that will
2485 make the pattern fail. */
2486 if (! rtx_equal_function_value_matters
2487 && ! reload_in_progress && ! reload_completed)
2489 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2490 emit_insn (gen_movsi (dest, source));
2493 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
2494 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
2495 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
2497 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
2498 gen_shifty_op (ASHIFT, operands);
2500 emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
2508 /* Prefix a symbol_ref name with "datalabel". */
2511 gen_datalabel_ref (sym)
2514 if (GET_CODE (sym) == LABEL_REF)
2515 return gen_rtx_CONST (GET_MODE (sym),
2516 gen_rtx_UNSPEC (GET_MODE (sym),
2520 if (GET_CODE (sym) != SYMBOL_REF)
2527 /* The SH cannot load a large constant into a register, constants have to
2528 come from a pc relative load. The reference of a pc relative load
2529 instruction must be less than 1k infront of the instruction. This
2530 means that we often have to dump a constant inside a function, and
2531 generate code to branch around it.
2533 It is important to minimize this, since the branches will slow things
2534 down and make things bigger.
2536 Worst case code looks like:
2554 We fix this by performing a scan before scheduling, which notices which
2555 instructions need to have their operands fetched from the constant table
2556 and builds the table.
2560 scan, find an instruction which needs a pcrel move. Look forward, find the
2561 last barrier which is within MAX_COUNT bytes of the requirement.
2562 If there isn't one, make one. Process all the instructions between
2563 the find and the barrier.
2565 In the above example, we can tell that L3 is within 1k of L1, so
2566 the first move can be shrunk from the 3 insn+constant sequence into
2567 just 1 insn, and the constant moved to L3 to make:
2578 Then the second move becomes the target for the shortening process. */
2582 rtx value; /* Value in table. */
2583 rtx label; /* Label of value. */
2584 rtx wend; /* End of window. */
2585 enum machine_mode mode; /* Mode of value. */
2587 /* True if this constant is accessed as part of a post-increment
2588 sequence. Note that HImode constants are never accessed in this way. */
2589 bool part_of_sequence_p;
2592 /* The maximum number of constants that can fit into one pool, since
2593 the pc relative range is 0...1020 bytes and constants are at least 4
2596 #define MAX_POOL_SIZE (1020/4)
2597 static pool_node pool_vector[MAX_POOL_SIZE];
2598 static int pool_size;
2599 static rtx pool_window_label;
2600 static int pool_window_last;
2602 /* ??? If we need a constant in HImode which is the truncated value of a
2603 constant we need in SImode, we could combine the two entries thus saving
2604 two bytes. Is this common enough to be worth the effort of implementing
2607 /* ??? This stuff should be done at the same time that we shorten branches.
2608 As it is now, we must assume that all branches are the maximum size, and
2609 this causes us to almost always output constant pools sooner than
2612 /* Add a constant to the pool and return its label. */
2615 add_constant (x, mode, last_value)
2617 enum machine_mode mode;
2621 rtx lab, new, ref, newref;
2623 /* First see if we've already got it. */
2624 for (i = 0; i < pool_size; i++)
2626 if (x->code == pool_vector[i].value->code
2627 && mode == pool_vector[i].mode)
2629 if (x->code == CODE_LABEL)
2631 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
2634 if (rtx_equal_p (x, pool_vector[i].value))
2639 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
2641 new = gen_label_rtx ();
2642 LABEL_REFS (new) = pool_vector[i].label;
2643 pool_vector[i].label = lab = new;
2645 if (lab && pool_window_label)
2647 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2648 ref = pool_vector[pool_window_last].wend;
2649 LABEL_NEXTREF (newref) = ref;
2650 pool_vector[pool_window_last].wend = newref;
2653 pool_window_label = new;
2654 pool_window_last = i;
2660 /* Need a new one. */
2661 pool_vector[pool_size].value = x;
2662 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
2665 pool_vector[pool_size - 1].part_of_sequence_p = true;
2668 lab = gen_label_rtx ();
2669 pool_vector[pool_size].mode = mode;
2670 pool_vector[pool_size].label = lab;
2671 pool_vector[pool_size].wend = NULL_RTX;
2672 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
2673 if (lab && pool_window_label)
2675 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2676 ref = pool_vector[pool_window_last].wend;
2677 LABEL_NEXTREF (newref) = ref;
2678 pool_vector[pool_window_last].wend = newref;
2681 pool_window_label = lab;
2682 pool_window_last = pool_size;
2687 /* Output the literal table. */
2698 /* Do two passes, first time dump out the HI sized constants. */
2700 for (i = 0; i < pool_size; i++)
2702 pool_node *p = &pool_vector[i];
2704 if (p->mode == HImode)
2708 scan = emit_insn_after (gen_align_2 (), scan);
2711 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2712 scan = emit_label_after (lab, scan);
2713 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
2715 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2717 lab = XEXP (ref, 0);
2718 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2721 else if (p->mode == DFmode)
2727 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
2729 rtx align_insn = NULL_RTX;
2731 scan = emit_label_after (gen_label_rtx (), scan);
2732 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2735 for (i = 0; i < pool_size; i++)
2737 pool_node *p = &pool_vector[i];
2745 if (align_insn && !p->part_of_sequence_p)
2747 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2748 emit_label_before (lab, align_insn);
2749 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
2751 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2753 lab = XEXP (ref, 0);
2754 emit_insn_before (gen_consttable_window_end (lab),
2757 delete_insn (align_insn);
2758 align_insn = NULL_RTX;
2763 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2764 scan = emit_label_after (lab, scan);
2765 scan = emit_insn_after (gen_consttable_4 (p->value,
2767 need_align = ! need_align;
2773 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2778 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2779 scan = emit_label_after (lab, scan);
2780 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2788 if (p->mode != HImode)
2790 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2792 lab = XEXP (ref, 0);
2793 scan = emit_insn_after (gen_consttable_window_end (lab),
2802 for (i = 0; i < pool_size; i++)
2804 pool_node *p = &pool_vector[i];
2815 scan = emit_label_after (gen_label_rtx (), scan);
2816 scan = emit_insn_after (gen_align_4 (), scan);
2818 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2819 scan = emit_label_after (lab, scan);
2820 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
2828 scan = emit_label_after (gen_label_rtx (), scan);
2829 scan = emit_insn_after (gen_align_4 (), scan);
2831 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2832 scan = emit_label_after (lab, scan);
2833 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2841 if (p->mode != HImode)
2843 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2845 lab = XEXP (ref, 0);
2846 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2851 scan = emit_insn_after (gen_consttable_end (), scan);
2852 scan = emit_barrier_after (scan);
2854 pool_window_label = NULL_RTX;
2855 pool_window_last = 0;
2858 /* Return nonzero if constant would be an ok source for a
2859 mov.w instead of a mov.l. */
2865 return (GET_CODE (src) == CONST_INT
2866 && INTVAL (src) >= -32768
2867 && INTVAL (src) <= 32767);
2870 /* Nonzero if the insn is a move instruction which needs to be fixed. */
2872 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2873 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
2874 need to fix it if the input value is CONST_OK_FOR_I08. */
2880 if (GET_CODE (insn) == INSN)
2882 rtx pat = PATTERN (insn);
2883 if (GET_CODE (pat) == PARALLEL)
2884 pat = XVECEXP (pat, 0, 0);
2885 if (GET_CODE (pat) == SET
2886 /* We can load any 8 bit value if we don't care what the high
2887 order bits end up as. */
2888 && GET_MODE (SET_DEST (pat)) != QImode
2889 && (CONSTANT_P (SET_SRC (pat))
2890 /* Match mova_const. */
2891 || (GET_CODE (SET_SRC (pat)) == UNSPEC
2892 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
2893 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
2895 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
2896 && (fp_zero_operand (SET_SRC (pat))
2897 || fp_one_operand (SET_SRC (pat)))
2898 /* ??? If this is a -m4 or -m4-single compilation, in general
2899 we don't know the current setting of fpscr, so disable fldi.
2900 There is an exception if this was a register-register move
2901 before reload - and hence it was ascertained that we have
2902 single precision setting - and in a post-reload optimization
2903 we changed this to do a constant load. In that case
2904 we don't have an r0 clobber, hence we must use fldi. */
2905 && (! TARGET_SH4 || TARGET_FMOVD
2906 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
2908 && GET_CODE (SET_DEST (pat)) == REG
2909 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
2910 && (GET_CODE (SET_SRC (pat)) != CONST_INT
2911 || ! CONST_OK_FOR_I08 (INTVAL (SET_SRC (pat)))))
2922 return (GET_CODE (insn) == INSN
2923 && GET_CODE (PATTERN (insn)) == SET
2924 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
2925 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
2926 /* Don't match mova_const. */
2927 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn)), 0, 0)) == LABEL_REF);
2930 /* Find the last barrier from insn FROM which is close enough to hold the
2931 constant pool. If we can't find one, then create one near the end of
2935 find_barrier (num_mova, mova, from)
2946 int leading_mova = num_mova;
2947 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
2951 /* For HImode: range is 510, add 4 because pc counts from address of
2952 second instruction after this one, subtract 2 for the jump instruction
2953 that we may need to emit before the table, subtract 2 for the instruction
2954 that fills the jump delay slot (in very rare cases, reorg will take an
2955 instruction from after the constant pool or will leave the delay slot
2956 empty). This gives 510.
2957 For SImode: range is 1020, add 4 because pc counts from address of
2958 second instruction after this one, subtract 2 in case pc is 2 byte
2959 aligned, subtract 2 for the jump instruction that we may need to emit
2960 before the table, subtract 2 for the instruction that fills the jump
2961 delay slot. This gives 1018. */
2963 /* The branch will always be shortened now that the reference address for
2964 forward branches is the successor address, thus we need no longer make
2965 adjustments to the [sh]i_limit for -O0. */
2970 while (from && count_si < si_limit && count_hi < hi_limit)
2972 int inc = get_attr_length (from);
2975 if (GET_CODE (from) == CODE_LABEL)
2978 new_align = 1 << label_to_alignment (from);
2979 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
2980 new_align = 1 << barrier_align (from);
2986 if (GET_CODE (from) == BARRIER)
2989 found_barrier = from;
2991 /* If we are at the end of the function, or in front of an alignment
2992 instruction, we need not insert an extra alignment. We prefer
2993 this kind of barrier. */
2994 if (barrier_align (from) > 2)
2995 good_barrier = from;
2998 if (broken_move (from))
3001 enum machine_mode mode;
3003 pat = PATTERN (from);
3004 if (GET_CODE (pat) == PARALLEL)
3005 pat = XVECEXP (pat, 0, 0);
3006 src = SET_SRC (pat);
3007 dst = SET_DEST (pat);
3008 mode = GET_MODE (dst);
3010 /* We must explicitly check the mode, because sometimes the
3011 front end will generate code to load unsigned constants into
3012 HImode targets without properly sign extending them. */
3014 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
3017 /* We put the short constants before the long constants, so
3018 we must count the length of short constants in the range
3019 for the long constants. */
3020 /* ??? This isn't optimal, but is easy to do. */
3025 /* We dump DF/DI constants before SF/SI ones, because
3026 the limit is the same, but the alignment requirements
3027 are higher. We may waste up to 4 additional bytes
3028 for alignment, and the DF/DI constant may have
3029 another SF/SI constant placed before it. */
3030 if (TARGET_SHCOMPACT
3032 && (mode == DFmode || mode == DImode))
3037 while (si_align > 2 && found_si + si_align - 2 > count_si)
3039 if (found_si > count_si)
3040 count_si = found_si;
3041 found_si += GET_MODE_SIZE (mode);
3043 si_limit -= GET_MODE_SIZE (mode);
3046 /* See the code in machine_dependent_reorg, which has a similar if
3047 statement that generates a new mova insn in many cases. */
3048 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
3058 barrier_before_mova = good_barrier ? good_barrier : found_barrier;
3060 if (found_si > count_si)
3061 count_si = found_si;
3063 else if (GET_CODE (from) == JUMP_INSN
3064 && (GET_CODE (PATTERN (from)) == ADDR_VEC
3065 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
3069 if (barrier_align (next_real_insn (from)) == align_jumps_log)
3071 /* We have just passed the barrier in front of the
3072 ADDR_DIFF_VEC, which is stored in found_barrier. Since
3073 the ADDR_DIFF_VEC is accessed as data, just like our pool
3074 constants, this is a good opportunity to accommodate what
3075 we have gathered so far.
3076 If we waited any longer, we could end up at a barrier in
3077 front of code, which gives worse cache usage for separated
3078 instruction / data caches. */
3079 good_barrier = found_barrier;
3084 rtx body = PATTERN (from);
3085 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
3088 /* For the SH1, we generate alignments even after jumps-around-jumps. */
3089 else if (GET_CODE (from) == JUMP_INSN
3091 && ! TARGET_SMALLCODE)
3097 if (new_align > si_align)
3099 si_limit -= (count_si - 1) & (new_align - si_align);
3100 si_align = new_align;
3102 count_si = (count_si + new_align - 1) & -new_align;
3107 if (new_align > hi_align)
3109 hi_limit -= (count_hi - 1) & (new_align - hi_align);
3110 hi_align = new_align;
3112 count_hi = (count_hi + new_align - 1) & -new_align;
3114 from = NEXT_INSN (from);
3121 /* Try as we might, the leading mova is out of range. Change
3122 it into a load (which will become a pcload) and retry. */
3123 SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3124 INSN_CODE (mova) = -1;
3125 return find_barrier (0, 0, mova);
3129 /* Insert the constant pool table before the mova instruction,
3130 to prevent the mova label reference from going out of range. */
3132 good_barrier = found_barrier = barrier_before_mova;
3138 if (good_barrier && next_real_insn (found_barrier))
3139 found_barrier = good_barrier;
3143 /* We didn't find a barrier in time to dump our stuff,
3144 so we'll make one. */
3145 rtx label = gen_label_rtx ();
3147 /* If we exceeded the range, then we must back up over the last
3148 instruction we looked at. Otherwise, we just need to undo the
3149 NEXT_INSN at the end of the loop. */
3150 if (count_hi > hi_limit || count_si > si_limit)
3151 from = PREV_INSN (PREV_INSN (from));
3153 from = PREV_INSN (from);
3155 /* Walk back to be just before any jump or label.
3156 Putting it before a label reduces the number of times the branch
3157 around the constant pool table will be hit. Putting it before
3158 a jump makes it more likely that the bra delay slot will be
3160 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
3161 || GET_CODE (from) == CODE_LABEL)
3162 from = PREV_INSN (from);
3164 from = emit_jump_insn_after (gen_jump (label), from);
3165 JUMP_LABEL (from) = label;
3166 LABEL_NUSES (label) = 1;
3167 found_barrier = emit_barrier_after (from);
3168 emit_label_after (label, found_barrier);
3171 return found_barrier;
3174 /* If the instruction INSN is implemented by a special function, and we can
3175 positively find the register that is used to call the sfunc, and this
3176 register is not used anywhere else in this instruction - except as the
3177 destination of a set, return this register; else, return 0. */
3179 sfunc_uses_reg (insn)
3183 rtx pattern, part, reg_part, reg;
3185 if (GET_CODE (insn) != INSN)
3187 pattern = PATTERN (insn);
3188 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
3191 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3193 part = XVECEXP (pattern, 0, i);
3194 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
3199 reg = XEXP (reg_part, 0);
3200 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
3202 part = XVECEXP (pattern, 0, i);
3203 if (part == reg_part || GET_CODE (part) == CLOBBER)
3205 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
3206 && GET_CODE (SET_DEST (part)) == REG)
3207 ? SET_SRC (part) : part)))
3213 /* See if the only way in which INSN uses REG is by calling it, or by
3214 setting it while calling it. Set *SET to a SET rtx if the register
3218 noncall_uses_reg (reg, insn, set)
3227 reg2 = sfunc_uses_reg (insn);
3228 if (reg2 && REGNO (reg2) == REGNO (reg))
3230 pattern = single_set (insn);
3232 && GET_CODE (SET_DEST (pattern)) == REG
3233 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3237 if (GET_CODE (insn) != CALL_INSN)
3239 /* We don't use rtx_equal_p because we don't care if the mode is
3241 pattern = single_set (insn);
3243 && GET_CODE (SET_DEST (pattern)) == REG
3244 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3250 par = PATTERN (insn);
3251 if (GET_CODE (par) == PARALLEL)
3252 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
3254 part = XVECEXP (par, 0, i);
3255 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
3258 return reg_mentioned_p (reg, SET_SRC (pattern));
3264 pattern = PATTERN (insn);
3266 if (GET_CODE (pattern) == PARALLEL)
3270 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3271 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
3273 pattern = XVECEXP (pattern, 0, 0);
3276 if (GET_CODE (pattern) == SET)
3278 if (reg_mentioned_p (reg, SET_DEST (pattern)))
3280 /* We don't use rtx_equal_p, because we don't care if the
3281 mode is different. */
3282 if (GET_CODE (SET_DEST (pattern)) != REG
3283 || REGNO (reg) != REGNO (SET_DEST (pattern)))
3289 pattern = SET_SRC (pattern);
3292 if (GET_CODE (pattern) != CALL
3293 || GET_CODE (XEXP (pattern, 0)) != MEM
3294 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
3300 /* Given a X, a pattern of an insn or a part of it, return a mask of used
3301 general registers. Bits 0..15 mean that the respective registers
3302 are used as inputs in the instruction. Bits 16..31 mean that the
3303 registers 0..15, respectively, are used as outputs, or are clobbered.
3304 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
3306 regs_used (x, is_dest)
3315 code = GET_CODE (x);
3320 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3321 << (REGNO (x) + is_dest));
3325 rtx y = SUBREG_REG (x);
3327 if (GET_CODE (y) != REG)
3330 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3332 subreg_regno_offset (REGNO (y),
3335 GET_MODE (x)) + is_dest));
3339 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
3341 /* If there was a return value, it must have been indicated with USE. */
3356 fmt = GET_RTX_FORMAT (code);
3358 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3363 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3364 used |= regs_used (XVECEXP (x, i, j), is_dest);
3366 else if (fmt[i] == 'e')
3367 used |= regs_used (XEXP (x, i), is_dest);
3372 /* Create an instruction that prevents redirection of a conditional branch
3373 to the destination of the JUMP with address ADDR.
3374 If the branch needs to be implemented as an indirect jump, try to find
3375 a scratch register for it.
3376 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3377 If any preceding insn that doesn't fit into a delay slot is good enough,
3378 pass 1. Pass 2 if a definite blocking insn is needed.
3379 -1 is used internally to avoid deep recursion.
3380 If a blocking instruction is made or recognized, return it. */
3383 gen_block_redirect (jump, addr, need_block)
3385 int addr, need_block;
3388 rtx prev = prev_nonnote_insn (jump);
3391 /* First, check if we already have an instruction that satisfies our need. */
3392 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
3394 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
3396 if (GET_CODE (PATTERN (prev)) == USE
3397 || GET_CODE (PATTERN (prev)) == CLOBBER
3398 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3400 else if ((need_block &= ~1) < 0)
3402 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
3405 /* We can't use JUMP_LABEL here because it might be undefined
3406 when not optimizing. */
3407 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
3408 /* If the branch is out of range, try to find a scratch register for it. */
3410 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3414 /* Don't look for the stack pointer as a scratch register,
3415 it would cause trouble if an interrupt occurred. */
3416 unsigned try = 0x7fff, used;
3417 int jump_left = flag_expensive_optimizations + 1;
3419 /* It is likely that the most recent eligible instruction is wanted for
3420 the delay slot. Therefore, find out which registers it uses, and
3421 try to avoid using them. */
3423 for (scan = jump; (scan = PREV_INSN (scan)); )
3427 if (INSN_DELETED_P (scan))
3429 code = GET_CODE (scan);
3430 if (code == CODE_LABEL || code == JUMP_INSN)
3433 && GET_CODE (PATTERN (scan)) != USE
3434 && GET_CODE (PATTERN (scan)) != CLOBBER
3435 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
3437 try &= ~regs_used (PATTERN (scan), 0);
3441 for (used = dead = 0, scan = JUMP_LABEL (jump);
3442 (scan = NEXT_INSN (scan)); )
3446 if (INSN_DELETED_P (scan))
3448 code = GET_CODE (scan);
3449 if (GET_RTX_CLASS (code) == 'i')
3451 used |= regs_used (PATTERN (scan), 0);
3452 if (code == CALL_INSN)
3453 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
3454 dead |= (used >> 16) & ~used;
3460 if (code == JUMP_INSN)
3462 if (jump_left-- && simplejump_p (scan))
3463 scan = JUMP_LABEL (scan);
3469 /* Mask out the stack pointer again, in case it was
3470 the only 'free' register we have found. */
3473 /* If the immediate destination is still in range, check for possible
3474 threading with a jump beyond the delay slot insn.
3475 Don't check if we are called recursively; the jump has been or will be
3476 checked in a different invocation then. */
3478 else if (optimize && need_block >= 0)
3480 rtx next = next_active_insn (next_active_insn (dest));
3481 if (next && GET_CODE (next) == JUMP_INSN
3482 && GET_CODE (PATTERN (next)) == SET
3483 && recog_memoized (next) == CODE_FOR_jump_compact)
3485 dest = JUMP_LABEL (next);
3487 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3489 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
3495 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
3497 /* It would be nice if we could convert the jump into an indirect
3498 jump / far branch right now, and thus exposing all constituent
3499 instructions to further optimization. However, reorg uses
3500 simplejump_p to determine if there is an unconditional jump where
3501 it should try to schedule instructions from the target of the
3502 branch; simplejump_p fails for indirect jumps even if they have
3504 rtx insn = emit_insn_before (gen_indirect_jump_scratch
3505 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
3507 /* ??? We would like this to have the scope of the jump, but that
3508 scope will change when a delay slot insn of an inner scope is added.
3509 Hence, after delay slot scheduling, we'll have to expect
3510 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
3513 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
3514 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
3517 else if (need_block)
3518 /* We can't use JUMP_LABEL here because it might be undefined
3519 when not optimizing. */
3520 return emit_insn_before (gen_block_branch_redirect
3521 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
3526 #define CONDJUMP_MIN -252
3527 #define CONDJUMP_MAX 262
3530 /* A label (to be placed) in front of the jump
3531 that jumps to our ultimate destination. */
3533 /* Where we are going to insert it if we cannot move the jump any farther,
3534 or the jump itself if we have picked up an existing jump. */
3536 /* The ultimate destination. */
3538 struct far_branch *prev;
3539 /* If the branch has already been created, its address;
3540 else the address of its first prospective user. */
3544 static void gen_far_branch PARAMS ((struct far_branch *));
3545 enum mdep_reorg_phase_e mdep_reorg_phase;
3548 struct far_branch *bp;
3550 rtx insn = bp->insert_place;
3552 rtx label = gen_label_rtx ();
3554 emit_label_after (label, insn);
3557 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
3558 LABEL_NUSES (bp->far_label)++;
3561 jump = emit_jump_insn_after (gen_return (), insn);
3562 /* Emit a barrier so that reorg knows that any following instructions
3563 are not reachable via a fall-through path.
3564 But don't do this when not optimizing, since we wouldn't suppress the
3565 alignment for the barrier then, and could end up with out-of-range
3566 pc-relative loads. */
3568 emit_barrier_after (jump);
3569 emit_label_after (bp->near_label, insn);
3570 JUMP_LABEL (jump) = bp->far_label;
3571 if (! invert_jump (insn, label, 1))
3574 (gen_stuff_delay_slot
3575 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
3576 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
3578 /* Prevent reorg from undoing our splits. */
3579 gen_block_redirect (jump, bp->address += 2, 2);
3582 /* Fix up ADDR_DIFF_VECs. */
3584 fixup_addr_diff_vecs (first)
3589 for (insn = first; insn; insn = NEXT_INSN (insn))
3591 rtx vec_lab, pat, prev, prevpat, x, braf_label;
3593 if (GET_CODE (insn) != JUMP_INSN
3594 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
3596 pat = PATTERN (insn);
3597 vec_lab = XEXP (XEXP (pat, 0), 0);
3599 /* Search the matching casesi_jump_2. */
3600 for (prev = vec_lab; ; prev = PREV_INSN (prev))
3602 if (GET_CODE (prev) != JUMP_INSN)
3604 prevpat = PATTERN (prev);
3605 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
3607 x = XVECEXP (prevpat, 0, 1);
3608 if (GET_CODE (x) != USE)
3611 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
3615 /* Emit the reference label of the braf where it belongs, right after
3616 the casesi_jump_2 (i.e. braf). */
3617 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
3618 emit_label_after (braf_label, prev);
3620 /* Fix up the ADDR_DIF_VEC to be relative
3621 to the reference address of the braf. */
3622 XEXP (XEXP (pat, 0), 0) = braf_label;
3626 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3627 a barrier. Return the base 2 logarithm of the desired alignment. */
3629 barrier_align (barrier_or_label)
3630 rtx barrier_or_label;
3632 rtx next = next_real_insn (barrier_or_label), pat, prev;
3633 int slot, credit, jump_to_next = 0;
3638 pat = PATTERN (next);
3640 if (GET_CODE (pat) == ADDR_DIFF_VEC)
3643 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
3644 /* This is a barrier in front of a constant table. */
3647 prev = prev_real_insn (barrier_or_label);
3648 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
3650 pat = PATTERN (prev);
3651 /* If this is a very small table, we want to keep the alignment after
3652 the table to the minimum for proper code alignment. */
3653 return ((TARGET_SMALLCODE
3654 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
3655 <= (unsigned)1 << (CACHE_LOG - 2)))
3656 ? 1 << TARGET_SHMEDIA : align_jumps_log);
3659 if (TARGET_SMALLCODE)
3662 if (! TARGET_SH2 || ! optimize)
3663 return align_jumps_log;
3665 /* When fixing up pcloads, a constant table might be inserted just before
3666 the basic block that ends with the barrier. Thus, we can't trust the
3667 instruction lengths before that. */
3668 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
3670 /* Check if there is an immediately preceding branch to the insn beyond
3671 the barrier. We must weight the cost of discarding useful information
3672 from the current cache line when executing this branch and there is
3673 an alignment, against that of fetching unneeded insn in front of the
3674 branch target when there is no alignment. */
3676 /* There are two delay_slot cases to consider. One is the simple case
3677 where the preceding branch is to the insn beyond the barrier (simple
3678 delay slot filling), and the other is where the preceding branch has
3679 a delay slot that is a duplicate of the insn after the barrier
3680 (fill_eager_delay_slots) and the branch is to the insn after the insn
3681 after the barrier. */
3683 /* PREV is presumed to be the JUMP_INSN for the barrier under
3684 investigation. Skip to the insn before it. */
3685 prev = prev_real_insn (prev);
3687 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
3688 credit >= 0 && prev && GET_CODE (prev) == INSN;
3689 prev = prev_real_insn (prev))
3692 if (GET_CODE (PATTERN (prev)) == USE
3693 || GET_CODE (PATTERN (prev)) == CLOBBER)
3695 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
3697 prev = XVECEXP (PATTERN (prev), 0, 1);
3698 if (INSN_UID (prev) == INSN_UID (next))
3700 /* Delay slot was filled with insn at jump target. */
3707 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3709 credit -= get_attr_length (prev);
3712 && GET_CODE (prev) == JUMP_INSN
3713 && JUMP_LABEL (prev))
3717 || next_real_insn (JUMP_LABEL (prev)) == next
3718 /* If relax_delay_slots() decides NEXT was redundant
3719 with some previous instruction, it will have
3720 redirected PREV's jump to the following insn. */
3721 || JUMP_LABEL (prev) == next_nonnote_insn (next)
3722 /* There is no upper bound on redundant instructions
3723 that might have been skipped, but we must not put an
3724 alignment where none had been before. */
3725 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
3727 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
3728 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
3729 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
3731 rtx pat = PATTERN (prev);
3732 if (GET_CODE (pat) == PARALLEL)
3733 pat = XVECEXP (pat, 0, 0);
3734 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
3740 return align_jumps_log;
3743 /* If we are inside a phony loop, almost any kind of label can turn up as the
3744 first one in the loop. Aligning a braf label causes incorrect switch
3745 destination addresses; we can detect braf labels because they are
3746 followed by a BARRIER.
3747 Applying loop alignment to small constant or switch tables is a waste
3748 of space, so we suppress this too. */
3750 sh_loop_align (label)
3756 next = next_nonnote_insn (next);
3757 while (next && GET_CODE (next) == CODE_LABEL);
3761 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
3762 || recog_memoized (next) == CODE_FOR_consttable_2)
3765 return align_loops_log;
3768 /* Do a final pass over the function, just before delayed branch
3774 rtx first, insn, mova = NULL_RTX;
3776 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
3777 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
3779 first = get_insns ();
3781 /* We must split call insns before introducing `mova's. If we're
3782 optimizing, they'll have already been split. Otherwise, make
3783 sure we don't split them too late. */
3785 split_all_insns_noflow ();
3790 /* If relaxing, generate pseudo-ops to associate function calls with
3791 the symbols they call. It does no harm to not generate these
3792 pseudo-ops. However, when we can generate them, it enables to
3793 linker to potentially relax the jsr to a bsr, and eliminate the
3794 register load and, possibly, the constant pool entry. */
3796 mdep_reorg_phase = SH_INSERT_USES_LABELS;
3799 /* Remove all REG_LABEL notes. We want to use them for our own
3800 purposes. This works because none of the remaining passes
3801 need to look at them.
3803 ??? But it may break in the future. We should use a machine
3804 dependent REG_NOTE, or some other approach entirely. */
3805 for (insn = first; insn; insn = NEXT_INSN (insn))
3811 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
3812 remove_note (insn, note);
3816 for (insn = first; insn; insn = NEXT_INSN (insn))
3818 rtx pattern, reg, link, set, scan, dies, label;
3819 int rescan = 0, foundinsn = 0;
3821 if (GET_CODE (insn) == CALL_INSN)
3823 pattern = PATTERN (insn);
3825 if (GET_CODE (pattern) == PARALLEL)
3826 pattern = XVECEXP (pattern, 0, 0);
3827 if (GET_CODE (pattern) == SET)
3828 pattern = SET_SRC (pattern);
3830 if (GET_CODE (pattern) != CALL
3831 || GET_CODE (XEXP (pattern, 0)) != MEM)
3834 reg = XEXP (XEXP (pattern, 0), 0);
3838 reg = sfunc_uses_reg (insn);
3843 if (GET_CODE (reg) != REG)
3846 /* This is a function call via REG. If the only uses of REG
3847 between the time that it is set and the time that it dies
3848 are in function calls, then we can associate all the
3849 function calls with the setting of REG. */
3851 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
3853 if (REG_NOTE_KIND (link) != 0)
3855 set = single_set (XEXP (link, 0));
3856 if (set && rtx_equal_p (reg, SET_DEST (set)))
3858 link = XEXP (link, 0);
3865 /* ??? Sometimes global register allocation will have
3866 deleted the insn pointed to by LOG_LINKS. Try
3867 scanning backward to find where the register is set. */
3868 for (scan = PREV_INSN (insn);
3869 scan && GET_CODE (scan) != CODE_LABEL;
3870 scan = PREV_INSN (scan))
3872 if (! INSN_P (scan))
3875 if (! reg_mentioned_p (reg, scan))
3878 if (noncall_uses_reg (reg, scan, &set))
3892 /* The register is set at LINK. */
3894 /* We can only optimize the function call if the register is
3895 being set to a symbol. In theory, we could sometimes
3896 optimize calls to a constant location, but the assembler
3897 and linker do not support that at present. */
3898 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
3899 && GET_CODE (SET_SRC (set)) != LABEL_REF)
3902 /* Scan forward from LINK to the place where REG dies, and
3903 make sure that the only insns which use REG are
3904 themselves function calls. */
3906 /* ??? This doesn't work for call targets that were allocated
3907 by reload, since there may not be a REG_DEAD note for the
3911 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
3915 /* Don't try to trace forward past a CODE_LABEL if we haven't
3916 seen INSN yet. Ordinarily, we will only find the setting insn
3917 in LOG_LINKS if it is in the same basic block. However,
3918 cross-jumping can insert code labels in between the load and
3919 the call, and can result in situations where a single call
3920 insn may have two targets depending on where we came from. */
3922 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
3925 if (! INSN_P (scan))
3928 /* Don't try to trace forward past a JUMP. To optimize
3929 safely, we would have to check that all the
3930 instructions at the jump destination did not use REG. */
3932 if (GET_CODE (scan) == JUMP_INSN)
3935 if (! reg_mentioned_p (reg, scan))
3938 if (noncall_uses_reg (reg, scan, &scanset))
3945 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
3947 /* There is a function call to this register other
3948 than the one we are checking. If we optimize
3949 this call, we need to rescan again below. */
3953 /* ??? We shouldn't have to worry about SCANSET here.
3954 We should just be able to check for a REG_DEAD note
3955 on a function call. However, the REG_DEAD notes are
3956 apparently not dependable around libcalls; c-torture
3957 execute/920501-2 is a test case. If SCANSET is set,
3958 then this insn sets the register, so it must have
3959 died earlier. Unfortunately, this will only handle
3960 the cases in which the register is, in fact, set in a
3963 /* ??? We shouldn't have to use FOUNDINSN here.
3964 However, the LOG_LINKS fields are apparently not
3965 entirely reliable around libcalls;
3966 newlib/libm/math/e_pow.c is a test case. Sometimes
3967 an insn will appear in LOG_LINKS even though it is
3968 not the most recent insn which sets the register. */
3972 || find_reg_note (scan, REG_DEAD, reg)))
3981 /* Either there was a branch, or some insn used REG
3982 other than as a function call address. */
3986 /* Create a code label, and put it in a REG_LABEL note on
3987 the insn which sets the register, and on each call insn
3988 which uses the register. In final_prescan_insn we look
3989 for the REG_LABEL notes, and output the appropriate label
3992 label = gen_label_rtx ();
3993 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL, label,
3995 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, label,
4004 scan = NEXT_INSN (scan);
4006 && ((GET_CODE (scan) == CALL_INSN
4007 && reg_mentioned_p (reg, scan))
4008 || ((reg2 = sfunc_uses_reg (scan))
4009 && REGNO (reg2) == REGNO (reg))))
4011 = gen_rtx_INSN_LIST (REG_LABEL, label, REG_NOTES (scan));
4013 while (scan != dies);
4019 fixup_addr_diff_vecs (first);
4023 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
4024 shorten_branches (first);
4026 /* Scan the function looking for move instructions which have to be
4027 changed to pc-relative loads and insert the literal tables. */
4029 mdep_reorg_phase = SH_FIXUP_PCLOAD;
4030 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
4037 else if (GET_CODE (insn) == JUMP_INSN
4038 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
4046 /* Some code might have been inserted between the mova and
4047 its ADDR_DIFF_VEC. Check if the mova is still in range. */
4048 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
4049 total += get_attr_length (scan);
4051 /* range of mova is 1020, add 4 because pc counts from address of
4052 second instruction after this one, subtract 2 in case pc is 2
4053 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
4054 cancels out with alignment effects of the mova itself. */
4057 /* Change the mova into a load, and restart scanning
4058 there. broken_move will then return true for mova. */
4059 SET_SRC (PATTERN (mova))
4060 = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4061 INSN_CODE (mova) = -1;
4065 if (broken_move (insn))
4068 /* Scan ahead looking for a barrier to stick the constant table
4070 rtx barrier = find_barrier (num_mova, mova, insn);
4071 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
4073 if (num_mova && ! mova_p (mova))
4075 /* find_barrier had to change the first mova into a
4076 pcload; thus, we have to start with this new pcload. */
4080 /* Now find all the moves between the points and modify them. */
4081 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
4083 if (GET_CODE (scan) == CODE_LABEL)
4085 if (broken_move (scan))
4087 rtx *patp = &PATTERN (scan), pat = *patp;
4091 enum machine_mode mode;
4093 if (GET_CODE (pat) == PARALLEL)
4094 patp = &XVECEXP (pat, 0, 0), pat = *patp;
4095 src = SET_SRC (pat);
4096 dst = SET_DEST (pat);
4097 mode = GET_MODE (dst);
4099 if (mode == SImode && hi_const (src)
4100 && REGNO (dst) != FPUL_REG)
4105 while (GET_CODE (dst) == SUBREG)
4107 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
4108 GET_MODE (SUBREG_REG (dst)),
4111 dst = SUBREG_REG (dst);
4113 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
4116 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
4118 /* This must be an insn that clobbers r0. */
4119 rtx clobber = XVECEXP (PATTERN (scan), 0,
4120 XVECLEN (PATTERN (scan), 0) - 1);
4122 if (GET_CODE (clobber) != CLOBBER
4123 || ! rtx_equal_p (XEXP (clobber, 0), r0_rtx))
4127 && reg_set_between_p (r0_rtx, last_float_move, scan))
4131 && GET_MODE_SIZE (mode) != 4
4132 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
4134 lab = add_constant (src, mode, last_float);
4136 emit_insn_before (gen_mova (lab), scan);
4139 /* There will be a REG_UNUSED note for r0 on
4140 LAST_FLOAT_MOVE; we have to change it to REG_INC,
4141 lest reorg:mark_target_live_regs will not
4142 consider r0 to be used, and we end up with delay
4143 slot insn in front of SCAN that clobbers r0. */
4145 = find_regno_note (last_float_move, REG_UNUSED, 0);
4147 /* If we are not optimizing, then there may not be
4150 PUT_MODE (note, REG_INC);
4152 *last_float_addr = r0_inc_rtx;
4154 last_float_move = scan;
4156 newsrc = gen_rtx (MEM, mode,
4157 (((TARGET_SH4 && ! TARGET_FMOVD)
4158 || REGNO (dst) == FPUL_REG)
4161 last_float_addr = &XEXP (newsrc, 0);
4163 /* Remove the clobber of r0. */
4164 XEXP (clobber, 0) = gen_rtx_SCRATCH (Pmode);
4165 RTX_UNCHANGING_P (newsrc) = 1;
4167 /* This is a mova needing a label. Create it. */
4168 else if (GET_CODE (src) == UNSPEC
4169 && XINT (src, 1) == UNSPEC_MOVA
4170 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
4172 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
4173 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
4174 newsrc = gen_rtx_UNSPEC (SImode,
4175 gen_rtvec (1, newsrc),
4180 lab = add_constant (src, mode, 0);
4181 newsrc = gen_rtx_MEM (mode,
4182 gen_rtx_LABEL_REF (VOIDmode, lab));
4183 RTX_UNCHANGING_P (newsrc) = 1;
4185 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
4186 INSN_CODE (scan) = -1;
4189 dump_table (barrier);
4194 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
4195 INSN_ADDRESSES_FREE ();
4196 split_branches (first);
4198 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
4199 also has an effect on the register that holds the address of the sfunc.
4200 Insert an extra dummy insn in front of each sfunc that pretends to
4201 use this register. */
4202 if (flag_delayed_branch)
4204 for (insn = first; insn; insn = NEXT_INSN (insn))
4206 rtx reg = sfunc_uses_reg (insn);
4210 emit_insn_before (gen_use_sfunc_addr (reg), insn);
4214 /* fpscr is not actually a user variable, but we pretend it is for the
4215 sake of the previous optimization passes, since we want it handled like
4216 one. However, we don't have any debugging information for it, so turn
4217 it into a non-user variable now. */
4219 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
4221 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
4225 get_dest_uid (label, max_uid)
4229 rtx dest = next_real_insn (label);
4232 /* This can happen for an undefined label. */
4234 dest_uid = INSN_UID (dest);
4235 /* If this is a newly created branch redirection blocking instruction,
4236 we cannot index the branch_uid or insn_addresses arrays with its
4237 uid. But then, we won't need to, because the actual destination is
4238 the following branch. */
4239 while (dest_uid >= max_uid)
4241 dest = NEXT_INSN (dest);
4242 dest_uid = INSN_UID (dest);
4244 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
4249 /* Split condbranches that are out of range. Also add clobbers for
4250 scratch registers that are needed in far jumps.
4251 We do this before delay slot scheduling, so that it can take our
4252 newly created instructions into account. It also allows us to
4253 find branches with common targets more easily. */
4256 split_branches (first)
4260 struct far_branch **uid_branch, *far_branch_list = 0;
4261 int max_uid = get_max_uid ();
4263 /* Find out which branches are out of range. */
4264 shorten_branches (first);
4266 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
4267 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
4269 for (insn = first; insn; insn = NEXT_INSN (insn))
4270 if (! INSN_P (insn))
4272 else if (INSN_DELETED_P (insn))
4274 /* Shorten_branches would split this instruction again,
4275 so transform it into a note. */
4276 PUT_CODE (insn, NOTE);
4277 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4278 NOTE_SOURCE_FILE (insn) = 0;
4280 else if (GET_CODE (insn) == JUMP_INSN
4281 /* Don't mess with ADDR_DIFF_VEC */
4282 && (GET_CODE (PATTERN (insn)) == SET
4283 || GET_CODE (PATTERN (insn)) == RETURN))
4285 enum attr_type type = get_attr_type (insn);
4286 if (type == TYPE_CBRANCH)
4290 if (get_attr_length (insn) > 4)
4292 rtx src = SET_SRC (PATTERN (insn));
4293 rtx olabel = XEXP (XEXP (src, 1), 0);
4294 int addr = INSN_ADDRESSES (INSN_UID (insn));
4296 int dest_uid = get_dest_uid (olabel, max_uid);
4297 struct far_branch *bp = uid_branch[dest_uid];
4299 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
4300 the label if the LABEL_NUSES count drops to zero. There is
4301 always a jump_optimize pass that sets these values, but it
4302 proceeds to delete unreferenced code, and then if not
4303 optimizing, to un-delete the deleted instructions, thus
4304 leaving labels with too low uses counts. */
4307 JUMP_LABEL (insn) = olabel;
4308 LABEL_NUSES (olabel)++;
4312 bp = (struct far_branch *) alloca (sizeof *bp);
4313 uid_branch[dest_uid] = bp;
4314 bp->prev = far_branch_list;
4315 far_branch_list = bp;
4317 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
4318 LABEL_NUSES (bp->far_label)++;
4322 label = bp->near_label;
4323 if (! label && bp->address - addr >= CONDJUMP_MIN)
4325 rtx block = bp->insert_place;
4327 if (GET_CODE (PATTERN (block)) == RETURN)
4328 block = PREV_INSN (block);
4330 block = gen_block_redirect (block,
4332 label = emit_label_after (gen_label_rtx (),
4334 bp->near_label = label;
4336 else if (label && ! NEXT_INSN (label))
4338 if (addr + 2 - bp->address <= CONDJUMP_MAX)
4339 bp->insert_place = insn;
4341 gen_far_branch (bp);
4345 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
4347 bp->near_label = label = gen_label_rtx ();
4348 bp->insert_place = insn;
4351 if (! redirect_jump (insn, label, 1))
4356 /* get_attr_length (insn) == 2 */
4357 /* Check if we have a pattern where reorg wants to redirect
4358 the branch to a label from an unconditional branch that
4360 /* We can't use JUMP_LABEL here because it might be undefined
4361 when not optimizing. */
4362 /* A syntax error might cause beyond to be NULL_RTX. */
4364 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
4368 && (GET_CODE (beyond) == JUMP_INSN
4369 || ((beyond = next_active_insn (beyond))
4370 && GET_CODE (beyond) == JUMP_INSN))
4371 && GET_CODE (PATTERN (beyond)) == SET
4372 && recog_memoized (beyond) == CODE_FOR_jump_compact
4374 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
4375 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4377 gen_block_redirect (beyond,
4378 INSN_ADDRESSES (INSN_UID (beyond)), 1);
4381 next = next_active_insn (insn);
4383 if ((GET_CODE (next) == JUMP_INSN
4384 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
4385 && GET_CODE (PATTERN (next)) == SET
4386 && recog_memoized (next) == CODE_FOR_jump_compact
4388 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
4389 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4391 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
4393 else if (type == TYPE_JUMP || type == TYPE_RETURN)
4395 int addr = INSN_ADDRESSES (INSN_UID (insn));
4398 struct far_branch *bp;
4400 if (type == TYPE_JUMP)
4402 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
4403 dest_uid = get_dest_uid (far_label, max_uid);
4406 /* Parse errors can lead to labels outside
4408 if (! NEXT_INSN (far_label))
4413 JUMP_LABEL (insn) = far_label;
4414 LABEL_NUSES (far_label)++;
4416 redirect_jump (insn, NULL_RTX, 1);
4420 bp = uid_branch[dest_uid];
4423 bp = (struct far_branch *) alloca (sizeof *bp);
4424 uid_branch[dest_uid] = bp;
4425 bp->prev = far_branch_list;
4426 far_branch_list = bp;
4428 bp->far_label = far_label;
4430 LABEL_NUSES (far_label)++;
4432 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
4433 if (addr - bp->address <= CONDJUMP_MAX)
4434 emit_label_after (bp->near_label, PREV_INSN (insn));
4437 gen_far_branch (bp);
4443 bp->insert_place = insn;
4445 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
4447 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
4450 /* Generate all pending far branches,
4451 and free our references to the far labels. */
4452 while (far_branch_list)
4454 if (far_branch_list->near_label
4455 && ! NEXT_INSN (far_branch_list->near_label))
4456 gen_far_branch (far_branch_list);
4458 && far_branch_list->far_label
4459 && ! --LABEL_NUSES (far_branch_list->far_label))
4460 delete_insn (far_branch_list->far_label);
4461 far_branch_list = far_branch_list->prev;
4464 /* Instruction length information is no longer valid due to the new
4465 instructions that have been generated. */
4466 init_insn_lengths ();
4469 /* Dump out instruction addresses, which is useful for debugging the
4470 constant pool table stuff.
4472 If relaxing, output the label and pseudo-ops used to link together
4473 calls and the instruction which set the registers. */
4475 /* ??? The addresses printed by this routine for insns are nonsense for
4476 insns which are inside of a sequence where none of the inner insns have
4477 variable length. This is because the second pass of shorten_branches
4478 does not bother to update them. */
4481 final_prescan_insn (insn, opvec, noperands)
4483 rtx *opvec ATTRIBUTE_UNUSED;
4484 int noperands ATTRIBUTE_UNUSED;
4486 if (TARGET_DUMPISIZE)
4487 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
4493 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
4498 pattern = PATTERN (insn);
4499 if (GET_CODE (pattern) == PARALLEL)
4500 pattern = XVECEXP (pattern, 0, 0);
4501 if (GET_CODE (pattern) == CALL
4502 || (GET_CODE (pattern) == SET
4503 && (GET_CODE (SET_SRC (pattern)) == CALL
4504 || get_attr_type (insn) == TYPE_SFUNC)))
4505 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
4506 CODE_LABEL_NUMBER (XEXP (note, 0)));
4507 else if (GET_CODE (pattern) == SET)
4508 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4509 CODE_LABEL_NUMBER (XEXP (note, 0)));
4516 /* Dump out any constants accumulated in the final pass. These will
4520 output_jump_label_table ()
4526 fprintf (asm_out_file, "\t.align 2\n");
4527 for (i = 0; i < pool_size; i++)
4529 pool_node *p = &pool_vector[i];
4531 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4532 CODE_LABEL_NUMBER (p->label));
4533 output_asm_insn (".long %O0", &p->value);
4541 /* A full frame looks like:
4545 [ if current_function_anonymous_args
4558 local-0 <- fp points here. */
4560 /* Number of bytes pushed for anonymous args, used to pass information
4561 between expand_prologue and expand_epilogue. */
4563 static int extra_push;
4565 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
4566 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
4567 for an epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET
4568 of all the registers that are about to be restored, and hence dead. */
4571 output_stack_adjust (int size, rtx reg, int epilogue_p,
4572 HARD_REG_SET *live_regs_mask)
4574 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
4577 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4582 if (CONST_OK_FOR_ADD (size))
4583 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
4584 /* Try to do it with two partial adjustments; however, we must make
4585 sure that the stack is properly aligned at all times, in case
4586 an interrupt occurs between the two partial adjustments. */
4587 else if (CONST_OK_FOR_ADD (size / 2 & -align)
4588 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
4590 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
4591 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
4597 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
4600 /* If TEMP is invalid, we could temporarily save a general
4601 register to MACL. However, there is currently no need
4602 to handle this case, so just abort when we see it. */
4603 if (current_function_interrupt
4604 || ! call_used_regs[temp] || fixed_regs[temp])
4606 if (temp < 0 && ! current_function_interrupt)
4609 COPY_HARD_REG_SET (temps, call_used_reg_set);
4610 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
4613 for (i = 0; i < HARD_REGNO_NREGS (FIRST_RET_REG, DImode); i++)
4614 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
4615 if (current_function_calls_eh_return)
4617 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
4618 for (i = 0; i <= 3; i++)
4619 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
4624 for (i = FIRST_PARM_REG;
4625 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
4626 CLEAR_HARD_REG_BIT (temps, i);
4627 if (current_function_needs_context)
4628 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
4630 temp = scavenge_reg (&temps);
4632 if (temp < 0 && live_regs_mask)
4633 temp = scavenge_reg (live_regs_mask);
4636 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
4638 /* If SIZE is negative, subtract the positive value.
4639 This sometimes allows a constant pool entry to be shared
4640 between prologue and epilogue code. */
4643 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
4644 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
4648 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
4649 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
4653 = (gen_rtx_EXPR_LIST
4654 (REG_FRAME_RELATED_EXPR,
4655 gen_rtx_SET (VOIDmode, reg,
4656 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
4667 RTX_FRAME_RELATED_P (x) = 1;
4671 /* Output RTL to push register RN onto the stack. */
4679 x = gen_push_fpul ();
4680 else if (rn == FPSCR_REG)
4681 x = gen_push_fpscr ();
4682 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4683 && FP_OR_XD_REGISTER_P (rn))
4685 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4687 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
4689 else if (TARGET_SH2E && FP_REGISTER_P (rn))
4690 x = gen_push_e (gen_rtx_REG (SFmode, rn));
4692 x = gen_push (gen_rtx_REG (SImode, rn));
4696 = gen_rtx_EXPR_LIST (REG_INC,
4697 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4701 /* Output RTL to pop register RN from the stack. */
4709 x = gen_pop_fpul ();
4710 else if (rn == FPSCR_REG)
4711 x = gen_pop_fpscr ();
4712 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4713 && FP_OR_XD_REGISTER_P (rn))
4715 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4717 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
4719 else if (TARGET_SH2E && FP_REGISTER_P (rn))
4720 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
4722 x = gen_pop (gen_rtx_REG (SImode, rn));
4726 = gen_rtx_EXPR_LIST (REG_INC,
4727 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4730 /* Generate code to push the regs specified in the mask. */
4733 push_regs (mask, interrupt_handler)
4735 int interrupt_handler;
4740 /* Push PR last; this gives better latencies after the prologue, and
4741 candidates for the return delay slot when there are no general
4742 registers pushed. */
4743 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4745 /* If this is an interrupt handler, and the SZ bit varies,
4746 and we have to push any floating point register, we need
4747 to switch to the correct precision first. */
4748 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
4749 && hard_regs_intersect_p (mask, ®_class_contents[DF_REGS]))
4751 HARD_REG_SET unsaved;
4754 COMPL_HARD_REG_SET(unsaved, *mask);
4755 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
4759 && (i != FPSCR_REG || ! skip_fpscr)
4760 && TEST_HARD_REG_BIT (*mask, i))
4763 if (TEST_HARD_REG_BIT (*mask, PR_REG))
4767 /* Calculate how much extra space is needed to save all callee-saved
4769 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4772 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
4775 int stack_space = 0;
4776 int interrupt_handler = sh_cfun_interrupt_handler_p ();
4778 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
4779 if ((! call_used_regs[reg] || interrupt_handler)
4780 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
4781 /* Leave space to save this target register on the stack,
4782 in case target register allocation wants to use it. */
4783 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4787 /* Decide whether we should reserve space for callee-save target registers,
4788 in case target register allocation wants to use them. REGS_SAVED is
4789 the space, in bytes, that is already required for register saves.
4790 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4793 shmedia_reserve_space_for_target_registers_p (int regs_saved,
4794 HARD_REG_SET *live_regs_mask)
4798 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
4801 /* Decide how much space to reserve for callee-save target registers
4802 in case target register allocation wants to use them.
4803 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4806 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
4808 if (shmedia_space_reserved_for_target_registers)
4809 return shmedia_target_regs_stack_space (live_regs_mask);
4814 /* Work out the registers which need to be saved, both as a mask and a
4815 count of saved words. Return the count.
4817 If doing a pragma interrupt function, then push all regs used by the
4818 function, and if we call another function (we can tell by looking at PR),
4819 make sure that all the regs it clobbers are safe too. */
4822 calc_live_regs (live_regs_mask)
4823 HARD_REG_SET *live_regs_mask;
4827 int interrupt_handler;
4828 int pr_live, has_call;
4830 interrupt_handler = sh_cfun_interrupt_handler_p ();
4832 CLEAR_HARD_REG_SET (*live_regs_mask);
4833 if (TARGET_SH4 && TARGET_FMOVD && interrupt_handler
4834 && regs_ever_live[FPSCR_REG])
4835 target_flags &= ~FPU_SINGLE_BIT;
4836 /* If we can save a lot of saves by switching to double mode, do that. */
4837 else if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
4838 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
4839 if (regs_ever_live[reg] && regs_ever_live[reg+1]
4840 && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa))
4843 target_flags &= ~FPU_SINGLE_BIT;
4846 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
4847 knows how to use it. That means the pseudo originally allocated for
4848 the initial value can become the PR_MEDIA_REG hard register, as seen for
4849 execute/20010122-1.c:test9. */
4851 /* ??? this function is called from initial_elimination_offset, hence we
4852 can't use the result of sh_media_register_for_return here. */
4853 pr_live = sh_pr_n_sets ();
4856 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
4857 pr_live = (pr_initial
4858 ? (GET_CODE (pr_initial) != REG
4859 || REGNO (pr_initial) != (PR_REG))
4860 : regs_ever_live[PR_REG]);
4861 /* For Shcompact, if not optimizing, we end up with a memory reference
4862 using the return address pointer for __builtin_return_address even
4863 though there is no actual need to put the PR register on the stack. */
4864 pr_live |= regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM];
4866 /* Force PR to be live if the prologue has to call the SHmedia
4867 argument decoder or register saver. */
4868 if (TARGET_SHCOMPACT
4869 && ((current_function_args_info.call_cookie
4870 & ~ CALL_COOKIE_RET_TRAMP (1))
4871 || current_function_has_nonlocal_label))
4873 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
4874 for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
4876 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
4878 : (interrupt_handler && ! pragma_trapa)
4879 ? (/* Need to save all the regs ever live. */
4880 (regs_ever_live[reg]
4881 || (call_used_regs[reg]
4882 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
4884 || (has_call && REGISTER_NATURAL_MODE (reg) == SImode
4885 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
4886 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
4887 && reg != RETURN_ADDRESS_POINTER_REGNUM
4888 && reg != T_REG && reg != GBR_REG
4889 /* Push fpscr only on targets which have FPU */
4890 && (reg != FPSCR_REG || TARGET_FPU_ANY))
4891 : (/* Only push those regs which are used and need to be saved. */
4894 && current_function_args_info.call_cookie
4895 && reg == (int) PIC_OFFSET_TABLE_REGNUM)
4896 || (regs_ever_live[reg] && ! call_used_regs[reg])
4897 || (current_function_calls_eh_return
4898 && (reg == (int) EH_RETURN_DATA_REGNO (0)
4899 || reg == (int) EH_RETURN_DATA_REGNO (1)
4900 || reg == (int) EH_RETURN_DATA_REGNO (2)
4901 || reg == (int) EH_RETURN_DATA_REGNO (3)))))
4903 SET_HARD_REG_BIT (*live_regs_mask, reg);
4904 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4906 if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD
4907 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
4909 if (FP_REGISTER_P (reg))
4911 if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
4913 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
4914 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
4917 else if (XD_REGISTER_P (reg))
4919 /* Must switch to double mode to access these registers. */
4920 target_flags &= ~FPU_SINGLE_BIT;
4925 /* If we have a target register optimization pass after prologue / epilogue
4926 threading, we need to assume all target registers will be live even if
4928 if (flag_branch_target_load_optimize2
4929 && TARGET_SAVE_ALL_TARGET_REGS
4930 && shmedia_space_reserved_for_target_registers)
4931 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
4932 if ((! call_used_regs[reg] || interrupt_handler)
4933 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
4935 SET_HARD_REG_BIT (*live_regs_mask, reg);
4936 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4938 /* If this is an interrupt handler, we don't have any call-clobbered
4939 registers we can conveniently use for target register save/restore.
4940 Make sure we save at least one general purpose register when we need
4941 to save target registers. */
4942 if (interrupt_handler
4943 && hard_regs_intersect_p (live_regs_mask,
4944 ®_class_contents[TARGET_REGS])
4945 && ! hard_regs_intersect_p (live_regs_mask,
4946 ®_class_contents[GENERAL_REGS]))
4948 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
4949 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
4955 /* Code to generate prologue and epilogue sequences */
4957 /* PUSHED is the number of bytes that are being pushed on the
4958 stack for register saves. Return the frame size, padded
4959 appropriately so that the stack stays properly aligned. */
4960 static HOST_WIDE_INT
4961 rounded_frame_size (pushed)
4964 HOST_WIDE_INT size = get_frame_size ();
4965 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4967 return ((size + pushed + align - 1) & -align) - pushed;
4970 /* Choose a call-clobbered target-branch register that remains
4971 unchanged along the whole function. We set it up as the return
4972 value in the prologue. */
4974 sh_media_register_for_return ()
4979 if (! current_function_is_leaf)
4981 if (lookup_attribute ("interrupt_handler",
4982 DECL_ATTRIBUTES (current_function_decl)))
4985 tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
4987 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
4988 if (call_used_regs[regno] && ! regs_ever_live[regno])
4994 /* The maximum registers we need to save are:
4995 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
4996 - 32 floating point registers (for each pair, we save none,
4997 one single precision value, or a double precision value).
4998 - 8 target registers
4999 - add 1 entry for a delimiter. */
5000 #define MAX_SAVED_REGS (62+32+8)
5002 typedef struct save_entry_s
5011 /* There will be a delimiter entry with VOIDmode both at the start and the
5012 end of a filled in schedule. The end delimiter has the offset of the
5013 save with the smallest (i.e. most negative) offset. */
5014 typedef struct save_schedule_s
5016 save_entry entries[MAX_SAVED_REGS + 2];
5017 int temps[MAX_TEMPS+1];
5020 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
5021 use reverse order. Returns the last entry written to (not counting
5022 the delimiter). OFFSET_BASE is a number to be added to all offset
5026 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
5030 save_entry *entry = schedule->entries;
5034 if (! current_function_interrupt)
5035 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
5036 if (call_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
5037 && ! FUNCTION_ARG_REGNO_P (i)
5038 && i != FIRST_RET_REG
5039 && ! (current_function_needs_context && i == STATIC_CHAIN_REGNUM)
5040 && ! (current_function_calls_eh_return
5041 && (i == EH_RETURN_STACKADJ_REGNO
5042 || ((unsigned)i <= EH_RETURN_DATA_REGNO (0)
5043 && (unsigned)i >= EH_RETURN_DATA_REGNO (3)))))
5044 schedule->temps[tmpx++] = i;
5046 entry->mode = VOIDmode;
5047 entry->offset = offset_base;
5049 /* We loop twice: first, we save 8-byte aligned registers in the
5050 higher addresses, that are known to be aligned. Then, we
5051 proceed to saving 32-bit registers that don't need 8-byte
5053 If this is an interrupt function, all registers that need saving
5054 need to be saved in full. moreover, we need to postpone saving
5055 target registers till we have saved some general purpose registers
5056 we can then use as scratch registers. */
5057 offset = offset_base;
5058 for (align = 1; align >= 0; align--)
5060 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
5061 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
5063 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5066 if (current_function_interrupt)
5068 if (TARGET_REGISTER_P (i))
5070 if (GENERAL_REGISTER_P (i))
5073 if (mode == SFmode && (i % 2) == 1
5074 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5075 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
5082 /* If we're doing the aligned pass and this is not aligned,
5083 or we're doing the unaligned pass and this is aligned,
5085 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
5089 if (current_function_interrupt
5090 && GENERAL_REGISTER_P (i)
5091 && tmpx < MAX_TEMPS)
5092 schedule->temps[tmpx++] = i;
5094 offset -= GET_MODE_SIZE (mode);
5097 entry->offset = offset;
5100 if (align && current_function_interrupt)
5101 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
5102 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
5104 offset -= GET_MODE_SIZE (DImode);
5106 entry->mode = DImode;
5107 entry->offset = offset;
5112 entry->mode = VOIDmode;
5113 entry->offset = offset;
5114 schedule->temps[tmpx] = -1;
5119 sh_expand_prologue ()
5121 HARD_REG_SET live_regs_mask;
5124 int save_flags = target_flags;
5126 current_function_interrupt = sh_cfun_interrupt_handler_p ();
5128 /* We have pretend args if we had an object sent partially in registers
5129 and partially on the stack, e.g. a large structure. */
5130 output_stack_adjust (-current_function_pretend_args_size
5131 - current_function_args_info.stack_regs * 8,
5132 stack_pointer_rtx, 0, NULL);
5136 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
5137 /* We're going to use the PIC register to load the address of the
5138 incoming-argument decoder and/or of the return trampoline from
5139 the GOT, so make sure the PIC register is preserved and
5141 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
5143 if (TARGET_SHCOMPACT
5144 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
5148 /* First, make all registers with incoming arguments that will
5149 be pushed onto the stack live, so that register renaming
5150 doesn't overwrite them. */
5151 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
5152 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
5153 >= NPARM_REGS (SImode) - reg)
5154 for (; reg < NPARM_REGS (SImode); reg++)
5155 emit_insn (gen_shcompact_preserve_incoming_args
5156 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
5157 else if (CALL_COOKIE_INT_REG_GET
5158 (current_function_args_info.call_cookie, reg) == 1)
5159 emit_insn (gen_shcompact_preserve_incoming_args
5160 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
5162 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
5164 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
5165 GEN_INT (current_function_args_info.call_cookie));
5166 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
5167 gen_rtx_REG (SImode, R0_REG));
5169 else if (TARGET_SHMEDIA)
5171 int tr = sh_media_register_for_return ();
5175 rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr),
5176 gen_rtx_REG (DImode, PR_MEDIA_REG));
5178 /* ??? We should suppress saving pr when we don't need it, but this
5179 is tricky because of builtin_return_address. */
5181 /* If this function only exits with sibcalls, this copy
5182 will be flagged as dead. */
5183 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5189 /* Emit the code for SETUP_VARARGS. */
5190 if (current_function_stdarg)
5192 /* This is not used by the SH2E calling convention */
5193 if (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 && ! TARGET_HITACHI)
5195 /* Push arg regs as if they'd been provided by caller in stack. */
5196 for (i = 0; i < NPARM_REGS(SImode); i++)
5198 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
5201 if (i >= (NPARM_REGS(SImode)
5202 - current_function_args_info.arg_count[(int) SH_ARG_INT]
5206 RTX_FRAME_RELATED_P (insn) = 0;
5212 /* If we're supposed to switch stacks at function entry, do so now. */
5214 emit_insn (gen_sp_switch_1 ());
5216 d = calc_live_regs (&live_regs_mask);
5217 /* ??? Maybe we could save some switching if we can move a mode switch
5218 that already happens to be at the function start into the prologue. */
5219 if (target_flags != save_flags && ! current_function_interrupt)
5220 emit_insn (gen_toggle_sz ());
5224 int offset_base, offset;
5226 int offset_in_r0 = -1;
5228 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
5229 int total_size, save_size;
5230 save_schedule schedule;
5234 if (call_used_regs[R0_REG] && ! fixed_regs[R0_REG]
5235 && ! current_function_interrupt)
5236 r0 = gen_rtx_REG (Pmode, R0_REG);
5238 /* D is the actual number of bytes that we need for saving registers,
5239 however, in initial_elimination_offset we have committed to using
5240 an additional TREGS_SPACE amount of bytes - in order to keep both
5241 addresses to arguments supplied by the caller and local variables
5242 valid, we must keep this gap. Place it between the incoming
5243 arguments and the actually saved registers in a bid to optimize
5244 locality of reference. */
5245 total_size = d + tregs_space;
5246 total_size += rounded_frame_size (total_size);
5247 save_size = total_size - rounded_frame_size (d);
5248 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
5249 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5250 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
5252 /* If adjusting the stack in a single step costs nothing extra, do so.
5253 I.e. either if a single addi is enough, or we need a movi anyway,
5254 and we don't exceed the maximum offset range (the test for the
5255 latter is conservative for simplicity). */
5257 && (CONST_OK_FOR_I10 (-total_size)
5258 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
5259 && total_size <= 2044)))
5260 d_rounding = total_size - save_size;
5262 offset_base = d + d_rounding;
5264 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
5267 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
5268 tmp_pnt = schedule.temps;
5269 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
5271 enum machine_mode mode = entry->mode;
5272 int reg = entry->reg;
5273 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
5275 offset = entry->offset;
5277 reg_rtx = gen_rtx_REG (mode, reg);
5279 mem_rtx = gen_rtx_MEM (mode,
5280 gen_rtx_PLUS (Pmode,
5284 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
5292 if (HAVE_PRE_DECREMENT
5293 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
5294 || mem_rtx == NULL_RTX
5295 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
5297 pre_dec = gen_rtx_MEM (mode,
5298 gen_rtx_PRE_DEC (Pmode, r0));
5300 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
5309 offset += GET_MODE_SIZE (mode);
5313 if (mem_rtx != NULL_RTX)
5316 if (offset_in_r0 == -1)
5318 emit_move_insn (r0, GEN_INT (offset));
5319 offset_in_r0 = offset;
5321 else if (offset != offset_in_r0)
5326 GEN_INT (offset - offset_in_r0)));
5327 offset_in_r0 += offset - offset_in_r0;
5330 if (pre_dec != NULL_RTX)
5336 (Pmode, r0, stack_pointer_rtx));
5340 offset -= GET_MODE_SIZE (mode);
5341 offset_in_r0 -= GET_MODE_SIZE (mode);
5346 mem_rtx = gen_rtx_MEM (mode, r0);
5348 mem_rtx = gen_rtx_MEM (mode,
5349 gen_rtx_PLUS (Pmode,
5353 /* We must not use an r0-based address for target-branch
5354 registers or for special registers without pre-dec
5355 memory addresses, since we store their values in r0
5357 if (TARGET_REGISTER_P (reg)
5358 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5359 && mem_rtx != pre_dec))
5363 if (TARGET_REGISTER_P (reg)
5364 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5365 && mem_rtx != pre_dec))
5367 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
5369 emit_move_insn (tmp_reg, reg_rtx);
5371 if (REGNO (tmp_reg) == R0_REG)
5375 if (refers_to_regno_p (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0))
5379 if (*++tmp_pnt <= 0)
5380 tmp_pnt = schedule.temps;
5387 /* Mark as interesting for dwarf cfi generator */
5388 insn = emit_move_insn (mem_rtx, reg_rtx);
5389 RTX_FRAME_RELATED_P (insn) = 1;
5391 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
5393 rtx reg_rtx = gen_rtx_REG (mode, reg);
5395 rtx mem_rtx = gen_rtx_MEM (mode,
5396 gen_rtx_PLUS (Pmode,
5400 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
5401 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
5403 REG_NOTES (insn) = note_rtx;
5408 if (entry->offset != d_rounding)
5412 push_regs (&live_regs_mask, current_function_interrupt);
5414 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5416 rtx insn = get_last_insn ();
5417 rtx last = emit_insn (gen_GOTaddr2picreg ());
5419 /* Mark these insns as possibly dead. Sometimes, flow2 may
5420 delete all uses of the PIC register. In this case, let it
5421 delete the initialization too. */
5424 insn = NEXT_INSN (insn);
5426 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5430 while (insn != last);
5433 if (SHMEDIA_REGS_STACK_ADJUST ())
5435 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5436 function_symbol (TARGET_FPU_ANY
5437 ? "__GCC_push_shmedia_regs"
5438 : "__GCC_push_shmedia_regs_nofpu"));
5439 /* This must NOT go through the PLT, otherwise mach and macl
5440 may be clobbered. */
5441 emit_insn (gen_shmedia_save_restore_regs_compact
5442 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
5445 if (target_flags != save_flags && ! current_function_interrupt)
5447 rtx insn = emit_insn (gen_toggle_sz ());
5449 /* If we're lucky, a mode switch in the function body will
5450 overwrite fpscr, turning this insn dead. Tell flow this
5451 insn is ok to delete. */
5452 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5457 target_flags = save_flags;
5459 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
5460 stack_pointer_rtx, 0, NULL);
5462 if (frame_pointer_needed)
5463 frame_insn (GEN_MOV (frame_pointer_rtx, stack_pointer_rtx));
5465 if (TARGET_SHCOMPACT
5466 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
5468 /* This must NOT go through the PLT, otherwise mach and macl
5469 may be clobbered. */
5470 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5471 function_symbol ("__GCC_shcompact_incoming_args"));
5472 emit_insn (gen_shcompact_incoming_args ());
5477 sh_expand_epilogue ()
5479 HARD_REG_SET live_regs_mask;
5483 int save_flags = target_flags;
5484 int frame_size, save_size;
5485 int fpscr_deferred = 0;
5487 d = calc_live_regs (&live_regs_mask);
5490 frame_size = rounded_frame_size (d);
5494 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
5496 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
5497 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5498 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
5500 total_size = d + tregs_space;
5501 total_size += rounded_frame_size (total_size);
5502 save_size = total_size - frame_size;
5504 /* If adjusting the stack in a single step costs nothing extra, do so.
5505 I.e. either if a single addi is enough, or we need a movi anyway,
5506 and we don't exceed the maximum offset range (the test for the
5507 latter is conservative for simplicity). */
5509 && ! frame_pointer_needed
5510 && (CONST_OK_FOR_I10 (total_size)
5511 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
5512 && total_size <= 2044)))
5513 d_rounding = frame_size;
5515 frame_size -= d_rounding;
5518 if (frame_pointer_needed)
5520 output_stack_adjust (frame_size, frame_pointer_rtx, 1, &live_regs_mask);
5522 /* We must avoid moving the stack pointer adjustment past code
5523 which reads from the local frame, else an interrupt could
5524 occur after the SP adjustment and clobber data in the local
5526 emit_insn (gen_blockage ());
5527 emit_insn (GEN_MOV (stack_pointer_rtx, frame_pointer_rtx));
5529 else if (frame_size)
5531 /* We must avoid moving the stack pointer adjustment past code
5532 which reads from the local frame, else an interrupt could
5533 occur after the SP adjustment and clobber data in the local
5535 emit_insn (gen_blockage ());
5536 output_stack_adjust (frame_size, stack_pointer_rtx, 1, &live_regs_mask);
5539 if (SHMEDIA_REGS_STACK_ADJUST ())
5541 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5542 function_symbol (TARGET_FPU_ANY
5543 ? "__GCC_pop_shmedia_regs"
5544 : "__GCC_pop_shmedia_regs_nofpu"));
5545 /* This must NOT go through the PLT, otherwise mach and macl
5546 may be clobbered. */
5547 emit_insn (gen_shmedia_save_restore_regs_compact
5548 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
5551 /* Pop all the registers. */
5553 if (target_flags != save_flags && ! current_function_interrupt)
5554 emit_insn (gen_toggle_sz ());
5557 int offset_base, offset;
5558 int offset_in_r0 = -1;
5560 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
5561 save_schedule schedule;
5565 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
5566 offset_base = -entry[1].offset + d_rounding;
5567 tmp_pnt = schedule.temps;
5568 for (; entry->mode != VOIDmode; entry--)
5570 enum machine_mode mode = entry->mode;
5571 int reg = entry->reg;
5572 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
5574 offset = offset_base + entry->offset;
5575 reg_rtx = gen_rtx_REG (mode, reg);
5577 mem_rtx = gen_rtx_MEM (mode,
5578 gen_rtx_PLUS (Pmode,
5582 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
5588 if (HAVE_POST_INCREMENT
5589 && (offset == offset_in_r0
5590 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
5591 && mem_rtx == NULL_RTX)
5592 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
5594 post_inc = gen_rtx_MEM (mode,
5595 gen_rtx_POST_INC (Pmode, r0));
5597 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
5600 post_inc = NULL_RTX;
5609 if (mem_rtx != NULL_RTX)
5612 if (offset_in_r0 == -1)
5614 emit_move_insn (r0, GEN_INT (offset));
5615 offset_in_r0 = offset;
5617 else if (offset != offset_in_r0)
5622 GEN_INT (offset - offset_in_r0)));
5623 offset_in_r0 += offset - offset_in_r0;
5626 if (post_inc != NULL_RTX)
5632 (Pmode, r0, stack_pointer_rtx));
5638 offset_in_r0 += GET_MODE_SIZE (mode);
5641 mem_rtx = gen_rtx_MEM (mode, r0);
5643 mem_rtx = gen_rtx_MEM (mode,
5644 gen_rtx_PLUS (Pmode,
5648 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5649 && mem_rtx != post_inc)
5653 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5654 && mem_rtx != post_inc)
5656 insn = emit_move_insn (r0, mem_rtx);
5659 else if (TARGET_REGISTER_P (reg))
5661 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
5663 /* Give the scheduler a bit of freedom by using up to
5664 MAX_TEMPS registers in a round-robin fashion. */
5665 insn = emit_move_insn (tmp_reg, mem_rtx);
5668 tmp_pnt = schedule.temps;
5671 insn = emit_move_insn (reg_rtx, mem_rtx);
5672 if (reg == PR_MEDIA_REG && sh_media_register_for_return () >= 0)
5673 /* This is dead, unless we return with a sibcall. */
5674 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5679 if (entry->offset + offset_base != d + d_rounding)
5682 else /* ! TARGET_SH5 */
5685 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
5687 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5689 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
5691 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
5692 && hard_regs_intersect_p (&live_regs_mask,
5693 ®_class_contents[DF_REGS]))
5695 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j))
5697 if (j == FIRST_FP_REG && fpscr_deferred)
5702 if (target_flags != save_flags && ! current_function_interrupt)
5703 emit_insn (gen_toggle_sz ());
5704 target_flags = save_flags;
5706 output_stack_adjust (extra_push + current_function_pretend_args_size
5707 + save_size + d_rounding
5708 + current_function_args_info.stack_regs * 8,
5709 stack_pointer_rtx, 1, NULL);
5711 if (current_function_calls_eh_return)
5712 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
5713 EH_RETURN_STACKADJ_RTX));
5715 /* Switch back to the normal stack if necessary. */
5717 emit_insn (gen_sp_switch_2 ());
5719 /* Tell flow the insn that pops PR isn't dead. */
5720 /* PR_REG will never be live in SHmedia mode, and we don't need to
5721 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
5722 by the return pattern. */
5723 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
5724 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
5727 static int sh_need_epilogue_known = 0;
5732 if (! sh_need_epilogue_known)
5737 sh_expand_epilogue ();
5738 epilogue = get_insns ();
5740 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
5742 return sh_need_epilogue_known > 0;
5745 /* Emit code to change the current function's return address to RA.
5746 TEMP is available as a scratch register, if needed. */
5749 sh_set_return_address (ra, tmp)
5752 HARD_REG_SET live_regs_mask;
5754 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
5757 d = calc_live_regs (&live_regs_mask);
5759 /* If pr_reg isn't life, we can set it (or the register given in
5760 sh_media_register_for_return) directly. */
5761 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
5767 int rr_regno = sh_media_register_for_return ();
5772 rr = gen_rtx_REG (DImode, rr_regno);
5775 rr = gen_rtx_REG (SImode, pr_reg);
5777 emit_insn (GEN_MOV (rr, ra));
5778 /* Tell flow the register for return isn't dead. */
5779 emit_insn (gen_rtx_USE (VOIDmode, rr));
5786 save_schedule schedule;
5789 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
5790 offset = entry[1].offset;
5791 for (; entry->mode != VOIDmode; entry--)
5792 if (entry->reg == pr_reg)
5795 /* We can't find pr register. */
5799 offset = entry->offset - offset;
5800 pr_offset = (rounded_frame_size (d) + offset
5801 + SHMEDIA_REGS_STACK_ADJUST ());
5804 pr_offset = rounded_frame_size (d);
5806 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
5807 emit_insn (GEN_ADD3 (tmp, tmp, frame_pointer_rtx));
5809 tmp = gen_rtx_MEM (Pmode, tmp);
5810 emit_insn (GEN_MOV (tmp, ra));
5813 /* Clear variables at function end. */
5816 sh_output_function_epilogue (file, size)
5817 FILE *file ATTRIBUTE_UNUSED;
5818 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
5820 trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
5821 sh_need_epilogue_known = 0;
5822 sp_switch = NULL_RTX;
5826 sh_builtin_saveregs ()
5828 /* First unnamed integer register. */
5829 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
5830 /* Number of integer registers we need to save. */
5831 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
5832 /* First unnamed SFmode float reg */
5833 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5834 /* Number of SFmode float regs to save. */
5835 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5838 HOST_WIDE_INT alias_set;
5844 int pushregs = n_intregs;
5846 while (pushregs < NPARM_REGS (SImode) - 1
5847 && (CALL_COOKIE_INT_REG_GET
5848 (current_function_args_info.call_cookie,
5849 NPARM_REGS (SImode) - pushregs)
5852 current_function_args_info.call_cookie
5853 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
5858 if (pushregs == NPARM_REGS (SImode))
5859 current_function_args_info.call_cookie
5860 |= (CALL_COOKIE_INT_REG (0, 1)
5861 | CALL_COOKIE_STACKSEQ (pushregs - 1));
5863 current_function_args_info.call_cookie
5864 |= CALL_COOKIE_STACKSEQ (pushregs);
5866 current_function_pretend_args_size += 8 * n_intregs;
5868 if (TARGET_SHCOMPACT)
5872 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
5874 error ("__builtin_saveregs not supported by this subtarget");
5881 /* Allocate block of memory for the regs. */
5882 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5883 Or can assign_stack_local accept a 0 SIZE argument? */
5884 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
5887 regbuf = gen_rtx_MEM (BLKmode,
5888 gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
5889 else if (n_floatregs & 1)
5893 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
5894 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
5895 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
5896 regbuf = change_address (regbuf, BLKmode, addr);
5899 regbuf = assign_stack_local (BLKmode, bufsize, 0);
5900 alias_set = get_varargs_alias_set ();
5901 set_mem_alias_set (regbuf, alias_set);
5904 This is optimized to only save the regs that are necessary. Explicitly
5905 named args need not be saved. */
5907 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
5908 adjust_address (regbuf, BLKmode,
5909 n_floatregs * UNITS_PER_WORD),
5913 /* Return the address of the regbuf. */
5914 return XEXP (regbuf, 0);
5917 This is optimized to only save the regs that are necessary. Explicitly
5918 named args need not be saved.
5919 We explicitly build a pointer to the buffer because it halves the insn
5920 count when not optimizing (otherwise the pointer is built for each reg
5922 We emit the moves in reverse order so that we can use predecrement. */
5924 fpregs = gen_reg_rtx (Pmode);
5925 emit_move_insn (fpregs, XEXP (regbuf, 0));
5926 emit_insn (gen_addsi3 (fpregs, fpregs,
5927 GEN_INT (n_floatregs * UNITS_PER_WORD)));
5931 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
5933 emit_insn (gen_addsi3 (fpregs, fpregs,
5934 GEN_INT (-2 * UNITS_PER_WORD)));
5935 mem = gen_rtx_MEM (DFmode, fpregs);
5936 set_mem_alias_set (mem, alias_set);
5937 emit_move_insn (mem,
5938 gen_rtx (REG, DFmode, BASE_ARG_REG (DFmode) + regno));
5940 regno = first_floatreg;
5943 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5944 mem = gen_rtx_MEM (SFmode, fpregs);
5945 set_mem_alias_set (mem, alias_set);
5946 emit_move_insn (mem,
5947 gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno
5948 - (TARGET_LITTLE_ENDIAN != 0)));
5952 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
5956 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5957 mem = gen_rtx_MEM (SFmode, fpregs);
5958 set_mem_alias_set (mem, alias_set);
5959 emit_move_insn (mem,
5960 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
5963 /* Return the address of the regbuf. */
5964 return XEXP (regbuf, 0);
5967 /* Define the `__builtin_va_list' type for the ABI. */
5972 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5975 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI)
5976 return ptr_type_node;
5978 record = make_node (RECORD_TYPE);
5980 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
5982 f_next_o_limit = build_decl (FIELD_DECL,
5983 get_identifier ("__va_next_o_limit"),
5985 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
5987 f_next_fp_limit = build_decl (FIELD_DECL,
5988 get_identifier ("__va_next_fp_limit"),
5990 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
5993 DECL_FIELD_CONTEXT (f_next_o) = record;
5994 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
5995 DECL_FIELD_CONTEXT (f_next_fp) = record;
5996 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
5997 DECL_FIELD_CONTEXT (f_next_stack) = record;
5999 TYPE_FIELDS (record) = f_next_o;
6000 TREE_CHAIN (f_next_o) = f_next_o_limit;
6001 TREE_CHAIN (f_next_o_limit) = f_next_fp;
6002 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
6003 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
6005 layout_type (record);
6010 /* Implement `va_start' for varargs and stdarg. */
6013 sh_va_start (valist, nextarg)
6017 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
6018 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
6024 expand_builtin_saveregs ();
6025 std_expand_builtin_va_start (valist, nextarg);
6029 if ((! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI)
6031 std_expand_builtin_va_start (valist, nextarg);
6035 f_next_o = TYPE_FIELDS (va_list_type_node);
6036 f_next_o_limit = TREE_CHAIN (f_next_o);
6037 f_next_fp = TREE_CHAIN (f_next_o_limit);
6038 f_next_fp_limit = TREE_CHAIN (f_next_fp);
6039 f_next_stack = TREE_CHAIN (f_next_fp_limit);
6041 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
6042 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
6043 valist, f_next_o_limit);
6044 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp);
6045 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
6046 valist, f_next_fp_limit);
6047 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
6048 valist, f_next_stack);
6050 /* Call __builtin_saveregs. */
6051 u = make_tree (ptr_type_node, expand_builtin_saveregs ());
6052 t = build (MODIFY_EXPR, ptr_type_node, next_fp, u);
6053 TREE_SIDE_EFFECTS (t) = 1;
6054 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6056 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
6061 u = fold (build (PLUS_EXPR, ptr_type_node, u,
6062 build_int_2 (UNITS_PER_WORD * nfp, 0)));
6063 t = build (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
6064 TREE_SIDE_EFFECTS (t) = 1;
6065 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6067 t = build (MODIFY_EXPR, ptr_type_node, next_o, u);
6068 TREE_SIDE_EFFECTS (t) = 1;
6069 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6071 nint = current_function_args_info.arg_count[SH_ARG_INT];
6076 u = fold (build (PLUS_EXPR, ptr_type_node, u,
6077 build_int_2 (UNITS_PER_WORD * nint, 0)));
6078 t = build (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
6079 TREE_SIDE_EFFECTS (t) = 1;
6080 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6082 u = make_tree (ptr_type_node, nextarg);
6083 t = build (MODIFY_EXPR, ptr_type_node, next_stack, u);
6084 TREE_SIDE_EFFECTS (t) = 1;
6085 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6088 /* Implement `va_arg'. */
6091 sh_va_arg (valist, type)
6094 HOST_WIDE_INT size, rsize;
6095 tree tmp, pptr_type_node;
6097 rtx result_ptr, result = NULL_RTX;
6098 int pass_by_ref = MUST_PASS_IN_STACK (TYPE_MODE (type), type);
6101 size = int_size_in_bytes (type);
6102 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6103 pptr_type_node = build_pointer_type (ptr_type_node);
6106 type = build_pointer_type (type);
6108 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4) && ! TARGET_HITACHI)
6110 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
6111 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
6115 f_next_o = TYPE_FIELDS (va_list_type_node);
6116 f_next_o_limit = TREE_CHAIN (f_next_o);
6117 f_next_fp = TREE_CHAIN (f_next_o_limit);
6118 f_next_fp_limit = TREE_CHAIN (f_next_fp);
6119 f_next_stack = TREE_CHAIN (f_next_fp_limit);
6121 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
6122 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
6123 valist, f_next_o_limit);
6124 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp),
6126 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
6127 valist, f_next_fp_limit);
6128 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
6129 valist, f_next_stack);
6131 /* Structures with a single member with a distinct mode are passed
6132 like their member. This is relevant if the latter has a REAL_TYPE
6133 or COMPLEX_TYPE type. */
6134 if (TREE_CODE (type) == RECORD_TYPE
6135 && TYPE_FIELDS (type)
6136 && TREE_CODE (TYPE_FIELDS (type)) == FIELD_DECL
6137 && (TREE_CODE (TREE_TYPE (TYPE_FIELDS (type))) == REAL_TYPE
6138 || TREE_CODE (TREE_TYPE (TYPE_FIELDS (type))) == COMPLEX_TYPE)
6139 && TREE_CHAIN (TYPE_FIELDS (type)) == NULL_TREE)
6140 type = TREE_TYPE (TYPE_FIELDS (type));
6143 pass_as_float = ((TREE_CODE (type) == REAL_TYPE && size <= 8)
6144 || (TREE_CODE (type) == COMPLEX_TYPE
6145 && TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
6150 pass_as_float = (TREE_CODE (type) == REAL_TYPE && size == 4);
6153 addr_rtx = gen_reg_rtx (Pmode);
6154 lab_false = gen_label_rtx ();
6155 lab_over = gen_label_rtx ();
6157 tmp = make_tree (pptr_type_node, addr_rtx);
6158 valist = build1 (INDIRECT_REF, ptr_type_node, tmp);
6163 = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
6164 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
6166 emit_cmp_and_jump_insns (expand_expr (next_fp, NULL_RTX, Pmode,
6168 expand_expr (next_fp_limit, NULL_RTX,
6169 Pmode, EXPAND_NORMAL),
6170 GE, const1_rtx, Pmode, 1, lab_false);
6172 if (TYPE_ALIGN (type) > BITS_PER_WORD
6173 || (((TREE_CODE (type) == REAL_TYPE && size == 8) || size == 16)
6174 && (n_floatregs & 1)))
6176 tmp = build (BIT_AND_EXPR, ptr_type_node, next_fp,
6177 build_int_2 (UNITS_PER_WORD, 0));
6178 tmp = build (PLUS_EXPR, ptr_type_node, next_fp, tmp);
6179 tmp = build (MODIFY_EXPR, ptr_type_node, next_fp, tmp);
6180 TREE_SIDE_EFFECTS (tmp) = 1;
6181 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
6184 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
6185 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6187 emit_move_insn (addr_rtx, r);
6189 #ifdef FUNCTION_ARG_SCmode_WART
6190 if (TYPE_MODE (type) == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
6192 rtx addr, real, imag, result_value, slot;
6193 tree subtype = TREE_TYPE (type);
6195 addr = std_expand_builtin_va_arg (valist, subtype);
6196 #ifdef POINTERS_EXTEND_UNSIGNED
6197 if (GET_MODE (addr) != Pmode)
6198 addr = convert_memory_address (Pmode, addr);
6200 imag = gen_rtx_MEM (TYPE_MODE (type), addr);
6201 set_mem_alias_set (imag, get_varargs_alias_set ());
6203 addr = std_expand_builtin_va_arg (valist, subtype);
6204 #ifdef POINTERS_EXTEND_UNSIGNED
6205 if (GET_MODE (addr) != Pmode)
6206 addr = convert_memory_address (Pmode, addr);
6208 real = gen_rtx_MEM (TYPE_MODE (type), addr);
6209 set_mem_alias_set (real, get_varargs_alias_set ());
6211 result_value = gen_rtx_CONCAT (SCmode, real, imag);
6212 /* ??? this interface is stupid - why require a pointer? */
6213 result = gen_reg_rtx (Pmode);
6214 slot = assign_stack_temp (SCmode, 8, 0);
6215 emit_move_insn (slot, result_value);
6216 emit_move_insn (result, XEXP (slot, 0));
6218 #endif /* FUNCTION_ARG_SCmode_WART */
6220 emit_jump_insn (gen_jump (lab_over));
6222 emit_label (lab_false);
6224 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
6225 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6227 emit_move_insn (addr_rtx, r);
6231 tmp = build (PLUS_EXPR, ptr_type_node, next_o,
6232 build_int_2 (rsize, 0));
6234 emit_cmp_and_jump_insns (expand_expr (tmp, NULL_RTX, Pmode,
6236 expand_expr (next_o_limit, NULL_RTX,
6237 Pmode, EXPAND_NORMAL),
6238 GT, const1_rtx, Pmode, 1, lab_false);
6240 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
6241 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6243 emit_move_insn (addr_rtx, r);
6245 emit_jump_insn (gen_jump (lab_over));
6247 emit_label (lab_false);
6249 if (size > 4 && ! TARGET_SH4)
6251 tmp = build (MODIFY_EXPR, ptr_type_node, next_o, next_o_limit);
6252 TREE_SIDE_EFFECTS (tmp) = 1;
6253 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
6256 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
6257 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6259 emit_move_insn (addr_rtx, r);
6263 emit_label (lab_over);
6266 /* ??? In va-sh.h, there had been code to make values larger than
6267 size 8 indirect. This does not match the FUNCTION_ARG macros. */
6269 result_ptr = std_expand_builtin_va_arg (valist, type);
6272 emit_move_insn (result, result_ptr);
6273 emit_label (lab_over);
6276 result = result_ptr;
6280 #ifdef POINTERS_EXTEND_UNSIGNED
6281 if (GET_MODE (addr) != Pmode)
6282 addr = convert_memory_address (Pmode, result);
6284 result = gen_rtx_MEM (ptr_mode, force_reg (Pmode, result));
6285 set_mem_alias_set (result, get_varargs_alias_set ());
6287 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
6288 argument to the varargs alias set. */
6292 /* Define the offset between two registers, one to be eliminated, and
6293 the other its replacement, at the start of a routine. */
6296 initial_elimination_offset (from, to)
6301 int regs_saved_rounding = 0;
6302 int total_saved_regs_space;
6303 int total_auto_space;
6304 int save_flags = target_flags;
6306 HARD_REG_SET live_regs_mask;
6308 shmedia_space_reserved_for_target_registers = false;
6309 regs_saved = calc_live_regs (&live_regs_mask);
6310 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
6312 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
6314 shmedia_space_reserved_for_target_registers = true;
6315 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
6318 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
6319 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6320 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
6322 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
6323 copy_flags = target_flags;
6324 target_flags = save_flags;
6326 total_saved_regs_space = regs_saved + regs_saved_rounding;
6328 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
6329 return total_saved_regs_space + total_auto_space
6330 + current_function_args_info.byref_regs * 8;
6332 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
6333 return total_saved_regs_space + total_auto_space
6334 + current_function_args_info.byref_regs * 8;
6336 /* Initial gap between fp and sp is 0. */
6337 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
6340 if (from == RETURN_ADDRESS_POINTER_REGNUM
6341 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
6345 int n = total_saved_regs_space;
6346 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
6347 save_schedule schedule;
6350 n += total_auto_space;
6352 /* If it wasn't saved, there's not much we can do. */
6353 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
6356 target_flags = copy_flags;
6358 sh5_schedule_saves (&live_regs_mask, &schedule, n);
6359 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6360 if (entry->reg == pr_reg)
6362 target_flags = save_flags;
6363 return entry->offset;
6368 return total_auto_space;
6374 /* Handle machine specific pragmas to be semi-compatible with Renesas
6378 sh_pr_interrupt (pfile)
6379 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
6381 pragma_interrupt = 1;
6386 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
6388 pragma_interrupt = pragma_trapa = 1;
6392 sh_pr_nosave_low_regs (pfile)
6393 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
6395 pragma_nosave_low_regs = 1;
6398 /* Generate 'handle_interrupt' attribute for decls */
6401 sh_insert_attributes (node, attributes)
6405 if (! pragma_interrupt
6406 || TREE_CODE (node) != FUNCTION_DECL)
6409 /* We are only interested in fields. */
6410 if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd')
6413 /* Add a 'handle_interrupt' attribute. */
6414 * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes);
6419 /* Supported attributes:
6421 interrupt_handler -- specifies this function is an interrupt handler.
6423 sp_switch -- specifies an alternate stack for an interrupt handler
6426 trap_exit -- use a trapa to exit an interrupt function instead of
6427 an rte instruction. */
6429 const struct attribute_spec sh_attribute_table[] =
6431 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6432 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
6433 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
6434 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
6435 { NULL, 0, 0, false, false, false, NULL }
6438 /* Handle an "interrupt_handler" attribute; arguments as in
6439 struct attribute_spec.handler. */
6441 sh_handle_interrupt_handler_attribute (node, name, args, flags, no_add_attrs)
6444 tree args ATTRIBUTE_UNUSED;
6445 int flags ATTRIBUTE_UNUSED;
6448 if (TREE_CODE (*node) != FUNCTION_DECL)
6450 warning ("`%s' attribute only applies to functions",
6451 IDENTIFIER_POINTER (name));
6452 *no_add_attrs = true;
6454 else if (TARGET_SHCOMPACT)
6456 error ("attribute interrupt_handler is not compatible with -m5-compact");
6457 *no_add_attrs = true;
6463 /* Handle an "sp_switch" attribute; arguments as in
6464 struct attribute_spec.handler. */
6466 sh_handle_sp_switch_attribute (node, name, args, flags, no_add_attrs)
6470 int flags ATTRIBUTE_UNUSED;
6473 if (TREE_CODE (*node) != FUNCTION_DECL)
6475 warning ("`%s' attribute only applies to functions",
6476 IDENTIFIER_POINTER (name));
6477 *no_add_attrs = true;
6479 else if (!pragma_interrupt)
6481 /* The sp_switch attribute only has meaning for interrupt functions. */
6482 warning ("`%s' attribute only applies to interrupt functions",
6483 IDENTIFIER_POINTER (name));
6484 *no_add_attrs = true;
6486 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
6488 /* The argument must be a constant string. */
6489 warning ("`%s' attribute argument not a string constant",
6490 IDENTIFIER_POINTER (name));
6491 *no_add_attrs = true;
6495 sp_switch = gen_rtx_SYMBOL_REF (VOIDmode,
6496 TREE_STRING_POINTER (TREE_VALUE (args)));
6502 /* Handle an "trap_exit" attribute; arguments as in
6503 struct attribute_spec.handler. */
6505 sh_handle_trap_exit_attribute (node, name, args, flags, no_add_attrs)
6509 int flags ATTRIBUTE_UNUSED;
6512 if (TREE_CODE (*node) != FUNCTION_DECL)
6514 warning ("`%s' attribute only applies to functions",
6515 IDENTIFIER_POINTER (name));
6516 *no_add_attrs = true;
6518 else if (!pragma_interrupt)
6520 /* The trap_exit attribute only has meaning for interrupt functions. */
6521 warning ("`%s' attribute only applies to interrupt functions",
6522 IDENTIFIER_POINTER (name));
6523 *no_add_attrs = true;
6525 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
6527 /* The argument must be a constant integer. */
6528 warning ("`%s' attribute argument not an integer constant",
6529 IDENTIFIER_POINTER (name));
6530 *no_add_attrs = true;
6534 trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
6541 sh_cfun_interrupt_handler_p ()
6543 return (lookup_attribute ("interrupt_handler",
6544 DECL_ATTRIBUTES (current_function_decl))
6548 /* Predicates used by the templates. */
6550 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
6551 Used only in general_movsrc_operand. */
6554 system_reg_operand (op, mode)
6556 enum machine_mode mode ATTRIBUTE_UNUSED;
6568 /* Returns 1 if OP can be source of a simple move operation.
6569 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
6570 invalid as are subregs of system registers. */
6573 general_movsrc_operand (op, mode)
6575 enum machine_mode mode;
6577 if (GET_CODE (op) == MEM)
6579 rtx inside = XEXP (op, 0);
6580 if (GET_CODE (inside) == CONST)
6581 inside = XEXP (inside, 0);
6583 if (GET_CODE (inside) == LABEL_REF)
6586 if (GET_CODE (inside) == PLUS
6587 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
6588 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
6591 /* Only post inc allowed. */
6592 if (GET_CODE (inside) == PRE_DEC)
6596 if ((mode == QImode || mode == HImode)
6597 && (GET_CODE (op) == SUBREG
6598 && GET_CODE (XEXP (op, 0)) == REG
6599 && system_reg_operand (XEXP (op, 0), mode)))
6602 return general_operand (op, mode);
6605 /* Returns 1 if OP can be a destination of a move.
6606 Same as general_operand, but no preinc allowed. */
6609 general_movdst_operand (op, mode)
6611 enum machine_mode mode;
6613 /* Only pre dec allowed. */
6614 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
6617 return general_operand (op, mode);
6620 /* Returns 1 if OP is a normal arithmetic register. */
6623 arith_reg_operand (op, mode)
6625 enum machine_mode mode;
6627 if (register_operand (op, mode))
6631 if (GET_CODE (op) == REG)
6633 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
6634 regno = REGNO (SUBREG_REG (op));
6638 return (regno != T_REG && regno != PR_REG
6639 && ! TARGET_REGISTER_P (regno)
6640 && (regno != FPUL_REG || TARGET_SH4)
6641 && regno != MACH_REG && regno != MACL_REG);
6646 /* Like above, but for DImode destinations: forbid paradoxical DImode subregs,
6647 because this would lead to missing sign extensions when truncating from
6648 DImode to SImode. */
6650 arith_reg_dest (op, mode)
6652 enum machine_mode mode;
6654 if (mode == DImode && GET_CODE (op) == SUBREG
6655 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
6657 return arith_reg_operand (op, mode);
6661 int_gpr_dest (op, mode)
6663 enum machine_mode mode ATTRIBUTE_UNUSED;
6665 enum machine_mode op_mode = GET_MODE (op);
6667 if (GET_MODE_CLASS (op_mode) != MODE_INT
6668 || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
6670 if (! reload_completed)
6672 return true_regnum (op) <= LAST_GENERAL_REG;
6676 fp_arith_reg_operand (op, mode)
6678 enum machine_mode mode;
6680 if (register_operand (op, mode))
6684 if (GET_CODE (op) == REG)
6686 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
6687 regno = REGNO (SUBREG_REG (op));
6691 return (regno >= FIRST_PSEUDO_REGISTER
6692 || FP_REGISTER_P (regno));
6697 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
6700 arith_operand (op, mode)
6702 enum machine_mode mode;
6704 if (arith_reg_operand (op, mode))
6709 /* FIXME: We should be checking whether the CONST_INT fits in a
6710 CONST_OK_FOR_I16 here, but this causes reload_cse to crash when
6711 attempting to transform a sequence of two 64-bit sets of the
6712 same register from literal constants into a set and an add,
6713 when the difference is too wide for an add. */
6714 if (GET_CODE (op) == CONST_INT
6715 || EXTRA_CONSTRAINT_C16 (op))
6720 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (op)))
6726 /* Returns 1 if OP is a valid source operand for a compare insn. */
6729 arith_reg_or_0_operand (op, mode)
6731 enum machine_mode mode;
6733 if (arith_reg_operand (op, mode))
6736 if (EXTRA_CONSTRAINT_Z (op))
6742 /* Return 1 if OP is a valid source operand for an SHmedia operation
6743 that takes either a register or a 6-bit immediate. */
6746 shmedia_6bit_operand (op, mode)
6748 enum machine_mode mode;
6750 return (arith_reg_operand (op, mode)
6751 || (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I06 (INTVAL (op))));
6754 /* Returns 1 if OP is a valid source operand for a logical operation. */
6757 logical_operand (op, mode)
6759 enum machine_mode mode;
6761 if (arith_reg_operand (op, mode))
6766 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I10 (INTVAL (op)))
6771 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K08 (INTVAL (op)))
6778 and_operand (op, mode)
6780 enum machine_mode mode;
6782 if (logical_operand (op, mode))
6785 /* Check mshflo.l / mshflhi.l opportunities. */
6788 && GET_CODE (op) == CONST_INT
6789 && CONST_OK_FOR_J16 (INTVAL (op)))
6795 /* Nonzero if OP is a floating point value with value 0.0. */
6798 fp_zero_operand (op)
6803 if (GET_MODE (op) != SFmode)
6806 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
6807 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
6810 /* Nonzero if OP is a floating point value with value 1.0. */
6818 if (GET_MODE (op) != SFmode)
6821 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
6822 return REAL_VALUES_EQUAL (r, dconst1);
6825 /* For -m4 and -m4-single-only, mode switching is used. If we are
6826 compiling without -mfmovd, movsf_ie isn't taken into account for
6827 mode switching. We could check in machine_dependent_reorg for
6828 cases where we know we are in single precision mode, but there is
6829 interface to find that out during reload, so we must avoid
6830 choosing an fldi alternative during reload and thus failing to
6831 allocate a scratch register for the constant loading. */
6835 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
6839 tertiary_reload_operand (op, mode)
6841 enum machine_mode mode ATTRIBUTE_UNUSED;
6843 enum rtx_code code = GET_CODE (op);
6844 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
6848 fpscr_operand (op, mode)
6850 enum machine_mode mode ATTRIBUTE_UNUSED;
6852 return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG
6853 && GET_MODE (op) == PSImode);
6857 fpul_operand (op, mode)
6859 enum machine_mode mode;
6862 return fp_arith_reg_operand (op, mode);
6864 return (GET_CODE (op) == REG
6865 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
6866 && GET_MODE (op) == mode);
6870 symbol_ref_operand (op, mode)
6872 enum machine_mode mode ATTRIBUTE_UNUSED;
6874 return (GET_CODE (op) == SYMBOL_REF);
6877 /* Return the TLS type for TLS symbols, 0 for otherwise. */
6879 tls_symbolic_operand (op, mode)
6881 enum machine_mode mode ATTRIBUTE_UNUSED;
6883 if (GET_CODE (op) != SYMBOL_REF)
6885 return SYMBOL_REF_TLS_MODEL (op);
6889 commutative_float_operator (op, mode)
6891 enum machine_mode mode;
6893 if (GET_MODE (op) != mode)
6895 switch (GET_CODE (op))
6907 noncommutative_float_operator (op, mode)
6909 enum machine_mode mode;
6911 if (GET_MODE (op) != mode)
6913 switch (GET_CODE (op))
6925 unary_float_operator (op, mode)
6927 enum machine_mode mode;
6929 if (GET_MODE (op) != mode)
6931 switch (GET_CODE (op))
6944 binary_float_operator (op, mode)
6946 enum machine_mode mode;
6948 if (GET_MODE (op) != mode)
6950 switch (GET_CODE (op))
6964 binary_logical_operator (op, mode)
6966 enum machine_mode mode;
6968 if (GET_MODE (op) != mode)
6970 switch (GET_CODE (op))
6983 equality_comparison_operator (op, mode)
6985 enum machine_mode mode;
6987 return ((mode == VOIDmode || GET_MODE (op) == mode)
6988 && (GET_CODE (op) == EQ || GET_CODE (op) == NE));
6991 int greater_comparison_operator (op, mode)
6993 enum machine_mode mode;
6995 if (mode != VOIDmode && GET_MODE (op) == mode)
6997 switch (GET_CODE (op))
7009 int less_comparison_operator (op, mode)
7011 enum machine_mode mode;
7013 if (mode != VOIDmode && GET_MODE (op) == mode)
7015 switch (GET_CODE (op))
7027 /* Accept pseudos and branch target registers. */
7029 target_reg_operand (op, mode)
7031 enum machine_mode mode;
7034 || GET_MODE (op) != DImode)
7037 if (GET_CODE (op) == SUBREG)
7040 if (GET_CODE (op) != REG)
7043 /* We must protect ourselves from matching pseudos that are virtual
7044 register, because they will eventually be replaced with hardware
7045 registers that aren't branch-target registers. */
7046 if (REGNO (op) > LAST_VIRTUAL_REGISTER
7047 || TARGET_REGISTER_P (REGNO (op)))
7053 /* Same as target_reg_operand, except that label_refs and symbol_refs
7054 are accepted before reload. */
7056 target_operand (op, mode)
7058 enum machine_mode mode;
7063 if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode)
7064 && EXTRA_CONSTRAINT_Csy (op))
7065 return ! reload_completed;
7067 return target_reg_operand (op, mode);
7071 mextr_bit_offset (op, mode)
7073 enum machine_mode mode ATTRIBUTE_UNUSED;
7077 if (GET_CODE (op) != CONST_INT)
7080 return i >= 1*8 && i <= 7*8 && (i & 7) == 0;
7084 extend_reg_operand (op, mode)
7086 enum machine_mode mode;
7088 return (GET_CODE (op) == TRUNCATE
7090 : arith_reg_operand) (op, mode);
7094 trunc_hi_operand (op, mode)
7096 enum machine_mode mode;
7098 enum machine_mode op_mode = GET_MODE (op);
7100 if (op_mode != SImode && op_mode != DImode
7101 && op_mode != V4HImode && op_mode != V2SImode)
7103 return extend_reg_operand (op, mode);
7107 extend_reg_or_0_operand (op, mode)
7109 enum machine_mode mode;
7111 return (GET_CODE (op) == TRUNCATE
7113 : arith_reg_or_0_operand) (op, mode);
7117 general_extend_operand (op, mode)
7119 enum machine_mode mode;
7121 return (GET_CODE (op) == TRUNCATE
7123 : nonimmediate_operand) (op, mode);
7127 inqhi_operand (op, mode)
7129 enum machine_mode mode;
7131 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
7134 /* Can't use true_regnum here because copy_cost wants to know about
7135 SECONDARY_INPUT_RELOAD_CLASS. */
7136 return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
7140 sh_rep_vec (v, mode)
7142 enum machine_mode mode;
7147 if ((GET_CODE (v) != CONST_VECTOR && GET_CODE (v) != PARALLEL)
7148 || (GET_MODE (v) != mode && mode != VOIDmode))
7150 i = XVECLEN (v, 0) - 2;
7151 x = XVECEXP (v, 0, i + 1);
7152 if (GET_MODE_UNIT_SIZE (mode) == 1)
7154 y = XVECEXP (v, 0, i);
7155 for (i -= 2 ; i >= 0; i -= 2)
7156 if (! rtx_equal_p (XVECEXP (v, 0, i + 1), x)
7157 || ! rtx_equal_p (XVECEXP (v, 0, i), y))
7162 if (XVECEXP (v, 0, i) != x)
7167 /* Determine if V is a constant vector matching MODE with only one element
7168 that is not a sign extension. Two byte-sized elements count as one. */
7170 sh_1el_vec (v, mode)
7172 enum machine_mode mode;
7175 int i, last, least, sign_ix;
7178 if (GET_CODE (v) != CONST_VECTOR
7179 || (GET_MODE (v) != mode && mode != VOIDmode))
7181 /* Determine numbers of last and of least significant elements. */
7182 last = XVECLEN (v, 0) - 1;
7183 least = TARGET_LITTLE_ENDIAN ? 0 : last;
7184 if (GET_CODE (XVECEXP (v, 0, least)) != CONST_INT)
7187 if (GET_MODE_UNIT_SIZE (mode) == 1)
7188 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
7189 if (GET_CODE (XVECEXP (v, 0, sign_ix)) != CONST_INT)
7191 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (v));
7192 sign = (INTVAL (XVECEXP (v, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
7193 ? constm1_rtx : const0_rtx);
7194 i = XVECLEN (v, 0) - 1;
7196 if (i != least && i != sign_ix && XVECEXP (v, 0, i) != sign)
7203 sh_const_vec (v, mode)
7205 enum machine_mode mode;
7209 if (GET_CODE (v) != CONST_VECTOR
7210 || (GET_MODE (v) != mode && mode != VOIDmode))
7212 i = XVECLEN (v, 0) - 1;
7214 if (GET_CODE (XVECEXP (v, 0, i)) != CONST_INT)
7219 /* Return the destination address of a branch. */
7222 branch_dest (branch)
7225 rtx dest = SET_SRC (PATTERN (branch));
7228 if (GET_CODE (dest) == IF_THEN_ELSE)
7229 dest = XEXP (dest, 1);
7230 dest = XEXP (dest, 0);
7231 dest_uid = INSN_UID (dest);
7232 return INSN_ADDRESSES (dest_uid);
7235 /* Return nonzero if REG is not used after INSN.
7236 We assume REG is a reload reg, and therefore does
7237 not live past labels. It may live past calls or jumps though. */
7239 reg_unused_after (reg, insn)
7246 /* If the reg is set by this instruction, then it is safe for our
7247 case. Disregard the case where this is a store to memory, since
7248 we are checking a register used in the store address. */
7249 set = single_set (insn);
7250 if (set && GET_CODE (SET_DEST (set)) != MEM
7251 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7254 while ((insn = NEXT_INSN (insn)))
7256 code = GET_CODE (insn);
7259 /* If this is a label that existed before reload, then the register
7260 if dead here. However, if this is a label added by reorg, then
7261 the register may still be live here. We can't tell the difference,
7262 so we just ignore labels completely. */
7263 if (code == CODE_LABEL)
7268 if (code == JUMP_INSN)
7271 /* If this is a sequence, we must handle them all at once.
7272 We could have for instance a call that sets the target register,
7273 and an insn in a delay slot that uses the register. In this case,
7274 we must return 0. */
7275 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
7280 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7282 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
7283 rtx set = single_set (this_insn);
7285 if (GET_CODE (this_insn) == CALL_INSN)
7287 else if (GET_CODE (this_insn) == JUMP_INSN)
7289 if (INSN_ANNULLED_BRANCH_P (this_insn))
7294 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
7296 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7298 if (GET_CODE (SET_DEST (set)) != MEM)
7304 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
7309 else if (code == JUMP_INSN)
7312 else if (GET_RTX_CLASS (code) == 'i')
7314 rtx set = single_set (insn);
7316 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
7318 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7319 return GET_CODE (SET_DEST (set)) != MEM;
7320 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
7324 if (code == CALL_INSN && call_used_regs[REGNO (reg)])
7332 static GTY(()) rtx fpscr_rtx;
7338 fpscr_rtx = gen_rtx (REG, PSImode, FPSCR_REG);
7339 REG_USERVAR_P (fpscr_rtx) = 1;
7340 mark_user_reg (fpscr_rtx);
7342 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
7343 mark_user_reg (fpscr_rtx);
7362 expand_sf_unop (fun, operands)
7363 rtx (*fun) PARAMS ((rtx, rtx, rtx));
7366 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
7370 expand_sf_binop (fun, operands)
7371 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
7374 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
7379 expand_df_unop (fun, operands)
7380 rtx (*fun) PARAMS ((rtx, rtx, rtx));
7383 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
7387 expand_df_binop (fun, operands)
7388 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
7391 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
7395 /* ??? gcc does flow analysis strictly after common subexpression
7396 elimination. As a result, common subexpression elimination fails
7397 when there are some intervening statements setting the same register.
7398 If we did nothing about this, this would hurt the precision switching
7399 for SH4 badly. There is some cse after reload, but it is unable to
7400 undo the extra register pressure from the unused instructions, and
7401 it cannot remove auto-increment loads.
7403 A C code example that shows this flow/cse weakness for (at least) SH
7404 and sparc (as of gcc ss-970706) is this:
7418 So we add another pass before common subexpression elimination, to
7419 remove assignments that are dead due to a following assignment in the
7420 same basic block. */
7423 mark_use (x, reg_set_block)
7424 rtx x, *reg_set_block;
7430 code = GET_CODE (x);
7435 int regno = REGNO (x);
7436 int nregs = (regno < FIRST_PSEUDO_REGISTER
7437 ? HARD_REGNO_NREGS (regno, GET_MODE (x))
7441 reg_set_block[regno + nregs - 1] = 0;
7448 rtx dest = SET_DEST (x);
7450 if (GET_CODE (dest) == SUBREG)
7451 dest = SUBREG_REG (dest);
7452 if (GET_CODE (dest) != REG)
7453 mark_use (dest, reg_set_block);
7454 mark_use (SET_SRC (x), reg_set_block);
7461 const char *fmt = GET_RTX_FORMAT (code);
7463 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7466 mark_use (XEXP (x, i), reg_set_block);
7467 else if (fmt[i] == 'E')
7468 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7469 mark_use (XVECEXP (x, i, j), reg_set_block);
7476 static rtx get_free_reg PARAMS ((HARD_REG_SET));
7478 /* This function returns a register to use to load the address to load
7479 the fpscr from. Currently it always returns r1 or r7, but when we are
7480 able to use pseudo registers after combine, or have a better mechanism
7481 for choosing a register, it should be done here. */
7482 /* REGS_LIVE is the liveness information for the point for which we
7483 need this allocation. In some bare-bones exit blocks, r1 is live at the
7484 start. We can even have all of r0..r3 being live:
7485 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
7486 INSN before which new insns are placed with will clobber the register
7487 we return. If a basic block consists only of setting the return value
7488 register to a pseudo and using that register, the return value is not
7489 live before or after this block, yet we we'll insert our insns right in
7493 get_free_reg (regs_live)
7494 HARD_REG_SET regs_live;
7496 if (! TEST_HARD_REG_BIT (regs_live, 1))
7497 return gen_rtx_REG (Pmode, 1);
7499 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
7500 there shouldn't be anything but a jump before the function end. */
7501 if (! TEST_HARD_REG_BIT (regs_live, 7))
7502 return gen_rtx_REG (Pmode, 7);
7507 /* This function will set the fpscr from memory.
7508 MODE is the mode we are setting it to. */
7510 fpscr_set_from_mem (mode, regs_live)
7512 HARD_REG_SET regs_live;
7514 enum attr_fp_mode fp_mode = mode;
7515 rtx addr_reg = get_free_reg (regs_live);
7517 if (fp_mode == (enum attr_fp_mode) ACTUAL_NORMAL_MODE (FP_MODE))
7518 emit_insn (gen_fpu_switch1 (addr_reg));
7520 emit_insn (gen_fpu_switch0 (addr_reg));
7523 /* Is the given character a logical line separator for the assembler? */
7524 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
7525 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
7529 sh_insn_length_adjustment (insn)
7532 /* Instructions with unfilled delay slots take up an extra two bytes for
7533 the nop in the delay slot. */
7534 if (((GET_CODE (insn) == INSN
7535 && GET_CODE (PATTERN (insn)) != USE
7536 && GET_CODE (PATTERN (insn)) != CLOBBER)
7537 || GET_CODE (insn) == CALL_INSN
7538 || (GET_CODE (insn) == JUMP_INSN
7539 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
7540 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
7541 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
7542 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
7545 /* SH2e has a bug that prevents the use of annulled branches, so if
7546 the delay slot is not filled, we'll have to put a NOP in it. */
7547 if (sh_cpu == CPU_SH2E
7548 && GET_CODE (insn) == JUMP_INSN
7549 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
7550 && GET_CODE (PATTERN (insn)) != ADDR_VEC
7551 && get_attr_type (insn) == TYPE_CBRANCH
7552 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
7555 /* sh-dsp parallel processing insn take four bytes instead of two. */
7557 if (GET_CODE (insn) == INSN)
7560 rtx body = PATTERN (insn);
7561 const char *template;
7563 int maybe_label = 1;
7565 if (GET_CODE (body) == ASM_INPUT)
7566 template = XSTR (body, 0);
7567 else if (asm_noperands (body) >= 0)
7569 = decode_asm_operands (body, NULL, NULL, NULL, NULL);
7578 while (c == ' ' || c == '\t');
7579 /* all sh-dsp parallel-processing insns start with p.
7580 The only non-ppi sh insn starting with p is pref.
7581 The only ppi starting with pr is prnd. */
7582 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
7584 /* The repeat pseudo-insn expands two three insns, a total of
7585 six bytes in size. */
7586 else if ((c == 'r' || c == 'R')
7587 && ! strncasecmp ("epeat", template, 5))
7589 while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c))
7591 /* If this is a label, it is obviously not a ppi insn. */
7592 if (c == ':' && maybe_label)
7597 else if (c == '\'' || c == '"')
7602 maybe_label = c != ':';
7610 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
7611 isn't protected by a PIC unspec. */
7613 nonpic_symbol_mentioned_p (x)
7616 register const char *fmt;
7619 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
7620 || GET_CODE (x) == PC)
7623 /* We don't want to look into the possible MEM location of a
7624 CONST_DOUBLE, since we're not going to use it, in general. */
7625 if (GET_CODE (x) == CONST_DOUBLE)
7628 if (GET_CODE (x) == UNSPEC
7629 && (XINT (x, 1) == UNSPEC_PIC
7630 || XINT (x, 1) == UNSPEC_GOT
7631 || XINT (x, 1) == UNSPEC_GOTOFF
7632 || XINT (x, 1) == UNSPEC_GOTPLT
7633 || XINT (x, 1) == UNSPEC_GOTTPOFF
7634 || XINT (x, 1) == UNSPEC_DTPOFF
7635 || XINT (x, 1) == UNSPEC_PLT))
7638 fmt = GET_RTX_FORMAT (GET_CODE (x));
7639 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
7645 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7646 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
7649 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
7656 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
7657 @GOTOFF in `reg'. */
7659 legitimize_pic_address (orig, mode, reg)
7661 enum machine_mode mode ATTRIBUTE_UNUSED;
7664 if (tls_symbolic_operand (orig, Pmode))
7667 if (GET_CODE (orig) == LABEL_REF
7668 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
7671 reg = gen_reg_rtx (Pmode);
7673 emit_insn (gen_symGOTOFF2reg (reg, orig));
7676 else if (GET_CODE (orig) == SYMBOL_REF)
7679 reg = gen_reg_rtx (Pmode);
7681 emit_insn (gen_symGOT2reg (reg, orig));
7687 /* Mark the use of a constant in the literal table. If the constant
7688 has multiple labels, make it unique. */
7690 mark_constant_pool_use (x)
7693 rtx insn, lab, pattern;
7698 switch (GET_CODE (x))
7708 /* Get the first label in the list of labels for the same constant
7709 and delete another labels in the list. */
7711 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
7713 if (GET_CODE (insn) != CODE_LABEL
7714 || LABEL_REFS (insn) != NEXT_INSN (insn))
7719 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
7720 INSN_DELETED_P (insn) = 1;
7722 /* Mark constants in a window. */
7723 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
7725 if (GET_CODE (insn) != INSN)
7728 pattern = PATTERN (insn);
7729 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
7732 switch (XINT (pattern, 1))
7734 case UNSPECV_CONST2:
7735 case UNSPECV_CONST4:
7736 case UNSPECV_CONST8:
7737 XVECEXP (pattern, 0, 1) = const1_rtx;
7739 case UNSPECV_WINDOW_END:
7740 if (XVECEXP (pattern, 0, 0) == x)
7743 case UNSPECV_CONST_END:
7753 /* Return true if it's possible to redirect BRANCH1 to the destination
7754 of an unconditional jump BRANCH2. We only want to do this if the
7755 resulting branch will have a short displacement. */
7757 sh_can_redirect_branch (branch1, branch2)
7761 if (flag_expensive_optimizations && simplejump_p (branch2))
7763 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
7767 for (distance = 0, insn = NEXT_INSN (branch1);
7768 insn && distance < 256;
7769 insn = PREV_INSN (insn))
7774 distance += get_attr_length (insn);
7776 for (distance = 0, insn = NEXT_INSN (branch1);
7777 insn && distance < 256;
7778 insn = NEXT_INSN (insn))
7783 distance += get_attr_length (insn);
7789 /* Return nonzero if register old_reg can be renamed to register new_reg. */
7791 sh_hard_regno_rename_ok (old_reg, new_reg)
7792 unsigned int old_reg ATTRIBUTE_UNUSED;
7793 unsigned int new_reg;
7796 /* Interrupt functions can only use registers that have already been
7797 saved by the prologue, even if they would normally be
7800 if (sh_cfun_interrupt_handler_p () && !regs_ever_live[new_reg])
7806 /* Function to update the integer COST
7807 based on the relationship between INSN that is dependent on
7808 DEP_INSN through the dependence LINK. The default is to make no
7809 adjustment to COST. This can be used for example to specify to
7810 the scheduler that an output- or anti-dependence does not incur
7811 the same cost as a data-dependence. The return value should be
7812 the new value for COST. */
7814 sh_adjust_cost (insn, link, dep_insn, cost)
7816 rtx link ATTRIBUTE_UNUSED;
7824 /* On SHmedia, if the dependence is an anti-dependence or
7825 output-dependence, there is no cost. */
7826 if (REG_NOTE_KIND (link) != 0)
7829 if (get_attr_is_mac_media (insn)
7830 && get_attr_is_mac_media (dep_insn))
7833 else if (REG_NOTE_KIND (link) == 0)
7835 enum attr_type dep_type, type;
7837 if (recog_memoized (insn) < 0
7838 || recog_memoized (dep_insn) < 0)
7841 dep_type = get_attr_type (dep_insn);
7842 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
7844 if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
7845 && (type = get_attr_type (insn)) != TYPE_CALL
7846 && type != TYPE_SFUNC)
7849 /* The only input for a call that is timing-critical is the
7850 function's address. */
7851 if (GET_CODE(insn) == CALL_INSN)
7853 rtx call = PATTERN (insn);
7855 if (GET_CODE (call) == PARALLEL)
7856 call = XVECEXP (call, 0 ,0);
7857 if (GET_CODE (call) == SET)
7858 call = SET_SRC (call);
7859 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
7860 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))
7863 /* Likewise, the most timing critical input for an sfuncs call
7864 is the function address. However, sfuncs typically start
7865 using their arguments pretty quickly.
7866 Assume a four cycle delay before they are needed. */
7867 /* All sfunc calls are parallels with at least four components.
7868 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
7869 else if (GET_CODE (PATTERN (insn)) == PARALLEL
7870 && XVECLEN (PATTERN (insn), 0) >= 4
7871 && (reg = sfunc_uses_reg (insn)))
7873 if (! reg_set_p (reg, dep_insn))
7876 /* When the preceding instruction loads the shift amount of
7877 the following SHAD/SHLD, the latency of the load is increased
7880 && get_attr_type (insn) == TYPE_DYN_SHIFT
7881 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
7882 && reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
7883 XEXP (SET_SRC (single_set(insn)),
7886 /* When an LS group instruction with a latency of less than
7887 3 cycles is followed by a double-precision floating-point
7888 instruction, FIPR, or FTRV, the latency of the first
7889 instruction is increased to 3 cycles. */
7891 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
7892 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
7894 /* The lsw register of a double-precision computation is ready one
7896 else if (reload_completed
7897 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
7898 && (use_pat = single_set (insn))
7899 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
7903 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
7904 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
7907 /* An anti-dependence penalty of two applies if the first insn is a double
7908 precision fadd / fsub / fmul. */
7909 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI
7910 && recog_memoized (dep_insn) >= 0
7911 && get_attr_type (dep_insn) == TYPE_DFP_ARITH
7912 /* A lot of alleged anti-flow dependences are fake,
7913 so check this one is real. */
7914 && flow_dependent_p (dep_insn, insn))
7921 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
7922 if DEP_INSN is anti-flow dependent on INSN. */
7924 flow_dependent_p (insn, dep_insn)
7927 rtx tmp = PATTERN (insn);
7929 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
7930 return tmp == NULL_RTX;
7933 /* A helper function for flow_dependent_p called through note_stores. */
7935 flow_dependent_p_1 (x, pat, data)
7937 rtx pat ATTRIBUTE_UNUSED;
7940 rtx * pinsn = (rtx *) data;
7942 if (*pinsn && reg_referenced_p (x, *pinsn))
7946 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
7947 'special function' patterns (type sfunc) that clobber pr, but that
7948 do not look like function calls to leaf_function_p. Hence we must
7949 do this extra check. */
7953 return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
7956 /* This Function returns nonzero if the DFA based scheduler interface
7957 is to be used. At present this is supported for the SH4 only. */
7959 sh_use_dfa_interface()
7961 if (TARGET_HARD_SH4)
7967 /* This function returns "2" to indicate dual issue for the SH4
7968 processor. To be used by the DFA pipeline description. */
7972 if (TARGET_SUPERSCALAR)
7978 /* SHmedia requires registers for branches, so we can't generate new
7979 branches past reload. */
7981 sh_cannot_modify_jumps_p ()
7983 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
7987 sh_target_reg_class (void)
7989 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
7993 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
7995 return (shmedia_space_reserved_for_target_registers
7996 && (! after_prologue_epilogue_gen || TARGET_SAVE_ALL_TARGET_REGS));
8000 sh_ms_bitfield_layout_p (record_type)
8001 tree record_type ATTRIBUTE_UNUSED;
8007 On the SH1..SH4, the trampoline looks like
8008 2 0002 D202 mov.l l2,r2
8009 1 0000 D301 mov.l l1,r3
8012 5 0008 00000000 l1: .long area
8013 6 000c 00000000 l2: .long function
8015 SH5 (compact) uses r1 instead of r3 for the static chain. */
8018 /* Emit RTL insns to initialize the variable parts of a trampoline.
8019 FNADDR is an RTX for the address of the function's pure code.
8020 CXT is an RTX for the static chain value for the function. */
8023 sh_initialize_trampoline (tramp, fnaddr, cxt)
8024 rtx tramp, fnaddr, cxt;
8026 if (TARGET_SHMEDIA64)
8031 rtx movi1 = GEN_INT (0xcc000010);
8032 rtx shori1 = GEN_INT (0xc8000010);
8035 /* The following trampoline works within a +- 128 KB range for cxt:
8036 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
8037 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
8038 gettr tr1,r1; blink tr0,r63 */
8039 /* Address rounding makes it hard to compute the exact bounds of the
8040 offset for this trampoline, but we have a rather generous offset
8041 range, so frame_offset should do fine as an upper bound. */
8042 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
8044 /* ??? could optimize this trampoline initialization
8045 by writing DImode words with two insns each. */
8046 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
8047 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
8048 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
8049 insn = gen_rtx_AND (DImode, insn, mask);
8050 /* Or in ptb/u .,tr1 pattern */
8051 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
8052 insn = force_operand (insn, NULL_RTX);
8053 insn = gen_lowpart (SImode, insn);
8054 emit_move_insn (gen_rtx_MEM (SImode, tramp), insn);
8055 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
8056 insn = gen_rtx_AND (DImode, insn, mask);
8057 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
8058 insn = gen_lowpart (SImode, insn);
8059 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), insn);
8060 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
8061 insn = gen_rtx_AND (DImode, insn, mask);
8062 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8063 insn = gen_lowpart (SImode, insn);
8064 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), insn);
8065 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
8066 insn = gen_rtx_AND (DImode, insn, mask);
8067 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8068 insn = gen_lowpart (SImode, insn);
8069 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
8071 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
8072 insn = gen_rtx_AND (DImode, insn, mask);
8073 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8074 insn = gen_lowpart (SImode, insn);
8075 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 16)),
8077 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 20)),
8078 GEN_INT (0x6bf10600));
8079 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 24)),
8080 GEN_INT (0x4415fc10));
8081 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 28)),
8082 GEN_INT (0x4401fff0));
8083 emit_insn (gen_ic_invalidate_line (tramp));
8086 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
8087 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
8089 tramp_templ = gen_datalabel_ref (tramp_templ);
8090 dst = gen_rtx_MEM (BLKmode, tramp);
8091 src = gen_rtx_MEM (BLKmode, tramp_templ);
8092 set_mem_align (dst, 256);
8093 set_mem_align (src, 64);
8094 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
8096 emit_move_insn (gen_rtx_MEM (Pmode, plus_constant (tramp, fixed_len)),
8098 emit_move_insn (gen_rtx_MEM (Pmode,
8099 plus_constant (tramp,
8101 + GET_MODE_SIZE (Pmode))),
8103 emit_insn (gen_ic_invalidate_line (tramp));
8106 else if (TARGET_SHMEDIA)
8108 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
8109 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
8110 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
8111 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
8112 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
8113 rotated 10 right, and higher 16 bit of every 32 selected. */
8115 = force_reg (V2HImode, (simplify_gen_subreg
8116 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
8117 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
8118 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
8120 tramp = force_reg (Pmode, tramp);
8121 fnaddr = force_reg (SImode, fnaddr);
8122 cxt = force_reg (SImode, cxt);
8123 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
8124 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
8126 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
8127 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
8128 emit_insn (gen_ashldi3_media (quad0, quad0, GEN_INT (2)));
8129 emit_move_insn (gen_rtx_MEM (DImode, tramp), quad0);
8130 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
8131 gen_rtx_SUBREG (V2HImode, cxt, 0),
8133 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
8134 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
8135 emit_insn (gen_ashldi3_media (cxtload, cxtload, GEN_INT (2)));
8136 if (TARGET_LITTLE_ENDIAN)
8138 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
8139 emit_insn (gen_mextr4 (quad2, cxtload, blink));
8143 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
8144 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
8146 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 8)), quad1);
8147 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), quad2);
8148 emit_insn (gen_ic_invalidate_line (tramp));
8151 else if (TARGET_SHCOMPACT)
8153 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
8156 emit_move_insn (gen_rtx_MEM (SImode, tramp),
8157 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
8159 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
8160 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
8162 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
8164 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
8168 if (TARGET_USERMODE)
8169 emit_library_call (function_symbol ("__ic_invalidate"),
8170 0, VOIDmode, 1, tramp, SImode);
8172 emit_insn (gen_ic_invalidate_line (tramp));
8176 /* FIXME: This is overly conservative. A SHcompact function that
8177 receives arguments ``by reference'' will have them stored in its
8178 own stack frame, so it must not pass pointers or references to
8179 these arguments to other functions by means of sibling calls. */
8181 sh_function_ok_for_sibcall (decl, exp)
8183 tree exp ATTRIBUTE_UNUSED;
8186 && (! TARGET_SHCOMPACT
8187 || current_function_args_info.stack_regs == 0)
8188 && ! sh_cfun_interrupt_handler_p ());
8191 /* Machine specific built-in functions. */
8193 struct builtin_description
8195 const enum insn_code icode;
8196 const char *const name;
8200 /* describe number and signedness of arguments; arg[0] == result
8201 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
8202 static const char signature_args[][4] =
8204 #define SH_BLTIN_V2SI2 0
8206 #define SH_BLTIN_V4HI2 1
8208 #define SH_BLTIN_V2SI3 2
8210 #define SH_BLTIN_V4HI3 3
8212 #define SH_BLTIN_V8QI3 4
8214 #define SH_BLTIN_MAC_HISI 5
8216 #define SH_BLTIN_SH_HI 6
8218 #define SH_BLTIN_SH_SI 7
8220 #define SH_BLTIN_V4HI2V2SI 8
8222 #define SH_BLTIN_V4HI2V8QI 9
8224 #define SH_BLTIN_SISF 10
8226 #define SH_BLTIN_LDUA_L 11
8228 #define SH_BLTIN_LDUA_Q 12
8230 #define SH_BLTIN_STUA_L 13
8232 #define SH_BLTIN_STUA_Q 14
8234 #define SH_BLTIN_UDI 15
8236 #define SH_BLTIN_NUM_SHARED_SIGNATURES 16
8237 #define SH_BLTIN_2 16
8238 #define SH_BLTIN_SU 16
8240 #define SH_BLTIN_3 17
8241 #define SH_BLTIN_SUS 17
8243 #define SH_BLTIN_PSSV 18
8245 #define SH_BLTIN_XXUU 19
8246 #define SH_BLTIN_UUUU 19
8248 #define SH_BLTIN_PV 20
8251 /* mcmv: operands considered unsigned. */
8252 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
8253 /* mperm: control value considered unsigned int. */
8254 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
8255 /* mshards_q: returns signed short. */
8256 /* nsb: takes long long arg, returns unsigned char. */
8257 static const struct builtin_description bdesc[] =
8259 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
8260 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
8261 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
8262 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
8263 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
8264 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
8265 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
8267 { CODE_FOR_alloco32, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
8268 { CODE_FOR_alloco64, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
8270 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
8271 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
8272 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
8273 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
8274 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
8275 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
8276 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
8277 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
8278 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
8279 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
8280 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI },
8281 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI },
8282 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI },
8283 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI },
8284 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI },
8285 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI },
8286 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI },
8287 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
8288 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
8289 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
8290 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
8291 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
8292 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
8293 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
8294 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
8295 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
8296 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
8297 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
8298 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
8299 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
8300 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
8301 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
8302 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
8303 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
8304 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
8305 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
8306 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
8307 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
8308 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
8309 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
8310 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
8311 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
8312 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
8313 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
8314 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
8315 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
8316 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
8317 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
8318 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
8319 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
8320 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
8321 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
8322 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
8323 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
8325 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
8326 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
8327 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
8328 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
8329 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
8330 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
8331 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
8332 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
8333 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
8334 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
8335 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
8336 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
8337 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
8338 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
8339 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
8340 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
8342 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
8343 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
8345 { CODE_FOR_prefetch32,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
8346 { CODE_FOR_prefetch64,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV }
8351 sh_media_init_builtins ()
8353 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
8354 const struct builtin_description *d;
8356 memset (shared, 0, sizeof shared);
8357 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
8359 tree type, arg_type;
8360 int signature = d->signature;
8363 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
8364 type = shared[signature];
8367 int has_result = signature_args[signature][0] != 0;
8369 if (signature_args[signature][1] == 8
8370 && (insn_data[d->icode].operand[has_result].mode != Pmode))
8372 if (! TARGET_FPU_ANY
8373 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
8375 type = void_list_node;
8378 int arg = signature_args[signature][i];
8379 int opno = i - 1 + has_result;
8382 arg_type = ptr_type_node;
8384 arg_type = ((*lang_hooks.types.type_for_mode)
8385 (insn_data[d->icode].operand[opno].mode,
8390 arg_type = void_type_node;
8393 type = tree_cons (NULL_TREE, arg_type, type);
8395 type = build_function_type (arg_type, type);
8396 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
8397 shared[signature] = type;
8399 builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
8408 sh_media_init_builtins ();
8411 /* Expand an expression EXP that calls a built-in function,
8412 with result going to TARGET if that's convenient
8413 (and in mode MODE if that's convenient).
8414 SUBTARGET may be used as the target for computing one of EXP's operands.
8415 IGNORE is nonzero if the value is to be ignored. */
8418 sh_expand_builtin (exp, target, subtarget, mode, ignore)
8421 rtx subtarget ATTRIBUTE_UNUSED;
8422 enum machine_mode mode ATTRIBUTE_UNUSED;
8425 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8426 tree arglist = TREE_OPERAND (exp, 1);
8427 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8428 const struct builtin_description *d = &bdesc[fcode];
8429 enum insn_code icode = d->icode;
8430 int signature = d->signature;
8431 enum machine_mode tmode = VOIDmode;
8436 if (signature_args[signature][0])
8441 tmode = insn_data[icode].operand[0].mode;
8443 || GET_MODE (target) != tmode
8444 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8445 target = gen_reg_rtx (tmode);
8451 for (i = 1; i <= 3; i++, nop++)
8454 enum machine_mode opmode, argmode;
8456 if (! signature_args[signature][i])
8458 arg = TREE_VALUE (arglist);
8459 if (arg == error_mark_node)
8461 arglist = TREE_CHAIN (arglist);
8462 opmode = insn_data[icode].operand[nop].mode;
8463 argmode = TYPE_MODE (TREE_TYPE (arg));
8464 if (argmode != opmode)
8465 arg = build1 (NOP_EXPR,
8466 (*lang_hooks.types.type_for_mode) (opmode, 0), arg);
8467 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
8468 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
8469 op[nop] = copy_to_mode_reg (opmode, op[nop]);
8475 pat = (*insn_data[d->icode].genfun) (op[0]);
8478 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
8481 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
8484 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
8496 sh_expand_unop_v2sf (code, op0, op1)
8500 rtx sel0 = const0_rtx;
8501 rtx sel1 = const1_rtx;
8502 rtx (*fn) PARAMS ((rtx, rtx, rtx, rtx, rtx)) = gen_unary_sf_op;
8503 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
8505 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
8506 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
8510 sh_expand_binop_v2sf (code, op0, op1, op2)
8514 rtx sel0 = const0_rtx;
8515 rtx sel1 = const1_rtx;
8516 rtx (*fn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx))
8518 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
8520 emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0, sel1));
8521 emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1, sel0));
8524 /* Return the class of registers for which a mode change from FROM to TO
8527 sh_cannot_change_mode_class (from, to, class)
8528 enum machine_mode from, to;
8529 enum reg_class class;
8531 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
8533 if (TARGET_LITTLE_ENDIAN)
8535 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
8536 return reg_classes_intersect_p (DF_REGS, class);
8540 if (GET_MODE_SIZE (from) < 8)
8541 return reg_classes_intersect_p (DF_HI_REGS, class);
8548 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
8549 that label is used. */
8552 sh_mark_label (address, nuses)
8556 if (GOTOFF_P (address))
8558 /* Extract the label or symbol. */
8559 address = XEXP (address, 0);
8560 if (GET_CODE (address) == PLUS)
8561 address = XEXP (address, 0);
8562 address = XVECEXP (address, 0, 0);
8564 if (GET_CODE (address) == LABEL_REF
8565 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
8566 LABEL_NUSES (XEXP (address, 0)) += nuses;
8569 /* Compute extra cost of moving data between one register class
8572 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
8573 uses this information. Hence, the general register <-> floating point
8574 register information here is not used for SFmode. */
8577 sh_register_move_cost (mode, srcclass, dstclass)
8578 enum machine_mode mode;
8579 enum reg_class srcclass, dstclass;
8581 if (dstclass == T_REGS || dstclass == PR_REGS)
8584 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
8587 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
8588 && REGCLASS_HAS_FP_REG (srcclass)
8589 && REGCLASS_HAS_FP_REG (dstclass))
8592 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
8593 || (dstclass== MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
8596 if ((REGCLASS_HAS_FP_REG (dstclass)
8597 && REGCLASS_HAS_GENERAL_REG (srcclass))
8598 || (REGCLASS_HAS_GENERAL_REG (dstclass)
8599 && REGCLASS_HAS_FP_REG (srcclass)))
8600 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
8601 * ((GET_MODE_SIZE (mode) + 7) / 8U));
8603 if ((dstclass == FPUL_REGS
8604 && REGCLASS_HAS_GENERAL_REG (srcclass))
8605 || (srcclass == FPUL_REGS
8606 && REGCLASS_HAS_GENERAL_REG (dstclass)))
8609 if ((dstclass == FPUL_REGS
8610 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
8611 || (srcclass == FPUL_REGS
8612 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
8615 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
8616 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
8619 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
8620 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
8625 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
8626 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
8627 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
8629 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
8632 /* Like register_operand, but take into account that SHMEDIA can use
8633 the constant zero like a general register. */
8635 sh_register_operand (op, mode)
8637 enum machine_mode mode;
8639 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
8641 return register_operand (op, mode);
8644 static rtx emit_load_ptr PARAMS ((rtx, rtx));
8647 emit_load_ptr (reg, addr)
8650 rtx mem = gen_rtx_MEM (ptr_mode, addr);
8652 if (Pmode != ptr_mode)
8653 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
8654 return emit_move_insn (reg, mem);
8658 sh_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
8660 tree thunk_fndecl ATTRIBUTE_UNUSED;
8661 HOST_WIDE_INT delta;
8662 HOST_WIDE_INT vcall_offset;
8665 CUMULATIVE_ARGS cum;
8666 int structure_value_byref = 0;
8667 rtx this, this_value, sibcall, insns, funexp;
8668 tree funtype = TREE_TYPE (function);
8669 int simple_add = CONST_OK_FOR_ADD (delta);
8671 rtx scratch0, scratch1, scratch2;
8673 reload_completed = 1;
8674 epilogue_completed = 1;
8676 current_function_uses_only_leaf_regs = 1;
8678 emit_note (NOTE_INSN_PROLOGUE_END);
8680 /* Find the "this" pointer. We have such a wide range of ABIs for the
8681 SH that it's best to do this completely machine independently.
8682 "this" is passed as first argument, unless a structure return pointer
8683 comes first, in which case "this" comes second. */
8684 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0);
8685 #ifndef PCC_STATIC_STRUCT_RETURN
8686 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
8687 structure_value_byref = 1;
8688 #endif /* not PCC_STATIC_STRUCT_RETURN */
8689 if (structure_value_byref && struct_value_rtx == 0)
8691 tree ptype = build_pointer_type (TREE_TYPE (funtype));
8693 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
8695 this = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
8697 /* For SHcompact, we only have r0 for a scratch register: r1 is the
8698 static chain pointer (even if you can't have nested virtual functions
8699 right now, someone might implement them sometime), and the rest of the
8700 registers are used for argument passing, are callee-saved, or reserved. */
8701 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
8704 scratch1 = gen_rtx_REG (ptr_mode, 1);
8705 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
8706 pointing where to return struct values. */
8707 scratch2 = gen_rtx_REG (Pmode, 3);
8709 else if (TARGET_SHMEDIA)
8711 scratch1 = gen_rtx_REG (ptr_mode, 21);
8712 scratch2 = gen_rtx_REG (Pmode, TR0_REG);
8715 this_value = plus_constant (this, delta);
8717 && (simple_add || scratch0 != scratch1)
8718 && strict_memory_address_p (ptr_mode, this_value))
8720 emit_load_ptr (scratch0, this_value);
8726 else if (simple_add)
8727 emit_move_insn (this, this_value);
8730 emit_move_insn (scratch1, GEN_INT (delta));
8731 emit_insn (gen_add2_insn (this, scratch1));
8739 emit_load_ptr (scratch0, this);
8741 offset_addr = plus_constant (scratch0, vcall_offset);
8742 if (strict_memory_address_p (ptr_mode, offset_addr))
8744 else if (! TARGET_SH5)
8746 /* scratch0 != scratch1, and we have indexed loads. Get better
8747 schedule by loading the offset into r1 and using an indexed
8748 load - then the load of r1 can issue before the load from
8749 (this + delta) finishes. */
8750 emit_move_insn (scratch1, GEN_INT (vcall_offset));
8751 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
8753 else if (CONST_OK_FOR_ADD (vcall_offset))
8755 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
8756 offset_addr = scratch0;
8758 else if (scratch0 != scratch1)
8760 emit_move_insn (scratch1, GEN_INT (vcall_offset));
8761 emit_insn (gen_add2_insn (scratch0, scratch1));
8762 offset_addr = scratch0;
8765 abort (); /* FIXME */
8766 emit_load_ptr (scratch0, offset_addr);
8768 if (Pmode != ptr_mode)
8769 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
8770 emit_insn (gen_add2_insn (this, scratch0));
8773 /* Generate a tail call to the target function. */
8774 if (! TREE_USED (function))
8776 assemble_external (function);
8777 TREE_USED (function) = 1;
8779 funexp = XEXP (DECL_RTL (function), 0);
8780 emit_move_insn (scratch2, funexp);
8781 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
8782 sibcall = emit_call_insn (gen_sibcall (funexp, const0_rtx, NULL_RTX));
8783 SIBLING_CALL_P (sibcall) = 1;
8784 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this);
8787 /* Run just enough of rest_of_compilation to do scheduling and get
8788 the insns emitted. Note that use_thunk calls
8789 assemble_start_function and assemble_end_function. */
8791 insn_locators_initialize ();
8792 insns = get_insns ();
8794 if (optimize > 0 && flag_schedule_insns_after_reload)
8797 find_basic_blocks (insns, max_reg_num (), rtl_dump_file);
8798 life_analysis (insns, rtl_dump_file, PROP_FINAL);
8800 split_all_insns (1);
8802 schedule_insns (rtl_dump_file);
8807 if (optimize > 0 && flag_delayed_branch)
8808 dbr_schedule (insns, rtl_dump_file);
8809 shorten_branches (insns);
8810 final_start_function (insns, file, 1);
8811 final (insns, file, 1, 0);
8812 final_end_function ();
8814 if (optimize > 0 && flag_schedule_insns_after_reload)
8816 /* Release all memory allocated by flow. */
8817 free_basic_block_vars (0);
8819 /* Release all memory held by regsets now. */
8820 regset_release_memory ();
8823 reload_completed = 0;
8824 epilogue_completed = 0;
8829 function_symbol (const char *name)
8831 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
8832 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
8836 /* Find the number of a general purpose register in S. */
8838 scavenge_reg (HARD_REG_SET *s)
8841 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
8842 if (TEST_HARD_REG_BIT (*s, r))
8848 sh_get_pr_initial_val (void)
8852 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
8853 PR register on SHcompact, because it might be clobbered by the prologue.
8854 We check first if that is known to be the case. */
8855 if (TARGET_SHCOMPACT
8856 && ((current_function_args_info.call_cookie
8857 & ~ CALL_COOKIE_RET_TRAMP (1))
8858 || current_function_has_nonlocal_label))
8859 return gen_rtx_MEM (SImode, return_address_pointer_rtx);
8861 /* If we haven't finished rtl generation, there might be a nonlocal label
8862 that we haven't seen yet.
8863 ??? get_hard_reg_initial_val fails if it is called while no_new_pseudos
8864 is set, unless it has been called before for the same register. And even
8865 then, we end in trouble if we didn't use the register in the same
8866 basic block before. So call get_hard_reg_initial_val now and wrap it
8867 in an unspec if we might need to replace it. */
8868 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
8869 combine can put the pseudo returned by get_hard_reg_initial_val into
8870 instructions that need a general purpose registers, which will fail to
8871 be recognized when the pseudo becomes allocated to PR. */
8873 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
8875 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);