1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "insn-config.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
40 #include "integrate.h"
44 #include "target-def.h"
46 #include "langhooks.h"
47 #include "basic-block.h"
49 #include "cfglayout.h"
51 #include "sched-int.h"
56 #include "alloc-pool.h"
57 #include "tm-constrs.h"
60 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
62 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
63 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
65 /* These are some macros to abstract register modes. */
66 #define CONST_OK_FOR_ADD(size) \
67 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
68 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
69 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
70 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
72 /* Used to simplify the logic below. Find the attributes wherever
74 #define SH_ATTRIBUTES(decl) \
75 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
76 : DECL_ATTRIBUTES (decl) \
77 ? (DECL_ATTRIBUTES (decl)) \
78 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
80 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
81 int current_function_interrupt;
83 tree sh_deferred_function_attributes;
84 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
86 /* Global variables for machine-dependent things. */
88 /* Which cpu are we scheduling for. */
89 enum processor_type sh_cpu;
91 /* Definitions used in ready queue reordering for first scheduling pass. */
93 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
94 static short *regmode_weight[2];
96 /* Total SFmode and SImode weights of scheduled insns. */
97 static int curr_regmode_pressure[2];
99 /* Number of r0 life regions. */
100 static int r0_life_regions;
102 /* If true, skip cycles for Q -> R movement. */
103 static int skip_cycles = 0;
105 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
106 and returned from sh_reorder2. */
107 static short cached_can_issue_more;
109 /* Provides the class number of the smallest class containing
112 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
114 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
147 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
148 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
149 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
150 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
151 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
152 GENERAL_REGS, GENERAL_REGS,
155 char sh_register_names[FIRST_PSEUDO_REGISTER] \
156 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
158 char sh_additional_register_names[ADDREGNAMES_SIZE] \
159 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
160 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
162 int assembler_dialect;
164 static bool shmedia_space_reserved_for_target_registers;
166 static bool sh_handle_option (size_t, const char *, int);
167 static void split_branches (rtx);
168 static int branch_dest (rtx);
169 static void force_into (rtx, rtx);
170 static void print_slot (rtx);
171 static rtx add_constant (rtx, enum machine_mode, rtx);
172 static void dump_table (rtx, rtx);
173 static int hi_const (rtx);
174 static int broken_move (rtx);
175 static int mova_p (rtx);
176 static rtx find_barrier (int, rtx, rtx);
177 static int noncall_uses_reg (rtx, rtx, rtx *);
178 static rtx gen_block_redirect (rtx, int, int);
179 static void sh_reorg (void);
180 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *, bool);
181 static rtx frame_insn (rtx);
182 static rtx push (int);
183 static void pop (int);
184 static void push_regs (HARD_REG_SET *, int);
185 static int calc_live_regs (HARD_REG_SET *);
186 static HOST_WIDE_INT rounded_frame_size (int);
187 static rtx mark_constant_pool_use (rtx);
188 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
189 static tree sh_handle_resbank_handler_attribute (tree *, tree,
191 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
193 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
194 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
195 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
196 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
197 static void sh_insert_attributes (tree, tree *);
198 static const char *sh_check_pch_target_flags (int);
199 static int sh_adjust_cost (rtx, rtx, rtx, int);
200 static int sh_issue_rate (void);
201 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
202 static short find_set_regmode_weight (rtx, enum machine_mode);
203 static short find_insn_regmode_weight (rtx, enum machine_mode);
204 static void find_regmode_weight (basic_block, enum machine_mode);
205 static int find_r0_life_regions (basic_block);
206 static void sh_md_init_global (FILE *, int, int);
207 static void sh_md_finish_global (FILE *, int);
208 static int rank_for_reorder (const void *, const void *);
209 static void swap_reorder (rtx *, int);
210 static void ready_reorder (rtx *, int);
211 static short high_pressure (enum machine_mode);
212 static int sh_reorder (FILE *, int, rtx *, int *, int);
213 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
214 static void sh_md_init (FILE *, int, int);
215 static int sh_variable_issue (FILE *, int, rtx, int);
217 static bool sh_function_ok_for_sibcall (tree, tree);
219 static bool sh_cannot_modify_jumps_p (void);
220 static enum reg_class sh_target_reg_class (void);
221 static bool sh_optimize_target_register_callee_saved (bool);
222 static bool sh_ms_bitfield_layout_p (const_tree);
224 static void sh_init_builtins (void);
225 static void sh_media_init_builtins (void);
226 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
227 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
228 static void sh_file_start (void);
229 static int flow_dependent_p (rtx, rtx);
230 static void flow_dependent_p_1 (rtx, const_rtx, void *);
231 static int shiftcosts (rtx);
232 static int andcosts (rtx);
233 static int addsubcosts (rtx);
234 static int multcosts (rtx);
235 static bool unspec_caller_rtx_p (rtx);
236 static bool sh_cannot_copy_insn_p (rtx);
237 static bool sh_rtx_costs (rtx, int, int, int *, bool);
238 static int sh_address_cost (rtx, bool);
239 static int sh_pr_n_sets (void);
240 static rtx sh_allocate_initial_value (rtx);
241 static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
242 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
243 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
244 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
245 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
246 static int scavenge_reg (HARD_REG_SET *s);
247 struct save_schedule_s;
248 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
249 struct save_schedule_s *, int);
251 static rtx sh_struct_value_rtx (tree, int);
252 static bool sh_return_in_memory (const_tree, const_tree);
253 static rtx sh_builtin_saveregs (void);
254 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
255 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
256 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
257 static tree sh_build_builtin_va_list (void);
258 static void sh_va_start (tree, rtx);
259 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
260 static enum machine_mode sh_promote_function_mode (const_tree type,
265 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
267 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
269 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
271 static bool sh_scalar_mode_supported_p (enum machine_mode);
272 static int sh_dwarf_calling_convention (const_tree);
273 static void sh_encode_section_info (tree, rtx, int);
274 static int sh2a_function_vector_p (tree);
275 static void sh_trampoline_init (rtx, tree, rtx);
276 static rtx sh_trampoline_adjust_address (rtx);
278 static const struct attribute_spec sh_attribute_table[] =
280 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
281 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
282 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
283 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
284 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
285 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
286 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
287 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
288 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
290 /* Symbian support adds three new attributes:
291 dllexport - for exporting a function/variable that will live in a dll
292 dllimport - for importing a function/variable from a dll
294 Microsoft allows multiple declspecs in one __declspec, separating
295 them with spaces. We do NOT support this. Instead, use __declspec
297 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
298 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
300 { NULL, 0, 0, false, false, false, NULL }
303 /* Initialize the GCC target structure. */
304 #undef TARGET_ATTRIBUTE_TABLE
305 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
307 /* The next two are used for debug info when compiling with -gdwarf. */
308 #undef TARGET_ASM_UNALIGNED_HI_OP
309 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
310 #undef TARGET_ASM_UNALIGNED_SI_OP
311 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
313 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
314 #undef TARGET_ASM_UNALIGNED_DI_OP
315 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
316 #undef TARGET_ASM_ALIGNED_DI_OP
317 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
319 #undef TARGET_ASM_FUNCTION_EPILOGUE
320 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
322 #undef TARGET_ASM_OUTPUT_MI_THUNK
323 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
325 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
326 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
328 #undef TARGET_ASM_FILE_START
329 #define TARGET_ASM_FILE_START sh_file_start
330 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
331 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
333 #undef TARGET_DEFAULT_TARGET_FLAGS
334 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
335 #undef TARGET_HANDLE_OPTION
336 #define TARGET_HANDLE_OPTION sh_handle_option
338 #undef TARGET_INSERT_ATTRIBUTES
339 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
341 #undef TARGET_SCHED_ADJUST_COST
342 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
344 #undef TARGET_SCHED_ISSUE_RATE
345 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
347 /* The next 5 hooks have been implemented for reenabling sched1. With the
348 help of these macros we are limiting the movement of insns in sched1 to
349 reduce the register pressure. The overall idea is to keep count of SImode
350 and SFmode regs required by already scheduled insns. When these counts
351 cross some threshold values; give priority to insns that free registers.
352 The insn that frees registers is most likely to be the insn with lowest
353 LUID (original insn order); but such an insn might be there in the stalled
354 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
355 upto a max of 8 cycles so that such insns may move from Q -> R.
357 The description of the hooks are as below:
359 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
360 scheduler; it is called inside the sched_init function just after
361 find_insn_reg_weights function call. It is used to calculate the SImode
362 and SFmode weights of insns of basic blocks; much similar to what
363 find_insn_reg_weights does.
364 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
366 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
367 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
370 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
371 high; reorder the ready queue so that the insn with lowest LUID will be
374 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
375 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
377 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
378 can be returned from TARGET_SCHED_REORDER2.
380 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
382 #undef TARGET_SCHED_DFA_NEW_CYCLE
383 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
385 #undef TARGET_SCHED_INIT_GLOBAL
386 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
388 #undef TARGET_SCHED_FINISH_GLOBAL
389 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
391 #undef TARGET_SCHED_VARIABLE_ISSUE
392 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
394 #undef TARGET_SCHED_REORDER
395 #define TARGET_SCHED_REORDER sh_reorder
397 #undef TARGET_SCHED_REORDER2
398 #define TARGET_SCHED_REORDER2 sh_reorder2
400 #undef TARGET_SCHED_INIT
401 #define TARGET_SCHED_INIT sh_md_init
403 #undef TARGET_LEGITIMIZE_ADDRESS
404 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
406 #undef TARGET_CANNOT_MODIFY_JUMPS_P
407 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
408 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
409 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
410 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
411 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
412 sh_optimize_target_register_callee_saved
414 #undef TARGET_MS_BITFIELD_LAYOUT_P
415 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
417 #undef TARGET_INIT_BUILTINS
418 #define TARGET_INIT_BUILTINS sh_init_builtins
419 #undef TARGET_EXPAND_BUILTIN
420 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
422 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
423 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
425 #undef TARGET_CANNOT_COPY_INSN_P
426 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
427 #undef TARGET_RTX_COSTS
428 #define TARGET_RTX_COSTS sh_rtx_costs
429 #undef TARGET_ADDRESS_COST
430 #define TARGET_ADDRESS_COST sh_address_cost
431 #undef TARGET_ALLOCATE_INITIAL_VALUE
432 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
434 #undef TARGET_MACHINE_DEPENDENT_REORG
435 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
437 #undef TARGET_DWARF_REGISTER_SPAN
438 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
441 #undef TARGET_HAVE_TLS
442 #define TARGET_HAVE_TLS true
445 #undef TARGET_PROMOTE_PROTOTYPES
446 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
447 #undef TARGET_PROMOTE_FUNCTION_MODE
448 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
450 #undef TARGET_STRUCT_VALUE_RTX
451 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
452 #undef TARGET_RETURN_IN_MEMORY
453 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
455 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
456 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
457 #undef TARGET_SETUP_INCOMING_VARARGS
458 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
459 #undef TARGET_STRICT_ARGUMENT_NAMING
460 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
461 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
462 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
463 #undef TARGET_MUST_PASS_IN_STACK
464 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
465 #undef TARGET_PASS_BY_REFERENCE
466 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
467 #undef TARGET_CALLEE_COPIES
468 #define TARGET_CALLEE_COPIES sh_callee_copies
469 #undef TARGET_ARG_PARTIAL_BYTES
470 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
472 #undef TARGET_BUILD_BUILTIN_VA_LIST
473 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
474 #undef TARGET_EXPAND_BUILTIN_VA_START
475 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
476 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
477 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
479 #undef TARGET_SCALAR_MODE_SUPPORTED_P
480 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
481 #undef TARGET_VECTOR_MODE_SUPPORTED_P
482 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
484 #undef TARGET_CHECK_PCH_TARGET_FLAGS
485 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
487 #undef TARGET_DWARF_CALLING_CONVENTION
488 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
490 /* Return regmode weight for insn. */
491 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
493 /* Return current register pressure for regmode. */
494 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
496 #undef TARGET_ENCODE_SECTION_INFO
497 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
501 #undef TARGET_ENCODE_SECTION_INFO
502 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
503 #undef TARGET_STRIP_NAME_ENCODING
504 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
505 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
506 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
510 #undef TARGET_SECONDARY_RELOAD
511 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
513 #undef TARGET_LEGITIMATE_ADDRESS_P
514 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
516 #undef TARGET_TRAMPOLINE_INIT
517 #define TARGET_TRAMPOLINE_INIT sh_trampoline_init
518 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
519 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
521 /* Machine-specific symbol_ref flags. */
522 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
524 struct gcc_target targetm = TARGET_INITIALIZER;
526 /* Implement TARGET_HANDLE_OPTION. */
529 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
530 int value ATTRIBUTE_UNUSED)
535 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
539 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
543 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
547 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
551 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
554 case OPT_m2a_single_only:
555 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
559 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
563 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
567 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
574 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
578 case OPT_m4_100_nofpu:
579 case OPT_m4_200_nofpu:
580 case OPT_m4_300_nofpu:
584 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
588 case OPT_m4_100_single:
589 case OPT_m4_200_single:
590 case OPT_m4_300_single:
591 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
594 case OPT_m4_single_only:
595 case OPT_m4_100_single_only:
596 case OPT_m4_200_single_only:
597 case OPT_m4_300_single_only:
598 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
602 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
607 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
611 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
614 case OPT_m4a_single_only:
615 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
619 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
622 case OPT_m5_32media_nofpu:
623 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
627 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
630 case OPT_m5_64media_nofpu:
631 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
635 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
638 case OPT_m5_compact_nofpu:
639 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
647 /* Set default optimization options. */
649 sh_optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
653 flag_omit_frame_pointer = 2;
655 sh_div_str = "inv:minlat";
659 target_flags |= MASK_SMALLCODE;
660 sh_div_str = SH_DIV_STR_FOR_SIZE ;
663 TARGET_CBRANCHDI4 = 1;
664 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options
665 haven't been parsed yet, hence we'd read only the default.
666 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so
667 it's OK to always set flag_branch_target_load_optimize. */
670 flag_branch_target_load_optimize = 1;
672 target_flags |= MASK_SAVE_ALL_TARGET_REGS;
674 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE
675 here, so leave it to OVERRIDE_OPTIONS to set
676 flag_finite_math_only. We set it to 2 here so we know if the user
677 explicitly requested this to be on or off. */
678 flag_finite_math_only = 2;
679 /* If flag_schedule_insns is 1, we set it to 2 here so we know if
680 the user explicitly requested this to be on or off. */
681 if (flag_schedule_insns > 0)
682 flag_schedule_insns = 2;
684 set_param_value ("simultaneous-prefetches", 2);
687 /* Implement OVERRIDE_OPTIONS macro. Validate and override various
688 options, and do some machine dependent initialization. */
690 sh_override_options (void)
694 SUBTARGET_OVERRIDE_OPTIONS;
695 if (flag_finite_math_only == 2)
696 flag_finite_math_only
697 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;
698 if (TARGET_SH2E && !flag_finite_math_only)
699 target_flags |= MASK_IEEE;
700 sh_cpu = PROCESSOR_SH1;
701 assembler_dialect = 0;
703 sh_cpu = PROCESSOR_SH2;
705 sh_cpu = PROCESSOR_SH2E;
707 sh_cpu = PROCESSOR_SH2A;
709 sh_cpu = PROCESSOR_SH3;
711 sh_cpu = PROCESSOR_SH3E;
714 assembler_dialect = 1;
715 sh_cpu = PROCESSOR_SH4;
717 if (TARGET_SH4A_ARCH)
719 assembler_dialect = 1;
720 sh_cpu = PROCESSOR_SH4A;
724 sh_cpu = PROCESSOR_SH5;
725 target_flags |= MASK_ALIGN_DOUBLE;
726 if (TARGET_SHMEDIA_FPU)
727 target_flags |= MASK_FMOVD;
730 /* There are no delay slots on SHmedia. */
731 flag_delayed_branch = 0;
732 /* Relaxation isn't yet supported for SHmedia */
733 target_flags &= ~MASK_RELAX;
734 /* After reload, if conversion does little good but can cause
736 - find_if_block doesn't do anything for SH because we don't
737 have conditional execution patterns. (We use conditional
738 move patterns, which are handled differently, and only
740 - find_cond_trap doesn't do anything for the SH because we
741 don't have conditional traps.
742 - find_if_case_1 uses redirect_edge_and_branch_force in
743 the only path that does an optimization, and this causes
744 an ICE when branch targets are in registers.
745 - find_if_case_2 doesn't do anything for the SHmedia after
746 reload except when it can redirect a tablejump - and
747 that's rather rare. */
748 flag_if_conversion2 = 0;
749 if (! strcmp (sh_div_str, "call"))
750 sh_div_strategy = SH_DIV_CALL;
751 else if (! strcmp (sh_div_str, "call2"))
752 sh_div_strategy = SH_DIV_CALL2;
753 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)
754 sh_div_strategy = SH_DIV_FP;
755 else if (! strcmp (sh_div_str, "inv"))
756 sh_div_strategy = SH_DIV_INV;
757 else if (! strcmp (sh_div_str, "inv:minlat"))
758 sh_div_strategy = SH_DIV_INV_MINLAT;
759 else if (! strcmp (sh_div_str, "inv20u"))
760 sh_div_strategy = SH_DIV_INV20U;
761 else if (! strcmp (sh_div_str, "inv20l"))
762 sh_div_strategy = SH_DIV_INV20L;
763 else if (! strcmp (sh_div_str, "inv:call2"))
764 sh_div_strategy = SH_DIV_INV_CALL2;
765 else if (! strcmp (sh_div_str, "inv:call"))
766 sh_div_strategy = SH_DIV_INV_CALL;
767 else if (! strcmp (sh_div_str, "inv:fp"))
770 sh_div_strategy = SH_DIV_INV_FP;
772 sh_div_strategy = SH_DIV_INV;
774 TARGET_CBRANCHDI4 = 0;
775 /* Assembler CFI isn't yet fully supported for SHmedia. */
776 flag_dwarf2_cfi_asm = 0;
781 /* Only the sh64-elf assembler fully supports .quad properly. */
782 targetm.asm_out.aligned_op.di = NULL;
783 targetm.asm_out.unaligned_op.di = NULL;
787 if (! strcmp (sh_div_str, "call-div1"))
788 sh_div_strategy = SH_DIV_CALL_DIV1;
789 else if (! strcmp (sh_div_str, "call-fp")
790 && (TARGET_FPU_DOUBLE
791 || (TARGET_HARD_SH4 && TARGET_SH2E)
792 || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))
793 sh_div_strategy = SH_DIV_CALL_FP;
794 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)
795 sh_div_strategy = SH_DIV_CALL_TABLE;
797 /* Pick one that makes most sense for the target in general.
798 It is not much good to use different functions depending
799 on -Os, since then we'll end up with two different functions
800 when some of the code is compiled for size, and some for
803 /* SH4 tends to emphasize speed. */
805 sh_div_strategy = SH_DIV_CALL_TABLE;
806 /* These have their own way of doing things. */
807 else if (TARGET_SH2A)
808 sh_div_strategy = SH_DIV_INTRINSIC;
809 /* ??? Should we use the integer SHmedia function instead? */
810 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
811 sh_div_strategy = SH_DIV_CALL_FP;
812 /* SH1 .. SH3 cores often go into small-footprint systems, so
813 default to the smallest implementation available. */
814 else if (TARGET_SH2) /* ??? EXPERIMENTAL */
815 sh_div_strategy = SH_DIV_CALL_TABLE;
817 sh_div_strategy = SH_DIV_CALL_DIV1;
820 TARGET_PRETEND_CMOVE = 0;
821 if (sh_divsi3_libfunc[0])
822 ; /* User supplied - leave it alone. */
823 else if (TARGET_DIVIDE_CALL_FP)
824 sh_divsi3_libfunc = "__sdivsi3_i4";
825 else if (TARGET_DIVIDE_CALL_TABLE)
826 sh_divsi3_libfunc = "__sdivsi3_i4i";
828 sh_divsi3_libfunc = "__sdivsi3_1";
830 sh_divsi3_libfunc = "__sdivsi3";
831 if (sh_branch_cost == -1)
833 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1;
835 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
836 if (! VALID_REGISTER_P (regno))
837 sh_register_names[regno][0] = '\0';
839 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
840 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
841 sh_additional_register_names[regno][0] = '\0';
843 if (flag_omit_frame_pointer == 2)
845 /* The debugging information is sufficient,
846 but gdb doesn't implement this yet */
848 flag_omit_frame_pointer
849 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);
851 flag_omit_frame_pointer = 0;
854 if ((flag_pic && ! TARGET_PREFERGOT)
855 || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
856 flag_no_function_cse = 1;
858 if (SMALL_REGISTER_CLASSES)
860 /* Never run scheduling before reload, since that can
861 break global alloc, and generates slower code anyway due
862 to the pressure on R0. */
863 /* Enable sched1 for SH4 if the user explicitly requests.
864 When sched1 is enabled, the ready queue will be reordered by
865 the target hooks if pressure is high. We can not do this for
866 PIC, SH3 and lower as they give spill failures for R0. */
867 if (!TARGET_HARD_SH4 || flag_pic)
868 flag_schedule_insns = 0;
869 /* ??? Current exception handling places basic block boundaries
870 after call_insns. It causes the high pressure on R0 and gives
871 spill failures for R0 in reload. See PR 22553 and the thread
873 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
874 else if (flag_exceptions)
876 if (flag_schedule_insns == 1)
877 warning (0, "ignoring -fschedule-insns because of exception handling bug");
878 flag_schedule_insns = 0;
880 else if (flag_schedule_insns == 2)
881 flag_schedule_insns = 0;
884 /* Unwinding with -freorder-blocks-and-partition does not work on this
885 architecture, because it requires far jumps to label crossing between
886 hot/cold sections which are rejected on this architecture. */
887 if (flag_reorder_blocks_and_partition)
891 inform (input_location,
892 "-freorder-blocks-and-partition does not work with "
893 "exceptions on this architecture");
894 flag_reorder_blocks_and_partition = 0;
895 flag_reorder_blocks = 1;
897 else if (flag_unwind_tables)
899 inform (input_location,
900 "-freorder-blocks-and-partition does not support unwind "
901 "info on this architecture");
902 flag_reorder_blocks_and_partition = 0;
903 flag_reorder_blocks = 1;
907 if (align_loops == 0)
908 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
909 if (align_jumps == 0)
910 align_jumps = 1 << CACHE_LOG;
911 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
912 align_jumps = TARGET_SHMEDIA ? 4 : 2;
914 /* Allocation boundary (in *bytes*) for the code of a function.
915 SH1: 32 bit alignment is faster, because instructions are always
916 fetched as a pair from a longword boundary.
917 SH2 .. SH5 : align to cache line start. */
918 if (align_functions == 0)
920 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
921 /* The linker relaxation code breaks when a function contains
922 alignments that are larger than that at the start of a
927 = align_loops > align_jumps ? align_loops : align_jumps;
929 /* Also take possible .long constants / mova tables int account. */
932 if (align_functions < min_align)
933 align_functions = min_align;
936 if (sh_fixed_range_str)
937 sh_fix_range (sh_fixed_range_str);
940 /* Print the operand address in x to the stream. */
943 print_operand_address (FILE *stream, rtx x)
945 switch (GET_CODE (x))
949 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
954 rtx base = XEXP (x, 0);
955 rtx index = XEXP (x, 1);
957 switch (GET_CODE (index))
960 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
961 reg_names[true_regnum (base)]);
967 int base_num = true_regnum (base);
968 int index_num = true_regnum (index);
970 fprintf (stream, "@(r0,%s)",
971 reg_names[MAX (base_num, index_num)]);
982 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
986 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
990 x = mark_constant_pool_use (x);
991 output_addr_const (stream, x);
996 /* Print operand x (an rtx) in assembler syntax to file stream
997 according to modifier code.
999 '.' print a .s if insn needs delay slot
1000 ',' print LOCAL_LABEL_PREFIX
1001 '@' print trap, rte or rts depending upon pragma interruptness
1002 '#' output a nop if there is nothing to put in the delay slot
1003 ''' print likelihood suffix (/u for unlikely).
1004 '>' print branch target if -fverbose-asm
1005 'O' print a constant without the #
1006 'R' print the LSW of a dp value - changes if in little endian
1007 'S' print the MSW of a dp value - changes if in little endian
1008 'T' print the next word of a dp value - same as 'R' in big endian mode.
1009 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
1010 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
1011 'N' print 'r63' if the operand is (const_int 0).
1012 'd' print a V2SF reg as dN instead of fpN.
1013 'm' print a pair `base,offset' or `base,index', for LD and ST.
1014 'U' Likewise for {LD,ST}{HI,LO}.
1015 'V' print the position of a single bit set.
1016 'W' print the position of a single bit cleared.
1017 't' print a memory address which is a register.
1018 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
1019 'o' output an operator. */
1022 print_operand (FILE *stream, rtx x, int code)
1025 enum machine_mode mode;
1033 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
1034 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
1035 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
1038 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
1041 trapa_attr = lookup_attribute ("trap_exit",
1042 DECL_ATTRIBUTES (current_function_decl));
1044 fprintf (stream, "trapa #%ld",
1045 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
1046 else if (sh_cfun_interrupt_handler_p ())
1048 if (sh_cfun_resbank_handler_p ())
1049 fprintf (stream, "resbank\n");
1050 fprintf (stream, "rte");
1053 fprintf (stream, "rts");
1056 /* Output a nop if there's nothing in the delay slot. */
1057 if (dbr_sequence_length () == 0)
1058 fprintf (stream, "\n\tnop");
1062 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1064 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
1065 fputs ("/u", stream);
1069 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
1071 fputs ("\t! target: ", stream);
1072 output_addr_const (stream, JUMP_LABEL (current_output_insn));
1076 x = mark_constant_pool_use (x);
1077 output_addr_const (stream, x);
1079 /* N.B.: %R / %S / %T adjust memory addresses by four.
1080 For SHMEDIA, that means they can be used to access the first and
1081 second 32 bit part of a 64 bit (or larger) value that
1082 might be held in floating point registers or memory.
1083 While they can be used to access 64 bit parts of a larger value
1084 held in general purpose registers, that won't work with memory -
1085 neither for fp registers, since the frxx names are used. */
1087 if (REG_P (x) || GET_CODE (x) == SUBREG)
1089 regno = true_regnum (x);
1090 regno += FP_REGISTER_P (regno) ? 1 : LSW;
1091 fputs (reg_names[regno], (stream));
1095 x = adjust_address (x, SImode, 4 * LSW);
1096 print_operand_address (stream, XEXP (x, 0));
1102 mode = GET_MODE (x);
1103 if (mode == VOIDmode)
1105 if (GET_MODE_SIZE (mode) >= 8)
1106 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
1108 print_operand (stream, sub, 0);
1110 output_operand_lossage ("invalid operand to %%R");
1114 if (REG_P (x) || GET_CODE (x) == SUBREG)
1116 regno = true_regnum (x);
1117 regno += FP_REGISTER_P (regno) ? 0 : MSW;
1118 fputs (reg_names[regno], (stream));
1122 x = adjust_address (x, SImode, 4 * MSW);
1123 print_operand_address (stream, XEXP (x, 0));
1129 mode = GET_MODE (x);
1130 if (mode == VOIDmode)
1132 if (GET_MODE_SIZE (mode) >= 8)
1133 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
1135 print_operand (stream, sub, 0);
1137 output_operand_lossage ("invalid operand to %%S");
1141 /* Next word of a double. */
1142 switch (GET_CODE (x))
1145 fputs (reg_names[REGNO (x) + 1], (stream));
1148 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1149 && GET_CODE (XEXP (x, 0)) != POST_INC)
1150 x = adjust_address (x, SImode, 4);
1151 print_operand_address (stream, XEXP (x, 0));
1159 gcc_assert (MEM_P (x));
1161 switch (GET_CODE (x))
1165 print_operand (stream, x, 0);
1173 switch (GET_CODE (x))
1175 case PLUS: fputs ("add", stream); break;
1176 case MINUS: fputs ("sub", stream); break;
1177 case MULT: fputs ("mul", stream); break;
1178 case DIV: fputs ("div", stream); break;
1179 case EQ: fputs ("eq", stream); break;
1180 case NE: fputs ("ne", stream); break;
1181 case GT: case LT: fputs ("gt", stream); break;
1182 case GE: case LE: fputs ("ge", stream); break;
1183 case GTU: case LTU: fputs ("gtu", stream); break;
1184 case GEU: case LEU: fputs ("geu", stream); break;
1193 && GET_CODE (XEXP (x, 0)) == PLUS
1194 && (REG_P (XEXP (XEXP (x, 0), 1))
1195 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
1196 fputc ('x', stream);
1202 switch (GET_MODE (x))
1204 case QImode: fputs (".b", stream); break;
1205 case HImode: fputs (".w", stream); break;
1206 case SImode: fputs (".l", stream); break;
1207 case SFmode: fputs (".s", stream); break;
1208 case DFmode: fputs (".d", stream); break;
1209 default: gcc_unreachable ();
1216 gcc_assert (MEM_P (x));
1220 switch (GET_CODE (x))
1224 print_operand (stream, x, 0);
1225 fputs (", 0", stream);
1229 print_operand (stream, XEXP (x, 0), 0);
1230 fputs (", ", stream);
1231 print_operand (stream, XEXP (x, 1), 0);
1241 int num = exact_log2 (INTVAL (x));
1242 gcc_assert (num >= 0);
1243 fprintf (stream, "#%d", num);
1249 int num = exact_log2 (~INTVAL (x));
1250 gcc_assert (num >= 0);
1251 fprintf (stream, "#%d", num);
1256 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
1258 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1262 if (x == CONST0_RTX (GET_MODE (x)))
1264 fprintf ((stream), "r63");
1267 goto default_output;
1269 if (CONST_INT_P (x))
1271 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1279 mode = GET_MODE (x);
1281 switch (GET_CODE (x))
1285 rtx inner = XEXP (x, 0);
1287 enum machine_mode inner_mode;
1289 /* We might see SUBREGs with vector mode registers inside. */
1290 if (GET_CODE (inner) == SUBREG
1291 && (GET_MODE_SIZE (GET_MODE (inner))
1292 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1293 && subreg_lowpart_p (inner))
1294 inner = SUBREG_REG (inner);
1295 if (CONST_INT_P (inner))
1297 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1298 goto default_output;
1300 inner_mode = GET_MODE (inner);
1301 if (GET_CODE (inner) == SUBREG
1302 && (GET_MODE_SIZE (GET_MODE (inner))
1303 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1304 && REG_P (SUBREG_REG (inner)))
1306 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1307 GET_MODE (SUBREG_REG (inner)),
1308 SUBREG_BYTE (inner),
1310 inner = SUBREG_REG (inner);
1312 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
1314 /* Floating point register pairs are always big endian;
1315 general purpose registers are 64 bit wide. */
1316 regno = REGNO (inner);
1317 regno = (HARD_REGNO_NREGS (regno, inner_mode)
1318 - HARD_REGNO_NREGS (regno, mode))
1326 /* FIXME: We need this on SHmedia32 because reload generates
1327 some sign-extended HI or QI loads into DImode registers
1328 but, because Pmode is SImode, the address ends up with a
1329 subreg:SI of the DImode register. Maybe reload should be
1330 fixed so as to apply alter_subreg to such loads? */
1332 gcc_assert (trapping_target_operand (x, VOIDmode));
1333 x = XEXP (XEXP (x, 2), 0);
1334 goto default_output;
1336 gcc_assert (SUBREG_BYTE (x) == 0
1337 && REG_P (SUBREG_REG (x)));
1345 if (FP_REGISTER_P (regno)
1346 && mode == V16SFmode)
1347 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1348 else if (FP_REGISTER_P (REGNO (x))
1349 && mode == V4SFmode)
1350 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1352 && mode == V2SFmode)
1353 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1354 else if (FP_REGISTER_P (REGNO (x))
1355 && GET_MODE_SIZE (mode) > 4)
1356 fprintf ((stream), "d%s", reg_names[regno] + 1);
1358 fputs (reg_names[regno], (stream));
1362 output_address (XEXP (x, 0));
1367 fputc ('#', stream);
1368 output_addr_const (stream, x);
1376 /* Encode symbol attributes of a SYMBOL_REF into its
1377 SYMBOL_REF_FLAGS. */
1379 sh_encode_section_info (tree decl, rtx rtl, int first)
1381 default_encode_section_info (decl, rtl, first);
1383 if (TREE_CODE (decl) == FUNCTION_DECL
1384 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1385 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1388 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1390 force_into (rtx value, rtx target)
1392 value = force_operand (value, target);
1393 if (! rtx_equal_p (value, target))
1394 emit_insn (gen_move_insn (target, value));
1397 /* Emit code to perform a block move. Choose the best method.
1399 OPERANDS[0] is the destination.
1400 OPERANDS[1] is the source.
1401 OPERANDS[2] is the size.
1402 OPERANDS[3] is the alignment safe to use. */
1405 expand_block_move (rtx *operands)
1407 int align = INTVAL (operands[3]);
1408 int constp = (CONST_INT_P (operands[2]));
1409 int bytes = (constp ? INTVAL (operands[2]) : 0);
1414 /* If we could use mov.l to move words and dest is word-aligned, we
1415 can use movua.l for loads and still generate a relatively short
1416 and efficient sequence. */
1417 if (TARGET_SH4A_ARCH && align < 4
1418 && MEM_ALIGN (operands[0]) >= 32
1419 && can_move_by_pieces (bytes, 32))
1421 rtx dest = copy_rtx (operands[0]);
1422 rtx src = copy_rtx (operands[1]);
1423 /* We could use different pseudos for each copied word, but
1424 since movua can only load into r0, it's kind of
1426 rtx temp = gen_reg_rtx (SImode);
1427 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1430 while (copied + 4 <= bytes)
1432 rtx to = adjust_address (dest, SImode, copied);
1433 rtx from = adjust_automodify_address (src, BLKmode,
1436 set_mem_size (from, GEN_INT (4));
1437 emit_insn (gen_movua (temp, from));
1438 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1439 emit_move_insn (to, temp);
1444 move_by_pieces (adjust_address (dest, BLKmode, copied),
1445 adjust_automodify_address (src, BLKmode,
1447 bytes - copied, align, 0);
1452 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1453 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1454 if (align < 4 || (bytes % 4 != 0))
1457 if (TARGET_HARD_SH4)
1461 else if (bytes == 12)
1463 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1464 rtx r4 = gen_rtx_REG (SImode, 4);
1465 rtx r5 = gen_rtx_REG (SImode, 5);
1467 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1468 force_into (XEXP (operands[0], 0), r4);
1469 force_into (XEXP (operands[1], 0), r5);
1470 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1473 else if (! TARGET_SMALLCODE)
1475 const char *entry_name;
1476 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1478 rtx r4 = gen_rtx_REG (SImode, 4);
1479 rtx r5 = gen_rtx_REG (SImode, 5);
1480 rtx r6 = gen_rtx_REG (SImode, 6);
1482 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1483 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1484 force_into (XEXP (operands[0], 0), r4);
1485 force_into (XEXP (operands[1], 0), r5);
1487 dwords = bytes >> 3;
1488 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1489 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1498 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1499 rtx r4 = gen_rtx_REG (SImode, 4);
1500 rtx r5 = gen_rtx_REG (SImode, 5);
1502 sprintf (entry, "__movmemSI%d", bytes);
1503 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1504 force_into (XEXP (operands[0], 0), r4);
1505 force_into (XEXP (operands[1], 0), r5);
1506 emit_insn (gen_block_move_real (func_addr_rtx));
1510 /* This is the same number of bytes as a memcpy call, but to a different
1511 less common function name, so this will occasionally use more space. */
1512 if (! TARGET_SMALLCODE)
1514 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1515 int final_switch, while_loop;
1516 rtx r4 = gen_rtx_REG (SImode, 4);
1517 rtx r5 = gen_rtx_REG (SImode, 5);
1518 rtx r6 = gen_rtx_REG (SImode, 6);
1520 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1521 force_into (XEXP (operands[0], 0), r4);
1522 force_into (XEXP (operands[1], 0), r5);
1524 /* r6 controls the size of the move. 16 is decremented from it
1525 for each 64 bytes moved. Then the negative bit left over is used
1526 as an index into a list of move instructions. e.g., a 72 byte move
1527 would be set up with size(r6) = 14, for one iteration through the
1528 big while loop, and a switch of -2 for the last part. */
1530 final_switch = 16 - ((bytes / 4) % 16);
1531 while_loop = ((bytes / 4) / 16 - 1) * 16;
1532 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1533 emit_insn (gen_block_lump_real (func_addr_rtx));
1540 /* Prepare operands for a move define_expand; specifically, one of the
1541 operands must be in a register. */
1544 prepare_move_operands (rtx operands[], enum machine_mode mode)
1546 if ((mode == SImode || mode == DImode)
1548 && ! ((mode == Pmode || mode == ptr_mode)
1549 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1552 if (SYMBOLIC_CONST_P (operands[1]))
1554 if (MEM_P (operands[0]))
1555 operands[1] = force_reg (Pmode, operands[1]);
1556 else if (TARGET_SHMEDIA
1557 && GET_CODE (operands[1]) == LABEL_REF
1558 && target_reg_operand (operands[0], mode))
1562 temp = (!can_create_pseudo_p ()
1564 : gen_reg_rtx (Pmode));
1565 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1568 else if (GET_CODE (operands[1]) == CONST
1569 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1570 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1572 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1573 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1575 operands[1] = expand_binop (mode, add_optab, temp,
1576 XEXP (XEXP (operands[1], 0), 1),
1577 (!can_create_pseudo_p ()
1579 : gen_reg_rtx (Pmode)),
1580 0, OPTAB_LIB_WIDEN);
1584 if (! reload_in_progress && ! reload_completed)
1586 /* Copy the source to a register if both operands aren't registers. */
1587 if (! register_operand (operands[0], mode)
1588 && ! sh_register_operand (operands[1], mode))
1589 operands[1] = copy_to_mode_reg (mode, operands[1]);
1591 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1593 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1594 except that we can't use that function because it is static. */
1595 rtx new_rtx = change_address (operands[0], mode, 0);
1596 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1597 operands[0] = new_rtx;
1600 /* This case can happen while generating code to move the result
1601 of a library call to the target. Reject `st r0,@(rX,rY)' because
1602 reload will fail to find a spill register for rX, since r0 is already
1603 being used for the source. */
1605 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1606 && MEM_P (operands[0])
1607 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1608 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1609 operands[1] = copy_to_mode_reg (mode, operands[1]);
1612 if (mode == Pmode || mode == ptr_mode)
1615 enum tls_model tls_kind;
1619 if (GET_CODE (op1) == CONST
1620 && GET_CODE (XEXP (op1, 0)) == PLUS
1621 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1624 opc = XEXP (XEXP (op1, 0), 1);
1625 op1 = XEXP (XEXP (op1, 0), 0);
1630 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1632 rtx tga_op1, tga_ret, tmp, tmp2;
1636 case TLS_MODEL_GLOBAL_DYNAMIC:
1637 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1638 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1642 case TLS_MODEL_LOCAL_DYNAMIC:
1643 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1644 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1646 tmp = gen_reg_rtx (Pmode);
1647 emit_move_insn (tmp, tga_ret);
1649 if (register_operand (op0, Pmode))
1652 tmp2 = gen_reg_rtx (Pmode);
1654 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1658 case TLS_MODEL_INITIAL_EXEC:
1661 /* Don't schedule insns for getting GOT address when
1662 the first scheduling is enabled, to avoid spill
1664 if (flag_schedule_insns)
1665 emit_insn (gen_blockage ());
1666 emit_insn (gen_GOTaddr2picreg ());
1667 emit_use (gen_rtx_REG (SImode, PIC_REG));
1668 if (flag_schedule_insns)
1669 emit_insn (gen_blockage ());
1671 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1672 tmp = gen_sym2GOTTPOFF (op1);
1673 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1677 case TLS_MODEL_LOCAL_EXEC:
1678 tmp2 = gen_reg_rtx (Pmode);
1679 emit_insn (gen_load_gbr (tmp2));
1680 tmp = gen_reg_rtx (Pmode);
1681 emit_insn (gen_symTPOFF2reg (tmp, op1));
1683 if (register_operand (op0, Pmode))
1686 op1 = gen_reg_rtx (Pmode);
1688 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1695 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1704 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1705 enum rtx_code comparison)
1708 rtx scratch = NULL_RTX;
1710 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1711 comparison = GET_CODE (operands[0]);
1713 scratch = operands[4];
1714 if (CONST_INT_P (operands[1])
1715 && !CONST_INT_P (operands[2]))
1717 rtx tmp = operands[1];
1719 operands[1] = operands[2];
1721 comparison = swap_condition (comparison);
1723 if (CONST_INT_P (operands[2]))
1725 HOST_WIDE_INT val = INTVAL (operands[2]);
1726 if ((val == -1 || val == -0x81)
1727 && (comparison == GT || comparison == LE))
1729 comparison = (comparison == GT) ? GE : LT;
1730 operands[2] = gen_int_mode (val + 1, mode);
1732 else if ((val == 1 || val == 0x80)
1733 && (comparison == GE || comparison == LT))
1735 comparison = (comparison == GE) ? GT : LE;
1736 operands[2] = gen_int_mode (val - 1, mode);
1738 else if (val == 1 && (comparison == GEU || comparison == LTU))
1740 comparison = (comparison == GEU) ? NE : EQ;
1741 operands[2] = CONST0_RTX (mode);
1743 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1745 comparison = (comparison == GEU) ? GTU : LEU;
1746 operands[2] = gen_int_mode (val - 1, mode);
1748 else if (val == 0 && (comparison == GTU || comparison == LEU))
1749 comparison = (comparison == GTU) ? NE : EQ;
1750 else if (mode == SImode
1751 && ((val == 0x7fffffff
1752 && (comparison == GTU || comparison == LEU))
1753 || ((unsigned HOST_WIDE_INT) val
1754 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1755 && (comparison == GEU || comparison == LTU))))
1757 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1758 operands[2] = CONST0_RTX (mode);
1762 if (can_create_pseudo_p ())
1763 operands[1] = force_reg (mode, op1);
1764 /* When we are handling DImode comparisons, we want to keep constants so
1765 that we can optimize the component comparisons; however, memory loads
1766 are better issued as a whole so that they can be scheduled well.
1767 SImode equality comparisons allow I08 constants, but only when they
1768 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1769 into a register, that register might as well be r0, and we allow the
1770 constant. If it is already in a register, this is likely to be
1771 allocated to a different hard register, thus we load the constant into
1772 a register unless it is zero. */
1773 if (!REG_P (operands[2])
1774 && (!CONST_INT_P (operands[2])
1775 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1776 && ((comparison != EQ && comparison != NE)
1777 || (REG_P (op1) && REGNO (op1) != R0_REG)
1778 || !satisfies_constraint_I08 (operands[2])))))
1780 if (scratch && GET_MODE (scratch) == mode)
1782 emit_move_insn (scratch, operands[2]);
1783 operands[2] = scratch;
1785 else if (can_create_pseudo_p ())
1786 operands[2] = force_reg (mode, operands[2]);
1792 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1794 rtx (*branch_expander) (rtx) = gen_branch_true;
1797 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1800 case NE: case LT: case LE: case LTU: case LEU:
1801 comparison = reverse_condition (comparison);
1802 branch_expander = gen_branch_false;
1805 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1806 gen_rtx_fmt_ee (comparison, SImode,
1807 operands[1], operands[2])));
1808 jump = emit_jump_insn (branch_expander (operands[3]));
1809 if (probability >= 0)
1810 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1814 /* ??? How should we distribute probabilities when more than one branch
1815 is generated. So far we only have soem ad-hoc observations:
1816 - If the operands are random, they are likely to differ in both parts.
1817 - If comparing items in a hash chain, the operands are random or equal;
1818 operation should be EQ or NE.
1819 - If items are searched in an ordered tree from the root, we can expect
1820 the highpart to be unequal about half of the time; operation should be
1821 an inequality comparison, operands non-constant, and overall probability
1822 about 50%. Likewise for quicksort.
1823 - Range checks will be often made against constants. Even if we assume for
1824 simplicity an even distribution of the non-constant operand over a
1825 sub-range here, the same probability could be generated with differently
1826 wide sub-ranges - as long as the ratio of the part of the subrange that
1827 is before the threshold to the part that comes after the threshold stays
1828 the same. Thus, we can't really tell anything here;
1829 assuming random distribution is at least simple.
1833 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1835 enum rtx_code msw_taken, msw_skip, lsw_taken;
1836 rtx skip_label = NULL_RTX;
1837 rtx op1h, op1l, op2h, op2l;
1840 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1841 rtx scratch = operands[4];
1843 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1844 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1845 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1846 op1l = gen_lowpart (SImode, operands[1]);
1847 op2l = gen_lowpart (SImode, operands[2]);
1848 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1849 prob = split_branch_probability;
1850 rev_prob = REG_BR_PROB_BASE - prob;
1853 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1854 That costs 1 cycle more when the first branch can be predicted taken,
1855 but saves us mispredicts because only one branch needs prediction.
1856 It also enables generating the cmpeqdi_t-1 pattern. */
1858 if (TARGET_CMPEQDI_T)
1860 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1861 emit_jump_insn (gen_branch_true (operands[3]));
1868 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1870 msw_skip_prob = rev_prob;
1871 if (REG_BR_PROB_BASE <= 65535)
1872 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1875 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1879 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1880 / ((HOST_WIDEST_INT) prob << 32)))
1886 if (TARGET_CMPEQDI_T)
1888 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1889 emit_jump_insn (gen_branch_false (operands[3]));
1893 msw_taken_prob = prob;
1898 msw_taken = comparison;
1899 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1901 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1902 msw_skip = swap_condition (msw_taken);
1906 if (op2l == CONST0_RTX (SImode))
1907 msw_taken = comparison;
1910 msw_taken = comparison == GE ? GT : GTU;
1911 msw_skip = swap_condition (msw_taken);
1916 msw_taken = comparison;
1917 if (op2l == CONST0_RTX (SImode))
1919 msw_skip = swap_condition (msw_taken);
1923 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1924 msw_taken = comparison;
1928 if (comparison == LE)
1930 else if (op2h != CONST0_RTX (SImode))
1934 msw_skip = swap_condition (msw_taken);
1937 default: return false;
1939 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1940 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1941 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1942 if (comparison != EQ && comparison != NE && num_branches > 1)
1944 if (!CONSTANT_P (operands[2])
1945 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1946 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1948 msw_taken_prob = prob / 2U;
1950 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1951 lsw_taken_prob = prob;
1955 msw_taken_prob = prob;
1956 msw_skip_prob = REG_BR_PROB_BASE;
1957 /* ??? If we have a constant op2h, should we use that when
1958 calculating lsw_taken_prob? */
1959 lsw_taken_prob = prob;
1964 operands[4] = NULL_RTX;
1965 if (reload_completed
1966 && ! arith_reg_or_0_operand (op2h, SImode)
1967 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
1968 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
1969 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
1971 emit_move_insn (scratch, operands[2]);
1972 operands[2] = scratch;
1974 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1975 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1976 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1978 rtx taken_label = operands[3];
1980 /* Operands were possibly modified, but msw_skip doesn't expect this.
1981 Always use the original ones. */
1982 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1988 operands[3] = skip_label = gen_label_rtx ();
1989 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1990 operands[3] = taken_label;
1994 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
1996 if (reload_completed
1997 && ! arith_reg_or_0_operand (op2l, SImode)
1998 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
2000 emit_move_insn (scratch, operands[2]);
2001 operands[2] = scratch;
2003 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
2005 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2006 emit_label (skip_label);
2010 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
2013 sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
2015 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
2017 insn = gen_rtx_PARALLEL (VOIDmode,
2019 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
2020 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
2026 /* Prepare the operands for an scc instruction; make sure that the
2027 compare has been done and the result is in T_REG. */
2029 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
2031 rtx t_reg = gen_rtx_REG (SImode, T_REG);
2032 enum rtx_code oldcode = code;
2033 enum machine_mode mode;
2035 /* First need a compare insn. */
2039 /* It isn't possible to handle this case. */
2056 if (code != oldcode)
2063 mode = GET_MODE (op0);
2064 if (mode == VOIDmode)
2065 mode = GET_MODE (op1);
2067 op0 = force_reg (mode, op0);
2068 if ((code != EQ && code != NE
2069 && (op1 != const0_rtx
2070 || code == GTU || code == GEU || code == LTU || code == LEU))
2071 || (mode == DImode && op1 != const0_rtx)
2072 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2073 op1 = force_reg (mode, op1);
2075 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
2076 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2081 sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
2084 rtx target = gen_reg_rtx (SImode);
2087 gcc_assert (TARGET_SHMEDIA);
2096 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
2097 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2107 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
2108 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2126 rtx t2 = gen_reg_rtx (DImode);
2127 emit_insn (gen_extendsidi2 (t2, target));
2131 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
2134 /* Called from the md file, set up the operands of a compare instruction. */
2137 sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
2139 enum rtx_code code = GET_CODE (operands[0]);
2140 enum rtx_code branch_code;
2141 rtx op0 = operands[1];
2142 rtx op1 = operands[2];
2144 bool need_ccmpeq = false;
2146 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
2148 op0 = force_reg (mode, op0);
2149 op1 = force_reg (mode, op1);
2153 if (code != EQ || mode == DImode)
2155 /* Force args into regs, since we can't use constants here. */
2156 op0 = force_reg (mode, op0);
2157 if (op1 != const0_rtx || code == GTU || code == GEU)
2158 op1 = force_reg (mode, op1);
2162 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2165 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2166 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2168 tem = op0, op0 = op1, op1 = tem;
2169 code = swap_condition (code);
2172 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2175 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2180 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2181 to EQ/GT respectively. */
2182 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2199 branch_code = reverse_condition (code);
2205 insn = gen_rtx_SET (VOIDmode,
2206 gen_rtx_REG (SImode, T_REG),
2207 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2209 sh_emit_set_t_insn (insn, mode);
2211 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2213 if (branch_code == code)
2214 emit_jump_insn (gen_branch_true (operands[3]));
2216 emit_jump_insn (gen_branch_false (operands[3]));
2220 sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
2222 enum rtx_code code = GET_CODE (operands[1]);
2223 rtx op0 = operands[2];
2224 rtx op1 = operands[3];
2226 bool invert = false;
2229 op0 = force_reg (mode, op0);
2230 if ((code != EQ && code != NE
2231 && (op1 != const0_rtx
2232 || code == GTU || code == GEU || code == LTU || code == LEU))
2233 || (mode == DImode && op1 != const0_rtx)
2234 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2235 op1 = force_reg (mode, op1);
2237 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2239 if (code == LT || code == LE)
2241 code = swap_condition (code);
2242 tem = op0, op0 = op1, op1 = tem;
2248 lab = gen_label_rtx ();
2249 sh_emit_scc_to_t (EQ, op0, op1);
2250 emit_jump_insn (gen_branch_true (lab));
2267 sh_emit_scc_to_t (code, op0, op1);
2271 emit_insn (gen_movnegt (operands[0]));
2273 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
2276 /* Functions to output assembly code. */
2278 /* Return a sequence of instructions to perform DI or DF move.
2280 Since the SH cannot move a DI or DF in one instruction, we have
2281 to take care when we see overlapping source and dest registers. */
2284 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2285 enum machine_mode mode)
2287 rtx dst = operands[0];
2288 rtx src = operands[1];
2291 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
2292 return "mov.l %T1,%0\n\tmov.l %1,%0";
2294 if (register_operand (dst, mode)
2295 && register_operand (src, mode))
2297 if (REGNO (src) == MACH_REG)
2298 return "sts mach,%S0\n\tsts macl,%R0";
2300 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2301 when mov.d r1,r0 do r1->r0 then r2->r1. */
2303 if (REGNO (src) + 1 == REGNO (dst))
2304 return "mov %T1,%T0\n\tmov %1,%0";
2306 return "mov %1,%0\n\tmov %T1,%T0";
2308 else if (CONST_INT_P (src))
2310 if (INTVAL (src) < 0)
2311 output_asm_insn ("mov #-1,%S0", operands);
2313 output_asm_insn ("mov #0,%S0", operands);
2315 return "mov %1,%R0";
2317 else if (MEM_P (src))
2320 int dreg = REGNO (dst);
2321 rtx inside = XEXP (src, 0);
2323 switch (GET_CODE (inside))
2326 ptrreg = REGNO (inside);
2330 ptrreg = subreg_regno (inside);
2334 ptrreg = REGNO (XEXP (inside, 0));
2335 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2336 an offsettable address. Unfortunately, offsettable addresses use
2337 QImode to check the offset, and a QImode offsettable address
2338 requires r0 for the other operand, which is not currently
2339 supported, so we can't use the 'o' constraint.
2340 Thus we must check for and handle r0+REG addresses here.
2341 We punt for now, since this is likely very rare. */
2342 gcc_assert (!REG_P (XEXP (inside, 1)));
2346 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2348 return "mov.l %1,%0\n\tmov.l %1,%T0";
2353 /* Work out the safe way to copy. Copy into the second half first. */
2355 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2358 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2361 /* Print an instruction which would have gone into a delay slot after
2362 another instruction, but couldn't because the other instruction expanded
2363 into a sequence where putting the slot insn at the end wouldn't work. */
2366 print_slot (rtx insn)
2368 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
2370 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2374 output_far_jump (rtx insn, rtx op)
2376 struct { rtx lab, reg, op; } this_jmp;
2377 rtx braf_base_lab = NULL_RTX;
2380 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2383 this_jmp.lab = gen_label_rtx ();
2387 && offset - get_attr_length (insn) <= 32766)
2390 jump = "mov.w %O0,%1; braf %1";
2398 jump = "mov.l %O0,%1; braf %1";
2400 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2403 jump = "mov.l %O0,%1; jmp @%1";
2405 /* If we have a scratch register available, use it. */
2406 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2407 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2409 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2410 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2411 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2412 output_asm_insn (jump, &this_jmp.lab);
2413 if (dbr_sequence_length ())
2414 print_slot (final_sequence);
2416 output_asm_insn ("nop", 0);
2420 /* Output the delay slot insn first if any. */
2421 if (dbr_sequence_length ())
2422 print_slot (final_sequence);
2424 this_jmp.reg = gen_rtx_REG (SImode, 13);
2425 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2426 Fortunately, MACL is fixed and call-clobbered, and we never
2427 need its value across jumps, so save r13 in it instead of in
2430 output_asm_insn ("lds r13, macl", 0);
2432 output_asm_insn ("mov.l r13,@-r15", 0);
2433 output_asm_insn (jump, &this_jmp.lab);
2435 output_asm_insn ("sts macl, r13", 0);
2437 output_asm_insn ("mov.l @r15+,r13", 0);
2439 if (far && flag_pic && TARGET_SH2)
2441 braf_base_lab = gen_label_rtx ();
2442 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2443 CODE_LABEL_NUMBER (braf_base_lab));
2446 output_asm_insn (".align 2", 0);
2447 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2449 if (far && flag_pic)
2452 this_jmp.lab = braf_base_lab;
2453 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2456 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2460 /* Local label counter, used for constants in the pool and inside
2461 pattern branches. */
2463 static int lf = 100;
2465 /* Output code for ordinary branches. */
2468 output_branch (int logic, rtx insn, rtx *operands)
2470 switch (get_attr_length (insn))
2473 /* This can happen if filling the delay slot has caused a forward
2474 branch to exceed its range (we could reverse it, but only
2475 when we know we won't overextend other branches; this should
2476 best be handled by relaxation).
2477 It can also happen when other condbranches hoist delay slot insn
2478 from their destination, thus leading to code size increase.
2479 But the branch will still be in the range -4092..+4098 bytes. */
2484 /* The call to print_slot will clobber the operands. */
2485 rtx op0 = operands[0];
2487 /* If the instruction in the delay slot is annulled (true), then
2488 there is no delay slot where we can put it now. The only safe
2489 place for it is after the label. final will do that by default. */
2492 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2493 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2495 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2496 ASSEMBLER_DIALECT ? "/" : ".", label);
2497 print_slot (final_sequence);
2500 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2502 output_asm_insn ("bra\t%l0", &op0);
2503 fprintf (asm_out_file, "\tnop\n");
2504 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2508 /* When relaxing, handle this like a short branch. The linker
2509 will fix it up if it still doesn't fit after relaxation. */
2511 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2513 /* These are for SH2e, in which we have to account for the
2514 extra nop because of the hardware bug in annulled branches. */
2520 gcc_assert (!final_sequence
2521 || !(INSN_ANNULLED_BRANCH_P
2522 (XVECEXP (final_sequence, 0, 0))));
2523 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2525 ASSEMBLER_DIALECT ? "/" : ".", label);
2526 fprintf (asm_out_file, "\tnop\n");
2527 output_asm_insn ("bra\t%l0", operands);
2528 fprintf (asm_out_file, "\tnop\n");
2529 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2533 /* When relaxing, fall through. */
2538 sprintf (buffer, "b%s%ss\t%%l0",
2540 ASSEMBLER_DIALECT ? "/" : ".");
2541 output_asm_insn (buffer, &operands[0]);
2546 /* There should be no longer branches now - that would
2547 indicate that something has destroyed the branches set
2548 up in machine_dependent_reorg. */
2553 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2554 fill in operands 9 as a label to the successor insn.
2555 We try to use jump threading where possible.
2556 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2557 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2558 follow jmp and bt, if the address is in range. */
2560 output_branchy_insn (enum rtx_code code, const char *templ,
2561 rtx insn, rtx *operands)
2563 rtx next_insn = NEXT_INSN (insn);
2565 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2567 rtx src = SET_SRC (PATTERN (next_insn));
2568 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2570 /* Following branch not taken */
2571 operands[9] = gen_label_rtx ();
2572 emit_label_after (operands[9], next_insn);
2573 INSN_ADDRESSES_NEW (operands[9],
2574 INSN_ADDRESSES (INSN_UID (next_insn))
2575 + get_attr_length (next_insn));
2580 int offset = (branch_dest (next_insn)
2581 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2582 if (offset >= -252 && offset <= 258)
2584 if (GET_CODE (src) == IF_THEN_ELSE)
2586 src = XEXP (src, 1);
2592 operands[9] = gen_label_rtx ();
2593 emit_label_after (operands[9], insn);
2594 INSN_ADDRESSES_NEW (operands[9],
2595 INSN_ADDRESSES (INSN_UID (insn))
2596 + get_attr_length (insn));
2601 output_ieee_ccmpeq (rtx insn, rtx *operands)
2603 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2607 /* Output the start of the assembler file. */
2610 sh_file_start (void)
2612 default_file_start ();
2615 /* Declare the .directive section before it is used. */
2616 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2617 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2621 /* We need to show the text section with the proper
2622 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2623 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2624 will complain. We can teach GAS specifically about the
2625 default attributes for our choice of text section, but
2626 then we would have to change GAS again if/when we change
2627 the text section name. */
2628 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2630 /* Switch to the data section so that the coffsem symbol
2631 isn't in the text section. */
2632 switch_to_section (data_section);
2634 if (TARGET_LITTLE_ENDIAN)
2635 fputs ("\t.little\n", asm_out_file);
2639 if (TARGET_SHCOMPACT)
2640 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2641 else if (TARGET_SHMEDIA)
2642 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2643 TARGET_SHMEDIA64 ? 64 : 32);
2647 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2650 unspec_caller_rtx_p (rtx pat)
2655 split_const (pat, &base, &offset);
2656 if (GET_CODE (base) == UNSPEC)
2658 if (XINT (base, 1) == UNSPEC_CALLER)
2660 for (i = 0; i < XVECLEN (base, 0); i++)
2661 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2667 /* Indicate that INSN cannot be duplicated. This is true for insn
2668 that generates a unique label. */
2671 sh_cannot_copy_insn_p (rtx insn)
2675 if (!reload_completed || !flag_pic)
2678 if (!NONJUMP_INSN_P (insn))
2680 if (asm_noperands (insn) >= 0)
2683 pat = PATTERN (insn);
2684 if (GET_CODE (pat) != SET)
2686 pat = SET_SRC (pat);
2688 if (unspec_caller_rtx_p (pat))
2694 /* Actual number of instructions used to make a shift by N. */
2695 static const char ashiftrt_insns[] =
2696 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2698 /* Left shift and logical right shift are the same. */
2699 static const char shift_insns[] =
2700 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2702 /* Individual shift amounts needed to get the above length sequences.
2703 One bit right shifts clobber the T bit, so when possible, put one bit
2704 shifts in the middle of the sequence, so the ends are eligible for
2705 branch delay slots. */
2706 static const short shift_amounts[32][5] = {
2707 {0}, {1}, {2}, {2, 1},
2708 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2709 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2710 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2711 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2712 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2713 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2714 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2716 /* Likewise, but for shift amounts < 16, up to three highmost bits
2717 might be clobbered. This is typically used when combined with some
2718 kind of sign or zero extension. */
2720 static const char ext_shift_insns[] =
2721 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2723 static const short ext_shift_amounts[32][4] = {
2724 {0}, {1}, {2}, {2, 1},
2725 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2726 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2727 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2728 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2729 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2730 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2731 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2733 /* Assuming we have a value that has been sign-extended by at least one bit,
2734 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2735 to shift it by N without data loss, and quicker than by other means? */
2736 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2738 /* This is used in length attributes in sh.md to help compute the length
2739 of arbitrary constant shift instructions. */
2742 shift_insns_rtx (rtx insn)
2744 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2745 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2746 enum rtx_code shift_code = GET_CODE (set_src);
2751 return ashiftrt_insns[shift_count];
2754 return shift_insns[shift_count];
2760 /* Return the cost of a shift. */
2770 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2772 if (GET_MODE (x) == DImode
2773 && CONST_INT_P (XEXP (x, 1))
2774 && INTVAL (XEXP (x, 1)) == 1)
2777 /* Everything else is invalid, because there is no pattern for it. */
2780 /* If shift by a non constant, then this will be expensive. */
2781 if (!CONST_INT_P (XEXP (x, 1)))
2782 return SH_DYNAMIC_SHIFT_COST;
2784 /* Otherwise, return the true cost in instructions. Cope with out of range
2785 shift counts more or less arbitrarily. */
2786 value = INTVAL (XEXP (x, 1)) & 31;
2788 if (GET_CODE (x) == ASHIFTRT)
2790 int cost = ashiftrt_insns[value];
2791 /* If SH3, then we put the constant in a reg and use shad. */
2792 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2793 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2797 return shift_insns[value];
2800 /* Return the cost of an AND operation. */
2807 /* Anding with a register is a single cycle and instruction. */
2808 if (!CONST_INT_P (XEXP (x, 1)))
2811 i = INTVAL (XEXP (x, 1));
2815 if (satisfies_constraint_I10 (XEXP (x, 1))
2816 || satisfies_constraint_J16 (XEXP (x, 1)))
2819 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
2822 /* These constants are single cycle extu.[bw] instructions. */
2823 if (i == 0xff || i == 0xffff)
2825 /* Constants that can be used in an and immediate instruction in a single
2826 cycle, but this requires r0, so make it a little more expensive. */
2827 if (CONST_OK_FOR_K08 (i))
2829 /* Constants that can be loaded with a mov immediate and an and.
2830 This case is probably unnecessary. */
2831 if (CONST_OK_FOR_I08 (i))
2833 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2834 This case is probably unnecessary. */
2838 /* Return the cost of an addition or a subtraction. */
2843 /* Adding a register is a single cycle insn. */
2844 if (REG_P (XEXP (x, 1))
2845 || GET_CODE (XEXP (x, 1)) == SUBREG)
2848 /* Likewise for small constants. */
2849 if (CONST_INT_P (XEXP (x, 1))
2850 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2854 switch (GET_CODE (XEXP (x, 1)))
2859 return TARGET_SHMEDIA64 ? 5 : 3;
2862 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2864 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2866 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2874 /* Any other constant requires a 2 cycle pc-relative load plus an
2879 /* Return the cost of a multiply. */
2881 multcosts (rtx x ATTRIBUTE_UNUSED)
2883 if (sh_multcost >= 0)
2886 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2887 accept constants. Ideally, we would use a cost of one or two and
2888 add the cost of the operand, but disregard the latter when inside loops
2889 and loop invariant code motion is still to follow.
2890 Using a multiply first and splitting it later if it's a loss
2891 doesn't work because of different sign / zero extension semantics
2892 of multiplies vs. shifts. */
2893 return TARGET_SMALLCODE ? 2 : 3;
2897 /* We have a mul insn, so we can never take more than the mul and the
2898 read of the mac reg, but count more because of the latency and extra
2900 if (TARGET_SMALLCODE)
2905 /* If we're aiming at small code, then just count the number of
2906 insns in a multiply call sequence. */
2907 if (TARGET_SMALLCODE)
2910 /* Otherwise count all the insns in the routine we'd be calling too. */
2914 /* Compute a (partial) cost for rtx X. Return true if the complete
2915 cost has been computed, and false if subexpressions should be
2916 scanned. In either case, *TOTAL contains the cost result. */
2919 sh_rtx_costs (rtx x, int code, int outer_code, int *total,
2920 bool speed ATTRIBUTE_UNUSED)
2927 if (INTVAL (x) == 0)
2929 else if (outer_code == AND && and_operand ((x), DImode))
2931 else if ((outer_code == IOR || outer_code == XOR
2932 || outer_code == PLUS)
2933 && CONST_OK_FOR_I10 (INTVAL (x)))
2935 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2936 *total = COSTS_N_INSNS (outer_code != SET);
2937 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2938 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2939 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2940 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2942 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2945 if (CONST_OK_FOR_I08 (INTVAL (x)))
2947 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2948 && CONST_OK_FOR_K08 (INTVAL (x)))
2950 /* prepare_cmp_insn will force costly constants int registers before
2951 the cbranch[sd]i4 patterns can see them, so preserve potentially
2952 interesting ones not covered by I08 above. */
2953 else if (outer_code == COMPARE
2954 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2955 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2956 || INTVAL (x) == 0x7fffffff
2957 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2966 if (TARGET_SHMEDIA64)
2967 *total = COSTS_N_INSNS (4);
2968 else if (TARGET_SHMEDIA32)
2969 *total = COSTS_N_INSNS (2);
2976 *total = COSTS_N_INSNS (4);
2977 /* prepare_cmp_insn will force costly constants int registers before
2978 the cbranchdi4 pattern can see them, so preserve potentially
2979 interesting ones. */
2980 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2986 if (x == CONST0_RTX (GET_MODE (x)))
2988 else if (sh_1el_vec (x, VOIDmode))
2989 *total = outer_code != SET;
2990 if (sh_rep_vec (x, VOIDmode))
2991 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2992 + (outer_code != SET));
2993 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2998 *total = COSTS_N_INSNS (addsubcosts (x));
3002 *total = COSTS_N_INSNS (andcosts (x));
3006 *total = COSTS_N_INSNS (multcosts (x));
3012 *total = COSTS_N_INSNS (shiftcosts (x));
3019 *total = COSTS_N_INSNS (20);
3023 if (sh_1el_vec (x, VOIDmode))
3024 *total = outer_code != SET;
3025 if (sh_rep_vec (x, VOIDmode))
3026 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3027 + (outer_code != SET));
3028 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3041 /* Compute the cost of an address. For the SH, all valid addresses are
3042 the same cost. Use a slightly higher cost for reg + reg addressing,
3043 since it increases pressure on r0. */
3046 sh_address_cost (rtx X,
3047 bool speed ATTRIBUTE_UNUSED)
3049 return (GET_CODE (X) == PLUS
3050 && ! CONSTANT_P (XEXP (X, 1))
3051 && ! TARGET_SHMEDIA ? 1 : 0);
3054 /* Code to expand a shift. */
3057 gen_ashift (int type, int n, rtx reg)
3059 /* Negative values here come from the shift_amounts array. */
3072 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
3076 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
3078 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
3081 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
3086 /* Same for HImode */
3089 gen_ashift_hi (int type, int n, rtx reg)
3091 /* Negative values here come from the shift_amounts array. */
3105 /* We don't have HImode right shift operations because using the
3106 ordinary 32 bit shift instructions for that doesn't generate proper
3107 zero/sign extension.
3108 gen_ashift_hi is only called in contexts where we know that the
3109 sign extension works out correctly. */
3112 if (GET_CODE (reg) == SUBREG)
3114 offset = SUBREG_BYTE (reg);
3115 reg = SUBREG_REG (reg);
3117 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
3121 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3126 /* Output RTL to split a constant shift into its component SH constant
3127 shift instructions. */
3130 gen_shifty_op (int code, rtx *operands)
3132 int value = INTVAL (operands[2]);
3135 /* Truncate the shift count in case it is out of bounds. */
3140 if (code == LSHIFTRT)
3142 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3143 emit_insn (gen_movt (operands[0]));
3146 else if (code == ASHIFT)
3148 /* There is a two instruction sequence for 31 bit left shifts,
3149 but it requires r0. */
3150 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
3152 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3153 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3158 else if (value == 0)
3160 /* This can happen even when optimizing, if there were subregs before
3161 reload. Don't output a nop here, as this is never optimized away;
3162 use a no-op move instead. */
3163 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
3167 max = shift_insns[value];
3168 for (i = 0; i < max; i++)
3169 gen_ashift (code, shift_amounts[value][i], operands[0]);
3172 /* Same as above, but optimized for values where the topmost bits don't
3176 gen_shifty_hi_op (int code, rtx *operands)
3178 int value = INTVAL (operands[2]);
3180 void (*gen_fun) (int, int, rtx);
3182 /* This operation is used by and_shl for SImode values with a few
3183 high bits known to be cleared. */
3187 emit_insn (gen_nop ());
3191 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3194 max = ext_shift_insns[value];
3195 for (i = 0; i < max; i++)
3196 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3199 /* When shifting right, emit the shifts in reverse order, so that
3200 solitary negative values come first. */
3201 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
3202 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3205 /* Output RTL for an arithmetic right shift. */
3207 /* ??? Rewrite to use super-optimizer sequences. */
3210 expand_ashiftrt (rtx *operands)
3218 if (!CONST_INT_P (operands[2]))
3220 rtx count = copy_to_mode_reg (SImode, operands[2]);
3221 emit_insn (gen_negsi2 (count, count));
3222 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3225 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3226 > 1 + SH_DYNAMIC_SHIFT_COST)
3229 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
3230 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3234 if (!CONST_INT_P (operands[2]))
3237 value = INTVAL (operands[2]) & 31;
3241 /* If we are called from abs expansion, arrange things so that we
3242 we can use a single MT instruction that doesn't clobber the source,
3243 if LICM can hoist out the load of the constant zero. */
3244 if (currently_expanding_to_rtl)
3246 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3248 emit_insn (gen_mov_neg_si_t (operands[0]));
3251 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3254 else if (value >= 16 && value <= 19)
3256 wrk = gen_reg_rtx (SImode);
3257 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3260 gen_ashift (ASHIFTRT, 1, wrk);
3261 emit_move_insn (operands[0], wrk);
3264 /* Expand a short sequence inline, longer call a magic routine. */
3265 else if (value <= 5)
3267 wrk = gen_reg_rtx (SImode);
3268 emit_move_insn (wrk, operands[1]);
3270 gen_ashift (ASHIFTRT, 1, wrk);
3271 emit_move_insn (operands[0], wrk);
3275 wrk = gen_reg_rtx (Pmode);
3277 /* Load the value into an arg reg and call a helper. */
3278 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3279 sprintf (func, "__ashiftrt_r4_%d", value);
3280 function_symbol (wrk, func, SFUNC_STATIC);
3281 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
3282 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
3287 sh_dynamicalize_shift_p (rtx count)
3289 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
3292 /* Try to find a good way to implement the combiner pattern
3293 [(set (match_operand:SI 0 "register_operand" "r")
3294 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3295 (match_operand:SI 2 "const_int_operand" "n"))
3296 (match_operand:SI 3 "const_int_operand" "n"))) .
3297 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3298 return 0 for simple right / left or left/right shift combination.
3299 return 1 for a combination of shifts with zero_extend.
3300 return 2 for a combination of shifts with an AND that needs r0.
3301 return 3 for a combination of shifts with an AND that needs an extra
3302 scratch register, when the three highmost bits of the AND mask are clear.
3303 return 4 for a combination of shifts with an AND that needs an extra
3304 scratch register, when any of the three highmost bits of the AND mask
3306 If ATTRP is set, store an initial right shift width in ATTRP[0],
3307 and the instruction length in ATTRP[1] . These values are not valid
3309 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3310 shift_amounts for the last shift value that is to be used before the
3313 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
3315 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3316 int left = INTVAL (left_rtx), right;
3318 int cost, best_cost = 10000;
3319 int best_right = 0, best_len = 0;
3323 if (left < 0 || left > 31)
3325 if (CONST_INT_P (mask_rtx))
3326 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3328 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3329 /* Can this be expressed as a right shift / left shift pair? */
3330 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3331 right = exact_log2 (lsb);
3332 mask2 = ~(mask + lsb - 1);
3333 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3334 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3336 best_cost = shift_insns[right] + shift_insns[right + left];
3337 /* mask has no trailing zeroes <==> ! right */
3338 else if (! right && mask2 == ~(lsb2 - 1))
3340 int late_right = exact_log2 (lsb2);
3341 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3343 /* Try to use zero extend. */
3344 if (mask2 == ~(lsb2 - 1))
3348 for (width = 8; width <= 16; width += 8)
3350 /* Can we zero-extend right away? */
3351 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3354 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3355 if (cost < best_cost)
3366 /* ??? Could try to put zero extend into initial right shift,
3367 or even shift a bit left before the right shift. */
3368 /* Determine value of first part of left shift, to get to the
3369 zero extend cut-off point. */
3370 first = width - exact_log2 (lsb2) + right;
3371 if (first >= 0 && right + left - first >= 0)
3373 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3374 + ext_shift_insns[right + left - first];
3375 if (cost < best_cost)
3387 /* Try to use r0 AND pattern */
3388 for (i = 0; i <= 2; i++)
3392 if (! CONST_OK_FOR_K08 (mask >> i))
3394 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3395 if (cost < best_cost)
3400 best_len = cost - 1;
3403 /* Try to use a scratch register to hold the AND operand. */
3404 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3405 for (i = 0; i <= 2; i++)
3409 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3410 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
3411 if (cost < best_cost)
3416 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
3422 attrp[0] = best_right;
3423 attrp[1] = best_len;
3428 /* This is used in length attributes of the unnamed instructions
3429 corresponding to shl_and_kind return values of 1 and 2. */
3431 shl_and_length (rtx insn)
3433 rtx set_src, left_rtx, mask_rtx;
3436 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3437 left_rtx = XEXP (XEXP (set_src, 0), 1);
3438 mask_rtx = XEXP (set_src, 1);
3439 shl_and_kind (left_rtx, mask_rtx, attributes);
3440 return attributes[1];
3443 /* This is used in length attribute of the and_shl_scratch instruction. */
3446 shl_and_scr_length (rtx insn)
3448 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3449 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
3450 rtx op = XEXP (set_src, 0);
3451 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
3452 op = XEXP (XEXP (op, 0), 0);
3453 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
3456 /* Generate rtl for instructions for which shl_and_kind advised a particular
3457 method of generating them, i.e. returned zero. */
3460 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3463 unsigned HOST_WIDE_INT mask;
3464 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3465 int right, total_shift;
3466 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3468 right = attributes[0];
3469 total_shift = INTVAL (left_rtx) + right;
3470 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3477 int first = attributes[2];
3482 emit_insn ((mask << right) <= 0xff
3483 ? gen_zero_extendqisi2 (dest,
3484 gen_lowpart (QImode, source))
3485 : gen_zero_extendhisi2 (dest,
3486 gen_lowpart (HImode, source)));
3490 emit_insn (gen_movsi (dest, source));
3494 operands[2] = GEN_INT (right);
3495 gen_shifty_hi_op (LSHIFTRT, operands);
3499 operands[2] = GEN_INT (first);
3500 gen_shifty_hi_op (ASHIFT, operands);
3501 total_shift -= first;
3505 emit_insn (mask <= 0xff
3506 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3507 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3508 if (total_shift > 0)
3510 operands[2] = GEN_INT (total_shift);
3511 gen_shifty_hi_op (ASHIFT, operands);
3516 shift_gen_fun = gen_shifty_op;
3518 /* If the topmost bit that matters is set, set the topmost bits
3519 that don't matter. This way, we might be able to get a shorter
3521 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3522 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3524 /* Don't expand fine-grained when combining, because that will
3525 make the pattern fail. */
3526 if (currently_expanding_to_rtl
3527 || reload_in_progress || reload_completed)
3531 /* Cases 3 and 4 should be handled by this split
3532 only while combining */
3533 gcc_assert (kind <= 2);
3536 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3539 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3544 operands[2] = GEN_INT (total_shift);
3545 shift_gen_fun (ASHIFT, operands);
3552 if (kind != 4 && total_shift < 16)
3554 neg = -ext_shift_amounts[total_shift][1];
3556 neg -= ext_shift_amounts[total_shift][2];
3560 emit_insn (gen_and_shl_scratch (dest, source,
3563 GEN_INT (total_shift + neg),
3565 emit_insn (gen_movsi (dest, dest));
3572 /* Try to find a good way to implement the combiner pattern
3573 [(set (match_operand:SI 0 "register_operand" "=r")
3574 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3575 (match_operand:SI 2 "const_int_operand" "n")
3576 (match_operand:SI 3 "const_int_operand" "n")
3578 (clobber (reg:SI T_REG))]
3579 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3580 return 0 for simple left / right shift combination.
3581 return 1 for left shift / 8 bit sign extend / left shift.
3582 return 2 for left shift / 16 bit sign extend / left shift.
3583 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3584 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3585 return 5 for left shift / 16 bit sign extend / right shift
3586 return 6 for < 8 bit sign extend / left shift.
3587 return 7 for < 8 bit sign extend / left shift / single right shift.
3588 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3591 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3593 int left, size, insize, ext;
3594 int cost = 0, best_cost;
3597 left = INTVAL (left_rtx);
3598 size = INTVAL (size_rtx);
3599 insize = size - left;
3600 gcc_assert (insize > 0);
3601 /* Default to left / right shift. */
3603 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3606 /* 16 bit shift / sign extend / 16 bit shift */
3607 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3608 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3609 below, by alternative 3 or something even better. */
3610 if (cost < best_cost)
3616 /* Try a plain sign extend between two shifts. */
3617 for (ext = 16; ext >= insize; ext -= 8)
3621 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3622 if (cost < best_cost)
3624 kind = ext / (unsigned) 8;
3628 /* Check if we can do a sloppy shift with a final signed shift
3629 restoring the sign. */
3630 if (EXT_SHIFT_SIGNED (size - ext))
3631 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3632 /* If not, maybe it's still cheaper to do the second shift sloppy,
3633 and do a final sign extend? */
3634 else if (size <= 16)
3635 cost = ext_shift_insns[ext - insize] + 1
3636 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3639 if (cost < best_cost)
3641 kind = ext / (unsigned) 8 + 2;
3645 /* Check if we can sign extend in r0 */
3648 cost = 3 + shift_insns[left];
3649 if (cost < best_cost)
3654 /* Try the same with a final signed shift. */
3657 cost = 3 + ext_shift_insns[left + 1] + 1;
3658 if (cost < best_cost)
3667 /* Try to use a dynamic shift. */
3668 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3669 if (cost < best_cost)
3680 /* Function to be used in the length attribute of the instructions
3681 implementing this pattern. */
3684 shl_sext_length (rtx insn)
3686 rtx set_src, left_rtx, size_rtx;
3689 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3690 left_rtx = XEXP (XEXP (set_src, 0), 1);
3691 size_rtx = XEXP (set_src, 1);
3692 shl_sext_kind (left_rtx, size_rtx, &cost);
3696 /* Generate rtl for this pattern */
3699 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3702 int left, size, insize, cost;
3705 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3706 left = INTVAL (left_rtx);
3707 size = INTVAL (size_rtx);
3708 insize = size - left;
3716 int ext = kind & 1 ? 8 : 16;
3717 int shift2 = size - ext;
3719 /* Don't expand fine-grained when combining, because that will
3720 make the pattern fail. */
3721 if (! currently_expanding_to_rtl
3722 && ! reload_in_progress && ! reload_completed)
3724 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3725 emit_insn (gen_movsi (dest, source));
3729 emit_insn (gen_movsi (dest, source));
3733 operands[2] = GEN_INT (ext - insize);
3734 gen_shifty_hi_op (ASHIFT, operands);
3737 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3738 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3743 operands[2] = GEN_INT (shift2);
3744 gen_shifty_op (ASHIFT, operands);
3751 if (EXT_SHIFT_SIGNED (shift2))
3753 operands[2] = GEN_INT (shift2 + 1);
3754 gen_shifty_op (ASHIFT, operands);
3755 operands[2] = const1_rtx;
3756 gen_shifty_op (ASHIFTRT, operands);
3759 operands[2] = GEN_INT (shift2);
3760 gen_shifty_hi_op (ASHIFT, operands);
3764 operands[2] = GEN_INT (-shift2);
3765 gen_shifty_hi_op (LSHIFTRT, operands);
3767 emit_insn (size <= 8
3768 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3769 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3776 if (! currently_expanding_to_rtl
3777 && ! reload_in_progress && ! reload_completed)
3778 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3782 operands[2] = GEN_INT (16 - insize);
3783 gen_shifty_hi_op (ASHIFT, operands);
3784 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3786 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3788 gen_ashift (ASHIFTRT, 1, dest);
3793 /* Don't expand fine-grained when combining, because that will
3794 make the pattern fail. */
3795 if (! currently_expanding_to_rtl
3796 && ! reload_in_progress && ! reload_completed)
3798 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3799 emit_insn (gen_movsi (dest, source));
3802 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3803 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3804 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3806 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3807 gen_shifty_op (ASHIFT, operands);
3809 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3817 /* Prefix a symbol_ref name with "datalabel". */
3820 gen_datalabel_ref (rtx sym)
3824 if (GET_CODE (sym) == LABEL_REF)
3825 return gen_rtx_CONST (GET_MODE (sym),
3826 gen_rtx_UNSPEC (GET_MODE (sym),
3830 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3832 str = XSTR (sym, 0);
3833 /* Share all SYMBOL_REF strings with the same value - that is important
3835 str = IDENTIFIER_POINTER (get_identifier (str));
3836 XSTR (sym, 0) = str;
3842 static alloc_pool label_ref_list_pool;
3844 typedef struct label_ref_list_d
3847 struct label_ref_list_d *next;
3848 } *label_ref_list_t;
3850 /* The SH cannot load a large constant into a register, constants have to
3851 come from a pc relative load. The reference of a pc relative load
3852 instruction must be less than 1k in front of the instruction. This
3853 means that we often have to dump a constant inside a function, and
3854 generate code to branch around it.
3856 It is important to minimize this, since the branches will slow things
3857 down and make things bigger.
3859 Worst case code looks like:
3877 We fix this by performing a scan before scheduling, which notices which
3878 instructions need to have their operands fetched from the constant table
3879 and builds the table.
3883 scan, find an instruction which needs a pcrel move. Look forward, find the
3884 last barrier which is within MAX_COUNT bytes of the requirement.
3885 If there isn't one, make one. Process all the instructions between
3886 the find and the barrier.
3888 In the above example, we can tell that L3 is within 1k of L1, so
3889 the first move can be shrunk from the 3 insn+constant sequence into
3890 just 1 insn, and the constant moved to L3 to make:
3901 Then the second move becomes the target for the shortening process. */
3905 rtx value; /* Value in table. */
3906 rtx label; /* Label of value. */
3907 label_ref_list_t wend; /* End of window. */
3908 enum machine_mode mode; /* Mode of value. */
3910 /* True if this constant is accessed as part of a post-increment
3911 sequence. Note that HImode constants are never accessed in this way. */
3912 bool part_of_sequence_p;
3915 /* The maximum number of constants that can fit into one pool, since
3916 constants in the range 0..510 are at least 2 bytes long, and in the
3917 range from there to 1018 at least 4 bytes. */
3919 #define MAX_POOL_SIZE 372
3920 static pool_node pool_vector[MAX_POOL_SIZE];
3921 static int pool_size;
3922 static rtx pool_window_label;
3923 static int pool_window_last;
3925 static int max_labelno_before_reorg;
3927 /* ??? If we need a constant in HImode which is the truncated value of a
3928 constant we need in SImode, we could combine the two entries thus saving
3929 two bytes. Is this common enough to be worth the effort of implementing
3932 /* ??? This stuff should be done at the same time that we shorten branches.
3933 As it is now, we must assume that all branches are the maximum size, and
3934 this causes us to almost always output constant pools sooner than
3937 /* Add a constant to the pool and return its label. */
3940 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3944 label_ref_list_t ref, newref;
3946 /* First see if we've already got it. */
3947 for (i = 0; i < pool_size; i++)
3949 if (x->code == pool_vector[i].value->code
3950 && mode == pool_vector[i].mode)
3952 if (x->code == CODE_LABEL)
3954 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3957 if (rtx_equal_p (x, pool_vector[i].value))
3962 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3964 new_rtx = gen_label_rtx ();
3965 LABEL_REFS (new_rtx) = pool_vector[i].label;
3966 pool_vector[i].label = lab = new_rtx;
3968 if (lab && pool_window_label)
3970 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3971 newref->label = pool_window_label;
3972 ref = pool_vector[pool_window_last].wend;
3974 pool_vector[pool_window_last].wend = newref;
3977 pool_window_label = new_rtx;
3978 pool_window_last = i;
3984 /* Need a new one. */
3985 pool_vector[pool_size].value = x;
3986 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3989 pool_vector[pool_size - 1].part_of_sequence_p = true;
3992 lab = gen_label_rtx ();
3993 pool_vector[pool_size].mode = mode;
3994 pool_vector[pool_size].label = lab;
3995 pool_vector[pool_size].wend = NULL;
3996 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3997 if (lab && pool_window_label)
3999 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
4000 newref->label = pool_window_label;
4001 ref = pool_vector[pool_window_last].wend;
4003 pool_vector[pool_window_last].wend = newref;
4006 pool_window_label = lab;
4007 pool_window_last = pool_size;
4012 /* Output the literal table. START, if nonzero, is the first instruction
4013 this table is needed for, and also indicates that there is at least one
4014 casesi_worker_2 instruction; We have to emit the operand3 labels from
4015 these insns at a 4-byte aligned position. BARRIER is the barrier
4016 after which we are to place the table. */
4019 dump_table (rtx start, rtx barrier)
4025 label_ref_list_t ref;
4028 /* Do two passes, first time dump out the HI sized constants. */
4030 for (i = 0; i < pool_size; i++)
4032 pool_node *p = &pool_vector[i];
4034 if (p->mode == HImode)
4038 scan = emit_insn_after (gen_align_2 (), scan);
4041 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4042 scan = emit_label_after (lab, scan);
4043 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4045 for (ref = p->wend; ref; ref = ref->next)
4048 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4051 else if (p->mode == DFmode)
4059 scan = emit_insn_after (gen_align_4 (), scan);
4061 for (; start != barrier; start = NEXT_INSN (start))
4062 if (NONJUMP_INSN_P (start)
4063 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4065 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4066 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4068 scan = emit_label_after (lab, scan);
4071 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
4073 rtx align_insn = NULL_RTX;
4075 scan = emit_label_after (gen_label_rtx (), scan);
4076 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4079 for (i = 0; i < pool_size; i++)
4081 pool_node *p = &pool_vector[i];
4089 if (align_insn && !p->part_of_sequence_p)
4091 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4092 emit_label_before (lab, align_insn);
4093 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4095 for (ref = p->wend; ref; ref = ref->next)
4098 emit_insn_before (gen_consttable_window_end (lab),
4101 delete_insn (align_insn);
4102 align_insn = NULL_RTX;
4107 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4108 scan = emit_label_after (lab, scan);
4109 scan = emit_insn_after (gen_consttable_4 (p->value,
4111 need_align = ! need_align;
4117 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4122 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4123 scan = emit_label_after (lab, scan);
4124 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4131 if (p->mode != HImode)
4133 for (ref = p->wend; ref; ref = ref->next)
4136 scan = emit_insn_after (gen_consttable_window_end (lab),
4145 for (i = 0; i < pool_size; i++)
4147 pool_node *p = &pool_vector[i];
4158 scan = emit_label_after (gen_label_rtx (), scan);
4159 scan = emit_insn_after (gen_align_4 (), scan);
4161 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4162 scan = emit_label_after (lab, scan);
4163 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4171 scan = emit_label_after (gen_label_rtx (), scan);
4172 scan = emit_insn_after (gen_align_4 (), scan);
4174 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4175 scan = emit_label_after (lab, scan);
4176 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4183 if (p->mode != HImode)
4185 for (ref = p->wend; ref; ref = ref->next)
4188 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4193 scan = emit_insn_after (gen_consttable_end (), scan);
4194 scan = emit_barrier_after (scan);
4196 pool_window_label = NULL_RTX;
4197 pool_window_last = 0;
4200 /* Return nonzero if constant would be an ok source for a
4201 mov.w instead of a mov.l. */
4206 return (CONST_INT_P (src)
4207 && INTVAL (src) >= -32768
4208 && INTVAL (src) <= 32767);
4211 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4213 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4215 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4216 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4217 need to fix it if the input value is CONST_OK_FOR_I08. */
4220 broken_move (rtx insn)
4222 if (NONJUMP_INSN_P (insn))
4224 rtx pat = PATTERN (insn);
4225 if (GET_CODE (pat) == PARALLEL)
4226 pat = XVECEXP (pat, 0, 0);
4227 if (GET_CODE (pat) == SET
4228 /* We can load any 8-bit value if we don't care what the high
4229 order bits end up as. */
4230 && GET_MODE (SET_DEST (pat)) != QImode
4231 && (CONSTANT_P (SET_SRC (pat))
4232 /* Match mova_const. */
4233 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4234 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4235 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
4237 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
4238 && (fp_zero_operand (SET_SRC (pat))
4239 || fp_one_operand (SET_SRC (pat)))
4240 /* In general we don't know the current setting of fpscr, so disable fldi.
4241 There is an exception if this was a register-register move
4242 before reload - and hence it was ascertained that we have
4243 single precision setting - and in a post-reload optimization
4244 we changed this to do a constant load. In that case
4245 we don't have an r0 clobber, hence we must use fldi. */
4247 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4249 && REG_P (SET_DEST (pat))
4250 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
4252 && GET_MODE (SET_DEST (pat)) == SImode
4253 && (satisfies_constraint_I20 (SET_SRC (pat))
4254 || satisfies_constraint_I28 (SET_SRC (pat))))
4255 && ! satisfies_constraint_I08 (SET_SRC (pat)))
4265 return (NONJUMP_INSN_P (insn)
4266 && GET_CODE (PATTERN (insn)) == SET
4267 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
4268 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4269 /* Don't match mova_const. */
4270 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
4273 /* Fix up a mova from a switch that went out of range. */
4275 fixup_mova (rtx mova)
4277 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
4280 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
4281 INSN_CODE (mova) = -1;
4286 rtx lab = gen_label_rtx ();
4287 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
4291 worker = NEXT_INSN (worker);
4293 && !LABEL_P (worker)
4294 && !JUMP_P (worker));
4295 } while (NOTE_P (worker)
4296 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
4297 wpat = PATTERN (worker);
4298 wpat0 = XVECEXP (wpat, 0, 0);
4299 wpat1 = XVECEXP (wpat, 0, 1);
4300 wsrc = SET_SRC (wpat0);
4301 PATTERN (worker) = (gen_casesi_worker_2
4302 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4303 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4305 INSN_CODE (worker) = -1;
4306 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4307 base = gen_rtx_LABEL_REF (Pmode, lab);
4308 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
4309 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4310 INSN_CODE (mova) = -1;
4314 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4315 *num_mova, and check if the new mova is not nested within the first one.
4316 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4317 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4319 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
4321 int n_addr = 0; /* Initialization to shut up spurious warning. */
4322 int f_target, n_target = 0; /* Likewise. */
4326 /* If NEW_MOVA has no address yet, it will be handled later. */
4327 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4330 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4331 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4332 if (n_addr > n_target || n_addr + 1022 < n_target)
4334 /* Change the mova into a load.
4335 broken_move will then return true for it. */
4336 fixup_mova (new_mova);
4342 *first_mova = new_mova;
4347 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4352 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4353 > n_target - n_addr)
4355 fixup_mova (*first_mova);
4360 fixup_mova (new_mova);
4365 /* Find the last barrier from insn FROM which is close enough to hold the
4366 constant pool. If we can't find one, then create one near the end of
4370 find_barrier (int num_mova, rtx mova, rtx from)
4379 int leading_mova = num_mova;
4380 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
4385 /* For HImode: range is 510, add 4 because pc counts from address of
4386 second instruction after this one, subtract 2 for the jump instruction
4387 that we may need to emit before the table, subtract 2 for the instruction
4388 that fills the jump delay slot (in very rare cases, reorg will take an
4389 instruction from after the constant pool or will leave the delay slot
4390 empty). This gives 510.
4391 For SImode: range is 1020, add 4 because pc counts from address of
4392 second instruction after this one, subtract 2 in case pc is 2 byte
4393 aligned, subtract 2 for the jump instruction that we may need to emit
4394 before the table, subtract 2 for the instruction that fills the jump
4395 delay slot. This gives 1018. */
4397 /* The branch will always be shortened now that the reference address for
4398 forward branches is the successor address, thus we need no longer make
4399 adjustments to the [sh]i_limit for -O0. */
4404 while (from && count_si < si_limit && count_hi < hi_limit)
4406 int inc = get_attr_length (from);
4409 /* If this is a label that existed at the time of the compute_alignments
4410 call, determine the alignment. N.B. When find_barrier recurses for
4411 an out-of-reach mova, we might see labels at the start of previously
4412 inserted constant tables. */
4414 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4417 new_align = 1 << label_to_alignment (from);
4418 else if (BARRIER_P (prev_nonnote_insn (from)))
4419 new_align = 1 << barrier_align (from);
4424 /* In case we are scanning a constant table because of recursion, check
4425 for explicit alignments. If the table is long, we might be forced
4426 to emit the new table in front of it; the length of the alignment
4427 might be the last straw. */
4428 else if (NONJUMP_INSN_P (from)
4429 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4430 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4431 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4432 /* When we find the end of a constant table, paste the new constant
4433 at the end. That is better than putting it in front because
4434 this way, we don't need extra alignment for adding a 4-byte-aligned
4435 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4436 else if (NONJUMP_INSN_P (from)
4437 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4438 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4441 if (BARRIER_P (from))
4445 found_barrier = from;
4447 /* If we are at the end of the function, or in front of an alignment
4448 instruction, we need not insert an extra alignment. We prefer
4449 this kind of barrier. */
4450 if (barrier_align (from) > 2)
4451 good_barrier = from;
4453 /* If we are at the end of a hot/cold block, dump the constants
4455 next = NEXT_INSN (from);
4458 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4462 if (broken_move (from))
4465 enum machine_mode mode;
4467 pat = PATTERN (from);
4468 if (GET_CODE (pat) == PARALLEL)
4469 pat = XVECEXP (pat, 0, 0);
4470 src = SET_SRC (pat);
4471 dst = SET_DEST (pat);
4472 mode = GET_MODE (dst);
4474 /* We must explicitly check the mode, because sometimes the
4475 front end will generate code to load unsigned constants into
4476 HImode targets without properly sign extending them. */
4478 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4481 /* We put the short constants before the long constants, so
4482 we must count the length of short constants in the range
4483 for the long constants. */
4484 /* ??? This isn't optimal, but is easy to do. */
4489 /* We dump DF/DI constants before SF/SI ones, because
4490 the limit is the same, but the alignment requirements
4491 are higher. We may waste up to 4 additional bytes
4492 for alignment, and the DF/DI constant may have
4493 another SF/SI constant placed before it. */
4494 if (TARGET_SHCOMPACT
4496 && (mode == DFmode || mode == DImode))
4501 while (si_align > 2 && found_si + si_align - 2 > count_si)
4503 if (found_si > count_si)
4504 count_si = found_si;
4505 found_si += GET_MODE_SIZE (mode);
4507 si_limit -= GET_MODE_SIZE (mode);
4513 switch (untangle_mova (&num_mova, &mova, from))
4515 case 0: return find_barrier (0, 0, mova);
4520 = good_barrier ? good_barrier : found_barrier;
4524 if (found_si > count_si)
4525 count_si = found_si;
4527 else if (JUMP_TABLE_DATA_P (from))
4529 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4531 && (prev_nonnote_insn (from)
4532 == XEXP (MOVA_LABELREF (mova), 0))))
4534 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4536 /* We have just passed the barrier in front of the
4537 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4538 the ADDR_DIFF_VEC is accessed as data, just like our pool
4539 constants, this is a good opportunity to accommodate what
4540 we have gathered so far.
4541 If we waited any longer, we could end up at a barrier in
4542 front of code, which gives worse cache usage for separated
4543 instruction / data caches. */
4544 good_barrier = found_barrier;
4549 rtx body = PATTERN (from);
4550 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4553 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4554 else if (JUMP_P (from)
4556 && ! TARGET_SMALLCODE)
4562 if (new_align > si_align)
4564 si_limit -= (count_si - 1) & (new_align - si_align);
4565 si_align = new_align;
4567 count_si = (count_si + new_align - 1) & -new_align;
4572 if (new_align > hi_align)
4574 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4575 hi_align = new_align;
4577 count_hi = (count_hi + new_align - 1) & -new_align;
4579 from = NEXT_INSN (from);
4586 /* Try as we might, the leading mova is out of range. Change
4587 it into a load (which will become a pcload) and retry. */
4589 return find_barrier (0, 0, mova);
4593 /* Insert the constant pool table before the mova instruction,
4594 to prevent the mova label reference from going out of range. */
4596 good_barrier = found_barrier = barrier_before_mova;
4602 if (good_barrier && next_real_insn (found_barrier))
4603 found_barrier = good_barrier;
4607 /* We didn't find a barrier in time to dump our stuff,
4608 so we'll make one. */
4609 rtx label = gen_label_rtx ();
4611 /* If we exceeded the range, then we must back up over the last
4612 instruction we looked at. Otherwise, we just need to undo the
4613 NEXT_INSN at the end of the loop. */
4614 if (PREV_INSN (from) != orig
4615 && (count_hi > hi_limit || count_si > si_limit))
4616 from = PREV_INSN (PREV_INSN (from));
4618 from = PREV_INSN (from);
4620 /* Walk back to be just before any jump or label.
4621 Putting it before a label reduces the number of times the branch
4622 around the constant pool table will be hit. Putting it before
4623 a jump makes it more likely that the bra delay slot will be
4625 while (NOTE_P (from) || JUMP_P (from)
4627 from = PREV_INSN (from);
4629 from = emit_jump_insn_after (gen_jump (label), from);
4630 JUMP_LABEL (from) = label;
4631 LABEL_NUSES (label) = 1;
4632 found_barrier = emit_barrier_after (from);
4633 emit_label_after (label, found_barrier);
4636 return found_barrier;
4639 /* If the instruction INSN is implemented by a special function, and we can
4640 positively find the register that is used to call the sfunc, and this
4641 register is not used anywhere else in this instruction - except as the
4642 destination of a set, return this register; else, return 0. */
4644 sfunc_uses_reg (rtx insn)
4647 rtx pattern, part, reg_part, reg;
4649 if (!NONJUMP_INSN_P (insn))
4651 pattern = PATTERN (insn);
4652 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4655 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4657 part = XVECEXP (pattern, 0, i);
4658 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4663 reg = XEXP (reg_part, 0);
4664 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4666 part = XVECEXP (pattern, 0, i);
4667 if (part == reg_part || GET_CODE (part) == CLOBBER)
4669 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4670 && REG_P (SET_DEST (part)))
4671 ? SET_SRC (part) : part)))
4677 /* See if the only way in which INSN uses REG is by calling it, or by
4678 setting it while calling it. Set *SET to a SET rtx if the register
4682 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4688 reg2 = sfunc_uses_reg (insn);
4689 if (reg2 && REGNO (reg2) == REGNO (reg))
4691 pattern = single_set (insn);
4693 && REG_P (SET_DEST (pattern))
4694 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4700 /* We don't use rtx_equal_p because we don't care if the mode is
4702 pattern = single_set (insn);
4704 && REG_P (SET_DEST (pattern))
4705 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4711 par = PATTERN (insn);
4712 if (GET_CODE (par) == PARALLEL)
4713 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4715 part = XVECEXP (par, 0, i);
4716 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4719 return reg_mentioned_p (reg, SET_SRC (pattern));
4725 pattern = PATTERN (insn);
4727 if (GET_CODE (pattern) == PARALLEL)
4731 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4732 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4734 pattern = XVECEXP (pattern, 0, 0);
4737 if (GET_CODE (pattern) == SET)
4739 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4741 /* We don't use rtx_equal_p, because we don't care if the
4742 mode is different. */
4743 if (!REG_P (SET_DEST (pattern))
4744 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4750 pattern = SET_SRC (pattern);
4753 if (GET_CODE (pattern) != CALL
4754 || !MEM_P (XEXP (pattern, 0))
4755 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4761 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4762 general registers. Bits 0..15 mean that the respective registers
4763 are used as inputs in the instruction. Bits 16..31 mean that the
4764 registers 0..15, respectively, are used as outputs, or are clobbered.
4765 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4767 regs_used (rtx x, int is_dest)
4775 code = GET_CODE (x);
4780 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4781 << (REGNO (x) + is_dest));
4785 rtx y = SUBREG_REG (x);
4790 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4792 subreg_regno_offset (REGNO (y),
4795 GET_MODE (x)) + is_dest));
4799 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4801 /* If there was a return value, it must have been indicated with USE. */
4816 fmt = GET_RTX_FORMAT (code);
4818 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4823 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4824 used |= regs_used (XVECEXP (x, i, j), is_dest);
4826 else if (fmt[i] == 'e')
4827 used |= regs_used (XEXP (x, i), is_dest);
4832 /* Create an instruction that prevents redirection of a conditional branch
4833 to the destination of the JUMP with address ADDR.
4834 If the branch needs to be implemented as an indirect jump, try to find
4835 a scratch register for it.
4836 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4837 If any preceding insn that doesn't fit into a delay slot is good enough,
4838 pass 1. Pass 2 if a definite blocking insn is needed.
4839 -1 is used internally to avoid deep recursion.
4840 If a blocking instruction is made or recognized, return it. */
4843 gen_block_redirect (rtx jump, int addr, int need_block)
4846 rtx prev = prev_nonnote_insn (jump);
4849 /* First, check if we already have an instruction that satisfies our need. */
4850 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
4852 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4854 if (GET_CODE (PATTERN (prev)) == USE
4855 || GET_CODE (PATTERN (prev)) == CLOBBER
4856 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4858 else if ((need_block &= ~1) < 0)
4860 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4863 if (GET_CODE (PATTERN (jump)) == RETURN)
4867 /* Reorg even does nasty things with return insns that cause branches
4868 to go out of range - see find_end_label and callers. */
4869 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4871 /* We can't use JUMP_LABEL here because it might be undefined
4872 when not optimizing. */
4873 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4874 /* If the branch is out of range, try to find a scratch register for it. */
4876 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4880 /* Don't look for the stack pointer as a scratch register,
4881 it would cause trouble if an interrupt occurred. */
4882 unsigned attempt = 0x7fff, used;
4883 int jump_left = flag_expensive_optimizations + 1;
4885 /* It is likely that the most recent eligible instruction is wanted for
4886 the delay slot. Therefore, find out which registers it uses, and
4887 try to avoid using them. */
4889 for (scan = jump; (scan = PREV_INSN (scan)); )
4893 if (INSN_DELETED_P (scan))
4895 code = GET_CODE (scan);
4896 if (code == CODE_LABEL || code == JUMP_INSN)
4899 && GET_CODE (PATTERN (scan)) != USE
4900 && GET_CODE (PATTERN (scan)) != CLOBBER
4901 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4903 attempt &= ~regs_used (PATTERN (scan), 0);
4907 for (used = dead = 0, scan = JUMP_LABEL (jump);
4908 (scan = NEXT_INSN (scan)); )
4912 if (INSN_DELETED_P (scan))
4914 code = GET_CODE (scan);
4917 used |= regs_used (PATTERN (scan), 0);
4918 if (code == CALL_INSN)
4919 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4920 dead |= (used >> 16) & ~used;
4926 if (code == JUMP_INSN)
4928 if (jump_left-- && simplejump_p (scan))
4929 scan = JUMP_LABEL (scan);
4935 /* Mask out the stack pointer again, in case it was
4936 the only 'free' register we have found. */
4939 /* If the immediate destination is still in range, check for possible
4940 threading with a jump beyond the delay slot insn.
4941 Don't check if we are called recursively; the jump has been or will be
4942 checked in a different invocation then. */
4944 else if (optimize && need_block >= 0)
4946 rtx next = next_active_insn (next_active_insn (dest));
4947 if (next && JUMP_P (next)
4948 && GET_CODE (PATTERN (next)) == SET
4949 && recog_memoized (next) == CODE_FOR_jump_compact)
4951 dest = JUMP_LABEL (next);
4953 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4955 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4961 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4963 /* It would be nice if we could convert the jump into an indirect
4964 jump / far branch right now, and thus exposing all constituent
4965 instructions to further optimization. However, reorg uses
4966 simplejump_p to determine if there is an unconditional jump where
4967 it should try to schedule instructions from the target of the
4968 branch; simplejump_p fails for indirect jumps even if they have
4970 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4971 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4973 /* ??? We would like this to have the scope of the jump, but that
4974 scope will change when a delay slot insn of an inner scope is added.
4975 Hence, after delay slot scheduling, we'll have to expect
4976 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4979 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4980 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4983 else if (need_block)
4984 /* We can't use JUMP_LABEL here because it might be undefined
4985 when not optimizing. */
4986 return emit_insn_before (gen_block_branch_redirect
4987 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4992 #define CONDJUMP_MIN -252
4993 #define CONDJUMP_MAX 262
4996 /* A label (to be placed) in front of the jump
4997 that jumps to our ultimate destination. */
4999 /* Where we are going to insert it if we cannot move the jump any farther,
5000 or the jump itself if we have picked up an existing jump. */
5002 /* The ultimate destination. */
5004 struct far_branch *prev;
5005 /* If the branch has already been created, its address;
5006 else the address of its first prospective user. */
5010 static void gen_far_branch (struct far_branch *);
5011 enum mdep_reorg_phase_e mdep_reorg_phase;
5013 gen_far_branch (struct far_branch *bp)
5015 rtx insn = bp->insert_place;
5017 rtx label = gen_label_rtx ();
5020 emit_label_after (label, insn);
5023 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
5024 LABEL_NUSES (bp->far_label)++;
5027 jump = emit_jump_insn_after (gen_return (), insn);
5028 /* Emit a barrier so that reorg knows that any following instructions
5029 are not reachable via a fall-through path.
5030 But don't do this when not optimizing, since we wouldn't suppress the
5031 alignment for the barrier then, and could end up with out-of-range
5032 pc-relative loads. */
5034 emit_barrier_after (jump);
5035 emit_label_after (bp->near_label, insn);
5036 JUMP_LABEL (jump) = bp->far_label;
5037 ok = invert_jump (insn, label, 1);
5040 /* If we are branching around a jump (rather than a return), prevent
5041 reorg from using an insn from the jump target as the delay slot insn -
5042 when reorg did this, it pessimized code (we rather hide the delay slot)
5043 and it could cause branches to go out of range. */
5046 (gen_stuff_delay_slot
5047 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
5048 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5050 /* Prevent reorg from undoing our splits. */
5051 gen_block_redirect (jump, bp->address += 2, 2);
5054 /* Fix up ADDR_DIFF_VECs. */
5056 fixup_addr_diff_vecs (rtx first)
5060 for (insn = first; insn; insn = NEXT_INSN (insn))
5062 rtx vec_lab, pat, prev, prevpat, x, braf_label;
5065 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5067 pat = PATTERN (insn);
5068 vec_lab = XEXP (XEXP (pat, 0), 0);
5070 /* Search the matching casesi_jump_2. */
5071 for (prev = vec_lab; ; prev = PREV_INSN (prev))
5075 prevpat = PATTERN (prev);
5076 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5078 x = XVECEXP (prevpat, 0, 1);
5079 if (GET_CODE (x) != USE)
5082 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5085 /* FIXME: This is a bug in the optimizer, but it seems harmless
5086 to just avoid panicing. */
5090 /* Emit the reference label of the braf where it belongs, right after
5091 the casesi_jump_2 (i.e. braf). */
5092 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5093 emit_label_after (braf_label, prev);
5095 /* Fix up the ADDR_DIF_VEC to be relative
5096 to the reference address of the braf. */
5097 XEXP (XEXP (pat, 0), 0) = braf_label;
5101 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5102 a barrier. Return the base 2 logarithm of the desired alignment. */
5104 barrier_align (rtx barrier_or_label)
5106 rtx next = next_real_insn (barrier_or_label), pat, prev;
5107 int slot, credit, jump_to_next = 0;
5112 pat = PATTERN (next);
5114 if (GET_CODE (pat) == ADDR_DIFF_VEC)
5117 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
5118 /* This is a barrier in front of a constant table. */
5121 prev = prev_real_insn (barrier_or_label);
5122 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
5124 pat = PATTERN (prev);
5125 /* If this is a very small table, we want to keep the alignment after
5126 the table to the minimum for proper code alignment. */
5127 return ((TARGET_SMALLCODE
5128 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
5129 <= (unsigned) 1 << (CACHE_LOG - 2)))
5130 ? 1 << TARGET_SHMEDIA : align_jumps_log);
5133 if (TARGET_SMALLCODE)
5136 if (! TARGET_SH2 || ! optimize)
5137 return align_jumps_log;
5139 /* When fixing up pcloads, a constant table might be inserted just before
5140 the basic block that ends with the barrier. Thus, we can't trust the
5141 instruction lengths before that. */
5142 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
5144 /* Check if there is an immediately preceding branch to the insn beyond
5145 the barrier. We must weight the cost of discarding useful information
5146 from the current cache line when executing this branch and there is
5147 an alignment, against that of fetching unneeded insn in front of the
5148 branch target when there is no alignment. */
5150 /* There are two delay_slot cases to consider. One is the simple case
5151 where the preceding branch is to the insn beyond the barrier (simple
5152 delay slot filling), and the other is where the preceding branch has
5153 a delay slot that is a duplicate of the insn after the barrier
5154 (fill_eager_delay_slots) and the branch is to the insn after the insn
5155 after the barrier. */
5157 /* PREV is presumed to be the JUMP_INSN for the barrier under
5158 investigation. Skip to the insn before it. */
5159 prev = prev_real_insn (prev);
5161 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
5162 credit >= 0 && prev && NONJUMP_INSN_P (prev);
5163 prev = prev_real_insn (prev))
5166 if (GET_CODE (PATTERN (prev)) == USE
5167 || GET_CODE (PATTERN (prev)) == CLOBBER)
5169 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
5171 prev = XVECEXP (PATTERN (prev), 0, 1);
5172 if (INSN_UID (prev) == INSN_UID (next))
5174 /* Delay slot was filled with insn at jump target. */
5181 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5183 credit -= get_attr_length (prev);
5187 && JUMP_LABEL (prev))
5191 || next_real_insn (JUMP_LABEL (prev)) == next
5192 /* If relax_delay_slots() decides NEXT was redundant
5193 with some previous instruction, it will have
5194 redirected PREV's jump to the following insn. */
5195 || JUMP_LABEL (prev) == next_nonnote_insn (next)
5196 /* There is no upper bound on redundant instructions
5197 that might have been skipped, but we must not put an
5198 alignment where none had been before. */
5199 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5201 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
5202 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5203 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
5205 rtx pat = PATTERN (prev);
5206 if (GET_CODE (pat) == PARALLEL)
5207 pat = XVECEXP (pat, 0, 0);
5208 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5214 return align_jumps_log;
5217 /* If we are inside a phony loop, almost any kind of label can turn up as the
5218 first one in the loop. Aligning a braf label causes incorrect switch
5219 destination addresses; we can detect braf labels because they are
5220 followed by a BARRIER.
5221 Applying loop alignment to small constant or switch tables is a waste
5222 of space, so we suppress this too. */
5224 sh_loop_align (rtx label)
5229 next = next_nonnote_insn (next);
5230 while (next && LABEL_P (next));
5234 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
5235 || recog_memoized (next) == CODE_FOR_consttable_2)
5238 return align_loops_log;
5241 /* Do a final pass over the function, just before delayed branch
5247 rtx first, insn, mova = NULL_RTX;
5249 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5250 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
5252 first = get_insns ();
5253 max_labelno_before_reorg = max_label_num ();
5255 /* We must split call insns before introducing `mova's. If we're
5256 optimizing, they'll have already been split. Otherwise, make
5257 sure we don't split them too late. */
5259 split_all_insns_noflow ();
5264 /* If relaxing, generate pseudo-ops to associate function calls with
5265 the symbols they call. It does no harm to not generate these
5266 pseudo-ops. However, when we can generate them, it enables to
5267 linker to potentially relax the jsr to a bsr, and eliminate the
5268 register load and, possibly, the constant pool entry. */
5270 mdep_reorg_phase = SH_INSERT_USES_LABELS;
5273 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5274 own purposes. This works because none of the remaining passes
5275 need to look at them.
5277 ??? But it may break in the future. We should use a machine
5278 dependent REG_NOTE, or some other approach entirely. */
5279 for (insn = first; insn; insn = NEXT_INSN (insn))
5285 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5287 remove_note (insn, note);
5291 for (insn = first; insn; insn = NEXT_INSN (insn))
5293 rtx pattern, reg, link, set, scan, dies, label;
5294 int rescan = 0, foundinsn = 0;
5298 pattern = PATTERN (insn);
5300 if (GET_CODE (pattern) == PARALLEL)
5301 pattern = XVECEXP (pattern, 0, 0);
5302 if (GET_CODE (pattern) == SET)
5303 pattern = SET_SRC (pattern);
5305 if (GET_CODE (pattern) != CALL
5306 || !MEM_P (XEXP (pattern, 0)))
5309 reg = XEXP (XEXP (pattern, 0), 0);
5313 reg = sfunc_uses_reg (insn);
5321 /* Try scanning backward to find where the register is set. */
5323 for (scan = PREV_INSN (insn);
5324 scan && !LABEL_P (scan);
5325 scan = PREV_INSN (scan))
5327 if (! INSN_P (scan))
5330 if (! reg_mentioned_p (reg, scan))
5333 if (noncall_uses_reg (reg, scan, &set))
5346 /* The register is set at LINK. */
5348 /* We can only optimize the function call if the register is
5349 being set to a symbol. In theory, we could sometimes
5350 optimize calls to a constant location, but the assembler
5351 and linker do not support that at present. */
5352 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5353 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5356 /* Scan forward from LINK to the place where REG dies, and
5357 make sure that the only insns which use REG are
5358 themselves function calls. */
5360 /* ??? This doesn't work for call targets that were allocated
5361 by reload, since there may not be a REG_DEAD note for the
5365 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5369 /* Don't try to trace forward past a CODE_LABEL if we haven't
5370 seen INSN yet. Ordinarily, we will only find the setting insn
5371 if it is in the same basic block. However,
5372 cross-jumping can insert code labels in between the load and
5373 the call, and can result in situations where a single call
5374 insn may have two targets depending on where we came from. */
5376 if (LABEL_P (scan) && ! foundinsn)
5379 if (! INSN_P (scan))
5382 /* Don't try to trace forward past a JUMP. To optimize
5383 safely, we would have to check that all the
5384 instructions at the jump destination did not use REG. */
5389 if (! reg_mentioned_p (reg, scan))
5392 if (noncall_uses_reg (reg, scan, &scanset))
5399 && (CALL_P (scan) || sfunc_uses_reg (scan)))
5401 /* There is a function call to this register other
5402 than the one we are checking. If we optimize
5403 this call, we need to rescan again below. */
5407 /* ??? We shouldn't have to worry about SCANSET here.
5408 We should just be able to check for a REG_DEAD note
5409 on a function call. However, the REG_DEAD notes are
5410 apparently not dependable around libcalls; c-torture
5411 execute/920501-2 is a test case. If SCANSET is set,
5412 then this insn sets the register, so it must have
5413 died earlier. Unfortunately, this will only handle
5414 the cases in which the register is, in fact, set in a
5417 /* ??? We shouldn't have to use FOUNDINSN here.
5418 This dates back to when we used LOG_LINKS to find
5419 the most recent insn which sets the register. */
5423 || find_reg_note (scan, REG_DEAD, reg)))
5432 /* Either there was a branch, or some insn used REG
5433 other than as a function call address. */
5437 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5438 on the insn which sets the register, and on each call insn
5439 which uses the register. In final_prescan_insn we look for
5440 the REG_LABEL_OPERAND notes, and output the appropriate label
5443 label = gen_label_rtx ();
5444 add_reg_note (link, REG_LABEL_OPERAND, label);
5445 add_reg_note (insn, REG_LABEL_OPERAND, label);
5453 scan = NEXT_INSN (scan);
5456 && reg_mentioned_p (reg, scan))
5457 || ((reg2 = sfunc_uses_reg (scan))
5458 && REGNO (reg2) == REGNO (reg))))
5459 add_reg_note (scan, REG_LABEL_OPERAND, label);
5461 while (scan != dies);
5467 fixup_addr_diff_vecs (first);
5471 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5472 shorten_branches (first);
5475 /* Scan the function looking for move instructions which have to be
5476 changed to pc-relative loads and insert the literal tables. */
5477 label_ref_list_pool = create_alloc_pool ("label references list",
5478 sizeof (struct label_ref_list_d),
5480 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5481 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5485 /* ??? basic block reordering can move a switch table dispatch
5486 below the switch table. Check if that has happened.
5487 We only have the addresses available when optimizing; but then,
5488 this check shouldn't be needed when not optimizing. */
5489 if (!untangle_mova (&num_mova, &mova, insn))
5495 else if (JUMP_P (insn)
5496 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5498 /* ??? loop invariant motion can also move a mova out of a
5499 loop. Since loop does this code motion anyway, maybe we
5500 should wrap UNSPEC_MOVA into a CONST, so that reload can
5503 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5504 || (prev_nonnote_insn (insn)
5505 == XEXP (MOVA_LABELREF (mova), 0))))
5512 /* Some code might have been inserted between the mova and
5513 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5514 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5515 total += get_attr_length (scan);
5517 /* range of mova is 1020, add 4 because pc counts from address of
5518 second instruction after this one, subtract 2 in case pc is 2
5519 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5520 cancels out with alignment effects of the mova itself. */
5523 /* Change the mova into a load, and restart scanning
5524 there. broken_move will then return true for mova. */
5529 if (broken_move (insn)
5530 || (NONJUMP_INSN_P (insn)
5531 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5534 /* Scan ahead looking for a barrier to stick the constant table
5536 rtx barrier = find_barrier (num_mova, mova, insn);
5537 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5538 int need_aligned_label = 0;
5540 if (num_mova && ! mova_p (mova))
5542 /* find_barrier had to change the first mova into a
5543 pcload; thus, we have to start with this new pcload. */
5547 /* Now find all the moves between the points and modify them. */
5548 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5552 if (NONJUMP_INSN_P (scan)
5553 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5554 need_aligned_label = 1;
5555 if (broken_move (scan))
5557 rtx *patp = &PATTERN (scan), pat = *patp;
5561 enum machine_mode mode;
5563 if (GET_CODE (pat) == PARALLEL)
5564 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5565 src = SET_SRC (pat);
5566 dst = SET_DEST (pat);
5567 mode = GET_MODE (dst);
5569 if (mode == SImode && hi_const (src)
5570 && REGNO (dst) != FPUL_REG)
5575 while (GET_CODE (dst) == SUBREG)
5577 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5578 GET_MODE (SUBREG_REG (dst)),
5581 dst = SUBREG_REG (dst);
5583 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5585 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
5587 /* This must be an insn that clobbers r0. */
5588 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5589 XVECLEN (PATTERN (scan), 0)
5591 rtx clobber = *clobberp;
5593 gcc_assert (GET_CODE (clobber) == CLOBBER
5594 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5597 && reg_set_between_p (r0_rtx, last_float_move, scan))
5601 && GET_MODE_SIZE (mode) != 4
5602 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5604 lab = add_constant (src, mode, last_float);
5606 emit_insn_before (gen_mova (lab), scan);
5609 /* There will be a REG_UNUSED note for r0 on
5610 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5611 lest reorg:mark_target_live_regs will not
5612 consider r0 to be used, and we end up with delay
5613 slot insn in front of SCAN that clobbers r0. */
5615 = find_regno_note (last_float_move, REG_UNUSED, 0);
5617 /* If we are not optimizing, then there may not be
5620 PUT_REG_NOTE_KIND (note, REG_INC);
5622 *last_float_addr = r0_inc_rtx;
5624 last_float_move = scan;
5626 newsrc = gen_const_mem (mode,
5627 (((TARGET_SH4 && ! TARGET_FMOVD)
5628 || REGNO (dst) == FPUL_REG)
5631 last_float_addr = &XEXP (newsrc, 0);
5633 /* Remove the clobber of r0. */
5634 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5635 gen_rtx_SCRATCH (Pmode));
5637 /* This is a mova needing a label. Create it. */
5638 else if (GET_CODE (src) == UNSPEC
5639 && XINT (src, 1) == UNSPEC_MOVA
5640 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5642 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5643 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5644 newsrc = gen_rtx_UNSPEC (SImode,
5645 gen_rtvec (1, newsrc),
5650 lab = add_constant (src, mode, 0);
5651 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5652 newsrc = gen_const_mem (mode, newsrc);
5654 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5655 INSN_CODE (scan) = -1;
5658 dump_table (need_aligned_label ? insn : 0, barrier);
5662 free_alloc_pool (label_ref_list_pool);
5663 for (insn = first; insn; insn = NEXT_INSN (insn))
5664 PUT_MODE (insn, VOIDmode);
5666 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5667 INSN_ADDRESSES_FREE ();
5668 split_branches (first);
5670 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5671 also has an effect on the register that holds the address of the sfunc.
5672 Insert an extra dummy insn in front of each sfunc that pretends to
5673 use this register. */
5674 if (flag_delayed_branch)
5676 for (insn = first; insn; insn = NEXT_INSN (insn))
5678 rtx reg = sfunc_uses_reg (insn);
5682 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5686 /* fpscr is not actually a user variable, but we pretend it is for the
5687 sake of the previous optimization passes, since we want it handled like
5688 one. However, we don't have any debugging information for it, so turn
5689 it into a non-user variable now. */
5691 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5693 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5697 get_dest_uid (rtx label, int max_uid)
5699 rtx dest = next_real_insn (label);
5702 /* This can happen for an undefined label. */
5704 dest_uid = INSN_UID (dest);
5705 /* If this is a newly created branch redirection blocking instruction,
5706 we cannot index the branch_uid or insn_addresses arrays with its
5707 uid. But then, we won't need to, because the actual destination is
5708 the following branch. */
5709 while (dest_uid >= max_uid)
5711 dest = NEXT_INSN (dest);
5712 dest_uid = INSN_UID (dest);
5714 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
5719 /* Split condbranches that are out of range. Also add clobbers for
5720 scratch registers that are needed in far jumps.
5721 We do this before delay slot scheduling, so that it can take our
5722 newly created instructions into account. It also allows us to
5723 find branches with common targets more easily. */
5726 split_branches (rtx first)
5729 struct far_branch **uid_branch, *far_branch_list = 0;
5730 int max_uid = get_max_uid ();
5733 /* Find out which branches are out of range. */
5734 shorten_branches (first);
5736 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5737 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5739 for (insn = first; insn; insn = NEXT_INSN (insn))
5740 if (! INSN_P (insn))
5742 else if (INSN_DELETED_P (insn))
5744 /* Shorten_branches would split this instruction again,
5745 so transform it into a note. */
5746 SET_INSN_DELETED (insn);
5748 else if (JUMP_P (insn)
5749 /* Don't mess with ADDR_DIFF_VEC */
5750 && (GET_CODE (PATTERN (insn)) == SET
5751 || GET_CODE (PATTERN (insn)) == RETURN))
5753 enum attr_type type = get_attr_type (insn);
5754 if (type == TYPE_CBRANCH)
5758 if (get_attr_length (insn) > 4)
5760 rtx src = SET_SRC (PATTERN (insn));
5761 rtx olabel = XEXP (XEXP (src, 1), 0);
5762 int addr = INSN_ADDRESSES (INSN_UID (insn));
5764 int dest_uid = get_dest_uid (olabel, max_uid);
5765 struct far_branch *bp = uid_branch[dest_uid];
5767 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5768 the label if the LABEL_NUSES count drops to zero. There is
5769 always a jump_optimize pass that sets these values, but it
5770 proceeds to delete unreferenced code, and then if not
5771 optimizing, to un-delete the deleted instructions, thus
5772 leaving labels with too low uses counts. */
5775 JUMP_LABEL (insn) = olabel;
5776 LABEL_NUSES (olabel)++;
5780 bp = (struct far_branch *) alloca (sizeof *bp);
5781 uid_branch[dest_uid] = bp;
5782 bp->prev = far_branch_list;
5783 far_branch_list = bp;
5785 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5786 LABEL_NUSES (bp->far_label)++;
5790 label = bp->near_label;
5791 if (! label && bp->address - addr >= CONDJUMP_MIN)
5793 rtx block = bp->insert_place;
5795 if (GET_CODE (PATTERN (block)) == RETURN)
5796 block = PREV_INSN (block);
5798 block = gen_block_redirect (block,
5800 label = emit_label_after (gen_label_rtx (),
5802 bp->near_label = label;
5804 else if (label && ! NEXT_INSN (label))
5806 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5807 bp->insert_place = insn;
5809 gen_far_branch (bp);
5813 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5815 bp->near_label = label = gen_label_rtx ();
5816 bp->insert_place = insn;
5819 ok = redirect_jump (insn, label, 0);
5824 /* get_attr_length (insn) == 2 */
5825 /* Check if we have a pattern where reorg wants to redirect
5826 the branch to a label from an unconditional branch that
5828 /* We can't use JUMP_LABEL here because it might be undefined
5829 when not optimizing. */
5830 /* A syntax error might cause beyond to be NULL_RTX. */
5832 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5837 || ((beyond = next_active_insn (beyond))
5838 && JUMP_P (beyond)))
5839 && GET_CODE (PATTERN (beyond)) == SET
5840 && recog_memoized (beyond) == CODE_FOR_jump_compact
5842 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5843 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5845 gen_block_redirect (beyond,
5846 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5849 next = next_active_insn (insn);
5853 || ((next = next_active_insn (next))
5855 && GET_CODE (PATTERN (next)) == SET
5856 && recog_memoized (next) == CODE_FOR_jump_compact
5858 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5859 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5861 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5863 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5865 int addr = INSN_ADDRESSES (INSN_UID (insn));
5868 struct far_branch *bp;
5870 if (type == TYPE_JUMP)
5872 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5873 dest_uid = get_dest_uid (far_label, max_uid);
5876 /* Parse errors can lead to labels outside
5878 if (! NEXT_INSN (far_label))
5883 JUMP_LABEL (insn) = far_label;
5884 LABEL_NUSES (far_label)++;
5886 redirect_jump (insn, NULL_RTX, 1);
5890 bp = uid_branch[dest_uid];
5893 bp = (struct far_branch *) alloca (sizeof *bp);
5894 uid_branch[dest_uid] = bp;
5895 bp->prev = far_branch_list;
5896 far_branch_list = bp;
5898 bp->far_label = far_label;
5900 LABEL_NUSES (far_label)++;
5902 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5903 if (addr - bp->address <= CONDJUMP_MAX)
5904 emit_label_after (bp->near_label, PREV_INSN (insn));
5907 gen_far_branch (bp);
5913 bp->insert_place = insn;
5915 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5917 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5920 /* Generate all pending far branches,
5921 and free our references to the far labels. */
5922 while (far_branch_list)
5924 if (far_branch_list->near_label
5925 && ! NEXT_INSN (far_branch_list->near_label))
5926 gen_far_branch (far_branch_list);
5928 && far_branch_list->far_label
5929 && ! --LABEL_NUSES (far_branch_list->far_label))
5930 delete_insn (far_branch_list->far_label);
5931 far_branch_list = far_branch_list->prev;
5934 /* Instruction length information is no longer valid due to the new
5935 instructions that have been generated. */
5936 init_insn_lengths ();
5939 /* Dump out instruction addresses, which is useful for debugging the
5940 constant pool table stuff.
5942 If relaxing, output the label and pseudo-ops used to link together
5943 calls and the instruction which set the registers. */
5945 /* ??? The addresses printed by this routine for insns are nonsense for
5946 insns which are inside of a sequence where none of the inner insns have
5947 variable length. This is because the second pass of shorten_branches
5948 does not bother to update them. */
5951 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5952 int noperands ATTRIBUTE_UNUSED)
5954 if (TARGET_DUMPISIZE)
5955 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5961 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
5966 pattern = PATTERN (insn);
5967 if (GET_CODE (pattern) == PARALLEL)
5968 pattern = XVECEXP (pattern, 0, 0);
5969 switch (GET_CODE (pattern))
5972 if (GET_CODE (SET_SRC (pattern)) != CALL
5973 && get_attr_type (insn) != TYPE_SFUNC)
5975 targetm.asm_out.internal_label
5976 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5979 /* else FALLTHROUGH */
5981 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5982 CODE_LABEL_NUMBER (XEXP (note, 0)));
5992 /* Dump out any constants accumulated in the final pass. These will
5996 output_jump_label_table (void)
6002 fprintf (asm_out_file, "\t.align 2\n");
6003 for (i = 0; i < pool_size; i++)
6005 pool_node *p = &pool_vector[i];
6007 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6008 CODE_LABEL_NUMBER (p->label));
6009 output_asm_insn (".long %O0", &p->value);
6017 /* A full frame looks like:
6021 [ if current_function_anonymous_args
6034 local-0 <- fp points here. */
6036 /* Number of bytes pushed for anonymous args, used to pass information
6037 between expand_prologue and expand_epilogue. */
6039 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6040 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6041 for an epilogue and a negative value means that it's for a sibcall
6042 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6043 all the registers that are about to be restored, and hence dead. */
6046 output_stack_adjust (int size, rtx reg, int epilogue_p,
6047 HARD_REG_SET *live_regs_mask, bool frame_p)
6049 rtx (*emit_fn) (rtx) = frame_p ? &frame_insn : &emit_insn;
6052 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6054 /* This test is bogus, as output_stack_adjust is used to re-align the
6057 gcc_assert (!(size % align));
6060 if (CONST_OK_FOR_ADD (size))
6061 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
6062 /* Try to do it with two partial adjustments; however, we must make
6063 sure that the stack is properly aligned at all times, in case
6064 an interrupt occurs between the two partial adjustments. */
6065 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6066 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
6068 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6069 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
6075 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
6078 /* If TEMP is invalid, we could temporarily save a general
6079 register to MACL. However, there is currently no need
6080 to handle this case, so just die when we see it. */
6082 || current_function_interrupt
6083 || ! call_really_used_regs[temp] || fixed_regs[temp])
6085 if (temp < 0 && ! current_function_interrupt
6086 && (TARGET_SHMEDIA || epilogue_p >= 0))
6089 COPY_HARD_REG_SET (temps, call_used_reg_set);
6090 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
6094 if (crtl->return_rtx)
6096 enum machine_mode mode;
6097 mode = GET_MODE (crtl->return_rtx);
6098 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6099 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
6101 for (i = 0; i < nreg; i++)
6102 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
6103 if (crtl->calls_eh_return)
6105 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6106 for (i = 0; i <= 3; i++)
6107 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6110 if (TARGET_SHMEDIA && epilogue_p < 0)
6111 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
6112 CLEAR_HARD_REG_BIT (temps, i);
6113 if (epilogue_p <= 0)
6115 for (i = FIRST_PARM_REG;
6116 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6117 CLEAR_HARD_REG_BIT (temps, i);
6118 if (cfun->static_chain_decl != NULL)
6119 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6121 temp = scavenge_reg (&temps);
6123 if (temp < 0 && live_regs_mask)
6127 COPY_HARD_REG_SET (temps, *live_regs_mask);
6128 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6129 temp = scavenge_reg (&temps);
6133 rtx adj_reg, tmp_reg, mem;
6135 /* If we reached here, the most likely case is the (sibcall)
6136 epilogue for non SHmedia. Put a special push/pop sequence
6137 for such case as the last resort. This looks lengthy but
6138 would not be problem because it seems to be very
6141 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
6144 /* ??? There is still the slight possibility that r4 or
6145 r5 have been reserved as fixed registers or assigned
6146 as global registers, and they change during an
6147 interrupt. There are possible ways to handle this:
6149 - If we are adjusting the frame pointer (r14), we can do
6150 with a single temp register and an ordinary push / pop
6152 - Grab any call-used or call-saved registers (i.e. not
6153 fixed or globals) for the temps we need. We might
6154 also grab r14 if we are adjusting the stack pointer.
6155 If we can't find enough available registers, issue
6156 a diagnostic and die - the user must have reserved
6157 way too many registers.
6158 But since all this is rather unlikely to happen and
6159 would require extra testing, we just die if r4 / r5
6160 are not available. */
6161 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6162 && !global_regs[4] && !global_regs[5]);
6164 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6165 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
6166 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
6167 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6168 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
6169 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6170 emit_move_insn (mem, tmp_reg);
6171 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6172 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6173 emit_move_insn (mem, tmp_reg);
6174 emit_move_insn (reg, adj_reg);
6175 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6176 emit_move_insn (adj_reg, mem);
6177 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6178 emit_move_insn (tmp_reg, mem);
6179 /* Tell flow the insns that pop r4/r5 aren't dead. */
6184 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
6186 /* If SIZE is negative, subtract the positive value.
6187 This sometimes allows a constant pool entry to be shared
6188 between prologue and epilogue code. */
6191 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
6192 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
6196 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
6197 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
6200 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6201 gen_rtx_SET (VOIDmode, reg,
6202 gen_rtx_PLUS (SImode, reg,
6212 RTX_FRAME_RELATED_P (x) = 1;
6216 /* Output RTL to push register RN onto the stack. */
6223 x = gen_push_fpul ();
6224 else if (rn == FPSCR_REG)
6225 x = gen_push_fpscr ();
6226 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6227 && FP_OR_XD_REGISTER_P (rn))
6229 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6231 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
6233 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6234 x = gen_push_e (gen_rtx_REG (SFmode, rn));
6236 x = gen_push (gen_rtx_REG (SImode, rn));
6239 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6243 /* Output RTL to pop register RN from the stack. */
6250 x = gen_pop_fpul ();
6251 else if (rn == FPSCR_REG)
6252 x = gen_pop_fpscr ();
6253 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6254 && FP_OR_XD_REGISTER_P (rn))
6256 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6258 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
6260 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6261 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
6263 x = gen_pop (gen_rtx_REG (SImode, rn));
6266 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6269 /* Generate code to push the regs specified in the mask. */
6272 push_regs (HARD_REG_SET *mask, int interrupt_handler)
6274 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
6277 /* Push PR last; this gives better latencies after the prologue, and
6278 candidates for the return delay slot when there are no general
6279 registers pushed. */
6280 for (; i < FIRST_PSEUDO_REGISTER; i++)
6282 /* If this is an interrupt handler, and the SZ bit varies,
6283 and we have to push any floating point register, we need
6284 to switch to the correct precision first. */
6285 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
6286 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
6288 HARD_REG_SET unsaved;
6291 COMPL_HARD_REG_SET (unsaved, *mask);
6292 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6296 && (i != FPSCR_REG || ! skip_fpscr)
6297 && TEST_HARD_REG_BIT (*mask, i))
6299 /* If the ISR has RESBANK attribute assigned, don't push any of
6300 the following registers - R0-R14, MACH, MACL and GBR. */
6301 if (! (sh_cfun_resbank_handler_p ()
6302 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6310 /* Push banked registers last to improve delay slot opportunities. */
6311 if (interrupt_handler)
6312 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6313 if (TEST_HARD_REG_BIT (*mask, i))
6316 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6317 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
6321 /* Calculate how much extra space is needed to save all callee-saved
6323 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6326 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6329 int stack_space = 0;
6330 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6332 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6333 if ((! call_really_used_regs[reg] || interrupt_handler)
6334 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6335 /* Leave space to save this target register on the stack,
6336 in case target register allocation wants to use it. */
6337 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6341 /* Decide whether we should reserve space for callee-save target registers,
6342 in case target register allocation wants to use them. REGS_SAVED is
6343 the space, in bytes, that is already required for register saves.
6344 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6347 shmedia_reserve_space_for_target_registers_p (int regs_saved,
6348 HARD_REG_SET *live_regs_mask)
6352 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6355 /* Decide how much space to reserve for callee-save target registers
6356 in case target register allocation wants to use them.
6357 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6360 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6362 if (shmedia_space_reserved_for_target_registers)
6363 return shmedia_target_regs_stack_space (live_regs_mask);
6368 /* Work out the registers which need to be saved, both as a mask and a
6369 count of saved words. Return the count.
6371 If doing a pragma interrupt function, then push all regs used by the
6372 function, and if we call another function (we can tell by looking at PR),
6373 make sure that all the regs it clobbers are safe too. */
6376 calc_live_regs (HARD_REG_SET *live_regs_mask)
6381 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6382 bool nosave_low_regs;
6383 int pr_live, has_call;
6385 attrs = DECL_ATTRIBUTES (current_function_decl);
6386 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6387 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6388 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6389 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6391 CLEAR_HARD_REG_SET (*live_regs_mask);
6392 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6393 && df_regs_ever_live_p (FPSCR_REG))
6394 target_flags &= ~MASK_FPU_SINGLE;
6395 /* If we can save a lot of saves by switching to double mode, do that. */
6396 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
6397 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6398 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6399 && (! call_really_used_regs[reg]
6400 || interrupt_handler)
6403 target_flags &= ~MASK_FPU_SINGLE;
6406 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6407 knows how to use it. That means the pseudo originally allocated for
6408 the initial value can become the PR_MEDIA_REG hard register, as seen for
6409 execute/20010122-1.c:test9. */
6411 /* ??? this function is called from initial_elimination_offset, hence we
6412 can't use the result of sh_media_register_for_return here. */
6413 pr_live = sh_pr_n_sets ();
6416 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6417 pr_live = (pr_initial
6418 ? (!REG_P (pr_initial)
6419 || REGNO (pr_initial) != (PR_REG))
6420 : df_regs_ever_live_p (PR_REG));
6421 /* For Shcompact, if not optimizing, we end up with a memory reference
6422 using the return address pointer for __builtin_return_address even
6423 though there is no actual need to put the PR register on the stack. */
6424 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
6426 /* Force PR to be live if the prologue has to call the SHmedia
6427 argument decoder or register saver. */
6428 if (TARGET_SHCOMPACT
6429 && ((crtl->args.info.call_cookie
6430 & ~ CALL_COOKIE_RET_TRAMP (1))
6431 || crtl->saves_all_registers))
6433 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
6434 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
6436 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
6439 ? (/* Need to save all the regs ever live. */
6440 (df_regs_ever_live_p (reg)
6441 || (call_really_used_regs[reg]
6442 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6443 || reg == PIC_OFFSET_TABLE_REGNUM)
6445 || (TARGET_SHMEDIA && has_call
6446 && REGISTER_NATURAL_MODE (reg) == SImode
6447 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
6448 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6449 && reg != RETURN_ADDRESS_POINTER_REGNUM
6450 && reg != T_REG && reg != GBR_REG
6451 /* Push fpscr only on targets which have FPU */
6452 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6453 : (/* Only push those regs which are used and need to be saved. */
6456 && crtl->args.info.call_cookie
6457 && reg == PIC_OFFSET_TABLE_REGNUM)
6458 || (df_regs_ever_live_p (reg)
6459 && ((!call_really_used_regs[reg]
6460 && !(reg != PIC_OFFSET_TABLE_REGNUM
6461 && fixed_regs[reg] && call_used_regs[reg]))
6462 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6463 || (crtl->calls_eh_return
6464 && (reg == EH_RETURN_DATA_REGNO (0)
6465 || reg == EH_RETURN_DATA_REGNO (1)
6466 || reg == EH_RETURN_DATA_REGNO (2)
6467 || reg == EH_RETURN_DATA_REGNO (3)))
6468 || ((reg == MACL_REG || reg == MACH_REG)
6469 && df_regs_ever_live_p (reg)
6470 && sh_cfun_attr_renesas_p ())
6473 SET_HARD_REG_BIT (*live_regs_mask, reg);
6474 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6476 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6477 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6479 if (FP_REGISTER_P (reg))
6481 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6483 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6484 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6487 else if (XD_REGISTER_P (reg))
6489 /* Must switch to double mode to access these registers. */
6490 target_flags &= ~MASK_FPU_SINGLE;
6494 if (nosave_low_regs && reg == R8_REG)
6497 /* If we have a target register optimization pass after prologue / epilogue
6498 threading, we need to assume all target registers will be live even if
6500 if (flag_branch_target_load_optimize2
6501 && TARGET_SAVE_ALL_TARGET_REGS
6502 && shmedia_space_reserved_for_target_registers)
6503 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6504 if ((! call_really_used_regs[reg] || interrupt_handler)
6505 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6507 SET_HARD_REG_BIT (*live_regs_mask, reg);
6508 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6510 /* If this is an interrupt handler, we don't have any call-clobbered
6511 registers we can conveniently use for target register save/restore.
6512 Make sure we save at least one general purpose register when we need
6513 to save target registers. */
6514 if (interrupt_handler
6515 && hard_reg_set_intersect_p (*live_regs_mask,
6516 reg_class_contents[TARGET_REGS])
6517 && ! hard_reg_set_intersect_p (*live_regs_mask,
6518 reg_class_contents[GENERAL_REGS]))
6520 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6521 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6527 /* Code to generate prologue and epilogue sequences */
6529 /* PUSHED is the number of bytes that are being pushed on the
6530 stack for register saves. Return the frame size, padded
6531 appropriately so that the stack stays properly aligned. */
6532 static HOST_WIDE_INT
6533 rounded_frame_size (int pushed)
6535 HOST_WIDE_INT size = get_frame_size ();
6536 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6538 return ((size + pushed + align - 1) & -align) - pushed;
6541 /* Choose a call-clobbered target-branch register that remains
6542 unchanged along the whole function. We set it up as the return
6543 value in the prologue. */
6545 sh_media_register_for_return (void)
6550 if (! current_function_is_leaf)
6552 if (lookup_attribute ("interrupt_handler",
6553 DECL_ATTRIBUTES (current_function_decl)))
6555 if (sh_cfun_interrupt_handler_p ())
6558 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6560 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6561 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6567 /* The maximum registers we need to save are:
6568 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6569 - 32 floating point registers (for each pair, we save none,
6570 one single precision value, or a double precision value).
6571 - 8 target registers
6572 - add 1 entry for a delimiter. */
6573 #define MAX_SAVED_REGS (62+32+8)
6575 typedef struct save_entry_s
6584 /* There will be a delimiter entry with VOIDmode both at the start and the
6585 end of a filled in schedule. The end delimiter has the offset of the
6586 save with the smallest (i.e. most negative) offset. */
6587 typedef struct save_schedule_s
6589 save_entry entries[MAX_SAVED_REGS + 2];
6590 int temps[MAX_TEMPS+1];
6593 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6594 use reverse order. Returns the last entry written to (not counting
6595 the delimiter). OFFSET_BASE is a number to be added to all offset
6599 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6603 save_entry *entry = schedule->entries;
6607 if (! current_function_interrupt)
6608 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6609 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6610 && ! FUNCTION_ARG_REGNO_P (i)
6611 && i != FIRST_RET_REG
6612 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6613 && ! (crtl->calls_eh_return
6614 && (i == EH_RETURN_STACKADJ_REGNO
6615 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6616 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6617 schedule->temps[tmpx++] = i;
6619 entry->mode = VOIDmode;
6620 entry->offset = offset_base;
6622 /* We loop twice: first, we save 8-byte aligned registers in the
6623 higher addresses, that are known to be aligned. Then, we
6624 proceed to saving 32-bit registers that don't need 8-byte
6626 If this is an interrupt function, all registers that need saving
6627 need to be saved in full. moreover, we need to postpone saving
6628 target registers till we have saved some general purpose registers
6629 we can then use as scratch registers. */
6630 offset = offset_base;
6631 for (align = 1; align >= 0; align--)
6633 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6634 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6636 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6639 if (current_function_interrupt)
6641 if (TARGET_REGISTER_P (i))
6643 if (GENERAL_REGISTER_P (i))
6646 if (mode == SFmode && (i % 2) == 1
6647 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6648 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6655 /* If we're doing the aligned pass and this is not aligned,
6656 or we're doing the unaligned pass and this is aligned,
6658 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6662 if (current_function_interrupt
6663 && GENERAL_REGISTER_P (i)
6664 && tmpx < MAX_TEMPS)
6665 schedule->temps[tmpx++] = i;
6667 offset -= GET_MODE_SIZE (mode);
6670 entry->offset = offset;
6673 if (align && current_function_interrupt)
6674 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6675 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6677 offset -= GET_MODE_SIZE (DImode);
6679 entry->mode = DImode;
6680 entry->offset = offset;
6685 entry->mode = VOIDmode;
6686 entry->offset = offset;
6687 schedule->temps[tmpx] = -1;
6692 sh_expand_prologue (void)
6694 HARD_REG_SET live_regs_mask;
6697 int save_flags = target_flags;
6700 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6702 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6704 /* We have pretend args if we had an object sent partially in registers
6705 and partially on the stack, e.g. a large structure. */
6706 pretend_args = crtl->args.pretend_args_size;
6707 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6708 && (NPARM_REGS(SImode)
6709 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6711 /* Dwarf2 module doesn't expect frame related insns here. */
6712 output_stack_adjust (-pretend_args
6713 - crtl->args.info.stack_regs * 8,
6714 stack_pointer_rtx, 0, NULL, false);
6716 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6717 /* We're going to use the PIC register to load the address of the
6718 incoming-argument decoder and/or of the return trampoline from
6719 the GOT, so make sure the PIC register is preserved and
6721 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6723 if (TARGET_SHCOMPACT
6724 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6728 /* First, make all registers with incoming arguments that will
6729 be pushed onto the stack live, so that register renaming
6730 doesn't overwrite them. */
6731 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6732 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6733 >= NPARM_REGS (SImode) - reg)
6734 for (; reg < NPARM_REGS (SImode); reg++)
6735 emit_insn (gen_shcompact_preserve_incoming_args
6736 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6737 else if (CALL_COOKIE_INT_REG_GET
6738 (crtl->args.info.call_cookie, reg) == 1)
6739 emit_insn (gen_shcompact_preserve_incoming_args
6740 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6742 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6744 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6745 GEN_INT (crtl->args.info.call_cookie));
6746 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6747 gen_rtx_REG (SImode, R0_REG));
6749 else if (TARGET_SHMEDIA)
6751 int tr = sh_media_register_for_return ();
6754 emit_move_insn (gen_rtx_REG (DImode, tr),
6755 gen_rtx_REG (DImode, PR_MEDIA_REG));
6758 /* Emit the code for SETUP_VARARGS. */
6761 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6763 /* Push arg regs as if they'd been provided by caller in stack. */
6764 for (i = 0; i < NPARM_REGS(SImode); i++)
6766 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6769 if (i >= (NPARM_REGS(SImode)
6770 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6778 /* If we're supposed to switch stacks at function entry, do so now. */
6782 /* The argument specifies a variable holding the address of the
6783 stack the interrupt function should switch to/from at entry/exit. */
6784 tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr));
6786 = ggc_strdup (TREE_STRING_POINTER (arg));
6787 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6789 lab = add_constant (sp_switch, SImode, 0);
6790 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
6791 newsrc = gen_const_mem (SImode, newsrc);
6793 emit_insn (gen_sp_switch_1 (newsrc));
6796 d = calc_live_regs (&live_regs_mask);
6797 /* ??? Maybe we could save some switching if we can move a mode switch
6798 that already happens to be at the function start into the prologue. */
6799 if (target_flags != save_flags && ! current_function_interrupt)
6800 emit_insn (gen_toggle_sz ());
6804 int offset_base, offset;
6806 int offset_in_r0 = -1;
6808 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6809 int total_size, save_size;
6810 save_schedule schedule;
6814 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6815 && ! current_function_interrupt)
6816 r0 = gen_rtx_REG (Pmode, R0_REG);
6818 /* D is the actual number of bytes that we need for saving registers,
6819 however, in initial_elimination_offset we have committed to using
6820 an additional TREGS_SPACE amount of bytes - in order to keep both
6821 addresses to arguments supplied by the caller and local variables
6822 valid, we must keep this gap. Place it between the incoming
6823 arguments and the actually saved registers in a bid to optimize
6824 locality of reference. */
6825 total_size = d + tregs_space;
6826 total_size += rounded_frame_size (total_size);
6827 save_size = total_size - rounded_frame_size (d);
6828 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6829 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6830 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6832 /* If adjusting the stack in a single step costs nothing extra, do so.
6833 I.e. either if a single addi is enough, or we need a movi anyway,
6834 and we don't exceed the maximum offset range (the test for the
6835 latter is conservative for simplicity). */
6837 && (CONST_OK_FOR_I10 (-total_size)
6838 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6839 && total_size <= 2044)))
6840 d_rounding = total_size - save_size;
6842 offset_base = d + d_rounding;
6844 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6847 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6848 tmp_pnt = schedule.temps;
6849 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6851 enum machine_mode mode = (enum machine_mode) entry->mode;
6852 unsigned int reg = entry->reg;
6853 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6856 offset = entry->offset;
6858 reg_rtx = gen_rtx_REG (mode, reg);
6860 mem_rtx = gen_frame_mem (mode,
6861 gen_rtx_PLUS (Pmode,
6865 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6871 if (HAVE_PRE_DECREMENT
6872 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6873 || mem_rtx == NULL_RTX
6874 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6876 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6878 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
6883 offset += GET_MODE_SIZE (mode);
6887 if (mem_rtx != NULL_RTX)
6890 if (offset_in_r0 == -1)
6892 emit_move_insn (r0, GEN_INT (offset));
6893 offset_in_r0 = offset;
6895 else if (offset != offset_in_r0)
6900 GEN_INT (offset - offset_in_r0)));
6901 offset_in_r0 += offset - offset_in_r0;
6904 if (pre_dec != NULL_RTX)
6910 (Pmode, r0, stack_pointer_rtx));
6914 offset -= GET_MODE_SIZE (mode);
6915 offset_in_r0 -= GET_MODE_SIZE (mode);
6920 mem_rtx = gen_frame_mem (mode, r0);
6922 mem_rtx = gen_frame_mem (mode,
6923 gen_rtx_PLUS (Pmode,
6927 /* We must not use an r0-based address for target-branch
6928 registers or for special registers without pre-dec
6929 memory addresses, since we store their values in r0
6931 gcc_assert (!TARGET_REGISTER_P (reg)
6932 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6933 || mem_rtx == pre_dec));
6936 orig_reg_rtx = reg_rtx;
6937 if (TARGET_REGISTER_P (reg)
6938 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6939 && mem_rtx != pre_dec))
6941 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6943 emit_move_insn (tmp_reg, reg_rtx);
6945 if (REGNO (tmp_reg) == R0_REG)
6949 gcc_assert (!refers_to_regno_p
6950 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6953 if (*++tmp_pnt <= 0)
6954 tmp_pnt = schedule.temps;
6961 /* Mark as interesting for dwarf cfi generator */
6962 insn = emit_move_insn (mem_rtx, reg_rtx);
6963 RTX_FRAME_RELATED_P (insn) = 1;
6964 /* If we use an intermediate register for the save, we can't
6965 describe this exactly in cfi as a copy of the to-be-saved
6966 register into the temporary register and then the temporary
6967 register on the stack, because the temporary register can
6968 have a different natural size than the to-be-saved register.
6969 Thus, we gloss over the intermediate copy and pretend we do
6970 a direct save from the to-be-saved register. */
6971 if (REGNO (reg_rtx) != reg)
6975 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6976 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6979 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6981 rtx reg_rtx = gen_rtx_REG (mode, reg);
6983 rtx mem_rtx = gen_frame_mem (mode,
6984 gen_rtx_PLUS (Pmode,
6988 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6989 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6994 gcc_assert (entry->offset == d_rounding);
6997 push_regs (&live_regs_mask, current_function_interrupt);
6999 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7000 emit_insn (gen_GOTaddr2picreg ());
7002 if (SHMEDIA_REGS_STACK_ADJUST ())
7004 /* This must NOT go through the PLT, otherwise mach and macl
7005 may be clobbered. */
7006 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7008 ? "__GCC_push_shmedia_regs"
7009 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
7010 emit_insn (gen_shmedia_save_restore_regs_compact
7011 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
7014 if (target_flags != save_flags && ! current_function_interrupt)
7015 emit_insn (gen_toggle_sz ());
7017 target_flags = save_flags;
7019 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
7020 stack_pointer_rtx, 0, NULL, true);
7022 if (frame_pointer_needed)
7023 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
7025 if (TARGET_SHCOMPACT
7026 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
7028 /* This must NOT go through the PLT, otherwise mach and macl
7029 may be clobbered. */
7030 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7031 "__GCC_shcompact_incoming_args", SFUNC_GOT);
7032 emit_insn (gen_shcompact_incoming_args ());
7037 sh_expand_epilogue (bool sibcall_p)
7039 HARD_REG_SET live_regs_mask;
7043 int save_flags = target_flags;
7044 int frame_size, save_size;
7045 int fpscr_deferred = 0;
7046 int e = sibcall_p ? -1 : 1;
7048 d = calc_live_regs (&live_regs_mask);
7051 frame_size = rounded_frame_size (d);
7055 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7057 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
7058 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7059 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
7061 total_size = d + tregs_space;
7062 total_size += rounded_frame_size (total_size);
7063 save_size = total_size - frame_size;
7065 /* If adjusting the stack in a single step costs nothing extra, do so.
7066 I.e. either if a single addi is enough, or we need a movi anyway,
7067 and we don't exceed the maximum offset range (the test for the
7068 latter is conservative for simplicity). */
7070 && ! frame_pointer_needed
7071 && (CONST_OK_FOR_I10 (total_size)
7072 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
7073 && total_size <= 2044)))
7074 d_rounding = frame_size;
7076 frame_size -= d_rounding;
7079 if (frame_pointer_needed)
7081 /* We must avoid scheduling the epilogue with previous basic blocks.
7082 See PR/18032 and PR/40313. */
7083 emit_insn (gen_blockage ());
7084 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7085 &live_regs_mask, false);
7087 /* We must avoid moving the stack pointer adjustment past code
7088 which reads from the local frame, else an interrupt could
7089 occur after the SP adjustment and clobber data in the local
7091 emit_insn (gen_blockage ());
7092 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
7094 else if (frame_size)
7096 /* We must avoid moving the stack pointer adjustment past code
7097 which reads from the local frame, else an interrupt could
7098 occur after the SP adjustment and clobber data in the local
7100 emit_insn (gen_blockage ());
7101 output_stack_adjust (frame_size, stack_pointer_rtx, e,
7102 &live_regs_mask, false);
7105 if (SHMEDIA_REGS_STACK_ADJUST ())
7107 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7109 ? "__GCC_pop_shmedia_regs"
7110 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
7111 /* This must NOT go through the PLT, otherwise mach and macl
7112 may be clobbered. */
7113 emit_insn (gen_shmedia_save_restore_regs_compact
7114 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7117 /* Pop all the registers. */
7119 if (target_flags != save_flags && ! current_function_interrupt)
7120 emit_insn (gen_toggle_sz ());
7123 int offset_base, offset;
7124 int offset_in_r0 = -1;
7126 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
7127 save_schedule schedule;
7131 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
7132 offset_base = -entry[1].offset + d_rounding;
7133 tmp_pnt = schedule.temps;
7134 for (; entry->mode != VOIDmode; entry--)
7136 enum machine_mode mode = (enum machine_mode) entry->mode;
7137 int reg = entry->reg;
7138 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
7140 offset = offset_base + entry->offset;
7141 reg_rtx = gen_rtx_REG (mode, reg);
7143 mem_rtx = gen_frame_mem (mode,
7144 gen_rtx_PLUS (Pmode,
7148 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7151 if (HAVE_POST_INCREMENT
7152 && (offset == offset_in_r0
7153 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
7154 && mem_rtx == NULL_RTX)
7155 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7157 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
7159 if (!memory_address_p (mode, XEXP (post_inc, 0)))
7160 post_inc = NULL_RTX;
7165 if (mem_rtx != NULL_RTX)
7168 if (offset_in_r0 == -1)
7170 emit_move_insn (r0, GEN_INT (offset));
7171 offset_in_r0 = offset;
7173 else if (offset != offset_in_r0)
7178 GEN_INT (offset - offset_in_r0)));
7179 offset_in_r0 += offset - offset_in_r0;
7182 if (post_inc != NULL_RTX)
7188 (Pmode, r0, stack_pointer_rtx));
7194 offset_in_r0 += GET_MODE_SIZE (mode);
7197 mem_rtx = gen_frame_mem (mode, r0);
7199 mem_rtx = gen_frame_mem (mode,
7200 gen_rtx_PLUS (Pmode,
7204 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7205 || mem_rtx == post_inc);
7208 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7209 && mem_rtx != post_inc)
7211 insn = emit_move_insn (r0, mem_rtx);
7214 else if (TARGET_REGISTER_P (reg))
7216 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
7218 /* Give the scheduler a bit of freedom by using up to
7219 MAX_TEMPS registers in a round-robin fashion. */
7220 insn = emit_move_insn (tmp_reg, mem_rtx);
7223 tmp_pnt = schedule.temps;
7226 insn = emit_move_insn (reg_rtx, mem_rtx);
7229 gcc_assert (entry->offset + offset_base == d + d_rounding);
7231 else /* ! TARGET_SH5 */
7236 /* For an ISR with RESBANK attribute assigned, don't pop PR
7238 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7239 && !sh_cfun_resbank_handler_p ())
7241 if (!frame_pointer_needed)
7242 emit_insn (gen_blockage ());
7246 /* Banked registers are poped first to avoid being scheduled in the
7247 delay slot. RTE switches banks before the ds instruction. */
7248 if (current_function_interrupt)
7250 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7251 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7252 pop (LAST_BANKED_REG - i);
7254 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7257 last_reg = FIRST_PSEUDO_REGISTER;
7259 for (i = 0; i < last_reg; i++)
7261 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
7263 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
7264 && hard_reg_set_intersect_p (live_regs_mask,
7265 reg_class_contents[DF_REGS]))
7267 /* For an ISR with RESBANK attribute assigned, don't pop
7268 following registers, R0-R14, MACH, MACL and GBR. */
7269 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7270 && ! (sh_cfun_resbank_handler_p ()
7271 && ((j >= FIRST_GENERAL_REG
7272 && j < LAST_GENERAL_REG)
7278 if (j == FIRST_FP_REG && fpscr_deferred)
7282 if (target_flags != save_flags && ! current_function_interrupt)
7283 emit_insn (gen_toggle_sz ());
7284 target_flags = save_flags;
7286 output_stack_adjust (crtl->args.pretend_args_size
7287 + save_size + d_rounding
7288 + crtl->args.info.stack_regs * 8,
7289 stack_pointer_rtx, e, NULL, false);
7291 if (crtl->calls_eh_return)
7292 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7293 EH_RETURN_STACKADJ_RTX));
7295 /* Switch back to the normal stack if necessary. */
7296 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
7297 emit_insn (gen_sp_switch_2 ());
7299 /* Tell flow the insn that pops PR isn't dead. */
7300 /* PR_REG will never be live in SHmedia mode, and we don't need to
7301 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7302 by the return pattern. */
7303 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7304 emit_use (gen_rtx_REG (SImode, PR_REG));
7307 static int sh_need_epilogue_known = 0;
7310 sh_need_epilogue (void)
7312 if (! sh_need_epilogue_known)
7317 sh_expand_epilogue (0);
7318 epilogue = get_insns ();
7320 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
7322 return sh_need_epilogue_known > 0;
7325 /* Emit code to change the current function's return address to RA.
7326 TEMP is available as a scratch register, if needed. */
7329 sh_set_return_address (rtx ra, rtx tmp)
7331 HARD_REG_SET live_regs_mask;
7333 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7336 d = calc_live_regs (&live_regs_mask);
7338 /* If pr_reg isn't life, we can set it (or the register given in
7339 sh_media_register_for_return) directly. */
7340 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7346 int rr_regno = sh_media_register_for_return ();
7351 rr = gen_rtx_REG (DImode, rr_regno);
7354 rr = gen_rtx_REG (SImode, pr_reg);
7356 emit_insn (GEN_MOV (rr, ra));
7357 /* Tell flow the register for return isn't dead. */
7365 save_schedule schedule;
7368 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7369 offset = entry[1].offset;
7370 for (; entry->mode != VOIDmode; entry--)
7371 if (entry->reg == pr_reg)
7374 /* We can't find pr register. */
7378 offset = entry->offset - offset;
7379 pr_offset = (rounded_frame_size (d) + offset
7380 + SHMEDIA_REGS_STACK_ADJUST ());
7383 pr_offset = rounded_frame_size (d);
7385 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7386 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7388 tmp = gen_frame_mem (Pmode, tmp);
7389 emit_insn (GEN_MOV (tmp, ra));
7390 /* Tell this store isn't dead. */
7394 /* Clear variables at function end. */
7397 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7398 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7400 sh_need_epilogue_known = 0;
7404 sh_builtin_saveregs (void)
7406 /* First unnamed integer register. */
7407 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7408 /* Number of integer registers we need to save. */
7409 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7410 /* First unnamed SFmode float reg */
7411 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7412 /* Number of SFmode float regs to save. */
7413 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7416 alias_set_type alias_set;
7422 int pushregs = n_intregs;
7424 while (pushregs < NPARM_REGS (SImode) - 1
7425 && (CALL_COOKIE_INT_REG_GET
7426 (crtl->args.info.call_cookie,
7427 NPARM_REGS (SImode) - pushregs)
7430 crtl->args.info.call_cookie
7431 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7436 if (pushregs == NPARM_REGS (SImode))
7437 crtl->args.info.call_cookie
7438 |= (CALL_COOKIE_INT_REG (0, 1)
7439 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7441 crtl->args.info.call_cookie
7442 |= CALL_COOKIE_STACKSEQ (pushregs);
7444 crtl->args.pretend_args_size += 8 * n_intregs;
7446 if (TARGET_SHCOMPACT)
7450 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7452 error ("__builtin_saveregs not supported by this subtarget");
7459 /* Allocate block of memory for the regs. */
7460 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7461 Or can assign_stack_local accept a 0 SIZE argument? */
7462 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7465 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7466 else if (n_floatregs & 1)
7470 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7471 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7472 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7473 regbuf = change_address (regbuf, BLKmode, addr);
7475 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7479 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7480 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7481 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7482 emit_insn (gen_andsi3 (addr, addr, mask));
7483 regbuf = change_address (regbuf, BLKmode, addr);
7486 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7487 alias_set = get_varargs_alias_set ();
7488 set_mem_alias_set (regbuf, alias_set);
7491 This is optimized to only save the regs that are necessary. Explicitly
7492 named args need not be saved. */
7494 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7495 adjust_address (regbuf, BLKmode,
7496 n_floatregs * UNITS_PER_WORD),
7500 /* Return the address of the regbuf. */
7501 return XEXP (regbuf, 0);
7504 This is optimized to only save the regs that are necessary. Explicitly
7505 named args need not be saved.
7506 We explicitly build a pointer to the buffer because it halves the insn
7507 count when not optimizing (otherwise the pointer is built for each reg
7509 We emit the moves in reverse order so that we can use predecrement. */
7511 fpregs = copy_to_mode_reg (Pmode,
7512 plus_constant (XEXP (regbuf, 0),
7513 n_floatregs * UNITS_PER_WORD));
7514 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7517 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7519 emit_insn (gen_addsi3 (fpregs, fpregs,
7520 GEN_INT (-2 * UNITS_PER_WORD)));
7521 mem = change_address (regbuf, DFmode, fpregs);
7522 emit_move_insn (mem,
7523 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7525 regno = first_floatreg;
7528 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7529 mem = change_address (regbuf, SFmode, fpregs);
7530 emit_move_insn (mem,
7531 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7532 - (TARGET_LITTLE_ENDIAN != 0)));
7536 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7540 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7541 mem = change_address (regbuf, SFmode, fpregs);
7542 emit_move_insn (mem,
7543 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7546 /* Return the address of the regbuf. */
7547 return XEXP (regbuf, 0);
7550 /* Define the `__builtin_va_list' type for the ABI. */
7553 sh_build_builtin_va_list (void)
7555 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7558 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7559 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7560 return ptr_type_node;
7562 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7564 f_next_o = build_decl (BUILTINS_LOCATION,
7565 FIELD_DECL, get_identifier ("__va_next_o"),
7567 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7569 get_identifier ("__va_next_o_limit"),
7571 f_next_fp = build_decl (BUILTINS_LOCATION,
7572 FIELD_DECL, get_identifier ("__va_next_fp"),
7574 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7576 get_identifier ("__va_next_fp_limit"),
7578 f_next_stack = build_decl (BUILTINS_LOCATION,
7579 FIELD_DECL, get_identifier ("__va_next_stack"),
7582 DECL_FIELD_CONTEXT (f_next_o) = record;
7583 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7584 DECL_FIELD_CONTEXT (f_next_fp) = record;
7585 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7586 DECL_FIELD_CONTEXT (f_next_stack) = record;
7588 TYPE_FIELDS (record) = f_next_o;
7589 TREE_CHAIN (f_next_o) = f_next_o_limit;
7590 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7591 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7592 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7594 layout_type (record);
7599 /* Implement `va_start' for varargs and stdarg. */
7602 sh_va_start (tree valist, rtx nextarg)
7604 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7605 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7611 expand_builtin_saveregs ();
7612 std_expand_builtin_va_start (valist, nextarg);
7616 if ((! TARGET_SH2E && ! TARGET_SH4)
7617 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7619 std_expand_builtin_va_start (valist, nextarg);
7623 f_next_o = TYPE_FIELDS (va_list_type_node);
7624 f_next_o_limit = TREE_CHAIN (f_next_o);
7625 f_next_fp = TREE_CHAIN (f_next_o_limit);
7626 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7627 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7629 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7631 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7632 valist, f_next_o_limit, NULL_TREE);
7633 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7635 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7636 valist, f_next_fp_limit, NULL_TREE);
7637 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7638 valist, f_next_stack, NULL_TREE);
7640 /* Call __builtin_saveregs. */
7641 u = make_tree (sizetype, expand_builtin_saveregs ());
7642 u = fold_convert (ptr_type_node, u);
7643 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7644 TREE_SIDE_EFFECTS (t) = 1;
7645 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7647 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7652 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7653 size_int (UNITS_PER_WORD * nfp));
7654 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7655 TREE_SIDE_EFFECTS (t) = 1;
7656 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7658 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7659 TREE_SIDE_EFFECTS (t) = 1;
7660 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7662 nint = crtl->args.info.arg_count[SH_ARG_INT];
7667 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7668 size_int (UNITS_PER_WORD * nint));
7669 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7670 TREE_SIDE_EFFECTS (t) = 1;
7671 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7673 u = make_tree (ptr_type_node, nextarg);
7674 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7675 TREE_SIDE_EFFECTS (t) = 1;
7676 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7679 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7680 member, return it. */
7682 find_sole_member (tree type)
7684 tree field, member = NULL_TREE;
7686 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7688 if (TREE_CODE (field) != FIELD_DECL)
7690 if (!DECL_SIZE (field))
7692 if (integer_zerop (DECL_SIZE (field)))
7700 /* Implement `va_arg'. */
7703 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7704 gimple_seq *post_p ATTRIBUTE_UNUSED)
7706 HOST_WIDE_INT size, rsize;
7707 tree tmp, pptr_type_node;
7708 tree addr, lab_over = NULL, result = NULL;
7709 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7713 type = build_pointer_type (type);
7715 size = int_size_in_bytes (type);
7716 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7717 pptr_type_node = build_pointer_type (ptr_type_node);
7719 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7720 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7722 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7723 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7728 f_next_o = TYPE_FIELDS (va_list_type_node);
7729 f_next_o_limit = TREE_CHAIN (f_next_o);
7730 f_next_fp = TREE_CHAIN (f_next_o_limit);
7731 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7732 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7734 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7736 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7737 valist, f_next_o_limit, NULL_TREE);
7738 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7739 valist, f_next_fp, NULL_TREE);
7740 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7741 valist, f_next_fp_limit, NULL_TREE);
7742 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7743 valist, f_next_stack, NULL_TREE);
7745 /* Structures with a single member with a distinct mode are passed
7746 like their member. This is relevant if the latter has a REAL_TYPE
7747 or COMPLEX_TYPE type. */
7749 while (TREE_CODE (eff_type) == RECORD_TYPE
7750 && (member = find_sole_member (eff_type))
7751 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7752 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7753 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7755 tree field_type = TREE_TYPE (member);
7757 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7758 eff_type = field_type;
7761 gcc_assert ((TYPE_ALIGN (eff_type)
7762 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7763 || (TYPE_ALIGN (eff_type)
7764 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7769 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7771 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7772 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7773 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7778 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7781 addr = create_tmp_var (pptr_type_node, NULL);
7782 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7783 lab_over = create_artificial_label (UNKNOWN_LOCATION);
7785 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7789 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7791 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7793 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7794 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7796 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7797 tmp = next_fp_limit;
7798 if (size > 4 && !is_double)
7799 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
7800 unshare_expr (tmp), size_int (4 - size));
7801 tmp = build2 (GE_EXPR, boolean_type_node,
7802 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7803 cmp = build3 (COND_EXPR, void_type_node, tmp,
7804 build1 (GOTO_EXPR, void_type_node,
7805 unshare_expr (lab_false)), NULL_TREE);
7807 gimplify_and_add (cmp, pre_p);
7809 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7810 || (is_double || size == 16))
7812 tmp = fold_convert (sizetype, next_fp_tmp);
7813 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7814 size_int (UNITS_PER_WORD));
7815 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7816 unshare_expr (next_fp_tmp), tmp);
7817 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7820 gimplify_and_add (cmp, pre_p);
7822 #ifdef FUNCTION_ARG_SCmode_WART
7823 if (TYPE_MODE (eff_type) == SCmode
7824 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7826 tree subtype = TREE_TYPE (eff_type);
7830 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7831 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7834 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7835 real = get_initialized_tmp_var (real, pre_p, NULL);
7837 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7838 if (type != eff_type)
7839 result = build1 (VIEW_CONVERT_EXPR, type, result);
7840 result = get_initialized_tmp_var (result, pre_p, NULL);
7842 #endif /* FUNCTION_ARG_SCmode_WART */
7844 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7845 gimplify_and_add (tmp, pre_p);
7847 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7848 gimplify_and_add (tmp, pre_p);
7850 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7851 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7852 gimplify_assign (unshare_expr (next_fp_tmp),
7853 unshare_expr (valist), pre_p);
7855 gimplify_assign (unshare_expr (valist),
7856 unshare_expr (next_fp_tmp), post_p);
7857 valist = next_fp_tmp;
7861 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7862 unshare_expr (next_o), size_int (rsize));
7863 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7864 unshare_expr (next_o_limit));
7865 tmp = build3 (COND_EXPR, void_type_node, tmp,
7866 build1 (GOTO_EXPR, void_type_node,
7867 unshare_expr (lab_false)),
7869 gimplify_and_add (tmp, pre_p);
7871 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7872 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7874 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7875 gimplify_and_add (tmp, pre_p);
7877 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7878 gimplify_and_add (tmp, pre_p);
7880 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7881 gimplify_assign (unshare_expr (next_o),
7882 unshare_expr (next_o_limit), pre_p);
7884 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7885 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7890 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7891 gimplify_and_add (tmp, pre_p);
7895 /* ??? In va-sh.h, there had been code to make values larger than
7896 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7898 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7901 gimplify_assign (result, tmp, pre_p);
7902 result = build1 (NOP_EXPR, TREE_TYPE (result), result);
7903 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7904 gimplify_and_add (tmp, pre_p);
7910 result = build_va_arg_indirect_ref (result);
7915 /* 64 bit floating points memory transfers are paired single precision loads
7916 or store. So DWARF information needs fixing in little endian (unless
7917 PR=SZ=1 in FPSCR). */
7919 sh_dwarf_register_span (rtx reg)
7921 unsigned regno = REGNO (reg);
7923 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
7927 gen_rtx_PARALLEL (VOIDmode,
7929 gen_rtx_REG (SFmode,
7930 DBX_REGISTER_NUMBER (regno+1)),
7931 gen_rtx_REG (SFmode,
7932 DBX_REGISTER_NUMBER (regno))));
7935 static enum machine_mode
7936 sh_promote_function_mode (const_tree type, enum machine_mode mode,
7937 int *punsignedp, const_tree funtype,
7938 int for_return ATTRIBUTE_UNUSED)
7940 if (sh_promote_prototypes (funtype))
7941 return promote_mode (type, mode, punsignedp);
7947 sh_promote_prototypes (const_tree type)
7953 return ! sh_attr_renesas_p (type);
7956 /* Whether an argument must be passed by reference. On SHcompact, we
7957 pretend arguments wider than 32-bits that would have been passed in
7958 registers are passed by reference, so that an SHmedia trampoline
7959 loads them into the full 64-bits registers. */
7962 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7963 const_tree type, bool named)
7965 unsigned HOST_WIDE_INT size;
7968 size = int_size_in_bytes (type);
7970 size = GET_MODE_SIZE (mode);
7972 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7974 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7975 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7976 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7978 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7979 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7986 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7987 const_tree type, bool named)
7989 if (targetm.calls.must_pass_in_stack (mode, type))
7992 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7993 wants to know about pass-by-reference semantics for incoming
7998 if (TARGET_SHCOMPACT)
8000 cum->byref = shcompact_byref (cum, mode, type, named);
8001 return cum->byref != 0;
8008 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8009 const_tree type, bool named ATTRIBUTE_UNUSED)
8011 /* ??? How can it possibly be correct to return true only on the
8012 caller side of the equation? Is there someplace else in the
8013 sh backend that's magically producing the copies? */
8014 return (cum->outgoing
8015 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
8016 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
8020 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8021 tree type, bool named ATTRIBUTE_UNUSED)
8026 && PASS_IN_REG_P (*cum, mode, type)
8027 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
8028 && (ROUND_REG (*cum, mode)
8030 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
8031 : ROUND_ADVANCE (int_size_in_bytes (type)))
8032 > NPARM_REGS (mode)))
8033 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
8035 else if (!TARGET_SHCOMPACT
8036 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8037 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
8039 return words * UNITS_PER_WORD;
8043 /* Define where to put the arguments to a function.
8044 Value is zero to push the argument on the stack,
8045 or a hard register in which to store the argument.
8047 MODE is the argument's machine mode.
8048 TYPE is the data type of the argument (as a tree).
8049 This is null for libcalls where that information may
8051 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8052 the preceding args and about the function being called.
8053 NAMED is nonzero if this argument is a named parameter
8054 (otherwise it is an extra parameter matching an ellipsis).
8056 On SH the first args are normally in registers
8057 and the rest are pushed. Any arg that starts within the first
8058 NPARM_REGS words is at least partially passed in a register unless
8059 its data type forbids. */
8063 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8064 tree type, int named)
8066 if (! TARGET_SH5 && mode == VOIDmode)
8067 return GEN_INT (ca->renesas_abi ? 1 : 0);
8070 && PASS_IN_REG_P (*ca, mode, type)
8071 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8075 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8076 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
8078 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8079 gen_rtx_REG (SFmode,
8081 + (ROUND_REG (*ca, mode) ^ 1)),
8083 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8084 gen_rtx_REG (SFmode,
8086 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
8088 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8091 /* If the alignment of a DF value causes an SF register to be
8092 skipped, we will use that skipped register for the next SF
8094 if ((TARGET_HITACHI || ca->renesas_abi)
8095 && ca->free_single_fp_reg
8097 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8099 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
8100 ^ (mode == SFmode && TARGET_SH4
8101 && TARGET_LITTLE_ENDIAN != 0
8102 && ! TARGET_HITACHI && ! ca->renesas_abi);
8103 return gen_rtx_REG (mode, regno);
8109 if (mode == VOIDmode && TARGET_SHCOMPACT)
8110 return GEN_INT (ca->call_cookie);
8112 /* The following test assumes unnamed arguments are promoted to
8114 if (mode == SFmode && ca->free_single_fp_reg)
8115 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
8117 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
8118 && (named || ! ca->prototype_p)
8119 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
8121 if (! ca->prototype_p && TARGET_SHMEDIA)
8122 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
8124 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
8126 + ca->arg_count[(int) SH_ARG_FLOAT]);
8129 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
8130 && (! TARGET_SHCOMPACT
8131 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
8132 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
8135 return gen_rtx_REG (mode, (FIRST_PARM_REG
8136 + ca->arg_count[(int) SH_ARG_INT]));
8145 /* Update the data in CUM to advance over an argument
8146 of mode MODE and data type TYPE.
8147 (TYPE is null for libcalls where that information may not be
8151 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8152 tree type, int named)
8156 else if (TARGET_SH5)
8158 tree type2 = (ca->byref && type
8161 enum machine_mode mode2 = (ca->byref && type
8164 int dwords = ((ca->byref
8167 ? int_size_in_bytes (type2)
8168 : GET_MODE_SIZE (mode2)) + 7) / 8;
8169 int numregs = MIN (dwords, NPARM_REGS (SImode)
8170 - ca->arg_count[(int) SH_ARG_INT]);
8174 ca->arg_count[(int) SH_ARG_INT] += numregs;
8175 if (TARGET_SHCOMPACT
8176 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
8179 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8181 /* N.B. We want this also for outgoing. */
8182 ca->stack_regs += numregs;
8187 ca->stack_regs += numregs;
8188 ca->byref_regs += numregs;
8192 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8196 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8199 else if (dwords > numregs)
8201 int pushregs = numregs;
8203 if (TARGET_SHCOMPACT)
8204 ca->stack_regs += numregs;
8205 while (pushregs < NPARM_REGS (SImode) - 1
8206 && (CALL_COOKIE_INT_REG_GET
8208 NPARM_REGS (SImode) - pushregs)
8212 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
8216 if (numregs == NPARM_REGS (SImode))
8218 |= CALL_COOKIE_INT_REG (0, 1)
8219 | CALL_COOKIE_STACKSEQ (numregs - 1);
8222 |= CALL_COOKIE_STACKSEQ (numregs);
8225 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
8226 && (named || ! ca->prototype_p))
8228 if (mode2 == SFmode && ca->free_single_fp_reg)
8229 ca->free_single_fp_reg = 0;
8230 else if (ca->arg_count[(int) SH_ARG_FLOAT]
8231 < NPARM_REGS (SFmode))
8234 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
8236 - ca->arg_count[(int) SH_ARG_FLOAT]);
8238 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
8240 if (TARGET_SHCOMPACT && ! ca->prototype_p)
8242 if (ca->outgoing && numregs > 0)
8246 |= (CALL_COOKIE_INT_REG
8247 (ca->arg_count[(int) SH_ARG_INT]
8248 - numregs + ((numfpregs - 2) / 2),
8249 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
8252 while (numfpregs -= 2);
8254 else if (mode2 == SFmode && (named)
8255 && (ca->arg_count[(int) SH_ARG_FLOAT]
8256 < NPARM_REGS (SFmode)))
8257 ca->free_single_fp_reg
8258 = FIRST_FP_PARM_REG - numfpregs
8259 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
8265 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8267 /* Note that we've used the skipped register. */
8268 if (mode == SFmode && ca->free_single_fp_reg)
8270 ca->free_single_fp_reg = 0;
8273 /* When we have a DF after an SF, there's an SF register that get
8274 skipped in order to align the DF value. We note this skipped
8275 register, because the next SF value will use it, and not the
8276 SF that follows the DF. */
8278 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
8280 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
8281 + BASE_ARG_REG (mode));
8285 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
8286 || PASS_IN_REG_P (*ca, mode, type))
8287 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
8288 = (ROUND_REG (*ca, mode)
8290 ? ROUND_ADVANCE (int_size_in_bytes (type))
8291 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
8294 /* The Renesas calling convention doesn't quite fit into this scheme since
8295 the address is passed like an invisible argument, but one that is always
8296 passed in memory. */
8298 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
8300 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8302 return gen_rtx_REG (Pmode, 2);
8305 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8308 sh_return_in_memory (const_tree type, const_tree fndecl)
8312 if (TYPE_MODE (type) == BLKmode)
8313 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
8315 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
8319 return (TYPE_MODE (type) == BLKmode
8320 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8321 && TREE_CODE (type) == RECORD_TYPE));
8325 /* We actually emit the code in sh_expand_prologue. We used to use
8326 a static variable to flag that we need to emit this code, but that
8327 doesn't when inlining, when functions are deferred and then emitted
8328 later. Fortunately, we already have two flags that are part of struct
8329 function that tell if a function uses varargs or stdarg. */
8331 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
8332 enum machine_mode mode,
8334 int *pretend_arg_size,
8335 int second_time ATTRIBUTE_UNUSED)
8337 gcc_assert (cfun->stdarg);
8338 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8340 int named_parm_regs, anon_parm_regs;
8342 named_parm_regs = (ROUND_REG (*ca, mode)
8344 ? ROUND_ADVANCE (int_size_in_bytes (type))
8345 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
8346 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8347 if (anon_parm_regs > 0)
8348 *pretend_arg_size = anon_parm_regs * 4;
8353 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
8359 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
8361 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8365 /* Define the offset between two registers, one to be eliminated, and
8366 the other its replacement, at the start of a routine. */
8369 initial_elimination_offset (int from, int to)
8372 int regs_saved_rounding = 0;
8373 int total_saved_regs_space;
8374 int total_auto_space;
8375 int save_flags = target_flags;
8377 HARD_REG_SET live_regs_mask;
8379 shmedia_space_reserved_for_target_registers = false;
8380 regs_saved = calc_live_regs (&live_regs_mask);
8381 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8383 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8385 shmedia_space_reserved_for_target_registers = true;
8386 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8389 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8390 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8391 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8393 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8394 copy_flags = target_flags;
8395 target_flags = save_flags;
8397 total_saved_regs_space = regs_saved + regs_saved_rounding;
8399 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8400 return total_saved_regs_space + total_auto_space
8401 + crtl->args.info.byref_regs * 8;
8403 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8404 return total_saved_regs_space + total_auto_space
8405 + crtl->args.info.byref_regs * 8;
8407 /* Initial gap between fp and sp is 0. */
8408 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8411 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8412 return rounded_frame_size (0);
8414 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8415 return rounded_frame_size (0);
8417 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8418 && (to == HARD_FRAME_POINTER_REGNUM
8419 || to == STACK_POINTER_REGNUM));
8422 int n = total_saved_regs_space;
8423 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8424 save_schedule schedule;
8427 n += total_auto_space;
8429 /* If it wasn't saved, there's not much we can do. */
8430 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8433 target_flags = copy_flags;
8435 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8436 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8437 if (entry->reg == pr_reg)
8439 target_flags = save_flags;
8440 return entry->offset;
8445 return total_auto_space;
8448 /* Parse the -mfixed-range= option string. */
8450 sh_fix_range (const char *const_str)
8453 char *str, *dash, *comma;
8455 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8456 REG2 are either register names or register numbers. The effect
8457 of this option is to mark the registers in the range from REG1 to
8458 REG2 as ``fixed'' so they won't be used by the compiler. */
8460 i = strlen (const_str);
8461 str = (char *) alloca (i + 1);
8462 memcpy (str, const_str, i + 1);
8466 dash = strchr (str, '-');
8469 warning (0, "value of -mfixed-range must have form REG1-REG2");
8473 comma = strchr (dash + 1, ',');
8477 first = decode_reg_name (str);
8480 warning (0, "unknown register name: %s", str);
8484 last = decode_reg_name (dash + 1);
8487 warning (0, "unknown register name: %s", dash + 1);
8495 warning (0, "%s-%s is an empty range", str, dash + 1);
8499 for (i = first; i <= last; ++i)
8500 fixed_regs[i] = call_used_regs[i] = 1;
8510 /* Insert any deferred function attributes from earlier pragmas. */
8512 sh_insert_attributes (tree node, tree *attributes)
8516 if (TREE_CODE (node) != FUNCTION_DECL)
8519 /* We are only interested in fields. */
8523 /* Append the attributes to the deferred attributes. */
8524 *sh_deferred_function_attributes_tail = *attributes;
8525 attrs = sh_deferred_function_attributes;
8529 /* Some attributes imply or require the interrupt attribute. */
8530 if (!lookup_attribute ("interrupt_handler", attrs)
8531 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8533 /* If we have a trapa_handler, but no interrupt_handler attribute,
8534 insert an interrupt_handler attribute. */
8535 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8536 /* We can't use sh_pr_interrupt here because that's not in the
8539 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8540 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8541 if the interrupt attribute is missing, we ignore the attribute
8543 else if (lookup_attribute ("sp_switch", attrs)
8544 || lookup_attribute ("trap_exit", attrs)
8545 || lookup_attribute ("nosave_low_regs", attrs)
8546 || lookup_attribute ("resbank", attrs))
8550 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8552 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8553 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8554 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8555 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8556 warning (OPT_Wattributes,
8557 "%qE attribute only applies to interrupt functions",
8558 TREE_PURPOSE (attrs));
8561 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8563 tail = &TREE_CHAIN (*tail);
8566 attrs = *attributes;
8570 /* Install the processed list. */
8571 *attributes = attrs;
8573 /* Clear deferred attributes. */
8574 sh_deferred_function_attributes = NULL_TREE;
8575 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8580 /* Supported attributes:
8582 interrupt_handler -- specifies this function is an interrupt handler.
8584 trapa_handler - like above, but don't save all registers.
8586 sp_switch -- specifies an alternate stack for an interrupt handler
8589 trap_exit -- use a trapa to exit an interrupt function instead of
8592 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8593 This is useful on the SH3 and upwards,
8594 which has a separate set of low regs for User and Supervisor modes.
8595 This should only be used for the lowest level of interrupts. Higher levels
8596 of interrupts must save the registers in case they themselves are
8599 renesas -- use Renesas calling/layout conventions (functions and
8602 resbank -- In case of an ISR, use a register bank to save registers
8603 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8606 /* Handle a 'resbank' attribute. */
8608 sh_handle_resbank_handler_attribute (tree * node, tree name,
8609 tree args ATTRIBUTE_UNUSED,
8610 int flags ATTRIBUTE_UNUSED,
8611 bool * no_add_attrs)
8615 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8617 *no_add_attrs = true;
8619 if (TREE_CODE (*node) != FUNCTION_DECL)
8621 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8623 *no_add_attrs = true;
8629 /* Handle an "interrupt_handler" attribute; arguments as in
8630 struct attribute_spec.handler. */
8632 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8633 tree args ATTRIBUTE_UNUSED,
8634 int flags ATTRIBUTE_UNUSED,
8637 if (TREE_CODE (*node) != FUNCTION_DECL)
8639 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8641 *no_add_attrs = true;
8643 else if (TARGET_SHCOMPACT)
8645 error ("attribute interrupt_handler is not compatible with -m5-compact");
8646 *no_add_attrs = true;
8652 /* Handle an 'function_vector' attribute; arguments as in
8653 struct attribute_spec.handler. */
8655 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8656 tree args ATTRIBUTE_UNUSED,
8657 int flags ATTRIBUTE_UNUSED,
8658 bool * no_add_attrs)
8662 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8664 *no_add_attrs = true;
8666 else if (TREE_CODE (*node) != FUNCTION_DECL)
8668 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8670 *no_add_attrs = true;
8672 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8674 /* The argument must be a constant integer. */
8675 warning (OPT_Wattributes,
8676 "%qE attribute argument not an integer constant",
8678 *no_add_attrs = true;
8680 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8682 /* The argument value must be between 0 to 255. */
8683 warning (OPT_Wattributes,
8684 "%qE attribute argument should be between 0 to 255",
8686 *no_add_attrs = true;
8691 /* Returns 1 if current function has been assigned the attribute
8692 'function_vector'. */
8694 sh2a_is_function_vector_call (rtx x)
8696 if (GET_CODE (x) == SYMBOL_REF
8697 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8699 tree tr = SYMBOL_REF_DECL (x);
8701 if (sh2a_function_vector_p (tr))
8708 /* Returns the function vector number, if the the attribute
8709 'function_vector' is assigned, otherwise returns zero. */
8711 sh2a_get_function_vector_number (rtx x)
8716 if ((GET_CODE (x) == SYMBOL_REF)
8717 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8719 t = SYMBOL_REF_DECL (x);
8721 if (TREE_CODE (t) != FUNCTION_DECL)
8724 list = SH_ATTRIBUTES (t);
8727 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8729 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8733 list = TREE_CHAIN (list);
8742 /* Handle an "sp_switch" attribute; arguments as in
8743 struct attribute_spec.handler. */
8745 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8746 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8748 if (TREE_CODE (*node) != FUNCTION_DECL)
8750 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8752 *no_add_attrs = true;
8754 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8756 /* The argument must be a constant string. */
8757 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
8759 *no_add_attrs = true;
8765 /* Handle an "trap_exit" attribute; arguments as in
8766 struct attribute_spec.handler. */
8768 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8769 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8771 if (TREE_CODE (*node) != FUNCTION_DECL)
8773 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8775 *no_add_attrs = true;
8777 /* The argument specifies a trap number to be used in a trapa instruction
8778 at function exit (instead of an rte instruction). */
8779 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8781 /* The argument must be a constant integer. */
8782 warning (OPT_Wattributes, "%qE attribute argument not an "
8783 "integer constant", name);
8784 *no_add_attrs = true;
8791 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8792 tree name ATTRIBUTE_UNUSED,
8793 tree args ATTRIBUTE_UNUSED,
8794 int flags ATTRIBUTE_UNUSED,
8795 bool *no_add_attrs ATTRIBUTE_UNUSED)
8800 /* True if __attribute__((renesas)) or -mrenesas. */
8802 sh_attr_renesas_p (const_tree td)
8809 td = TREE_TYPE (td);
8810 if (td == error_mark_node)
8812 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8816 /* True if __attribute__((renesas)) or -mrenesas, for the current
8819 sh_cfun_attr_renesas_p (void)
8821 return sh_attr_renesas_p (current_function_decl);
8825 sh_cfun_interrupt_handler_p (void)
8827 return (lookup_attribute ("interrupt_handler",
8828 DECL_ATTRIBUTES (current_function_decl))
8832 /* Returns 1 if FUNC has been assigned the attribute
8833 "function_vector". */
8835 sh2a_function_vector_p (tree func)
8838 if (TREE_CODE (func) != FUNCTION_DECL)
8841 list = SH_ATTRIBUTES (func);
8844 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8847 list = TREE_CHAIN (list);
8852 /* Returns TRUE if given tree has the "resbank" attribute. */
8855 sh_cfun_resbank_handler_p (void)
8857 return ((lookup_attribute ("resbank",
8858 DECL_ATTRIBUTES (current_function_decl))
8860 && (lookup_attribute ("interrupt_handler",
8861 DECL_ATTRIBUTES (current_function_decl))
8862 != NULL_TREE) && TARGET_SH2A);
8865 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8868 sh_check_pch_target_flags (int old_flags)
8870 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8871 | MASK_SH_E | MASK_HARD_SH4
8872 | MASK_FPU_SINGLE | MASK_SH4))
8873 return _("created and used with different architectures / ABIs");
8874 if ((old_flags ^ target_flags) & MASK_HITACHI)
8875 return _("created and used with different ABIs");
8876 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8877 return _("created and used with different endianness");
8881 /* Predicates used by the templates. */
8883 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8884 Used only in general_movsrc_operand. */
8887 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8899 /* Nonzero if OP is a floating point value with value 0.0. */
8902 fp_zero_operand (rtx op)
8906 if (GET_MODE (op) != SFmode)
8909 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8910 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8913 /* Nonzero if OP is a floating point value with value 1.0. */
8916 fp_one_operand (rtx op)
8920 if (GET_MODE (op) != SFmode)
8923 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8924 return REAL_VALUES_EQUAL (r, dconst1);
8927 /* In general mode switching is used. If we are
8928 compiling without -mfmovd, movsf_ie isn't taken into account for
8929 mode switching. We could check in machine_dependent_reorg for
8930 cases where we know we are in single precision mode, but there is
8931 interface to find that out during reload, so we must avoid
8932 choosing an fldi alternative during reload and thus failing to
8933 allocate a scratch register for the constant loading. */
8941 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8943 enum rtx_code code = GET_CODE (op);
8944 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8947 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8949 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8951 if (GET_CODE (op) != SYMBOL_REF)
8952 return TLS_MODEL_NONE;
8953 return SYMBOL_REF_TLS_MODEL (op);
8956 /* Return the destination address of a branch. */
8959 branch_dest (rtx branch)
8961 rtx dest = SET_SRC (PATTERN (branch));
8964 if (GET_CODE (dest) == IF_THEN_ELSE)
8965 dest = XEXP (dest, 1);
8966 dest = XEXP (dest, 0);
8967 dest_uid = INSN_UID (dest);
8968 return INSN_ADDRESSES (dest_uid);
8971 /* Return nonzero if REG is not used after INSN.
8972 We assume REG is a reload reg, and therefore does
8973 not live past labels. It may live past calls or jumps though. */
8975 reg_unused_after (rtx reg, rtx insn)
8980 /* If the reg is set by this instruction, then it is safe for our
8981 case. Disregard the case where this is a store to memory, since
8982 we are checking a register used in the store address. */
8983 set = single_set (insn);
8984 if (set && !MEM_P (SET_DEST (set))
8985 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8988 while ((insn = NEXT_INSN (insn)))
8994 code = GET_CODE (insn);
8997 /* If this is a label that existed before reload, then the register
8998 if dead here. However, if this is a label added by reorg, then
8999 the register may still be live here. We can't tell the difference,
9000 so we just ignore labels completely. */
9001 if (code == CODE_LABEL)
9006 if (code == JUMP_INSN)
9009 /* If this is a sequence, we must handle them all at once.
9010 We could have for instance a call that sets the target register,
9011 and an insn in a delay slot that uses the register. In this case,
9012 we must return 0. */
9013 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
9018 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9020 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
9021 rtx set = single_set (this_insn);
9023 if (CALL_P (this_insn))
9025 else if (JUMP_P (this_insn))
9027 if (INSN_ANNULLED_BRANCH_P (this_insn))
9032 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9034 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9036 if (!MEM_P (SET_DEST (set)))
9042 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
9047 else if (code == JUMP_INSN)
9051 set = single_set (insn);
9052 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9054 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9055 return !MEM_P (SET_DEST (set));
9056 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9059 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
9067 static GTY(()) rtx fpscr_rtx;
9069 get_fpscr_rtx (void)
9073 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
9074 REG_USERVAR_P (fpscr_rtx) = 1;
9075 mark_user_reg (fpscr_rtx);
9077 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
9078 mark_user_reg (fpscr_rtx);
9082 static GTY(()) tree fpscr_values;
9085 emit_fpu_switch (rtx scratch, int index)
9089 if (fpscr_values == NULL)
9093 t = build_index_type (integer_one_node);
9094 t = build_array_type (integer_type_node, t);
9095 t = build_decl (BUILTINS_LOCATION,
9096 VAR_DECL, get_identifier ("__fpscr_values"), t);
9097 DECL_ARTIFICIAL (t) = 1;
9098 DECL_IGNORED_P (t) = 1;
9099 DECL_EXTERNAL (t) = 1;
9100 TREE_STATIC (t) = 1;
9101 TREE_PUBLIC (t) = 1;
9107 src = DECL_RTL (fpscr_values);
9108 if (!can_create_pseudo_p ())
9110 emit_move_insn (scratch, XEXP (src, 0));
9112 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
9113 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
9116 src = adjust_address (src, PSImode, index * 4);
9118 dst = get_fpscr_rtx ();
9119 emit_move_insn (dst, src);
9123 emit_sf_insn (rtx pat)
9129 emit_df_insn (rtx pat)
9135 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9137 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9141 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9143 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
9148 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9150 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9154 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9156 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
9160 static rtx get_free_reg (HARD_REG_SET);
9162 /* This function returns a register to use to load the address to load
9163 the fpscr from. Currently it always returns r1 or r7, but when we are
9164 able to use pseudo registers after combine, or have a better mechanism
9165 for choosing a register, it should be done here. */
9166 /* REGS_LIVE is the liveness information for the point for which we
9167 need this allocation. In some bare-bones exit blocks, r1 is live at the
9168 start. We can even have all of r0..r3 being live:
9169 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9170 INSN before which new insns are placed with will clobber the register
9171 we return. If a basic block consists only of setting the return value
9172 register to a pseudo and using that register, the return value is not
9173 live before or after this block, yet we we'll insert our insns right in
9177 get_free_reg (HARD_REG_SET regs_live)
9179 if (! TEST_HARD_REG_BIT (regs_live, 1))
9180 return gen_rtx_REG (Pmode, 1);
9182 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
9183 there shouldn't be anything but a jump before the function end. */
9184 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
9185 return gen_rtx_REG (Pmode, 7);
9188 /* This function will set the fpscr from memory.
9189 MODE is the mode we are setting it to. */
9191 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
9193 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
9194 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
9197 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
9198 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
9201 /* Is the given character a logical line separator for the assembler? */
9202 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
9203 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9207 sh_insn_length_adjustment (rtx insn)
9209 /* Instructions with unfilled delay slots take up an extra two bytes for
9210 the nop in the delay slot. */
9211 if (((NONJUMP_INSN_P (insn)
9212 && GET_CODE (PATTERN (insn)) != USE
9213 && GET_CODE (PATTERN (insn)) != CLOBBER)
9216 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9217 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
9218 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
9219 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
9222 /* SH2e has a bug that prevents the use of annulled branches, so if
9223 the delay slot is not filled, we'll have to put a NOP in it. */
9224 if (sh_cpu_attr == CPU_SH2E
9226 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9227 && GET_CODE (PATTERN (insn)) != ADDR_VEC
9228 && get_attr_type (insn) == TYPE_CBRANCH
9229 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
9232 /* sh-dsp parallel processing insn take four bytes instead of two. */
9234 if (NONJUMP_INSN_P (insn))
9237 rtx body = PATTERN (insn);
9240 int maybe_label = 1;
9242 if (GET_CODE (body) == ASM_INPUT)
9243 templ = XSTR (body, 0);
9244 else if (asm_noperands (body) >= 0)
9246 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
9255 while (c == ' ' || c == '\t');
9256 /* all sh-dsp parallel-processing insns start with p.
9257 The only non-ppi sh insn starting with p is pref.
9258 The only ppi starting with pr is prnd. */
9259 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
9261 /* The repeat pseudo-insn expands two three insns, a total of
9262 six bytes in size. */
9263 else if ((c == 'r' || c == 'R')
9264 && ! strncasecmp ("epeat", templ, 5))
9266 while (c && c != '\n'
9267 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
9269 /* If this is a label, it is obviously not a ppi insn. */
9270 if (c == ':' && maybe_label)
9275 else if (c == '\'' || c == '"')
9280 maybe_label = c != ':';
9288 /* Return TRUE for a valid displacement for the REG+disp addressing
9291 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
9292 into the FRx registers. We implement this by setting the maximum offset
9293 to zero when the value is SFmode. This also restricts loading of SFmode
9294 values into the integer registers, but that can't be helped. */
9296 /* The SH allows a displacement in a QI or HI amode, but only when the
9297 other operand is R0. GCC doesn't handle this very well, so we forgot
9300 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
9301 DI can be any number 0..60. */
9304 sh_legitimate_index_p (enum machine_mode mode, rtx op)
9306 if (CONST_INT_P (op))
9312 /* Check if this the address of an unaligned load / store. */
9313 if (mode == VOIDmode)
9314 return CONST_OK_FOR_I06 (INTVAL (op));
9316 size = GET_MODE_SIZE (mode);
9317 return (!(INTVAL (op) & (size - 1))
9318 && INTVAL (op) >= -512 * size
9319 && INTVAL (op) < 512 * size);
9324 if (GET_MODE_SIZE (mode) == 1
9325 && (unsigned) INTVAL (op) < 4096)
9329 if ((GET_MODE_SIZE (mode) == 4
9330 && (unsigned) INTVAL (op) < 64
9331 && !(INTVAL (op) & 3)
9332 && !(TARGET_SH2E && mode == SFmode))
9333 || (GET_MODE_SIZE (mode) == 4
9334 && (unsigned) INTVAL (op) < 16383
9335 && !(INTVAL (op) & 3) && TARGET_SH2A))
9338 if ((GET_MODE_SIZE (mode) == 8
9339 && (unsigned) INTVAL (op) < 60
9340 && !(INTVAL (op) & 3)
9341 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9342 || ((GET_MODE_SIZE (mode)==8)
9343 && (unsigned) INTVAL (op) < 8192
9344 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9345 && (TARGET_SH2A && mode == DFmode)))
9352 /* Recognize an RTL expression that is a valid memory address for
9354 The MODE argument is the machine mode for the MEM expression
9355 that wants to use this address.
9363 sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9365 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9367 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9369 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9371 else if (GET_CODE (x) == PLUS
9372 && (mode != PSImode || reload_completed))
9374 rtx xop0 = XEXP (x, 0);
9375 rtx xop1 = XEXP (x, 1);
9377 if (GET_MODE_SIZE (mode) <= 8
9378 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9379 && sh_legitimate_index_p (mode, xop1))
9382 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9383 || ((xop0 == stack_pointer_rtx
9384 || xop0 == hard_frame_pointer_rtx)
9385 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9386 || ((xop1 == stack_pointer_rtx
9387 || xop1 == hard_frame_pointer_rtx)
9388 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9389 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9390 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9391 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9392 && TARGET_FMOVD && mode == DFmode)))
9394 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9395 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9397 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9398 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9406 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9407 isn't protected by a PIC unspec. */
9409 nonpic_symbol_mentioned_p (rtx x)
9411 register const char *fmt;
9414 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9415 || GET_CODE (x) == PC)
9418 /* We don't want to look into the possible MEM location of a
9419 CONST_DOUBLE, since we're not going to use it, in general. */
9420 if (GET_CODE (x) == CONST_DOUBLE)
9423 if (GET_CODE (x) == UNSPEC
9424 && (XINT (x, 1) == UNSPEC_PIC
9425 || XINT (x, 1) == UNSPEC_GOT
9426 || XINT (x, 1) == UNSPEC_GOTOFF
9427 || XINT (x, 1) == UNSPEC_GOTPLT
9428 || XINT (x, 1) == UNSPEC_GOTTPOFF
9429 || XINT (x, 1) == UNSPEC_DTPOFF
9430 || XINT (x, 1) == UNSPEC_PLT
9431 || XINT (x, 1) == UNSPEC_SYMOFF
9432 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
9435 fmt = GET_RTX_FORMAT (GET_CODE (x));
9436 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9442 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9443 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9446 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9453 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9454 @GOTOFF in `reg'. */
9456 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9459 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9462 if (GET_CODE (orig) == LABEL_REF
9463 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9466 reg = gen_reg_rtx (Pmode);
9468 emit_insn (gen_symGOTOFF2reg (reg, orig));
9471 else if (GET_CODE (orig) == SYMBOL_REF)
9474 reg = gen_reg_rtx (Pmode);
9476 emit_insn (gen_symGOT2reg (reg, orig));
9482 /* Try machine-dependent ways of modifying an illegitimate address
9483 to be legitimate. If we find one, return the new, valid address.
9484 Otherwise, return X.
9486 For the SH, if X is almost suitable for indexing, but the offset is
9487 out of range, convert it into a normal form so that CSE has a chance
9488 of reducing the number of address registers used. */
9491 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9494 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9496 if (GET_CODE (x) == PLUS
9497 && (GET_MODE_SIZE (mode) == 4
9498 || GET_MODE_SIZE (mode) == 8)
9499 && CONST_INT_P (XEXP (x, 1))
9500 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9502 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9503 && ! (TARGET_SH2E && mode == SFmode))
9505 rtx index_rtx = XEXP (x, 1);
9506 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9509 /* On rare occasions, we might get an unaligned pointer
9510 that is indexed in a way to give an aligned address.
9511 Therefore, keep the lower two bits in offset_base. */
9512 /* Instead of offset_base 128..131 use 124..127, so that
9513 simple add suffices. */
9515 offset_base = ((offset + 4) & ~60) - 4;
9517 offset_base = offset & ~60;
9519 /* Sometimes the normal form does not suit DImode. We
9520 could avoid that by using smaller ranges, but that
9521 would give less optimized code when SImode is
9523 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9525 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9526 GEN_INT (offset_base), NULL_RTX, 0,
9529 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9536 /* Mark the use of a constant in the literal table. If the constant
9537 has multiple labels, make it unique. */
9539 mark_constant_pool_use (rtx x)
9541 rtx insn, lab, pattern;
9546 switch (GET_CODE (x))
9556 /* Get the first label in the list of labels for the same constant
9557 and delete another labels in the list. */
9559 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
9562 || LABEL_REFS (insn) != NEXT_INSN (insn))
9567 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9568 INSN_DELETED_P (insn) = 1;
9570 /* Mark constants in a window. */
9571 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
9573 if (!NONJUMP_INSN_P (insn))
9576 pattern = PATTERN (insn);
9577 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9580 switch (XINT (pattern, 1))
9582 case UNSPECV_CONST2:
9583 case UNSPECV_CONST4:
9584 case UNSPECV_CONST8:
9585 XVECEXP (pattern, 0, 1) = const1_rtx;
9587 case UNSPECV_WINDOW_END:
9588 if (XVECEXP (pattern, 0, 0) == x)
9591 case UNSPECV_CONST_END:
9601 /* Return true if it's possible to redirect BRANCH1 to the destination
9602 of an unconditional jump BRANCH2. We only want to do this if the
9603 resulting branch will have a short displacement. */
9605 sh_can_redirect_branch (rtx branch1, rtx branch2)
9607 if (flag_expensive_optimizations && simplejump_p (branch2))
9609 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
9613 for (distance = 0, insn = NEXT_INSN (branch1);
9614 insn && distance < 256;
9615 insn = PREV_INSN (insn))
9620 distance += get_attr_length (insn);
9622 for (distance = 0, insn = NEXT_INSN (branch1);
9623 insn && distance < 256;
9624 insn = NEXT_INSN (insn))
9629 distance += get_attr_length (insn);
9635 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9637 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9638 unsigned int new_reg)
9640 /* Interrupt functions can only use registers that have already been
9641 saved by the prologue, even if they would normally be
9644 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
9650 /* Function to update the integer COST
9651 based on the relationship between INSN that is dependent on
9652 DEP_INSN through the dependence LINK. The default is to make no
9653 adjustment to COST. This can be used for example to specify to
9654 the scheduler that an output- or anti-dependence does not incur
9655 the same cost as a data-dependence. The return value should be
9656 the new value for COST. */
9658 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
9664 /* On SHmedia, if the dependence is an anti-dependence or
9665 output-dependence, there is no cost. */
9666 if (REG_NOTE_KIND (link) != 0)
9668 /* However, dependencies between target register loads and
9669 uses of the register in a subsequent block that are separated
9670 by a conditional branch are not modelled - we have to do with
9671 the anti-dependency between the target register load and the
9672 conditional branch that ends the current block. */
9673 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9674 && GET_CODE (PATTERN (dep_insn)) == SET
9675 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
9676 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
9677 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
9679 int orig_cost = cost;
9680 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
9681 rtx target = ((! note
9682 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
9683 ? insn : JUMP_LABEL (insn));
9684 /* On the likely path, the branch costs 1, on the unlikely path,
9688 target = next_active_insn (target);
9689 while (target && ! flow_dependent_p (target, dep_insn)
9691 /* If two branches are executed in immediate succession, with the
9692 first branch properly predicted, this causes a stall at the
9693 second branch, hence we won't need the target for the
9694 second branch for two cycles after the launch of the first
9696 if (cost > orig_cost - 2)
9697 cost = orig_cost - 2;
9703 else if (get_attr_is_mac_media (insn)
9704 && get_attr_is_mac_media (dep_insn))
9707 else if (! reload_completed
9708 && GET_CODE (PATTERN (insn)) == SET
9709 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9710 && GET_CODE (PATTERN (dep_insn)) == SET
9711 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9714 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9715 that is needed at the target. */
9716 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9717 && ! flow_dependent_p (insn, dep_insn))
9720 else if (REG_NOTE_KIND (link) == 0)
9722 enum attr_type type;
9725 if (recog_memoized (insn) < 0
9726 || recog_memoized (dep_insn) < 0)
9729 dep_set = single_set (dep_insn);
9731 /* The latency that we specify in the scheduling description refers
9732 to the actual output, not to an auto-increment register; for that,
9733 the latency is one. */
9734 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9736 rtx set = single_set (insn);
9739 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9740 && (!MEM_P (SET_DEST (set))
9741 || !reg_mentioned_p (SET_DEST (dep_set),
9742 XEXP (SET_DEST (set), 0))))
9745 /* The only input for a call that is timing-critical is the
9746 function's address. */
9749 rtx call = PATTERN (insn);
9751 if (GET_CODE (call) == PARALLEL)
9752 call = XVECEXP (call, 0 ,0);
9753 if (GET_CODE (call) == SET)
9754 call = SET_SRC (call);
9755 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
9756 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9757 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9758 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9759 cost -= TARGET_SH4_300 ? 3 : 6;
9761 /* Likewise, the most timing critical input for an sfuncs call
9762 is the function address. However, sfuncs typically start
9763 using their arguments pretty quickly.
9764 Assume a four cycle delay for SH4 before they are needed.
9765 Cached ST40-300 calls are quicker, so assume only a one
9767 ??? Maybe we should encode the delays till input registers
9768 are needed by sfuncs into the sfunc call insn. */
9769 /* All sfunc calls are parallels with at least four components.
9770 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9771 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9772 && XVECLEN (PATTERN (insn), 0) >= 4
9773 && (reg = sfunc_uses_reg (insn)))
9775 if (! reg_set_p (reg, dep_insn))
9776 cost -= TARGET_SH4_300 ? 1 : 4;
9778 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9780 enum attr_type dep_type = get_attr_type (dep_insn);
9782 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9784 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9785 && (type = get_attr_type (insn)) != TYPE_CALL
9786 && type != TYPE_SFUNC)
9788 /* When the preceding instruction loads the shift amount of
9789 the following SHAD/SHLD, the latency of the load is increased
9791 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9792 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9793 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9794 XEXP (SET_SRC (single_set (insn)),
9797 /* When an LS group instruction with a latency of less than
9798 3 cycles is followed by a double-precision floating-point
9799 instruction, FIPR, or FTRV, the latency of the first
9800 instruction is increased to 3 cycles. */
9802 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9803 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9805 /* The lsw register of a double-precision computation is ready one
9807 else if (reload_completed
9808 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9809 && (use_pat = single_set (insn))
9810 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9814 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9815 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9818 else if (TARGET_SH4_300)
9820 /* Stores need their input register two cycles later. */
9821 if (dep_set && cost >= 1
9822 && ((type = get_attr_type (insn)) == TYPE_STORE
9823 || type == TYPE_PSTORE
9824 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9826 rtx set = single_set (insn);
9828 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9829 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9832 /* But don't reduce the cost below 1 if the address depends
9833 on a side effect of dep_insn. */
9835 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9841 /* An anti-dependence penalty of two applies if the first insn is a double
9842 precision fadd / fsub / fmul. */
9843 else if (!TARGET_SH4_300
9844 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9845 && recog_memoized (dep_insn) >= 0
9846 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9847 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9848 /* A lot of alleged anti-flow dependences are fake,
9849 so check this one is real. */
9850 && flow_dependent_p (dep_insn, insn))
9856 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9857 if DEP_INSN is anti-flow dependent on INSN. */
9859 flow_dependent_p (rtx insn, rtx dep_insn)
9861 rtx tmp = PATTERN (insn);
9863 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9864 return tmp == NULL_RTX;
9867 /* A helper function for flow_dependent_p called through note_stores. */
9869 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9871 rtx * pinsn = (rtx *) data;
9873 if (*pinsn && reg_referenced_p (x, *pinsn))
9877 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9878 'special function' patterns (type sfunc) that clobber pr, but that
9879 do not look like function calls to leaf_function_p. Hence we must
9880 do this extra check. */
9884 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9887 /* Return where to allocate pseudo for a given hard register initial
9890 sh_allocate_initial_value (rtx hard_reg)
9894 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9896 if (current_function_is_leaf
9897 && ! sh_pr_n_sets ()
9898 && ! (TARGET_SHCOMPACT
9899 && ((crtl->args.info.call_cookie
9900 & ~ CALL_COOKIE_RET_TRAMP (1))
9901 || crtl->saves_all_registers)))
9904 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9912 /* This function returns "2" to indicate dual issue for the SH4
9913 processor. To be used by the DFA pipeline description. */
9915 sh_issue_rate (void)
9917 if (TARGET_SUPERSCALAR)
9923 /* Functions for ready queue reordering for sched1. */
9925 /* Get weight for mode for a set x. */
9927 find_set_regmode_weight (rtx x, enum machine_mode mode)
9929 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9931 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9933 if (REG_P (SET_DEST (x)))
9935 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9945 /* Get regmode weight for insn. */
9947 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9949 short reg_weight = 0;
9952 /* Increment weight for each register born here. */
9954 reg_weight += find_set_regmode_weight (x, mode);
9955 if (GET_CODE (x) == PARALLEL)
9958 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9960 x = XVECEXP (PATTERN (insn), 0, j);
9961 reg_weight += find_set_regmode_weight (x, mode);
9964 /* Decrement weight for each register that dies here. */
9965 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9967 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9969 rtx note = XEXP (x, 0);
9970 if (REG_P (note) && GET_MODE (note) == mode)
9977 /* Calculate regmode weights for all insns of a basic block. */
9979 find_regmode_weight (basic_block b, enum machine_mode mode)
9981 rtx insn, next_tail, head, tail;
9983 get_ebb_head_tail (b, b, &head, &tail);
9984 next_tail = NEXT_INSN (tail);
9986 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9988 /* Handle register life information. */
9993 INSN_REGMODE_WEIGHT (insn, mode) =
9994 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9995 else if (mode == SImode)
9996 INSN_REGMODE_WEIGHT (insn, mode) =
9997 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
10001 /* Comparison function for ready queue sorting. */
10003 rank_for_reorder (const void *x, const void *y)
10005 rtx tmp = *(const rtx *) y;
10006 rtx tmp2 = *(const rtx *) x;
10008 /* The insn in a schedule group should be issued the first. */
10009 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
10010 return SCHED_GROUP_P (tmp2) ? 1 : -1;
10012 /* If insns are equally good, sort by INSN_LUID (original insn order), This
10013 minimizes instruction movement, thus minimizing sched's effect on
10014 register pressure. */
10015 return INSN_LUID (tmp) - INSN_LUID (tmp2);
10018 /* Resort the array A in which only element at index N may be out of order. */
10020 swap_reorder (rtx *a, int n)
10022 rtx insn = a[n - 1];
10025 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
10033 #define SCHED_REORDER(READY, N_READY) \
10036 if ((N_READY) == 2) \
10037 swap_reorder (READY, N_READY); \
10038 else if ((N_READY) > 2) \
10039 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
10043 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
10046 ready_reorder (rtx *ready, int nready)
10048 SCHED_REORDER (ready, nready);
10051 /* Count life regions of r0 for a block. */
10053 find_r0_life_regions (basic_block b)
10062 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
10073 insn = BB_HEAD (b);
10075 r0_reg = gen_rtx_REG (SImode, R0_REG);
10080 if (find_regno_note (insn, REG_DEAD, R0_REG))
10086 && (pset = single_set (insn))
10087 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
10088 && !find_regno_note (insn, REG_UNUSED, R0_REG))
10096 insn = NEXT_INSN (insn);
10098 return set - death;
10101 /* Calculate regmode weights for all insns of all basic block. */
10103 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
10104 int verbose ATTRIBUTE_UNUSED,
10109 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
10110 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
10111 r0_life_regions = 0;
10113 FOR_EACH_BB_REVERSE (b)
10115 find_regmode_weight (b, SImode);
10116 find_regmode_weight (b, SFmode);
10117 if (!reload_completed)
10118 r0_life_regions += find_r0_life_regions (b);
10121 CURR_REGMODE_PRESSURE (SImode) = 0;
10122 CURR_REGMODE_PRESSURE (SFmode) = 0;
10128 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
10129 int verbose ATTRIBUTE_UNUSED)
10131 if (regmode_weight[0])
10133 free (regmode_weight[0]);
10134 regmode_weight[0] = NULL;
10136 if (regmode_weight[1])
10138 free (regmode_weight[1]);
10139 regmode_weight[1] = NULL;
10143 /* The scalar modes supported differs from the default version in TImode
10144 for 32-bit SHMEDIA. */
10146 sh_scalar_mode_supported_p (enum machine_mode mode)
10148 if (TARGET_SHMEDIA32 && mode == TImode)
10151 return default_scalar_mode_supported_p (mode);
10154 /* Cache the can_issue_more so that we can return it from reorder2. Also,
10155 keep count of register pressures on SImode and SFmode. */
10157 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
10158 int sched_verbose ATTRIBUTE_UNUSED,
10160 int can_issue_more)
10162 if (GET_CODE (PATTERN (insn)) != USE
10163 && GET_CODE (PATTERN (insn)) != CLOBBER)
10164 cached_can_issue_more = can_issue_more - 1;
10166 cached_can_issue_more = can_issue_more;
10168 if (reload_completed)
10169 return cached_can_issue_more;
10171 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
10172 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
10174 return cached_can_issue_more;
10178 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
10179 int verbose ATTRIBUTE_UNUSED,
10180 int veclen ATTRIBUTE_UNUSED)
10182 CURR_REGMODE_PRESSURE (SImode) = 0;
10183 CURR_REGMODE_PRESSURE (SFmode) = 0;
10186 /* Some magic numbers. */
10187 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10188 functions that already have high pressure on r0. */
10189 #define R0_MAX_LIFE_REGIONS 2
10190 /* Register Pressure thresholds for SImode and SFmode registers. */
10191 #define SIMODE_MAX_WEIGHT 5
10192 #define SFMODE_MAX_WEIGHT 10
10194 /* Return true if the pressure is high for MODE. */
10196 high_pressure (enum machine_mode mode)
10198 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10199 functions that already have high pressure on r0. */
10200 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
10203 if (mode == SFmode)
10204 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
10206 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
10209 /* Reorder ready queue if register pressure is high. */
10211 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
10212 int sched_verbose ATTRIBUTE_UNUSED,
10215 int clock_var ATTRIBUTE_UNUSED)
10217 if (reload_completed)
10218 return sh_issue_rate ();
10220 if (high_pressure (SFmode) || high_pressure (SImode))
10222 ready_reorder (ready, *n_readyp);
10225 return sh_issue_rate ();
10228 /* Skip cycles if the current register pressure is high. */
10230 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
10231 int sched_verbose ATTRIBUTE_UNUSED,
10232 rtx *ready ATTRIBUTE_UNUSED,
10233 int *n_readyp ATTRIBUTE_UNUSED,
10234 int clock_var ATTRIBUTE_UNUSED)
10236 if (reload_completed)
10237 return cached_can_issue_more;
10239 if (high_pressure(SFmode) || high_pressure (SImode))
10242 return cached_can_issue_more;
10245 /* Skip cycles without sorting the ready queue. This will move insn from
10246 Q->R. If this is the last cycle we are skipping; allow sorting of ready
10247 queue by sh_reorder. */
10249 /* Generally, skipping these many cycles are sufficient for all insns to move
10251 #define MAX_SKIPS 8
10254 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10255 int sched_verbose ATTRIBUTE_UNUSED,
10256 rtx insn ATTRIBUTE_UNUSED,
10257 int last_clock_var,
10261 if (reload_completed)
10266 if ((clock_var - last_clock_var) < MAX_SKIPS)
10271 /* If this is the last cycle we are skipping, allow reordering of R. */
10272 if ((clock_var - last_clock_var) == MAX_SKIPS)
10284 /* SHmedia requires registers for branches, so we can't generate new
10285 branches past reload. */
10287 sh_cannot_modify_jumps_p (void)
10289 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
10292 static enum reg_class
10293 sh_target_reg_class (void)
10295 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
10299 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
10301 HARD_REG_SET dummy;
10306 if (! shmedia_space_reserved_for_target_registers)
10308 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
10310 if (calc_live_regs (&dummy) >= 6 * 8)
10316 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
10318 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
10322 On the SH1..SH4, the trampoline looks like
10323 2 0002 D202 mov.l l2,r2
10324 1 0000 D301 mov.l l1,r3
10325 3 0004 422B jmp @r2
10327 5 0008 00000000 l1: .long area
10328 6 000c 00000000 l2: .long function
10330 SH5 (compact) uses r1 instead of r3 for the static chain. */
10333 /* Emit RTL insns to initialize the variable parts of a trampoline.
10334 FNADDR is an RTX for the address of the function's pure code.
10335 CXT is an RTX for the static chain value for the function. */
10338 sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
10340 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10341 rtx tramp = force_reg (Pmode, XEXP (tramp_mem, 0));
10343 if (TARGET_SHMEDIA64)
10348 rtx movi1 = GEN_INT (0xcc000010);
10349 rtx shori1 = GEN_INT (0xc8000010);
10352 /* The following trampoline works within a +- 128 KB range for cxt:
10353 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10354 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10355 gettr tr1,r1; blink tr0,r63 */
10356 /* Address rounding makes it hard to compute the exact bounds of the
10357 offset for this trampoline, but we have a rather generous offset
10358 range, so frame_offset should do fine as an upper bound. */
10359 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10361 /* ??? could optimize this trampoline initialization
10362 by writing DImode words with two insns each. */
10363 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10364 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10365 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10366 insn = gen_rtx_AND (DImode, insn, mask);
10367 /* Or in ptb/u .,tr1 pattern */
10368 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10369 insn = force_operand (insn, NULL_RTX);
10370 insn = gen_lowpart (SImode, insn);
10371 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
10372 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10373 insn = gen_rtx_AND (DImode, insn, mask);
10374 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10375 insn = gen_lowpart (SImode, insn);
10376 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
10377 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10378 insn = gen_rtx_AND (DImode, insn, mask);
10379 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10380 insn = gen_lowpart (SImode, insn);
10381 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
10382 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10383 insn = gen_rtx_AND (DImode, insn, mask);
10384 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10385 insn = gen_lowpart (SImode, insn);
10386 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
10387 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10388 insn = gen_rtx_AND (DImode, insn, mask);
10389 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10390 insn = gen_lowpart (SImode, insn);
10391 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10392 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
10393 GEN_INT (0x6bf10600));
10394 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
10395 GEN_INT (0x4415fc10));
10396 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
10397 GEN_INT (0x4401fff0));
10398 emit_insn (gen_ic_invalidate_line (tramp));
10401 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10402 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10404 tramp_templ = gen_datalabel_ref (tramp_templ);
10406 src = gen_const_mem (BLKmode, tramp_templ);
10407 set_mem_align (dst, 256);
10408 set_mem_align (src, 64);
10409 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
10411 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10412 emit_move_insn (adjust_address (tramp_mem, Pmode,
10413 fixed_len + GET_MODE_SIZE (Pmode)),
10415 emit_insn (gen_ic_invalidate_line (tramp));
10418 else if (TARGET_SHMEDIA)
10420 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10421 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10422 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10423 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10424 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10425 rotated 10 right, and higher 16 bit of every 32 selected. */
10427 = force_reg (V2HImode, (simplify_gen_subreg
10428 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10429 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10430 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10432 fnaddr = force_reg (SImode, fnaddr);
10433 cxt = force_reg (SImode, cxt);
10434 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10435 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10437 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
10438 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10439 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
10440 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
10441 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10442 gen_rtx_SUBREG (V2HImode, cxt, 0),
10444 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
10445 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10446 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
10447 if (TARGET_LITTLE_ENDIAN)
10449 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10450 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10454 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10455 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10457 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10458 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
10459 emit_insn (gen_ic_invalidate_line (tramp));
10462 else if (TARGET_SHCOMPACT)
10464 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10467 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
10468 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10470 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
10471 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10473 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10474 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
10475 if (TARGET_HARVARD)
10477 if (!TARGET_INLINE_IC_INVALIDATE
10478 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
10479 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10480 FUNCTION_ORDINARY),
10481 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
10483 emit_insn (gen_ic_invalidate_line (tramp));
10487 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
10490 sh_trampoline_adjust_address (rtx tramp)
10492 if (TARGET_SHMEDIA)
10493 tramp = expand_simple_binop (Pmode, PLUS, tramp, const1_rtx,
10494 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN);
10498 /* FIXME: This is overly conservative. A SHcompact function that
10499 receives arguments ``by reference'' will have them stored in its
10500 own stack frame, so it must not pass pointers or references to
10501 these arguments to other functions by means of sibling calls. */
10502 /* If PIC, we cannot make sibling calls to global functions
10503 because the PLT requires r12 to be live. */
10505 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10508 && (! TARGET_SHCOMPACT
10509 || crtl->args.info.stack_regs == 0)
10510 && ! sh_cfun_interrupt_handler_p ()
10512 || (decl && ! TREE_PUBLIC (decl))
10513 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10516 /* Machine specific built-in functions. */
10518 struct builtin_description
10520 const enum insn_code icode;
10521 const char *const name;
10525 /* describe number and signedness of arguments; arg[0] == result
10526 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10527 /* 9: 64-bit pointer, 10: 32-bit pointer */
10528 static const char signature_args[][4] =
10530 #define SH_BLTIN_V2SI2 0
10532 #define SH_BLTIN_V4HI2 1
10534 #define SH_BLTIN_V2SI3 2
10536 #define SH_BLTIN_V4HI3 3
10538 #define SH_BLTIN_V8QI3 4
10540 #define SH_BLTIN_MAC_HISI 5
10542 #define SH_BLTIN_SH_HI 6
10544 #define SH_BLTIN_SH_SI 7
10546 #define SH_BLTIN_V4HI2V2SI 8
10548 #define SH_BLTIN_V4HI2V8QI 9
10550 #define SH_BLTIN_SISF 10
10552 #define SH_BLTIN_LDUA_L 11
10554 #define SH_BLTIN_LDUA_Q 12
10556 #define SH_BLTIN_STUA_L 13
10558 #define SH_BLTIN_STUA_Q 14
10560 #define SH_BLTIN_LDUA_L64 15
10562 #define SH_BLTIN_LDUA_Q64 16
10564 #define SH_BLTIN_STUA_L64 17
10566 #define SH_BLTIN_STUA_Q64 18
10568 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10569 #define SH_BLTIN_2 19
10570 #define SH_BLTIN_SU 19
10572 #define SH_BLTIN_3 20
10573 #define SH_BLTIN_SUS 20
10575 #define SH_BLTIN_PSSV 21
10577 #define SH_BLTIN_XXUU 22
10578 #define SH_BLTIN_UUUU 22
10580 #define SH_BLTIN_PV 23
10583 /* mcmv: operands considered unsigned. */
10584 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10585 /* mperm: control value considered unsigned int. */
10586 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10587 /* mshards_q: returns signed short. */
10588 /* nsb: takes long long arg, returns unsigned char. */
10589 static const struct builtin_description bdesc[] =
10591 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
10592 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
10593 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
10594 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
10595 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
10596 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
10597 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
10598 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
10599 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
10600 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
10601 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
10602 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
10603 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
10604 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
10605 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
10606 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
10607 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
10608 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
10609 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
10610 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
10611 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
10612 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
10613 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
10614 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
10615 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
10616 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
10617 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
10618 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
10619 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
10620 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
10621 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
10622 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
10623 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
10624 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
10625 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
10626 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
10627 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
10628 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
10629 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
10630 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
10631 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
10632 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
10633 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
10634 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
10635 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
10636 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
10637 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
10638 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
10639 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
10640 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
10641 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
10642 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
10643 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
10644 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
10645 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
10646 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
10647 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
10648 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
10649 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
10650 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
10651 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
10652 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
10653 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
10654 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
10655 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
10656 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
10657 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
10658 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
10659 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
10660 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
10661 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
10662 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
10663 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
10664 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
10665 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
10666 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
10667 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
10668 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
10669 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
10670 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
10671 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
10672 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
10673 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
10674 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
10678 sh_media_init_builtins (void)
10680 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10681 const struct builtin_description *d;
10683 memset (shared, 0, sizeof shared);
10684 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
10686 tree type, arg_type = 0;
10687 int signature = d->signature;
10690 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10691 type = shared[signature];
10694 int has_result = signature_args[signature][0] != 0;
10696 if ((signature_args[signature][1] & 8)
10697 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
10698 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
10700 if (! TARGET_FPU_ANY
10701 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10703 type = void_list_node;
10706 int arg = signature_args[signature][i];
10707 int opno = i - 1 + has_result;
10710 arg_type = ptr_type_node;
10712 arg_type = (*lang_hooks.types.type_for_mode)
10713 (insn_data[d->icode].operand[opno].mode,
10718 arg_type = void_type_node;
10721 type = tree_cons (NULL_TREE, arg_type, type);
10723 type = build_function_type (arg_type, type);
10724 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10725 shared[signature] = type;
10727 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10732 /* Implements target hook vector_mode_supported_p. */
10734 sh_vector_mode_supported_p (enum machine_mode mode)
10737 && ((mode == V2SFmode)
10738 || (mode == V4SFmode)
10739 || (mode == V16SFmode)))
10742 else if (TARGET_SHMEDIA
10743 && ((mode == V8QImode)
10744 || (mode == V2HImode)
10745 || (mode == V4HImode)
10746 || (mode == V2SImode)))
10752 /* Implements target hook dwarf_calling_convention. Return an enum
10753 of dwarf_calling_convention. */
10755 sh_dwarf_calling_convention (const_tree func)
10757 if (sh_attr_renesas_p (func))
10758 return DW_CC_GNU_renesas_sh;
10760 return DW_CC_normal;
10764 sh_init_builtins (void)
10766 if (TARGET_SHMEDIA)
10767 sh_media_init_builtins ();
10770 /* Expand an expression EXP that calls a built-in function,
10771 with result going to TARGET if that's convenient
10772 (and in mode MODE if that's convenient).
10773 SUBTARGET may be used as the target for computing one of EXP's operands.
10774 IGNORE is nonzero if the value is to be ignored. */
10777 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10778 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10780 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10781 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10782 const struct builtin_description *d = &bdesc[fcode];
10783 enum insn_code icode = d->icode;
10784 int signature = d->signature;
10785 enum machine_mode tmode = VOIDmode;
10790 if (signature_args[signature][0])
10795 tmode = insn_data[icode].operand[0].mode;
10797 || GET_MODE (target) != tmode
10798 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10799 target = gen_reg_rtx (tmode);
10800 op[nop++] = target;
10805 for (i = 1; i <= 3; i++, nop++)
10808 enum machine_mode opmode, argmode;
10811 if (! signature_args[signature][i])
10813 arg = CALL_EXPR_ARG (exp, i - 1);
10814 if (arg == error_mark_node)
10816 if (signature_args[signature][i] & 8)
10819 optype = ptr_type_node;
10823 opmode = insn_data[icode].operand[nop].mode;
10824 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10826 argmode = TYPE_MODE (TREE_TYPE (arg));
10827 if (argmode != opmode)
10828 arg = build1 (NOP_EXPR, optype, arg);
10829 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
10830 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10831 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10837 pat = (*insn_data[d->icode].genfun) (op[0]);
10840 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10843 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10846 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10849 gcc_unreachable ();
10858 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
10860 rtx sel0 = const0_rtx;
10861 rtx sel1 = const1_rtx;
10862 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
10863 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10865 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10866 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10870 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
10872 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10874 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10875 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
10878 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
10879 We can allow any mode in any general register. The special registers
10880 only allow SImode. Don't allow any mode in the PR.
10882 We cannot hold DCmode values in the XD registers because alter_reg
10883 handles subregs of them incorrectly. We could work around this by
10884 spacing the XD registers like the DR registers, but this would require
10885 additional memory in every compilation to hold larger register vectors.
10886 We could hold SFmode / SCmode values in XD registers, but that
10887 would require a tertiary reload when reloading from / to memory,
10888 and a secondary reload to reload from / to general regs; that
10889 seems to be a loosing proposition.
10891 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10892 it won't be ferried through GP registers first. */
10895 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10897 if (SPECIAL_REGISTER_P (regno))
10898 return mode == SImode;
10900 if (regno == FPUL_REG)
10901 return (mode == SImode || mode == SFmode);
10903 if (FP_REGISTER_P (regno) && mode == SFmode)
10906 if (mode == V2SFmode)
10908 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
10909 || GENERAL_REGISTER_P (regno)))
10915 if (mode == V4SFmode)
10917 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
10918 || GENERAL_REGISTER_P (regno))
10924 if (mode == V16SFmode)
10926 if (TARGET_SHMEDIA)
10928 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
10934 return regno == FIRST_XD_REG;
10937 if (FP_REGISTER_P (regno))
10941 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
10942 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
10945 && (mode == DFmode || mode == DImode
10946 || mode == V2SFmode || mode == TImode)))
10947 && ((regno - FIRST_FP_REG) & 1) == 0)
10948 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
10949 && ((regno - FIRST_FP_REG) & 3) == 0))
10955 if (XD_REGISTER_P (regno))
10956 return mode == DFmode;
10958 if (TARGET_REGISTER_P (regno))
10959 return (mode == DImode || mode == SImode || mode == PDImode);
10961 if (regno == PR_REG)
10962 return mode == SImode;
10964 if (regno == FPSCR_REG)
10965 return mode == PSImode;
10967 /* FIXME. This works around PR target/37633 for -O0. */
10968 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
10970 unsigned int n = GET_MODE_SIZE (mode) / 8;
10972 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
10973 && regno <= FIRST_GENERAL_REG + 14)
10980 /* Return the class of registers for which a mode change from FROM to TO
10983 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
10984 enum reg_class rclass)
10986 /* We want to enable the use of SUBREGs as a means to
10987 VEC_SELECT a single element of a vector. */
10988 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10989 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
10991 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10993 if (TARGET_LITTLE_ENDIAN)
10995 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10996 return reg_classes_intersect_p (DF_REGS, rclass);
11000 if (GET_MODE_SIZE (from) < 8)
11001 return reg_classes_intersect_p (DF_HI_REGS, rclass);
11008 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
11009 that label is used. */
11012 sh_mark_label (rtx address, int nuses)
11014 if (GOTOFF_P (address))
11016 /* Extract the label or symbol. */
11017 address = XEXP (address, 0);
11018 if (GET_CODE (address) == PLUS)
11019 address = XEXP (address, 0);
11020 address = XVECEXP (address, 0, 0);
11022 if (GET_CODE (address) == LABEL_REF
11023 && LABEL_P (XEXP (address, 0)))
11024 LABEL_NUSES (XEXP (address, 0)) += nuses;
11027 /* Compute extra cost of moving data between one register class
11030 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
11031 uses this information. Hence, the general register <-> floating point
11032 register information here is not used for SFmode. */
11035 sh_register_move_cost (enum machine_mode mode,
11036 enum reg_class srcclass, enum reg_class dstclass)
11038 if (dstclass == T_REGS || dstclass == PR_REGS)
11041 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
11044 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
11045 && REGCLASS_HAS_FP_REG (srcclass)
11046 && REGCLASS_HAS_FP_REG (dstclass))
11049 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
11050 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
11052 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
11053 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
11056 if ((REGCLASS_HAS_FP_REG (dstclass)
11057 && REGCLASS_HAS_GENERAL_REG (srcclass))
11058 || (REGCLASS_HAS_GENERAL_REG (dstclass)
11059 && REGCLASS_HAS_FP_REG (srcclass)))
11060 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
11061 * ((GET_MODE_SIZE (mode) + 7) / 8U));
11063 if ((dstclass == FPUL_REGS
11064 && REGCLASS_HAS_GENERAL_REG (srcclass))
11065 || (srcclass == FPUL_REGS
11066 && REGCLASS_HAS_GENERAL_REG (dstclass)))
11069 if ((dstclass == FPUL_REGS
11070 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
11071 || (srcclass == FPUL_REGS
11072 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
11075 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11076 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11079 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11081 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
11083 if (sh_gettrcost >= 0)
11084 return sh_gettrcost;
11085 else if (!TARGET_PT_FIXED)
11089 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11090 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11095 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
11096 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
11097 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
11099 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
11102 static rtx emit_load_ptr (rtx, rtx);
11105 emit_load_ptr (rtx reg, rtx addr)
11107 rtx mem = gen_const_mem (ptr_mode, addr);
11109 if (Pmode != ptr_mode)
11110 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
11111 return emit_move_insn (reg, mem);
11115 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11116 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11119 CUMULATIVE_ARGS cum;
11120 int structure_value_byref = 0;
11121 rtx this_rtx, this_value, sibcall, insns, funexp;
11122 tree funtype = TREE_TYPE (function);
11123 int simple_add = CONST_OK_FOR_ADD (delta);
11125 rtx scratch0, scratch1, scratch2;
11128 reload_completed = 1;
11129 epilogue_completed = 1;
11130 current_function_uses_only_leaf_regs = 1;
11132 emit_note (NOTE_INSN_PROLOGUE_END);
11134 /* Find the "this" pointer. We have such a wide range of ABIs for the
11135 SH that it's best to do this completely machine independently.
11136 "this" is passed as first argument, unless a structure return pointer
11137 comes first, in which case "this" comes second. */
11138 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
11139 #ifndef PCC_STATIC_STRUCT_RETURN
11140 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11141 structure_value_byref = 1;
11142 #endif /* not PCC_STATIC_STRUCT_RETURN */
11143 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
11145 tree ptype = build_pointer_type (TREE_TYPE (funtype));
11147 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
11149 this_rtx = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
11151 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11152 static chain pointer (even if you can't have nested virtual functions
11153 right now, someone might implement them sometime), and the rest of the
11154 registers are used for argument passing, are callee-saved, or reserved. */
11155 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11156 -ffixed-reg has been used. */
11157 if (! call_used_regs[0] || fixed_regs[0])
11158 error ("r0 needs to be available as a call-clobbered register");
11159 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
11162 if (call_used_regs[1] && ! fixed_regs[1])
11163 scratch1 = gen_rtx_REG (ptr_mode, 1);
11164 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11165 pointing where to return struct values. */
11166 if (call_used_regs[3] && ! fixed_regs[3])
11167 scratch2 = gen_rtx_REG (Pmode, 3);
11169 else if (TARGET_SHMEDIA)
11171 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
11172 if (i != REGNO (scratch0) &&
11173 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
11175 scratch1 = gen_rtx_REG (ptr_mode, i);
11178 if (scratch1 == scratch0)
11179 error ("Need a second call-clobbered general purpose register");
11180 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
11181 if (call_used_regs[i] && ! fixed_regs[i])
11183 scratch2 = gen_rtx_REG (Pmode, i);
11186 if (scratch2 == scratch0)
11187 error ("Need a call-clobbered target register");
11190 this_value = plus_constant (this_rtx, delta);
11192 && (simple_add || scratch0 != scratch1)
11193 && strict_memory_address_p (ptr_mode, this_value))
11195 emit_load_ptr (scratch0, this_value);
11200 ; /* Do nothing. */
11201 else if (simple_add)
11202 emit_move_insn (this_rtx, this_value);
11205 emit_move_insn (scratch1, GEN_INT (delta));
11206 emit_insn (gen_add2_insn (this_rtx, scratch1));
11214 emit_load_ptr (scratch0, this_rtx);
11216 offset_addr = plus_constant (scratch0, vcall_offset);
11217 if (strict_memory_address_p (ptr_mode, offset_addr))
11218 ; /* Do nothing. */
11219 else if (! TARGET_SH5 && scratch0 != scratch1)
11221 /* scratch0 != scratch1, and we have indexed loads. Get better
11222 schedule by loading the offset into r1 and using an indexed
11223 load - then the load of r1 can issue before the load from
11224 (this_rtx + delta) finishes. */
11225 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11226 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
11228 else if (CONST_OK_FOR_ADD (vcall_offset))
11230 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
11231 offset_addr = scratch0;
11233 else if (scratch0 != scratch1)
11235 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11236 emit_insn (gen_add2_insn (scratch0, scratch1));
11237 offset_addr = scratch0;
11240 gcc_unreachable (); /* FIXME */
11241 emit_load_ptr (scratch0, offset_addr);
11243 if (Pmode != ptr_mode)
11244 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
11245 emit_insn (gen_add2_insn (this_rtx, scratch0));
11248 /* Generate a tail call to the target function. */
11249 if (! TREE_USED (function))
11251 assemble_external (function);
11252 TREE_USED (function) = 1;
11254 funexp = XEXP (DECL_RTL (function), 0);
11255 /* If the function is overridden, so is the thunk, hence we don't
11256 need GOT addressing even if this is a public symbol. */
11258 if (TARGET_SH1 && ! flag_weak)
11259 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
11262 if (TARGET_SH2 && flag_pic)
11264 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
11265 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
11269 if (TARGET_SHMEDIA && flag_pic)
11271 funexp = gen_sym2PIC (funexp);
11272 PUT_MODE (funexp, Pmode);
11274 emit_move_insn (scratch2, funexp);
11275 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
11276 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
11278 sibcall = emit_call_insn (sibcall);
11279 SIBLING_CALL_P (sibcall) = 1;
11280 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
11283 /* Run just enough of rest_of_compilation to do scheduling and get
11284 the insns emitted. Note that use_thunk calls
11285 assemble_start_function and assemble_end_function. */
11287 insn_locators_alloc ();
11288 insns = get_insns ();
11294 split_all_insns_noflow ();
11299 if (optimize > 0 && flag_delayed_branch)
11300 dbr_schedule (insns);
11302 shorten_branches (insns);
11303 final_start_function (insns, file, 1);
11304 final (insns, file, 1);
11305 final_end_function ();
11307 reload_completed = 0;
11308 epilogue_completed = 0;
11312 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
11316 /* If this is not an ordinary function, the name usually comes from a
11317 string literal or an sprintf buffer. Make sure we use the same
11318 string consistently, so that cse will be able to unify address loads. */
11319 if (kind != FUNCTION_ORDINARY)
11320 name = IDENTIFIER_POINTER (get_identifier (name));
11321 sym = gen_rtx_SYMBOL_REF (Pmode, name);
11322 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
11326 case FUNCTION_ORDINARY:
11330 rtx reg = target ? target : gen_reg_rtx (Pmode);
11332 emit_insn (gen_symGOT2reg (reg, sym));
11338 /* ??? To allow cse to work, we use GOTOFF relocations.
11339 we could add combiner patterns to transform this into
11340 straight pc-relative calls with sym2PIC / bsrf when
11341 label load and function call are still 1:1 and in the
11342 same basic block during combine. */
11343 rtx reg = target ? target : gen_reg_rtx (Pmode);
11345 emit_insn (gen_symGOTOFF2reg (reg, sym));
11350 if (target && sym != target)
11352 emit_move_insn (target, sym);
11358 /* Find the number of a general purpose register in S. */
11360 scavenge_reg (HARD_REG_SET *s)
11363 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11364 if (TEST_HARD_REG_BIT (*s, r))
11370 sh_get_pr_initial_val (void)
11374 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11375 PR register on SHcompact, because it might be clobbered by the prologue.
11376 We check first if that is known to be the case. */
11377 if (TARGET_SHCOMPACT
11378 && ((crtl->args.info.call_cookie
11379 & ~ CALL_COOKIE_RET_TRAMP (1))
11380 || crtl->saves_all_registers))
11381 return gen_frame_mem (SImode, return_address_pointer_rtx);
11383 /* If we haven't finished rtl generation, there might be a nonlocal label
11384 that we haven't seen yet.
11385 ??? get_hard_reg_initial_val fails if it is called after register
11386 allocation has started, unless it has been called before for the
11387 same register. And even then, we end in trouble if we didn't use
11388 the register in the same basic block before. So call
11389 get_hard_reg_initial_val now and wrap it in an unspec if we might
11390 need to replace it. */
11391 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11392 combine can put the pseudo returned by get_hard_reg_initial_val into
11393 instructions that need a general purpose registers, which will fail to
11394 be recognized when the pseudo becomes allocated to PR. */
11396 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
11398 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11403 sh_expand_t_scc (rtx operands[])
11405 enum rtx_code code = GET_CODE (operands[1]);
11406 rtx target = operands[0];
11407 rtx op0 = operands[2];
11408 rtx op1 = operands[3];
11409 rtx result = target;
11412 if (!REG_P (op0) || REGNO (op0) != T_REG
11413 || !CONST_INT_P (op1))
11415 if (!REG_P (result))
11416 result = gen_reg_rtx (SImode);
11417 val = INTVAL (op1);
11418 if ((code == EQ && val == 1) || (code == NE && val == 0))
11419 emit_insn (gen_movt (result));
11420 else if (TARGET_SH2A && ((code == EQ && val == 0)
11421 || (code == NE && val == 1)))
11422 emit_insn (gen_xorsi3_movrt (result));
11423 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11425 emit_clobber (result);
11426 emit_insn (gen_subc (result, result, result));
11427 emit_insn (gen_addsi3 (result, result, const1_rtx));
11429 else if (code == EQ || code == NE)
11430 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11433 if (result != target)
11434 emit_move_insn (target, result);
11438 /* INSN is an sfunc; return the rtx that describes the address used. */
11440 extract_sfunc_addr (rtx insn)
11442 rtx pattern, part = NULL_RTX;
11445 pattern = PATTERN (insn);
11446 len = XVECLEN (pattern, 0);
11447 for (i = 0; i < len; i++)
11449 part = XVECEXP (pattern, 0, i);
11450 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11451 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11452 return XEXP (part, 0);
11454 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11455 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11458 /* Verify that the register in use_sfunc_addr still agrees with the address
11459 used in the sfunc. This prevents fill_slots_from_thread from changing
11461 INSN is the use_sfunc_addr instruction, and REG is the register it
11464 check_use_sfunc_addr (rtx insn, rtx reg)
11466 /* Search for the sfunc. It should really come right after INSN. */
11467 while ((insn = NEXT_INSN (insn)))
11469 if (LABEL_P (insn) || JUMP_P (insn))
11471 if (! INSN_P (insn))
11474 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11475 insn = XVECEXP (PATTERN (insn), 0, 0);
11476 if (GET_CODE (PATTERN (insn)) != PARALLEL
11477 || get_attr_type (insn) != TYPE_SFUNC)
11479 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11481 gcc_unreachable ();
11484 /* This function returns a constant rtx that represents pi / 2**15 in
11485 SFmode. it's used to scale SFmode angles, in radians, to a
11486 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11487 maps to 0x10000). */
11489 static GTY(()) rtx sh_fsca_sf2int_rtx;
11492 sh_fsca_sf2int (void)
11494 if (! sh_fsca_sf2int_rtx)
11496 REAL_VALUE_TYPE rv;
11498 real_from_string (&rv, "10430.378350470453");
11499 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11502 return sh_fsca_sf2int_rtx;
11505 /* This function returns a constant rtx that represents pi / 2**15 in
11506 DFmode. it's used to scale DFmode angles, in radians, to a
11507 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11508 maps to 0x10000). */
11510 static GTY(()) rtx sh_fsca_df2int_rtx;
11513 sh_fsca_df2int (void)
11515 if (! sh_fsca_df2int_rtx)
11517 REAL_VALUE_TYPE rv;
11519 real_from_string (&rv, "10430.378350470453");
11520 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
11523 return sh_fsca_df2int_rtx;
11526 /* This function returns a constant rtx that represents 2**15 / pi in
11527 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
11528 of a full circle back to a SFmode value, i.e., 0x10000 maps to
11531 static GTY(()) rtx sh_fsca_int2sf_rtx;
11534 sh_fsca_int2sf (void)
11536 if (! sh_fsca_int2sf_rtx)
11538 REAL_VALUE_TYPE rv;
11540 real_from_string (&rv, "9.587379924285257e-5");
11541 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
11544 return sh_fsca_int2sf_rtx;
11547 /* Initialize the CUMULATIVE_ARGS structure. */
11550 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
11552 rtx libname ATTRIBUTE_UNUSED,
11554 signed int n_named_args,
11555 enum machine_mode mode)
11557 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
11558 pcum->free_single_fp_reg = 0;
11559 pcum->stack_regs = 0;
11560 pcum->byref_regs = 0;
11562 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
11564 /* XXX - Should we check TARGET_HITACHI here ??? */
11565 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
11569 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
11570 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
11571 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
11572 pcum->arg_count [(int) SH_ARG_INT]
11573 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
11576 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11577 && pcum->arg_count [(int) SH_ARG_INT] == 0
11578 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
11579 ? int_size_in_bytes (TREE_TYPE (fntype))
11580 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
11581 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
11582 == FIRST_RET_REG));
11586 pcum->arg_count [(int) SH_ARG_INT] = 0;
11587 pcum->prototype_p = FALSE;
11588 if (mode != VOIDmode)
11590 pcum->call_cookie =
11591 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11592 && GET_MODE_SIZE (mode) > 4
11593 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
11595 /* If the default ABI is the Renesas ABI then all library
11596 calls must assume that the library will be using the
11597 Renesas ABI. So if the function would return its result
11598 in memory then we must force the address of this memory
11599 block onto the stack. Ideally we would like to call
11600 targetm.calls.return_in_memory() here but we do not have
11601 the TYPE or the FNDECL available so we synthesize the
11602 contents of that function as best we can. */
11604 (TARGET_DEFAULT & MASK_HITACHI)
11605 && (mode == BLKmode
11606 || (GET_MODE_SIZE (mode) > 4
11607 && !(mode == DFmode
11608 && TARGET_FPU_DOUBLE)));
11612 pcum->call_cookie = 0;
11613 pcum->force_mem = FALSE;
11618 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
11619 not enter into CONST_DOUBLE for the replace.
11621 Note that copying is not done so X must not be shared unless all copies
11622 are to be modified.
11624 This is like replace_rtx, except that we operate on N_REPLACEMENTS
11625 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
11626 replacements[n*2+1] - and that we take mode changes into account.
11628 If a replacement is ambiguous, return NULL_RTX.
11630 If MODIFY is zero, don't modify any rtl in place,
11631 just return zero or nonzero for failure / success. */
11634 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
11639 /* The following prevents loops occurrence when we change MEM in
11640 CONST_DOUBLE onto the same CONST_DOUBLE. */
11641 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
11644 for (i = n_replacements - 1; i >= 0 ; i--)
11645 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
11646 return replacements[i*2+1];
11648 /* Allow this function to make replacements in EXPR_LISTs. */
11652 if (GET_CODE (x) == SUBREG)
11654 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
11655 n_replacements, modify);
11657 if (CONST_INT_P (new_rtx))
11659 x = simplify_subreg (GET_MODE (x), new_rtx,
11660 GET_MODE (SUBREG_REG (x)),
11666 SUBREG_REG (x) = new_rtx;
11670 else if (REG_P (x))
11672 unsigned regno = REGNO (x);
11673 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
11674 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11675 rtx result = NULL_RTX;
11677 for (i = n_replacements - 1; i >= 0; i--)
11679 rtx from = replacements[i*2];
11680 rtx to = replacements[i*2+1];
11681 unsigned from_regno, from_nregs, to_regno, new_regno;
11685 from_regno = REGNO (from);
11686 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
11687 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
11688 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
11690 if (regno < from_regno
11691 || regno + nregs > from_regno + nregs
11695 to_regno = REGNO (to);
11696 if (to_regno < FIRST_PSEUDO_REGISTER)
11698 new_regno = regno + to_regno - from_regno;
11699 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
11702 result = gen_rtx_REG (GET_MODE (x), new_regno);
11704 else if (GET_MODE (x) <= GET_MODE (to))
11705 result = gen_lowpart_common (GET_MODE (x), to);
11707 result = gen_lowpart_SUBREG (GET_MODE (x), to);
11710 return result ? result : x;
11712 else if (GET_CODE (x) == ZERO_EXTEND)
11714 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
11715 n_replacements, modify);
11717 if (CONST_INT_P (new_rtx))
11719 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
11720 new_rtx, GET_MODE (XEXP (x, 0)));
11725 XEXP (x, 0) = new_rtx;
11730 fmt = GET_RTX_FORMAT (GET_CODE (x));
11731 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
11737 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
11738 n_replacements, modify);
11742 XEXP (x, i) = new_rtx;
11744 else if (fmt[i] == 'E')
11745 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11747 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
11748 n_replacements, modify);
11752 XVECEXP (x, i, j) = new_rtx;
11760 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
11762 enum rtx_code code = TRUNCATE;
11764 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11766 rtx inner = XEXP (x, 0);
11767 enum machine_mode inner_mode = GET_MODE (inner);
11769 if (inner_mode == mode)
11771 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11773 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11774 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11776 code = GET_CODE (x);
11780 return gen_rtx_fmt_e (code, mode, x);
11783 /* called via for_each_rtx after reload, to clean up truncates of
11784 registers that span multiple actual hard registers. */
11786 shmedia_cleanup_truncate (rtx *p, void *n_changes)
11790 if (GET_CODE (x) != TRUNCATE)
11793 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
11795 enum machine_mode reg_mode = GET_MODE (reg);
11796 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
11797 subreg_lowpart_offset (DImode, reg_mode));
11798 *(int*) n_changes += 1;
11804 /* Load and store depend on the highpart of the address. However,
11805 set_attr_alternative does not give well-defined results before reload,
11806 so we must look at the rtl ourselves to see if any of the feeding
11807 registers is used in a memref. */
11809 /* Called by sh_contains_memref_p via for_each_rtx. */
11811 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
11813 return (MEM_P (*loc));
11816 /* Return nonzero iff INSN contains a MEM. */
11818 sh_contains_memref_p (rtx insn)
11820 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11823 /* Return nonzero iff INSN loads a banked register. */
11825 sh_loads_bankedreg_p (rtx insn)
11827 if (GET_CODE (PATTERN (insn)) == SET)
11829 rtx op = SET_DEST (PATTERN(insn));
11830 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11837 /* FNADDR is the MEM expression from a call expander. Return an address
11838 to use in an SHmedia insn pattern. */
11840 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11844 fnaddr = XEXP (fnaddr, 0);
11845 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11846 if (flag_pic && is_sym)
11848 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11850 rtx reg = gen_reg_rtx (Pmode);
11852 /* We must not use GOTPLT for sibcalls, because PIC_REG
11853 must be restored before the PLT code gets to run. */
11855 emit_insn (gen_symGOT2reg (reg, fnaddr));
11857 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11862 fnaddr = gen_sym2PIC (fnaddr);
11863 PUT_MODE (fnaddr, Pmode);
11866 /* If ptabs might trap, make this visible to the rest of the compiler.
11867 We generally assume that symbols pertain to valid locations, but
11868 it is possible to generate invalid symbols with asm or linker tricks.
11869 In a list of functions where each returns its successor, an invalid
11870 symbol might denote an empty list. */
11871 if (!TARGET_PT_FIXED
11872 && (!is_sym || TARGET_INVALID_SYMBOLS)
11873 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11875 rtx tr = gen_reg_rtx (PDImode);
11877 emit_insn (gen_ptabs (tr, fnaddr));
11880 else if (! target_reg_operand (fnaddr, Pmode))
11881 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11886 sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
11887 enum machine_mode mode, secondary_reload_info *sri)
11891 if (REGCLASS_HAS_FP_REG (rclass)
11892 && ! TARGET_SHMEDIA
11893 && immediate_operand ((x), mode)
11894 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11895 && mode == SFmode && fldi_ok ()))
11899 sri->icode = CODE_FOR_reload_insf__frn;
11902 sri->icode = CODE_FOR_reload_indf__frn;
11905 /* ??? If we knew that we are in the appropriate mode -
11906 single precision - we could use a reload pattern directly. */
11911 if (rclass == FPUL_REGS
11913 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11914 || REGNO (x) == T_REG))
11915 || GET_CODE (x) == PLUS))
11916 return GENERAL_REGS;
11917 if (rclass == FPUL_REGS && immediate_operand (x, mode))
11919 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11920 return GENERAL_REGS;
11921 else if (mode == SFmode)
11923 sri->icode = CODE_FOR_reload_insi__i_fpul;
11926 if (rclass == FPSCR_REGS
11927 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11928 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
11929 return GENERAL_REGS;
11930 if (REGCLASS_HAS_FP_REG (rclass)
11932 && immediate_operand (x, mode)
11933 && x != CONST0_RTX (GET_MODE (x))
11934 && GET_MODE (x) != V4SFmode)
11935 return GENERAL_REGS;
11936 if ((mode == QImode || mode == HImode)
11937 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11939 sri->icode = ((mode == QImode)
11940 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11943 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
11944 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
11945 return TARGET_REGS;
11946 } /* end of input-only processing. */
11948 if (((REGCLASS_HAS_FP_REG (rclass)
11950 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11951 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11952 && TARGET_FMOVD))))
11953 || (REGCLASS_HAS_GENERAL_REG (rclass)
11955 && FP_REGISTER_P (REGNO (x))))
11956 && ! TARGET_SHMEDIA
11957 && (mode == SFmode || mode == SImode))
11959 if ((rclass == FPUL_REGS
11960 || (REGCLASS_HAS_FP_REG (rclass)
11961 && ! TARGET_SHMEDIA && mode == SImode))
11964 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11965 || REGNO (x) == T_REG
11966 || system_reg_operand (x, VOIDmode)))))
11968 if (rclass == FPUL_REGS)
11969 return GENERAL_REGS;
11972 if ((rclass == TARGET_REGS
11973 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
11974 && !satisfies_constraint_Csy (x)
11975 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
11976 return GENERAL_REGS;
11977 if ((rclass == MAC_REGS || rclass == PR_REGS)
11978 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
11979 && rclass != REGNO_REG_CLASS (REGNO (x)))
11980 return GENERAL_REGS;
11981 if (rclass != GENERAL_REGS && REG_P (x)
11982 && TARGET_REGISTER_P (REGNO (x)))
11983 return GENERAL_REGS;
11987 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;
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