1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "insn-config.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
40 #include "integrate.h"
44 #include "target-def.h"
46 #include "langhooks.h"
47 #include "basic-block.h"
49 #include "cfglayout.h"
51 #include "sched-int.h"
56 #include "alloc-pool.h"
57 #include "tm-constrs.h"
60 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
62 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
63 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
65 /* These are some macros to abstract register modes. */
66 #define CONST_OK_FOR_ADD(size) \
67 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
68 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
69 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
70 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
72 /* Used to simplify the logic below. Find the attributes wherever
74 #define SH_ATTRIBUTES(decl) \
75 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
76 : DECL_ATTRIBUTES (decl) \
77 ? (DECL_ATTRIBUTES (decl)) \
78 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
80 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
81 int current_function_interrupt;
83 tree sh_deferred_function_attributes;
84 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
86 /* Global variables for machine-dependent things. */
88 /* Which cpu are we scheduling for. */
89 enum processor_type sh_cpu;
91 /* Definitions used in ready queue reordering for first scheduling pass. */
93 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
94 static short *regmode_weight[2];
96 /* Total SFmode and SImode weights of scheduled insns. */
97 static int curr_regmode_pressure[2];
99 /* Number of r0 life regions. */
100 static int r0_life_regions;
102 /* If true, skip cycles for Q -> R movement. */
103 static int skip_cycles = 0;
105 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
106 and returned from sh_reorder2. */
107 static short cached_can_issue_more;
109 /* Provides the class number of the smallest class containing
112 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
114 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
147 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
148 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
149 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
150 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
151 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
152 GENERAL_REGS, GENERAL_REGS,
155 char sh_register_names[FIRST_PSEUDO_REGISTER] \
156 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
158 char sh_additional_register_names[ADDREGNAMES_SIZE] \
159 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
160 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
162 int assembler_dialect;
164 static bool shmedia_space_reserved_for_target_registers;
166 static bool sh_handle_option (size_t, const char *, int);
167 static void split_branches (rtx);
168 static int branch_dest (rtx);
169 static void force_into (rtx, rtx);
170 static void print_slot (rtx);
171 static rtx add_constant (rtx, enum machine_mode, rtx);
172 static void dump_table (rtx, rtx);
173 static int hi_const (rtx);
174 static int broken_move (rtx);
175 static int mova_p (rtx);
176 static rtx find_barrier (int, rtx, rtx);
177 static int noncall_uses_reg (rtx, rtx, rtx *);
178 static rtx gen_block_redirect (rtx, int, int);
179 static void sh_reorg (void);
180 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
181 static rtx frame_insn (rtx);
182 static rtx push (int);
183 static void pop (int);
184 static void push_regs (HARD_REG_SET *, int);
185 static int calc_live_regs (HARD_REG_SET *);
186 static HOST_WIDE_INT rounded_frame_size (int);
187 static rtx mark_constant_pool_use (rtx);
188 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
189 static tree sh_handle_resbank_handler_attribute (tree *, tree,
191 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
193 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
194 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
195 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
196 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
197 static void sh_insert_attributes (tree, tree *);
198 static const char *sh_check_pch_target_flags (int);
199 static int sh_adjust_cost (rtx, rtx, rtx, int);
200 static int sh_issue_rate (void);
201 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
202 static short find_set_regmode_weight (rtx, enum machine_mode);
203 static short find_insn_regmode_weight (rtx, enum machine_mode);
204 static void find_regmode_weight (basic_block, enum machine_mode);
205 static int find_r0_life_regions (basic_block);
206 static void sh_md_init_global (FILE *, int, int);
207 static void sh_md_finish_global (FILE *, int);
208 static int rank_for_reorder (const void *, const void *);
209 static void swap_reorder (rtx *, int);
210 static void ready_reorder (rtx *, int);
211 static short high_pressure (enum machine_mode);
212 static int sh_reorder (FILE *, int, rtx *, int *, int);
213 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
214 static void sh_md_init (FILE *, int, int);
215 static int sh_variable_issue (FILE *, int, rtx, int);
217 static bool sh_function_ok_for_sibcall (tree, tree);
219 static bool sh_cannot_modify_jumps_p (void);
220 static enum reg_class sh_target_reg_class (void);
221 static bool sh_optimize_target_register_callee_saved (bool);
222 static bool sh_ms_bitfield_layout_p (const_tree);
224 static void sh_init_builtins (void);
225 static void sh_media_init_builtins (void);
226 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
227 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
228 static void sh_file_start (void);
229 static int flow_dependent_p (rtx, rtx);
230 static void flow_dependent_p_1 (rtx, const_rtx, void *);
231 static int shiftcosts (rtx);
232 static int andcosts (rtx);
233 static int addsubcosts (rtx);
234 static int multcosts (rtx);
235 static bool unspec_caller_rtx_p (rtx);
236 static bool sh_cannot_copy_insn_p (rtx);
237 static bool sh_rtx_costs (rtx, int, int, int *, bool);
238 static int sh_address_cost (rtx, bool);
239 static int sh_pr_n_sets (void);
240 static rtx sh_allocate_initial_value (rtx);
241 static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
242 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
243 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
244 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
245 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
246 static int scavenge_reg (HARD_REG_SET *s);
247 struct save_schedule_s;
248 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
249 struct save_schedule_s *, int);
251 static rtx sh_struct_value_rtx (tree, int);
252 static bool sh_return_in_memory (const_tree, const_tree);
253 static rtx sh_builtin_saveregs (void);
254 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
255 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
256 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
257 static tree sh_build_builtin_va_list (void);
258 static void sh_va_start (tree, rtx);
259 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
260 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
262 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
264 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
266 static bool sh_scalar_mode_supported_p (enum machine_mode);
267 static int sh_dwarf_calling_convention (const_tree);
268 static void sh_encode_section_info (tree, rtx, int);
269 static int sh2a_function_vector_p (tree);
271 static const struct attribute_spec sh_attribute_table[] =
273 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
274 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
275 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
276 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
277 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
278 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
279 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
280 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
281 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
283 /* Symbian support adds three new attributes:
284 dllexport - for exporting a function/variable that will live in a dll
285 dllimport - for importing a function/variable from a dll
287 Microsoft allows multiple declspecs in one __declspec, separating
288 them with spaces. We do NOT support this. Instead, use __declspec
290 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
291 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
293 { NULL, 0, 0, false, false, false, NULL }
296 /* Initialize the GCC target structure. */
297 #undef TARGET_ATTRIBUTE_TABLE
298 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
300 /* The next two are used for debug info when compiling with -gdwarf. */
301 #undef TARGET_ASM_UNALIGNED_HI_OP
302 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
303 #undef TARGET_ASM_UNALIGNED_SI_OP
304 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
306 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
307 #undef TARGET_ASM_UNALIGNED_DI_OP
308 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
309 #undef TARGET_ASM_ALIGNED_DI_OP
310 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
312 #undef TARGET_ASM_FUNCTION_EPILOGUE
313 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
315 #undef TARGET_ASM_OUTPUT_MI_THUNK
316 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
318 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
319 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
321 #undef TARGET_ASM_FILE_START
322 #define TARGET_ASM_FILE_START sh_file_start
323 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
324 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
326 #undef TARGET_DEFAULT_TARGET_FLAGS
327 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
328 #undef TARGET_HANDLE_OPTION
329 #define TARGET_HANDLE_OPTION sh_handle_option
331 #undef TARGET_INSERT_ATTRIBUTES
332 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
334 #undef TARGET_SCHED_ADJUST_COST
335 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
337 #undef TARGET_SCHED_ISSUE_RATE
338 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
340 /* The next 5 hooks have been implemented for reenabling sched1. With the
341 help of these macros we are limiting the movement of insns in sched1 to
342 reduce the register pressure. The overall idea is to keep count of SImode
343 and SFmode regs required by already scheduled insns. When these counts
344 cross some threshold values; give priority to insns that free registers.
345 The insn that frees registers is most likely to be the insn with lowest
346 LUID (original insn order); but such an insn might be there in the stalled
347 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
348 upto a max of 8 cycles so that such insns may move from Q -> R.
350 The description of the hooks are as below:
352 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
353 scheduler; it is called inside the sched_init function just after
354 find_insn_reg_weights function call. It is used to calculate the SImode
355 and SFmode weights of insns of basic blocks; much similar to what
356 find_insn_reg_weights does.
357 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
359 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
360 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
363 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
364 high; reorder the ready queue so that the insn with lowest LUID will be
367 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
368 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
370 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
371 can be returned from TARGET_SCHED_REORDER2.
373 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
375 #undef TARGET_SCHED_DFA_NEW_CYCLE
376 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
378 #undef TARGET_SCHED_INIT_GLOBAL
379 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
381 #undef TARGET_SCHED_FINISH_GLOBAL
382 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
384 #undef TARGET_SCHED_VARIABLE_ISSUE
385 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
387 #undef TARGET_SCHED_REORDER
388 #define TARGET_SCHED_REORDER sh_reorder
390 #undef TARGET_SCHED_REORDER2
391 #define TARGET_SCHED_REORDER2 sh_reorder2
393 #undef TARGET_SCHED_INIT
394 #define TARGET_SCHED_INIT sh_md_init
396 #undef TARGET_LEGITIMIZE_ADDRESS
397 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
399 #undef TARGET_CANNOT_MODIFY_JUMPS_P
400 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
401 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
402 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
403 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
404 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
405 sh_optimize_target_register_callee_saved
407 #undef TARGET_MS_BITFIELD_LAYOUT_P
408 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
410 #undef TARGET_INIT_BUILTINS
411 #define TARGET_INIT_BUILTINS sh_init_builtins
412 #undef TARGET_EXPAND_BUILTIN
413 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
415 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
416 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
418 #undef TARGET_CANNOT_COPY_INSN_P
419 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
420 #undef TARGET_RTX_COSTS
421 #define TARGET_RTX_COSTS sh_rtx_costs
422 #undef TARGET_ADDRESS_COST
423 #define TARGET_ADDRESS_COST sh_address_cost
424 #undef TARGET_ALLOCATE_INITIAL_VALUE
425 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
427 #undef TARGET_MACHINE_DEPENDENT_REORG
428 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
430 #undef TARGET_DWARF_REGISTER_SPAN
431 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
434 #undef TARGET_HAVE_TLS
435 #define TARGET_HAVE_TLS true
438 #undef TARGET_PROMOTE_PROTOTYPES
439 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
440 #undef TARGET_PROMOTE_FUNCTION_ARGS
441 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_function_mode
443 #undef TARGET_STRUCT_VALUE_RTX
444 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
445 #undef TARGET_RETURN_IN_MEMORY
446 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
448 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
449 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
450 #undef TARGET_SETUP_INCOMING_VARARGS
451 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
452 #undef TARGET_STRICT_ARGUMENT_NAMING
453 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
454 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
455 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
456 #undef TARGET_MUST_PASS_IN_STACK
457 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
458 #undef TARGET_PASS_BY_REFERENCE
459 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
460 #undef TARGET_CALLEE_COPIES
461 #define TARGET_CALLEE_COPIES sh_callee_copies
462 #undef TARGET_ARG_PARTIAL_BYTES
463 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
465 #undef TARGET_BUILD_BUILTIN_VA_LIST
466 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
467 #undef TARGET_EXPAND_BUILTIN_VA_START
468 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
469 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
470 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
472 #undef TARGET_SCALAR_MODE_SUPPORTED_P
473 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
474 #undef TARGET_VECTOR_MODE_SUPPORTED_P
475 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
477 #undef TARGET_CHECK_PCH_TARGET_FLAGS
478 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
480 #undef TARGET_DWARF_CALLING_CONVENTION
481 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
483 /* Return regmode weight for insn. */
484 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
486 /* Return current register pressure for regmode. */
487 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
489 #undef TARGET_ENCODE_SECTION_INFO
490 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
494 #undef TARGET_ENCODE_SECTION_INFO
495 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
496 #undef TARGET_STRIP_NAME_ENCODING
497 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
498 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
499 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
503 #undef TARGET_SECONDARY_RELOAD
504 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
506 #undef TARGET_LEGITIMATE_ADDRESS_P
507 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
509 /* Machine-specific symbol_ref flags. */
510 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
512 struct gcc_target targetm = TARGET_INITIALIZER;
514 /* Implement TARGET_HANDLE_OPTION. */
517 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
518 int value ATTRIBUTE_UNUSED)
523 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
527 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
531 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
535 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
539 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
542 case OPT_m2a_single_only:
543 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
547 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
551 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
555 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
562 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
566 case OPT_m4_100_nofpu:
567 case OPT_m4_200_nofpu:
568 case OPT_m4_300_nofpu:
572 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
576 case OPT_m4_100_single:
577 case OPT_m4_200_single:
578 case OPT_m4_300_single:
579 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
582 case OPT_m4_single_only:
583 case OPT_m4_100_single_only:
584 case OPT_m4_200_single_only:
585 case OPT_m4_300_single_only:
586 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
590 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
595 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
599 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
602 case OPT_m4a_single_only:
603 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
607 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
610 case OPT_m5_32media_nofpu:
611 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
615 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
618 case OPT_m5_64media_nofpu:
619 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
623 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
626 case OPT_m5_compact_nofpu:
627 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
635 /* Set default optimization options. */
637 sh_optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
641 flag_omit_frame_pointer = 2;
643 sh_div_str = "inv:minlat";
647 target_flags |= MASK_SMALLCODE;
648 sh_div_str = SH_DIV_STR_FOR_SIZE ;
651 TARGET_CBRANCHDI4 = 1;
652 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options
653 haven't been parsed yet, hence we'd read only the default.
654 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so
655 it's OK to always set flag_branch_target_load_optimize. */
658 flag_branch_target_load_optimize = 1;
660 target_flags |= MASK_SAVE_ALL_TARGET_REGS;
662 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE
663 here, so leave it to OVERRIDE_OPTIONS to set
664 flag_finite_math_only. We set it to 2 here so we know if the user
665 explicitly requested this to be on or off. */
666 flag_finite_math_only = 2;
667 /* If flag_schedule_insns is 1, we set it to 2 here so we know if
668 the user explicitly requested this to be on or off. */
669 if (flag_schedule_insns > 0)
670 flag_schedule_insns = 2;
672 set_param_value ("simultaneous-prefetches", 2);
675 /* Implement OVERRIDE_OPTIONS macro. Validate and override various
676 options, and do some machine dependent initialization. */
678 sh_override_options (void)
682 SUBTARGET_OVERRIDE_OPTIONS;
683 if (flag_finite_math_only == 2)
684 flag_finite_math_only
685 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;
686 if (TARGET_SH2E && !flag_finite_math_only)
687 target_flags |= MASK_IEEE;
688 sh_cpu = PROCESSOR_SH1;
689 assembler_dialect = 0;
691 sh_cpu = PROCESSOR_SH2;
693 sh_cpu = PROCESSOR_SH2E;
695 sh_cpu = PROCESSOR_SH2A;
697 sh_cpu = PROCESSOR_SH3;
699 sh_cpu = PROCESSOR_SH3E;
702 assembler_dialect = 1;
703 sh_cpu = PROCESSOR_SH4;
705 if (TARGET_SH4A_ARCH)
707 assembler_dialect = 1;
708 sh_cpu = PROCESSOR_SH4A;
712 sh_cpu = PROCESSOR_SH5;
713 target_flags |= MASK_ALIGN_DOUBLE;
714 if (TARGET_SHMEDIA_FPU)
715 target_flags |= MASK_FMOVD;
718 /* There are no delay slots on SHmedia. */
719 flag_delayed_branch = 0;
720 /* Relaxation isn't yet supported for SHmedia */
721 target_flags &= ~MASK_RELAX;
722 /* After reload, if conversion does little good but can cause
724 - find_if_block doesn't do anything for SH because we don't
725 have conditional execution patterns. (We use conditional
726 move patterns, which are handled differently, and only
728 - find_cond_trap doesn't do anything for the SH because we
729 don't have conditional traps.
730 - find_if_case_1 uses redirect_edge_and_branch_force in
731 the only path that does an optimization, and this causes
732 an ICE when branch targets are in registers.
733 - find_if_case_2 doesn't do anything for the SHmedia after
734 reload except when it can redirect a tablejump - and
735 that's rather rare. */
736 flag_if_conversion2 = 0;
737 if (! strcmp (sh_div_str, "call"))
738 sh_div_strategy = SH_DIV_CALL;
739 else if (! strcmp (sh_div_str, "call2"))
740 sh_div_strategy = SH_DIV_CALL2;
741 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)
742 sh_div_strategy = SH_DIV_FP;
743 else if (! strcmp (sh_div_str, "inv"))
744 sh_div_strategy = SH_DIV_INV;
745 else if (! strcmp (sh_div_str, "inv:minlat"))
746 sh_div_strategy = SH_DIV_INV_MINLAT;
747 else if (! strcmp (sh_div_str, "inv20u"))
748 sh_div_strategy = SH_DIV_INV20U;
749 else if (! strcmp (sh_div_str, "inv20l"))
750 sh_div_strategy = SH_DIV_INV20L;
751 else if (! strcmp (sh_div_str, "inv:call2"))
752 sh_div_strategy = SH_DIV_INV_CALL2;
753 else if (! strcmp (sh_div_str, "inv:call"))
754 sh_div_strategy = SH_DIV_INV_CALL;
755 else if (! strcmp (sh_div_str, "inv:fp"))
758 sh_div_strategy = SH_DIV_INV_FP;
760 sh_div_strategy = SH_DIV_INV;
762 TARGET_CBRANCHDI4 = 0;
763 /* Assembler CFI isn't yet fully supported for SHmedia. */
764 flag_dwarf2_cfi_asm = 0;
769 /* Only the sh64-elf assembler fully supports .quad properly. */
770 targetm.asm_out.aligned_op.di = NULL;
771 targetm.asm_out.unaligned_op.di = NULL;
775 if (! strcmp (sh_div_str, "call-div1"))
776 sh_div_strategy = SH_DIV_CALL_DIV1;
777 else if (! strcmp (sh_div_str, "call-fp")
778 && (TARGET_FPU_DOUBLE
779 || (TARGET_HARD_SH4 && TARGET_SH2E)
780 || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))
781 sh_div_strategy = SH_DIV_CALL_FP;
782 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)
783 sh_div_strategy = SH_DIV_CALL_TABLE;
785 /* Pick one that makes most sense for the target in general.
786 It is not much good to use different functions depending
787 on -Os, since then we'll end up with two different functions
788 when some of the code is compiled for size, and some for
791 /* SH4 tends to emphasize speed. */
793 sh_div_strategy = SH_DIV_CALL_TABLE;
794 /* These have their own way of doing things. */
795 else if (TARGET_SH2A)
796 sh_div_strategy = SH_DIV_INTRINSIC;
797 /* ??? Should we use the integer SHmedia function instead? */
798 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
799 sh_div_strategy = SH_DIV_CALL_FP;
800 /* SH1 .. SH3 cores often go into small-footprint systems, so
801 default to the smallest implementation available. */
802 else if (TARGET_SH2) /* ??? EXPERIMENTAL */
803 sh_div_strategy = SH_DIV_CALL_TABLE;
805 sh_div_strategy = SH_DIV_CALL_DIV1;
808 TARGET_PRETEND_CMOVE = 0;
809 if (sh_divsi3_libfunc[0])
810 ; /* User supplied - leave it alone. */
811 else if (TARGET_DIVIDE_CALL_FP)
812 sh_divsi3_libfunc = "__sdivsi3_i4";
813 else if (TARGET_DIVIDE_CALL_TABLE)
814 sh_divsi3_libfunc = "__sdivsi3_i4i";
816 sh_divsi3_libfunc = "__sdivsi3_1";
818 sh_divsi3_libfunc = "__sdivsi3";
819 if (sh_branch_cost == -1)
821 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1;
823 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
824 if (! VALID_REGISTER_P (regno))
825 sh_register_names[regno][0] = '\0';
827 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
828 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
829 sh_additional_register_names[regno][0] = '\0';
831 if (flag_omit_frame_pointer == 2)
833 /* The debugging information is sufficient,
834 but gdb doesn't implement this yet */
836 flag_omit_frame_pointer
837 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);
839 flag_omit_frame_pointer = 0;
842 if ((flag_pic && ! TARGET_PREFERGOT)
843 || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
844 flag_no_function_cse = 1;
846 if (SMALL_REGISTER_CLASSES)
848 /* Never run scheduling before reload, since that can
849 break global alloc, and generates slower code anyway due
850 to the pressure on R0. */
851 /* Enable sched1 for SH4 if the user explicitly requests.
852 When sched1 is enabled, the ready queue will be reordered by
853 the target hooks if pressure is high. We can not do this for
854 PIC, SH3 and lower as they give spill failures for R0. */
855 if (!TARGET_HARD_SH4 || flag_pic)
856 flag_schedule_insns = 0;
857 /* ??? Current exception handling places basic block boundaries
858 after call_insns. It causes the high pressure on R0 and gives
859 spill failures for R0 in reload. See PR 22553 and the thread
861 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
862 else if (flag_exceptions)
864 if (flag_schedule_insns == 1)
865 warning (0, "ignoring -fschedule-insns because of exception handling bug");
866 flag_schedule_insns = 0;
868 else if (flag_schedule_insns == 2)
869 flag_schedule_insns = 0;
872 if (align_loops == 0)
873 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
874 if (align_jumps == 0)
875 align_jumps = 1 << CACHE_LOG;
876 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
877 align_jumps = TARGET_SHMEDIA ? 4 : 2;
879 /* Allocation boundary (in *bytes*) for the code of a function.
880 SH1: 32 bit alignment is faster, because instructions are always
881 fetched as a pair from a longword boundary.
882 SH2 .. SH5 : align to cache line start. */
883 if (align_functions == 0)
885 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
886 /* The linker relaxation code breaks when a function contains
887 alignments that are larger than that at the start of a
892 = align_loops > align_jumps ? align_loops : align_jumps;
894 /* Also take possible .long constants / mova tables int account. */
897 if (align_functions < min_align)
898 align_functions = min_align;
901 if (sh_fixed_range_str)
902 sh_fix_range (sh_fixed_range_str);
905 /* Print the operand address in x to the stream. */
908 print_operand_address (FILE *stream, rtx x)
910 switch (GET_CODE (x))
914 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
919 rtx base = XEXP (x, 0);
920 rtx index = XEXP (x, 1);
922 switch (GET_CODE (index))
925 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
926 reg_names[true_regnum (base)]);
932 int base_num = true_regnum (base);
933 int index_num = true_regnum (index);
935 fprintf (stream, "@(r0,%s)",
936 reg_names[MAX (base_num, index_num)]);
947 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
951 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
955 x = mark_constant_pool_use (x);
956 output_addr_const (stream, x);
961 /* Print operand x (an rtx) in assembler syntax to file stream
962 according to modifier code.
964 '.' print a .s if insn needs delay slot
965 ',' print LOCAL_LABEL_PREFIX
966 '@' print trap, rte or rts depending upon pragma interruptness
967 '#' output a nop if there is nothing to put in the delay slot
968 ''' print likelihood suffix (/u for unlikely).
969 '>' print branch target if -fverbose-asm
970 'O' print a constant without the #
971 'R' print the LSW of a dp value - changes if in little endian
972 'S' print the MSW of a dp value - changes if in little endian
973 'T' print the next word of a dp value - same as 'R' in big endian mode.
974 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
975 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
976 'N' print 'r63' if the operand is (const_int 0).
977 'd' print a V2SF reg as dN instead of fpN.
978 'm' print a pair `base,offset' or `base,index', for LD and ST.
979 'U' Likewise for {LD,ST}{HI,LO}.
980 'V' print the position of a single bit set.
981 'W' print the position of a single bit cleared.
982 't' print a memory address which is a register.
983 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
984 'o' output an operator. */
987 print_operand (FILE *stream, rtx x, int code)
990 enum machine_mode mode;
998 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
999 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
1000 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
1003 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
1006 trapa_attr = lookup_attribute ("trap_exit",
1007 DECL_ATTRIBUTES (current_function_decl));
1009 fprintf (stream, "trapa #%ld",
1010 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
1011 else if (sh_cfun_interrupt_handler_p ())
1013 if (sh_cfun_resbank_handler_p ())
1014 fprintf (stream, "resbank\n");
1015 fprintf (stream, "rte");
1018 fprintf (stream, "rts");
1021 /* Output a nop if there's nothing in the delay slot. */
1022 if (dbr_sequence_length () == 0)
1023 fprintf (stream, "\n\tnop");
1027 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1029 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
1030 fputs ("/u", stream);
1034 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
1036 fputs ("\t! target: ", stream);
1037 output_addr_const (stream, JUMP_LABEL (current_output_insn));
1041 x = mark_constant_pool_use (x);
1042 output_addr_const (stream, x);
1044 /* N.B.: %R / %S / %T adjust memory addresses by four.
1045 For SHMEDIA, that means they can be used to access the first and
1046 second 32 bit part of a 64 bit (or larger) value that
1047 might be held in floating point registers or memory.
1048 While they can be used to access 64 bit parts of a larger value
1049 held in general purpose registers, that won't work with memory -
1050 neither for fp registers, since the frxx names are used. */
1052 if (REG_P (x) || GET_CODE (x) == SUBREG)
1054 regno = true_regnum (x);
1055 regno += FP_REGISTER_P (regno) ? 1 : LSW;
1056 fputs (reg_names[regno], (stream));
1060 x = adjust_address (x, SImode, 4 * LSW);
1061 print_operand_address (stream, XEXP (x, 0));
1067 mode = GET_MODE (x);
1068 if (mode == VOIDmode)
1070 if (GET_MODE_SIZE (mode) >= 8)
1071 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
1073 print_operand (stream, sub, 0);
1075 output_operand_lossage ("invalid operand to %%R");
1079 if (REG_P (x) || GET_CODE (x) == SUBREG)
1081 regno = true_regnum (x);
1082 regno += FP_REGISTER_P (regno) ? 0 : MSW;
1083 fputs (reg_names[regno], (stream));
1087 x = adjust_address (x, SImode, 4 * MSW);
1088 print_operand_address (stream, XEXP (x, 0));
1094 mode = GET_MODE (x);
1095 if (mode == VOIDmode)
1097 if (GET_MODE_SIZE (mode) >= 8)
1098 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
1100 print_operand (stream, sub, 0);
1102 output_operand_lossage ("invalid operand to %%S");
1106 /* Next word of a double. */
1107 switch (GET_CODE (x))
1110 fputs (reg_names[REGNO (x) + 1], (stream));
1113 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1114 && GET_CODE (XEXP (x, 0)) != POST_INC)
1115 x = adjust_address (x, SImode, 4);
1116 print_operand_address (stream, XEXP (x, 0));
1124 gcc_assert (MEM_P (x));
1126 switch (GET_CODE (x))
1130 print_operand (stream, x, 0);
1138 switch (GET_CODE (x))
1140 case PLUS: fputs ("add", stream); break;
1141 case MINUS: fputs ("sub", stream); break;
1142 case MULT: fputs ("mul", stream); break;
1143 case DIV: fputs ("div", stream); break;
1144 case EQ: fputs ("eq", stream); break;
1145 case NE: fputs ("ne", stream); break;
1146 case GT: case LT: fputs ("gt", stream); break;
1147 case GE: case LE: fputs ("ge", stream); break;
1148 case GTU: case LTU: fputs ("gtu", stream); break;
1149 case GEU: case LEU: fputs ("geu", stream); break;
1158 && GET_CODE (XEXP (x, 0)) == PLUS
1159 && (REG_P (XEXP (XEXP (x, 0), 1))
1160 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
1161 fputc ('x', stream);
1167 switch (GET_MODE (x))
1169 case QImode: fputs (".b", stream); break;
1170 case HImode: fputs (".w", stream); break;
1171 case SImode: fputs (".l", stream); break;
1172 case SFmode: fputs (".s", stream); break;
1173 case DFmode: fputs (".d", stream); break;
1174 default: gcc_unreachable ();
1181 gcc_assert (MEM_P (x));
1185 switch (GET_CODE (x))
1189 print_operand (stream, x, 0);
1190 fputs (", 0", stream);
1194 print_operand (stream, XEXP (x, 0), 0);
1195 fputs (", ", stream);
1196 print_operand (stream, XEXP (x, 1), 0);
1206 int num = exact_log2 (INTVAL (x));
1207 gcc_assert (num >= 0);
1208 fprintf (stream, "#%d", num);
1214 int num = exact_log2 (~INTVAL (x));
1215 gcc_assert (num >= 0);
1216 fprintf (stream, "#%d", num);
1221 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
1223 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1227 if (x == CONST0_RTX (GET_MODE (x)))
1229 fprintf ((stream), "r63");
1232 goto default_output;
1234 if (CONST_INT_P (x))
1236 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1244 mode = GET_MODE (x);
1246 switch (GET_CODE (x))
1250 rtx inner = XEXP (x, 0);
1252 enum machine_mode inner_mode;
1254 /* We might see SUBREGs with vector mode registers inside. */
1255 if (GET_CODE (inner) == SUBREG
1256 && (GET_MODE_SIZE (GET_MODE (inner))
1257 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1258 && subreg_lowpart_p (inner))
1259 inner = SUBREG_REG (inner);
1260 if (CONST_INT_P (inner))
1262 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1263 goto default_output;
1265 inner_mode = GET_MODE (inner);
1266 if (GET_CODE (inner) == SUBREG
1267 && (GET_MODE_SIZE (GET_MODE (inner))
1268 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1269 && REG_P (SUBREG_REG (inner)))
1271 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1272 GET_MODE (SUBREG_REG (inner)),
1273 SUBREG_BYTE (inner),
1275 inner = SUBREG_REG (inner);
1277 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
1279 /* Floating point register pairs are always big endian;
1280 general purpose registers are 64 bit wide. */
1281 regno = REGNO (inner);
1282 regno = (HARD_REGNO_NREGS (regno, inner_mode)
1283 - HARD_REGNO_NREGS (regno, mode))
1291 /* FIXME: We need this on SHmedia32 because reload generates
1292 some sign-extended HI or QI loads into DImode registers
1293 but, because Pmode is SImode, the address ends up with a
1294 subreg:SI of the DImode register. Maybe reload should be
1295 fixed so as to apply alter_subreg to such loads? */
1297 gcc_assert (trapping_target_operand (x, VOIDmode));
1298 x = XEXP (XEXP (x, 2), 0);
1299 goto default_output;
1301 gcc_assert (SUBREG_BYTE (x) == 0
1302 && REG_P (SUBREG_REG (x)));
1310 if (FP_REGISTER_P (regno)
1311 && mode == V16SFmode)
1312 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1313 else if (FP_REGISTER_P (REGNO (x))
1314 && mode == V4SFmode)
1315 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1317 && mode == V2SFmode)
1318 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1319 else if (FP_REGISTER_P (REGNO (x))
1320 && GET_MODE_SIZE (mode) > 4)
1321 fprintf ((stream), "d%s", reg_names[regno] + 1);
1323 fputs (reg_names[regno], (stream));
1327 output_address (XEXP (x, 0));
1332 fputc ('#', stream);
1333 output_addr_const (stream, x);
1341 /* Encode symbol attributes of a SYMBOL_REF into its
1342 SYMBOL_REF_FLAGS. */
1344 sh_encode_section_info (tree decl, rtx rtl, int first)
1346 default_encode_section_info (decl, rtl, first);
1348 if (TREE_CODE (decl) == FUNCTION_DECL
1349 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1350 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1353 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1355 force_into (rtx value, rtx target)
1357 value = force_operand (value, target);
1358 if (! rtx_equal_p (value, target))
1359 emit_insn (gen_move_insn (target, value));
1362 /* Emit code to perform a block move. Choose the best method.
1364 OPERANDS[0] is the destination.
1365 OPERANDS[1] is the source.
1366 OPERANDS[2] is the size.
1367 OPERANDS[3] is the alignment safe to use. */
1370 expand_block_move (rtx *operands)
1372 int align = INTVAL (operands[3]);
1373 int constp = (CONST_INT_P (operands[2]));
1374 int bytes = (constp ? INTVAL (operands[2]) : 0);
1379 /* If we could use mov.l to move words and dest is word-aligned, we
1380 can use movua.l for loads and still generate a relatively short
1381 and efficient sequence. */
1382 if (TARGET_SH4A_ARCH && align < 4
1383 && MEM_ALIGN (operands[0]) >= 32
1384 && can_move_by_pieces (bytes, 32))
1386 rtx dest = copy_rtx (operands[0]);
1387 rtx src = copy_rtx (operands[1]);
1388 /* We could use different pseudos for each copied word, but
1389 since movua can only load into r0, it's kind of
1391 rtx temp = gen_reg_rtx (SImode);
1392 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1395 while (copied + 4 <= bytes)
1397 rtx to = adjust_address (dest, SImode, copied);
1398 rtx from = adjust_automodify_address (src, BLKmode,
1401 set_mem_size (from, GEN_INT (4));
1402 emit_insn (gen_movua (temp, from));
1403 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1404 emit_move_insn (to, temp);
1409 move_by_pieces (adjust_address (dest, BLKmode, copied),
1410 adjust_automodify_address (src, BLKmode,
1412 bytes - copied, align, 0);
1417 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1418 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1419 if (align < 4 || (bytes % 4 != 0))
1422 if (TARGET_HARD_SH4)
1426 else if (bytes == 12)
1428 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1429 rtx r4 = gen_rtx_REG (SImode, 4);
1430 rtx r5 = gen_rtx_REG (SImode, 5);
1432 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1433 force_into (XEXP (operands[0], 0), r4);
1434 force_into (XEXP (operands[1], 0), r5);
1435 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1438 else if (! TARGET_SMALLCODE)
1440 const char *entry_name;
1441 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1443 rtx r4 = gen_rtx_REG (SImode, 4);
1444 rtx r5 = gen_rtx_REG (SImode, 5);
1445 rtx r6 = gen_rtx_REG (SImode, 6);
1447 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1448 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1449 force_into (XEXP (operands[0], 0), r4);
1450 force_into (XEXP (operands[1], 0), r5);
1452 dwords = bytes >> 3;
1453 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1454 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1463 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1464 rtx r4 = gen_rtx_REG (SImode, 4);
1465 rtx r5 = gen_rtx_REG (SImode, 5);
1467 sprintf (entry, "__movmemSI%d", bytes);
1468 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1469 force_into (XEXP (operands[0], 0), r4);
1470 force_into (XEXP (operands[1], 0), r5);
1471 emit_insn (gen_block_move_real (func_addr_rtx));
1475 /* This is the same number of bytes as a memcpy call, but to a different
1476 less common function name, so this will occasionally use more space. */
1477 if (! TARGET_SMALLCODE)
1479 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1480 int final_switch, while_loop;
1481 rtx r4 = gen_rtx_REG (SImode, 4);
1482 rtx r5 = gen_rtx_REG (SImode, 5);
1483 rtx r6 = gen_rtx_REG (SImode, 6);
1485 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1486 force_into (XEXP (operands[0], 0), r4);
1487 force_into (XEXP (operands[1], 0), r5);
1489 /* r6 controls the size of the move. 16 is decremented from it
1490 for each 64 bytes moved. Then the negative bit left over is used
1491 as an index into a list of move instructions. e.g., a 72 byte move
1492 would be set up with size(r6) = 14, for one iteration through the
1493 big while loop, and a switch of -2 for the last part. */
1495 final_switch = 16 - ((bytes / 4) % 16);
1496 while_loop = ((bytes / 4) / 16 - 1) * 16;
1497 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1498 emit_insn (gen_block_lump_real (func_addr_rtx));
1505 /* Prepare operands for a move define_expand; specifically, one of the
1506 operands must be in a register. */
1509 prepare_move_operands (rtx operands[], enum machine_mode mode)
1511 if ((mode == SImode || mode == DImode)
1513 && ! ((mode == Pmode || mode == ptr_mode)
1514 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1517 if (SYMBOLIC_CONST_P (operands[1]))
1519 if (MEM_P (operands[0]))
1520 operands[1] = force_reg (Pmode, operands[1]);
1521 else if (TARGET_SHMEDIA
1522 && GET_CODE (operands[1]) == LABEL_REF
1523 && target_reg_operand (operands[0], mode))
1527 temp = (!can_create_pseudo_p ()
1529 : gen_reg_rtx (Pmode));
1530 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1533 else if (GET_CODE (operands[1]) == CONST
1534 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1535 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1537 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1538 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1540 operands[1] = expand_binop (mode, add_optab, temp,
1541 XEXP (XEXP (operands[1], 0), 1),
1542 (!can_create_pseudo_p ()
1544 : gen_reg_rtx (Pmode)),
1545 0, OPTAB_LIB_WIDEN);
1549 if (! reload_in_progress && ! reload_completed)
1551 /* Copy the source to a register if both operands aren't registers. */
1552 if (! register_operand (operands[0], mode)
1553 && ! sh_register_operand (operands[1], mode))
1554 operands[1] = copy_to_mode_reg (mode, operands[1]);
1556 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1558 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1559 except that we can't use that function because it is static. */
1560 rtx new_rtx = change_address (operands[0], mode, 0);
1561 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1562 operands[0] = new_rtx;
1565 /* This case can happen while generating code to move the result
1566 of a library call to the target. Reject `st r0,@(rX,rY)' because
1567 reload will fail to find a spill register for rX, since r0 is already
1568 being used for the source. */
1570 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1571 && MEM_P (operands[0])
1572 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1573 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1574 operands[1] = copy_to_mode_reg (mode, operands[1]);
1577 if (mode == Pmode || mode == ptr_mode)
1580 enum tls_model tls_kind;
1584 if (GET_CODE (op1) == CONST
1585 && GET_CODE (XEXP (op1, 0)) == PLUS
1586 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1589 opc = XEXP (XEXP (op1, 0), 1);
1590 op1 = XEXP (XEXP (op1, 0), 0);
1595 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1597 rtx tga_op1, tga_ret, tmp, tmp2;
1601 case TLS_MODEL_GLOBAL_DYNAMIC:
1602 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1603 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1607 case TLS_MODEL_LOCAL_DYNAMIC:
1608 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1609 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1611 tmp = gen_reg_rtx (Pmode);
1612 emit_move_insn (tmp, tga_ret);
1614 if (register_operand (op0, Pmode))
1617 tmp2 = gen_reg_rtx (Pmode);
1619 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1623 case TLS_MODEL_INITIAL_EXEC:
1626 /* Don't schedule insns for getting GOT address when
1627 the first scheduling is enabled, to avoid spill
1629 if (flag_schedule_insns)
1630 emit_insn (gen_blockage ());
1631 emit_insn (gen_GOTaddr2picreg ());
1632 emit_use (gen_rtx_REG (SImode, PIC_REG));
1633 if (flag_schedule_insns)
1634 emit_insn (gen_blockage ());
1636 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1637 tmp = gen_sym2GOTTPOFF (op1);
1638 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1642 case TLS_MODEL_LOCAL_EXEC:
1643 tmp2 = gen_reg_rtx (Pmode);
1644 emit_insn (gen_load_gbr (tmp2));
1645 tmp = gen_reg_rtx (Pmode);
1646 emit_insn (gen_symTPOFF2reg (tmp, op1));
1648 if (register_operand (op0, Pmode))
1651 op1 = gen_reg_rtx (Pmode);
1653 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1660 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1669 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1670 enum rtx_code comparison)
1673 rtx scratch = NULL_RTX;
1675 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1676 comparison = GET_CODE (operands[0]);
1678 scratch = operands[4];
1679 if (CONST_INT_P (operands[1])
1680 && !CONST_INT_P (operands[2]))
1682 rtx tmp = operands[1];
1684 operands[1] = operands[2];
1686 comparison = swap_condition (comparison);
1688 if (CONST_INT_P (operands[2]))
1690 HOST_WIDE_INT val = INTVAL (operands[2]);
1691 if ((val == -1 || val == -0x81)
1692 && (comparison == GT || comparison == LE))
1694 comparison = (comparison == GT) ? GE : LT;
1695 operands[2] = gen_int_mode (val + 1, mode);
1697 else if ((val == 1 || val == 0x80)
1698 && (comparison == GE || comparison == LT))
1700 comparison = (comparison == GE) ? GT : LE;
1701 operands[2] = gen_int_mode (val - 1, mode);
1703 else if (val == 1 && (comparison == GEU || comparison == LTU))
1705 comparison = (comparison == GEU) ? NE : EQ;
1706 operands[2] = CONST0_RTX (mode);
1708 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1710 comparison = (comparison == GEU) ? GTU : LEU;
1711 operands[2] = gen_int_mode (val - 1, mode);
1713 else if (val == 0 && (comparison == GTU || comparison == LEU))
1714 comparison = (comparison == GTU) ? NE : EQ;
1715 else if (mode == SImode
1716 && ((val == 0x7fffffff
1717 && (comparison == GTU || comparison == LEU))
1718 || ((unsigned HOST_WIDE_INT) val
1719 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1720 && (comparison == GEU || comparison == LTU))))
1722 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1723 operands[2] = CONST0_RTX (mode);
1727 if (can_create_pseudo_p ())
1728 operands[1] = force_reg (mode, op1);
1729 /* When we are handling DImode comparisons, we want to keep constants so
1730 that we can optimize the component comparisons; however, memory loads
1731 are better issued as a whole so that they can be scheduled well.
1732 SImode equality comparisons allow I08 constants, but only when they
1733 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1734 into a register, that register might as well be r0, and we allow the
1735 constant. If it is already in a register, this is likely to be
1736 allocated to a different hard register, thus we load the constant into
1737 a register unless it is zero. */
1738 if (!REG_P (operands[2])
1739 && (!CONST_INT_P (operands[2])
1740 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1741 && ((comparison != EQ && comparison != NE)
1742 || (REG_P (op1) && REGNO (op1) != R0_REG)
1743 || !satisfies_constraint_I08 (operands[2])))))
1745 if (scratch && GET_MODE (scratch) == mode)
1747 emit_move_insn (scratch, operands[2]);
1748 operands[2] = scratch;
1750 else if (can_create_pseudo_p ())
1751 operands[2] = force_reg (mode, operands[2]);
1757 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1759 rtx (*branch_expander) (rtx) = gen_branch_true;
1762 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1765 case NE: case LT: case LE: case LTU: case LEU:
1766 comparison = reverse_condition (comparison);
1767 branch_expander = gen_branch_false;
1770 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1771 gen_rtx_fmt_ee (comparison, SImode,
1772 operands[1], operands[2])));
1773 jump = emit_jump_insn (branch_expander (operands[3]));
1774 if (probability >= 0)
1775 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1779 /* ??? How should we distribute probabilities when more than one branch
1780 is generated. So far we only have soem ad-hoc observations:
1781 - If the operands are random, they are likely to differ in both parts.
1782 - If comparing items in a hash chain, the operands are random or equal;
1783 operation should be EQ or NE.
1784 - If items are searched in an ordered tree from the root, we can expect
1785 the highpart to be unequal about half of the time; operation should be
1786 an inequality comparison, operands non-constant, and overall probability
1787 about 50%. Likewise for quicksort.
1788 - Range checks will be often made against constants. Even if we assume for
1789 simplicity an even distribution of the non-constant operand over a
1790 sub-range here, the same probability could be generated with differently
1791 wide sub-ranges - as long as the ratio of the part of the subrange that
1792 is before the threshold to the part that comes after the threshold stays
1793 the same. Thus, we can't really tell anything here;
1794 assuming random distribution is at least simple.
1798 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1800 enum rtx_code msw_taken, msw_skip, lsw_taken;
1801 rtx skip_label = NULL_RTX;
1802 rtx op1h, op1l, op2h, op2l;
1805 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1806 rtx scratch = operands[4];
1808 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1809 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1810 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1811 op1l = gen_lowpart (SImode, operands[1]);
1812 op2l = gen_lowpart (SImode, operands[2]);
1813 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1814 prob = split_branch_probability;
1815 rev_prob = REG_BR_PROB_BASE - prob;
1818 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1819 That costs 1 cycle more when the first branch can be predicted taken,
1820 but saves us mispredicts because only one branch needs prediction.
1821 It also enables generating the cmpeqdi_t-1 pattern. */
1823 if (TARGET_CMPEQDI_T)
1825 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1826 emit_jump_insn (gen_branch_true (operands[3]));
1833 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1835 msw_skip_prob = rev_prob;
1836 if (REG_BR_PROB_BASE <= 65535)
1837 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1840 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1844 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1845 / ((HOST_WIDEST_INT) prob << 32)))
1851 if (TARGET_CMPEQDI_T)
1853 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1854 emit_jump_insn (gen_branch_false (operands[3]));
1858 msw_taken_prob = prob;
1863 msw_taken = comparison;
1864 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1866 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1867 msw_skip = swap_condition (msw_taken);
1871 if (op2l == CONST0_RTX (SImode))
1872 msw_taken = comparison;
1875 msw_taken = comparison == GE ? GT : GTU;
1876 msw_skip = swap_condition (msw_taken);
1881 msw_taken = comparison;
1882 if (op2l == CONST0_RTX (SImode))
1884 msw_skip = swap_condition (msw_taken);
1888 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1889 msw_taken = comparison;
1893 if (comparison == LE)
1895 else if (op2h != CONST0_RTX (SImode))
1899 msw_skip = swap_condition (msw_taken);
1902 default: return false;
1904 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1905 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1906 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1907 if (comparison != EQ && comparison != NE && num_branches > 1)
1909 if (!CONSTANT_P (operands[2])
1910 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1911 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1913 msw_taken_prob = prob / 2U;
1915 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1916 lsw_taken_prob = prob;
1920 msw_taken_prob = prob;
1921 msw_skip_prob = REG_BR_PROB_BASE;
1922 /* ??? If we have a constant op2h, should we use that when
1923 calculating lsw_taken_prob? */
1924 lsw_taken_prob = prob;
1929 operands[4] = NULL_RTX;
1930 if (reload_completed
1931 && ! arith_reg_or_0_operand (op2h, SImode)
1932 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
1933 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
1934 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
1936 emit_move_insn (scratch, operands[2]);
1937 operands[2] = scratch;
1939 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1940 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1941 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1943 rtx taken_label = operands[3];
1945 /* Operands were possibly modified, but msw_skip doesn't expect this.
1946 Always use the original ones. */
1947 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1953 operands[3] = skip_label = gen_label_rtx ();
1954 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1955 operands[3] = taken_label;
1959 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
1961 if (reload_completed
1962 && ! arith_reg_or_0_operand (op2l, SImode)
1963 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
1965 emit_move_insn (scratch, operands[2]);
1966 operands[2] = scratch;
1968 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1970 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1971 emit_label (skip_label);
1975 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
1978 sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
1980 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1982 insn = gen_rtx_PARALLEL (VOIDmode,
1984 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1985 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1991 /* Prepare the operands for an scc instruction; make sure that the
1992 compare has been done and the result is in T_REG. */
1994 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
1996 rtx t_reg = gen_rtx_REG (SImode, T_REG);
1997 enum rtx_code oldcode = code;
1998 enum machine_mode mode;
2000 /* First need a compare insn. */
2004 /* It isn't possible to handle this case. */
2021 if (code != oldcode)
2028 mode = GET_MODE (op0);
2029 if (mode == VOIDmode)
2030 mode = GET_MODE (op1);
2032 op0 = force_reg (mode, op0);
2033 if ((code != EQ && code != NE
2034 && (op1 != const0_rtx
2035 || code == GTU || code == GEU || code == LTU || code == LEU))
2036 || (mode == DImode && op1 != const0_rtx)
2037 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2038 op1 = force_reg (mode, op1);
2040 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
2041 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2046 sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
2049 rtx target = gen_reg_rtx (SImode);
2052 gcc_assert (TARGET_SHMEDIA);
2061 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
2062 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2072 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
2073 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2091 rtx t2 = gen_reg_rtx (DImode);
2092 emit_insn (gen_extendsidi2 (t2, target));
2096 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
2099 /* Called from the md file, set up the operands of a compare instruction. */
2102 sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
2104 enum rtx_code code = GET_CODE (operands[0]);
2105 enum rtx_code branch_code;
2106 rtx op0 = operands[1];
2107 rtx op1 = operands[2];
2109 bool need_ccmpeq = false;
2111 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
2113 op0 = force_reg (mode, op0);
2114 op1 = force_reg (mode, op1);
2118 if (code != EQ || mode == DImode)
2120 /* Force args into regs, since we can't use constants here. */
2121 op0 = force_reg (mode, op0);
2122 if (op1 != const0_rtx || code == GTU || code == GEU)
2123 op1 = force_reg (mode, op1);
2127 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2130 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2131 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2133 tem = op0, op0 = op1, op1 = tem;
2134 code = swap_condition (code);
2137 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2140 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2145 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2146 to EQ/GT respectively. */
2147 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2164 branch_code = reverse_condition (code);
2170 insn = gen_rtx_SET (VOIDmode,
2171 gen_rtx_REG (SImode, T_REG),
2172 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2174 sh_emit_set_t_insn (insn, mode);
2176 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2178 if (branch_code == code)
2179 emit_jump_insn (gen_branch_true (operands[3]));
2181 emit_jump_insn (gen_branch_false (operands[3]));
2185 sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
2187 enum rtx_code code = GET_CODE (operands[1]);
2188 rtx op0 = operands[2];
2189 rtx op1 = operands[3];
2191 bool invert = false;
2194 op0 = force_reg (mode, op0);
2195 if ((code != EQ && code != NE
2196 && (op1 != const0_rtx
2197 || code == GTU || code == GEU || code == LTU || code == LEU))
2198 || (mode == DImode && op1 != const0_rtx)
2199 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2200 op1 = force_reg (mode, op1);
2202 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2204 if (code == LT || code == LE)
2206 code = swap_condition (code);
2207 tem = op0, op0 = op1, op1 = tem;
2213 lab = gen_label_rtx ();
2214 sh_emit_scc_to_t (EQ, op0, op1);
2215 emit_jump_insn (gen_branch_true (lab));
2232 sh_emit_scc_to_t (code, op0, op1);
2236 emit_insn (gen_movnegt (operands[0]));
2238 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
2241 /* Functions to output assembly code. */
2243 /* Return a sequence of instructions to perform DI or DF move.
2245 Since the SH cannot move a DI or DF in one instruction, we have
2246 to take care when we see overlapping source and dest registers. */
2249 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2250 enum machine_mode mode)
2252 rtx dst = operands[0];
2253 rtx src = operands[1];
2256 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
2257 return "mov.l %T1,%0\n\tmov.l %1,%0";
2259 if (register_operand (dst, mode)
2260 && register_operand (src, mode))
2262 if (REGNO (src) == MACH_REG)
2263 return "sts mach,%S0\n\tsts macl,%R0";
2265 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2266 when mov.d r1,r0 do r1->r0 then r2->r1. */
2268 if (REGNO (src) + 1 == REGNO (dst))
2269 return "mov %T1,%T0\n\tmov %1,%0";
2271 return "mov %1,%0\n\tmov %T1,%T0";
2273 else if (CONST_INT_P (src))
2275 if (INTVAL (src) < 0)
2276 output_asm_insn ("mov #-1,%S0", operands);
2278 output_asm_insn ("mov #0,%S0", operands);
2280 return "mov %1,%R0";
2282 else if (MEM_P (src))
2285 int dreg = REGNO (dst);
2286 rtx inside = XEXP (src, 0);
2288 switch (GET_CODE (inside))
2291 ptrreg = REGNO (inside);
2295 ptrreg = subreg_regno (inside);
2299 ptrreg = REGNO (XEXP (inside, 0));
2300 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2301 an offsettable address. Unfortunately, offsettable addresses use
2302 QImode to check the offset, and a QImode offsettable address
2303 requires r0 for the other operand, which is not currently
2304 supported, so we can't use the 'o' constraint.
2305 Thus we must check for and handle r0+REG addresses here.
2306 We punt for now, since this is likely very rare. */
2307 gcc_assert (!REG_P (XEXP (inside, 1)));
2311 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2313 return "mov.l %1,%0\n\tmov.l %1,%T0";
2318 /* Work out the safe way to copy. Copy into the second half first. */
2320 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2323 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2326 /* Print an instruction which would have gone into a delay slot after
2327 another instruction, but couldn't because the other instruction expanded
2328 into a sequence where putting the slot insn at the end wouldn't work. */
2331 print_slot (rtx insn)
2333 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
2335 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2339 output_far_jump (rtx insn, rtx op)
2341 struct { rtx lab, reg, op; } this_jmp;
2342 rtx braf_base_lab = NULL_RTX;
2345 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2348 this_jmp.lab = gen_label_rtx ();
2352 && offset - get_attr_length (insn) <= 32766)
2355 jump = "mov.w %O0,%1; braf %1";
2363 jump = "mov.l %O0,%1; braf %1";
2365 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2368 jump = "mov.l %O0,%1; jmp @%1";
2370 /* If we have a scratch register available, use it. */
2371 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2372 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2374 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2375 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2376 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2377 output_asm_insn (jump, &this_jmp.lab);
2378 if (dbr_sequence_length ())
2379 print_slot (final_sequence);
2381 output_asm_insn ("nop", 0);
2385 /* Output the delay slot insn first if any. */
2386 if (dbr_sequence_length ())
2387 print_slot (final_sequence);
2389 this_jmp.reg = gen_rtx_REG (SImode, 13);
2390 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2391 Fortunately, MACL is fixed and call-clobbered, and we never
2392 need its value across jumps, so save r13 in it instead of in
2395 output_asm_insn ("lds r13, macl", 0);
2397 output_asm_insn ("mov.l r13,@-r15", 0);
2398 output_asm_insn (jump, &this_jmp.lab);
2400 output_asm_insn ("sts macl, r13", 0);
2402 output_asm_insn ("mov.l @r15+,r13", 0);
2404 if (far && flag_pic && TARGET_SH2)
2406 braf_base_lab = gen_label_rtx ();
2407 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2408 CODE_LABEL_NUMBER (braf_base_lab));
2411 output_asm_insn (".align 2", 0);
2412 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2414 if (far && flag_pic)
2417 this_jmp.lab = braf_base_lab;
2418 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2421 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2425 /* Local label counter, used for constants in the pool and inside
2426 pattern branches. */
2428 static int lf = 100;
2430 /* Output code for ordinary branches. */
2433 output_branch (int logic, rtx insn, rtx *operands)
2435 switch (get_attr_length (insn))
2438 /* This can happen if filling the delay slot has caused a forward
2439 branch to exceed its range (we could reverse it, but only
2440 when we know we won't overextend other branches; this should
2441 best be handled by relaxation).
2442 It can also happen when other condbranches hoist delay slot insn
2443 from their destination, thus leading to code size increase.
2444 But the branch will still be in the range -4092..+4098 bytes. */
2449 /* The call to print_slot will clobber the operands. */
2450 rtx op0 = operands[0];
2452 /* If the instruction in the delay slot is annulled (true), then
2453 there is no delay slot where we can put it now. The only safe
2454 place for it is after the label. final will do that by default. */
2457 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2458 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2460 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2461 ASSEMBLER_DIALECT ? "/" : ".", label);
2462 print_slot (final_sequence);
2465 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2467 output_asm_insn ("bra\t%l0", &op0);
2468 fprintf (asm_out_file, "\tnop\n");
2469 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2473 /* When relaxing, handle this like a short branch. The linker
2474 will fix it up if it still doesn't fit after relaxation. */
2476 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2478 /* These are for SH2e, in which we have to account for the
2479 extra nop because of the hardware bug in annulled branches. */
2485 gcc_assert (!final_sequence
2486 || !(INSN_ANNULLED_BRANCH_P
2487 (XVECEXP (final_sequence, 0, 0))));
2488 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2490 ASSEMBLER_DIALECT ? "/" : ".", label);
2491 fprintf (asm_out_file, "\tnop\n");
2492 output_asm_insn ("bra\t%l0", operands);
2493 fprintf (asm_out_file, "\tnop\n");
2494 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2498 /* When relaxing, fall through. */
2503 sprintf (buffer, "b%s%ss\t%%l0",
2505 ASSEMBLER_DIALECT ? "/" : ".");
2506 output_asm_insn (buffer, &operands[0]);
2511 /* There should be no longer branches now - that would
2512 indicate that something has destroyed the branches set
2513 up in machine_dependent_reorg. */
2518 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2519 fill in operands 9 as a label to the successor insn.
2520 We try to use jump threading where possible.
2521 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2522 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2523 follow jmp and bt, if the address is in range. */
2525 output_branchy_insn (enum rtx_code code, const char *templ,
2526 rtx insn, rtx *operands)
2528 rtx next_insn = NEXT_INSN (insn);
2530 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2532 rtx src = SET_SRC (PATTERN (next_insn));
2533 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2535 /* Following branch not taken */
2536 operands[9] = gen_label_rtx ();
2537 emit_label_after (operands[9], next_insn);
2538 INSN_ADDRESSES_NEW (operands[9],
2539 INSN_ADDRESSES (INSN_UID (next_insn))
2540 + get_attr_length (next_insn));
2545 int offset = (branch_dest (next_insn)
2546 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2547 if (offset >= -252 && offset <= 258)
2549 if (GET_CODE (src) == IF_THEN_ELSE)
2551 src = XEXP (src, 1);
2557 operands[9] = gen_label_rtx ();
2558 emit_label_after (operands[9], insn);
2559 INSN_ADDRESSES_NEW (operands[9],
2560 INSN_ADDRESSES (INSN_UID (insn))
2561 + get_attr_length (insn));
2566 output_ieee_ccmpeq (rtx insn, rtx *operands)
2568 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2572 /* Output the start of the assembler file. */
2575 sh_file_start (void)
2577 default_file_start ();
2580 /* Declare the .directive section before it is used. */
2581 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2582 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2586 /* We need to show the text section with the proper
2587 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2588 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2589 will complain. We can teach GAS specifically about the
2590 default attributes for our choice of text section, but
2591 then we would have to change GAS again if/when we change
2592 the text section name. */
2593 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2595 /* Switch to the data section so that the coffsem symbol
2596 isn't in the text section. */
2597 switch_to_section (data_section);
2599 if (TARGET_LITTLE_ENDIAN)
2600 fputs ("\t.little\n", asm_out_file);
2604 if (TARGET_SHCOMPACT)
2605 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2606 else if (TARGET_SHMEDIA)
2607 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2608 TARGET_SHMEDIA64 ? 64 : 32);
2612 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2615 unspec_caller_rtx_p (rtx pat)
2620 split_const (pat, &base, &offset);
2621 if (GET_CODE (base) == UNSPEC)
2623 if (XINT (base, 1) == UNSPEC_CALLER)
2625 for (i = 0; i < XVECLEN (base, 0); i++)
2626 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2632 /* Indicate that INSN cannot be duplicated. This is true for insn
2633 that generates a unique label. */
2636 sh_cannot_copy_insn_p (rtx insn)
2640 if (!reload_completed || !flag_pic)
2643 if (!NONJUMP_INSN_P (insn))
2645 if (asm_noperands (insn) >= 0)
2648 pat = PATTERN (insn);
2649 if (GET_CODE (pat) != SET)
2651 pat = SET_SRC (pat);
2653 if (unspec_caller_rtx_p (pat))
2659 /* Actual number of instructions used to make a shift by N. */
2660 static const char ashiftrt_insns[] =
2661 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2663 /* Left shift and logical right shift are the same. */
2664 static const char shift_insns[] =
2665 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2667 /* Individual shift amounts needed to get the above length sequences.
2668 One bit right shifts clobber the T bit, so when possible, put one bit
2669 shifts in the middle of the sequence, so the ends are eligible for
2670 branch delay slots. */
2671 static const short shift_amounts[32][5] = {
2672 {0}, {1}, {2}, {2, 1},
2673 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2674 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2675 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2676 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2677 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2678 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2679 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2681 /* Likewise, but for shift amounts < 16, up to three highmost bits
2682 might be clobbered. This is typically used when combined with some
2683 kind of sign or zero extension. */
2685 static const char ext_shift_insns[] =
2686 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2688 static const short ext_shift_amounts[32][4] = {
2689 {0}, {1}, {2}, {2, 1},
2690 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2691 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2692 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2693 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2694 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2695 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2696 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2698 /* Assuming we have a value that has been sign-extended by at least one bit,
2699 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2700 to shift it by N without data loss, and quicker than by other means? */
2701 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2703 /* This is used in length attributes in sh.md to help compute the length
2704 of arbitrary constant shift instructions. */
2707 shift_insns_rtx (rtx insn)
2709 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2710 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2711 enum rtx_code shift_code = GET_CODE (set_src);
2716 return ashiftrt_insns[shift_count];
2719 return shift_insns[shift_count];
2725 /* Return the cost of a shift. */
2735 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2737 if (GET_MODE (x) == DImode
2738 && CONST_INT_P (XEXP (x, 1))
2739 && INTVAL (XEXP (x, 1)) == 1)
2742 /* Everything else is invalid, because there is no pattern for it. */
2745 /* If shift by a non constant, then this will be expensive. */
2746 if (!CONST_INT_P (XEXP (x, 1)))
2747 return SH_DYNAMIC_SHIFT_COST;
2749 /* Otherwise, return the true cost in instructions. Cope with out of range
2750 shift counts more or less arbitrarily. */
2751 value = INTVAL (XEXP (x, 1)) & 31;
2753 if (GET_CODE (x) == ASHIFTRT)
2755 int cost = ashiftrt_insns[value];
2756 /* If SH3, then we put the constant in a reg and use shad. */
2757 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2758 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2762 return shift_insns[value];
2765 /* Return the cost of an AND operation. */
2772 /* Anding with a register is a single cycle and instruction. */
2773 if (!CONST_INT_P (XEXP (x, 1)))
2776 i = INTVAL (XEXP (x, 1));
2780 if (satisfies_constraint_I10 (XEXP (x, 1))
2781 || satisfies_constraint_J16 (XEXP (x, 1)))
2784 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
2787 /* These constants are single cycle extu.[bw] instructions. */
2788 if (i == 0xff || i == 0xffff)
2790 /* Constants that can be used in an and immediate instruction in a single
2791 cycle, but this requires r0, so make it a little more expensive. */
2792 if (CONST_OK_FOR_K08 (i))
2794 /* Constants that can be loaded with a mov immediate and an and.
2795 This case is probably unnecessary. */
2796 if (CONST_OK_FOR_I08 (i))
2798 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2799 This case is probably unnecessary. */
2803 /* Return the cost of an addition or a subtraction. */
2808 /* Adding a register is a single cycle insn. */
2809 if (REG_P (XEXP (x, 1))
2810 || GET_CODE (XEXP (x, 1)) == SUBREG)
2813 /* Likewise for small constants. */
2814 if (CONST_INT_P (XEXP (x, 1))
2815 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2819 switch (GET_CODE (XEXP (x, 1)))
2824 return TARGET_SHMEDIA64 ? 5 : 3;
2827 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2829 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2831 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2839 /* Any other constant requires a 2 cycle pc-relative load plus an
2844 /* Return the cost of a multiply. */
2846 multcosts (rtx x ATTRIBUTE_UNUSED)
2848 if (sh_multcost >= 0)
2851 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2852 accept constants. Ideally, we would use a cost of one or two and
2853 add the cost of the operand, but disregard the latter when inside loops
2854 and loop invariant code motion is still to follow.
2855 Using a multiply first and splitting it later if it's a loss
2856 doesn't work because of different sign / zero extension semantics
2857 of multiplies vs. shifts. */
2858 return TARGET_SMALLCODE ? 2 : 3;
2862 /* We have a mul insn, so we can never take more than the mul and the
2863 read of the mac reg, but count more because of the latency and extra
2865 if (TARGET_SMALLCODE)
2870 /* If we're aiming at small code, then just count the number of
2871 insns in a multiply call sequence. */
2872 if (TARGET_SMALLCODE)
2875 /* Otherwise count all the insns in the routine we'd be calling too. */
2879 /* Compute a (partial) cost for rtx X. Return true if the complete
2880 cost has been computed, and false if subexpressions should be
2881 scanned. In either case, *TOTAL contains the cost result. */
2884 sh_rtx_costs (rtx x, int code, int outer_code, int *total,
2885 bool speed ATTRIBUTE_UNUSED)
2892 if (INTVAL (x) == 0)
2894 else if (outer_code == AND && and_operand ((x), DImode))
2896 else if ((outer_code == IOR || outer_code == XOR
2897 || outer_code == PLUS)
2898 && CONST_OK_FOR_I10 (INTVAL (x)))
2900 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2901 *total = COSTS_N_INSNS (outer_code != SET);
2902 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2903 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2904 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2905 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2907 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2910 if (CONST_OK_FOR_I08 (INTVAL (x)))
2912 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2913 && CONST_OK_FOR_K08 (INTVAL (x)))
2915 /* prepare_cmp_insn will force costly constants int registers before
2916 the cbranch[sd]i4 patterns can see them, so preserve potentially
2917 interesting ones not covered by I08 above. */
2918 else if (outer_code == COMPARE
2919 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2920 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2921 || INTVAL (x) == 0x7fffffff
2922 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2931 if (TARGET_SHMEDIA64)
2932 *total = COSTS_N_INSNS (4);
2933 else if (TARGET_SHMEDIA32)
2934 *total = COSTS_N_INSNS (2);
2941 *total = COSTS_N_INSNS (4);
2942 /* prepare_cmp_insn will force costly constants int registers before
2943 the cbranchdi4 pattern can see them, so preserve potentially
2944 interesting ones. */
2945 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2951 if (x == CONST0_RTX (GET_MODE (x)))
2953 else if (sh_1el_vec (x, VOIDmode))
2954 *total = outer_code != SET;
2955 if (sh_rep_vec (x, VOIDmode))
2956 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2957 + (outer_code != SET));
2958 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2963 *total = COSTS_N_INSNS (addsubcosts (x));
2967 *total = COSTS_N_INSNS (andcosts (x));
2971 *total = COSTS_N_INSNS (multcosts (x));
2977 *total = COSTS_N_INSNS (shiftcosts (x));
2984 *total = COSTS_N_INSNS (20);
2988 if (sh_1el_vec (x, VOIDmode))
2989 *total = outer_code != SET;
2990 if (sh_rep_vec (x, VOIDmode))
2991 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2992 + (outer_code != SET));
2993 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3006 /* Compute the cost of an address. For the SH, all valid addresses are
3007 the same cost. Use a slightly higher cost for reg + reg addressing,
3008 since it increases pressure on r0. */
3011 sh_address_cost (rtx X,
3012 bool speed ATTRIBUTE_UNUSED)
3014 return (GET_CODE (X) == PLUS
3015 && ! CONSTANT_P (XEXP (X, 1))
3016 && ! TARGET_SHMEDIA ? 1 : 0);
3019 /* Code to expand a shift. */
3022 gen_ashift (int type, int n, rtx reg)
3024 /* Negative values here come from the shift_amounts array. */
3037 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
3041 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
3043 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
3046 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
3051 /* Same for HImode */
3054 gen_ashift_hi (int type, int n, rtx reg)
3056 /* Negative values here come from the shift_amounts array. */
3070 /* We don't have HImode right shift operations because using the
3071 ordinary 32 bit shift instructions for that doesn't generate proper
3072 zero/sign extension.
3073 gen_ashift_hi is only called in contexts where we know that the
3074 sign extension works out correctly. */
3077 if (GET_CODE (reg) == SUBREG)
3079 offset = SUBREG_BYTE (reg);
3080 reg = SUBREG_REG (reg);
3082 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
3086 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3091 /* Output RTL to split a constant shift into its component SH constant
3092 shift instructions. */
3095 gen_shifty_op (int code, rtx *operands)
3097 int value = INTVAL (operands[2]);
3100 /* Truncate the shift count in case it is out of bounds. */
3105 if (code == LSHIFTRT)
3107 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3108 emit_insn (gen_movt (operands[0]));
3111 else if (code == ASHIFT)
3113 /* There is a two instruction sequence for 31 bit left shifts,
3114 but it requires r0. */
3115 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
3117 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3118 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3123 else if (value == 0)
3125 /* This can happen even when optimizing, if there were subregs before
3126 reload. Don't output a nop here, as this is never optimized away;
3127 use a no-op move instead. */
3128 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
3132 max = shift_insns[value];
3133 for (i = 0; i < max; i++)
3134 gen_ashift (code, shift_amounts[value][i], operands[0]);
3137 /* Same as above, but optimized for values where the topmost bits don't
3141 gen_shifty_hi_op (int code, rtx *operands)
3143 int value = INTVAL (operands[2]);
3145 void (*gen_fun) (int, int, rtx);
3147 /* This operation is used by and_shl for SImode values with a few
3148 high bits known to be cleared. */
3152 emit_insn (gen_nop ());
3156 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3159 max = ext_shift_insns[value];
3160 for (i = 0; i < max; i++)
3161 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3164 /* When shifting right, emit the shifts in reverse order, so that
3165 solitary negative values come first. */
3166 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
3167 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3170 /* Output RTL for an arithmetic right shift. */
3172 /* ??? Rewrite to use super-optimizer sequences. */
3175 expand_ashiftrt (rtx *operands)
3183 if (!CONST_INT_P (operands[2]))
3185 rtx count = copy_to_mode_reg (SImode, operands[2]);
3186 emit_insn (gen_negsi2 (count, count));
3187 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3190 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3191 > 1 + SH_DYNAMIC_SHIFT_COST)
3194 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
3195 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3199 if (!CONST_INT_P (operands[2]))
3202 value = INTVAL (operands[2]) & 31;
3206 /* If we are called from abs expansion, arrange things so that we
3207 we can use a single MT instruction that doesn't clobber the source,
3208 if LICM can hoist out the load of the constant zero. */
3209 if (currently_expanding_to_rtl)
3211 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3213 emit_insn (gen_mov_neg_si_t (operands[0]));
3216 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3219 else if (value >= 16 && value <= 19)
3221 wrk = gen_reg_rtx (SImode);
3222 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3225 gen_ashift (ASHIFTRT, 1, wrk);
3226 emit_move_insn (operands[0], wrk);
3229 /* Expand a short sequence inline, longer call a magic routine. */
3230 else if (value <= 5)
3232 wrk = gen_reg_rtx (SImode);
3233 emit_move_insn (wrk, operands[1]);
3235 gen_ashift (ASHIFTRT, 1, wrk);
3236 emit_move_insn (operands[0], wrk);
3240 wrk = gen_reg_rtx (Pmode);
3242 /* Load the value into an arg reg and call a helper. */
3243 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3244 sprintf (func, "__ashiftrt_r4_%d", value);
3245 function_symbol (wrk, func, SFUNC_STATIC);
3246 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
3247 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
3252 sh_dynamicalize_shift_p (rtx count)
3254 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
3257 /* Try to find a good way to implement the combiner pattern
3258 [(set (match_operand:SI 0 "register_operand" "r")
3259 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3260 (match_operand:SI 2 "const_int_operand" "n"))
3261 (match_operand:SI 3 "const_int_operand" "n"))) .
3262 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3263 return 0 for simple right / left or left/right shift combination.
3264 return 1 for a combination of shifts with zero_extend.
3265 return 2 for a combination of shifts with an AND that needs r0.
3266 return 3 for a combination of shifts with an AND that needs an extra
3267 scratch register, when the three highmost bits of the AND mask are clear.
3268 return 4 for a combination of shifts with an AND that needs an extra
3269 scratch register, when any of the three highmost bits of the AND mask
3271 If ATTRP is set, store an initial right shift width in ATTRP[0],
3272 and the instruction length in ATTRP[1] . These values are not valid
3274 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3275 shift_amounts for the last shift value that is to be used before the
3278 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
3280 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3281 int left = INTVAL (left_rtx), right;
3283 int cost, best_cost = 10000;
3284 int best_right = 0, best_len = 0;
3288 if (left < 0 || left > 31)
3290 if (CONST_INT_P (mask_rtx))
3291 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3293 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3294 /* Can this be expressed as a right shift / left shift pair? */
3295 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3296 right = exact_log2 (lsb);
3297 mask2 = ~(mask + lsb - 1);
3298 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3299 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3301 best_cost = shift_insns[right] + shift_insns[right + left];
3302 /* mask has no trailing zeroes <==> ! right */
3303 else if (! right && mask2 == ~(lsb2 - 1))
3305 int late_right = exact_log2 (lsb2);
3306 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3308 /* Try to use zero extend. */
3309 if (mask2 == ~(lsb2 - 1))
3313 for (width = 8; width <= 16; width += 8)
3315 /* Can we zero-extend right away? */
3316 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3319 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3320 if (cost < best_cost)
3331 /* ??? Could try to put zero extend into initial right shift,
3332 or even shift a bit left before the right shift. */
3333 /* Determine value of first part of left shift, to get to the
3334 zero extend cut-off point. */
3335 first = width - exact_log2 (lsb2) + right;
3336 if (first >= 0 && right + left - first >= 0)
3338 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3339 + ext_shift_insns[right + left - first];
3340 if (cost < best_cost)
3352 /* Try to use r0 AND pattern */
3353 for (i = 0; i <= 2; i++)
3357 if (! CONST_OK_FOR_K08 (mask >> i))
3359 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3360 if (cost < best_cost)
3365 best_len = cost - 1;
3368 /* Try to use a scratch register to hold the AND operand. */
3369 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3370 for (i = 0; i <= 2; i++)
3374 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3375 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
3376 if (cost < best_cost)
3381 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
3387 attrp[0] = best_right;
3388 attrp[1] = best_len;
3393 /* This is used in length attributes of the unnamed instructions
3394 corresponding to shl_and_kind return values of 1 and 2. */
3396 shl_and_length (rtx insn)
3398 rtx set_src, left_rtx, mask_rtx;
3401 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3402 left_rtx = XEXP (XEXP (set_src, 0), 1);
3403 mask_rtx = XEXP (set_src, 1);
3404 shl_and_kind (left_rtx, mask_rtx, attributes);
3405 return attributes[1];
3408 /* This is used in length attribute of the and_shl_scratch instruction. */
3411 shl_and_scr_length (rtx insn)
3413 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3414 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
3415 rtx op = XEXP (set_src, 0);
3416 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
3417 op = XEXP (XEXP (op, 0), 0);
3418 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
3421 /* Generate rtl for instructions for which shl_and_kind advised a particular
3422 method of generating them, i.e. returned zero. */
3425 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3428 unsigned HOST_WIDE_INT mask;
3429 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3430 int right, total_shift;
3431 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3433 right = attributes[0];
3434 total_shift = INTVAL (left_rtx) + right;
3435 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3442 int first = attributes[2];
3447 emit_insn ((mask << right) <= 0xff
3448 ? gen_zero_extendqisi2 (dest,
3449 gen_lowpart (QImode, source))
3450 : gen_zero_extendhisi2 (dest,
3451 gen_lowpart (HImode, source)));
3455 emit_insn (gen_movsi (dest, source));
3459 operands[2] = GEN_INT (right);
3460 gen_shifty_hi_op (LSHIFTRT, operands);
3464 operands[2] = GEN_INT (first);
3465 gen_shifty_hi_op (ASHIFT, operands);
3466 total_shift -= first;
3470 emit_insn (mask <= 0xff
3471 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3472 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3473 if (total_shift > 0)
3475 operands[2] = GEN_INT (total_shift);
3476 gen_shifty_hi_op (ASHIFT, operands);
3481 shift_gen_fun = gen_shifty_op;
3483 /* If the topmost bit that matters is set, set the topmost bits
3484 that don't matter. This way, we might be able to get a shorter
3486 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3487 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3489 /* Don't expand fine-grained when combining, because that will
3490 make the pattern fail. */
3491 if (currently_expanding_to_rtl
3492 || reload_in_progress || reload_completed)
3496 /* Cases 3 and 4 should be handled by this split
3497 only while combining */
3498 gcc_assert (kind <= 2);
3501 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3504 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3509 operands[2] = GEN_INT (total_shift);
3510 shift_gen_fun (ASHIFT, operands);
3517 if (kind != 4 && total_shift < 16)
3519 neg = -ext_shift_amounts[total_shift][1];
3521 neg -= ext_shift_amounts[total_shift][2];
3525 emit_insn (gen_and_shl_scratch (dest, source,
3528 GEN_INT (total_shift + neg),
3530 emit_insn (gen_movsi (dest, dest));
3537 /* Try to find a good way to implement the combiner pattern
3538 [(set (match_operand:SI 0 "register_operand" "=r")
3539 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3540 (match_operand:SI 2 "const_int_operand" "n")
3541 (match_operand:SI 3 "const_int_operand" "n")
3543 (clobber (reg:SI T_REG))]
3544 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3545 return 0 for simple left / right shift combination.
3546 return 1 for left shift / 8 bit sign extend / left shift.
3547 return 2 for left shift / 16 bit sign extend / left shift.
3548 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3549 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3550 return 5 for left shift / 16 bit sign extend / right shift
3551 return 6 for < 8 bit sign extend / left shift.
3552 return 7 for < 8 bit sign extend / left shift / single right shift.
3553 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3556 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3558 int left, size, insize, ext;
3559 int cost = 0, best_cost;
3562 left = INTVAL (left_rtx);
3563 size = INTVAL (size_rtx);
3564 insize = size - left;
3565 gcc_assert (insize > 0);
3566 /* Default to left / right shift. */
3568 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3571 /* 16 bit shift / sign extend / 16 bit shift */
3572 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3573 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3574 below, by alternative 3 or something even better. */
3575 if (cost < best_cost)
3581 /* Try a plain sign extend between two shifts. */
3582 for (ext = 16; ext >= insize; ext -= 8)
3586 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3587 if (cost < best_cost)
3589 kind = ext / (unsigned) 8;
3593 /* Check if we can do a sloppy shift with a final signed shift
3594 restoring the sign. */
3595 if (EXT_SHIFT_SIGNED (size - ext))
3596 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3597 /* If not, maybe it's still cheaper to do the second shift sloppy,
3598 and do a final sign extend? */
3599 else if (size <= 16)
3600 cost = ext_shift_insns[ext - insize] + 1
3601 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3604 if (cost < best_cost)
3606 kind = ext / (unsigned) 8 + 2;
3610 /* Check if we can sign extend in r0 */
3613 cost = 3 + shift_insns[left];
3614 if (cost < best_cost)
3619 /* Try the same with a final signed shift. */
3622 cost = 3 + ext_shift_insns[left + 1] + 1;
3623 if (cost < best_cost)
3632 /* Try to use a dynamic shift. */
3633 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3634 if (cost < best_cost)
3645 /* Function to be used in the length attribute of the instructions
3646 implementing this pattern. */
3649 shl_sext_length (rtx insn)
3651 rtx set_src, left_rtx, size_rtx;
3654 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3655 left_rtx = XEXP (XEXP (set_src, 0), 1);
3656 size_rtx = XEXP (set_src, 1);
3657 shl_sext_kind (left_rtx, size_rtx, &cost);
3661 /* Generate rtl for this pattern */
3664 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3667 int left, size, insize, cost;
3670 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3671 left = INTVAL (left_rtx);
3672 size = INTVAL (size_rtx);
3673 insize = size - left;
3681 int ext = kind & 1 ? 8 : 16;
3682 int shift2 = size - ext;
3684 /* Don't expand fine-grained when combining, because that will
3685 make the pattern fail. */
3686 if (! currently_expanding_to_rtl
3687 && ! reload_in_progress && ! reload_completed)
3689 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3690 emit_insn (gen_movsi (dest, source));
3694 emit_insn (gen_movsi (dest, source));
3698 operands[2] = GEN_INT (ext - insize);
3699 gen_shifty_hi_op (ASHIFT, operands);
3702 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3703 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3708 operands[2] = GEN_INT (shift2);
3709 gen_shifty_op (ASHIFT, operands);
3716 if (EXT_SHIFT_SIGNED (shift2))
3718 operands[2] = GEN_INT (shift2 + 1);
3719 gen_shifty_op (ASHIFT, operands);
3720 operands[2] = const1_rtx;
3721 gen_shifty_op (ASHIFTRT, operands);
3724 operands[2] = GEN_INT (shift2);
3725 gen_shifty_hi_op (ASHIFT, operands);
3729 operands[2] = GEN_INT (-shift2);
3730 gen_shifty_hi_op (LSHIFTRT, operands);
3732 emit_insn (size <= 8
3733 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3734 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3741 if (! currently_expanding_to_rtl
3742 && ! reload_in_progress && ! reload_completed)
3743 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3747 operands[2] = GEN_INT (16 - insize);
3748 gen_shifty_hi_op (ASHIFT, operands);
3749 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3751 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3753 gen_ashift (ASHIFTRT, 1, dest);
3758 /* Don't expand fine-grained when combining, because that will
3759 make the pattern fail. */
3760 if (! currently_expanding_to_rtl
3761 && ! reload_in_progress && ! reload_completed)
3763 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3764 emit_insn (gen_movsi (dest, source));
3767 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3768 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3769 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3771 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3772 gen_shifty_op (ASHIFT, operands);
3774 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3782 /* Prefix a symbol_ref name with "datalabel". */
3785 gen_datalabel_ref (rtx sym)
3789 if (GET_CODE (sym) == LABEL_REF)
3790 return gen_rtx_CONST (GET_MODE (sym),
3791 gen_rtx_UNSPEC (GET_MODE (sym),
3795 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3797 str = XSTR (sym, 0);
3798 /* Share all SYMBOL_REF strings with the same value - that is important
3800 str = IDENTIFIER_POINTER (get_identifier (str));
3801 XSTR (sym, 0) = str;
3807 static alloc_pool label_ref_list_pool;
3809 typedef struct label_ref_list_d
3812 struct label_ref_list_d *next;
3813 } *label_ref_list_t;
3815 /* The SH cannot load a large constant into a register, constants have to
3816 come from a pc relative load. The reference of a pc relative load
3817 instruction must be less than 1k in front of the instruction. This
3818 means that we often have to dump a constant inside a function, and
3819 generate code to branch around it.
3821 It is important to minimize this, since the branches will slow things
3822 down and make things bigger.
3824 Worst case code looks like:
3842 We fix this by performing a scan before scheduling, which notices which
3843 instructions need to have their operands fetched from the constant table
3844 and builds the table.
3848 scan, find an instruction which needs a pcrel move. Look forward, find the
3849 last barrier which is within MAX_COUNT bytes of the requirement.
3850 If there isn't one, make one. Process all the instructions between
3851 the find and the barrier.
3853 In the above example, we can tell that L3 is within 1k of L1, so
3854 the first move can be shrunk from the 3 insn+constant sequence into
3855 just 1 insn, and the constant moved to L3 to make:
3866 Then the second move becomes the target for the shortening process. */
3870 rtx value; /* Value in table. */
3871 rtx label; /* Label of value. */
3872 label_ref_list_t wend; /* End of window. */
3873 enum machine_mode mode; /* Mode of value. */
3875 /* True if this constant is accessed as part of a post-increment
3876 sequence. Note that HImode constants are never accessed in this way. */
3877 bool part_of_sequence_p;
3880 /* The maximum number of constants that can fit into one pool, since
3881 constants in the range 0..510 are at least 2 bytes long, and in the
3882 range from there to 1018 at least 4 bytes. */
3884 #define MAX_POOL_SIZE 372
3885 static pool_node pool_vector[MAX_POOL_SIZE];
3886 static int pool_size;
3887 static rtx pool_window_label;
3888 static int pool_window_last;
3890 static int max_labelno_before_reorg;
3892 /* ??? If we need a constant in HImode which is the truncated value of a
3893 constant we need in SImode, we could combine the two entries thus saving
3894 two bytes. Is this common enough to be worth the effort of implementing
3897 /* ??? This stuff should be done at the same time that we shorten branches.
3898 As it is now, we must assume that all branches are the maximum size, and
3899 this causes us to almost always output constant pools sooner than
3902 /* Add a constant to the pool and return its label. */
3905 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3909 label_ref_list_t ref, newref;
3911 /* First see if we've already got it. */
3912 for (i = 0; i < pool_size; i++)
3914 if (x->code == pool_vector[i].value->code
3915 && mode == pool_vector[i].mode)
3917 if (x->code == CODE_LABEL)
3919 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3922 if (rtx_equal_p (x, pool_vector[i].value))
3927 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3929 new_rtx = gen_label_rtx ();
3930 LABEL_REFS (new_rtx) = pool_vector[i].label;
3931 pool_vector[i].label = lab = new_rtx;
3933 if (lab && pool_window_label)
3935 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3936 newref->label = pool_window_label;
3937 ref = pool_vector[pool_window_last].wend;
3939 pool_vector[pool_window_last].wend = newref;
3942 pool_window_label = new_rtx;
3943 pool_window_last = i;
3949 /* Need a new one. */
3950 pool_vector[pool_size].value = x;
3951 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3954 pool_vector[pool_size - 1].part_of_sequence_p = true;
3957 lab = gen_label_rtx ();
3958 pool_vector[pool_size].mode = mode;
3959 pool_vector[pool_size].label = lab;
3960 pool_vector[pool_size].wend = NULL;
3961 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3962 if (lab && pool_window_label)
3964 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3965 newref->label = pool_window_label;
3966 ref = pool_vector[pool_window_last].wend;
3968 pool_vector[pool_window_last].wend = newref;
3971 pool_window_label = lab;
3972 pool_window_last = pool_size;
3977 /* Output the literal table. START, if nonzero, is the first instruction
3978 this table is needed for, and also indicates that there is at least one
3979 casesi_worker_2 instruction; We have to emit the operand3 labels from
3980 these insns at a 4-byte aligned position. BARRIER is the barrier
3981 after which we are to place the table. */
3984 dump_table (rtx start, rtx barrier)
3990 label_ref_list_t ref;
3993 /* Do two passes, first time dump out the HI sized constants. */
3995 for (i = 0; i < pool_size; i++)
3997 pool_node *p = &pool_vector[i];
3999 if (p->mode == HImode)
4003 scan = emit_insn_after (gen_align_2 (), scan);
4006 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4007 scan = emit_label_after (lab, scan);
4008 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4010 for (ref = p->wend; ref; ref = ref->next)
4013 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4016 else if (p->mode == DFmode)
4024 scan = emit_insn_after (gen_align_4 (), scan);
4026 for (; start != barrier; start = NEXT_INSN (start))
4027 if (NONJUMP_INSN_P (start)
4028 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4030 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4031 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4033 scan = emit_label_after (lab, scan);
4036 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
4038 rtx align_insn = NULL_RTX;
4040 scan = emit_label_after (gen_label_rtx (), scan);
4041 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4044 for (i = 0; i < pool_size; i++)
4046 pool_node *p = &pool_vector[i];
4054 if (align_insn && !p->part_of_sequence_p)
4056 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4057 emit_label_before (lab, align_insn);
4058 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4060 for (ref = p->wend; ref; ref = ref->next)
4063 emit_insn_before (gen_consttable_window_end (lab),
4066 delete_insn (align_insn);
4067 align_insn = NULL_RTX;
4072 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4073 scan = emit_label_after (lab, scan);
4074 scan = emit_insn_after (gen_consttable_4 (p->value,
4076 need_align = ! need_align;
4082 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4087 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4088 scan = emit_label_after (lab, scan);
4089 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4096 if (p->mode != HImode)
4098 for (ref = p->wend; ref; ref = ref->next)
4101 scan = emit_insn_after (gen_consttable_window_end (lab),
4110 for (i = 0; i < pool_size; i++)
4112 pool_node *p = &pool_vector[i];
4123 scan = emit_label_after (gen_label_rtx (), scan);
4124 scan = emit_insn_after (gen_align_4 (), scan);
4126 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4127 scan = emit_label_after (lab, scan);
4128 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4136 scan = emit_label_after (gen_label_rtx (), scan);
4137 scan = emit_insn_after (gen_align_4 (), scan);
4139 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4140 scan = emit_label_after (lab, scan);
4141 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4148 if (p->mode != HImode)
4150 for (ref = p->wend; ref; ref = ref->next)
4153 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4158 scan = emit_insn_after (gen_consttable_end (), scan);
4159 scan = emit_barrier_after (scan);
4161 pool_window_label = NULL_RTX;
4162 pool_window_last = 0;
4165 /* Return nonzero if constant would be an ok source for a
4166 mov.w instead of a mov.l. */
4171 return (CONST_INT_P (src)
4172 && INTVAL (src) >= -32768
4173 && INTVAL (src) <= 32767);
4176 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4178 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4180 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4181 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4182 need to fix it if the input value is CONST_OK_FOR_I08. */
4185 broken_move (rtx insn)
4187 if (NONJUMP_INSN_P (insn))
4189 rtx pat = PATTERN (insn);
4190 if (GET_CODE (pat) == PARALLEL)
4191 pat = XVECEXP (pat, 0, 0);
4192 if (GET_CODE (pat) == SET
4193 /* We can load any 8-bit value if we don't care what the high
4194 order bits end up as. */
4195 && GET_MODE (SET_DEST (pat)) != QImode
4196 && (CONSTANT_P (SET_SRC (pat))
4197 /* Match mova_const. */
4198 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4199 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4200 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
4202 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
4203 && (fp_zero_operand (SET_SRC (pat))
4204 || fp_one_operand (SET_SRC (pat)))
4205 /* In general we don't know the current setting of fpscr, so disable fldi.
4206 There is an exception if this was a register-register move
4207 before reload - and hence it was ascertained that we have
4208 single precision setting - and in a post-reload optimization
4209 we changed this to do a constant load. In that case
4210 we don't have an r0 clobber, hence we must use fldi. */
4212 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4214 && REG_P (SET_DEST (pat))
4215 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
4217 && GET_MODE (SET_DEST (pat)) == SImode
4218 && (satisfies_constraint_I20 (SET_SRC (pat))
4219 || satisfies_constraint_I28 (SET_SRC (pat))))
4220 && ! satisfies_constraint_I08 (SET_SRC (pat)))
4230 return (NONJUMP_INSN_P (insn)
4231 && GET_CODE (PATTERN (insn)) == SET
4232 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
4233 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4234 /* Don't match mova_const. */
4235 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
4238 /* Fix up a mova from a switch that went out of range. */
4240 fixup_mova (rtx mova)
4242 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
4245 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
4246 INSN_CODE (mova) = -1;
4251 rtx lab = gen_label_rtx ();
4252 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
4256 worker = NEXT_INSN (worker);
4258 && !LABEL_P (worker)
4259 && !JUMP_P (worker));
4260 } while (NOTE_P (worker)
4261 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
4262 wpat = PATTERN (worker);
4263 wpat0 = XVECEXP (wpat, 0, 0);
4264 wpat1 = XVECEXP (wpat, 0, 1);
4265 wsrc = SET_SRC (wpat0);
4266 PATTERN (worker) = (gen_casesi_worker_2
4267 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4268 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4270 INSN_CODE (worker) = -1;
4271 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4272 base = gen_rtx_LABEL_REF (Pmode, lab);
4273 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
4274 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4275 INSN_CODE (mova) = -1;
4279 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4280 *num_mova, and check if the new mova is not nested within the first one.
4281 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4282 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4284 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
4286 int n_addr = 0; /* Initialization to shut up spurious warning. */
4287 int f_target, n_target = 0; /* Likewise. */
4291 /* If NEW_MOVA has no address yet, it will be handled later. */
4292 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4295 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4296 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4297 if (n_addr > n_target || n_addr + 1022 < n_target)
4299 /* Change the mova into a load.
4300 broken_move will then return true for it. */
4301 fixup_mova (new_mova);
4307 *first_mova = new_mova;
4312 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4317 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4318 > n_target - n_addr)
4320 fixup_mova (*first_mova);
4325 fixup_mova (new_mova);
4330 /* Find the last barrier from insn FROM which is close enough to hold the
4331 constant pool. If we can't find one, then create one near the end of
4335 find_barrier (int num_mova, rtx mova, rtx from)
4344 int leading_mova = num_mova;
4345 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
4350 /* For HImode: range is 510, add 4 because pc counts from address of
4351 second instruction after this one, subtract 2 for the jump instruction
4352 that we may need to emit before the table, subtract 2 for the instruction
4353 that fills the jump delay slot (in very rare cases, reorg will take an
4354 instruction from after the constant pool or will leave the delay slot
4355 empty). This gives 510.
4356 For SImode: range is 1020, add 4 because pc counts from address of
4357 second instruction after this one, subtract 2 in case pc is 2 byte
4358 aligned, subtract 2 for the jump instruction that we may need to emit
4359 before the table, subtract 2 for the instruction that fills the jump
4360 delay slot. This gives 1018. */
4362 /* The branch will always be shortened now that the reference address for
4363 forward branches is the successor address, thus we need no longer make
4364 adjustments to the [sh]i_limit for -O0. */
4369 while (from && count_si < si_limit && count_hi < hi_limit)
4371 int inc = get_attr_length (from);
4374 /* If this is a label that existed at the time of the compute_alignments
4375 call, determine the alignment. N.B. When find_barrier recurses for
4376 an out-of-reach mova, we might see labels at the start of previously
4377 inserted constant tables. */
4379 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4382 new_align = 1 << label_to_alignment (from);
4383 else if (BARRIER_P (prev_nonnote_insn (from)))
4384 new_align = 1 << barrier_align (from);
4389 /* In case we are scanning a constant table because of recursion, check
4390 for explicit alignments. If the table is long, we might be forced
4391 to emit the new table in front of it; the length of the alignment
4392 might be the last straw. */
4393 else if (NONJUMP_INSN_P (from)
4394 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4395 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4396 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4397 /* When we find the end of a constant table, paste the new constant
4398 at the end. That is better than putting it in front because
4399 this way, we don't need extra alignment for adding a 4-byte-aligned
4400 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4401 else if (NONJUMP_INSN_P (from)
4402 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4403 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4406 if (BARRIER_P (from))
4410 found_barrier = from;
4412 /* If we are at the end of the function, or in front of an alignment
4413 instruction, we need not insert an extra alignment. We prefer
4414 this kind of barrier. */
4415 if (barrier_align (from) > 2)
4416 good_barrier = from;
4418 /* If we are at the end of a hot/cold block, dump the constants
4420 next = NEXT_INSN (from);
4423 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4427 if (broken_move (from))
4430 enum machine_mode mode;
4432 pat = PATTERN (from);
4433 if (GET_CODE (pat) == PARALLEL)
4434 pat = XVECEXP (pat, 0, 0);
4435 src = SET_SRC (pat);
4436 dst = SET_DEST (pat);
4437 mode = GET_MODE (dst);
4439 /* We must explicitly check the mode, because sometimes the
4440 front end will generate code to load unsigned constants into
4441 HImode targets without properly sign extending them. */
4443 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4446 /* We put the short constants before the long constants, so
4447 we must count the length of short constants in the range
4448 for the long constants. */
4449 /* ??? This isn't optimal, but is easy to do. */
4454 /* We dump DF/DI constants before SF/SI ones, because
4455 the limit is the same, but the alignment requirements
4456 are higher. We may waste up to 4 additional bytes
4457 for alignment, and the DF/DI constant may have
4458 another SF/SI constant placed before it. */
4459 if (TARGET_SHCOMPACT
4461 && (mode == DFmode || mode == DImode))
4466 while (si_align > 2 && found_si + si_align - 2 > count_si)
4468 if (found_si > count_si)
4469 count_si = found_si;
4470 found_si += GET_MODE_SIZE (mode);
4472 si_limit -= GET_MODE_SIZE (mode);
4478 switch (untangle_mova (&num_mova, &mova, from))
4480 case 0: return find_barrier (0, 0, mova);
4485 = good_barrier ? good_barrier : found_barrier;
4489 if (found_si > count_si)
4490 count_si = found_si;
4492 else if (JUMP_TABLE_DATA_P (from))
4494 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4496 && (prev_nonnote_insn (from)
4497 == XEXP (MOVA_LABELREF (mova), 0))))
4499 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4501 /* We have just passed the barrier in front of the
4502 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4503 the ADDR_DIFF_VEC is accessed as data, just like our pool
4504 constants, this is a good opportunity to accommodate what
4505 we have gathered so far.
4506 If we waited any longer, we could end up at a barrier in
4507 front of code, which gives worse cache usage for separated
4508 instruction / data caches. */
4509 good_barrier = found_barrier;
4514 rtx body = PATTERN (from);
4515 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4518 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4519 else if (JUMP_P (from)
4521 && ! TARGET_SMALLCODE)
4527 if (new_align > si_align)
4529 si_limit -= (count_si - 1) & (new_align - si_align);
4530 si_align = new_align;
4532 count_si = (count_si + new_align - 1) & -new_align;
4537 if (new_align > hi_align)
4539 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4540 hi_align = new_align;
4542 count_hi = (count_hi + new_align - 1) & -new_align;
4544 from = NEXT_INSN (from);
4551 /* Try as we might, the leading mova is out of range. Change
4552 it into a load (which will become a pcload) and retry. */
4554 return find_barrier (0, 0, mova);
4558 /* Insert the constant pool table before the mova instruction,
4559 to prevent the mova label reference from going out of range. */
4561 good_barrier = found_barrier = barrier_before_mova;
4567 if (good_barrier && next_real_insn (found_barrier))
4568 found_barrier = good_barrier;
4572 /* We didn't find a barrier in time to dump our stuff,
4573 so we'll make one. */
4574 rtx label = gen_label_rtx ();
4576 /* If we exceeded the range, then we must back up over the last
4577 instruction we looked at. Otherwise, we just need to undo the
4578 NEXT_INSN at the end of the loop. */
4579 if (PREV_INSN (from) != orig
4580 && (count_hi > hi_limit || count_si > si_limit))
4581 from = PREV_INSN (PREV_INSN (from));
4583 from = PREV_INSN (from);
4585 /* Walk back to be just before any jump or label.
4586 Putting it before a label reduces the number of times the branch
4587 around the constant pool table will be hit. Putting it before
4588 a jump makes it more likely that the bra delay slot will be
4590 while (NOTE_P (from) || JUMP_P (from)
4592 from = PREV_INSN (from);
4594 from = emit_jump_insn_after (gen_jump (label), from);
4595 JUMP_LABEL (from) = label;
4596 LABEL_NUSES (label) = 1;
4597 found_barrier = emit_barrier_after (from);
4598 emit_label_after (label, found_barrier);
4601 return found_barrier;
4604 /* If the instruction INSN is implemented by a special function, and we can
4605 positively find the register that is used to call the sfunc, and this
4606 register is not used anywhere else in this instruction - except as the
4607 destination of a set, return this register; else, return 0. */
4609 sfunc_uses_reg (rtx insn)
4612 rtx pattern, part, reg_part, reg;
4614 if (!NONJUMP_INSN_P (insn))
4616 pattern = PATTERN (insn);
4617 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4620 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4622 part = XVECEXP (pattern, 0, i);
4623 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4628 reg = XEXP (reg_part, 0);
4629 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4631 part = XVECEXP (pattern, 0, i);
4632 if (part == reg_part || GET_CODE (part) == CLOBBER)
4634 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4635 && REG_P (SET_DEST (part)))
4636 ? SET_SRC (part) : part)))
4642 /* See if the only way in which INSN uses REG is by calling it, or by
4643 setting it while calling it. Set *SET to a SET rtx if the register
4647 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4653 reg2 = sfunc_uses_reg (insn);
4654 if (reg2 && REGNO (reg2) == REGNO (reg))
4656 pattern = single_set (insn);
4658 && REG_P (SET_DEST (pattern))
4659 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4665 /* We don't use rtx_equal_p because we don't care if the mode is
4667 pattern = single_set (insn);
4669 && REG_P (SET_DEST (pattern))
4670 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4676 par = PATTERN (insn);
4677 if (GET_CODE (par) == PARALLEL)
4678 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4680 part = XVECEXP (par, 0, i);
4681 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4684 return reg_mentioned_p (reg, SET_SRC (pattern));
4690 pattern = PATTERN (insn);
4692 if (GET_CODE (pattern) == PARALLEL)
4696 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4697 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4699 pattern = XVECEXP (pattern, 0, 0);
4702 if (GET_CODE (pattern) == SET)
4704 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4706 /* We don't use rtx_equal_p, because we don't care if the
4707 mode is different. */
4708 if (!REG_P (SET_DEST (pattern))
4709 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4715 pattern = SET_SRC (pattern);
4718 if (GET_CODE (pattern) != CALL
4719 || !MEM_P (XEXP (pattern, 0))
4720 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4726 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4727 general registers. Bits 0..15 mean that the respective registers
4728 are used as inputs in the instruction. Bits 16..31 mean that the
4729 registers 0..15, respectively, are used as outputs, or are clobbered.
4730 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4732 regs_used (rtx x, int is_dest)
4740 code = GET_CODE (x);
4745 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4746 << (REGNO (x) + is_dest));
4750 rtx y = SUBREG_REG (x);
4755 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4757 subreg_regno_offset (REGNO (y),
4760 GET_MODE (x)) + is_dest));
4764 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4766 /* If there was a return value, it must have been indicated with USE. */
4781 fmt = GET_RTX_FORMAT (code);
4783 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4788 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4789 used |= regs_used (XVECEXP (x, i, j), is_dest);
4791 else if (fmt[i] == 'e')
4792 used |= regs_used (XEXP (x, i), is_dest);
4797 /* Create an instruction that prevents redirection of a conditional branch
4798 to the destination of the JUMP with address ADDR.
4799 If the branch needs to be implemented as an indirect jump, try to find
4800 a scratch register for it.
4801 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4802 If any preceding insn that doesn't fit into a delay slot is good enough,
4803 pass 1. Pass 2 if a definite blocking insn is needed.
4804 -1 is used internally to avoid deep recursion.
4805 If a blocking instruction is made or recognized, return it. */
4808 gen_block_redirect (rtx jump, int addr, int need_block)
4811 rtx prev = prev_nonnote_insn (jump);
4814 /* First, check if we already have an instruction that satisfies our need. */
4815 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
4817 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4819 if (GET_CODE (PATTERN (prev)) == USE
4820 || GET_CODE (PATTERN (prev)) == CLOBBER
4821 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4823 else if ((need_block &= ~1) < 0)
4825 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4828 if (GET_CODE (PATTERN (jump)) == RETURN)
4832 /* Reorg even does nasty things with return insns that cause branches
4833 to go out of range - see find_end_label and callers. */
4834 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4836 /* We can't use JUMP_LABEL here because it might be undefined
4837 when not optimizing. */
4838 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4839 /* If the branch is out of range, try to find a scratch register for it. */
4841 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4845 /* Don't look for the stack pointer as a scratch register,
4846 it would cause trouble if an interrupt occurred. */
4847 unsigned attempt = 0x7fff, used;
4848 int jump_left = flag_expensive_optimizations + 1;
4850 /* It is likely that the most recent eligible instruction is wanted for
4851 the delay slot. Therefore, find out which registers it uses, and
4852 try to avoid using them. */
4854 for (scan = jump; (scan = PREV_INSN (scan)); )
4858 if (INSN_DELETED_P (scan))
4860 code = GET_CODE (scan);
4861 if (code == CODE_LABEL || code == JUMP_INSN)
4864 && GET_CODE (PATTERN (scan)) != USE
4865 && GET_CODE (PATTERN (scan)) != CLOBBER
4866 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4868 attempt &= ~regs_used (PATTERN (scan), 0);
4872 for (used = dead = 0, scan = JUMP_LABEL (jump);
4873 (scan = NEXT_INSN (scan)); )
4877 if (INSN_DELETED_P (scan))
4879 code = GET_CODE (scan);
4882 used |= regs_used (PATTERN (scan), 0);
4883 if (code == CALL_INSN)
4884 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4885 dead |= (used >> 16) & ~used;
4891 if (code == JUMP_INSN)
4893 if (jump_left-- && simplejump_p (scan))
4894 scan = JUMP_LABEL (scan);
4900 /* Mask out the stack pointer again, in case it was
4901 the only 'free' register we have found. */
4904 /* If the immediate destination is still in range, check for possible
4905 threading with a jump beyond the delay slot insn.
4906 Don't check if we are called recursively; the jump has been or will be
4907 checked in a different invocation then. */
4909 else if (optimize && need_block >= 0)
4911 rtx next = next_active_insn (next_active_insn (dest));
4912 if (next && JUMP_P (next)
4913 && GET_CODE (PATTERN (next)) == SET
4914 && recog_memoized (next) == CODE_FOR_jump_compact)
4916 dest = JUMP_LABEL (next);
4918 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4920 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4926 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4928 /* It would be nice if we could convert the jump into an indirect
4929 jump / far branch right now, and thus exposing all constituent
4930 instructions to further optimization. However, reorg uses
4931 simplejump_p to determine if there is an unconditional jump where
4932 it should try to schedule instructions from the target of the
4933 branch; simplejump_p fails for indirect jumps even if they have
4935 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4936 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4938 /* ??? We would like this to have the scope of the jump, but that
4939 scope will change when a delay slot insn of an inner scope is added.
4940 Hence, after delay slot scheduling, we'll have to expect
4941 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4944 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4945 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4948 else if (need_block)
4949 /* We can't use JUMP_LABEL here because it might be undefined
4950 when not optimizing. */
4951 return emit_insn_before (gen_block_branch_redirect
4952 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4957 #define CONDJUMP_MIN -252
4958 #define CONDJUMP_MAX 262
4961 /* A label (to be placed) in front of the jump
4962 that jumps to our ultimate destination. */
4964 /* Where we are going to insert it if we cannot move the jump any farther,
4965 or the jump itself if we have picked up an existing jump. */
4967 /* The ultimate destination. */
4969 struct far_branch *prev;
4970 /* If the branch has already been created, its address;
4971 else the address of its first prospective user. */
4975 static void gen_far_branch (struct far_branch *);
4976 enum mdep_reorg_phase_e mdep_reorg_phase;
4978 gen_far_branch (struct far_branch *bp)
4980 rtx insn = bp->insert_place;
4982 rtx label = gen_label_rtx ();
4985 emit_label_after (label, insn);
4988 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
4989 LABEL_NUSES (bp->far_label)++;
4992 jump = emit_jump_insn_after (gen_return (), insn);
4993 /* Emit a barrier so that reorg knows that any following instructions
4994 are not reachable via a fall-through path.
4995 But don't do this when not optimizing, since we wouldn't suppress the
4996 alignment for the barrier then, and could end up with out-of-range
4997 pc-relative loads. */
4999 emit_barrier_after (jump);
5000 emit_label_after (bp->near_label, insn);
5001 JUMP_LABEL (jump) = bp->far_label;
5002 ok = invert_jump (insn, label, 1);
5005 /* If we are branching around a jump (rather than a return), prevent
5006 reorg from using an insn from the jump target as the delay slot insn -
5007 when reorg did this, it pessimized code (we rather hide the delay slot)
5008 and it could cause branches to go out of range. */
5011 (gen_stuff_delay_slot
5012 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
5013 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5015 /* Prevent reorg from undoing our splits. */
5016 gen_block_redirect (jump, bp->address += 2, 2);
5019 /* Fix up ADDR_DIFF_VECs. */
5021 fixup_addr_diff_vecs (rtx first)
5025 for (insn = first; insn; insn = NEXT_INSN (insn))
5027 rtx vec_lab, pat, prev, prevpat, x, braf_label;
5030 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5032 pat = PATTERN (insn);
5033 vec_lab = XEXP (XEXP (pat, 0), 0);
5035 /* Search the matching casesi_jump_2. */
5036 for (prev = vec_lab; ; prev = PREV_INSN (prev))
5040 prevpat = PATTERN (prev);
5041 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5043 x = XVECEXP (prevpat, 0, 1);
5044 if (GET_CODE (x) != USE)
5047 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5050 /* FIXME: This is a bug in the optimizer, but it seems harmless
5051 to just avoid panicing. */
5055 /* Emit the reference label of the braf where it belongs, right after
5056 the casesi_jump_2 (i.e. braf). */
5057 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5058 emit_label_after (braf_label, prev);
5060 /* Fix up the ADDR_DIF_VEC to be relative
5061 to the reference address of the braf. */
5062 XEXP (XEXP (pat, 0), 0) = braf_label;
5066 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5067 a barrier. Return the base 2 logarithm of the desired alignment. */
5069 barrier_align (rtx barrier_or_label)
5071 rtx next = next_real_insn (barrier_or_label), pat, prev;
5072 int slot, credit, jump_to_next = 0;
5077 pat = PATTERN (next);
5079 if (GET_CODE (pat) == ADDR_DIFF_VEC)
5082 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
5083 /* This is a barrier in front of a constant table. */
5086 prev = prev_real_insn (barrier_or_label);
5087 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
5089 pat = PATTERN (prev);
5090 /* If this is a very small table, we want to keep the alignment after
5091 the table to the minimum for proper code alignment. */
5092 return ((TARGET_SMALLCODE
5093 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
5094 <= (unsigned) 1 << (CACHE_LOG - 2)))
5095 ? 1 << TARGET_SHMEDIA : align_jumps_log);
5098 if (TARGET_SMALLCODE)
5101 if (! TARGET_SH2 || ! optimize)
5102 return align_jumps_log;
5104 /* When fixing up pcloads, a constant table might be inserted just before
5105 the basic block that ends with the barrier. Thus, we can't trust the
5106 instruction lengths before that. */
5107 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
5109 /* Check if there is an immediately preceding branch to the insn beyond
5110 the barrier. We must weight the cost of discarding useful information
5111 from the current cache line when executing this branch and there is
5112 an alignment, against that of fetching unneeded insn in front of the
5113 branch target when there is no alignment. */
5115 /* There are two delay_slot cases to consider. One is the simple case
5116 where the preceding branch is to the insn beyond the barrier (simple
5117 delay slot filling), and the other is where the preceding branch has
5118 a delay slot that is a duplicate of the insn after the barrier
5119 (fill_eager_delay_slots) and the branch is to the insn after the insn
5120 after the barrier. */
5122 /* PREV is presumed to be the JUMP_INSN for the barrier under
5123 investigation. Skip to the insn before it. */
5124 prev = prev_real_insn (prev);
5126 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
5127 credit >= 0 && prev && NONJUMP_INSN_P (prev);
5128 prev = prev_real_insn (prev))
5131 if (GET_CODE (PATTERN (prev)) == USE
5132 || GET_CODE (PATTERN (prev)) == CLOBBER)
5134 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
5136 prev = XVECEXP (PATTERN (prev), 0, 1);
5137 if (INSN_UID (prev) == INSN_UID (next))
5139 /* Delay slot was filled with insn at jump target. */
5146 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5148 credit -= get_attr_length (prev);
5152 && JUMP_LABEL (prev))
5156 || next_real_insn (JUMP_LABEL (prev)) == next
5157 /* If relax_delay_slots() decides NEXT was redundant
5158 with some previous instruction, it will have
5159 redirected PREV's jump to the following insn. */
5160 || JUMP_LABEL (prev) == next_nonnote_insn (next)
5161 /* There is no upper bound on redundant instructions
5162 that might have been skipped, but we must not put an
5163 alignment where none had been before. */
5164 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5166 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
5167 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5168 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
5170 rtx pat = PATTERN (prev);
5171 if (GET_CODE (pat) == PARALLEL)
5172 pat = XVECEXP (pat, 0, 0);
5173 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5179 return align_jumps_log;
5182 /* If we are inside a phony loop, almost any kind of label can turn up as the
5183 first one in the loop. Aligning a braf label causes incorrect switch
5184 destination addresses; we can detect braf labels because they are
5185 followed by a BARRIER.
5186 Applying loop alignment to small constant or switch tables is a waste
5187 of space, so we suppress this too. */
5189 sh_loop_align (rtx label)
5194 next = next_nonnote_insn (next);
5195 while (next && LABEL_P (next));
5199 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
5200 || recog_memoized (next) == CODE_FOR_consttable_2)
5203 return align_loops_log;
5206 /* Do a final pass over the function, just before delayed branch
5212 rtx first, insn, mova = NULL_RTX;
5214 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5215 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
5217 first = get_insns ();
5218 max_labelno_before_reorg = max_label_num ();
5220 /* We must split call insns before introducing `mova's. If we're
5221 optimizing, they'll have already been split. Otherwise, make
5222 sure we don't split them too late. */
5224 split_all_insns_noflow ();
5229 /* If relaxing, generate pseudo-ops to associate function calls with
5230 the symbols they call. It does no harm to not generate these
5231 pseudo-ops. However, when we can generate them, it enables to
5232 linker to potentially relax the jsr to a bsr, and eliminate the
5233 register load and, possibly, the constant pool entry. */
5235 mdep_reorg_phase = SH_INSERT_USES_LABELS;
5238 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5239 own purposes. This works because none of the remaining passes
5240 need to look at them.
5242 ??? But it may break in the future. We should use a machine
5243 dependent REG_NOTE, or some other approach entirely. */
5244 for (insn = first; insn; insn = NEXT_INSN (insn))
5250 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5252 remove_note (insn, note);
5256 for (insn = first; insn; insn = NEXT_INSN (insn))
5258 rtx pattern, reg, link, set, scan, dies, label;
5259 int rescan = 0, foundinsn = 0;
5263 pattern = PATTERN (insn);
5265 if (GET_CODE (pattern) == PARALLEL)
5266 pattern = XVECEXP (pattern, 0, 0);
5267 if (GET_CODE (pattern) == SET)
5268 pattern = SET_SRC (pattern);
5270 if (GET_CODE (pattern) != CALL
5271 || !MEM_P (XEXP (pattern, 0)))
5274 reg = XEXP (XEXP (pattern, 0), 0);
5278 reg = sfunc_uses_reg (insn);
5286 /* Try scanning backward to find where the register is set. */
5288 for (scan = PREV_INSN (insn);
5289 scan && !LABEL_P (scan);
5290 scan = PREV_INSN (scan))
5292 if (! INSN_P (scan))
5295 if (! reg_mentioned_p (reg, scan))
5298 if (noncall_uses_reg (reg, scan, &set))
5311 /* The register is set at LINK. */
5313 /* We can only optimize the function call if the register is
5314 being set to a symbol. In theory, we could sometimes
5315 optimize calls to a constant location, but the assembler
5316 and linker do not support that at present. */
5317 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5318 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5321 /* Scan forward from LINK to the place where REG dies, and
5322 make sure that the only insns which use REG are
5323 themselves function calls. */
5325 /* ??? This doesn't work for call targets that were allocated
5326 by reload, since there may not be a REG_DEAD note for the
5330 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5334 /* Don't try to trace forward past a CODE_LABEL if we haven't
5335 seen INSN yet. Ordinarily, we will only find the setting insn
5336 if it is in the same basic block. However,
5337 cross-jumping can insert code labels in between the load and
5338 the call, and can result in situations where a single call
5339 insn may have two targets depending on where we came from. */
5341 if (LABEL_P (scan) && ! foundinsn)
5344 if (! INSN_P (scan))
5347 /* Don't try to trace forward past a JUMP. To optimize
5348 safely, we would have to check that all the
5349 instructions at the jump destination did not use REG. */
5354 if (! reg_mentioned_p (reg, scan))
5357 if (noncall_uses_reg (reg, scan, &scanset))
5364 && (CALL_P (scan) || sfunc_uses_reg (scan)))
5366 /* There is a function call to this register other
5367 than the one we are checking. If we optimize
5368 this call, we need to rescan again below. */
5372 /* ??? We shouldn't have to worry about SCANSET here.
5373 We should just be able to check for a REG_DEAD note
5374 on a function call. However, the REG_DEAD notes are
5375 apparently not dependable around libcalls; c-torture
5376 execute/920501-2 is a test case. If SCANSET is set,
5377 then this insn sets the register, so it must have
5378 died earlier. Unfortunately, this will only handle
5379 the cases in which the register is, in fact, set in a
5382 /* ??? We shouldn't have to use FOUNDINSN here.
5383 This dates back to when we used LOG_LINKS to find
5384 the most recent insn which sets the register. */
5388 || find_reg_note (scan, REG_DEAD, reg)))
5397 /* Either there was a branch, or some insn used REG
5398 other than as a function call address. */
5402 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5403 on the insn which sets the register, and on each call insn
5404 which uses the register. In final_prescan_insn we look for
5405 the REG_LABEL_OPERAND notes, and output the appropriate label
5408 label = gen_label_rtx ();
5409 add_reg_note (link, REG_LABEL_OPERAND, label);
5410 add_reg_note (insn, REG_LABEL_OPERAND, label);
5418 scan = NEXT_INSN (scan);
5421 && reg_mentioned_p (reg, scan))
5422 || ((reg2 = sfunc_uses_reg (scan))
5423 && REGNO (reg2) == REGNO (reg))))
5424 add_reg_note (scan, REG_LABEL_OPERAND, label);
5426 while (scan != dies);
5432 fixup_addr_diff_vecs (first);
5436 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5437 shorten_branches (first);
5440 /* Scan the function looking for move instructions which have to be
5441 changed to pc-relative loads and insert the literal tables. */
5442 label_ref_list_pool = create_alloc_pool ("label references list",
5443 sizeof (struct label_ref_list_d),
5445 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5446 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5450 /* ??? basic block reordering can move a switch table dispatch
5451 below the switch table. Check if that has happened.
5452 We only have the addresses available when optimizing; but then,
5453 this check shouldn't be needed when not optimizing. */
5454 if (!untangle_mova (&num_mova, &mova, insn))
5460 else if (JUMP_P (insn)
5461 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5463 /* ??? loop invariant motion can also move a mova out of a
5464 loop. Since loop does this code motion anyway, maybe we
5465 should wrap UNSPEC_MOVA into a CONST, so that reload can
5468 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5469 || (prev_nonnote_insn (insn)
5470 == XEXP (MOVA_LABELREF (mova), 0))))
5477 /* Some code might have been inserted between the mova and
5478 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5479 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5480 total += get_attr_length (scan);
5482 /* range of mova is 1020, add 4 because pc counts from address of
5483 second instruction after this one, subtract 2 in case pc is 2
5484 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5485 cancels out with alignment effects of the mova itself. */
5488 /* Change the mova into a load, and restart scanning
5489 there. broken_move will then return true for mova. */
5494 if (broken_move (insn)
5495 || (NONJUMP_INSN_P (insn)
5496 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5499 /* Scan ahead looking for a barrier to stick the constant table
5501 rtx barrier = find_barrier (num_mova, mova, insn);
5502 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5503 int need_aligned_label = 0;
5505 if (num_mova && ! mova_p (mova))
5507 /* find_barrier had to change the first mova into a
5508 pcload; thus, we have to start with this new pcload. */
5512 /* Now find all the moves between the points and modify them. */
5513 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5517 if (NONJUMP_INSN_P (scan)
5518 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5519 need_aligned_label = 1;
5520 if (broken_move (scan))
5522 rtx *patp = &PATTERN (scan), pat = *patp;
5526 enum machine_mode mode;
5528 if (GET_CODE (pat) == PARALLEL)
5529 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5530 src = SET_SRC (pat);
5531 dst = SET_DEST (pat);
5532 mode = GET_MODE (dst);
5534 if (mode == SImode && hi_const (src)
5535 && REGNO (dst) != FPUL_REG)
5540 while (GET_CODE (dst) == SUBREG)
5542 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5543 GET_MODE (SUBREG_REG (dst)),
5546 dst = SUBREG_REG (dst);
5548 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5550 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
5552 /* This must be an insn that clobbers r0. */
5553 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5554 XVECLEN (PATTERN (scan), 0)
5556 rtx clobber = *clobberp;
5558 gcc_assert (GET_CODE (clobber) == CLOBBER
5559 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5562 && reg_set_between_p (r0_rtx, last_float_move, scan))
5566 && GET_MODE_SIZE (mode) != 4
5567 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5569 lab = add_constant (src, mode, last_float);
5571 emit_insn_before (gen_mova (lab), scan);
5574 /* There will be a REG_UNUSED note for r0 on
5575 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5576 lest reorg:mark_target_live_regs will not
5577 consider r0 to be used, and we end up with delay
5578 slot insn in front of SCAN that clobbers r0. */
5580 = find_regno_note (last_float_move, REG_UNUSED, 0);
5582 /* If we are not optimizing, then there may not be
5585 PUT_REG_NOTE_KIND (note, REG_INC);
5587 *last_float_addr = r0_inc_rtx;
5589 last_float_move = scan;
5591 newsrc = gen_const_mem (mode,
5592 (((TARGET_SH4 && ! TARGET_FMOVD)
5593 || REGNO (dst) == FPUL_REG)
5596 last_float_addr = &XEXP (newsrc, 0);
5598 /* Remove the clobber of r0. */
5599 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5600 gen_rtx_SCRATCH (Pmode));
5602 /* This is a mova needing a label. Create it. */
5603 else if (GET_CODE (src) == UNSPEC
5604 && XINT (src, 1) == UNSPEC_MOVA
5605 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5607 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5608 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5609 newsrc = gen_rtx_UNSPEC (SImode,
5610 gen_rtvec (1, newsrc),
5615 lab = add_constant (src, mode, 0);
5616 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5617 newsrc = gen_const_mem (mode, newsrc);
5619 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5620 INSN_CODE (scan) = -1;
5623 dump_table (need_aligned_label ? insn : 0, barrier);
5627 free_alloc_pool (label_ref_list_pool);
5628 for (insn = first; insn; insn = NEXT_INSN (insn))
5629 PUT_MODE (insn, VOIDmode);
5631 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5632 INSN_ADDRESSES_FREE ();
5633 split_branches (first);
5635 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5636 also has an effect on the register that holds the address of the sfunc.
5637 Insert an extra dummy insn in front of each sfunc that pretends to
5638 use this register. */
5639 if (flag_delayed_branch)
5641 for (insn = first; insn; insn = NEXT_INSN (insn))
5643 rtx reg = sfunc_uses_reg (insn);
5647 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5651 /* fpscr is not actually a user variable, but we pretend it is for the
5652 sake of the previous optimization passes, since we want it handled like
5653 one. However, we don't have any debugging information for it, so turn
5654 it into a non-user variable now. */
5656 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5658 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5662 get_dest_uid (rtx label, int max_uid)
5664 rtx dest = next_real_insn (label);
5667 /* This can happen for an undefined label. */
5669 dest_uid = INSN_UID (dest);
5670 /* If this is a newly created branch redirection blocking instruction,
5671 we cannot index the branch_uid or insn_addresses arrays with its
5672 uid. But then, we won't need to, because the actual destination is
5673 the following branch. */
5674 while (dest_uid >= max_uid)
5676 dest = NEXT_INSN (dest);
5677 dest_uid = INSN_UID (dest);
5679 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
5684 /* Split condbranches that are out of range. Also add clobbers for
5685 scratch registers that are needed in far jumps.
5686 We do this before delay slot scheduling, so that it can take our
5687 newly created instructions into account. It also allows us to
5688 find branches with common targets more easily. */
5691 split_branches (rtx first)
5694 struct far_branch **uid_branch, *far_branch_list = 0;
5695 int max_uid = get_max_uid ();
5698 /* Find out which branches are out of range. */
5699 shorten_branches (first);
5701 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5702 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5704 for (insn = first; insn; insn = NEXT_INSN (insn))
5705 if (! INSN_P (insn))
5707 else if (INSN_DELETED_P (insn))
5709 /* Shorten_branches would split this instruction again,
5710 so transform it into a note. */
5711 SET_INSN_DELETED (insn);
5713 else if (JUMP_P (insn)
5714 /* Don't mess with ADDR_DIFF_VEC */
5715 && (GET_CODE (PATTERN (insn)) == SET
5716 || GET_CODE (PATTERN (insn)) == RETURN))
5718 enum attr_type type = get_attr_type (insn);
5719 if (type == TYPE_CBRANCH)
5723 if (get_attr_length (insn) > 4)
5725 rtx src = SET_SRC (PATTERN (insn));
5726 rtx olabel = XEXP (XEXP (src, 1), 0);
5727 int addr = INSN_ADDRESSES (INSN_UID (insn));
5729 int dest_uid = get_dest_uid (olabel, max_uid);
5730 struct far_branch *bp = uid_branch[dest_uid];
5732 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5733 the label if the LABEL_NUSES count drops to zero. There is
5734 always a jump_optimize pass that sets these values, but it
5735 proceeds to delete unreferenced code, and then if not
5736 optimizing, to un-delete the deleted instructions, thus
5737 leaving labels with too low uses counts. */
5740 JUMP_LABEL (insn) = olabel;
5741 LABEL_NUSES (olabel)++;
5745 bp = (struct far_branch *) alloca (sizeof *bp);
5746 uid_branch[dest_uid] = bp;
5747 bp->prev = far_branch_list;
5748 far_branch_list = bp;
5750 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5751 LABEL_NUSES (bp->far_label)++;
5755 label = bp->near_label;
5756 if (! label && bp->address - addr >= CONDJUMP_MIN)
5758 rtx block = bp->insert_place;
5760 if (GET_CODE (PATTERN (block)) == RETURN)
5761 block = PREV_INSN (block);
5763 block = gen_block_redirect (block,
5765 label = emit_label_after (gen_label_rtx (),
5767 bp->near_label = label;
5769 else if (label && ! NEXT_INSN (label))
5771 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5772 bp->insert_place = insn;
5774 gen_far_branch (bp);
5778 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5780 bp->near_label = label = gen_label_rtx ();
5781 bp->insert_place = insn;
5784 ok = redirect_jump (insn, label, 0);
5789 /* get_attr_length (insn) == 2 */
5790 /* Check if we have a pattern where reorg wants to redirect
5791 the branch to a label from an unconditional branch that
5793 /* We can't use JUMP_LABEL here because it might be undefined
5794 when not optimizing. */
5795 /* A syntax error might cause beyond to be NULL_RTX. */
5797 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5802 || ((beyond = next_active_insn (beyond))
5803 && JUMP_P (beyond)))
5804 && GET_CODE (PATTERN (beyond)) == SET
5805 && recog_memoized (beyond) == CODE_FOR_jump_compact
5807 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5808 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5810 gen_block_redirect (beyond,
5811 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5814 next = next_active_insn (insn);
5817 || ((next = next_active_insn (next))
5819 && GET_CODE (PATTERN (next)) == SET
5820 && recog_memoized (next) == CODE_FOR_jump_compact
5822 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5823 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5825 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5827 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5829 int addr = INSN_ADDRESSES (INSN_UID (insn));
5832 struct far_branch *bp;
5834 if (type == TYPE_JUMP)
5836 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5837 dest_uid = get_dest_uid (far_label, max_uid);
5840 /* Parse errors can lead to labels outside
5842 if (! NEXT_INSN (far_label))
5847 JUMP_LABEL (insn) = far_label;
5848 LABEL_NUSES (far_label)++;
5850 redirect_jump (insn, NULL_RTX, 1);
5854 bp = uid_branch[dest_uid];
5857 bp = (struct far_branch *) alloca (sizeof *bp);
5858 uid_branch[dest_uid] = bp;
5859 bp->prev = far_branch_list;
5860 far_branch_list = bp;
5862 bp->far_label = far_label;
5864 LABEL_NUSES (far_label)++;
5866 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5867 if (addr - bp->address <= CONDJUMP_MAX)
5868 emit_label_after (bp->near_label, PREV_INSN (insn));
5871 gen_far_branch (bp);
5877 bp->insert_place = insn;
5879 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5881 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5884 /* Generate all pending far branches,
5885 and free our references to the far labels. */
5886 while (far_branch_list)
5888 if (far_branch_list->near_label
5889 && ! NEXT_INSN (far_branch_list->near_label))
5890 gen_far_branch (far_branch_list);
5892 && far_branch_list->far_label
5893 && ! --LABEL_NUSES (far_branch_list->far_label))
5894 delete_insn (far_branch_list->far_label);
5895 far_branch_list = far_branch_list->prev;
5898 /* Instruction length information is no longer valid due to the new
5899 instructions that have been generated. */
5900 init_insn_lengths ();
5903 /* Dump out instruction addresses, which is useful for debugging the
5904 constant pool table stuff.
5906 If relaxing, output the label and pseudo-ops used to link together
5907 calls and the instruction which set the registers. */
5909 /* ??? The addresses printed by this routine for insns are nonsense for
5910 insns which are inside of a sequence where none of the inner insns have
5911 variable length. This is because the second pass of shorten_branches
5912 does not bother to update them. */
5915 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5916 int noperands ATTRIBUTE_UNUSED)
5918 if (TARGET_DUMPISIZE)
5919 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5925 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
5930 pattern = PATTERN (insn);
5931 if (GET_CODE (pattern) == PARALLEL)
5932 pattern = XVECEXP (pattern, 0, 0);
5933 switch (GET_CODE (pattern))
5936 if (GET_CODE (SET_SRC (pattern)) != CALL
5937 && get_attr_type (insn) != TYPE_SFUNC)
5939 targetm.asm_out.internal_label
5940 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5943 /* else FALLTHROUGH */
5945 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5946 CODE_LABEL_NUMBER (XEXP (note, 0)));
5956 /* Dump out any constants accumulated in the final pass. These will
5960 output_jump_label_table (void)
5966 fprintf (asm_out_file, "\t.align 2\n");
5967 for (i = 0; i < pool_size; i++)
5969 pool_node *p = &pool_vector[i];
5971 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5972 CODE_LABEL_NUMBER (p->label));
5973 output_asm_insn (".long %O0", &p->value);
5981 /* A full frame looks like:
5985 [ if current_function_anonymous_args
5998 local-0 <- fp points here. */
6000 /* Number of bytes pushed for anonymous args, used to pass information
6001 between expand_prologue and expand_epilogue. */
6003 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6004 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6005 for an epilogue and a negative value means that it's for a sibcall
6006 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6007 all the registers that are about to be restored, and hence dead. */
6010 output_stack_adjust (int size, rtx reg, int epilogue_p,
6011 HARD_REG_SET *live_regs_mask)
6013 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
6016 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6018 /* This test is bogus, as output_stack_adjust is used to re-align the
6021 gcc_assert (!(size % align));
6024 if (CONST_OK_FOR_ADD (size))
6025 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
6026 /* Try to do it with two partial adjustments; however, we must make
6027 sure that the stack is properly aligned at all times, in case
6028 an interrupt occurs between the two partial adjustments. */
6029 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6030 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
6032 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6033 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
6039 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
6042 /* If TEMP is invalid, we could temporarily save a general
6043 register to MACL. However, there is currently no need
6044 to handle this case, so just die when we see it. */
6046 || current_function_interrupt
6047 || ! call_really_used_regs[temp] || fixed_regs[temp])
6049 if (temp < 0 && ! current_function_interrupt
6050 && (TARGET_SHMEDIA || epilogue_p >= 0))
6053 COPY_HARD_REG_SET (temps, call_used_reg_set);
6054 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
6058 if (crtl->return_rtx)
6060 enum machine_mode mode;
6061 mode = GET_MODE (crtl->return_rtx);
6062 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6063 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
6065 for (i = 0; i < nreg; i++)
6066 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
6067 if (crtl->calls_eh_return)
6069 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6070 for (i = 0; i <= 3; i++)
6071 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6074 if (TARGET_SHMEDIA && epilogue_p < 0)
6075 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
6076 CLEAR_HARD_REG_BIT (temps, i);
6077 if (epilogue_p <= 0)
6079 for (i = FIRST_PARM_REG;
6080 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6081 CLEAR_HARD_REG_BIT (temps, i);
6082 if (cfun->static_chain_decl != NULL)
6083 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6085 temp = scavenge_reg (&temps);
6087 if (temp < 0 && live_regs_mask)
6091 COPY_HARD_REG_SET (temps, *live_regs_mask);
6092 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6093 temp = scavenge_reg (&temps);
6097 rtx adj_reg, tmp_reg, mem;
6099 /* If we reached here, the most likely case is the (sibcall)
6100 epilogue for non SHmedia. Put a special push/pop sequence
6101 for such case as the last resort. This looks lengthy but
6102 would not be problem because it seems to be very
6105 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
6108 /* ??? There is still the slight possibility that r4 or
6109 r5 have been reserved as fixed registers or assigned
6110 as global registers, and they change during an
6111 interrupt. There are possible ways to handle this:
6113 - If we are adjusting the frame pointer (r14), we can do
6114 with a single temp register and an ordinary push / pop
6116 - Grab any call-used or call-saved registers (i.e. not
6117 fixed or globals) for the temps we need. We might
6118 also grab r14 if we are adjusting the stack pointer.
6119 If we can't find enough available registers, issue
6120 a diagnostic and die - the user must have reserved
6121 way too many registers.
6122 But since all this is rather unlikely to happen and
6123 would require extra testing, we just die if r4 / r5
6124 are not available. */
6125 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6126 && !global_regs[4] && !global_regs[5]);
6128 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6129 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
6130 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
6131 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6132 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
6133 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6134 emit_move_insn (mem, tmp_reg);
6135 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6136 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6137 emit_move_insn (mem, tmp_reg);
6138 emit_move_insn (reg, adj_reg);
6139 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6140 emit_move_insn (adj_reg, mem);
6141 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6142 emit_move_insn (tmp_reg, mem);
6143 /* Tell flow the insns that pop r4/r5 aren't dead. */
6148 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
6150 /* If SIZE is negative, subtract the positive value.
6151 This sometimes allows a constant pool entry to be shared
6152 between prologue and epilogue code. */
6155 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
6156 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
6160 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
6161 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
6164 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6165 gen_rtx_SET (VOIDmode, reg,
6166 gen_rtx_PLUS (SImode, reg,
6176 RTX_FRAME_RELATED_P (x) = 1;
6180 /* Output RTL to push register RN onto the stack. */
6187 x = gen_push_fpul ();
6188 else if (rn == FPSCR_REG)
6189 x = gen_push_fpscr ();
6190 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6191 && FP_OR_XD_REGISTER_P (rn))
6193 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6195 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
6197 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6198 x = gen_push_e (gen_rtx_REG (SFmode, rn));
6200 x = gen_push (gen_rtx_REG (SImode, rn));
6203 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6207 /* Output RTL to pop register RN from the stack. */
6214 x = gen_pop_fpul ();
6215 else if (rn == FPSCR_REG)
6216 x = gen_pop_fpscr ();
6217 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6218 && FP_OR_XD_REGISTER_P (rn))
6220 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6222 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
6224 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6225 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
6227 x = gen_pop (gen_rtx_REG (SImode, rn));
6230 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6233 /* Generate code to push the regs specified in the mask. */
6236 push_regs (HARD_REG_SET *mask, int interrupt_handler)
6238 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
6241 /* Push PR last; this gives better latencies after the prologue, and
6242 candidates for the return delay slot when there are no general
6243 registers pushed. */
6244 for (; i < FIRST_PSEUDO_REGISTER; i++)
6246 /* If this is an interrupt handler, and the SZ bit varies,
6247 and we have to push any floating point register, we need
6248 to switch to the correct precision first. */
6249 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
6250 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
6252 HARD_REG_SET unsaved;
6255 COMPL_HARD_REG_SET (unsaved, *mask);
6256 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6260 && (i != FPSCR_REG || ! skip_fpscr)
6261 && TEST_HARD_REG_BIT (*mask, i))
6263 /* If the ISR has RESBANK attribute assigned, don't push any of
6264 the following registers - R0-R14, MACH, MACL and GBR. */
6265 if (! (sh_cfun_resbank_handler_p ()
6266 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6274 /* Push banked registers last to improve delay slot opportunities. */
6275 if (interrupt_handler)
6276 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6277 if (TEST_HARD_REG_BIT (*mask, i))
6280 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6281 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
6285 /* Calculate how much extra space is needed to save all callee-saved
6287 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6290 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6293 int stack_space = 0;
6294 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6296 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6297 if ((! call_really_used_regs[reg] || interrupt_handler)
6298 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6299 /* Leave space to save this target register on the stack,
6300 in case target register allocation wants to use it. */
6301 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6305 /* Decide whether we should reserve space for callee-save target registers,
6306 in case target register allocation wants to use them. REGS_SAVED is
6307 the space, in bytes, that is already required for register saves.
6308 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6311 shmedia_reserve_space_for_target_registers_p (int regs_saved,
6312 HARD_REG_SET *live_regs_mask)
6316 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6319 /* Decide how much space to reserve for callee-save target registers
6320 in case target register allocation wants to use them.
6321 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6324 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6326 if (shmedia_space_reserved_for_target_registers)
6327 return shmedia_target_regs_stack_space (live_regs_mask);
6332 /* Work out the registers which need to be saved, both as a mask and a
6333 count of saved words. Return the count.
6335 If doing a pragma interrupt function, then push all regs used by the
6336 function, and if we call another function (we can tell by looking at PR),
6337 make sure that all the regs it clobbers are safe too. */
6340 calc_live_regs (HARD_REG_SET *live_regs_mask)
6345 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6346 bool nosave_low_regs;
6347 int pr_live, has_call;
6349 attrs = DECL_ATTRIBUTES (current_function_decl);
6350 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6351 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6352 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6353 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6355 CLEAR_HARD_REG_SET (*live_regs_mask);
6356 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6357 && df_regs_ever_live_p (FPSCR_REG))
6358 target_flags &= ~MASK_FPU_SINGLE;
6359 /* If we can save a lot of saves by switching to double mode, do that. */
6360 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
6361 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6362 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6363 && (! call_really_used_regs[reg]
6364 || interrupt_handler)
6367 target_flags &= ~MASK_FPU_SINGLE;
6370 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6371 knows how to use it. That means the pseudo originally allocated for
6372 the initial value can become the PR_MEDIA_REG hard register, as seen for
6373 execute/20010122-1.c:test9. */
6375 /* ??? this function is called from initial_elimination_offset, hence we
6376 can't use the result of sh_media_register_for_return here. */
6377 pr_live = sh_pr_n_sets ();
6380 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6381 pr_live = (pr_initial
6382 ? (!REG_P (pr_initial)
6383 || REGNO (pr_initial) != (PR_REG))
6384 : df_regs_ever_live_p (PR_REG));
6385 /* For Shcompact, if not optimizing, we end up with a memory reference
6386 using the return address pointer for __builtin_return_address even
6387 though there is no actual need to put the PR register on the stack. */
6388 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
6390 /* Force PR to be live if the prologue has to call the SHmedia
6391 argument decoder or register saver. */
6392 if (TARGET_SHCOMPACT
6393 && ((crtl->args.info.call_cookie
6394 & ~ CALL_COOKIE_RET_TRAMP (1))
6395 || crtl->saves_all_registers))
6397 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
6398 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
6400 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
6403 ? (/* Need to save all the regs ever live. */
6404 (df_regs_ever_live_p (reg)
6405 || (call_really_used_regs[reg]
6406 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6407 || reg == PIC_OFFSET_TABLE_REGNUM)
6409 || (TARGET_SHMEDIA && has_call
6410 && REGISTER_NATURAL_MODE (reg) == SImode
6411 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
6412 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6413 && reg != RETURN_ADDRESS_POINTER_REGNUM
6414 && reg != T_REG && reg != GBR_REG
6415 /* Push fpscr only on targets which have FPU */
6416 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6417 : (/* Only push those regs which are used and need to be saved. */
6420 && crtl->args.info.call_cookie
6421 && reg == PIC_OFFSET_TABLE_REGNUM)
6422 || (df_regs_ever_live_p (reg)
6423 && ((!call_really_used_regs[reg]
6424 && !(reg != PIC_OFFSET_TABLE_REGNUM
6425 && fixed_regs[reg] && call_used_regs[reg]))
6426 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6427 || (crtl->calls_eh_return
6428 && (reg == EH_RETURN_DATA_REGNO (0)
6429 || reg == EH_RETURN_DATA_REGNO (1)
6430 || reg == EH_RETURN_DATA_REGNO (2)
6431 || reg == EH_RETURN_DATA_REGNO (3)))
6432 || ((reg == MACL_REG || reg == MACH_REG)
6433 && df_regs_ever_live_p (reg)
6434 && sh_cfun_attr_renesas_p ())
6437 SET_HARD_REG_BIT (*live_regs_mask, reg);
6438 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6440 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6441 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6443 if (FP_REGISTER_P (reg))
6445 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6447 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6448 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6451 else if (XD_REGISTER_P (reg))
6453 /* Must switch to double mode to access these registers. */
6454 target_flags &= ~MASK_FPU_SINGLE;
6458 if (nosave_low_regs && reg == R8_REG)
6461 /* If we have a target register optimization pass after prologue / epilogue
6462 threading, we need to assume all target registers will be live even if
6464 if (flag_branch_target_load_optimize2
6465 && TARGET_SAVE_ALL_TARGET_REGS
6466 && shmedia_space_reserved_for_target_registers)
6467 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6468 if ((! call_really_used_regs[reg] || interrupt_handler)
6469 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6471 SET_HARD_REG_BIT (*live_regs_mask, reg);
6472 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6474 /* If this is an interrupt handler, we don't have any call-clobbered
6475 registers we can conveniently use for target register save/restore.
6476 Make sure we save at least one general purpose register when we need
6477 to save target registers. */
6478 if (interrupt_handler
6479 && hard_reg_set_intersect_p (*live_regs_mask,
6480 reg_class_contents[TARGET_REGS])
6481 && ! hard_reg_set_intersect_p (*live_regs_mask,
6482 reg_class_contents[GENERAL_REGS]))
6484 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6485 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6491 /* Code to generate prologue and epilogue sequences */
6493 /* PUSHED is the number of bytes that are being pushed on the
6494 stack for register saves. Return the frame size, padded
6495 appropriately so that the stack stays properly aligned. */
6496 static HOST_WIDE_INT
6497 rounded_frame_size (int pushed)
6499 HOST_WIDE_INT size = get_frame_size ();
6500 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6502 return ((size + pushed + align - 1) & -align) - pushed;
6505 /* Choose a call-clobbered target-branch register that remains
6506 unchanged along the whole function. We set it up as the return
6507 value in the prologue. */
6509 sh_media_register_for_return (void)
6514 if (! current_function_is_leaf)
6516 if (lookup_attribute ("interrupt_handler",
6517 DECL_ATTRIBUTES (current_function_decl)))
6519 if (sh_cfun_interrupt_handler_p ())
6522 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6524 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6525 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6531 /* The maximum registers we need to save are:
6532 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6533 - 32 floating point registers (for each pair, we save none,
6534 one single precision value, or a double precision value).
6535 - 8 target registers
6536 - add 1 entry for a delimiter. */
6537 #define MAX_SAVED_REGS (62+32+8)
6539 typedef struct save_entry_s
6548 /* There will be a delimiter entry with VOIDmode both at the start and the
6549 end of a filled in schedule. The end delimiter has the offset of the
6550 save with the smallest (i.e. most negative) offset. */
6551 typedef struct save_schedule_s
6553 save_entry entries[MAX_SAVED_REGS + 2];
6554 int temps[MAX_TEMPS+1];
6557 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6558 use reverse order. Returns the last entry written to (not counting
6559 the delimiter). OFFSET_BASE is a number to be added to all offset
6563 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6567 save_entry *entry = schedule->entries;
6571 if (! current_function_interrupt)
6572 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6573 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6574 && ! FUNCTION_ARG_REGNO_P (i)
6575 && i != FIRST_RET_REG
6576 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6577 && ! (crtl->calls_eh_return
6578 && (i == EH_RETURN_STACKADJ_REGNO
6579 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6580 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6581 schedule->temps[tmpx++] = i;
6583 entry->mode = VOIDmode;
6584 entry->offset = offset_base;
6586 /* We loop twice: first, we save 8-byte aligned registers in the
6587 higher addresses, that are known to be aligned. Then, we
6588 proceed to saving 32-bit registers that don't need 8-byte
6590 If this is an interrupt function, all registers that need saving
6591 need to be saved in full. moreover, we need to postpone saving
6592 target registers till we have saved some general purpose registers
6593 we can then use as scratch registers. */
6594 offset = offset_base;
6595 for (align = 1; align >= 0; align--)
6597 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6598 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6600 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6603 if (current_function_interrupt)
6605 if (TARGET_REGISTER_P (i))
6607 if (GENERAL_REGISTER_P (i))
6610 if (mode == SFmode && (i % 2) == 1
6611 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6612 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6619 /* If we're doing the aligned pass and this is not aligned,
6620 or we're doing the unaligned pass and this is aligned,
6622 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6626 if (current_function_interrupt
6627 && GENERAL_REGISTER_P (i)
6628 && tmpx < MAX_TEMPS)
6629 schedule->temps[tmpx++] = i;
6631 offset -= GET_MODE_SIZE (mode);
6634 entry->offset = offset;
6637 if (align && current_function_interrupt)
6638 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6639 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6641 offset -= GET_MODE_SIZE (DImode);
6643 entry->mode = DImode;
6644 entry->offset = offset;
6649 entry->mode = VOIDmode;
6650 entry->offset = offset;
6651 schedule->temps[tmpx] = -1;
6656 sh_expand_prologue (void)
6658 HARD_REG_SET live_regs_mask;
6661 int save_flags = target_flags;
6664 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6666 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6668 /* We have pretend args if we had an object sent partially in registers
6669 and partially on the stack, e.g. a large structure. */
6670 pretend_args = crtl->args.pretend_args_size;
6671 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6672 && (NPARM_REGS(SImode)
6673 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6675 output_stack_adjust (-pretend_args
6676 - crtl->args.info.stack_regs * 8,
6677 stack_pointer_rtx, 0, NULL);
6679 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6680 /* We're going to use the PIC register to load the address of the
6681 incoming-argument decoder and/or of the return trampoline from
6682 the GOT, so make sure the PIC register is preserved and
6684 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6686 if (TARGET_SHCOMPACT
6687 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6691 /* First, make all registers with incoming arguments that will
6692 be pushed onto the stack live, so that register renaming
6693 doesn't overwrite them. */
6694 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6695 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6696 >= NPARM_REGS (SImode) - reg)
6697 for (; reg < NPARM_REGS (SImode); reg++)
6698 emit_insn (gen_shcompact_preserve_incoming_args
6699 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6700 else if (CALL_COOKIE_INT_REG_GET
6701 (crtl->args.info.call_cookie, reg) == 1)
6702 emit_insn (gen_shcompact_preserve_incoming_args
6703 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6705 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6707 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6708 GEN_INT (crtl->args.info.call_cookie));
6709 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6710 gen_rtx_REG (SImode, R0_REG));
6712 else if (TARGET_SHMEDIA)
6714 int tr = sh_media_register_for_return ();
6717 emit_move_insn (gen_rtx_REG (DImode, tr),
6718 gen_rtx_REG (DImode, PR_MEDIA_REG));
6721 /* Emit the code for SETUP_VARARGS. */
6724 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6726 /* Push arg regs as if they'd been provided by caller in stack. */
6727 for (i = 0; i < NPARM_REGS(SImode); i++)
6729 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6732 if (i >= (NPARM_REGS(SImode)
6733 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6741 /* If we're supposed to switch stacks at function entry, do so now. */
6745 /* The argument specifies a variable holding the address of the
6746 stack the interrupt function should switch to/from at entry/exit. */
6747 tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr));
6749 = ggc_strdup (TREE_STRING_POINTER (arg));
6750 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6752 lab = add_constant (sp_switch, SImode, 0);
6753 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
6754 newsrc = gen_const_mem (SImode, newsrc);
6756 emit_insn (gen_sp_switch_1 (newsrc));
6759 d = calc_live_regs (&live_regs_mask);
6760 /* ??? Maybe we could save some switching if we can move a mode switch
6761 that already happens to be at the function start into the prologue. */
6762 if (target_flags != save_flags && ! current_function_interrupt)
6763 emit_insn (gen_toggle_sz ());
6767 int offset_base, offset;
6769 int offset_in_r0 = -1;
6771 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6772 int total_size, save_size;
6773 save_schedule schedule;
6777 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6778 && ! current_function_interrupt)
6779 r0 = gen_rtx_REG (Pmode, R0_REG);
6781 /* D is the actual number of bytes that we need for saving registers,
6782 however, in initial_elimination_offset we have committed to using
6783 an additional TREGS_SPACE amount of bytes - in order to keep both
6784 addresses to arguments supplied by the caller and local variables
6785 valid, we must keep this gap. Place it between the incoming
6786 arguments and the actually saved registers in a bid to optimize
6787 locality of reference. */
6788 total_size = d + tregs_space;
6789 total_size += rounded_frame_size (total_size);
6790 save_size = total_size - rounded_frame_size (d);
6791 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6792 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6793 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6795 /* If adjusting the stack in a single step costs nothing extra, do so.
6796 I.e. either if a single addi is enough, or we need a movi anyway,
6797 and we don't exceed the maximum offset range (the test for the
6798 latter is conservative for simplicity). */
6800 && (CONST_OK_FOR_I10 (-total_size)
6801 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6802 && total_size <= 2044)))
6803 d_rounding = total_size - save_size;
6805 offset_base = d + d_rounding;
6807 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6810 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6811 tmp_pnt = schedule.temps;
6812 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6814 enum machine_mode mode = (enum machine_mode) entry->mode;
6815 unsigned int reg = entry->reg;
6816 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6819 offset = entry->offset;
6821 reg_rtx = gen_rtx_REG (mode, reg);
6823 mem_rtx = gen_frame_mem (mode,
6824 gen_rtx_PLUS (Pmode,
6828 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6834 if (HAVE_PRE_DECREMENT
6835 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6836 || mem_rtx == NULL_RTX
6837 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6839 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6841 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
6846 offset += GET_MODE_SIZE (mode);
6850 if (mem_rtx != NULL_RTX)
6853 if (offset_in_r0 == -1)
6855 emit_move_insn (r0, GEN_INT (offset));
6856 offset_in_r0 = offset;
6858 else if (offset != offset_in_r0)
6863 GEN_INT (offset - offset_in_r0)));
6864 offset_in_r0 += offset - offset_in_r0;
6867 if (pre_dec != NULL_RTX)
6873 (Pmode, r0, stack_pointer_rtx));
6877 offset -= GET_MODE_SIZE (mode);
6878 offset_in_r0 -= GET_MODE_SIZE (mode);
6883 mem_rtx = gen_frame_mem (mode, r0);
6885 mem_rtx = gen_frame_mem (mode,
6886 gen_rtx_PLUS (Pmode,
6890 /* We must not use an r0-based address for target-branch
6891 registers or for special registers without pre-dec
6892 memory addresses, since we store their values in r0
6894 gcc_assert (!TARGET_REGISTER_P (reg)
6895 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6896 || mem_rtx == pre_dec));
6899 orig_reg_rtx = reg_rtx;
6900 if (TARGET_REGISTER_P (reg)
6901 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6902 && mem_rtx != pre_dec))
6904 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6906 emit_move_insn (tmp_reg, reg_rtx);
6908 if (REGNO (tmp_reg) == R0_REG)
6912 gcc_assert (!refers_to_regno_p
6913 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6916 if (*++tmp_pnt <= 0)
6917 tmp_pnt = schedule.temps;
6924 /* Mark as interesting for dwarf cfi generator */
6925 insn = emit_move_insn (mem_rtx, reg_rtx);
6926 RTX_FRAME_RELATED_P (insn) = 1;
6927 /* If we use an intermediate register for the save, we can't
6928 describe this exactly in cfi as a copy of the to-be-saved
6929 register into the temporary register and then the temporary
6930 register on the stack, because the temporary register can
6931 have a different natural size than the to-be-saved register.
6932 Thus, we gloss over the intermediate copy and pretend we do
6933 a direct save from the to-be-saved register. */
6934 if (REGNO (reg_rtx) != reg)
6938 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6939 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6942 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6944 rtx reg_rtx = gen_rtx_REG (mode, reg);
6946 rtx mem_rtx = gen_frame_mem (mode,
6947 gen_rtx_PLUS (Pmode,
6951 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6952 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6957 gcc_assert (entry->offset == d_rounding);
6960 push_regs (&live_regs_mask, current_function_interrupt);
6962 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
6963 emit_insn (gen_GOTaddr2picreg ());
6965 if (SHMEDIA_REGS_STACK_ADJUST ())
6967 /* This must NOT go through the PLT, otherwise mach and macl
6968 may be clobbered. */
6969 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6971 ? "__GCC_push_shmedia_regs"
6972 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
6973 emit_insn (gen_shmedia_save_restore_regs_compact
6974 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
6977 if (target_flags != save_flags && ! current_function_interrupt)
6978 emit_insn (gen_toggle_sz ());
6980 target_flags = save_flags;
6982 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
6983 stack_pointer_rtx, 0, NULL);
6985 if (frame_pointer_needed)
6986 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
6988 if (TARGET_SHCOMPACT
6989 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6991 /* This must NOT go through the PLT, otherwise mach and macl
6992 may be clobbered. */
6993 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6994 "__GCC_shcompact_incoming_args", SFUNC_GOT);
6995 emit_insn (gen_shcompact_incoming_args ());
7000 sh_expand_epilogue (bool sibcall_p)
7002 HARD_REG_SET live_regs_mask;
7006 int save_flags = target_flags;
7007 int frame_size, save_size;
7008 int fpscr_deferred = 0;
7009 int e = sibcall_p ? -1 : 1;
7011 d = calc_live_regs (&live_regs_mask);
7014 frame_size = rounded_frame_size (d);
7018 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7020 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
7021 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7022 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
7024 total_size = d + tregs_space;
7025 total_size += rounded_frame_size (total_size);
7026 save_size = total_size - frame_size;
7028 /* If adjusting the stack in a single step costs nothing extra, do so.
7029 I.e. either if a single addi is enough, or we need a movi anyway,
7030 and we don't exceed the maximum offset range (the test for the
7031 latter is conservative for simplicity). */
7033 && ! frame_pointer_needed
7034 && (CONST_OK_FOR_I10 (total_size)
7035 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
7036 && total_size <= 2044)))
7037 d_rounding = frame_size;
7039 frame_size -= d_rounding;
7042 if (frame_pointer_needed)
7044 /* We must avoid scheduling the epilogue with previous basic blocks.
7045 See PR/18032 and PR/40313. */
7046 emit_insn (gen_blockage ());
7047 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7050 /* We must avoid moving the stack pointer adjustment past code
7051 which reads from the local frame, else an interrupt could
7052 occur after the SP adjustment and clobber data in the local
7054 emit_insn (gen_blockage ());
7055 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
7057 else if (frame_size)
7059 /* We must avoid moving the stack pointer adjustment past code
7060 which reads from the local frame, else an interrupt could
7061 occur after the SP adjustment and clobber data in the local
7063 emit_insn (gen_blockage ());
7064 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
7067 if (SHMEDIA_REGS_STACK_ADJUST ())
7069 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7071 ? "__GCC_pop_shmedia_regs"
7072 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
7073 /* This must NOT go through the PLT, otherwise mach and macl
7074 may be clobbered. */
7075 emit_insn (gen_shmedia_save_restore_regs_compact
7076 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7079 /* Pop all the registers. */
7081 if (target_flags != save_flags && ! current_function_interrupt)
7082 emit_insn (gen_toggle_sz ());
7085 int offset_base, offset;
7086 int offset_in_r0 = -1;
7088 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
7089 save_schedule schedule;
7093 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
7094 offset_base = -entry[1].offset + d_rounding;
7095 tmp_pnt = schedule.temps;
7096 for (; entry->mode != VOIDmode; entry--)
7098 enum machine_mode mode = (enum machine_mode) entry->mode;
7099 int reg = entry->reg;
7100 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
7102 offset = offset_base + entry->offset;
7103 reg_rtx = gen_rtx_REG (mode, reg);
7105 mem_rtx = gen_frame_mem (mode,
7106 gen_rtx_PLUS (Pmode,
7110 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7113 if (HAVE_POST_INCREMENT
7114 && (offset == offset_in_r0
7115 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
7116 && mem_rtx == NULL_RTX)
7117 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7119 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
7121 if (!memory_address_p (mode, XEXP (post_inc, 0)))
7122 post_inc = NULL_RTX;
7127 if (mem_rtx != NULL_RTX)
7130 if (offset_in_r0 == -1)
7132 emit_move_insn (r0, GEN_INT (offset));
7133 offset_in_r0 = offset;
7135 else if (offset != offset_in_r0)
7140 GEN_INT (offset - offset_in_r0)));
7141 offset_in_r0 += offset - offset_in_r0;
7144 if (post_inc != NULL_RTX)
7150 (Pmode, r0, stack_pointer_rtx));
7156 offset_in_r0 += GET_MODE_SIZE (mode);
7159 mem_rtx = gen_frame_mem (mode, r0);
7161 mem_rtx = gen_frame_mem (mode,
7162 gen_rtx_PLUS (Pmode,
7166 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7167 || mem_rtx == post_inc);
7170 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7171 && mem_rtx != post_inc)
7173 insn = emit_move_insn (r0, mem_rtx);
7176 else if (TARGET_REGISTER_P (reg))
7178 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
7180 /* Give the scheduler a bit of freedom by using up to
7181 MAX_TEMPS registers in a round-robin fashion. */
7182 insn = emit_move_insn (tmp_reg, mem_rtx);
7185 tmp_pnt = schedule.temps;
7188 insn = emit_move_insn (reg_rtx, mem_rtx);
7191 gcc_assert (entry->offset + offset_base == d + d_rounding);
7193 else /* ! TARGET_SH5 */
7198 /* For an ISR with RESBANK attribute assigned, don't pop PR
7200 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7201 && !sh_cfun_resbank_handler_p ())
7203 if (!frame_pointer_needed)
7204 emit_insn (gen_blockage ());
7208 /* Banked registers are poped first to avoid being scheduled in the
7209 delay slot. RTE switches banks before the ds instruction. */
7210 if (current_function_interrupt)
7212 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7213 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7214 pop (LAST_BANKED_REG - i);
7216 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7219 last_reg = FIRST_PSEUDO_REGISTER;
7221 for (i = 0; i < last_reg; i++)
7223 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
7225 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
7226 && hard_reg_set_intersect_p (live_regs_mask,
7227 reg_class_contents[DF_REGS]))
7229 /* For an ISR with RESBANK attribute assigned, don't pop
7230 following registers, R0-R14, MACH, MACL and GBR. */
7231 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7232 && ! (sh_cfun_resbank_handler_p ()
7233 && ((j >= FIRST_GENERAL_REG
7234 && j < LAST_GENERAL_REG)
7240 if (j == FIRST_FP_REG && fpscr_deferred)
7244 if (target_flags != save_flags && ! current_function_interrupt)
7245 emit_insn (gen_toggle_sz ());
7246 target_flags = save_flags;
7248 output_stack_adjust (crtl->args.pretend_args_size
7249 + save_size + d_rounding
7250 + crtl->args.info.stack_regs * 8,
7251 stack_pointer_rtx, e, NULL);
7253 if (crtl->calls_eh_return)
7254 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7255 EH_RETURN_STACKADJ_RTX));
7257 /* Switch back to the normal stack if necessary. */
7258 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
7259 emit_insn (gen_sp_switch_2 ());
7261 /* Tell flow the insn that pops PR isn't dead. */
7262 /* PR_REG will never be live in SHmedia mode, and we don't need to
7263 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7264 by the return pattern. */
7265 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7266 emit_use (gen_rtx_REG (SImode, PR_REG));
7269 static int sh_need_epilogue_known = 0;
7272 sh_need_epilogue (void)
7274 if (! sh_need_epilogue_known)
7279 sh_expand_epilogue (0);
7280 epilogue = get_insns ();
7282 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
7284 return sh_need_epilogue_known > 0;
7287 /* Emit code to change the current function's return address to RA.
7288 TEMP is available as a scratch register, if needed. */
7291 sh_set_return_address (rtx ra, rtx tmp)
7293 HARD_REG_SET live_regs_mask;
7295 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7298 d = calc_live_regs (&live_regs_mask);
7300 /* If pr_reg isn't life, we can set it (or the register given in
7301 sh_media_register_for_return) directly. */
7302 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7308 int rr_regno = sh_media_register_for_return ();
7313 rr = gen_rtx_REG (DImode, rr_regno);
7316 rr = gen_rtx_REG (SImode, pr_reg);
7318 emit_insn (GEN_MOV (rr, ra));
7319 /* Tell flow the register for return isn't dead. */
7327 save_schedule schedule;
7330 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7331 offset = entry[1].offset;
7332 for (; entry->mode != VOIDmode; entry--)
7333 if (entry->reg == pr_reg)
7336 /* We can't find pr register. */
7340 offset = entry->offset - offset;
7341 pr_offset = (rounded_frame_size (d) + offset
7342 + SHMEDIA_REGS_STACK_ADJUST ());
7345 pr_offset = rounded_frame_size (d);
7347 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7348 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7350 tmp = gen_frame_mem (Pmode, tmp);
7351 emit_insn (GEN_MOV (tmp, ra));
7352 /* Tell this store isn't dead. */
7356 /* Clear variables at function end. */
7359 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7360 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7362 sh_need_epilogue_known = 0;
7366 sh_builtin_saveregs (void)
7368 /* First unnamed integer register. */
7369 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7370 /* Number of integer registers we need to save. */
7371 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7372 /* First unnamed SFmode float reg */
7373 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7374 /* Number of SFmode float regs to save. */
7375 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7378 alias_set_type alias_set;
7384 int pushregs = n_intregs;
7386 while (pushregs < NPARM_REGS (SImode) - 1
7387 && (CALL_COOKIE_INT_REG_GET
7388 (crtl->args.info.call_cookie,
7389 NPARM_REGS (SImode) - pushregs)
7392 crtl->args.info.call_cookie
7393 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7398 if (pushregs == NPARM_REGS (SImode))
7399 crtl->args.info.call_cookie
7400 |= (CALL_COOKIE_INT_REG (0, 1)
7401 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7403 crtl->args.info.call_cookie
7404 |= CALL_COOKIE_STACKSEQ (pushregs);
7406 crtl->args.pretend_args_size += 8 * n_intregs;
7408 if (TARGET_SHCOMPACT)
7412 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7414 error ("__builtin_saveregs not supported by this subtarget");
7421 /* Allocate block of memory for the regs. */
7422 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7423 Or can assign_stack_local accept a 0 SIZE argument? */
7424 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7427 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7428 else if (n_floatregs & 1)
7432 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7433 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7434 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7435 regbuf = change_address (regbuf, BLKmode, addr);
7437 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7441 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7442 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7443 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7444 emit_insn (gen_andsi3 (addr, addr, mask));
7445 regbuf = change_address (regbuf, BLKmode, addr);
7448 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7449 alias_set = get_varargs_alias_set ();
7450 set_mem_alias_set (regbuf, alias_set);
7453 This is optimized to only save the regs that are necessary. Explicitly
7454 named args need not be saved. */
7456 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7457 adjust_address (regbuf, BLKmode,
7458 n_floatregs * UNITS_PER_WORD),
7462 /* Return the address of the regbuf. */
7463 return XEXP (regbuf, 0);
7466 This is optimized to only save the regs that are necessary. Explicitly
7467 named args need not be saved.
7468 We explicitly build a pointer to the buffer because it halves the insn
7469 count when not optimizing (otherwise the pointer is built for each reg
7471 We emit the moves in reverse order so that we can use predecrement. */
7473 fpregs = copy_to_mode_reg (Pmode,
7474 plus_constant (XEXP (regbuf, 0),
7475 n_floatregs * UNITS_PER_WORD));
7476 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7479 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7481 emit_insn (gen_addsi3 (fpregs, fpregs,
7482 GEN_INT (-2 * UNITS_PER_WORD)));
7483 mem = change_address (regbuf, DFmode, fpregs);
7484 emit_move_insn (mem,
7485 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7487 regno = first_floatreg;
7490 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7491 mem = change_address (regbuf, SFmode, fpregs);
7492 emit_move_insn (mem,
7493 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7494 - (TARGET_LITTLE_ENDIAN != 0)));
7498 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7502 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7503 mem = change_address (regbuf, SFmode, fpregs);
7504 emit_move_insn (mem,
7505 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7508 /* Return the address of the regbuf. */
7509 return XEXP (regbuf, 0);
7512 /* Define the `__builtin_va_list' type for the ABI. */
7515 sh_build_builtin_va_list (void)
7517 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7520 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7521 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7522 return ptr_type_node;
7524 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7526 f_next_o = build_decl (BUILTINS_LOCATION,
7527 FIELD_DECL, get_identifier ("__va_next_o"),
7529 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7531 get_identifier ("__va_next_o_limit"),
7533 f_next_fp = build_decl (BUILTINS_LOCATION,
7534 FIELD_DECL, get_identifier ("__va_next_fp"),
7536 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7538 get_identifier ("__va_next_fp_limit"),
7540 f_next_stack = build_decl (BUILTINS_LOCATION,
7541 FIELD_DECL, get_identifier ("__va_next_stack"),
7544 DECL_FIELD_CONTEXT (f_next_o) = record;
7545 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7546 DECL_FIELD_CONTEXT (f_next_fp) = record;
7547 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7548 DECL_FIELD_CONTEXT (f_next_stack) = record;
7550 TYPE_FIELDS (record) = f_next_o;
7551 TREE_CHAIN (f_next_o) = f_next_o_limit;
7552 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7553 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7554 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7556 layout_type (record);
7561 /* Implement `va_start' for varargs and stdarg. */
7564 sh_va_start (tree valist, rtx nextarg)
7566 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7567 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7573 expand_builtin_saveregs ();
7574 std_expand_builtin_va_start (valist, nextarg);
7578 if ((! TARGET_SH2E && ! TARGET_SH4)
7579 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7581 std_expand_builtin_va_start (valist, nextarg);
7585 f_next_o = TYPE_FIELDS (va_list_type_node);
7586 f_next_o_limit = TREE_CHAIN (f_next_o);
7587 f_next_fp = TREE_CHAIN (f_next_o_limit);
7588 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7589 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7591 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7593 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7594 valist, f_next_o_limit, NULL_TREE);
7595 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7597 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7598 valist, f_next_fp_limit, NULL_TREE);
7599 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7600 valist, f_next_stack, NULL_TREE);
7602 /* Call __builtin_saveregs. */
7603 u = make_tree (sizetype, expand_builtin_saveregs ());
7604 u = fold_convert (ptr_type_node, u);
7605 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7606 TREE_SIDE_EFFECTS (t) = 1;
7607 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7609 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7614 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7615 size_int (UNITS_PER_WORD * nfp));
7616 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7617 TREE_SIDE_EFFECTS (t) = 1;
7618 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7620 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7621 TREE_SIDE_EFFECTS (t) = 1;
7622 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7624 nint = crtl->args.info.arg_count[SH_ARG_INT];
7629 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7630 size_int (UNITS_PER_WORD * nint));
7631 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7632 TREE_SIDE_EFFECTS (t) = 1;
7633 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7635 u = make_tree (ptr_type_node, nextarg);
7636 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7637 TREE_SIDE_EFFECTS (t) = 1;
7638 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7641 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7642 member, return it. */
7644 find_sole_member (tree type)
7646 tree field, member = NULL_TREE;
7648 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7650 if (TREE_CODE (field) != FIELD_DECL)
7652 if (!DECL_SIZE (field))
7654 if (integer_zerop (DECL_SIZE (field)))
7662 /* Implement `va_arg'. */
7665 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7666 gimple_seq *post_p ATTRIBUTE_UNUSED)
7668 HOST_WIDE_INT size, rsize;
7669 tree tmp, pptr_type_node;
7670 tree addr, lab_over = NULL, result = NULL;
7671 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7675 type = build_pointer_type (type);
7677 size = int_size_in_bytes (type);
7678 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7679 pptr_type_node = build_pointer_type (ptr_type_node);
7681 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7682 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7684 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7685 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7690 f_next_o = TYPE_FIELDS (va_list_type_node);
7691 f_next_o_limit = TREE_CHAIN (f_next_o);
7692 f_next_fp = TREE_CHAIN (f_next_o_limit);
7693 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7694 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7696 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7698 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7699 valist, f_next_o_limit, NULL_TREE);
7700 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7701 valist, f_next_fp, NULL_TREE);
7702 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7703 valist, f_next_fp_limit, NULL_TREE);
7704 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7705 valist, f_next_stack, NULL_TREE);
7707 /* Structures with a single member with a distinct mode are passed
7708 like their member. This is relevant if the latter has a REAL_TYPE
7709 or COMPLEX_TYPE type. */
7711 while (TREE_CODE (eff_type) == RECORD_TYPE
7712 && (member = find_sole_member (eff_type))
7713 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7714 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7715 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7717 tree field_type = TREE_TYPE (member);
7719 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7720 eff_type = field_type;
7723 gcc_assert ((TYPE_ALIGN (eff_type)
7724 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7725 || (TYPE_ALIGN (eff_type)
7726 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7731 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7733 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7734 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7735 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7740 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7743 addr = create_tmp_var (pptr_type_node, NULL);
7744 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7745 lab_over = create_artificial_label (UNKNOWN_LOCATION);
7747 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7751 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7753 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7755 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7756 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7758 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7759 tmp = next_fp_limit;
7760 if (size > 4 && !is_double)
7761 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
7762 unshare_expr (tmp), size_int (4 - size));
7763 tmp = build2 (GE_EXPR, boolean_type_node,
7764 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7765 cmp = build3 (COND_EXPR, void_type_node, tmp,
7766 build1 (GOTO_EXPR, void_type_node,
7767 unshare_expr (lab_false)), NULL_TREE);
7769 gimplify_and_add (cmp, pre_p);
7771 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7772 || (is_double || size == 16))
7774 tmp = fold_convert (sizetype, next_fp_tmp);
7775 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7776 size_int (UNITS_PER_WORD));
7777 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7778 unshare_expr (next_fp_tmp), tmp);
7779 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7782 gimplify_and_add (cmp, pre_p);
7784 #ifdef FUNCTION_ARG_SCmode_WART
7785 if (TYPE_MODE (eff_type) == SCmode
7786 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7788 tree subtype = TREE_TYPE (eff_type);
7792 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7793 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7796 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7797 real = get_initialized_tmp_var (real, pre_p, NULL);
7799 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7800 if (type != eff_type)
7801 result = build1 (VIEW_CONVERT_EXPR, type, result);
7802 result = get_initialized_tmp_var (result, pre_p, NULL);
7804 #endif /* FUNCTION_ARG_SCmode_WART */
7806 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7807 gimplify_and_add (tmp, pre_p);
7809 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7810 gimplify_and_add (tmp, pre_p);
7812 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7813 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7814 gimplify_assign (unshare_expr (next_fp_tmp),
7815 unshare_expr (valist), pre_p);
7817 gimplify_assign (unshare_expr (valist),
7818 unshare_expr (next_fp_tmp), post_p);
7819 valist = next_fp_tmp;
7823 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7824 unshare_expr (next_o), size_int (rsize));
7825 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7826 unshare_expr (next_o_limit));
7827 tmp = build3 (COND_EXPR, void_type_node, tmp,
7828 build1 (GOTO_EXPR, void_type_node,
7829 unshare_expr (lab_false)),
7831 gimplify_and_add (tmp, pre_p);
7833 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7834 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7836 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7837 gimplify_and_add (tmp, pre_p);
7839 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7840 gimplify_and_add (tmp, pre_p);
7842 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7843 gimplify_assign (unshare_expr (next_o),
7844 unshare_expr (next_o_limit), pre_p);
7846 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7847 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7852 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7853 gimplify_and_add (tmp, pre_p);
7857 /* ??? In va-sh.h, there had been code to make values larger than
7858 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7860 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7863 gimplify_assign (result, tmp, pre_p);
7864 result = build1 (NOP_EXPR, TREE_TYPE (result), result);
7865 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7866 gimplify_and_add (tmp, pre_p);
7872 result = build_va_arg_indirect_ref (result);
7877 /* 64 bit floating points memory transfers are paired single precision loads
7878 or store. So DWARF information needs fixing in little endian (unless
7879 PR=SZ=1 in FPSCR). */
7881 sh_dwarf_register_span (rtx reg)
7883 unsigned regno = REGNO (reg);
7885 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
7889 gen_rtx_PARALLEL (VOIDmode,
7891 gen_rtx_REG (SFmode,
7892 DBX_REGISTER_NUMBER (regno+1)),
7893 gen_rtx_REG (SFmode,
7894 DBX_REGISTER_NUMBER (regno))));
7898 sh_promote_function_mode (const_tree type, enum machine_mode mode,
7899 int *punsignedp, const_tree funtype, int for_return)
7901 if (sh_promote_prototypes (funtype))
7902 return promote_mode (type, machine_mode, punsignedp);
7908 sh_promote_prototypes (const_tree type)
7914 return ! sh_attr_renesas_p (type);
7917 /* Whether an argument must be passed by reference. On SHcompact, we
7918 pretend arguments wider than 32-bits that would have been passed in
7919 registers are passed by reference, so that an SHmedia trampoline
7920 loads them into the full 64-bits registers. */
7923 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7924 const_tree type, bool named)
7926 unsigned HOST_WIDE_INT size;
7929 size = int_size_in_bytes (type);
7931 size = GET_MODE_SIZE (mode);
7933 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7935 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7936 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7937 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7939 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7940 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7947 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7948 const_tree type, bool named)
7950 if (targetm.calls.must_pass_in_stack (mode, type))
7953 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7954 wants to know about pass-by-reference semantics for incoming
7959 if (TARGET_SHCOMPACT)
7961 cum->byref = shcompact_byref (cum, mode, type, named);
7962 return cum->byref != 0;
7969 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7970 const_tree type, bool named ATTRIBUTE_UNUSED)
7972 /* ??? How can it possibly be correct to return true only on the
7973 caller side of the equation? Is there someplace else in the
7974 sh backend that's magically producing the copies? */
7975 return (cum->outgoing
7976 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7977 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7981 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7982 tree type, bool named ATTRIBUTE_UNUSED)
7987 && PASS_IN_REG_P (*cum, mode, type)
7988 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7989 && (ROUND_REG (*cum, mode)
7991 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7992 : ROUND_ADVANCE (int_size_in_bytes (type)))
7993 > NPARM_REGS (mode)))
7994 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
7996 else if (!TARGET_SHCOMPACT
7997 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7998 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
8000 return words * UNITS_PER_WORD;
8004 /* Define where to put the arguments to a function.
8005 Value is zero to push the argument on the stack,
8006 or a hard register in which to store the argument.
8008 MODE is the argument's machine mode.
8009 TYPE is the data type of the argument (as a tree).
8010 This is null for libcalls where that information may
8012 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8013 the preceding args and about the function being called.
8014 NAMED is nonzero if this argument is a named parameter
8015 (otherwise it is an extra parameter matching an ellipsis).
8017 On SH the first args are normally in registers
8018 and the rest are pushed. Any arg that starts within the first
8019 NPARM_REGS words is at least partially passed in a register unless
8020 its data type forbids. */
8024 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8025 tree type, int named)
8027 if (! TARGET_SH5 && mode == VOIDmode)
8028 return GEN_INT (ca->renesas_abi ? 1 : 0);
8031 && PASS_IN_REG_P (*ca, mode, type)
8032 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8036 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8037 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
8039 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8040 gen_rtx_REG (SFmode,
8042 + (ROUND_REG (*ca, mode) ^ 1)),
8044 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8045 gen_rtx_REG (SFmode,
8047 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
8049 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8052 /* If the alignment of a DF value causes an SF register to be
8053 skipped, we will use that skipped register for the next SF
8055 if ((TARGET_HITACHI || ca->renesas_abi)
8056 && ca->free_single_fp_reg
8058 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8060 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
8061 ^ (mode == SFmode && TARGET_SH4
8062 && TARGET_LITTLE_ENDIAN != 0
8063 && ! TARGET_HITACHI && ! ca->renesas_abi);
8064 return gen_rtx_REG (mode, regno);
8070 if (mode == VOIDmode && TARGET_SHCOMPACT)
8071 return GEN_INT (ca->call_cookie);
8073 /* The following test assumes unnamed arguments are promoted to
8075 if (mode == SFmode && ca->free_single_fp_reg)
8076 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
8078 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
8079 && (named || ! ca->prototype_p)
8080 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
8082 if (! ca->prototype_p && TARGET_SHMEDIA)
8083 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
8085 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
8087 + ca->arg_count[(int) SH_ARG_FLOAT]);
8090 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
8091 && (! TARGET_SHCOMPACT
8092 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
8093 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
8096 return gen_rtx_REG (mode, (FIRST_PARM_REG
8097 + ca->arg_count[(int) SH_ARG_INT]));
8106 /* Update the data in CUM to advance over an argument
8107 of mode MODE and data type TYPE.
8108 (TYPE is null for libcalls where that information may not be
8112 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8113 tree type, int named)
8117 else if (TARGET_SH5)
8119 tree type2 = (ca->byref && type
8122 enum machine_mode mode2 = (ca->byref && type
8125 int dwords = ((ca->byref
8128 ? int_size_in_bytes (type2)
8129 : GET_MODE_SIZE (mode2)) + 7) / 8;
8130 int numregs = MIN (dwords, NPARM_REGS (SImode)
8131 - ca->arg_count[(int) SH_ARG_INT]);
8135 ca->arg_count[(int) SH_ARG_INT] += numregs;
8136 if (TARGET_SHCOMPACT
8137 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
8140 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8142 /* N.B. We want this also for outgoing. */
8143 ca->stack_regs += numregs;
8148 ca->stack_regs += numregs;
8149 ca->byref_regs += numregs;
8153 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8157 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8160 else if (dwords > numregs)
8162 int pushregs = numregs;
8164 if (TARGET_SHCOMPACT)
8165 ca->stack_regs += numregs;
8166 while (pushregs < NPARM_REGS (SImode) - 1
8167 && (CALL_COOKIE_INT_REG_GET
8169 NPARM_REGS (SImode) - pushregs)
8173 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
8177 if (numregs == NPARM_REGS (SImode))
8179 |= CALL_COOKIE_INT_REG (0, 1)
8180 | CALL_COOKIE_STACKSEQ (numregs - 1);
8183 |= CALL_COOKIE_STACKSEQ (numregs);
8186 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
8187 && (named || ! ca->prototype_p))
8189 if (mode2 == SFmode && ca->free_single_fp_reg)
8190 ca->free_single_fp_reg = 0;
8191 else if (ca->arg_count[(int) SH_ARG_FLOAT]
8192 < NPARM_REGS (SFmode))
8195 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
8197 - ca->arg_count[(int) SH_ARG_FLOAT]);
8199 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
8201 if (TARGET_SHCOMPACT && ! ca->prototype_p)
8203 if (ca->outgoing && numregs > 0)
8207 |= (CALL_COOKIE_INT_REG
8208 (ca->arg_count[(int) SH_ARG_INT]
8209 - numregs + ((numfpregs - 2) / 2),
8210 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
8213 while (numfpregs -= 2);
8215 else if (mode2 == SFmode && (named)
8216 && (ca->arg_count[(int) SH_ARG_FLOAT]
8217 < NPARM_REGS (SFmode)))
8218 ca->free_single_fp_reg
8219 = FIRST_FP_PARM_REG - numfpregs
8220 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
8226 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8228 /* Note that we've used the skipped register. */
8229 if (mode == SFmode && ca->free_single_fp_reg)
8231 ca->free_single_fp_reg = 0;
8234 /* When we have a DF after an SF, there's an SF register that get
8235 skipped in order to align the DF value. We note this skipped
8236 register, because the next SF value will use it, and not the
8237 SF that follows the DF. */
8239 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
8241 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
8242 + BASE_ARG_REG (mode));
8246 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
8247 || PASS_IN_REG_P (*ca, mode, type))
8248 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
8249 = (ROUND_REG (*ca, mode)
8251 ? ROUND_ADVANCE (int_size_in_bytes (type))
8252 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
8255 /* The Renesas calling convention doesn't quite fit into this scheme since
8256 the address is passed like an invisible argument, but one that is always
8257 passed in memory. */
8259 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
8261 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8263 return gen_rtx_REG (Pmode, 2);
8266 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8269 sh_return_in_memory (const_tree type, const_tree fndecl)
8273 if (TYPE_MODE (type) == BLKmode)
8274 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
8276 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
8280 return (TYPE_MODE (type) == BLKmode
8281 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8282 && TREE_CODE (type) == RECORD_TYPE));
8286 /* We actually emit the code in sh_expand_prologue. We used to use
8287 a static variable to flag that we need to emit this code, but that
8288 doesn't when inlining, when functions are deferred and then emitted
8289 later. Fortunately, we already have two flags that are part of struct
8290 function that tell if a function uses varargs or stdarg. */
8292 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
8293 enum machine_mode mode,
8295 int *pretend_arg_size,
8296 int second_time ATTRIBUTE_UNUSED)
8298 gcc_assert (cfun->stdarg);
8299 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8301 int named_parm_regs, anon_parm_regs;
8303 named_parm_regs = (ROUND_REG (*ca, mode)
8305 ? ROUND_ADVANCE (int_size_in_bytes (type))
8306 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
8307 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8308 if (anon_parm_regs > 0)
8309 *pretend_arg_size = anon_parm_regs * 4;
8314 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
8320 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
8322 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8326 /* Define the offset between two registers, one to be eliminated, and
8327 the other its replacement, at the start of a routine. */
8330 initial_elimination_offset (int from, int to)
8333 int regs_saved_rounding = 0;
8334 int total_saved_regs_space;
8335 int total_auto_space;
8336 int save_flags = target_flags;
8338 HARD_REG_SET live_regs_mask;
8340 shmedia_space_reserved_for_target_registers = false;
8341 regs_saved = calc_live_regs (&live_regs_mask);
8342 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8344 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8346 shmedia_space_reserved_for_target_registers = true;
8347 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8350 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8351 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8352 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8354 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8355 copy_flags = target_flags;
8356 target_flags = save_flags;
8358 total_saved_regs_space = regs_saved + regs_saved_rounding;
8360 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8361 return total_saved_regs_space + total_auto_space
8362 + crtl->args.info.byref_regs * 8;
8364 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8365 return total_saved_regs_space + total_auto_space
8366 + crtl->args.info.byref_regs * 8;
8368 /* Initial gap between fp and sp is 0. */
8369 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8372 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8373 return rounded_frame_size (0);
8375 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8376 return rounded_frame_size (0);
8378 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8379 && (to == HARD_FRAME_POINTER_REGNUM
8380 || to == STACK_POINTER_REGNUM));
8383 int n = total_saved_regs_space;
8384 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8385 save_schedule schedule;
8388 n += total_auto_space;
8390 /* If it wasn't saved, there's not much we can do. */
8391 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8394 target_flags = copy_flags;
8396 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8397 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8398 if (entry->reg == pr_reg)
8400 target_flags = save_flags;
8401 return entry->offset;
8406 return total_auto_space;
8409 /* Parse the -mfixed-range= option string. */
8411 sh_fix_range (const char *const_str)
8414 char *str, *dash, *comma;
8416 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8417 REG2 are either register names or register numbers. The effect
8418 of this option is to mark the registers in the range from REG1 to
8419 REG2 as ``fixed'' so they won't be used by the compiler. */
8421 i = strlen (const_str);
8422 str = (char *) alloca (i + 1);
8423 memcpy (str, const_str, i + 1);
8427 dash = strchr (str, '-');
8430 warning (0, "value of -mfixed-range must have form REG1-REG2");
8434 comma = strchr (dash + 1, ',');
8438 first = decode_reg_name (str);
8441 warning (0, "unknown register name: %s", str);
8445 last = decode_reg_name (dash + 1);
8448 warning (0, "unknown register name: %s", dash + 1);
8456 warning (0, "%s-%s is an empty range", str, dash + 1);
8460 for (i = first; i <= last; ++i)
8461 fixed_regs[i] = call_used_regs[i] = 1;
8471 /* Insert any deferred function attributes from earlier pragmas. */
8473 sh_insert_attributes (tree node, tree *attributes)
8477 if (TREE_CODE (node) != FUNCTION_DECL)
8480 /* We are only interested in fields. */
8484 /* Append the attributes to the deferred attributes. */
8485 *sh_deferred_function_attributes_tail = *attributes;
8486 attrs = sh_deferred_function_attributes;
8490 /* Some attributes imply or require the interrupt attribute. */
8491 if (!lookup_attribute ("interrupt_handler", attrs)
8492 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8494 /* If we have a trapa_handler, but no interrupt_handler attribute,
8495 insert an interrupt_handler attribute. */
8496 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8497 /* We can't use sh_pr_interrupt here because that's not in the
8500 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8501 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8502 if the interrupt attribute is missing, we ignore the attribute
8504 else if (lookup_attribute ("sp_switch", attrs)
8505 || lookup_attribute ("trap_exit", attrs)
8506 || lookup_attribute ("nosave_low_regs", attrs)
8507 || lookup_attribute ("resbank", attrs))
8511 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8513 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8514 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8515 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8516 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8517 warning (OPT_Wattributes,
8518 "%qE attribute only applies to interrupt functions",
8519 TREE_PURPOSE (attrs));
8522 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8524 tail = &TREE_CHAIN (*tail);
8527 attrs = *attributes;
8531 /* Install the processed list. */
8532 *attributes = attrs;
8534 /* Clear deferred attributes. */
8535 sh_deferred_function_attributes = NULL_TREE;
8536 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8541 /* Supported attributes:
8543 interrupt_handler -- specifies this function is an interrupt handler.
8545 trapa_handler - like above, but don't save all registers.
8547 sp_switch -- specifies an alternate stack for an interrupt handler
8550 trap_exit -- use a trapa to exit an interrupt function instead of
8553 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8554 This is useful on the SH3 and upwards,
8555 which has a separate set of low regs for User and Supervisor modes.
8556 This should only be used for the lowest level of interrupts. Higher levels
8557 of interrupts must save the registers in case they themselves are
8560 renesas -- use Renesas calling/layout conventions (functions and
8563 resbank -- In case of an ISR, use a register bank to save registers
8564 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8567 /* Handle a 'resbank' attribute. */
8569 sh_handle_resbank_handler_attribute (tree * node, tree name,
8570 tree args ATTRIBUTE_UNUSED,
8571 int flags ATTRIBUTE_UNUSED,
8572 bool * no_add_attrs)
8576 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8578 *no_add_attrs = true;
8580 if (TREE_CODE (*node) != FUNCTION_DECL)
8582 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8584 *no_add_attrs = true;
8590 /* Handle an "interrupt_handler" attribute; arguments as in
8591 struct attribute_spec.handler. */
8593 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8594 tree args ATTRIBUTE_UNUSED,
8595 int flags ATTRIBUTE_UNUSED,
8598 if (TREE_CODE (*node) != FUNCTION_DECL)
8600 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8602 *no_add_attrs = true;
8604 else if (TARGET_SHCOMPACT)
8606 error ("attribute interrupt_handler is not compatible with -m5-compact");
8607 *no_add_attrs = true;
8613 /* Handle an 'function_vector' attribute; arguments as in
8614 struct attribute_spec.handler. */
8616 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8617 tree args ATTRIBUTE_UNUSED,
8618 int flags ATTRIBUTE_UNUSED,
8619 bool * no_add_attrs)
8623 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8625 *no_add_attrs = true;
8627 else if (TREE_CODE (*node) != FUNCTION_DECL)
8629 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8631 *no_add_attrs = true;
8633 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8635 /* The argument must be a constant integer. */
8636 warning (OPT_Wattributes,
8637 "%qE attribute argument not an integer constant",
8639 *no_add_attrs = true;
8641 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8643 /* The argument value must be between 0 to 255. */
8644 warning (OPT_Wattributes,
8645 "%qE attribute argument should be between 0 to 255",
8647 *no_add_attrs = true;
8652 /* Returns 1 if current function has been assigned the attribute
8653 'function_vector'. */
8655 sh2a_is_function_vector_call (rtx x)
8657 if (GET_CODE (x) == SYMBOL_REF
8658 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8660 tree tr = SYMBOL_REF_DECL (x);
8662 if (sh2a_function_vector_p (tr))
8669 /* Returns the function vector number, if the the attribute
8670 'function_vector' is assigned, otherwise returns zero. */
8672 sh2a_get_function_vector_number (rtx x)
8677 if ((GET_CODE (x) == SYMBOL_REF)
8678 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8680 t = SYMBOL_REF_DECL (x);
8682 if (TREE_CODE (t) != FUNCTION_DECL)
8685 list = SH_ATTRIBUTES (t);
8688 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8690 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8694 list = TREE_CHAIN (list);
8703 /* Handle an "sp_switch" attribute; arguments as in
8704 struct attribute_spec.handler. */
8706 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8707 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8709 if (TREE_CODE (*node) != FUNCTION_DECL)
8711 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8713 *no_add_attrs = true;
8715 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8717 /* The argument must be a constant string. */
8718 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
8720 *no_add_attrs = true;
8726 /* Handle an "trap_exit" attribute; arguments as in
8727 struct attribute_spec.handler. */
8729 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8730 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8732 if (TREE_CODE (*node) != FUNCTION_DECL)
8734 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8736 *no_add_attrs = true;
8738 /* The argument specifies a trap number to be used in a trapa instruction
8739 at function exit (instead of an rte instruction). */
8740 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8742 /* The argument must be a constant integer. */
8743 warning (OPT_Wattributes, "%qE attribute argument not an "
8744 "integer constant", name);
8745 *no_add_attrs = true;
8752 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8753 tree name ATTRIBUTE_UNUSED,
8754 tree args ATTRIBUTE_UNUSED,
8755 int flags ATTRIBUTE_UNUSED,
8756 bool *no_add_attrs ATTRIBUTE_UNUSED)
8761 /* True if __attribute__((renesas)) or -mrenesas. */
8763 sh_attr_renesas_p (const_tree td)
8770 td = TREE_TYPE (td);
8771 if (td == error_mark_node)
8773 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8777 /* True if __attribute__((renesas)) or -mrenesas, for the current
8780 sh_cfun_attr_renesas_p (void)
8782 return sh_attr_renesas_p (current_function_decl);
8786 sh_cfun_interrupt_handler_p (void)
8788 return (lookup_attribute ("interrupt_handler",
8789 DECL_ATTRIBUTES (current_function_decl))
8793 /* Returns 1 if FUNC has been assigned the attribute
8794 "function_vector". */
8796 sh2a_function_vector_p (tree func)
8799 if (TREE_CODE (func) != FUNCTION_DECL)
8802 list = SH_ATTRIBUTES (func);
8805 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8808 list = TREE_CHAIN (list);
8813 /* Returns TRUE if given tree has the "resbank" attribute. */
8816 sh_cfun_resbank_handler_p (void)
8818 return ((lookup_attribute ("resbank",
8819 DECL_ATTRIBUTES (current_function_decl))
8821 && (lookup_attribute ("interrupt_handler",
8822 DECL_ATTRIBUTES (current_function_decl))
8823 != NULL_TREE) && TARGET_SH2A);
8826 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8829 sh_check_pch_target_flags (int old_flags)
8831 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8832 | MASK_SH_E | MASK_HARD_SH4
8833 | MASK_FPU_SINGLE | MASK_SH4))
8834 return _("created and used with different architectures / ABIs");
8835 if ((old_flags ^ target_flags) & MASK_HITACHI)
8836 return _("created and used with different ABIs");
8837 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8838 return _("created and used with different endianness");
8842 /* Predicates used by the templates. */
8844 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8845 Used only in general_movsrc_operand. */
8848 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8860 /* Nonzero if OP is a floating point value with value 0.0. */
8863 fp_zero_operand (rtx op)
8867 if (GET_MODE (op) != SFmode)
8870 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8871 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8874 /* Nonzero if OP is a floating point value with value 1.0. */
8877 fp_one_operand (rtx op)
8881 if (GET_MODE (op) != SFmode)
8884 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8885 return REAL_VALUES_EQUAL (r, dconst1);
8888 /* In general mode switching is used. If we are
8889 compiling without -mfmovd, movsf_ie isn't taken into account for
8890 mode switching. We could check in machine_dependent_reorg for
8891 cases where we know we are in single precision mode, but there is
8892 interface to find that out during reload, so we must avoid
8893 choosing an fldi alternative during reload and thus failing to
8894 allocate a scratch register for the constant loading. */
8902 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8904 enum rtx_code code = GET_CODE (op);
8905 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8908 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8910 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8912 if (GET_CODE (op) != SYMBOL_REF)
8913 return TLS_MODEL_NONE;
8914 return SYMBOL_REF_TLS_MODEL (op);
8917 /* Return the destination address of a branch. */
8920 branch_dest (rtx branch)
8922 rtx dest = SET_SRC (PATTERN (branch));
8925 if (GET_CODE (dest) == IF_THEN_ELSE)
8926 dest = XEXP (dest, 1);
8927 dest = XEXP (dest, 0);
8928 dest_uid = INSN_UID (dest);
8929 return INSN_ADDRESSES (dest_uid);
8932 /* Return nonzero if REG is not used after INSN.
8933 We assume REG is a reload reg, and therefore does
8934 not live past labels. It may live past calls or jumps though. */
8936 reg_unused_after (rtx reg, rtx insn)
8941 /* If the reg is set by this instruction, then it is safe for our
8942 case. Disregard the case where this is a store to memory, since
8943 we are checking a register used in the store address. */
8944 set = single_set (insn);
8945 if (set && !MEM_P (SET_DEST (set))
8946 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8949 while ((insn = NEXT_INSN (insn)))
8955 code = GET_CODE (insn);
8958 /* If this is a label that existed before reload, then the register
8959 if dead here. However, if this is a label added by reorg, then
8960 the register may still be live here. We can't tell the difference,
8961 so we just ignore labels completely. */
8962 if (code == CODE_LABEL)
8967 if (code == JUMP_INSN)
8970 /* If this is a sequence, we must handle them all at once.
8971 We could have for instance a call that sets the target register,
8972 and an insn in a delay slot that uses the register. In this case,
8973 we must return 0. */
8974 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8979 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8981 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
8982 rtx set = single_set (this_insn);
8984 if (CALL_P (this_insn))
8986 else if (JUMP_P (this_insn))
8988 if (INSN_ANNULLED_BRANCH_P (this_insn))
8993 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8995 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8997 if (!MEM_P (SET_DEST (set)))
9003 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
9008 else if (code == JUMP_INSN)
9012 set = single_set (insn);
9013 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9015 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9016 return !MEM_P (SET_DEST (set));
9017 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9020 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
9028 static GTY(()) rtx fpscr_rtx;
9030 get_fpscr_rtx (void)
9034 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
9035 REG_USERVAR_P (fpscr_rtx) = 1;
9036 mark_user_reg (fpscr_rtx);
9038 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
9039 mark_user_reg (fpscr_rtx);
9043 static GTY(()) tree fpscr_values;
9046 emit_fpu_switch (rtx scratch, int index)
9050 if (fpscr_values == NULL)
9054 t = build_index_type (integer_one_node);
9055 t = build_array_type (integer_type_node, t);
9056 t = build_decl (BUILTINS_LOCATION,
9057 VAR_DECL, get_identifier ("__fpscr_values"), t);
9058 DECL_ARTIFICIAL (t) = 1;
9059 DECL_IGNORED_P (t) = 1;
9060 DECL_EXTERNAL (t) = 1;
9061 TREE_STATIC (t) = 1;
9062 TREE_PUBLIC (t) = 1;
9068 src = DECL_RTL (fpscr_values);
9069 if (!can_create_pseudo_p ())
9071 emit_move_insn (scratch, XEXP (src, 0));
9073 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
9074 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
9077 src = adjust_address (src, PSImode, index * 4);
9079 dst = get_fpscr_rtx ();
9080 emit_move_insn (dst, src);
9084 emit_sf_insn (rtx pat)
9090 emit_df_insn (rtx pat)
9096 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9098 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9102 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9104 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
9109 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9111 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9115 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9117 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
9121 static rtx get_free_reg (HARD_REG_SET);
9123 /* This function returns a register to use to load the address to load
9124 the fpscr from. Currently it always returns r1 or r7, but when we are
9125 able to use pseudo registers after combine, or have a better mechanism
9126 for choosing a register, it should be done here. */
9127 /* REGS_LIVE is the liveness information for the point for which we
9128 need this allocation. In some bare-bones exit blocks, r1 is live at the
9129 start. We can even have all of r0..r3 being live:
9130 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9131 INSN before which new insns are placed with will clobber the register
9132 we return. If a basic block consists only of setting the return value
9133 register to a pseudo and using that register, the return value is not
9134 live before or after this block, yet we we'll insert our insns right in
9138 get_free_reg (HARD_REG_SET regs_live)
9140 if (! TEST_HARD_REG_BIT (regs_live, 1))
9141 return gen_rtx_REG (Pmode, 1);
9143 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
9144 there shouldn't be anything but a jump before the function end. */
9145 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
9146 return gen_rtx_REG (Pmode, 7);
9149 /* This function will set the fpscr from memory.
9150 MODE is the mode we are setting it to. */
9152 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
9154 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
9155 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
9158 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
9159 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
9162 /* Is the given character a logical line separator for the assembler? */
9163 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
9164 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9168 sh_insn_length_adjustment (rtx insn)
9170 /* Instructions with unfilled delay slots take up an extra two bytes for
9171 the nop in the delay slot. */
9172 if (((NONJUMP_INSN_P (insn)
9173 && GET_CODE (PATTERN (insn)) != USE
9174 && GET_CODE (PATTERN (insn)) != CLOBBER)
9177 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9178 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
9179 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
9180 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
9183 /* SH2e has a bug that prevents the use of annulled branches, so if
9184 the delay slot is not filled, we'll have to put a NOP in it. */
9185 if (sh_cpu_attr == CPU_SH2E
9187 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9188 && GET_CODE (PATTERN (insn)) != ADDR_VEC
9189 && get_attr_type (insn) == TYPE_CBRANCH
9190 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
9193 /* sh-dsp parallel processing insn take four bytes instead of two. */
9195 if (NONJUMP_INSN_P (insn))
9198 rtx body = PATTERN (insn);
9201 int maybe_label = 1;
9203 if (GET_CODE (body) == ASM_INPUT)
9204 templ = XSTR (body, 0);
9205 else if (asm_noperands (body) >= 0)
9207 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
9216 while (c == ' ' || c == '\t');
9217 /* all sh-dsp parallel-processing insns start with p.
9218 The only non-ppi sh insn starting with p is pref.
9219 The only ppi starting with pr is prnd. */
9220 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
9222 /* The repeat pseudo-insn expands two three insns, a total of
9223 six bytes in size. */
9224 else if ((c == 'r' || c == 'R')
9225 && ! strncasecmp ("epeat", templ, 5))
9227 while (c && c != '\n'
9228 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
9230 /* If this is a label, it is obviously not a ppi insn. */
9231 if (c == ':' && maybe_label)
9236 else if (c == '\'' || c == '"')
9241 maybe_label = c != ':';
9249 /* Return TRUE for a valid displacement for the REG+disp addressing
9252 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
9253 into the FRx registers. We implement this by setting the maximum offset
9254 to zero when the value is SFmode. This also restricts loading of SFmode
9255 values into the integer registers, but that can't be helped. */
9257 /* The SH allows a displacement in a QI or HI amode, but only when the
9258 other operand is R0. GCC doesn't handle this very well, so we forgot
9261 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
9262 DI can be any number 0..60. */
9265 sh_legitimate_index_p (enum machine_mode mode, rtx op)
9267 if (CONST_INT_P (op))
9273 /* Check if this the address of an unaligned load / store. */
9274 if (mode == VOIDmode)
9275 return CONST_OK_FOR_I06 (INTVAL (op));
9277 size = GET_MODE_SIZE (mode);
9278 return (!(INTVAL (op) & (size - 1))
9279 && INTVAL (op) >= -512 * size
9280 && INTVAL (op) < 512 * size);
9285 if (GET_MODE_SIZE (mode) == 1
9286 && (unsigned) INTVAL (op) < 4096)
9290 if ((GET_MODE_SIZE (mode) == 4
9291 && (unsigned) INTVAL (op) < 64
9292 && !(INTVAL (op) & 3)
9293 && !(TARGET_SH2E && mode == SFmode))
9294 || (GET_MODE_SIZE (mode) == 4
9295 && (unsigned) INTVAL (op) < 16383
9296 && !(INTVAL (op) & 3) && TARGET_SH2A))
9299 if ((GET_MODE_SIZE (mode) == 8
9300 && (unsigned) INTVAL (op) < 60
9301 && !(INTVAL (op) & 3)
9302 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9303 || ((GET_MODE_SIZE (mode)==8)
9304 && (unsigned) INTVAL (op) < 8192
9305 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9306 && (TARGET_SH2A && mode == DFmode)))
9313 /* Recognize an RTL expression that is a valid memory address for
9315 The MODE argument is the machine mode for the MEM expression
9316 that wants to use this address.
9324 sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9326 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9328 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9330 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9332 else if (GET_CODE (x) == PLUS
9333 && (mode != PSImode || reload_completed))
9335 rtx xop0 = XEXP (x, 0);
9336 rtx xop1 = XEXP (x, 1);
9338 if (GET_MODE_SIZE (mode) <= 8
9339 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9340 && sh_legitimate_index_p (mode, xop1))
9343 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9344 || ((xop0 == stack_pointer_rtx
9345 || xop0 == hard_frame_pointer_rtx)
9346 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9347 || ((xop1 == stack_pointer_rtx
9348 || xop1 == hard_frame_pointer_rtx)
9349 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9350 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9351 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9352 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9353 && TARGET_FMOVD && mode == DFmode)))
9355 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9356 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9358 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9359 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9367 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9368 isn't protected by a PIC unspec. */
9370 nonpic_symbol_mentioned_p (rtx x)
9372 register const char *fmt;
9375 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9376 || GET_CODE (x) == PC)
9379 /* We don't want to look into the possible MEM location of a
9380 CONST_DOUBLE, since we're not going to use it, in general. */
9381 if (GET_CODE (x) == CONST_DOUBLE)
9384 if (GET_CODE (x) == UNSPEC
9385 && (XINT (x, 1) == UNSPEC_PIC
9386 || XINT (x, 1) == UNSPEC_GOT
9387 || XINT (x, 1) == UNSPEC_GOTOFF
9388 || XINT (x, 1) == UNSPEC_GOTPLT
9389 || XINT (x, 1) == UNSPEC_GOTTPOFF
9390 || XINT (x, 1) == UNSPEC_DTPOFF
9391 || XINT (x, 1) == UNSPEC_PLT
9392 || XINT (x, 1) == UNSPEC_SYMOFF
9393 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
9396 fmt = GET_RTX_FORMAT (GET_CODE (x));
9397 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9403 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9404 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9407 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9414 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9415 @GOTOFF in `reg'. */
9417 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9420 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9423 if (GET_CODE (orig) == LABEL_REF
9424 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9427 reg = gen_reg_rtx (Pmode);
9429 emit_insn (gen_symGOTOFF2reg (reg, orig));
9432 else if (GET_CODE (orig) == SYMBOL_REF)
9435 reg = gen_reg_rtx (Pmode);
9437 emit_insn (gen_symGOT2reg (reg, orig));
9443 /* Try machine-dependent ways of modifying an illegitimate address
9444 to be legitimate. If we find one, return the new, valid address.
9445 Otherwise, return X.
9447 For the SH, if X is almost suitable for indexing, but the offset is
9448 out of range, convert it into a normal form so that CSE has a chance
9449 of reducing the number of address registers used. */
9452 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9455 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9457 if (GET_CODE (x) == PLUS
9458 && (GET_MODE_SIZE (mode) == 4
9459 || GET_MODE_SIZE (mode) == 8)
9460 && CONST_INT_P (XEXP (x, 1))
9461 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9463 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9464 && ! (TARGET_SH2E && mode == SFmode))
9466 rtx index_rtx = XEXP (x, 1);
9467 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9470 /* On rare occasions, we might get an unaligned pointer
9471 that is indexed in a way to give an aligned address.
9472 Therefore, keep the lower two bits in offset_base. */
9473 /* Instead of offset_base 128..131 use 124..127, so that
9474 simple add suffices. */
9476 offset_base = ((offset + 4) & ~60) - 4;
9478 offset_base = offset & ~60;
9480 /* Sometimes the normal form does not suit DImode. We
9481 could avoid that by using smaller ranges, but that
9482 would give less optimized code when SImode is
9484 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9486 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9487 GEN_INT (offset_base), NULL_RTX, 0,
9490 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9497 /* Mark the use of a constant in the literal table. If the constant
9498 has multiple labels, make it unique. */
9500 mark_constant_pool_use (rtx x)
9502 rtx insn, lab, pattern;
9507 switch (GET_CODE (x))
9517 /* Get the first label in the list of labels for the same constant
9518 and delete another labels in the list. */
9520 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
9523 || LABEL_REFS (insn) != NEXT_INSN (insn))
9528 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9529 INSN_DELETED_P (insn) = 1;
9531 /* Mark constants in a window. */
9532 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
9534 if (!NONJUMP_INSN_P (insn))
9537 pattern = PATTERN (insn);
9538 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9541 switch (XINT (pattern, 1))
9543 case UNSPECV_CONST2:
9544 case UNSPECV_CONST4:
9545 case UNSPECV_CONST8:
9546 XVECEXP (pattern, 0, 1) = const1_rtx;
9548 case UNSPECV_WINDOW_END:
9549 if (XVECEXP (pattern, 0, 0) == x)
9552 case UNSPECV_CONST_END:
9562 /* Return true if it's possible to redirect BRANCH1 to the destination
9563 of an unconditional jump BRANCH2. We only want to do this if the
9564 resulting branch will have a short displacement. */
9566 sh_can_redirect_branch (rtx branch1, rtx branch2)
9568 if (flag_expensive_optimizations && simplejump_p (branch2))
9570 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
9574 for (distance = 0, insn = NEXT_INSN (branch1);
9575 insn && distance < 256;
9576 insn = PREV_INSN (insn))
9581 distance += get_attr_length (insn);
9583 for (distance = 0, insn = NEXT_INSN (branch1);
9584 insn && distance < 256;
9585 insn = NEXT_INSN (insn))
9590 distance += get_attr_length (insn);
9596 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9598 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9599 unsigned int new_reg)
9601 /* Interrupt functions can only use registers that have already been
9602 saved by the prologue, even if they would normally be
9605 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
9611 /* Function to update the integer COST
9612 based on the relationship between INSN that is dependent on
9613 DEP_INSN through the dependence LINK. The default is to make no
9614 adjustment to COST. This can be used for example to specify to
9615 the scheduler that an output- or anti-dependence does not incur
9616 the same cost as a data-dependence. The return value should be
9617 the new value for COST. */
9619 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
9625 /* On SHmedia, if the dependence is an anti-dependence or
9626 output-dependence, there is no cost. */
9627 if (REG_NOTE_KIND (link) != 0)
9629 /* However, dependencies between target register loads and
9630 uses of the register in a subsequent block that are separated
9631 by a conditional branch are not modelled - we have to do with
9632 the anti-dependency between the target register load and the
9633 conditional branch that ends the current block. */
9634 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9635 && GET_CODE (PATTERN (dep_insn)) == SET
9636 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
9637 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
9638 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
9640 int orig_cost = cost;
9641 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
9642 rtx target = ((! note
9643 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
9644 ? insn : JUMP_LABEL (insn));
9645 /* On the likely path, the branch costs 1, on the unlikely path,
9649 target = next_active_insn (target);
9650 while (target && ! flow_dependent_p (target, dep_insn)
9652 /* If two branches are executed in immediate succession, with the
9653 first branch properly predicted, this causes a stall at the
9654 second branch, hence we won't need the target for the
9655 second branch for two cycles after the launch of the first
9657 if (cost > orig_cost - 2)
9658 cost = orig_cost - 2;
9664 else if (get_attr_is_mac_media (insn)
9665 && get_attr_is_mac_media (dep_insn))
9668 else if (! reload_completed
9669 && GET_CODE (PATTERN (insn)) == SET
9670 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9671 && GET_CODE (PATTERN (dep_insn)) == SET
9672 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9675 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9676 that is needed at the target. */
9677 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9678 && ! flow_dependent_p (insn, dep_insn))
9681 else if (REG_NOTE_KIND (link) == 0)
9683 enum attr_type type;
9686 if (recog_memoized (insn) < 0
9687 || recog_memoized (dep_insn) < 0)
9690 dep_set = single_set (dep_insn);
9692 /* The latency that we specify in the scheduling description refers
9693 to the actual output, not to an auto-increment register; for that,
9694 the latency is one. */
9695 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9697 rtx set = single_set (insn);
9700 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9701 && (!MEM_P (SET_DEST (set))
9702 || !reg_mentioned_p (SET_DEST (dep_set),
9703 XEXP (SET_DEST (set), 0))))
9706 /* The only input for a call that is timing-critical is the
9707 function's address. */
9710 rtx call = PATTERN (insn);
9712 if (GET_CODE (call) == PARALLEL)
9713 call = XVECEXP (call, 0 ,0);
9714 if (GET_CODE (call) == SET)
9715 call = SET_SRC (call);
9716 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
9717 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9718 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9719 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9720 cost -= TARGET_SH4_300 ? 3 : 6;
9722 /* Likewise, the most timing critical input for an sfuncs call
9723 is the function address. However, sfuncs typically start
9724 using their arguments pretty quickly.
9725 Assume a four cycle delay for SH4 before they are needed.
9726 Cached ST40-300 calls are quicker, so assume only a one
9728 ??? Maybe we should encode the delays till input registers
9729 are needed by sfuncs into the sfunc call insn. */
9730 /* All sfunc calls are parallels with at least four components.
9731 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9732 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9733 && XVECLEN (PATTERN (insn), 0) >= 4
9734 && (reg = sfunc_uses_reg (insn)))
9736 if (! reg_set_p (reg, dep_insn))
9737 cost -= TARGET_SH4_300 ? 1 : 4;
9739 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9741 enum attr_type dep_type = get_attr_type (dep_insn);
9743 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9745 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9746 && (type = get_attr_type (insn)) != TYPE_CALL
9747 && type != TYPE_SFUNC)
9749 /* When the preceding instruction loads the shift amount of
9750 the following SHAD/SHLD, the latency of the load is increased
9752 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9753 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9754 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9755 XEXP (SET_SRC (single_set (insn)),
9758 /* When an LS group instruction with a latency of less than
9759 3 cycles is followed by a double-precision floating-point
9760 instruction, FIPR, or FTRV, the latency of the first
9761 instruction is increased to 3 cycles. */
9763 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9764 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9766 /* The lsw register of a double-precision computation is ready one
9768 else if (reload_completed
9769 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9770 && (use_pat = single_set (insn))
9771 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9775 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9776 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9779 else if (TARGET_SH4_300)
9781 /* Stores need their input register two cycles later. */
9782 if (dep_set && cost >= 1
9783 && ((type = get_attr_type (insn)) == TYPE_STORE
9784 || type == TYPE_PSTORE
9785 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9787 rtx set = single_set (insn);
9789 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9790 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9793 /* But don't reduce the cost below 1 if the address depends
9794 on a side effect of dep_insn. */
9796 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9802 /* An anti-dependence penalty of two applies if the first insn is a double
9803 precision fadd / fsub / fmul. */
9804 else if (!TARGET_SH4_300
9805 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9806 && recog_memoized (dep_insn) >= 0
9807 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9808 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9809 /* A lot of alleged anti-flow dependences are fake,
9810 so check this one is real. */
9811 && flow_dependent_p (dep_insn, insn))
9817 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9818 if DEP_INSN is anti-flow dependent on INSN. */
9820 flow_dependent_p (rtx insn, rtx dep_insn)
9822 rtx tmp = PATTERN (insn);
9824 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9825 return tmp == NULL_RTX;
9828 /* A helper function for flow_dependent_p called through note_stores. */
9830 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9832 rtx * pinsn = (rtx *) data;
9834 if (*pinsn && reg_referenced_p (x, *pinsn))
9838 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9839 'special function' patterns (type sfunc) that clobber pr, but that
9840 do not look like function calls to leaf_function_p. Hence we must
9841 do this extra check. */
9845 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9848 /* Return where to allocate pseudo for a given hard register initial
9851 sh_allocate_initial_value (rtx hard_reg)
9855 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9857 if (current_function_is_leaf
9858 && ! sh_pr_n_sets ()
9859 && ! (TARGET_SHCOMPACT
9860 && ((crtl->args.info.call_cookie
9861 & ~ CALL_COOKIE_RET_TRAMP (1))
9862 || crtl->saves_all_registers)))
9865 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9873 /* This function returns "2" to indicate dual issue for the SH4
9874 processor. To be used by the DFA pipeline description. */
9876 sh_issue_rate (void)
9878 if (TARGET_SUPERSCALAR)
9884 /* Functions for ready queue reordering for sched1. */
9886 /* Get weight for mode for a set x. */
9888 find_set_regmode_weight (rtx x, enum machine_mode mode)
9890 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9892 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9894 if (REG_P (SET_DEST (x)))
9896 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9906 /* Get regmode weight for insn. */
9908 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9910 short reg_weight = 0;
9913 /* Increment weight for each register born here. */
9915 reg_weight += find_set_regmode_weight (x, mode);
9916 if (GET_CODE (x) == PARALLEL)
9919 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9921 x = XVECEXP (PATTERN (insn), 0, j);
9922 reg_weight += find_set_regmode_weight (x, mode);
9925 /* Decrement weight for each register that dies here. */
9926 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9928 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9930 rtx note = XEXP (x, 0);
9931 if (REG_P (note) && GET_MODE (note) == mode)
9938 /* Calculate regmode weights for all insns of a basic block. */
9940 find_regmode_weight (basic_block b, enum machine_mode mode)
9942 rtx insn, next_tail, head, tail;
9944 get_ebb_head_tail (b, b, &head, &tail);
9945 next_tail = NEXT_INSN (tail);
9947 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9949 /* Handle register life information. */
9954 INSN_REGMODE_WEIGHT (insn, mode) =
9955 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9956 else if (mode == SImode)
9957 INSN_REGMODE_WEIGHT (insn, mode) =
9958 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9962 /* Comparison function for ready queue sorting. */
9964 rank_for_reorder (const void *x, const void *y)
9966 rtx tmp = *(const rtx *) y;
9967 rtx tmp2 = *(const rtx *) x;
9969 /* The insn in a schedule group should be issued the first. */
9970 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9971 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9973 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9974 minimizes instruction movement, thus minimizing sched's effect on
9975 register pressure. */
9976 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9979 /* Resort the array A in which only element at index N may be out of order. */
9981 swap_reorder (rtx *a, int n)
9983 rtx insn = a[n - 1];
9986 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9994 #define SCHED_REORDER(READY, N_READY) \
9997 if ((N_READY) == 2) \
9998 swap_reorder (READY, N_READY); \
9999 else if ((N_READY) > 2) \
10000 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
10004 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
10007 ready_reorder (rtx *ready, int nready)
10009 SCHED_REORDER (ready, nready);
10012 /* Count life regions of r0 for a block. */
10014 find_r0_life_regions (basic_block b)
10023 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
10034 insn = BB_HEAD (b);
10036 r0_reg = gen_rtx_REG (SImode, R0_REG);
10041 if (find_regno_note (insn, REG_DEAD, R0_REG))
10047 && (pset = single_set (insn))
10048 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
10049 && !find_regno_note (insn, REG_UNUSED, R0_REG))
10057 insn = NEXT_INSN (insn);
10059 return set - death;
10062 /* Calculate regmode weights for all insns of all basic block. */
10064 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
10065 int verbose ATTRIBUTE_UNUSED,
10070 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
10071 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
10072 r0_life_regions = 0;
10074 FOR_EACH_BB_REVERSE (b)
10076 find_regmode_weight (b, SImode);
10077 find_regmode_weight (b, SFmode);
10078 if (!reload_completed)
10079 r0_life_regions += find_r0_life_regions (b);
10082 CURR_REGMODE_PRESSURE (SImode) = 0;
10083 CURR_REGMODE_PRESSURE (SFmode) = 0;
10089 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
10090 int verbose ATTRIBUTE_UNUSED)
10092 if (regmode_weight[0])
10094 free (regmode_weight[0]);
10095 regmode_weight[0] = NULL;
10097 if (regmode_weight[1])
10099 free (regmode_weight[1]);
10100 regmode_weight[1] = NULL;
10104 /* The scalar modes supported differs from the default version in TImode
10105 for 32-bit SHMEDIA. */
10107 sh_scalar_mode_supported_p (enum machine_mode mode)
10109 if (TARGET_SHMEDIA32 && mode == TImode)
10112 return default_scalar_mode_supported_p (mode);
10115 /* Cache the can_issue_more so that we can return it from reorder2. Also,
10116 keep count of register pressures on SImode and SFmode. */
10118 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
10119 int sched_verbose ATTRIBUTE_UNUSED,
10121 int can_issue_more)
10123 if (GET_CODE (PATTERN (insn)) != USE
10124 && GET_CODE (PATTERN (insn)) != CLOBBER)
10125 cached_can_issue_more = can_issue_more - 1;
10127 cached_can_issue_more = can_issue_more;
10129 if (reload_completed)
10130 return cached_can_issue_more;
10132 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
10133 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
10135 return cached_can_issue_more;
10139 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
10140 int verbose ATTRIBUTE_UNUSED,
10141 int veclen ATTRIBUTE_UNUSED)
10143 CURR_REGMODE_PRESSURE (SImode) = 0;
10144 CURR_REGMODE_PRESSURE (SFmode) = 0;
10147 /* Some magic numbers. */
10148 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10149 functions that already have high pressure on r0. */
10150 #define R0_MAX_LIFE_REGIONS 2
10151 /* Register Pressure thresholds for SImode and SFmode registers. */
10152 #define SIMODE_MAX_WEIGHT 5
10153 #define SFMODE_MAX_WEIGHT 10
10155 /* Return true if the pressure is high for MODE. */
10157 high_pressure (enum machine_mode mode)
10159 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10160 functions that already have high pressure on r0. */
10161 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
10164 if (mode == SFmode)
10165 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
10167 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
10170 /* Reorder ready queue if register pressure is high. */
10172 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
10173 int sched_verbose ATTRIBUTE_UNUSED,
10176 int clock_var ATTRIBUTE_UNUSED)
10178 if (reload_completed)
10179 return sh_issue_rate ();
10181 if (high_pressure (SFmode) || high_pressure (SImode))
10183 ready_reorder (ready, *n_readyp);
10186 return sh_issue_rate ();
10189 /* Skip cycles if the current register pressure is high. */
10191 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
10192 int sched_verbose ATTRIBUTE_UNUSED,
10193 rtx *ready ATTRIBUTE_UNUSED,
10194 int *n_readyp ATTRIBUTE_UNUSED,
10195 int clock_var ATTRIBUTE_UNUSED)
10197 if (reload_completed)
10198 return cached_can_issue_more;
10200 if (high_pressure(SFmode) || high_pressure (SImode))
10203 return cached_can_issue_more;
10206 /* Skip cycles without sorting the ready queue. This will move insn from
10207 Q->R. If this is the last cycle we are skipping; allow sorting of ready
10208 queue by sh_reorder. */
10210 /* Generally, skipping these many cycles are sufficient for all insns to move
10212 #define MAX_SKIPS 8
10215 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10216 int sched_verbose ATTRIBUTE_UNUSED,
10217 rtx insn ATTRIBUTE_UNUSED,
10218 int last_clock_var,
10222 if (reload_completed)
10227 if ((clock_var - last_clock_var) < MAX_SKIPS)
10232 /* If this is the last cycle we are skipping, allow reordering of R. */
10233 if ((clock_var - last_clock_var) == MAX_SKIPS)
10245 /* SHmedia requires registers for branches, so we can't generate new
10246 branches past reload. */
10248 sh_cannot_modify_jumps_p (void)
10250 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
10253 static enum reg_class
10254 sh_target_reg_class (void)
10256 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
10260 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
10262 HARD_REG_SET dummy;
10267 if (! shmedia_space_reserved_for_target_registers)
10269 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
10271 if (calc_live_regs (&dummy) >= 6 * 8)
10277 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
10279 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
10283 On the SH1..SH4, the trampoline looks like
10284 2 0002 D202 mov.l l2,r2
10285 1 0000 D301 mov.l l1,r3
10286 3 0004 422B jmp @r2
10288 5 0008 00000000 l1: .long area
10289 6 000c 00000000 l2: .long function
10291 SH5 (compact) uses r1 instead of r3 for the static chain. */
10294 /* Emit RTL insns to initialize the variable parts of a trampoline.
10295 FNADDR is an RTX for the address of the function's pure code.
10296 CXT is an RTX for the static chain value for the function. */
10299 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
10301 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
10303 if (TARGET_SHMEDIA64)
10308 rtx movi1 = GEN_INT (0xcc000010);
10309 rtx shori1 = GEN_INT (0xc8000010);
10312 /* The following trampoline works within a +- 128 KB range for cxt:
10313 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10314 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10315 gettr tr1,r1; blink tr0,r63 */
10316 /* Address rounding makes it hard to compute the exact bounds of the
10317 offset for this trampoline, but we have a rather generous offset
10318 range, so frame_offset should do fine as an upper bound. */
10319 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10321 /* ??? could optimize this trampoline initialization
10322 by writing DImode words with two insns each. */
10323 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10324 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10325 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10326 insn = gen_rtx_AND (DImode, insn, mask);
10327 /* Or in ptb/u .,tr1 pattern */
10328 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10329 insn = force_operand (insn, NULL_RTX);
10330 insn = gen_lowpart (SImode, insn);
10331 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
10332 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10333 insn = gen_rtx_AND (DImode, insn, mask);
10334 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10335 insn = gen_lowpart (SImode, insn);
10336 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
10337 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10338 insn = gen_rtx_AND (DImode, insn, mask);
10339 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10340 insn = gen_lowpart (SImode, insn);
10341 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
10342 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10343 insn = gen_rtx_AND (DImode, insn, mask);
10344 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10345 insn = gen_lowpart (SImode, insn);
10346 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
10347 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10348 insn = gen_rtx_AND (DImode, insn, mask);
10349 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10350 insn = gen_lowpart (SImode, insn);
10351 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10352 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
10353 GEN_INT (0x6bf10600));
10354 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
10355 GEN_INT (0x4415fc10));
10356 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
10357 GEN_INT (0x4401fff0));
10358 emit_insn (gen_ic_invalidate_line (tramp));
10361 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10362 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10364 tramp_templ = gen_datalabel_ref (tramp_templ);
10366 src = gen_const_mem (BLKmode, tramp_templ);
10367 set_mem_align (dst, 256);
10368 set_mem_align (src, 64);
10369 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
10371 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10372 emit_move_insn (adjust_address (tramp_mem, Pmode,
10373 fixed_len + GET_MODE_SIZE (Pmode)),
10375 emit_insn (gen_ic_invalidate_line (tramp));
10378 else if (TARGET_SHMEDIA)
10380 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10381 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10382 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10383 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10384 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10385 rotated 10 right, and higher 16 bit of every 32 selected. */
10387 = force_reg (V2HImode, (simplify_gen_subreg
10388 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10389 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10390 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10392 tramp = force_reg (Pmode, tramp);
10393 fnaddr = force_reg (SImode, fnaddr);
10394 cxt = force_reg (SImode, cxt);
10395 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10396 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10398 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
10399 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10400 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
10401 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
10402 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10403 gen_rtx_SUBREG (V2HImode, cxt, 0),
10405 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
10406 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10407 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
10408 if (TARGET_LITTLE_ENDIAN)
10410 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10411 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10415 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10416 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10418 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10419 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
10420 emit_insn (gen_ic_invalidate_line (tramp));
10423 else if (TARGET_SHCOMPACT)
10425 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10428 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
10429 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10431 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
10432 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10434 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10435 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
10436 if (TARGET_HARVARD)
10438 if (!TARGET_INLINE_IC_INVALIDATE
10439 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
10440 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10441 FUNCTION_ORDINARY),
10442 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
10444 emit_insn (gen_ic_invalidate_line (tramp));
10448 /* FIXME: This is overly conservative. A SHcompact function that
10449 receives arguments ``by reference'' will have them stored in its
10450 own stack frame, so it must not pass pointers or references to
10451 these arguments to other functions by means of sibling calls. */
10452 /* If PIC, we cannot make sibling calls to global functions
10453 because the PLT requires r12 to be live. */
10455 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10458 && (! TARGET_SHCOMPACT
10459 || crtl->args.info.stack_regs == 0)
10460 && ! sh_cfun_interrupt_handler_p ()
10462 || (decl && ! TREE_PUBLIC (decl))
10463 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10466 /* Machine specific built-in functions. */
10468 struct builtin_description
10470 const enum insn_code icode;
10471 const char *const name;
10475 /* describe number and signedness of arguments; arg[0] == result
10476 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10477 /* 9: 64-bit pointer, 10: 32-bit pointer */
10478 static const char signature_args[][4] =
10480 #define SH_BLTIN_V2SI2 0
10482 #define SH_BLTIN_V4HI2 1
10484 #define SH_BLTIN_V2SI3 2
10486 #define SH_BLTIN_V4HI3 3
10488 #define SH_BLTIN_V8QI3 4
10490 #define SH_BLTIN_MAC_HISI 5
10492 #define SH_BLTIN_SH_HI 6
10494 #define SH_BLTIN_SH_SI 7
10496 #define SH_BLTIN_V4HI2V2SI 8
10498 #define SH_BLTIN_V4HI2V8QI 9
10500 #define SH_BLTIN_SISF 10
10502 #define SH_BLTIN_LDUA_L 11
10504 #define SH_BLTIN_LDUA_Q 12
10506 #define SH_BLTIN_STUA_L 13
10508 #define SH_BLTIN_STUA_Q 14
10510 #define SH_BLTIN_LDUA_L64 15
10512 #define SH_BLTIN_LDUA_Q64 16
10514 #define SH_BLTIN_STUA_L64 17
10516 #define SH_BLTIN_STUA_Q64 18
10518 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10519 #define SH_BLTIN_2 19
10520 #define SH_BLTIN_SU 19
10522 #define SH_BLTIN_3 20
10523 #define SH_BLTIN_SUS 20
10525 #define SH_BLTIN_PSSV 21
10527 #define SH_BLTIN_XXUU 22
10528 #define SH_BLTIN_UUUU 22
10530 #define SH_BLTIN_PV 23
10533 /* mcmv: operands considered unsigned. */
10534 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10535 /* mperm: control value considered unsigned int. */
10536 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10537 /* mshards_q: returns signed short. */
10538 /* nsb: takes long long arg, returns unsigned char. */
10539 static const struct builtin_description bdesc[] =
10541 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
10542 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
10543 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
10544 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
10545 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
10546 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
10547 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
10548 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
10549 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
10550 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
10551 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
10552 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
10553 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
10554 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
10555 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
10556 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
10557 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
10558 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
10559 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
10560 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
10561 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
10562 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
10563 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
10564 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
10565 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
10566 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
10567 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
10568 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
10569 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
10570 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
10571 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
10572 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
10573 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
10574 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
10575 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
10576 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
10577 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
10578 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
10579 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
10580 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
10581 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
10582 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
10583 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
10584 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
10585 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
10586 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
10587 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
10588 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
10589 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
10590 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
10591 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
10592 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
10593 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
10594 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
10595 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
10596 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
10597 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
10598 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
10599 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
10600 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
10601 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
10602 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
10603 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
10604 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
10605 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
10606 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
10607 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
10608 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
10609 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
10610 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
10611 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
10612 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
10613 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
10614 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
10615 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
10616 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
10617 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
10618 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
10619 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
10620 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
10621 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
10622 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
10623 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
10624 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
10628 sh_media_init_builtins (void)
10630 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10631 const struct builtin_description *d;
10633 memset (shared, 0, sizeof shared);
10634 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
10636 tree type, arg_type = 0;
10637 int signature = d->signature;
10640 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10641 type = shared[signature];
10644 int has_result = signature_args[signature][0] != 0;
10646 if ((signature_args[signature][1] & 8)
10647 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
10648 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
10650 if (! TARGET_FPU_ANY
10651 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10653 type = void_list_node;
10656 int arg = signature_args[signature][i];
10657 int opno = i - 1 + has_result;
10660 arg_type = ptr_type_node;
10662 arg_type = (*lang_hooks.types.type_for_mode)
10663 (insn_data[d->icode].operand[opno].mode,
10668 arg_type = void_type_node;
10671 type = tree_cons (NULL_TREE, arg_type, type);
10673 type = build_function_type (arg_type, type);
10674 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10675 shared[signature] = type;
10677 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10682 /* Implements target hook vector_mode_supported_p. */
10684 sh_vector_mode_supported_p (enum machine_mode mode)
10687 && ((mode == V2SFmode)
10688 || (mode == V4SFmode)
10689 || (mode == V16SFmode)))
10692 else if (TARGET_SHMEDIA
10693 && ((mode == V8QImode)
10694 || (mode == V2HImode)
10695 || (mode == V4HImode)
10696 || (mode == V2SImode)))
10702 /* Implements target hook dwarf_calling_convention. Return an enum
10703 of dwarf_calling_convention. */
10705 sh_dwarf_calling_convention (const_tree func)
10707 if (sh_attr_renesas_p (func))
10708 return DW_CC_GNU_renesas_sh;
10710 return DW_CC_normal;
10714 sh_init_builtins (void)
10716 if (TARGET_SHMEDIA)
10717 sh_media_init_builtins ();
10720 /* Expand an expression EXP that calls a built-in function,
10721 with result going to TARGET if that's convenient
10722 (and in mode MODE if that's convenient).
10723 SUBTARGET may be used as the target for computing one of EXP's operands.
10724 IGNORE is nonzero if the value is to be ignored. */
10727 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10728 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10730 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10731 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10732 const struct builtin_description *d = &bdesc[fcode];
10733 enum insn_code icode = d->icode;
10734 int signature = d->signature;
10735 enum machine_mode tmode = VOIDmode;
10740 if (signature_args[signature][0])
10745 tmode = insn_data[icode].operand[0].mode;
10747 || GET_MODE (target) != tmode
10748 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10749 target = gen_reg_rtx (tmode);
10750 op[nop++] = target;
10755 for (i = 1; i <= 3; i++, nop++)
10758 enum machine_mode opmode, argmode;
10761 if (! signature_args[signature][i])
10763 arg = CALL_EXPR_ARG (exp, i - 1);
10764 if (arg == error_mark_node)
10766 if (signature_args[signature][i] & 8)
10769 optype = ptr_type_node;
10773 opmode = insn_data[icode].operand[nop].mode;
10774 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10776 argmode = TYPE_MODE (TREE_TYPE (arg));
10777 if (argmode != opmode)
10778 arg = build1 (NOP_EXPR, optype, arg);
10779 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
10780 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10781 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10787 pat = (*insn_data[d->icode].genfun) (op[0]);
10790 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10793 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10796 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10799 gcc_unreachable ();
10808 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
10810 rtx sel0 = const0_rtx;
10811 rtx sel1 = const1_rtx;
10812 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
10813 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10815 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10816 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10820 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
10822 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10824 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10825 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
10828 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
10829 We can allow any mode in any general register. The special registers
10830 only allow SImode. Don't allow any mode in the PR.
10832 We cannot hold DCmode values in the XD registers because alter_reg
10833 handles subregs of them incorrectly. We could work around this by
10834 spacing the XD registers like the DR registers, but this would require
10835 additional memory in every compilation to hold larger register vectors.
10836 We could hold SFmode / SCmode values in XD registers, but that
10837 would require a tertiary reload when reloading from / to memory,
10838 and a secondary reload to reload from / to general regs; that
10839 seems to be a loosing proposition.
10841 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10842 it won't be ferried through GP registers first. */
10845 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10847 if (SPECIAL_REGISTER_P (regno))
10848 return mode == SImode;
10850 if (regno == FPUL_REG)
10851 return (mode == SImode || mode == SFmode);
10853 if (FP_REGISTER_P (regno) && mode == SFmode)
10856 if (mode == V2SFmode)
10858 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
10859 || GENERAL_REGISTER_P (regno)))
10865 if (mode == V4SFmode)
10867 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
10868 || GENERAL_REGISTER_P (regno))
10874 if (mode == V16SFmode)
10876 if (TARGET_SHMEDIA)
10878 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
10884 return regno == FIRST_XD_REG;
10887 if (FP_REGISTER_P (regno))
10891 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
10892 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
10895 && (mode == DFmode || mode == DImode
10896 || mode == V2SFmode || mode == TImode)))
10897 && ((regno - FIRST_FP_REG) & 1) == 0)
10898 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
10899 && ((regno - FIRST_FP_REG) & 3) == 0))
10905 if (XD_REGISTER_P (regno))
10906 return mode == DFmode;
10908 if (TARGET_REGISTER_P (regno))
10909 return (mode == DImode || mode == SImode || mode == PDImode);
10911 if (regno == PR_REG)
10912 return mode == SImode;
10914 if (regno == FPSCR_REG)
10915 return mode == PSImode;
10917 /* FIXME. This works around PR target/37633 for -O0. */
10918 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
10920 unsigned int n = GET_MODE_SIZE (mode) / 8;
10922 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
10923 && regno <= FIRST_GENERAL_REG + 14)
10930 /* Return the class of registers for which a mode change from FROM to TO
10933 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
10934 enum reg_class rclass)
10936 /* We want to enable the use of SUBREGs as a means to
10937 VEC_SELECT a single element of a vector. */
10938 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10939 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
10941 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10943 if (TARGET_LITTLE_ENDIAN)
10945 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10946 return reg_classes_intersect_p (DF_REGS, rclass);
10950 if (GET_MODE_SIZE (from) < 8)
10951 return reg_classes_intersect_p (DF_HI_REGS, rclass);
10958 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10959 that label is used. */
10962 sh_mark_label (rtx address, int nuses)
10964 if (GOTOFF_P (address))
10966 /* Extract the label or symbol. */
10967 address = XEXP (address, 0);
10968 if (GET_CODE (address) == PLUS)
10969 address = XEXP (address, 0);
10970 address = XVECEXP (address, 0, 0);
10972 if (GET_CODE (address) == LABEL_REF
10973 && LABEL_P (XEXP (address, 0)))
10974 LABEL_NUSES (XEXP (address, 0)) += nuses;
10977 /* Compute extra cost of moving data between one register class
10980 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10981 uses this information. Hence, the general register <-> floating point
10982 register information here is not used for SFmode. */
10985 sh_register_move_cost (enum machine_mode mode,
10986 enum reg_class srcclass, enum reg_class dstclass)
10988 if (dstclass == T_REGS || dstclass == PR_REGS)
10991 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10994 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
10995 && REGCLASS_HAS_FP_REG (srcclass)
10996 && REGCLASS_HAS_FP_REG (dstclass))
10999 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
11000 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
11002 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
11003 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
11006 if ((REGCLASS_HAS_FP_REG (dstclass)
11007 && REGCLASS_HAS_GENERAL_REG (srcclass))
11008 || (REGCLASS_HAS_GENERAL_REG (dstclass)
11009 && REGCLASS_HAS_FP_REG (srcclass)))
11010 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
11011 * ((GET_MODE_SIZE (mode) + 7) / 8U));
11013 if ((dstclass == FPUL_REGS
11014 && REGCLASS_HAS_GENERAL_REG (srcclass))
11015 || (srcclass == FPUL_REGS
11016 && REGCLASS_HAS_GENERAL_REG (dstclass)))
11019 if ((dstclass == FPUL_REGS
11020 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
11021 || (srcclass == FPUL_REGS
11022 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
11025 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11026 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11029 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11031 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
11033 if (sh_gettrcost >= 0)
11034 return sh_gettrcost;
11035 else if (!TARGET_PT_FIXED)
11039 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11040 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11045 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
11046 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
11047 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
11049 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
11052 static rtx emit_load_ptr (rtx, rtx);
11055 emit_load_ptr (rtx reg, rtx addr)
11057 rtx mem = gen_const_mem (ptr_mode, addr);
11059 if (Pmode != ptr_mode)
11060 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
11061 return emit_move_insn (reg, mem);
11065 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11066 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11069 CUMULATIVE_ARGS cum;
11070 int structure_value_byref = 0;
11071 rtx this_rtx, this_value, sibcall, insns, funexp;
11072 tree funtype = TREE_TYPE (function);
11073 int simple_add = CONST_OK_FOR_ADD (delta);
11075 rtx scratch0, scratch1, scratch2;
11078 reload_completed = 1;
11079 epilogue_completed = 1;
11080 current_function_uses_only_leaf_regs = 1;
11082 emit_note (NOTE_INSN_PROLOGUE_END);
11084 /* Find the "this" pointer. We have such a wide range of ABIs for the
11085 SH that it's best to do this completely machine independently.
11086 "this" is passed as first argument, unless a structure return pointer
11087 comes first, in which case "this" comes second. */
11088 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
11089 #ifndef PCC_STATIC_STRUCT_RETURN
11090 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11091 structure_value_byref = 1;
11092 #endif /* not PCC_STATIC_STRUCT_RETURN */
11093 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
11095 tree ptype = build_pointer_type (TREE_TYPE (funtype));
11097 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
11099 this_rtx = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
11101 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11102 static chain pointer (even if you can't have nested virtual functions
11103 right now, someone might implement them sometime), and the rest of the
11104 registers are used for argument passing, are callee-saved, or reserved. */
11105 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11106 -ffixed-reg has been used. */
11107 if (! call_used_regs[0] || fixed_regs[0])
11108 error ("r0 needs to be available as a call-clobbered register");
11109 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
11112 if (call_used_regs[1] && ! fixed_regs[1])
11113 scratch1 = gen_rtx_REG (ptr_mode, 1);
11114 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11115 pointing where to return struct values. */
11116 if (call_used_regs[3] && ! fixed_regs[3])
11117 scratch2 = gen_rtx_REG (Pmode, 3);
11119 else if (TARGET_SHMEDIA)
11121 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
11122 if (i != REGNO (scratch0) &&
11123 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
11125 scratch1 = gen_rtx_REG (ptr_mode, i);
11128 if (scratch1 == scratch0)
11129 error ("Need a second call-clobbered general purpose register");
11130 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
11131 if (call_used_regs[i] && ! fixed_regs[i])
11133 scratch2 = gen_rtx_REG (Pmode, i);
11136 if (scratch2 == scratch0)
11137 error ("Need a call-clobbered target register");
11140 this_value = plus_constant (this_rtx, delta);
11142 && (simple_add || scratch0 != scratch1)
11143 && strict_memory_address_p (ptr_mode, this_value))
11145 emit_load_ptr (scratch0, this_value);
11150 ; /* Do nothing. */
11151 else if (simple_add)
11152 emit_move_insn (this_rtx, this_value);
11155 emit_move_insn (scratch1, GEN_INT (delta));
11156 emit_insn (gen_add2_insn (this_rtx, scratch1));
11164 emit_load_ptr (scratch0, this_rtx);
11166 offset_addr = plus_constant (scratch0, vcall_offset);
11167 if (strict_memory_address_p (ptr_mode, offset_addr))
11168 ; /* Do nothing. */
11169 else if (! TARGET_SH5 && scratch0 != scratch1)
11171 /* scratch0 != scratch1, and we have indexed loads. Get better
11172 schedule by loading the offset into r1 and using an indexed
11173 load - then the load of r1 can issue before the load from
11174 (this_rtx + delta) finishes. */
11175 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11176 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
11178 else if (CONST_OK_FOR_ADD (vcall_offset))
11180 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
11181 offset_addr = scratch0;
11183 else if (scratch0 != scratch1)
11185 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11186 emit_insn (gen_add2_insn (scratch0, scratch1));
11187 offset_addr = scratch0;
11190 gcc_unreachable (); /* FIXME */
11191 emit_load_ptr (scratch0, offset_addr);
11193 if (Pmode != ptr_mode)
11194 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
11195 emit_insn (gen_add2_insn (this_rtx, scratch0));
11198 /* Generate a tail call to the target function. */
11199 if (! TREE_USED (function))
11201 assemble_external (function);
11202 TREE_USED (function) = 1;
11204 funexp = XEXP (DECL_RTL (function), 0);
11205 /* If the function is overridden, so is the thunk, hence we don't
11206 need GOT addressing even if this is a public symbol. */
11208 if (TARGET_SH1 && ! flag_weak)
11209 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
11212 if (TARGET_SH2 && flag_pic)
11214 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
11215 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
11219 if (TARGET_SHMEDIA && flag_pic)
11221 funexp = gen_sym2PIC (funexp);
11222 PUT_MODE (funexp, Pmode);
11224 emit_move_insn (scratch2, funexp);
11225 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
11226 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
11228 sibcall = emit_call_insn (sibcall);
11229 SIBLING_CALL_P (sibcall) = 1;
11230 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
11233 /* Run just enough of rest_of_compilation to do scheduling and get
11234 the insns emitted. Note that use_thunk calls
11235 assemble_start_function and assemble_end_function. */
11237 insn_locators_alloc ();
11238 insns = get_insns ();
11244 split_all_insns_noflow ();
11249 if (optimize > 0 && flag_delayed_branch)
11250 dbr_schedule (insns);
11252 shorten_branches (insns);
11253 final_start_function (insns, file, 1);
11254 final (insns, file, 1);
11255 final_end_function ();
11256 free_after_compilation (cfun);
11258 reload_completed = 0;
11259 epilogue_completed = 0;
11263 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
11267 /* If this is not an ordinary function, the name usually comes from a
11268 string literal or an sprintf buffer. Make sure we use the same
11269 string consistently, so that cse will be able to unify address loads. */
11270 if (kind != FUNCTION_ORDINARY)
11271 name = IDENTIFIER_POINTER (get_identifier (name));
11272 sym = gen_rtx_SYMBOL_REF (Pmode, name);
11273 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
11277 case FUNCTION_ORDINARY:
11281 rtx reg = target ? target : gen_reg_rtx (Pmode);
11283 emit_insn (gen_symGOT2reg (reg, sym));
11289 /* ??? To allow cse to work, we use GOTOFF relocations.
11290 we could add combiner patterns to transform this into
11291 straight pc-relative calls with sym2PIC / bsrf when
11292 label load and function call are still 1:1 and in the
11293 same basic block during combine. */
11294 rtx reg = target ? target : gen_reg_rtx (Pmode);
11296 emit_insn (gen_symGOTOFF2reg (reg, sym));
11301 if (target && sym != target)
11303 emit_move_insn (target, sym);
11309 /* Find the number of a general purpose register in S. */
11311 scavenge_reg (HARD_REG_SET *s)
11314 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11315 if (TEST_HARD_REG_BIT (*s, r))
11321 sh_get_pr_initial_val (void)
11325 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11326 PR register on SHcompact, because it might be clobbered by the prologue.
11327 We check first if that is known to be the case. */
11328 if (TARGET_SHCOMPACT
11329 && ((crtl->args.info.call_cookie
11330 & ~ CALL_COOKIE_RET_TRAMP (1))
11331 || crtl->saves_all_registers))
11332 return gen_frame_mem (SImode, return_address_pointer_rtx);
11334 /* If we haven't finished rtl generation, there might be a nonlocal label
11335 that we haven't seen yet.
11336 ??? get_hard_reg_initial_val fails if it is called after register
11337 allocation has started, unless it has been called before for the
11338 same register. And even then, we end in trouble if we didn't use
11339 the register in the same basic block before. So call
11340 get_hard_reg_initial_val now and wrap it in an unspec if we might
11341 need to replace it. */
11342 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11343 combine can put the pseudo returned by get_hard_reg_initial_val into
11344 instructions that need a general purpose registers, which will fail to
11345 be recognized when the pseudo becomes allocated to PR. */
11347 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
11349 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11354 sh_expand_t_scc (rtx operands[])
11356 enum rtx_code code = GET_CODE (operands[1]);
11357 rtx target = operands[0];
11358 rtx op0 = operands[2];
11359 rtx op1 = operands[3];
11360 rtx result = target;
11363 if (!REG_P (op0) || REGNO (op0) != T_REG
11364 || !CONST_INT_P (op1))
11366 if (!REG_P (result))
11367 result = gen_reg_rtx (SImode);
11368 val = INTVAL (op1);
11369 if ((code == EQ && val == 1) || (code == NE && val == 0))
11370 emit_insn (gen_movt (result));
11371 else if (TARGET_SH2A && ((code == EQ && val == 0)
11372 || (code == NE && val == 1)))
11373 emit_insn (gen_xorsi3_movrt (result));
11374 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11376 emit_clobber (result);
11377 emit_insn (gen_subc (result, result, result));
11378 emit_insn (gen_addsi3 (result, result, const1_rtx));
11380 else if (code == EQ || code == NE)
11381 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11384 if (result != target)
11385 emit_move_insn (target, result);
11389 /* INSN is an sfunc; return the rtx that describes the address used. */
11391 extract_sfunc_addr (rtx insn)
11393 rtx pattern, part = NULL_RTX;
11396 pattern = PATTERN (insn);
11397 len = XVECLEN (pattern, 0);
11398 for (i = 0; i < len; i++)
11400 part = XVECEXP (pattern, 0, i);
11401 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11402 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11403 return XEXP (part, 0);
11405 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11406 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11409 /* Verify that the register in use_sfunc_addr still agrees with the address
11410 used in the sfunc. This prevents fill_slots_from_thread from changing
11412 INSN is the use_sfunc_addr instruction, and REG is the register it
11415 check_use_sfunc_addr (rtx insn, rtx reg)
11417 /* Search for the sfunc. It should really come right after INSN. */
11418 while ((insn = NEXT_INSN (insn)))
11420 if (LABEL_P (insn) || JUMP_P (insn))
11422 if (! INSN_P (insn))
11425 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11426 insn = XVECEXP (PATTERN (insn), 0, 0);
11427 if (GET_CODE (PATTERN (insn)) != PARALLEL
11428 || get_attr_type (insn) != TYPE_SFUNC)
11430 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11432 gcc_unreachable ();
11435 /* This function returns a constant rtx that represents pi / 2**15 in
11436 SFmode. it's used to scale SFmode angles, in radians, to a
11437 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11438 maps to 0x10000). */
11440 static GTY(()) rtx sh_fsca_sf2int_rtx;
11443 sh_fsca_sf2int (void)
11445 if (! sh_fsca_sf2int_rtx)
11447 REAL_VALUE_TYPE rv;
11449 real_from_string (&rv, "10430.378350470453");
11450 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11453 return sh_fsca_sf2int_rtx;
11456 /* This function returns a constant rtx that represents pi / 2**15 in
11457 DFmode. it's used to scale DFmode angles, in radians, to a
11458 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11459 maps to 0x10000). */
11461 static GTY(()) rtx sh_fsca_df2int_rtx;
11464 sh_fsca_df2int (void)
11466 if (! sh_fsca_df2int_rtx)
11468 REAL_VALUE_TYPE rv;
11470 real_from_string (&rv, "10430.378350470453");
11471 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
11474 return sh_fsca_df2int_rtx;
11477 /* This function returns a constant rtx that represents 2**15 / pi in
11478 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
11479 of a full circle back to a SFmode value, i.e., 0x10000 maps to
11482 static GTY(()) rtx sh_fsca_int2sf_rtx;
11485 sh_fsca_int2sf (void)
11487 if (! sh_fsca_int2sf_rtx)
11489 REAL_VALUE_TYPE rv;
11491 real_from_string (&rv, "9.587379924285257e-5");
11492 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
11495 return sh_fsca_int2sf_rtx;
11498 /* Initialize the CUMULATIVE_ARGS structure. */
11501 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
11503 rtx libname ATTRIBUTE_UNUSED,
11505 signed int n_named_args,
11506 enum machine_mode mode)
11508 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
11509 pcum->free_single_fp_reg = 0;
11510 pcum->stack_regs = 0;
11511 pcum->byref_regs = 0;
11513 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
11515 /* XXX - Should we check TARGET_HITACHI here ??? */
11516 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
11520 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
11521 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
11522 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
11523 pcum->arg_count [(int) SH_ARG_INT]
11524 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
11527 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11528 && pcum->arg_count [(int) SH_ARG_INT] == 0
11529 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
11530 ? int_size_in_bytes (TREE_TYPE (fntype))
11531 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
11532 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
11533 == FIRST_RET_REG));
11537 pcum->arg_count [(int) SH_ARG_INT] = 0;
11538 pcum->prototype_p = FALSE;
11539 if (mode != VOIDmode)
11541 pcum->call_cookie =
11542 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11543 && GET_MODE_SIZE (mode) > 4
11544 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
11546 /* If the default ABI is the Renesas ABI then all library
11547 calls must assume that the library will be using the
11548 Renesas ABI. So if the function would return its result
11549 in memory then we must force the address of this memory
11550 block onto the stack. Ideally we would like to call
11551 targetm.calls.return_in_memory() here but we do not have
11552 the TYPE or the FNDECL available so we synthesize the
11553 contents of that function as best we can. */
11555 (TARGET_DEFAULT & MASK_HITACHI)
11556 && (mode == BLKmode
11557 || (GET_MODE_SIZE (mode) > 4
11558 && !(mode == DFmode
11559 && TARGET_FPU_DOUBLE)));
11563 pcum->call_cookie = 0;
11564 pcum->force_mem = FALSE;
11569 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
11570 not enter into CONST_DOUBLE for the replace.
11572 Note that copying is not done so X must not be shared unless all copies
11573 are to be modified.
11575 This is like replace_rtx, except that we operate on N_REPLACEMENTS
11576 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
11577 replacements[n*2+1] - and that we take mode changes into account.
11579 If a replacement is ambiguous, return NULL_RTX.
11581 If MODIFY is zero, don't modify any rtl in place,
11582 just return zero or nonzero for failure / success. */
11585 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
11590 /* The following prevents loops occurrence when we change MEM in
11591 CONST_DOUBLE onto the same CONST_DOUBLE. */
11592 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
11595 for (i = n_replacements - 1; i >= 0 ; i--)
11596 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
11597 return replacements[i*2+1];
11599 /* Allow this function to make replacements in EXPR_LISTs. */
11603 if (GET_CODE (x) == SUBREG)
11605 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
11606 n_replacements, modify);
11608 if (CONST_INT_P (new_rtx))
11610 x = simplify_subreg (GET_MODE (x), new_rtx,
11611 GET_MODE (SUBREG_REG (x)),
11617 SUBREG_REG (x) = new_rtx;
11621 else if (REG_P (x))
11623 unsigned regno = REGNO (x);
11624 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
11625 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11626 rtx result = NULL_RTX;
11628 for (i = n_replacements - 1; i >= 0; i--)
11630 rtx from = replacements[i*2];
11631 rtx to = replacements[i*2+1];
11632 unsigned from_regno, from_nregs, to_regno, new_regno;
11636 from_regno = REGNO (from);
11637 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
11638 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
11639 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
11641 if (regno < from_regno
11642 || regno + nregs > from_regno + nregs
11646 to_regno = REGNO (to);
11647 if (to_regno < FIRST_PSEUDO_REGISTER)
11649 new_regno = regno + to_regno - from_regno;
11650 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
11653 result = gen_rtx_REG (GET_MODE (x), new_regno);
11655 else if (GET_MODE (x) <= GET_MODE (to))
11656 result = gen_lowpart_common (GET_MODE (x), to);
11658 result = gen_lowpart_SUBREG (GET_MODE (x), to);
11661 return result ? result : x;
11663 else if (GET_CODE (x) == ZERO_EXTEND)
11665 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
11666 n_replacements, modify);
11668 if (CONST_INT_P (new_rtx))
11670 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
11671 new_rtx, GET_MODE (XEXP (x, 0)));
11676 XEXP (x, 0) = new_rtx;
11681 fmt = GET_RTX_FORMAT (GET_CODE (x));
11682 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
11688 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
11689 n_replacements, modify);
11693 XEXP (x, i) = new_rtx;
11695 else if (fmt[i] == 'E')
11696 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11698 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
11699 n_replacements, modify);
11703 XVECEXP (x, i, j) = new_rtx;
11711 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
11713 enum rtx_code code = TRUNCATE;
11715 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11717 rtx inner = XEXP (x, 0);
11718 enum machine_mode inner_mode = GET_MODE (inner);
11720 if (inner_mode == mode)
11722 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11724 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11725 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11727 code = GET_CODE (x);
11731 return gen_rtx_fmt_e (code, mode, x);
11734 /* called via for_each_rtx after reload, to clean up truncates of
11735 registers that span multiple actual hard registers. */
11737 shmedia_cleanup_truncate (rtx *p, void *n_changes)
11741 if (GET_CODE (x) != TRUNCATE)
11744 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
11746 enum machine_mode reg_mode = GET_MODE (reg);
11747 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
11748 subreg_lowpart_offset (DImode, reg_mode));
11749 *(int*) n_changes += 1;
11755 /* Load and store depend on the highpart of the address. However,
11756 set_attr_alternative does not give well-defined results before reload,
11757 so we must look at the rtl ourselves to see if any of the feeding
11758 registers is used in a memref. */
11760 /* Called by sh_contains_memref_p via for_each_rtx. */
11762 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
11764 return (MEM_P (*loc));
11767 /* Return nonzero iff INSN contains a MEM. */
11769 sh_contains_memref_p (rtx insn)
11771 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11774 /* Return nonzero iff INSN loads a banked register. */
11776 sh_loads_bankedreg_p (rtx insn)
11778 if (GET_CODE (PATTERN (insn)) == SET)
11780 rtx op = SET_DEST (PATTERN(insn));
11781 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11788 /* FNADDR is the MEM expression from a call expander. Return an address
11789 to use in an SHmedia insn pattern. */
11791 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11795 fnaddr = XEXP (fnaddr, 0);
11796 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11797 if (flag_pic && is_sym)
11799 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11801 rtx reg = gen_reg_rtx (Pmode);
11803 /* We must not use GOTPLT for sibcalls, because PIC_REG
11804 must be restored before the PLT code gets to run. */
11806 emit_insn (gen_symGOT2reg (reg, fnaddr));
11808 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11813 fnaddr = gen_sym2PIC (fnaddr);
11814 PUT_MODE (fnaddr, Pmode);
11817 /* If ptabs might trap, make this visible to the rest of the compiler.
11818 We generally assume that symbols pertain to valid locations, but
11819 it is possible to generate invalid symbols with asm or linker tricks.
11820 In a list of functions where each returns its successor, an invalid
11821 symbol might denote an empty list. */
11822 if (!TARGET_PT_FIXED
11823 && (!is_sym || TARGET_INVALID_SYMBOLS)
11824 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11826 rtx tr = gen_reg_rtx (PDImode);
11828 emit_insn (gen_ptabs (tr, fnaddr));
11831 else if (! target_reg_operand (fnaddr, Pmode))
11832 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11837 sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
11838 enum machine_mode mode, secondary_reload_info *sri)
11842 if (REGCLASS_HAS_FP_REG (rclass)
11843 && ! TARGET_SHMEDIA
11844 && immediate_operand ((x), mode)
11845 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11846 && mode == SFmode && fldi_ok ()))
11850 sri->icode = CODE_FOR_reload_insf__frn;
11853 sri->icode = CODE_FOR_reload_indf__frn;
11856 /* ??? If we knew that we are in the appropriate mode -
11857 single precision - we could use a reload pattern directly. */
11862 if (rclass == FPUL_REGS
11864 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11865 || REGNO (x) == T_REG))
11866 || GET_CODE (x) == PLUS))
11867 return GENERAL_REGS;
11868 if (rclass == FPUL_REGS && immediate_operand (x, mode))
11870 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11871 return GENERAL_REGS;
11872 else if (mode == SFmode)
11874 sri->icode = CODE_FOR_reload_insi__i_fpul;
11877 if (rclass == FPSCR_REGS
11878 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11879 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
11880 return GENERAL_REGS;
11881 if (REGCLASS_HAS_FP_REG (rclass)
11883 && immediate_operand (x, mode)
11884 && x != CONST0_RTX (GET_MODE (x))
11885 && GET_MODE (x) != V4SFmode)
11886 return GENERAL_REGS;
11887 if ((mode == QImode || mode == HImode)
11888 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11890 sri->icode = ((mode == QImode)
11891 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11894 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
11895 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
11896 return TARGET_REGS;
11897 } /* end of input-only processing. */
11899 if (((REGCLASS_HAS_FP_REG (rclass)
11901 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11902 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11903 && TARGET_FMOVD))))
11904 || (REGCLASS_HAS_GENERAL_REG (rclass)
11906 && FP_REGISTER_P (REGNO (x))))
11907 && ! TARGET_SHMEDIA
11908 && (mode == SFmode || mode == SImode))
11910 if ((rclass == FPUL_REGS
11911 || (REGCLASS_HAS_FP_REG (rclass)
11912 && ! TARGET_SHMEDIA && mode == SImode))
11915 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11916 || REGNO (x) == T_REG
11917 || system_reg_operand (x, VOIDmode)))))
11919 if (rclass == FPUL_REGS)
11920 return GENERAL_REGS;
11923 if ((rclass == TARGET_REGS
11924 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
11925 && !satisfies_constraint_Csy (x)
11926 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
11927 return GENERAL_REGS;
11928 if ((rclass == MAC_REGS || rclass == PR_REGS)
11929 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
11930 && rclass != REGNO_REG_CLASS (REGNO (x)))
11931 return GENERAL_REGS;
11932 if (rclass != GENERAL_REGS && REG_P (x)
11933 && TARGET_REGISTER_P (REGNO (x)))
11934 return GENERAL_REGS;
11938 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;