1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "insn-config.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
40 #include "integrate.h"
44 #include "target-def.h"
46 #include "langhooks.h"
47 #include "basic-block.h"
49 #include "cfglayout.h"
51 #include "sched-int.h"
55 #include "alloc-pool.h"
56 #include "tm-constrs.h"
59 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
61 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
62 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
64 /* These are some macros to abstract register modes. */
65 #define CONST_OK_FOR_ADD(size) \
66 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
67 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
68 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
69 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
71 /* Used to simplify the logic below. Find the attributes wherever
73 #define SH_ATTRIBUTES(decl) \
74 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
75 : DECL_ATTRIBUTES (decl) \
76 ? (DECL_ATTRIBUTES (decl)) \
77 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
79 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
80 int current_function_interrupt;
82 tree sh_deferred_function_attributes;
83 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
85 /* Global variables for machine-dependent things. */
87 /* Which cpu are we scheduling for. */
88 enum processor_type sh_cpu;
90 /* Definitions used in ready queue reordering for first scheduling pass. */
92 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
93 static short *regmode_weight[2];
95 /* Total SFmode and SImode weights of scheduled insns. */
96 static int curr_regmode_pressure[2];
98 /* Number of r0 life regions. */
99 static int r0_life_regions;
101 /* If true, skip cycles for Q -> R movement. */
102 static int skip_cycles = 0;
104 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
105 and returned from sh_reorder2. */
106 static short cached_can_issue_more;
108 /* Provides the class number of the smallest class containing
111 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
113 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
114 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
130 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
146 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
147 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
148 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
149 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
150 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
151 GENERAL_REGS, GENERAL_REGS,
154 char sh_register_names[FIRST_PSEUDO_REGISTER] \
155 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
157 char sh_additional_register_names[ADDREGNAMES_SIZE] \
158 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
159 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
161 int assembler_dialect;
163 static bool shmedia_space_reserved_for_target_registers;
165 static bool sh_handle_option (size_t, const char *, int);
166 static void split_branches (rtx);
167 static int branch_dest (rtx);
168 static void force_into (rtx, rtx);
169 static void print_slot (rtx);
170 static rtx add_constant (rtx, enum machine_mode, rtx);
171 static void dump_table (rtx, rtx);
172 static int hi_const (rtx);
173 static int broken_move (rtx);
174 static int mova_p (rtx);
175 static rtx find_barrier (int, rtx, rtx);
176 static int noncall_uses_reg (rtx, rtx, rtx *);
177 static rtx gen_block_redirect (rtx, int, int);
178 static void sh_reorg (void);
179 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
180 static rtx frame_insn (rtx);
181 static rtx push (int);
182 static void pop (int);
183 static void push_regs (HARD_REG_SET *, int);
184 static int calc_live_regs (HARD_REG_SET *);
185 static HOST_WIDE_INT rounded_frame_size (int);
186 static rtx mark_constant_pool_use (rtx);
187 EXPORTED_CONST struct attribute_spec sh_attribute_table[];
188 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
189 static tree sh_handle_resbank_handler_attribute (tree *, tree,
191 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
193 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
194 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
195 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
196 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
197 static void sh_insert_attributes (tree, tree *);
198 static const char *sh_check_pch_target_flags (int);
199 static int sh_adjust_cost (rtx, rtx, rtx, int);
200 static int sh_issue_rate (void);
201 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
202 static short find_set_regmode_weight (rtx, enum machine_mode);
203 static short find_insn_regmode_weight (rtx, enum machine_mode);
204 static void find_regmode_weight (basic_block, enum machine_mode);
205 static int find_r0_life_regions (basic_block);
206 static void sh_md_init_global (FILE *, int, int);
207 static void sh_md_finish_global (FILE *, int);
208 static int rank_for_reorder (const void *, const void *);
209 static void swap_reorder (rtx *, int);
210 static void ready_reorder (rtx *, int);
211 static short high_pressure (enum machine_mode);
212 static int sh_reorder (FILE *, int, rtx *, int *, int);
213 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
214 static void sh_md_init (FILE *, int, int);
215 static int sh_variable_issue (FILE *, int, rtx, int);
217 static bool sh_function_ok_for_sibcall (tree, tree);
219 static bool sh_cannot_modify_jumps_p (void);
220 static enum reg_class sh_target_reg_class (void);
221 static bool sh_optimize_target_register_callee_saved (bool);
222 static bool sh_ms_bitfield_layout_p (const_tree);
224 static void sh_init_builtins (void);
225 static void sh_media_init_builtins (void);
226 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
227 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
228 static void sh_file_start (void);
229 static int flow_dependent_p (rtx, rtx);
230 static void flow_dependent_p_1 (rtx, const_rtx, void *);
231 static int shiftcosts (rtx);
232 static int andcosts (rtx);
233 static int addsubcosts (rtx);
234 static int multcosts (rtx);
235 static bool unspec_caller_rtx_p (rtx);
236 static bool sh_cannot_copy_insn_p (rtx);
237 static bool sh_rtx_costs (rtx, int, int, int *, bool);
238 static int sh_address_cost (rtx, bool);
239 static int sh_pr_n_sets (void);
240 static rtx sh_allocate_initial_value (rtx);
241 static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
242 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
243 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
244 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
245 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
246 static int scavenge_reg (HARD_REG_SET *s);
247 struct save_schedule_s;
248 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
249 struct save_schedule_s *, int);
251 static rtx sh_struct_value_rtx (tree, int);
252 static bool sh_return_in_memory (const_tree, const_tree);
253 static rtx sh_builtin_saveregs (void);
254 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
255 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
256 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
257 static tree sh_build_builtin_va_list (void);
258 static void sh_va_start (tree, rtx);
259 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
260 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
262 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
264 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
266 static bool sh_scalar_mode_supported_p (enum machine_mode);
267 static int sh_dwarf_calling_convention (const_tree);
268 static void sh_encode_section_info (tree, rtx, int);
269 static int sh2a_function_vector_p (tree);
272 /* Initialize the GCC target structure. */
273 #undef TARGET_ATTRIBUTE_TABLE
274 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
276 /* The next two are used for debug info when compiling with -gdwarf. */
277 #undef TARGET_ASM_UNALIGNED_HI_OP
278 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
279 #undef TARGET_ASM_UNALIGNED_SI_OP
280 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
282 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
283 #undef TARGET_ASM_UNALIGNED_DI_OP
284 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
285 #undef TARGET_ASM_ALIGNED_DI_OP
286 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
288 #undef TARGET_ASM_FUNCTION_EPILOGUE
289 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
291 #undef TARGET_ASM_OUTPUT_MI_THUNK
292 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
294 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
295 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
297 #undef TARGET_ASM_FILE_START
298 #define TARGET_ASM_FILE_START sh_file_start
299 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
300 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
302 #undef TARGET_DEFAULT_TARGET_FLAGS
303 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
304 #undef TARGET_HANDLE_OPTION
305 #define TARGET_HANDLE_OPTION sh_handle_option
307 #undef TARGET_INSERT_ATTRIBUTES
308 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
310 #undef TARGET_SCHED_ADJUST_COST
311 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
313 #undef TARGET_SCHED_ISSUE_RATE
314 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
316 /* The next 5 hooks have been implemented for reenabling sched1. With the
317 help of these macros we are limiting the movement of insns in sched1 to
318 reduce the register pressure. The overall idea is to keep count of SImode
319 and SFmode regs required by already scheduled insns. When these counts
320 cross some threshold values; give priority to insns that free registers.
321 The insn that frees registers is most likely to be the insn with lowest
322 LUID (original insn order); but such an insn might be there in the stalled
323 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
324 upto a max of 8 cycles so that such insns may move from Q -> R.
326 The description of the hooks are as below:
328 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
329 scheduler; it is called inside the sched_init function just after
330 find_insn_reg_weights function call. It is used to calculate the SImode
331 and SFmode weights of insns of basic blocks; much similar to what
332 find_insn_reg_weights does.
333 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
335 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
336 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
339 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
340 high; reorder the ready queue so that the insn with lowest LUID will be
343 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
344 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
346 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
347 can be returned from TARGET_SCHED_REORDER2.
349 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
351 #undef TARGET_SCHED_DFA_NEW_CYCLE
352 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
354 #undef TARGET_SCHED_INIT_GLOBAL
355 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
357 #undef TARGET_SCHED_FINISH_GLOBAL
358 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
360 #undef TARGET_SCHED_VARIABLE_ISSUE
361 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
363 #undef TARGET_SCHED_REORDER
364 #define TARGET_SCHED_REORDER sh_reorder
366 #undef TARGET_SCHED_REORDER2
367 #define TARGET_SCHED_REORDER2 sh_reorder2
369 #undef TARGET_SCHED_INIT
370 #define TARGET_SCHED_INIT sh_md_init
372 #undef TARGET_LEGITIMIZE_ADDRESS
373 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
375 #undef TARGET_CANNOT_MODIFY_JUMPS_P
376 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
377 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
378 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
379 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
380 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
381 sh_optimize_target_register_callee_saved
383 #undef TARGET_MS_BITFIELD_LAYOUT_P
384 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
386 #undef TARGET_INIT_BUILTINS
387 #define TARGET_INIT_BUILTINS sh_init_builtins
388 #undef TARGET_EXPAND_BUILTIN
389 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
391 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
392 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
394 #undef TARGET_CANNOT_COPY_INSN_P
395 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
396 #undef TARGET_RTX_COSTS
397 #define TARGET_RTX_COSTS sh_rtx_costs
398 #undef TARGET_ADDRESS_COST
399 #define TARGET_ADDRESS_COST sh_address_cost
400 #undef TARGET_ALLOCATE_INITIAL_VALUE
401 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
403 #undef TARGET_MACHINE_DEPENDENT_REORG
404 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
406 #undef TARGET_DWARF_REGISTER_SPAN
407 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
410 #undef TARGET_HAVE_TLS
411 #define TARGET_HAVE_TLS true
414 #undef TARGET_PROMOTE_PROTOTYPES
415 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
416 #undef TARGET_PROMOTE_FUNCTION_ARGS
417 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
418 #undef TARGET_PROMOTE_FUNCTION_RETURN
419 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
421 #undef TARGET_STRUCT_VALUE_RTX
422 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
423 #undef TARGET_RETURN_IN_MEMORY
424 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
426 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
427 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
428 #undef TARGET_SETUP_INCOMING_VARARGS
429 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
430 #undef TARGET_STRICT_ARGUMENT_NAMING
431 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
432 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
433 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
434 #undef TARGET_MUST_PASS_IN_STACK
435 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
436 #undef TARGET_PASS_BY_REFERENCE
437 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
438 #undef TARGET_CALLEE_COPIES
439 #define TARGET_CALLEE_COPIES sh_callee_copies
440 #undef TARGET_ARG_PARTIAL_BYTES
441 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
443 #undef TARGET_BUILD_BUILTIN_VA_LIST
444 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
445 #undef TARGET_EXPAND_BUILTIN_VA_START
446 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
447 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
448 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
450 #undef TARGET_SCALAR_MODE_SUPPORTED_P
451 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
452 #undef TARGET_VECTOR_MODE_SUPPORTED_P
453 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
455 #undef TARGET_CHECK_PCH_TARGET_FLAGS
456 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
458 #undef TARGET_DWARF_CALLING_CONVENTION
459 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
461 /* Return regmode weight for insn. */
462 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
464 /* Return current register pressure for regmode. */
465 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
467 #undef TARGET_ENCODE_SECTION_INFO
468 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
472 #undef TARGET_ENCODE_SECTION_INFO
473 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
474 #undef TARGET_STRIP_NAME_ENCODING
475 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
476 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
477 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
481 #undef TARGET_SECONDARY_RELOAD
482 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
484 #undef TARGET_LEGITIMATE_ADDRESS_P
485 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
487 /* Machine-specific symbol_ref flags. */
488 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
490 struct gcc_target targetm = TARGET_INITIALIZER;
492 /* Implement TARGET_HANDLE_OPTION. */
495 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
496 int value ATTRIBUTE_UNUSED)
501 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
505 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
509 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
513 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
517 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
520 case OPT_m2a_single_only:
521 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
525 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
529 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
533 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
540 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
544 case OPT_m4_100_nofpu:
545 case OPT_m4_200_nofpu:
546 case OPT_m4_300_nofpu:
550 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
554 case OPT_m4_100_single:
555 case OPT_m4_200_single:
556 case OPT_m4_300_single:
557 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
560 case OPT_m4_single_only:
561 case OPT_m4_100_single_only:
562 case OPT_m4_200_single_only:
563 case OPT_m4_300_single_only:
564 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
568 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
573 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
577 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
580 case OPT_m4a_single_only:
581 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
585 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
588 case OPT_m5_32media_nofpu:
589 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
593 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
596 case OPT_m5_64media_nofpu:
597 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
601 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
604 case OPT_m5_compact_nofpu:
605 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
613 /* Print the operand address in x to the stream. */
616 print_operand_address (FILE *stream, rtx x)
618 switch (GET_CODE (x))
622 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
627 rtx base = XEXP (x, 0);
628 rtx index = XEXP (x, 1);
630 switch (GET_CODE (index))
633 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
634 reg_names[true_regnum (base)]);
640 int base_num = true_regnum (base);
641 int index_num = true_regnum (index);
643 fprintf (stream, "@(r0,%s)",
644 reg_names[MAX (base_num, index_num)]);
655 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
659 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
663 x = mark_constant_pool_use (x);
664 output_addr_const (stream, x);
669 /* Print operand x (an rtx) in assembler syntax to file stream
670 according to modifier code.
672 '.' print a .s if insn needs delay slot
673 ',' print LOCAL_LABEL_PREFIX
674 '@' print trap, rte or rts depending upon pragma interruptness
675 '#' output a nop if there is nothing to put in the delay slot
676 ''' print likelihood suffix (/u for unlikely).
677 '>' print branch target if -fverbose-asm
678 'O' print a constant without the #
679 'R' print the LSW of a dp value - changes if in little endian
680 'S' print the MSW of a dp value - changes if in little endian
681 'T' print the next word of a dp value - same as 'R' in big endian mode.
682 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
683 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
684 'N' print 'r63' if the operand is (const_int 0).
685 'd' print a V2SF reg as dN instead of fpN.
686 'm' print a pair `base,offset' or `base,index', for LD and ST.
687 'U' Likewise for {LD,ST}{HI,LO}.
688 'V' print the position of a single bit set.
689 'W' print the position of a single bit cleared.
690 't' print a memory address which is a register.
691 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
692 'o' output an operator. */
695 print_operand (FILE *stream, rtx x, int code)
698 enum machine_mode mode;
706 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
707 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
708 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
711 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
714 trapa_attr = lookup_attribute ("trap_exit",
715 DECL_ATTRIBUTES (current_function_decl));
717 fprintf (stream, "trapa #%ld",
718 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
719 else if (sh_cfun_interrupt_handler_p ())
721 if (sh_cfun_resbank_handler_p ())
722 fprintf (stream, "resbank\n");
723 fprintf (stream, "rte");
726 fprintf (stream, "rts");
729 /* Output a nop if there's nothing in the delay slot. */
730 if (dbr_sequence_length () == 0)
731 fprintf (stream, "\n\tnop");
735 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
737 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
738 fputs ("/u", stream);
742 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
744 fputs ("\t! target: ", stream);
745 output_addr_const (stream, JUMP_LABEL (current_output_insn));
749 x = mark_constant_pool_use (x);
750 output_addr_const (stream, x);
752 /* N.B.: %R / %S / %T adjust memory addresses by four.
753 For SHMEDIA, that means they can be used to access the first and
754 second 32 bit part of a 64 bit (or larger) value that
755 might be held in floating point registers or memory.
756 While they can be used to access 64 bit parts of a larger value
757 held in general purpose registers, that won't work with memory -
758 neither for fp registers, since the frxx names are used. */
760 if (REG_P (x) || GET_CODE (x) == SUBREG)
762 regno = true_regnum (x);
763 regno += FP_REGISTER_P (regno) ? 1 : LSW;
764 fputs (reg_names[regno], (stream));
768 x = adjust_address (x, SImode, 4 * LSW);
769 print_operand_address (stream, XEXP (x, 0));
776 if (mode == VOIDmode)
778 if (GET_MODE_SIZE (mode) >= 8)
779 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
781 print_operand (stream, sub, 0);
783 output_operand_lossage ("invalid operand to %%R");
787 if (REG_P (x) || GET_CODE (x) == SUBREG)
789 regno = true_regnum (x);
790 regno += FP_REGISTER_P (regno) ? 0 : MSW;
791 fputs (reg_names[regno], (stream));
795 x = adjust_address (x, SImode, 4 * MSW);
796 print_operand_address (stream, XEXP (x, 0));
803 if (mode == VOIDmode)
805 if (GET_MODE_SIZE (mode) >= 8)
806 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
808 print_operand (stream, sub, 0);
810 output_operand_lossage ("invalid operand to %%S");
814 /* Next word of a double. */
815 switch (GET_CODE (x))
818 fputs (reg_names[REGNO (x) + 1], (stream));
821 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
822 && GET_CODE (XEXP (x, 0)) != POST_INC)
823 x = adjust_address (x, SImode, 4);
824 print_operand_address (stream, XEXP (x, 0));
832 gcc_assert (MEM_P (x));
834 switch (GET_CODE (x))
838 print_operand (stream, x, 0);
846 switch (GET_CODE (x))
848 case PLUS: fputs ("add", stream); break;
849 case MINUS: fputs ("sub", stream); break;
850 case MULT: fputs ("mul", stream); break;
851 case DIV: fputs ("div", stream); break;
852 case EQ: fputs ("eq", stream); break;
853 case NE: fputs ("ne", stream); break;
854 case GT: case LT: fputs ("gt", stream); break;
855 case GE: case LE: fputs ("ge", stream); break;
856 case GTU: case LTU: fputs ("gtu", stream); break;
857 case GEU: case LEU: fputs ("geu", stream); break;
866 && GET_CODE (XEXP (x, 0)) == PLUS
867 && (REG_P (XEXP (XEXP (x, 0), 1))
868 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
875 switch (GET_MODE (x))
877 case QImode: fputs (".b", stream); break;
878 case HImode: fputs (".w", stream); break;
879 case SImode: fputs (".l", stream); break;
880 case SFmode: fputs (".s", stream); break;
881 case DFmode: fputs (".d", stream); break;
882 default: gcc_unreachable ();
889 gcc_assert (MEM_P (x));
893 switch (GET_CODE (x))
897 print_operand (stream, x, 0);
898 fputs (", 0", stream);
902 print_operand (stream, XEXP (x, 0), 0);
903 fputs (", ", stream);
904 print_operand (stream, XEXP (x, 1), 0);
914 int num = exact_log2 (INTVAL (x));
915 gcc_assert (num >= 0);
916 fprintf (stream, "#%d", num);
922 int num = exact_log2 (~INTVAL (x));
923 gcc_assert (num >= 0);
924 fprintf (stream, "#%d", num);
929 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
931 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
935 if (x == CONST0_RTX (GET_MODE (x)))
937 fprintf ((stream), "r63");
944 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
954 switch (GET_CODE (x))
958 rtx inner = XEXP (x, 0);
960 enum machine_mode inner_mode;
962 /* We might see SUBREGs with vector mode registers inside. */
963 if (GET_CODE (inner) == SUBREG
964 && (GET_MODE_SIZE (GET_MODE (inner))
965 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
966 && subreg_lowpart_p (inner))
967 inner = SUBREG_REG (inner);
968 if (CONST_INT_P (inner))
970 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
973 inner_mode = GET_MODE (inner);
974 if (GET_CODE (inner) == SUBREG
975 && (GET_MODE_SIZE (GET_MODE (inner))
976 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
977 && REG_P (SUBREG_REG (inner)))
979 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
980 GET_MODE (SUBREG_REG (inner)),
983 inner = SUBREG_REG (inner);
985 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
987 /* Floating point register pairs are always big endian;
988 general purpose registers are 64 bit wide. */
989 regno = REGNO (inner);
990 regno = (HARD_REGNO_NREGS (regno, inner_mode)
991 - HARD_REGNO_NREGS (regno, mode))
999 /* FIXME: We need this on SHmedia32 because reload generates
1000 some sign-extended HI or QI loads into DImode registers
1001 but, because Pmode is SImode, the address ends up with a
1002 subreg:SI of the DImode register. Maybe reload should be
1003 fixed so as to apply alter_subreg to such loads? */
1005 gcc_assert (trapping_target_operand (x, VOIDmode));
1006 x = XEXP (XEXP (x, 2), 0);
1007 goto default_output;
1009 gcc_assert (SUBREG_BYTE (x) == 0
1010 && REG_P (SUBREG_REG (x)));
1018 if (FP_REGISTER_P (regno)
1019 && mode == V16SFmode)
1020 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1021 else if (FP_REGISTER_P (REGNO (x))
1022 && mode == V4SFmode)
1023 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1025 && mode == V2SFmode)
1026 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1027 else if (FP_REGISTER_P (REGNO (x))
1028 && GET_MODE_SIZE (mode) > 4)
1029 fprintf ((stream), "d%s", reg_names[regno] + 1);
1031 fputs (reg_names[regno], (stream));
1035 output_address (XEXP (x, 0));
1040 fputc ('#', stream);
1041 output_addr_const (stream, x);
1049 /* Encode symbol attributes of a SYMBOL_REF into its
1050 SYMBOL_REF_FLAGS. */
1052 sh_encode_section_info (tree decl, rtx rtl, int first)
1054 default_encode_section_info (decl, rtl, first);
1056 if (TREE_CODE (decl) == FUNCTION_DECL
1057 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1058 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1061 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1063 force_into (rtx value, rtx target)
1065 value = force_operand (value, target);
1066 if (! rtx_equal_p (value, target))
1067 emit_insn (gen_move_insn (target, value));
1070 /* Emit code to perform a block move. Choose the best method.
1072 OPERANDS[0] is the destination.
1073 OPERANDS[1] is the source.
1074 OPERANDS[2] is the size.
1075 OPERANDS[3] is the alignment safe to use. */
1078 expand_block_move (rtx *operands)
1080 int align = INTVAL (operands[3]);
1081 int constp = (CONST_INT_P (operands[2]));
1082 int bytes = (constp ? INTVAL (operands[2]) : 0);
1087 /* If we could use mov.l to move words and dest is word-aligned, we
1088 can use movua.l for loads and still generate a relatively short
1089 and efficient sequence. */
1090 if (TARGET_SH4A_ARCH && align < 4
1091 && MEM_ALIGN (operands[0]) >= 32
1092 && can_move_by_pieces (bytes, 32))
1094 rtx dest = copy_rtx (operands[0]);
1095 rtx src = copy_rtx (operands[1]);
1096 /* We could use different pseudos for each copied word, but
1097 since movua can only load into r0, it's kind of
1099 rtx temp = gen_reg_rtx (SImode);
1100 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1103 while (copied + 4 <= bytes)
1105 rtx to = adjust_address (dest, SImode, copied);
1106 rtx from = adjust_automodify_address (src, BLKmode,
1109 set_mem_size (from, GEN_INT (4));
1110 emit_insn (gen_movua (temp, from));
1111 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1112 emit_move_insn (to, temp);
1117 move_by_pieces (adjust_address (dest, BLKmode, copied),
1118 adjust_automodify_address (src, BLKmode,
1120 bytes - copied, align, 0);
1125 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1126 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1127 if (align < 4 || (bytes % 4 != 0))
1130 if (TARGET_HARD_SH4)
1134 else if (bytes == 12)
1136 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1137 rtx r4 = gen_rtx_REG (SImode, 4);
1138 rtx r5 = gen_rtx_REG (SImode, 5);
1140 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1141 force_into (XEXP (operands[0], 0), r4);
1142 force_into (XEXP (operands[1], 0), r5);
1143 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1146 else if (! TARGET_SMALLCODE)
1148 const char *entry_name;
1149 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1151 rtx r4 = gen_rtx_REG (SImode, 4);
1152 rtx r5 = gen_rtx_REG (SImode, 5);
1153 rtx r6 = gen_rtx_REG (SImode, 6);
1155 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1156 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1157 force_into (XEXP (operands[0], 0), r4);
1158 force_into (XEXP (operands[1], 0), r5);
1160 dwords = bytes >> 3;
1161 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1162 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1171 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1172 rtx r4 = gen_rtx_REG (SImode, 4);
1173 rtx r5 = gen_rtx_REG (SImode, 5);
1175 sprintf (entry, "__movmemSI%d", bytes);
1176 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1177 force_into (XEXP (operands[0], 0), r4);
1178 force_into (XEXP (operands[1], 0), r5);
1179 emit_insn (gen_block_move_real (func_addr_rtx));
1183 /* This is the same number of bytes as a memcpy call, but to a different
1184 less common function name, so this will occasionally use more space. */
1185 if (! TARGET_SMALLCODE)
1187 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1188 int final_switch, while_loop;
1189 rtx r4 = gen_rtx_REG (SImode, 4);
1190 rtx r5 = gen_rtx_REG (SImode, 5);
1191 rtx r6 = gen_rtx_REG (SImode, 6);
1193 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1194 force_into (XEXP (operands[0], 0), r4);
1195 force_into (XEXP (operands[1], 0), r5);
1197 /* r6 controls the size of the move. 16 is decremented from it
1198 for each 64 bytes moved. Then the negative bit left over is used
1199 as an index into a list of move instructions. e.g., a 72 byte move
1200 would be set up with size(r6) = 14, for one iteration through the
1201 big while loop, and a switch of -2 for the last part. */
1203 final_switch = 16 - ((bytes / 4) % 16);
1204 while_loop = ((bytes / 4) / 16 - 1) * 16;
1205 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1206 emit_insn (gen_block_lump_real (func_addr_rtx));
1213 /* Prepare operands for a move define_expand; specifically, one of the
1214 operands must be in a register. */
1217 prepare_move_operands (rtx operands[], enum machine_mode mode)
1219 if ((mode == SImode || mode == DImode)
1221 && ! ((mode == Pmode || mode == ptr_mode)
1222 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1225 if (SYMBOLIC_CONST_P (operands[1]))
1227 if (MEM_P (operands[0]))
1228 operands[1] = force_reg (Pmode, operands[1]);
1229 else if (TARGET_SHMEDIA
1230 && GET_CODE (operands[1]) == LABEL_REF
1231 && target_reg_operand (operands[0], mode))
1235 temp = (!can_create_pseudo_p ()
1237 : gen_reg_rtx (Pmode));
1238 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1241 else if (GET_CODE (operands[1]) == CONST
1242 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1243 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1245 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1246 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1248 operands[1] = expand_binop (mode, add_optab, temp,
1249 XEXP (XEXP (operands[1], 0), 1),
1250 (!can_create_pseudo_p ()
1252 : gen_reg_rtx (Pmode)),
1253 0, OPTAB_LIB_WIDEN);
1257 if (! reload_in_progress && ! reload_completed)
1259 /* Copy the source to a register if both operands aren't registers. */
1260 if (! register_operand (operands[0], mode)
1261 && ! sh_register_operand (operands[1], mode))
1262 operands[1] = copy_to_mode_reg (mode, operands[1]);
1264 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1266 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1267 except that we can't use that function because it is static. */
1268 rtx new_rtx = change_address (operands[0], mode, 0);
1269 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1270 operands[0] = new_rtx;
1273 /* This case can happen while generating code to move the result
1274 of a library call to the target. Reject `st r0,@(rX,rY)' because
1275 reload will fail to find a spill register for rX, since r0 is already
1276 being used for the source. */
1278 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1279 && MEM_P (operands[0])
1280 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1281 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1282 operands[1] = copy_to_mode_reg (mode, operands[1]);
1285 if (mode == Pmode || mode == ptr_mode)
1288 enum tls_model tls_kind;
1292 if (GET_CODE (op1) == CONST
1293 && GET_CODE (XEXP (op1, 0)) == PLUS
1294 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1297 opc = XEXP (XEXP (op1, 0), 1);
1298 op1 = XEXP (XEXP (op1, 0), 0);
1303 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1305 rtx tga_op1, tga_ret, tmp, tmp2;
1309 case TLS_MODEL_GLOBAL_DYNAMIC:
1310 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1311 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1315 case TLS_MODEL_LOCAL_DYNAMIC:
1316 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1317 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1319 tmp = gen_reg_rtx (Pmode);
1320 emit_move_insn (tmp, tga_ret);
1322 if (register_operand (op0, Pmode))
1325 tmp2 = gen_reg_rtx (Pmode);
1327 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1331 case TLS_MODEL_INITIAL_EXEC:
1334 /* Don't schedule insns for getting GOT address when
1335 the first scheduling is enabled, to avoid spill
1337 if (flag_schedule_insns)
1338 emit_insn (gen_blockage ());
1339 emit_insn (gen_GOTaddr2picreg ());
1340 emit_use (gen_rtx_REG (SImode, PIC_REG));
1341 if (flag_schedule_insns)
1342 emit_insn (gen_blockage ());
1344 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1345 tmp = gen_sym2GOTTPOFF (op1);
1346 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1350 case TLS_MODEL_LOCAL_EXEC:
1351 tmp2 = gen_reg_rtx (Pmode);
1352 emit_insn (gen_load_gbr (tmp2));
1353 tmp = gen_reg_rtx (Pmode);
1354 emit_insn (gen_symTPOFF2reg (tmp, op1));
1356 if (register_operand (op0, Pmode))
1359 op1 = gen_reg_rtx (Pmode);
1361 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1368 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1377 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1378 enum rtx_code comparison)
1381 rtx scratch = NULL_RTX;
1383 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1384 comparison = GET_CODE (operands[0]);
1386 scratch = operands[4];
1387 if (CONST_INT_P (operands[1])
1388 && !CONST_INT_P (operands[2]))
1390 rtx tmp = operands[1];
1392 operands[1] = operands[2];
1394 comparison = swap_condition (comparison);
1396 if (CONST_INT_P (operands[2]))
1398 HOST_WIDE_INT val = INTVAL (operands[2]);
1399 if ((val == -1 || val == -0x81)
1400 && (comparison == GT || comparison == LE))
1402 comparison = (comparison == GT) ? GE : LT;
1403 operands[2] = gen_int_mode (val + 1, mode);
1405 else if ((val == 1 || val == 0x80)
1406 && (comparison == GE || comparison == LT))
1408 comparison = (comparison == GE) ? GT : LE;
1409 operands[2] = gen_int_mode (val - 1, mode);
1411 else if (val == 1 && (comparison == GEU || comparison == LTU))
1413 comparison = (comparison == GEU) ? NE : EQ;
1414 operands[2] = CONST0_RTX (mode);
1416 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1418 comparison = (comparison == GEU) ? GTU : LEU;
1419 operands[2] = gen_int_mode (val - 1, mode);
1421 else if (val == 0 && (comparison == GTU || comparison == LEU))
1422 comparison = (comparison == GTU) ? NE : EQ;
1423 else if (mode == SImode
1424 && ((val == 0x7fffffff
1425 && (comparison == GTU || comparison == LEU))
1426 || ((unsigned HOST_WIDE_INT) val
1427 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1428 && (comparison == GEU || comparison == LTU))))
1430 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1431 operands[2] = CONST0_RTX (mode);
1435 if (can_create_pseudo_p ())
1436 operands[1] = force_reg (mode, op1);
1437 /* When we are handling DImode comparisons, we want to keep constants so
1438 that we can optimize the component comparisons; however, memory loads
1439 are better issued as a whole so that they can be scheduled well.
1440 SImode equality comparisons allow I08 constants, but only when they
1441 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1442 into a register, that register might as well be r0, and we allow the
1443 constant. If it is already in a register, this is likely to be
1444 allocated to a different hard register, thus we load the constant into
1445 a register unless it is zero. */
1446 if (!REG_P (operands[2])
1447 && (!CONST_INT_P (operands[2])
1448 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1449 && ((comparison != EQ && comparison != NE)
1450 || (REG_P (op1) && REGNO (op1) != R0_REG)
1451 || !satisfies_constraint_I08 (operands[2])))))
1453 if (scratch && GET_MODE (scratch) == mode)
1455 emit_move_insn (scratch, operands[2]);
1456 operands[2] = scratch;
1458 else if (can_create_pseudo_p ())
1459 operands[2] = force_reg (mode, operands[2]);
1465 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1467 rtx (*branch_expander) (rtx) = gen_branch_true;
1470 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1473 case NE: case LT: case LE: case LTU: case LEU:
1474 comparison = reverse_condition (comparison);
1475 branch_expander = gen_branch_false;
1478 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1479 gen_rtx_fmt_ee (comparison, SImode,
1480 operands[1], operands[2])));
1481 jump = emit_jump_insn (branch_expander (operands[3]));
1482 if (probability >= 0)
1483 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1487 /* ??? How should we distribute probabilities when more than one branch
1488 is generated. So far we only have soem ad-hoc observations:
1489 - If the operands are random, they are likely to differ in both parts.
1490 - If comparing items in a hash chain, the operands are random or equal;
1491 operation should be EQ or NE.
1492 - If items are searched in an ordered tree from the root, we can expect
1493 the highpart to be unequal about half of the time; operation should be
1494 an inequality comparison, operands non-constant, and overall probability
1495 about 50%. Likewise for quicksort.
1496 - Range checks will be often made against constants. Even if we assume for
1497 simplicity an even distribution of the non-constant operand over a
1498 sub-range here, the same probability could be generated with differently
1499 wide sub-ranges - as long as the ratio of the part of the subrange that
1500 is before the threshold to the part that comes after the threshold stays
1501 the same. Thus, we can't really tell anything here;
1502 assuming random distribution is at least simple.
1506 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1508 enum rtx_code msw_taken, msw_skip, lsw_taken;
1509 rtx skip_label = NULL_RTX;
1510 rtx op1h, op1l, op2h, op2l;
1513 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1514 rtx scratch = operands[4];
1516 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1517 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1518 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1519 op1l = gen_lowpart (SImode, operands[1]);
1520 op2l = gen_lowpart (SImode, operands[2]);
1521 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1522 prob = split_branch_probability;
1523 rev_prob = REG_BR_PROB_BASE - prob;
1526 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1527 That costs 1 cycle more when the first branch can be predicted taken,
1528 but saves us mispredicts because only one branch needs prediction.
1529 It also enables generating the cmpeqdi_t-1 pattern. */
1531 if (TARGET_CMPEQDI_T)
1533 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1534 emit_jump_insn (gen_branch_true (operands[3]));
1541 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1543 msw_skip_prob = rev_prob;
1544 if (REG_BR_PROB_BASE <= 65535)
1545 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1548 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1552 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1553 / ((HOST_WIDEST_INT) prob << 32)))
1559 if (TARGET_CMPEQDI_T)
1561 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1562 emit_jump_insn (gen_branch_false (operands[3]));
1566 msw_taken_prob = prob;
1571 msw_taken = comparison;
1572 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1574 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1575 msw_skip = swap_condition (msw_taken);
1579 if (op2l == CONST0_RTX (SImode))
1580 msw_taken = comparison;
1583 msw_taken = comparison == GE ? GT : GTU;
1584 msw_skip = swap_condition (msw_taken);
1589 msw_taken = comparison;
1590 if (op2l == CONST0_RTX (SImode))
1592 msw_skip = swap_condition (msw_taken);
1596 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1597 msw_taken = comparison;
1601 if (comparison == LE)
1603 else if (op2h != CONST0_RTX (SImode))
1607 msw_skip = swap_condition (msw_taken);
1610 default: return false;
1612 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1613 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1614 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1615 if (comparison != EQ && comparison != NE && num_branches > 1)
1617 if (!CONSTANT_P (operands[2])
1618 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1619 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1621 msw_taken_prob = prob / 2U;
1623 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1624 lsw_taken_prob = prob;
1628 msw_taken_prob = prob;
1629 msw_skip_prob = REG_BR_PROB_BASE;
1630 /* ??? If we have a constant op2h, should we use that when
1631 calculating lsw_taken_prob? */
1632 lsw_taken_prob = prob;
1637 operands[4] = NULL_RTX;
1638 if (reload_completed
1639 && ! arith_reg_or_0_operand (op2h, SImode)
1640 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
1641 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
1642 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
1644 emit_move_insn (scratch, operands[2]);
1645 operands[2] = scratch;
1647 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1648 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1649 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1651 rtx taken_label = operands[3];
1653 /* Operands were possibly modified, but msw_skip doesn't expect this.
1654 Always use the original ones. */
1655 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1661 operands[3] = skip_label = gen_label_rtx ();
1662 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1663 operands[3] = taken_label;
1667 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
1669 if (reload_completed
1670 && ! arith_reg_or_0_operand (op2l, SImode)
1671 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
1673 emit_move_insn (scratch, operands[2]);
1674 operands[2] = scratch;
1676 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1678 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1679 emit_label (skip_label);
1683 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
1686 sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
1688 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1690 insn = gen_rtx_PARALLEL (VOIDmode,
1692 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1693 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1699 /* Prepare the operands for an scc instruction; make sure that the
1700 compare has been done and the result is in T_REG. */
1702 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
1704 rtx t_reg = gen_rtx_REG (SImode, T_REG);
1705 enum rtx_code oldcode = code;
1706 enum machine_mode mode;
1708 /* First need a compare insn. */
1712 /* It isn't possible to handle this case. */
1729 if (code != oldcode)
1736 mode = GET_MODE (op0);
1737 if (mode == VOIDmode)
1738 mode = GET_MODE (op1);
1740 op0 = force_reg (mode, op0);
1741 if ((code != EQ && code != NE
1742 && (op1 != const0_rtx
1743 || code == GTU || code == GEU || code == LTU || code == LEU))
1744 || (mode == DImode && op1 != const0_rtx)
1745 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1746 op1 = force_reg (mode, op1);
1748 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
1749 gen_rtx_fmt_ee (code, SImode, op0, op1)),
1754 sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
1757 rtx target = gen_reg_rtx (SImode);
1760 gcc_assert (TARGET_SHMEDIA);
1769 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
1770 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
1780 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
1781 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
1799 rtx t2 = gen_reg_rtx (DImode);
1800 emit_insn (gen_extendsidi2 (t2, target));
1804 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
1807 /* Called from the md file, set up the operands of a compare instruction. */
1810 sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
1812 enum rtx_code code = GET_CODE (operands[0]);
1813 enum rtx_code branch_code;
1814 rtx op0 = operands[1];
1815 rtx op1 = operands[2];
1817 bool need_ccmpeq = false;
1819 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
1821 op0 = force_reg (mode, op0);
1822 op1 = force_reg (mode, op1);
1826 if (code != EQ || mode == DImode)
1828 /* Force args into regs, since we can't use constants here. */
1829 op0 = force_reg (mode, op0);
1830 if (op1 != const0_rtx || code == GTU || code == GEU)
1831 op1 = force_reg (mode, op1);
1835 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1838 || (code == LE && TARGET_IEEE && TARGET_SH2E)
1839 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
1841 tem = op0, op0 = op1, op1 = tem;
1842 code = swap_condition (code);
1845 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
1848 gcc_assert (TARGET_IEEE && TARGET_SH2E);
1853 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
1854 to EQ/GT respectively. */
1855 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
1872 branch_code = reverse_condition (code);
1878 insn = gen_rtx_SET (VOIDmode,
1879 gen_rtx_REG (SImode, T_REG),
1880 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
1882 sh_emit_set_t_insn (insn, mode);
1884 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
1886 if (branch_code == code)
1887 emit_jump_insn (gen_branch_true (operands[3]));
1889 emit_jump_insn (gen_branch_false (operands[3]));
1893 sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
1895 enum rtx_code code = GET_CODE (operands[1]);
1896 rtx op0 = operands[2];
1897 rtx op1 = operands[3];
1899 bool invert = false;
1902 op0 = force_reg (mode, op0);
1903 if ((code != EQ && code != NE
1904 && (op1 != const0_rtx
1905 || code == GTU || code == GEU || code == LTU || code == LEU))
1906 || (mode == DImode && op1 != const0_rtx)
1907 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1908 op1 = force_reg (mode, op1);
1910 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1912 if (code == LT || code == LE)
1914 code = swap_condition (code);
1915 tem = op0, op0 = op1, op1 = tem;
1921 lab = gen_label_rtx ();
1922 sh_emit_scc_to_t (EQ, op0, op1);
1923 emit_jump_insn (gen_branch_true (lab));
1940 sh_emit_scc_to_t (code, op0, op1);
1944 emit_insn (gen_movnegt (operands[0]));
1946 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
1949 /* Functions to output assembly code. */
1951 /* Return a sequence of instructions to perform DI or DF move.
1953 Since the SH cannot move a DI or DF in one instruction, we have
1954 to take care when we see overlapping source and dest registers. */
1957 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1958 enum machine_mode mode)
1960 rtx dst = operands[0];
1961 rtx src = operands[1];
1964 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
1965 return "mov.l %T1,%0\n\tmov.l %1,%0";
1967 if (register_operand (dst, mode)
1968 && register_operand (src, mode))
1970 if (REGNO (src) == MACH_REG)
1971 return "sts mach,%S0\n\tsts macl,%R0";
1973 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1974 when mov.d r1,r0 do r1->r0 then r2->r1. */
1976 if (REGNO (src) + 1 == REGNO (dst))
1977 return "mov %T1,%T0\n\tmov %1,%0";
1979 return "mov %1,%0\n\tmov %T1,%T0";
1981 else if (CONST_INT_P (src))
1983 if (INTVAL (src) < 0)
1984 output_asm_insn ("mov #-1,%S0", operands);
1986 output_asm_insn ("mov #0,%S0", operands);
1988 return "mov %1,%R0";
1990 else if (MEM_P (src))
1993 int dreg = REGNO (dst);
1994 rtx inside = XEXP (src, 0);
1996 switch (GET_CODE (inside))
1999 ptrreg = REGNO (inside);
2003 ptrreg = subreg_regno (inside);
2007 ptrreg = REGNO (XEXP (inside, 0));
2008 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2009 an offsettable address. Unfortunately, offsettable addresses use
2010 QImode to check the offset, and a QImode offsettable address
2011 requires r0 for the other operand, which is not currently
2012 supported, so we can't use the 'o' constraint.
2013 Thus we must check for and handle r0+REG addresses here.
2014 We punt for now, since this is likely very rare. */
2015 gcc_assert (!REG_P (XEXP (inside, 1)));
2019 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2021 return "mov.l %1,%0\n\tmov.l %1,%T0";
2026 /* Work out the safe way to copy. Copy into the second half first. */
2028 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2031 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2034 /* Print an instruction which would have gone into a delay slot after
2035 another instruction, but couldn't because the other instruction expanded
2036 into a sequence where putting the slot insn at the end wouldn't work. */
2039 print_slot (rtx insn)
2041 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
2043 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2047 output_far_jump (rtx insn, rtx op)
2049 struct { rtx lab, reg, op; } this_jmp;
2050 rtx braf_base_lab = NULL_RTX;
2053 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2056 this_jmp.lab = gen_label_rtx ();
2060 && offset - get_attr_length (insn) <= 32766)
2063 jump = "mov.w %O0,%1; braf %1";
2071 jump = "mov.l %O0,%1; braf %1";
2073 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2076 jump = "mov.l %O0,%1; jmp @%1";
2078 /* If we have a scratch register available, use it. */
2079 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2080 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2082 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2083 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2084 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2085 output_asm_insn (jump, &this_jmp.lab);
2086 if (dbr_sequence_length ())
2087 print_slot (final_sequence);
2089 output_asm_insn ("nop", 0);
2093 /* Output the delay slot insn first if any. */
2094 if (dbr_sequence_length ())
2095 print_slot (final_sequence);
2097 this_jmp.reg = gen_rtx_REG (SImode, 13);
2098 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2099 Fortunately, MACL is fixed and call-clobbered, and we never
2100 need its value across jumps, so save r13 in it instead of in
2103 output_asm_insn ("lds r13, macl", 0);
2105 output_asm_insn ("mov.l r13,@-r15", 0);
2106 output_asm_insn (jump, &this_jmp.lab);
2108 output_asm_insn ("sts macl, r13", 0);
2110 output_asm_insn ("mov.l @r15+,r13", 0);
2112 if (far && flag_pic && TARGET_SH2)
2114 braf_base_lab = gen_label_rtx ();
2115 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2116 CODE_LABEL_NUMBER (braf_base_lab));
2119 output_asm_insn (".align 2", 0);
2120 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2122 if (far && flag_pic)
2125 this_jmp.lab = braf_base_lab;
2126 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2129 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2133 /* Local label counter, used for constants in the pool and inside
2134 pattern branches. */
2136 static int lf = 100;
2138 /* Output code for ordinary branches. */
2141 output_branch (int logic, rtx insn, rtx *operands)
2143 switch (get_attr_length (insn))
2146 /* This can happen if filling the delay slot has caused a forward
2147 branch to exceed its range (we could reverse it, but only
2148 when we know we won't overextend other branches; this should
2149 best be handled by relaxation).
2150 It can also happen when other condbranches hoist delay slot insn
2151 from their destination, thus leading to code size increase.
2152 But the branch will still be in the range -4092..+4098 bytes. */
2157 /* The call to print_slot will clobber the operands. */
2158 rtx op0 = operands[0];
2160 /* If the instruction in the delay slot is annulled (true), then
2161 there is no delay slot where we can put it now. The only safe
2162 place for it is after the label. final will do that by default. */
2165 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2166 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2168 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2169 ASSEMBLER_DIALECT ? "/" : ".", label);
2170 print_slot (final_sequence);
2173 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2175 output_asm_insn ("bra\t%l0", &op0);
2176 fprintf (asm_out_file, "\tnop\n");
2177 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2181 /* When relaxing, handle this like a short branch. The linker
2182 will fix it up if it still doesn't fit after relaxation. */
2184 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2186 /* These are for SH2e, in which we have to account for the
2187 extra nop because of the hardware bug in annulled branches. */
2193 gcc_assert (!final_sequence
2194 || !(INSN_ANNULLED_BRANCH_P
2195 (XVECEXP (final_sequence, 0, 0))));
2196 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2198 ASSEMBLER_DIALECT ? "/" : ".", label);
2199 fprintf (asm_out_file, "\tnop\n");
2200 output_asm_insn ("bra\t%l0", operands);
2201 fprintf (asm_out_file, "\tnop\n");
2202 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2206 /* When relaxing, fall through. */
2211 sprintf (buffer, "b%s%ss\t%%l0",
2213 ASSEMBLER_DIALECT ? "/" : ".");
2214 output_asm_insn (buffer, &operands[0]);
2219 /* There should be no longer branches now - that would
2220 indicate that something has destroyed the branches set
2221 up in machine_dependent_reorg. */
2226 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2227 fill in operands 9 as a label to the successor insn.
2228 We try to use jump threading where possible.
2229 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2230 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2231 follow jmp and bt, if the address is in range. */
2233 output_branchy_insn (enum rtx_code code, const char *templ,
2234 rtx insn, rtx *operands)
2236 rtx next_insn = NEXT_INSN (insn);
2238 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2240 rtx src = SET_SRC (PATTERN (next_insn));
2241 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2243 /* Following branch not taken */
2244 operands[9] = gen_label_rtx ();
2245 emit_label_after (operands[9], next_insn);
2246 INSN_ADDRESSES_NEW (operands[9],
2247 INSN_ADDRESSES (INSN_UID (next_insn))
2248 + get_attr_length (next_insn));
2253 int offset = (branch_dest (next_insn)
2254 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2255 if (offset >= -252 && offset <= 258)
2257 if (GET_CODE (src) == IF_THEN_ELSE)
2259 src = XEXP (src, 1);
2265 operands[9] = gen_label_rtx ();
2266 emit_label_after (operands[9], insn);
2267 INSN_ADDRESSES_NEW (operands[9],
2268 INSN_ADDRESSES (INSN_UID (insn))
2269 + get_attr_length (insn));
2274 output_ieee_ccmpeq (rtx insn, rtx *operands)
2276 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2280 /* Output the start of the assembler file. */
2283 sh_file_start (void)
2285 default_file_start ();
2288 /* Declare the .directive section before it is used. */
2289 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2290 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2294 /* We need to show the text section with the proper
2295 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2296 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2297 will complain. We can teach GAS specifically about the
2298 default attributes for our choice of text section, but
2299 then we would have to change GAS again if/when we change
2300 the text section name. */
2301 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2303 /* Switch to the data section so that the coffsem symbol
2304 isn't in the text section. */
2305 switch_to_section (data_section);
2307 if (TARGET_LITTLE_ENDIAN)
2308 fputs ("\t.little\n", asm_out_file);
2312 if (TARGET_SHCOMPACT)
2313 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2314 else if (TARGET_SHMEDIA)
2315 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2316 TARGET_SHMEDIA64 ? 64 : 32);
2320 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2323 unspec_caller_rtx_p (rtx pat)
2328 split_const (pat, &base, &offset);
2329 if (GET_CODE (base) == UNSPEC)
2331 if (XINT (base, 1) == UNSPEC_CALLER)
2333 for (i = 0; i < XVECLEN (base, 0); i++)
2334 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2340 /* Indicate that INSN cannot be duplicated. This is true for insn
2341 that generates a unique label. */
2344 sh_cannot_copy_insn_p (rtx insn)
2348 if (!reload_completed || !flag_pic)
2351 if (!NONJUMP_INSN_P (insn))
2353 if (asm_noperands (insn) >= 0)
2356 pat = PATTERN (insn);
2357 if (GET_CODE (pat) != SET)
2359 pat = SET_SRC (pat);
2361 if (unspec_caller_rtx_p (pat))
2367 /* Actual number of instructions used to make a shift by N. */
2368 static const char ashiftrt_insns[] =
2369 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2371 /* Left shift and logical right shift are the same. */
2372 static const char shift_insns[] =
2373 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2375 /* Individual shift amounts needed to get the above length sequences.
2376 One bit right shifts clobber the T bit, so when possible, put one bit
2377 shifts in the middle of the sequence, so the ends are eligible for
2378 branch delay slots. */
2379 static const short shift_amounts[32][5] = {
2380 {0}, {1}, {2}, {2, 1},
2381 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2382 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2383 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2384 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2385 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2386 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2387 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2389 /* Likewise, but for shift amounts < 16, up to three highmost bits
2390 might be clobbered. This is typically used when combined with some
2391 kind of sign or zero extension. */
2393 static const char ext_shift_insns[] =
2394 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2396 static const short ext_shift_amounts[32][4] = {
2397 {0}, {1}, {2}, {2, 1},
2398 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2399 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2400 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2401 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2402 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2403 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2404 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2406 /* Assuming we have a value that has been sign-extended by at least one bit,
2407 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2408 to shift it by N without data loss, and quicker than by other means? */
2409 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2411 /* This is used in length attributes in sh.md to help compute the length
2412 of arbitrary constant shift instructions. */
2415 shift_insns_rtx (rtx insn)
2417 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2418 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2419 enum rtx_code shift_code = GET_CODE (set_src);
2424 return ashiftrt_insns[shift_count];
2427 return shift_insns[shift_count];
2433 /* Return the cost of a shift. */
2443 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2445 if (GET_MODE (x) == DImode
2446 && CONST_INT_P (XEXP (x, 1))
2447 && INTVAL (XEXP (x, 1)) == 1)
2450 /* Everything else is invalid, because there is no pattern for it. */
2453 /* If shift by a non constant, then this will be expensive. */
2454 if (!CONST_INT_P (XEXP (x, 1)))
2455 return SH_DYNAMIC_SHIFT_COST;
2457 /* Otherwise, return the true cost in instructions. Cope with out of range
2458 shift counts more or less arbitrarily. */
2459 value = INTVAL (XEXP (x, 1)) & 31;
2461 if (GET_CODE (x) == ASHIFTRT)
2463 int cost = ashiftrt_insns[value];
2464 /* If SH3, then we put the constant in a reg and use shad. */
2465 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2466 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2470 return shift_insns[value];
2473 /* Return the cost of an AND operation. */
2480 /* Anding with a register is a single cycle and instruction. */
2481 if (!CONST_INT_P (XEXP (x, 1)))
2484 i = INTVAL (XEXP (x, 1));
2488 if (satisfies_constraint_I10 (XEXP (x, 1))
2489 || satisfies_constraint_J16 (XEXP (x, 1)))
2492 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
2495 /* These constants are single cycle extu.[bw] instructions. */
2496 if (i == 0xff || i == 0xffff)
2498 /* Constants that can be used in an and immediate instruction in a single
2499 cycle, but this requires r0, so make it a little more expensive. */
2500 if (CONST_OK_FOR_K08 (i))
2502 /* Constants that can be loaded with a mov immediate and an and.
2503 This case is probably unnecessary. */
2504 if (CONST_OK_FOR_I08 (i))
2506 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2507 This case is probably unnecessary. */
2511 /* Return the cost of an addition or a subtraction. */
2516 /* Adding a register is a single cycle insn. */
2517 if (REG_P (XEXP (x, 1))
2518 || GET_CODE (XEXP (x, 1)) == SUBREG)
2521 /* Likewise for small constants. */
2522 if (CONST_INT_P (XEXP (x, 1))
2523 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2527 switch (GET_CODE (XEXP (x, 1)))
2532 return TARGET_SHMEDIA64 ? 5 : 3;
2535 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2537 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2539 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2547 /* Any other constant requires a 2 cycle pc-relative load plus an
2552 /* Return the cost of a multiply. */
2554 multcosts (rtx x ATTRIBUTE_UNUSED)
2556 if (sh_multcost >= 0)
2559 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2560 accept constants. Ideally, we would use a cost of one or two and
2561 add the cost of the operand, but disregard the latter when inside loops
2562 and loop invariant code motion is still to follow.
2563 Using a multiply first and splitting it later if it's a loss
2564 doesn't work because of different sign / zero extension semantics
2565 of multiplies vs. shifts. */
2566 return TARGET_SMALLCODE ? 2 : 3;
2570 /* We have a mul insn, so we can never take more than the mul and the
2571 read of the mac reg, but count more because of the latency and extra
2573 if (TARGET_SMALLCODE)
2578 /* If we're aiming at small code, then just count the number of
2579 insns in a multiply call sequence. */
2580 if (TARGET_SMALLCODE)
2583 /* Otherwise count all the insns in the routine we'd be calling too. */
2587 /* Compute a (partial) cost for rtx X. Return true if the complete
2588 cost has been computed, and false if subexpressions should be
2589 scanned. In either case, *TOTAL contains the cost result. */
2592 sh_rtx_costs (rtx x, int code, int outer_code, int *total,
2593 bool speed ATTRIBUTE_UNUSED)
2600 if (INTVAL (x) == 0)
2602 else if (outer_code == AND && and_operand ((x), DImode))
2604 else if ((outer_code == IOR || outer_code == XOR
2605 || outer_code == PLUS)
2606 && CONST_OK_FOR_I10 (INTVAL (x)))
2608 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2609 *total = COSTS_N_INSNS (outer_code != SET);
2610 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2611 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2612 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2613 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2615 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2618 if (CONST_OK_FOR_I08 (INTVAL (x)))
2620 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2621 && CONST_OK_FOR_K08 (INTVAL (x)))
2623 /* prepare_cmp_insn will force costly constants int registers before
2624 the cbranch[sd]i4 patterns can see them, so preserve potentially
2625 interesting ones not covered by I08 above. */
2626 else if (outer_code == COMPARE
2627 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2628 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2629 || INTVAL (x) == 0x7fffffff
2630 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2639 if (TARGET_SHMEDIA64)
2640 *total = COSTS_N_INSNS (4);
2641 else if (TARGET_SHMEDIA32)
2642 *total = COSTS_N_INSNS (2);
2649 *total = COSTS_N_INSNS (4);
2650 /* prepare_cmp_insn will force costly constants int registers before
2651 the cbranchdi4 pattern can see them, so preserve potentially
2652 interesting ones. */
2653 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2659 if (x == CONST0_RTX (GET_MODE (x)))
2661 else if (sh_1el_vec (x, VOIDmode))
2662 *total = outer_code != SET;
2663 if (sh_rep_vec (x, VOIDmode))
2664 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2665 + (outer_code != SET));
2666 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2671 *total = COSTS_N_INSNS (addsubcosts (x));
2675 *total = COSTS_N_INSNS (andcosts (x));
2679 *total = COSTS_N_INSNS (multcosts (x));
2685 *total = COSTS_N_INSNS (shiftcosts (x));
2692 *total = COSTS_N_INSNS (20);
2696 if (sh_1el_vec (x, VOIDmode))
2697 *total = outer_code != SET;
2698 if (sh_rep_vec (x, VOIDmode))
2699 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2700 + (outer_code != SET));
2701 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2714 /* Compute the cost of an address. For the SH, all valid addresses are
2715 the same cost. Use a slightly higher cost for reg + reg addressing,
2716 since it increases pressure on r0. */
2719 sh_address_cost (rtx X,
2720 bool speed ATTRIBUTE_UNUSED)
2722 return (GET_CODE (X) == PLUS
2723 && ! CONSTANT_P (XEXP (X, 1))
2724 && ! TARGET_SHMEDIA ? 1 : 0);
2727 /* Code to expand a shift. */
2730 gen_ashift (int type, int n, rtx reg)
2732 /* Negative values here come from the shift_amounts array. */
2745 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
2749 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
2751 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
2754 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
2759 /* Same for HImode */
2762 gen_ashift_hi (int type, int n, rtx reg)
2764 /* Negative values here come from the shift_amounts array. */
2778 /* We don't have HImode right shift operations because using the
2779 ordinary 32 bit shift instructions for that doesn't generate proper
2780 zero/sign extension.
2781 gen_ashift_hi is only called in contexts where we know that the
2782 sign extension works out correctly. */
2785 if (GET_CODE (reg) == SUBREG)
2787 offset = SUBREG_BYTE (reg);
2788 reg = SUBREG_REG (reg);
2790 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
2794 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
2799 /* Output RTL to split a constant shift into its component SH constant
2800 shift instructions. */
2803 gen_shifty_op (int code, rtx *operands)
2805 int value = INTVAL (operands[2]);
2808 /* Truncate the shift count in case it is out of bounds. */
2813 if (code == LSHIFTRT)
2815 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2816 emit_insn (gen_movt (operands[0]));
2819 else if (code == ASHIFT)
2821 /* There is a two instruction sequence for 31 bit left shifts,
2822 but it requires r0. */
2823 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
2825 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
2826 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2831 else if (value == 0)
2833 /* This can happen even when optimizing, if there were subregs before
2834 reload. Don't output a nop here, as this is never optimized away;
2835 use a no-op move instead. */
2836 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
2840 max = shift_insns[value];
2841 for (i = 0; i < max; i++)
2842 gen_ashift (code, shift_amounts[value][i], operands[0]);
2845 /* Same as above, but optimized for values where the topmost bits don't
2849 gen_shifty_hi_op (int code, rtx *operands)
2851 int value = INTVAL (operands[2]);
2853 void (*gen_fun) (int, int, rtx);
2855 /* This operation is used by and_shl for SImode values with a few
2856 high bits known to be cleared. */
2860 emit_insn (gen_nop ());
2864 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
2867 max = ext_shift_insns[value];
2868 for (i = 0; i < max; i++)
2869 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2872 /* When shifting right, emit the shifts in reverse order, so that
2873 solitary negative values come first. */
2874 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
2875 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2878 /* Output RTL for an arithmetic right shift. */
2880 /* ??? Rewrite to use super-optimizer sequences. */
2883 expand_ashiftrt (rtx *operands)
2891 if (!CONST_INT_P (operands[2]))
2893 rtx count = copy_to_mode_reg (SImode, operands[2]);
2894 emit_insn (gen_negsi2 (count, count));
2895 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2898 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
2899 > 1 + SH_DYNAMIC_SHIFT_COST)
2902 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
2903 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2907 if (!CONST_INT_P (operands[2]))
2910 value = INTVAL (operands[2]) & 31;
2914 /* If we are called from abs expansion, arrange things so that we
2915 we can use a single MT instruction that doesn't clobber the source,
2916 if LICM can hoist out the load of the constant zero. */
2917 if (currently_expanding_to_rtl)
2919 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
2921 emit_insn (gen_mov_neg_si_t (operands[0]));
2924 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
2927 else if (value >= 16 && value <= 19)
2929 wrk = gen_reg_rtx (SImode);
2930 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
2933 gen_ashift (ASHIFTRT, 1, wrk);
2934 emit_move_insn (operands[0], wrk);
2937 /* Expand a short sequence inline, longer call a magic routine. */
2938 else if (value <= 5)
2940 wrk = gen_reg_rtx (SImode);
2941 emit_move_insn (wrk, operands[1]);
2943 gen_ashift (ASHIFTRT, 1, wrk);
2944 emit_move_insn (operands[0], wrk);
2948 wrk = gen_reg_rtx (Pmode);
2950 /* Load the value into an arg reg and call a helper. */
2951 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2952 sprintf (func, "__ashiftrt_r4_%d", value);
2953 function_symbol (wrk, func, SFUNC_STATIC);
2954 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
2955 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
2960 sh_dynamicalize_shift_p (rtx count)
2962 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
2965 /* Try to find a good way to implement the combiner pattern
2966 [(set (match_operand:SI 0 "register_operand" "r")
2967 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2968 (match_operand:SI 2 "const_int_operand" "n"))
2969 (match_operand:SI 3 "const_int_operand" "n"))) .
2970 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
2971 return 0 for simple right / left or left/right shift combination.
2972 return 1 for a combination of shifts with zero_extend.
2973 return 2 for a combination of shifts with an AND that needs r0.
2974 return 3 for a combination of shifts with an AND that needs an extra
2975 scratch register, when the three highmost bits of the AND mask are clear.
2976 return 4 for a combination of shifts with an AND that needs an extra
2977 scratch register, when any of the three highmost bits of the AND mask
2979 If ATTRP is set, store an initial right shift width in ATTRP[0],
2980 and the instruction length in ATTRP[1] . These values are not valid
2982 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
2983 shift_amounts for the last shift value that is to be used before the
2986 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
2988 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
2989 int left = INTVAL (left_rtx), right;
2991 int cost, best_cost = 10000;
2992 int best_right = 0, best_len = 0;
2996 if (left < 0 || left > 31)
2998 if (CONST_INT_P (mask_rtx))
2999 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3001 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3002 /* Can this be expressed as a right shift / left shift pair? */
3003 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3004 right = exact_log2 (lsb);
3005 mask2 = ~(mask + lsb - 1);
3006 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3007 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3009 best_cost = shift_insns[right] + shift_insns[right + left];
3010 /* mask has no trailing zeroes <==> ! right */
3011 else if (! right && mask2 == ~(lsb2 - 1))
3013 int late_right = exact_log2 (lsb2);
3014 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3016 /* Try to use zero extend. */
3017 if (mask2 == ~(lsb2 - 1))
3021 for (width = 8; width <= 16; width += 8)
3023 /* Can we zero-extend right away? */
3024 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3027 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3028 if (cost < best_cost)
3039 /* ??? Could try to put zero extend into initial right shift,
3040 or even shift a bit left before the right shift. */
3041 /* Determine value of first part of left shift, to get to the
3042 zero extend cut-off point. */
3043 first = width - exact_log2 (lsb2) + right;
3044 if (first >= 0 && right + left - first >= 0)
3046 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3047 + ext_shift_insns[right + left - first];
3048 if (cost < best_cost)
3060 /* Try to use r0 AND pattern */
3061 for (i = 0; i <= 2; i++)
3065 if (! CONST_OK_FOR_K08 (mask >> i))
3067 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3068 if (cost < best_cost)
3073 best_len = cost - 1;
3076 /* Try to use a scratch register to hold the AND operand. */
3077 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3078 for (i = 0; i <= 2; i++)
3082 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3083 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
3084 if (cost < best_cost)
3089 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
3095 attrp[0] = best_right;
3096 attrp[1] = best_len;
3101 /* This is used in length attributes of the unnamed instructions
3102 corresponding to shl_and_kind return values of 1 and 2. */
3104 shl_and_length (rtx insn)
3106 rtx set_src, left_rtx, mask_rtx;
3109 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3110 left_rtx = XEXP (XEXP (set_src, 0), 1);
3111 mask_rtx = XEXP (set_src, 1);
3112 shl_and_kind (left_rtx, mask_rtx, attributes);
3113 return attributes[1];
3116 /* This is used in length attribute of the and_shl_scratch instruction. */
3119 shl_and_scr_length (rtx insn)
3121 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3122 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
3123 rtx op = XEXP (set_src, 0);
3124 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
3125 op = XEXP (XEXP (op, 0), 0);
3126 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
3129 /* Generate rtl for instructions for which shl_and_kind advised a particular
3130 method of generating them, i.e. returned zero. */
3133 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3136 unsigned HOST_WIDE_INT mask;
3137 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3138 int right, total_shift;
3139 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3141 right = attributes[0];
3142 total_shift = INTVAL (left_rtx) + right;
3143 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3150 int first = attributes[2];
3155 emit_insn ((mask << right) <= 0xff
3156 ? gen_zero_extendqisi2 (dest,
3157 gen_lowpart (QImode, source))
3158 : gen_zero_extendhisi2 (dest,
3159 gen_lowpart (HImode, source)));
3163 emit_insn (gen_movsi (dest, source));
3167 operands[2] = GEN_INT (right);
3168 gen_shifty_hi_op (LSHIFTRT, operands);
3172 operands[2] = GEN_INT (first);
3173 gen_shifty_hi_op (ASHIFT, operands);
3174 total_shift -= first;
3178 emit_insn (mask <= 0xff
3179 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3180 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3181 if (total_shift > 0)
3183 operands[2] = GEN_INT (total_shift);
3184 gen_shifty_hi_op (ASHIFT, operands);
3189 shift_gen_fun = gen_shifty_op;
3191 /* If the topmost bit that matters is set, set the topmost bits
3192 that don't matter. This way, we might be able to get a shorter
3194 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3195 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3197 /* Don't expand fine-grained when combining, because that will
3198 make the pattern fail. */
3199 if (currently_expanding_to_rtl
3200 || reload_in_progress || reload_completed)
3204 /* Cases 3 and 4 should be handled by this split
3205 only while combining */
3206 gcc_assert (kind <= 2);
3209 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3212 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3217 operands[2] = GEN_INT (total_shift);
3218 shift_gen_fun (ASHIFT, operands);
3225 if (kind != 4 && total_shift < 16)
3227 neg = -ext_shift_amounts[total_shift][1];
3229 neg -= ext_shift_amounts[total_shift][2];
3233 emit_insn (gen_and_shl_scratch (dest, source,
3236 GEN_INT (total_shift + neg),
3238 emit_insn (gen_movsi (dest, dest));
3245 /* Try to find a good way to implement the combiner pattern
3246 [(set (match_operand:SI 0 "register_operand" "=r")
3247 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3248 (match_operand:SI 2 "const_int_operand" "n")
3249 (match_operand:SI 3 "const_int_operand" "n")
3251 (clobber (reg:SI T_REG))]
3252 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3253 return 0 for simple left / right shift combination.
3254 return 1 for left shift / 8 bit sign extend / left shift.
3255 return 2 for left shift / 16 bit sign extend / left shift.
3256 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3257 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3258 return 5 for left shift / 16 bit sign extend / right shift
3259 return 6 for < 8 bit sign extend / left shift.
3260 return 7 for < 8 bit sign extend / left shift / single right shift.
3261 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3264 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3266 int left, size, insize, ext;
3267 int cost = 0, best_cost;
3270 left = INTVAL (left_rtx);
3271 size = INTVAL (size_rtx);
3272 insize = size - left;
3273 gcc_assert (insize > 0);
3274 /* Default to left / right shift. */
3276 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3279 /* 16 bit shift / sign extend / 16 bit shift */
3280 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3281 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3282 below, by alternative 3 or something even better. */
3283 if (cost < best_cost)
3289 /* Try a plain sign extend between two shifts. */
3290 for (ext = 16; ext >= insize; ext -= 8)
3294 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3295 if (cost < best_cost)
3297 kind = ext / (unsigned) 8;
3301 /* Check if we can do a sloppy shift with a final signed shift
3302 restoring the sign. */
3303 if (EXT_SHIFT_SIGNED (size - ext))
3304 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3305 /* If not, maybe it's still cheaper to do the second shift sloppy,
3306 and do a final sign extend? */
3307 else if (size <= 16)
3308 cost = ext_shift_insns[ext - insize] + 1
3309 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3312 if (cost < best_cost)
3314 kind = ext / (unsigned) 8 + 2;
3318 /* Check if we can sign extend in r0 */
3321 cost = 3 + shift_insns[left];
3322 if (cost < best_cost)
3327 /* Try the same with a final signed shift. */
3330 cost = 3 + ext_shift_insns[left + 1] + 1;
3331 if (cost < best_cost)
3340 /* Try to use a dynamic shift. */
3341 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3342 if (cost < best_cost)
3353 /* Function to be used in the length attribute of the instructions
3354 implementing this pattern. */
3357 shl_sext_length (rtx insn)
3359 rtx set_src, left_rtx, size_rtx;
3362 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3363 left_rtx = XEXP (XEXP (set_src, 0), 1);
3364 size_rtx = XEXP (set_src, 1);
3365 shl_sext_kind (left_rtx, size_rtx, &cost);
3369 /* Generate rtl for this pattern */
3372 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3375 int left, size, insize, cost;
3378 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3379 left = INTVAL (left_rtx);
3380 size = INTVAL (size_rtx);
3381 insize = size - left;
3389 int ext = kind & 1 ? 8 : 16;
3390 int shift2 = size - ext;
3392 /* Don't expand fine-grained when combining, because that will
3393 make the pattern fail. */
3394 if (! currently_expanding_to_rtl
3395 && ! reload_in_progress && ! reload_completed)
3397 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3398 emit_insn (gen_movsi (dest, source));
3402 emit_insn (gen_movsi (dest, source));
3406 operands[2] = GEN_INT (ext - insize);
3407 gen_shifty_hi_op (ASHIFT, operands);
3410 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3411 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3416 operands[2] = GEN_INT (shift2);
3417 gen_shifty_op (ASHIFT, operands);
3424 if (EXT_SHIFT_SIGNED (shift2))
3426 operands[2] = GEN_INT (shift2 + 1);
3427 gen_shifty_op (ASHIFT, operands);
3428 operands[2] = const1_rtx;
3429 gen_shifty_op (ASHIFTRT, operands);
3432 operands[2] = GEN_INT (shift2);
3433 gen_shifty_hi_op (ASHIFT, operands);
3437 operands[2] = GEN_INT (-shift2);
3438 gen_shifty_hi_op (LSHIFTRT, operands);
3440 emit_insn (size <= 8
3441 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3442 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3449 if (! currently_expanding_to_rtl
3450 && ! reload_in_progress && ! reload_completed)
3451 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3455 operands[2] = GEN_INT (16 - insize);
3456 gen_shifty_hi_op (ASHIFT, operands);
3457 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3459 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3461 gen_ashift (ASHIFTRT, 1, dest);
3466 /* Don't expand fine-grained when combining, because that will
3467 make the pattern fail. */
3468 if (! currently_expanding_to_rtl
3469 && ! reload_in_progress && ! reload_completed)
3471 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3472 emit_insn (gen_movsi (dest, source));
3475 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3476 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3477 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3479 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3480 gen_shifty_op (ASHIFT, operands);
3482 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3490 /* Prefix a symbol_ref name with "datalabel". */
3493 gen_datalabel_ref (rtx sym)
3497 if (GET_CODE (sym) == LABEL_REF)
3498 return gen_rtx_CONST (GET_MODE (sym),
3499 gen_rtx_UNSPEC (GET_MODE (sym),
3503 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3505 str = XSTR (sym, 0);
3506 /* Share all SYMBOL_REF strings with the same value - that is important
3508 str = IDENTIFIER_POINTER (get_identifier (str));
3509 XSTR (sym, 0) = str;
3515 static alloc_pool label_ref_list_pool;
3517 typedef struct label_ref_list_d
3520 struct label_ref_list_d *next;
3521 } *label_ref_list_t;
3523 /* The SH cannot load a large constant into a register, constants have to
3524 come from a pc relative load. The reference of a pc relative load
3525 instruction must be less than 1k in front of the instruction. This
3526 means that we often have to dump a constant inside a function, and
3527 generate code to branch around it.
3529 It is important to minimize this, since the branches will slow things
3530 down and make things bigger.
3532 Worst case code looks like:
3550 We fix this by performing a scan before scheduling, which notices which
3551 instructions need to have their operands fetched from the constant table
3552 and builds the table.
3556 scan, find an instruction which needs a pcrel move. Look forward, find the
3557 last barrier which is within MAX_COUNT bytes of the requirement.
3558 If there isn't one, make one. Process all the instructions between
3559 the find and the barrier.
3561 In the above example, we can tell that L3 is within 1k of L1, so
3562 the first move can be shrunk from the 3 insn+constant sequence into
3563 just 1 insn, and the constant moved to L3 to make:
3574 Then the second move becomes the target for the shortening process. */
3578 rtx value; /* Value in table. */
3579 rtx label; /* Label of value. */
3580 label_ref_list_t wend; /* End of window. */
3581 enum machine_mode mode; /* Mode of value. */
3583 /* True if this constant is accessed as part of a post-increment
3584 sequence. Note that HImode constants are never accessed in this way. */
3585 bool part_of_sequence_p;
3588 /* The maximum number of constants that can fit into one pool, since
3589 constants in the range 0..510 are at least 2 bytes long, and in the
3590 range from there to 1018 at least 4 bytes. */
3592 #define MAX_POOL_SIZE 372
3593 static pool_node pool_vector[MAX_POOL_SIZE];
3594 static int pool_size;
3595 static rtx pool_window_label;
3596 static int pool_window_last;
3598 static int max_labelno_before_reorg;
3600 /* ??? If we need a constant in HImode which is the truncated value of a
3601 constant we need in SImode, we could combine the two entries thus saving
3602 two bytes. Is this common enough to be worth the effort of implementing
3605 /* ??? This stuff should be done at the same time that we shorten branches.
3606 As it is now, we must assume that all branches are the maximum size, and
3607 this causes us to almost always output constant pools sooner than
3610 /* Add a constant to the pool and return its label. */
3613 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3617 label_ref_list_t ref, newref;
3619 /* First see if we've already got it. */
3620 for (i = 0; i < pool_size; i++)
3622 if (x->code == pool_vector[i].value->code
3623 && mode == pool_vector[i].mode)
3625 if (x->code == CODE_LABEL)
3627 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3630 if (rtx_equal_p (x, pool_vector[i].value))
3635 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3637 new_rtx = gen_label_rtx ();
3638 LABEL_REFS (new_rtx) = pool_vector[i].label;
3639 pool_vector[i].label = lab = new_rtx;
3641 if (lab && pool_window_label)
3643 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3644 newref->label = pool_window_label;
3645 ref = pool_vector[pool_window_last].wend;
3647 pool_vector[pool_window_last].wend = newref;
3650 pool_window_label = new_rtx;
3651 pool_window_last = i;
3657 /* Need a new one. */
3658 pool_vector[pool_size].value = x;
3659 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3662 pool_vector[pool_size - 1].part_of_sequence_p = true;
3665 lab = gen_label_rtx ();
3666 pool_vector[pool_size].mode = mode;
3667 pool_vector[pool_size].label = lab;
3668 pool_vector[pool_size].wend = NULL;
3669 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3670 if (lab && pool_window_label)
3672 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3673 newref->label = pool_window_label;
3674 ref = pool_vector[pool_window_last].wend;
3676 pool_vector[pool_window_last].wend = newref;
3679 pool_window_label = lab;
3680 pool_window_last = pool_size;
3685 /* Output the literal table. START, if nonzero, is the first instruction
3686 this table is needed for, and also indicates that there is at least one
3687 casesi_worker_2 instruction; We have to emit the operand3 labels from
3688 these insns at a 4-byte aligned position. BARRIER is the barrier
3689 after which we are to place the table. */
3692 dump_table (rtx start, rtx barrier)
3698 label_ref_list_t ref;
3701 /* Do two passes, first time dump out the HI sized constants. */
3703 for (i = 0; i < pool_size; i++)
3705 pool_node *p = &pool_vector[i];
3707 if (p->mode == HImode)
3711 scan = emit_insn_after (gen_align_2 (), scan);
3714 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3715 scan = emit_label_after (lab, scan);
3716 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
3718 for (ref = p->wend; ref; ref = ref->next)
3721 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3724 else if (p->mode == DFmode)
3732 scan = emit_insn_after (gen_align_4 (), scan);
3734 for (; start != barrier; start = NEXT_INSN (start))
3735 if (NONJUMP_INSN_P (start)
3736 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
3738 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
3739 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
3741 scan = emit_label_after (lab, scan);
3744 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
3746 rtx align_insn = NULL_RTX;
3748 scan = emit_label_after (gen_label_rtx (), scan);
3749 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3752 for (i = 0; i < pool_size; i++)
3754 pool_node *p = &pool_vector[i];
3762 if (align_insn && !p->part_of_sequence_p)
3764 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3765 emit_label_before (lab, align_insn);
3766 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
3768 for (ref = p->wend; ref; ref = ref->next)
3771 emit_insn_before (gen_consttable_window_end (lab),
3774 delete_insn (align_insn);
3775 align_insn = NULL_RTX;
3780 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3781 scan = emit_label_after (lab, scan);
3782 scan = emit_insn_after (gen_consttable_4 (p->value,
3784 need_align = ! need_align;
3790 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3795 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3796 scan = emit_label_after (lab, scan);
3797 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3804 if (p->mode != HImode)
3806 for (ref = p->wend; ref; ref = ref->next)
3809 scan = emit_insn_after (gen_consttable_window_end (lab),
3818 for (i = 0; i < pool_size; i++)
3820 pool_node *p = &pool_vector[i];
3831 scan = emit_label_after (gen_label_rtx (), scan);
3832 scan = emit_insn_after (gen_align_4 (), scan);
3834 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3835 scan = emit_label_after (lab, scan);
3836 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
3844 scan = emit_label_after (gen_label_rtx (), scan);
3845 scan = emit_insn_after (gen_align_4 (), scan);
3847 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3848 scan = emit_label_after (lab, scan);
3849 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3856 if (p->mode != HImode)
3858 for (ref = p->wend; ref; ref = ref->next)
3861 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3866 scan = emit_insn_after (gen_consttable_end (), scan);
3867 scan = emit_barrier_after (scan);
3869 pool_window_label = NULL_RTX;
3870 pool_window_last = 0;
3873 /* Return nonzero if constant would be an ok source for a
3874 mov.w instead of a mov.l. */
3879 return (CONST_INT_P (src)
3880 && INTVAL (src) >= -32768
3881 && INTVAL (src) <= 32767);
3884 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
3886 /* Nonzero if the insn is a move instruction which needs to be fixed. */
3888 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
3889 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
3890 need to fix it if the input value is CONST_OK_FOR_I08. */
3893 broken_move (rtx insn)
3895 if (NONJUMP_INSN_P (insn))
3897 rtx pat = PATTERN (insn);
3898 if (GET_CODE (pat) == PARALLEL)
3899 pat = XVECEXP (pat, 0, 0);
3900 if (GET_CODE (pat) == SET
3901 /* We can load any 8-bit value if we don't care what the high
3902 order bits end up as. */
3903 && GET_MODE (SET_DEST (pat)) != QImode
3904 && (CONSTANT_P (SET_SRC (pat))
3905 /* Match mova_const. */
3906 || (GET_CODE (SET_SRC (pat)) == UNSPEC
3907 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
3908 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
3910 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
3911 && (fp_zero_operand (SET_SRC (pat))
3912 || fp_one_operand (SET_SRC (pat)))
3913 /* ??? If this is a -m4 or -m4-single compilation, in general
3914 we don't know the current setting of fpscr, so disable fldi.
3915 There is an exception if this was a register-register move
3916 before reload - and hence it was ascertained that we have
3917 single precision setting - and in a post-reload optimization
3918 we changed this to do a constant load. In that case
3919 we don't have an r0 clobber, hence we must use fldi. */
3920 && (! TARGET_SH4 || TARGET_FMOVD
3921 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
3923 && REG_P (SET_DEST (pat))
3924 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
3926 && GET_MODE (SET_DEST (pat)) == SImode
3927 && (satisfies_constraint_I20 (SET_SRC (pat))
3928 || satisfies_constraint_I28 (SET_SRC (pat))))
3929 && ! satisfies_constraint_I08 (SET_SRC (pat)))
3939 return (NONJUMP_INSN_P (insn)
3940 && GET_CODE (PATTERN (insn)) == SET
3941 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
3942 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
3943 /* Don't match mova_const. */
3944 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
3947 /* Fix up a mova from a switch that went out of range. */
3949 fixup_mova (rtx mova)
3951 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
3954 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
3955 INSN_CODE (mova) = -1;
3960 rtx lab = gen_label_rtx ();
3961 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
3965 worker = NEXT_INSN (worker);
3967 && !LABEL_P (worker)
3968 && !JUMP_P (worker));
3969 } while (NOTE_P (worker)
3970 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
3971 wpat = PATTERN (worker);
3972 wpat0 = XVECEXP (wpat, 0, 0);
3973 wpat1 = XVECEXP (wpat, 0, 1);
3974 wsrc = SET_SRC (wpat0);
3975 PATTERN (worker) = (gen_casesi_worker_2
3976 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
3977 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
3979 INSN_CODE (worker) = -1;
3980 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3981 base = gen_rtx_LABEL_REF (Pmode, lab);
3982 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
3983 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
3984 INSN_CODE (mova) = -1;
3988 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
3989 *num_mova, and check if the new mova is not nested within the first one.
3990 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
3991 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
3993 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
3995 int n_addr = 0; /* Initialization to shut up spurious warning. */
3996 int f_target, n_target = 0; /* Likewise. */
4000 /* If NEW_MOVA has no address yet, it will be handled later. */
4001 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4004 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4005 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4006 if (n_addr > n_target || n_addr + 1022 < n_target)
4008 /* Change the mova into a load.
4009 broken_move will then return true for it. */
4010 fixup_mova (new_mova);
4016 *first_mova = new_mova;
4021 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4026 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4027 > n_target - n_addr)
4029 fixup_mova (*first_mova);
4034 fixup_mova (new_mova);
4039 /* Find the last barrier from insn FROM which is close enough to hold the
4040 constant pool. If we can't find one, then create one near the end of
4044 find_barrier (int num_mova, rtx mova, rtx from)
4053 int leading_mova = num_mova;
4054 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
4059 /* For HImode: range is 510, add 4 because pc counts from address of
4060 second instruction after this one, subtract 2 for the jump instruction
4061 that we may need to emit before the table, subtract 2 for the instruction
4062 that fills the jump delay slot (in very rare cases, reorg will take an
4063 instruction from after the constant pool or will leave the delay slot
4064 empty). This gives 510.
4065 For SImode: range is 1020, add 4 because pc counts from address of
4066 second instruction after this one, subtract 2 in case pc is 2 byte
4067 aligned, subtract 2 for the jump instruction that we may need to emit
4068 before the table, subtract 2 for the instruction that fills the jump
4069 delay slot. This gives 1018. */
4071 /* The branch will always be shortened now that the reference address for
4072 forward branches is the successor address, thus we need no longer make
4073 adjustments to the [sh]i_limit for -O0. */
4078 while (from && count_si < si_limit && count_hi < hi_limit)
4080 int inc = get_attr_length (from);
4083 /* If this is a label that existed at the time of the compute_alignments
4084 call, determine the alignment. N.B. When find_barrier recurses for
4085 an out-of-reach mova, we might see labels at the start of previously
4086 inserted constant tables. */
4088 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4091 new_align = 1 << label_to_alignment (from);
4092 else if (BARRIER_P (prev_nonnote_insn (from)))
4093 new_align = 1 << barrier_align (from);
4098 /* In case we are scanning a constant table because of recursion, check
4099 for explicit alignments. If the table is long, we might be forced
4100 to emit the new table in front of it; the length of the alignment
4101 might be the last straw. */
4102 else if (NONJUMP_INSN_P (from)
4103 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4104 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4105 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4106 /* When we find the end of a constant table, paste the new constant
4107 at the end. That is better than putting it in front because
4108 this way, we don't need extra alignment for adding a 4-byte-aligned
4109 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4110 else if (NONJUMP_INSN_P (from)
4111 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4112 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4115 if (BARRIER_P (from))
4119 found_barrier = from;
4121 /* If we are at the end of the function, or in front of an alignment
4122 instruction, we need not insert an extra alignment. We prefer
4123 this kind of barrier. */
4124 if (barrier_align (from) > 2)
4125 good_barrier = from;
4127 /* If we are at the end of a hot/cold block, dump the constants
4129 next = NEXT_INSN (from);
4132 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4136 if (broken_move (from))
4139 enum machine_mode mode;
4141 pat = PATTERN (from);
4142 if (GET_CODE (pat) == PARALLEL)
4143 pat = XVECEXP (pat, 0, 0);
4144 src = SET_SRC (pat);
4145 dst = SET_DEST (pat);
4146 mode = GET_MODE (dst);
4148 /* We must explicitly check the mode, because sometimes the
4149 front end will generate code to load unsigned constants into
4150 HImode targets without properly sign extending them. */
4152 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4155 /* We put the short constants before the long constants, so
4156 we must count the length of short constants in the range
4157 for the long constants. */
4158 /* ??? This isn't optimal, but is easy to do. */
4163 /* We dump DF/DI constants before SF/SI ones, because
4164 the limit is the same, but the alignment requirements
4165 are higher. We may waste up to 4 additional bytes
4166 for alignment, and the DF/DI constant may have
4167 another SF/SI constant placed before it. */
4168 if (TARGET_SHCOMPACT
4170 && (mode == DFmode || mode == DImode))
4175 while (si_align > 2 && found_si + si_align - 2 > count_si)
4177 if (found_si > count_si)
4178 count_si = found_si;
4179 found_si += GET_MODE_SIZE (mode);
4181 si_limit -= GET_MODE_SIZE (mode);
4187 switch (untangle_mova (&num_mova, &mova, from))
4189 case 0: return find_barrier (0, 0, mova);
4194 = good_barrier ? good_barrier : found_barrier;
4198 if (found_si > count_si)
4199 count_si = found_si;
4201 else if (JUMP_TABLE_DATA_P (from))
4203 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4205 && (prev_nonnote_insn (from)
4206 == XEXP (MOVA_LABELREF (mova), 0))))
4208 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4210 /* We have just passed the barrier in front of the
4211 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4212 the ADDR_DIFF_VEC is accessed as data, just like our pool
4213 constants, this is a good opportunity to accommodate what
4214 we have gathered so far.
4215 If we waited any longer, we could end up at a barrier in
4216 front of code, which gives worse cache usage for separated
4217 instruction / data caches. */
4218 good_barrier = found_barrier;
4223 rtx body = PATTERN (from);
4224 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4227 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4228 else if (JUMP_P (from)
4230 && ! TARGET_SMALLCODE)
4236 if (new_align > si_align)
4238 si_limit -= (count_si - 1) & (new_align - si_align);
4239 si_align = new_align;
4241 count_si = (count_si + new_align - 1) & -new_align;
4246 if (new_align > hi_align)
4248 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4249 hi_align = new_align;
4251 count_hi = (count_hi + new_align - 1) & -new_align;
4253 from = NEXT_INSN (from);
4260 /* Try as we might, the leading mova is out of range. Change
4261 it into a load (which will become a pcload) and retry. */
4263 return find_barrier (0, 0, mova);
4267 /* Insert the constant pool table before the mova instruction,
4268 to prevent the mova label reference from going out of range. */
4270 good_barrier = found_barrier = barrier_before_mova;
4276 if (good_barrier && next_real_insn (found_barrier))
4277 found_barrier = good_barrier;
4281 /* We didn't find a barrier in time to dump our stuff,
4282 so we'll make one. */
4283 rtx label = gen_label_rtx ();
4285 /* If we exceeded the range, then we must back up over the last
4286 instruction we looked at. Otherwise, we just need to undo the
4287 NEXT_INSN at the end of the loop. */
4288 if (PREV_INSN (from) != orig
4289 && (count_hi > hi_limit || count_si > si_limit))
4290 from = PREV_INSN (PREV_INSN (from));
4292 from = PREV_INSN (from);
4294 /* Walk back to be just before any jump or label.
4295 Putting it before a label reduces the number of times the branch
4296 around the constant pool table will be hit. Putting it before
4297 a jump makes it more likely that the bra delay slot will be
4299 while (NOTE_P (from) || JUMP_P (from)
4301 from = PREV_INSN (from);
4303 from = emit_jump_insn_after (gen_jump (label), from);
4304 JUMP_LABEL (from) = label;
4305 LABEL_NUSES (label) = 1;
4306 found_barrier = emit_barrier_after (from);
4307 emit_label_after (label, found_barrier);
4310 return found_barrier;
4313 /* If the instruction INSN is implemented by a special function, and we can
4314 positively find the register that is used to call the sfunc, and this
4315 register is not used anywhere else in this instruction - except as the
4316 destination of a set, return this register; else, return 0. */
4318 sfunc_uses_reg (rtx insn)
4321 rtx pattern, part, reg_part, reg;
4323 if (!NONJUMP_INSN_P (insn))
4325 pattern = PATTERN (insn);
4326 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4329 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4331 part = XVECEXP (pattern, 0, i);
4332 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4337 reg = XEXP (reg_part, 0);
4338 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4340 part = XVECEXP (pattern, 0, i);
4341 if (part == reg_part || GET_CODE (part) == CLOBBER)
4343 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4344 && REG_P (SET_DEST (part)))
4345 ? SET_SRC (part) : part)))
4351 /* See if the only way in which INSN uses REG is by calling it, or by
4352 setting it while calling it. Set *SET to a SET rtx if the register
4356 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4362 reg2 = sfunc_uses_reg (insn);
4363 if (reg2 && REGNO (reg2) == REGNO (reg))
4365 pattern = single_set (insn);
4367 && REG_P (SET_DEST (pattern))
4368 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4374 /* We don't use rtx_equal_p because we don't care if the mode is
4376 pattern = single_set (insn);
4378 && REG_P (SET_DEST (pattern))
4379 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4385 par = PATTERN (insn);
4386 if (GET_CODE (par) == PARALLEL)
4387 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4389 part = XVECEXP (par, 0, i);
4390 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4393 return reg_mentioned_p (reg, SET_SRC (pattern));
4399 pattern = PATTERN (insn);
4401 if (GET_CODE (pattern) == PARALLEL)
4405 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4406 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4408 pattern = XVECEXP (pattern, 0, 0);
4411 if (GET_CODE (pattern) == SET)
4413 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4415 /* We don't use rtx_equal_p, because we don't care if the
4416 mode is different. */
4417 if (!REG_P (SET_DEST (pattern))
4418 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4424 pattern = SET_SRC (pattern);
4427 if (GET_CODE (pattern) != CALL
4428 || !MEM_P (XEXP (pattern, 0))
4429 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4435 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4436 general registers. Bits 0..15 mean that the respective registers
4437 are used as inputs in the instruction. Bits 16..31 mean that the
4438 registers 0..15, respectively, are used as outputs, or are clobbered.
4439 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4441 regs_used (rtx x, int is_dest)
4449 code = GET_CODE (x);
4454 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4455 << (REGNO (x) + is_dest));
4459 rtx y = SUBREG_REG (x);
4464 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4466 subreg_regno_offset (REGNO (y),
4469 GET_MODE (x)) + is_dest));
4473 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4475 /* If there was a return value, it must have been indicated with USE. */
4490 fmt = GET_RTX_FORMAT (code);
4492 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4497 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4498 used |= regs_used (XVECEXP (x, i, j), is_dest);
4500 else if (fmt[i] == 'e')
4501 used |= regs_used (XEXP (x, i), is_dest);
4506 /* Create an instruction that prevents redirection of a conditional branch
4507 to the destination of the JUMP with address ADDR.
4508 If the branch needs to be implemented as an indirect jump, try to find
4509 a scratch register for it.
4510 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4511 If any preceding insn that doesn't fit into a delay slot is good enough,
4512 pass 1. Pass 2 if a definite blocking insn is needed.
4513 -1 is used internally to avoid deep recursion.
4514 If a blocking instruction is made or recognized, return it. */
4517 gen_block_redirect (rtx jump, int addr, int need_block)
4520 rtx prev = prev_nonnote_insn (jump);
4523 /* First, check if we already have an instruction that satisfies our need. */
4524 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
4526 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4528 if (GET_CODE (PATTERN (prev)) == USE
4529 || GET_CODE (PATTERN (prev)) == CLOBBER
4530 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4532 else if ((need_block &= ~1) < 0)
4534 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4537 if (GET_CODE (PATTERN (jump)) == RETURN)
4541 /* Reorg even does nasty things with return insns that cause branches
4542 to go out of range - see find_end_label and callers. */
4543 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4545 /* We can't use JUMP_LABEL here because it might be undefined
4546 when not optimizing. */
4547 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4548 /* If the branch is out of range, try to find a scratch register for it. */
4550 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4554 /* Don't look for the stack pointer as a scratch register,
4555 it would cause trouble if an interrupt occurred. */
4556 unsigned attempt = 0x7fff, used;
4557 int jump_left = flag_expensive_optimizations + 1;
4559 /* It is likely that the most recent eligible instruction is wanted for
4560 the delay slot. Therefore, find out which registers it uses, and
4561 try to avoid using them. */
4563 for (scan = jump; (scan = PREV_INSN (scan)); )
4567 if (INSN_DELETED_P (scan))
4569 code = GET_CODE (scan);
4570 if (code == CODE_LABEL || code == JUMP_INSN)
4573 && GET_CODE (PATTERN (scan)) != USE
4574 && GET_CODE (PATTERN (scan)) != CLOBBER
4575 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4577 attempt &= ~regs_used (PATTERN (scan), 0);
4581 for (used = dead = 0, scan = JUMP_LABEL (jump);
4582 (scan = NEXT_INSN (scan)); )
4586 if (INSN_DELETED_P (scan))
4588 code = GET_CODE (scan);
4591 used |= regs_used (PATTERN (scan), 0);
4592 if (code == CALL_INSN)
4593 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4594 dead |= (used >> 16) & ~used;
4600 if (code == JUMP_INSN)
4602 if (jump_left-- && simplejump_p (scan))
4603 scan = JUMP_LABEL (scan);
4609 /* Mask out the stack pointer again, in case it was
4610 the only 'free' register we have found. */
4613 /* If the immediate destination is still in range, check for possible
4614 threading with a jump beyond the delay slot insn.
4615 Don't check if we are called recursively; the jump has been or will be
4616 checked in a different invocation then. */
4618 else if (optimize && need_block >= 0)
4620 rtx next = next_active_insn (next_active_insn (dest));
4621 if (next && JUMP_P (next)
4622 && GET_CODE (PATTERN (next)) == SET
4623 && recog_memoized (next) == CODE_FOR_jump_compact)
4625 dest = JUMP_LABEL (next);
4627 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4629 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4635 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4637 /* It would be nice if we could convert the jump into an indirect
4638 jump / far branch right now, and thus exposing all constituent
4639 instructions to further optimization. However, reorg uses
4640 simplejump_p to determine if there is an unconditional jump where
4641 it should try to schedule instructions from the target of the
4642 branch; simplejump_p fails for indirect jumps even if they have
4644 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4645 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4647 /* ??? We would like this to have the scope of the jump, but that
4648 scope will change when a delay slot insn of an inner scope is added.
4649 Hence, after delay slot scheduling, we'll have to expect
4650 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4653 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4654 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4657 else if (need_block)
4658 /* We can't use JUMP_LABEL here because it might be undefined
4659 when not optimizing. */
4660 return emit_insn_before (gen_block_branch_redirect
4661 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4666 #define CONDJUMP_MIN -252
4667 #define CONDJUMP_MAX 262
4670 /* A label (to be placed) in front of the jump
4671 that jumps to our ultimate destination. */
4673 /* Where we are going to insert it if we cannot move the jump any farther,
4674 or the jump itself if we have picked up an existing jump. */
4676 /* The ultimate destination. */
4678 struct far_branch *prev;
4679 /* If the branch has already been created, its address;
4680 else the address of its first prospective user. */
4684 static void gen_far_branch (struct far_branch *);
4685 enum mdep_reorg_phase_e mdep_reorg_phase;
4687 gen_far_branch (struct far_branch *bp)
4689 rtx insn = bp->insert_place;
4691 rtx label = gen_label_rtx ();
4694 emit_label_after (label, insn);
4697 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
4698 LABEL_NUSES (bp->far_label)++;
4701 jump = emit_jump_insn_after (gen_return (), insn);
4702 /* Emit a barrier so that reorg knows that any following instructions
4703 are not reachable via a fall-through path.
4704 But don't do this when not optimizing, since we wouldn't suppress the
4705 alignment for the barrier then, and could end up with out-of-range
4706 pc-relative loads. */
4708 emit_barrier_after (jump);
4709 emit_label_after (bp->near_label, insn);
4710 JUMP_LABEL (jump) = bp->far_label;
4711 ok = invert_jump (insn, label, 1);
4714 /* If we are branching around a jump (rather than a return), prevent
4715 reorg from using an insn from the jump target as the delay slot insn -
4716 when reorg did this, it pessimized code (we rather hide the delay slot)
4717 and it could cause branches to go out of range. */
4720 (gen_stuff_delay_slot
4721 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
4722 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
4724 /* Prevent reorg from undoing our splits. */
4725 gen_block_redirect (jump, bp->address += 2, 2);
4728 /* Fix up ADDR_DIFF_VECs. */
4730 fixup_addr_diff_vecs (rtx first)
4734 for (insn = first; insn; insn = NEXT_INSN (insn))
4736 rtx vec_lab, pat, prev, prevpat, x, braf_label;
4739 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
4741 pat = PATTERN (insn);
4742 vec_lab = XEXP (XEXP (pat, 0), 0);
4744 /* Search the matching casesi_jump_2. */
4745 for (prev = vec_lab; ; prev = PREV_INSN (prev))
4749 prevpat = PATTERN (prev);
4750 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
4752 x = XVECEXP (prevpat, 0, 1);
4753 if (GET_CODE (x) != USE)
4756 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
4759 /* FIXME: This is a bug in the optimizer, but it seems harmless
4760 to just avoid panicing. */
4764 /* Emit the reference label of the braf where it belongs, right after
4765 the casesi_jump_2 (i.e. braf). */
4766 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
4767 emit_label_after (braf_label, prev);
4769 /* Fix up the ADDR_DIF_VEC to be relative
4770 to the reference address of the braf. */
4771 XEXP (XEXP (pat, 0), 0) = braf_label;
4775 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
4776 a barrier. Return the base 2 logarithm of the desired alignment. */
4778 barrier_align (rtx barrier_or_label)
4780 rtx next = next_real_insn (barrier_or_label), pat, prev;
4781 int slot, credit, jump_to_next = 0;
4786 pat = PATTERN (next);
4788 if (GET_CODE (pat) == ADDR_DIFF_VEC)
4791 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
4792 /* This is a barrier in front of a constant table. */
4795 prev = prev_real_insn (barrier_or_label);
4796 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
4798 pat = PATTERN (prev);
4799 /* If this is a very small table, we want to keep the alignment after
4800 the table to the minimum for proper code alignment. */
4801 return ((TARGET_SMALLCODE
4802 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
4803 <= (unsigned) 1 << (CACHE_LOG - 2)))
4804 ? 1 << TARGET_SHMEDIA : align_jumps_log);
4807 if (TARGET_SMALLCODE)
4810 if (! TARGET_SH2 || ! optimize)
4811 return align_jumps_log;
4813 /* When fixing up pcloads, a constant table might be inserted just before
4814 the basic block that ends with the barrier. Thus, we can't trust the
4815 instruction lengths before that. */
4816 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
4818 /* Check if there is an immediately preceding branch to the insn beyond
4819 the barrier. We must weight the cost of discarding useful information
4820 from the current cache line when executing this branch and there is
4821 an alignment, against that of fetching unneeded insn in front of the
4822 branch target when there is no alignment. */
4824 /* There are two delay_slot cases to consider. One is the simple case
4825 where the preceding branch is to the insn beyond the barrier (simple
4826 delay slot filling), and the other is where the preceding branch has
4827 a delay slot that is a duplicate of the insn after the barrier
4828 (fill_eager_delay_slots) and the branch is to the insn after the insn
4829 after the barrier. */
4831 /* PREV is presumed to be the JUMP_INSN for the barrier under
4832 investigation. Skip to the insn before it. */
4833 prev = prev_real_insn (prev);
4835 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
4836 credit >= 0 && prev && NONJUMP_INSN_P (prev);
4837 prev = prev_real_insn (prev))
4840 if (GET_CODE (PATTERN (prev)) == USE
4841 || GET_CODE (PATTERN (prev)) == CLOBBER)
4843 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
4845 prev = XVECEXP (PATTERN (prev), 0, 1);
4846 if (INSN_UID (prev) == INSN_UID (next))
4848 /* Delay slot was filled with insn at jump target. */
4855 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4857 credit -= get_attr_length (prev);
4861 && JUMP_LABEL (prev))
4865 || next_real_insn (JUMP_LABEL (prev)) == next
4866 /* If relax_delay_slots() decides NEXT was redundant
4867 with some previous instruction, it will have
4868 redirected PREV's jump to the following insn. */
4869 || JUMP_LABEL (prev) == next_nonnote_insn (next)
4870 /* There is no upper bound on redundant instructions
4871 that might have been skipped, but we must not put an
4872 alignment where none had been before. */
4873 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
4875 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
4876 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
4877 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
4879 rtx pat = PATTERN (prev);
4880 if (GET_CODE (pat) == PARALLEL)
4881 pat = XVECEXP (pat, 0, 0);
4882 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
4888 return align_jumps_log;
4891 /* If we are inside a phony loop, almost any kind of label can turn up as the
4892 first one in the loop. Aligning a braf label causes incorrect switch
4893 destination addresses; we can detect braf labels because they are
4894 followed by a BARRIER.
4895 Applying loop alignment to small constant or switch tables is a waste
4896 of space, so we suppress this too. */
4898 sh_loop_align (rtx label)
4903 next = next_nonnote_insn (next);
4904 while (next && LABEL_P (next));
4908 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
4909 || recog_memoized (next) == CODE_FOR_consttable_2)
4912 return align_loops_log;
4915 /* Do a final pass over the function, just before delayed branch
4921 rtx first, insn, mova = NULL_RTX;
4923 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
4924 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
4926 first = get_insns ();
4927 max_labelno_before_reorg = max_label_num ();
4929 /* We must split call insns before introducing `mova's. If we're
4930 optimizing, they'll have already been split. Otherwise, make
4931 sure we don't split them too late. */
4933 split_all_insns_noflow ();
4938 /* If relaxing, generate pseudo-ops to associate function calls with
4939 the symbols they call. It does no harm to not generate these
4940 pseudo-ops. However, when we can generate them, it enables to
4941 linker to potentially relax the jsr to a bsr, and eliminate the
4942 register load and, possibly, the constant pool entry. */
4944 mdep_reorg_phase = SH_INSERT_USES_LABELS;
4947 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
4948 own purposes. This works because none of the remaining passes
4949 need to look at them.
4951 ??? But it may break in the future. We should use a machine
4952 dependent REG_NOTE, or some other approach entirely. */
4953 for (insn = first; insn; insn = NEXT_INSN (insn))
4959 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
4961 remove_note (insn, note);
4965 for (insn = first; insn; insn = NEXT_INSN (insn))
4967 rtx pattern, reg, link, set, scan, dies, label;
4968 int rescan = 0, foundinsn = 0;
4972 pattern = PATTERN (insn);
4974 if (GET_CODE (pattern) == PARALLEL)
4975 pattern = XVECEXP (pattern, 0, 0);
4976 if (GET_CODE (pattern) == SET)
4977 pattern = SET_SRC (pattern);
4979 if (GET_CODE (pattern) != CALL
4980 || !MEM_P (XEXP (pattern, 0)))
4983 reg = XEXP (XEXP (pattern, 0), 0);
4987 reg = sfunc_uses_reg (insn);
4995 /* Try scanning backward to find where the register is set. */
4997 for (scan = PREV_INSN (insn);
4998 scan && !LABEL_P (scan);
4999 scan = PREV_INSN (scan))
5001 if (! INSN_P (scan))
5004 if (! reg_mentioned_p (reg, scan))
5007 if (noncall_uses_reg (reg, scan, &set))
5020 /* The register is set at LINK. */
5022 /* We can only optimize the function call if the register is
5023 being set to a symbol. In theory, we could sometimes
5024 optimize calls to a constant location, but the assembler
5025 and linker do not support that at present. */
5026 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5027 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5030 /* Scan forward from LINK to the place where REG dies, and
5031 make sure that the only insns which use REG are
5032 themselves function calls. */
5034 /* ??? This doesn't work for call targets that were allocated
5035 by reload, since there may not be a REG_DEAD note for the
5039 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5043 /* Don't try to trace forward past a CODE_LABEL if we haven't
5044 seen INSN yet. Ordinarily, we will only find the setting insn
5045 if it is in the same basic block. However,
5046 cross-jumping can insert code labels in between the load and
5047 the call, and can result in situations where a single call
5048 insn may have two targets depending on where we came from. */
5050 if (LABEL_P (scan) && ! foundinsn)
5053 if (! INSN_P (scan))
5056 /* Don't try to trace forward past a JUMP. To optimize
5057 safely, we would have to check that all the
5058 instructions at the jump destination did not use REG. */
5063 if (! reg_mentioned_p (reg, scan))
5066 if (noncall_uses_reg (reg, scan, &scanset))
5073 && (CALL_P (scan) || sfunc_uses_reg (scan)))
5075 /* There is a function call to this register other
5076 than the one we are checking. If we optimize
5077 this call, we need to rescan again below. */
5081 /* ??? We shouldn't have to worry about SCANSET here.
5082 We should just be able to check for a REG_DEAD note
5083 on a function call. However, the REG_DEAD notes are
5084 apparently not dependable around libcalls; c-torture
5085 execute/920501-2 is a test case. If SCANSET is set,
5086 then this insn sets the register, so it must have
5087 died earlier. Unfortunately, this will only handle
5088 the cases in which the register is, in fact, set in a
5091 /* ??? We shouldn't have to use FOUNDINSN here.
5092 This dates back to when we used LOG_LINKS to find
5093 the most recent insn which sets the register. */
5097 || find_reg_note (scan, REG_DEAD, reg)))
5106 /* Either there was a branch, or some insn used REG
5107 other than as a function call address. */
5111 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5112 on the insn which sets the register, and on each call insn
5113 which uses the register. In final_prescan_insn we look for
5114 the REG_LABEL_OPERAND notes, and output the appropriate label
5117 label = gen_label_rtx ();
5118 add_reg_note (link, REG_LABEL_OPERAND, label);
5119 add_reg_note (insn, REG_LABEL_OPERAND, label);
5127 scan = NEXT_INSN (scan);
5130 && reg_mentioned_p (reg, scan))
5131 || ((reg2 = sfunc_uses_reg (scan))
5132 && REGNO (reg2) == REGNO (reg))))
5133 add_reg_note (scan, REG_LABEL_OPERAND, label);
5135 while (scan != dies);
5141 fixup_addr_diff_vecs (first);
5145 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5146 shorten_branches (first);
5149 /* Scan the function looking for move instructions which have to be
5150 changed to pc-relative loads and insert the literal tables. */
5151 label_ref_list_pool = create_alloc_pool ("label references list",
5152 sizeof (struct label_ref_list_d),
5154 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5155 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5159 /* ??? basic block reordering can move a switch table dispatch
5160 below the switch table. Check if that has happened.
5161 We only have the addresses available when optimizing; but then,
5162 this check shouldn't be needed when not optimizing. */
5163 if (!untangle_mova (&num_mova, &mova, insn))
5169 else if (JUMP_P (insn)
5170 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5172 /* ??? loop invariant motion can also move a mova out of a
5173 loop. Since loop does this code motion anyway, maybe we
5174 should wrap UNSPEC_MOVA into a CONST, so that reload can
5177 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5178 || (prev_nonnote_insn (insn)
5179 == XEXP (MOVA_LABELREF (mova), 0))))
5186 /* Some code might have been inserted between the mova and
5187 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5188 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5189 total += get_attr_length (scan);
5191 /* range of mova is 1020, add 4 because pc counts from address of
5192 second instruction after this one, subtract 2 in case pc is 2
5193 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5194 cancels out with alignment effects of the mova itself. */
5197 /* Change the mova into a load, and restart scanning
5198 there. broken_move will then return true for mova. */
5203 if (broken_move (insn)
5204 || (NONJUMP_INSN_P (insn)
5205 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5208 /* Scan ahead looking for a barrier to stick the constant table
5210 rtx barrier = find_barrier (num_mova, mova, insn);
5211 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5212 int need_aligned_label = 0;
5214 if (num_mova && ! mova_p (mova))
5216 /* find_barrier had to change the first mova into a
5217 pcload; thus, we have to start with this new pcload. */
5221 /* Now find all the moves between the points and modify them. */
5222 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5226 if (NONJUMP_INSN_P (scan)
5227 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5228 need_aligned_label = 1;
5229 if (broken_move (scan))
5231 rtx *patp = &PATTERN (scan), pat = *patp;
5235 enum machine_mode mode;
5237 if (GET_CODE (pat) == PARALLEL)
5238 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5239 src = SET_SRC (pat);
5240 dst = SET_DEST (pat);
5241 mode = GET_MODE (dst);
5243 if (mode == SImode && hi_const (src)
5244 && REGNO (dst) != FPUL_REG)
5249 while (GET_CODE (dst) == SUBREG)
5251 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5252 GET_MODE (SUBREG_REG (dst)),
5255 dst = SUBREG_REG (dst);
5257 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5259 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
5261 /* This must be an insn that clobbers r0. */
5262 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5263 XVECLEN (PATTERN (scan), 0)
5265 rtx clobber = *clobberp;
5267 gcc_assert (GET_CODE (clobber) == CLOBBER
5268 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5271 && reg_set_between_p (r0_rtx, last_float_move, scan))
5275 && GET_MODE_SIZE (mode) != 4
5276 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5278 lab = add_constant (src, mode, last_float);
5280 emit_insn_before (gen_mova (lab), scan);
5283 /* There will be a REG_UNUSED note for r0 on
5284 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5285 lest reorg:mark_target_live_regs will not
5286 consider r0 to be used, and we end up with delay
5287 slot insn in front of SCAN that clobbers r0. */
5289 = find_regno_note (last_float_move, REG_UNUSED, 0);
5291 /* If we are not optimizing, then there may not be
5294 PUT_REG_NOTE_KIND (note, REG_INC);
5296 *last_float_addr = r0_inc_rtx;
5298 last_float_move = scan;
5300 newsrc = gen_const_mem (mode,
5301 (((TARGET_SH4 && ! TARGET_FMOVD)
5302 || REGNO (dst) == FPUL_REG)
5305 last_float_addr = &XEXP (newsrc, 0);
5307 /* Remove the clobber of r0. */
5308 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5309 gen_rtx_SCRATCH (Pmode));
5311 /* This is a mova needing a label. Create it. */
5312 else if (GET_CODE (src) == UNSPEC
5313 && XINT (src, 1) == UNSPEC_MOVA
5314 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5316 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5317 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5318 newsrc = gen_rtx_UNSPEC (SImode,
5319 gen_rtvec (1, newsrc),
5324 lab = add_constant (src, mode, 0);
5325 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5326 newsrc = gen_const_mem (mode, newsrc);
5328 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5329 INSN_CODE (scan) = -1;
5332 dump_table (need_aligned_label ? insn : 0, barrier);
5336 free_alloc_pool (label_ref_list_pool);
5337 for (insn = first; insn; insn = NEXT_INSN (insn))
5338 PUT_MODE (insn, VOIDmode);
5340 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5341 INSN_ADDRESSES_FREE ();
5342 split_branches (first);
5344 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5345 also has an effect on the register that holds the address of the sfunc.
5346 Insert an extra dummy insn in front of each sfunc that pretends to
5347 use this register. */
5348 if (flag_delayed_branch)
5350 for (insn = first; insn; insn = NEXT_INSN (insn))
5352 rtx reg = sfunc_uses_reg (insn);
5356 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5360 /* fpscr is not actually a user variable, but we pretend it is for the
5361 sake of the previous optimization passes, since we want it handled like
5362 one. However, we don't have any debugging information for it, so turn
5363 it into a non-user variable now. */
5365 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5367 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5371 get_dest_uid (rtx label, int max_uid)
5373 rtx dest = next_real_insn (label);
5376 /* This can happen for an undefined label. */
5378 dest_uid = INSN_UID (dest);
5379 /* If this is a newly created branch redirection blocking instruction,
5380 we cannot index the branch_uid or insn_addresses arrays with its
5381 uid. But then, we won't need to, because the actual destination is
5382 the following branch. */
5383 while (dest_uid >= max_uid)
5385 dest = NEXT_INSN (dest);
5386 dest_uid = INSN_UID (dest);
5388 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
5393 /* Split condbranches that are out of range. Also add clobbers for
5394 scratch registers that are needed in far jumps.
5395 We do this before delay slot scheduling, so that it can take our
5396 newly created instructions into account. It also allows us to
5397 find branches with common targets more easily. */
5400 split_branches (rtx first)
5403 struct far_branch **uid_branch, *far_branch_list = 0;
5404 int max_uid = get_max_uid ();
5407 /* Find out which branches are out of range. */
5408 shorten_branches (first);
5410 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5411 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5413 for (insn = first; insn; insn = NEXT_INSN (insn))
5414 if (! INSN_P (insn))
5416 else if (INSN_DELETED_P (insn))
5418 /* Shorten_branches would split this instruction again,
5419 so transform it into a note. */
5420 SET_INSN_DELETED (insn);
5422 else if (JUMP_P (insn)
5423 /* Don't mess with ADDR_DIFF_VEC */
5424 && (GET_CODE (PATTERN (insn)) == SET
5425 || GET_CODE (PATTERN (insn)) == RETURN))
5427 enum attr_type type = get_attr_type (insn);
5428 if (type == TYPE_CBRANCH)
5432 if (get_attr_length (insn) > 4)
5434 rtx src = SET_SRC (PATTERN (insn));
5435 rtx olabel = XEXP (XEXP (src, 1), 0);
5436 int addr = INSN_ADDRESSES (INSN_UID (insn));
5438 int dest_uid = get_dest_uid (olabel, max_uid);
5439 struct far_branch *bp = uid_branch[dest_uid];
5441 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5442 the label if the LABEL_NUSES count drops to zero. There is
5443 always a jump_optimize pass that sets these values, but it
5444 proceeds to delete unreferenced code, and then if not
5445 optimizing, to un-delete the deleted instructions, thus
5446 leaving labels with too low uses counts. */
5449 JUMP_LABEL (insn) = olabel;
5450 LABEL_NUSES (olabel)++;
5454 bp = (struct far_branch *) alloca (sizeof *bp);
5455 uid_branch[dest_uid] = bp;
5456 bp->prev = far_branch_list;
5457 far_branch_list = bp;
5459 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5460 LABEL_NUSES (bp->far_label)++;
5464 label = bp->near_label;
5465 if (! label && bp->address - addr >= CONDJUMP_MIN)
5467 rtx block = bp->insert_place;
5469 if (GET_CODE (PATTERN (block)) == RETURN)
5470 block = PREV_INSN (block);
5472 block = gen_block_redirect (block,
5474 label = emit_label_after (gen_label_rtx (),
5476 bp->near_label = label;
5478 else if (label && ! NEXT_INSN (label))
5480 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5481 bp->insert_place = insn;
5483 gen_far_branch (bp);
5487 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5489 bp->near_label = label = gen_label_rtx ();
5490 bp->insert_place = insn;
5493 ok = redirect_jump (insn, label, 0);
5498 /* get_attr_length (insn) == 2 */
5499 /* Check if we have a pattern where reorg wants to redirect
5500 the branch to a label from an unconditional branch that
5502 /* We can't use JUMP_LABEL here because it might be undefined
5503 when not optimizing. */
5504 /* A syntax error might cause beyond to be NULL_RTX. */
5506 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5511 || ((beyond = next_active_insn (beyond))
5512 && JUMP_P (beyond)))
5513 && GET_CODE (PATTERN (beyond)) == SET
5514 && recog_memoized (beyond) == CODE_FOR_jump_compact
5516 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5517 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5519 gen_block_redirect (beyond,
5520 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5523 next = next_active_insn (insn);
5526 || ((next = next_active_insn (next))
5528 && GET_CODE (PATTERN (next)) == SET
5529 && recog_memoized (next) == CODE_FOR_jump_compact
5531 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5532 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5534 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5536 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5538 int addr = INSN_ADDRESSES (INSN_UID (insn));
5541 struct far_branch *bp;
5543 if (type == TYPE_JUMP)
5545 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5546 dest_uid = get_dest_uid (far_label, max_uid);
5549 /* Parse errors can lead to labels outside
5551 if (! NEXT_INSN (far_label))
5556 JUMP_LABEL (insn) = far_label;
5557 LABEL_NUSES (far_label)++;
5559 redirect_jump (insn, NULL_RTX, 1);
5563 bp = uid_branch[dest_uid];
5566 bp = (struct far_branch *) alloca (sizeof *bp);
5567 uid_branch[dest_uid] = bp;
5568 bp->prev = far_branch_list;
5569 far_branch_list = bp;
5571 bp->far_label = far_label;
5573 LABEL_NUSES (far_label)++;
5575 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5576 if (addr - bp->address <= CONDJUMP_MAX)
5577 emit_label_after (bp->near_label, PREV_INSN (insn));
5580 gen_far_branch (bp);
5586 bp->insert_place = insn;
5588 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5590 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5593 /* Generate all pending far branches,
5594 and free our references to the far labels. */
5595 while (far_branch_list)
5597 if (far_branch_list->near_label
5598 && ! NEXT_INSN (far_branch_list->near_label))
5599 gen_far_branch (far_branch_list);
5601 && far_branch_list->far_label
5602 && ! --LABEL_NUSES (far_branch_list->far_label))
5603 delete_insn (far_branch_list->far_label);
5604 far_branch_list = far_branch_list->prev;
5607 /* Instruction length information is no longer valid due to the new
5608 instructions that have been generated. */
5609 init_insn_lengths ();
5612 /* Dump out instruction addresses, which is useful for debugging the
5613 constant pool table stuff.
5615 If relaxing, output the label and pseudo-ops used to link together
5616 calls and the instruction which set the registers. */
5618 /* ??? The addresses printed by this routine for insns are nonsense for
5619 insns which are inside of a sequence where none of the inner insns have
5620 variable length. This is because the second pass of shorten_branches
5621 does not bother to update them. */
5624 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5625 int noperands ATTRIBUTE_UNUSED)
5627 if (TARGET_DUMPISIZE)
5628 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5634 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
5639 pattern = PATTERN (insn);
5640 if (GET_CODE (pattern) == PARALLEL)
5641 pattern = XVECEXP (pattern, 0, 0);
5642 switch (GET_CODE (pattern))
5645 if (GET_CODE (SET_SRC (pattern)) != CALL
5646 && get_attr_type (insn) != TYPE_SFUNC)
5648 targetm.asm_out.internal_label
5649 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5652 /* else FALLTHROUGH */
5654 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5655 CODE_LABEL_NUMBER (XEXP (note, 0)));
5665 /* Dump out any constants accumulated in the final pass. These will
5669 output_jump_label_table (void)
5675 fprintf (asm_out_file, "\t.align 2\n");
5676 for (i = 0; i < pool_size; i++)
5678 pool_node *p = &pool_vector[i];
5680 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5681 CODE_LABEL_NUMBER (p->label));
5682 output_asm_insn (".long %O0", &p->value);
5690 /* A full frame looks like:
5694 [ if current_function_anonymous_args
5707 local-0 <- fp points here. */
5709 /* Number of bytes pushed for anonymous args, used to pass information
5710 between expand_prologue and expand_epilogue. */
5712 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
5713 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
5714 for an epilogue and a negative value means that it's for a sibcall
5715 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
5716 all the registers that are about to be restored, and hence dead. */
5719 output_stack_adjust (int size, rtx reg, int epilogue_p,
5720 HARD_REG_SET *live_regs_mask)
5722 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
5725 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
5727 /* This test is bogus, as output_stack_adjust is used to re-align the
5730 gcc_assert (!(size % align));
5733 if (CONST_OK_FOR_ADD (size))
5734 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
5735 /* Try to do it with two partial adjustments; however, we must make
5736 sure that the stack is properly aligned at all times, in case
5737 an interrupt occurs between the two partial adjustments. */
5738 else if (CONST_OK_FOR_ADD (size / 2 & -align)
5739 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
5741 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
5742 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
5748 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
5751 /* If TEMP is invalid, we could temporarily save a general
5752 register to MACL. However, there is currently no need
5753 to handle this case, so just die when we see it. */
5755 || current_function_interrupt
5756 || ! call_really_used_regs[temp] || fixed_regs[temp])
5758 if (temp < 0 && ! current_function_interrupt
5759 && (TARGET_SHMEDIA || epilogue_p >= 0))
5762 COPY_HARD_REG_SET (temps, call_used_reg_set);
5763 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
5767 if (crtl->return_rtx)
5769 enum machine_mode mode;
5770 mode = GET_MODE (crtl->return_rtx);
5771 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
5772 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
5774 for (i = 0; i < nreg; i++)
5775 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
5776 if (crtl->calls_eh_return)
5778 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
5779 for (i = 0; i <= 3; i++)
5780 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
5783 if (TARGET_SHMEDIA && epilogue_p < 0)
5784 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
5785 CLEAR_HARD_REG_BIT (temps, i);
5786 if (epilogue_p <= 0)
5788 for (i = FIRST_PARM_REG;
5789 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
5790 CLEAR_HARD_REG_BIT (temps, i);
5791 if (cfun->static_chain_decl != NULL)
5792 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
5794 temp = scavenge_reg (&temps);
5796 if (temp < 0 && live_regs_mask)
5800 COPY_HARD_REG_SET (temps, *live_regs_mask);
5801 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
5802 temp = scavenge_reg (&temps);
5806 rtx adj_reg, tmp_reg, mem;
5808 /* If we reached here, the most likely case is the (sibcall)
5809 epilogue for non SHmedia. Put a special push/pop sequence
5810 for such case as the last resort. This looks lengthy but
5811 would not be problem because it seems to be very
5814 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
5817 /* ??? There is still the slight possibility that r4 or
5818 r5 have been reserved as fixed registers or assigned
5819 as global registers, and they change during an
5820 interrupt. There are possible ways to handle this:
5822 - If we are adjusting the frame pointer (r14), we can do
5823 with a single temp register and an ordinary push / pop
5825 - Grab any call-used or call-saved registers (i.e. not
5826 fixed or globals) for the temps we need. We might
5827 also grab r14 if we are adjusting the stack pointer.
5828 If we can't find enough available registers, issue
5829 a diagnostic and die - the user must have reserved
5830 way too many registers.
5831 But since all this is rather unlikely to happen and
5832 would require extra testing, we just die if r4 / r5
5833 are not available. */
5834 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
5835 && !global_regs[4] && !global_regs[5]);
5837 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
5838 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
5839 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
5840 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
5841 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
5842 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5843 emit_move_insn (mem, tmp_reg);
5844 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
5845 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5846 emit_move_insn (mem, tmp_reg);
5847 emit_move_insn (reg, adj_reg);
5848 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5849 emit_move_insn (adj_reg, mem);
5850 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5851 emit_move_insn (tmp_reg, mem);
5852 /* Tell flow the insns that pop r4/r5 aren't dead. */
5857 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
5859 /* If SIZE is negative, subtract the positive value.
5860 This sometimes allows a constant pool entry to be shared
5861 between prologue and epilogue code. */
5864 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
5865 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
5869 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
5870 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
5873 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
5874 gen_rtx_SET (VOIDmode, reg,
5875 gen_rtx_PLUS (SImode, reg,
5885 RTX_FRAME_RELATED_P (x) = 1;
5889 /* Output RTL to push register RN onto the stack. */
5896 x = gen_push_fpul ();
5897 else if (rn == FPSCR_REG)
5898 x = gen_push_fpscr ();
5899 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5900 && FP_OR_XD_REGISTER_P (rn))
5902 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5904 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
5906 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5907 x = gen_push_e (gen_rtx_REG (SFmode, rn));
5909 x = gen_push (gen_rtx_REG (SImode, rn));
5912 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
5916 /* Output RTL to pop register RN from the stack. */
5923 x = gen_pop_fpul ();
5924 else if (rn == FPSCR_REG)
5925 x = gen_pop_fpscr ();
5926 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5927 && FP_OR_XD_REGISTER_P (rn))
5929 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5931 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
5933 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5934 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
5936 x = gen_pop (gen_rtx_REG (SImode, rn));
5939 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
5942 /* Generate code to push the regs specified in the mask. */
5945 push_regs (HARD_REG_SET *mask, int interrupt_handler)
5947 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
5950 /* Push PR last; this gives better latencies after the prologue, and
5951 candidates for the return delay slot when there are no general
5952 registers pushed. */
5953 for (; i < FIRST_PSEUDO_REGISTER; i++)
5955 /* If this is an interrupt handler, and the SZ bit varies,
5956 and we have to push any floating point register, we need
5957 to switch to the correct precision first. */
5958 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
5959 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
5961 HARD_REG_SET unsaved;
5964 COMPL_HARD_REG_SET (unsaved, *mask);
5965 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
5969 && (i != FPSCR_REG || ! skip_fpscr)
5970 && TEST_HARD_REG_BIT (*mask, i))
5972 /* If the ISR has RESBANK attribute assigned, don't push any of
5973 the following registers - R0-R14, MACH, MACL and GBR. */
5974 if (! (sh_cfun_resbank_handler_p ()
5975 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
5983 /* Push banked registers last to improve delay slot opportunities. */
5984 if (interrupt_handler)
5985 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
5986 if (TEST_HARD_REG_BIT (*mask, i))
5989 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
5990 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
5994 /* Calculate how much extra space is needed to save all callee-saved
5996 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5999 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6002 int stack_space = 0;
6003 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6005 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6006 if ((! call_really_used_regs[reg] || interrupt_handler)
6007 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6008 /* Leave space to save this target register on the stack,
6009 in case target register allocation wants to use it. */
6010 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6014 /* Decide whether we should reserve space for callee-save target registers,
6015 in case target register allocation wants to use them. REGS_SAVED is
6016 the space, in bytes, that is already required for register saves.
6017 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6020 shmedia_reserve_space_for_target_registers_p (int regs_saved,
6021 HARD_REG_SET *live_regs_mask)
6025 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6028 /* Decide how much space to reserve for callee-save target registers
6029 in case target register allocation wants to use them.
6030 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6033 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6035 if (shmedia_space_reserved_for_target_registers)
6036 return shmedia_target_regs_stack_space (live_regs_mask);
6041 /* Work out the registers which need to be saved, both as a mask and a
6042 count of saved words. Return the count.
6044 If doing a pragma interrupt function, then push all regs used by the
6045 function, and if we call another function (we can tell by looking at PR),
6046 make sure that all the regs it clobbers are safe too. */
6049 calc_live_regs (HARD_REG_SET *live_regs_mask)
6054 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6055 bool nosave_low_regs;
6056 int pr_live, has_call;
6058 attrs = DECL_ATTRIBUTES (current_function_decl);
6059 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6060 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6061 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6062 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6064 CLEAR_HARD_REG_SET (*live_regs_mask);
6065 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6066 && df_regs_ever_live_p (FPSCR_REG))
6067 target_flags &= ~MASK_FPU_SINGLE;
6068 /* If we can save a lot of saves by switching to double mode, do that. */
6069 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
6070 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6071 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6072 && (! call_really_used_regs[reg]
6073 || interrupt_handler)
6076 target_flags &= ~MASK_FPU_SINGLE;
6079 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6080 knows how to use it. That means the pseudo originally allocated for
6081 the initial value can become the PR_MEDIA_REG hard register, as seen for
6082 execute/20010122-1.c:test9. */
6084 /* ??? this function is called from initial_elimination_offset, hence we
6085 can't use the result of sh_media_register_for_return here. */
6086 pr_live = sh_pr_n_sets ();
6089 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6090 pr_live = (pr_initial
6091 ? (!REG_P (pr_initial)
6092 || REGNO (pr_initial) != (PR_REG))
6093 : df_regs_ever_live_p (PR_REG));
6094 /* For Shcompact, if not optimizing, we end up with a memory reference
6095 using the return address pointer for __builtin_return_address even
6096 though there is no actual need to put the PR register on the stack. */
6097 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
6099 /* Force PR to be live if the prologue has to call the SHmedia
6100 argument decoder or register saver. */
6101 if (TARGET_SHCOMPACT
6102 && ((crtl->args.info.call_cookie
6103 & ~ CALL_COOKIE_RET_TRAMP (1))
6104 || crtl->saves_all_registers))
6106 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
6107 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
6109 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
6112 ? (/* Need to save all the regs ever live. */
6113 (df_regs_ever_live_p (reg)
6114 || (call_really_used_regs[reg]
6115 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6116 || reg == PIC_OFFSET_TABLE_REGNUM)
6118 || (TARGET_SHMEDIA && has_call
6119 && REGISTER_NATURAL_MODE (reg) == SImode
6120 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
6121 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6122 && reg != RETURN_ADDRESS_POINTER_REGNUM
6123 && reg != T_REG && reg != GBR_REG
6124 /* Push fpscr only on targets which have FPU */
6125 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6126 : (/* Only push those regs which are used and need to be saved. */
6129 && crtl->args.info.call_cookie
6130 && reg == PIC_OFFSET_TABLE_REGNUM)
6131 || (df_regs_ever_live_p (reg)
6132 && ((!call_really_used_regs[reg]
6133 && !(reg != PIC_OFFSET_TABLE_REGNUM
6134 && fixed_regs[reg] && call_used_regs[reg]))
6135 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6136 || (crtl->calls_eh_return
6137 && (reg == EH_RETURN_DATA_REGNO (0)
6138 || reg == EH_RETURN_DATA_REGNO (1)
6139 || reg == EH_RETURN_DATA_REGNO (2)
6140 || reg == EH_RETURN_DATA_REGNO (3)))
6141 || ((reg == MACL_REG || reg == MACH_REG)
6142 && df_regs_ever_live_p (reg)
6143 && sh_cfun_attr_renesas_p ())
6146 SET_HARD_REG_BIT (*live_regs_mask, reg);
6147 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6149 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6150 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6152 if (FP_REGISTER_P (reg))
6154 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6156 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6157 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6160 else if (XD_REGISTER_P (reg))
6162 /* Must switch to double mode to access these registers. */
6163 target_flags &= ~MASK_FPU_SINGLE;
6167 if (nosave_low_regs && reg == R8_REG)
6170 /* If we have a target register optimization pass after prologue / epilogue
6171 threading, we need to assume all target registers will be live even if
6173 if (flag_branch_target_load_optimize2
6174 && TARGET_SAVE_ALL_TARGET_REGS
6175 && shmedia_space_reserved_for_target_registers)
6176 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6177 if ((! call_really_used_regs[reg] || interrupt_handler)
6178 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6180 SET_HARD_REG_BIT (*live_regs_mask, reg);
6181 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6183 /* If this is an interrupt handler, we don't have any call-clobbered
6184 registers we can conveniently use for target register save/restore.
6185 Make sure we save at least one general purpose register when we need
6186 to save target registers. */
6187 if (interrupt_handler
6188 && hard_reg_set_intersect_p (*live_regs_mask,
6189 reg_class_contents[TARGET_REGS])
6190 && ! hard_reg_set_intersect_p (*live_regs_mask,
6191 reg_class_contents[GENERAL_REGS]))
6193 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6194 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6200 /* Code to generate prologue and epilogue sequences */
6202 /* PUSHED is the number of bytes that are being pushed on the
6203 stack for register saves. Return the frame size, padded
6204 appropriately so that the stack stays properly aligned. */
6205 static HOST_WIDE_INT
6206 rounded_frame_size (int pushed)
6208 HOST_WIDE_INT size = get_frame_size ();
6209 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6211 return ((size + pushed + align - 1) & -align) - pushed;
6214 /* Choose a call-clobbered target-branch register that remains
6215 unchanged along the whole function. We set it up as the return
6216 value in the prologue. */
6218 sh_media_register_for_return (void)
6223 if (! current_function_is_leaf)
6225 if (lookup_attribute ("interrupt_handler",
6226 DECL_ATTRIBUTES (current_function_decl)))
6228 if (sh_cfun_interrupt_handler_p ())
6231 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6233 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6234 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6240 /* The maximum registers we need to save are:
6241 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6242 - 32 floating point registers (for each pair, we save none,
6243 one single precision value, or a double precision value).
6244 - 8 target registers
6245 - add 1 entry for a delimiter. */
6246 #define MAX_SAVED_REGS (62+32+8)
6248 typedef struct save_entry_s
6257 /* There will be a delimiter entry with VOIDmode both at the start and the
6258 end of a filled in schedule. The end delimiter has the offset of the
6259 save with the smallest (i.e. most negative) offset. */
6260 typedef struct save_schedule_s
6262 save_entry entries[MAX_SAVED_REGS + 2];
6263 int temps[MAX_TEMPS+1];
6266 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6267 use reverse order. Returns the last entry written to (not counting
6268 the delimiter). OFFSET_BASE is a number to be added to all offset
6272 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6276 save_entry *entry = schedule->entries;
6280 if (! current_function_interrupt)
6281 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6282 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6283 && ! FUNCTION_ARG_REGNO_P (i)
6284 && i != FIRST_RET_REG
6285 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6286 && ! (crtl->calls_eh_return
6287 && (i == EH_RETURN_STACKADJ_REGNO
6288 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6289 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6290 schedule->temps[tmpx++] = i;
6292 entry->mode = VOIDmode;
6293 entry->offset = offset_base;
6295 /* We loop twice: first, we save 8-byte aligned registers in the
6296 higher addresses, that are known to be aligned. Then, we
6297 proceed to saving 32-bit registers that don't need 8-byte
6299 If this is an interrupt function, all registers that need saving
6300 need to be saved in full. moreover, we need to postpone saving
6301 target registers till we have saved some general purpose registers
6302 we can then use as scratch registers. */
6303 offset = offset_base;
6304 for (align = 1; align >= 0; align--)
6306 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6307 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6309 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6312 if (current_function_interrupt)
6314 if (TARGET_REGISTER_P (i))
6316 if (GENERAL_REGISTER_P (i))
6319 if (mode == SFmode && (i % 2) == 1
6320 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6321 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6328 /* If we're doing the aligned pass and this is not aligned,
6329 or we're doing the unaligned pass and this is aligned,
6331 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6335 if (current_function_interrupt
6336 && GENERAL_REGISTER_P (i)
6337 && tmpx < MAX_TEMPS)
6338 schedule->temps[tmpx++] = i;
6340 offset -= GET_MODE_SIZE (mode);
6343 entry->offset = offset;
6346 if (align && current_function_interrupt)
6347 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6348 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6350 offset -= GET_MODE_SIZE (DImode);
6352 entry->mode = DImode;
6353 entry->offset = offset;
6358 entry->mode = VOIDmode;
6359 entry->offset = offset;
6360 schedule->temps[tmpx] = -1;
6365 sh_expand_prologue (void)
6367 HARD_REG_SET live_regs_mask;
6370 int save_flags = target_flags;
6373 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6375 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6377 /* We have pretend args if we had an object sent partially in registers
6378 and partially on the stack, e.g. a large structure. */
6379 pretend_args = crtl->args.pretend_args_size;
6380 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6381 && (NPARM_REGS(SImode)
6382 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6384 output_stack_adjust (-pretend_args
6385 - crtl->args.info.stack_regs * 8,
6386 stack_pointer_rtx, 0, NULL);
6388 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6389 /* We're going to use the PIC register to load the address of the
6390 incoming-argument decoder and/or of the return trampoline from
6391 the GOT, so make sure the PIC register is preserved and
6393 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6395 if (TARGET_SHCOMPACT
6396 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6400 /* First, make all registers with incoming arguments that will
6401 be pushed onto the stack live, so that register renaming
6402 doesn't overwrite them. */
6403 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6404 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6405 >= NPARM_REGS (SImode) - reg)
6406 for (; reg < NPARM_REGS (SImode); reg++)
6407 emit_insn (gen_shcompact_preserve_incoming_args
6408 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6409 else if (CALL_COOKIE_INT_REG_GET
6410 (crtl->args.info.call_cookie, reg) == 1)
6411 emit_insn (gen_shcompact_preserve_incoming_args
6412 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6414 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6416 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6417 GEN_INT (crtl->args.info.call_cookie));
6418 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6419 gen_rtx_REG (SImode, R0_REG));
6421 else if (TARGET_SHMEDIA)
6423 int tr = sh_media_register_for_return ();
6426 emit_move_insn (gen_rtx_REG (DImode, tr),
6427 gen_rtx_REG (DImode, PR_MEDIA_REG));
6430 /* Emit the code for SETUP_VARARGS. */
6433 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6435 /* Push arg regs as if they'd been provided by caller in stack. */
6436 for (i = 0; i < NPARM_REGS(SImode); i++)
6438 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6441 if (i >= (NPARM_REGS(SImode)
6442 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6450 /* If we're supposed to switch stacks at function entry, do so now. */
6453 /* The argument specifies a variable holding the address of the
6454 stack the interrupt function should switch to/from at entry/exit. */
6456 = ggc_strdup (TREE_STRING_POINTER (TREE_VALUE (sp_switch_attr)));
6457 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6459 emit_insn (gen_sp_switch_1 (sp_switch));
6462 d = calc_live_regs (&live_regs_mask);
6463 /* ??? Maybe we could save some switching if we can move a mode switch
6464 that already happens to be at the function start into the prologue. */
6465 if (target_flags != save_flags && ! current_function_interrupt)
6466 emit_insn (gen_toggle_sz ());
6470 int offset_base, offset;
6472 int offset_in_r0 = -1;
6474 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6475 int total_size, save_size;
6476 save_schedule schedule;
6480 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6481 && ! current_function_interrupt)
6482 r0 = gen_rtx_REG (Pmode, R0_REG);
6484 /* D is the actual number of bytes that we need for saving registers,
6485 however, in initial_elimination_offset we have committed to using
6486 an additional TREGS_SPACE amount of bytes - in order to keep both
6487 addresses to arguments supplied by the caller and local variables
6488 valid, we must keep this gap. Place it between the incoming
6489 arguments and the actually saved registers in a bid to optimize
6490 locality of reference. */
6491 total_size = d + tregs_space;
6492 total_size += rounded_frame_size (total_size);
6493 save_size = total_size - rounded_frame_size (d);
6494 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6495 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6496 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6498 /* If adjusting the stack in a single step costs nothing extra, do so.
6499 I.e. either if a single addi is enough, or we need a movi anyway,
6500 and we don't exceed the maximum offset range (the test for the
6501 latter is conservative for simplicity). */
6503 && (CONST_OK_FOR_I10 (-total_size)
6504 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6505 && total_size <= 2044)))
6506 d_rounding = total_size - save_size;
6508 offset_base = d + d_rounding;
6510 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6513 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6514 tmp_pnt = schedule.temps;
6515 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6517 enum machine_mode mode = (enum machine_mode) entry->mode;
6518 unsigned int reg = entry->reg;
6519 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6522 offset = entry->offset;
6524 reg_rtx = gen_rtx_REG (mode, reg);
6526 mem_rtx = gen_frame_mem (mode,
6527 gen_rtx_PLUS (Pmode,
6531 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6537 if (HAVE_PRE_DECREMENT
6538 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6539 || mem_rtx == NULL_RTX
6540 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6542 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6544 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
6549 offset += GET_MODE_SIZE (mode);
6553 if (mem_rtx != NULL_RTX)
6556 if (offset_in_r0 == -1)
6558 emit_move_insn (r0, GEN_INT (offset));
6559 offset_in_r0 = offset;
6561 else if (offset != offset_in_r0)
6566 GEN_INT (offset - offset_in_r0)));
6567 offset_in_r0 += offset - offset_in_r0;
6570 if (pre_dec != NULL_RTX)
6576 (Pmode, r0, stack_pointer_rtx));
6580 offset -= GET_MODE_SIZE (mode);
6581 offset_in_r0 -= GET_MODE_SIZE (mode);
6586 mem_rtx = gen_frame_mem (mode, r0);
6588 mem_rtx = gen_frame_mem (mode,
6589 gen_rtx_PLUS (Pmode,
6593 /* We must not use an r0-based address for target-branch
6594 registers or for special registers without pre-dec
6595 memory addresses, since we store their values in r0
6597 gcc_assert (!TARGET_REGISTER_P (reg)
6598 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6599 || mem_rtx == pre_dec));
6602 orig_reg_rtx = reg_rtx;
6603 if (TARGET_REGISTER_P (reg)
6604 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6605 && mem_rtx != pre_dec))
6607 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6609 emit_move_insn (tmp_reg, reg_rtx);
6611 if (REGNO (tmp_reg) == R0_REG)
6615 gcc_assert (!refers_to_regno_p
6616 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6619 if (*++tmp_pnt <= 0)
6620 tmp_pnt = schedule.temps;
6627 /* Mark as interesting for dwarf cfi generator */
6628 insn = emit_move_insn (mem_rtx, reg_rtx);
6629 RTX_FRAME_RELATED_P (insn) = 1;
6630 /* If we use an intermediate register for the save, we can't
6631 describe this exactly in cfi as a copy of the to-be-saved
6632 register into the temporary register and then the temporary
6633 register on the stack, because the temporary register can
6634 have a different natural size than the to-be-saved register.
6635 Thus, we gloss over the intermediate copy and pretend we do
6636 a direct save from the to-be-saved register. */
6637 if (REGNO (reg_rtx) != reg)
6641 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6642 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6645 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6647 rtx reg_rtx = gen_rtx_REG (mode, reg);
6649 rtx mem_rtx = gen_frame_mem (mode,
6650 gen_rtx_PLUS (Pmode,
6654 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6655 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6660 gcc_assert (entry->offset == d_rounding);
6663 push_regs (&live_regs_mask, current_function_interrupt);
6665 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
6666 emit_insn (gen_GOTaddr2picreg ());
6668 if (SHMEDIA_REGS_STACK_ADJUST ())
6670 /* This must NOT go through the PLT, otherwise mach and macl
6671 may be clobbered. */
6672 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6674 ? "__GCC_push_shmedia_regs"
6675 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
6676 emit_insn (gen_shmedia_save_restore_regs_compact
6677 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
6680 if (target_flags != save_flags && ! current_function_interrupt)
6681 emit_insn (gen_toggle_sz ());
6683 target_flags = save_flags;
6685 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
6686 stack_pointer_rtx, 0, NULL);
6688 if (frame_pointer_needed)
6689 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
6691 if (TARGET_SHCOMPACT
6692 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6694 /* This must NOT go through the PLT, otherwise mach and macl
6695 may be clobbered. */
6696 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6697 "__GCC_shcompact_incoming_args", SFUNC_GOT);
6698 emit_insn (gen_shcompact_incoming_args ());
6703 sh_expand_epilogue (bool sibcall_p)
6705 HARD_REG_SET live_regs_mask;
6709 int save_flags = target_flags;
6710 int frame_size, save_size;
6711 int fpscr_deferred = 0;
6712 int e = sibcall_p ? -1 : 1;
6714 d = calc_live_regs (&live_regs_mask);
6717 frame_size = rounded_frame_size (d);
6721 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6723 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
6724 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6725 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
6727 total_size = d + tregs_space;
6728 total_size += rounded_frame_size (total_size);
6729 save_size = total_size - frame_size;
6731 /* If adjusting the stack in a single step costs nothing extra, do so.
6732 I.e. either if a single addi is enough, or we need a movi anyway,
6733 and we don't exceed the maximum offset range (the test for the
6734 latter is conservative for simplicity). */
6736 && ! frame_pointer_needed
6737 && (CONST_OK_FOR_I10 (total_size)
6738 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
6739 && total_size <= 2044)))
6740 d_rounding = frame_size;
6742 frame_size -= d_rounding;
6745 if (frame_pointer_needed)
6747 /* We must avoid scheduling the epilogue with previous basic blocks.
6748 See PR/18032 and PR/40313. */
6749 emit_insn (gen_blockage ());
6750 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
6753 /* We must avoid moving the stack pointer adjustment past code
6754 which reads from the local frame, else an interrupt could
6755 occur after the SP adjustment and clobber data in the local
6757 emit_insn (gen_blockage ());
6758 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
6760 else if (frame_size)
6762 /* We must avoid moving the stack pointer adjustment past code
6763 which reads from the local frame, else an interrupt could
6764 occur after the SP adjustment and clobber data in the local
6766 emit_insn (gen_blockage ());
6767 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
6770 if (SHMEDIA_REGS_STACK_ADJUST ())
6772 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6774 ? "__GCC_pop_shmedia_regs"
6775 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
6776 /* This must NOT go through the PLT, otherwise mach and macl
6777 may be clobbered. */
6778 emit_insn (gen_shmedia_save_restore_regs_compact
6779 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
6782 /* Pop all the registers. */
6784 if (target_flags != save_flags && ! current_function_interrupt)
6785 emit_insn (gen_toggle_sz ());
6788 int offset_base, offset;
6789 int offset_in_r0 = -1;
6791 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
6792 save_schedule schedule;
6796 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
6797 offset_base = -entry[1].offset + d_rounding;
6798 tmp_pnt = schedule.temps;
6799 for (; entry->mode != VOIDmode; entry--)
6801 enum machine_mode mode = (enum machine_mode) entry->mode;
6802 int reg = entry->reg;
6803 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
6805 offset = offset_base + entry->offset;
6806 reg_rtx = gen_rtx_REG (mode, reg);
6808 mem_rtx = gen_frame_mem (mode,
6809 gen_rtx_PLUS (Pmode,
6813 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6816 if (HAVE_POST_INCREMENT
6817 && (offset == offset_in_r0
6818 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
6819 && mem_rtx == NULL_RTX)
6820 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6822 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
6824 if (!memory_address_p (mode, XEXP (post_inc, 0)))
6825 post_inc = NULL_RTX;
6830 if (mem_rtx != NULL_RTX)
6833 if (offset_in_r0 == -1)
6835 emit_move_insn (r0, GEN_INT (offset));
6836 offset_in_r0 = offset;
6838 else if (offset != offset_in_r0)
6843 GEN_INT (offset - offset_in_r0)));
6844 offset_in_r0 += offset - offset_in_r0;
6847 if (post_inc != NULL_RTX)
6853 (Pmode, r0, stack_pointer_rtx));
6859 offset_in_r0 += GET_MODE_SIZE (mode);
6862 mem_rtx = gen_frame_mem (mode, r0);
6864 mem_rtx = gen_frame_mem (mode,
6865 gen_rtx_PLUS (Pmode,
6869 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6870 || mem_rtx == post_inc);
6873 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6874 && mem_rtx != post_inc)
6876 insn = emit_move_insn (r0, mem_rtx);
6879 else if (TARGET_REGISTER_P (reg))
6881 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
6883 /* Give the scheduler a bit of freedom by using up to
6884 MAX_TEMPS registers in a round-robin fashion. */
6885 insn = emit_move_insn (tmp_reg, mem_rtx);
6888 tmp_pnt = schedule.temps;
6891 insn = emit_move_insn (reg_rtx, mem_rtx);
6894 gcc_assert (entry->offset + offset_base == d + d_rounding);
6896 else /* ! TARGET_SH5 */
6901 /* For an ISR with RESBANK attribute assigned, don't pop PR
6903 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
6904 && !sh_cfun_resbank_handler_p ())
6906 if (!frame_pointer_needed)
6907 emit_insn (gen_blockage ());
6911 /* Banked registers are poped first to avoid being scheduled in the
6912 delay slot. RTE switches banks before the ds instruction. */
6913 if (current_function_interrupt)
6915 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6916 if (TEST_HARD_REG_BIT (live_regs_mask, i))
6917 pop (LAST_BANKED_REG - i);
6919 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
6922 last_reg = FIRST_PSEUDO_REGISTER;
6924 for (i = 0; i < last_reg; i++)
6926 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
6928 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
6929 && hard_reg_set_intersect_p (live_regs_mask,
6930 reg_class_contents[DF_REGS]))
6932 /* For an ISR with RESBANK attribute assigned, don't pop
6933 following registers, R0-R14, MACH, MACL and GBR. */
6934 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
6935 && ! (sh_cfun_resbank_handler_p ()
6936 && ((j >= FIRST_GENERAL_REG
6937 && j < LAST_GENERAL_REG)
6943 if (j == FIRST_FP_REG && fpscr_deferred)
6947 if (target_flags != save_flags && ! current_function_interrupt)
6948 emit_insn (gen_toggle_sz ());
6949 target_flags = save_flags;
6951 output_stack_adjust (crtl->args.pretend_args_size
6952 + save_size + d_rounding
6953 + crtl->args.info.stack_regs * 8,
6954 stack_pointer_rtx, e, NULL);
6956 if (crtl->calls_eh_return)
6957 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
6958 EH_RETURN_STACKADJ_RTX));
6960 /* Switch back to the normal stack if necessary. */
6961 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
6962 emit_insn (gen_sp_switch_2 ());
6964 /* Tell flow the insn that pops PR isn't dead. */
6965 /* PR_REG will never be live in SHmedia mode, and we don't need to
6966 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
6967 by the return pattern. */
6968 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
6969 emit_use (gen_rtx_REG (SImode, PR_REG));
6972 static int sh_need_epilogue_known = 0;
6975 sh_need_epilogue (void)
6977 if (! sh_need_epilogue_known)
6982 sh_expand_epilogue (0);
6983 epilogue = get_insns ();
6985 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
6987 return sh_need_epilogue_known > 0;
6990 /* Emit code to change the current function's return address to RA.
6991 TEMP is available as a scratch register, if needed. */
6994 sh_set_return_address (rtx ra, rtx tmp)
6996 HARD_REG_SET live_regs_mask;
6998 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7001 d = calc_live_regs (&live_regs_mask);
7003 /* If pr_reg isn't life, we can set it (or the register given in
7004 sh_media_register_for_return) directly. */
7005 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7011 int rr_regno = sh_media_register_for_return ();
7016 rr = gen_rtx_REG (DImode, rr_regno);
7019 rr = gen_rtx_REG (SImode, pr_reg);
7021 emit_insn (GEN_MOV (rr, ra));
7022 /* Tell flow the register for return isn't dead. */
7030 save_schedule schedule;
7033 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7034 offset = entry[1].offset;
7035 for (; entry->mode != VOIDmode; entry--)
7036 if (entry->reg == pr_reg)
7039 /* We can't find pr register. */
7043 offset = entry->offset - offset;
7044 pr_offset = (rounded_frame_size (d) + offset
7045 + SHMEDIA_REGS_STACK_ADJUST ());
7048 pr_offset = rounded_frame_size (d);
7050 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7051 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7053 tmp = gen_frame_mem (Pmode, tmp);
7054 emit_insn (GEN_MOV (tmp, ra));
7055 /* Tell this store isn't dead. */
7059 /* Clear variables at function end. */
7062 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7063 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7065 sh_need_epilogue_known = 0;
7069 sh_builtin_saveregs (void)
7071 /* First unnamed integer register. */
7072 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7073 /* Number of integer registers we need to save. */
7074 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7075 /* First unnamed SFmode float reg */
7076 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7077 /* Number of SFmode float regs to save. */
7078 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7081 alias_set_type alias_set;
7087 int pushregs = n_intregs;
7089 while (pushregs < NPARM_REGS (SImode) - 1
7090 && (CALL_COOKIE_INT_REG_GET
7091 (crtl->args.info.call_cookie,
7092 NPARM_REGS (SImode) - pushregs)
7095 crtl->args.info.call_cookie
7096 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7101 if (pushregs == NPARM_REGS (SImode))
7102 crtl->args.info.call_cookie
7103 |= (CALL_COOKIE_INT_REG (0, 1)
7104 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7106 crtl->args.info.call_cookie
7107 |= CALL_COOKIE_STACKSEQ (pushregs);
7109 crtl->args.pretend_args_size += 8 * n_intregs;
7111 if (TARGET_SHCOMPACT)
7115 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7117 error ("__builtin_saveregs not supported by this subtarget");
7124 /* Allocate block of memory for the regs. */
7125 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7126 Or can assign_stack_local accept a 0 SIZE argument? */
7127 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7130 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7131 else if (n_floatregs & 1)
7135 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7136 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7137 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7138 regbuf = change_address (regbuf, BLKmode, addr);
7140 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7144 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7145 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7146 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7147 emit_insn (gen_andsi3 (addr, addr, mask));
7148 regbuf = change_address (regbuf, BLKmode, addr);
7151 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7152 alias_set = get_varargs_alias_set ();
7153 set_mem_alias_set (regbuf, alias_set);
7156 This is optimized to only save the regs that are necessary. Explicitly
7157 named args need not be saved. */
7159 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7160 adjust_address (regbuf, BLKmode,
7161 n_floatregs * UNITS_PER_WORD),
7165 /* Return the address of the regbuf. */
7166 return XEXP (regbuf, 0);
7169 This is optimized to only save the regs that are necessary. Explicitly
7170 named args need not be saved.
7171 We explicitly build a pointer to the buffer because it halves the insn
7172 count when not optimizing (otherwise the pointer is built for each reg
7174 We emit the moves in reverse order so that we can use predecrement. */
7176 fpregs = copy_to_mode_reg (Pmode,
7177 plus_constant (XEXP (regbuf, 0),
7178 n_floatregs * UNITS_PER_WORD));
7179 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7182 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7184 emit_insn (gen_addsi3 (fpregs, fpregs,
7185 GEN_INT (-2 * UNITS_PER_WORD)));
7186 mem = change_address (regbuf, DFmode, fpregs);
7187 emit_move_insn (mem,
7188 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7190 regno = first_floatreg;
7193 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7194 mem = change_address (regbuf, SFmode, fpregs);
7195 emit_move_insn (mem,
7196 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7197 - (TARGET_LITTLE_ENDIAN != 0)));
7201 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7205 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7206 mem = change_address (regbuf, SFmode, fpregs);
7207 emit_move_insn (mem,
7208 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7211 /* Return the address of the regbuf. */
7212 return XEXP (regbuf, 0);
7215 /* Define the `__builtin_va_list' type for the ABI. */
7218 sh_build_builtin_va_list (void)
7220 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7223 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7224 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7225 return ptr_type_node;
7227 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7229 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
7231 f_next_o_limit = build_decl (FIELD_DECL,
7232 get_identifier ("__va_next_o_limit"),
7234 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
7236 f_next_fp_limit = build_decl (FIELD_DECL,
7237 get_identifier ("__va_next_fp_limit"),
7239 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
7242 DECL_FIELD_CONTEXT (f_next_o) = record;
7243 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7244 DECL_FIELD_CONTEXT (f_next_fp) = record;
7245 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7246 DECL_FIELD_CONTEXT (f_next_stack) = record;
7248 TYPE_FIELDS (record) = f_next_o;
7249 TREE_CHAIN (f_next_o) = f_next_o_limit;
7250 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7251 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7252 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7254 layout_type (record);
7259 /* Implement `va_start' for varargs and stdarg. */
7262 sh_va_start (tree valist, rtx nextarg)
7264 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7265 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7271 expand_builtin_saveregs ();
7272 std_expand_builtin_va_start (valist, nextarg);
7276 if ((! TARGET_SH2E && ! TARGET_SH4)
7277 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7279 std_expand_builtin_va_start (valist, nextarg);
7283 f_next_o = TYPE_FIELDS (va_list_type_node);
7284 f_next_o_limit = TREE_CHAIN (f_next_o);
7285 f_next_fp = TREE_CHAIN (f_next_o_limit);
7286 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7287 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7289 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7291 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7292 valist, f_next_o_limit, NULL_TREE);
7293 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7295 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7296 valist, f_next_fp_limit, NULL_TREE);
7297 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7298 valist, f_next_stack, NULL_TREE);
7300 /* Call __builtin_saveregs. */
7301 u = make_tree (sizetype, expand_builtin_saveregs ());
7302 u = fold_convert (ptr_type_node, u);
7303 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7304 TREE_SIDE_EFFECTS (t) = 1;
7305 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7307 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7312 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7313 size_int (UNITS_PER_WORD * nfp));
7314 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7315 TREE_SIDE_EFFECTS (t) = 1;
7316 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7318 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7319 TREE_SIDE_EFFECTS (t) = 1;
7320 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7322 nint = crtl->args.info.arg_count[SH_ARG_INT];
7327 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7328 size_int (UNITS_PER_WORD * nint));
7329 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7330 TREE_SIDE_EFFECTS (t) = 1;
7331 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7333 u = make_tree (ptr_type_node, nextarg);
7334 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7335 TREE_SIDE_EFFECTS (t) = 1;
7336 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7339 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7340 member, return it. */
7342 find_sole_member (tree type)
7344 tree field, member = NULL_TREE;
7346 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7348 if (TREE_CODE (field) != FIELD_DECL)
7350 if (!DECL_SIZE (field))
7352 if (integer_zerop (DECL_SIZE (field)))
7360 /* Implement `va_arg'. */
7363 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7364 gimple_seq *post_p ATTRIBUTE_UNUSED)
7366 HOST_WIDE_INT size, rsize;
7367 tree tmp, pptr_type_node;
7368 tree addr, lab_over = NULL, result = NULL;
7369 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7373 type = build_pointer_type (type);
7375 size = int_size_in_bytes (type);
7376 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7377 pptr_type_node = build_pointer_type (ptr_type_node);
7379 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7380 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7382 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7383 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7388 f_next_o = TYPE_FIELDS (va_list_type_node);
7389 f_next_o_limit = TREE_CHAIN (f_next_o);
7390 f_next_fp = TREE_CHAIN (f_next_o_limit);
7391 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7392 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7394 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7396 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7397 valist, f_next_o_limit, NULL_TREE);
7398 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7399 valist, f_next_fp, NULL_TREE);
7400 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7401 valist, f_next_fp_limit, NULL_TREE);
7402 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7403 valist, f_next_stack, NULL_TREE);
7405 /* Structures with a single member with a distinct mode are passed
7406 like their member. This is relevant if the latter has a REAL_TYPE
7407 or COMPLEX_TYPE type. */
7409 while (TREE_CODE (eff_type) == RECORD_TYPE
7410 && (member = find_sole_member (eff_type))
7411 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7412 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7413 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7415 tree field_type = TREE_TYPE (member);
7417 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7418 eff_type = field_type;
7421 gcc_assert ((TYPE_ALIGN (eff_type)
7422 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7423 || (TYPE_ALIGN (eff_type)
7424 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7429 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7431 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7432 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7433 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7438 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7441 addr = create_tmp_var (pptr_type_node, NULL);
7442 lab_false = create_artificial_label ();
7443 lab_over = create_artificial_label ();
7445 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7449 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7451 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7453 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7454 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7456 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7457 tmp = next_fp_limit;
7458 if (size > 4 && !is_double)
7459 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
7460 unshare_expr (tmp), size_int (4 - size));
7461 tmp = build2 (GE_EXPR, boolean_type_node,
7462 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7463 cmp = build3 (COND_EXPR, void_type_node, tmp,
7464 build1 (GOTO_EXPR, void_type_node,
7465 unshare_expr (lab_false)), NULL_TREE);
7467 gimplify_and_add (cmp, pre_p);
7469 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7470 || (is_double || size == 16))
7472 tmp = fold_convert (sizetype, next_fp_tmp);
7473 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7474 size_int (UNITS_PER_WORD));
7475 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7476 unshare_expr (next_fp_tmp), tmp);
7477 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7480 gimplify_and_add (cmp, pre_p);
7482 #ifdef FUNCTION_ARG_SCmode_WART
7483 if (TYPE_MODE (eff_type) == SCmode
7484 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7486 tree subtype = TREE_TYPE (eff_type);
7490 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7491 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7494 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7495 real = get_initialized_tmp_var (real, pre_p, NULL);
7497 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7498 if (type != eff_type)
7499 result = build1 (VIEW_CONVERT_EXPR, type, result);
7500 result = get_initialized_tmp_var (result, pre_p, NULL);
7502 #endif /* FUNCTION_ARG_SCmode_WART */
7504 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7505 gimplify_and_add (tmp, pre_p);
7507 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7508 gimplify_and_add (tmp, pre_p);
7510 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7511 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7512 gimplify_assign (unshare_expr (next_fp_tmp),
7513 unshare_expr (valist), pre_p);
7515 gimplify_assign (unshare_expr (valist),
7516 unshare_expr (next_fp_tmp), post_p);
7517 valist = next_fp_tmp;
7521 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7522 unshare_expr (next_o), size_int (rsize));
7523 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7524 unshare_expr (next_o_limit));
7525 tmp = build3 (COND_EXPR, void_type_node, tmp,
7526 build1 (GOTO_EXPR, void_type_node,
7527 unshare_expr (lab_false)),
7529 gimplify_and_add (tmp, pre_p);
7531 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7532 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7534 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7535 gimplify_and_add (tmp, pre_p);
7537 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7538 gimplify_and_add (tmp, pre_p);
7540 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7541 gimplify_assign (unshare_expr (next_o),
7542 unshare_expr (next_o_limit), pre_p);
7544 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7545 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7550 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7551 gimplify_and_add (tmp, pre_p);
7555 /* ??? In va-sh.h, there had been code to make values larger than
7556 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7558 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7561 gimplify_assign (result, tmp, pre_p);
7563 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7564 gimplify_and_add (tmp, pre_p);
7570 result = build_va_arg_indirect_ref (result);
7575 /* 64 bit floating points memory transfers are paired single precision loads
7576 or store. So DWARF information needs fixing in little endian (unless
7577 PR=SZ=1 in FPSCR). */
7579 sh_dwarf_register_span (rtx reg)
7581 unsigned regno = REGNO (reg);
7583 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
7587 gen_rtx_PARALLEL (VOIDmode,
7589 gen_rtx_REG (SFmode,
7590 DBX_REGISTER_NUMBER (regno+1)),
7591 gen_rtx_REG (SFmode,
7592 DBX_REGISTER_NUMBER (regno))));
7596 sh_promote_prototypes (const_tree type)
7602 return ! sh_attr_renesas_p (type);
7605 /* Whether an argument must be passed by reference. On SHcompact, we
7606 pretend arguments wider than 32-bits that would have been passed in
7607 registers are passed by reference, so that an SHmedia trampoline
7608 loads them into the full 64-bits registers. */
7611 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7612 const_tree type, bool named)
7614 unsigned HOST_WIDE_INT size;
7617 size = int_size_in_bytes (type);
7619 size = GET_MODE_SIZE (mode);
7621 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7623 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7624 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7625 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7627 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7628 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7635 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7636 const_tree type, bool named)
7638 if (targetm.calls.must_pass_in_stack (mode, type))
7641 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7642 wants to know about pass-by-reference semantics for incoming
7647 if (TARGET_SHCOMPACT)
7649 cum->byref = shcompact_byref (cum, mode, type, named);
7650 return cum->byref != 0;
7657 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7658 const_tree type, bool named ATTRIBUTE_UNUSED)
7660 /* ??? How can it possibly be correct to return true only on the
7661 caller side of the equation? Is there someplace else in the
7662 sh backend that's magically producing the copies? */
7663 return (cum->outgoing
7664 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7665 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7669 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7670 tree type, bool named ATTRIBUTE_UNUSED)
7675 && PASS_IN_REG_P (*cum, mode, type)
7676 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7677 && (ROUND_REG (*cum, mode)
7679 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7680 : ROUND_ADVANCE (int_size_in_bytes (type)))
7681 > NPARM_REGS (mode)))
7682 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
7684 else if (!TARGET_SHCOMPACT
7685 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7686 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
7688 return words * UNITS_PER_WORD;
7692 /* Define where to put the arguments to a function.
7693 Value is zero to push the argument on the stack,
7694 or a hard register in which to store the argument.
7696 MODE is the argument's machine mode.
7697 TYPE is the data type of the argument (as a tree).
7698 This is null for libcalls where that information may
7700 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7701 the preceding args and about the function being called.
7702 NAMED is nonzero if this argument is a named parameter
7703 (otherwise it is an extra parameter matching an ellipsis).
7705 On SH the first args are normally in registers
7706 and the rest are pushed. Any arg that starts within the first
7707 NPARM_REGS words is at least partially passed in a register unless
7708 its data type forbids. */
7712 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7713 tree type, int named)
7715 if (! TARGET_SH5 && mode == VOIDmode)
7716 return GEN_INT (ca->renesas_abi ? 1 : 0);
7719 && PASS_IN_REG_P (*ca, mode, type)
7720 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
7724 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
7725 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
7727 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
7728 gen_rtx_REG (SFmode,
7730 + (ROUND_REG (*ca, mode) ^ 1)),
7732 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
7733 gen_rtx_REG (SFmode,
7735 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
7737 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
7740 /* If the alignment of a DF value causes an SF register to be
7741 skipped, we will use that skipped register for the next SF
7743 if ((TARGET_HITACHI || ca->renesas_abi)
7744 && ca->free_single_fp_reg
7746 return gen_rtx_REG (mode, ca->free_single_fp_reg);
7748 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
7749 ^ (mode == SFmode && TARGET_SH4
7750 && TARGET_LITTLE_ENDIAN != 0
7751 && ! TARGET_HITACHI && ! ca->renesas_abi);
7752 return gen_rtx_REG (mode, regno);
7758 if (mode == VOIDmode && TARGET_SHCOMPACT)
7759 return GEN_INT (ca->call_cookie);
7761 /* The following test assumes unnamed arguments are promoted to
7763 if (mode == SFmode && ca->free_single_fp_reg)
7764 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
7766 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
7767 && (named || ! ca->prototype_p)
7768 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
7770 if (! ca->prototype_p && TARGET_SHMEDIA)
7771 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
7773 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
7775 + ca->arg_count[(int) SH_ARG_FLOAT]);
7778 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
7779 && (! TARGET_SHCOMPACT
7780 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
7781 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
7784 return gen_rtx_REG (mode, (FIRST_PARM_REG
7785 + ca->arg_count[(int) SH_ARG_INT]));
7794 /* Update the data in CUM to advance over an argument
7795 of mode MODE and data type TYPE.
7796 (TYPE is null for libcalls where that information may not be
7800 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7801 tree type, int named)
7805 else if (TARGET_SH5)
7807 tree type2 = (ca->byref && type
7810 enum machine_mode mode2 = (ca->byref && type
7813 int dwords = ((ca->byref
7816 ? int_size_in_bytes (type2)
7817 : GET_MODE_SIZE (mode2)) + 7) / 8;
7818 int numregs = MIN (dwords, NPARM_REGS (SImode)
7819 - ca->arg_count[(int) SH_ARG_INT]);
7823 ca->arg_count[(int) SH_ARG_INT] += numregs;
7824 if (TARGET_SHCOMPACT
7825 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
7828 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7830 /* N.B. We want this also for outgoing. */
7831 ca->stack_regs += numregs;
7836 ca->stack_regs += numregs;
7837 ca->byref_regs += numregs;
7841 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7845 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7848 else if (dwords > numregs)
7850 int pushregs = numregs;
7852 if (TARGET_SHCOMPACT)
7853 ca->stack_regs += numregs;
7854 while (pushregs < NPARM_REGS (SImode) - 1
7855 && (CALL_COOKIE_INT_REG_GET
7857 NPARM_REGS (SImode) - pushregs)
7861 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7865 if (numregs == NPARM_REGS (SImode))
7867 |= CALL_COOKIE_INT_REG (0, 1)
7868 | CALL_COOKIE_STACKSEQ (numregs - 1);
7871 |= CALL_COOKIE_STACKSEQ (numregs);
7874 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
7875 && (named || ! ca->prototype_p))
7877 if (mode2 == SFmode && ca->free_single_fp_reg)
7878 ca->free_single_fp_reg = 0;
7879 else if (ca->arg_count[(int) SH_ARG_FLOAT]
7880 < NPARM_REGS (SFmode))
7883 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
7885 - ca->arg_count[(int) SH_ARG_FLOAT]);
7887 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
7889 if (TARGET_SHCOMPACT && ! ca->prototype_p)
7891 if (ca->outgoing && numregs > 0)
7895 |= (CALL_COOKIE_INT_REG
7896 (ca->arg_count[(int) SH_ARG_INT]
7897 - numregs + ((numfpregs - 2) / 2),
7898 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
7901 while (numfpregs -= 2);
7903 else if (mode2 == SFmode && (named)
7904 && (ca->arg_count[(int) SH_ARG_FLOAT]
7905 < NPARM_REGS (SFmode)))
7906 ca->free_single_fp_reg
7907 = FIRST_FP_PARM_REG - numfpregs
7908 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
7914 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
7916 /* Note that we've used the skipped register. */
7917 if (mode == SFmode && ca->free_single_fp_reg)
7919 ca->free_single_fp_reg = 0;
7922 /* When we have a DF after an SF, there's an SF register that get
7923 skipped in order to align the DF value. We note this skipped
7924 register, because the next SF value will use it, and not the
7925 SF that follows the DF. */
7927 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
7929 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
7930 + BASE_ARG_REG (mode));
7934 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
7935 || PASS_IN_REG_P (*ca, mode, type))
7936 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
7937 = (ROUND_REG (*ca, mode)
7939 ? ROUND_ADVANCE (int_size_in_bytes (type))
7940 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
7943 /* The Renesas calling convention doesn't quite fit into this scheme since
7944 the address is passed like an invisible argument, but one that is always
7945 passed in memory. */
7947 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
7949 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7951 return gen_rtx_REG (Pmode, 2);
7954 /* Worker function for TARGET_RETURN_IN_MEMORY. */
7957 sh_return_in_memory (const_tree type, const_tree fndecl)
7961 if (TYPE_MODE (type) == BLKmode)
7962 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
7964 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
7968 return (TYPE_MODE (type) == BLKmode
7969 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7970 && TREE_CODE (type) == RECORD_TYPE));
7974 /* We actually emit the code in sh_expand_prologue. We used to use
7975 a static variable to flag that we need to emit this code, but that
7976 doesn't when inlining, when functions are deferred and then emitted
7977 later. Fortunately, we already have two flags that are part of struct
7978 function that tell if a function uses varargs or stdarg. */
7980 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
7981 enum machine_mode mode,
7983 int *pretend_arg_size,
7984 int second_time ATTRIBUTE_UNUSED)
7986 gcc_assert (cfun->stdarg);
7987 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
7989 int named_parm_regs, anon_parm_regs;
7991 named_parm_regs = (ROUND_REG (*ca, mode)
7993 ? ROUND_ADVANCE (int_size_in_bytes (type))
7994 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
7995 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
7996 if (anon_parm_regs > 0)
7997 *pretend_arg_size = anon_parm_regs * 4;
8002 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
8008 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
8010 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8014 /* Define the offset between two registers, one to be eliminated, and
8015 the other its replacement, at the start of a routine. */
8018 initial_elimination_offset (int from, int to)
8021 int regs_saved_rounding = 0;
8022 int total_saved_regs_space;
8023 int total_auto_space;
8024 int save_flags = target_flags;
8026 HARD_REG_SET live_regs_mask;
8028 shmedia_space_reserved_for_target_registers = false;
8029 regs_saved = calc_live_regs (&live_regs_mask);
8030 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8032 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8034 shmedia_space_reserved_for_target_registers = true;
8035 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8038 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8039 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8040 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8042 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8043 copy_flags = target_flags;
8044 target_flags = save_flags;
8046 total_saved_regs_space = regs_saved + regs_saved_rounding;
8048 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8049 return total_saved_regs_space + total_auto_space
8050 + crtl->args.info.byref_regs * 8;
8052 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8053 return total_saved_regs_space + total_auto_space
8054 + crtl->args.info.byref_regs * 8;
8056 /* Initial gap between fp and sp is 0. */
8057 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8060 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8061 return rounded_frame_size (0);
8063 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8064 return rounded_frame_size (0);
8066 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8067 && (to == HARD_FRAME_POINTER_REGNUM
8068 || to == STACK_POINTER_REGNUM));
8071 int n = total_saved_regs_space;
8072 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8073 save_schedule schedule;
8076 n += total_auto_space;
8078 /* If it wasn't saved, there's not much we can do. */
8079 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8082 target_flags = copy_flags;
8084 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8085 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8086 if (entry->reg == pr_reg)
8088 target_flags = save_flags;
8089 return entry->offset;
8094 return total_auto_space;
8097 /* Parse the -mfixed-range= option string. */
8099 sh_fix_range (const char *const_str)
8102 char *str, *dash, *comma;
8104 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8105 REG2 are either register names or register numbers. The effect
8106 of this option is to mark the registers in the range from REG1 to
8107 REG2 as ``fixed'' so they won't be used by the compiler. */
8109 i = strlen (const_str);
8110 str = (char *) alloca (i + 1);
8111 memcpy (str, const_str, i + 1);
8115 dash = strchr (str, '-');
8118 warning (0, "value of -mfixed-range must have form REG1-REG2");
8122 comma = strchr (dash + 1, ',');
8126 first = decode_reg_name (str);
8129 warning (0, "unknown register name: %s", str);
8133 last = decode_reg_name (dash + 1);
8136 warning (0, "unknown register name: %s", dash + 1);
8144 warning (0, "%s-%s is an empty range", str, dash + 1);
8148 for (i = first; i <= last; ++i)
8149 fixed_regs[i] = call_used_regs[i] = 1;
8159 /* Insert any deferred function attributes from earlier pragmas. */
8161 sh_insert_attributes (tree node, tree *attributes)
8165 if (TREE_CODE (node) != FUNCTION_DECL)
8168 /* We are only interested in fields. */
8172 /* Append the attributes to the deferred attributes. */
8173 *sh_deferred_function_attributes_tail = *attributes;
8174 attrs = sh_deferred_function_attributes;
8178 /* Some attributes imply or require the interrupt attribute. */
8179 if (!lookup_attribute ("interrupt_handler", attrs)
8180 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8182 /* If we have a trapa_handler, but no interrupt_handler attribute,
8183 insert an interrupt_handler attribute. */
8184 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8185 /* We can't use sh_pr_interrupt here because that's not in the
8188 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8189 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8190 if the interrupt attribute is missing, we ignore the attribute
8192 else if (lookup_attribute ("sp_switch", attrs)
8193 || lookup_attribute ("trap_exit", attrs)
8194 || lookup_attribute ("nosave_low_regs", attrs)
8195 || lookup_attribute ("resbank", attrs))
8199 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8201 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8202 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8203 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8204 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8205 warning (OPT_Wattributes,
8206 "%qE attribute only applies to interrupt functions",
8207 TREE_PURPOSE (attrs));
8210 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8212 tail = &TREE_CHAIN (*tail);
8215 attrs = *attributes;
8219 /* Install the processed list. */
8220 *attributes = attrs;
8222 /* Clear deferred attributes. */
8223 sh_deferred_function_attributes = NULL_TREE;
8224 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8229 /* Supported attributes:
8231 interrupt_handler -- specifies this function is an interrupt handler.
8233 trapa_handler - like above, but don't save all registers.
8235 sp_switch -- specifies an alternate stack for an interrupt handler
8238 trap_exit -- use a trapa to exit an interrupt function instead of
8241 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8242 This is useful on the SH3 and upwards,
8243 which has a separate set of low regs for User and Supervisor modes.
8244 This should only be used for the lowest level of interrupts. Higher levels
8245 of interrupts must save the registers in case they themselves are
8248 renesas -- use Renesas calling/layout conventions (functions and
8251 resbank -- In case of an ISR, use a register bank to save registers
8252 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8255 const struct attribute_spec sh_attribute_table[] =
8257 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8258 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8259 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
8260 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
8261 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
8262 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8263 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8264 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
8265 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
8267 /* Symbian support adds three new attributes:
8268 dllexport - for exporting a function/variable that will live in a dll
8269 dllimport - for importing a function/variable from a dll
8271 Microsoft allows multiple declspecs in one __declspec, separating
8272 them with spaces. We do NOT support this. Instead, use __declspec
8274 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8275 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8277 { NULL, 0, 0, false, false, false, NULL }
8280 /* Handle a 'resbank' attribute. */
8282 sh_handle_resbank_handler_attribute (tree * node, tree name,
8283 tree args ATTRIBUTE_UNUSED,
8284 int flags ATTRIBUTE_UNUSED,
8285 bool * no_add_attrs)
8289 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8291 *no_add_attrs = true;
8293 if (TREE_CODE (*node) != FUNCTION_DECL)
8295 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8297 *no_add_attrs = true;
8303 /* Handle an "interrupt_handler" attribute; arguments as in
8304 struct attribute_spec.handler. */
8306 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8307 tree args ATTRIBUTE_UNUSED,
8308 int flags ATTRIBUTE_UNUSED,
8311 if (TREE_CODE (*node) != FUNCTION_DECL)
8313 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8315 *no_add_attrs = true;
8317 else if (TARGET_SHCOMPACT)
8319 error ("attribute interrupt_handler is not compatible with -m5-compact");
8320 *no_add_attrs = true;
8326 /* Handle an 'function_vector' attribute; arguments as in
8327 struct attribute_spec.handler. */
8329 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8330 tree args ATTRIBUTE_UNUSED,
8331 int flags ATTRIBUTE_UNUSED,
8332 bool * no_add_attrs)
8336 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8338 *no_add_attrs = true;
8340 else if (TREE_CODE (*node) != FUNCTION_DECL)
8342 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8344 *no_add_attrs = true;
8346 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8348 /* The argument must be a constant integer. */
8349 warning (OPT_Wattributes,
8350 "%qE attribute argument not an integer constant",
8352 *no_add_attrs = true;
8354 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8356 /* The argument value must be between 0 to 255. */
8357 warning (OPT_Wattributes,
8358 "%qE attribute argument should be between 0 to 255",
8360 *no_add_attrs = true;
8365 /* Returns 1 if current function has been assigned the attribute
8366 'function_vector'. */
8368 sh2a_is_function_vector_call (rtx x)
8370 if (GET_CODE (x) == SYMBOL_REF
8371 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8373 tree tr = SYMBOL_REF_DECL (x);
8375 if (sh2a_function_vector_p (tr))
8382 /* Returns the function vector number, if the the attribute
8383 'function_vector' is assigned, otherwise returns zero. */
8385 sh2a_get_function_vector_number (rtx x)
8390 if ((GET_CODE (x) == SYMBOL_REF)
8391 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8393 t = SYMBOL_REF_DECL (x);
8395 if (TREE_CODE (t) != FUNCTION_DECL)
8398 list = SH_ATTRIBUTES (t);
8401 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8403 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8407 list = TREE_CHAIN (list);
8416 /* Handle an "sp_switch" attribute; arguments as in
8417 struct attribute_spec.handler. */
8419 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8420 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8422 if (TREE_CODE (*node) != FUNCTION_DECL)
8424 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8426 *no_add_attrs = true;
8428 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8430 /* The argument must be a constant string. */
8431 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
8433 *no_add_attrs = true;
8439 /* Handle an "trap_exit" attribute; arguments as in
8440 struct attribute_spec.handler. */
8442 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8443 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8445 if (TREE_CODE (*node) != FUNCTION_DECL)
8447 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8449 *no_add_attrs = true;
8451 /* The argument specifies a trap number to be used in a trapa instruction
8452 at function exit (instead of an rte instruction). */
8453 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8455 /* The argument must be a constant integer. */
8456 warning (OPT_Wattributes, "%qE attribute argument not an "
8457 "integer constant", name);
8458 *no_add_attrs = true;
8465 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8466 tree name ATTRIBUTE_UNUSED,
8467 tree args ATTRIBUTE_UNUSED,
8468 int flags ATTRIBUTE_UNUSED,
8469 bool *no_add_attrs ATTRIBUTE_UNUSED)
8474 /* True if __attribute__((renesas)) or -mrenesas. */
8476 sh_attr_renesas_p (const_tree td)
8483 td = TREE_TYPE (td);
8484 if (td == error_mark_node)
8486 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8490 /* True if __attribute__((renesas)) or -mrenesas, for the current
8493 sh_cfun_attr_renesas_p (void)
8495 return sh_attr_renesas_p (current_function_decl);
8499 sh_cfun_interrupt_handler_p (void)
8501 return (lookup_attribute ("interrupt_handler",
8502 DECL_ATTRIBUTES (current_function_decl))
8506 /* Returns 1 if FUNC has been assigned the attribute
8507 "function_vector". */
8509 sh2a_function_vector_p (tree func)
8512 if (TREE_CODE (func) != FUNCTION_DECL)
8515 list = SH_ATTRIBUTES (func);
8518 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8521 list = TREE_CHAIN (list);
8526 /* Returns TRUE if given tree has the "resbank" attribute. */
8529 sh_cfun_resbank_handler_p (void)
8531 return ((lookup_attribute ("resbank",
8532 DECL_ATTRIBUTES (current_function_decl))
8534 && (lookup_attribute ("interrupt_handler",
8535 DECL_ATTRIBUTES (current_function_decl))
8536 != NULL_TREE) && TARGET_SH2A);
8539 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8542 sh_check_pch_target_flags (int old_flags)
8544 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8545 | MASK_SH_E | MASK_HARD_SH4
8546 | MASK_FPU_SINGLE | MASK_SH4))
8547 return _("created and used with different architectures / ABIs");
8548 if ((old_flags ^ target_flags) & MASK_HITACHI)
8549 return _("created and used with different ABIs");
8550 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8551 return _("created and used with different endianness");
8555 /* Predicates used by the templates. */
8557 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8558 Used only in general_movsrc_operand. */
8561 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8573 /* Nonzero if OP is a floating point value with value 0.0. */
8576 fp_zero_operand (rtx op)
8580 if (GET_MODE (op) != SFmode)
8583 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8584 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8587 /* Nonzero if OP is a floating point value with value 1.0. */
8590 fp_one_operand (rtx op)
8594 if (GET_MODE (op) != SFmode)
8597 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8598 return REAL_VALUES_EQUAL (r, dconst1);
8601 /* For -m4 and -m4-single-only, mode switching is used. If we are
8602 compiling without -mfmovd, movsf_ie isn't taken into account for
8603 mode switching. We could check in machine_dependent_reorg for
8604 cases where we know we are in single precision mode, but there is
8605 interface to find that out during reload, so we must avoid
8606 choosing an fldi alternative during reload and thus failing to
8607 allocate a scratch register for the constant loading. */
8611 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
8615 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8617 enum rtx_code code = GET_CODE (op);
8618 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8621 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8623 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8625 if (GET_CODE (op) != SYMBOL_REF)
8626 return TLS_MODEL_NONE;
8627 return SYMBOL_REF_TLS_MODEL (op);
8630 /* Return the destination address of a branch. */
8633 branch_dest (rtx branch)
8635 rtx dest = SET_SRC (PATTERN (branch));
8638 if (GET_CODE (dest) == IF_THEN_ELSE)
8639 dest = XEXP (dest, 1);
8640 dest = XEXP (dest, 0);
8641 dest_uid = INSN_UID (dest);
8642 return INSN_ADDRESSES (dest_uid);
8645 /* Return nonzero if REG is not used after INSN.
8646 We assume REG is a reload reg, and therefore does
8647 not live past labels. It may live past calls or jumps though. */
8649 reg_unused_after (rtx reg, rtx insn)
8654 /* If the reg is set by this instruction, then it is safe for our
8655 case. Disregard the case where this is a store to memory, since
8656 we are checking a register used in the store address. */
8657 set = single_set (insn);
8658 if (set && !MEM_P (SET_DEST (set))
8659 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8662 while ((insn = NEXT_INSN (insn)))
8668 code = GET_CODE (insn);
8671 /* If this is a label that existed before reload, then the register
8672 if dead here. However, if this is a label added by reorg, then
8673 the register may still be live here. We can't tell the difference,
8674 so we just ignore labels completely. */
8675 if (code == CODE_LABEL)
8680 if (code == JUMP_INSN)
8683 /* If this is a sequence, we must handle them all at once.
8684 We could have for instance a call that sets the target register,
8685 and an insn in a delay slot that uses the register. In this case,
8686 we must return 0. */
8687 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8692 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8694 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
8695 rtx set = single_set (this_insn);
8697 if (CALL_P (this_insn))
8699 else if (JUMP_P (this_insn))
8701 if (INSN_ANNULLED_BRANCH_P (this_insn))
8706 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8708 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8710 if (!MEM_P (SET_DEST (set)))
8716 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8721 else if (code == JUMP_INSN)
8725 set = single_set (insn);
8726 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8728 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8729 return !MEM_P (SET_DEST (set));
8730 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8733 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
8741 static GTY(()) rtx fpscr_rtx;
8743 get_fpscr_rtx (void)
8747 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
8748 REG_USERVAR_P (fpscr_rtx) = 1;
8749 mark_user_reg (fpscr_rtx);
8751 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
8752 mark_user_reg (fpscr_rtx);
8756 static GTY(()) tree fpscr_values;
8759 emit_fpu_switch (rtx scratch, int index)
8763 if (fpscr_values == NULL)
8767 t = build_index_type (integer_one_node);
8768 t = build_array_type (integer_type_node, t);
8769 t = build_decl (VAR_DECL, get_identifier ("__fpscr_values"), t);
8770 DECL_ARTIFICIAL (t) = 1;
8771 DECL_IGNORED_P (t) = 1;
8772 DECL_EXTERNAL (t) = 1;
8773 TREE_STATIC (t) = 1;
8774 TREE_PUBLIC (t) = 1;
8780 src = DECL_RTL (fpscr_values);
8781 if (!can_create_pseudo_p ())
8783 emit_move_insn (scratch, XEXP (src, 0));
8785 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
8786 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
8789 src = adjust_address (src, PSImode, index * 4);
8791 dst = get_fpscr_rtx ();
8792 emit_move_insn (dst, src);
8796 emit_sf_insn (rtx pat)
8802 emit_df_insn (rtx pat)
8808 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8810 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8814 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8816 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
8821 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8823 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8827 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8829 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
8833 static rtx get_free_reg (HARD_REG_SET);
8835 /* This function returns a register to use to load the address to load
8836 the fpscr from. Currently it always returns r1 or r7, but when we are
8837 able to use pseudo registers after combine, or have a better mechanism
8838 for choosing a register, it should be done here. */
8839 /* REGS_LIVE is the liveness information for the point for which we
8840 need this allocation. In some bare-bones exit blocks, r1 is live at the
8841 start. We can even have all of r0..r3 being live:
8842 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
8843 INSN before which new insns are placed with will clobber the register
8844 we return. If a basic block consists only of setting the return value
8845 register to a pseudo and using that register, the return value is not
8846 live before or after this block, yet we we'll insert our insns right in
8850 get_free_reg (HARD_REG_SET regs_live)
8852 if (! TEST_HARD_REG_BIT (regs_live, 1))
8853 return gen_rtx_REG (Pmode, 1);
8855 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
8856 there shouldn't be anything but a jump before the function end. */
8857 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
8858 return gen_rtx_REG (Pmode, 7);
8861 /* This function will set the fpscr from memory.
8862 MODE is the mode we are setting it to. */
8864 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
8866 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
8867 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
8870 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
8871 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
8874 /* Is the given character a logical line separator for the assembler? */
8875 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
8876 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
8880 sh_insn_length_adjustment (rtx insn)
8882 /* Instructions with unfilled delay slots take up an extra two bytes for
8883 the nop in the delay slot. */
8884 if (((NONJUMP_INSN_P (insn)
8885 && GET_CODE (PATTERN (insn)) != USE
8886 && GET_CODE (PATTERN (insn)) != CLOBBER)
8889 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8890 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
8891 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
8892 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
8895 /* SH2e has a bug that prevents the use of annulled branches, so if
8896 the delay slot is not filled, we'll have to put a NOP in it. */
8897 if (sh_cpu_attr == CPU_SH2E
8899 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8900 && GET_CODE (PATTERN (insn)) != ADDR_VEC
8901 && get_attr_type (insn) == TYPE_CBRANCH
8902 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
8905 /* sh-dsp parallel processing insn take four bytes instead of two. */
8907 if (NONJUMP_INSN_P (insn))
8910 rtx body = PATTERN (insn);
8913 int maybe_label = 1;
8915 if (GET_CODE (body) == ASM_INPUT)
8916 templ = XSTR (body, 0);
8917 else if (asm_noperands (body) >= 0)
8919 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
8928 while (c == ' ' || c == '\t');
8929 /* all sh-dsp parallel-processing insns start with p.
8930 The only non-ppi sh insn starting with p is pref.
8931 The only ppi starting with pr is prnd. */
8932 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
8934 /* The repeat pseudo-insn expands two three insns, a total of
8935 six bytes in size. */
8936 else if ((c == 'r' || c == 'R')
8937 && ! strncasecmp ("epeat", templ, 5))
8939 while (c && c != '\n'
8940 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
8942 /* If this is a label, it is obviously not a ppi insn. */
8943 if (c == ':' && maybe_label)
8948 else if (c == '\'' || c == '"')
8953 maybe_label = c != ':';
8961 /* Return TRUE for a valid displacement for the REG+disp addressing
8964 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
8965 into the FRx registers. We implement this by setting the maximum offset
8966 to zero when the value is SFmode. This also restricts loading of SFmode
8967 values into the integer registers, but that can't be helped. */
8969 /* The SH allows a displacement in a QI or HI amode, but only when the
8970 other operand is R0. GCC doesn't handle this very well, so we forgot
8973 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
8974 DI can be any number 0..60. */
8977 sh_legitimate_index_p (enum machine_mode mode, rtx op)
8979 if (CONST_INT_P (op))
8985 /* Check if this the address of an unaligned load / store. */
8986 if (mode == VOIDmode)
8987 return CONST_OK_FOR_I06 (INTVAL (op));
8989 size = GET_MODE_SIZE (mode);
8990 return (!(INTVAL (op) & (size - 1))
8991 && INTVAL (op) >= -512 * size
8992 && INTVAL (op) < 512 * size);
8997 if (GET_MODE_SIZE (mode) == 1
8998 && (unsigned) INTVAL (op) < 4096)
9002 if ((GET_MODE_SIZE (mode) == 4
9003 && (unsigned) INTVAL (op) < 64
9004 && !(INTVAL (op) & 3)
9005 && !(TARGET_SH2E && mode == SFmode))
9006 || (GET_MODE_SIZE (mode) == 4
9007 && (unsigned) INTVAL (op) < 16383
9008 && !(INTVAL (op) & 3) && TARGET_SH2A))
9011 if ((GET_MODE_SIZE (mode) == 8
9012 && (unsigned) INTVAL (op) < 60
9013 && !(INTVAL (op) & 3)
9014 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9015 || ((GET_MODE_SIZE (mode)==8)
9016 && (unsigned) INTVAL (op) < 8192
9017 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9018 && (TARGET_SH2A && mode == DFmode)))
9025 /* Recognize an RTL expression that is a valid memory address for
9027 The MODE argument is the machine mode for the MEM expression
9028 that wants to use this address.
9036 sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9038 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9040 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9042 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9044 else if (GET_CODE (x) == PLUS
9045 && (mode != PSImode || reload_completed))
9047 rtx xop0 = XEXP (x, 0);
9048 rtx xop1 = XEXP (x, 1);
9050 if (GET_MODE_SIZE (mode) <= 8
9051 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9052 && sh_legitimate_index_p (mode, xop1))
9055 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9056 || ((xop0 == stack_pointer_rtx
9057 || xop0 == hard_frame_pointer_rtx)
9058 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9059 || ((xop1 == stack_pointer_rtx
9060 || xop1 == hard_frame_pointer_rtx)
9061 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9062 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9063 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9064 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9065 && TARGET_FMOVD && mode == DFmode)))
9067 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9068 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9070 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9071 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9079 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9080 isn't protected by a PIC unspec. */
9082 nonpic_symbol_mentioned_p (rtx x)
9084 register const char *fmt;
9087 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9088 || GET_CODE (x) == PC)
9091 /* We don't want to look into the possible MEM location of a
9092 CONST_DOUBLE, since we're not going to use it, in general. */
9093 if (GET_CODE (x) == CONST_DOUBLE)
9096 if (GET_CODE (x) == UNSPEC
9097 && (XINT (x, 1) == UNSPEC_PIC
9098 || XINT (x, 1) == UNSPEC_GOT
9099 || XINT (x, 1) == UNSPEC_GOTOFF
9100 || XINT (x, 1) == UNSPEC_GOTPLT
9101 || XINT (x, 1) == UNSPEC_GOTTPOFF
9102 || XINT (x, 1) == UNSPEC_DTPOFF
9103 || XINT (x, 1) == UNSPEC_PLT
9104 || XINT (x, 1) == UNSPEC_SYMOFF
9105 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
9108 fmt = GET_RTX_FORMAT (GET_CODE (x));
9109 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9115 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9116 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9119 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9126 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9127 @GOTOFF in `reg'. */
9129 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9132 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9135 if (GET_CODE (orig) == LABEL_REF
9136 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9139 reg = gen_reg_rtx (Pmode);
9141 emit_insn (gen_symGOTOFF2reg (reg, orig));
9144 else if (GET_CODE (orig) == SYMBOL_REF)
9147 reg = gen_reg_rtx (Pmode);
9149 emit_insn (gen_symGOT2reg (reg, orig));
9155 /* Try machine-dependent ways of modifying an illegitimate address
9156 to be legitimate. If we find one, return the new, valid address.
9157 Otherwise, return X.
9159 For the SH, if X is almost suitable for indexing, but the offset is
9160 out of range, convert it into a normal form so that CSE has a chance
9161 of reducing the number of address registers used. */
9164 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9167 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9169 if (GET_CODE (x) == PLUS
9170 && (GET_MODE_SIZE (mode) == 4
9171 || GET_MODE_SIZE (mode) == 8)
9172 && CONST_INT_P (XEXP (x, 1))
9173 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9175 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9176 && ! (TARGET_SH2E && mode == SFmode))
9178 rtx index_rtx = XEXP (x, 1);
9179 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9182 /* On rare occasions, we might get an unaligned pointer
9183 that is indexed in a way to give an aligned address.
9184 Therefore, keep the lower two bits in offset_base. */
9185 /* Instead of offset_base 128..131 use 124..127, so that
9186 simple add suffices. */
9188 offset_base = ((offset + 4) & ~60) - 4;
9190 offset_base = offset & ~60;
9192 /* Sometimes the normal form does not suit DImode. We
9193 could avoid that by using smaller ranges, but that
9194 would give less optimized code when SImode is
9196 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9198 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9199 GEN_INT (offset_base), NULL_RTX, 0,
9202 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9209 /* Mark the use of a constant in the literal table. If the constant
9210 has multiple labels, make it unique. */
9212 mark_constant_pool_use (rtx x)
9214 rtx insn, lab, pattern;
9219 switch (GET_CODE (x))
9229 /* Get the first label in the list of labels for the same constant
9230 and delete another labels in the list. */
9232 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
9235 || LABEL_REFS (insn) != NEXT_INSN (insn))
9240 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9241 INSN_DELETED_P (insn) = 1;
9243 /* Mark constants in a window. */
9244 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
9246 if (!NONJUMP_INSN_P (insn))
9249 pattern = PATTERN (insn);
9250 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9253 switch (XINT (pattern, 1))
9255 case UNSPECV_CONST2:
9256 case UNSPECV_CONST4:
9257 case UNSPECV_CONST8:
9258 XVECEXP (pattern, 0, 1) = const1_rtx;
9260 case UNSPECV_WINDOW_END:
9261 if (XVECEXP (pattern, 0, 0) == x)
9264 case UNSPECV_CONST_END:
9274 /* Return true if it's possible to redirect BRANCH1 to the destination
9275 of an unconditional jump BRANCH2. We only want to do this if the
9276 resulting branch will have a short displacement. */
9278 sh_can_redirect_branch (rtx branch1, rtx branch2)
9280 if (flag_expensive_optimizations && simplejump_p (branch2))
9282 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
9286 for (distance = 0, insn = NEXT_INSN (branch1);
9287 insn && distance < 256;
9288 insn = PREV_INSN (insn))
9293 distance += get_attr_length (insn);
9295 for (distance = 0, insn = NEXT_INSN (branch1);
9296 insn && distance < 256;
9297 insn = NEXT_INSN (insn))
9302 distance += get_attr_length (insn);
9308 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9310 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9311 unsigned int new_reg)
9313 /* Interrupt functions can only use registers that have already been
9314 saved by the prologue, even if they would normally be
9317 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
9323 /* Function to update the integer COST
9324 based on the relationship between INSN that is dependent on
9325 DEP_INSN through the dependence LINK. The default is to make no
9326 adjustment to COST. This can be used for example to specify to
9327 the scheduler that an output- or anti-dependence does not incur
9328 the same cost as a data-dependence. The return value should be
9329 the new value for COST. */
9331 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
9337 /* On SHmedia, if the dependence is an anti-dependence or
9338 output-dependence, there is no cost. */
9339 if (REG_NOTE_KIND (link) != 0)
9341 /* However, dependencies between target register loads and
9342 uses of the register in a subsequent block that are separated
9343 by a conditional branch are not modelled - we have to do with
9344 the anti-dependency between the target register load and the
9345 conditional branch that ends the current block. */
9346 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9347 && GET_CODE (PATTERN (dep_insn)) == SET
9348 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
9349 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
9350 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
9352 int orig_cost = cost;
9353 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
9354 rtx target = ((! note
9355 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
9356 ? insn : JUMP_LABEL (insn));
9357 /* On the likely path, the branch costs 1, on the unlikely path,
9361 target = next_active_insn (target);
9362 while (target && ! flow_dependent_p (target, dep_insn)
9364 /* If two branches are executed in immediate succession, with the
9365 first branch properly predicted, this causes a stall at the
9366 second branch, hence we won't need the target for the
9367 second branch for two cycles after the launch of the first
9369 if (cost > orig_cost - 2)
9370 cost = orig_cost - 2;
9376 else if (get_attr_is_mac_media (insn)
9377 && get_attr_is_mac_media (dep_insn))
9380 else if (! reload_completed
9381 && GET_CODE (PATTERN (insn)) == SET
9382 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9383 && GET_CODE (PATTERN (dep_insn)) == SET
9384 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9387 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9388 that is needed at the target. */
9389 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9390 && ! flow_dependent_p (insn, dep_insn))
9393 else if (REG_NOTE_KIND (link) == 0)
9395 enum attr_type type;
9398 if (recog_memoized (insn) < 0
9399 || recog_memoized (dep_insn) < 0)
9402 dep_set = single_set (dep_insn);
9404 /* The latency that we specify in the scheduling description refers
9405 to the actual output, not to an auto-increment register; for that,
9406 the latency is one. */
9407 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9409 rtx set = single_set (insn);
9412 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9413 && (!MEM_P (SET_DEST (set))
9414 || !reg_mentioned_p (SET_DEST (dep_set),
9415 XEXP (SET_DEST (set), 0))))
9418 /* The only input for a call that is timing-critical is the
9419 function's address. */
9422 rtx call = PATTERN (insn);
9424 if (GET_CODE (call) == PARALLEL)
9425 call = XVECEXP (call, 0 ,0);
9426 if (GET_CODE (call) == SET)
9427 call = SET_SRC (call);
9428 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
9429 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9430 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9431 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9432 cost -= TARGET_SH4_300 ? 3 : 6;
9434 /* Likewise, the most timing critical input for an sfuncs call
9435 is the function address. However, sfuncs typically start
9436 using their arguments pretty quickly.
9437 Assume a four cycle delay for SH4 before they are needed.
9438 Cached ST40-300 calls are quicker, so assume only a one
9440 ??? Maybe we should encode the delays till input registers
9441 are needed by sfuncs into the sfunc call insn. */
9442 /* All sfunc calls are parallels with at least four components.
9443 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9444 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9445 && XVECLEN (PATTERN (insn), 0) >= 4
9446 && (reg = sfunc_uses_reg (insn)))
9448 if (! reg_set_p (reg, dep_insn))
9449 cost -= TARGET_SH4_300 ? 1 : 4;
9451 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9453 enum attr_type dep_type = get_attr_type (dep_insn);
9455 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9457 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9458 && (type = get_attr_type (insn)) != TYPE_CALL
9459 && type != TYPE_SFUNC)
9461 /* When the preceding instruction loads the shift amount of
9462 the following SHAD/SHLD, the latency of the load is increased
9464 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9465 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9466 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9467 XEXP (SET_SRC (single_set (insn)),
9470 /* When an LS group instruction with a latency of less than
9471 3 cycles is followed by a double-precision floating-point
9472 instruction, FIPR, or FTRV, the latency of the first
9473 instruction is increased to 3 cycles. */
9475 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9476 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9478 /* The lsw register of a double-precision computation is ready one
9480 else if (reload_completed
9481 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9482 && (use_pat = single_set (insn))
9483 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9487 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9488 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9491 else if (TARGET_SH4_300)
9493 /* Stores need their input register two cycles later. */
9494 if (dep_set && cost >= 1
9495 && ((type = get_attr_type (insn)) == TYPE_STORE
9496 || type == TYPE_PSTORE
9497 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9499 rtx set = single_set (insn);
9501 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9502 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9505 /* But don't reduce the cost below 1 if the address depends
9506 on a side effect of dep_insn. */
9508 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9514 /* An anti-dependence penalty of two applies if the first insn is a double
9515 precision fadd / fsub / fmul. */
9516 else if (!TARGET_SH4_300
9517 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9518 && recog_memoized (dep_insn) >= 0
9519 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9520 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9521 /* A lot of alleged anti-flow dependences are fake,
9522 so check this one is real. */
9523 && flow_dependent_p (dep_insn, insn))
9529 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9530 if DEP_INSN is anti-flow dependent on INSN. */
9532 flow_dependent_p (rtx insn, rtx dep_insn)
9534 rtx tmp = PATTERN (insn);
9536 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9537 return tmp == NULL_RTX;
9540 /* A helper function for flow_dependent_p called through note_stores. */
9542 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9544 rtx * pinsn = (rtx *) data;
9546 if (*pinsn && reg_referenced_p (x, *pinsn))
9550 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9551 'special function' patterns (type sfunc) that clobber pr, but that
9552 do not look like function calls to leaf_function_p. Hence we must
9553 do this extra check. */
9557 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9560 /* Return where to allocate pseudo for a given hard register initial
9563 sh_allocate_initial_value (rtx hard_reg)
9567 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9569 if (current_function_is_leaf
9570 && ! sh_pr_n_sets ()
9571 && ! (TARGET_SHCOMPACT
9572 && ((crtl->args.info.call_cookie
9573 & ~ CALL_COOKIE_RET_TRAMP (1))
9574 || crtl->saves_all_registers)))
9577 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9585 /* This function returns "2" to indicate dual issue for the SH4
9586 processor. To be used by the DFA pipeline description. */
9588 sh_issue_rate (void)
9590 if (TARGET_SUPERSCALAR)
9596 /* Functions for ready queue reordering for sched1. */
9598 /* Get weight for mode for a set x. */
9600 find_set_regmode_weight (rtx x, enum machine_mode mode)
9602 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9604 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9606 if (REG_P (SET_DEST (x)))
9608 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9618 /* Get regmode weight for insn. */
9620 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9622 short reg_weight = 0;
9625 /* Increment weight for each register born here. */
9627 reg_weight += find_set_regmode_weight (x, mode);
9628 if (GET_CODE (x) == PARALLEL)
9631 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9633 x = XVECEXP (PATTERN (insn), 0, j);
9634 reg_weight += find_set_regmode_weight (x, mode);
9637 /* Decrement weight for each register that dies here. */
9638 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9640 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9642 rtx note = XEXP (x, 0);
9643 if (REG_P (note) && GET_MODE (note) == mode)
9650 /* Calculate regmode weights for all insns of a basic block. */
9652 find_regmode_weight (basic_block b, enum machine_mode mode)
9654 rtx insn, next_tail, head, tail;
9656 get_ebb_head_tail (b, b, &head, &tail);
9657 next_tail = NEXT_INSN (tail);
9659 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9661 /* Handle register life information. */
9666 INSN_REGMODE_WEIGHT (insn, mode) =
9667 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9668 else if (mode == SImode)
9669 INSN_REGMODE_WEIGHT (insn, mode) =
9670 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9674 /* Comparison function for ready queue sorting. */
9676 rank_for_reorder (const void *x, const void *y)
9678 rtx tmp = *(const rtx *) y;
9679 rtx tmp2 = *(const rtx *) x;
9681 /* The insn in a schedule group should be issued the first. */
9682 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9683 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9685 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9686 minimizes instruction movement, thus minimizing sched's effect on
9687 register pressure. */
9688 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9691 /* Resort the array A in which only element at index N may be out of order. */
9693 swap_reorder (rtx *a, int n)
9695 rtx insn = a[n - 1];
9698 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9706 #define SCHED_REORDER(READY, N_READY) \
9709 if ((N_READY) == 2) \
9710 swap_reorder (READY, N_READY); \
9711 else if ((N_READY) > 2) \
9712 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
9716 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
9719 ready_reorder (rtx *ready, int nready)
9721 SCHED_REORDER (ready, nready);
9724 /* Count life regions of r0 for a block. */
9726 find_r0_life_regions (basic_block b)
9735 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
9748 r0_reg = gen_rtx_REG (SImode, R0_REG);
9753 if (find_regno_note (insn, REG_DEAD, R0_REG))
9759 && (pset = single_set (insn))
9760 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
9761 && !find_regno_note (insn, REG_UNUSED, R0_REG))
9769 insn = NEXT_INSN (insn);
9774 /* Calculate regmode weights for all insns of all basic block. */
9776 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
9777 int verbose ATTRIBUTE_UNUSED,
9782 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
9783 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
9784 r0_life_regions = 0;
9786 FOR_EACH_BB_REVERSE (b)
9788 find_regmode_weight (b, SImode);
9789 find_regmode_weight (b, SFmode);
9790 if (!reload_completed)
9791 r0_life_regions += find_r0_life_regions (b);
9794 CURR_REGMODE_PRESSURE (SImode) = 0;
9795 CURR_REGMODE_PRESSURE (SFmode) = 0;
9801 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
9802 int verbose ATTRIBUTE_UNUSED)
9804 if (regmode_weight[0])
9806 free (regmode_weight[0]);
9807 regmode_weight[0] = NULL;
9809 if (regmode_weight[1])
9811 free (regmode_weight[1]);
9812 regmode_weight[1] = NULL;
9816 /* The scalar modes supported differs from the default version in TImode
9817 for 32-bit SHMEDIA. */
9819 sh_scalar_mode_supported_p (enum machine_mode mode)
9821 if (TARGET_SHMEDIA32 && mode == TImode)
9824 return default_scalar_mode_supported_p (mode);
9827 /* Cache the can_issue_more so that we can return it from reorder2. Also,
9828 keep count of register pressures on SImode and SFmode. */
9830 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
9831 int sched_verbose ATTRIBUTE_UNUSED,
9835 if (GET_CODE (PATTERN (insn)) != USE
9836 && GET_CODE (PATTERN (insn)) != CLOBBER)
9837 cached_can_issue_more = can_issue_more - 1;
9839 cached_can_issue_more = can_issue_more;
9841 if (reload_completed)
9842 return cached_can_issue_more;
9844 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
9845 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
9847 return cached_can_issue_more;
9851 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
9852 int verbose ATTRIBUTE_UNUSED,
9853 int veclen ATTRIBUTE_UNUSED)
9855 CURR_REGMODE_PRESSURE (SImode) = 0;
9856 CURR_REGMODE_PRESSURE (SFmode) = 0;
9859 /* Some magic numbers. */
9860 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9861 functions that already have high pressure on r0. */
9862 #define R0_MAX_LIFE_REGIONS 2
9863 /* Register Pressure thresholds for SImode and SFmode registers. */
9864 #define SIMODE_MAX_WEIGHT 5
9865 #define SFMODE_MAX_WEIGHT 10
9867 /* Return true if the pressure is high for MODE. */
9869 high_pressure (enum machine_mode mode)
9871 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9872 functions that already have high pressure on r0. */
9873 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
9877 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
9879 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
9882 /* Reorder ready queue if register pressure is high. */
9884 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
9885 int sched_verbose ATTRIBUTE_UNUSED,
9888 int clock_var ATTRIBUTE_UNUSED)
9890 if (reload_completed)
9891 return sh_issue_rate ();
9893 if (high_pressure (SFmode) || high_pressure (SImode))
9895 ready_reorder (ready, *n_readyp);
9898 return sh_issue_rate ();
9901 /* Skip cycles if the current register pressure is high. */
9903 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
9904 int sched_verbose ATTRIBUTE_UNUSED,
9905 rtx *ready ATTRIBUTE_UNUSED,
9906 int *n_readyp ATTRIBUTE_UNUSED,
9907 int clock_var ATTRIBUTE_UNUSED)
9909 if (reload_completed)
9910 return cached_can_issue_more;
9912 if (high_pressure(SFmode) || high_pressure (SImode))
9915 return cached_can_issue_more;
9918 /* Skip cycles without sorting the ready queue. This will move insn from
9919 Q->R. If this is the last cycle we are skipping; allow sorting of ready
9920 queue by sh_reorder. */
9922 /* Generally, skipping these many cycles are sufficient for all insns to move
9927 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
9928 int sched_verbose ATTRIBUTE_UNUSED,
9929 rtx insn ATTRIBUTE_UNUSED,
9934 if (reload_completed)
9939 if ((clock_var - last_clock_var) < MAX_SKIPS)
9944 /* If this is the last cycle we are skipping, allow reordering of R. */
9945 if ((clock_var - last_clock_var) == MAX_SKIPS)
9957 /* SHmedia requires registers for branches, so we can't generate new
9958 branches past reload. */
9960 sh_cannot_modify_jumps_p (void)
9962 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
9965 static enum reg_class
9966 sh_target_reg_class (void)
9968 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
9972 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
9979 if (! shmedia_space_reserved_for_target_registers)
9981 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
9983 if (calc_live_regs (&dummy) >= 6 * 8)
9989 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
9991 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
9995 On the SH1..SH4, the trampoline looks like
9996 2 0002 D202 mov.l l2,r2
9997 1 0000 D301 mov.l l1,r3
10000 5 0008 00000000 l1: .long area
10001 6 000c 00000000 l2: .long function
10003 SH5 (compact) uses r1 instead of r3 for the static chain. */
10006 /* Emit RTL insns to initialize the variable parts of a trampoline.
10007 FNADDR is an RTX for the address of the function's pure code.
10008 CXT is an RTX for the static chain value for the function. */
10011 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
10013 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
10015 if (TARGET_SHMEDIA64)
10020 rtx movi1 = GEN_INT (0xcc000010);
10021 rtx shori1 = GEN_INT (0xc8000010);
10024 /* The following trampoline works within a +- 128 KB range for cxt:
10025 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10026 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10027 gettr tr1,r1; blink tr0,r63 */
10028 /* Address rounding makes it hard to compute the exact bounds of the
10029 offset for this trampoline, but we have a rather generous offset
10030 range, so frame_offset should do fine as an upper bound. */
10031 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10033 /* ??? could optimize this trampoline initialization
10034 by writing DImode words with two insns each. */
10035 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10036 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10037 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10038 insn = gen_rtx_AND (DImode, insn, mask);
10039 /* Or in ptb/u .,tr1 pattern */
10040 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10041 insn = force_operand (insn, NULL_RTX);
10042 insn = gen_lowpart (SImode, insn);
10043 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
10044 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10045 insn = gen_rtx_AND (DImode, insn, mask);
10046 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10047 insn = gen_lowpart (SImode, insn);
10048 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
10049 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10050 insn = gen_rtx_AND (DImode, insn, mask);
10051 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10052 insn = gen_lowpart (SImode, insn);
10053 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
10054 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10055 insn = gen_rtx_AND (DImode, insn, mask);
10056 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10057 insn = gen_lowpart (SImode, insn);
10058 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
10059 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10060 insn = gen_rtx_AND (DImode, insn, mask);
10061 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10062 insn = gen_lowpart (SImode, insn);
10063 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10064 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
10065 GEN_INT (0x6bf10600));
10066 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
10067 GEN_INT (0x4415fc10));
10068 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
10069 GEN_INT (0x4401fff0));
10070 emit_insn (gen_ic_invalidate_line (tramp));
10073 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10074 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10076 tramp_templ = gen_datalabel_ref (tramp_templ);
10078 src = gen_const_mem (BLKmode, tramp_templ);
10079 set_mem_align (dst, 256);
10080 set_mem_align (src, 64);
10081 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
10083 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10084 emit_move_insn (adjust_address (tramp_mem, Pmode,
10085 fixed_len + GET_MODE_SIZE (Pmode)),
10087 emit_insn (gen_ic_invalidate_line (tramp));
10090 else if (TARGET_SHMEDIA)
10092 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10093 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10094 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10095 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10096 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10097 rotated 10 right, and higher 16 bit of every 32 selected. */
10099 = force_reg (V2HImode, (simplify_gen_subreg
10100 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10101 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10102 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10104 tramp = force_reg (Pmode, tramp);
10105 fnaddr = force_reg (SImode, fnaddr);
10106 cxt = force_reg (SImode, cxt);
10107 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10108 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10110 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
10111 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10112 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
10113 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
10114 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10115 gen_rtx_SUBREG (V2HImode, cxt, 0),
10117 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
10118 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10119 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
10120 if (TARGET_LITTLE_ENDIAN)
10122 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10123 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10127 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10128 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10130 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10131 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
10132 emit_insn (gen_ic_invalidate_line (tramp));
10135 else if (TARGET_SHCOMPACT)
10137 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10140 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
10141 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10143 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
10144 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10146 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10147 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
10148 if (TARGET_HARVARD)
10150 if (!TARGET_INLINE_IC_INVALIDATE
10151 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
10152 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10153 FUNCTION_ORDINARY),
10154 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
10156 emit_insn (gen_ic_invalidate_line (tramp));
10160 /* FIXME: This is overly conservative. A SHcompact function that
10161 receives arguments ``by reference'' will have them stored in its
10162 own stack frame, so it must not pass pointers or references to
10163 these arguments to other functions by means of sibling calls. */
10164 /* If PIC, we cannot make sibling calls to global functions
10165 because the PLT requires r12 to be live. */
10167 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10170 && (! TARGET_SHCOMPACT
10171 || crtl->args.info.stack_regs == 0)
10172 && ! sh_cfun_interrupt_handler_p ()
10174 || (decl && ! TREE_PUBLIC (decl))
10175 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10178 /* Machine specific built-in functions. */
10180 struct builtin_description
10182 const enum insn_code icode;
10183 const char *const name;
10187 /* describe number and signedness of arguments; arg[0] == result
10188 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10189 /* 9: 64-bit pointer, 10: 32-bit pointer */
10190 static const char signature_args[][4] =
10192 #define SH_BLTIN_V2SI2 0
10194 #define SH_BLTIN_V4HI2 1
10196 #define SH_BLTIN_V2SI3 2
10198 #define SH_BLTIN_V4HI3 3
10200 #define SH_BLTIN_V8QI3 4
10202 #define SH_BLTIN_MAC_HISI 5
10204 #define SH_BLTIN_SH_HI 6
10206 #define SH_BLTIN_SH_SI 7
10208 #define SH_BLTIN_V4HI2V2SI 8
10210 #define SH_BLTIN_V4HI2V8QI 9
10212 #define SH_BLTIN_SISF 10
10214 #define SH_BLTIN_LDUA_L 11
10216 #define SH_BLTIN_LDUA_Q 12
10218 #define SH_BLTIN_STUA_L 13
10220 #define SH_BLTIN_STUA_Q 14
10222 #define SH_BLTIN_LDUA_L64 15
10224 #define SH_BLTIN_LDUA_Q64 16
10226 #define SH_BLTIN_STUA_L64 17
10228 #define SH_BLTIN_STUA_Q64 18
10230 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10231 #define SH_BLTIN_2 19
10232 #define SH_BLTIN_SU 19
10234 #define SH_BLTIN_3 20
10235 #define SH_BLTIN_SUS 20
10237 #define SH_BLTIN_PSSV 21
10239 #define SH_BLTIN_XXUU 22
10240 #define SH_BLTIN_UUUU 22
10242 #define SH_BLTIN_PV 23
10245 /* mcmv: operands considered unsigned. */
10246 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10247 /* mperm: control value considered unsigned int. */
10248 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10249 /* mshards_q: returns signed short. */
10250 /* nsb: takes long long arg, returns unsigned char. */
10251 static const struct builtin_description bdesc[] =
10253 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
10254 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
10255 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
10256 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
10257 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
10258 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
10259 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
10260 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
10261 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
10262 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
10263 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
10264 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
10265 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
10266 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
10267 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
10268 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
10269 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
10270 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
10271 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
10272 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
10273 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
10274 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
10275 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
10276 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
10277 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
10278 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
10279 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
10280 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
10281 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
10282 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
10283 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
10284 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
10285 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
10286 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
10287 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
10288 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
10289 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
10290 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
10291 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
10292 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
10293 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
10294 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
10295 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
10296 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
10297 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
10298 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
10299 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
10300 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
10301 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
10302 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
10303 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
10304 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
10305 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
10306 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
10307 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
10308 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
10309 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
10310 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
10311 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
10312 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
10313 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
10314 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
10315 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
10316 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
10317 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
10318 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
10319 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
10320 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
10321 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
10322 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
10323 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
10324 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
10325 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
10326 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
10327 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
10328 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
10329 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
10330 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
10331 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
10332 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
10333 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
10334 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
10335 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
10336 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
10340 sh_media_init_builtins (void)
10342 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10343 const struct builtin_description *d;
10345 memset (shared, 0, sizeof shared);
10346 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
10348 tree type, arg_type = 0;
10349 int signature = d->signature;
10352 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10353 type = shared[signature];
10356 int has_result = signature_args[signature][0] != 0;
10358 if ((signature_args[signature][1] & 8)
10359 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
10360 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
10362 if (! TARGET_FPU_ANY
10363 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10365 type = void_list_node;
10368 int arg = signature_args[signature][i];
10369 int opno = i - 1 + has_result;
10372 arg_type = ptr_type_node;
10374 arg_type = (*lang_hooks.types.type_for_mode)
10375 (insn_data[d->icode].operand[opno].mode,
10380 arg_type = void_type_node;
10383 type = tree_cons (NULL_TREE, arg_type, type);
10385 type = build_function_type (arg_type, type);
10386 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10387 shared[signature] = type;
10389 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10394 /* Implements target hook vector_mode_supported_p. */
10396 sh_vector_mode_supported_p (enum machine_mode mode)
10399 && ((mode == V2SFmode)
10400 || (mode == V4SFmode)
10401 || (mode == V16SFmode)))
10404 else if (TARGET_SHMEDIA
10405 && ((mode == V8QImode)
10406 || (mode == V2HImode)
10407 || (mode == V4HImode)
10408 || (mode == V2SImode)))
10414 /* Implements target hook dwarf_calling_convention. Return an enum
10415 of dwarf_calling_convention. */
10417 sh_dwarf_calling_convention (const_tree func)
10419 if (sh_attr_renesas_p (func))
10420 return DW_CC_GNU_renesas_sh;
10422 return DW_CC_normal;
10426 sh_init_builtins (void)
10428 if (TARGET_SHMEDIA)
10429 sh_media_init_builtins ();
10432 /* Expand an expression EXP that calls a built-in function,
10433 with result going to TARGET if that's convenient
10434 (and in mode MODE if that's convenient).
10435 SUBTARGET may be used as the target for computing one of EXP's operands.
10436 IGNORE is nonzero if the value is to be ignored. */
10439 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10440 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10442 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10443 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10444 const struct builtin_description *d = &bdesc[fcode];
10445 enum insn_code icode = d->icode;
10446 int signature = d->signature;
10447 enum machine_mode tmode = VOIDmode;
10452 if (signature_args[signature][0])
10457 tmode = insn_data[icode].operand[0].mode;
10459 || GET_MODE (target) != tmode
10460 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10461 target = gen_reg_rtx (tmode);
10462 op[nop++] = target;
10467 for (i = 1; i <= 3; i++, nop++)
10470 enum machine_mode opmode, argmode;
10473 if (! signature_args[signature][i])
10475 arg = CALL_EXPR_ARG (exp, i - 1);
10476 if (arg == error_mark_node)
10478 if (signature_args[signature][i] & 8)
10481 optype = ptr_type_node;
10485 opmode = insn_data[icode].operand[nop].mode;
10486 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10488 argmode = TYPE_MODE (TREE_TYPE (arg));
10489 if (argmode != opmode)
10490 arg = build1 (NOP_EXPR, optype, arg);
10491 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
10492 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10493 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10499 pat = (*insn_data[d->icode].genfun) (op[0]);
10502 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10505 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10508 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10511 gcc_unreachable ();
10520 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
10522 rtx sel0 = const0_rtx;
10523 rtx sel1 = const1_rtx;
10524 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
10525 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10527 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10528 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10532 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
10534 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10536 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10537 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
10540 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
10541 We can allow any mode in any general register. The special registers
10542 only allow SImode. Don't allow any mode in the PR.
10544 We cannot hold DCmode values in the XD registers because alter_reg
10545 handles subregs of them incorrectly. We could work around this by
10546 spacing the XD registers like the DR registers, but this would require
10547 additional memory in every compilation to hold larger register vectors.
10548 We could hold SFmode / SCmode values in XD registers, but that
10549 would require a tertiary reload when reloading from / to memory,
10550 and a secondary reload to reload from / to general regs; that
10551 seems to be a loosing proposition.
10553 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10554 it won't be ferried through GP registers first. */
10557 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10559 if (SPECIAL_REGISTER_P (regno))
10560 return mode == SImode;
10562 if (regno == FPUL_REG)
10563 return (mode == SImode || mode == SFmode);
10565 if (FP_REGISTER_P (regno) && mode == SFmode)
10568 if (mode == V2SFmode)
10570 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
10571 || GENERAL_REGISTER_P (regno)))
10577 if (mode == V4SFmode)
10579 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
10580 || GENERAL_REGISTER_P (regno))
10586 if (mode == V16SFmode)
10588 if (TARGET_SHMEDIA)
10590 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
10596 return regno == FIRST_XD_REG;
10599 if (FP_REGISTER_P (regno))
10603 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
10604 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
10607 && (mode == DFmode || mode == DImode
10608 || mode == V2SFmode || mode == TImode)))
10609 && ((regno - FIRST_FP_REG) & 1) == 0)
10610 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
10611 && ((regno - FIRST_FP_REG) & 3) == 0))
10617 if (XD_REGISTER_P (regno))
10618 return mode == DFmode;
10620 if (TARGET_REGISTER_P (regno))
10621 return (mode == DImode || mode == SImode || mode == PDImode);
10623 if (regno == PR_REG)
10624 return mode == SImode;
10626 if (regno == FPSCR_REG)
10627 return mode == PSImode;
10629 /* FIXME. This works around PR target/37633 for -O0. */
10630 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
10632 unsigned int n = GET_MODE_SIZE (mode) / 8;
10634 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
10635 && regno <= FIRST_GENERAL_REG + 14)
10642 /* Return the class of registers for which a mode change from FROM to TO
10645 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
10646 enum reg_class rclass)
10648 /* We want to enable the use of SUBREGs as a means to
10649 VEC_SELECT a single element of a vector. */
10650 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10651 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
10653 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10655 if (TARGET_LITTLE_ENDIAN)
10657 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10658 return reg_classes_intersect_p (DF_REGS, rclass);
10662 if (GET_MODE_SIZE (from) < 8)
10663 return reg_classes_intersect_p (DF_HI_REGS, rclass);
10670 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10671 that label is used. */
10674 sh_mark_label (rtx address, int nuses)
10676 if (GOTOFF_P (address))
10678 /* Extract the label or symbol. */
10679 address = XEXP (address, 0);
10680 if (GET_CODE (address) == PLUS)
10681 address = XEXP (address, 0);
10682 address = XVECEXP (address, 0, 0);
10684 if (GET_CODE (address) == LABEL_REF
10685 && LABEL_P (XEXP (address, 0)))
10686 LABEL_NUSES (XEXP (address, 0)) += nuses;
10689 /* Compute extra cost of moving data between one register class
10692 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10693 uses this information. Hence, the general register <-> floating point
10694 register information here is not used for SFmode. */
10697 sh_register_move_cost (enum machine_mode mode,
10698 enum reg_class srcclass, enum reg_class dstclass)
10700 if (dstclass == T_REGS || dstclass == PR_REGS)
10703 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10706 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
10707 && REGCLASS_HAS_FP_REG (srcclass)
10708 && REGCLASS_HAS_FP_REG (dstclass))
10711 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10712 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10714 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
10715 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
10718 if ((REGCLASS_HAS_FP_REG (dstclass)
10719 && REGCLASS_HAS_GENERAL_REG (srcclass))
10720 || (REGCLASS_HAS_GENERAL_REG (dstclass)
10721 && REGCLASS_HAS_FP_REG (srcclass)))
10722 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
10723 * ((GET_MODE_SIZE (mode) + 7) / 8U));
10725 if ((dstclass == FPUL_REGS
10726 && REGCLASS_HAS_GENERAL_REG (srcclass))
10727 || (srcclass == FPUL_REGS
10728 && REGCLASS_HAS_GENERAL_REG (dstclass)))
10731 if ((dstclass == FPUL_REGS
10732 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
10733 || (srcclass == FPUL_REGS
10734 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
10737 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10738 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10741 /* ??? ptabs faults on (value & 0x3) == 0x3 */
10743 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
10745 if (sh_gettrcost >= 0)
10746 return sh_gettrcost;
10747 else if (!TARGET_PT_FIXED)
10751 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10752 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10757 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
10758 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
10759 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
10761 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
10764 static rtx emit_load_ptr (rtx, rtx);
10767 emit_load_ptr (rtx reg, rtx addr)
10769 rtx mem = gen_const_mem (ptr_mode, addr);
10771 if (Pmode != ptr_mode)
10772 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
10773 return emit_move_insn (reg, mem);
10777 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10778 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10781 CUMULATIVE_ARGS cum;
10782 int structure_value_byref = 0;
10783 rtx this_rtx, this_value, sibcall, insns, funexp;
10784 tree funtype = TREE_TYPE (function);
10785 int simple_add = CONST_OK_FOR_ADD (delta);
10787 rtx scratch0, scratch1, scratch2;
10790 reload_completed = 1;
10791 epilogue_completed = 1;
10792 current_function_uses_only_leaf_regs = 1;
10794 emit_note (NOTE_INSN_PROLOGUE_END);
10796 /* Find the "this" pointer. We have such a wide range of ABIs for the
10797 SH that it's best to do this completely machine independently.
10798 "this" is passed as first argument, unless a structure return pointer
10799 comes first, in which case "this" comes second. */
10800 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
10801 #ifndef PCC_STATIC_STRUCT_RETURN
10802 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10803 structure_value_byref = 1;
10804 #endif /* not PCC_STATIC_STRUCT_RETURN */
10805 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
10807 tree ptype = build_pointer_type (TREE_TYPE (funtype));
10809 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
10811 this_rtx = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
10813 /* For SHcompact, we only have r0 for a scratch register: r1 is the
10814 static chain pointer (even if you can't have nested virtual functions
10815 right now, someone might implement them sometime), and the rest of the
10816 registers are used for argument passing, are callee-saved, or reserved. */
10817 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
10818 -ffixed-reg has been used. */
10819 if (! call_used_regs[0] || fixed_regs[0])
10820 error ("r0 needs to be available as a call-clobbered register");
10821 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
10824 if (call_used_regs[1] && ! fixed_regs[1])
10825 scratch1 = gen_rtx_REG (ptr_mode, 1);
10826 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
10827 pointing where to return struct values. */
10828 if (call_used_regs[3] && ! fixed_regs[3])
10829 scratch2 = gen_rtx_REG (Pmode, 3);
10831 else if (TARGET_SHMEDIA)
10833 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
10834 if (i != REGNO (scratch0) &&
10835 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
10837 scratch1 = gen_rtx_REG (ptr_mode, i);
10840 if (scratch1 == scratch0)
10841 error ("Need a second call-clobbered general purpose register");
10842 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
10843 if (call_used_regs[i] && ! fixed_regs[i])
10845 scratch2 = gen_rtx_REG (Pmode, i);
10848 if (scratch2 == scratch0)
10849 error ("Need a call-clobbered target register");
10852 this_value = plus_constant (this_rtx, delta);
10854 && (simple_add || scratch0 != scratch1)
10855 && strict_memory_address_p (ptr_mode, this_value))
10857 emit_load_ptr (scratch0, this_value);
10862 ; /* Do nothing. */
10863 else if (simple_add)
10864 emit_move_insn (this_rtx, this_value);
10867 emit_move_insn (scratch1, GEN_INT (delta));
10868 emit_insn (gen_add2_insn (this_rtx, scratch1));
10876 emit_load_ptr (scratch0, this_rtx);
10878 offset_addr = plus_constant (scratch0, vcall_offset);
10879 if (strict_memory_address_p (ptr_mode, offset_addr))
10880 ; /* Do nothing. */
10881 else if (! TARGET_SH5 && scratch0 != scratch1)
10883 /* scratch0 != scratch1, and we have indexed loads. Get better
10884 schedule by loading the offset into r1 and using an indexed
10885 load - then the load of r1 can issue before the load from
10886 (this_rtx + delta) finishes. */
10887 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10888 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
10890 else if (CONST_OK_FOR_ADD (vcall_offset))
10892 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
10893 offset_addr = scratch0;
10895 else if (scratch0 != scratch1)
10897 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10898 emit_insn (gen_add2_insn (scratch0, scratch1));
10899 offset_addr = scratch0;
10902 gcc_unreachable (); /* FIXME */
10903 emit_load_ptr (scratch0, offset_addr);
10905 if (Pmode != ptr_mode)
10906 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
10907 emit_insn (gen_add2_insn (this_rtx, scratch0));
10910 /* Generate a tail call to the target function. */
10911 if (! TREE_USED (function))
10913 assemble_external (function);
10914 TREE_USED (function) = 1;
10916 funexp = XEXP (DECL_RTL (function), 0);
10917 /* If the function is overridden, so is the thunk, hence we don't
10918 need GOT addressing even if this is a public symbol. */
10920 if (TARGET_SH1 && ! flag_weak)
10921 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
10924 if (TARGET_SH2 && flag_pic)
10926 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
10927 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
10931 if (TARGET_SHMEDIA && flag_pic)
10933 funexp = gen_sym2PIC (funexp);
10934 PUT_MODE (funexp, Pmode);
10936 emit_move_insn (scratch2, funexp);
10937 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
10938 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
10940 sibcall = emit_call_insn (sibcall);
10941 SIBLING_CALL_P (sibcall) = 1;
10942 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
10945 /* Run just enough of rest_of_compilation to do scheduling and get
10946 the insns emitted. Note that use_thunk calls
10947 assemble_start_function and assemble_end_function. */
10949 insn_locators_alloc ();
10950 insns = get_insns ();
10956 split_all_insns_noflow ();
10961 if (optimize > 0 && flag_delayed_branch)
10962 dbr_schedule (insns);
10964 shorten_branches (insns);
10965 final_start_function (insns, file, 1);
10966 final (insns, file, 1);
10967 final_end_function ();
10968 free_after_compilation (cfun);
10970 reload_completed = 0;
10971 epilogue_completed = 0;
10975 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
10979 /* If this is not an ordinary function, the name usually comes from a
10980 string literal or an sprintf buffer. Make sure we use the same
10981 string consistently, so that cse will be able to unify address loads. */
10982 if (kind != FUNCTION_ORDINARY)
10983 name = IDENTIFIER_POINTER (get_identifier (name));
10984 sym = gen_rtx_SYMBOL_REF (Pmode, name);
10985 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
10989 case FUNCTION_ORDINARY:
10993 rtx reg = target ? target : gen_reg_rtx (Pmode);
10995 emit_insn (gen_symGOT2reg (reg, sym));
11001 /* ??? To allow cse to work, we use GOTOFF relocations.
11002 we could add combiner patterns to transform this into
11003 straight pc-relative calls with sym2PIC / bsrf when
11004 label load and function call are still 1:1 and in the
11005 same basic block during combine. */
11006 rtx reg = target ? target : gen_reg_rtx (Pmode);
11008 emit_insn (gen_symGOTOFF2reg (reg, sym));
11013 if (target && sym != target)
11015 emit_move_insn (target, sym);
11021 /* Find the number of a general purpose register in S. */
11023 scavenge_reg (HARD_REG_SET *s)
11026 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11027 if (TEST_HARD_REG_BIT (*s, r))
11033 sh_get_pr_initial_val (void)
11037 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11038 PR register on SHcompact, because it might be clobbered by the prologue.
11039 We check first if that is known to be the case. */
11040 if (TARGET_SHCOMPACT
11041 && ((crtl->args.info.call_cookie
11042 & ~ CALL_COOKIE_RET_TRAMP (1))
11043 || crtl->saves_all_registers))
11044 return gen_frame_mem (SImode, return_address_pointer_rtx);
11046 /* If we haven't finished rtl generation, there might be a nonlocal label
11047 that we haven't seen yet.
11048 ??? get_hard_reg_initial_val fails if it is called after register
11049 allocation has started, unless it has been called before for the
11050 same register. And even then, we end in trouble if we didn't use
11051 the register in the same basic block before. So call
11052 get_hard_reg_initial_val now and wrap it in an unspec if we might
11053 need to replace it. */
11054 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11055 combine can put the pseudo returned by get_hard_reg_initial_val into
11056 instructions that need a general purpose registers, which will fail to
11057 be recognized when the pseudo becomes allocated to PR. */
11059 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
11061 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11066 sh_expand_t_scc (rtx operands[])
11068 enum rtx_code code = GET_CODE (operands[1]);
11069 rtx target = operands[0];
11070 rtx op0 = operands[2];
11071 rtx op1 = operands[3];
11072 rtx result = target;
11075 if (!REG_P (op0) || REGNO (op0) != T_REG
11076 || !CONST_INT_P (op1))
11078 if (!REG_P (result))
11079 result = gen_reg_rtx (SImode);
11080 val = INTVAL (op1);
11081 if ((code == EQ && val == 1) || (code == NE && val == 0))
11082 emit_insn (gen_movt (result));
11083 else if (TARGET_SH2A && ((code == EQ && val == 0)
11084 || (code == NE && val == 1)))
11085 emit_insn (gen_xorsi3_movrt (result));
11086 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11088 emit_clobber (result);
11089 emit_insn (gen_subc (result, result, result));
11090 emit_insn (gen_addsi3 (result, result, const1_rtx));
11092 else if (code == EQ || code == NE)
11093 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11096 if (result != target)
11097 emit_move_insn (target, result);
11101 /* INSN is an sfunc; return the rtx that describes the address used. */
11103 extract_sfunc_addr (rtx insn)
11105 rtx pattern, part = NULL_RTX;
11108 pattern = PATTERN (insn);
11109 len = XVECLEN (pattern, 0);
11110 for (i = 0; i < len; i++)
11112 part = XVECEXP (pattern, 0, i);
11113 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11114 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11115 return XEXP (part, 0);
11117 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11118 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11121 /* Verify that the register in use_sfunc_addr still agrees with the address
11122 used in the sfunc. This prevents fill_slots_from_thread from changing
11124 INSN is the use_sfunc_addr instruction, and REG is the register it
11127 check_use_sfunc_addr (rtx insn, rtx reg)
11129 /* Search for the sfunc. It should really come right after INSN. */
11130 while ((insn = NEXT_INSN (insn)))
11132 if (LABEL_P (insn) || JUMP_P (insn))
11134 if (! INSN_P (insn))
11137 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11138 insn = XVECEXP (PATTERN (insn), 0, 0);
11139 if (GET_CODE (PATTERN (insn)) != PARALLEL
11140 || get_attr_type (insn) != TYPE_SFUNC)
11142 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11144 gcc_unreachable ();
11147 /* This function returns a constant rtx that represents pi / 2**15 in
11148 SFmode. it's used to scale SFmode angles, in radians, to a
11149 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11150 maps to 0x10000). */
11152 static GTY(()) rtx sh_fsca_sf2int_rtx;
11155 sh_fsca_sf2int (void)
11157 if (! sh_fsca_sf2int_rtx)
11159 REAL_VALUE_TYPE rv;
11161 real_from_string (&rv, "10430.378350470453");
11162 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11165 return sh_fsca_sf2int_rtx;
11168 /* This function returns a constant rtx that represents pi / 2**15 in
11169 DFmode. it's used to scale DFmode angles, in radians, to a
11170 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11171 maps to 0x10000). */
11173 static GTY(()) rtx sh_fsca_df2int_rtx;
11176 sh_fsca_df2int (void)
11178 if (! sh_fsca_df2int_rtx)
11180 REAL_VALUE_TYPE rv;
11182 real_from_string (&rv, "10430.378350470453");
11183 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
11186 return sh_fsca_df2int_rtx;
11189 /* This function returns a constant rtx that represents 2**15 / pi in
11190 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
11191 of a full circle back to a SFmode value, i.e., 0x10000 maps to
11194 static GTY(()) rtx sh_fsca_int2sf_rtx;
11197 sh_fsca_int2sf (void)
11199 if (! sh_fsca_int2sf_rtx)
11201 REAL_VALUE_TYPE rv;
11203 real_from_string (&rv, "9.587379924285257e-5");
11204 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
11207 return sh_fsca_int2sf_rtx;
11210 /* Initialize the CUMULATIVE_ARGS structure. */
11213 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
11215 rtx libname ATTRIBUTE_UNUSED,
11217 signed int n_named_args,
11218 enum machine_mode mode)
11220 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
11221 pcum->free_single_fp_reg = 0;
11222 pcum->stack_regs = 0;
11223 pcum->byref_regs = 0;
11225 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
11227 /* XXX - Should we check TARGET_HITACHI here ??? */
11228 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
11232 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
11233 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
11234 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
11235 pcum->arg_count [(int) SH_ARG_INT]
11236 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
11239 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11240 && pcum->arg_count [(int) SH_ARG_INT] == 0
11241 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
11242 ? int_size_in_bytes (TREE_TYPE (fntype))
11243 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
11244 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
11245 == FIRST_RET_REG));
11249 pcum->arg_count [(int) SH_ARG_INT] = 0;
11250 pcum->prototype_p = FALSE;
11251 if (mode != VOIDmode)
11253 pcum->call_cookie =
11254 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11255 && GET_MODE_SIZE (mode) > 4
11256 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
11258 /* If the default ABI is the Renesas ABI then all library
11259 calls must assume that the library will be using the
11260 Renesas ABI. So if the function would return its result
11261 in memory then we must force the address of this memory
11262 block onto the stack. Ideally we would like to call
11263 targetm.calls.return_in_memory() here but we do not have
11264 the TYPE or the FNDECL available so we synthesize the
11265 contents of that function as best we can. */
11267 (TARGET_DEFAULT & MASK_HITACHI)
11268 && (mode == BLKmode
11269 || (GET_MODE_SIZE (mode) > 4
11270 && !(mode == DFmode
11271 && TARGET_FPU_DOUBLE)));
11275 pcum->call_cookie = 0;
11276 pcum->force_mem = FALSE;
11281 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
11282 not enter into CONST_DOUBLE for the replace.
11284 Note that copying is not done so X must not be shared unless all copies
11285 are to be modified.
11287 This is like replace_rtx, except that we operate on N_REPLACEMENTS
11288 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
11289 replacements[n*2+1] - and that we take mode changes into account.
11291 If a replacement is ambiguous, return NULL_RTX.
11293 If MODIFY is zero, don't modify any rtl in place,
11294 just return zero or nonzero for failure / success. */
11297 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
11302 /* The following prevents loops occurrence when we change MEM in
11303 CONST_DOUBLE onto the same CONST_DOUBLE. */
11304 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
11307 for (i = n_replacements - 1; i >= 0 ; i--)
11308 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
11309 return replacements[i*2+1];
11311 /* Allow this function to make replacements in EXPR_LISTs. */
11315 if (GET_CODE (x) == SUBREG)
11317 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
11318 n_replacements, modify);
11320 if (CONST_INT_P (new_rtx))
11322 x = simplify_subreg (GET_MODE (x), new_rtx,
11323 GET_MODE (SUBREG_REG (x)),
11329 SUBREG_REG (x) = new_rtx;
11333 else if (REG_P (x))
11335 unsigned regno = REGNO (x);
11336 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
11337 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11338 rtx result = NULL_RTX;
11340 for (i = n_replacements - 1; i >= 0; i--)
11342 rtx from = replacements[i*2];
11343 rtx to = replacements[i*2+1];
11344 unsigned from_regno, from_nregs, to_regno, new_regno;
11348 from_regno = REGNO (from);
11349 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
11350 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
11351 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
11353 if (regno < from_regno
11354 || regno + nregs > from_regno + nregs
11358 to_regno = REGNO (to);
11359 if (to_regno < FIRST_PSEUDO_REGISTER)
11361 new_regno = regno + to_regno - from_regno;
11362 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
11365 result = gen_rtx_REG (GET_MODE (x), new_regno);
11367 else if (GET_MODE (x) <= GET_MODE (to))
11368 result = gen_lowpart_common (GET_MODE (x), to);
11370 result = gen_lowpart_SUBREG (GET_MODE (x), to);
11373 return result ? result : x;
11375 else if (GET_CODE (x) == ZERO_EXTEND)
11377 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
11378 n_replacements, modify);
11380 if (CONST_INT_P (new_rtx))
11382 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
11383 new_rtx, GET_MODE (XEXP (x, 0)));
11388 XEXP (x, 0) = new_rtx;
11393 fmt = GET_RTX_FORMAT (GET_CODE (x));
11394 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
11400 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
11401 n_replacements, modify);
11405 XEXP (x, i) = new_rtx;
11407 else if (fmt[i] == 'E')
11408 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11410 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
11411 n_replacements, modify);
11415 XVECEXP (x, i, j) = new_rtx;
11423 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
11425 enum rtx_code code = TRUNCATE;
11427 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11429 rtx inner = XEXP (x, 0);
11430 enum machine_mode inner_mode = GET_MODE (inner);
11432 if (inner_mode == mode)
11434 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11436 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11437 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11439 code = GET_CODE (x);
11443 return gen_rtx_fmt_e (code, mode, x);
11446 /* called via for_each_rtx after reload, to clean up truncates of
11447 registers that span multiple actual hard registers. */
11449 shmedia_cleanup_truncate (rtx *p, void *n_changes)
11453 if (GET_CODE (x) != TRUNCATE)
11456 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
11458 enum machine_mode reg_mode = GET_MODE (reg);
11459 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
11460 subreg_lowpart_offset (DImode, reg_mode));
11461 *(int*) n_changes += 1;
11467 /* Load and store depend on the highpart of the address. However,
11468 set_attr_alternative does not give well-defined results before reload,
11469 so we must look at the rtl ourselves to see if any of the feeding
11470 registers is used in a memref. */
11472 /* Called by sh_contains_memref_p via for_each_rtx. */
11474 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
11476 return (MEM_P (*loc));
11479 /* Return nonzero iff INSN contains a MEM. */
11481 sh_contains_memref_p (rtx insn)
11483 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11486 /* Return nonzero iff INSN loads a banked register. */
11488 sh_loads_bankedreg_p (rtx insn)
11490 if (GET_CODE (PATTERN (insn)) == SET)
11492 rtx op = SET_DEST (PATTERN(insn));
11493 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11500 /* FNADDR is the MEM expression from a call expander. Return an address
11501 to use in an SHmedia insn pattern. */
11503 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11507 fnaddr = XEXP (fnaddr, 0);
11508 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11509 if (flag_pic && is_sym)
11511 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11513 rtx reg = gen_reg_rtx (Pmode);
11515 /* We must not use GOTPLT for sibcalls, because PIC_REG
11516 must be restored before the PLT code gets to run. */
11518 emit_insn (gen_symGOT2reg (reg, fnaddr));
11520 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11525 fnaddr = gen_sym2PIC (fnaddr);
11526 PUT_MODE (fnaddr, Pmode);
11529 /* If ptabs might trap, make this visible to the rest of the compiler.
11530 We generally assume that symbols pertain to valid locations, but
11531 it is possible to generate invalid symbols with asm or linker tricks.
11532 In a list of functions where each returns its successor, an invalid
11533 symbol might denote an empty list. */
11534 if (!TARGET_PT_FIXED
11535 && (!is_sym || TARGET_INVALID_SYMBOLS)
11536 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11538 rtx tr = gen_reg_rtx (PDImode);
11540 emit_insn (gen_ptabs (tr, fnaddr));
11543 else if (! target_reg_operand (fnaddr, Pmode))
11544 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11549 sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
11550 enum machine_mode mode, secondary_reload_info *sri)
11554 if (REGCLASS_HAS_FP_REG (rclass)
11555 && ! TARGET_SHMEDIA
11556 && immediate_operand ((x), mode)
11557 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11558 && mode == SFmode && fldi_ok ()))
11562 sri->icode = CODE_FOR_reload_insf__frn;
11565 sri->icode = CODE_FOR_reload_indf__frn;
11568 /* ??? If we knew that we are in the appropriate mode -
11569 single precision - we could use a reload pattern directly. */
11574 if (rclass == FPUL_REGS
11576 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11577 || REGNO (x) == T_REG))
11578 || GET_CODE (x) == PLUS))
11579 return GENERAL_REGS;
11580 if (rclass == FPUL_REGS && immediate_operand (x, mode))
11582 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11583 return GENERAL_REGS;
11584 else if (mode == SFmode)
11586 sri->icode = CODE_FOR_reload_insi__i_fpul;
11589 if (rclass == FPSCR_REGS
11590 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11591 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
11592 return GENERAL_REGS;
11593 if (REGCLASS_HAS_FP_REG (rclass)
11595 && immediate_operand (x, mode)
11596 && x != CONST0_RTX (GET_MODE (x))
11597 && GET_MODE (x) != V4SFmode)
11598 return GENERAL_REGS;
11599 if ((mode == QImode || mode == HImode)
11600 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11602 sri->icode = ((mode == QImode)
11603 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11606 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
11607 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
11608 return TARGET_REGS;
11609 } /* end of input-only processing. */
11611 if (((REGCLASS_HAS_FP_REG (rclass)
11613 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11614 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11615 && TARGET_FMOVD))))
11616 || (REGCLASS_HAS_GENERAL_REG (rclass)
11618 && FP_REGISTER_P (REGNO (x))))
11619 && ! TARGET_SHMEDIA
11620 && (mode == SFmode || mode == SImode))
11622 if ((rclass == FPUL_REGS
11623 || (REGCLASS_HAS_FP_REG (rclass)
11624 && ! TARGET_SHMEDIA && mode == SImode))
11627 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11628 || REGNO (x) == T_REG
11629 || system_reg_operand (x, VOIDmode)))))
11631 if (rclass == FPUL_REGS)
11632 return GENERAL_REGS;
11635 if ((rclass == TARGET_REGS
11636 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
11637 && !satisfies_constraint_Csy (x)
11638 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
11639 return GENERAL_REGS;
11640 if ((rclass == MAC_REGS || rclass == PR_REGS)
11641 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
11642 && rclass != REGNO_REG_CLASS (REGNO (x)))
11643 return GENERAL_REGS;
11644 if (rclass != GENERAL_REGS && REG_P (x)
11645 && TARGET_REGISTER_P (REGNO (x)))
11646 return GENERAL_REGS;
11650 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;