1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "insn-config.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
40 #include "integrate.h"
44 #include "target-def.h"
46 #include "langhooks.h"
47 #include "basic-block.h"
49 #include "cfglayout.h"
51 #include "sched-int.h"
55 #include "alloc-pool.h"
56 #include "tm-constrs.h"
59 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
61 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
62 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
64 /* These are some macros to abstract register modes. */
65 #define CONST_OK_FOR_ADD(size) \
66 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
67 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
68 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
69 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
71 /* Used to simplify the logic below. Find the attributes wherever
73 #define SH_ATTRIBUTES(decl) \
74 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
75 : DECL_ATTRIBUTES (decl) \
76 ? (DECL_ATTRIBUTES (decl)) \
77 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
79 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
80 int current_function_interrupt;
82 tree sh_deferred_function_attributes;
83 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
85 /* Global variables for machine-dependent things. */
87 /* Which cpu are we scheduling for. */
88 enum processor_type sh_cpu;
90 /* Definitions used in ready queue reordering for first scheduling pass. */
92 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
93 static short *regmode_weight[2];
95 /* Total SFmode and SImode weights of scheduled insns. */
96 static int curr_regmode_pressure[2];
98 /* Number of r0 life regions. */
99 static int r0_life_regions;
101 /* If true, skip cycles for Q -> R movement. */
102 static int skip_cycles = 0;
104 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
105 and returned from sh_reorder2. */
106 static short cached_can_issue_more;
108 /* Saved operands from the last compare to use when we generate an scc
114 /* Provides the class number of the smallest class containing
117 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
119 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
152 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
153 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
154 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
155 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
156 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
157 GENERAL_REGS, GENERAL_REGS,
160 char sh_register_names[FIRST_PSEUDO_REGISTER] \
161 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
163 char sh_additional_register_names[ADDREGNAMES_SIZE] \
164 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
165 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
167 int assembler_dialect;
169 static bool shmedia_space_reserved_for_target_registers;
171 static bool sh_handle_option (size_t, const char *, int);
172 static void split_branches (rtx);
173 static int branch_dest (rtx);
174 static void force_into (rtx, rtx);
175 static void print_slot (rtx);
176 static rtx add_constant (rtx, enum machine_mode, rtx);
177 static void dump_table (rtx, rtx);
178 static int hi_const (rtx);
179 static int broken_move (rtx);
180 static int mova_p (rtx);
181 static rtx find_barrier (int, rtx, rtx);
182 static int noncall_uses_reg (rtx, rtx, rtx *);
183 static rtx gen_block_redirect (rtx, int, int);
184 static void sh_reorg (void);
185 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
186 static rtx frame_insn (rtx);
187 static rtx push (int);
188 static void pop (int);
189 static void push_regs (HARD_REG_SET *, int);
190 static int calc_live_regs (HARD_REG_SET *);
191 static HOST_WIDE_INT rounded_frame_size (int);
192 static rtx mark_constant_pool_use (rtx);
193 const struct attribute_spec sh_attribute_table[];
194 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
195 static tree sh_handle_resbank_handler_attribute (tree *, tree,
197 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
199 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
200 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
201 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
202 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
203 static void sh_insert_attributes (tree, tree *);
204 static const char *sh_check_pch_target_flags (int);
205 static int sh_adjust_cost (rtx, rtx, rtx, int);
206 static int sh_issue_rate (void);
207 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
208 static short find_set_regmode_weight (rtx, enum machine_mode);
209 static short find_insn_regmode_weight (rtx, enum machine_mode);
210 static void find_regmode_weight (basic_block, enum machine_mode);
211 static int find_r0_life_regions (basic_block);
212 static void sh_md_init_global (FILE *, int, int);
213 static void sh_md_finish_global (FILE *, int);
214 static int rank_for_reorder (const void *, const void *);
215 static void swap_reorder (rtx *, int);
216 static void ready_reorder (rtx *, int);
217 static short high_pressure (enum machine_mode);
218 static int sh_reorder (FILE *, int, rtx *, int *, int);
219 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
220 static void sh_md_init (FILE *, int, int);
221 static int sh_variable_issue (FILE *, int, rtx, int);
223 static bool sh_function_ok_for_sibcall (tree, tree);
225 static bool sh_cannot_modify_jumps_p (void);
226 static enum reg_class sh_target_reg_class (void);
227 static bool sh_optimize_target_register_callee_saved (bool);
228 static bool sh_ms_bitfield_layout_p (const_tree);
230 static void sh_init_builtins (void);
231 static void sh_media_init_builtins (void);
232 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
233 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
234 static void sh_file_start (void);
235 static int flow_dependent_p (rtx, rtx);
236 static void flow_dependent_p_1 (rtx, const_rtx, void *);
237 static int shiftcosts (rtx);
238 static int andcosts (rtx);
239 static int addsubcosts (rtx);
240 static int multcosts (rtx);
241 static bool unspec_caller_rtx_p (rtx);
242 static bool sh_cannot_copy_insn_p (rtx);
243 static bool sh_rtx_costs (rtx, int, int, int *, bool);
244 static int sh_address_cost (rtx, bool);
245 static int sh_pr_n_sets (void);
246 static rtx sh_allocate_initial_value (rtx);
247 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
248 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
249 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
250 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
251 static int scavenge_reg (HARD_REG_SET *s);
252 struct save_schedule_s;
253 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
254 struct save_schedule_s *, int);
256 static rtx sh_struct_value_rtx (tree, int);
257 static bool sh_return_in_memory (const_tree, const_tree);
258 static rtx sh_builtin_saveregs (void);
259 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
260 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
261 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
262 static tree sh_build_builtin_va_list (void);
263 static void sh_va_start (tree, rtx);
264 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
265 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
267 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
269 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
271 static bool sh_scalar_mode_supported_p (enum machine_mode);
272 static int sh_dwarf_calling_convention (const_tree);
273 static void sh_encode_section_info (tree, rtx, int);
274 static int sh2a_function_vector_p (tree);
277 /* Initialize the GCC target structure. */
278 #undef TARGET_ATTRIBUTE_TABLE
279 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
281 /* The next two are used for debug info when compiling with -gdwarf. */
282 #undef TARGET_ASM_UNALIGNED_HI_OP
283 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
284 #undef TARGET_ASM_UNALIGNED_SI_OP
285 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
287 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
288 #undef TARGET_ASM_UNALIGNED_DI_OP
289 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
290 #undef TARGET_ASM_ALIGNED_DI_OP
291 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
293 #undef TARGET_ASM_FUNCTION_EPILOGUE
294 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
296 #undef TARGET_ASM_OUTPUT_MI_THUNK
297 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
299 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
300 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
302 #undef TARGET_ASM_FILE_START
303 #define TARGET_ASM_FILE_START sh_file_start
304 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
305 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
307 #undef TARGET_DEFAULT_TARGET_FLAGS
308 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
309 #undef TARGET_HANDLE_OPTION
310 #define TARGET_HANDLE_OPTION sh_handle_option
312 #undef TARGET_INSERT_ATTRIBUTES
313 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
315 #undef TARGET_SCHED_ADJUST_COST
316 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
318 #undef TARGET_SCHED_ISSUE_RATE
319 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
321 /* The next 5 hooks have been implemented for reenabling sched1. With the
322 help of these macros we are limiting the movement of insns in sched1 to
323 reduce the register pressure. The overall idea is to keep count of SImode
324 and SFmode regs required by already scheduled insns. When these counts
325 cross some threshold values; give priority to insns that free registers.
326 The insn that frees registers is most likely to be the insn with lowest
327 LUID (original insn order); but such an insn might be there in the stalled
328 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
329 upto a max of 8 cycles so that such insns may move from Q -> R.
331 The description of the hooks are as below:
333 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
334 scheduler; it is called inside the sched_init function just after
335 find_insn_reg_weights function call. It is used to calculate the SImode
336 and SFmode weights of insns of basic blocks; much similar to what
337 find_insn_reg_weights does.
338 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
340 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
341 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
344 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
345 high; reorder the ready queue so that the insn with lowest LUID will be
348 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
349 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
351 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
352 can be returned from TARGET_SCHED_REORDER2.
354 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
356 #undef TARGET_SCHED_DFA_NEW_CYCLE
357 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
359 #undef TARGET_SCHED_INIT_GLOBAL
360 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
362 #undef TARGET_SCHED_FINISH_GLOBAL
363 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
365 #undef TARGET_SCHED_VARIABLE_ISSUE
366 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
368 #undef TARGET_SCHED_REORDER
369 #define TARGET_SCHED_REORDER sh_reorder
371 #undef TARGET_SCHED_REORDER2
372 #define TARGET_SCHED_REORDER2 sh_reorder2
374 #undef TARGET_SCHED_INIT
375 #define TARGET_SCHED_INIT sh_md_init
377 #undef TARGET_LEGITIMIZE_ADDRESS
378 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
380 #undef TARGET_CANNOT_MODIFY_JUMPS_P
381 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
382 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
383 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
384 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
385 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
386 sh_optimize_target_register_callee_saved
388 #undef TARGET_MS_BITFIELD_LAYOUT_P
389 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
391 #undef TARGET_INIT_BUILTINS
392 #define TARGET_INIT_BUILTINS sh_init_builtins
393 #undef TARGET_EXPAND_BUILTIN
394 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
396 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
397 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
399 #undef TARGET_CANNOT_COPY_INSN_P
400 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
401 #undef TARGET_RTX_COSTS
402 #define TARGET_RTX_COSTS sh_rtx_costs
403 #undef TARGET_ADDRESS_COST
404 #define TARGET_ADDRESS_COST sh_address_cost
405 #undef TARGET_ALLOCATE_INITIAL_VALUE
406 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
408 #undef TARGET_MACHINE_DEPENDENT_REORG
409 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
411 #undef TARGET_DWARF_REGISTER_SPAN
412 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
415 #undef TARGET_HAVE_TLS
416 #define TARGET_HAVE_TLS true
419 #undef TARGET_PROMOTE_PROTOTYPES
420 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
421 #undef TARGET_PROMOTE_FUNCTION_ARGS
422 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
423 #undef TARGET_PROMOTE_FUNCTION_RETURN
424 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
426 #undef TARGET_STRUCT_VALUE_RTX
427 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
428 #undef TARGET_RETURN_IN_MEMORY
429 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
431 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
432 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
433 #undef TARGET_SETUP_INCOMING_VARARGS
434 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
435 #undef TARGET_STRICT_ARGUMENT_NAMING
436 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
437 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
438 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
439 #undef TARGET_MUST_PASS_IN_STACK
440 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
441 #undef TARGET_PASS_BY_REFERENCE
442 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
443 #undef TARGET_CALLEE_COPIES
444 #define TARGET_CALLEE_COPIES sh_callee_copies
445 #undef TARGET_ARG_PARTIAL_BYTES
446 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
448 #undef TARGET_BUILD_BUILTIN_VA_LIST
449 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
450 #undef TARGET_EXPAND_BUILTIN_VA_START
451 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
452 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
453 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
455 #undef TARGET_SCALAR_MODE_SUPPORTED_P
456 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
457 #undef TARGET_VECTOR_MODE_SUPPORTED_P
458 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
460 #undef TARGET_CHECK_PCH_TARGET_FLAGS
461 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
463 #undef TARGET_DWARF_CALLING_CONVENTION
464 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
466 /* Return regmode weight for insn. */
467 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
469 /* Return current register pressure for regmode. */
470 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
472 #undef TARGET_ENCODE_SECTION_INFO
473 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
477 #undef TARGET_ENCODE_SECTION_INFO
478 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
479 #undef TARGET_STRIP_NAME_ENCODING
480 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
481 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
482 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
486 #undef TARGET_SECONDARY_RELOAD
487 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
489 /* Machine-specific symbol_ref flags. */
490 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
492 struct gcc_target targetm = TARGET_INITIALIZER;
494 /* Implement TARGET_HANDLE_OPTION. */
497 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
498 int value ATTRIBUTE_UNUSED)
503 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
507 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
511 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
515 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
519 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
522 case OPT_m2a_single_only:
523 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
527 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
531 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
535 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
542 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
546 case OPT_m4_100_nofpu:
547 case OPT_m4_200_nofpu:
548 case OPT_m4_300_nofpu:
552 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
556 case OPT_m4_100_single:
557 case OPT_m4_200_single:
558 case OPT_m4_300_single:
559 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
562 case OPT_m4_single_only:
563 case OPT_m4_100_single_only:
564 case OPT_m4_200_single_only:
565 case OPT_m4_300_single_only:
566 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
570 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
575 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
579 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
582 case OPT_m4a_single_only:
583 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
587 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
590 case OPT_m5_32media_nofpu:
591 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
595 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
598 case OPT_m5_64media_nofpu:
599 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
603 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
606 case OPT_m5_compact_nofpu:
607 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
615 /* Print the operand address in x to the stream. */
618 print_operand_address (FILE *stream, rtx x)
620 switch (GET_CODE (x))
624 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
629 rtx base = XEXP (x, 0);
630 rtx index = XEXP (x, 1);
632 switch (GET_CODE (index))
635 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
636 reg_names[true_regnum (base)]);
642 int base_num = true_regnum (base);
643 int index_num = true_regnum (index);
645 fprintf (stream, "@(r0,%s)",
646 reg_names[MAX (base_num, index_num)]);
657 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
661 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
665 x = mark_constant_pool_use (x);
666 output_addr_const (stream, x);
671 /* Print operand x (an rtx) in assembler syntax to file stream
672 according to modifier code.
674 '.' print a .s if insn needs delay slot
675 ',' print LOCAL_LABEL_PREFIX
676 '@' print trap, rte or rts depending upon pragma interruptness
677 '#' output a nop if there is nothing to put in the delay slot
678 ''' print likelihood suffix (/u for unlikely).
679 '>' print branch target if -fverbose-asm
680 'O' print a constant without the #
681 'R' print the LSW of a dp value - changes if in little endian
682 'S' print the MSW of a dp value - changes if in little endian
683 'T' print the next word of a dp value - same as 'R' in big endian mode.
684 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
685 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
686 'N' print 'r63' if the operand is (const_int 0).
687 'd' print a V2SF reg as dN instead of fpN.
688 'm' print a pair `base,offset' or `base,index', for LD and ST.
689 'U' Likewise for {LD,ST}{HI,LO}.
690 'V' print the position of a single bit set.
691 'W' print the position of a single bit cleared.
692 't' print a memory address which is a register.
693 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
694 'o' output an operator. */
697 print_operand (FILE *stream, rtx x, int code)
700 enum machine_mode mode;
708 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
709 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
710 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
713 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
716 trapa_attr = lookup_attribute ("trap_exit",
717 DECL_ATTRIBUTES (current_function_decl));
719 fprintf (stream, "trapa #%ld",
720 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
721 else if (sh_cfun_interrupt_handler_p ())
723 if (sh_cfun_resbank_handler_p ())
724 fprintf (stream, "resbank\n");
725 fprintf (stream, "rte");
728 fprintf (stream, "rts");
731 /* Output a nop if there's nothing in the delay slot. */
732 if (dbr_sequence_length () == 0)
733 fprintf (stream, "\n\tnop");
737 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
739 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
740 fputs ("/u", stream);
744 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
746 fputs ("\t! target: ", stream);
747 output_addr_const (stream, JUMP_LABEL (current_output_insn));
751 x = mark_constant_pool_use (x);
752 output_addr_const (stream, x);
754 /* N.B.: %R / %S / %T adjust memory addresses by four.
755 For SHMEDIA, that means they can be used to access the first and
756 second 32 bit part of a 64 bit (or larger) value that
757 might be held in floating point registers or memory.
758 While they can be used to access 64 bit parts of a larger value
759 held in general purpose registers, that won't work with memory -
760 neither for fp registers, since the frxx names are used. */
762 if (REG_P (x) || GET_CODE (x) == SUBREG)
764 regno = true_regnum (x);
765 regno += FP_REGISTER_P (regno) ? 1 : LSW;
766 fputs (reg_names[regno], (stream));
770 x = adjust_address (x, SImode, 4 * LSW);
771 print_operand_address (stream, XEXP (x, 0));
778 if (mode == VOIDmode)
780 if (GET_MODE_SIZE (mode) >= 8)
781 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
783 print_operand (stream, sub, 0);
785 output_operand_lossage ("invalid operand to %%R");
789 if (REG_P (x) || GET_CODE (x) == SUBREG)
791 regno = true_regnum (x);
792 regno += FP_REGISTER_P (regno) ? 0 : MSW;
793 fputs (reg_names[regno], (stream));
797 x = adjust_address (x, SImode, 4 * MSW);
798 print_operand_address (stream, XEXP (x, 0));
805 if (mode == VOIDmode)
807 if (GET_MODE_SIZE (mode) >= 8)
808 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
810 print_operand (stream, sub, 0);
812 output_operand_lossage ("invalid operand to %%S");
816 /* Next word of a double. */
817 switch (GET_CODE (x))
820 fputs (reg_names[REGNO (x) + 1], (stream));
823 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
824 && GET_CODE (XEXP (x, 0)) != POST_INC)
825 x = adjust_address (x, SImode, 4);
826 print_operand_address (stream, XEXP (x, 0));
834 gcc_assert (GET_CODE (x) == MEM);
836 switch (GET_CODE (x))
840 print_operand (stream, x, 0);
848 switch (GET_CODE (x))
850 case PLUS: fputs ("add", stream); break;
851 case MINUS: fputs ("sub", stream); break;
852 case MULT: fputs ("mul", stream); break;
853 case DIV: fputs ("div", stream); break;
854 case EQ: fputs ("eq", stream); break;
855 case NE: fputs ("ne", stream); break;
856 case GT: case LT: fputs ("gt", stream); break;
857 case GE: case LE: fputs ("ge", stream); break;
858 case GTU: case LTU: fputs ("gtu", stream); break;
859 case GEU: case LEU: fputs ("geu", stream); break;
867 if (GET_CODE (x) == MEM
868 && GET_CODE (XEXP (x, 0)) == PLUS
869 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
870 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
875 if (GET_CODE (x) == MEM)
877 switch (GET_MODE (x))
879 case QImode: fputs (".b", stream); break;
880 case HImode: fputs (".w", stream); break;
881 case SImode: fputs (".l", stream); break;
882 case SFmode: fputs (".s", stream); break;
883 case DFmode: fputs (".d", stream); break;
884 default: gcc_unreachable ();
891 gcc_assert (GET_CODE (x) == MEM);
895 switch (GET_CODE (x))
899 print_operand (stream, x, 0);
900 fputs (", 0", stream);
904 print_operand (stream, XEXP (x, 0), 0);
905 fputs (", ", stream);
906 print_operand (stream, XEXP (x, 1), 0);
916 int num = exact_log2 (INTVAL (x));
917 gcc_assert (num >= 0);
918 fprintf (stream, "#%d", num);
924 int num = exact_log2 (~INTVAL (x));
925 gcc_assert (num >= 0);
926 fprintf (stream, "#%d", num);
931 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == V2SFmode);
933 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
937 if (x == CONST0_RTX (GET_MODE (x)))
939 fprintf ((stream), "r63");
944 if (GET_CODE (x) == CONST_INT)
946 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
956 switch (GET_CODE (x))
960 rtx inner = XEXP (x, 0);
962 enum machine_mode inner_mode;
964 /* We might see SUBREGs with vector mode registers inside. */
965 if (GET_CODE (inner) == SUBREG
966 && (GET_MODE_SIZE (GET_MODE (inner))
967 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
968 && subreg_lowpart_p (inner))
969 inner = SUBREG_REG (inner);
970 if (GET_CODE (inner) == CONST_INT)
972 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
975 inner_mode = GET_MODE (inner);
976 if (GET_CODE (inner) == SUBREG
977 && (GET_MODE_SIZE (GET_MODE (inner))
978 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
979 && GET_CODE (SUBREG_REG (inner)) == REG)
981 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
982 GET_MODE (SUBREG_REG (inner)),
985 inner = SUBREG_REG (inner);
987 if (GET_CODE (inner) != REG || GET_MODE_SIZE (inner_mode) > 8)
989 /* Floating point register pairs are always big endian;
990 general purpose registers are 64 bit wide. */
991 regno = REGNO (inner);
992 regno = (HARD_REGNO_NREGS (regno, inner_mode)
993 - HARD_REGNO_NREGS (regno, mode))
1001 /* FIXME: We need this on SHmedia32 because reload generates
1002 some sign-extended HI or QI loads into DImode registers
1003 but, because Pmode is SImode, the address ends up with a
1004 subreg:SI of the DImode register. Maybe reload should be
1005 fixed so as to apply alter_subreg to such loads? */
1007 gcc_assert (trapping_target_operand (x, VOIDmode));
1008 x = XEXP (XEXP (x, 2), 0);
1009 goto default_output;
1011 gcc_assert (SUBREG_BYTE (x) == 0
1012 && GET_CODE (SUBREG_REG (x)) == REG);
1020 if (FP_REGISTER_P (regno)
1021 && mode == V16SFmode)
1022 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1023 else if (FP_REGISTER_P (REGNO (x))
1024 && mode == V4SFmode)
1025 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1026 else if (GET_CODE (x) == REG
1027 && mode == V2SFmode)
1028 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1029 else if (FP_REGISTER_P (REGNO (x))
1030 && GET_MODE_SIZE (mode) > 4)
1031 fprintf ((stream), "d%s", reg_names[regno] + 1);
1033 fputs (reg_names[regno], (stream));
1037 output_address (XEXP (x, 0));
1042 fputc ('#', stream);
1043 output_addr_const (stream, x);
1051 /* Encode symbol attributes of a SYMBOL_REF into its
1052 SYMBOL_REF_FLAGS. */
1054 sh_encode_section_info (tree decl, rtx rtl, int first)
1056 default_encode_section_info (decl, rtl, first);
1058 if (TREE_CODE (decl) == FUNCTION_DECL
1059 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1060 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1063 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1065 force_into (rtx value, rtx target)
1067 value = force_operand (value, target);
1068 if (! rtx_equal_p (value, target))
1069 emit_insn (gen_move_insn (target, value));
1072 /* Emit code to perform a block move. Choose the best method.
1074 OPERANDS[0] is the destination.
1075 OPERANDS[1] is the source.
1076 OPERANDS[2] is the size.
1077 OPERANDS[3] is the alignment safe to use. */
1080 expand_block_move (rtx *operands)
1082 int align = INTVAL (operands[3]);
1083 int constp = (GET_CODE (operands[2]) == CONST_INT);
1084 int bytes = (constp ? INTVAL (operands[2]) : 0);
1089 /* If we could use mov.l to move words and dest is word-aligned, we
1090 can use movua.l for loads and still generate a relatively short
1091 and efficient sequence. */
1092 if (TARGET_SH4A_ARCH && align < 4
1093 && MEM_ALIGN (operands[0]) >= 32
1094 && can_move_by_pieces (bytes, 32))
1096 rtx dest = copy_rtx (operands[0]);
1097 rtx src = copy_rtx (operands[1]);
1098 /* We could use different pseudos for each copied word, but
1099 since movua can only load into r0, it's kind of
1101 rtx temp = gen_reg_rtx (SImode);
1102 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1105 while (copied + 4 <= bytes)
1107 rtx to = adjust_address (dest, SImode, copied);
1108 rtx from = adjust_automodify_address (src, BLKmode,
1111 set_mem_size (from, GEN_INT (4));
1112 emit_insn (gen_movua (temp, from));
1113 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1114 emit_move_insn (to, temp);
1119 move_by_pieces (adjust_address (dest, BLKmode, copied),
1120 adjust_automodify_address (src, BLKmode,
1122 bytes - copied, align, 0);
1127 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1128 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1129 if (align < 4 || (bytes % 4 != 0))
1132 if (TARGET_HARD_SH4)
1136 else if (bytes == 12)
1138 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1139 rtx r4 = gen_rtx_REG (SImode, 4);
1140 rtx r5 = gen_rtx_REG (SImode, 5);
1142 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1143 force_into (XEXP (operands[0], 0), r4);
1144 force_into (XEXP (operands[1], 0), r5);
1145 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1148 else if (! TARGET_SMALLCODE)
1150 const char *entry_name;
1151 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1153 rtx r4 = gen_rtx_REG (SImode, 4);
1154 rtx r5 = gen_rtx_REG (SImode, 5);
1155 rtx r6 = gen_rtx_REG (SImode, 6);
1157 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1158 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1159 force_into (XEXP (operands[0], 0), r4);
1160 force_into (XEXP (operands[1], 0), r5);
1162 dwords = bytes >> 3;
1163 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1164 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1173 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1174 rtx r4 = gen_rtx_REG (SImode, 4);
1175 rtx r5 = gen_rtx_REG (SImode, 5);
1177 sprintf (entry, "__movmemSI%d", bytes);
1178 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1179 force_into (XEXP (operands[0], 0), r4);
1180 force_into (XEXP (operands[1], 0), r5);
1181 emit_insn (gen_block_move_real (func_addr_rtx));
1185 /* This is the same number of bytes as a memcpy call, but to a different
1186 less common function name, so this will occasionally use more space. */
1187 if (! TARGET_SMALLCODE)
1189 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1190 int final_switch, while_loop;
1191 rtx r4 = gen_rtx_REG (SImode, 4);
1192 rtx r5 = gen_rtx_REG (SImode, 5);
1193 rtx r6 = gen_rtx_REG (SImode, 6);
1195 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1196 force_into (XEXP (operands[0], 0), r4);
1197 force_into (XEXP (operands[1], 0), r5);
1199 /* r6 controls the size of the move. 16 is decremented from it
1200 for each 64 bytes moved. Then the negative bit left over is used
1201 as an index into a list of move instructions. e.g., a 72 byte move
1202 would be set up with size(r6) = 14, for one iteration through the
1203 big while loop, and a switch of -2 for the last part. */
1205 final_switch = 16 - ((bytes / 4) % 16);
1206 while_loop = ((bytes / 4) / 16 - 1) * 16;
1207 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1208 emit_insn (gen_block_lump_real (func_addr_rtx));
1215 /* Prepare operands for a move define_expand; specifically, one of the
1216 operands must be in a register. */
1219 prepare_move_operands (rtx operands[], enum machine_mode mode)
1221 if ((mode == SImode || mode == DImode)
1223 && ! ((mode == Pmode || mode == ptr_mode)
1224 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1227 if (SYMBOLIC_CONST_P (operands[1]))
1229 if (GET_CODE (operands[0]) == MEM)
1230 operands[1] = force_reg (Pmode, operands[1]);
1231 else if (TARGET_SHMEDIA
1232 && GET_CODE (operands[1]) == LABEL_REF
1233 && target_reg_operand (operands[0], mode))
1237 temp = (!can_create_pseudo_p ()
1239 : gen_reg_rtx (Pmode));
1240 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1243 else if (GET_CODE (operands[1]) == CONST
1244 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1245 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1247 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1248 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1250 operands[1] = expand_binop (mode, add_optab, temp,
1251 XEXP (XEXP (operands[1], 0), 1),
1252 (!can_create_pseudo_p ()
1254 : gen_reg_rtx (Pmode)),
1255 0, OPTAB_LIB_WIDEN);
1259 if (! reload_in_progress && ! reload_completed)
1261 /* Copy the source to a register if both operands aren't registers. */
1262 if (! register_operand (operands[0], mode)
1263 && ! sh_register_operand (operands[1], mode))
1264 operands[1] = copy_to_mode_reg (mode, operands[1]);
1266 if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode))
1268 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1269 except that we can't use that function because it is static. */
1270 rtx new_rtx = change_address (operands[0], mode, 0);
1271 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1272 operands[0] = new_rtx;
1275 /* This case can happen while generating code to move the result
1276 of a library call to the target. Reject `st r0,@(rX,rY)' because
1277 reload will fail to find a spill register for rX, since r0 is already
1278 being used for the source. */
1280 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1281 && GET_CODE (operands[0]) == MEM
1282 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1283 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
1284 operands[1] = copy_to_mode_reg (mode, operands[1]);
1287 if (mode == Pmode || mode == ptr_mode)
1290 enum tls_model tls_kind;
1294 if (GET_CODE (op1) == CONST
1295 && GET_CODE (XEXP (op1, 0)) == PLUS
1296 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1299 opc = XEXP (XEXP (op1, 0), 1);
1300 op1 = XEXP (XEXP (op1, 0), 0);
1305 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1307 rtx tga_op1, tga_ret, tmp, tmp2;
1311 case TLS_MODEL_GLOBAL_DYNAMIC:
1312 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1313 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1317 case TLS_MODEL_LOCAL_DYNAMIC:
1318 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1319 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1321 tmp = gen_reg_rtx (Pmode);
1322 emit_move_insn (tmp, tga_ret);
1324 if (register_operand (op0, Pmode))
1327 tmp2 = gen_reg_rtx (Pmode);
1329 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1333 case TLS_MODEL_INITIAL_EXEC:
1336 /* Don't schedule insns for getting GOT address when
1337 the first scheduling is enabled, to avoid spill
1339 if (flag_schedule_insns)
1340 emit_insn (gen_blockage ());
1341 emit_insn (gen_GOTaddr2picreg ());
1342 emit_use (gen_rtx_REG (SImode, PIC_REG));
1343 if (flag_schedule_insns)
1344 emit_insn (gen_blockage ());
1346 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1347 tmp = gen_sym2GOTTPOFF (op1);
1348 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1352 case TLS_MODEL_LOCAL_EXEC:
1353 tmp2 = gen_reg_rtx (Pmode);
1354 emit_insn (gen_load_gbr (tmp2));
1355 tmp = gen_reg_rtx (Pmode);
1356 emit_insn (gen_symTPOFF2reg (tmp, op1));
1358 if (register_operand (op0, Pmode))
1361 op1 = gen_reg_rtx (Pmode);
1363 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1370 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1379 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1380 enum rtx_code comparison)
1383 rtx scratch = NULL_RTX;
1385 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1386 comparison = GET_CODE (operands[0]);
1388 scratch = operands[4];
1389 if (GET_CODE (operands[1]) == CONST_INT
1390 && GET_CODE (operands[2]) != CONST_INT)
1392 rtx tmp = operands[1];
1394 operands[1] = operands[2];
1396 comparison = swap_condition (comparison);
1398 if (GET_CODE (operands[2]) == CONST_INT)
1400 HOST_WIDE_INT val = INTVAL (operands[2]);
1401 if ((val == -1 || val == -0x81)
1402 && (comparison == GT || comparison == LE))
1404 comparison = (comparison == GT) ? GE : LT;
1405 operands[2] = gen_int_mode (val + 1, mode);
1407 else if ((val == 1 || val == 0x80)
1408 && (comparison == GE || comparison == LT))
1410 comparison = (comparison == GE) ? GT : LE;
1411 operands[2] = gen_int_mode (val - 1, mode);
1413 else if (val == 1 && (comparison == GEU || comparison == LTU))
1415 comparison = (comparison == GEU) ? NE : EQ;
1416 operands[2] = CONST0_RTX (mode);
1418 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1420 comparison = (comparison == GEU) ? GTU : LEU;
1421 operands[2] = gen_int_mode (val - 1, mode);
1423 else if (val == 0 && (comparison == GTU || comparison == LEU))
1424 comparison = (comparison == GTU) ? NE : EQ;
1425 else if (mode == SImode
1426 && ((val == 0x7fffffff
1427 && (comparison == GTU || comparison == LEU))
1428 || ((unsigned HOST_WIDE_INT) val
1429 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1430 && (comparison == GEU || comparison == LTU))))
1432 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1433 operands[2] = CONST0_RTX (mode);
1437 if (can_create_pseudo_p ())
1438 operands[1] = force_reg (mode, op1);
1439 /* When we are handling DImode comparisons, we want to keep constants so
1440 that we can optimize the component comparisons; however, memory loads
1441 are better issued as a whole so that they can be scheduled well.
1442 SImode equality comparisons allow I08 constants, but only when they
1443 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1444 into a register, that register might as well be r0, and we allow the
1445 constant. If it is already in a register, this is likely to be
1446 allocated to a different hard register, thus we load the constant into
1447 a register unless it is zero. */
1448 if (!REG_P (operands[2])
1449 && (GET_CODE (operands[2]) != CONST_INT
1450 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1451 && ((comparison != EQ && comparison != NE)
1452 || (REG_P (op1) && REGNO (op1) != R0_REG)
1453 || !satisfies_constraint_I08 (operands[2])))))
1455 if (scratch && GET_MODE (scratch) == mode)
1457 emit_move_insn (scratch, operands[2]);
1458 operands[2] = scratch;
1460 else if (can_create_pseudo_p ())
1461 operands[2] = force_reg (mode, operands[2]);
1467 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1469 rtx (*branch_expander) (rtx) = gen_branch_true;
1472 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1475 case NE: case LT: case LE: case LTU: case LEU:
1476 comparison = reverse_condition (comparison);
1477 branch_expander = gen_branch_false;
1480 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1481 gen_rtx_fmt_ee (comparison, SImode,
1482 operands[1], operands[2])));
1483 jump = emit_jump_insn (branch_expander (operands[3]));
1484 if (probability >= 0)
1485 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1489 /* ??? How should we distribute probabilities when more than one branch
1490 is generated. So far we only have soem ad-hoc observations:
1491 - If the operands are random, they are likely to differ in both parts.
1492 - If comparing items in a hash chain, the operands are random or equal;
1493 operation should be EQ or NE.
1494 - If items are searched in an ordered tree from the root, we can expect
1495 the highpart to be unequal about half of the time; operation should be
1496 an inequality comparison, operands non-constant, and overall probability
1497 about 50%. Likewise for quicksort.
1498 - Range checks will be often made against constants. Even if we assume for
1499 simplicity an even distribution of the non-constant operand over a
1500 sub-range here, the same probability could be generated with differently
1501 wide sub-ranges - as long as the ratio of the part of the subrange that
1502 is before the threshold to the part that comes after the threshold stays
1503 the same. Thus, we can't really tell anything here;
1504 assuming random distribution is at least simple.
1508 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1510 enum rtx_code msw_taken, msw_skip, lsw_taken;
1511 rtx skip_label = NULL_RTX;
1512 rtx op1h, op1l, op2h, op2l;
1515 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1516 rtx scratch = operands[4];
1518 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1519 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1520 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1521 op1l = gen_lowpart (SImode, operands[1]);
1522 op2l = gen_lowpart (SImode, operands[2]);
1523 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1524 prob = split_branch_probability;
1525 rev_prob = REG_BR_PROB_BASE - prob;
1528 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1529 That costs 1 cycle more when the first branch can be predicted taken,
1530 but saves us mispredicts because only one branch needs prediction.
1531 It also enables generating the cmpeqdi_t-1 pattern. */
1533 if (TARGET_CMPEQDI_T)
1535 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1536 emit_jump_insn (gen_branch_true (operands[3]));
1543 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1545 msw_skip_prob = rev_prob;
1546 if (REG_BR_PROB_BASE <= 65535)
1547 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1550 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1554 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1555 / ((HOST_WIDEST_INT) prob << 32)))
1561 if (TARGET_CMPEQDI_T)
1563 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1564 emit_jump_insn (gen_branch_false (operands[3]));
1568 msw_taken_prob = prob;
1573 msw_taken = comparison;
1574 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1576 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1577 msw_skip = swap_condition (msw_taken);
1581 if (op2l == CONST0_RTX (SImode))
1582 msw_taken = comparison;
1585 msw_taken = comparison == GE ? GT : GTU;
1586 msw_skip = swap_condition (msw_taken);
1591 msw_taken = comparison;
1592 if (op2l == CONST0_RTX (SImode))
1594 msw_skip = swap_condition (msw_taken);
1598 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1599 msw_taken = comparison;
1603 if (comparison == LE)
1605 else if (op2h != CONST0_RTX (SImode))
1609 msw_skip = swap_condition (msw_taken);
1612 default: return false;
1614 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1615 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1616 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1617 if (comparison != EQ && comparison != NE && num_branches > 1)
1619 if (!CONSTANT_P (operands[2])
1620 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1621 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1623 msw_taken_prob = prob / 2U;
1625 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1626 lsw_taken_prob = prob;
1630 msw_taken_prob = prob;
1631 msw_skip_prob = REG_BR_PROB_BASE;
1632 /* ??? If we have a constant op2h, should we use that when
1633 calculating lsw_taken_prob? */
1634 lsw_taken_prob = prob;
1639 operands[4] = NULL_RTX;
1640 if (reload_completed
1641 && ! arith_reg_or_0_operand (op2h, SImode) && true_regnum (op1h)
1642 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
1643 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
1645 emit_move_insn (scratch, operands[2]);
1646 operands[2] = scratch;
1648 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1649 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1650 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1652 rtx taken_label = operands[3];
1654 /* Operands were possibly modified, but msw_skip doesn't expect this.
1655 Always use the original ones. */
1656 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1662 operands[3] = skip_label = gen_label_rtx ();
1663 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1664 operands[3] = taken_label;
1668 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
1670 if (reload_completed
1671 && ! arith_reg_or_0_operand (op2l, SImode) && true_regnum (op1l))
1672 operands[4] = scratch;
1673 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1675 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1676 emit_label (skip_label);
1680 /* Prepare the operands for an scc instruction; make sure that the
1681 compare has been done. */
1683 prepare_scc_operands (enum rtx_code code)
1685 rtx t_reg = gen_rtx_REG (SImode, T_REG);
1686 enum rtx_code oldcode = code;
1687 enum machine_mode mode;
1689 /* First need a compare insn. */
1693 /* It isn't possible to handle this case. */
1710 if (code != oldcode)
1712 rtx tmp = sh_compare_op0;
1713 sh_compare_op0 = sh_compare_op1;
1714 sh_compare_op1 = tmp;
1717 mode = GET_MODE (sh_compare_op0);
1718 if (mode == VOIDmode)
1719 mode = GET_MODE (sh_compare_op1);
1721 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1722 if ((code != EQ && code != NE
1723 && (sh_compare_op1 != const0_rtx
1724 || code == GTU || code == GEU || code == LTU || code == LEU))
1725 || (mode == DImode && sh_compare_op1 != const0_rtx)
1726 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1727 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1729 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1730 (mode == SFmode ? emit_sf_insn : emit_df_insn)
1731 (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
1732 gen_rtx_SET (VOIDmode, t_reg,
1733 gen_rtx_fmt_ee (code, SImode,
1734 sh_compare_op0, sh_compare_op1)),
1735 gen_rtx_USE (VOIDmode, get_fpscr_rtx ()))));
1737 emit_insn (gen_rtx_SET (VOIDmode, t_reg,
1738 gen_rtx_fmt_ee (code, SImode,
1739 sh_compare_op0, sh_compare_op1)));
1744 /* Called from the md file, set up the operands of a compare instruction. */
1747 from_compare (rtx *operands, int code)
1749 enum machine_mode mode = GET_MODE (sh_compare_op0);
1751 if (mode == VOIDmode)
1752 mode = GET_MODE (sh_compare_op1);
1755 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1757 /* Force args into regs, since we can't use constants here. */
1758 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1759 if (sh_compare_op1 != const0_rtx
1760 || code == GTU || code == GEU
1761 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1762 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1764 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
1766 from_compare (operands, GT);
1767 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
1770 insn = gen_rtx_SET (VOIDmode,
1771 gen_rtx_REG (SImode, T_REG),
1772 gen_rtx_fmt_ee ((enum rtx_code) code, SImode,
1773 sh_compare_op0, sh_compare_op1));
1774 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1776 insn = gen_rtx_PARALLEL (VOIDmode,
1778 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1779 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1785 /* Functions to output assembly code. */
1787 /* Return a sequence of instructions to perform DI or DF move.
1789 Since the SH cannot move a DI or DF in one instruction, we have
1790 to take care when we see overlapping source and dest registers. */
1793 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1794 enum machine_mode mode)
1796 rtx dst = operands[0];
1797 rtx src = operands[1];
1799 if (GET_CODE (dst) == MEM
1800 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
1801 return "mov.l %T1,%0\n\tmov.l %1,%0";
1803 if (register_operand (dst, mode)
1804 && register_operand (src, mode))
1806 if (REGNO (src) == MACH_REG)
1807 return "sts mach,%S0\n\tsts macl,%R0";
1809 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1810 when mov.d r1,r0 do r1->r0 then r2->r1. */
1812 if (REGNO (src) + 1 == REGNO (dst))
1813 return "mov %T1,%T0\n\tmov %1,%0";
1815 return "mov %1,%0\n\tmov %T1,%T0";
1817 else if (GET_CODE (src) == CONST_INT)
1819 if (INTVAL (src) < 0)
1820 output_asm_insn ("mov #-1,%S0", operands);
1822 output_asm_insn ("mov #0,%S0", operands);
1824 return "mov %1,%R0";
1826 else if (GET_CODE (src) == MEM)
1829 int dreg = REGNO (dst);
1830 rtx inside = XEXP (src, 0);
1832 switch (GET_CODE (inside))
1835 ptrreg = REGNO (inside);
1839 ptrreg = subreg_regno (inside);
1843 ptrreg = REGNO (XEXP (inside, 0));
1844 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1845 an offsettable address. Unfortunately, offsettable addresses use
1846 QImode to check the offset, and a QImode offsettable address
1847 requires r0 for the other operand, which is not currently
1848 supported, so we can't use the 'o' constraint.
1849 Thus we must check for and handle r0+REG addresses here.
1850 We punt for now, since this is likely very rare. */
1851 gcc_assert (GET_CODE (XEXP (inside, 1)) != REG);
1855 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1857 return "mov.l %1,%0\n\tmov.l %1,%T0";
1862 /* Work out the safe way to copy. Copy into the second half first. */
1864 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1867 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1870 /* Print an instruction which would have gone into a delay slot after
1871 another instruction, but couldn't because the other instruction expanded
1872 into a sequence where putting the slot insn at the end wouldn't work. */
1875 print_slot (rtx insn)
1877 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
1879 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1883 output_far_jump (rtx insn, rtx op)
1885 struct { rtx lab, reg, op; } this_jmp;
1886 rtx braf_base_lab = NULL_RTX;
1889 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
1892 this_jmp.lab = gen_label_rtx ();
1896 && offset - get_attr_length (insn) <= 32766)
1899 jump = "mov.w %O0,%1; braf %1";
1907 jump = "mov.l %O0,%1; braf %1";
1909 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1912 jump = "mov.l %O0,%1; jmp @%1";
1914 /* If we have a scratch register available, use it. */
1915 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
1916 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1918 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
1919 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1920 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1921 output_asm_insn (jump, &this_jmp.lab);
1922 if (dbr_sequence_length ())
1923 print_slot (final_sequence);
1925 output_asm_insn ("nop", 0);
1929 /* Output the delay slot insn first if any. */
1930 if (dbr_sequence_length ())
1931 print_slot (final_sequence);
1933 this_jmp.reg = gen_rtx_REG (SImode, 13);
1934 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1935 Fortunately, MACL is fixed and call-clobbered, and we never
1936 need its value across jumps, so save r13 in it instead of in
1939 output_asm_insn ("lds r13, macl", 0);
1941 output_asm_insn ("mov.l r13,@-r15", 0);
1942 output_asm_insn (jump, &this_jmp.lab);
1944 output_asm_insn ("sts macl, r13", 0);
1946 output_asm_insn ("mov.l @r15+,r13", 0);
1948 if (far && flag_pic && TARGET_SH2)
1950 braf_base_lab = gen_label_rtx ();
1951 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1952 CODE_LABEL_NUMBER (braf_base_lab));
1955 output_asm_insn (".align 2", 0);
1956 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
1958 if (far && flag_pic)
1961 this_jmp.lab = braf_base_lab;
1962 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
1965 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
1969 /* Local label counter, used for constants in the pool and inside
1970 pattern branches. */
1972 static int lf = 100;
1974 /* Output code for ordinary branches. */
1977 output_branch (int logic, rtx insn, rtx *operands)
1979 switch (get_attr_length (insn))
1982 /* This can happen if filling the delay slot has caused a forward
1983 branch to exceed its range (we could reverse it, but only
1984 when we know we won't overextend other branches; this should
1985 best be handled by relaxation).
1986 It can also happen when other condbranches hoist delay slot insn
1987 from their destination, thus leading to code size increase.
1988 But the branch will still be in the range -4092..+4098 bytes. */
1993 /* The call to print_slot will clobber the operands. */
1994 rtx op0 = operands[0];
1996 /* If the instruction in the delay slot is annulled (true), then
1997 there is no delay slot where we can put it now. The only safe
1998 place for it is after the label. final will do that by default. */
2001 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2002 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2004 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2005 ASSEMBLER_DIALECT ? "/" : ".", label);
2006 print_slot (final_sequence);
2009 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2011 output_asm_insn ("bra\t%l0", &op0);
2012 fprintf (asm_out_file, "\tnop\n");
2013 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2017 /* When relaxing, handle this like a short branch. The linker
2018 will fix it up if it still doesn't fit after relaxation. */
2020 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2022 /* These are for SH2e, in which we have to account for the
2023 extra nop because of the hardware bug in annulled branches. */
2029 gcc_assert (!final_sequence
2030 || !(INSN_ANNULLED_BRANCH_P
2031 (XVECEXP (final_sequence, 0, 0))));
2032 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2034 ASSEMBLER_DIALECT ? "/" : ".", label);
2035 fprintf (asm_out_file, "\tnop\n");
2036 output_asm_insn ("bra\t%l0", operands);
2037 fprintf (asm_out_file, "\tnop\n");
2038 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2042 /* When relaxing, fall through. */
2047 sprintf (buffer, "b%s%ss\t%%l0",
2049 ASSEMBLER_DIALECT ? "/" : ".");
2050 output_asm_insn (buffer, &operands[0]);
2055 /* There should be no longer branches now - that would
2056 indicate that something has destroyed the branches set
2057 up in machine_dependent_reorg. */
2062 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2063 fill in operands 9 as a label to the successor insn.
2064 We try to use jump threading where possible.
2065 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2066 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2067 follow jmp and bt, if the address is in range. */
2069 output_branchy_insn (enum rtx_code code, const char *templ,
2070 rtx insn, rtx *operands)
2072 rtx next_insn = NEXT_INSN (insn);
2074 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
2076 rtx src = SET_SRC (PATTERN (next_insn));
2077 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2079 /* Following branch not taken */
2080 operands[9] = gen_label_rtx ();
2081 emit_label_after (operands[9], next_insn);
2082 INSN_ADDRESSES_NEW (operands[9],
2083 INSN_ADDRESSES (INSN_UID (next_insn))
2084 + get_attr_length (next_insn));
2089 int offset = (branch_dest (next_insn)
2090 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2091 if (offset >= -252 && offset <= 258)
2093 if (GET_CODE (src) == IF_THEN_ELSE)
2095 src = XEXP (src, 1);
2101 operands[9] = gen_label_rtx ();
2102 emit_label_after (operands[9], insn);
2103 INSN_ADDRESSES_NEW (operands[9],
2104 INSN_ADDRESSES (INSN_UID (insn))
2105 + get_attr_length (insn));
2110 output_ieee_ccmpeq (rtx insn, rtx *operands)
2112 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2116 /* Output the start of the assembler file. */
2119 sh_file_start (void)
2121 default_file_start ();
2124 /* Declare the .directive section before it is used. */
2125 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2126 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2130 /* We need to show the text section with the proper
2131 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2132 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2133 will complain. We can teach GAS specifically about the
2134 default attributes for our choice of text section, but
2135 then we would have to change GAS again if/when we change
2136 the text section name. */
2137 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2139 /* Switch to the data section so that the coffsem symbol
2140 isn't in the text section. */
2141 switch_to_section (data_section);
2143 if (TARGET_LITTLE_ENDIAN)
2144 fputs ("\t.little\n", asm_out_file);
2148 if (TARGET_SHCOMPACT)
2149 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2150 else if (TARGET_SHMEDIA)
2151 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2152 TARGET_SHMEDIA64 ? 64 : 32);
2156 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2159 unspec_caller_rtx_p (rtx pat)
2164 split_const (pat, &base, &offset);
2165 if (GET_CODE (base) == UNSPEC)
2167 if (XINT (base, 1) == UNSPEC_CALLER)
2169 for (i = 0; i < XVECLEN (base, 0); i++)
2170 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2176 /* Indicate that INSN cannot be duplicated. This is true for insn
2177 that generates a unique label. */
2180 sh_cannot_copy_insn_p (rtx insn)
2184 if (!reload_completed || !flag_pic)
2187 if (GET_CODE (insn) != INSN)
2189 if (asm_noperands (insn) >= 0)
2192 pat = PATTERN (insn);
2193 if (GET_CODE (pat) != SET)
2195 pat = SET_SRC (pat);
2197 if (unspec_caller_rtx_p (pat))
2203 /* Actual number of instructions used to make a shift by N. */
2204 static const char ashiftrt_insns[] =
2205 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2207 /* Left shift and logical right shift are the same. */
2208 static const char shift_insns[] =
2209 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2211 /* Individual shift amounts needed to get the above length sequences.
2212 One bit right shifts clobber the T bit, so when possible, put one bit
2213 shifts in the middle of the sequence, so the ends are eligible for
2214 branch delay slots. */
2215 static const short shift_amounts[32][5] = {
2216 {0}, {1}, {2}, {2, 1},
2217 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2218 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2219 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2220 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2221 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2222 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2223 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2225 /* Likewise, but for shift amounts < 16, up to three highmost bits
2226 might be clobbered. This is typically used when combined with some
2227 kind of sign or zero extension. */
2229 static const char ext_shift_insns[] =
2230 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2232 static const short ext_shift_amounts[32][4] = {
2233 {0}, {1}, {2}, {2, 1},
2234 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2235 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2236 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2237 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2238 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2239 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2240 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2242 /* Assuming we have a value that has been sign-extended by at least one bit,
2243 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2244 to shift it by N without data loss, and quicker than by other means? */
2245 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2247 /* This is used in length attributes in sh.md to help compute the length
2248 of arbitrary constant shift instructions. */
2251 shift_insns_rtx (rtx insn)
2253 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2254 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2255 enum rtx_code shift_code = GET_CODE (set_src);
2260 return ashiftrt_insns[shift_count];
2263 return shift_insns[shift_count];
2269 /* Return the cost of a shift. */
2279 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2281 if (GET_MODE (x) == DImode
2282 && GET_CODE (XEXP (x, 1)) == CONST_INT
2283 && INTVAL (XEXP (x, 1)) == 1)
2286 /* Everything else is invalid, because there is no pattern for it. */
2289 /* If shift by a non constant, then this will be expensive. */
2290 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2291 return SH_DYNAMIC_SHIFT_COST;
2293 /* Otherwise, return the true cost in instructions. Cope with out of range
2294 shift counts more or less arbitrarily. */
2295 value = INTVAL (XEXP (x, 1)) & 31;
2297 if (GET_CODE (x) == ASHIFTRT)
2299 int cost = ashiftrt_insns[value];
2300 /* If SH3, then we put the constant in a reg and use shad. */
2301 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2302 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2306 return shift_insns[value];
2309 /* Return the cost of an AND operation. */
2316 /* Anding with a register is a single cycle and instruction. */
2317 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2320 i = INTVAL (XEXP (x, 1));
2324 if (satisfies_constraint_I10 (XEXP (x, 1))
2325 || satisfies_constraint_J16 (XEXP (x, 1)))
2328 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
2331 /* These constants are single cycle extu.[bw] instructions. */
2332 if (i == 0xff || i == 0xffff)
2334 /* Constants that can be used in an and immediate instruction in a single
2335 cycle, but this requires r0, so make it a little more expensive. */
2336 if (CONST_OK_FOR_K08 (i))
2338 /* Constants that can be loaded with a mov immediate and an and.
2339 This case is probably unnecessary. */
2340 if (CONST_OK_FOR_I08 (i))
2342 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2343 This case is probably unnecessary. */
2347 /* Return the cost of an addition or a subtraction. */
2352 /* Adding a register is a single cycle insn. */
2353 if (GET_CODE (XEXP (x, 1)) == REG
2354 || GET_CODE (XEXP (x, 1)) == SUBREG)
2357 /* Likewise for small constants. */
2358 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2359 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2363 switch (GET_CODE (XEXP (x, 1)))
2368 return TARGET_SHMEDIA64 ? 5 : 3;
2371 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2373 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2375 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2383 /* Any other constant requires a 2 cycle pc-relative load plus an
2388 /* Return the cost of a multiply. */
2390 multcosts (rtx x ATTRIBUTE_UNUSED)
2392 if (sh_multcost >= 0)
2395 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2396 accept constants. Ideally, we would use a cost of one or two and
2397 add the cost of the operand, but disregard the latter when inside loops
2398 and loop invariant code motion is still to follow.
2399 Using a multiply first and splitting it later if it's a loss
2400 doesn't work because of different sign / zero extension semantics
2401 of multiplies vs. shifts. */
2402 return TARGET_SMALLCODE ? 2 : 3;
2406 /* We have a mul insn, so we can never take more than the mul and the
2407 read of the mac reg, but count more because of the latency and extra
2409 if (TARGET_SMALLCODE)
2414 /* If we're aiming at small code, then just count the number of
2415 insns in a multiply call sequence. */
2416 if (TARGET_SMALLCODE)
2419 /* Otherwise count all the insns in the routine we'd be calling too. */
2423 /* Compute a (partial) cost for rtx X. Return true if the complete
2424 cost has been computed, and false if subexpressions should be
2425 scanned. In either case, *TOTAL contains the cost result. */
2428 sh_rtx_costs (rtx x, int code, int outer_code, int *total,
2429 bool speed ATTRIBUTE_UNUSED)
2436 if (INTVAL (x) == 0)
2438 else if (outer_code == AND && and_operand ((x), DImode))
2440 else if ((outer_code == IOR || outer_code == XOR
2441 || outer_code == PLUS)
2442 && CONST_OK_FOR_I10 (INTVAL (x)))
2444 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2445 *total = COSTS_N_INSNS (outer_code != SET);
2446 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2447 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2448 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2449 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2451 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2454 if (CONST_OK_FOR_I08 (INTVAL (x)))
2456 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2457 && CONST_OK_FOR_K08 (INTVAL (x)))
2459 /* prepare_cmp_insn will force costly constants int registers before
2460 the cbranch[sd]i4 patterns can see them, so preserve potentially
2461 interesting ones not covered by I08 above. */
2462 else if (outer_code == COMPARE
2463 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2464 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2465 || INTVAL (x) == 0x7fffffff
2466 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2475 if (TARGET_SHMEDIA64)
2476 *total = COSTS_N_INSNS (4);
2477 else if (TARGET_SHMEDIA32)
2478 *total = COSTS_N_INSNS (2);
2485 *total = COSTS_N_INSNS (4);
2486 /* prepare_cmp_insn will force costly constants int registers before
2487 the cbranchdi4 pattern can see them, so preserve potentially
2488 interesting ones. */
2489 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2495 if (x == CONST0_RTX (GET_MODE (x)))
2497 else if (sh_1el_vec (x, VOIDmode))
2498 *total = outer_code != SET;
2499 if (sh_rep_vec (x, VOIDmode))
2500 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2501 + (outer_code != SET));
2502 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2507 *total = COSTS_N_INSNS (addsubcosts (x));
2511 *total = COSTS_N_INSNS (andcosts (x));
2515 *total = COSTS_N_INSNS (multcosts (x));
2521 *total = COSTS_N_INSNS (shiftcosts (x));
2528 *total = COSTS_N_INSNS (20);
2532 if (sh_1el_vec (x, VOIDmode))
2533 *total = outer_code != SET;
2534 if (sh_rep_vec (x, VOIDmode))
2535 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2536 + (outer_code != SET));
2537 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2550 /* Compute the cost of an address. For the SH, all valid addresses are
2551 the same cost. Use a slightly higher cost for reg + reg addressing,
2552 since it increases pressure on r0. */
2555 sh_address_cost (rtx X,
2556 bool speed ATTRIBUTE_UNUSED)
2558 return (GET_CODE (X) == PLUS
2559 && ! CONSTANT_P (XEXP (X, 1))
2560 && ! TARGET_SHMEDIA ? 1 : 0);
2563 /* Code to expand a shift. */
2566 gen_ashift (int type, int n, rtx reg)
2568 /* Negative values here come from the shift_amounts array. */
2581 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
2585 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
2587 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
2590 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
2595 /* Same for HImode */
2598 gen_ashift_hi (int type, int n, rtx reg)
2600 /* Negative values here come from the shift_amounts array. */
2614 /* We don't have HImode right shift operations because using the
2615 ordinary 32 bit shift instructions for that doesn't generate proper
2616 zero/sign extension.
2617 gen_ashift_hi is only called in contexts where we know that the
2618 sign extension works out correctly. */
2621 if (GET_CODE (reg) == SUBREG)
2623 offset = SUBREG_BYTE (reg);
2624 reg = SUBREG_REG (reg);
2626 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
2630 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
2635 /* Output RTL to split a constant shift into its component SH constant
2636 shift instructions. */
2639 gen_shifty_op (int code, rtx *operands)
2641 int value = INTVAL (operands[2]);
2644 /* Truncate the shift count in case it is out of bounds. */
2649 if (code == LSHIFTRT)
2651 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2652 emit_insn (gen_movt (operands[0]));
2655 else if (code == ASHIFT)
2657 /* There is a two instruction sequence for 31 bit left shifts,
2658 but it requires r0. */
2659 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
2661 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
2662 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2667 else if (value == 0)
2669 /* This can happen even when optimizing, if there were subregs before
2670 reload. Don't output a nop here, as this is never optimized away;
2671 use a no-op move instead. */
2672 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
2676 max = shift_insns[value];
2677 for (i = 0; i < max; i++)
2678 gen_ashift (code, shift_amounts[value][i], operands[0]);
2681 /* Same as above, but optimized for values where the topmost bits don't
2685 gen_shifty_hi_op (int code, rtx *operands)
2687 int value = INTVAL (operands[2]);
2689 void (*gen_fun) (int, int, rtx);
2691 /* This operation is used by and_shl for SImode values with a few
2692 high bits known to be cleared. */
2696 emit_insn (gen_nop ());
2700 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
2703 max = ext_shift_insns[value];
2704 for (i = 0; i < max; i++)
2705 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2708 /* When shifting right, emit the shifts in reverse order, so that
2709 solitary negative values come first. */
2710 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
2711 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2714 /* Output RTL for an arithmetic right shift. */
2716 /* ??? Rewrite to use super-optimizer sequences. */
2719 expand_ashiftrt (rtx *operands)
2727 if (GET_CODE (operands[2]) != CONST_INT)
2729 rtx count = copy_to_mode_reg (SImode, operands[2]);
2730 emit_insn (gen_negsi2 (count, count));
2731 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2734 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
2735 > 1 + SH_DYNAMIC_SHIFT_COST)
2738 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
2739 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2743 if (GET_CODE (operands[2]) != CONST_INT)
2746 value = INTVAL (operands[2]) & 31;
2750 /* If we are called from abs expansion, arrange things so that we
2751 we can use a single MT instruction that doesn't clobber the source,
2752 if LICM can hoist out the load of the constant zero. */
2753 if (currently_expanding_to_rtl)
2755 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
2757 emit_insn (gen_mov_neg_si_t (operands[0]));
2760 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
2763 else if (value >= 16 && value <= 19)
2765 wrk = gen_reg_rtx (SImode);
2766 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
2769 gen_ashift (ASHIFTRT, 1, wrk);
2770 emit_move_insn (operands[0], wrk);
2773 /* Expand a short sequence inline, longer call a magic routine. */
2774 else if (value <= 5)
2776 wrk = gen_reg_rtx (SImode);
2777 emit_move_insn (wrk, operands[1]);
2779 gen_ashift (ASHIFTRT, 1, wrk);
2780 emit_move_insn (operands[0], wrk);
2784 wrk = gen_reg_rtx (Pmode);
2786 /* Load the value into an arg reg and call a helper. */
2787 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2788 sprintf (func, "__ashiftrt_r4_%d", value);
2789 function_symbol (wrk, func, SFUNC_STATIC);
2790 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
2791 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
2796 sh_dynamicalize_shift_p (rtx count)
2798 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
2801 /* Try to find a good way to implement the combiner pattern
2802 [(set (match_operand:SI 0 "register_operand" "r")
2803 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2804 (match_operand:SI 2 "const_int_operand" "n"))
2805 (match_operand:SI 3 "const_int_operand" "n"))) .
2806 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
2807 return 0 for simple right / left or left/right shift combination.
2808 return 1 for a combination of shifts with zero_extend.
2809 return 2 for a combination of shifts with an AND that needs r0.
2810 return 3 for a combination of shifts with an AND that needs an extra
2811 scratch register, when the three highmost bits of the AND mask are clear.
2812 return 4 for a combination of shifts with an AND that needs an extra
2813 scratch register, when any of the three highmost bits of the AND mask
2815 If ATTRP is set, store an initial right shift width in ATTRP[0],
2816 and the instruction length in ATTRP[1] . These values are not valid
2818 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
2819 shift_amounts for the last shift value that is to be used before the
2822 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
2824 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
2825 int left = INTVAL (left_rtx), right;
2827 int cost, best_cost = 10000;
2828 int best_right = 0, best_len = 0;
2832 if (left < 0 || left > 31)
2834 if (GET_CODE (mask_rtx) == CONST_INT)
2835 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
2837 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
2838 /* Can this be expressed as a right shift / left shift pair? */
2839 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
2840 right = exact_log2 (lsb);
2841 mask2 = ~(mask + lsb - 1);
2842 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
2843 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
2845 best_cost = shift_insns[right] + shift_insns[right + left];
2846 /* mask has no trailing zeroes <==> ! right */
2847 else if (! right && mask2 == ~(lsb2 - 1))
2849 int late_right = exact_log2 (lsb2);
2850 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
2852 /* Try to use zero extend. */
2853 if (mask2 == ~(lsb2 - 1))
2857 for (width = 8; width <= 16; width += 8)
2859 /* Can we zero-extend right away? */
2860 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
2863 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
2864 if (cost < best_cost)
2875 /* ??? Could try to put zero extend into initial right shift,
2876 or even shift a bit left before the right shift. */
2877 /* Determine value of first part of left shift, to get to the
2878 zero extend cut-off point. */
2879 first = width - exact_log2 (lsb2) + right;
2880 if (first >= 0 && right + left - first >= 0)
2882 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
2883 + ext_shift_insns[right + left - first];
2884 if (cost < best_cost)
2896 /* Try to use r0 AND pattern */
2897 for (i = 0; i <= 2; i++)
2901 if (! CONST_OK_FOR_K08 (mask >> i))
2903 cost = (i != 0) + 2 + ext_shift_insns[left + i];
2904 if (cost < best_cost)
2909 best_len = cost - 1;
2912 /* Try to use a scratch register to hold the AND operand. */
2913 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
2914 for (i = 0; i <= 2; i++)
2918 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
2919 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
2920 if (cost < best_cost)
2925 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
2931 attrp[0] = best_right;
2932 attrp[1] = best_len;
2937 /* This is used in length attributes of the unnamed instructions
2938 corresponding to shl_and_kind return values of 1 and 2. */
2940 shl_and_length (rtx insn)
2942 rtx set_src, left_rtx, mask_rtx;
2945 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2946 left_rtx = XEXP (XEXP (set_src, 0), 1);
2947 mask_rtx = XEXP (set_src, 1);
2948 shl_and_kind (left_rtx, mask_rtx, attributes);
2949 return attributes[1];
2952 /* This is used in length attribute of the and_shl_scratch instruction. */
2955 shl_and_scr_length (rtx insn)
2957 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2958 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
2959 rtx op = XEXP (set_src, 0);
2960 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
2961 op = XEXP (XEXP (op, 0), 0);
2962 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
2965 /* Generate rtl for instructions for which shl_and_kind advised a particular
2966 method of generating them, i.e. returned zero. */
2969 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
2972 unsigned HOST_WIDE_INT mask;
2973 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
2974 int right, total_shift;
2975 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
2977 right = attributes[0];
2978 total_shift = INTVAL (left_rtx) + right;
2979 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
2986 int first = attributes[2];
2991 emit_insn ((mask << right) <= 0xff
2992 ? gen_zero_extendqisi2 (dest,
2993 gen_lowpart (QImode, source))
2994 : gen_zero_extendhisi2 (dest,
2995 gen_lowpart (HImode, source)));
2999 emit_insn (gen_movsi (dest, source));
3003 operands[2] = GEN_INT (right);
3004 gen_shifty_hi_op (LSHIFTRT, operands);
3008 operands[2] = GEN_INT (first);
3009 gen_shifty_hi_op (ASHIFT, operands);
3010 total_shift -= first;
3014 emit_insn (mask <= 0xff
3015 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3016 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3017 if (total_shift > 0)
3019 operands[2] = GEN_INT (total_shift);
3020 gen_shifty_hi_op (ASHIFT, operands);
3025 shift_gen_fun = gen_shifty_op;
3027 /* If the topmost bit that matters is set, set the topmost bits
3028 that don't matter. This way, we might be able to get a shorter
3030 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3031 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3033 /* Don't expand fine-grained when combining, because that will
3034 make the pattern fail. */
3035 if (currently_expanding_to_rtl
3036 || reload_in_progress || reload_completed)
3040 /* Cases 3 and 4 should be handled by this split
3041 only while combining */
3042 gcc_assert (kind <= 2);
3045 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3048 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3053 operands[2] = GEN_INT (total_shift);
3054 shift_gen_fun (ASHIFT, operands);
3061 if (kind != 4 && total_shift < 16)
3063 neg = -ext_shift_amounts[total_shift][1];
3065 neg -= ext_shift_amounts[total_shift][2];
3069 emit_insn (gen_and_shl_scratch (dest, source,
3072 GEN_INT (total_shift + neg),
3074 emit_insn (gen_movsi (dest, dest));
3081 /* Try to find a good way to implement the combiner pattern
3082 [(set (match_operand:SI 0 "register_operand" "=r")
3083 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3084 (match_operand:SI 2 "const_int_operand" "n")
3085 (match_operand:SI 3 "const_int_operand" "n")
3087 (clobber (reg:SI T_REG))]
3088 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3089 return 0 for simple left / right shift combination.
3090 return 1 for left shift / 8 bit sign extend / left shift.
3091 return 2 for left shift / 16 bit sign extend / left shift.
3092 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3093 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3094 return 5 for left shift / 16 bit sign extend / right shift
3095 return 6 for < 8 bit sign extend / left shift.
3096 return 7 for < 8 bit sign extend / left shift / single right shift.
3097 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3100 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3102 int left, size, insize, ext;
3103 int cost = 0, best_cost;
3106 left = INTVAL (left_rtx);
3107 size = INTVAL (size_rtx);
3108 insize = size - left;
3109 gcc_assert (insize > 0);
3110 /* Default to left / right shift. */
3112 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3115 /* 16 bit shift / sign extend / 16 bit shift */
3116 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3117 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3118 below, by alternative 3 or something even better. */
3119 if (cost < best_cost)
3125 /* Try a plain sign extend between two shifts. */
3126 for (ext = 16; ext >= insize; ext -= 8)
3130 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3131 if (cost < best_cost)
3133 kind = ext / (unsigned) 8;
3137 /* Check if we can do a sloppy shift with a final signed shift
3138 restoring the sign. */
3139 if (EXT_SHIFT_SIGNED (size - ext))
3140 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3141 /* If not, maybe it's still cheaper to do the second shift sloppy,
3142 and do a final sign extend? */
3143 else if (size <= 16)
3144 cost = ext_shift_insns[ext - insize] + 1
3145 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3148 if (cost < best_cost)
3150 kind = ext / (unsigned) 8 + 2;
3154 /* Check if we can sign extend in r0 */
3157 cost = 3 + shift_insns[left];
3158 if (cost < best_cost)
3163 /* Try the same with a final signed shift. */
3166 cost = 3 + ext_shift_insns[left + 1] + 1;
3167 if (cost < best_cost)
3176 /* Try to use a dynamic shift. */
3177 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3178 if (cost < best_cost)
3189 /* Function to be used in the length attribute of the instructions
3190 implementing this pattern. */
3193 shl_sext_length (rtx insn)
3195 rtx set_src, left_rtx, size_rtx;
3198 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3199 left_rtx = XEXP (XEXP (set_src, 0), 1);
3200 size_rtx = XEXP (set_src, 1);
3201 shl_sext_kind (left_rtx, size_rtx, &cost);
3205 /* Generate rtl for this pattern */
3208 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3211 int left, size, insize, cost;
3214 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3215 left = INTVAL (left_rtx);
3216 size = INTVAL (size_rtx);
3217 insize = size - left;
3225 int ext = kind & 1 ? 8 : 16;
3226 int shift2 = size - ext;
3228 /* Don't expand fine-grained when combining, because that will
3229 make the pattern fail. */
3230 if (! currently_expanding_to_rtl
3231 && ! reload_in_progress && ! reload_completed)
3233 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3234 emit_insn (gen_movsi (dest, source));
3238 emit_insn (gen_movsi (dest, source));
3242 operands[2] = GEN_INT (ext - insize);
3243 gen_shifty_hi_op (ASHIFT, operands);
3246 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3247 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3252 operands[2] = GEN_INT (shift2);
3253 gen_shifty_op (ASHIFT, operands);
3260 if (EXT_SHIFT_SIGNED (shift2))
3262 operands[2] = GEN_INT (shift2 + 1);
3263 gen_shifty_op (ASHIFT, operands);
3264 operands[2] = const1_rtx;
3265 gen_shifty_op (ASHIFTRT, operands);
3268 operands[2] = GEN_INT (shift2);
3269 gen_shifty_hi_op (ASHIFT, operands);
3273 operands[2] = GEN_INT (-shift2);
3274 gen_shifty_hi_op (LSHIFTRT, operands);
3276 emit_insn (size <= 8
3277 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3278 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3285 if (! currently_expanding_to_rtl
3286 && ! reload_in_progress && ! reload_completed)
3287 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3291 operands[2] = GEN_INT (16 - insize);
3292 gen_shifty_hi_op (ASHIFT, operands);
3293 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3295 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3297 gen_ashift (ASHIFTRT, 1, dest);
3302 /* Don't expand fine-grained when combining, because that will
3303 make the pattern fail. */
3304 if (! currently_expanding_to_rtl
3305 && ! reload_in_progress && ! reload_completed)
3307 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3308 emit_insn (gen_movsi (dest, source));
3311 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3312 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3313 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3315 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3316 gen_shifty_op (ASHIFT, operands);
3318 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3326 /* Prefix a symbol_ref name with "datalabel". */
3329 gen_datalabel_ref (rtx sym)
3333 if (GET_CODE (sym) == LABEL_REF)
3334 return gen_rtx_CONST (GET_MODE (sym),
3335 gen_rtx_UNSPEC (GET_MODE (sym),
3339 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3341 str = XSTR (sym, 0);
3342 /* Share all SYMBOL_REF strings with the same value - that is important
3344 str = IDENTIFIER_POINTER (get_identifier (str));
3345 XSTR (sym, 0) = str;
3351 static alloc_pool label_ref_list_pool;
3353 typedef struct label_ref_list_d
3356 struct label_ref_list_d *next;
3357 } *label_ref_list_t;
3359 /* The SH cannot load a large constant into a register, constants have to
3360 come from a pc relative load. The reference of a pc relative load
3361 instruction must be less than 1k in front of the instruction. This
3362 means that we often have to dump a constant inside a function, and
3363 generate code to branch around it.
3365 It is important to minimize this, since the branches will slow things
3366 down and make things bigger.
3368 Worst case code looks like:
3386 We fix this by performing a scan before scheduling, which notices which
3387 instructions need to have their operands fetched from the constant table
3388 and builds the table.
3392 scan, find an instruction which needs a pcrel move. Look forward, find the
3393 last barrier which is within MAX_COUNT bytes of the requirement.
3394 If there isn't one, make one. Process all the instructions between
3395 the find and the barrier.
3397 In the above example, we can tell that L3 is within 1k of L1, so
3398 the first move can be shrunk from the 3 insn+constant sequence into
3399 just 1 insn, and the constant moved to L3 to make:
3410 Then the second move becomes the target for the shortening process. */
3414 rtx value; /* Value in table. */
3415 rtx label; /* Label of value. */
3416 label_ref_list_t wend; /* End of window. */
3417 enum machine_mode mode; /* Mode of value. */
3419 /* True if this constant is accessed as part of a post-increment
3420 sequence. Note that HImode constants are never accessed in this way. */
3421 bool part_of_sequence_p;
3424 /* The maximum number of constants that can fit into one pool, since
3425 constants in the range 0..510 are at least 2 bytes long, and in the
3426 range from there to 1018 at least 4 bytes. */
3428 #define MAX_POOL_SIZE 372
3429 static pool_node pool_vector[MAX_POOL_SIZE];
3430 static int pool_size;
3431 static rtx pool_window_label;
3432 static int pool_window_last;
3434 static int max_labelno_before_reorg;
3436 /* ??? If we need a constant in HImode which is the truncated value of a
3437 constant we need in SImode, we could combine the two entries thus saving
3438 two bytes. Is this common enough to be worth the effort of implementing
3441 /* ??? This stuff should be done at the same time that we shorten branches.
3442 As it is now, we must assume that all branches are the maximum size, and
3443 this causes us to almost always output constant pools sooner than
3446 /* Add a constant to the pool and return its label. */
3449 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3453 label_ref_list_t ref, newref;
3455 /* First see if we've already got it. */
3456 for (i = 0; i < pool_size; i++)
3458 if (x->code == pool_vector[i].value->code
3459 && mode == pool_vector[i].mode)
3461 if (x->code == CODE_LABEL)
3463 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3466 if (rtx_equal_p (x, pool_vector[i].value))
3471 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3473 new_rtx = gen_label_rtx ();
3474 LABEL_REFS (new_rtx) = pool_vector[i].label;
3475 pool_vector[i].label = lab = new_rtx;
3477 if (lab && pool_window_label)
3479 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3480 newref->label = pool_window_label;
3481 ref = pool_vector[pool_window_last].wend;
3483 pool_vector[pool_window_last].wend = newref;
3486 pool_window_label = new_rtx;
3487 pool_window_last = i;
3493 /* Need a new one. */
3494 pool_vector[pool_size].value = x;
3495 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3498 pool_vector[pool_size - 1].part_of_sequence_p = true;
3501 lab = gen_label_rtx ();
3502 pool_vector[pool_size].mode = mode;
3503 pool_vector[pool_size].label = lab;
3504 pool_vector[pool_size].wend = NULL;
3505 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3506 if (lab && pool_window_label)
3508 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3509 newref->label = pool_window_label;
3510 ref = pool_vector[pool_window_last].wend;
3512 pool_vector[pool_window_last].wend = newref;
3515 pool_window_label = lab;
3516 pool_window_last = pool_size;
3521 /* Output the literal table. START, if nonzero, is the first instruction
3522 this table is needed for, and also indicates that there is at least one
3523 casesi_worker_2 instruction; We have to emit the operand3 labels from
3524 these insns at a 4-byte aligned position. BARRIER is the barrier
3525 after which we are to place the table. */
3528 dump_table (rtx start, rtx barrier)
3534 label_ref_list_t ref;
3537 /* Do two passes, first time dump out the HI sized constants. */
3539 for (i = 0; i < pool_size; i++)
3541 pool_node *p = &pool_vector[i];
3543 if (p->mode == HImode)
3547 scan = emit_insn_after (gen_align_2 (), scan);
3550 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3551 scan = emit_label_after (lab, scan);
3552 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
3554 for (ref = p->wend; ref; ref = ref->next)
3557 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3560 else if (p->mode == DFmode)
3568 scan = emit_insn_after (gen_align_4 (), scan);
3570 for (; start != barrier; start = NEXT_INSN (start))
3571 if (GET_CODE (start) == INSN
3572 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
3574 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
3575 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
3577 scan = emit_label_after (lab, scan);
3580 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
3582 rtx align_insn = NULL_RTX;
3584 scan = emit_label_after (gen_label_rtx (), scan);
3585 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3588 for (i = 0; i < pool_size; i++)
3590 pool_node *p = &pool_vector[i];
3598 if (align_insn && !p->part_of_sequence_p)
3600 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3601 emit_label_before (lab, align_insn);
3602 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
3604 for (ref = p->wend; ref; ref = ref->next)
3607 emit_insn_before (gen_consttable_window_end (lab),
3610 delete_insn (align_insn);
3611 align_insn = NULL_RTX;
3616 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3617 scan = emit_label_after (lab, scan);
3618 scan = emit_insn_after (gen_consttable_4 (p->value,
3620 need_align = ! need_align;
3626 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3631 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3632 scan = emit_label_after (lab, scan);
3633 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3640 if (p->mode != HImode)
3642 for (ref = p->wend; ref; ref = ref->next)
3645 scan = emit_insn_after (gen_consttable_window_end (lab),
3654 for (i = 0; i < pool_size; i++)
3656 pool_node *p = &pool_vector[i];
3667 scan = emit_label_after (gen_label_rtx (), scan);
3668 scan = emit_insn_after (gen_align_4 (), scan);
3670 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3671 scan = emit_label_after (lab, scan);
3672 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
3680 scan = emit_label_after (gen_label_rtx (), scan);
3681 scan = emit_insn_after (gen_align_4 (), scan);
3683 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3684 scan = emit_label_after (lab, scan);
3685 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3692 if (p->mode != HImode)
3694 for (ref = p->wend; ref; ref = ref->next)
3697 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3702 scan = emit_insn_after (gen_consttable_end (), scan);
3703 scan = emit_barrier_after (scan);
3705 pool_window_label = NULL_RTX;
3706 pool_window_last = 0;
3709 /* Return nonzero if constant would be an ok source for a
3710 mov.w instead of a mov.l. */
3715 return (GET_CODE (src) == CONST_INT
3716 && INTVAL (src) >= -32768
3717 && INTVAL (src) <= 32767);
3720 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
3722 /* Nonzero if the insn is a move instruction which needs to be fixed. */
3724 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
3725 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
3726 need to fix it if the input value is CONST_OK_FOR_I08. */
3729 broken_move (rtx insn)
3731 if (GET_CODE (insn) == INSN)
3733 rtx pat = PATTERN (insn);
3734 if (GET_CODE (pat) == PARALLEL)
3735 pat = XVECEXP (pat, 0, 0);
3736 if (GET_CODE (pat) == SET
3737 /* We can load any 8-bit value if we don't care what the high
3738 order bits end up as. */
3739 && GET_MODE (SET_DEST (pat)) != QImode
3740 && (CONSTANT_P (SET_SRC (pat))
3741 /* Match mova_const. */
3742 || (GET_CODE (SET_SRC (pat)) == UNSPEC
3743 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
3744 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
3746 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
3747 && (fp_zero_operand (SET_SRC (pat))
3748 || fp_one_operand (SET_SRC (pat)))
3749 /* ??? If this is a -m4 or -m4-single compilation, in general
3750 we don't know the current setting of fpscr, so disable fldi.
3751 There is an exception if this was a register-register move
3752 before reload - and hence it was ascertained that we have
3753 single precision setting - and in a post-reload optimization
3754 we changed this to do a constant load. In that case
3755 we don't have an r0 clobber, hence we must use fldi. */
3756 && (! TARGET_SH4 || TARGET_FMOVD
3757 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
3759 && GET_CODE (SET_DEST (pat)) == REG
3760 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
3762 && GET_MODE (SET_DEST (pat)) == SImode
3763 && (satisfies_constraint_I20 (SET_SRC (pat))
3764 || satisfies_constraint_I28 (SET_SRC (pat))))
3765 && ! satisfies_constraint_I08 (SET_SRC (pat)))
3775 return (GET_CODE (insn) == INSN
3776 && GET_CODE (PATTERN (insn)) == SET
3777 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
3778 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
3779 /* Don't match mova_const. */
3780 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
3783 /* Fix up a mova from a switch that went out of range. */
3785 fixup_mova (rtx mova)
3787 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
3790 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
3791 INSN_CODE (mova) = -1;
3796 rtx lab = gen_label_rtx ();
3797 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
3801 worker = NEXT_INSN (worker);
3803 && GET_CODE (worker) != CODE_LABEL
3804 && GET_CODE (worker) != JUMP_INSN);
3805 } while (GET_CODE (worker) == NOTE
3806 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
3807 wpat = PATTERN (worker);
3808 wpat0 = XVECEXP (wpat, 0, 0);
3809 wpat1 = XVECEXP (wpat, 0, 1);
3810 wsrc = SET_SRC (wpat0);
3811 PATTERN (worker) = (gen_casesi_worker_2
3812 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
3813 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
3815 INSN_CODE (worker) = -1;
3816 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3817 base = gen_rtx_LABEL_REF (Pmode, lab);
3818 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
3819 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
3820 INSN_CODE (mova) = -1;
3824 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
3825 *num_mova, and check if the new mova is not nested within the first one.
3826 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
3827 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
3829 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
3831 int n_addr = 0; /* Initialization to shut up spurious warning. */
3832 int f_target, n_target = 0; /* Likewise. */
3836 /* If NEW_MOVA has no address yet, it will be handled later. */
3837 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
3840 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
3841 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
3842 if (n_addr > n_target || n_addr + 1022 < n_target)
3844 /* Change the mova into a load.
3845 broken_move will then return true for it. */
3846 fixup_mova (new_mova);
3852 *first_mova = new_mova;
3857 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
3862 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
3863 > n_target - n_addr)
3865 fixup_mova (*first_mova);
3870 fixup_mova (new_mova);
3875 /* Find the last barrier from insn FROM which is close enough to hold the
3876 constant pool. If we can't find one, then create one near the end of
3880 find_barrier (int num_mova, rtx mova, rtx from)
3889 int leading_mova = num_mova;
3890 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
3895 /* For HImode: range is 510, add 4 because pc counts from address of
3896 second instruction after this one, subtract 2 for the jump instruction
3897 that we may need to emit before the table, subtract 2 for the instruction
3898 that fills the jump delay slot (in very rare cases, reorg will take an
3899 instruction from after the constant pool or will leave the delay slot
3900 empty). This gives 510.
3901 For SImode: range is 1020, add 4 because pc counts from address of
3902 second instruction after this one, subtract 2 in case pc is 2 byte
3903 aligned, subtract 2 for the jump instruction that we may need to emit
3904 before the table, subtract 2 for the instruction that fills the jump
3905 delay slot. This gives 1018. */
3907 /* The branch will always be shortened now that the reference address for
3908 forward branches is the successor address, thus we need no longer make
3909 adjustments to the [sh]i_limit for -O0. */
3914 while (from && count_si < si_limit && count_hi < hi_limit)
3916 int inc = get_attr_length (from);
3919 /* If this is a label that existed at the time of the compute_alignments
3920 call, determine the alignment. N.B. When find_barrier recurses for
3921 an out-of-reach mova, we might see labels at the start of previously
3922 inserted constant tables. */
3923 if (GET_CODE (from) == CODE_LABEL
3924 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
3927 new_align = 1 << label_to_alignment (from);
3928 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
3929 new_align = 1 << barrier_align (from);
3934 /* In case we are scanning a constant table because of recursion, check
3935 for explicit alignments. If the table is long, we might be forced
3936 to emit the new table in front of it; the length of the alignment
3937 might be the last straw. */
3938 else if (GET_CODE (from) == INSN
3939 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
3940 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
3941 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
3942 /* When we find the end of a constant table, paste the new constant
3943 at the end. That is better than putting it in front because
3944 this way, we don't need extra alignment for adding a 4-byte-aligned
3945 mov(a) label to a 2/4 or 8/4 byte aligned table. */
3946 else if (GET_CODE (from) == INSN
3947 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
3948 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
3951 if (GET_CODE (from) == BARRIER)
3955 found_barrier = from;
3957 /* If we are at the end of the function, or in front of an alignment
3958 instruction, we need not insert an extra alignment. We prefer
3959 this kind of barrier. */
3960 if (barrier_align (from) > 2)
3961 good_barrier = from;
3963 /* If we are at the end of a hot/cold block, dump the constants
3965 next = NEXT_INSN (from);
3968 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
3972 if (broken_move (from))
3975 enum machine_mode mode;
3977 pat = PATTERN (from);
3978 if (GET_CODE (pat) == PARALLEL)
3979 pat = XVECEXP (pat, 0, 0);
3980 src = SET_SRC (pat);
3981 dst = SET_DEST (pat);
3982 mode = GET_MODE (dst);
3984 /* We must explicitly check the mode, because sometimes the
3985 front end will generate code to load unsigned constants into
3986 HImode targets without properly sign extending them. */
3988 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
3991 /* We put the short constants before the long constants, so
3992 we must count the length of short constants in the range
3993 for the long constants. */
3994 /* ??? This isn't optimal, but is easy to do. */
3999 /* We dump DF/DI constants before SF/SI ones, because
4000 the limit is the same, but the alignment requirements
4001 are higher. We may waste up to 4 additional bytes
4002 for alignment, and the DF/DI constant may have
4003 another SF/SI constant placed before it. */
4004 if (TARGET_SHCOMPACT
4006 && (mode == DFmode || mode == DImode))
4011 while (si_align > 2 && found_si + si_align - 2 > count_si)
4013 if (found_si > count_si)
4014 count_si = found_si;
4015 found_si += GET_MODE_SIZE (mode);
4017 si_limit -= GET_MODE_SIZE (mode);
4023 switch (untangle_mova (&num_mova, &mova, from))
4025 case 0: return find_barrier (0, 0, mova);
4030 = good_barrier ? good_barrier : found_barrier;
4034 if (found_si > count_si)
4035 count_si = found_si;
4037 else if (GET_CODE (from) == JUMP_INSN
4038 && (GET_CODE (PATTERN (from)) == ADDR_VEC
4039 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
4041 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4043 && (prev_nonnote_insn (from)
4044 == XEXP (MOVA_LABELREF (mova), 0))))
4046 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4048 /* We have just passed the barrier in front of the
4049 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4050 the ADDR_DIFF_VEC is accessed as data, just like our pool
4051 constants, this is a good opportunity to accommodate what
4052 we have gathered so far.
4053 If we waited any longer, we could end up at a barrier in
4054 front of code, which gives worse cache usage for separated
4055 instruction / data caches. */
4056 good_barrier = found_barrier;
4061 rtx body = PATTERN (from);
4062 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4065 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4066 else if (GET_CODE (from) == JUMP_INSN
4068 && ! TARGET_SMALLCODE)
4074 if (new_align > si_align)
4076 si_limit -= (count_si - 1) & (new_align - si_align);
4077 si_align = new_align;
4079 count_si = (count_si + new_align - 1) & -new_align;
4084 if (new_align > hi_align)
4086 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4087 hi_align = new_align;
4089 count_hi = (count_hi + new_align - 1) & -new_align;
4091 from = NEXT_INSN (from);
4098 /* Try as we might, the leading mova is out of range. Change
4099 it into a load (which will become a pcload) and retry. */
4101 return find_barrier (0, 0, mova);
4105 /* Insert the constant pool table before the mova instruction,
4106 to prevent the mova label reference from going out of range. */
4108 good_barrier = found_barrier = barrier_before_mova;
4114 if (good_barrier && next_real_insn (found_barrier))
4115 found_barrier = good_barrier;
4119 /* We didn't find a barrier in time to dump our stuff,
4120 so we'll make one. */
4121 rtx label = gen_label_rtx ();
4123 /* If we exceeded the range, then we must back up over the last
4124 instruction we looked at. Otherwise, we just need to undo the
4125 NEXT_INSN at the end of the loop. */
4126 if (PREV_INSN (from) != orig
4127 && (count_hi > hi_limit || count_si > si_limit))
4128 from = PREV_INSN (PREV_INSN (from));
4130 from = PREV_INSN (from);
4132 /* Walk back to be just before any jump or label.
4133 Putting it before a label reduces the number of times the branch
4134 around the constant pool table will be hit. Putting it before
4135 a jump makes it more likely that the bra delay slot will be
4137 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
4138 || GET_CODE (from) == CODE_LABEL)
4139 from = PREV_INSN (from);
4141 from = emit_jump_insn_after (gen_jump (label), from);
4142 JUMP_LABEL (from) = label;
4143 LABEL_NUSES (label) = 1;
4144 found_barrier = emit_barrier_after (from);
4145 emit_label_after (label, found_barrier);
4148 return found_barrier;
4151 /* If the instruction INSN is implemented by a special function, and we can
4152 positively find the register that is used to call the sfunc, and this
4153 register is not used anywhere else in this instruction - except as the
4154 destination of a set, return this register; else, return 0. */
4156 sfunc_uses_reg (rtx insn)
4159 rtx pattern, part, reg_part, reg;
4161 if (GET_CODE (insn) != INSN)
4163 pattern = PATTERN (insn);
4164 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4167 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4169 part = XVECEXP (pattern, 0, i);
4170 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4175 reg = XEXP (reg_part, 0);
4176 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4178 part = XVECEXP (pattern, 0, i);
4179 if (part == reg_part || GET_CODE (part) == CLOBBER)
4181 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4182 && GET_CODE (SET_DEST (part)) == REG)
4183 ? SET_SRC (part) : part)))
4189 /* See if the only way in which INSN uses REG is by calling it, or by
4190 setting it while calling it. Set *SET to a SET rtx if the register
4194 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4200 reg2 = sfunc_uses_reg (insn);
4201 if (reg2 && REGNO (reg2) == REGNO (reg))
4203 pattern = single_set (insn);
4205 && GET_CODE (SET_DEST (pattern)) == REG
4206 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4210 if (GET_CODE (insn) != CALL_INSN)
4212 /* We don't use rtx_equal_p because we don't care if the mode is
4214 pattern = single_set (insn);
4216 && GET_CODE (SET_DEST (pattern)) == REG
4217 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4223 par = PATTERN (insn);
4224 if (GET_CODE (par) == PARALLEL)
4225 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4227 part = XVECEXP (par, 0, i);
4228 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4231 return reg_mentioned_p (reg, SET_SRC (pattern));
4237 pattern = PATTERN (insn);
4239 if (GET_CODE (pattern) == PARALLEL)
4243 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4244 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4246 pattern = XVECEXP (pattern, 0, 0);
4249 if (GET_CODE (pattern) == SET)
4251 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4253 /* We don't use rtx_equal_p, because we don't care if the
4254 mode is different. */
4255 if (GET_CODE (SET_DEST (pattern)) != REG
4256 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4262 pattern = SET_SRC (pattern);
4265 if (GET_CODE (pattern) != CALL
4266 || GET_CODE (XEXP (pattern, 0)) != MEM
4267 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4273 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4274 general registers. Bits 0..15 mean that the respective registers
4275 are used as inputs in the instruction. Bits 16..31 mean that the
4276 registers 0..15, respectively, are used as outputs, or are clobbered.
4277 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4279 regs_used (rtx x, int is_dest)
4287 code = GET_CODE (x);
4292 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4293 << (REGNO (x) + is_dest));
4297 rtx y = SUBREG_REG (x);
4299 if (GET_CODE (y) != REG)
4302 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4304 subreg_regno_offset (REGNO (y),
4307 GET_MODE (x)) + is_dest));
4311 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4313 /* If there was a return value, it must have been indicated with USE. */
4328 fmt = GET_RTX_FORMAT (code);
4330 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4335 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4336 used |= regs_used (XVECEXP (x, i, j), is_dest);
4338 else if (fmt[i] == 'e')
4339 used |= regs_used (XEXP (x, i), is_dest);
4344 /* Create an instruction that prevents redirection of a conditional branch
4345 to the destination of the JUMP with address ADDR.
4346 If the branch needs to be implemented as an indirect jump, try to find
4347 a scratch register for it.
4348 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4349 If any preceding insn that doesn't fit into a delay slot is good enough,
4350 pass 1. Pass 2 if a definite blocking insn is needed.
4351 -1 is used internally to avoid deep recursion.
4352 If a blocking instruction is made or recognized, return it. */
4355 gen_block_redirect (rtx jump, int addr, int need_block)
4358 rtx prev = prev_nonnote_insn (jump);
4361 /* First, check if we already have an instruction that satisfies our need. */
4362 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
4364 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4366 if (GET_CODE (PATTERN (prev)) == USE
4367 || GET_CODE (PATTERN (prev)) == CLOBBER
4368 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4370 else if ((need_block &= ~1) < 0)
4372 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4375 if (GET_CODE (PATTERN (jump)) == RETURN)
4379 /* Reorg even does nasty things with return insns that cause branches
4380 to go out of range - see find_end_label and callers. */
4381 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4383 /* We can't use JUMP_LABEL here because it might be undefined
4384 when not optimizing. */
4385 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4386 /* If the branch is out of range, try to find a scratch register for it. */
4388 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4392 /* Don't look for the stack pointer as a scratch register,
4393 it would cause trouble if an interrupt occurred. */
4394 unsigned attempt = 0x7fff, used;
4395 int jump_left = flag_expensive_optimizations + 1;
4397 /* It is likely that the most recent eligible instruction is wanted for
4398 the delay slot. Therefore, find out which registers it uses, and
4399 try to avoid using them. */
4401 for (scan = jump; (scan = PREV_INSN (scan)); )
4405 if (INSN_DELETED_P (scan))
4407 code = GET_CODE (scan);
4408 if (code == CODE_LABEL || code == JUMP_INSN)
4411 && GET_CODE (PATTERN (scan)) != USE
4412 && GET_CODE (PATTERN (scan)) != CLOBBER
4413 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4415 attempt &= ~regs_used (PATTERN (scan), 0);
4419 for (used = dead = 0, scan = JUMP_LABEL (jump);
4420 (scan = NEXT_INSN (scan)); )
4424 if (INSN_DELETED_P (scan))
4426 code = GET_CODE (scan);
4429 used |= regs_used (PATTERN (scan), 0);
4430 if (code == CALL_INSN)
4431 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4432 dead |= (used >> 16) & ~used;
4438 if (code == JUMP_INSN)
4440 if (jump_left-- && simplejump_p (scan))
4441 scan = JUMP_LABEL (scan);
4447 /* Mask out the stack pointer again, in case it was
4448 the only 'free' register we have found. */
4451 /* If the immediate destination is still in range, check for possible
4452 threading with a jump beyond the delay slot insn.
4453 Don't check if we are called recursively; the jump has been or will be
4454 checked in a different invocation then. */
4456 else if (optimize && need_block >= 0)
4458 rtx next = next_active_insn (next_active_insn (dest));
4459 if (next && GET_CODE (next) == JUMP_INSN
4460 && GET_CODE (PATTERN (next)) == SET
4461 && recog_memoized (next) == CODE_FOR_jump_compact)
4463 dest = JUMP_LABEL (next);
4465 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4467 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4473 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4475 /* It would be nice if we could convert the jump into an indirect
4476 jump / far branch right now, and thus exposing all constituent
4477 instructions to further optimization. However, reorg uses
4478 simplejump_p to determine if there is an unconditional jump where
4479 it should try to schedule instructions from the target of the
4480 branch; simplejump_p fails for indirect jumps even if they have
4482 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4483 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4485 /* ??? We would like this to have the scope of the jump, but that
4486 scope will change when a delay slot insn of an inner scope is added.
4487 Hence, after delay slot scheduling, we'll have to expect
4488 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4491 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4492 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4495 else if (need_block)
4496 /* We can't use JUMP_LABEL here because it might be undefined
4497 when not optimizing. */
4498 return emit_insn_before (gen_block_branch_redirect
4499 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4504 #define CONDJUMP_MIN -252
4505 #define CONDJUMP_MAX 262
4508 /* A label (to be placed) in front of the jump
4509 that jumps to our ultimate destination. */
4511 /* Where we are going to insert it if we cannot move the jump any farther,
4512 or the jump itself if we have picked up an existing jump. */
4514 /* The ultimate destination. */
4516 struct far_branch *prev;
4517 /* If the branch has already been created, its address;
4518 else the address of its first prospective user. */
4522 static void gen_far_branch (struct far_branch *);
4523 enum mdep_reorg_phase_e mdep_reorg_phase;
4525 gen_far_branch (struct far_branch *bp)
4527 rtx insn = bp->insert_place;
4529 rtx label = gen_label_rtx ();
4532 emit_label_after (label, insn);
4535 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
4536 LABEL_NUSES (bp->far_label)++;
4539 jump = emit_jump_insn_after (gen_return (), insn);
4540 /* Emit a barrier so that reorg knows that any following instructions
4541 are not reachable via a fall-through path.
4542 But don't do this when not optimizing, since we wouldn't suppress the
4543 alignment for the barrier then, and could end up with out-of-range
4544 pc-relative loads. */
4546 emit_barrier_after (jump);
4547 emit_label_after (bp->near_label, insn);
4548 JUMP_LABEL (jump) = bp->far_label;
4549 ok = invert_jump (insn, label, 1);
4552 /* If we are branching around a jump (rather than a return), prevent
4553 reorg from using an insn from the jump target as the delay slot insn -
4554 when reorg did this, it pessimized code (we rather hide the delay slot)
4555 and it could cause branches to go out of range. */
4558 (gen_stuff_delay_slot
4559 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
4560 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
4562 /* Prevent reorg from undoing our splits. */
4563 gen_block_redirect (jump, bp->address += 2, 2);
4566 /* Fix up ADDR_DIFF_VECs. */
4568 fixup_addr_diff_vecs (rtx first)
4572 for (insn = first; insn; insn = NEXT_INSN (insn))
4574 rtx vec_lab, pat, prev, prevpat, x, braf_label;
4576 if (GET_CODE (insn) != JUMP_INSN
4577 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
4579 pat = PATTERN (insn);
4580 vec_lab = XEXP (XEXP (pat, 0), 0);
4582 /* Search the matching casesi_jump_2. */
4583 for (prev = vec_lab; ; prev = PREV_INSN (prev))
4585 if (GET_CODE (prev) != JUMP_INSN)
4587 prevpat = PATTERN (prev);
4588 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
4590 x = XVECEXP (prevpat, 0, 1);
4591 if (GET_CODE (x) != USE)
4594 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
4597 /* FIXME: This is a bug in the optimizer, but it seems harmless
4598 to just avoid panicing. */
4602 /* Emit the reference label of the braf where it belongs, right after
4603 the casesi_jump_2 (i.e. braf). */
4604 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
4605 emit_label_after (braf_label, prev);
4607 /* Fix up the ADDR_DIF_VEC to be relative
4608 to the reference address of the braf. */
4609 XEXP (XEXP (pat, 0), 0) = braf_label;
4613 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
4614 a barrier. Return the base 2 logarithm of the desired alignment. */
4616 barrier_align (rtx barrier_or_label)
4618 rtx next = next_real_insn (barrier_or_label), pat, prev;
4619 int slot, credit, jump_to_next = 0;
4624 pat = PATTERN (next);
4626 if (GET_CODE (pat) == ADDR_DIFF_VEC)
4629 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
4630 /* This is a barrier in front of a constant table. */
4633 prev = prev_real_insn (barrier_or_label);
4634 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
4636 pat = PATTERN (prev);
4637 /* If this is a very small table, we want to keep the alignment after
4638 the table to the minimum for proper code alignment. */
4639 return ((TARGET_SMALLCODE
4640 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
4641 <= (unsigned) 1 << (CACHE_LOG - 2)))
4642 ? 1 << TARGET_SHMEDIA : align_jumps_log);
4645 if (TARGET_SMALLCODE)
4648 if (! TARGET_SH2 || ! optimize)
4649 return align_jumps_log;
4651 /* When fixing up pcloads, a constant table might be inserted just before
4652 the basic block that ends with the barrier. Thus, we can't trust the
4653 instruction lengths before that. */
4654 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
4656 /* Check if there is an immediately preceding branch to the insn beyond
4657 the barrier. We must weight the cost of discarding useful information
4658 from the current cache line when executing this branch and there is
4659 an alignment, against that of fetching unneeded insn in front of the
4660 branch target when there is no alignment. */
4662 /* There are two delay_slot cases to consider. One is the simple case
4663 where the preceding branch is to the insn beyond the barrier (simple
4664 delay slot filling), and the other is where the preceding branch has
4665 a delay slot that is a duplicate of the insn after the barrier
4666 (fill_eager_delay_slots) and the branch is to the insn after the insn
4667 after the barrier. */
4669 /* PREV is presumed to be the JUMP_INSN for the barrier under
4670 investigation. Skip to the insn before it. */
4671 prev = prev_real_insn (prev);
4673 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
4674 credit >= 0 && prev && GET_CODE (prev) == INSN;
4675 prev = prev_real_insn (prev))
4678 if (GET_CODE (PATTERN (prev)) == USE
4679 || GET_CODE (PATTERN (prev)) == CLOBBER)
4681 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
4683 prev = XVECEXP (PATTERN (prev), 0, 1);
4684 if (INSN_UID (prev) == INSN_UID (next))
4686 /* Delay slot was filled with insn at jump target. */
4693 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4695 credit -= get_attr_length (prev);
4698 && GET_CODE (prev) == JUMP_INSN
4699 && JUMP_LABEL (prev))
4703 || next_real_insn (JUMP_LABEL (prev)) == next
4704 /* If relax_delay_slots() decides NEXT was redundant
4705 with some previous instruction, it will have
4706 redirected PREV's jump to the following insn. */
4707 || JUMP_LABEL (prev) == next_nonnote_insn (next)
4708 /* There is no upper bound on redundant instructions
4709 that might have been skipped, but we must not put an
4710 alignment where none had been before. */
4711 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
4713 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
4714 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
4715 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
4717 rtx pat = PATTERN (prev);
4718 if (GET_CODE (pat) == PARALLEL)
4719 pat = XVECEXP (pat, 0, 0);
4720 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
4726 return align_jumps_log;
4729 /* If we are inside a phony loop, almost any kind of label can turn up as the
4730 first one in the loop. Aligning a braf label causes incorrect switch
4731 destination addresses; we can detect braf labels because they are
4732 followed by a BARRIER.
4733 Applying loop alignment to small constant or switch tables is a waste
4734 of space, so we suppress this too. */
4736 sh_loop_align (rtx label)
4741 next = next_nonnote_insn (next);
4742 while (next && GET_CODE (next) == CODE_LABEL);
4746 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
4747 || recog_memoized (next) == CODE_FOR_consttable_2)
4750 return align_loops_log;
4753 /* Do a final pass over the function, just before delayed branch
4759 rtx first, insn, mova = NULL_RTX;
4761 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
4762 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
4764 first = get_insns ();
4765 max_labelno_before_reorg = max_label_num ();
4767 /* We must split call insns before introducing `mova's. If we're
4768 optimizing, they'll have already been split. Otherwise, make
4769 sure we don't split them too late. */
4771 split_all_insns_noflow ();
4776 /* If relaxing, generate pseudo-ops to associate function calls with
4777 the symbols they call. It does no harm to not generate these
4778 pseudo-ops. However, when we can generate them, it enables to
4779 linker to potentially relax the jsr to a bsr, and eliminate the
4780 register load and, possibly, the constant pool entry. */
4782 mdep_reorg_phase = SH_INSERT_USES_LABELS;
4785 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
4786 own purposes. This works because none of the remaining passes
4787 need to look at them.
4789 ??? But it may break in the future. We should use a machine
4790 dependent REG_NOTE, or some other approach entirely. */
4791 for (insn = first; insn; insn = NEXT_INSN (insn))
4797 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
4799 remove_note (insn, note);
4803 for (insn = first; insn; insn = NEXT_INSN (insn))
4805 rtx pattern, reg, link, set, scan, dies, label;
4806 int rescan = 0, foundinsn = 0;
4808 if (GET_CODE (insn) == CALL_INSN)
4810 pattern = PATTERN (insn);
4812 if (GET_CODE (pattern) == PARALLEL)
4813 pattern = XVECEXP (pattern, 0, 0);
4814 if (GET_CODE (pattern) == SET)
4815 pattern = SET_SRC (pattern);
4817 if (GET_CODE (pattern) != CALL
4818 || GET_CODE (XEXP (pattern, 0)) != MEM)
4821 reg = XEXP (XEXP (pattern, 0), 0);
4825 reg = sfunc_uses_reg (insn);
4830 if (GET_CODE (reg) != REG)
4833 /* Try scanning backward to find where the register is set. */
4835 for (scan = PREV_INSN (insn);
4836 scan && GET_CODE (scan) != CODE_LABEL;
4837 scan = PREV_INSN (scan))
4839 if (! INSN_P (scan))
4842 if (! reg_mentioned_p (reg, scan))
4845 if (noncall_uses_reg (reg, scan, &set))
4858 /* The register is set at LINK. */
4860 /* We can only optimize the function call if the register is
4861 being set to a symbol. In theory, we could sometimes
4862 optimize calls to a constant location, but the assembler
4863 and linker do not support that at present. */
4864 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
4865 && GET_CODE (SET_SRC (set)) != LABEL_REF)
4868 /* Scan forward from LINK to the place where REG dies, and
4869 make sure that the only insns which use REG are
4870 themselves function calls. */
4872 /* ??? This doesn't work for call targets that were allocated
4873 by reload, since there may not be a REG_DEAD note for the
4877 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
4881 /* Don't try to trace forward past a CODE_LABEL if we haven't
4882 seen INSN yet. Ordinarily, we will only find the setting insn
4883 if it is in the same basic block. However,
4884 cross-jumping can insert code labels in between the load and
4885 the call, and can result in situations where a single call
4886 insn may have two targets depending on where we came from. */
4888 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
4891 if (! INSN_P (scan))
4894 /* Don't try to trace forward past a JUMP. To optimize
4895 safely, we would have to check that all the
4896 instructions at the jump destination did not use REG. */
4898 if (GET_CODE (scan) == JUMP_INSN)
4901 if (! reg_mentioned_p (reg, scan))
4904 if (noncall_uses_reg (reg, scan, &scanset))
4911 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
4913 /* There is a function call to this register other
4914 than the one we are checking. If we optimize
4915 this call, we need to rescan again below. */
4919 /* ??? We shouldn't have to worry about SCANSET here.
4920 We should just be able to check for a REG_DEAD note
4921 on a function call. However, the REG_DEAD notes are
4922 apparently not dependable around libcalls; c-torture
4923 execute/920501-2 is a test case. If SCANSET is set,
4924 then this insn sets the register, so it must have
4925 died earlier. Unfortunately, this will only handle
4926 the cases in which the register is, in fact, set in a
4929 /* ??? We shouldn't have to use FOUNDINSN here.
4930 This dates back to when we used LOG_LINKS to find
4931 the most recent insn which sets the register. */
4935 || find_reg_note (scan, REG_DEAD, reg)))
4944 /* Either there was a branch, or some insn used REG
4945 other than as a function call address. */
4949 /* Create a code label, and put it in a REG_LABEL_OPERAND note
4950 on the insn which sets the register, and on each call insn
4951 which uses the register. In final_prescan_insn we look for
4952 the REG_LABEL_OPERAND notes, and output the appropriate label
4955 label = gen_label_rtx ();
4956 add_reg_note (link, REG_LABEL_OPERAND, label);
4957 add_reg_note (insn, REG_LABEL_OPERAND, label);
4965 scan = NEXT_INSN (scan);
4967 && ((GET_CODE (scan) == CALL_INSN
4968 && reg_mentioned_p (reg, scan))
4969 || ((reg2 = sfunc_uses_reg (scan))
4970 && REGNO (reg2) == REGNO (reg))))
4971 add_reg_note (scan, REG_LABEL_OPERAND, label);
4973 while (scan != dies);
4979 fixup_addr_diff_vecs (first);
4983 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
4984 shorten_branches (first);
4987 /* Scan the function looking for move instructions which have to be
4988 changed to pc-relative loads and insert the literal tables. */
4989 label_ref_list_pool = create_alloc_pool ("label references list",
4990 sizeof (struct label_ref_list_d),
4992 mdep_reorg_phase = SH_FIXUP_PCLOAD;
4993 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
4997 /* ??? basic block reordering can move a switch table dispatch
4998 below the switch table. Check if that has happened.
4999 We only have the addresses available when optimizing; but then,
5000 this check shouldn't be needed when not optimizing. */
5001 if (!untangle_mova (&num_mova, &mova, insn))
5007 else if (GET_CODE (insn) == JUMP_INSN
5008 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5010 /* ??? loop invariant motion can also move a mova out of a
5011 loop. Since loop does this code motion anyway, maybe we
5012 should wrap UNSPEC_MOVA into a CONST, so that reload can
5015 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5016 || (prev_nonnote_insn (insn)
5017 == XEXP (MOVA_LABELREF (mova), 0))))
5024 /* Some code might have been inserted between the mova and
5025 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5026 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5027 total += get_attr_length (scan);
5029 /* range of mova is 1020, add 4 because pc counts from address of
5030 second instruction after this one, subtract 2 in case pc is 2
5031 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5032 cancels out with alignment effects of the mova itself. */
5035 /* Change the mova into a load, and restart scanning
5036 there. broken_move will then return true for mova. */
5041 if (broken_move (insn)
5042 || (GET_CODE (insn) == INSN
5043 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5046 /* Scan ahead looking for a barrier to stick the constant table
5048 rtx barrier = find_barrier (num_mova, mova, insn);
5049 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5050 int need_aligned_label = 0;
5052 if (num_mova && ! mova_p (mova))
5054 /* find_barrier had to change the first mova into a
5055 pcload; thus, we have to start with this new pcload. */
5059 /* Now find all the moves between the points and modify them. */
5060 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5062 if (GET_CODE (scan) == CODE_LABEL)
5064 if (GET_CODE (scan) == INSN
5065 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5066 need_aligned_label = 1;
5067 if (broken_move (scan))
5069 rtx *patp = &PATTERN (scan), pat = *patp;
5073 enum machine_mode mode;
5075 if (GET_CODE (pat) == PARALLEL)
5076 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5077 src = SET_SRC (pat);
5078 dst = SET_DEST (pat);
5079 mode = GET_MODE (dst);
5081 if (mode == SImode && hi_const (src)
5082 && REGNO (dst) != FPUL_REG)
5087 while (GET_CODE (dst) == SUBREG)
5089 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5090 GET_MODE (SUBREG_REG (dst)),
5093 dst = SUBREG_REG (dst);
5095 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5097 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
5099 /* This must be an insn that clobbers r0. */
5100 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5101 XVECLEN (PATTERN (scan), 0)
5103 rtx clobber = *clobberp;
5105 gcc_assert (GET_CODE (clobber) == CLOBBER
5106 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5109 && reg_set_between_p (r0_rtx, last_float_move, scan))
5113 && GET_MODE_SIZE (mode) != 4
5114 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5116 lab = add_constant (src, mode, last_float);
5118 emit_insn_before (gen_mova (lab), scan);
5121 /* There will be a REG_UNUSED note for r0 on
5122 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5123 lest reorg:mark_target_live_regs will not
5124 consider r0 to be used, and we end up with delay
5125 slot insn in front of SCAN that clobbers r0. */
5127 = find_regno_note (last_float_move, REG_UNUSED, 0);
5129 /* If we are not optimizing, then there may not be
5132 PUT_REG_NOTE_KIND (note, REG_INC);
5134 *last_float_addr = r0_inc_rtx;
5136 last_float_move = scan;
5138 newsrc = gen_const_mem (mode,
5139 (((TARGET_SH4 && ! TARGET_FMOVD)
5140 || REGNO (dst) == FPUL_REG)
5143 last_float_addr = &XEXP (newsrc, 0);
5145 /* Remove the clobber of r0. */
5146 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5147 gen_rtx_SCRATCH (Pmode));
5149 /* This is a mova needing a label. Create it. */
5150 else if (GET_CODE (src) == UNSPEC
5151 && XINT (src, 1) == UNSPEC_MOVA
5152 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5154 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5155 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5156 newsrc = gen_rtx_UNSPEC (SImode,
5157 gen_rtvec (1, newsrc),
5162 lab = add_constant (src, mode, 0);
5163 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5164 newsrc = gen_const_mem (mode, newsrc);
5166 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5167 INSN_CODE (scan) = -1;
5170 dump_table (need_aligned_label ? insn : 0, barrier);
5174 free_alloc_pool (label_ref_list_pool);
5175 for (insn = first; insn; insn = NEXT_INSN (insn))
5176 PUT_MODE (insn, VOIDmode);
5178 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5179 INSN_ADDRESSES_FREE ();
5180 split_branches (first);
5182 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5183 also has an effect on the register that holds the address of the sfunc.
5184 Insert an extra dummy insn in front of each sfunc that pretends to
5185 use this register. */
5186 if (flag_delayed_branch)
5188 for (insn = first; insn; insn = NEXT_INSN (insn))
5190 rtx reg = sfunc_uses_reg (insn);
5194 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5198 /* fpscr is not actually a user variable, but we pretend it is for the
5199 sake of the previous optimization passes, since we want it handled like
5200 one. However, we don't have any debugging information for it, so turn
5201 it into a non-user variable now. */
5203 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5205 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5209 get_dest_uid (rtx label, int max_uid)
5211 rtx dest = next_real_insn (label);
5214 /* This can happen for an undefined label. */
5216 dest_uid = INSN_UID (dest);
5217 /* If this is a newly created branch redirection blocking instruction,
5218 we cannot index the branch_uid or insn_addresses arrays with its
5219 uid. But then, we won't need to, because the actual destination is
5220 the following branch. */
5221 while (dest_uid >= max_uid)
5223 dest = NEXT_INSN (dest);
5224 dest_uid = INSN_UID (dest);
5226 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
5231 /* Split condbranches that are out of range. Also add clobbers for
5232 scratch registers that are needed in far jumps.
5233 We do this before delay slot scheduling, so that it can take our
5234 newly created instructions into account. It also allows us to
5235 find branches with common targets more easily. */
5238 split_branches (rtx first)
5241 struct far_branch **uid_branch, *far_branch_list = 0;
5242 int max_uid = get_max_uid ();
5245 /* Find out which branches are out of range. */
5246 shorten_branches (first);
5248 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5249 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5251 for (insn = first; insn; insn = NEXT_INSN (insn))
5252 if (! INSN_P (insn))
5254 else if (INSN_DELETED_P (insn))
5256 /* Shorten_branches would split this instruction again,
5257 so transform it into a note. */
5258 SET_INSN_DELETED (insn);
5260 else if (GET_CODE (insn) == JUMP_INSN
5261 /* Don't mess with ADDR_DIFF_VEC */
5262 && (GET_CODE (PATTERN (insn)) == SET
5263 || GET_CODE (PATTERN (insn)) == RETURN))
5265 enum attr_type type = get_attr_type (insn);
5266 if (type == TYPE_CBRANCH)
5270 if (get_attr_length (insn) > 4)
5272 rtx src = SET_SRC (PATTERN (insn));
5273 rtx olabel = XEXP (XEXP (src, 1), 0);
5274 int addr = INSN_ADDRESSES (INSN_UID (insn));
5276 int dest_uid = get_dest_uid (olabel, max_uid);
5277 struct far_branch *bp = uid_branch[dest_uid];
5279 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5280 the label if the LABEL_NUSES count drops to zero. There is
5281 always a jump_optimize pass that sets these values, but it
5282 proceeds to delete unreferenced code, and then if not
5283 optimizing, to un-delete the deleted instructions, thus
5284 leaving labels with too low uses counts. */
5287 JUMP_LABEL (insn) = olabel;
5288 LABEL_NUSES (olabel)++;
5292 bp = (struct far_branch *) alloca (sizeof *bp);
5293 uid_branch[dest_uid] = bp;
5294 bp->prev = far_branch_list;
5295 far_branch_list = bp;
5297 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5298 LABEL_NUSES (bp->far_label)++;
5302 label = bp->near_label;
5303 if (! label && bp->address - addr >= CONDJUMP_MIN)
5305 rtx block = bp->insert_place;
5307 if (GET_CODE (PATTERN (block)) == RETURN)
5308 block = PREV_INSN (block);
5310 block = gen_block_redirect (block,
5312 label = emit_label_after (gen_label_rtx (),
5314 bp->near_label = label;
5316 else if (label && ! NEXT_INSN (label))
5318 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5319 bp->insert_place = insn;
5321 gen_far_branch (bp);
5325 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5327 bp->near_label = label = gen_label_rtx ();
5328 bp->insert_place = insn;
5331 ok = redirect_jump (insn, label, 0);
5336 /* get_attr_length (insn) == 2 */
5337 /* Check if we have a pattern where reorg wants to redirect
5338 the branch to a label from an unconditional branch that
5340 /* We can't use JUMP_LABEL here because it might be undefined
5341 when not optimizing. */
5342 /* A syntax error might cause beyond to be NULL_RTX. */
5344 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5348 && (GET_CODE (beyond) == JUMP_INSN
5349 || ((beyond = next_active_insn (beyond))
5350 && GET_CODE (beyond) == JUMP_INSN))
5351 && GET_CODE (PATTERN (beyond)) == SET
5352 && recog_memoized (beyond) == CODE_FOR_jump_compact
5354 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5355 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5357 gen_block_redirect (beyond,
5358 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5361 next = next_active_insn (insn);
5363 if ((GET_CODE (next) == JUMP_INSN
5364 || ((next = next_active_insn (next))
5365 && GET_CODE (next) == JUMP_INSN))
5366 && GET_CODE (PATTERN (next)) == SET
5367 && recog_memoized (next) == CODE_FOR_jump_compact
5369 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5370 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5372 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5374 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5376 int addr = INSN_ADDRESSES (INSN_UID (insn));
5379 struct far_branch *bp;
5381 if (type == TYPE_JUMP)
5383 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5384 dest_uid = get_dest_uid (far_label, max_uid);
5387 /* Parse errors can lead to labels outside
5389 if (! NEXT_INSN (far_label))
5394 JUMP_LABEL (insn) = far_label;
5395 LABEL_NUSES (far_label)++;
5397 redirect_jump (insn, NULL_RTX, 1);
5401 bp = uid_branch[dest_uid];
5404 bp = (struct far_branch *) alloca (sizeof *bp);
5405 uid_branch[dest_uid] = bp;
5406 bp->prev = far_branch_list;
5407 far_branch_list = bp;
5409 bp->far_label = far_label;
5411 LABEL_NUSES (far_label)++;
5413 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5414 if (addr - bp->address <= CONDJUMP_MAX)
5415 emit_label_after (bp->near_label, PREV_INSN (insn));
5418 gen_far_branch (bp);
5424 bp->insert_place = insn;
5426 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5428 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5431 /* Generate all pending far branches,
5432 and free our references to the far labels. */
5433 while (far_branch_list)
5435 if (far_branch_list->near_label
5436 && ! NEXT_INSN (far_branch_list->near_label))
5437 gen_far_branch (far_branch_list);
5439 && far_branch_list->far_label
5440 && ! --LABEL_NUSES (far_branch_list->far_label))
5441 delete_insn (far_branch_list->far_label);
5442 far_branch_list = far_branch_list->prev;
5445 /* Instruction length information is no longer valid due to the new
5446 instructions that have been generated. */
5447 init_insn_lengths ();
5450 /* Dump out instruction addresses, which is useful for debugging the
5451 constant pool table stuff.
5453 If relaxing, output the label and pseudo-ops used to link together
5454 calls and the instruction which set the registers. */
5456 /* ??? The addresses printed by this routine for insns are nonsense for
5457 insns which are inside of a sequence where none of the inner insns have
5458 variable length. This is because the second pass of shorten_branches
5459 does not bother to update them. */
5462 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5463 int noperands ATTRIBUTE_UNUSED)
5465 if (TARGET_DUMPISIZE)
5466 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5472 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
5477 pattern = PATTERN (insn);
5478 if (GET_CODE (pattern) == PARALLEL)
5479 pattern = XVECEXP (pattern, 0, 0);
5480 switch (GET_CODE (pattern))
5483 if (GET_CODE (SET_SRC (pattern)) != CALL
5484 && get_attr_type (insn) != TYPE_SFUNC)
5486 targetm.asm_out.internal_label
5487 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5490 /* else FALLTHROUGH */
5492 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5493 CODE_LABEL_NUMBER (XEXP (note, 0)));
5503 /* Dump out any constants accumulated in the final pass. These will
5507 output_jump_label_table (void)
5513 fprintf (asm_out_file, "\t.align 2\n");
5514 for (i = 0; i < pool_size; i++)
5516 pool_node *p = &pool_vector[i];
5518 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5519 CODE_LABEL_NUMBER (p->label));
5520 output_asm_insn (".long %O0", &p->value);
5528 /* A full frame looks like:
5532 [ if current_function_anonymous_args
5545 local-0 <- fp points here. */
5547 /* Number of bytes pushed for anonymous args, used to pass information
5548 between expand_prologue and expand_epilogue. */
5550 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
5551 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
5552 for an epilogue and a negative value means that it's for a sibcall
5553 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
5554 all the registers that are about to be restored, and hence dead. */
5557 output_stack_adjust (int size, rtx reg, int epilogue_p,
5558 HARD_REG_SET *live_regs_mask)
5560 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
5563 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
5565 /* This test is bogus, as output_stack_adjust is used to re-align the
5568 gcc_assert (!(size % align));
5571 if (CONST_OK_FOR_ADD (size))
5572 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
5573 /* Try to do it with two partial adjustments; however, we must make
5574 sure that the stack is properly aligned at all times, in case
5575 an interrupt occurs between the two partial adjustments. */
5576 else if (CONST_OK_FOR_ADD (size / 2 & -align)
5577 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
5579 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
5580 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
5586 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
5589 /* If TEMP is invalid, we could temporarily save a general
5590 register to MACL. However, there is currently no need
5591 to handle this case, so just die when we see it. */
5593 || current_function_interrupt
5594 || ! call_really_used_regs[temp] || fixed_regs[temp])
5596 if (temp < 0 && ! current_function_interrupt
5597 && (TARGET_SHMEDIA || epilogue_p >= 0))
5600 COPY_HARD_REG_SET (temps, call_used_reg_set);
5601 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
5605 if (crtl->return_rtx)
5607 enum machine_mode mode;
5608 mode = GET_MODE (crtl->return_rtx);
5609 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
5610 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
5612 for (i = 0; i < nreg; i++)
5613 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
5614 if (crtl->calls_eh_return)
5616 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
5617 for (i = 0; i <= 3; i++)
5618 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
5621 if (TARGET_SHMEDIA && epilogue_p < 0)
5622 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
5623 CLEAR_HARD_REG_BIT (temps, i);
5624 if (epilogue_p <= 0)
5626 for (i = FIRST_PARM_REG;
5627 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
5628 CLEAR_HARD_REG_BIT (temps, i);
5629 if (cfun->static_chain_decl != NULL)
5630 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
5632 temp = scavenge_reg (&temps);
5634 if (temp < 0 && live_regs_mask)
5638 COPY_HARD_REG_SET (temps, *live_regs_mask);
5639 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
5640 temp = scavenge_reg (&temps);
5644 rtx adj_reg, tmp_reg, mem;
5646 /* If we reached here, the most likely case is the (sibcall)
5647 epilogue for non SHmedia. Put a special push/pop sequence
5648 for such case as the last resort. This looks lengthy but
5649 would not be problem because it seems to be very
5652 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
5655 /* ??? There is still the slight possibility that r4 or
5656 r5 have been reserved as fixed registers or assigned
5657 as global registers, and they change during an
5658 interrupt. There are possible ways to handle this:
5660 - If we are adjusting the frame pointer (r14), we can do
5661 with a single temp register and an ordinary push / pop
5663 - Grab any call-used or call-saved registers (i.e. not
5664 fixed or globals) for the temps we need. We might
5665 also grab r14 if we are adjusting the stack pointer.
5666 If we can't find enough available registers, issue
5667 a diagnostic and die - the user must have reserved
5668 way too many registers.
5669 But since all this is rather unlikely to happen and
5670 would require extra testing, we just die if r4 / r5
5671 are not available. */
5672 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
5673 && !global_regs[4] && !global_regs[5]);
5675 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
5676 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
5677 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
5678 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
5679 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
5680 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5681 emit_move_insn (mem, tmp_reg);
5682 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
5683 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5684 emit_move_insn (mem, tmp_reg);
5685 emit_move_insn (reg, adj_reg);
5686 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5687 emit_move_insn (adj_reg, mem);
5688 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5689 emit_move_insn (tmp_reg, mem);
5690 /* Tell flow the insns that pop r4/r5 aren't dead. */
5695 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
5697 /* If SIZE is negative, subtract the positive value.
5698 This sometimes allows a constant pool entry to be shared
5699 between prologue and epilogue code. */
5702 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
5703 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
5707 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
5708 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
5711 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
5712 gen_rtx_SET (VOIDmode, reg,
5713 gen_rtx_PLUS (SImode, reg,
5723 RTX_FRAME_RELATED_P (x) = 1;
5727 /* Output RTL to push register RN onto the stack. */
5734 x = gen_push_fpul ();
5735 else if (rn == FPSCR_REG)
5736 x = gen_push_fpscr ();
5737 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5738 && FP_OR_XD_REGISTER_P (rn))
5740 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5742 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
5744 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5745 x = gen_push_e (gen_rtx_REG (SFmode, rn));
5747 x = gen_push (gen_rtx_REG (SImode, rn));
5750 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
5754 /* Output RTL to pop register RN from the stack. */
5761 x = gen_pop_fpul ();
5762 else if (rn == FPSCR_REG)
5763 x = gen_pop_fpscr ();
5764 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5765 && FP_OR_XD_REGISTER_P (rn))
5767 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5769 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
5771 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5772 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
5774 x = gen_pop (gen_rtx_REG (SImode, rn));
5777 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
5780 /* Generate code to push the regs specified in the mask. */
5783 push_regs (HARD_REG_SET *mask, int interrupt_handler)
5785 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
5788 /* Push PR last; this gives better latencies after the prologue, and
5789 candidates for the return delay slot when there are no general
5790 registers pushed. */
5791 for (; i < FIRST_PSEUDO_REGISTER; i++)
5793 /* If this is an interrupt handler, and the SZ bit varies,
5794 and we have to push any floating point register, we need
5795 to switch to the correct precision first. */
5796 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
5797 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
5799 HARD_REG_SET unsaved;
5802 COMPL_HARD_REG_SET (unsaved, *mask);
5803 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
5807 && (i != FPSCR_REG || ! skip_fpscr)
5808 && TEST_HARD_REG_BIT (*mask, i))
5810 /* If the ISR has RESBANK attribute assigned, don't push any of
5811 the following registers - R0-R14, MACH, MACL and GBR. */
5812 if (! (sh_cfun_resbank_handler_p ()
5813 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
5821 /* Push banked registers last to improve delay slot opportunities. */
5822 if (interrupt_handler)
5823 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
5824 if (TEST_HARD_REG_BIT (*mask, i))
5827 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
5828 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
5832 /* Calculate how much extra space is needed to save all callee-saved
5834 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5837 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
5840 int stack_space = 0;
5841 int interrupt_handler = sh_cfun_interrupt_handler_p ();
5843 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
5844 if ((! call_really_used_regs[reg] || interrupt_handler)
5845 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
5846 /* Leave space to save this target register on the stack,
5847 in case target register allocation wants to use it. */
5848 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5852 /* Decide whether we should reserve space for callee-save target registers,
5853 in case target register allocation wants to use them. REGS_SAVED is
5854 the space, in bytes, that is already required for register saves.
5855 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5858 shmedia_reserve_space_for_target_registers_p (int regs_saved,
5859 HARD_REG_SET *live_regs_mask)
5863 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
5866 /* Decide how much space to reserve for callee-save target registers
5867 in case target register allocation wants to use them.
5868 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5871 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
5873 if (shmedia_space_reserved_for_target_registers)
5874 return shmedia_target_regs_stack_space (live_regs_mask);
5879 /* Work out the registers which need to be saved, both as a mask and a
5880 count of saved words. Return the count.
5882 If doing a pragma interrupt function, then push all regs used by the
5883 function, and if we call another function (we can tell by looking at PR),
5884 make sure that all the regs it clobbers are safe too. */
5887 calc_live_regs (HARD_REG_SET *live_regs_mask)
5892 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
5893 bool nosave_low_regs;
5894 int pr_live, has_call;
5896 attrs = DECL_ATTRIBUTES (current_function_decl);
5897 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
5898 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
5899 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
5900 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
5902 CLEAR_HARD_REG_SET (*live_regs_mask);
5903 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
5904 && df_regs_ever_live_p (FPSCR_REG))
5905 target_flags &= ~MASK_FPU_SINGLE;
5906 /* If we can save a lot of saves by switching to double mode, do that. */
5907 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
5908 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
5909 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
5910 && (! call_really_used_regs[reg]
5911 || interrupt_handler)
5914 target_flags &= ~MASK_FPU_SINGLE;
5917 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
5918 knows how to use it. That means the pseudo originally allocated for
5919 the initial value can become the PR_MEDIA_REG hard register, as seen for
5920 execute/20010122-1.c:test9. */
5922 /* ??? this function is called from initial_elimination_offset, hence we
5923 can't use the result of sh_media_register_for_return here. */
5924 pr_live = sh_pr_n_sets ();
5927 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
5928 pr_live = (pr_initial
5929 ? (GET_CODE (pr_initial) != REG
5930 || REGNO (pr_initial) != (PR_REG))
5931 : df_regs_ever_live_p (PR_REG));
5932 /* For Shcompact, if not optimizing, we end up with a memory reference
5933 using the return address pointer for __builtin_return_address even
5934 though there is no actual need to put the PR register on the stack. */
5935 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
5937 /* Force PR to be live if the prologue has to call the SHmedia
5938 argument decoder or register saver. */
5939 if (TARGET_SHCOMPACT
5940 && ((crtl->args.info.call_cookie
5941 & ~ CALL_COOKIE_RET_TRAMP (1))
5942 || crtl->saves_all_registers))
5944 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
5945 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
5947 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
5950 ? (/* Need to save all the regs ever live. */
5951 (df_regs_ever_live_p (reg)
5952 || (call_really_used_regs[reg]
5953 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
5954 || reg == PIC_OFFSET_TABLE_REGNUM)
5956 || (TARGET_SHMEDIA && has_call
5957 && REGISTER_NATURAL_MODE (reg) == SImode
5958 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
5959 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
5960 && reg != RETURN_ADDRESS_POINTER_REGNUM
5961 && reg != T_REG && reg != GBR_REG
5962 /* Push fpscr only on targets which have FPU */
5963 && (reg != FPSCR_REG || TARGET_FPU_ANY))
5964 : (/* Only push those regs which are used and need to be saved. */
5967 && crtl->args.info.call_cookie
5968 && reg == PIC_OFFSET_TABLE_REGNUM)
5969 || (df_regs_ever_live_p (reg)
5970 && ((!call_really_used_regs[reg]
5971 && !(reg != PIC_OFFSET_TABLE_REGNUM
5972 && fixed_regs[reg] && call_used_regs[reg]))
5973 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
5974 || (crtl->calls_eh_return
5975 && (reg == EH_RETURN_DATA_REGNO (0)
5976 || reg == EH_RETURN_DATA_REGNO (1)
5977 || reg == EH_RETURN_DATA_REGNO (2)
5978 || reg == EH_RETURN_DATA_REGNO (3)))
5979 || ((reg == MACL_REG || reg == MACH_REG)
5980 && df_regs_ever_live_p (reg)
5981 && sh_cfun_attr_renesas_p ())
5984 SET_HARD_REG_BIT (*live_regs_mask, reg);
5985 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5987 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
5988 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
5990 if (FP_REGISTER_P (reg))
5992 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
5994 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
5995 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
5998 else if (XD_REGISTER_P (reg))
6000 /* Must switch to double mode to access these registers. */
6001 target_flags &= ~MASK_FPU_SINGLE;
6005 if (nosave_low_regs && reg == R8_REG)
6008 /* If we have a target register optimization pass after prologue / epilogue
6009 threading, we need to assume all target registers will be live even if
6011 if (flag_branch_target_load_optimize2
6012 && TARGET_SAVE_ALL_TARGET_REGS
6013 && shmedia_space_reserved_for_target_registers)
6014 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6015 if ((! call_really_used_regs[reg] || interrupt_handler)
6016 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6018 SET_HARD_REG_BIT (*live_regs_mask, reg);
6019 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6021 /* If this is an interrupt handler, we don't have any call-clobbered
6022 registers we can conveniently use for target register save/restore.
6023 Make sure we save at least one general purpose register when we need
6024 to save target registers. */
6025 if (interrupt_handler
6026 && hard_reg_set_intersect_p (*live_regs_mask,
6027 reg_class_contents[TARGET_REGS])
6028 && ! hard_reg_set_intersect_p (*live_regs_mask,
6029 reg_class_contents[GENERAL_REGS]))
6031 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6032 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6038 /* Code to generate prologue and epilogue sequences */
6040 /* PUSHED is the number of bytes that are being pushed on the
6041 stack for register saves. Return the frame size, padded
6042 appropriately so that the stack stays properly aligned. */
6043 static HOST_WIDE_INT
6044 rounded_frame_size (int pushed)
6046 HOST_WIDE_INT size = get_frame_size ();
6047 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6049 return ((size + pushed + align - 1) & -align) - pushed;
6052 /* Choose a call-clobbered target-branch register that remains
6053 unchanged along the whole function. We set it up as the return
6054 value in the prologue. */
6056 sh_media_register_for_return (void)
6061 if (! current_function_is_leaf)
6063 if (lookup_attribute ("interrupt_handler",
6064 DECL_ATTRIBUTES (current_function_decl)))
6066 if (sh_cfun_interrupt_handler_p ())
6069 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6071 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6072 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6078 /* The maximum registers we need to save are:
6079 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6080 - 32 floating point registers (for each pair, we save none,
6081 one single precision value, or a double precision value).
6082 - 8 target registers
6083 - add 1 entry for a delimiter. */
6084 #define MAX_SAVED_REGS (62+32+8)
6086 typedef struct save_entry_s
6095 /* There will be a delimiter entry with VOIDmode both at the start and the
6096 end of a filled in schedule. The end delimiter has the offset of the
6097 save with the smallest (i.e. most negative) offset. */
6098 typedef struct save_schedule_s
6100 save_entry entries[MAX_SAVED_REGS + 2];
6101 int temps[MAX_TEMPS+1];
6104 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6105 use reverse order. Returns the last entry written to (not counting
6106 the delimiter). OFFSET_BASE is a number to be added to all offset
6110 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6114 save_entry *entry = schedule->entries;
6118 if (! current_function_interrupt)
6119 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6120 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6121 && ! FUNCTION_ARG_REGNO_P (i)
6122 && i != FIRST_RET_REG
6123 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6124 && ! (crtl->calls_eh_return
6125 && (i == EH_RETURN_STACKADJ_REGNO
6126 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6127 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6128 schedule->temps[tmpx++] = i;
6130 entry->mode = VOIDmode;
6131 entry->offset = offset_base;
6133 /* We loop twice: first, we save 8-byte aligned registers in the
6134 higher addresses, that are known to be aligned. Then, we
6135 proceed to saving 32-bit registers that don't need 8-byte
6137 If this is an interrupt function, all registers that need saving
6138 need to be saved in full. moreover, we need to postpone saving
6139 target registers till we have saved some general purpose registers
6140 we can then use as scratch registers. */
6141 offset = offset_base;
6142 for (align = 1; align >= 0; align--)
6144 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6145 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6147 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6150 if (current_function_interrupt)
6152 if (TARGET_REGISTER_P (i))
6154 if (GENERAL_REGISTER_P (i))
6157 if (mode == SFmode && (i % 2) == 1
6158 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6159 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6166 /* If we're doing the aligned pass and this is not aligned,
6167 or we're doing the unaligned pass and this is aligned,
6169 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6173 if (current_function_interrupt
6174 && GENERAL_REGISTER_P (i)
6175 && tmpx < MAX_TEMPS)
6176 schedule->temps[tmpx++] = i;
6178 offset -= GET_MODE_SIZE (mode);
6181 entry->offset = offset;
6184 if (align && current_function_interrupt)
6185 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6186 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6188 offset -= GET_MODE_SIZE (DImode);
6190 entry->mode = DImode;
6191 entry->offset = offset;
6196 entry->mode = VOIDmode;
6197 entry->offset = offset;
6198 schedule->temps[tmpx] = -1;
6203 sh_expand_prologue (void)
6205 HARD_REG_SET live_regs_mask;
6208 int save_flags = target_flags;
6211 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6213 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6215 /* We have pretend args if we had an object sent partially in registers
6216 and partially on the stack, e.g. a large structure. */
6217 pretend_args = crtl->args.pretend_args_size;
6218 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6219 && (NPARM_REGS(SImode)
6220 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6222 output_stack_adjust (-pretend_args
6223 - crtl->args.info.stack_regs * 8,
6224 stack_pointer_rtx, 0, NULL);
6226 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6227 /* We're going to use the PIC register to load the address of the
6228 incoming-argument decoder and/or of the return trampoline from
6229 the GOT, so make sure the PIC register is preserved and
6231 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6233 if (TARGET_SHCOMPACT
6234 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6238 /* First, make all registers with incoming arguments that will
6239 be pushed onto the stack live, so that register renaming
6240 doesn't overwrite them. */
6241 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6242 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6243 >= NPARM_REGS (SImode) - reg)
6244 for (; reg < NPARM_REGS (SImode); reg++)
6245 emit_insn (gen_shcompact_preserve_incoming_args
6246 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6247 else if (CALL_COOKIE_INT_REG_GET
6248 (crtl->args.info.call_cookie, reg) == 1)
6249 emit_insn (gen_shcompact_preserve_incoming_args
6250 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6252 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6254 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6255 GEN_INT (crtl->args.info.call_cookie));
6256 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6257 gen_rtx_REG (SImode, R0_REG));
6259 else if (TARGET_SHMEDIA)
6261 int tr = sh_media_register_for_return ();
6264 emit_move_insn (gen_rtx_REG (DImode, tr),
6265 gen_rtx_REG (DImode, PR_MEDIA_REG));
6268 /* Emit the code for SETUP_VARARGS. */
6271 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6273 /* Push arg regs as if they'd been provided by caller in stack. */
6274 for (i = 0; i < NPARM_REGS(SImode); i++)
6276 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6279 if (i >= (NPARM_REGS(SImode)
6280 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6288 /* If we're supposed to switch stacks at function entry, do so now. */
6291 /* The argument specifies a variable holding the address of the
6292 stack the interrupt function should switch to/from at entry/exit. */
6294 = ggc_strdup (TREE_STRING_POINTER (TREE_VALUE (sp_switch_attr)));
6295 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6297 emit_insn (gen_sp_switch_1 (sp_switch));
6300 d = calc_live_regs (&live_regs_mask);
6301 /* ??? Maybe we could save some switching if we can move a mode switch
6302 that already happens to be at the function start into the prologue. */
6303 if (target_flags != save_flags && ! current_function_interrupt)
6304 emit_insn (gen_toggle_sz ());
6308 int offset_base, offset;
6310 int offset_in_r0 = -1;
6312 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6313 int total_size, save_size;
6314 save_schedule schedule;
6318 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6319 && ! current_function_interrupt)
6320 r0 = gen_rtx_REG (Pmode, R0_REG);
6322 /* D is the actual number of bytes that we need for saving registers,
6323 however, in initial_elimination_offset we have committed to using
6324 an additional TREGS_SPACE amount of bytes - in order to keep both
6325 addresses to arguments supplied by the caller and local variables
6326 valid, we must keep this gap. Place it between the incoming
6327 arguments and the actually saved registers in a bid to optimize
6328 locality of reference. */
6329 total_size = d + tregs_space;
6330 total_size += rounded_frame_size (total_size);
6331 save_size = total_size - rounded_frame_size (d);
6332 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6333 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6334 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6336 /* If adjusting the stack in a single step costs nothing extra, do so.
6337 I.e. either if a single addi is enough, or we need a movi anyway,
6338 and we don't exceed the maximum offset range (the test for the
6339 latter is conservative for simplicity). */
6341 && (CONST_OK_FOR_I10 (-total_size)
6342 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6343 && total_size <= 2044)))
6344 d_rounding = total_size - save_size;
6346 offset_base = d + d_rounding;
6348 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6351 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6352 tmp_pnt = schedule.temps;
6353 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6355 enum machine_mode mode = (enum machine_mode) entry->mode;
6356 unsigned int reg = entry->reg;
6357 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6360 offset = entry->offset;
6362 reg_rtx = gen_rtx_REG (mode, reg);
6364 mem_rtx = gen_frame_mem (mode,
6365 gen_rtx_PLUS (Pmode,
6369 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6375 if (HAVE_PRE_DECREMENT
6376 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6377 || mem_rtx == NULL_RTX
6378 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6380 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6382 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
6387 offset += GET_MODE_SIZE (mode);
6391 if (mem_rtx != NULL_RTX)
6394 if (offset_in_r0 == -1)
6396 emit_move_insn (r0, GEN_INT (offset));
6397 offset_in_r0 = offset;
6399 else if (offset != offset_in_r0)
6404 GEN_INT (offset - offset_in_r0)));
6405 offset_in_r0 += offset - offset_in_r0;
6408 if (pre_dec != NULL_RTX)
6414 (Pmode, r0, stack_pointer_rtx));
6418 offset -= GET_MODE_SIZE (mode);
6419 offset_in_r0 -= GET_MODE_SIZE (mode);
6424 mem_rtx = gen_frame_mem (mode, r0);
6426 mem_rtx = gen_frame_mem (mode,
6427 gen_rtx_PLUS (Pmode,
6431 /* We must not use an r0-based address for target-branch
6432 registers or for special registers without pre-dec
6433 memory addresses, since we store their values in r0
6435 gcc_assert (!TARGET_REGISTER_P (reg)
6436 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6437 || mem_rtx == pre_dec));
6440 orig_reg_rtx = reg_rtx;
6441 if (TARGET_REGISTER_P (reg)
6442 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6443 && mem_rtx != pre_dec))
6445 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6447 emit_move_insn (tmp_reg, reg_rtx);
6449 if (REGNO (tmp_reg) == R0_REG)
6453 gcc_assert (!refers_to_regno_p
6454 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6457 if (*++tmp_pnt <= 0)
6458 tmp_pnt = schedule.temps;
6465 /* Mark as interesting for dwarf cfi generator */
6466 insn = emit_move_insn (mem_rtx, reg_rtx);
6467 RTX_FRAME_RELATED_P (insn) = 1;
6468 /* If we use an intermediate register for the save, we can't
6469 describe this exactly in cfi as a copy of the to-be-saved
6470 register into the temporary register and then the temporary
6471 register on the stack, because the temporary register can
6472 have a different natural size than the to-be-saved register.
6473 Thus, we gloss over the intermediate copy and pretend we do
6474 a direct save from the to-be-saved register. */
6475 if (REGNO (reg_rtx) != reg)
6479 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6480 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6483 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6485 rtx reg_rtx = gen_rtx_REG (mode, reg);
6487 rtx mem_rtx = gen_frame_mem (mode,
6488 gen_rtx_PLUS (Pmode,
6492 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6493 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6498 gcc_assert (entry->offset == d_rounding);
6501 push_regs (&live_regs_mask, current_function_interrupt);
6503 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
6504 emit_insn (gen_GOTaddr2picreg ());
6506 if (SHMEDIA_REGS_STACK_ADJUST ())
6508 /* This must NOT go through the PLT, otherwise mach and macl
6509 may be clobbered. */
6510 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6512 ? "__GCC_push_shmedia_regs"
6513 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
6514 emit_insn (gen_shmedia_save_restore_regs_compact
6515 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
6518 if (target_flags != save_flags && ! current_function_interrupt)
6519 emit_insn (gen_toggle_sz ());
6521 target_flags = save_flags;
6523 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
6524 stack_pointer_rtx, 0, NULL);
6526 if (frame_pointer_needed)
6527 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
6529 if (TARGET_SHCOMPACT
6530 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6532 /* This must NOT go through the PLT, otherwise mach and macl
6533 may be clobbered. */
6534 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6535 "__GCC_shcompact_incoming_args", SFUNC_GOT);
6536 emit_insn (gen_shcompact_incoming_args ());
6541 sh_expand_epilogue (bool sibcall_p)
6543 HARD_REG_SET live_regs_mask;
6547 int save_flags = target_flags;
6548 int frame_size, save_size;
6549 int fpscr_deferred = 0;
6550 int e = sibcall_p ? -1 : 1;
6552 d = calc_live_regs (&live_regs_mask);
6555 frame_size = rounded_frame_size (d);
6559 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6561 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
6562 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6563 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
6565 total_size = d + tregs_space;
6566 total_size += rounded_frame_size (total_size);
6567 save_size = total_size - frame_size;
6569 /* If adjusting the stack in a single step costs nothing extra, do so.
6570 I.e. either if a single addi is enough, or we need a movi anyway,
6571 and we don't exceed the maximum offset range (the test for the
6572 latter is conservative for simplicity). */
6574 && ! frame_pointer_needed
6575 && (CONST_OK_FOR_I10 (total_size)
6576 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
6577 && total_size <= 2044)))
6578 d_rounding = frame_size;
6580 frame_size -= d_rounding;
6583 if (frame_pointer_needed)
6585 /* We must avoid scheduling the epilogue with previous basic blocks
6586 when exception handling is enabled. See PR/18032. */
6587 if (flag_exceptions)
6588 emit_insn (gen_blockage ());
6589 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
6592 /* We must avoid moving the stack pointer adjustment past code
6593 which reads from the local frame, else an interrupt could
6594 occur after the SP adjustment and clobber data in the local
6596 emit_insn (gen_blockage ());
6597 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
6599 else if (frame_size)
6601 /* We must avoid moving the stack pointer adjustment past code
6602 which reads from the local frame, else an interrupt could
6603 occur after the SP adjustment and clobber data in the local
6605 emit_insn (gen_blockage ());
6606 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
6609 if (SHMEDIA_REGS_STACK_ADJUST ())
6611 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6613 ? "__GCC_pop_shmedia_regs"
6614 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
6615 /* This must NOT go through the PLT, otherwise mach and macl
6616 may be clobbered. */
6617 emit_insn (gen_shmedia_save_restore_regs_compact
6618 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
6621 /* Pop all the registers. */
6623 if (target_flags != save_flags && ! current_function_interrupt)
6624 emit_insn (gen_toggle_sz ());
6627 int offset_base, offset;
6628 int offset_in_r0 = -1;
6630 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
6631 save_schedule schedule;
6635 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
6636 offset_base = -entry[1].offset + d_rounding;
6637 tmp_pnt = schedule.temps;
6638 for (; entry->mode != VOIDmode; entry--)
6640 enum machine_mode mode = (enum machine_mode) entry->mode;
6641 int reg = entry->reg;
6642 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
6644 offset = offset_base + entry->offset;
6645 reg_rtx = gen_rtx_REG (mode, reg);
6647 mem_rtx = gen_frame_mem (mode,
6648 gen_rtx_PLUS (Pmode,
6652 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6655 if (HAVE_POST_INCREMENT
6656 && (offset == offset_in_r0
6657 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
6658 && mem_rtx == NULL_RTX)
6659 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6661 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
6663 if (!memory_address_p (mode, XEXP (post_inc, 0)))
6664 post_inc = NULL_RTX;
6669 if (mem_rtx != NULL_RTX)
6672 if (offset_in_r0 == -1)
6674 emit_move_insn (r0, GEN_INT (offset));
6675 offset_in_r0 = offset;
6677 else if (offset != offset_in_r0)
6682 GEN_INT (offset - offset_in_r0)));
6683 offset_in_r0 += offset - offset_in_r0;
6686 if (post_inc != NULL_RTX)
6692 (Pmode, r0, stack_pointer_rtx));
6698 offset_in_r0 += GET_MODE_SIZE (mode);
6701 mem_rtx = gen_frame_mem (mode, r0);
6703 mem_rtx = gen_frame_mem (mode,
6704 gen_rtx_PLUS (Pmode,
6708 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6709 || mem_rtx == post_inc);
6712 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6713 && mem_rtx != post_inc)
6715 insn = emit_move_insn (r0, mem_rtx);
6718 else if (TARGET_REGISTER_P (reg))
6720 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
6722 /* Give the scheduler a bit of freedom by using up to
6723 MAX_TEMPS registers in a round-robin fashion. */
6724 insn = emit_move_insn (tmp_reg, mem_rtx);
6727 tmp_pnt = schedule.temps;
6730 insn = emit_move_insn (reg_rtx, mem_rtx);
6733 gcc_assert (entry->offset + offset_base == d + d_rounding);
6735 else /* ! TARGET_SH5 */
6740 /* For an ISR with RESBANK attribute assigned, don't pop PR
6742 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
6743 && !sh_cfun_resbank_handler_p ())
6745 if (!frame_pointer_needed)
6746 emit_insn (gen_blockage ());
6750 /* Banked registers are poped first to avoid being scheduled in the
6751 delay slot. RTE switches banks before the ds instruction. */
6752 if (current_function_interrupt)
6754 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6755 if (TEST_HARD_REG_BIT (live_regs_mask, i))
6756 pop (LAST_BANKED_REG - i);
6758 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
6761 last_reg = FIRST_PSEUDO_REGISTER;
6763 for (i = 0; i < last_reg; i++)
6765 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
6767 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
6768 && hard_reg_set_intersect_p (live_regs_mask,
6769 reg_class_contents[DF_REGS]))
6771 /* For an ISR with RESBANK attribute assigned, don't pop
6772 following registers, R0-R14, MACH, MACL and GBR. */
6773 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
6774 && ! (sh_cfun_resbank_handler_p ()
6775 && ((j >= FIRST_GENERAL_REG
6776 && j < LAST_GENERAL_REG)
6782 if (j == FIRST_FP_REG && fpscr_deferred)
6786 if (target_flags != save_flags && ! current_function_interrupt)
6787 emit_insn (gen_toggle_sz ());
6788 target_flags = save_flags;
6790 output_stack_adjust (crtl->args.pretend_args_size
6791 + save_size + d_rounding
6792 + crtl->args.info.stack_regs * 8,
6793 stack_pointer_rtx, e, NULL);
6795 if (crtl->calls_eh_return)
6796 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
6797 EH_RETURN_STACKADJ_RTX));
6799 /* Switch back to the normal stack if necessary. */
6800 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
6801 emit_insn (gen_sp_switch_2 ());
6803 /* Tell flow the insn that pops PR isn't dead. */
6804 /* PR_REG will never be live in SHmedia mode, and we don't need to
6805 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
6806 by the return pattern. */
6807 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
6808 emit_use (gen_rtx_REG (SImode, PR_REG));
6811 static int sh_need_epilogue_known = 0;
6814 sh_need_epilogue (void)
6816 if (! sh_need_epilogue_known)
6821 sh_expand_epilogue (0);
6822 epilogue = get_insns ();
6824 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
6826 return sh_need_epilogue_known > 0;
6829 /* Emit code to change the current function's return address to RA.
6830 TEMP is available as a scratch register, if needed. */
6833 sh_set_return_address (rtx ra, rtx tmp)
6835 HARD_REG_SET live_regs_mask;
6837 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
6840 d = calc_live_regs (&live_regs_mask);
6842 /* If pr_reg isn't life, we can set it (or the register given in
6843 sh_media_register_for_return) directly. */
6844 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
6850 int rr_regno = sh_media_register_for_return ();
6855 rr = gen_rtx_REG (DImode, rr_regno);
6858 rr = gen_rtx_REG (SImode, pr_reg);
6860 emit_insn (GEN_MOV (rr, ra));
6861 /* Tell flow the register for return isn't dead. */
6869 save_schedule schedule;
6872 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
6873 offset = entry[1].offset;
6874 for (; entry->mode != VOIDmode; entry--)
6875 if (entry->reg == pr_reg)
6878 /* We can't find pr register. */
6882 offset = entry->offset - offset;
6883 pr_offset = (rounded_frame_size (d) + offset
6884 + SHMEDIA_REGS_STACK_ADJUST ());
6887 pr_offset = rounded_frame_size (d);
6889 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
6890 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
6892 tmp = gen_frame_mem (Pmode, tmp);
6893 emit_insn (GEN_MOV (tmp, ra));
6896 /* Clear variables at function end. */
6899 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6900 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6902 sh_need_epilogue_known = 0;
6906 sh_builtin_saveregs (void)
6908 /* First unnamed integer register. */
6909 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
6910 /* Number of integer registers we need to save. */
6911 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
6912 /* First unnamed SFmode float reg */
6913 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
6914 /* Number of SFmode float regs to save. */
6915 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
6918 alias_set_type alias_set;
6924 int pushregs = n_intregs;
6926 while (pushregs < NPARM_REGS (SImode) - 1
6927 && (CALL_COOKIE_INT_REG_GET
6928 (crtl->args.info.call_cookie,
6929 NPARM_REGS (SImode) - pushregs)
6932 crtl->args.info.call_cookie
6933 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
6938 if (pushregs == NPARM_REGS (SImode))
6939 crtl->args.info.call_cookie
6940 |= (CALL_COOKIE_INT_REG (0, 1)
6941 | CALL_COOKIE_STACKSEQ (pushregs - 1));
6943 crtl->args.info.call_cookie
6944 |= CALL_COOKIE_STACKSEQ (pushregs);
6946 crtl->args.pretend_args_size += 8 * n_intregs;
6948 if (TARGET_SHCOMPACT)
6952 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
6954 error ("__builtin_saveregs not supported by this subtarget");
6961 /* Allocate block of memory for the regs. */
6962 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
6963 Or can assign_stack_local accept a 0 SIZE argument? */
6964 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
6967 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
6968 else if (n_floatregs & 1)
6972 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
6973 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
6974 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
6975 regbuf = change_address (regbuf, BLKmode, addr);
6977 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
6981 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
6982 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
6983 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
6984 emit_insn (gen_andsi3 (addr, addr, mask));
6985 regbuf = change_address (regbuf, BLKmode, addr);
6988 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
6989 alias_set = get_varargs_alias_set ();
6990 set_mem_alias_set (regbuf, alias_set);
6993 This is optimized to only save the regs that are necessary. Explicitly
6994 named args need not be saved. */
6996 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
6997 adjust_address (regbuf, BLKmode,
6998 n_floatregs * UNITS_PER_WORD),
7002 /* Return the address of the regbuf. */
7003 return XEXP (regbuf, 0);
7006 This is optimized to only save the regs that are necessary. Explicitly
7007 named args need not be saved.
7008 We explicitly build a pointer to the buffer because it halves the insn
7009 count when not optimizing (otherwise the pointer is built for each reg
7011 We emit the moves in reverse order so that we can use predecrement. */
7013 fpregs = copy_to_mode_reg (Pmode,
7014 plus_constant (XEXP (regbuf, 0),
7015 n_floatregs * UNITS_PER_WORD));
7016 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7019 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7021 emit_insn (gen_addsi3 (fpregs, fpregs,
7022 GEN_INT (-2 * UNITS_PER_WORD)));
7023 mem = change_address (regbuf, DFmode, fpregs);
7024 emit_move_insn (mem,
7025 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7027 regno = first_floatreg;
7030 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7031 mem = change_address (regbuf, SFmode, fpregs);
7032 emit_move_insn (mem,
7033 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7034 - (TARGET_LITTLE_ENDIAN != 0)));
7038 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7042 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7043 mem = change_address (regbuf, SFmode, fpregs);
7044 emit_move_insn (mem,
7045 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7048 /* Return the address of the regbuf. */
7049 return XEXP (regbuf, 0);
7052 /* Define the `__builtin_va_list' type for the ABI. */
7055 sh_build_builtin_va_list (void)
7057 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7060 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7061 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7062 return ptr_type_node;
7064 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7066 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
7068 f_next_o_limit = build_decl (FIELD_DECL,
7069 get_identifier ("__va_next_o_limit"),
7071 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
7073 f_next_fp_limit = build_decl (FIELD_DECL,
7074 get_identifier ("__va_next_fp_limit"),
7076 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
7079 DECL_FIELD_CONTEXT (f_next_o) = record;
7080 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7081 DECL_FIELD_CONTEXT (f_next_fp) = record;
7082 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7083 DECL_FIELD_CONTEXT (f_next_stack) = record;
7085 TYPE_FIELDS (record) = f_next_o;
7086 TREE_CHAIN (f_next_o) = f_next_o_limit;
7087 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7088 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7089 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7091 layout_type (record);
7096 /* Implement `va_start' for varargs and stdarg. */
7099 sh_va_start (tree valist, rtx nextarg)
7101 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7102 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7108 expand_builtin_saveregs ();
7109 std_expand_builtin_va_start (valist, nextarg);
7113 if ((! TARGET_SH2E && ! TARGET_SH4)
7114 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7116 std_expand_builtin_va_start (valist, nextarg);
7120 f_next_o = TYPE_FIELDS (va_list_type_node);
7121 f_next_o_limit = TREE_CHAIN (f_next_o);
7122 f_next_fp = TREE_CHAIN (f_next_o_limit);
7123 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7124 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7126 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7128 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7129 valist, f_next_o_limit, NULL_TREE);
7130 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7132 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7133 valist, f_next_fp_limit, NULL_TREE);
7134 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7135 valist, f_next_stack, NULL_TREE);
7137 /* Call __builtin_saveregs. */
7138 u = make_tree (sizetype, expand_builtin_saveregs ());
7139 u = fold_convert (ptr_type_node, u);
7140 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7141 TREE_SIDE_EFFECTS (t) = 1;
7142 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7144 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7149 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7150 size_int (UNITS_PER_WORD * nfp));
7151 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7152 TREE_SIDE_EFFECTS (t) = 1;
7153 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7155 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7156 TREE_SIDE_EFFECTS (t) = 1;
7157 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7159 nint = crtl->args.info.arg_count[SH_ARG_INT];
7164 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7165 size_int (UNITS_PER_WORD * nint));
7166 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7167 TREE_SIDE_EFFECTS (t) = 1;
7168 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7170 u = make_tree (ptr_type_node, nextarg);
7171 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7172 TREE_SIDE_EFFECTS (t) = 1;
7173 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7176 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7177 member, return it. */
7179 find_sole_member (tree type)
7181 tree field, member = NULL_TREE;
7183 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7185 if (TREE_CODE (field) != FIELD_DECL)
7187 if (!DECL_SIZE (field))
7189 if (integer_zerop (DECL_SIZE (field)))
7197 /* Implement `va_arg'. */
7200 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7201 gimple_seq *post_p ATTRIBUTE_UNUSED)
7203 HOST_WIDE_INT size, rsize;
7204 tree tmp, pptr_type_node;
7205 tree addr, lab_over = NULL, result = NULL;
7206 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7210 type = build_pointer_type (type);
7212 size = int_size_in_bytes (type);
7213 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7214 pptr_type_node = build_pointer_type (ptr_type_node);
7216 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7217 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7219 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7220 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7225 f_next_o = TYPE_FIELDS (va_list_type_node);
7226 f_next_o_limit = TREE_CHAIN (f_next_o);
7227 f_next_fp = TREE_CHAIN (f_next_o_limit);
7228 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7229 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7231 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7233 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7234 valist, f_next_o_limit, NULL_TREE);
7235 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7236 valist, f_next_fp, NULL_TREE);
7237 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7238 valist, f_next_fp_limit, NULL_TREE);
7239 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7240 valist, f_next_stack, NULL_TREE);
7242 /* Structures with a single member with a distinct mode are passed
7243 like their member. This is relevant if the latter has a REAL_TYPE
7244 or COMPLEX_TYPE type. */
7246 while (TREE_CODE (eff_type) == RECORD_TYPE
7247 && (member = find_sole_member (eff_type))
7248 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7249 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7250 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7252 tree field_type = TREE_TYPE (member);
7254 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7255 eff_type = field_type;
7258 gcc_assert ((TYPE_ALIGN (eff_type)
7259 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7260 || (TYPE_ALIGN (eff_type)
7261 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7266 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7268 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7269 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7270 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7275 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7278 addr = create_tmp_var (pptr_type_node, NULL);
7279 lab_false = create_artificial_label ();
7280 lab_over = create_artificial_label ();
7282 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7286 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7288 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7290 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7291 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7293 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7294 tmp = next_fp_limit;
7295 if (size > 4 && !is_double)
7296 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
7297 unshare_expr (tmp), size_int (4 - size));
7298 tmp = build2 (GE_EXPR, boolean_type_node,
7299 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7300 cmp = build3 (COND_EXPR, void_type_node, tmp,
7301 build1 (GOTO_EXPR, void_type_node,
7302 unshare_expr (lab_false)), NULL_TREE);
7304 gimplify_and_add (cmp, pre_p);
7306 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7307 || (is_double || size == 16))
7309 tmp = fold_convert (sizetype, next_fp_tmp);
7310 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7311 size_int (UNITS_PER_WORD));
7312 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7313 unshare_expr (next_fp_tmp), tmp);
7314 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7317 gimplify_and_add (cmp, pre_p);
7319 #ifdef FUNCTION_ARG_SCmode_WART
7320 if (TYPE_MODE (eff_type) == SCmode
7321 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7323 tree subtype = TREE_TYPE (eff_type);
7327 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7328 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7331 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7332 real = get_initialized_tmp_var (real, pre_p, NULL);
7334 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7335 if (type != eff_type)
7336 result = build1 (VIEW_CONVERT_EXPR, type, result);
7337 result = get_initialized_tmp_var (result, pre_p, NULL);
7339 #endif /* FUNCTION_ARG_SCmode_WART */
7341 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7342 gimplify_and_add (tmp, pre_p);
7344 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7345 gimplify_and_add (tmp, pre_p);
7347 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7348 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7349 gimplify_assign (unshare_expr (next_fp_tmp),
7350 unshare_expr (valist), pre_p);
7352 gimplify_assign (unshare_expr (valist),
7353 unshare_expr (next_fp_tmp), post_p);
7354 valist = next_fp_tmp;
7358 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7359 unshare_expr (next_o), size_int (rsize));
7360 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7361 unshare_expr (next_o_limit));
7362 tmp = build3 (COND_EXPR, void_type_node, tmp,
7363 build1 (GOTO_EXPR, void_type_node,
7364 unshare_expr (lab_false)),
7366 gimplify_and_add (tmp, pre_p);
7368 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7369 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7371 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7372 gimplify_and_add (tmp, pre_p);
7374 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7375 gimplify_and_add (tmp, pre_p);
7377 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7378 gimplify_assign (unshare_expr (next_o),
7379 unshare_expr (next_o_limit), pre_p);
7381 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7382 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7387 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7388 gimplify_and_add (tmp, pre_p);
7392 /* ??? In va-sh.h, there had been code to make values larger than
7393 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7395 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7398 gimplify_assign (result, tmp, pre_p);
7400 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7401 gimplify_and_add (tmp, pre_p);
7407 result = build_va_arg_indirect_ref (result);
7412 /* 64 bit floating points memory transfers are paired single precision loads
7413 or store. So DWARF information needs fixing in little endian (unless
7414 PR=SZ=1 in FPSCR). */
7416 sh_dwarf_register_span (rtx reg)
7418 unsigned regno = REGNO (reg);
7420 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
7424 gen_rtx_PARALLEL (VOIDmode,
7426 gen_rtx_REG (SFmode,
7427 DBX_REGISTER_NUMBER (regno+1)),
7428 gen_rtx_REG (SFmode,
7429 DBX_REGISTER_NUMBER (regno))));
7433 sh_promote_prototypes (const_tree type)
7439 return ! sh_attr_renesas_p (type);
7442 /* Whether an argument must be passed by reference. On SHcompact, we
7443 pretend arguments wider than 32-bits that would have been passed in
7444 registers are passed by reference, so that an SHmedia trampoline
7445 loads them into the full 64-bits registers. */
7448 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7449 const_tree type, bool named)
7451 unsigned HOST_WIDE_INT size;
7454 size = int_size_in_bytes (type);
7456 size = GET_MODE_SIZE (mode);
7458 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7460 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7461 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7462 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7464 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7465 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7472 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7473 const_tree type, bool named)
7475 if (targetm.calls.must_pass_in_stack (mode, type))
7478 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7479 wants to know about pass-by-reference semantics for incoming
7484 if (TARGET_SHCOMPACT)
7486 cum->byref = shcompact_byref (cum, mode, type, named);
7487 return cum->byref != 0;
7494 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7495 const_tree type, bool named ATTRIBUTE_UNUSED)
7497 /* ??? How can it possibly be correct to return true only on the
7498 caller side of the equation? Is there someplace else in the
7499 sh backend that's magically producing the copies? */
7500 return (cum->outgoing
7501 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7502 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7506 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7507 tree type, bool named ATTRIBUTE_UNUSED)
7512 && PASS_IN_REG_P (*cum, mode, type)
7513 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7514 && (ROUND_REG (*cum, mode)
7516 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7517 : ROUND_ADVANCE (int_size_in_bytes (type)))
7518 > NPARM_REGS (mode)))
7519 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
7521 else if (!TARGET_SHCOMPACT
7522 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7523 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
7525 return words * UNITS_PER_WORD;
7529 /* Define where to put the arguments to a function.
7530 Value is zero to push the argument on the stack,
7531 or a hard register in which to store the argument.
7533 MODE is the argument's machine mode.
7534 TYPE is the data type of the argument (as a tree).
7535 This is null for libcalls where that information may
7537 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7538 the preceding args and about the function being called.
7539 NAMED is nonzero if this argument is a named parameter
7540 (otherwise it is an extra parameter matching an ellipsis).
7542 On SH the first args are normally in registers
7543 and the rest are pushed. Any arg that starts within the first
7544 NPARM_REGS words is at least partially passed in a register unless
7545 its data type forbids. */
7549 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7550 tree type, int named)
7552 if (! TARGET_SH5 && mode == VOIDmode)
7553 return GEN_INT (ca->renesas_abi ? 1 : 0);
7556 && PASS_IN_REG_P (*ca, mode, type)
7557 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
7561 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
7562 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
7564 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
7565 gen_rtx_REG (SFmode,
7567 + (ROUND_REG (*ca, mode) ^ 1)),
7569 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
7570 gen_rtx_REG (SFmode,
7572 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
7574 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
7577 /* If the alignment of a DF value causes an SF register to be
7578 skipped, we will use that skipped register for the next SF
7580 if ((TARGET_HITACHI || ca->renesas_abi)
7581 && ca->free_single_fp_reg
7583 return gen_rtx_REG (mode, ca->free_single_fp_reg);
7585 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
7586 ^ (mode == SFmode && TARGET_SH4
7587 && TARGET_LITTLE_ENDIAN != 0
7588 && ! TARGET_HITACHI && ! ca->renesas_abi);
7589 return gen_rtx_REG (mode, regno);
7595 if (mode == VOIDmode && TARGET_SHCOMPACT)
7596 return GEN_INT (ca->call_cookie);
7598 /* The following test assumes unnamed arguments are promoted to
7600 if (mode == SFmode && ca->free_single_fp_reg)
7601 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
7603 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
7604 && (named || ! ca->prototype_p)
7605 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
7607 if (! ca->prototype_p && TARGET_SHMEDIA)
7608 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
7610 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
7612 + ca->arg_count[(int) SH_ARG_FLOAT]);
7615 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
7616 && (! TARGET_SHCOMPACT
7617 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
7618 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
7621 return gen_rtx_REG (mode, (FIRST_PARM_REG
7622 + ca->arg_count[(int) SH_ARG_INT]));
7631 /* Update the data in CUM to advance over an argument
7632 of mode MODE and data type TYPE.
7633 (TYPE is null for libcalls where that information may not be
7637 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7638 tree type, int named)
7642 else if (TARGET_SH5)
7644 tree type2 = (ca->byref && type
7647 enum machine_mode mode2 = (ca->byref && type
7650 int dwords = ((ca->byref
7653 ? int_size_in_bytes (type2)
7654 : GET_MODE_SIZE (mode2)) + 7) / 8;
7655 int numregs = MIN (dwords, NPARM_REGS (SImode)
7656 - ca->arg_count[(int) SH_ARG_INT]);
7660 ca->arg_count[(int) SH_ARG_INT] += numregs;
7661 if (TARGET_SHCOMPACT
7662 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
7665 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7667 /* N.B. We want this also for outgoing. */
7668 ca->stack_regs += numregs;
7673 ca->stack_regs += numregs;
7674 ca->byref_regs += numregs;
7678 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7682 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7685 else if (dwords > numregs)
7687 int pushregs = numregs;
7689 if (TARGET_SHCOMPACT)
7690 ca->stack_regs += numregs;
7691 while (pushregs < NPARM_REGS (SImode) - 1
7692 && (CALL_COOKIE_INT_REG_GET
7694 NPARM_REGS (SImode) - pushregs)
7698 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7702 if (numregs == NPARM_REGS (SImode))
7704 |= CALL_COOKIE_INT_REG (0, 1)
7705 | CALL_COOKIE_STACKSEQ (numregs - 1);
7708 |= CALL_COOKIE_STACKSEQ (numregs);
7711 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
7712 && (named || ! ca->prototype_p))
7714 if (mode2 == SFmode && ca->free_single_fp_reg)
7715 ca->free_single_fp_reg = 0;
7716 else if (ca->arg_count[(int) SH_ARG_FLOAT]
7717 < NPARM_REGS (SFmode))
7720 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
7722 - ca->arg_count[(int) SH_ARG_FLOAT]);
7724 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
7726 if (TARGET_SHCOMPACT && ! ca->prototype_p)
7728 if (ca->outgoing && numregs > 0)
7732 |= (CALL_COOKIE_INT_REG
7733 (ca->arg_count[(int) SH_ARG_INT]
7734 - numregs + ((numfpregs - 2) / 2),
7735 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
7738 while (numfpregs -= 2);
7740 else if (mode2 == SFmode && (named)
7741 && (ca->arg_count[(int) SH_ARG_FLOAT]
7742 < NPARM_REGS (SFmode)))
7743 ca->free_single_fp_reg
7744 = FIRST_FP_PARM_REG - numfpregs
7745 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
7751 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
7753 /* Note that we've used the skipped register. */
7754 if (mode == SFmode && ca->free_single_fp_reg)
7756 ca->free_single_fp_reg = 0;
7759 /* When we have a DF after an SF, there's an SF register that get
7760 skipped in order to align the DF value. We note this skipped
7761 register, because the next SF value will use it, and not the
7762 SF that follows the DF. */
7764 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
7766 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
7767 + BASE_ARG_REG (mode));
7771 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
7772 || PASS_IN_REG_P (*ca, mode, type))
7773 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
7774 = (ROUND_REG (*ca, mode)
7776 ? ROUND_ADVANCE (int_size_in_bytes (type))
7777 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
7780 /* The Renesas calling convention doesn't quite fit into this scheme since
7781 the address is passed like an invisible argument, but one that is always
7782 passed in memory. */
7784 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
7786 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7788 return gen_rtx_REG (Pmode, 2);
7791 /* Worker function for TARGET_RETURN_IN_MEMORY. */
7794 sh_return_in_memory (const_tree type, const_tree fndecl)
7798 if (TYPE_MODE (type) == BLKmode)
7799 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
7801 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
7805 return (TYPE_MODE (type) == BLKmode
7806 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7807 && TREE_CODE (type) == RECORD_TYPE));
7811 /* We actually emit the code in sh_expand_prologue. We used to use
7812 a static variable to flag that we need to emit this code, but that
7813 doesn't when inlining, when functions are deferred and then emitted
7814 later. Fortunately, we already have two flags that are part of struct
7815 function that tell if a function uses varargs or stdarg. */
7817 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
7818 enum machine_mode mode,
7820 int *pretend_arg_size,
7821 int second_time ATTRIBUTE_UNUSED)
7823 gcc_assert (cfun->stdarg);
7824 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
7826 int named_parm_regs, anon_parm_regs;
7828 named_parm_regs = (ROUND_REG (*ca, mode)
7830 ? ROUND_ADVANCE (int_size_in_bytes (type))
7831 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
7832 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
7833 if (anon_parm_regs > 0)
7834 *pretend_arg_size = anon_parm_regs * 4;
7839 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
7845 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
7847 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
7851 /* Define the offset between two registers, one to be eliminated, and
7852 the other its replacement, at the start of a routine. */
7855 initial_elimination_offset (int from, int to)
7858 int regs_saved_rounding = 0;
7859 int total_saved_regs_space;
7860 int total_auto_space;
7861 int save_flags = target_flags;
7863 HARD_REG_SET live_regs_mask;
7865 shmedia_space_reserved_for_target_registers = false;
7866 regs_saved = calc_live_regs (&live_regs_mask);
7867 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
7869 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
7871 shmedia_space_reserved_for_target_registers = true;
7872 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
7875 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
7876 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7877 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
7879 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
7880 copy_flags = target_flags;
7881 target_flags = save_flags;
7883 total_saved_regs_space = regs_saved + regs_saved_rounding;
7885 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7886 return total_saved_regs_space + total_auto_space
7887 + crtl->args.info.byref_regs * 8;
7889 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7890 return total_saved_regs_space + total_auto_space
7891 + crtl->args.info.byref_regs * 8;
7893 /* Initial gap between fp and sp is 0. */
7894 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7897 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7898 return rounded_frame_size (0);
7900 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7901 return rounded_frame_size (0);
7903 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
7904 && (to == HARD_FRAME_POINTER_REGNUM
7905 || to == STACK_POINTER_REGNUM));
7908 int n = total_saved_regs_space;
7909 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7910 save_schedule schedule;
7913 n += total_auto_space;
7915 /* If it wasn't saved, there's not much we can do. */
7916 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7919 target_flags = copy_flags;
7921 sh5_schedule_saves (&live_regs_mask, &schedule, n);
7922 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
7923 if (entry->reg == pr_reg)
7925 target_flags = save_flags;
7926 return entry->offset;
7931 return total_auto_space;
7934 /* Parse the -mfixed-range= option string. */
7936 sh_fix_range (const char *const_str)
7939 char *str, *dash, *comma;
7941 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
7942 REG2 are either register names or register numbers. The effect
7943 of this option is to mark the registers in the range from REG1 to
7944 REG2 as ``fixed'' so they won't be used by the compiler. */
7946 i = strlen (const_str);
7947 str = (char *) alloca (i + 1);
7948 memcpy (str, const_str, i + 1);
7952 dash = strchr (str, '-');
7955 warning (0, "value of -mfixed-range must have form REG1-REG2");
7959 comma = strchr (dash + 1, ',');
7963 first = decode_reg_name (str);
7966 warning (0, "unknown register name: %s", str);
7970 last = decode_reg_name (dash + 1);
7973 warning (0, "unknown register name: %s", dash + 1);
7981 warning (0, "%s-%s is an empty range", str, dash + 1);
7985 for (i = first; i <= last; ++i)
7986 fixed_regs[i] = call_used_regs[i] = 1;
7996 /* Insert any deferred function attributes from earlier pragmas. */
7998 sh_insert_attributes (tree node, tree *attributes)
8002 if (TREE_CODE (node) != FUNCTION_DECL)
8005 /* We are only interested in fields. */
8009 /* Append the attributes to the deferred attributes. */
8010 *sh_deferred_function_attributes_tail = *attributes;
8011 attrs = sh_deferred_function_attributes;
8015 /* Some attributes imply or require the interrupt attribute. */
8016 if (!lookup_attribute ("interrupt_handler", attrs)
8017 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8019 /* If we have a trapa_handler, but no interrupt_handler attribute,
8020 insert an interrupt_handler attribute. */
8021 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8022 /* We can't use sh_pr_interrupt here because that's not in the
8025 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8026 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8027 if the interrupt attribute is missing, we ignore the attribute
8029 else if (lookup_attribute ("sp_switch", attrs)
8030 || lookup_attribute ("trap_exit", attrs)
8031 || lookup_attribute ("nosave_low_regs", attrs)
8032 || lookup_attribute ("resbank", attrs))
8036 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8038 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8039 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8040 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8041 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8042 warning (OPT_Wattributes,
8043 "%qE attribute only applies to interrupt functions",
8044 TREE_PURPOSE (attrs));
8047 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8049 tail = &TREE_CHAIN (*tail);
8052 attrs = *attributes;
8056 /* Install the processed list. */
8057 *attributes = attrs;
8059 /* Clear deferred attributes. */
8060 sh_deferred_function_attributes = NULL_TREE;
8061 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8066 /* Supported attributes:
8068 interrupt_handler -- specifies this function is an interrupt handler.
8070 trapa_handler - like above, but don't save all registers.
8072 sp_switch -- specifies an alternate stack for an interrupt handler
8075 trap_exit -- use a trapa to exit an interrupt function instead of
8078 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8079 This is useful on the SH3 and upwards,
8080 which has a separate set of low regs for User and Supervisor modes.
8081 This should only be used for the lowest level of interrupts. Higher levels
8082 of interrupts must save the registers in case they themselves are
8085 renesas -- use Renesas calling/layout conventions (functions and
8088 resbank -- In case of an ISR, use a register bank to save registers
8089 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8092 const struct attribute_spec sh_attribute_table[] =
8094 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8095 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8096 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
8097 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
8098 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
8099 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8100 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8101 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
8102 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
8104 /* Symbian support adds three new attributes:
8105 dllexport - for exporting a function/variable that will live in a dll
8106 dllimport - for importing a function/variable from a dll
8108 Microsoft allows multiple declspecs in one __declspec, separating
8109 them with spaces. We do NOT support this. Instead, use __declspec
8111 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8112 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8114 { NULL, 0, 0, false, false, false, NULL }
8117 /* Handle a 'resbank' attribute. */
8119 sh_handle_resbank_handler_attribute (tree * node, tree name,
8120 tree args ATTRIBUTE_UNUSED,
8121 int flags ATTRIBUTE_UNUSED,
8122 bool * no_add_attrs)
8126 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8128 *no_add_attrs = true;
8130 if (TREE_CODE (*node) != FUNCTION_DECL)
8132 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8134 *no_add_attrs = true;
8140 /* Handle an "interrupt_handler" attribute; arguments as in
8141 struct attribute_spec.handler. */
8143 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8144 tree args ATTRIBUTE_UNUSED,
8145 int flags ATTRIBUTE_UNUSED,
8148 if (TREE_CODE (*node) != FUNCTION_DECL)
8150 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8152 *no_add_attrs = true;
8154 else if (TARGET_SHCOMPACT)
8156 error ("attribute interrupt_handler is not compatible with -m5-compact");
8157 *no_add_attrs = true;
8163 /* Handle an 'function_vector' attribute; arguments as in
8164 struct attribute_spec.handler. */
8166 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8167 tree args ATTRIBUTE_UNUSED,
8168 int flags ATTRIBUTE_UNUSED,
8169 bool * no_add_attrs)
8173 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8175 *no_add_attrs = true;
8177 else if (TREE_CODE (*node) != FUNCTION_DECL)
8179 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8181 *no_add_attrs = true;
8183 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8185 /* The argument must be a constant integer. */
8186 warning (OPT_Wattributes,
8187 "%qE attribute argument not an integer constant",
8189 *no_add_attrs = true;
8191 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8193 /* The argument value must be between 0 to 255. */
8194 warning (OPT_Wattributes,
8195 "%qE attribute argument should be between 0 to 255",
8197 *no_add_attrs = true;
8202 /* Returns 1 if current function has been assigned the attribute
8203 'function_vector'. */
8205 sh2a_is_function_vector_call (rtx x)
8207 if (GET_CODE (x) == SYMBOL_REF
8208 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8210 tree tr = SYMBOL_REF_DECL (x);
8212 if (sh2a_function_vector_p (tr))
8219 /* Returns the function vector number, if the the attribute
8220 'function_vector' is assigned, otherwise returns zero. */
8222 sh2a_get_function_vector_number (rtx x)
8227 if ((GET_CODE (x) == SYMBOL_REF)
8228 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8230 t = SYMBOL_REF_DECL (x);
8232 if (TREE_CODE (t) != FUNCTION_DECL)
8235 list = SH_ATTRIBUTES (t);
8238 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8240 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8244 list = TREE_CHAIN (list);
8253 /* Handle an "sp_switch" attribute; arguments as in
8254 struct attribute_spec.handler. */
8256 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8257 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8259 if (TREE_CODE (*node) != FUNCTION_DECL)
8261 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8263 *no_add_attrs = true;
8265 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8267 /* The argument must be a constant string. */
8268 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
8270 *no_add_attrs = true;
8276 /* Handle an "trap_exit" attribute; arguments as in
8277 struct attribute_spec.handler. */
8279 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8280 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8282 if (TREE_CODE (*node) != FUNCTION_DECL)
8284 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8286 *no_add_attrs = true;
8288 /* The argument specifies a trap number to be used in a trapa instruction
8289 at function exit (instead of an rte instruction). */
8290 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8292 /* The argument must be a constant integer. */
8293 warning (OPT_Wattributes, "%qE attribute argument not an "
8294 "integer constant", name);
8295 *no_add_attrs = true;
8302 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8303 tree name ATTRIBUTE_UNUSED,
8304 tree args ATTRIBUTE_UNUSED,
8305 int flags ATTRIBUTE_UNUSED,
8306 bool *no_add_attrs ATTRIBUTE_UNUSED)
8311 /* True if __attribute__((renesas)) or -mrenesas. */
8313 sh_attr_renesas_p (const_tree td)
8320 td = TREE_TYPE (td);
8321 if (td == error_mark_node)
8323 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8327 /* True if __attribute__((renesas)) or -mrenesas, for the current
8330 sh_cfun_attr_renesas_p (void)
8332 return sh_attr_renesas_p (current_function_decl);
8336 sh_cfun_interrupt_handler_p (void)
8338 return (lookup_attribute ("interrupt_handler",
8339 DECL_ATTRIBUTES (current_function_decl))
8343 /* Returns 1 if FUNC has been assigned the attribute
8344 "function_vector". */
8346 sh2a_function_vector_p (tree func)
8349 if (TREE_CODE (func) != FUNCTION_DECL)
8352 list = SH_ATTRIBUTES (func);
8355 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8358 list = TREE_CHAIN (list);
8363 /* Returns TRUE if given tree has the "resbank" attribute. */
8366 sh_cfun_resbank_handler_p (void)
8368 return ((lookup_attribute ("resbank",
8369 DECL_ATTRIBUTES (current_function_decl))
8371 && (lookup_attribute ("interrupt_handler",
8372 DECL_ATTRIBUTES (current_function_decl))
8373 != NULL_TREE) && TARGET_SH2A);
8376 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8379 sh_check_pch_target_flags (int old_flags)
8381 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8382 | MASK_SH_E | MASK_HARD_SH4
8383 | MASK_FPU_SINGLE | MASK_SH4))
8384 return _("created and used with different architectures / ABIs");
8385 if ((old_flags ^ target_flags) & MASK_HITACHI)
8386 return _("created and used with different ABIs");
8387 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8388 return _("created and used with different endianness");
8392 /* Predicates used by the templates. */
8394 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8395 Used only in general_movsrc_operand. */
8398 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8410 /* Nonzero if OP is a floating point value with value 0.0. */
8413 fp_zero_operand (rtx op)
8417 if (GET_MODE (op) != SFmode)
8420 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8421 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8424 /* Nonzero if OP is a floating point value with value 1.0. */
8427 fp_one_operand (rtx op)
8431 if (GET_MODE (op) != SFmode)
8434 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8435 return REAL_VALUES_EQUAL (r, dconst1);
8438 /* For -m4 and -m4-single-only, mode switching is used. If we are
8439 compiling without -mfmovd, movsf_ie isn't taken into account for
8440 mode switching. We could check in machine_dependent_reorg for
8441 cases where we know we are in single precision mode, but there is
8442 interface to find that out during reload, so we must avoid
8443 choosing an fldi alternative during reload and thus failing to
8444 allocate a scratch register for the constant loading. */
8448 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
8452 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8454 enum rtx_code code = GET_CODE (op);
8455 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8458 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8460 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8462 if (GET_CODE (op) != SYMBOL_REF)
8463 return TLS_MODEL_NONE;
8464 return SYMBOL_REF_TLS_MODEL (op);
8467 /* Return the destination address of a branch. */
8470 branch_dest (rtx branch)
8472 rtx dest = SET_SRC (PATTERN (branch));
8475 if (GET_CODE (dest) == IF_THEN_ELSE)
8476 dest = XEXP (dest, 1);
8477 dest = XEXP (dest, 0);
8478 dest_uid = INSN_UID (dest);
8479 return INSN_ADDRESSES (dest_uid);
8482 /* Return nonzero if REG is not used after INSN.
8483 We assume REG is a reload reg, and therefore does
8484 not live past labels. It may live past calls or jumps though. */
8486 reg_unused_after (rtx reg, rtx insn)
8491 /* If the reg is set by this instruction, then it is safe for our
8492 case. Disregard the case where this is a store to memory, since
8493 we are checking a register used in the store address. */
8494 set = single_set (insn);
8495 if (set && GET_CODE (SET_DEST (set)) != MEM
8496 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8499 while ((insn = NEXT_INSN (insn)))
8505 code = GET_CODE (insn);
8508 /* If this is a label that existed before reload, then the register
8509 if dead here. However, if this is a label added by reorg, then
8510 the register may still be live here. We can't tell the difference,
8511 so we just ignore labels completely. */
8512 if (code == CODE_LABEL)
8517 if (code == JUMP_INSN)
8520 /* If this is a sequence, we must handle them all at once.
8521 We could have for instance a call that sets the target register,
8522 and an insn in a delay slot that uses the register. In this case,
8523 we must return 0. */
8524 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8529 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8531 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
8532 rtx set = single_set (this_insn);
8534 if (GET_CODE (this_insn) == CALL_INSN)
8536 else if (GET_CODE (this_insn) == JUMP_INSN)
8538 if (INSN_ANNULLED_BRANCH_P (this_insn))
8543 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8545 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8547 if (GET_CODE (SET_DEST (set)) != MEM)
8553 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8558 else if (code == JUMP_INSN)
8562 set = single_set (insn);
8563 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8565 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8566 return GET_CODE (SET_DEST (set)) != MEM;
8567 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8570 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
8578 static GTY(()) rtx fpscr_rtx;
8580 get_fpscr_rtx (void)
8584 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
8585 REG_USERVAR_P (fpscr_rtx) = 1;
8586 mark_user_reg (fpscr_rtx);
8588 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
8589 mark_user_reg (fpscr_rtx);
8593 static GTY(()) tree fpscr_values;
8596 emit_fpu_switch (rtx scratch, int index)
8600 if (fpscr_values == NULL)
8604 t = build_index_type (integer_one_node);
8605 t = build_array_type (integer_type_node, t);
8606 t = build_decl (VAR_DECL, get_identifier ("__fpscr_values"), t);
8607 DECL_ARTIFICIAL (t) = 1;
8608 DECL_IGNORED_P (t) = 1;
8609 DECL_EXTERNAL (t) = 1;
8610 TREE_STATIC (t) = 1;
8611 TREE_PUBLIC (t) = 1;
8617 src = DECL_RTL (fpscr_values);
8618 if (!can_create_pseudo_p ())
8620 emit_move_insn (scratch, XEXP (src, 0));
8622 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
8623 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
8626 src = adjust_address (src, PSImode, index * 4);
8628 dst = get_fpscr_rtx ();
8629 emit_move_insn (dst, src);
8633 emit_sf_insn (rtx pat)
8639 emit_df_insn (rtx pat)
8645 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8647 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8651 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8653 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
8658 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8660 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8664 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8666 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
8670 static rtx get_free_reg (HARD_REG_SET);
8672 /* This function returns a register to use to load the address to load
8673 the fpscr from. Currently it always returns r1 or r7, but when we are
8674 able to use pseudo registers after combine, or have a better mechanism
8675 for choosing a register, it should be done here. */
8676 /* REGS_LIVE is the liveness information for the point for which we
8677 need this allocation. In some bare-bones exit blocks, r1 is live at the
8678 start. We can even have all of r0..r3 being live:
8679 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
8680 INSN before which new insns are placed with will clobber the register
8681 we return. If a basic block consists only of setting the return value
8682 register to a pseudo and using that register, the return value is not
8683 live before or after this block, yet we we'll insert our insns right in
8687 get_free_reg (HARD_REG_SET regs_live)
8689 if (! TEST_HARD_REG_BIT (regs_live, 1))
8690 return gen_rtx_REG (Pmode, 1);
8692 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
8693 there shouldn't be anything but a jump before the function end. */
8694 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
8695 return gen_rtx_REG (Pmode, 7);
8698 /* This function will set the fpscr from memory.
8699 MODE is the mode we are setting it to. */
8701 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
8703 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
8704 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
8707 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
8708 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
8711 /* Is the given character a logical line separator for the assembler? */
8712 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
8713 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
8717 sh_insn_length_adjustment (rtx insn)
8719 /* Instructions with unfilled delay slots take up an extra two bytes for
8720 the nop in the delay slot. */
8721 if (((GET_CODE (insn) == INSN
8722 && GET_CODE (PATTERN (insn)) != USE
8723 && GET_CODE (PATTERN (insn)) != CLOBBER)
8724 || GET_CODE (insn) == CALL_INSN
8725 || (GET_CODE (insn) == JUMP_INSN
8726 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8727 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
8728 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
8729 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
8732 /* SH2e has a bug that prevents the use of annulled branches, so if
8733 the delay slot is not filled, we'll have to put a NOP in it. */
8734 if (sh_cpu_attr == CPU_SH2E
8735 && GET_CODE (insn) == JUMP_INSN
8736 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8737 && GET_CODE (PATTERN (insn)) != ADDR_VEC
8738 && get_attr_type (insn) == TYPE_CBRANCH
8739 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
8742 /* sh-dsp parallel processing insn take four bytes instead of two. */
8744 if (GET_CODE (insn) == INSN)
8747 rtx body = PATTERN (insn);
8750 int maybe_label = 1;
8752 if (GET_CODE (body) == ASM_INPUT)
8753 templ = XSTR (body, 0);
8754 else if (asm_noperands (body) >= 0)
8756 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
8765 while (c == ' ' || c == '\t');
8766 /* all sh-dsp parallel-processing insns start with p.
8767 The only non-ppi sh insn starting with p is pref.
8768 The only ppi starting with pr is prnd. */
8769 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
8771 /* The repeat pseudo-insn expands two three insns, a total of
8772 six bytes in size. */
8773 else if ((c == 'r' || c == 'R')
8774 && ! strncasecmp ("epeat", templ, 5))
8776 while (c && c != '\n'
8777 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
8779 /* If this is a label, it is obviously not a ppi insn. */
8780 if (c == ':' && maybe_label)
8785 else if (c == '\'' || c == '"')
8790 maybe_label = c != ':';
8798 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
8799 isn't protected by a PIC unspec. */
8801 nonpic_symbol_mentioned_p (rtx x)
8803 register const char *fmt;
8806 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
8807 || GET_CODE (x) == PC)
8810 /* We don't want to look into the possible MEM location of a
8811 CONST_DOUBLE, since we're not going to use it, in general. */
8812 if (GET_CODE (x) == CONST_DOUBLE)
8815 if (GET_CODE (x) == UNSPEC
8816 && (XINT (x, 1) == UNSPEC_PIC
8817 || XINT (x, 1) == UNSPEC_GOT
8818 || XINT (x, 1) == UNSPEC_GOTOFF
8819 || XINT (x, 1) == UNSPEC_GOTPLT
8820 || XINT (x, 1) == UNSPEC_GOTTPOFF
8821 || XINT (x, 1) == UNSPEC_DTPOFF
8822 || XINT (x, 1) == UNSPEC_PLT
8823 || XINT (x, 1) == UNSPEC_SYMOFF
8824 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
8827 fmt = GET_RTX_FORMAT (GET_CODE (x));
8828 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8834 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8835 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
8838 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
8845 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
8846 @GOTOFF in `reg'. */
8848 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
8851 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
8854 if (GET_CODE (orig) == LABEL_REF
8855 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
8858 reg = gen_reg_rtx (Pmode);
8860 emit_insn (gen_symGOTOFF2reg (reg, orig));
8863 else if (GET_CODE (orig) == SYMBOL_REF)
8866 reg = gen_reg_rtx (Pmode);
8868 emit_insn (gen_symGOT2reg (reg, orig));
8874 /* Try machine-dependent ways of modifying an illegitimate address
8875 to be legitimate. If we find one, return the new, valid address.
8876 Otherwise, return X.
8878 For the SH, if X is almost suitable for indexing, but the offset is
8879 out of range, convert it into a normal form so that CSE has a chance
8880 of reducing the number of address registers used. */
8883 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
8886 x = legitimize_pic_address (oldx, mode, NULL_RTX);
8888 if (GET_CODE (x) == PLUS
8889 && (GET_MODE_SIZE (mode) == 4
8890 || GET_MODE_SIZE (mode) == 8)
8891 && GET_CODE (XEXP (x, 1)) == CONST_INT
8892 && BASE_REGISTER_RTX_P (XEXP (x, 0))
8894 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
8895 && ! (TARGET_SH2E && mode == SFmode))
8897 rtx index_rtx = XEXP (x, 1);
8898 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
8901 /* On rare occasions, we might get an unaligned pointer
8902 that is indexed in a way to give an aligned address.
8903 Therefore, keep the lower two bits in offset_base. */
8904 /* Instead of offset_base 128..131 use 124..127, so that
8905 simple add suffices. */
8907 offset_base = ((offset + 4) & ~60) - 4;
8909 offset_base = offset & ~60;
8911 /* Sometimes the normal form does not suit DImode. We
8912 could avoid that by using smaller ranges, but that
8913 would give less optimized code when SImode is
8915 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
8917 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
8918 GEN_INT (offset_base), NULL_RTX, 0,
8921 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
8928 /* Mark the use of a constant in the literal table. If the constant
8929 has multiple labels, make it unique. */
8931 mark_constant_pool_use (rtx x)
8933 rtx insn, lab, pattern;
8938 switch (GET_CODE (x))
8948 /* Get the first label in the list of labels for the same constant
8949 and delete another labels in the list. */
8951 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
8953 if (GET_CODE (insn) != CODE_LABEL
8954 || LABEL_REFS (insn) != NEXT_INSN (insn))
8959 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
8960 INSN_DELETED_P (insn) = 1;
8962 /* Mark constants in a window. */
8963 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
8965 if (GET_CODE (insn) != INSN)
8968 pattern = PATTERN (insn);
8969 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
8972 switch (XINT (pattern, 1))
8974 case UNSPECV_CONST2:
8975 case UNSPECV_CONST4:
8976 case UNSPECV_CONST8:
8977 XVECEXP (pattern, 0, 1) = const1_rtx;
8979 case UNSPECV_WINDOW_END:
8980 if (XVECEXP (pattern, 0, 0) == x)
8983 case UNSPECV_CONST_END:
8993 /* Return true if it's possible to redirect BRANCH1 to the destination
8994 of an unconditional jump BRANCH2. We only want to do this if the
8995 resulting branch will have a short displacement. */
8997 sh_can_redirect_branch (rtx branch1, rtx branch2)
8999 if (flag_expensive_optimizations && simplejump_p (branch2))
9001 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
9005 for (distance = 0, insn = NEXT_INSN (branch1);
9006 insn && distance < 256;
9007 insn = PREV_INSN (insn))
9012 distance += get_attr_length (insn);
9014 for (distance = 0, insn = NEXT_INSN (branch1);
9015 insn && distance < 256;
9016 insn = NEXT_INSN (insn))
9021 distance += get_attr_length (insn);
9027 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9029 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9030 unsigned int new_reg)
9032 /* Interrupt functions can only use registers that have already been
9033 saved by the prologue, even if they would normally be
9036 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
9042 /* Function to update the integer COST
9043 based on the relationship between INSN that is dependent on
9044 DEP_INSN through the dependence LINK. The default is to make no
9045 adjustment to COST. This can be used for example to specify to
9046 the scheduler that an output- or anti-dependence does not incur
9047 the same cost as a data-dependence. The return value should be
9048 the new value for COST. */
9050 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
9056 /* On SHmedia, if the dependence is an anti-dependence or
9057 output-dependence, there is no cost. */
9058 if (REG_NOTE_KIND (link) != 0)
9060 /* However, dependencies between target register loads and
9061 uses of the register in a subsequent block that are separated
9062 by a conditional branch are not modelled - we have to do with
9063 the anti-dependency between the target register load and the
9064 conditional branch that ends the current block. */
9065 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9066 && GET_CODE (PATTERN (dep_insn)) == SET
9067 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
9068 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
9069 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
9071 int orig_cost = cost;
9072 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
9073 rtx target = ((! note
9074 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
9075 ? insn : JUMP_LABEL (insn));
9076 /* On the likely path, the branch costs 1, on the unlikely path,
9080 target = next_active_insn (target);
9081 while (target && ! flow_dependent_p (target, dep_insn)
9083 /* If two branches are executed in immediate succession, with the
9084 first branch properly predicted, this causes a stall at the
9085 second branch, hence we won't need the target for the
9086 second branch for two cycles after the launch of the first
9088 if (cost > orig_cost - 2)
9089 cost = orig_cost - 2;
9095 else if (get_attr_is_mac_media (insn)
9096 && get_attr_is_mac_media (dep_insn))
9099 else if (! reload_completed
9100 && GET_CODE (PATTERN (insn)) == SET
9101 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9102 && GET_CODE (PATTERN (dep_insn)) == SET
9103 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9106 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9107 that is needed at the target. */
9108 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9109 && ! flow_dependent_p (insn, dep_insn))
9112 else if (REG_NOTE_KIND (link) == 0)
9114 enum attr_type type;
9117 if (recog_memoized (insn) < 0
9118 || recog_memoized (dep_insn) < 0)
9121 dep_set = single_set (dep_insn);
9123 /* The latency that we specify in the scheduling description refers
9124 to the actual output, not to an auto-increment register; for that,
9125 the latency is one. */
9126 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9128 rtx set = single_set (insn);
9131 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9132 && (!MEM_P (SET_DEST (set))
9133 || !reg_mentioned_p (SET_DEST (dep_set),
9134 XEXP (SET_DEST (set), 0))))
9137 /* The only input for a call that is timing-critical is the
9138 function's address. */
9139 if (GET_CODE (insn) == CALL_INSN)
9141 rtx call = PATTERN (insn);
9143 if (GET_CODE (call) == PARALLEL)
9144 call = XVECEXP (call, 0 ,0);
9145 if (GET_CODE (call) == SET)
9146 call = SET_SRC (call);
9147 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
9148 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9149 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9150 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9151 cost -= TARGET_SH4_300 ? 3 : 6;
9153 /* Likewise, the most timing critical input for an sfuncs call
9154 is the function address. However, sfuncs typically start
9155 using their arguments pretty quickly.
9156 Assume a four cycle delay for SH4 before they are needed.
9157 Cached ST40-300 calls are quicker, so assume only a one
9159 ??? Maybe we should encode the delays till input registers
9160 are needed by sfuncs into the sfunc call insn. */
9161 /* All sfunc calls are parallels with at least four components.
9162 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9163 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9164 && XVECLEN (PATTERN (insn), 0) >= 4
9165 && (reg = sfunc_uses_reg (insn)))
9167 if (! reg_set_p (reg, dep_insn))
9168 cost -= TARGET_SH4_300 ? 1 : 4;
9170 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9172 enum attr_type dep_type = get_attr_type (dep_insn);
9174 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9176 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9177 && (type = get_attr_type (insn)) != TYPE_CALL
9178 && type != TYPE_SFUNC)
9180 /* When the preceding instruction loads the shift amount of
9181 the following SHAD/SHLD, the latency of the load is increased
9183 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9184 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9185 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9186 XEXP (SET_SRC (single_set (insn)),
9189 /* When an LS group instruction with a latency of less than
9190 3 cycles is followed by a double-precision floating-point
9191 instruction, FIPR, or FTRV, the latency of the first
9192 instruction is increased to 3 cycles. */
9194 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9195 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9197 /* The lsw register of a double-precision computation is ready one
9199 else if (reload_completed
9200 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9201 && (use_pat = single_set (insn))
9202 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9206 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9207 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9210 else if (TARGET_SH4_300)
9212 /* Stores need their input register two cycles later. */
9213 if (dep_set && cost >= 1
9214 && ((type = get_attr_type (insn)) == TYPE_STORE
9215 || type == TYPE_PSTORE
9216 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9218 rtx set = single_set (insn);
9220 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9221 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9224 /* But don't reduce the cost below 1 if the address depends
9225 on a side effect of dep_insn. */
9227 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9233 /* An anti-dependence penalty of two applies if the first insn is a double
9234 precision fadd / fsub / fmul. */
9235 else if (!TARGET_SH4_300
9236 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9237 && recog_memoized (dep_insn) >= 0
9238 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9239 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9240 /* A lot of alleged anti-flow dependences are fake,
9241 so check this one is real. */
9242 && flow_dependent_p (dep_insn, insn))
9248 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9249 if DEP_INSN is anti-flow dependent on INSN. */
9251 flow_dependent_p (rtx insn, rtx dep_insn)
9253 rtx tmp = PATTERN (insn);
9255 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9256 return tmp == NULL_RTX;
9259 /* A helper function for flow_dependent_p called through note_stores. */
9261 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9263 rtx * pinsn = (rtx *) data;
9265 if (*pinsn && reg_referenced_p (x, *pinsn))
9269 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9270 'special function' patterns (type sfunc) that clobber pr, but that
9271 do not look like function calls to leaf_function_p. Hence we must
9272 do this extra check. */
9276 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9279 /* Return where to allocate pseudo for a given hard register initial
9282 sh_allocate_initial_value (rtx hard_reg)
9286 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9288 if (current_function_is_leaf
9289 && ! sh_pr_n_sets ()
9290 && ! (TARGET_SHCOMPACT
9291 && ((crtl->args.info.call_cookie
9292 & ~ CALL_COOKIE_RET_TRAMP (1))
9293 || crtl->saves_all_registers)))
9296 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9304 /* This function returns "2" to indicate dual issue for the SH4
9305 processor. To be used by the DFA pipeline description. */
9307 sh_issue_rate (void)
9309 if (TARGET_SUPERSCALAR)
9315 /* Functions for ready queue reordering for sched1. */
9317 /* Get weight for mode for a set x. */
9319 find_set_regmode_weight (rtx x, enum machine_mode mode)
9321 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9323 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9325 if (GET_CODE (SET_DEST (x)) == REG)
9327 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9337 /* Get regmode weight for insn. */
9339 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9341 short reg_weight = 0;
9344 /* Increment weight for each register born here. */
9346 reg_weight += find_set_regmode_weight (x, mode);
9347 if (GET_CODE (x) == PARALLEL)
9350 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9352 x = XVECEXP (PATTERN (insn), 0, j);
9353 reg_weight += find_set_regmode_weight (x, mode);
9356 /* Decrement weight for each register that dies here. */
9357 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9359 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9361 rtx note = XEXP (x, 0);
9362 if (GET_CODE (note) == REG && GET_MODE (note) == mode)
9369 /* Calculate regmode weights for all insns of a basic block. */
9371 find_regmode_weight (basic_block b, enum machine_mode mode)
9373 rtx insn, next_tail, head, tail;
9375 get_ebb_head_tail (b, b, &head, &tail);
9376 next_tail = NEXT_INSN (tail);
9378 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9380 /* Handle register life information. */
9385 INSN_REGMODE_WEIGHT (insn, mode) =
9386 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9387 else if (mode == SImode)
9388 INSN_REGMODE_WEIGHT (insn, mode) =
9389 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9393 /* Comparison function for ready queue sorting. */
9395 rank_for_reorder (const void *x, const void *y)
9397 rtx tmp = *(const rtx *) y;
9398 rtx tmp2 = *(const rtx *) x;
9400 /* The insn in a schedule group should be issued the first. */
9401 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9402 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9404 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9405 minimizes instruction movement, thus minimizing sched's effect on
9406 register pressure. */
9407 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9410 /* Resort the array A in which only element at index N may be out of order. */
9412 swap_reorder (rtx *a, int n)
9414 rtx insn = a[n - 1];
9417 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9425 #define SCHED_REORDER(READY, N_READY) \
9428 if ((N_READY) == 2) \
9429 swap_reorder (READY, N_READY); \
9430 else if ((N_READY) > 2) \
9431 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
9435 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
9438 ready_reorder (rtx *ready, int nready)
9440 SCHED_REORDER (ready, nready);
9443 /* Count life regions of r0 for a block. */
9445 find_r0_life_regions (basic_block b)
9454 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
9467 r0_reg = gen_rtx_REG (SImode, R0_REG);
9472 if (find_regno_note (insn, REG_DEAD, R0_REG))
9478 && (pset = single_set (insn))
9479 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
9480 && !find_regno_note (insn, REG_UNUSED, R0_REG))
9488 insn = NEXT_INSN (insn);
9493 /* Calculate regmode weights for all insns of all basic block. */
9495 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
9496 int verbose ATTRIBUTE_UNUSED,
9501 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
9502 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
9503 r0_life_regions = 0;
9505 FOR_EACH_BB_REVERSE (b)
9507 find_regmode_weight (b, SImode);
9508 find_regmode_weight (b, SFmode);
9509 if (!reload_completed)
9510 r0_life_regions += find_r0_life_regions (b);
9513 CURR_REGMODE_PRESSURE (SImode) = 0;
9514 CURR_REGMODE_PRESSURE (SFmode) = 0;
9520 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
9521 int verbose ATTRIBUTE_UNUSED)
9523 if (regmode_weight[0])
9525 free (regmode_weight[0]);
9526 regmode_weight[0] = NULL;
9528 if (regmode_weight[1])
9530 free (regmode_weight[1]);
9531 regmode_weight[1] = NULL;
9535 /* The scalar modes supported differs from the default version in TImode
9536 for 32-bit SHMEDIA. */
9538 sh_scalar_mode_supported_p (enum machine_mode mode)
9540 if (TARGET_SHMEDIA32 && mode == TImode)
9543 return default_scalar_mode_supported_p (mode);
9546 /* Cache the can_issue_more so that we can return it from reorder2. Also,
9547 keep count of register pressures on SImode and SFmode. */
9549 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
9550 int sched_verbose ATTRIBUTE_UNUSED,
9554 if (GET_CODE (PATTERN (insn)) != USE
9555 && GET_CODE (PATTERN (insn)) != CLOBBER)
9556 cached_can_issue_more = can_issue_more - 1;
9558 cached_can_issue_more = can_issue_more;
9560 if (reload_completed)
9561 return cached_can_issue_more;
9563 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
9564 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
9566 return cached_can_issue_more;
9570 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
9571 int verbose ATTRIBUTE_UNUSED,
9572 int veclen ATTRIBUTE_UNUSED)
9574 CURR_REGMODE_PRESSURE (SImode) = 0;
9575 CURR_REGMODE_PRESSURE (SFmode) = 0;
9578 /* Some magic numbers. */
9579 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9580 functions that already have high pressure on r0. */
9581 #define R0_MAX_LIFE_REGIONS 2
9582 /* Register Pressure thresholds for SImode and SFmode registers. */
9583 #define SIMODE_MAX_WEIGHT 5
9584 #define SFMODE_MAX_WEIGHT 10
9586 /* Return true if the pressure is high for MODE. */
9588 high_pressure (enum machine_mode mode)
9590 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9591 functions that already have high pressure on r0. */
9592 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
9596 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
9598 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
9601 /* Reorder ready queue if register pressure is high. */
9603 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
9604 int sched_verbose ATTRIBUTE_UNUSED,
9607 int clock_var ATTRIBUTE_UNUSED)
9609 if (reload_completed)
9610 return sh_issue_rate ();
9612 if (high_pressure (SFmode) || high_pressure (SImode))
9614 ready_reorder (ready, *n_readyp);
9617 return sh_issue_rate ();
9620 /* Skip cycles if the current register pressure is high. */
9622 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
9623 int sched_verbose ATTRIBUTE_UNUSED,
9624 rtx *ready ATTRIBUTE_UNUSED,
9625 int *n_readyp ATTRIBUTE_UNUSED,
9626 int clock_var ATTRIBUTE_UNUSED)
9628 if (reload_completed)
9629 return cached_can_issue_more;
9631 if (high_pressure(SFmode) || high_pressure (SImode))
9634 return cached_can_issue_more;
9637 /* Skip cycles without sorting the ready queue. This will move insn from
9638 Q->R. If this is the last cycle we are skipping; allow sorting of ready
9639 queue by sh_reorder. */
9641 /* Generally, skipping these many cycles are sufficient for all insns to move
9646 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
9647 int sched_verbose ATTRIBUTE_UNUSED,
9648 rtx insn ATTRIBUTE_UNUSED,
9653 if (reload_completed)
9658 if ((clock_var - last_clock_var) < MAX_SKIPS)
9663 /* If this is the last cycle we are skipping, allow reordering of R. */
9664 if ((clock_var - last_clock_var) == MAX_SKIPS)
9676 /* SHmedia requires registers for branches, so we can't generate new
9677 branches past reload. */
9679 sh_cannot_modify_jumps_p (void)
9681 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
9684 static enum reg_class
9685 sh_target_reg_class (void)
9687 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
9691 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
9698 if (! shmedia_space_reserved_for_target_registers)
9700 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
9702 if (calc_live_regs (&dummy) >= 6 * 8)
9708 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
9710 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
9714 On the SH1..SH4, the trampoline looks like
9715 2 0002 D202 mov.l l2,r2
9716 1 0000 D301 mov.l l1,r3
9719 5 0008 00000000 l1: .long area
9720 6 000c 00000000 l2: .long function
9722 SH5 (compact) uses r1 instead of r3 for the static chain. */
9725 /* Emit RTL insns to initialize the variable parts of a trampoline.
9726 FNADDR is an RTX for the address of the function's pure code.
9727 CXT is an RTX for the static chain value for the function. */
9730 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
9732 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
9734 if (TARGET_SHMEDIA64)
9739 rtx movi1 = GEN_INT (0xcc000010);
9740 rtx shori1 = GEN_INT (0xc8000010);
9743 /* The following trampoline works within a +- 128 KB range for cxt:
9744 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
9745 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
9746 gettr tr1,r1; blink tr0,r63 */
9747 /* Address rounding makes it hard to compute the exact bounds of the
9748 offset for this trampoline, but we have a rather generous offset
9749 range, so frame_offset should do fine as an upper bound. */
9750 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
9752 /* ??? could optimize this trampoline initialization
9753 by writing DImode words with two insns each. */
9754 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
9755 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
9756 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
9757 insn = gen_rtx_AND (DImode, insn, mask);
9758 /* Or in ptb/u .,tr1 pattern */
9759 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
9760 insn = force_operand (insn, NULL_RTX);
9761 insn = gen_lowpart (SImode, insn);
9762 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
9763 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
9764 insn = gen_rtx_AND (DImode, insn, mask);
9765 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
9766 insn = gen_lowpart (SImode, insn);
9767 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
9768 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
9769 insn = gen_rtx_AND (DImode, insn, mask);
9770 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9771 insn = gen_lowpart (SImode, insn);
9772 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
9773 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
9774 insn = gen_rtx_AND (DImode, insn, mask);
9775 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9776 insn = gen_lowpart (SImode, insn);
9777 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
9778 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
9779 insn = gen_rtx_AND (DImode, insn, mask);
9780 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9781 insn = gen_lowpart (SImode, insn);
9782 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
9783 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
9784 GEN_INT (0x6bf10600));
9785 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
9786 GEN_INT (0x4415fc10));
9787 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
9788 GEN_INT (0x4401fff0));
9789 emit_insn (gen_ic_invalidate_line (tramp));
9792 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
9793 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
9795 tramp_templ = gen_datalabel_ref (tramp_templ);
9797 src = gen_const_mem (BLKmode, tramp_templ);
9798 set_mem_align (dst, 256);
9799 set_mem_align (src, 64);
9800 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
9802 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
9803 emit_move_insn (adjust_address (tramp_mem, Pmode,
9804 fixed_len + GET_MODE_SIZE (Pmode)),
9806 emit_insn (gen_ic_invalidate_line (tramp));
9809 else if (TARGET_SHMEDIA)
9811 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
9812 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
9813 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
9814 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
9815 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
9816 rotated 10 right, and higher 16 bit of every 32 selected. */
9818 = force_reg (V2HImode, (simplify_gen_subreg
9819 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
9820 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
9821 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
9823 tramp = force_reg (Pmode, tramp);
9824 fnaddr = force_reg (SImode, fnaddr);
9825 cxt = force_reg (SImode, cxt);
9826 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
9827 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
9829 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
9830 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
9831 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
9832 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
9833 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
9834 gen_rtx_SUBREG (V2HImode, cxt, 0),
9836 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
9837 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
9838 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
9839 if (TARGET_LITTLE_ENDIAN)
9841 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
9842 emit_insn (gen_mextr4 (quad2, cxtload, blink));
9846 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
9847 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
9849 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
9850 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
9851 emit_insn (gen_ic_invalidate_line (tramp));
9854 else if (TARGET_SHCOMPACT)
9856 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
9859 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
9860 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
9862 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
9863 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
9865 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
9866 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
9869 if (!TARGET_INLINE_IC_INVALIDATE
9870 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
9871 emit_library_call (function_symbol (NULL, "__ic_invalidate",
9873 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
9875 emit_insn (gen_ic_invalidate_line (tramp));
9879 /* FIXME: This is overly conservative. A SHcompact function that
9880 receives arguments ``by reference'' will have them stored in its
9881 own stack frame, so it must not pass pointers or references to
9882 these arguments to other functions by means of sibling calls. */
9883 /* If PIC, we cannot make sibling calls to global functions
9884 because the PLT requires r12 to be live. */
9886 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
9889 && (! TARGET_SHCOMPACT
9890 || crtl->args.info.stack_regs == 0)
9891 && ! sh_cfun_interrupt_handler_p ()
9893 || (decl && ! TREE_PUBLIC (decl))
9894 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
9897 /* Machine specific built-in functions. */
9899 struct builtin_description
9901 const enum insn_code icode;
9902 const char *const name;
9906 /* describe number and signedness of arguments; arg[0] == result
9907 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
9908 /* 9: 64-bit pointer, 10: 32-bit pointer */
9909 static const char signature_args[][4] =
9911 #define SH_BLTIN_V2SI2 0
9913 #define SH_BLTIN_V4HI2 1
9915 #define SH_BLTIN_V2SI3 2
9917 #define SH_BLTIN_V4HI3 3
9919 #define SH_BLTIN_V8QI3 4
9921 #define SH_BLTIN_MAC_HISI 5
9923 #define SH_BLTIN_SH_HI 6
9925 #define SH_BLTIN_SH_SI 7
9927 #define SH_BLTIN_V4HI2V2SI 8
9929 #define SH_BLTIN_V4HI2V8QI 9
9931 #define SH_BLTIN_SISF 10
9933 #define SH_BLTIN_LDUA_L 11
9935 #define SH_BLTIN_LDUA_Q 12
9937 #define SH_BLTIN_STUA_L 13
9939 #define SH_BLTIN_STUA_Q 14
9941 #define SH_BLTIN_LDUA_L64 15
9943 #define SH_BLTIN_LDUA_Q64 16
9945 #define SH_BLTIN_STUA_L64 17
9947 #define SH_BLTIN_STUA_Q64 18
9949 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
9950 #define SH_BLTIN_2 19
9951 #define SH_BLTIN_SU 19
9953 #define SH_BLTIN_3 20
9954 #define SH_BLTIN_SUS 20
9956 #define SH_BLTIN_PSSV 21
9958 #define SH_BLTIN_XXUU 22
9959 #define SH_BLTIN_UUUU 22
9961 #define SH_BLTIN_PV 23
9964 /* mcmv: operands considered unsigned. */
9965 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
9966 /* mperm: control value considered unsigned int. */
9967 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
9968 /* mshards_q: returns signed short. */
9969 /* nsb: takes long long arg, returns unsigned char. */
9970 static const struct builtin_description bdesc[] =
9972 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
9973 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
9974 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
9975 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
9976 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
9977 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
9978 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
9979 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
9980 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
9981 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
9982 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
9983 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
9984 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
9985 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
9986 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
9987 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
9988 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
9989 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
9990 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
9991 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
9992 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
9993 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
9994 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
9995 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
9996 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
9997 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
9998 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
9999 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
10000 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
10001 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
10002 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
10003 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
10004 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
10005 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
10006 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
10007 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
10008 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
10009 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
10010 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
10011 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
10012 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
10013 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
10014 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
10015 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
10016 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
10017 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
10018 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
10019 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
10020 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
10021 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
10022 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
10023 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
10024 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
10025 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
10026 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
10027 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
10028 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
10029 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
10030 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
10031 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
10032 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
10033 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
10034 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
10035 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
10036 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
10037 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
10038 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
10039 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
10040 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
10041 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
10042 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
10043 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
10044 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
10045 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
10046 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
10047 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
10048 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
10049 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
10050 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
10051 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
10052 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
10053 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
10054 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
10055 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
10059 sh_media_init_builtins (void)
10061 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10062 const struct builtin_description *d;
10064 memset (shared, 0, sizeof shared);
10065 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
10067 tree type, arg_type = 0;
10068 int signature = d->signature;
10071 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10072 type = shared[signature];
10075 int has_result = signature_args[signature][0] != 0;
10077 if ((signature_args[signature][1] & 8)
10078 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
10079 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
10081 if (! TARGET_FPU_ANY
10082 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10084 type = void_list_node;
10087 int arg = signature_args[signature][i];
10088 int opno = i - 1 + has_result;
10091 arg_type = ptr_type_node;
10093 arg_type = (*lang_hooks.types.type_for_mode)
10094 (insn_data[d->icode].operand[opno].mode,
10099 arg_type = void_type_node;
10102 type = tree_cons (NULL_TREE, arg_type, type);
10104 type = build_function_type (arg_type, type);
10105 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10106 shared[signature] = type;
10108 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10113 /* Implements target hook vector_mode_supported_p. */
10115 sh_vector_mode_supported_p (enum machine_mode mode)
10118 && ((mode == V2SFmode)
10119 || (mode == V4SFmode)
10120 || (mode == V16SFmode)))
10123 else if (TARGET_SHMEDIA
10124 && ((mode == V8QImode)
10125 || (mode == V2HImode)
10126 || (mode == V4HImode)
10127 || (mode == V2SImode)))
10133 /* Implements target hook dwarf_calling_convention. Return an enum
10134 of dwarf_calling_convention. */
10136 sh_dwarf_calling_convention (const_tree func)
10138 if (sh_attr_renesas_p (func))
10139 return DW_CC_GNU_renesas_sh;
10141 return DW_CC_normal;
10145 sh_init_builtins (void)
10147 if (TARGET_SHMEDIA)
10148 sh_media_init_builtins ();
10151 /* Expand an expression EXP that calls a built-in function,
10152 with result going to TARGET if that's convenient
10153 (and in mode MODE if that's convenient).
10154 SUBTARGET may be used as the target for computing one of EXP's operands.
10155 IGNORE is nonzero if the value is to be ignored. */
10158 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10159 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10161 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10162 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10163 const struct builtin_description *d = &bdesc[fcode];
10164 enum insn_code icode = d->icode;
10165 int signature = d->signature;
10166 enum machine_mode tmode = VOIDmode;
10171 if (signature_args[signature][0])
10176 tmode = insn_data[icode].operand[0].mode;
10178 || GET_MODE (target) != tmode
10179 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10180 target = gen_reg_rtx (tmode);
10181 op[nop++] = target;
10186 for (i = 1; i <= 3; i++, nop++)
10189 enum machine_mode opmode, argmode;
10192 if (! signature_args[signature][i])
10194 arg = CALL_EXPR_ARG (exp, i - 1);
10195 if (arg == error_mark_node)
10197 if (signature_args[signature][i] & 8)
10200 optype = ptr_type_node;
10204 opmode = insn_data[icode].operand[nop].mode;
10205 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10207 argmode = TYPE_MODE (TREE_TYPE (arg));
10208 if (argmode != opmode)
10209 arg = build1 (NOP_EXPR, optype, arg);
10210 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
10211 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10212 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10218 pat = (*insn_data[d->icode].genfun) (op[0]);
10221 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10224 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10227 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10230 gcc_unreachable ();
10239 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
10241 rtx sel0 = const0_rtx;
10242 rtx sel1 = const1_rtx;
10243 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
10244 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10246 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10247 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10251 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
10253 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10255 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10256 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
10259 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
10260 We can allow any mode in any general register. The special registers
10261 only allow SImode. Don't allow any mode in the PR.
10263 We cannot hold DCmode values in the XD registers because alter_reg
10264 handles subregs of them incorrectly. We could work around this by
10265 spacing the XD registers like the DR registers, but this would require
10266 additional memory in every compilation to hold larger register vectors.
10267 We could hold SFmode / SCmode values in XD registers, but that
10268 would require a tertiary reload when reloading from / to memory,
10269 and a secondary reload to reload from / to general regs; that
10270 seems to be a loosing proposition.
10272 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10273 it won't be ferried through GP registers first. */
10276 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10278 if (SPECIAL_REGISTER_P (regno))
10279 return mode == SImode;
10281 if (regno == FPUL_REG)
10282 return (mode == SImode || mode == SFmode);
10284 if (FP_REGISTER_P (regno) && mode == SFmode)
10287 if (mode == V2SFmode)
10289 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
10290 || GENERAL_REGISTER_P (regno)))
10296 if (mode == V4SFmode)
10298 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
10299 || GENERAL_REGISTER_P (regno))
10305 if (mode == V16SFmode)
10307 if (TARGET_SHMEDIA)
10309 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
10315 return regno == FIRST_XD_REG;
10318 if (FP_REGISTER_P (regno))
10322 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
10323 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
10326 && (mode == DFmode || mode == DImode
10327 || mode == V2SFmode || mode == TImode)))
10328 && ((regno - FIRST_FP_REG) & 1) == 0)
10329 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
10330 && ((regno - FIRST_FP_REG) & 3) == 0))
10336 if (XD_REGISTER_P (regno))
10337 return mode == DFmode;
10339 if (TARGET_REGISTER_P (regno))
10340 return (mode == DImode || mode == SImode || mode == PDImode);
10342 if (regno == PR_REG)
10343 return mode == SImode;
10345 if (regno == FPSCR_REG)
10346 return mode == PSImode;
10348 /* FIXME. This works around PR target/37633 for -O0. */
10349 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
10351 unsigned int n = GET_MODE_SIZE (mode) / 8;
10353 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
10354 && regno <= FIRST_GENERAL_REG + 14)
10361 /* Return the class of registers for which a mode change from FROM to TO
10364 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
10365 enum reg_class rclass)
10367 /* We want to enable the use of SUBREGs as a means to
10368 VEC_SELECT a single element of a vector. */
10369 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10370 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
10372 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10374 if (TARGET_LITTLE_ENDIAN)
10376 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10377 return reg_classes_intersect_p (DF_REGS, rclass);
10381 if (GET_MODE_SIZE (from) < 8)
10382 return reg_classes_intersect_p (DF_HI_REGS, rclass);
10389 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10390 that label is used. */
10393 sh_mark_label (rtx address, int nuses)
10395 if (GOTOFF_P (address))
10397 /* Extract the label or symbol. */
10398 address = XEXP (address, 0);
10399 if (GET_CODE (address) == PLUS)
10400 address = XEXP (address, 0);
10401 address = XVECEXP (address, 0, 0);
10403 if (GET_CODE (address) == LABEL_REF
10404 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
10405 LABEL_NUSES (XEXP (address, 0)) += nuses;
10408 /* Compute extra cost of moving data between one register class
10411 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10412 uses this information. Hence, the general register <-> floating point
10413 register information here is not used for SFmode. */
10416 sh_register_move_cost (enum machine_mode mode,
10417 enum reg_class srcclass, enum reg_class dstclass)
10419 if (dstclass == T_REGS || dstclass == PR_REGS)
10422 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10425 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
10426 && REGCLASS_HAS_FP_REG (srcclass)
10427 && REGCLASS_HAS_FP_REG (dstclass))
10430 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10431 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10433 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
10434 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
10437 if ((REGCLASS_HAS_FP_REG (dstclass)
10438 && REGCLASS_HAS_GENERAL_REG (srcclass))
10439 || (REGCLASS_HAS_GENERAL_REG (dstclass)
10440 && REGCLASS_HAS_FP_REG (srcclass)))
10441 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
10442 * ((GET_MODE_SIZE (mode) + 7) / 8U));
10444 if ((dstclass == FPUL_REGS
10445 && REGCLASS_HAS_GENERAL_REG (srcclass))
10446 || (srcclass == FPUL_REGS
10447 && REGCLASS_HAS_GENERAL_REG (dstclass)))
10450 if ((dstclass == FPUL_REGS
10451 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
10452 || (srcclass == FPUL_REGS
10453 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
10456 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10457 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10460 /* ??? ptabs faults on (value & 0x3) == 0x3 */
10462 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
10464 if (sh_gettrcost >= 0)
10465 return sh_gettrcost;
10466 else if (!TARGET_PT_FIXED)
10470 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10471 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10476 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
10477 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
10478 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
10480 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
10483 static rtx emit_load_ptr (rtx, rtx);
10486 emit_load_ptr (rtx reg, rtx addr)
10488 rtx mem = gen_const_mem (ptr_mode, addr);
10490 if (Pmode != ptr_mode)
10491 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
10492 return emit_move_insn (reg, mem);
10496 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10497 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10500 CUMULATIVE_ARGS cum;
10501 int structure_value_byref = 0;
10502 rtx this_rtx, this_value, sibcall, insns, funexp;
10503 tree funtype = TREE_TYPE (function);
10504 int simple_add = CONST_OK_FOR_ADD (delta);
10506 rtx scratch0, scratch1, scratch2;
10509 reload_completed = 1;
10510 epilogue_completed = 1;
10511 current_function_uses_only_leaf_regs = 1;
10513 emit_note (NOTE_INSN_PROLOGUE_END);
10515 /* Find the "this" pointer. We have such a wide range of ABIs for the
10516 SH that it's best to do this completely machine independently.
10517 "this" is passed as first argument, unless a structure return pointer
10518 comes first, in which case "this" comes second. */
10519 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
10520 #ifndef PCC_STATIC_STRUCT_RETURN
10521 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10522 structure_value_byref = 1;
10523 #endif /* not PCC_STATIC_STRUCT_RETURN */
10524 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
10526 tree ptype = build_pointer_type (TREE_TYPE (funtype));
10528 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
10530 this_rtx = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
10532 /* For SHcompact, we only have r0 for a scratch register: r1 is the
10533 static chain pointer (even if you can't have nested virtual functions
10534 right now, someone might implement them sometime), and the rest of the
10535 registers are used for argument passing, are callee-saved, or reserved. */
10536 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
10537 -ffixed-reg has been used. */
10538 if (! call_used_regs[0] || fixed_regs[0])
10539 error ("r0 needs to be available as a call-clobbered register");
10540 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
10543 if (call_used_regs[1] && ! fixed_regs[1])
10544 scratch1 = gen_rtx_REG (ptr_mode, 1);
10545 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
10546 pointing where to return struct values. */
10547 if (call_used_regs[3] && ! fixed_regs[3])
10548 scratch2 = gen_rtx_REG (Pmode, 3);
10550 else if (TARGET_SHMEDIA)
10552 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
10553 if (i != REGNO (scratch0) &&
10554 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
10556 scratch1 = gen_rtx_REG (ptr_mode, i);
10559 if (scratch1 == scratch0)
10560 error ("Need a second call-clobbered general purpose register");
10561 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
10562 if (call_used_regs[i] && ! fixed_regs[i])
10564 scratch2 = gen_rtx_REG (Pmode, i);
10567 if (scratch2 == scratch0)
10568 error ("Need a call-clobbered target register");
10571 this_value = plus_constant (this_rtx, delta);
10573 && (simple_add || scratch0 != scratch1)
10574 && strict_memory_address_p (ptr_mode, this_value))
10576 emit_load_ptr (scratch0, this_value);
10581 ; /* Do nothing. */
10582 else if (simple_add)
10583 emit_move_insn (this_rtx, this_value);
10586 emit_move_insn (scratch1, GEN_INT (delta));
10587 emit_insn (gen_add2_insn (this_rtx, scratch1));
10595 emit_load_ptr (scratch0, this_rtx);
10597 offset_addr = plus_constant (scratch0, vcall_offset);
10598 if (strict_memory_address_p (ptr_mode, offset_addr))
10599 ; /* Do nothing. */
10600 else if (! TARGET_SH5 && scratch0 != scratch1)
10602 /* scratch0 != scratch1, and we have indexed loads. Get better
10603 schedule by loading the offset into r1 and using an indexed
10604 load - then the load of r1 can issue before the load from
10605 (this_rtx + delta) finishes. */
10606 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10607 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
10609 else if (CONST_OK_FOR_ADD (vcall_offset))
10611 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
10612 offset_addr = scratch0;
10614 else if (scratch0 != scratch1)
10616 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10617 emit_insn (gen_add2_insn (scratch0, scratch1));
10618 offset_addr = scratch0;
10621 gcc_unreachable (); /* FIXME */
10622 emit_load_ptr (scratch0, offset_addr);
10624 if (Pmode != ptr_mode)
10625 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
10626 emit_insn (gen_add2_insn (this_rtx, scratch0));
10629 /* Generate a tail call to the target function. */
10630 if (! TREE_USED (function))
10632 assemble_external (function);
10633 TREE_USED (function) = 1;
10635 funexp = XEXP (DECL_RTL (function), 0);
10636 /* If the function is overridden, so is the thunk, hence we don't
10637 need GOT addressing even if this is a public symbol. */
10639 if (TARGET_SH1 && ! flag_weak)
10640 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
10643 if (TARGET_SH2 && flag_pic)
10645 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
10646 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
10650 if (TARGET_SHMEDIA && flag_pic)
10652 funexp = gen_sym2PIC (funexp);
10653 PUT_MODE (funexp, Pmode);
10655 emit_move_insn (scratch2, funexp);
10656 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
10657 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
10659 sibcall = emit_call_insn (sibcall);
10660 SIBLING_CALL_P (sibcall) = 1;
10661 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
10664 /* Run just enough of rest_of_compilation to do scheduling and get
10665 the insns emitted. Note that use_thunk calls
10666 assemble_start_function and assemble_end_function. */
10668 insn_locators_alloc ();
10669 insns = get_insns ();
10675 split_all_insns_noflow ();
10680 if (optimize > 0 && flag_delayed_branch)
10681 dbr_schedule (insns);
10683 shorten_branches (insns);
10684 final_start_function (insns, file, 1);
10685 final (insns, file, 1);
10686 final_end_function ();
10687 free_after_compilation (cfun);
10689 reload_completed = 0;
10690 epilogue_completed = 0;
10694 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
10698 /* If this is not an ordinary function, the name usually comes from a
10699 string literal or an sprintf buffer. Make sure we use the same
10700 string consistently, so that cse will be able to unify address loads. */
10701 if (kind != FUNCTION_ORDINARY)
10702 name = IDENTIFIER_POINTER (get_identifier (name));
10703 sym = gen_rtx_SYMBOL_REF (Pmode, name);
10704 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
10708 case FUNCTION_ORDINARY:
10712 rtx reg = target ? target : gen_reg_rtx (Pmode);
10714 emit_insn (gen_symGOT2reg (reg, sym));
10720 /* ??? To allow cse to work, we use GOTOFF relocations.
10721 we could add combiner patterns to transform this into
10722 straight pc-relative calls with sym2PIC / bsrf when
10723 label load and function call are still 1:1 and in the
10724 same basic block during combine. */
10725 rtx reg = target ? target : gen_reg_rtx (Pmode);
10727 emit_insn (gen_symGOTOFF2reg (reg, sym));
10732 if (target && sym != target)
10734 emit_move_insn (target, sym);
10740 /* Find the number of a general purpose register in S. */
10742 scavenge_reg (HARD_REG_SET *s)
10745 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
10746 if (TEST_HARD_REG_BIT (*s, r))
10752 sh_get_pr_initial_val (void)
10756 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
10757 PR register on SHcompact, because it might be clobbered by the prologue.
10758 We check first if that is known to be the case. */
10759 if (TARGET_SHCOMPACT
10760 && ((crtl->args.info.call_cookie
10761 & ~ CALL_COOKIE_RET_TRAMP (1))
10762 || crtl->saves_all_registers))
10763 return gen_frame_mem (SImode, return_address_pointer_rtx);
10765 /* If we haven't finished rtl generation, there might be a nonlocal label
10766 that we haven't seen yet.
10767 ??? get_hard_reg_initial_val fails if it is called after register
10768 allocation has started, unless it has been called before for the
10769 same register. And even then, we end in trouble if we didn't use
10770 the register in the same basic block before. So call
10771 get_hard_reg_initial_val now and wrap it in an unspec if we might
10772 need to replace it. */
10773 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
10774 combine can put the pseudo returned by get_hard_reg_initial_val into
10775 instructions that need a general purpose registers, which will fail to
10776 be recognized when the pseudo becomes allocated to PR. */
10778 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
10780 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
10785 sh_expand_t_scc (enum rtx_code code, rtx target)
10787 rtx result = target;
10790 if (GET_CODE (sh_compare_op0) != REG || REGNO (sh_compare_op0) != T_REG
10791 || GET_CODE (sh_compare_op1) != CONST_INT)
10793 if (GET_CODE (result) != REG)
10794 result = gen_reg_rtx (SImode);
10795 val = INTVAL (sh_compare_op1);
10796 if ((code == EQ && val == 1) || (code == NE && val == 0))
10797 emit_insn (gen_movt (result));
10798 else if (TARGET_SH2A && ((code == EQ && val == 0)
10799 || (code == NE && val == 1)))
10800 emit_insn (gen_movrt (result));
10801 else if ((code == EQ && val == 0) || (code == NE && val == 1))
10803 emit_clobber (result);
10804 emit_insn (gen_subc (result, result, result));
10805 emit_insn (gen_addsi3 (result, result, const1_rtx));
10807 else if (code == EQ || code == NE)
10808 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
10811 if (result != target)
10812 emit_move_insn (target, result);
10816 /* INSN is an sfunc; return the rtx that describes the address used. */
10818 extract_sfunc_addr (rtx insn)
10820 rtx pattern, part = NULL_RTX;
10823 pattern = PATTERN (insn);
10824 len = XVECLEN (pattern, 0);
10825 for (i = 0; i < len; i++)
10827 part = XVECEXP (pattern, 0, i);
10828 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
10829 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
10830 return XEXP (part, 0);
10832 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
10833 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
10836 /* Verify that the register in use_sfunc_addr still agrees with the address
10837 used in the sfunc. This prevents fill_slots_from_thread from changing
10839 INSN is the use_sfunc_addr instruction, and REG is the register it
10842 check_use_sfunc_addr (rtx insn, rtx reg)
10844 /* Search for the sfunc. It should really come right after INSN. */
10845 while ((insn = NEXT_INSN (insn)))
10847 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
10849 if (! INSN_P (insn))
10852 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
10853 insn = XVECEXP (PATTERN (insn), 0, 0);
10854 if (GET_CODE (PATTERN (insn)) != PARALLEL
10855 || get_attr_type (insn) != TYPE_SFUNC)
10857 return rtx_equal_p (extract_sfunc_addr (insn), reg);
10859 gcc_unreachable ();
10862 /* This function returns a constant rtx that represents pi / 2**15 in
10863 SFmode. it's used to scale SFmode angles, in radians, to a
10864 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
10865 maps to 0x10000). */
10867 static GTY(()) rtx sh_fsca_sf2int_rtx;
10870 sh_fsca_sf2int (void)
10872 if (! sh_fsca_sf2int_rtx)
10874 REAL_VALUE_TYPE rv;
10876 real_from_string (&rv, "10430.378350470453");
10877 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
10880 return sh_fsca_sf2int_rtx;
10883 /* This function returns a constant rtx that represents pi / 2**15 in
10884 DFmode. it's used to scale DFmode angles, in radians, to a
10885 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
10886 maps to 0x10000). */
10888 static GTY(()) rtx sh_fsca_df2int_rtx;
10891 sh_fsca_df2int (void)
10893 if (! sh_fsca_df2int_rtx)
10895 REAL_VALUE_TYPE rv;
10897 real_from_string (&rv, "10430.378350470453");
10898 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
10901 return sh_fsca_df2int_rtx;
10904 /* This function returns a constant rtx that represents 2**15 / pi in
10905 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
10906 of a full circle back to a SFmode value, i.e., 0x10000 maps to
10909 static GTY(()) rtx sh_fsca_int2sf_rtx;
10912 sh_fsca_int2sf (void)
10914 if (! sh_fsca_int2sf_rtx)
10916 REAL_VALUE_TYPE rv;
10918 real_from_string (&rv, "9.587379924285257e-5");
10919 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
10922 return sh_fsca_int2sf_rtx;
10925 /* Initialize the CUMULATIVE_ARGS structure. */
10928 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
10930 rtx libname ATTRIBUTE_UNUSED,
10932 signed int n_named_args,
10933 enum machine_mode mode)
10935 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
10936 pcum->free_single_fp_reg = 0;
10937 pcum->stack_regs = 0;
10938 pcum->byref_regs = 0;
10940 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
10942 /* XXX - Should we check TARGET_HITACHI here ??? */
10943 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
10947 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
10948 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
10949 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
10950 pcum->arg_count [(int) SH_ARG_INT]
10951 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
10954 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
10955 && pcum->arg_count [(int) SH_ARG_INT] == 0
10956 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
10957 ? int_size_in_bytes (TREE_TYPE (fntype))
10958 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
10959 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
10960 == FIRST_RET_REG));
10964 pcum->arg_count [(int) SH_ARG_INT] = 0;
10965 pcum->prototype_p = FALSE;
10966 if (mode != VOIDmode)
10968 pcum->call_cookie =
10969 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
10970 && GET_MODE_SIZE (mode) > 4
10971 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
10973 /* If the default ABI is the Renesas ABI then all library
10974 calls must assume that the library will be using the
10975 Renesas ABI. So if the function would return its result
10976 in memory then we must force the address of this memory
10977 block onto the stack. Ideally we would like to call
10978 targetm.calls.return_in_memory() here but we do not have
10979 the TYPE or the FNDECL available so we synthesize the
10980 contents of that function as best we can. */
10982 (TARGET_DEFAULT & MASK_HITACHI)
10983 && (mode == BLKmode
10984 || (GET_MODE_SIZE (mode) > 4
10985 && !(mode == DFmode
10986 && TARGET_FPU_DOUBLE)));
10990 pcum->call_cookie = 0;
10991 pcum->force_mem = FALSE;
10996 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
10997 not enter into CONST_DOUBLE for the replace.
10999 Note that copying is not done so X must not be shared unless all copies
11000 are to be modified.
11002 This is like replace_rtx, except that we operate on N_REPLACEMENTS
11003 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
11004 replacements[n*2+1] - and that we take mode changes into account.
11006 If a replacement is ambiguous, return NULL_RTX.
11008 If MODIFY is zero, don't modify any rtl in place,
11009 just return zero or nonzero for failure / success. */
11012 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
11017 /* The following prevents loops occurrence when we change MEM in
11018 CONST_DOUBLE onto the same CONST_DOUBLE. */
11019 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
11022 for (i = n_replacements - 1; i >= 0 ; i--)
11023 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
11024 return replacements[i*2+1];
11026 /* Allow this function to make replacements in EXPR_LISTs. */
11030 if (GET_CODE (x) == SUBREG)
11032 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
11033 n_replacements, modify);
11035 if (GET_CODE (new_rtx) == CONST_INT)
11037 x = simplify_subreg (GET_MODE (x), new_rtx,
11038 GET_MODE (SUBREG_REG (x)),
11044 SUBREG_REG (x) = new_rtx;
11048 else if (GET_CODE (x) == REG)
11050 unsigned regno = REGNO (x);
11051 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
11052 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11053 rtx result = NULL_RTX;
11055 for (i = n_replacements - 1; i >= 0; i--)
11057 rtx from = replacements[i*2];
11058 rtx to = replacements[i*2+1];
11059 unsigned from_regno, from_nregs, to_regno, new_regno;
11061 if (GET_CODE (from) != REG)
11063 from_regno = REGNO (from);
11064 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
11065 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
11066 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
11068 if (regno < from_regno
11069 || regno + nregs > from_regno + nregs
11070 || GET_CODE (to) != REG
11073 to_regno = REGNO (to);
11074 if (to_regno < FIRST_PSEUDO_REGISTER)
11076 new_regno = regno + to_regno - from_regno;
11077 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
11080 result = gen_rtx_REG (GET_MODE (x), new_regno);
11082 else if (GET_MODE (x) <= GET_MODE (to))
11083 result = gen_lowpart_common (GET_MODE (x), to);
11085 result = gen_lowpart_SUBREG (GET_MODE (x), to);
11088 return result ? result : x;
11090 else if (GET_CODE (x) == ZERO_EXTEND)
11092 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
11093 n_replacements, modify);
11095 if (GET_CODE (new_rtx) == CONST_INT)
11097 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
11098 new_rtx, GET_MODE (XEXP (x, 0)));
11103 XEXP (x, 0) = new_rtx;
11108 fmt = GET_RTX_FORMAT (GET_CODE (x));
11109 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
11115 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
11116 n_replacements, modify);
11120 XEXP (x, i) = new_rtx;
11122 else if (fmt[i] == 'E')
11123 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11125 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
11126 n_replacements, modify);
11130 XVECEXP (x, i, j) = new_rtx;
11138 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
11140 enum rtx_code code = TRUNCATE;
11142 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11144 rtx inner = XEXP (x, 0);
11145 enum machine_mode inner_mode = GET_MODE (inner);
11147 if (inner_mode == mode)
11149 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11151 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11152 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11154 code = GET_CODE (x);
11158 return gen_rtx_fmt_e (code, mode, x);
11161 /* called via for_each_rtx after reload, to clean up truncates of
11162 registers that span multiple actual hard registers. */
11164 shmedia_cleanup_truncate (rtx *p, void *n_changes)
11168 if (GET_CODE (x) != TRUNCATE)
11171 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && GET_CODE (reg) == REG)
11173 enum machine_mode reg_mode = GET_MODE (reg);
11174 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
11175 subreg_lowpart_offset (DImode, reg_mode));
11176 *(int*) n_changes += 1;
11182 /* Load and store depend on the highpart of the address. However,
11183 set_attr_alternative does not give well-defined results before reload,
11184 so we must look at the rtl ourselves to see if any of the feeding
11185 registers is used in a memref. */
11187 /* Called by sh_contains_memref_p via for_each_rtx. */
11189 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
11191 return (GET_CODE (*loc) == MEM);
11194 /* Return nonzero iff INSN contains a MEM. */
11196 sh_contains_memref_p (rtx insn)
11198 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11201 /* Return nonzero iff INSN loads a banked register. */
11203 sh_loads_bankedreg_p (rtx insn)
11205 if (GET_CODE (PATTERN (insn)) == SET)
11207 rtx op = SET_DEST (PATTERN(insn));
11208 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11215 /* FNADDR is the MEM expression from a call expander. Return an address
11216 to use in an SHmedia insn pattern. */
11218 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11222 fnaddr = XEXP (fnaddr, 0);
11223 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11224 if (flag_pic && is_sym)
11226 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11228 rtx reg = gen_reg_rtx (Pmode);
11230 /* We must not use GOTPLT for sibcalls, because PIC_REG
11231 must be restored before the PLT code gets to run. */
11233 emit_insn (gen_symGOT2reg (reg, fnaddr));
11235 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11240 fnaddr = gen_sym2PIC (fnaddr);
11241 PUT_MODE (fnaddr, Pmode);
11244 /* If ptabs might trap, make this visible to the rest of the compiler.
11245 We generally assume that symbols pertain to valid locations, but
11246 it is possible to generate invalid symbols with asm or linker tricks.
11247 In a list of functions where each returns its successor, an invalid
11248 symbol might denote an empty list. */
11249 if (!TARGET_PT_FIXED
11250 && (!is_sym || TARGET_INVALID_SYMBOLS)
11251 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11253 rtx tr = gen_reg_rtx (PDImode);
11255 emit_insn (gen_ptabs (tr, fnaddr));
11258 else if (! target_reg_operand (fnaddr, Pmode))
11259 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11264 sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
11265 enum machine_mode mode, secondary_reload_info *sri)
11269 if (REGCLASS_HAS_FP_REG (rclass)
11270 && ! TARGET_SHMEDIA
11271 && immediate_operand ((x), mode)
11272 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11273 && mode == SFmode && fldi_ok ()))
11277 sri->icode = CODE_FOR_reload_insf__frn;
11280 sri->icode = CODE_FOR_reload_indf__frn;
11283 /* ??? If we knew that we are in the appropriate mode -
11284 single precision - we could use a reload pattern directly. */
11289 if (rclass == FPUL_REGS
11290 && ((GET_CODE (x) == REG
11291 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11292 || REGNO (x) == T_REG))
11293 || GET_CODE (x) == PLUS))
11294 return GENERAL_REGS;
11295 if (rclass == FPUL_REGS && immediate_operand (x, mode))
11297 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11298 return GENERAL_REGS;
11299 else if (mode == SFmode)
11301 sri->icode = CODE_FOR_reload_insi__i_fpul;
11304 if (rclass == FPSCR_REGS
11305 && ((GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11306 || (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PLUS)))
11307 return GENERAL_REGS;
11308 if (REGCLASS_HAS_FP_REG (rclass)
11310 && immediate_operand (x, mode)
11311 && x != CONST0_RTX (GET_MODE (x))
11312 && GET_MODE (x) != V4SFmode)
11313 return GENERAL_REGS;
11314 if ((mode == QImode || mode == HImode)
11315 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11317 sri->icode = ((mode == QImode)
11318 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11321 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
11322 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
11323 return TARGET_REGS;
11324 } /* end of input-only processing. */
11326 if (((REGCLASS_HAS_FP_REG (rclass)
11327 && (GET_CODE (x) == REG
11328 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11329 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11330 && TARGET_FMOVD))))
11331 || (REGCLASS_HAS_GENERAL_REG (rclass)
11332 && GET_CODE (x) == REG
11333 && FP_REGISTER_P (REGNO (x))))
11334 && ! TARGET_SHMEDIA
11335 && (mode == SFmode || mode == SImode))
11337 if ((rclass == FPUL_REGS
11338 || (REGCLASS_HAS_FP_REG (rclass)
11339 && ! TARGET_SHMEDIA && mode == SImode))
11340 && (GET_CODE (x) == MEM
11341 || (GET_CODE (x) == REG
11342 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11343 || REGNO (x) == T_REG
11344 || system_reg_operand (x, VOIDmode)))))
11346 if (rclass == FPUL_REGS)
11347 return GENERAL_REGS;
11350 if ((rclass == TARGET_REGS
11351 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
11352 && !satisfies_constraint_Csy (x)
11353 && (GET_CODE (x) != REG || ! GENERAL_REGISTER_P (REGNO (x))))
11354 return GENERAL_REGS;
11355 if ((rclass == MAC_REGS || rclass == PR_REGS)
11356 && GET_CODE (x) == REG && ! GENERAL_REGISTER_P (REGNO (x))
11357 && rclass != REGNO_REG_CLASS (REGNO (x)))
11358 return GENERAL_REGS;
11359 if (rclass != GENERAL_REGS && GET_CODE (x) == REG
11360 && TARGET_REGISTER_P (REGNO (x)))
11361 return GENERAL_REGS;
11365 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;