1 /* Output routines for GCC for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
28 #include "insn-config.h"
36 #include "hard-reg-set.h"
38 #include "insn-attr.h"
42 #include "integrate.h"
45 #include "target-def.h"
47 #include "langhooks.h"
49 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
51 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
52 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
54 /* These are some macros to abstract register modes. */
55 #define CONST_OK_FOR_ADD(size) \
56 (TARGET_SHMEDIA ? CONST_OK_FOR_P (size) : CONST_OK_FOR_I (size))
57 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
58 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
59 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
61 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
62 int current_function_interrupt;
64 /* ??? The pragma interrupt support will not work for SH3. */
65 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
66 output code for the next function appropriate for an interrupt handler. */
69 /* This is set by the trap_exit attribute for functions. It specifies
70 a trap number to be used in a trapa instruction at function exit
71 (instead of an rte instruction). */
74 /* This is used by the sp_switch attribute for functions. It specifies
75 a variable holding the address of the stack the interrupt function
76 should switch to/from at entry/exit. */
79 /* This is set by #pragma trapa, and is similar to the above, except that
80 the compiler doesn't emit code to preserve all registers. */
81 static int pragma_trapa;
83 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
84 which has a separate set of low regs for User and Supervisor modes.
85 This should only be used for the lowest level of interrupts. Higher levels
86 of interrupts must save the registers in case they themselves are
88 int pragma_nosave_low_regs;
90 /* This is used for communication between SETUP_INCOMING_VARARGS and
91 sh_expand_prologue. */
92 int current_function_anonymous_args;
94 /* Global variables for machine-dependent things. */
96 /* Which cpu are we scheduling for. */
97 enum processor_type sh_cpu;
99 /* Saved operands from the last compare to use when we generate an scc
105 /* Provides the class number of the smallest class containing
108 int regno_reg_class[FIRST_PSEUDO_REGISTER] =
110 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
111 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
112 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
113 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
114 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
127 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
128 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
129 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
130 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
143 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
144 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
145 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
146 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
147 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
151 char sh_register_names[FIRST_PSEUDO_REGISTER] \
152 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
154 char sh_additional_register_names[ADDREGNAMES_SIZE] \
155 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
156 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
158 /* Provide reg_class from a letter such as appears in the machine
159 description. *: target independently reserved letter.
160 reg_class_from_letter['e'] is set to NO_REGS for TARGET_FMOVD. */
162 enum reg_class reg_class_from_letter[] =
164 /* a */ ALL_REGS, /* b */ TARGET_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
165 /* e */ FP_REGS, /* f */ FP_REGS, /* g **/ NO_REGS, /* h */ NO_REGS,
166 /* i **/ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
167 /* m **/ NO_REGS, /* n **/ NO_REGS, /* o **/ NO_REGS, /* p **/ NO_REGS,
168 /* q */ NO_REGS, /* r **/ NO_REGS, /* s **/ NO_REGS, /* t */ T_REGS,
169 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
170 /* y */ FPUL_REGS, /* z */ R0_REGS
173 int assembler_dialect;
175 static void split_branches PARAMS ((rtx));
176 static int branch_dest PARAMS ((rtx));
177 static void force_into PARAMS ((rtx, rtx));
178 static void print_slot PARAMS ((rtx));
179 static rtx add_constant PARAMS ((rtx, enum machine_mode, rtx));
180 static void dump_table PARAMS ((rtx));
181 static int hi_const PARAMS ((rtx));
182 static int broken_move PARAMS ((rtx));
183 static int mova_p PARAMS ((rtx));
184 static rtx find_barrier PARAMS ((int, rtx, rtx));
185 static int noncall_uses_reg PARAMS ((rtx, rtx, rtx *));
186 static rtx gen_block_redirect PARAMS ((rtx, int, int));
187 static void output_stack_adjust PARAMS ((int, rtx, int, rtx (*) (rtx)));
188 static rtx frame_insn PARAMS ((rtx));
189 static rtx push PARAMS ((int));
190 static void pop PARAMS ((int));
191 static void push_regs PARAMS ((HOST_WIDE_INT *));
192 static void calc_live_regs PARAMS ((int *, HOST_WIDE_INT *));
193 static void mark_use PARAMS ((rtx, rtx *));
194 static HOST_WIDE_INT rounded_frame_size PARAMS ((int));
195 static rtx mark_constant_pool_use PARAMS ((rtx));
196 const struct attribute_spec sh_attribute_table[];
197 static tree sh_handle_interrupt_handler_attribute PARAMS ((tree *, tree, tree, int, bool *));
198 static tree sh_handle_sp_switch_attribute PARAMS ((tree *, tree, tree, int, bool *));
199 static tree sh_handle_trap_exit_attribute PARAMS ((tree *, tree, tree, int, bool *));
200 static void sh_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
201 static void sh_insert_attributes PARAMS ((tree, tree *));
202 static int sh_adjust_cost PARAMS ((rtx, rtx, rtx, int));
203 static int sh_use_dfa_interface PARAMS ((void));
204 static int sh_issue_rate PARAMS ((void));
205 static bool sh_function_ok_for_sibcall PARAMS ((tree, tree));
207 static bool sh_cannot_modify_jumps_p PARAMS ((void));
208 static bool sh_ms_bitfield_layout_p PARAMS ((tree));
210 static void sh_encode_section_info PARAMS ((tree, int));
211 static const char *sh_strip_name_encoding PARAMS ((const char *));
212 static void sh_init_builtins PARAMS ((void));
213 static void sh_media_init_builtins PARAMS ((void));
214 static rtx sh_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
215 static int flow_dependent_p PARAMS ((rtx, rtx));
216 static void flow_dependent_p_1 PARAMS ((rtx, rtx, void *));
217 static int shiftcosts PARAMS ((rtx));
218 static int andcosts PARAMS ((rtx));
219 static int addsubcosts PARAMS ((rtx));
220 static int multcosts PARAMS ((rtx));
221 static bool unspec_caller_rtx_p PARAMS ((rtx));
222 static bool sh_cannot_copy_insn_p PARAMS ((rtx));
223 static bool sh_rtx_costs PARAMS ((rtx, int, int, int *));
224 static int sh_address_cost PARAMS ((rtx));
226 /* Initialize the GCC target structure. */
227 #undef TARGET_ATTRIBUTE_TABLE
228 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
230 /* The next two are used for debug info when compiling with -gdwarf. */
231 #undef TARGET_ASM_UNALIGNED_HI_OP
232 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
233 #undef TARGET_ASM_UNALIGNED_SI_OP
234 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
236 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
237 #undef TARGET_ASM_UNALIGNED_DI_OP
238 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
239 #undef TARGET_ASM_ALIGNED_DI_OP
240 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
242 #undef TARGET_ASM_FUNCTION_EPILOGUE
243 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
245 #undef TARGET_INSERT_ATTRIBUTES
246 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
248 #undef TARGET_SCHED_ADJUST_COST
249 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
251 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
252 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
254 #undef TARGET_SCHED_ISSUE_RATE
255 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
257 #undef TARGET_CANNOT_MODIFY_JUMPS_P
258 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
260 #undef TARGET_MS_BITFIELD_LAYOUT_P
261 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
263 #undef TARGET_ENCODE_SECTION_INFO
264 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
265 #undef TARGET_STRIP_NAME_ENCODING
266 #define TARGET_STRIP_NAME_ENCODING sh_strip_name_encoding
268 #undef TARGET_INIT_BUILTINS
269 #define TARGET_INIT_BUILTINS sh_init_builtins
270 #undef TARGET_EXPAND_BUILTIN
271 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
273 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
274 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
276 #undef TARGET_CANNOT_COPY_INSN_P
277 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
278 #undef TARGET_RTX_COSTS
279 #define TARGET_RTX_COSTS sh_rtx_costs
280 #undef TARGET_ADDRESS_COST
281 #define TARGET_ADDRESS_COST sh_address_cost
283 struct gcc_target targetm = TARGET_INITIALIZER;
285 /* Print the operand address in x to the stream. */
288 print_operand_address (stream, x)
292 switch (GET_CODE (x))
296 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
301 rtx base = XEXP (x, 0);
302 rtx index = XEXP (x, 1);
304 switch (GET_CODE (index))
307 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
308 reg_names[true_regnum (base)]);
314 int base_num = true_regnum (base);
315 int index_num = true_regnum (index);
317 fprintf (stream, "@(r0,%s)",
318 reg_names[MAX (base_num, index_num)]);
330 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
334 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
338 x = mark_constant_pool_use (x);
339 output_addr_const (stream, x);
344 /* Print operand x (an rtx) in assembler syntax to file stream
345 according to modifier code.
347 '.' print a .s if insn needs delay slot
348 ',' print LOCAL_LABEL_PREFIX
349 '@' print trap, rte or rts depending upon pragma interruptness
350 '#' output a nop if there is nothing to put in the delay slot
351 ''' print likelyhood suffix (/u for unlikely).
352 'O' print a constant without the #
353 'R' print the LSW of a dp value - changes if in little endian
354 'S' print the MSW of a dp value - changes if in little endian
355 'T' print the next word of a dp value - same as 'R' in big endian mode.
356 'M' print an `x' if `m' will print `base,index'.
357 'N' print 'r63' if the operand is (const_int 0).
358 'm' print a pair `base,offset' or `base,index', for LD and ST.
359 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
360 'o' output an operator. */
363 print_operand (stream, x, code)
372 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
373 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
374 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
377 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
381 fprintf (stream, "trapa #%d", trap_exit);
382 else if (sh_cfun_interrupt_handler_p ())
383 fprintf (stream, "rte");
385 fprintf (stream, "rts");
388 /* Output a nop if there's nothing in the delay slot. */
389 if (dbr_sequence_length () == 0)
390 fprintf (stream, "\n\tnop");
394 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
396 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
397 fputs ("/u", stream);
401 x = mark_constant_pool_use (x);
402 output_addr_const (stream, x);
405 fputs (reg_names[REGNO (x) + LSW], (stream));
408 fputs (reg_names[REGNO (x) + MSW], (stream));
411 /* Next word of a double. */
412 switch (GET_CODE (x))
415 fputs (reg_names[REGNO (x) + 1], (stream));
418 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
419 && GET_CODE (XEXP (x, 0)) != POST_INC)
420 x = adjust_address (x, SImode, 4);
421 print_operand_address (stream, XEXP (x, 0));
428 switch (GET_CODE (x))
430 case PLUS: fputs ("add", stream); break;
431 case MINUS: fputs ("sub", stream); break;
432 case MULT: fputs ("mul", stream); break;
433 case DIV: fputs ("div", stream); break;
434 case EQ: fputs ("eq", stream); break;
435 case NE: fputs ("ne", stream); break;
436 case GT: case LT: fputs ("gt", stream); break;
437 case GE: case LE: fputs ("ge", stream); break;
438 case GTU: case LTU: fputs ("gtu", stream); break;
439 case GEU: case LEU: fputs ("geu", stream); break;
445 if (GET_CODE (x) == MEM
446 && GET_CODE (XEXP (x, 0)) == PLUS
447 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
448 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
453 if (GET_CODE (x) != MEM)
456 switch (GET_CODE (x))
460 print_operand (stream, x, 0);
461 fputs (", 0", stream);
465 print_operand (stream, XEXP (x, 0), 0);
466 fputs (", ", stream);
467 print_operand (stream, XEXP (x, 1), 0);
476 if (x == CONST0_RTX (GET_MODE (x)))
478 fprintf ((stream), "r63");
483 if (GET_CODE (x) == CONST_INT)
485 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
492 switch (GET_CODE (x))
494 /* FIXME: We need this on SHmedia32 because reload generates
495 some sign-extended HI or QI loads into DImode registers
496 but, because Pmode is SImode, the address ends up with a
497 subreg:SI of the DImode register. Maybe reload should be
498 fixed so as to apply alter_subreg to such loads? */
500 if (SUBREG_BYTE (x) != 0
501 || GET_CODE (SUBREG_REG (x)) != REG)
508 if (FP_REGISTER_P (REGNO (x))
509 && GET_MODE (x) == V16SFmode)
510 fprintf ((stream), "mtrx%s", reg_names[REGNO (x)] + 2);
511 else if (FP_REGISTER_P (REGNO (x))
512 && GET_MODE (x) == V4SFmode)
513 fprintf ((stream), "fv%s", reg_names[REGNO (x)] + 2);
514 else if (GET_CODE (x) == REG
515 && GET_MODE (x) == V2SFmode)
516 fprintf ((stream), "fp%s", reg_names[REGNO (x)] + 2);
517 else if (FP_REGISTER_P (REGNO (x))
518 && GET_MODE_SIZE (GET_MODE (x)) > 4)
519 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
521 fputs (reg_names[REGNO (x)], (stream));
525 output_address (XEXP (x, 0));
530 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
531 && GET_MODE (XEXP (x, 0)) == DImode
532 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
533 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
535 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
538 if (GET_CODE (val) == ASHIFTRT)
541 if (GET_CODE (XEXP (val, 0)) == CONST)
543 output_addr_const (stream, XEXP (val, 0));
544 if (GET_CODE (XEXP (val, 0)) == CONST)
546 fputs (" >> ", stream);
547 output_addr_const (stream, XEXP (val, 1));
552 if (GET_CODE (val) == CONST)
554 output_addr_const (stream, val);
555 if (GET_CODE (val) == CONST)
558 fputs (" & 65535)", stream);
566 output_addr_const (stream, x);
573 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
575 force_into (value, target)
578 value = force_operand (value, target);
579 if (! rtx_equal_p (value, target))
580 emit_insn (gen_move_insn (target, value));
583 /* Emit code to perform a block move. Choose the best method.
585 OPERANDS[0] is the destination.
586 OPERANDS[1] is the source.
587 OPERANDS[2] is the size.
588 OPERANDS[3] is the alignment safe to use. */
591 expand_block_move (operands)
594 int align = INTVAL (operands[3]);
595 int constp = (GET_CODE (operands[2]) == CONST_INT);
596 int bytes = (constp ? INTVAL (operands[2]) : 0);
598 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
599 alignment, or if it isn't a multiple of 4 bytes, then fail. */
600 if (! constp || align < 4 || (bytes % 4 != 0))
607 else if (bytes == 12)
612 rtx r4 = gen_rtx (REG, SImode, 4);
613 rtx r5 = gen_rtx (REG, SImode, 5);
615 entry_name = get_identifier ("__movstrSI12_i4");
617 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
618 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
619 force_into (XEXP (operands[0], 0), r4);
620 force_into (XEXP (operands[1], 0), r5);
621 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
624 else if (! TARGET_SMALLCODE)
630 rtx r4 = gen_rtx (REG, SImode, 4);
631 rtx r5 = gen_rtx (REG, SImode, 5);
632 rtx r6 = gen_rtx (REG, SImode, 6);
634 entry_name = get_identifier (bytes & 4
636 : "__movstr_i4_even");
637 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
638 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
639 force_into (XEXP (operands[0], 0), r4);
640 force_into (XEXP (operands[1], 0), r5);
643 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
644 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
656 rtx r4 = gen_rtx_REG (SImode, 4);
657 rtx r5 = gen_rtx_REG (SImode, 5);
659 sprintf (entry, "__movstrSI%d", bytes);
660 entry_name = get_identifier (entry);
661 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
662 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
663 force_into (XEXP (operands[0], 0), r4);
664 force_into (XEXP (operands[1], 0), r5);
665 emit_insn (gen_block_move_real (func_addr_rtx));
669 /* This is the same number of bytes as a memcpy call, but to a different
670 less common function name, so this will occasionally use more space. */
671 if (! TARGET_SMALLCODE)
676 int final_switch, while_loop;
677 rtx r4 = gen_rtx_REG (SImode, 4);
678 rtx r5 = gen_rtx_REG (SImode, 5);
679 rtx r6 = gen_rtx_REG (SImode, 6);
681 entry_name = get_identifier ("__movstr");
682 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
683 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
684 force_into (XEXP (operands[0], 0), r4);
685 force_into (XEXP (operands[1], 0), r5);
687 /* r6 controls the size of the move. 16 is decremented from it
688 for each 64 bytes moved. Then the negative bit left over is used
689 as an index into a list of move instructions. e.g., a 72 byte move
690 would be set up with size(r6) = 14, for one iteration through the
691 big while loop, and a switch of -2 for the last part. */
693 final_switch = 16 - ((bytes / 4) % 16);
694 while_loop = ((bytes / 4) / 16 - 1) * 16;
695 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
696 emit_insn (gen_block_lump_real (func_addr_rtx));
703 /* Prepare operands for a move define_expand; specifically, one of the
704 operands must be in a register. */
707 prepare_move_operands (operands, mode)
709 enum machine_mode mode;
711 if ((mode == SImode || mode == DImode) && flag_pic)
714 if (SYMBOLIC_CONST_P (operands[1]))
716 if (GET_CODE (operands[0]) == MEM)
717 operands[1] = force_reg (Pmode, operands[1]);
718 else if (TARGET_SHMEDIA
719 && GET_CODE (operands[1]) == LABEL_REF
720 && target_reg_operand (operands[0], mode))
724 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
725 operands[1] = legitimize_pic_address (operands[1], mode, temp);
728 else if (GET_CODE (operands[1]) == CONST
729 && GET_CODE (XEXP (operands[1], 0)) == PLUS
730 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
732 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
733 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
735 operands[1] = expand_binop (mode, add_optab, temp,
736 XEXP (XEXP (operands[1], 0), 1),
737 no_new_pseudos ? temp
738 : gen_reg_rtx (Pmode),
743 if (! reload_in_progress && ! reload_completed)
745 /* Copy the source to a register if both operands aren't registers. */
746 if (! register_operand (operands[0], mode)
747 && ! sh_register_operand (operands[1], mode))
748 operands[1] = copy_to_mode_reg (mode, operands[1]);
750 /* This case can happen while generating code to move the result
751 of a library call to the target. Reject `st r0,@(rX,rY)' because
752 reload will fail to find a spill register for rX, since r0 is already
753 being used for the source. */
754 else if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 0
755 && GET_CODE (operands[0]) == MEM
756 && GET_CODE (XEXP (operands[0], 0)) == PLUS
757 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
758 operands[1] = copy_to_mode_reg (mode, operands[1]);
764 /* Prepare the operands for an scc instruction; make sure that the
765 compare has been done. */
767 prepare_scc_operands (code)
770 rtx t_reg = gen_rtx_REG (SImode, T_REG);
771 enum rtx_code oldcode = code;
772 enum machine_mode mode;
774 /* First need a compare insn. */
778 /* It isn't possible to handle this case. */
797 rtx tmp = sh_compare_op0;
798 sh_compare_op0 = sh_compare_op1;
799 sh_compare_op1 = tmp;
802 mode = GET_MODE (sh_compare_op0);
803 if (mode == VOIDmode)
804 mode = GET_MODE (sh_compare_op1);
806 sh_compare_op0 = force_reg (mode, sh_compare_op0);
807 if ((code != EQ && code != NE
808 && (sh_compare_op1 != const0_rtx
809 || code == GTU || code == GEU || code == LTU || code == LEU))
810 || (mode == DImode && sh_compare_op1 != const0_rtx)
811 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
812 sh_compare_op1 = force_reg (mode, sh_compare_op1);
814 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
815 (mode == SFmode ? emit_sf_insn : emit_df_insn)
816 (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
817 gen_rtx (SET, VOIDmode, t_reg,
818 gen_rtx (code, SImode,
819 sh_compare_op0, sh_compare_op1)),
820 gen_rtx (USE, VOIDmode, get_fpscr_rtx ()))));
822 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
823 gen_rtx (code, SImode, sh_compare_op0,
829 /* Called from the md file, set up the operands of a compare instruction. */
832 from_compare (operands, code)
836 enum machine_mode mode = GET_MODE (sh_compare_op0);
838 if (mode == VOIDmode)
839 mode = GET_MODE (sh_compare_op1);
842 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
844 /* Force args into regs, since we can't use constants here. */
845 sh_compare_op0 = force_reg (mode, sh_compare_op0);
846 if (sh_compare_op1 != const0_rtx
847 || code == GTU || code == GEU
848 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
849 sh_compare_op1 = force_reg (mode, sh_compare_op1);
851 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
853 from_compare (operands, GT);
854 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
857 insn = gen_rtx_SET (VOIDmode,
858 gen_rtx_REG (SImode, T_REG),
859 gen_rtx (code, SImode, sh_compare_op0,
861 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
863 insn = gen_rtx (PARALLEL, VOIDmode,
865 gen_rtx (USE, VOIDmode, get_fpscr_rtx ())));
866 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
872 /* Functions to output assembly code. */
874 /* Return a sequence of instructions to perform DI or DF move.
876 Since the SH cannot move a DI or DF in one instruction, we have
877 to take care when we see overlapping source and dest registers. */
880 output_movedouble (insn, operands, mode)
881 rtx insn ATTRIBUTE_UNUSED;
883 enum machine_mode mode;
885 rtx dst = operands[0];
886 rtx src = operands[1];
888 if (GET_CODE (dst) == MEM
889 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
890 return "mov.l %T1,%0\n\tmov.l %1,%0";
892 if (register_operand (dst, mode)
893 && register_operand (src, mode))
895 if (REGNO (src) == MACH_REG)
896 return "sts mach,%S0\n\tsts macl,%R0";
898 /* When mov.d r1,r2 do r2->r3 then r1->r2;
899 when mov.d r1,r0 do r1->r0 then r2->r1. */
901 if (REGNO (src) + 1 == REGNO (dst))
902 return "mov %T1,%T0\n\tmov %1,%0";
904 return "mov %1,%0\n\tmov %T1,%T0";
906 else if (GET_CODE (src) == CONST_INT)
908 if (INTVAL (src) < 0)
909 output_asm_insn ("mov #-1,%S0", operands);
911 output_asm_insn ("mov #0,%S0", operands);
915 else if (GET_CODE (src) == MEM)
918 int dreg = REGNO (dst);
919 rtx inside = XEXP (src, 0);
921 if (GET_CODE (inside) == REG)
922 ptrreg = REGNO (inside);
923 else if (GET_CODE (inside) == SUBREG)
924 ptrreg = subreg_regno (inside);
925 else if (GET_CODE (inside) == PLUS)
927 ptrreg = REGNO (XEXP (inside, 0));
928 /* ??? A r0+REG address shouldn't be possible here, because it isn't
929 an offsettable address. Unfortunately, offsettable addresses use
930 QImode to check the offset, and a QImode offsettable address
931 requires r0 for the other operand, which is not currently
932 supported, so we can't use the 'o' constraint.
933 Thus we must check for and handle r0+REG addresses here.
934 We punt for now, since this is likely very rare. */
935 if (GET_CODE (XEXP (inside, 1)) == REG)
938 else if (GET_CODE (inside) == LABEL_REF)
939 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
940 else if (GET_CODE (inside) == POST_INC)
941 return "mov.l %1,%0\n\tmov.l %1,%T0";
945 /* Work out the safe way to copy. Copy into the second half first. */
947 return "mov.l %T1,%T0\n\tmov.l %1,%0";
950 return "mov.l %1,%0\n\tmov.l %T1,%T0";
953 /* Print an instruction which would have gone into a delay slot after
954 another instruction, but couldn't because the other instruction expanded
955 into a sequence where putting the slot insn at the end wouldn't work. */
961 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
963 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
967 output_far_jump (insn, op)
971 struct { rtx lab, reg, op; } this;
972 rtx braf_base_lab = NULL_RTX;
975 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
977 this.lab = gen_label_rtx ();
981 && offset - get_attr_length (insn) <= 32766)
984 jump = "mov.w %O0,%1; braf %1";
992 jump = "mov.l %O0,%1; braf %1";
994 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
997 jump = "mov.l %O0,%1; jmp @%1";
999 /* If we have a scratch register available, use it. */
1000 if (GET_CODE (PREV_INSN (insn)) == INSN
1001 && INSN_CODE (PREV_INSN (insn)) == CODE_FOR_indirect_jump_scratch)
1003 this.reg = SET_DEST (PATTERN (PREV_INSN (insn)));
1004 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1005 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1006 output_asm_insn (jump, &this.lab);
1007 if (dbr_sequence_length ())
1008 print_slot (final_sequence);
1010 output_asm_insn ("nop", 0);
1014 /* Output the delay slot insn first if any. */
1015 if (dbr_sequence_length ())
1016 print_slot (final_sequence);
1018 this.reg = gen_rtx_REG (SImode, 13);
1019 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1020 Fortunately, MACL is fixed and call-clobbered, and we never
1021 need its value across jumps, so save r13 in it instead of in
1024 output_asm_insn ("lds r13, macl", 0);
1026 output_asm_insn ("mov.l r13,@-r15", 0);
1027 output_asm_insn (jump, &this.lab);
1029 output_asm_insn ("sts macl, r13", 0);
1031 output_asm_insn ("mov.l @r15+,r13", 0);
1033 if (far && flag_pic && TARGET_SH2)
1035 braf_base_lab = gen_label_rtx ();
1036 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1037 CODE_LABEL_NUMBER (braf_base_lab));
1040 output_asm_insn (".align 2", 0);
1041 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
1043 if (far && flag_pic)
1046 this.lab = braf_base_lab;
1047 output_asm_insn (".long %O2-%O0", &this.lab);
1050 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
1054 /* Local label counter, used for constants in the pool and inside
1055 pattern branches. */
1057 static int lf = 100;
1059 /* Output code for ordinary branches. */
1062 output_branch (logic, insn, operands)
1067 switch (get_attr_length (insn))
1070 /* This can happen if filling the delay slot has caused a forward
1071 branch to exceed its range (we could reverse it, but only
1072 when we know we won't overextend other branches; this should
1073 best be handled by relaxation).
1074 It can also happen when other condbranches hoist delay slot insn
1075 from their destination, thus leading to code size increase.
1076 But the branch will still be in the range -4092..+4098 bytes. */
1081 /* The call to print_slot will clobber the operands. */
1082 rtx op0 = operands[0];
1084 /* If the instruction in the delay slot is annulled (true), then
1085 there is no delay slot where we can put it now. The only safe
1086 place for it is after the label. final will do that by default. */
1089 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1091 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
1092 ASSEMBLER_DIALECT ? "/" : ".", label);
1093 print_slot (final_sequence);
1096 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
1098 output_asm_insn ("bra\t%l0", &op0);
1099 fprintf (asm_out_file, "\tnop\n");
1100 (*targetm.asm_out.internal_label)(asm_out_file, "LF", label);
1104 /* When relaxing, handle this like a short branch. The linker
1105 will fix it up if it still doesn't fit after relaxation. */
1107 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
1109 /* These are for SH2e, in which we have to account for the
1110 extra nop because of the hardware bug in annulled branches. */
1117 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1119 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
1121 ASSEMBLER_DIALECT ? "/" : ".", label);
1122 fprintf (asm_out_file, "\tnop\n");
1123 output_asm_insn ("bra\t%l0", operands);
1124 fprintf (asm_out_file, "\tnop\n");
1125 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
1129 /* When relaxing, fall through. */
1134 sprintf (buffer, "b%s%ss\t%%l0",
1136 ASSEMBLER_DIALECT ? "/" : ".");
1137 output_asm_insn (buffer, &operands[0]);
1142 /* There should be no longer branches now - that would
1143 indicate that something has destroyed the branches set
1144 up in machine_dependent_reorg. */
1150 output_branchy_insn (code, template, insn, operands)
1152 const char *template;
1156 rtx next_insn = NEXT_INSN (insn);
1158 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
1160 rtx src = SET_SRC (PATTERN (next_insn));
1161 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
1163 /* Following branch not taken */
1164 operands[9] = gen_label_rtx ();
1165 emit_label_after (operands[9], next_insn);
1166 INSN_ADDRESSES_NEW (operands[9],
1167 INSN_ADDRESSES (INSN_UID (next_insn))
1168 + get_attr_length (next_insn));
1173 int offset = (branch_dest (next_insn)
1174 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
1175 if (offset >= -252 && offset <= 258)
1177 if (GET_CODE (src) == IF_THEN_ELSE)
1179 src = XEXP (src, 1);
1185 operands[9] = gen_label_rtx ();
1186 emit_label_after (operands[9], insn);
1187 INSN_ADDRESSES_NEW (operands[9],
1188 INSN_ADDRESSES (INSN_UID (insn))
1189 + get_attr_length (insn));
1194 output_ieee_ccmpeq (insn, operands)
1195 rtx insn, *operands;
1197 return output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
1200 /* Output to FILE the start of the assembler file. */
1203 output_file_start (file)
1206 output_file_directive (file, main_input_filename);
1208 /* Switch to the data section so that the coffsem symbol
1209 isn't in the text section. */
1212 if (TARGET_LITTLE_ENDIAN)
1213 fprintf (file, "\t.little\n");
1215 if (TARGET_SHCOMPACT)
1216 fprintf (file, "\t.mode\tSHcompact\n");
1217 else if (TARGET_SHMEDIA)
1218 fprintf (file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1219 TARGET_SHMEDIA64 ? 64 : 32);
1222 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
1225 unspec_caller_rtx_p (pat)
1228 switch (GET_CODE (pat))
1231 return unspec_caller_rtx_p (XEXP (pat, 0));
1234 if (unspec_caller_rtx_p (XEXP (pat, 0)))
1236 return unspec_caller_rtx_p (XEXP (pat, 1));
1238 if (XINT (pat, 1) == UNSPEC_CALLER)
1247 /* Indicate that INSN cannot be duplicated. This is true for insn
1248 that generates an unique label. */
1251 sh_cannot_copy_insn_p (insn)
1256 if (!reload_completed || !flag_pic)
1259 if (GET_CODE (insn) != INSN)
1261 if (asm_noperands (insn) >= 0)
1264 pat = PATTERN (insn);
1265 if (GET_CODE (pat) != SET)
1267 pat = SET_SRC (pat);
1269 if (unspec_caller_rtx_p (pat))
1275 /* Actual number of instructions used to make a shift by N. */
1276 static const char ashiftrt_insns[] =
1277 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1279 /* Left shift and logical right shift are the same. */
1280 static const char shift_insns[] =
1281 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1283 /* Individual shift amounts needed to get the above length sequences.
1284 One bit right shifts clobber the T bit, so when possible, put one bit
1285 shifts in the middle of the sequence, so the ends are eligible for
1286 branch delay slots. */
1287 static const short shift_amounts[32][5] = {
1288 {0}, {1}, {2}, {2, 1},
1289 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1290 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1291 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1292 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1293 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1294 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1295 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1297 /* Likewise, but for shift amounts < 16, up to three highmost bits
1298 might be clobbered. This is typically used when combined with some
1299 kind of sign or zero extension. */
1301 static const char ext_shift_insns[] =
1302 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1304 static const short ext_shift_amounts[32][4] = {
1305 {0}, {1}, {2}, {2, 1},
1306 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1307 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1308 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1309 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1310 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1311 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1312 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1314 /* Assuming we have a value that has been sign-extended by at least one bit,
1315 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1316 to shift it by N without data loss, and quicker than by other means? */
1317 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1319 /* This is used in length attributes in sh.md to help compute the length
1320 of arbitrary constant shift instructions. */
1323 shift_insns_rtx (insn)
1326 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1327 int shift_count = INTVAL (XEXP (set_src, 1));
1328 enum rtx_code shift_code = GET_CODE (set_src);
1333 return ashiftrt_insns[shift_count];
1336 return shift_insns[shift_count];
1342 /* Return the cost of a shift. */
1353 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
1355 if (GET_MODE (x) == DImode
1356 && GET_CODE (XEXP (x, 1)) == CONST_INT
1357 && INTVAL (XEXP (x, 1)) == 1)
1360 /* Everything else is invalid, because there is no pattern for it. */
1363 /* If shift by a non constant, then this will be expensive. */
1364 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1365 return SH_DYNAMIC_SHIFT_COST;
1367 value = INTVAL (XEXP (x, 1));
1369 /* Otherwise, return the true cost in instructions. */
1370 if (GET_CODE (x) == ASHIFTRT)
1372 int cost = ashiftrt_insns[value];
1373 /* If SH3, then we put the constant in a reg and use shad. */
1374 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
1375 cost = 1 + SH_DYNAMIC_SHIFT_COST;
1379 return shift_insns[value];
1382 /* Return the cost of an AND operation. */
1390 /* Anding with a register is a single cycle and instruction. */
1391 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1394 i = INTVAL (XEXP (x, 1));
1398 if ((GET_CODE (XEXP (x, 1)) == CONST_INT
1399 && CONST_OK_FOR_J (INTVAL (XEXP (x, 1))))
1400 || EXTRA_CONSTRAINT_S (XEXP (x, 1)))
1406 /* These constants are single cycle extu.[bw] instructions. */
1407 if (i == 0xff || i == 0xffff)
1409 /* Constants that can be used in an and immediate instruction is a single
1410 cycle, but this requires r0, so make it a little more expensive. */
1411 if (CONST_OK_FOR_L (i))
1413 /* Constants that can be loaded with a mov immediate and an and.
1414 This case is probably unnecessary. */
1415 if (CONST_OK_FOR_I (i))
1417 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1418 This case is probably unnecessary. */
1422 /* Return the cost of an addition or a subtraction. */
1428 /* Adding a register is a single cycle insn. */
1429 if (GET_CODE (XEXP (x, 1)) == REG
1430 || GET_CODE (XEXP (x, 1)) == SUBREG)
1433 /* Likewise for small constants. */
1434 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1435 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
1439 switch (GET_CODE (XEXP (x, 1)))
1444 return TARGET_SHMEDIA64 ? 5 : 3;
1447 if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1))))
1449 else if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1)) >> 16))
1451 else if (CONST_OK_FOR_J ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
1459 /* Any other constant requires a 2 cycle pc-relative load plus an
1464 /* Return the cost of a multiply. */
1467 rtx x ATTRIBUTE_UNUSED;
1474 /* We have a mul insn, so we can never take more than the mul and the
1475 read of the mac reg, but count more because of the latency and extra
1477 if (TARGET_SMALLCODE)
1482 /* If we're aiming at small code, then just count the number of
1483 insns in a multiply call sequence. */
1484 if (TARGET_SMALLCODE)
1487 /* Otherwise count all the insns in the routine we'd be calling too. */
1491 /* Compute a (partial) cost for rtx X. Return true if the complete
1492 cost has been computed, and false if subexpressions should be
1493 scanned. In either case, *TOTAL contains the cost result. */
1496 sh_rtx_costs (x, code, outer_code, total)
1498 int code, outer_code, *total;
1505 if (INTVAL (x) == 0)
1507 else if (outer_code == AND && and_operand ((x), DImode))
1509 else if ((outer_code == IOR || outer_code == XOR
1510 || outer_code == PLUS)
1511 && CONST_OK_FOR_P (INTVAL (x)))
1513 else if (CONST_OK_FOR_J (INTVAL (x)))
1514 *total = COSTS_N_INSNS (outer_code != SET);
1515 else if (CONST_OK_FOR_J (INTVAL (x) >> 16))
1516 *total = COSTS_N_INSNS (2);
1517 else if (CONST_OK_FOR_J ((INTVAL (x) >> 16) >> 16))
1518 *total = COSTS_N_INSNS (3);
1520 *total = COSTS_N_INSNS (4);
1523 if (CONST_OK_FOR_I (INTVAL (x)))
1525 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
1526 && CONST_OK_FOR_L (INTVAL (x)))
1535 if (TARGET_SHMEDIA64)
1536 *total = COSTS_N_INSNS (4);
1537 else if (TARGET_SHMEDIA32)
1538 *total = COSTS_N_INSNS (2);
1545 *total = COSTS_N_INSNS (4);
1551 *total = COSTS_N_INSNS (addsubcosts (x));
1555 *total = COSTS_N_INSNS (andcosts (x));
1559 *total = COSTS_N_INSNS (multcosts (x));
1565 *total = COSTS_N_INSNS (shiftcosts (x));
1572 *total = COSTS_N_INSNS (20);
1585 /* Compute the cost of an address. For the SH, all valid addresses are
1586 the same cost. Use a slightly higher cost for reg + reg addressing,
1587 since it increases pressure on r0. */
1593 return (GET_CODE (X) == PLUS
1594 && ! CONSTANT_P (XEXP (X, 1))
1595 && ! TARGET_SHMEDIA ? 1 : 0);
1598 /* Code to expand a shift. */
1601 gen_ashift (type, n, reg)
1606 /* Negative values here come from the shift_amounts array. */
1619 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
1623 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
1625 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
1628 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
1633 /* Same for HImode */
1636 gen_ashift_hi (type, n, reg)
1641 /* Negative values here come from the shift_amounts array. */
1655 /* We don't have HImode right shift operations because using the
1656 ordinary 32 bit shift instructions for that doesn't generate proper
1657 zero/sign extension.
1658 gen_ashift_hi is only called in contexts where we know that the
1659 sign extension works out correctly. */
1662 if (GET_CODE (reg) == SUBREG)
1664 offset = SUBREG_BYTE (reg);
1665 reg = SUBREG_REG (reg);
1667 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
1671 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
1676 /* Output RTL to split a constant shift into its component SH constant
1677 shift instructions. */
1680 gen_shifty_op (code, operands)
1684 int value = INTVAL (operands[2]);
1687 /* Truncate the shift count in case it is out of bounds. */
1688 value = value & 0x1f;
1692 if (code == LSHIFTRT)
1694 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1695 emit_insn (gen_movt (operands[0]));
1698 else if (code == ASHIFT)
1700 /* There is a two instruction sequence for 31 bit left shifts,
1701 but it requires r0. */
1702 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
1704 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
1705 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1710 else if (value == 0)
1712 /* This can happen when not optimizing. We must output something here
1713 to prevent the compiler from aborting in final.c after the try_split
1715 emit_insn (gen_nop ());
1719 max = shift_insns[value];
1720 for (i = 0; i < max; i++)
1721 gen_ashift (code, shift_amounts[value][i], operands[0]);
1724 /* Same as above, but optimized for values where the topmost bits don't
1728 gen_shifty_hi_op (code, operands)
1732 int value = INTVAL (operands[2]);
1734 void (*gen_fun) PARAMS ((int, int, rtx));
1736 /* This operation is used by and_shl for SImode values with a few
1737 high bits known to be cleared. */
1741 emit_insn (gen_nop ());
1745 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
1748 max = ext_shift_insns[value];
1749 for (i = 0; i < max; i++)
1750 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1753 /* When shifting right, emit the shifts in reverse order, so that
1754 solitary negative values come first. */
1755 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
1756 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1759 /* Output RTL for an arithmetic right shift. */
1761 /* ??? Rewrite to use super-optimizer sequences. */
1764 expand_ashiftrt (operands)
1775 if (GET_CODE (operands[2]) != CONST_INT)
1777 rtx count = copy_to_mode_reg (SImode, operands[2]);
1778 emit_insn (gen_negsi2 (count, count));
1779 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1782 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
1783 > 1 + SH_DYNAMIC_SHIFT_COST)
1786 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
1787 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1791 if (GET_CODE (operands[2]) != CONST_INT)
1794 value = INTVAL (operands[2]) & 31;
1798 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
1801 else if (value >= 16 && value <= 19)
1803 wrk = gen_reg_rtx (SImode);
1804 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
1807 gen_ashift (ASHIFTRT, 1, wrk);
1808 emit_move_insn (operands[0], wrk);
1811 /* Expand a short sequence inline, longer call a magic routine. */
1812 else if (value <= 5)
1814 wrk = gen_reg_rtx (SImode);
1815 emit_move_insn (wrk, operands[1]);
1817 gen_ashift (ASHIFTRT, 1, wrk);
1818 emit_move_insn (operands[0], wrk);
1822 wrk = gen_reg_rtx (Pmode);
1824 /* Load the value into an arg reg and call a helper. */
1825 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1826 sprintf (func, "__ashiftrt_r4_%d", value);
1827 func_name = get_identifier (func);
1828 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (func_name));
1829 emit_move_insn (wrk, sym);
1830 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1831 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
1836 sh_dynamicalize_shift_p (count)
1839 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
1842 /* Try to find a good way to implement the combiner pattern
1843 [(set (match_operand:SI 0 "register_operand" "r")
1844 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1845 (match_operand:SI 2 "const_int_operand" "n"))
1846 (match_operand:SI 3 "const_int_operand" "n"))) .
1847 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1848 return 0 for simple right / left or left/right shift combination.
1849 return 1 for a combination of shifts with zero_extend.
1850 return 2 for a combination of shifts with an AND that needs r0.
1851 return 3 for a combination of shifts with an AND that needs an extra
1852 scratch register, when the three highmost bits of the AND mask are clear.
1853 return 4 for a combination of shifts with an AND that needs an extra
1854 scratch register, when any of the three highmost bits of the AND mask
1856 If ATTRP is set, store an initial right shift width in ATTRP[0],
1857 and the instruction length in ATTRP[1] . These values are not valid
1859 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1860 shift_amounts for the last shift value that is to be used before the
1863 shl_and_kind (left_rtx, mask_rtx, attrp)
1864 rtx left_rtx, mask_rtx;
1867 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
1868 int left = INTVAL (left_rtx), right;
1870 int cost, best_cost = 10000;
1871 int best_right = 0, best_len = 0;
1875 if (left < 0 || left > 31)
1877 if (GET_CODE (mask_rtx) == CONST_INT)
1878 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
1880 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
1881 /* Can this be expressed as a right shift / left shift pair ? */
1882 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
1883 right = exact_log2 (lsb);
1884 mask2 = ~(mask + lsb - 1);
1885 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
1886 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1888 best_cost = shift_insns[right] + shift_insns[right + left];
1889 /* mask has no trailing zeroes <==> ! right */
1890 else if (! right && mask2 == ~(lsb2 - 1))
1892 int late_right = exact_log2 (lsb2);
1893 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
1895 /* Try to use zero extend */
1896 if (mask2 == ~(lsb2 - 1))
1900 for (width = 8; width <= 16; width += 8)
1902 /* Can we zero-extend right away? */
1903 if (lsb2 == (unsigned HOST_WIDE_INT)1 << width)
1906 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
1907 if (cost < best_cost)
1918 /* ??? Could try to put zero extend into initial right shift,
1919 or even shift a bit left before the right shift. */
1920 /* Determine value of first part of left shift, to get to the
1921 zero extend cut-off point. */
1922 first = width - exact_log2 (lsb2) + right;
1923 if (first >= 0 && right + left - first >= 0)
1925 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
1926 + ext_shift_insns[right + left - first];
1927 if (cost < best_cost)
1939 /* Try to use r0 AND pattern */
1940 for (i = 0; i <= 2; i++)
1944 if (! CONST_OK_FOR_L (mask >> i))
1946 cost = (i != 0) + 2 + ext_shift_insns[left + i];
1947 if (cost < best_cost)
1952 best_len = cost - 1;
1955 /* Try to use a scratch register to hold the AND operand. */
1956 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT)3 << 30)) == 0;
1957 for (i = 0; i <= 2; i++)
1961 cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3)
1962 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
1963 if (cost < best_cost)
1968 best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i);
1974 attrp[0] = best_right;
1975 attrp[1] = best_len;
1980 /* This is used in length attributes of the unnamed instructions
1981 corresponding to shl_and_kind return values of 1 and 2. */
1983 shl_and_length (insn)
1986 rtx set_src, left_rtx, mask_rtx;
1989 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1990 left_rtx = XEXP (XEXP (set_src, 0), 1);
1991 mask_rtx = XEXP (set_src, 1);
1992 shl_and_kind (left_rtx, mask_rtx, attributes);
1993 return attributes[1];
1996 /* This is used in length attribute of the and_shl_scratch instruction. */
1999 shl_and_scr_length (insn)
2002 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2003 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
2004 rtx op = XEXP (set_src, 0);
2005 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
2006 op = XEXP (XEXP (op, 0), 0);
2007 return len + shift_insns[INTVAL (XEXP (op, 1))];
2010 /* Generating rtl? */
2011 extern int rtx_equal_function_value_matters;
2013 /* Generate rtl for instructions for which shl_and_kind advised a particular
2014 method of generating them, i.e. returned zero. */
2017 gen_shl_and (dest, left_rtx, mask_rtx, source)
2018 rtx dest, left_rtx, mask_rtx, source;
2021 unsigned HOST_WIDE_INT mask;
2022 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
2023 int right, total_shift;
2024 void (*shift_gen_fun) PARAMS ((int, rtx*)) = gen_shifty_hi_op;
2026 right = attributes[0];
2027 total_shift = INTVAL (left_rtx) + right;
2028 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
2035 int first = attributes[2];
2040 emit_insn ((mask << right) <= 0xff
2041 ? gen_zero_extendqisi2(dest,
2042 gen_lowpart (QImode, source))
2043 : gen_zero_extendhisi2(dest,
2044 gen_lowpart (HImode, source)));
2048 emit_insn (gen_movsi (dest, source));
2052 operands[2] = GEN_INT (right);
2053 gen_shifty_hi_op (LSHIFTRT, operands);
2057 operands[2] = GEN_INT (first);
2058 gen_shifty_hi_op (ASHIFT, operands);
2059 total_shift -= first;
2063 emit_insn (mask <= 0xff
2064 ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
2065 : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
2066 if (total_shift > 0)
2068 operands[2] = GEN_INT (total_shift);
2069 gen_shifty_hi_op (ASHIFT, operands);
2074 shift_gen_fun = gen_shifty_op;
2076 /* If the topmost bit that matters is set, set the topmost bits
2077 that don't matter. This way, we might be able to get a shorter
2079 if (mask & ((HOST_WIDE_INT)1 << (31 - total_shift)))
2080 mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
2082 /* Don't expand fine-grained when combining, because that will
2083 make the pattern fail. */
2084 if (rtx_equal_function_value_matters
2085 || reload_in_progress || reload_completed)
2089 /* Cases 3 and 4 should be handled by this split
2090 only while combining */
2095 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
2098 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
2103 operands[2] = GEN_INT (total_shift);
2104 shift_gen_fun (ASHIFT, operands);
2111 if (kind != 4 && total_shift < 16)
2113 neg = -ext_shift_amounts[total_shift][1];
2115 neg -= ext_shift_amounts[total_shift][2];
2119 emit_insn (gen_and_shl_scratch (dest, source,
2122 GEN_INT (total_shift + neg),
2124 emit_insn (gen_movsi (dest, dest));
2131 /* Try to find a good way to implement the combiner pattern
2132 [(set (match_operand:SI 0 "register_operand" "=r")
2133 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2134 (match_operand:SI 2 "const_int_operand" "n")
2135 (match_operand:SI 3 "const_int_operand" "n")
2137 (clobber (reg:SI T_REG))]
2138 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
2139 return 0 for simple left / right shift combination.
2140 return 1 for left shift / 8 bit sign extend / left shift.
2141 return 2 for left shift / 16 bit sign extend / left shift.
2142 return 3 for left shift / 8 bit sign extend / shift / sign extend.
2143 return 4 for left shift / 16 bit sign extend / shift / sign extend.
2144 return 5 for left shift / 16 bit sign extend / right shift
2145 return 6 for < 8 bit sign extend / left shift.
2146 return 7 for < 8 bit sign extend / left shift / single right shift.
2147 If COSTP is nonzero, assign the calculated cost to *COSTP. */
2150 shl_sext_kind (left_rtx, size_rtx, costp)
2151 rtx left_rtx, size_rtx;
2154 int left, size, insize, ext;
2155 int cost = 0, best_cost;
2158 left = INTVAL (left_rtx);
2159 size = INTVAL (size_rtx);
2160 insize = size - left;
2163 /* Default to left / right shift. */
2165 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
2168 /* 16 bit shift / sign extend / 16 bit shift */
2169 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
2170 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
2171 below, by alternative 3 or something even better. */
2172 if (cost < best_cost)
2178 /* Try a plain sign extend between two shifts. */
2179 for (ext = 16; ext >= insize; ext -= 8)
2183 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
2184 if (cost < best_cost)
2186 kind = ext / (unsigned) 8;
2190 /* Check if we can do a sloppy shift with a final signed shift
2191 restoring the sign. */
2192 if (EXT_SHIFT_SIGNED (size - ext))
2193 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
2194 /* If not, maybe it's still cheaper to do the second shift sloppy,
2195 and do a final sign extend? */
2196 else if (size <= 16)
2197 cost = ext_shift_insns[ext - insize] + 1
2198 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
2201 if (cost < best_cost)
2203 kind = ext / (unsigned) 8 + 2;
2207 /* Check if we can sign extend in r0 */
2210 cost = 3 + shift_insns[left];
2211 if (cost < best_cost)
2216 /* Try the same with a final signed shift. */
2219 cost = 3 + ext_shift_insns[left + 1] + 1;
2220 if (cost < best_cost)
2229 /* Try to use a dynamic shift. */
2230 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
2231 if (cost < best_cost)
2242 /* Function to be used in the length attribute of the instructions
2243 implementing this pattern. */
2246 shl_sext_length (insn)
2249 rtx set_src, left_rtx, size_rtx;
2252 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2253 left_rtx = XEXP (XEXP (set_src, 0), 1);
2254 size_rtx = XEXP (set_src, 1);
2255 shl_sext_kind (left_rtx, size_rtx, &cost);
2259 /* Generate rtl for this pattern */
2262 gen_shl_sext (dest, left_rtx, size_rtx, source)
2263 rtx dest, left_rtx, size_rtx, source;
2266 int left, size, insize, cost;
2269 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
2270 left = INTVAL (left_rtx);
2271 size = INTVAL (size_rtx);
2272 insize = size - left;
2280 int ext = kind & 1 ? 8 : 16;
2281 int shift2 = size - ext;
2283 /* Don't expand fine-grained when combining, because that will
2284 make the pattern fail. */
2285 if (! rtx_equal_function_value_matters
2286 && ! reload_in_progress && ! reload_completed)
2288 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2289 emit_insn (gen_movsi (dest, source));
2293 emit_insn (gen_movsi (dest, source));
2297 operands[2] = GEN_INT (ext - insize);
2298 gen_shifty_hi_op (ASHIFT, operands);
2301 ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
2302 : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
2307 operands[2] = GEN_INT (shift2);
2308 gen_shifty_op (ASHIFT, operands);
2315 if (EXT_SHIFT_SIGNED (shift2))
2317 operands[2] = GEN_INT (shift2 + 1);
2318 gen_shifty_op (ASHIFT, operands);
2319 operands[2] = GEN_INT (1);
2320 gen_shifty_op (ASHIFTRT, operands);
2323 operands[2] = GEN_INT (shift2);
2324 gen_shifty_hi_op (ASHIFT, operands);
2328 operands[2] = GEN_INT (-shift2);
2329 gen_shifty_hi_op (LSHIFTRT, operands);
2331 emit_insn (size <= 8
2332 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
2333 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2340 if (! rtx_equal_function_value_matters
2341 && ! reload_in_progress && ! reload_completed)
2342 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2346 operands[2] = GEN_INT (16 - insize);
2347 gen_shifty_hi_op (ASHIFT, operands);
2348 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2350 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2352 gen_ashift (ASHIFTRT, 1, dest);
2357 /* Don't expand fine-grained when combining, because that will
2358 make the pattern fail. */
2359 if (! rtx_equal_function_value_matters
2360 && ! reload_in_progress && ! reload_completed)
2362 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2363 emit_insn (gen_movsi (dest, source));
2366 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
2367 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
2368 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
2370 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
2371 gen_shifty_op (ASHIFT, operands);
2373 emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
2381 /* Prefix a symbol_ref name with "datalabel". */
2384 gen_datalabel_ref (sym)
2387 if (GET_CODE (sym) == LABEL_REF)
2388 return gen_rtx_CONST (GET_MODE (sym),
2389 gen_rtx_UNSPEC (GET_MODE (sym),
2393 if (GET_CODE (sym) != SYMBOL_REF)
2396 XSTR (sym, 0) = concat (SH_DATALABEL_ENCODING, XSTR (sym, 0), NULL);
2402 /* The SH cannot load a large constant into a register, constants have to
2403 come from a pc relative load. The reference of a pc relative load
2404 instruction must be less than 1k infront of the instruction. This
2405 means that we often have to dump a constant inside a function, and
2406 generate code to branch around it.
2408 It is important to minimize this, since the branches will slow things
2409 down and make things bigger.
2411 Worst case code looks like:
2429 We fix this by performing a scan before scheduling, which notices which
2430 instructions need to have their operands fetched from the constant table
2431 and builds the table.
2435 scan, find an instruction which needs a pcrel move. Look forward, find the
2436 last barrier which is within MAX_COUNT bytes of the requirement.
2437 If there isn't one, make one. Process all the instructions between
2438 the find and the barrier.
2440 In the above example, we can tell that L3 is within 1k of L1, so
2441 the first move can be shrunk from the 3 insn+constant sequence into
2442 just 1 insn, and the constant moved to L3 to make:
2453 Then the second move becomes the target for the shortening process. */
2457 rtx value; /* Value in table. */
2458 rtx label; /* Label of value. */
2459 rtx wend; /* End of window. */
2460 enum machine_mode mode; /* Mode of value. */
2462 /* True if this constant is accessed as part of a post-increment
2463 sequence. Note that HImode constants are never accessed in this way. */
2464 bool part_of_sequence_p;
2467 /* The maximum number of constants that can fit into one pool, since
2468 the pc relative range is 0...1020 bytes and constants are at least 4
2471 #define MAX_POOL_SIZE (1020/4)
2472 static pool_node pool_vector[MAX_POOL_SIZE];
2473 static int pool_size;
2474 static rtx pool_window_label;
2475 static int pool_window_last;
2477 /* ??? If we need a constant in HImode which is the truncated value of a
2478 constant we need in SImode, we could combine the two entries thus saving
2479 two bytes. Is this common enough to be worth the effort of implementing
2482 /* ??? This stuff should be done at the same time that we shorten branches.
2483 As it is now, we must assume that all branches are the maximum size, and
2484 this causes us to almost always output constant pools sooner than
2487 /* Add a constant to the pool and return its label. */
2490 add_constant (x, mode, last_value)
2492 enum machine_mode mode;
2496 rtx lab, new, ref, newref;
2498 /* First see if we've already got it. */
2499 for (i = 0; i < pool_size; i++)
2501 if (x->code == pool_vector[i].value->code
2502 && mode == pool_vector[i].mode)
2504 if (x->code == CODE_LABEL)
2506 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
2509 if (rtx_equal_p (x, pool_vector[i].value))
2514 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
2516 new = gen_label_rtx ();
2517 LABEL_REFS (new) = pool_vector[i].label;
2518 pool_vector[i].label = lab = new;
2520 if (lab && pool_window_label)
2522 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2523 ref = pool_vector[pool_window_last].wend;
2524 LABEL_NEXTREF (newref) = ref;
2525 pool_vector[pool_window_last].wend = newref;
2528 pool_window_label = new;
2529 pool_window_last = i;
2535 /* Need a new one. */
2536 pool_vector[pool_size].value = x;
2537 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
2540 pool_vector[pool_size - 1].part_of_sequence_p = true;
2543 lab = gen_label_rtx ();
2544 pool_vector[pool_size].mode = mode;
2545 pool_vector[pool_size].label = lab;
2546 pool_vector[pool_size].wend = NULL_RTX;
2547 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
2548 if (lab && pool_window_label)
2550 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2551 ref = pool_vector[pool_window_last].wend;
2552 LABEL_NEXTREF (newref) = ref;
2553 pool_vector[pool_window_last].wend = newref;
2556 pool_window_label = lab;
2557 pool_window_last = pool_size;
2562 /* Output the literal table. */
2573 /* Do two passes, first time dump out the HI sized constants. */
2575 for (i = 0; i < pool_size; i++)
2577 pool_node *p = &pool_vector[i];
2579 if (p->mode == HImode)
2583 scan = emit_insn_after (gen_align_2 (), scan);
2586 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2587 scan = emit_label_after (lab, scan);
2588 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
2590 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2592 lab = XEXP (ref, 0);
2593 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2596 else if (p->mode == DFmode)
2602 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
2604 rtx align_insn = NULL_RTX;
2606 scan = emit_label_after (gen_label_rtx (), scan);
2607 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2610 for (i = 0; i < pool_size; i++)
2612 pool_node *p = &pool_vector[i];
2620 if (align_insn && !p->part_of_sequence_p)
2622 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2623 emit_label_before (lab, align_insn);
2624 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
2626 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2628 lab = XEXP (ref, 0);
2629 emit_insn_before (gen_consttable_window_end (lab),
2632 delete_insn (align_insn);
2633 align_insn = NULL_RTX;
2638 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2639 scan = emit_label_after (lab, scan);
2640 scan = emit_insn_after (gen_consttable_4 (p->value,
2642 need_align = ! need_align;
2648 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2653 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2654 scan = emit_label_after (lab, scan);
2655 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2663 if (p->mode != HImode)
2665 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2667 lab = XEXP (ref, 0);
2668 scan = emit_insn_after (gen_consttable_window_end (lab),
2677 for (i = 0; i < pool_size; i++)
2679 pool_node *p = &pool_vector[i];
2690 scan = emit_label_after (gen_label_rtx (), scan);
2691 scan = emit_insn_after (gen_align_4 (), scan);
2693 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2694 scan = emit_label_after (lab, scan);
2695 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
2703 scan = emit_label_after (gen_label_rtx (), scan);
2704 scan = emit_insn_after (gen_align_4 (), scan);
2706 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2707 scan = emit_label_after (lab, scan);
2708 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2716 if (p->mode != HImode)
2718 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2720 lab = XEXP (ref, 0);
2721 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2726 scan = emit_insn_after (gen_consttable_end (), scan);
2727 scan = emit_barrier_after (scan);
2729 pool_window_label = NULL_RTX;
2730 pool_window_last = 0;
2733 /* Return nonzero if constant would be an ok source for a
2734 mov.w instead of a mov.l. */
2740 return (GET_CODE (src) == CONST_INT
2741 && INTVAL (src) >= -32768
2742 && INTVAL (src) <= 32767);
2745 /* Nonzero if the insn is a move instruction which needs to be fixed. */
2747 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2748 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
2749 need to fix it if the input value is CONST_OK_FOR_I. */
2755 if (GET_CODE (insn) == INSN)
2757 rtx pat = PATTERN (insn);
2758 if (GET_CODE (pat) == PARALLEL)
2759 pat = XVECEXP (pat, 0, 0);
2760 if (GET_CODE (pat) == SET
2761 /* We can load any 8 bit value if we don't care what the high
2762 order bits end up as. */
2763 && GET_MODE (SET_DEST (pat)) != QImode
2764 && (CONSTANT_P (SET_SRC (pat))
2765 /* Match mova_const. */
2766 || (GET_CODE (SET_SRC (pat)) == UNSPEC
2767 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
2768 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
2770 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
2771 && (fp_zero_operand (SET_SRC (pat))
2772 || fp_one_operand (SET_SRC (pat)))
2773 /* ??? If this is a -m4 or -m4-single compilation, in general
2774 we don't know the current setting of fpscr, so disable fldi.
2775 There is an exception if this was a register-register move
2776 before reload - and hence it was ascertained that we have
2777 single precision setting - and in a post-reload optimization
2778 we changed this to do a constant load. In that case
2779 we don't have an r0 clobber, hence we must use fldi. */
2780 && (! TARGET_SH4 || TARGET_FMOVD
2781 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
2783 && GET_CODE (SET_DEST (pat)) == REG
2784 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
2785 && (GET_CODE (SET_SRC (pat)) != CONST_INT
2786 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat)))))
2797 return (GET_CODE (insn) == INSN
2798 && GET_CODE (PATTERN (insn)) == SET
2799 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
2800 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
2801 /* Don't match mova_const. */
2802 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn)), 0, 0)) == LABEL_REF);
2805 /* Find the last barrier from insn FROM which is close enough to hold the
2806 constant pool. If we can't find one, then create one near the end of
2810 find_barrier (num_mova, mova, from)
2821 int leading_mova = num_mova;
2822 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
2826 /* For HImode: range is 510, add 4 because pc counts from address of
2827 second instruction after this one, subtract 2 for the jump instruction
2828 that we may need to emit before the table, subtract 2 for the instruction
2829 that fills the jump delay slot (in very rare cases, reorg will take an
2830 instruction from after the constant pool or will leave the delay slot
2831 empty). This gives 510.
2832 For SImode: range is 1020, add 4 because pc counts from address of
2833 second instruction after this one, subtract 2 in case pc is 2 byte
2834 aligned, subtract 2 for the jump instruction that we may need to emit
2835 before the table, subtract 2 for the instruction that fills the jump
2836 delay slot. This gives 1018. */
2838 /* The branch will always be shortened now that the reference address for
2839 forward branches is the successor address, thus we need no longer make
2840 adjustments to the [sh]i_limit for -O0. */
2845 while (from && count_si < si_limit && count_hi < hi_limit)
2847 int inc = get_attr_length (from);
2850 if (GET_CODE (from) == CODE_LABEL)
2853 new_align = 1 << label_to_alignment (from);
2854 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
2855 new_align = 1 << barrier_align (from);
2861 if (GET_CODE (from) == BARRIER)
2864 found_barrier = from;
2866 /* If we are at the end of the function, or in front of an alignment
2867 instruction, we need not insert an extra alignment. We prefer
2868 this kind of barrier. */
2869 if (barrier_align (from) > 2)
2870 good_barrier = from;
2873 if (broken_move (from))
2876 enum machine_mode mode;
2878 pat = PATTERN (from);
2879 if (GET_CODE (pat) == PARALLEL)
2880 pat = XVECEXP (pat, 0, 0);
2881 src = SET_SRC (pat);
2882 dst = SET_DEST (pat);
2883 mode = GET_MODE (dst);
2885 /* We must explicitly check the mode, because sometimes the
2886 front end will generate code to load unsigned constants into
2887 HImode targets without properly sign extending them. */
2889 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
2892 /* We put the short constants before the long constants, so
2893 we must count the length of short constants in the range
2894 for the long constants. */
2895 /* ??? This isn't optimal, but is easy to do. */
2900 /* We dump DF/DI constants before SF/SI ones, because
2901 the limit is the same, but the alignment requirements
2902 are higher. We may waste up to 4 additional bytes
2903 for alignment, and the DF/DI constant may have
2904 another SF/SI constant placed before it. */
2905 if (TARGET_SHCOMPACT
2907 && (mode == DFmode || mode == DImode))
2912 while (si_align > 2 && found_si + si_align - 2 > count_si)
2914 if (found_si > count_si)
2915 count_si = found_si;
2916 found_si += GET_MODE_SIZE (mode);
2918 si_limit -= GET_MODE_SIZE (mode);
2921 /* See the code in machine_dependent_reorg, which has a similar if
2922 statement that generates a new mova insn in many cases. */
2923 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
2933 barrier_before_mova = good_barrier ? good_barrier : found_barrier;
2935 if (found_si > count_si)
2936 count_si = found_si;
2938 else if (GET_CODE (from) == JUMP_INSN
2939 && (GET_CODE (PATTERN (from)) == ADDR_VEC
2940 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
2944 if (barrier_align (next_real_insn (from)) == CACHE_LOG)
2946 /* We have just passed the barrier in front of the
2947 ADDR_DIFF_VEC, which is stored in found_barrier. Since
2948 the ADDR_DIFF_VEC is accessed as data, just like our pool
2949 constants, this is a good opportunity to accommodate what
2950 we have gathered so far.
2951 If we waited any longer, we could end up at a barrier in
2952 front of code, which gives worse cache usage for separated
2953 instruction / data caches. */
2954 good_barrier = found_barrier;
2959 rtx body = PATTERN (from);
2960 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
2963 /* For the SH1, we generate alignments even after jumps-around-jumps. */
2964 else if (GET_CODE (from) == JUMP_INSN
2966 && ! TARGET_SMALLCODE)
2972 if (new_align > si_align)
2974 si_limit -= (count_si - 1) & (new_align - si_align);
2975 si_align = new_align;
2977 count_si = (count_si + new_align - 1) & -new_align;
2982 if (new_align > hi_align)
2984 hi_limit -= (count_hi - 1) & (new_align - hi_align);
2985 hi_align = new_align;
2987 count_hi = (count_hi + new_align - 1) & -new_align;
2989 from = NEXT_INSN (from);
2996 /* Try as we might, the leading mova is out of range. Change
2997 it into a load (which will become a pcload) and retry. */
2998 SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
2999 INSN_CODE (mova) = -1;
3000 return find_barrier (0, 0, mova);
3004 /* Insert the constant pool table before the mova instruction,
3005 to prevent the mova label reference from going out of range. */
3007 good_barrier = found_barrier = barrier_before_mova;
3013 if (good_barrier && next_real_insn (found_barrier))
3014 found_barrier = good_barrier;
3018 /* We didn't find a barrier in time to dump our stuff,
3019 so we'll make one. */
3020 rtx label = gen_label_rtx ();
3022 /* If we exceeded the range, then we must back up over the last
3023 instruction we looked at. Otherwise, we just need to undo the
3024 NEXT_INSN at the end of the loop. */
3025 if (count_hi > hi_limit || count_si > si_limit)
3026 from = PREV_INSN (PREV_INSN (from));
3028 from = PREV_INSN (from);
3030 /* Walk back to be just before any jump or label.
3031 Putting it before a label reduces the number of times the branch
3032 around the constant pool table will be hit. Putting it before
3033 a jump makes it more likely that the bra delay slot will be
3035 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
3036 || GET_CODE (from) == CODE_LABEL)
3037 from = PREV_INSN (from);
3039 from = emit_jump_insn_after (gen_jump (label), from);
3040 JUMP_LABEL (from) = label;
3041 LABEL_NUSES (label) = 1;
3042 found_barrier = emit_barrier_after (from);
3043 emit_label_after (label, found_barrier);
3046 return found_barrier;
3049 /* If the instruction INSN is implemented by a special function, and we can
3050 positively find the register that is used to call the sfunc, and this
3051 register is not used anywhere else in this instruction - except as the
3052 destination of a set, return this register; else, return 0. */
3054 sfunc_uses_reg (insn)
3058 rtx pattern, part, reg_part, reg;
3060 if (GET_CODE (insn) != INSN)
3062 pattern = PATTERN (insn);
3063 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
3066 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3068 part = XVECEXP (pattern, 0, i);
3069 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
3074 reg = XEXP (reg_part, 0);
3075 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
3077 part = XVECEXP (pattern, 0, i);
3078 if (part == reg_part || GET_CODE (part) == CLOBBER)
3080 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
3081 && GET_CODE (SET_DEST (part)) == REG)
3082 ? SET_SRC (part) : part)))
3088 /* See if the only way in which INSN uses REG is by calling it, or by
3089 setting it while calling it. Set *SET to a SET rtx if the register
3093 noncall_uses_reg (reg, insn, set)
3102 reg2 = sfunc_uses_reg (insn);
3103 if (reg2 && REGNO (reg2) == REGNO (reg))
3105 pattern = single_set (insn);
3107 && GET_CODE (SET_DEST (pattern)) == REG
3108 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3112 if (GET_CODE (insn) != CALL_INSN)
3114 /* We don't use rtx_equal_p because we don't care if the mode is
3116 pattern = single_set (insn);
3118 && GET_CODE (SET_DEST (pattern)) == REG
3119 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3125 par = PATTERN (insn);
3126 if (GET_CODE (par) == PARALLEL)
3127 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
3129 part = XVECEXP (par, 0, i);
3130 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
3133 return reg_mentioned_p (reg, SET_SRC (pattern));
3139 pattern = PATTERN (insn);
3141 if (GET_CODE (pattern) == PARALLEL)
3145 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3146 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
3148 pattern = XVECEXP (pattern, 0, 0);
3151 if (GET_CODE (pattern) == SET)
3153 if (reg_mentioned_p (reg, SET_DEST (pattern)))
3155 /* We don't use rtx_equal_p, because we don't care if the
3156 mode is different. */
3157 if (GET_CODE (SET_DEST (pattern)) != REG
3158 || REGNO (reg) != REGNO (SET_DEST (pattern)))
3164 pattern = SET_SRC (pattern);
3167 if (GET_CODE (pattern) != CALL
3168 || GET_CODE (XEXP (pattern, 0)) != MEM
3169 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
3175 /* Given a X, a pattern of an insn or a part of it, return a mask of used
3176 general registers. Bits 0..15 mean that the respective registers
3177 are used as inputs in the instruction. Bits 16..31 mean that the
3178 registers 0..15, respectively, are used as outputs, or are clobbered.
3179 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
3181 regs_used (x, is_dest)
3190 code = GET_CODE (x);
3195 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3196 << (REGNO (x) + is_dest));
3200 rtx y = SUBREG_REG (x);
3202 if (GET_CODE (y) != REG)
3205 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3207 subreg_regno_offset (REGNO (y),
3210 GET_MODE (x)) + is_dest));
3214 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
3216 /* If there was a return value, it must have been indicated with USE. */
3231 fmt = GET_RTX_FORMAT (code);
3233 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3238 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3239 used |= regs_used (XVECEXP (x, i, j), is_dest);
3241 else if (fmt[i] == 'e')
3242 used |= regs_used (XEXP (x, i), is_dest);
3247 /* Create an instruction that prevents redirection of a conditional branch
3248 to the destination of the JUMP with address ADDR.
3249 If the branch needs to be implemented as an indirect jump, try to find
3250 a scratch register for it.
3251 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3252 If any preceding insn that doesn't fit into a delay slot is good enough,
3253 pass 1. Pass 2 if a definite blocking insn is needed.
3254 -1 is used internally to avoid deep recursion.
3255 If a blocking instruction is made or recognized, return it. */
3258 gen_block_redirect (jump, addr, need_block)
3260 int addr, need_block;
3263 rtx prev = prev_nonnote_insn (jump);
3266 /* First, check if we already have an instruction that satisfies our need. */
3267 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
3269 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
3271 if (GET_CODE (PATTERN (prev)) == USE
3272 || GET_CODE (PATTERN (prev)) == CLOBBER
3273 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3275 else if ((need_block &= ~1) < 0)
3277 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
3280 /* We can't use JUMP_LABEL here because it might be undefined
3281 when not optimizing. */
3282 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
3283 /* If the branch is out of range, try to find a scratch register for it. */
3285 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3289 /* Don't look for the stack pointer as a scratch register,
3290 it would cause trouble if an interrupt occurred. */
3291 unsigned try = 0x7fff, used;
3292 int jump_left = flag_expensive_optimizations + 1;
3294 /* It is likely that the most recent eligible instruction is wanted for
3295 the delay slot. Therefore, find out which registers it uses, and
3296 try to avoid using them. */
3298 for (scan = jump; (scan = PREV_INSN (scan)); )
3302 if (INSN_DELETED_P (scan))
3304 code = GET_CODE (scan);
3305 if (code == CODE_LABEL || code == JUMP_INSN)
3308 && GET_CODE (PATTERN (scan)) != USE
3309 && GET_CODE (PATTERN (scan)) != CLOBBER
3310 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
3312 try &= ~regs_used (PATTERN (scan), 0);
3316 for (used = dead = 0, scan = JUMP_LABEL (jump);
3317 (scan = NEXT_INSN (scan)); )
3321 if (INSN_DELETED_P (scan))
3323 code = GET_CODE (scan);
3324 if (GET_RTX_CLASS (code) == 'i')
3326 used |= regs_used (PATTERN (scan), 0);
3327 if (code == CALL_INSN)
3328 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
3329 dead |= (used >> 16) & ~used;
3335 if (code == JUMP_INSN)
3337 if (jump_left-- && simplejump_p (scan))
3338 scan = JUMP_LABEL (scan);
3344 /* Mask out the stack pointer again, in case it was
3345 the only 'free' register we have found. */
3348 /* If the immediate destination is still in range, check for possible
3349 threading with a jump beyond the delay slot insn.
3350 Don't check if we are called recursively; the jump has been or will be
3351 checked in a different invocation then. */
3353 else if (optimize && need_block >= 0)
3355 rtx next = next_active_insn (next_active_insn (dest));
3356 if (next && GET_CODE (next) == JUMP_INSN
3357 && GET_CODE (PATTERN (next)) == SET
3358 && recog_memoized (next) == CODE_FOR_jump)
3360 dest = JUMP_LABEL (next);
3362 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3364 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
3370 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
3372 /* It would be nice if we could convert the jump into an indirect
3373 jump / far branch right now, and thus exposing all constituent
3374 instructions to further optimization. However, reorg uses
3375 simplejump_p to determine if there is an unconditional jump where
3376 it should try to schedule instructions from the target of the
3377 branch; simplejump_p fails for indirect jumps even if they have
3379 rtx insn = emit_insn_before (gen_indirect_jump_scratch
3380 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
3382 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
3385 else if (need_block)
3386 /* We can't use JUMP_LABEL here because it might be undefined
3387 when not optimizing. */
3388 return emit_insn_before (gen_block_branch_redirect
3389 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
3394 #define CONDJUMP_MIN -252
3395 #define CONDJUMP_MAX 262
3398 /* A label (to be placed) in front of the jump
3399 that jumps to our ultimate destination. */
3401 /* Where we are going to insert it if we cannot move the jump any farther,
3402 or the jump itself if we have picked up an existing jump. */
3404 /* The ultimate destination. */
3406 struct far_branch *prev;
3407 /* If the branch has already been created, its address;
3408 else the address of its first prospective user. */
3412 static void gen_far_branch PARAMS ((struct far_branch *));
3413 enum mdep_reorg_phase_e mdep_reorg_phase;
3416 struct far_branch *bp;
3418 rtx insn = bp->insert_place;
3420 rtx label = gen_label_rtx ();
3422 emit_label_after (label, insn);
3425 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
3426 LABEL_NUSES (bp->far_label)++;
3429 jump = emit_jump_insn_after (gen_return (), insn);
3430 /* Emit a barrier so that reorg knows that any following instructions
3431 are not reachable via a fall-through path.
3432 But don't do this when not optimizing, since we wouldn't supress the
3433 alignment for the barrier then, and could end up with out-of-range
3434 pc-relative loads. */
3436 emit_barrier_after (jump);
3437 emit_label_after (bp->near_label, insn);
3438 JUMP_LABEL (jump) = bp->far_label;
3439 if (! invert_jump (insn, label, 1))
3442 (gen_stuff_delay_slot
3443 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
3444 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
3446 /* Prevent reorg from undoing our splits. */
3447 gen_block_redirect (jump, bp->address += 2, 2);
3450 /* Fix up ADDR_DIFF_VECs. */
3452 fixup_addr_diff_vecs (first)
3457 for (insn = first; insn; insn = NEXT_INSN (insn))
3459 rtx vec_lab, pat, prev, prevpat, x, braf_label;
3461 if (GET_CODE (insn) != JUMP_INSN
3462 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
3464 pat = PATTERN (insn);
3465 vec_lab = XEXP (XEXP (pat, 0), 0);
3467 /* Search the matching casesi_jump_2. */
3468 for (prev = vec_lab; ; prev = PREV_INSN (prev))
3470 if (GET_CODE (prev) != JUMP_INSN)
3472 prevpat = PATTERN (prev);
3473 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
3475 x = XVECEXP (prevpat, 0, 1);
3476 if (GET_CODE (x) != USE)
3479 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
3483 /* Emit the reference label of the braf where it belongs, right after
3484 the casesi_jump_2 (i.e. braf). */
3485 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
3486 emit_label_after (braf_label, prev);
3488 /* Fix up the ADDR_DIF_VEC to be relative
3489 to the reference address of the braf. */
3490 XEXP (XEXP (pat, 0), 0) = braf_label;
3494 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3495 a barrier. Return the base 2 logarithm of the desired alignment. */
3497 barrier_align (barrier_or_label)
3498 rtx barrier_or_label;
3500 rtx next = next_real_insn (barrier_or_label), pat, prev;
3501 int slot, credit, jump_to_next = 0;
3506 pat = PATTERN (next);
3508 if (GET_CODE (pat) == ADDR_DIFF_VEC)
3511 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
3512 /* This is a barrier in front of a constant table. */
3515 prev = prev_real_insn (barrier_or_label);
3516 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
3518 pat = PATTERN (prev);
3519 /* If this is a very small table, we want to keep the alignment after
3520 the table to the minimum for proper code alignment. */
3521 return ((TARGET_SMALLCODE
3522 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
3523 <= (unsigned)1 << (CACHE_LOG - 2)))
3524 ? 1 << TARGET_SHMEDIA : CACHE_LOG);
3527 if (TARGET_SMALLCODE)
3530 if (! TARGET_SH2 || ! optimize)
3533 /* When fixing up pcloads, a constant table might be inserted just before
3534 the basic block that ends with the barrier. Thus, we can't trust the
3535 instruction lengths before that. */
3536 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
3538 /* Check if there is an immediately preceding branch to the insn beyond
3539 the barrier. We must weight the cost of discarding useful information
3540 from the current cache line when executing this branch and there is
3541 an alignment, against that of fetching unneeded insn in front of the
3542 branch target when there is no alignment. */
3544 /* There are two delay_slot cases to consider. One is the simple case
3545 where the preceding branch is to the insn beyond the barrier (simple
3546 delay slot filling), and the other is where the preceding branch has
3547 a delay slot that is a duplicate of the insn after the barrier
3548 (fill_eager_delay_slots) and the branch is to the insn after the insn
3549 after the barrier. */
3551 /* PREV is presumed to be the JUMP_INSN for the barrier under
3552 investigation. Skip to the insn before it. */
3553 prev = prev_real_insn (prev);
3555 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
3556 credit >= 0 && prev && GET_CODE (prev) == INSN;
3557 prev = prev_real_insn (prev))
3560 if (GET_CODE (PATTERN (prev)) == USE
3561 || GET_CODE (PATTERN (prev)) == CLOBBER)
3563 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
3565 prev = XVECEXP (PATTERN (prev), 0, 1);
3566 if (INSN_UID (prev) == INSN_UID (next))
3568 /* Delay slot was filled with insn at jump target. */
3575 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3577 credit -= get_attr_length (prev);
3580 && GET_CODE (prev) == JUMP_INSN
3581 && JUMP_LABEL (prev))
3585 || next_real_insn (JUMP_LABEL (prev)) == next
3586 /* If relax_delay_slots() decides NEXT was redundant
3587 with some previous instruction, it will have
3588 redirected PREV's jump to the following insn. */
3589 || JUMP_LABEL (prev) == next_nonnote_insn (next)
3590 /* There is no upper bound on redundant instructions
3591 that might have been skipped, but we must not put an
3592 alignment where none had been before. */
3593 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
3595 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
3596 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch))))
3598 rtx pat = PATTERN (prev);
3599 if (GET_CODE (pat) == PARALLEL)
3600 pat = XVECEXP (pat, 0, 0);
3601 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
3610 /* If we are inside a phony loop, almost any kind of label can turn up as the
3611 first one in the loop. Aligning a braf label causes incorrect switch
3612 destination addresses; we can detect braf labels because they are
3613 followed by a BARRIER.
3614 Applying loop alignment to small constant or switch tables is a waste
3615 of space, so we suppress this too. */
3617 sh_loop_align (label)
3623 next = next_nonnote_insn (next);
3624 while (next && GET_CODE (next) == CODE_LABEL);
3628 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
3629 || recog_memoized (next) == CODE_FOR_consttable_2)
3638 /* Exported to toplev.c.
3640 Do a final pass over the function, just before delayed branch
3644 machine_dependent_reorg (first)
3647 rtx insn, mova = NULL_RTX;
3649 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
3650 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
3652 /* We must split call insns before introducing `mova's. If we're
3653 optimizing, they'll have already been split. Otherwise, make
3654 sure we don't split them too late. */
3656 split_all_insns_noflow ();
3661 /* If relaxing, generate pseudo-ops to associate function calls with
3662 the symbols they call. It does no harm to not generate these
3663 pseudo-ops. However, when we can generate them, it enables to
3664 linker to potentially relax the jsr to a bsr, and eliminate the
3665 register load and, possibly, the constant pool entry. */
3667 mdep_reorg_phase = SH_INSERT_USES_LABELS;
3670 /* Remove all REG_LABEL notes. We want to use them for our own
3671 purposes. This works because none of the remaining passes
3672 need to look at them.
3674 ??? But it may break in the future. We should use a machine
3675 dependent REG_NOTE, or some other approach entirely. */
3676 for (insn = first; insn; insn = NEXT_INSN (insn))
3682 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
3683 remove_note (insn, note);
3687 for (insn = first; insn; insn = NEXT_INSN (insn))
3689 rtx pattern, reg, link, set, scan, dies, label;
3690 int rescan = 0, foundinsn = 0;
3692 if (GET_CODE (insn) == CALL_INSN)
3694 pattern = PATTERN (insn);
3696 if (GET_CODE (pattern) == PARALLEL)
3697 pattern = XVECEXP (pattern, 0, 0);
3698 if (GET_CODE (pattern) == SET)
3699 pattern = SET_SRC (pattern);
3701 if (GET_CODE (pattern) != CALL
3702 || GET_CODE (XEXP (pattern, 0)) != MEM)
3705 reg = XEXP (XEXP (pattern, 0), 0);
3709 reg = sfunc_uses_reg (insn);
3714 if (GET_CODE (reg) != REG)
3717 /* This is a function call via REG. If the only uses of REG
3718 between the time that it is set and the time that it dies
3719 are in function calls, then we can associate all the
3720 function calls with the setting of REG. */
3722 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
3724 if (REG_NOTE_KIND (link) != 0)
3726 set = single_set (XEXP (link, 0));
3727 if (set && rtx_equal_p (reg, SET_DEST (set)))
3729 link = XEXP (link, 0);
3736 /* ??? Sometimes global register allocation will have
3737 deleted the insn pointed to by LOG_LINKS. Try
3738 scanning backward to find where the register is set. */
3739 for (scan = PREV_INSN (insn);
3740 scan && GET_CODE (scan) != CODE_LABEL;
3741 scan = PREV_INSN (scan))
3743 if (! INSN_P (scan))
3746 if (! reg_mentioned_p (reg, scan))
3749 if (noncall_uses_reg (reg, scan, &set))
3763 /* The register is set at LINK. */
3765 /* We can only optimize the function call if the register is
3766 being set to a symbol. In theory, we could sometimes
3767 optimize calls to a constant location, but the assembler
3768 and linker do not support that at present. */
3769 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
3770 && GET_CODE (SET_SRC (set)) != LABEL_REF)
3773 /* Scan forward from LINK to the place where REG dies, and
3774 make sure that the only insns which use REG are
3775 themselves function calls. */
3777 /* ??? This doesn't work for call targets that were allocated
3778 by reload, since there may not be a REG_DEAD note for the
3782 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
3786 /* Don't try to trace forward past a CODE_LABEL if we haven't
3787 seen INSN yet. Ordinarily, we will only find the setting insn
3788 in LOG_LINKS if it is in the same basic block. However,
3789 cross-jumping can insert code labels in between the load and
3790 the call, and can result in situations where a single call
3791 insn may have two targets depending on where we came from. */
3793 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
3796 if (! INSN_P (scan))
3799 /* Don't try to trace forward past a JUMP. To optimize
3800 safely, we would have to check that all the
3801 instructions at the jump destination did not use REG. */
3803 if (GET_CODE (scan) == JUMP_INSN)
3806 if (! reg_mentioned_p (reg, scan))
3809 if (noncall_uses_reg (reg, scan, &scanset))
3816 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
3818 /* There is a function call to this register other
3819 than the one we are checking. If we optimize
3820 this call, we need to rescan again below. */
3824 /* ??? We shouldn't have to worry about SCANSET here.
3825 We should just be able to check for a REG_DEAD note
3826 on a function call. However, the REG_DEAD notes are
3827 apparently not dependable around libcalls; c-torture
3828 execute/920501-2 is a test case. If SCANSET is set,
3829 then this insn sets the register, so it must have
3830 died earlier. Unfortunately, this will only handle
3831 the cases in which the register is, in fact, set in a
3834 /* ??? We shouldn't have to use FOUNDINSN here.
3835 However, the LOG_LINKS fields are apparently not
3836 entirely reliable around libcalls;
3837 newlib/libm/math/e_pow.c is a test case. Sometimes
3838 an insn will appear in LOG_LINKS even though it is
3839 not the most recent insn which sets the register. */
3843 || find_reg_note (scan, REG_DEAD, reg)))
3852 /* Either there was a branch, or some insn used REG
3853 other than as a function call address. */
3857 /* Create a code label, and put it in a REG_LABEL note on
3858 the insn which sets the register, and on each call insn
3859 which uses the register. In final_prescan_insn we look
3860 for the REG_LABEL notes, and output the appropriate label
3863 label = gen_label_rtx ();
3864 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL, label,
3866 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, label,
3875 scan = NEXT_INSN (scan);
3877 && ((GET_CODE (scan) == CALL_INSN
3878 && reg_mentioned_p (reg, scan))
3879 || ((reg2 = sfunc_uses_reg (scan))
3880 && REGNO (reg2) == REGNO (reg))))
3882 = gen_rtx_INSN_LIST (REG_LABEL, label, REG_NOTES (scan));
3884 while (scan != dies);
3890 fixup_addr_diff_vecs (first);
3894 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
3895 shorten_branches (first);
3897 /* Scan the function looking for move instructions which have to be
3898 changed to pc-relative loads and insert the literal tables. */
3900 mdep_reorg_phase = SH_FIXUP_PCLOAD;
3901 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
3908 else if (GET_CODE (insn) == JUMP_INSN
3909 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3917 /* Some code might have been inserted between the mova and
3918 its ADDR_DIFF_VEC. Check if the mova is still in range. */
3919 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
3920 total += get_attr_length (scan);
3922 /* range of mova is 1020, add 4 because pc counts from address of
3923 second instruction after this one, subtract 2 in case pc is 2
3924 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
3925 cancels out with alignment effects of the mova itself. */
3928 /* Change the mova into a load, and restart scanning
3929 there. broken_move will then return true for mova. */
3930 SET_SRC (PATTERN (mova))
3931 = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3932 INSN_CODE (mova) = -1;
3936 if (broken_move (insn))
3939 /* Scan ahead looking for a barrier to stick the constant table
3941 rtx barrier = find_barrier (num_mova, mova, insn);
3942 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
3944 if (num_mova && ! mova_p (mova))
3946 /* find_barrier had to change the first mova into a
3947 pcload; thus, we have to start with this new pcload. */
3951 /* Now find all the moves between the points and modify them. */
3952 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
3954 if (GET_CODE (scan) == CODE_LABEL)
3956 if (broken_move (scan))
3958 rtx *patp = &PATTERN (scan), pat = *patp;
3962 enum machine_mode mode;
3964 if (GET_CODE (pat) == PARALLEL)
3965 patp = &XVECEXP (pat, 0, 0), pat = *patp;
3966 src = SET_SRC (pat);
3967 dst = SET_DEST (pat);
3968 mode = GET_MODE (dst);
3970 if (mode == SImode && hi_const (src)
3971 && REGNO (dst) != FPUL_REG)
3976 while (GET_CODE (dst) == SUBREG)
3978 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
3979 GET_MODE (SUBREG_REG (dst)),
3982 dst = SUBREG_REG (dst);
3984 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
3987 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
3989 /* This must be an insn that clobbers r0. */
3990 rtx clobber = XVECEXP (PATTERN (scan), 0,
3991 XVECLEN (PATTERN (scan), 0) - 1);
3993 if (GET_CODE (clobber) != CLOBBER
3994 || ! rtx_equal_p (XEXP (clobber, 0), r0_rtx))
3998 && reg_set_between_p (r0_rtx, last_float_move, scan))
4002 && GET_MODE_SIZE (mode) != 4
4003 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
4005 lab = add_constant (src, mode, last_float);
4007 emit_insn_before (gen_mova (lab), scan);
4010 /* There will be a REG_UNUSED note for r0 on
4011 LAST_FLOAT_MOVE; we have to change it to REG_INC,
4012 lest reorg:mark_target_live_regs will not
4013 consider r0 to be used, and we end up with delay
4014 slot insn in front of SCAN that clobbers r0. */
4016 = find_regno_note (last_float_move, REG_UNUSED, 0);
4018 /* If we are not optimizing, then there may not be
4021 PUT_MODE (note, REG_INC);
4023 *last_float_addr = r0_inc_rtx;
4025 last_float_move = scan;
4027 newsrc = gen_rtx (MEM, mode,
4028 (((TARGET_SH4 && ! TARGET_FMOVD)
4029 || REGNO (dst) == FPUL_REG)
4032 last_float_addr = &XEXP (newsrc, 0);
4034 /* Remove the clobber of r0. */
4035 XEXP (clobber, 0) = gen_rtx_SCRATCH (Pmode);
4036 RTX_UNCHANGING_P (newsrc) = 1;
4038 /* This is a mova needing a label. Create it. */
4039 else if (GET_CODE (src) == UNSPEC
4040 && XINT (src, 1) == UNSPEC_MOVA
4041 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
4043 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
4044 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
4045 newsrc = gen_rtx_UNSPEC (SImode,
4046 gen_rtvec (1, newsrc),
4051 lab = add_constant (src, mode, 0);
4052 newsrc = gen_rtx_MEM (mode,
4053 gen_rtx_LABEL_REF (VOIDmode, lab));
4054 RTX_UNCHANGING_P (newsrc) = 1;
4056 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
4057 INSN_CODE (scan) = -1;
4060 dump_table (barrier);
4065 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
4066 INSN_ADDRESSES_FREE ();
4067 split_branches (first);
4069 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
4070 also has an effect on the register that holds the address of the sfunc.
4071 Insert an extra dummy insn in front of each sfunc that pretends to
4072 use this register. */
4073 if (flag_delayed_branch)
4075 for (insn = first; insn; insn = NEXT_INSN (insn))
4077 rtx reg = sfunc_uses_reg (insn);
4081 emit_insn_before (gen_use_sfunc_addr (reg), insn);
4085 /* fpscr is not actually a user variable, but we pretend it is for the
4086 sake of the previous optimization passes, since we want it handled like
4087 one. However, we don't have any debugging information for it, so turn
4088 it into a non-user variable now. */
4090 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
4092 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
4096 get_dest_uid (label, max_uid)
4100 rtx dest = next_real_insn (label);
4103 /* This can happen for an undefined label. */
4105 dest_uid = INSN_UID (dest);
4106 /* If this is a newly created branch redirection blocking instruction,
4107 we cannot index the branch_uid or insn_addresses arrays with its
4108 uid. But then, we won't need to, because the actual destination is
4109 the following branch. */
4110 while (dest_uid >= max_uid)
4112 dest = NEXT_INSN (dest);
4113 dest_uid = INSN_UID (dest);
4115 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
4120 /* Split condbranches that are out of range. Also add clobbers for
4121 scratch registers that are needed in far jumps.
4122 We do this before delay slot scheduling, so that it can take our
4123 newly created instructions into account. It also allows us to
4124 find branches with common targets more easily. */
4127 split_branches (first)
4131 struct far_branch **uid_branch, *far_branch_list = 0;
4132 int max_uid = get_max_uid ();
4134 /* Find out which branches are out of range. */
4135 shorten_branches (first);
4137 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
4138 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
4140 for (insn = first; insn; insn = NEXT_INSN (insn))
4141 if (! INSN_P (insn))
4143 else if (INSN_DELETED_P (insn))
4145 /* Shorten_branches would split this instruction again,
4146 so transform it into a note. */
4147 PUT_CODE (insn, NOTE);
4148 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4149 NOTE_SOURCE_FILE (insn) = 0;
4151 else if (GET_CODE (insn) == JUMP_INSN
4152 /* Don't mess with ADDR_DIFF_VEC */
4153 && (GET_CODE (PATTERN (insn)) == SET
4154 || GET_CODE (PATTERN (insn)) == RETURN))
4156 enum attr_type type = get_attr_type (insn);
4157 if (type == TYPE_CBRANCH)
4161 if (get_attr_length (insn) > 4)
4163 rtx src = SET_SRC (PATTERN (insn));
4164 rtx olabel = XEXP (XEXP (src, 1), 0);
4165 int addr = INSN_ADDRESSES (INSN_UID (insn));
4167 int dest_uid = get_dest_uid (olabel, max_uid);
4168 struct far_branch *bp = uid_branch[dest_uid];
4170 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
4171 the label if the LABEL_NUSES count drops to zero. There is
4172 always a jump_optimize pass that sets these values, but it
4173 proceeds to delete unreferenced code, and then if not
4174 optimizing, to un-delete the deleted instructions, thus
4175 leaving labels with too low uses counts. */
4178 JUMP_LABEL (insn) = olabel;
4179 LABEL_NUSES (olabel)++;
4183 bp = (struct far_branch *) alloca (sizeof *bp);
4184 uid_branch[dest_uid] = bp;
4185 bp->prev = far_branch_list;
4186 far_branch_list = bp;
4188 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
4189 LABEL_NUSES (bp->far_label)++;
4193 label = bp->near_label;
4194 if (! label && bp->address - addr >= CONDJUMP_MIN)
4196 rtx block = bp->insert_place;
4198 if (GET_CODE (PATTERN (block)) == RETURN)
4199 block = PREV_INSN (block);
4201 block = gen_block_redirect (block,
4203 label = emit_label_after (gen_label_rtx (),
4205 bp->near_label = label;
4207 else if (label && ! NEXT_INSN (label))
4209 if (addr + 2 - bp->address <= CONDJUMP_MAX)
4210 bp->insert_place = insn;
4212 gen_far_branch (bp);
4216 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
4218 bp->near_label = label = gen_label_rtx ();
4219 bp->insert_place = insn;
4222 if (! redirect_jump (insn, label, 1))
4227 /* get_attr_length (insn) == 2 */
4228 /* Check if we have a pattern where reorg wants to redirect
4229 the branch to a label from an unconditional branch that
4231 /* We can't use JUMP_LABEL here because it might be undefined
4232 when not optimizing. */
4233 /* A syntax error might cause beyond to be NULL_RTX. */
4235 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
4239 && (GET_CODE (beyond) == JUMP_INSN
4240 || ((beyond = next_active_insn (beyond))
4241 && GET_CODE (beyond) == JUMP_INSN))
4242 && GET_CODE (PATTERN (beyond)) == SET
4243 && recog_memoized (beyond) == CODE_FOR_jump
4245 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
4246 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4248 gen_block_redirect (beyond,
4249 INSN_ADDRESSES (INSN_UID (beyond)), 1);
4252 next = next_active_insn (insn);
4254 if ((GET_CODE (next) == JUMP_INSN
4255 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
4256 && GET_CODE (PATTERN (next)) == SET
4257 && recog_memoized (next) == CODE_FOR_jump
4259 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
4260 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4262 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
4264 else if (type == TYPE_JUMP || type == TYPE_RETURN)
4266 int addr = INSN_ADDRESSES (INSN_UID (insn));
4269 struct far_branch *bp;
4271 if (type == TYPE_JUMP)
4273 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
4274 dest_uid = get_dest_uid (far_label, max_uid);
4277 /* Parse errors can lead to labels outside
4279 if (! NEXT_INSN (far_label))
4284 JUMP_LABEL (insn) = far_label;
4285 LABEL_NUSES (far_label)++;
4287 redirect_jump (insn, NULL_RTX, 1);
4291 bp = uid_branch[dest_uid];
4294 bp = (struct far_branch *) alloca (sizeof *bp);
4295 uid_branch[dest_uid] = bp;
4296 bp->prev = far_branch_list;
4297 far_branch_list = bp;
4299 bp->far_label = far_label;
4301 LABEL_NUSES (far_label)++;
4303 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
4304 if (addr - bp->address <= CONDJUMP_MAX)
4305 emit_label_after (bp->near_label, PREV_INSN (insn));
4308 gen_far_branch (bp);
4314 bp->insert_place = insn;
4316 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
4318 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
4321 /* Generate all pending far branches,
4322 and free our references to the far labels. */
4323 while (far_branch_list)
4325 if (far_branch_list->near_label
4326 && ! NEXT_INSN (far_branch_list->near_label))
4327 gen_far_branch (far_branch_list);
4329 && far_branch_list->far_label
4330 && ! --LABEL_NUSES (far_branch_list->far_label))
4331 delete_insn (far_branch_list->far_label);
4332 far_branch_list = far_branch_list->prev;
4335 /* Instruction length information is no longer valid due to the new
4336 instructions that have been generated. */
4337 init_insn_lengths ();
4340 /* Dump out instruction addresses, which is useful for debugging the
4341 constant pool table stuff.
4343 If relaxing, output the label and pseudo-ops used to link together
4344 calls and the instruction which set the registers. */
4346 /* ??? This is unnecessary, and probably should be deleted. This makes
4347 the insn_addresses declaration above unnecessary. */
4349 /* ??? The addresses printed by this routine for insns are nonsense for
4350 insns which are inside of a sequence where none of the inner insns have
4351 variable length. This is because the second pass of shorten_branches
4352 does not bother to update them. */
4355 final_prescan_insn (insn, opvec, noperands)
4357 rtx *opvec ATTRIBUTE_UNUSED;
4358 int noperands ATTRIBUTE_UNUSED;
4360 if (TARGET_DUMPISIZE)
4361 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
4367 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
4372 pattern = PATTERN (insn);
4373 if (GET_CODE (pattern) == PARALLEL)
4374 pattern = XVECEXP (pattern, 0, 0);
4375 if (GET_CODE (pattern) == CALL
4376 || (GET_CODE (pattern) == SET
4377 && (GET_CODE (SET_SRC (pattern)) == CALL
4378 || get_attr_type (insn) == TYPE_SFUNC)))
4379 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
4380 CODE_LABEL_NUMBER (XEXP (note, 0)));
4381 else if (GET_CODE (pattern) == SET)
4382 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4383 CODE_LABEL_NUMBER (XEXP (note, 0)));
4390 /* Dump out any constants accumulated in the final pass. These will
4394 output_jump_label_table ()
4400 fprintf (asm_out_file, "\t.align 2\n");
4401 for (i = 0; i < pool_size; i++)
4403 pool_node *p = &pool_vector[i];
4405 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4406 CODE_LABEL_NUMBER (p->label));
4407 output_asm_insn (".long %O0", &p->value);
4415 /* A full frame looks like:
4419 [ if current_function_anonymous_args
4432 local-0 <- fp points here. */
4434 /* Number of bytes pushed for anonymous args, used to pass information
4435 between expand_prologue and expand_epilogue. */
4437 static int extra_push;
4439 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
4440 to be adjusted, and TEMP, if nonnegative, holds the register number
4441 of a general register that we may clobber. */
4444 output_stack_adjust (size, reg, temp, emit_fn)
4448 rtx (*emit_fn) PARAMS ((rtx));
4452 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4457 if (CONST_OK_FOR_ADD (size))
4458 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
4459 /* Try to do it with two partial adjustments; however, we must make
4460 sure that the stack is properly aligned at all times, in case
4461 an interrupt occurs between the two partial adjustments. */
4462 else if (CONST_OK_FOR_ADD (size / 2 & -align)
4463 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
4465 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
4466 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
4473 /* If TEMP is invalid, we could temporarily save a general
4474 register to MACL. However, there is currently no need
4475 to handle this case, so just abort when we see it. */
4478 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
4480 /* If SIZE is negative, subtract the positive value.
4481 This sometimes allows a constant pool entry to be shared
4482 between prologue and epilogue code. */
4485 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
4486 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
4490 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
4491 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
4493 if (emit_fn == frame_insn)
4495 = (gen_rtx_EXPR_LIST
4496 (REG_FRAME_RELATED_EXPR,
4497 gen_rtx_SET (VOIDmode, reg,
4498 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
4509 RTX_FRAME_RELATED_P (x) = 1;
4513 /* Output RTL to push register RN onto the stack. */
4521 x = gen_push_fpul ();
4522 else if (rn == FPSCR_REG)
4523 x = gen_push_fpscr ();
4524 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4525 && FP_OR_XD_REGISTER_P (rn))
4527 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4529 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
4531 else if (TARGET_SH2E && FP_REGISTER_P (rn))
4532 x = gen_push_e (gen_rtx_REG (SFmode, rn));
4534 x = gen_push (gen_rtx_REG (SImode, rn));
4538 = gen_rtx_EXPR_LIST (REG_INC,
4539 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4543 /* Output RTL to pop register RN from the stack. */
4551 x = gen_pop_fpul ();
4552 else if (rn == FPSCR_REG)
4553 x = gen_pop_fpscr ();
4554 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4555 && FP_OR_XD_REGISTER_P (rn))
4557 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4559 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
4561 else if (TARGET_SH2E && FP_REGISTER_P (rn))
4562 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
4564 x = gen_pop (gen_rtx_REG (SImode, rn));
4568 = gen_rtx_EXPR_LIST (REG_INC,
4569 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4572 /* Generate code to push the regs specified in the mask. */
4576 HOST_WIDE_INT *mask;
4580 /* Push PR last; this gives better latencies after the prologue, and
4581 candidates for the return delay slot when there are no general
4582 registers pushed. */
4583 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4584 if (i != PR_REG && mask[i / 32] & (1 << (i % 32)))
4586 if (mask[PR_REG / 32] & (1 << (PR_REG % 32)))
4590 /* Work out the registers which need to be saved, both as a mask and a
4591 count of saved words.
4593 If doing a pragma interrupt function, then push all regs used by the
4594 function, and if we call another function (we can tell by looking at PR),
4595 make sure that all the regs it clobbers are safe too. */
4598 calc_live_regs (count_ptr, live_regs_mask)
4600 HOST_WIDE_INT *live_regs_mask;
4604 int interrupt_handler;
4607 interrupt_handler = sh_cfun_interrupt_handler_p ();
4609 for (count = 0; 32 * count < FIRST_PSEUDO_REGISTER; count++)
4610 live_regs_mask[count] = 0;
4611 /* If we can save a lot of saves by switching to double mode, do that. */
4612 if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
4613 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
4614 if (regs_ever_live[reg] && regs_ever_live[reg+1]
4615 && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa))
4618 target_flags &= ~FPU_SINGLE_BIT;
4621 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
4622 knows how to use it. That means the pseudo originally allocated for
4623 the initial value can become the PR_MEDIA_REG hard register, as seen for
4624 execute/20010122-1.c:test9. */
4626 pr_live = regs_ever_live[PR_MEDIA_REG];
4629 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
4630 pr_live = (pr_initial
4631 ? (GET_CODE (pr_initial) != REG
4632 || REGNO (pr_initial) != (PR_REG))
4633 : regs_ever_live[PR_REG]);
4635 /* Force PR to be live if the prologue has to call the SHmedia
4636 argument decoder or register saver. */
4637 if (TARGET_SHCOMPACT
4638 && ((current_function_args_info.call_cookie
4639 & ~ CALL_COOKIE_RET_TRAMP (1))
4640 || current_function_has_nonlocal_label))
4642 for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
4644 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
4646 : (interrupt_handler && ! pragma_trapa)
4647 ? (/* Need to save all the regs ever live. */
4648 (regs_ever_live[reg]
4649 || (call_used_regs[reg]
4650 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
4652 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
4653 && reg != RETURN_ADDRESS_POINTER_REGNUM
4654 && reg != T_REG && reg != GBR_REG
4655 /* Push fpscr only on targets which have FPU */
4656 && (reg != FPSCR_REG || TARGET_FPU_ANY))
4657 : (/* Only push those regs which are used and need to be saved. */
4660 && current_function_args_info.call_cookie
4661 && reg == PIC_OFFSET_TABLE_REGNUM)
4662 || (regs_ever_live[reg] && ! call_used_regs[reg])
4663 || (current_function_calls_eh_return
4664 && (reg == EH_RETURN_DATA_REGNO (0)
4665 || reg == EH_RETURN_DATA_REGNO (1)
4666 || reg == EH_RETURN_DATA_REGNO (2)
4667 || reg == EH_RETURN_DATA_REGNO (3)))))
4669 live_regs_mask[reg / 32] |= 1 << (reg % 32);
4670 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4672 if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD
4673 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
4675 if (FP_REGISTER_P (reg))
4677 if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
4679 live_regs_mask[(reg ^ 1) / 32] |= 1 << ((reg ^ 1) % 32);
4680 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
4683 else if (XD_REGISTER_P (reg))
4685 /* Must switch to double mode to access these registers. */
4686 target_flags &= ~FPU_SINGLE_BIT;
4695 /* Code to generate prologue and epilogue sequences */
4697 /* PUSHED is the number of bytes that are bing pushed on the
4698 stack for register saves. Return the frame size, padded
4699 appropriately so that the stack stays properly aligned. */
4700 static HOST_WIDE_INT
4701 rounded_frame_size (pushed)
4704 HOST_WIDE_INT size = get_frame_size ();
4705 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4707 return ((size + pushed + align - 1) & -align) - pushed;
4710 /* Choose a call-clobbered target-branch register that remains
4711 unchanged along the whole function. We set it up as the return
4712 value in the prologue. */
4714 sh_media_register_for_return ()
4719 if (! current_function_is_leaf)
4722 tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
4724 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
4725 if (call_used_regs[regno] && ! regs_ever_live[regno])
4732 sh_expand_prologue ()
4734 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
4737 int save_flags = target_flags;
4739 current_function_interrupt = sh_cfun_interrupt_handler_p ();
4741 /* We have pretend args if we had an object sent partially in registers
4742 and partially on the stack, e.g. a large structure. */
4743 output_stack_adjust (-current_function_pretend_args_size
4744 - current_function_args_info.stack_regs * 8,
4745 stack_pointer_rtx, TARGET_SH5 ? 0 : 1, frame_insn);
4749 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
4750 /* We're going to use the PIC register to load the address of the
4751 incoming-argument decoder and/or of the return trampoline from
4752 the GOT, so make sure the PIC register is preserved and
4754 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
4756 if (TARGET_SHCOMPACT
4757 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
4761 /* First, make all registers with incoming arguments that will
4762 be pushed onto the stack live, so that register renaming
4763 doesn't overwrite them. */
4764 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
4765 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
4766 >= NPARM_REGS (SImode) - reg)
4767 for (; reg < NPARM_REGS (SImode); reg++)
4768 emit_insn (gen_shcompact_preserve_incoming_args
4769 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
4770 else if (CALL_COOKIE_INT_REG_GET
4771 (current_function_args_info.call_cookie, reg) == 1)
4772 emit_insn (gen_shcompact_preserve_incoming_args
4773 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
4775 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
4777 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
4778 GEN_INT (current_function_args_info.call_cookie));
4779 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
4780 gen_rtx_REG (SImode, R0_REG));
4782 else if (TARGET_SHMEDIA)
4784 int tr = sh_media_register_for_return ();
4788 rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr),
4789 gen_rtx_REG (DImode, PR_MEDIA_REG));
4791 /* If this function only exits with sibcalls, this copy
4792 will be flagged as dead. */
4793 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4799 /* Emit the code for SETUP_VARARGS. */
4800 if (current_function_stdarg)
4802 /* This is not used by the SH2E calling convention */
4803 if (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 && ! TARGET_HITACHI)
4805 /* Push arg regs as if they'd been provided by caller in stack. */
4806 for (i = 0; i < NPARM_REGS(SImode); i++)
4808 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
4811 if (i >= (NPARM_REGS(SImode)
4812 - current_function_args_info.arg_count[(int) SH_ARG_INT]
4816 RTX_FRAME_RELATED_P (insn) = 0;
4822 /* If we're supposed to switch stacks at function entry, do so now. */
4824 emit_insn (gen_sp_switch_1 ());
4826 calc_live_regs (&d, live_regs_mask);
4827 /* ??? Maybe we could save some switching if we can move a mode switch
4828 that already happens to be at the function start into the prologue. */
4829 if (target_flags != save_flags)
4830 emit_insn (gen_toggle_sz ());
4837 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
4838 int offset_in_r0 = -1;
4841 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
4842 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
4843 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
4845 offset = d + d_rounding;
4846 output_stack_adjust (-offset, stack_pointer_rtx, 1, frame_insn);
4848 /* We loop twice: first, we save 8-byte aligned registers in the
4849 higher addresses, that are known to be aligned. Then, we
4850 proceed to saving 32-bit registers that don't need 8-byte
4852 /* Note that if you change this code in a way that affects where
4853 the return register is saved, you have to update not only
4854 sh_expand_epilogue, but also sh_set_return_address. */
4855 for (align = 1; align >= 0; align--)
4856 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
4857 if (live_regs_mask[i/32] & (1 << (i % 32)))
4859 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
4861 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
4863 if (mode == SFmode && (i % 2) == 1
4864 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
4865 && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
4872 /* If we're doing the aligned pass and this is not aligned,
4873 or we're doing the unaligned pass and this is aligned,
4875 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
4879 offset -= GET_MODE_SIZE (mode);
4881 reg_rtx = gen_rtx_REG (mode, reg);
4883 mem_rtx = gen_rtx_MEM (mode,
4884 gen_rtx_PLUS (Pmode,
4888 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
4894 if (HAVE_PRE_DECREMENT
4895 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
4896 || mem_rtx == NULL_RTX
4897 || i == PR_REG || SPECIAL_REGISTER_P (i)))
4899 pre_dec = gen_rtx_MEM (mode,
4900 gen_rtx_PRE_DEC (Pmode, r0));
4902 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
4911 offset += GET_MODE_SIZE (mode);
4915 if (mem_rtx != NULL_RTX)
4918 if (offset_in_r0 == -1)
4920 emit_move_insn (r0, GEN_INT (offset));
4921 offset_in_r0 = offset;
4923 else if (offset != offset_in_r0)
4928 GEN_INT (offset - offset_in_r0)));
4929 offset_in_r0 += offset - offset_in_r0;
4932 if (pre_dec != NULL_RTX)
4938 (Pmode, r0, stack_pointer_rtx));
4942 offset -= GET_MODE_SIZE (mode);
4943 offset_in_r0 -= GET_MODE_SIZE (mode);
4948 mem_rtx = gen_rtx_MEM (mode, r0);
4950 mem_rtx = gen_rtx_MEM (mode,
4951 gen_rtx_PLUS (Pmode,
4955 /* We must not use an r0-based address for target-branch
4956 registers or for special registers without pre-dec
4957 memory addresses, since we store their values in r0
4959 if (TARGET_REGISTER_P (i)
4960 || ((i == PR_REG || SPECIAL_REGISTER_P (i))
4961 && mem_rtx != pre_dec))
4965 if (TARGET_REGISTER_P (i)
4966 || ((i == PR_REG || SPECIAL_REGISTER_P (i))
4967 && mem_rtx != pre_dec))
4969 rtx r0mode = gen_rtx_REG (GET_MODE (reg_rtx), R0_REG);
4971 emit_move_insn (r0mode, reg_rtx);
4979 emit_move_insn (mem_rtx, reg_rtx);
4982 if (offset != d_rounding)
4986 push_regs (live_regs_mask);
4988 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
4990 rtx insn = get_last_insn ();
4991 rtx last = emit_insn (gen_GOTaddr2picreg ());
4993 /* Mark these insns as possibly dead. Sometimes, flow2 may
4994 delete all uses of the PIC register. In this case, let it
4995 delete the initialization too. */
4998 insn = NEXT_INSN (insn);
5000 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5004 while (insn != last);
5007 if (SHMEDIA_REGS_STACK_ADJUST ())
5009 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5010 gen_rtx_SYMBOL_REF (Pmode,
5012 ? "__GCC_push_shmedia_regs"
5013 : "__GCC_push_shmedia_regs_nofpu"));
5014 /* This must NOT go through the PLT, otherwise mach and macl
5015 may be clobbered. */
5016 emit_insn (gen_shmedia_save_restore_regs_compact
5017 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
5020 if (target_flags != save_flags)
5022 rtx insn = emit_insn (gen_toggle_sz ());
5024 /* If we're lucky, a mode switch in the function body will
5025 overwrite fpscr, turning this insn dead. Tell flow this
5026 insn is ok to delete. */
5027 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5032 target_flags = save_flags;
5034 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
5035 stack_pointer_rtx, TARGET_SH5 ? 0 : 1, frame_insn);
5037 if (frame_pointer_needed)
5038 frame_insn (GEN_MOV (frame_pointer_rtx, stack_pointer_rtx));
5040 if (TARGET_SHCOMPACT
5041 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
5043 /* This must NOT go through the PLT, otherwise mach and macl
5044 may be clobbered. */
5045 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5046 gen_rtx_SYMBOL_REF (Pmode,
5047 "__GCC_shcompact_incoming_args"));
5048 emit_insn (gen_shcompact_incoming_args ());
5053 sh_expand_epilogue ()
5055 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
5059 int save_flags = target_flags;
5062 calc_live_regs (&d, live_regs_mask);
5064 if (TARGET_SH5 && d % (STACK_BOUNDARY / BITS_PER_UNIT))
5065 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5066 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
5068 frame_size = rounded_frame_size (d) - d_rounding;
5070 if (frame_pointer_needed)
5072 output_stack_adjust (frame_size, frame_pointer_rtx, 7, emit_insn);
5074 /* We must avoid moving the stack pointer adjustment past code
5075 which reads from the local frame, else an interrupt could
5076 occur after the SP adjustment and clobber data in the local
5078 emit_insn (gen_blockage ());
5079 emit_insn (GEN_MOV (stack_pointer_rtx, frame_pointer_rtx));
5081 else if (frame_size)
5083 /* We must avoid moving the stack pointer adjustment past code
5084 which reads from the local frame, else an interrupt could
5085 occur after the SP adjustment and clobber data in the local
5087 emit_insn (gen_blockage ());
5088 output_stack_adjust (frame_size, stack_pointer_rtx, 7, emit_insn);
5091 if (SHMEDIA_REGS_STACK_ADJUST ())
5093 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5094 gen_rtx_SYMBOL_REF (Pmode,
5096 ? "__GCC_pop_shmedia_regs"
5097 : "__GCC_pop_shmedia_regs_nofpu"));
5098 /* This must NOT go through the PLT, otherwise mach and macl
5099 may be clobbered. */
5100 emit_insn (gen_shmedia_save_restore_regs_compact
5101 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
5104 /* Pop all the registers. */
5106 if (target_flags != save_flags)
5107 emit_insn (gen_toggle_sz ());
5110 int offset = d_rounding;
5111 int offset_in_r0 = -1;
5114 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
5116 /* We loop twice: first, we save 8-byte aligned registers in the
5117 higher addresses, that are known to be aligned. Then, we
5118 proceed to saving 32-bit registers that don't need 8-byte
5120 for (align = 0; align <= 1; align++)
5121 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5122 if (live_regs_mask[i/32] & (1 << (i % 32)))
5124 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5126 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
5128 if (mode == SFmode && (i % 2) == 0
5129 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5130 && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
5136 /* If we're doing the aligned pass and this is not aligned,
5137 or we're doing the unaligned pass and this is aligned,
5139 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
5143 reg_rtx = gen_rtx_REG (mode, reg);
5145 mem_rtx = gen_rtx_MEM (mode,
5146 gen_rtx_PLUS (Pmode,
5150 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
5156 if (HAVE_POST_INCREMENT
5157 && (offset == offset_in_r0
5158 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
5159 && mem_rtx == NULL_RTX)
5160 || i == PR_REG || SPECIAL_REGISTER_P (i)))
5162 post_inc = gen_rtx_MEM (mode,
5163 gen_rtx_POST_INC (Pmode, r0));
5165 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
5168 post_inc = NULL_RTX;
5177 if (mem_rtx != NULL_RTX)
5180 if (offset_in_r0 == -1)
5182 emit_move_insn (r0, GEN_INT (offset));
5183 offset_in_r0 = offset;
5185 else if (offset != offset_in_r0)
5190 GEN_INT (offset - offset_in_r0)));
5191 offset_in_r0 += offset - offset_in_r0;
5194 if (post_inc != NULL_RTX)
5200 (Pmode, r0, stack_pointer_rtx));
5206 offset_in_r0 += GET_MODE_SIZE (mode);
5209 mem_rtx = gen_rtx_MEM (mode, r0);
5211 mem_rtx = gen_rtx_MEM (mode,
5212 gen_rtx_PLUS (Pmode,
5216 if ((i == PR_REG || SPECIAL_REGISTER_P (i))
5217 && mem_rtx != post_inc)
5221 if ((i == PR_REG || SPECIAL_REGISTER_P (i))
5222 && mem_rtx != post_inc)
5224 insn = emit_move_insn (r0, mem_rtx);
5227 else if (TARGET_REGISTER_P (i))
5229 rtx r1 = gen_rtx_REG (mode, R1_REG);
5231 insn = emit_move_insn (r1, mem_rtx);
5235 insn = emit_move_insn (reg_rtx, mem_rtx);
5237 offset += GET_MODE_SIZE (mode);
5240 if (offset != d + d_rounding)
5247 if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32)))
5249 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5251 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
5253 if (j != PR_REG && live_regs_mask[j / 32] & (1 << (j % 32)))
5257 if (target_flags != save_flags)
5258 emit_insn (gen_toggle_sz ());
5259 target_flags = save_flags;
5261 output_stack_adjust (extra_push + current_function_pretend_args_size
5263 + current_function_args_info.stack_regs * 8,
5264 stack_pointer_rtx, 7, emit_insn);
5266 if (current_function_calls_eh_return)
5267 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
5268 EH_RETURN_STACKADJ_RTX));
5270 /* Switch back to the normal stack if necessary. */
5272 emit_insn (gen_sp_switch_2 ());
5274 /* Tell flow the insn that pops PR isn't dead. */
5275 /* PR_REG will never be live in SHmedia mode, and we don't need to
5276 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
5277 by the return pattern. */
5278 if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32)))
5279 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
5282 static int sh_need_epilogue_known = 0;
5287 if (! sh_need_epilogue_known)
5292 sh_expand_epilogue ();
5293 epilogue = get_insns ();
5295 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
5297 return sh_need_epilogue_known > 0;
5300 /* Emit code to change the current function's return address to RA.
5301 TEMP is available as a scratch register, if needed. */
5304 sh_set_return_address (ra, tmp)
5307 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
5310 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
5313 calc_live_regs (&d, live_regs_mask);
5315 /* If pr_reg isn't life, we can set it (or the register given in
5316 sh_media_register_for_return) directly. */
5317 if ((live_regs_mask[pr_reg / 32] & (1 << (pr_reg % 32))) == 0)
5323 int rr_regno = sh_media_register_for_return ();
5328 rr = gen_rtx_REG (DImode, rr_regno);
5331 rr = gen_rtx_REG (SImode, pr_reg);
5333 emit_insn (GEN_MOV (rr, ra));
5334 /* Tell flow the register for return isn't dead. */
5335 emit_insn (gen_rtx_USE (VOIDmode, rr));
5345 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
5346 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5347 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
5351 /* We loop twice: first, we save 8-byte aligned registers in the
5352 higher addresses, that are known to be aligned. Then, we
5353 proceed to saving 32-bit registers that don't need 8-byte
5355 for (align = 0; align <= 1; align++)
5356 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5357 if (live_regs_mask[i/32] & (1 << (i % 32)))
5359 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5361 if (mode == SFmode && (i % 2) == 0
5362 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5363 && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
5369 /* If we're doing the aligned pass and this is not aligned,
5370 or we're doing the unaligned pass and this is aligned,
5372 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
5379 offset += GET_MODE_SIZE (mode);
5382 /* We can't find pr register. */
5386 pr_offset = (rounded_frame_size (d) - d_rounding + offset
5387 + SHMEDIA_REGS_STACK_ADJUST ());
5390 pr_offset = rounded_frame_size (d) - d_rounding;
5392 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
5393 emit_insn (GEN_ADD3 (tmp, tmp, frame_pointer_rtx));
5395 tmp = gen_rtx_MEM (Pmode, tmp);
5396 emit_insn (GEN_MOV (tmp, ra));
5399 /* Clear variables at function end. */
5402 sh_output_function_epilogue (file, size)
5403 FILE *file ATTRIBUTE_UNUSED;
5404 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
5406 trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
5407 sh_need_epilogue_known = 0;
5408 sp_switch = NULL_RTX;
5412 sh_builtin_saveregs ()
5414 /* First unnamed integer register. */
5415 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
5416 /* Number of integer registers we need to save. */
5417 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
5418 /* First unnamed SFmode float reg */
5419 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5420 /* Number of SFmode float regs to save. */
5421 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5424 HOST_WIDE_INT alias_set;
5430 int pushregs = n_intregs;
5432 while (pushregs < NPARM_REGS (SImode) - 1
5433 && (CALL_COOKIE_INT_REG_GET
5434 (current_function_args_info.call_cookie,
5435 NPARM_REGS (SImode) - pushregs)
5438 current_function_args_info.call_cookie
5439 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
5444 if (pushregs == NPARM_REGS (SImode))
5445 current_function_args_info.call_cookie
5446 |= (CALL_COOKIE_INT_REG (0, 1)
5447 | CALL_COOKIE_STACKSEQ (pushregs - 1));
5449 current_function_args_info.call_cookie
5450 |= CALL_COOKIE_STACKSEQ (pushregs);
5452 current_function_pretend_args_size += 8 * n_intregs;
5454 if (TARGET_SHCOMPACT)
5458 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
5460 error ("__builtin_saveregs not supported by this subtarget");
5467 /* Allocate block of memory for the regs. */
5468 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5469 Or can assign_stack_local accept a 0 SIZE argument? */
5470 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
5473 regbuf = gen_rtx_MEM (BLKmode,
5474 gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
5475 else if (n_floatregs & 1)
5479 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
5480 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
5481 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
5482 regbuf = change_address (regbuf, BLKmode, addr);
5485 regbuf = assign_stack_local (BLKmode, bufsize, 0);
5486 alias_set = get_varargs_alias_set ();
5487 set_mem_alias_set (regbuf, alias_set);
5490 This is optimized to only save the regs that are necessary. Explicitly
5491 named args need not be saved. */
5493 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
5494 adjust_address (regbuf, BLKmode,
5495 n_floatregs * UNITS_PER_WORD),
5496 n_intregs, n_intregs * UNITS_PER_WORD);
5499 /* Return the address of the regbuf. */
5500 return XEXP (regbuf, 0);
5503 This is optimized to only save the regs that are necessary. Explicitly
5504 named args need not be saved.
5505 We explicitly build a pointer to the buffer because it halves the insn
5506 count when not optimizing (otherwise the pointer is built for each reg
5508 We emit the moves in reverse order so that we can use predecrement. */
5510 fpregs = gen_reg_rtx (Pmode);
5511 emit_move_insn (fpregs, XEXP (regbuf, 0));
5512 emit_insn (gen_addsi3 (fpregs, fpregs,
5513 GEN_INT (n_floatregs * UNITS_PER_WORD)));
5517 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
5519 emit_insn (gen_addsi3 (fpregs, fpregs,
5520 GEN_INT (-2 * UNITS_PER_WORD)));
5521 mem = gen_rtx_MEM (DFmode, fpregs);
5522 set_mem_alias_set (mem, alias_set);
5523 emit_move_insn (mem,
5524 gen_rtx (REG, DFmode, BASE_ARG_REG (DFmode) + regno));
5526 regno = first_floatreg;
5529 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5530 mem = gen_rtx_MEM (SFmode, fpregs);
5531 set_mem_alias_set (mem, alias_set);
5532 emit_move_insn (mem,
5533 gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno
5534 - (TARGET_LITTLE_ENDIAN != 0)));
5538 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
5542 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5543 mem = gen_rtx_MEM (SFmode, fpregs);
5544 set_mem_alias_set (mem, alias_set);
5545 emit_move_insn (mem,
5546 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
5549 /* Return the address of the regbuf. */
5550 return XEXP (regbuf, 0);
5553 /* Define the `__builtin_va_list' type for the ABI. */
5558 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5561 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI)
5562 return ptr_type_node;
5564 record = make_node (RECORD_TYPE);
5566 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
5568 f_next_o_limit = build_decl (FIELD_DECL,
5569 get_identifier ("__va_next_o_limit"),
5571 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
5573 f_next_fp_limit = build_decl (FIELD_DECL,
5574 get_identifier ("__va_next_fp_limit"),
5576 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
5579 DECL_FIELD_CONTEXT (f_next_o) = record;
5580 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
5581 DECL_FIELD_CONTEXT (f_next_fp) = record;
5582 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
5583 DECL_FIELD_CONTEXT (f_next_stack) = record;
5585 TYPE_FIELDS (record) = f_next_o;
5586 TREE_CHAIN (f_next_o) = f_next_o_limit;
5587 TREE_CHAIN (f_next_o_limit) = f_next_fp;
5588 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
5589 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
5591 layout_type (record);
5596 /* Implement `va_start' for varargs and stdarg. */
5599 sh_va_start (valist, nextarg)
5603 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5604 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
5610 expand_builtin_saveregs ();
5611 std_expand_builtin_va_start (valist, nextarg);
5615 if ((! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI)
5617 std_expand_builtin_va_start (valist, nextarg);
5621 f_next_o = TYPE_FIELDS (va_list_type_node);
5622 f_next_o_limit = TREE_CHAIN (f_next_o);
5623 f_next_fp = TREE_CHAIN (f_next_o_limit);
5624 f_next_fp_limit = TREE_CHAIN (f_next_fp);
5625 f_next_stack = TREE_CHAIN (f_next_fp_limit);
5627 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
5628 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
5629 valist, f_next_o_limit);
5630 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp);
5631 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
5632 valist, f_next_fp_limit);
5633 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
5634 valist, f_next_stack);
5636 /* Call __builtin_saveregs. */
5637 u = make_tree (ptr_type_node, expand_builtin_saveregs ());
5638 t = build (MODIFY_EXPR, ptr_type_node, next_fp, u);
5639 TREE_SIDE_EFFECTS (t) = 1;
5640 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5642 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
5647 u = fold (build (PLUS_EXPR, ptr_type_node, u,
5648 build_int_2 (UNITS_PER_WORD * nfp, 0)));
5649 t = build (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
5650 TREE_SIDE_EFFECTS (t) = 1;
5651 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5653 t = build (MODIFY_EXPR, ptr_type_node, next_o, u);
5654 TREE_SIDE_EFFECTS (t) = 1;
5655 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5657 nint = current_function_args_info.arg_count[SH_ARG_INT];
5662 u = fold (build (PLUS_EXPR, ptr_type_node, u,
5663 build_int_2 (UNITS_PER_WORD * nint, 0)));
5664 t = build (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
5665 TREE_SIDE_EFFECTS (t) = 1;
5666 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5668 u = make_tree (ptr_type_node, nextarg);
5669 t = build (MODIFY_EXPR, ptr_type_node, next_stack, u);
5670 TREE_SIDE_EFFECTS (t) = 1;
5671 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5674 /* Implement `va_arg'. */
5677 sh_va_arg (valist, type)
5680 HOST_WIDE_INT size, rsize;
5681 tree tmp, pptr_type_node;
5684 int pass_by_ref = MUST_PASS_IN_STACK (TYPE_MODE (type), type);
5686 size = int_size_in_bytes (type);
5687 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5688 pptr_type_node = build_pointer_type (ptr_type_node);
5691 type = build_pointer_type (type);
5693 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4) && ! TARGET_HITACHI)
5695 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5696 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
5698 rtx lab_false, lab_over;
5700 f_next_o = TYPE_FIELDS (va_list_type_node);
5701 f_next_o_limit = TREE_CHAIN (f_next_o);
5702 f_next_fp = TREE_CHAIN (f_next_o_limit);
5703 f_next_fp_limit = TREE_CHAIN (f_next_fp);
5704 f_next_stack = TREE_CHAIN (f_next_fp_limit);
5706 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
5707 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
5708 valist, f_next_o_limit);
5709 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp),
5711 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
5712 valist, f_next_fp_limit);
5713 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
5714 valist, f_next_stack);
5718 pass_as_float = ((TREE_CODE (type) == REAL_TYPE && size <= 8)
5719 || (TREE_CODE (type) == COMPLEX_TYPE
5720 && TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
5725 pass_as_float = (TREE_CODE (type) == REAL_TYPE && size == 4);
5728 addr_rtx = gen_reg_rtx (Pmode);
5729 lab_false = gen_label_rtx ();
5730 lab_over = gen_label_rtx ();
5735 = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5736 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5738 emit_cmp_and_jump_insns (expand_expr (next_fp, NULL_RTX, Pmode,
5740 expand_expr (next_fp_limit, NULL_RTX,
5741 Pmode, EXPAND_NORMAL),
5742 GE, const1_rtx, Pmode, 1, lab_false);
5744 if (TYPE_ALIGN (type) > BITS_PER_WORD
5745 || (((TREE_CODE (type) == REAL_TYPE && size == 8) || size == 16)
5746 && (n_floatregs & 1)))
5748 tmp = build (BIT_AND_EXPR, ptr_type_node, next_fp,
5749 build_int_2 (UNITS_PER_WORD, 0));
5750 tmp = build (PLUS_EXPR, ptr_type_node, next_fp, tmp);
5751 tmp = build (MODIFY_EXPR, ptr_type_node, next_fp, tmp);
5752 TREE_SIDE_EFFECTS (tmp) = 1;
5753 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
5756 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
5757 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5759 emit_move_insn (addr_rtx, r);
5761 emit_jump_insn (gen_jump (lab_over));
5763 emit_label (lab_false);
5765 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
5766 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5768 emit_move_insn (addr_rtx, r);
5772 tmp = build (PLUS_EXPR, ptr_type_node, next_o,
5773 build_int_2 (rsize, 0));
5775 emit_cmp_and_jump_insns (expand_expr (tmp, NULL_RTX, Pmode,
5777 expand_expr (next_o_limit, NULL_RTX,
5778 Pmode, EXPAND_NORMAL),
5779 GT, const1_rtx, Pmode, 1, lab_false);
5781 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
5782 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5784 emit_move_insn (addr_rtx, r);
5786 emit_jump_insn (gen_jump (lab_over));
5788 emit_label (lab_false);
5790 if (size > 4 && ! TARGET_SH4)
5792 tmp = build (MODIFY_EXPR, ptr_type_node, next_o, next_o_limit);
5793 TREE_SIDE_EFFECTS (tmp) = 1;
5794 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
5797 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
5798 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5800 emit_move_insn (addr_rtx, r);
5803 emit_label (lab_over);
5805 tmp = make_tree (pptr_type_node, addr_rtx);
5806 valist = build1 (INDIRECT_REF, ptr_type_node, tmp);
5809 /* ??? In va-sh.h, there had been code to make values larger than
5810 size 8 indirect. This does not match the FUNCTION_ARG macros. */
5812 result = std_expand_builtin_va_arg (valist, type);
5815 #ifdef POINTERS_EXTEND_UNSIGNED
5816 if (GET_MODE (addr) != Pmode)
5817 addr = convert_memory_address (Pmode, result);
5819 result = gen_rtx_MEM (ptr_mode, force_reg (Pmode, result));
5820 set_mem_alias_set (result, get_varargs_alias_set ());
5822 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
5823 argument to the varargs alias set. */
5827 /* Define the offset between two registers, one to be eliminated, and
5828 the other its replacement, at the start of a routine. */
5831 initial_elimination_offset (from, to)
5836 int regs_saved_rounding = 0;
5837 int total_saved_regs_space;
5838 int total_auto_space;
5839 int save_flags = target_flags;
5842 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
5843 calc_live_regs (®s_saved, live_regs_mask);
5844 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
5845 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
5846 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5847 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
5849 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
5850 copy_flags = target_flags;
5851 target_flags = save_flags;
5853 total_saved_regs_space = regs_saved + regs_saved_rounding;
5855 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
5856 return total_saved_regs_space + total_auto_space
5857 + current_function_args_info.byref_regs * 8;
5859 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
5860 return total_saved_regs_space + total_auto_space
5861 + current_function_args_info.byref_regs * 8;
5863 /* Initial gap between fp and sp is 0. */
5864 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
5867 if (from == RETURN_ADDRESS_POINTER_REGNUM
5868 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
5872 int i, n = total_saved_regs_space;
5874 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
5876 n += total_auto_space;
5878 /* If it wasn't saved, there's not much we can do. */
5879 if ((live_regs_mask[pr_reg / 32] & (1 << (pr_reg % 32))) == 0)
5882 target_flags = copy_flags;
5884 /* We loop twice: first, check 8-byte aligned registers,
5885 that are stored in the higher addresses, that are known
5886 to be aligned. Then, check 32-bit registers that don't
5887 need 8-byte alignment. */
5888 for (align = 1; align >= 0; align--)
5889 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
5890 if (live_regs_mask[i/32] & (1 << (i % 32)))
5892 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5894 if (mode == SFmode && (i % 2) == 1
5895 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5896 && (live_regs_mask[(i ^ 1) / 32]
5897 & (1 << ((i ^ 1) % 32))))
5903 /* If we're doing the aligned pass and this is not aligned,
5904 or we're doing the unaligned pass and this is aligned,
5906 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
5910 n -= GET_MODE_SIZE (mode);
5914 target_flags = save_flags;
5922 return total_auto_space;
5928 /* Handle machine specific pragmas to be semi-compatible with Hitachi
5932 sh_pr_interrupt (pfile)
5933 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
5935 pragma_interrupt = 1;
5940 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
5942 pragma_interrupt = pragma_trapa = 1;
5946 sh_pr_nosave_low_regs (pfile)
5947 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
5949 pragma_nosave_low_regs = 1;
5952 /* Generate 'handle_interrupt' attribute for decls */
5955 sh_insert_attributes (node, attributes)
5959 if (! pragma_interrupt
5960 || TREE_CODE (node) != FUNCTION_DECL)
5963 /* We are only interested in fields. */
5964 if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd')
5967 /* Add a 'handle_interrupt' attribute. */
5968 * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes);
5973 /* Supported attributes:
5975 interrupt_handler -- specifies this function is an interrupt handler.
5977 sp_switch -- specifies an alternate stack for an interrupt handler
5980 trap_exit -- use a trapa to exit an interrupt function instead of
5981 an rte instruction. */
5983 const struct attribute_spec sh_attribute_table[] =
5985 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5986 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
5987 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
5988 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
5989 { NULL, 0, 0, false, false, false, NULL }
5992 /* Handle an "interrupt_handler" attribute; arguments as in
5993 struct attribute_spec.handler. */
5995 sh_handle_interrupt_handler_attribute (node, name, args, flags, no_add_attrs)
5998 tree args ATTRIBUTE_UNUSED;
5999 int flags ATTRIBUTE_UNUSED;
6002 if (TREE_CODE (*node) != FUNCTION_DECL)
6004 warning ("`%s' attribute only applies to functions",
6005 IDENTIFIER_POINTER (name));
6006 *no_add_attrs = true;
6008 else if (TARGET_SHCOMPACT)
6010 error ("attribute interrupt_handler is not compatible with -m5-compact");
6011 *no_add_attrs = true;
6017 /* Handle an "sp_switch" attribute; arguments as in
6018 struct attribute_spec.handler. */
6020 sh_handle_sp_switch_attribute (node, name, args, flags, no_add_attrs)
6024 int flags ATTRIBUTE_UNUSED;
6027 if (TREE_CODE (*node) != FUNCTION_DECL)
6029 warning ("`%s' attribute only applies to functions",
6030 IDENTIFIER_POINTER (name));
6031 *no_add_attrs = true;
6033 else if (!pragma_interrupt)
6035 /* The sp_switch attribute only has meaning for interrupt functions. */
6036 warning ("`%s' attribute only applies to interrupt functions",
6037 IDENTIFIER_POINTER (name));
6038 *no_add_attrs = true;
6040 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
6042 /* The argument must be a constant string. */
6043 warning ("`%s' attribute argument not a string constant",
6044 IDENTIFIER_POINTER (name));
6045 *no_add_attrs = true;
6049 sp_switch = gen_rtx_SYMBOL_REF (VOIDmode,
6050 TREE_STRING_POINTER (TREE_VALUE (args)));
6056 /* Handle an "trap_exit" attribute; arguments as in
6057 struct attribute_spec.handler. */
6059 sh_handle_trap_exit_attribute (node, name, args, flags, no_add_attrs)
6063 int flags ATTRIBUTE_UNUSED;
6066 if (TREE_CODE (*node) != FUNCTION_DECL)
6068 warning ("`%s' attribute only applies to functions",
6069 IDENTIFIER_POINTER (name));
6070 *no_add_attrs = true;
6072 else if (!pragma_interrupt)
6074 /* The trap_exit attribute only has meaning for interrupt functions. */
6075 warning ("`%s' attribute only applies to interrupt functions",
6076 IDENTIFIER_POINTER (name));
6077 *no_add_attrs = true;
6079 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
6081 /* The argument must be a constant integer. */
6082 warning ("`%s' attribute argument not an integer constant",
6083 IDENTIFIER_POINTER (name));
6084 *no_add_attrs = true;
6088 trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
6095 sh_cfun_interrupt_handler_p ()
6097 return (lookup_attribute ("interrupt_handler",
6098 DECL_ATTRIBUTES (current_function_decl))
6102 /* Predicates used by the templates. */
6104 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
6105 Used only in general_movsrc_operand. */
6108 system_reg_operand (op, mode)
6110 enum machine_mode mode ATTRIBUTE_UNUSED;
6122 /* Returns 1 if OP can be source of a simple move operation.
6123 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
6124 invalid as are subregs of system registers. */
6127 general_movsrc_operand (op, mode)
6129 enum machine_mode mode;
6131 if (GET_CODE (op) == MEM)
6133 rtx inside = XEXP (op, 0);
6134 if (GET_CODE (inside) == CONST)
6135 inside = XEXP (inside, 0);
6137 if (GET_CODE (inside) == LABEL_REF)
6140 if (GET_CODE (inside) == PLUS
6141 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
6142 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
6145 /* Only post inc allowed. */
6146 if (GET_CODE (inside) == PRE_DEC)
6150 if ((mode == QImode || mode == HImode)
6151 && (GET_CODE (op) == SUBREG
6152 && GET_CODE (XEXP (op, 0)) == REG
6153 && system_reg_operand (XEXP (op, 0), mode)))
6156 return general_operand (op, mode);
6159 /* Returns 1 if OP can be a destination of a move.
6160 Same as general_operand, but no preinc allowed. */
6163 general_movdst_operand (op, mode)
6165 enum machine_mode mode;
6167 /* Only pre dec allowed. */
6168 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
6171 return general_operand (op, mode);
6174 /* Returns 1 if OP is a normal arithmetic register. */
6177 arith_reg_operand (op, mode)
6179 enum machine_mode mode;
6181 if (register_operand (op, mode))
6185 if (GET_CODE (op) == REG)
6187 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
6188 regno = REGNO (SUBREG_REG (op));
6192 return (regno != T_REG && regno != PR_REG
6193 && ! TARGET_REGISTER_P (regno)
6194 && (regno != FPUL_REG || TARGET_SH4)
6195 && regno != MACH_REG && regno != MACL_REG);
6200 /* Like above, but for DImode destinations: forbid paradoxical DImode subregs,
6201 because this would lead to missing sign extensions when truncating from
6202 DImode to SImode. */
6204 arith_reg_dest (op, mode)
6206 enum machine_mode mode;
6208 if (mode == DImode && GET_CODE (op) == SUBREG
6209 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
6211 return arith_reg_operand (op, mode);
6215 int_gpr_dest (op, mode)
6217 enum machine_mode mode ATTRIBUTE_UNUSED;
6219 enum machine_mode op_mode = GET_MODE (op);
6221 if (GET_MODE_CLASS (op_mode) != MODE_INT
6222 || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
6224 if (! reload_completed)
6226 return true_regnum (op) <= LAST_GENERAL_REG;
6230 fp_arith_reg_operand (op, mode)
6232 enum machine_mode mode;
6234 if (register_operand (op, mode))
6238 if (GET_CODE (op) == REG)
6240 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
6241 regno = REGNO (SUBREG_REG (op));
6245 return (regno >= FIRST_PSEUDO_REGISTER
6246 || FP_REGISTER_P (regno));
6251 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
6254 arith_operand (op, mode)
6256 enum machine_mode mode;
6258 if (arith_reg_operand (op, mode))
6263 /* FIXME: We should be checking whether the CONST_INT fits in a
6264 CONST_OK_FOR_J here, but this causes reload_cse to crash when
6265 attempting to transform a sequence of two 64-bit sets of the
6266 same register from literal constants into a set and an add,
6267 when the difference is too wide for an add. */
6268 if (GET_CODE (op) == CONST_INT
6269 || EXTRA_CONSTRAINT_S (op))
6274 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
6280 /* Returns 1 if OP is a valid source operand for a compare insn. */
6283 arith_reg_or_0_operand (op, mode)
6285 enum machine_mode mode;
6287 if (arith_reg_operand (op, mode))
6290 if (EXTRA_CONSTRAINT_U (op))
6296 /* Return 1 if OP is a valid source operand for an SHmedia operation
6297 that takes either a register or a 6-bit immediate. */
6300 shmedia_6bit_operand (op, mode)
6302 enum machine_mode mode;
6304 return (arith_reg_operand (op, mode)
6305 || (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op))));
6308 /* Returns 1 if OP is a valid source operand for a logical operation. */
6311 logical_operand (op, mode)
6313 enum machine_mode mode;
6315 if (arith_reg_operand (op, mode))
6320 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_P (INTVAL (op)))
6325 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
6332 and_operand (op, mode)
6334 enum machine_mode mode;
6336 if (logical_operand (op, mode))
6339 /* Check mshflo.l / mshflhi.l opportunities. */
6342 && GET_CODE (op) == CONST_INT
6343 && (INTVAL (op) == (unsigned) 0xffffffff
6344 || INTVAL (op) == (HOST_WIDE_INT) -1 << 32))
6350 /* Nonzero if OP is a floating point value with value 0.0. */
6353 fp_zero_operand (op)
6358 if (GET_MODE (op) != SFmode)
6361 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
6362 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
6365 /* Nonzero if OP is a floating point value with value 1.0. */
6373 if (GET_MODE (op) != SFmode)
6376 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
6377 return REAL_VALUES_EQUAL (r, dconst1);
6380 /* For -m4 and -m4-single-only, mode switching is used. If we are
6381 compiling without -mfmovd, movsf_ie isn't taken into account for
6382 mode switching. We could check in machine_dependent_reorg for
6383 cases where we know we are in single precision mode, but there is
6384 interface to find that out during reload, so we must avoid
6385 choosing an fldi alternative during reload and thus failing to
6386 allocate a scratch register for the constant loading. */
6390 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
6394 tertiary_reload_operand (op, mode)
6396 enum machine_mode mode ATTRIBUTE_UNUSED;
6398 enum rtx_code code = GET_CODE (op);
6399 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
6403 fpscr_operand (op, mode)
6405 enum machine_mode mode ATTRIBUTE_UNUSED;
6407 return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG
6408 && GET_MODE (op) == PSImode);
6412 fpul_operand (op, mode)
6414 enum machine_mode mode;
6417 return fp_arith_reg_operand (op, mode);
6419 return (GET_CODE (op) == REG
6420 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
6421 && GET_MODE (op) == mode);
6425 symbol_ref_operand (op, mode)
6427 enum machine_mode mode ATTRIBUTE_UNUSED;
6429 return (GET_CODE (op) == SYMBOL_REF);
6433 commutative_float_operator (op, mode)
6435 enum machine_mode mode;
6437 if (GET_MODE (op) != mode)
6439 switch (GET_CODE (op))
6451 noncommutative_float_operator (op, mode)
6453 enum machine_mode mode;
6455 if (GET_MODE (op) != mode)
6457 switch (GET_CODE (op))
6469 unary_float_operator (op, mode)
6471 enum machine_mode mode;
6473 if (GET_MODE (op) != mode)
6475 switch (GET_CODE (op))
6488 binary_float_operator (op, mode)
6490 enum machine_mode mode;
6492 if (GET_MODE (op) != mode)
6494 switch (GET_CODE (op))
6508 binary_logical_operator (op, mode)
6510 enum machine_mode mode;
6512 if (GET_MODE (op) != mode)
6514 switch (GET_CODE (op))
6527 equality_comparison_operator (op, mode)
6529 enum machine_mode mode;
6531 return ((mode == VOIDmode || GET_MODE (op) == mode)
6532 && (GET_CODE (op) == EQ || GET_CODE (op) == NE));
6535 int greater_comparison_operator (op, mode)
6537 enum machine_mode mode;
6539 if (mode != VOIDmode && GET_MODE (op) == mode)
6541 switch (GET_CODE (op))
6553 int less_comparison_operator (op, mode)
6555 enum machine_mode mode;
6557 if (mode != VOIDmode && GET_MODE (op) == mode)
6559 switch (GET_CODE (op))
6571 /* Accept pseudos and branch target registers. */
6573 target_reg_operand (op, mode)
6575 enum machine_mode mode;
6578 || GET_MODE (op) != DImode)
6581 if (GET_CODE (op) == SUBREG)
6584 if (GET_CODE (op) != REG)
6587 /* We must protect ourselves from matching pseudos that are virtual
6588 register, because they will eventually be replaced with hardware
6589 registers that aren't branch-target registers. */
6590 if (REGNO (op) > LAST_VIRTUAL_REGISTER
6591 || TARGET_REGISTER_P (REGNO (op)))
6597 /* Same as target_reg_operand, except that label_refs and symbol_refs
6598 are accepted before reload. */
6600 target_operand (op, mode)
6602 enum machine_mode mode;
6607 if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode)
6608 && EXTRA_CONSTRAINT_T (op))
6609 return ! reload_completed;
6611 return target_reg_operand (op, mode);
6615 mextr_bit_offset (op, mode)
6617 enum machine_mode mode ATTRIBUTE_UNUSED;
6621 if (GET_CODE (op) != CONST_INT)
6624 return i >= 1*8 && i <= 7*8 && (i & 7) == 0;
6628 extend_reg_operand (op, mode)
6630 enum machine_mode mode;
6632 return (GET_CODE (op) == TRUNCATE
6634 : arith_reg_operand) (op, mode);
6638 trunc_hi_operand (op, mode)
6640 enum machine_mode mode;
6642 enum machine_mode op_mode = GET_MODE (op);
6644 if (op_mode != SImode && op_mode != DImode
6645 && op_mode != V4HImode && op_mode != V2SImode)
6647 return extend_reg_operand (op, mode);
6651 extend_reg_or_0_operand (op, mode)
6653 enum machine_mode mode;
6655 return (GET_CODE (op) == TRUNCATE
6657 : arith_reg_or_0_operand) (op, mode);
6661 general_extend_operand (op, mode)
6663 enum machine_mode mode;
6665 return (GET_CODE (op) == TRUNCATE
6667 : nonimmediate_operand) (op, mode);
6671 inqhi_operand (op, mode)
6673 enum machine_mode mode;
6675 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
6678 /* Can't use true_regnum here because copy_cost wants to know about
6679 SECONDARY_INPUT_RELOAD_CLASS. */
6680 return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
6684 sh_rep_vec (v, mode)
6686 enum machine_mode mode;
6691 if ((GET_CODE (v) != CONST_VECTOR && GET_CODE (v) != PARALLEL)
6692 || (GET_MODE (v) != mode && mode != VOIDmode))
6694 i = XVECLEN (v, 0) - 2;
6695 x = XVECEXP (v, 0, i + 1);
6696 if (GET_MODE_UNIT_SIZE (mode) == 1)
6698 y = XVECEXP (v, 0, i);
6699 for (i -= 2 ; i >= 0; i -= 2)
6700 if (! rtx_equal_p (XVECEXP (v, 0, i + 1), x)
6701 || ! rtx_equal_p (XVECEXP (v, 0, i), y))
6706 if (XVECEXP (v, 0, i) != x)
6711 /* Determine if V is a constant vector matching MODE with only one element
6712 that is not a sign extension. Two byte-sized elements count as one. */
6714 sh_1el_vec (v, mode)
6716 enum machine_mode mode;
6719 int i, last, least, sign_ix;
6722 if (GET_CODE (v) != CONST_VECTOR
6723 || (GET_MODE (v) != mode && mode != VOIDmode))
6725 /* Determine numbers of last and of least significant elements. */
6726 last = XVECLEN (v, 0) - 1;
6727 least = TARGET_LITTLE_ENDIAN ? 0 : last;
6728 if (GET_CODE (XVECEXP (v, 0, least)) != CONST_INT)
6731 if (GET_MODE_UNIT_SIZE (mode) == 1)
6732 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
6733 if (GET_CODE (XVECEXP (v, 0, sign_ix)) != CONST_INT)
6735 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (v));
6736 sign = (INTVAL (XVECEXP (v, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
6737 ? constm1_rtx : const0_rtx);
6738 i = XVECLEN (v, 0) - 1;
6740 if (i != least && i != sign_ix && XVECEXP (v, 0, i) != sign)
6747 sh_const_vec (v, mode)
6749 enum machine_mode mode;
6753 if (GET_CODE (v) != CONST_VECTOR
6754 || (GET_MODE (v) != mode && mode != VOIDmode))
6756 i = XVECLEN (v, 0) - 1;
6758 if (GET_CODE (XVECEXP (v, 0, i)) != CONST_INT)
6763 /* Return the destination address of a branch. */
6766 branch_dest (branch)
6769 rtx dest = SET_SRC (PATTERN (branch));
6772 if (GET_CODE (dest) == IF_THEN_ELSE)
6773 dest = XEXP (dest, 1);
6774 dest = XEXP (dest, 0);
6775 dest_uid = INSN_UID (dest);
6776 return INSN_ADDRESSES (dest_uid);
6779 /* Return nonzero if REG is not used after INSN.
6780 We assume REG is a reload reg, and therefore does
6781 not live past labels. It may live past calls or jumps though. */
6783 reg_unused_after (reg, insn)
6790 /* If the reg is set by this instruction, then it is safe for our
6791 case. Disregard the case where this is a store to memory, since
6792 we are checking a register used in the store address. */
6793 set = single_set (insn);
6794 if (set && GET_CODE (SET_DEST (set)) != MEM
6795 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6798 while ((insn = NEXT_INSN (insn)))
6800 code = GET_CODE (insn);
6803 /* If this is a label that existed before reload, then the register
6804 if dead here. However, if this is a label added by reorg, then
6805 the register may still be live here. We can't tell the difference,
6806 so we just ignore labels completely. */
6807 if (code == CODE_LABEL)
6812 if (code == JUMP_INSN)
6815 /* If this is a sequence, we must handle them all at once.
6816 We could have for instance a call that sets the target register,
6817 and an insn in a delay slot that uses the register. In this case,
6818 we must return 0. */
6819 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
6824 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
6826 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
6827 rtx set = single_set (this_insn);
6829 if (GET_CODE (this_insn) == CALL_INSN)
6831 else if (GET_CODE (this_insn) == JUMP_INSN)
6833 if (INSN_ANNULLED_BRANCH_P (this_insn))
6838 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
6840 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6842 if (GET_CODE (SET_DEST (set)) != MEM)
6848 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
6853 else if (code == JUMP_INSN)
6856 else if (GET_RTX_CLASS (code) == 'i')
6858 rtx set = single_set (insn);
6860 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
6862 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6863 return GET_CODE (SET_DEST (set)) != MEM;
6864 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
6868 if (code == CALL_INSN && call_used_regs[REGNO (reg)])
6876 static GTY(()) rtx fpscr_rtx;
6882 fpscr_rtx = gen_rtx (REG, PSImode, FPSCR_REG);
6883 REG_USERVAR_P (fpscr_rtx) = 1;
6884 mark_user_reg (fpscr_rtx);
6886 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
6887 mark_user_reg (fpscr_rtx);
6906 expand_sf_unop (fun, operands)
6907 rtx (*fun) PARAMS ((rtx, rtx, rtx));
6910 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
6914 expand_sf_binop (fun, operands)
6915 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
6918 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
6923 expand_df_unop (fun, operands)
6924 rtx (*fun) PARAMS ((rtx, rtx, rtx));
6927 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
6931 expand_df_binop (fun, operands)
6932 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
6935 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
6939 /* ??? gcc does flow analysis strictly after common subexpression
6940 elimination. As a result, common subexpression elimination fails
6941 when there are some intervening statements setting the same register.
6942 If we did nothing about this, this would hurt the precision switching
6943 for SH4 badly. There is some cse after reload, but it is unable to
6944 undo the extra register pressure from the unused instructions, and
6945 it cannot remove auto-increment loads.
6947 A C code example that shows this flow/cse weakness for (at least) SH
6948 and sparc (as of gcc ss-970706) is this:
6962 So we add another pass before common subexpression elimination, to
6963 remove assignments that are dead due to a following assignment in the
6964 same basic block. */
6967 mark_use (x, reg_set_block)
6968 rtx x, *reg_set_block;
6974 code = GET_CODE (x);
6979 int regno = REGNO (x);
6980 int nregs = (regno < FIRST_PSEUDO_REGISTER
6981 ? HARD_REGNO_NREGS (regno, GET_MODE (x))
6985 reg_set_block[regno + nregs - 1] = 0;
6992 rtx dest = SET_DEST (x);
6994 if (GET_CODE (dest) == SUBREG)
6995 dest = SUBREG_REG (dest);
6996 if (GET_CODE (dest) != REG)
6997 mark_use (dest, reg_set_block);
6998 mark_use (SET_SRC (x), reg_set_block);
7005 const char *fmt = GET_RTX_FORMAT (code);
7007 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7010 mark_use (XEXP (x, i), reg_set_block);
7011 else if (fmt[i] == 'E')
7012 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7013 mark_use (XVECEXP (x, i, j), reg_set_block);
7020 static rtx get_free_reg PARAMS ((HARD_REG_SET));
7022 /* This function returns a register to use to load the address to load
7023 the fpscr from. Currently it always returns r1 or r7, but when we are
7024 able to use pseudo registers after combine, or have a better mechanism
7025 for choosing a register, it should be done here. */
7026 /* REGS_LIVE is the liveness information for the point for which we
7027 need this allocation. In some bare-bones exit blocks, r1 is live at the
7028 start. We can even have all of r0..r3 being live:
7029 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
7030 INSN before which new insns are placed with will clobber the register
7031 we return. If a basic block consists only of setting the return value
7032 register to a pseudo and using that register, the return value is not
7033 live before or after this block, yet we we'll insert our insns right in
7037 get_free_reg (regs_live)
7038 HARD_REG_SET regs_live;
7040 if (! TEST_HARD_REG_BIT (regs_live, 1))
7041 return gen_rtx_REG (Pmode, 1);
7043 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
7044 there shouldn't be anything but a jump before the function end. */
7045 if (! TEST_HARD_REG_BIT (regs_live, 7))
7046 return gen_rtx_REG (Pmode, 7);
7051 /* This function will set the fpscr from memory.
7052 MODE is the mode we are setting it to. */
7054 fpscr_set_from_mem (mode, regs_live)
7056 HARD_REG_SET regs_live;
7058 enum attr_fp_mode fp_mode = mode;
7059 rtx addr_reg = get_free_reg (regs_live);
7061 if (fp_mode == (enum attr_fp_mode) NORMAL_MODE (FP_MODE))
7062 emit_insn (gen_fpu_switch1 (addr_reg));
7064 emit_insn (gen_fpu_switch0 (addr_reg));
7067 /* Is the given character a logical line separator for the assembler? */
7068 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
7069 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
7073 sh_insn_length_adjustment (insn)
7076 /* Instructions with unfilled delay slots take up an extra two bytes for
7077 the nop in the delay slot. */
7078 if (((GET_CODE (insn) == INSN
7079 && GET_CODE (PATTERN (insn)) != USE
7080 && GET_CODE (PATTERN (insn)) != CLOBBER)
7081 || GET_CODE (insn) == CALL_INSN
7082 || (GET_CODE (insn) == JUMP_INSN
7083 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
7084 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
7085 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
7086 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
7089 /* SH2e has a bug that prevents the use of annulled branches, so if
7090 the delay slot is not filled, we'll have to put a NOP in it. */
7091 if (sh_cpu == CPU_SH2E
7092 && GET_CODE (insn) == JUMP_INSN
7093 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
7094 && GET_CODE (PATTERN (insn)) != ADDR_VEC
7095 && get_attr_type (insn) == TYPE_CBRANCH
7096 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
7099 /* sh-dsp parallel processing insn take four bytes instead of two. */
7101 if (GET_CODE (insn) == INSN)
7104 rtx body = PATTERN (insn);
7105 const char *template;
7107 int maybe_label = 1;
7109 if (GET_CODE (body) == ASM_INPUT)
7110 template = XSTR (body, 0);
7111 else if (asm_noperands (body) >= 0)
7113 = decode_asm_operands (body, NULL, NULL, NULL, NULL);
7122 while (c == ' ' || c == '\t');
7123 /* all sh-dsp parallel-processing insns start with p.
7124 The only non-ppi sh insn starting with p is pref.
7125 The only ppi starting with pr is prnd. */
7126 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
7128 /* The repeat pseudo-insn expands two three insns, a total of
7129 six bytes in size. */
7130 else if ((c == 'r' || c == 'R')
7131 && ! strncasecmp ("epeat", template, 5))
7133 while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c))
7135 /* If this is a label, it is obviously not a ppi insn. */
7136 if (c == ':' && maybe_label)
7141 else if (c == '\'' || c == '"')
7146 maybe_label = c != ':';
7154 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
7155 isn't protected by a PIC unspec. */
7157 nonpic_symbol_mentioned_p (x)
7160 register const char *fmt;
7163 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
7164 || GET_CODE (x) == PC)
7167 /* We don't want to look into the possible MEM location of a
7168 CONST_DOUBLE, since we're not going to use it, in general. */
7169 if (GET_CODE (x) == CONST_DOUBLE)
7172 if (GET_CODE (x) == UNSPEC
7173 && (XINT (x, 1) == UNSPEC_PIC
7174 || XINT (x, 1) == UNSPEC_GOT
7175 || XINT (x, 1) == UNSPEC_GOTOFF
7176 || XINT (x, 1) == UNSPEC_GOTPLT
7177 || XINT (x, 1) == UNSPEC_PLT))
7180 fmt = GET_RTX_FORMAT (GET_CODE (x));
7181 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
7187 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7188 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
7191 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
7198 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
7199 @GOTOFF in `reg'. */
7201 legitimize_pic_address (orig, mode, reg)
7203 enum machine_mode mode ATTRIBUTE_UNUSED;
7206 if (GET_CODE (orig) == LABEL_REF
7207 || (GET_CODE (orig) == SYMBOL_REF
7208 && (CONSTANT_POOL_ADDRESS_P (orig)
7209 /* SYMBOL_REF_FLAG is set on static symbols. */
7210 || SYMBOL_REF_FLAG (orig))))
7213 reg = gen_reg_rtx (Pmode);
7215 emit_insn (gen_symGOTOFF2reg (reg, orig));
7218 else if (GET_CODE (orig) == SYMBOL_REF)
7221 reg = gen_reg_rtx (Pmode);
7223 emit_insn (gen_symGOT2reg (reg, orig));
7229 /* Mark the use of a constant in the literal table. If the constant
7230 has multiple labels, make it unique. */
7232 mark_constant_pool_use (x)
7235 rtx insn, lab, pattern;
7240 switch (GET_CODE (x))
7250 /* Get the first label in the list of labels for the same constant
7251 and delete another labels in the list. */
7253 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
7255 if (GET_CODE (insn) != CODE_LABEL
7256 || LABEL_REFS (insn) != NEXT_INSN (insn))
7261 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
7262 INSN_DELETED_P (insn) = 1;
7264 /* Mark constants in a window. */
7265 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
7267 if (GET_CODE (insn) != INSN)
7270 pattern = PATTERN (insn);
7271 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
7274 switch (XINT (pattern, 1))
7276 case UNSPECV_CONST2:
7277 case UNSPECV_CONST4:
7278 case UNSPECV_CONST8:
7279 XVECEXP (pattern, 0, 1) = const1_rtx;
7281 case UNSPECV_WINDOW_END:
7282 if (XVECEXP (pattern, 0, 0) == x)
7285 case UNSPECV_CONST_END:
7295 /* Return true if it's possible to redirect BRANCH1 to the destination
7296 of an unconditional jump BRANCH2. We only want to do this if the
7297 resulting branch will have a short displacement. */
7299 sh_can_redirect_branch (branch1, branch2)
7303 if (flag_expensive_optimizations && simplejump_p (branch2))
7305 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
7309 for (distance = 0, insn = NEXT_INSN (branch1);
7310 insn && distance < 256;
7311 insn = PREV_INSN (insn))
7316 distance += get_attr_length (insn);
7318 for (distance = 0, insn = NEXT_INSN (branch1);
7319 insn && distance < 256;
7320 insn = NEXT_INSN (insn))
7325 distance += get_attr_length (insn);
7331 /* Return nonzero if register old_reg can be renamed to register new_reg. */
7333 sh_hard_regno_rename_ok (old_reg, new_reg)
7334 unsigned int old_reg ATTRIBUTE_UNUSED;
7335 unsigned int new_reg;
7338 /* Interrupt functions can only use registers that have already been
7339 saved by the prologue, even if they would normally be
7342 if (sh_cfun_interrupt_handler_p () && !regs_ever_live[new_reg])
7348 /* Function to update the integer COST
7349 based on the relationship between INSN that is dependent on
7350 DEP_INSN through the dependence LINK. The default is to make no
7351 adjustment to COST. This can be used for example to specify to
7352 the scheduler that an output- or anti-dependence does not incur
7353 the same cost as a data-dependence. The return value should be
7354 the new value for COST. */
7356 sh_adjust_cost (insn, link, dep_insn, cost)
7358 rtx link ATTRIBUTE_UNUSED;
7366 /* On SHmedia, if the dependence is an anti-dependence or
7367 output-dependence, there is no cost. */
7368 if (REG_NOTE_KIND (link) != 0)
7371 if (get_attr_is_mac_media (insn)
7372 && get_attr_is_mac_media (dep_insn))
7375 else if (REG_NOTE_KIND (link) == 0)
7377 enum attr_type dep_type, type;
7379 if (recog_memoized (insn) < 0
7380 || recog_memoized (dep_insn) < 0)
7383 dep_type = get_attr_type (dep_insn);
7384 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
7386 if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
7387 && (type = get_attr_type (insn)) != TYPE_CALL
7388 && type != TYPE_SFUNC)
7391 /* The only input for a call that is timing-critical is the
7392 function's address. */
7393 if (GET_CODE(insn) == CALL_INSN)
7395 rtx call = PATTERN (insn);
7397 if (GET_CODE (call) == PARALLEL)
7398 call = XVECEXP (call, 0 ,0);
7399 if (GET_CODE (call) == SET)
7400 call = SET_SRC (call);
7401 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
7402 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))
7405 /* Likewise, the most timing critical input for an sfuncs call
7406 is the function address. However, sfuncs typically start
7407 using their arguments pretty quickly.
7408 Assume a four cycle delay before they are needed. */
7409 /* All sfunc calls are parallels with at least four components.
7410 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
7411 else if (GET_CODE (PATTERN (insn)) == PARALLEL
7412 && XVECLEN (PATTERN (insn), 0) >= 4
7413 && (reg = sfunc_uses_reg (insn)))
7415 if (! reg_set_p (reg, dep_insn))
7418 /* When the preceding instruction loads the shift amount of
7419 the following SHAD/SHLD, the latency of the load is increased
7422 && get_attr_type (insn) == TYPE_DYN_SHIFT
7423 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
7424 && reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
7425 XEXP (SET_SRC (single_set(insn)),
7428 /* When an LS group instruction with a latency of less than
7429 3 cycles is followed by a double-precision floating-point
7430 instruction, FIPR, or FTRV, the latency of the first
7431 instruction is increased to 3 cycles. */
7433 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
7434 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
7436 /* The lsw register of a double-precision computation is ready one
7438 else if (reload_completed
7439 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
7440 && (use_pat = single_set (insn))
7441 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
7445 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
7446 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
7449 /* An anti-dependence penalty of two applies if the first insn is a double
7450 precision fadd / fsub / fmul. */
7451 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI
7452 && recog_memoized (dep_insn) >= 0
7453 && get_attr_type (dep_insn) == TYPE_DFP_ARITH
7454 /* A lot of alleged anti-flow dependences are fake,
7455 so check this one is real. */
7456 && flow_dependent_p (dep_insn, insn))
7463 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
7464 if DEP_INSN is anti-flow dependent on INSN. */
7466 flow_dependent_p (insn, dep_insn)
7469 rtx tmp = PATTERN (insn);
7471 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
7472 return tmp == NULL_RTX;
7475 /* A helper function for flow_dependent_p called through note_stores. */
7477 flow_dependent_p_1 (x, pat, data)
7479 rtx pat ATTRIBUTE_UNUSED;
7482 rtx * pinsn = (rtx *) data;
7484 if (*pinsn && reg_referenced_p (x, *pinsn))
7488 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
7489 'special function' patterns (type sfunc) that clobber pr, but that
7490 do not look like function calls to leaf_function_p. Hence we must
7491 do this extra check. */
7495 return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
7498 /* This Function returns nonzero if the DFA based scheduler interface
7499 is to be used. At present this is supported for the SH4 only. */
7501 sh_use_dfa_interface()
7503 if (TARGET_HARD_SH4)
7509 /* This function returns "2" to indicate dual issue for the SH4
7510 processor. To be used by the DFA pipeline description. */
7514 if (TARGET_SUPERSCALAR)
7520 /* SHmedia requires registers for branches, so we can't generate new
7521 branches past reload. */
7523 sh_cannot_modify_jumps_p ()
7525 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
7529 sh_ms_bitfield_layout_p (record_type)
7530 tree record_type ATTRIBUTE_UNUSED;
7535 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
7536 may access it using GOTOFF instead of GOT. */
7539 sh_encode_section_info (decl, first)
7546 rtl = DECL_RTL (decl);
7548 rtl = TREE_CST_RTL (decl);
7549 if (GET_CODE (rtl) != MEM)
7551 symbol = XEXP (rtl, 0);
7552 if (GET_CODE (symbol) != SYMBOL_REF)
7556 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
7558 if (TARGET_SH5 && first && TREE_CODE (decl) != FUNCTION_DECL)
7559 XEXP (rtl, 0) = gen_datalabel_ref (symbol);
7562 /* Undo the effects of the above. */
7565 sh_strip_name_encoding (str)
7568 STRIP_DATALABEL_ENCODING (str, str);
7575 On the SH1..SH4, the trampoline looks like
7576 2 0002 D202 mov.l l2,r2
7577 1 0000 D301 mov.l l1,r3
7580 5 0008 00000000 l1: .long area
7581 6 000c 00000000 l2: .long function
7583 SH5 (compact) uses r1 instead of r3 for the static chain. */
7586 /* Emit RTL insns to initialize the variable parts of a trampoline.
7587 FNADDR is an RTX for the address of the function's pure code.
7588 CXT is an RTX for the static chain value for the function. */
7591 sh_initialize_trampoline (tramp, fnaddr, cxt)
7592 rtx tramp, fnaddr, cxt;
7594 if (TARGET_SHMEDIA64)
7599 rtx movi1 = GEN_INT (0xcc000010);
7600 rtx shori1 = GEN_INT (0xc8000010);
7603 /* The following trampoline works within a +- 128 KB range for cxt:
7604 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
7605 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
7606 gettr tr1,r1; blink tr0,r63 */
7607 /* Address rounding makes it hard to compute the exact bounds of the
7608 offset for this trampoline, but we have a rather generous offset
7609 range, so frame_offset should do fine as an upper bound. */
7610 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
7612 /* ??? could optimize this trampoline initialization
7613 by writing DImode words with two insns each. */
7614 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
7615 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
7616 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
7617 insn = gen_rtx_AND (DImode, insn, mask);
7618 /* Or in ptb/u .,tr1 pattern */
7619 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
7620 insn = force_operand (insn, NULL_RTX);
7621 insn = gen_lowpart (SImode, insn);
7622 emit_move_insn (gen_rtx_MEM (SImode, tramp), insn);
7623 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
7624 insn = gen_rtx_AND (DImode, insn, mask);
7625 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
7626 insn = gen_lowpart (SImode, insn);
7627 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), insn);
7628 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
7629 insn = gen_rtx_AND (DImode, insn, mask);
7630 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
7631 insn = gen_lowpart (SImode, insn);
7632 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), insn);
7633 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
7634 insn = gen_rtx_AND (DImode, insn, mask);
7635 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
7636 insn = gen_lowpart (SImode, insn);
7637 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7639 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
7640 insn = gen_rtx_AND (DImode, insn, mask);
7641 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
7642 insn = gen_lowpart (SImode, insn);
7643 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 16)),
7645 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 20)),
7646 GEN_INT (0x6bf10600));
7647 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 24)),
7648 GEN_INT (0x4415fc10));
7649 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 28)),
7650 GEN_INT (0x4401fff0));
7651 emit_insn (gen_ic_invalidate_line (tramp));
7654 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
7655 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
7657 tramp_templ = gen_datalabel_ref (tramp_templ);
7658 dst = gen_rtx_MEM (BLKmode, tramp);
7659 src = gen_rtx_MEM (BLKmode, tramp_templ);
7660 set_mem_align (dst, 256);
7661 set_mem_align (src, 64);
7662 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
7664 emit_move_insn (gen_rtx_MEM (Pmode, plus_constant (tramp, fixed_len)),
7666 emit_move_insn (gen_rtx_MEM (Pmode,
7667 plus_constant (tramp,
7669 + GET_MODE_SIZE (Pmode))),
7671 emit_insn (gen_ic_invalidate_line (tramp));
7674 else if (TARGET_SHMEDIA)
7676 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
7677 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
7678 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
7679 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
7680 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
7681 rotated 10 right, and higher 16 bit of every 32 selected. */
7683 = force_reg (V2HImode, (simplify_gen_subreg
7684 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
7685 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
7686 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
7688 tramp = force_reg (Pmode, tramp);
7689 fnaddr = force_reg (SImode, fnaddr);
7690 cxt = force_reg (SImode, cxt);
7691 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
7692 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
7694 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
7695 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
7696 emit_insn (gen_ashldi3_media (quad0, quad0, GEN_INT (2)));
7697 emit_move_insn (gen_rtx_MEM (DImode, tramp), quad0);
7698 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
7699 gen_rtx_SUBREG (V2HImode, cxt, 0),
7701 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
7702 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
7703 emit_insn (gen_ashldi3_media (cxtload, cxtload, GEN_INT (2)));
7704 if (TARGET_LITTLE_ENDIAN)
7706 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
7707 emit_insn (gen_mextr4 (quad2, cxtload, blink));
7711 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
7712 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
7714 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 8)), quad1);
7715 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), quad2);
7716 emit_insn (gen_ic_invalidate_line (tramp));
7719 else if (TARGET_SHCOMPACT)
7721 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
7724 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7725 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
7727 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7728 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
7730 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7732 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7736 if (TARGET_USERMODE)
7737 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__ic_invalidate"),
7738 0, VOIDmode, 1, tramp, SImode);
7740 emit_insn (gen_ic_invalidate_line (tramp));
7744 /* FIXME: This is overly conservative. A SHcompact function that
7745 receives arguments ``by reference'' will have them stored in its
7746 own stack frame, so it must not pass pointers or references to
7747 these arguments to other functions by means of sibling calls. */
7749 sh_function_ok_for_sibcall (decl, exp)
7751 tree exp ATTRIBUTE_UNUSED;
7754 && (! TARGET_SHCOMPACT
7755 || current_function_args_info.stack_regs == 0));
7758 /* Machine specific built-in functions. */
7760 struct builtin_description
7762 const enum insn_code icode;
7763 const char *const name;
7767 /* describe number and signedness of arguments; arg[0] == result
7768 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
7769 static const char signature_args[][4] =
7771 #define SH_BLTIN_V2SI2 0
7773 #define SH_BLTIN_V4HI2 1
7775 #define SH_BLTIN_V2SI3 2
7777 #define SH_BLTIN_V4HI3 3
7779 #define SH_BLTIN_V8QI3 4
7781 #define SH_BLTIN_MAC_HISI 5
7783 #define SH_BLTIN_SH_HI 6
7785 #define SH_BLTIN_SH_SI 7
7787 #define SH_BLTIN_V4HI2V2SI 8
7789 #define SH_BLTIN_V4HI2V8QI 9
7791 #define SH_BLTIN_SISF 10
7793 #define SH_BLTIN_LDUA_L 11
7795 #define SH_BLTIN_LDUA_Q 12
7797 #define SH_BLTIN_STUA_L 13
7799 #define SH_BLTIN_STUA_Q 14
7801 #define SH_BLTIN_UDI 15
7803 #define SH_BLTIN_NUM_SHARED_SIGNATURES 16
7804 #define SH_BLTIN_2 16
7805 #define SH_BLTIN_SU 16
7807 #define SH_BLTIN_3 17
7808 #define SH_BLTIN_SUS 17
7810 #define SH_BLTIN_PSSV 18
7812 #define SH_BLTIN_XXUU 19
7813 #define SH_BLTIN_UUUU 19
7815 #define SH_BLTIN_PV 20
7818 /* mcmv: operands considered unsigned. */
7819 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
7820 /* mperm: control value considered unsigned int. */
7821 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
7822 /* mshards_q: returns signed short. */
7823 /* nsb: takes long long arg, returns unsigned char. */
7824 static const struct builtin_description bdesc[] =
7826 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
7827 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
7828 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
7829 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
7830 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
7831 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
7832 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
7834 { CODE_FOR_alloco32, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
7835 { CODE_FOR_alloco64, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
7837 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
7838 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
7839 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
7840 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
7841 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
7842 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
7843 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
7844 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
7845 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
7846 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
7847 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI },
7848 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI },
7849 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI },
7850 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI },
7851 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI },
7852 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI },
7853 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI },
7854 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
7855 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
7856 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
7857 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
7858 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
7859 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
7860 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
7861 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
7862 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
7863 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
7864 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
7865 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
7866 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
7867 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
7868 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
7869 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
7870 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
7871 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
7872 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
7873 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
7874 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
7875 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
7876 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
7877 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
7878 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
7879 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
7880 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
7881 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
7882 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
7883 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
7884 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
7885 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
7886 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
7887 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
7888 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
7889 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
7890 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
7892 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
7893 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
7894 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
7895 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
7896 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
7897 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
7898 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
7899 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
7900 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
7901 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
7902 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
7903 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
7904 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
7905 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
7906 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
7907 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
7909 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
7910 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
7912 { CODE_FOR_prefetch32,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
7913 { CODE_FOR_prefetch64,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV }
7918 sh_media_init_builtins ()
7920 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
7921 const struct builtin_description *d;
7923 memset (shared, 0, sizeof shared);
7924 for (d = bdesc; d - bdesc < (int) (sizeof bdesc / sizeof bdesc[0]); d++)
7926 tree type, arg_type;
7927 int signature = d->signature;
7930 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
7931 type = shared[signature];
7934 int has_result = signature_args[signature][0] != 0;
7936 if (signature_args[signature][1] == 8
7937 && (insn_data[d->icode].operand[has_result].mode != Pmode))
7939 if (! TARGET_FPU_ANY
7940 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
7942 type = void_list_node;
7945 int arg = signature_args[signature][i];
7946 int opno = i - 1 + has_result;
7949 arg_type = ptr_type_node;
7951 arg_type = ((*lang_hooks.types.type_for_mode)
7952 (insn_data[d->icode].operand[opno].mode,
7957 arg_type = void_type_node;
7960 type = tree_cons (NULL_TREE, arg_type, type);
7962 type = build_function_type (arg_type, type);
7963 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
7964 shared[signature] = type;
7966 builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
7975 sh_media_init_builtins ();
7978 /* Expand an expression EXP that calls a built-in function,
7979 with result going to TARGET if that's convenient
7980 (and in mode MODE if that's convenient).
7981 SUBTARGET may be used as the target for computing one of EXP's operands.
7982 IGNORE is nonzero if the value is to be ignored. */
7985 sh_expand_builtin (exp, target, subtarget, mode, ignore)
7988 rtx subtarget ATTRIBUTE_UNUSED;
7989 enum machine_mode mode ATTRIBUTE_UNUSED;
7992 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7993 tree arglist = TREE_OPERAND (exp, 1);
7994 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7995 const struct builtin_description *d = &bdesc[fcode];
7996 enum insn_code icode = d->icode;
7997 int signature = d->signature;
7998 enum machine_mode tmode = VOIDmode;
8003 if (signature_args[signature][0])
8008 tmode = insn_data[icode].operand[0].mode;
8010 || GET_MODE (target) != tmode
8011 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8012 target = gen_reg_rtx (tmode);
8018 for (i = 1; i <= 3; i++, nop++)
8021 enum machine_mode opmode, argmode;
8023 if (! signature_args[signature][i])
8025 arg = TREE_VALUE (arglist);
8026 if (arg == error_mark_node)
8028 arglist = TREE_CHAIN (arglist);
8029 opmode = insn_data[icode].operand[nop].mode;
8030 argmode = TYPE_MODE (TREE_TYPE (arg));
8031 if (argmode != opmode)
8032 arg = build1 (NOP_EXPR,
8033 (*lang_hooks.types.type_for_mode) (opmode, 0), arg);
8034 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
8035 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
8036 op[nop] = copy_to_mode_reg (opmode, op[nop]);
8042 pat = (*insn_data[d->icode].genfun) (op[0]);
8045 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
8048 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
8051 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
8063 sh_expand_unop_v2sf (code, op0, op1)
8067 rtx sel0 = const0_rtx;
8068 rtx sel1 = const1_rtx;
8069 rtx (*fn) PARAMS ((rtx, rtx, rtx, rtx, rtx)) = gen_unary_sf_op;
8070 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
8072 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
8073 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
8077 sh_expand_binop_v2sf (code, op0, op1, op2)
8081 rtx sel0 = const0_rtx;
8082 rtx sel1 = const1_rtx;
8083 rtx (*fn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx, rtx)) = gen_binary_sf_op;
8084 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
8086 emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0));
8087 emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1));
8090 /* Return the class of registers for which a mode change from FROM to TO
8093 sh_cannot_change_mode_class (from, to, class)
8094 enum machine_mode from, to;
8095 enum reg_class class;
8097 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
8099 if (TARGET_LITTLE_ENDIAN)
8101 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
8102 return reg_classes_intersect_p (DF_REGS, class);
8106 if (GET_MODE_SIZE (from) < 8)
8107 return reg_classes_intersect_p (DF_HI_REGS, class);
8114 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
8115 that label is used. */
8118 sh_mark_label (address, nuses)
8122 if (GOTOFF_P (address))
8124 /* Extract the label or symbol. */
8125 address = XEXP (address, 0);
8126 if (GET_CODE (address) == PLUS)
8127 address = XEXP (address, 0);
8128 address = XVECEXP (address, 0, 0);
8130 if (GET_CODE (address) == LABEL_REF
8131 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
8132 LABEL_NUSES (XEXP (address, 0)) += nuses;
8135 /* Compute extra cost of moving data between one register class
8138 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
8139 uses this information. Hence, the general register <-> floating point
8140 register information here is not used for SFmode. */
8143 sh_register_move_cost (mode, srcclass, dstclass)
8144 enum machine_mode mode;
8145 enum reg_class srcclass, dstclass;
8147 if (dstclass == T_REGS || dstclass == PR_REGS)
8150 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
8151 && REGCLASS_HAS_FP_REG (srcclass)
8152 && REGCLASS_HAS_FP_REG (dstclass))
8155 if ((REGCLASS_HAS_FP_REG (dstclass)
8156 && REGCLASS_HAS_GENERAL_REG (srcclass))
8157 || (REGCLASS_HAS_GENERAL_REG (dstclass)
8158 && REGCLASS_HAS_FP_REG (srcclass)))
8159 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
8160 * ((GET_MODE_SIZE (mode) + 7) / 8U));
8162 if ((dstclass == FPUL_REGS
8163 && REGCLASS_HAS_GENERAL_REG (srcclass))
8164 || (srcclass == FPUL_REGS
8165 && REGCLASS_HAS_GENERAL_REG (dstclass)))
8168 if ((dstclass == FPUL_REGS
8169 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
8170 || (srcclass == FPUL_REGS
8171 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
8174 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
8175 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
8178 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
8179 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
8184 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
8185 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
8186 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
8188 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
8191 /* Like register_operand, but take into account that SHMEDIA can use
8192 the constant zero like a general register. */
8194 sh_register_operand (op, mode)
8196 enum machine_mode mode;
8198 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
8200 return register_operand (op, mode);