1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "insn-config.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
41 #include "integrate.h"
45 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 #include "sched-int.h"
54 #include "tree-gimple.h"
56 #include "alloc-pool.h"
57 #include "tm-constrs.h"
60 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
62 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
63 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
65 /* These are some macros to abstract register modes. */
66 #define CONST_OK_FOR_ADD(size) \
67 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
68 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
69 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
70 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
72 /* Used to simplify the logic below. Find the attributes wherever
74 #define SH_ATTRIBUTES(decl) \
75 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
76 : DECL_ATTRIBUTES (decl) \
77 ? (DECL_ATTRIBUTES (decl)) \
78 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
80 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
81 int current_function_interrupt;
83 tree sh_deferred_function_attributes;
84 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
86 /* Global variables for machine-dependent things. */
88 /* Which cpu are we scheduling for. */
89 enum processor_type sh_cpu;
91 /* Definitions used in ready queue reordering for first scheduling pass. */
93 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
94 static short *regmode_weight[2];
96 /* Total SFmode and SImode weights of scheduled insns. */
97 static int curr_regmode_pressure[2];
99 /* Number of r0 life regions. */
100 static int r0_life_regions;
102 /* If true, skip cycles for Q -> R movement. */
103 static int skip_cycles = 0;
105 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
106 and returned from sh_reorder2. */
107 static short cached_can_issue_more;
109 /* Saved operands from the last compare to use when we generate an scc
115 /* Provides the class number of the smallest class containing
118 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
120 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
136 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
152 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
153 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
154 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
155 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
156 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
157 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
158 GENERAL_REGS, GENERAL_REGS,
161 char sh_register_names[FIRST_PSEUDO_REGISTER] \
162 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
164 char sh_additional_register_names[ADDREGNAMES_SIZE] \
165 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
166 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
168 int assembler_dialect;
170 static bool shmedia_space_reserved_for_target_registers;
172 static bool sh_handle_option (size_t, const char *, int);
173 static void split_branches (rtx);
174 static int branch_dest (rtx);
175 static void force_into (rtx, rtx);
176 static void print_slot (rtx);
177 static rtx add_constant (rtx, enum machine_mode, rtx);
178 static void dump_table (rtx, rtx);
179 static int hi_const (rtx);
180 static int broken_move (rtx);
181 static int mova_p (rtx);
182 static rtx find_barrier (int, rtx, rtx);
183 static int noncall_uses_reg (rtx, rtx, rtx *);
184 static rtx gen_block_redirect (rtx, int, int);
185 static void sh_reorg (void);
186 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
187 static rtx frame_insn (rtx);
188 static rtx push (int);
189 static void pop (int);
190 static void push_regs (HARD_REG_SET *, int);
191 static int calc_live_regs (HARD_REG_SET *);
192 static HOST_WIDE_INT rounded_frame_size (int);
193 static rtx mark_constant_pool_use (rtx);
194 const struct attribute_spec sh_attribute_table[];
195 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
196 static tree sh_handle_resbank_handler_attribute (tree *, tree,
198 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
200 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
201 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
202 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
203 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
204 static void sh_insert_attributes (tree, tree *);
205 static const char *sh_check_pch_target_flags (int);
206 static int sh_adjust_cost (rtx, rtx, rtx, int);
207 static int sh_issue_rate (void);
208 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
209 static short find_set_regmode_weight (rtx, enum machine_mode);
210 static short find_insn_regmode_weight (rtx, enum machine_mode);
211 static void find_regmode_weight (basic_block, enum machine_mode);
212 static int find_r0_life_regions (basic_block);
213 static void sh_md_init_global (FILE *, int, int);
214 static void sh_md_finish_global (FILE *, int);
215 static int rank_for_reorder (const void *, const void *);
216 static void swap_reorder (rtx *, int);
217 static void ready_reorder (rtx *, int);
218 static short high_pressure (enum machine_mode);
219 static int sh_reorder (FILE *, int, rtx *, int *, int);
220 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
221 static void sh_md_init (FILE *, int, int);
222 static int sh_variable_issue (FILE *, int, rtx, int);
224 static bool sh_function_ok_for_sibcall (tree, tree);
226 static bool sh_cannot_modify_jumps_p (void);
227 static int sh_target_reg_class (void);
228 static bool sh_optimize_target_register_callee_saved (bool);
229 static bool sh_ms_bitfield_layout_p (const_tree);
231 static void sh_init_builtins (void);
232 static void sh_media_init_builtins (void);
233 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
234 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
235 static void sh_file_start (void);
236 static int flow_dependent_p (rtx, rtx);
237 static void flow_dependent_p_1 (rtx, const_rtx, void *);
238 static int shiftcosts (rtx);
239 static int andcosts (rtx);
240 static int addsubcosts (rtx);
241 static int multcosts (rtx);
242 static bool unspec_caller_rtx_p (rtx);
243 static bool sh_cannot_copy_insn_p (rtx);
244 static bool sh_rtx_costs (rtx, int, int, int *);
245 static int sh_address_cost (rtx);
246 static int sh_pr_n_sets (void);
247 static rtx sh_allocate_initial_value (rtx);
248 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
249 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
250 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
251 static int scavenge_reg (HARD_REG_SET *s);
252 struct save_schedule_s;
253 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
254 struct save_schedule_s *, int);
256 static rtx sh_struct_value_rtx (tree, int);
257 static bool sh_return_in_memory (const_tree, const_tree);
258 static rtx sh_builtin_saveregs (void);
259 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
260 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
261 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
262 static tree sh_build_builtin_va_list (void);
263 static void sh_va_start (tree, rtx);
264 static tree sh_gimplify_va_arg_expr (tree, tree, tree *, tree *);
265 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
267 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
269 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
271 static bool sh_scalar_mode_supported_p (enum machine_mode);
272 static int sh_dwarf_calling_convention (const_tree);
273 static void sh_encode_section_info (tree, rtx, int);
274 static int sh2a_function_vector_p (tree);
277 /* Initialize the GCC target structure. */
278 #undef TARGET_ATTRIBUTE_TABLE
279 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
281 /* The next two are used for debug info when compiling with -gdwarf. */
282 #undef TARGET_ASM_UNALIGNED_HI_OP
283 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
284 #undef TARGET_ASM_UNALIGNED_SI_OP
285 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
287 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
288 #undef TARGET_ASM_UNALIGNED_DI_OP
289 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
290 #undef TARGET_ASM_ALIGNED_DI_OP
291 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
293 #undef TARGET_ASM_FUNCTION_EPILOGUE
294 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
296 #undef TARGET_ASM_OUTPUT_MI_THUNK
297 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
299 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
300 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
302 #undef TARGET_ASM_FILE_START
303 #define TARGET_ASM_FILE_START sh_file_start
304 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
305 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
307 #undef TARGET_DEFAULT_TARGET_FLAGS
308 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
309 #undef TARGET_HANDLE_OPTION
310 #define TARGET_HANDLE_OPTION sh_handle_option
312 #undef TARGET_INSERT_ATTRIBUTES
313 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
315 #undef TARGET_SCHED_ADJUST_COST
316 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
318 #undef TARGET_SCHED_ISSUE_RATE
319 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
321 /* The next 5 hooks have been implemented for reenabling sched1. With the
322 help of these macros we are limiting the movement of insns in sched1 to
323 reduce the register pressure. The overall idea is to keep count of SImode
324 and SFmode regs required by already scheduled insns. When these counts
325 cross some threshold values; give priority to insns that free registers.
326 The insn that frees registers is most likely to be the insn with lowest
327 LUID (original insn order); but such an insn might be there in the stalled
328 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
329 upto a max of 8 cycles so that such insns may move from Q -> R.
331 The description of the hooks are as below:
333 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
334 scheduler; it is called inside the sched_init function just after
335 find_insn_reg_weights function call. It is used to calculate the SImode
336 and SFmode weights of insns of basic blocks; much similar to what
337 find_insn_reg_weights does.
338 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
340 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
341 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
344 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
345 high; reorder the ready queue so that the insn with lowest LUID will be
348 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
349 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
351 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
352 can be returned from TARGET_SCHED_REORDER2.
354 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
356 #undef TARGET_SCHED_DFA_NEW_CYCLE
357 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
359 #undef TARGET_SCHED_INIT_GLOBAL
360 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
362 #undef TARGET_SCHED_FINISH_GLOBAL
363 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
365 #undef TARGET_SCHED_VARIABLE_ISSUE
366 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
368 #undef TARGET_SCHED_REORDER
369 #define TARGET_SCHED_REORDER sh_reorder
371 #undef TARGET_SCHED_REORDER2
372 #define TARGET_SCHED_REORDER2 sh_reorder2
374 #undef TARGET_SCHED_INIT
375 #define TARGET_SCHED_INIT sh_md_init
377 #undef TARGET_CANNOT_MODIFY_JUMPS_P
378 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
379 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
380 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
381 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
382 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
383 sh_optimize_target_register_callee_saved
385 #undef TARGET_MS_BITFIELD_LAYOUT_P
386 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
388 #undef TARGET_INIT_BUILTINS
389 #define TARGET_INIT_BUILTINS sh_init_builtins
390 #undef TARGET_EXPAND_BUILTIN
391 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
393 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
394 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
396 #undef TARGET_CANNOT_COPY_INSN_P
397 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
398 #undef TARGET_RTX_COSTS
399 #define TARGET_RTX_COSTS sh_rtx_costs
400 #undef TARGET_ADDRESS_COST
401 #define TARGET_ADDRESS_COST sh_address_cost
402 #undef TARGET_ALLOCATE_INITIAL_VALUE
403 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
405 #undef TARGET_MACHINE_DEPENDENT_REORG
406 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
409 #undef TARGET_HAVE_TLS
410 #define TARGET_HAVE_TLS true
413 #undef TARGET_PROMOTE_PROTOTYPES
414 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
415 #undef TARGET_PROMOTE_FUNCTION_ARGS
416 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
417 #undef TARGET_PROMOTE_FUNCTION_RETURN
418 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
420 #undef TARGET_STRUCT_VALUE_RTX
421 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
422 #undef TARGET_RETURN_IN_MEMORY
423 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
425 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
426 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
427 #undef TARGET_SETUP_INCOMING_VARARGS
428 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
429 #undef TARGET_STRICT_ARGUMENT_NAMING
430 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
431 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
432 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
433 #undef TARGET_MUST_PASS_IN_STACK
434 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
435 #undef TARGET_PASS_BY_REFERENCE
436 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
437 #undef TARGET_CALLEE_COPIES
438 #define TARGET_CALLEE_COPIES sh_callee_copies
439 #undef TARGET_ARG_PARTIAL_BYTES
440 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
442 #undef TARGET_BUILD_BUILTIN_VA_LIST
443 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
444 #undef TARGET_EXPAND_BUILTIN_VA_START
445 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
446 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
447 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
449 #undef TARGET_SCALAR_MODE_SUPPORTED_P
450 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
451 #undef TARGET_VECTOR_MODE_SUPPORTED_P
452 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
454 #undef TARGET_CHECK_PCH_TARGET_FLAGS
455 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
457 #undef TARGET_DWARF_CALLING_CONVENTION
458 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
460 /* Return regmode weight for insn. */
461 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
463 /* Return current register pressure for regmode. */
464 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
466 #undef TARGET_ENCODE_SECTION_INFO
467 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
471 #undef TARGET_ENCODE_SECTION_INFO
472 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
473 #undef TARGET_STRIP_NAME_ENCODING
474 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
475 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
476 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
480 #undef TARGET_SECONDARY_RELOAD
481 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
483 /* Machine-specific symbol_ref flags. */
484 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
486 struct gcc_target targetm = TARGET_INITIALIZER;
488 /* Implement TARGET_HANDLE_OPTION. */
491 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
492 int value ATTRIBUTE_UNUSED)
497 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
501 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
505 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
509 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
513 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
516 case OPT_m2a_single_only:
517 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
521 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
525 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
529 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
536 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
540 case OPT_m4_100_nofpu:
541 case OPT_m4_200_nofpu:
542 case OPT_m4_300_nofpu:
546 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
550 case OPT_m4_100_single:
551 case OPT_m4_200_single:
552 case OPT_m4_300_single:
553 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
556 case OPT_m4_single_only:
557 case OPT_m4_100_single_only:
558 case OPT_m4_200_single_only:
559 case OPT_m4_300_single_only:
560 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
564 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
569 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
573 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
576 case OPT_m4a_single_only:
577 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
581 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
584 case OPT_m5_32media_nofpu:
585 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
589 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
592 case OPT_m5_64media_nofpu:
593 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
597 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
600 case OPT_m5_compact_nofpu:
601 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
609 /* Print the operand address in x to the stream. */
612 print_operand_address (FILE *stream, rtx x)
614 switch (GET_CODE (x))
618 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
623 rtx base = XEXP (x, 0);
624 rtx index = XEXP (x, 1);
626 switch (GET_CODE (index))
629 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
630 reg_names[true_regnum (base)]);
636 int base_num = true_regnum (base);
637 int index_num = true_regnum (index);
639 fprintf (stream, "@(r0,%s)",
640 reg_names[MAX (base_num, index_num)]);
651 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
655 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
659 x = mark_constant_pool_use (x);
660 output_addr_const (stream, x);
665 /* Print operand x (an rtx) in assembler syntax to file stream
666 according to modifier code.
668 '.' print a .s if insn needs delay slot
669 ',' print LOCAL_LABEL_PREFIX
670 '@' print trap, rte or rts depending upon pragma interruptness
671 '#' output a nop if there is nothing to put in the delay slot
672 ''' print likelihood suffix (/u for unlikely).
673 '>' print branch target if -fverbose-asm
674 'O' print a constant without the #
675 'R' print the LSW of a dp value - changes if in little endian
676 'S' print the MSW of a dp value - changes if in little endian
677 'T' print the next word of a dp value - same as 'R' in big endian mode.
678 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
679 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
680 'N' print 'r63' if the operand is (const_int 0).
681 'd' print a V2SF reg as dN instead of fpN.
682 'm' print a pair `base,offset' or `base,index', for LD and ST.
683 'U' Likewise for {LD,ST}{HI,LO}.
684 'V' print the position of a single bit set.
685 'W' print the position of a single bit cleared.
686 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
687 'o' output an operator. */
690 print_operand (FILE *stream, rtx x, int code)
693 enum machine_mode mode;
701 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
702 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
703 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
706 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
709 trapa_attr = lookup_attribute ("trap_exit",
710 DECL_ATTRIBUTES (current_function_decl));
712 fprintf (stream, "trapa #%ld",
713 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
714 else if (sh_cfun_interrupt_handler_p ())
716 if (sh_cfun_resbank_handler_p ())
717 fprintf (stream, "resbank\n");
718 fprintf (stream, "rte");
721 fprintf (stream, "rts");
724 /* Output a nop if there's nothing in the delay slot. */
725 if (dbr_sequence_length () == 0)
726 fprintf (stream, "\n\tnop");
730 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
732 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
733 fputs ("/u", stream);
737 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
739 fputs ("\t! target: ", stream);
740 output_addr_const (stream, JUMP_LABEL (current_output_insn));
744 x = mark_constant_pool_use (x);
745 output_addr_const (stream, x);
747 /* N.B.: %R / %S / %T adjust memory addresses by four.
748 For SHMEDIA, that means they can be used to access the first and
749 second 32 bit part of a 64 bit (or larger) value that
750 might be held in floating point registers or memory.
751 While they can be used to access 64 bit parts of a larger value
752 held in general purpose registers, that won't work with memory -
753 neither for fp registers, since the frxx names are used. */
755 if (REG_P (x) || GET_CODE (x) == SUBREG)
757 regno = true_regnum (x);
758 regno += FP_REGISTER_P (regno) ? 1 : LSW;
759 fputs (reg_names[regno], (stream));
763 x = adjust_address (x, SImode, 4 * LSW);
764 print_operand_address (stream, XEXP (x, 0));
771 if (mode == VOIDmode)
773 if (GET_MODE_SIZE (mode) >= 8)
774 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
776 print_operand (stream, sub, 0);
778 output_operand_lossage ("invalid operand to %%R");
782 if (REG_P (x) || GET_CODE (x) == SUBREG)
784 regno = true_regnum (x);
785 regno += FP_REGISTER_P (regno) ? 0 : MSW;
786 fputs (reg_names[regno], (stream));
790 x = adjust_address (x, SImode, 4 * MSW);
791 print_operand_address (stream, XEXP (x, 0));
798 if (mode == VOIDmode)
800 if (GET_MODE_SIZE (mode) >= 8)
801 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
803 print_operand (stream, sub, 0);
805 output_operand_lossage ("invalid operand to %%S");
809 /* Next word of a double. */
810 switch (GET_CODE (x))
813 fputs (reg_names[REGNO (x) + 1], (stream));
816 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
817 && GET_CODE (XEXP (x, 0)) != POST_INC)
818 x = adjust_address (x, SImode, 4);
819 print_operand_address (stream, XEXP (x, 0));
826 switch (GET_CODE (x))
828 case PLUS: fputs ("add", stream); break;
829 case MINUS: fputs ("sub", stream); break;
830 case MULT: fputs ("mul", stream); break;
831 case DIV: fputs ("div", stream); break;
832 case EQ: fputs ("eq", stream); break;
833 case NE: fputs ("ne", stream); break;
834 case GT: case LT: fputs ("gt", stream); break;
835 case GE: case LE: fputs ("ge", stream); break;
836 case GTU: case LTU: fputs ("gtu", stream); break;
837 case GEU: case LEU: fputs ("geu", stream); break;
845 if (GET_CODE (x) == MEM
846 && GET_CODE (XEXP (x, 0)) == PLUS
847 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
848 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
853 if (GET_CODE (x) == MEM)
855 switch (GET_MODE (x))
857 case QImode: fputs (".b", stream); break;
858 case HImode: fputs (".w", stream); break;
859 case SImode: fputs (".l", stream); break;
860 case SFmode: fputs (".s", stream); break;
861 case DFmode: fputs (".d", stream); break;
862 default: gcc_unreachable ();
869 gcc_assert (GET_CODE (x) == MEM);
873 switch (GET_CODE (x))
877 print_operand (stream, x, 0);
878 fputs (", 0", stream);
882 print_operand (stream, XEXP (x, 0), 0);
883 fputs (", ", stream);
884 print_operand (stream, XEXP (x, 1), 0);
894 int num = exact_log2 (INTVAL (x));
895 gcc_assert (num >= 0);
896 fprintf (stream, "#%d", num);
902 int num = exact_log2 (~INTVAL (x));
903 gcc_assert (num >= 0);
904 fprintf (stream, "#%d", num);
909 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == V2SFmode);
911 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
915 if (x == CONST0_RTX (GET_MODE (x)))
917 fprintf ((stream), "r63");
922 if (GET_CODE (x) == CONST_INT)
924 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
934 switch (GET_CODE (x))
938 rtx inner = XEXP (x, 0);
940 enum machine_mode inner_mode;
942 /* We might see SUBREGs with vector mode registers inside. */
943 if (GET_CODE (inner) == SUBREG
944 && (GET_MODE_SIZE (GET_MODE (inner))
945 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
946 && subreg_lowpart_p (inner))
947 inner = SUBREG_REG (inner);
948 if (GET_CODE (inner) == CONST_INT)
950 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
953 inner_mode = GET_MODE (inner);
954 if (GET_CODE (inner) == SUBREG
955 && (GET_MODE_SIZE (GET_MODE (inner))
956 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
957 && GET_CODE (SUBREG_REG (inner)) == REG)
959 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
960 GET_MODE (SUBREG_REG (inner)),
963 inner = SUBREG_REG (inner);
965 if (GET_CODE (inner) != REG || GET_MODE_SIZE (inner_mode) > 8)
967 /* Floating point register pairs are always big endian;
968 general purpose registers are 64 bit wide. */
969 regno = REGNO (inner);
970 regno = (HARD_REGNO_NREGS (regno, inner_mode)
971 - HARD_REGNO_NREGS (regno, mode))
979 /* FIXME: We need this on SHmedia32 because reload generates
980 some sign-extended HI or QI loads into DImode registers
981 but, because Pmode is SImode, the address ends up with a
982 subreg:SI of the DImode register. Maybe reload should be
983 fixed so as to apply alter_subreg to such loads? */
985 gcc_assert (trapping_target_operand (x, VOIDmode));
986 x = XEXP (XEXP (x, 2), 0);
989 gcc_assert (SUBREG_BYTE (x) == 0
990 && GET_CODE (SUBREG_REG (x)) == REG);
998 if (FP_REGISTER_P (regno)
999 && mode == V16SFmode)
1000 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1001 else if (FP_REGISTER_P (REGNO (x))
1002 && mode == V4SFmode)
1003 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1004 else if (GET_CODE (x) == REG
1005 && mode == V2SFmode)
1006 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1007 else if (FP_REGISTER_P (REGNO (x))
1008 && GET_MODE_SIZE (mode) > 4)
1009 fprintf ((stream), "d%s", reg_names[regno] + 1);
1011 fputs (reg_names[regno], (stream));
1015 output_address (XEXP (x, 0));
1020 && (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
1021 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
1022 && (GET_MODE (XEXP (x, 0)) == DImode
1023 || GET_MODE (XEXP (x, 0)) == SImode)
1024 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
1025 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
1027 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
1029 bool nested_expr = false;
1031 fputc ('(', stream);
1032 if (GET_CODE (val) == ASHIFTRT)
1034 fputc ('(', stream);
1035 val2 = XEXP (val, 0);
1037 if (GET_CODE (val2) == CONST
1038 || GET_RTX_CLASS (GET_CODE (val2)) != RTX_OBJ)
1040 fputc ('(', stream);
1043 output_addr_const (stream, val2);
1045 fputc (')', stream);
1046 if (GET_CODE (val) == ASHIFTRT)
1048 fputs (" >> ", stream);
1049 output_addr_const (stream, XEXP (val, 1));
1050 fputc (')', stream);
1052 fputs (" & 65535)", stream);
1059 fputc ('#', stream);
1060 output_addr_const (stream, x);
1068 /* Encode symbol attributes of a SYMBOL_REF into its
1069 SYMBOL_REF_FLAGS. */
1071 sh_encode_section_info (tree decl, rtx rtl, int first)
1073 default_encode_section_info (decl, rtl, first);
1075 if (TREE_CODE (decl) == FUNCTION_DECL
1076 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1077 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1080 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1082 force_into (rtx value, rtx target)
1084 value = force_operand (value, target);
1085 if (! rtx_equal_p (value, target))
1086 emit_insn (gen_move_insn (target, value));
1089 /* Emit code to perform a block move. Choose the best method.
1091 OPERANDS[0] is the destination.
1092 OPERANDS[1] is the source.
1093 OPERANDS[2] is the size.
1094 OPERANDS[3] is the alignment safe to use. */
1097 expand_block_move (rtx *operands)
1099 int align = INTVAL (operands[3]);
1100 int constp = (GET_CODE (operands[2]) == CONST_INT);
1101 int bytes = (constp ? INTVAL (operands[2]) : 0);
1106 /* If we could use mov.l to move words and dest is word-aligned, we
1107 can use movua.l for loads and still generate a relatively short
1108 and efficient sequence. */
1109 if (TARGET_SH4A_ARCH && align < 4
1110 && MEM_ALIGN (operands[0]) >= 32
1111 && can_move_by_pieces (bytes, 32))
1113 rtx dest = copy_rtx (operands[0]);
1114 rtx src = copy_rtx (operands[1]);
1115 /* We could use different pseudos for each copied word, but
1116 since movua can only load into r0, it's kind of
1118 rtx temp = gen_reg_rtx (SImode);
1119 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1122 while (copied + 4 <= bytes)
1124 rtx to = adjust_address (dest, SImode, copied);
1125 rtx from = adjust_automodify_address (src, BLKmode,
1128 set_mem_size (from, GEN_INT (4));
1129 emit_insn (gen_movua (temp, from));
1130 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1131 emit_move_insn (to, temp);
1136 move_by_pieces (adjust_address (dest, BLKmode, copied),
1137 adjust_automodify_address (src, BLKmode,
1139 bytes - copied, align, 0);
1144 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1145 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1146 if (align < 4 || (bytes % 4 != 0))
1149 if (TARGET_HARD_SH4)
1153 else if (bytes == 12)
1155 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1156 rtx r4 = gen_rtx_REG (SImode, 4);
1157 rtx r5 = gen_rtx_REG (SImode, 5);
1159 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1160 force_into (XEXP (operands[0], 0), r4);
1161 force_into (XEXP (operands[1], 0), r5);
1162 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1165 else if (! TARGET_SMALLCODE)
1167 const char *entry_name;
1168 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1170 rtx r4 = gen_rtx_REG (SImode, 4);
1171 rtx r5 = gen_rtx_REG (SImode, 5);
1172 rtx r6 = gen_rtx_REG (SImode, 6);
1174 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1175 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1176 force_into (XEXP (operands[0], 0), r4);
1177 force_into (XEXP (operands[1], 0), r5);
1179 dwords = bytes >> 3;
1180 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1181 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1190 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1191 rtx r4 = gen_rtx_REG (SImode, 4);
1192 rtx r5 = gen_rtx_REG (SImode, 5);
1194 sprintf (entry, "__movmemSI%d", bytes);
1195 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1196 force_into (XEXP (operands[0], 0), r4);
1197 force_into (XEXP (operands[1], 0), r5);
1198 emit_insn (gen_block_move_real (func_addr_rtx));
1202 /* This is the same number of bytes as a memcpy call, but to a different
1203 less common function name, so this will occasionally use more space. */
1204 if (! TARGET_SMALLCODE)
1206 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1207 int final_switch, while_loop;
1208 rtx r4 = gen_rtx_REG (SImode, 4);
1209 rtx r5 = gen_rtx_REG (SImode, 5);
1210 rtx r6 = gen_rtx_REG (SImode, 6);
1212 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1213 force_into (XEXP (operands[0], 0), r4);
1214 force_into (XEXP (operands[1], 0), r5);
1216 /* r6 controls the size of the move. 16 is decremented from it
1217 for each 64 bytes moved. Then the negative bit left over is used
1218 as an index into a list of move instructions. e.g., a 72 byte move
1219 would be set up with size(r6) = 14, for one iteration through the
1220 big while loop, and a switch of -2 for the last part. */
1222 final_switch = 16 - ((bytes / 4) % 16);
1223 while_loop = ((bytes / 4) / 16 - 1) * 16;
1224 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1225 emit_insn (gen_block_lump_real (func_addr_rtx));
1232 /* Prepare operands for a move define_expand; specifically, one of the
1233 operands must be in a register. */
1236 prepare_move_operands (rtx operands[], enum machine_mode mode)
1238 if ((mode == SImode || mode == DImode)
1240 && ! ((mode == Pmode || mode == ptr_mode)
1241 && tls_symbolic_operand (operands[1], Pmode) != 0))
1244 if (SYMBOLIC_CONST_P (operands[1]))
1246 if (GET_CODE (operands[0]) == MEM)
1247 operands[1] = force_reg (Pmode, operands[1]);
1248 else if (TARGET_SHMEDIA
1249 && GET_CODE (operands[1]) == LABEL_REF
1250 && target_reg_operand (operands[0], mode))
1254 temp = (!can_create_pseudo_p ()
1256 : gen_reg_rtx (Pmode));
1257 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1260 else if (GET_CODE (operands[1]) == CONST
1261 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1262 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1264 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1265 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1267 operands[1] = expand_binop (mode, add_optab, temp,
1268 XEXP (XEXP (operands[1], 0), 1),
1269 (!can_create_pseudo_p ()
1271 : gen_reg_rtx (Pmode)),
1272 0, OPTAB_LIB_WIDEN);
1276 if (! reload_in_progress && ! reload_completed)
1278 /* Copy the source to a register if both operands aren't registers. */
1279 if (! register_operand (operands[0], mode)
1280 && ! sh_register_operand (operands[1], mode))
1281 operands[1] = copy_to_mode_reg (mode, operands[1]);
1283 if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode))
1285 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1286 except that we can't use that function because it is static. */
1287 rtx new = change_address (operands[0], mode, 0);
1288 MEM_COPY_ATTRIBUTES (new, operands[0]);
1292 /* This case can happen while generating code to move the result
1293 of a library call to the target. Reject `st r0,@(rX,rY)' because
1294 reload will fail to find a spill register for rX, since r0 is already
1295 being used for the source. */
1297 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1298 && GET_CODE (operands[0]) == MEM
1299 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1300 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
1301 operands[1] = copy_to_mode_reg (mode, operands[1]);
1304 if (mode == Pmode || mode == ptr_mode)
1307 enum tls_model tls_kind;
1311 if (GET_CODE (op1) == CONST
1312 && GET_CODE (XEXP (op1, 0)) == PLUS
1313 && tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode))
1315 opc = XEXP (XEXP (op1, 0), 1);
1316 op1 = XEXP (XEXP (op1, 0), 0);
1321 if ((tls_kind = tls_symbolic_operand (op1, Pmode)))
1323 rtx tga_op1, tga_ret, tmp, tmp2;
1327 case TLS_MODEL_GLOBAL_DYNAMIC:
1328 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1329 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1333 case TLS_MODEL_LOCAL_DYNAMIC:
1334 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1335 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1337 tmp = gen_reg_rtx (Pmode);
1338 emit_move_insn (tmp, tga_ret);
1340 if (register_operand (op0, Pmode))
1343 tmp2 = gen_reg_rtx (Pmode);
1345 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1349 case TLS_MODEL_INITIAL_EXEC:
1352 /* Don't schedule insns for getting GOT address when
1353 the first scheduling is enabled, to avoid spill
1355 if (flag_schedule_insns)
1356 emit_insn (gen_blockage ());
1357 emit_insn (gen_GOTaddr2picreg ());
1358 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode,
1360 if (flag_schedule_insns)
1361 emit_insn (gen_blockage ());
1363 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1364 tmp = gen_sym2GOTTPOFF (op1);
1365 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1369 case TLS_MODEL_LOCAL_EXEC:
1370 tmp2 = gen_reg_rtx (Pmode);
1371 emit_insn (gen_load_gbr (tmp2));
1372 tmp = gen_reg_rtx (Pmode);
1373 emit_insn (gen_symTPOFF2reg (tmp, op1));
1375 if (register_operand (op0, Pmode))
1378 op1 = gen_reg_rtx (Pmode);
1380 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1387 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1396 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1397 enum rtx_code comparison)
1400 rtx scratch = NULL_RTX;
1402 if (comparison == CODE_FOR_nothing)
1403 comparison = GET_CODE (operands[0]);
1405 scratch = operands[4];
1406 if (GET_CODE (operands[1]) == CONST_INT
1407 && GET_CODE (operands[2]) != CONST_INT)
1409 rtx tmp = operands[1];
1411 operands[1] = operands[2];
1413 comparison = swap_condition (comparison);
1415 if (GET_CODE (operands[2]) == CONST_INT)
1417 HOST_WIDE_INT val = INTVAL (operands[2]);
1418 if ((val == -1 || val == -0x81)
1419 && (comparison == GT || comparison == LE))
1421 comparison = (comparison == GT) ? GE : LT;
1422 operands[2] = gen_int_mode (val + 1, mode);
1424 else if ((val == 1 || val == 0x80)
1425 && (comparison == GE || comparison == LT))
1427 comparison = (comparison == GE) ? GT : LE;
1428 operands[2] = gen_int_mode (val - 1, mode);
1430 else if (val == 1 && (comparison == GEU || comparison == LTU))
1432 comparison = (comparison == GEU) ? NE : EQ;
1433 operands[2] = CONST0_RTX (mode);
1435 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1437 comparison = (comparison == GEU) ? GTU : LEU;
1438 operands[2] = gen_int_mode (val - 1, mode);
1440 else if (val == 0 && (comparison == GTU || comparison == LEU))
1441 comparison = (comparison == GTU) ? NE : EQ;
1442 else if (mode == SImode
1443 && ((val == 0x7fffffff
1444 && (comparison == GTU || comparison == LEU))
1445 || ((unsigned HOST_WIDE_INT) val
1446 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1447 && (comparison == GEU || comparison == LTU))))
1449 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1450 operands[2] = CONST0_RTX (mode);
1454 if (can_create_pseudo_p ())
1455 operands[1] = force_reg (mode, op1);
1456 /* When we are handling DImode comparisons, we want to keep constants so
1457 that we can optimize the component comparisons; however, memory loads
1458 are better issued as a whole so that they can be scheduled well.
1459 SImode equality comparisons allow I08 constants, but only when they
1460 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1461 into a register, that register might as well be r0, and we allow the
1462 constant. If it is already in a register, this is likely to be
1463 allocated to a different hard register, thus we load the constant into
1464 a register unless it is zero. */
1465 if (!REG_P (operands[2])
1466 && (GET_CODE (operands[2]) != CONST_INT
1467 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1468 && ((comparison != EQ && comparison != NE)
1469 || (REG_P (op1) && REGNO (op1) != R0_REG)
1470 || !satisfies_constraint_I08 (operands[2])))))
1472 if (scratch && GET_MODE (scratch) == mode)
1474 emit_move_insn (scratch, operands[2]);
1475 operands[2] = scratch;
1477 else if (can_create_pseudo_p ())
1478 operands[2] = force_reg (mode, operands[2]);
1484 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1486 rtx (*branch_expander) (rtx) = gen_branch_true;
1489 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1492 case NE: case LT: case LE: case LTU: case LEU:
1493 comparison = reverse_condition (comparison);
1494 branch_expander = gen_branch_false;
1497 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1498 gen_rtx_fmt_ee (comparison, SImode,
1499 operands[1], operands[2])));
1500 jump = emit_jump_insn (branch_expander (operands[3]));
1501 if (probability >= 0)
1503 = gen_rtx_EXPR_LIST (REG_BR_PROB, GEN_INT (probability),
1508 /* ??? How should we distribute probabilities when more than one branch
1509 is generated. So far we only have soem ad-hoc observations:
1510 - If the operands are random, they are likely to differ in both parts.
1511 - If comparing items in a hash chain, the operands are random or equal;
1512 operation should be EQ or NE.
1513 - If items are searched in an ordered tree from the root, we can expect
1514 the highpart to be unequal about half of the time; operation should be
1515 an inequality comparison, operands non-constant, and overall probability
1516 about 50%. Likewise for quicksort.
1517 - Range checks will be often made against constants. Even if we assume for
1518 simplicity an even distribution of the non-constant operand over a
1519 sub-range here, the same probability could be generated with differently
1520 wide sub-ranges - as long as the ratio of the part of the subrange that
1521 is before the threshold to the part that comes after the threshold stays
1522 the same. Thus, we can't really tell anything here;
1523 assuming random distribution is at least simple.
1527 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1529 enum rtx_code msw_taken, msw_skip, lsw_taken;
1530 rtx skip_label = NULL_RTX;
1531 rtx op1h, op1l, op2h, op2l;
1534 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1535 rtx scratch = operands[4];
1537 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1538 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1539 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1540 op1l = gen_lowpart (SImode, operands[1]);
1541 op2l = gen_lowpart (SImode, operands[2]);
1542 msw_taken = msw_skip = lsw_taken = CODE_FOR_nothing;
1543 prob = split_branch_probability;
1544 rev_prob = REG_BR_PROB_BASE - prob;
1547 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1548 That costs 1 cycle more when the first branch can be predicted taken,
1549 but saves us mispredicts because only one branch needs prediction.
1550 It also enables generating the cmpeqdi_t-1 pattern. */
1552 if (TARGET_CMPEQDI_T)
1554 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1555 emit_jump_insn (gen_branch_true (operands[3]));
1562 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1564 msw_skip_prob = rev_prob;
1565 if (REG_BR_PROB_BASE <= 65535)
1566 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1569 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1573 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1574 / ((HOST_WIDEST_INT) prob << 32)))
1580 if (TARGET_CMPEQDI_T)
1582 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1583 emit_jump_insn (gen_branch_false (operands[3]));
1587 msw_taken_prob = prob;
1592 msw_taken = comparison;
1593 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1595 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1596 msw_skip = swap_condition (msw_taken);
1600 if (op2l == CONST0_RTX (SImode))
1601 msw_taken = comparison;
1604 msw_taken = comparison == GE ? GT : GTU;
1605 msw_skip = swap_condition (msw_taken);
1610 msw_taken = comparison;
1611 if (op2l == CONST0_RTX (SImode))
1613 msw_skip = swap_condition (msw_taken);
1617 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1618 msw_taken = comparison;
1622 if (comparison == LE)
1624 else if (op2h != CONST0_RTX (SImode))
1628 msw_skip = swap_condition (msw_taken);
1631 default: return false;
1633 num_branches = ((msw_taken != CODE_FOR_nothing)
1634 + (msw_skip != CODE_FOR_nothing)
1635 + (lsw_taken != CODE_FOR_nothing));
1636 if (comparison != EQ && comparison != NE && num_branches > 1)
1638 if (!CONSTANT_P (operands[2])
1639 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1640 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1642 msw_taken_prob = prob / 2U;
1644 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1645 lsw_taken_prob = prob;
1649 msw_taken_prob = prob;
1650 msw_skip_prob = REG_BR_PROB_BASE;
1651 /* ??? If we have a constant op2h, should we use that when
1652 calculating lsw_taken_prob? */
1653 lsw_taken_prob = prob;
1658 operands[4] = NULL_RTX;
1659 if (reload_completed
1660 && ! arith_reg_or_0_operand (op2h, SImode) && true_regnum (op1h)
1661 && (msw_taken != CODE_FOR_nothing || msw_skip != CODE_FOR_nothing))
1663 emit_move_insn (scratch, operands[2]);
1664 operands[2] = scratch;
1666 if (msw_taken != CODE_FOR_nothing)
1667 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1668 if (msw_skip != CODE_FOR_nothing)
1670 rtx taken_label = operands[3];
1672 operands[3] = skip_label = gen_label_rtx ();
1673 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1674 operands[3] = taken_label;
1678 if (lsw_taken != CODE_FOR_nothing)
1680 if (reload_completed
1681 && ! arith_reg_or_0_operand (op2l, SImode) && true_regnum (op1l))
1682 operands[4] = scratch;
1683 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1685 if (msw_skip != CODE_FOR_nothing)
1686 emit_label (skip_label);
1690 /* Prepare the operands for an scc instruction; make sure that the
1691 compare has been done. */
1693 prepare_scc_operands (enum rtx_code code)
1695 rtx t_reg = gen_rtx_REG (SImode, T_REG);
1696 enum rtx_code oldcode = code;
1697 enum machine_mode mode;
1699 /* First need a compare insn. */
1703 /* It isn't possible to handle this case. */
1720 if (code != oldcode)
1722 rtx tmp = sh_compare_op0;
1723 sh_compare_op0 = sh_compare_op1;
1724 sh_compare_op1 = tmp;
1727 mode = GET_MODE (sh_compare_op0);
1728 if (mode == VOIDmode)
1729 mode = GET_MODE (sh_compare_op1);
1731 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1732 if ((code != EQ && code != NE
1733 && (sh_compare_op1 != const0_rtx
1734 || code == GTU || code == GEU || code == LTU || code == LEU))
1735 || (mode == DImode && sh_compare_op1 != const0_rtx)
1736 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1737 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1739 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1740 (mode == SFmode ? emit_sf_insn : emit_df_insn)
1741 (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
1742 gen_rtx_SET (VOIDmode, t_reg,
1743 gen_rtx_fmt_ee (code, SImode,
1744 sh_compare_op0, sh_compare_op1)),
1745 gen_rtx_USE (VOIDmode, get_fpscr_rtx ()))));
1747 emit_insn (gen_rtx_SET (VOIDmode, t_reg,
1748 gen_rtx_fmt_ee (code, SImode,
1749 sh_compare_op0, sh_compare_op1)));
1754 /* Called from the md file, set up the operands of a compare instruction. */
1757 from_compare (rtx *operands, int code)
1759 enum machine_mode mode = GET_MODE (sh_compare_op0);
1761 if (mode == VOIDmode)
1762 mode = GET_MODE (sh_compare_op1);
1765 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1767 /* Force args into regs, since we can't use constants here. */
1768 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1769 if (sh_compare_op1 != const0_rtx
1770 || code == GTU || code == GEU
1771 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1772 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1774 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
1776 from_compare (operands, GT);
1777 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
1780 insn = gen_rtx_SET (VOIDmode,
1781 gen_rtx_REG (SImode, T_REG),
1782 gen_rtx_fmt_ee (code, SImode,
1783 sh_compare_op0, sh_compare_op1));
1784 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1786 insn = gen_rtx_PARALLEL (VOIDmode,
1788 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1789 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1795 /* Functions to output assembly code. */
1797 /* Return a sequence of instructions to perform DI or DF move.
1799 Since the SH cannot move a DI or DF in one instruction, we have
1800 to take care when we see overlapping source and dest registers. */
1803 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1804 enum machine_mode mode)
1806 rtx dst = operands[0];
1807 rtx src = operands[1];
1809 if (GET_CODE (dst) == MEM
1810 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
1811 return "mov.l %T1,%0\n\tmov.l %1,%0";
1813 if (register_operand (dst, mode)
1814 && register_operand (src, mode))
1816 if (REGNO (src) == MACH_REG)
1817 return "sts mach,%S0\n\tsts macl,%R0";
1819 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1820 when mov.d r1,r0 do r1->r0 then r2->r1. */
1822 if (REGNO (src) + 1 == REGNO (dst))
1823 return "mov %T1,%T0\n\tmov %1,%0";
1825 return "mov %1,%0\n\tmov %T1,%T0";
1827 else if (GET_CODE (src) == CONST_INT)
1829 if (INTVAL (src) < 0)
1830 output_asm_insn ("mov #-1,%S0", operands);
1832 output_asm_insn ("mov #0,%S0", operands);
1834 return "mov %1,%R0";
1836 else if (GET_CODE (src) == MEM)
1839 int dreg = REGNO (dst);
1840 rtx inside = XEXP (src, 0);
1842 switch (GET_CODE (inside))
1845 ptrreg = REGNO (inside);
1849 ptrreg = subreg_regno (inside);
1853 ptrreg = REGNO (XEXP (inside, 0));
1854 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1855 an offsettable address. Unfortunately, offsettable addresses use
1856 QImode to check the offset, and a QImode offsettable address
1857 requires r0 for the other operand, which is not currently
1858 supported, so we can't use the 'o' constraint.
1859 Thus we must check for and handle r0+REG addresses here.
1860 We punt for now, since this is likely very rare. */
1861 gcc_assert (GET_CODE (XEXP (inside, 1)) != REG);
1865 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1867 return "mov.l %1,%0\n\tmov.l %1,%T0";
1872 /* Work out the safe way to copy. Copy into the second half first. */
1874 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1877 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1880 /* Print an instruction which would have gone into a delay slot after
1881 another instruction, but couldn't because the other instruction expanded
1882 into a sequence where putting the slot insn at the end wouldn't work. */
1885 print_slot (rtx insn)
1887 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
1889 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1893 output_far_jump (rtx insn, rtx op)
1895 struct { rtx lab, reg, op; } this;
1896 rtx braf_base_lab = NULL_RTX;
1899 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
1902 this.lab = gen_label_rtx ();
1906 && offset - get_attr_length (insn) <= 32766)
1909 jump = "mov.w %O0,%1; braf %1";
1917 jump = "mov.l %O0,%1; braf %1";
1919 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1922 jump = "mov.l %O0,%1; jmp @%1";
1924 /* If we have a scratch register available, use it. */
1925 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
1926 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1928 this.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
1929 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1930 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1931 output_asm_insn (jump, &this.lab);
1932 if (dbr_sequence_length ())
1933 print_slot (final_sequence);
1935 output_asm_insn ("nop", 0);
1939 /* Output the delay slot insn first if any. */
1940 if (dbr_sequence_length ())
1941 print_slot (final_sequence);
1943 this.reg = gen_rtx_REG (SImode, 13);
1944 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1945 Fortunately, MACL is fixed and call-clobbered, and we never
1946 need its value across jumps, so save r13 in it instead of in
1949 output_asm_insn ("lds r13, macl", 0);
1951 output_asm_insn ("mov.l r13,@-r15", 0);
1952 output_asm_insn (jump, &this.lab);
1954 output_asm_insn ("sts macl, r13", 0);
1956 output_asm_insn ("mov.l @r15+,r13", 0);
1958 if (far && flag_pic && TARGET_SH2)
1960 braf_base_lab = gen_label_rtx ();
1961 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1962 CODE_LABEL_NUMBER (braf_base_lab));
1965 output_asm_insn (".align 2", 0);
1966 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
1968 if (far && flag_pic)
1971 this.lab = braf_base_lab;
1972 output_asm_insn (".long %O2-%O0", &this.lab);
1975 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
1979 /* Local label counter, used for constants in the pool and inside
1980 pattern branches. */
1982 static int lf = 100;
1984 /* Output code for ordinary branches. */
1987 output_branch (int logic, rtx insn, rtx *operands)
1989 switch (get_attr_length (insn))
1992 /* This can happen if filling the delay slot has caused a forward
1993 branch to exceed its range (we could reverse it, but only
1994 when we know we won't overextend other branches; this should
1995 best be handled by relaxation).
1996 It can also happen when other condbranches hoist delay slot insn
1997 from their destination, thus leading to code size increase.
1998 But the branch will still be in the range -4092..+4098 bytes. */
2003 /* The call to print_slot will clobber the operands. */
2004 rtx op0 = operands[0];
2006 /* If the instruction in the delay slot is annulled (true), then
2007 there is no delay slot where we can put it now. The only safe
2008 place for it is after the label. final will do that by default. */
2011 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2012 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2014 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2015 ASSEMBLER_DIALECT ? "/" : ".", label);
2016 print_slot (final_sequence);
2019 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2021 output_asm_insn ("bra\t%l0", &op0);
2022 fprintf (asm_out_file, "\tnop\n");
2023 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2027 /* When relaxing, handle this like a short branch. The linker
2028 will fix it up if it still doesn't fit after relaxation. */
2030 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2032 /* These are for SH2e, in which we have to account for the
2033 extra nop because of the hardware bug in annulled branches. */
2039 gcc_assert (!final_sequence
2040 || !(INSN_ANNULLED_BRANCH_P
2041 (XVECEXP (final_sequence, 0, 0))));
2042 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2044 ASSEMBLER_DIALECT ? "/" : ".", label);
2045 fprintf (asm_out_file, "\tnop\n");
2046 output_asm_insn ("bra\t%l0", operands);
2047 fprintf (asm_out_file, "\tnop\n");
2048 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2052 /* When relaxing, fall through. */
2057 sprintf (buffer, "b%s%ss\t%%l0",
2059 ASSEMBLER_DIALECT ? "/" : ".");
2060 output_asm_insn (buffer, &operands[0]);
2065 /* There should be no longer branches now - that would
2066 indicate that something has destroyed the branches set
2067 up in machine_dependent_reorg. */
2072 /* Output a code sequence for INSN using TEMPLATE with OPERANDS; but before,
2073 fill in operands 9 as a label to the successor insn.
2074 We try to use jump threading where possible.
2075 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2076 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2077 follow jmp and bt, if the address is in range. */
2079 output_branchy_insn (enum rtx_code code, const char *template,
2080 rtx insn, rtx *operands)
2082 rtx next_insn = NEXT_INSN (insn);
2084 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
2086 rtx src = SET_SRC (PATTERN (next_insn));
2087 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2089 /* Following branch not taken */
2090 operands[9] = gen_label_rtx ();
2091 emit_label_after (operands[9], next_insn);
2092 INSN_ADDRESSES_NEW (operands[9],
2093 INSN_ADDRESSES (INSN_UID (next_insn))
2094 + get_attr_length (next_insn));
2099 int offset = (branch_dest (next_insn)
2100 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2101 if (offset >= -252 && offset <= 258)
2103 if (GET_CODE (src) == IF_THEN_ELSE)
2105 src = XEXP (src, 1);
2111 operands[9] = gen_label_rtx ();
2112 emit_label_after (operands[9], insn);
2113 INSN_ADDRESSES_NEW (operands[9],
2114 INSN_ADDRESSES (INSN_UID (insn))
2115 + get_attr_length (insn));
2120 output_ieee_ccmpeq (rtx insn, rtx *operands)
2122 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2126 /* Output the start of the assembler file. */
2129 sh_file_start (void)
2131 default_file_start ();
2134 /* Declare the .directive section before it is used. */
2135 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2136 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2140 /* We need to show the text section with the proper
2141 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2142 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2143 will complain. We can teach GAS specifically about the
2144 default attributes for our choice of text section, but
2145 then we would have to change GAS again if/when we change
2146 the text section name. */
2147 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2149 /* Switch to the data section so that the coffsem symbol
2150 isn't in the text section. */
2151 switch_to_section (data_section);
2153 if (TARGET_LITTLE_ENDIAN)
2154 fputs ("\t.little\n", asm_out_file);
2158 if (TARGET_SHCOMPACT)
2159 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2160 else if (TARGET_SHMEDIA)
2161 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2162 TARGET_SHMEDIA64 ? 64 : 32);
2166 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2169 unspec_caller_rtx_p (rtx pat)
2171 switch (GET_CODE (pat))
2174 return unspec_caller_rtx_p (XEXP (pat, 0));
2177 if (unspec_caller_rtx_p (XEXP (pat, 0)))
2179 return unspec_caller_rtx_p (XEXP (pat, 1));
2181 if (XINT (pat, 1) == UNSPEC_CALLER)
2190 /* Indicate that INSN cannot be duplicated. This is true for insn
2191 that generates a unique label. */
2194 sh_cannot_copy_insn_p (rtx insn)
2198 if (!reload_completed || !flag_pic)
2201 if (GET_CODE (insn) != INSN)
2203 if (asm_noperands (insn) >= 0)
2206 pat = PATTERN (insn);
2207 if (GET_CODE (pat) != SET)
2209 pat = SET_SRC (pat);
2211 if (unspec_caller_rtx_p (pat))
2217 /* Actual number of instructions used to make a shift by N. */
2218 static const char ashiftrt_insns[] =
2219 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2221 /* Left shift and logical right shift are the same. */
2222 static const char shift_insns[] =
2223 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2225 /* Individual shift amounts needed to get the above length sequences.
2226 One bit right shifts clobber the T bit, so when possible, put one bit
2227 shifts in the middle of the sequence, so the ends are eligible for
2228 branch delay slots. */
2229 static const short shift_amounts[32][5] = {
2230 {0}, {1}, {2}, {2, 1},
2231 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2232 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2233 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2234 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2235 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2236 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2237 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2239 /* Likewise, but for shift amounts < 16, up to three highmost bits
2240 might be clobbered. This is typically used when combined with some
2241 kind of sign or zero extension. */
2243 static const char ext_shift_insns[] =
2244 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2246 static const short ext_shift_amounts[32][4] = {
2247 {0}, {1}, {2}, {2, 1},
2248 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2249 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2250 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2251 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2252 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2253 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2254 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2256 /* Assuming we have a value that has been sign-extended by at least one bit,
2257 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2258 to shift it by N without data loss, and quicker than by other means? */
2259 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2261 /* This is used in length attributes in sh.md to help compute the length
2262 of arbitrary constant shift instructions. */
2265 shift_insns_rtx (rtx insn)
2267 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2268 int shift_count = INTVAL (XEXP (set_src, 1));
2269 enum rtx_code shift_code = GET_CODE (set_src);
2274 return ashiftrt_insns[shift_count];
2277 return shift_insns[shift_count];
2283 /* Return the cost of a shift. */
2293 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2295 if (GET_MODE (x) == DImode
2296 && GET_CODE (XEXP (x, 1)) == CONST_INT
2297 && INTVAL (XEXP (x, 1)) == 1)
2300 /* Everything else is invalid, because there is no pattern for it. */
2303 /* If shift by a non constant, then this will be expensive. */
2304 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2305 return SH_DYNAMIC_SHIFT_COST;
2307 value = INTVAL (XEXP (x, 1));
2309 /* Otherwise, return the true cost in instructions. */
2310 if (GET_CODE (x) == ASHIFTRT)
2312 int cost = ashiftrt_insns[value];
2313 /* If SH3, then we put the constant in a reg and use shad. */
2314 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2315 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2319 return shift_insns[value];
2322 /* Return the cost of an AND operation. */
2329 /* Anding with a register is a single cycle and instruction. */
2330 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2333 i = INTVAL (XEXP (x, 1));
2337 if (satisfies_constraint_I10 (XEXP (x, 1))
2338 || satisfies_constraint_J16 (XEXP (x, 1)))
2341 return 1 + rtx_cost (XEXP (x, 1), AND);
2344 /* These constants are single cycle extu.[bw] instructions. */
2345 if (i == 0xff || i == 0xffff)
2347 /* Constants that can be used in an and immediate instruction in a single
2348 cycle, but this requires r0, so make it a little more expensive. */
2349 if (CONST_OK_FOR_K08 (i))
2351 /* Constants that can be loaded with a mov immediate and an and.
2352 This case is probably unnecessary. */
2353 if (CONST_OK_FOR_I08 (i))
2355 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2356 This case is probably unnecessary. */
2360 /* Return the cost of an addition or a subtraction. */
2365 /* Adding a register is a single cycle insn. */
2366 if (GET_CODE (XEXP (x, 1)) == REG
2367 || GET_CODE (XEXP (x, 1)) == SUBREG)
2370 /* Likewise for small constants. */
2371 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2372 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2376 switch (GET_CODE (XEXP (x, 1)))
2381 return TARGET_SHMEDIA64 ? 5 : 3;
2384 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2386 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2388 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2396 /* Any other constant requires a 2 cycle pc-relative load plus an
2401 /* Return the cost of a multiply. */
2403 multcosts (rtx x ATTRIBUTE_UNUSED)
2405 if (sh_multcost >= 0)
2408 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2409 accept constants. Ideally, we would use a cost of one or two and
2410 add the cost of the operand, but disregard the latter when inside loops
2411 and loop invariant code motion is still to follow.
2412 Using a multiply first and splitting it later if it's a loss
2413 doesn't work because of different sign / zero extension semantics
2414 of multiplies vs. shifts. */
2415 return TARGET_SMALLCODE ? 2 : 3;
2419 /* We have a mul insn, so we can never take more than the mul and the
2420 read of the mac reg, but count more because of the latency and extra
2422 if (TARGET_SMALLCODE)
2427 /* If we're aiming at small code, then just count the number of
2428 insns in a multiply call sequence. */
2429 if (TARGET_SMALLCODE)
2432 /* Otherwise count all the insns in the routine we'd be calling too. */
2436 /* Compute a (partial) cost for rtx X. Return true if the complete
2437 cost has been computed, and false if subexpressions should be
2438 scanned. In either case, *TOTAL contains the cost result. */
2441 sh_rtx_costs (rtx x, int code, int outer_code, int *total)
2448 if (INTVAL (x) == 0)
2450 else if (outer_code == AND && and_operand ((x), DImode))
2452 else if ((outer_code == IOR || outer_code == XOR
2453 || outer_code == PLUS)
2454 && CONST_OK_FOR_I10 (INTVAL (x)))
2456 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2457 *total = COSTS_N_INSNS (outer_code != SET);
2458 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2459 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2460 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2461 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2463 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2466 if (CONST_OK_FOR_I08 (INTVAL (x)))
2468 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2469 && CONST_OK_FOR_K08 (INTVAL (x)))
2471 /* prepare_cmp_insn will force costly constants int registers before
2472 the cbranch[sd]i4 patterns can see them, so preserve potentially
2473 interesting ones not covered by I08 above. */
2474 else if (outer_code == COMPARE
2475 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2476 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2477 || INTVAL (x) == 0x7fffffff
2478 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2487 if (TARGET_SHMEDIA64)
2488 *total = COSTS_N_INSNS (4);
2489 else if (TARGET_SHMEDIA32)
2490 *total = COSTS_N_INSNS (2);
2497 *total = COSTS_N_INSNS (4);
2498 /* prepare_cmp_insn will force costly constants int registers before
2499 the cbranchdi4 pattern can see them, so preserve potentially
2500 interesting ones. */
2501 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2507 if (x == CONST0_RTX (GET_MODE (x)))
2509 else if (sh_1el_vec (x, VOIDmode))
2510 *total = outer_code != SET;
2511 if (sh_rep_vec (x, VOIDmode))
2512 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2513 + (outer_code != SET));
2514 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2519 *total = COSTS_N_INSNS (addsubcosts (x));
2523 *total = COSTS_N_INSNS (andcosts (x));
2527 *total = COSTS_N_INSNS (multcosts (x));
2533 *total = COSTS_N_INSNS (shiftcosts (x));
2540 *total = COSTS_N_INSNS (20);
2544 if (sh_1el_vec (x, VOIDmode))
2545 *total = outer_code != SET;
2546 if (sh_rep_vec (x, VOIDmode))
2547 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2548 + (outer_code != SET));
2549 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2562 /* Compute the cost of an address. For the SH, all valid addresses are
2563 the same cost. Use a slightly higher cost for reg + reg addressing,
2564 since it increases pressure on r0. */
2567 sh_address_cost (rtx X)
2569 return (GET_CODE (X) == PLUS
2570 && ! CONSTANT_P (XEXP (X, 1))
2571 && ! TARGET_SHMEDIA ? 1 : 0);
2574 /* Code to expand a shift. */
2577 gen_ashift (int type, int n, rtx reg)
2579 /* Negative values here come from the shift_amounts array. */
2592 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
2596 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
2598 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
2601 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
2606 /* Same for HImode */
2609 gen_ashift_hi (int type, int n, rtx reg)
2611 /* Negative values here come from the shift_amounts array. */
2625 /* We don't have HImode right shift operations because using the
2626 ordinary 32 bit shift instructions for that doesn't generate proper
2627 zero/sign extension.
2628 gen_ashift_hi is only called in contexts where we know that the
2629 sign extension works out correctly. */
2632 if (GET_CODE (reg) == SUBREG)
2634 offset = SUBREG_BYTE (reg);
2635 reg = SUBREG_REG (reg);
2637 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
2641 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
2646 /* Output RTL to split a constant shift into its component SH constant
2647 shift instructions. */
2650 gen_shifty_op (int code, rtx *operands)
2652 int value = INTVAL (operands[2]);
2655 /* Truncate the shift count in case it is out of bounds. */
2656 value = value & 0x1f;
2660 if (code == LSHIFTRT)
2662 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2663 emit_insn (gen_movt (operands[0]));
2666 else if (code == ASHIFT)
2668 /* There is a two instruction sequence for 31 bit left shifts,
2669 but it requires r0. */
2670 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
2672 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
2673 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2678 else if (value == 0)
2680 /* This can happen even when optimizing, if there were subregs before
2681 reload. Don't output a nop here, as this is never optimized away;
2682 use a no-op move instead. */
2683 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
2687 max = shift_insns[value];
2688 for (i = 0; i < max; i++)
2689 gen_ashift (code, shift_amounts[value][i], operands[0]);
2692 /* Same as above, but optimized for values where the topmost bits don't
2696 gen_shifty_hi_op (int code, rtx *operands)
2698 int value = INTVAL (operands[2]);
2700 void (*gen_fun) (int, int, rtx);
2702 /* This operation is used by and_shl for SImode values with a few
2703 high bits known to be cleared. */
2707 emit_insn (gen_nop ());
2711 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
2714 max = ext_shift_insns[value];
2715 for (i = 0; i < max; i++)
2716 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2719 /* When shifting right, emit the shifts in reverse order, so that
2720 solitary negative values come first. */
2721 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
2722 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2725 /* Output RTL for an arithmetic right shift. */
2727 /* ??? Rewrite to use super-optimizer sequences. */
2730 expand_ashiftrt (rtx *operands)
2738 if (GET_CODE (operands[2]) != CONST_INT)
2740 rtx count = copy_to_mode_reg (SImode, operands[2]);
2741 emit_insn (gen_negsi2 (count, count));
2742 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2745 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
2746 > 1 + SH_DYNAMIC_SHIFT_COST)
2749 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
2750 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2754 if (GET_CODE (operands[2]) != CONST_INT)
2757 value = INTVAL (operands[2]) & 31;
2761 /* If we are called from abs expansion, arrange things so that we
2762 we can use a single MT instruction that doesn't clobber the source,
2763 if LICM can hoist out the load of the constant zero. */
2764 if (currently_expanding_to_rtl)
2766 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
2768 emit_insn (gen_mov_neg_si_t (operands[0]));
2771 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
2774 else if (value >= 16 && value <= 19)
2776 wrk = gen_reg_rtx (SImode);
2777 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
2780 gen_ashift (ASHIFTRT, 1, wrk);
2781 emit_move_insn (operands[0], wrk);
2784 /* Expand a short sequence inline, longer call a magic routine. */
2785 else if (value <= 5)
2787 wrk = gen_reg_rtx (SImode);
2788 emit_move_insn (wrk, operands[1]);
2790 gen_ashift (ASHIFTRT, 1, wrk);
2791 emit_move_insn (operands[0], wrk);
2795 wrk = gen_reg_rtx (Pmode);
2797 /* Load the value into an arg reg and call a helper. */
2798 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2799 sprintf (func, "__ashiftrt_r4_%d", value);
2800 function_symbol (wrk, func, SFUNC_STATIC);
2801 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
2802 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
2807 sh_dynamicalize_shift_p (rtx count)
2809 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
2812 /* Try to find a good way to implement the combiner pattern
2813 [(set (match_operand:SI 0 "register_operand" "r")
2814 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2815 (match_operand:SI 2 "const_int_operand" "n"))
2816 (match_operand:SI 3 "const_int_operand" "n"))) .
2817 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
2818 return 0 for simple right / left or left/right shift combination.
2819 return 1 for a combination of shifts with zero_extend.
2820 return 2 for a combination of shifts with an AND that needs r0.
2821 return 3 for a combination of shifts with an AND that needs an extra
2822 scratch register, when the three highmost bits of the AND mask are clear.
2823 return 4 for a combination of shifts with an AND that needs an extra
2824 scratch register, when any of the three highmost bits of the AND mask
2826 If ATTRP is set, store an initial right shift width in ATTRP[0],
2827 and the instruction length in ATTRP[1] . These values are not valid
2829 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
2830 shift_amounts for the last shift value that is to be used before the
2833 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
2835 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
2836 int left = INTVAL (left_rtx), right;
2838 int cost, best_cost = 10000;
2839 int best_right = 0, best_len = 0;
2843 if (left < 0 || left > 31)
2845 if (GET_CODE (mask_rtx) == CONST_INT)
2846 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
2848 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
2849 /* Can this be expressed as a right shift / left shift pair? */
2850 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
2851 right = exact_log2 (lsb);
2852 mask2 = ~(mask + lsb - 1);
2853 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
2854 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
2856 best_cost = shift_insns[right] + shift_insns[right + left];
2857 /* mask has no trailing zeroes <==> ! right */
2858 else if (! right && mask2 == ~(lsb2 - 1))
2860 int late_right = exact_log2 (lsb2);
2861 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
2863 /* Try to use zero extend. */
2864 if (mask2 == ~(lsb2 - 1))
2868 for (width = 8; width <= 16; width += 8)
2870 /* Can we zero-extend right away? */
2871 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
2874 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
2875 if (cost < best_cost)
2886 /* ??? Could try to put zero extend into initial right shift,
2887 or even shift a bit left before the right shift. */
2888 /* Determine value of first part of left shift, to get to the
2889 zero extend cut-off point. */
2890 first = width - exact_log2 (lsb2) + right;
2891 if (first >= 0 && right + left - first >= 0)
2893 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
2894 + ext_shift_insns[right + left - first];
2895 if (cost < best_cost)
2907 /* Try to use r0 AND pattern */
2908 for (i = 0; i <= 2; i++)
2912 if (! CONST_OK_FOR_K08 (mask >> i))
2914 cost = (i != 0) + 2 + ext_shift_insns[left + i];
2915 if (cost < best_cost)
2920 best_len = cost - 1;
2923 /* Try to use a scratch register to hold the AND operand. */
2924 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
2925 for (i = 0; i <= 2; i++)
2929 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
2930 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
2931 if (cost < best_cost)
2936 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
2942 attrp[0] = best_right;
2943 attrp[1] = best_len;
2948 /* This is used in length attributes of the unnamed instructions
2949 corresponding to shl_and_kind return values of 1 and 2. */
2951 shl_and_length (rtx insn)
2953 rtx set_src, left_rtx, mask_rtx;
2956 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2957 left_rtx = XEXP (XEXP (set_src, 0), 1);
2958 mask_rtx = XEXP (set_src, 1);
2959 shl_and_kind (left_rtx, mask_rtx, attributes);
2960 return attributes[1];
2963 /* This is used in length attribute of the and_shl_scratch instruction. */
2966 shl_and_scr_length (rtx insn)
2968 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2969 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
2970 rtx op = XEXP (set_src, 0);
2971 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
2972 op = XEXP (XEXP (op, 0), 0);
2973 return len + shift_insns[INTVAL (XEXP (op, 1))];
2976 /* Generate rtl for instructions for which shl_and_kind advised a particular
2977 method of generating them, i.e. returned zero. */
2980 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
2983 unsigned HOST_WIDE_INT mask;
2984 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
2985 int right, total_shift;
2986 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
2988 right = attributes[0];
2989 total_shift = INTVAL (left_rtx) + right;
2990 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
2997 int first = attributes[2];
3002 emit_insn ((mask << right) <= 0xff
3003 ? gen_zero_extendqisi2 (dest,
3004 gen_lowpart (QImode, source))
3005 : gen_zero_extendhisi2 (dest,
3006 gen_lowpart (HImode, source)));
3010 emit_insn (gen_movsi (dest, source));
3014 operands[2] = GEN_INT (right);
3015 gen_shifty_hi_op (LSHIFTRT, operands);
3019 operands[2] = GEN_INT (first);
3020 gen_shifty_hi_op (ASHIFT, operands);
3021 total_shift -= first;
3025 emit_insn (mask <= 0xff
3026 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3027 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3028 if (total_shift > 0)
3030 operands[2] = GEN_INT (total_shift);
3031 gen_shifty_hi_op (ASHIFT, operands);
3036 shift_gen_fun = gen_shifty_op;
3038 /* If the topmost bit that matters is set, set the topmost bits
3039 that don't matter. This way, we might be able to get a shorter
3041 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3042 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3044 /* Don't expand fine-grained when combining, because that will
3045 make the pattern fail. */
3046 if (currently_expanding_to_rtl
3047 || reload_in_progress || reload_completed)
3051 /* Cases 3 and 4 should be handled by this split
3052 only while combining */
3053 gcc_assert (kind <= 2);
3056 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3059 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3064 operands[2] = GEN_INT (total_shift);
3065 shift_gen_fun (ASHIFT, operands);
3072 if (kind != 4 && total_shift < 16)
3074 neg = -ext_shift_amounts[total_shift][1];
3076 neg -= ext_shift_amounts[total_shift][2];
3080 emit_insn (gen_and_shl_scratch (dest, source,
3083 GEN_INT (total_shift + neg),
3085 emit_insn (gen_movsi (dest, dest));
3092 /* Try to find a good way to implement the combiner pattern
3093 [(set (match_operand:SI 0 "register_operand" "=r")
3094 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3095 (match_operand:SI 2 "const_int_operand" "n")
3096 (match_operand:SI 3 "const_int_operand" "n")
3098 (clobber (reg:SI T_REG))]
3099 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3100 return 0 for simple left / right shift combination.
3101 return 1 for left shift / 8 bit sign extend / left shift.
3102 return 2 for left shift / 16 bit sign extend / left shift.
3103 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3104 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3105 return 5 for left shift / 16 bit sign extend / right shift
3106 return 6 for < 8 bit sign extend / left shift.
3107 return 7 for < 8 bit sign extend / left shift / single right shift.
3108 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3111 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3113 int left, size, insize, ext;
3114 int cost = 0, best_cost;
3117 left = INTVAL (left_rtx);
3118 size = INTVAL (size_rtx);
3119 insize = size - left;
3120 gcc_assert (insize > 0);
3121 /* Default to left / right shift. */
3123 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3126 /* 16 bit shift / sign extend / 16 bit shift */
3127 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3128 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3129 below, by alternative 3 or something even better. */
3130 if (cost < best_cost)
3136 /* Try a plain sign extend between two shifts. */
3137 for (ext = 16; ext >= insize; ext -= 8)
3141 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3142 if (cost < best_cost)
3144 kind = ext / (unsigned) 8;
3148 /* Check if we can do a sloppy shift with a final signed shift
3149 restoring the sign. */
3150 if (EXT_SHIFT_SIGNED (size - ext))
3151 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3152 /* If not, maybe it's still cheaper to do the second shift sloppy,
3153 and do a final sign extend? */
3154 else if (size <= 16)
3155 cost = ext_shift_insns[ext - insize] + 1
3156 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3159 if (cost < best_cost)
3161 kind = ext / (unsigned) 8 + 2;
3165 /* Check if we can sign extend in r0 */
3168 cost = 3 + shift_insns[left];
3169 if (cost < best_cost)
3174 /* Try the same with a final signed shift. */
3177 cost = 3 + ext_shift_insns[left + 1] + 1;
3178 if (cost < best_cost)
3187 /* Try to use a dynamic shift. */
3188 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3189 if (cost < best_cost)
3200 /* Function to be used in the length attribute of the instructions
3201 implementing this pattern. */
3204 shl_sext_length (rtx insn)
3206 rtx set_src, left_rtx, size_rtx;
3209 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3210 left_rtx = XEXP (XEXP (set_src, 0), 1);
3211 size_rtx = XEXP (set_src, 1);
3212 shl_sext_kind (left_rtx, size_rtx, &cost);
3216 /* Generate rtl for this pattern */
3219 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3222 int left, size, insize, cost;
3225 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3226 left = INTVAL (left_rtx);
3227 size = INTVAL (size_rtx);
3228 insize = size - left;
3236 int ext = kind & 1 ? 8 : 16;
3237 int shift2 = size - ext;
3239 /* Don't expand fine-grained when combining, because that will
3240 make the pattern fail. */
3241 if (! currently_expanding_to_rtl
3242 && ! reload_in_progress && ! reload_completed)
3244 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3245 emit_insn (gen_movsi (dest, source));
3249 emit_insn (gen_movsi (dest, source));
3253 operands[2] = GEN_INT (ext - insize);
3254 gen_shifty_hi_op (ASHIFT, operands);
3257 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3258 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3263 operands[2] = GEN_INT (shift2);
3264 gen_shifty_op (ASHIFT, operands);
3271 if (EXT_SHIFT_SIGNED (shift2))
3273 operands[2] = GEN_INT (shift2 + 1);
3274 gen_shifty_op (ASHIFT, operands);
3275 operands[2] = const1_rtx;
3276 gen_shifty_op (ASHIFTRT, operands);
3279 operands[2] = GEN_INT (shift2);
3280 gen_shifty_hi_op (ASHIFT, operands);
3284 operands[2] = GEN_INT (-shift2);
3285 gen_shifty_hi_op (LSHIFTRT, operands);
3287 emit_insn (size <= 8
3288 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3289 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3296 if (! currently_expanding_to_rtl
3297 && ! reload_in_progress && ! reload_completed)
3298 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3302 operands[2] = GEN_INT (16 - insize);
3303 gen_shifty_hi_op (ASHIFT, operands);
3304 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3306 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3308 gen_ashift (ASHIFTRT, 1, dest);
3313 /* Don't expand fine-grained when combining, because that will
3314 make the pattern fail. */
3315 if (! currently_expanding_to_rtl
3316 && ! reload_in_progress && ! reload_completed)
3318 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3319 emit_insn (gen_movsi (dest, source));
3322 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3323 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3324 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3326 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3327 gen_shifty_op (ASHIFT, operands);
3329 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3337 /* Prefix a symbol_ref name with "datalabel". */
3340 gen_datalabel_ref (rtx sym)
3344 if (GET_CODE (sym) == LABEL_REF)
3345 return gen_rtx_CONST (GET_MODE (sym),
3346 gen_rtx_UNSPEC (GET_MODE (sym),
3350 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3352 str = XSTR (sym, 0);
3353 /* Share all SYMBOL_REF strings with the same value - that is important
3355 str = IDENTIFIER_POINTER (get_identifier (str));
3356 XSTR (sym, 0) = str;
3362 static alloc_pool label_ref_list_pool;
3364 typedef struct label_ref_list_d
3367 struct label_ref_list_d *next;
3368 } *label_ref_list_t;
3370 /* The SH cannot load a large constant into a register, constants have to
3371 come from a pc relative load. The reference of a pc relative load
3372 instruction must be less than 1k in front of the instruction. This
3373 means that we often have to dump a constant inside a function, and
3374 generate code to branch around it.
3376 It is important to minimize this, since the branches will slow things
3377 down and make things bigger.
3379 Worst case code looks like:
3397 We fix this by performing a scan before scheduling, which notices which
3398 instructions need to have their operands fetched from the constant table
3399 and builds the table.
3403 scan, find an instruction which needs a pcrel move. Look forward, find the
3404 last barrier which is within MAX_COUNT bytes of the requirement.
3405 If there isn't one, make one. Process all the instructions between
3406 the find and the barrier.
3408 In the above example, we can tell that L3 is within 1k of L1, so
3409 the first move can be shrunk from the 3 insn+constant sequence into
3410 just 1 insn, and the constant moved to L3 to make:
3421 Then the second move becomes the target for the shortening process. */
3425 rtx value; /* Value in table. */
3426 rtx label; /* Label of value. */
3427 label_ref_list_t wend; /* End of window. */
3428 enum machine_mode mode; /* Mode of value. */
3430 /* True if this constant is accessed as part of a post-increment
3431 sequence. Note that HImode constants are never accessed in this way. */
3432 bool part_of_sequence_p;
3435 /* The maximum number of constants that can fit into one pool, since
3436 constants in the range 0..510 are at least 2 bytes long, and in the
3437 range from there to 1018 at least 4 bytes. */
3439 #define MAX_POOL_SIZE 372
3440 static pool_node pool_vector[MAX_POOL_SIZE];
3441 static int pool_size;
3442 static rtx pool_window_label;
3443 static int pool_window_last;
3445 static int max_labelno_before_reorg;
3447 /* ??? If we need a constant in HImode which is the truncated value of a
3448 constant we need in SImode, we could combine the two entries thus saving
3449 two bytes. Is this common enough to be worth the effort of implementing
3452 /* ??? This stuff should be done at the same time that we shorten branches.
3453 As it is now, we must assume that all branches are the maximum size, and
3454 this causes us to almost always output constant pools sooner than
3457 /* Add a constant to the pool and return its label. */
3460 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3464 label_ref_list_t ref, newref;
3466 /* First see if we've already got it. */
3467 for (i = 0; i < pool_size; i++)
3469 if (x->code == pool_vector[i].value->code
3470 && mode == pool_vector[i].mode)
3472 if (x->code == CODE_LABEL)
3474 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3477 if (rtx_equal_p (x, pool_vector[i].value))
3482 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3484 new = gen_label_rtx ();
3485 LABEL_REFS (new) = pool_vector[i].label;
3486 pool_vector[i].label = lab = new;
3488 if (lab && pool_window_label)
3490 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3491 newref->label = pool_window_label;
3492 ref = pool_vector[pool_window_last].wend;
3494 pool_vector[pool_window_last].wend = newref;
3497 pool_window_label = new;
3498 pool_window_last = i;
3504 /* Need a new one. */
3505 pool_vector[pool_size].value = x;
3506 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3509 pool_vector[pool_size - 1].part_of_sequence_p = true;
3512 lab = gen_label_rtx ();
3513 pool_vector[pool_size].mode = mode;
3514 pool_vector[pool_size].label = lab;
3515 pool_vector[pool_size].wend = NULL;
3516 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3517 if (lab && pool_window_label)
3519 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3520 newref->label = pool_window_label;
3521 ref = pool_vector[pool_window_last].wend;
3523 pool_vector[pool_window_last].wend = newref;
3526 pool_window_label = lab;
3527 pool_window_last = pool_size;
3532 /* Output the literal table. START, if nonzero, is the first instruction
3533 this table is needed for, and also indicates that there is at least one
3534 casesi_worker_2 instruction; We have to emit the operand3 labels from
3535 these insns at a 4-byte aligned position. BARRIER is the barrier
3536 after which we are to place the table. */
3539 dump_table (rtx start, rtx barrier)
3545 label_ref_list_t ref;
3548 /* Do two passes, first time dump out the HI sized constants. */
3550 for (i = 0; i < pool_size; i++)
3552 pool_node *p = &pool_vector[i];
3554 if (p->mode == HImode)
3558 scan = emit_insn_after (gen_align_2 (), scan);
3561 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3562 scan = emit_label_after (lab, scan);
3563 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
3565 for (ref = p->wend; ref; ref = ref->next)
3568 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3571 else if (p->mode == DFmode)
3579 scan = emit_insn_after (gen_align_4 (), scan);
3581 for (; start != barrier; start = NEXT_INSN (start))
3582 if (GET_CODE (start) == INSN
3583 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
3585 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
3586 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
3588 scan = emit_label_after (lab, scan);
3591 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
3593 rtx align_insn = NULL_RTX;
3595 scan = emit_label_after (gen_label_rtx (), scan);
3596 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3599 for (i = 0; i < pool_size; i++)
3601 pool_node *p = &pool_vector[i];
3609 if (align_insn && !p->part_of_sequence_p)
3611 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3612 emit_label_before (lab, align_insn);
3613 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
3615 for (ref = p->wend; ref; ref = ref->next)
3618 emit_insn_before (gen_consttable_window_end (lab),
3621 delete_insn (align_insn);
3622 align_insn = NULL_RTX;
3627 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3628 scan = emit_label_after (lab, scan);
3629 scan = emit_insn_after (gen_consttable_4 (p->value,
3631 need_align = ! need_align;
3637 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3642 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3643 scan = emit_label_after (lab, scan);
3644 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3651 if (p->mode != HImode)
3653 for (ref = p->wend; ref; ref = ref->next)
3656 scan = emit_insn_after (gen_consttable_window_end (lab),
3665 for (i = 0; i < pool_size; i++)
3667 pool_node *p = &pool_vector[i];
3678 scan = emit_label_after (gen_label_rtx (), scan);
3679 scan = emit_insn_after (gen_align_4 (), scan);
3681 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3682 scan = emit_label_after (lab, scan);
3683 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
3691 scan = emit_label_after (gen_label_rtx (), scan);
3692 scan = emit_insn_after (gen_align_4 (), scan);
3694 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3695 scan = emit_label_after (lab, scan);
3696 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3703 if (p->mode != HImode)
3705 for (ref = p->wend; ref; ref = ref->next)
3708 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3713 scan = emit_insn_after (gen_consttable_end (), scan);
3714 scan = emit_barrier_after (scan);
3716 pool_window_label = NULL_RTX;
3717 pool_window_last = 0;
3720 /* Return nonzero if constant would be an ok source for a
3721 mov.w instead of a mov.l. */
3726 return (GET_CODE (src) == CONST_INT
3727 && INTVAL (src) >= -32768
3728 && INTVAL (src) <= 32767);
3731 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
3733 /* Nonzero if the insn is a move instruction which needs to be fixed. */
3735 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
3736 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
3737 need to fix it if the input value is CONST_OK_FOR_I08. */
3740 broken_move (rtx insn)
3742 if (GET_CODE (insn) == INSN)
3744 rtx pat = PATTERN (insn);
3745 if (GET_CODE (pat) == PARALLEL)
3746 pat = XVECEXP (pat, 0, 0);
3747 if (GET_CODE (pat) == SET
3748 /* We can load any 8-bit value if we don't care what the high
3749 order bits end up as. */
3750 && GET_MODE (SET_DEST (pat)) != QImode
3751 && (CONSTANT_P (SET_SRC (pat))
3752 /* Match mova_const. */
3753 || (GET_CODE (SET_SRC (pat)) == UNSPEC
3754 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
3755 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
3757 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
3758 && (fp_zero_operand (SET_SRC (pat))
3759 || fp_one_operand (SET_SRC (pat)))
3760 /* ??? If this is a -m4 or -m4-single compilation, in general
3761 we don't know the current setting of fpscr, so disable fldi.
3762 There is an exception if this was a register-register move
3763 before reload - and hence it was ascertained that we have
3764 single precision setting - and in a post-reload optimization
3765 we changed this to do a constant load. In that case
3766 we don't have an r0 clobber, hence we must use fldi. */
3767 && (! TARGET_SH4 || TARGET_FMOVD
3768 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
3770 && GET_CODE (SET_DEST (pat)) == REG
3771 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
3773 && GET_MODE (SET_DEST (pat)) == SImode
3774 && (satisfies_constraint_I20 (SET_SRC (pat))
3775 || satisfies_constraint_I28 (SET_SRC (pat))))
3776 && ! satisfies_constraint_I08 (SET_SRC (pat)))
3786 return (GET_CODE (insn) == INSN
3787 && GET_CODE (PATTERN (insn)) == SET
3788 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
3789 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
3790 /* Don't match mova_const. */
3791 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
3794 /* Fix up a mova from a switch that went out of range. */
3796 fixup_mova (rtx mova)
3798 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
3801 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
3802 INSN_CODE (mova) = -1;
3807 rtx lab = gen_label_rtx ();
3808 rtx wpat, wpat0, wpat1, wsrc, diff;
3812 worker = NEXT_INSN (worker);
3814 && GET_CODE (worker) != CODE_LABEL
3815 && GET_CODE (worker) != JUMP_INSN);
3816 } while (GET_CODE (worker) == NOTE
3817 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
3818 wpat = PATTERN (worker);
3819 wpat0 = XVECEXP (wpat, 0, 0);
3820 wpat1 = XVECEXP (wpat, 0, 1);
3821 wsrc = SET_SRC (wpat0);
3822 PATTERN (worker) = (gen_casesi_worker_2
3823 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
3824 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
3826 INSN_CODE (worker) = -1;
3827 diff = gen_rtx_MINUS (Pmode, XVECEXP (SET_SRC (PATTERN (mova)), 0, 0),
3828 gen_rtx_LABEL_REF (Pmode, lab));
3829 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, diff), UNSPEC_PIC);
3830 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
3831 INSN_CODE (mova) = -1;
3835 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
3836 *num_mova, and check if the new mova is not nested within the first one.
3837 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
3838 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
3840 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
3842 int n_addr = 0; /* Initialization to shut up spurious warning. */
3843 int f_target, n_target = 0; /* Likewise. */
3847 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
3848 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
3849 if (n_addr > n_target || n_addr + 1022 < n_target)
3851 /* Change the mova into a load.
3852 broken_move will then return true for it. */
3853 fixup_mova (new_mova);
3859 *first_mova = new_mova;
3864 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
3869 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
3870 > n_target - n_addr)
3872 fixup_mova (*first_mova);
3877 fixup_mova (new_mova);
3882 /* Find the last barrier from insn FROM which is close enough to hold the
3883 constant pool. If we can't find one, then create one near the end of
3887 find_barrier (int num_mova, rtx mova, rtx from)
3896 int leading_mova = num_mova;
3897 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
3902 /* For HImode: range is 510, add 4 because pc counts from address of
3903 second instruction after this one, subtract 2 for the jump instruction
3904 that we may need to emit before the table, subtract 2 for the instruction
3905 that fills the jump delay slot (in very rare cases, reorg will take an
3906 instruction from after the constant pool or will leave the delay slot
3907 empty). This gives 510.
3908 For SImode: range is 1020, add 4 because pc counts from address of
3909 second instruction after this one, subtract 2 in case pc is 2 byte
3910 aligned, subtract 2 for the jump instruction that we may need to emit
3911 before the table, subtract 2 for the instruction that fills the jump
3912 delay slot. This gives 1018. */
3914 /* The branch will always be shortened now that the reference address for
3915 forward branches is the successor address, thus we need no longer make
3916 adjustments to the [sh]i_limit for -O0. */
3921 while (from && count_si < si_limit && count_hi < hi_limit)
3923 int inc = get_attr_length (from);
3926 /* If this is a label that existed at the time of the compute_alignments
3927 call, determine the alignment. N.B. When find_barrier recurses for
3928 an out-of-reach mova, we might see labels at the start of previously
3929 inserted constant tables. */
3930 if (GET_CODE (from) == CODE_LABEL
3931 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
3934 new_align = 1 << label_to_alignment (from);
3935 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
3936 new_align = 1 << barrier_align (from);
3941 /* In case we are scanning a constant table because of recursion, check
3942 for explicit alignments. If the table is long, we might be forced
3943 to emit the new table in front of it; the length of the alignment
3944 might be the last straw. */
3945 else if (GET_CODE (from) == INSN
3946 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
3947 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
3948 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
3949 /* When we find the end of a constant table, paste the new constant
3950 at the end. That is better than putting it in front because
3951 this way, we don't need extra alignment for adding a 4-byte-aligned
3952 mov(a) label to a 2/4 or 8/4 byte aligned table. */
3953 else if (GET_CODE (from) == INSN
3954 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
3955 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
3958 if (GET_CODE (from) == BARRIER)
3962 found_barrier = from;
3964 /* If we are at the end of the function, or in front of an alignment
3965 instruction, we need not insert an extra alignment. We prefer
3966 this kind of barrier. */
3967 if (barrier_align (from) > 2)
3968 good_barrier = from;
3970 /* If we are at the end of a hot/cold block, dump the constants
3972 next = NEXT_INSN (from);
3975 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
3979 if (broken_move (from))
3982 enum machine_mode mode;
3984 pat = PATTERN (from);
3985 if (GET_CODE (pat) == PARALLEL)
3986 pat = XVECEXP (pat, 0, 0);
3987 src = SET_SRC (pat);
3988 dst = SET_DEST (pat);
3989 mode = GET_MODE (dst);
3991 /* We must explicitly check the mode, because sometimes the
3992 front end will generate code to load unsigned constants into
3993 HImode targets without properly sign extending them. */
3995 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
3998 /* We put the short constants before the long constants, so
3999 we must count the length of short constants in the range
4000 for the long constants. */
4001 /* ??? This isn't optimal, but is easy to do. */
4006 /* We dump DF/DI constants before SF/SI ones, because
4007 the limit is the same, but the alignment requirements
4008 are higher. We may waste up to 4 additional bytes
4009 for alignment, and the DF/DI constant may have
4010 another SF/SI constant placed before it. */
4011 if (TARGET_SHCOMPACT
4013 && (mode == DFmode || mode == DImode))
4018 while (si_align > 2 && found_si + si_align - 2 > count_si)
4020 if (found_si > count_si)
4021 count_si = found_si;
4022 found_si += GET_MODE_SIZE (mode);
4024 si_limit -= GET_MODE_SIZE (mode);
4030 switch (untangle_mova (&num_mova, &mova, from))
4032 case 0: return find_barrier (0, 0, mova);
4037 = good_barrier ? good_barrier : found_barrier;
4041 if (found_si > count_si)
4042 count_si = found_si;
4044 else if (GET_CODE (from) == JUMP_INSN
4045 && (GET_CODE (PATTERN (from)) == ADDR_VEC
4046 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
4048 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4050 && (prev_nonnote_insn (from)
4051 == XEXP (MOVA_LABELREF (mova), 0))))
4053 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4055 /* We have just passed the barrier in front of the
4056 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4057 the ADDR_DIFF_VEC is accessed as data, just like our pool
4058 constants, this is a good opportunity to accommodate what
4059 we have gathered so far.
4060 If we waited any longer, we could end up at a barrier in
4061 front of code, which gives worse cache usage for separated
4062 instruction / data caches. */
4063 good_barrier = found_barrier;
4068 rtx body = PATTERN (from);
4069 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4072 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4073 else if (GET_CODE (from) == JUMP_INSN
4075 && ! TARGET_SMALLCODE)
4081 if (new_align > si_align)
4083 si_limit -= (count_si - 1) & (new_align - si_align);
4084 si_align = new_align;
4086 count_si = (count_si + new_align - 1) & -new_align;
4091 if (new_align > hi_align)
4093 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4094 hi_align = new_align;
4096 count_hi = (count_hi + new_align - 1) & -new_align;
4098 from = NEXT_INSN (from);
4105 /* Try as we might, the leading mova is out of range. Change
4106 it into a load (which will become a pcload) and retry. */
4108 return find_barrier (0, 0, mova);
4112 /* Insert the constant pool table before the mova instruction,
4113 to prevent the mova label reference from going out of range. */
4115 good_barrier = found_barrier = barrier_before_mova;
4121 if (good_barrier && next_real_insn (found_barrier))
4122 found_barrier = good_barrier;
4126 /* We didn't find a barrier in time to dump our stuff,
4127 so we'll make one. */
4128 rtx label = gen_label_rtx ();
4130 /* If we exceeded the range, then we must back up over the last
4131 instruction we looked at. Otherwise, we just need to undo the
4132 NEXT_INSN at the end of the loop. */
4133 if (PREV_INSN (from) != orig
4134 && (count_hi > hi_limit || count_si > si_limit))
4135 from = PREV_INSN (PREV_INSN (from));
4137 from = PREV_INSN (from);
4139 /* Walk back to be just before any jump or label.
4140 Putting it before a label reduces the number of times the branch
4141 around the constant pool table will be hit. Putting it before
4142 a jump makes it more likely that the bra delay slot will be
4144 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
4145 || GET_CODE (from) == CODE_LABEL)
4146 from = PREV_INSN (from);
4148 from = emit_jump_insn_after (gen_jump (label), from);
4149 JUMP_LABEL (from) = label;
4150 LABEL_NUSES (label) = 1;
4151 found_barrier = emit_barrier_after (from);
4152 emit_label_after (label, found_barrier);
4155 return found_barrier;
4158 /* If the instruction INSN is implemented by a special function, and we can
4159 positively find the register that is used to call the sfunc, and this
4160 register is not used anywhere else in this instruction - except as the
4161 destination of a set, return this register; else, return 0. */
4163 sfunc_uses_reg (rtx insn)
4166 rtx pattern, part, reg_part, reg;
4168 if (GET_CODE (insn) != INSN)
4170 pattern = PATTERN (insn);
4171 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4174 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4176 part = XVECEXP (pattern, 0, i);
4177 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4182 reg = XEXP (reg_part, 0);
4183 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4185 part = XVECEXP (pattern, 0, i);
4186 if (part == reg_part || GET_CODE (part) == CLOBBER)
4188 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4189 && GET_CODE (SET_DEST (part)) == REG)
4190 ? SET_SRC (part) : part)))
4196 /* See if the only way in which INSN uses REG is by calling it, or by
4197 setting it while calling it. Set *SET to a SET rtx if the register
4201 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4207 reg2 = sfunc_uses_reg (insn);
4208 if (reg2 && REGNO (reg2) == REGNO (reg))
4210 pattern = single_set (insn);
4212 && GET_CODE (SET_DEST (pattern)) == REG
4213 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4217 if (GET_CODE (insn) != CALL_INSN)
4219 /* We don't use rtx_equal_p because we don't care if the mode is
4221 pattern = single_set (insn);
4223 && GET_CODE (SET_DEST (pattern)) == REG
4224 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4230 par = PATTERN (insn);
4231 if (GET_CODE (par) == PARALLEL)
4232 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4234 part = XVECEXP (par, 0, i);
4235 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4238 return reg_mentioned_p (reg, SET_SRC (pattern));
4244 pattern = PATTERN (insn);
4246 if (GET_CODE (pattern) == PARALLEL)
4250 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4251 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4253 pattern = XVECEXP (pattern, 0, 0);
4256 if (GET_CODE (pattern) == SET)
4258 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4260 /* We don't use rtx_equal_p, because we don't care if the
4261 mode is different. */
4262 if (GET_CODE (SET_DEST (pattern)) != REG
4263 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4269 pattern = SET_SRC (pattern);
4272 if (GET_CODE (pattern) != CALL
4273 || GET_CODE (XEXP (pattern, 0)) != MEM
4274 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4280 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4281 general registers. Bits 0..15 mean that the respective registers
4282 are used as inputs in the instruction. Bits 16..31 mean that the
4283 registers 0..15, respectively, are used as outputs, or are clobbered.
4284 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4286 regs_used (rtx x, int is_dest)
4294 code = GET_CODE (x);
4299 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4300 << (REGNO (x) + is_dest));
4304 rtx y = SUBREG_REG (x);
4306 if (GET_CODE (y) != REG)
4309 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4311 subreg_regno_offset (REGNO (y),
4314 GET_MODE (x)) + is_dest));
4318 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4320 /* If there was a return value, it must have been indicated with USE. */
4335 fmt = GET_RTX_FORMAT (code);
4337 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4342 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4343 used |= regs_used (XVECEXP (x, i, j), is_dest);
4345 else if (fmt[i] == 'e')
4346 used |= regs_used (XEXP (x, i), is_dest);
4351 /* Create an instruction that prevents redirection of a conditional branch
4352 to the destination of the JUMP with address ADDR.
4353 If the branch needs to be implemented as an indirect jump, try to find
4354 a scratch register for it.
4355 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4356 If any preceding insn that doesn't fit into a delay slot is good enough,
4357 pass 1. Pass 2 if a definite blocking insn is needed.
4358 -1 is used internally to avoid deep recursion.
4359 If a blocking instruction is made or recognized, return it. */
4362 gen_block_redirect (rtx jump, int addr, int need_block)
4365 rtx prev = prev_nonnote_insn (jump);
4368 /* First, check if we already have an instruction that satisfies our need. */
4369 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
4371 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4373 if (GET_CODE (PATTERN (prev)) == USE
4374 || GET_CODE (PATTERN (prev)) == CLOBBER
4375 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4377 else if ((need_block &= ~1) < 0)
4379 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4382 if (GET_CODE (PATTERN (jump)) == RETURN)
4386 /* Reorg even does nasty things with return insns that cause branches
4387 to go out of range - see find_end_label and callers. */
4388 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4390 /* We can't use JUMP_LABEL here because it might be undefined
4391 when not optimizing. */
4392 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4393 /* If the branch is out of range, try to find a scratch register for it. */
4395 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4399 /* Don't look for the stack pointer as a scratch register,
4400 it would cause trouble if an interrupt occurred. */
4401 unsigned try = 0x7fff, used;
4402 int jump_left = flag_expensive_optimizations + 1;
4404 /* It is likely that the most recent eligible instruction is wanted for
4405 the delay slot. Therefore, find out which registers it uses, and
4406 try to avoid using them. */
4408 for (scan = jump; (scan = PREV_INSN (scan)); )
4412 if (INSN_DELETED_P (scan))
4414 code = GET_CODE (scan);
4415 if (code == CODE_LABEL || code == JUMP_INSN)
4418 && GET_CODE (PATTERN (scan)) != USE
4419 && GET_CODE (PATTERN (scan)) != CLOBBER
4420 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4422 try &= ~regs_used (PATTERN (scan), 0);
4426 for (used = dead = 0, scan = JUMP_LABEL (jump);
4427 (scan = NEXT_INSN (scan)); )
4431 if (INSN_DELETED_P (scan))
4433 code = GET_CODE (scan);
4436 used |= regs_used (PATTERN (scan), 0);
4437 if (code == CALL_INSN)
4438 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4439 dead |= (used >> 16) & ~used;
4445 if (code == JUMP_INSN)
4447 if (jump_left-- && simplejump_p (scan))
4448 scan = JUMP_LABEL (scan);
4454 /* Mask out the stack pointer again, in case it was
4455 the only 'free' register we have found. */
4458 /* If the immediate destination is still in range, check for possible
4459 threading with a jump beyond the delay slot insn.
4460 Don't check if we are called recursively; the jump has been or will be
4461 checked in a different invocation then. */
4463 else if (optimize && need_block >= 0)
4465 rtx next = next_active_insn (next_active_insn (dest));
4466 if (next && GET_CODE (next) == JUMP_INSN
4467 && GET_CODE (PATTERN (next)) == SET
4468 && recog_memoized (next) == CODE_FOR_jump_compact)
4470 dest = JUMP_LABEL (next);
4472 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4474 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4480 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4482 /* It would be nice if we could convert the jump into an indirect
4483 jump / far branch right now, and thus exposing all constituent
4484 instructions to further optimization. However, reorg uses
4485 simplejump_p to determine if there is an unconditional jump where
4486 it should try to schedule instructions from the target of the
4487 branch; simplejump_p fails for indirect jumps even if they have
4489 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4490 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4492 /* ??? We would like this to have the scope of the jump, but that
4493 scope will change when a delay slot insn of an inner scope is added.
4494 Hence, after delay slot scheduling, we'll have to expect
4495 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4498 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4499 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4502 else if (need_block)
4503 /* We can't use JUMP_LABEL here because it might be undefined
4504 when not optimizing. */
4505 return emit_insn_before (gen_block_branch_redirect
4506 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4511 #define CONDJUMP_MIN -252
4512 #define CONDJUMP_MAX 262
4515 /* A label (to be placed) in front of the jump
4516 that jumps to our ultimate destination. */
4518 /* Where we are going to insert it if we cannot move the jump any farther,
4519 or the jump itself if we have picked up an existing jump. */
4521 /* The ultimate destination. */
4523 struct far_branch *prev;
4524 /* If the branch has already been created, its address;
4525 else the address of its first prospective user. */
4529 static void gen_far_branch (struct far_branch *);
4530 enum mdep_reorg_phase_e mdep_reorg_phase;
4532 gen_far_branch (struct far_branch *bp)
4534 rtx insn = bp->insert_place;
4536 rtx label = gen_label_rtx ();
4539 emit_label_after (label, insn);
4542 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
4543 LABEL_NUSES (bp->far_label)++;
4546 jump = emit_jump_insn_after (gen_return (), insn);
4547 /* Emit a barrier so that reorg knows that any following instructions
4548 are not reachable via a fall-through path.
4549 But don't do this when not optimizing, since we wouldn't suppress the
4550 alignment for the barrier then, and could end up with out-of-range
4551 pc-relative loads. */
4553 emit_barrier_after (jump);
4554 emit_label_after (bp->near_label, insn);
4555 JUMP_LABEL (jump) = bp->far_label;
4556 ok = invert_jump (insn, label, 1);
4559 /* If we are branching around a jump (rather than a return), prevent
4560 reorg from using an insn from the jump target as the delay slot insn -
4561 when reorg did this, it pessimized code (we rather hide the delay slot)
4562 and it could cause branches to go out of range. */
4565 (gen_stuff_delay_slot
4566 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
4567 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
4569 /* Prevent reorg from undoing our splits. */
4570 gen_block_redirect (jump, bp->address += 2, 2);
4573 /* Fix up ADDR_DIFF_VECs. */
4575 fixup_addr_diff_vecs (rtx first)
4579 for (insn = first; insn; insn = NEXT_INSN (insn))
4581 rtx vec_lab, pat, prev, prevpat, x, braf_label;
4583 if (GET_CODE (insn) != JUMP_INSN
4584 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
4586 pat = PATTERN (insn);
4587 vec_lab = XEXP (XEXP (pat, 0), 0);
4589 /* Search the matching casesi_jump_2. */
4590 for (prev = vec_lab; ; prev = PREV_INSN (prev))
4592 if (GET_CODE (prev) != JUMP_INSN)
4594 prevpat = PATTERN (prev);
4595 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
4597 x = XVECEXP (prevpat, 0, 1);
4598 if (GET_CODE (x) != USE)
4601 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
4604 /* FIXME: This is a bug in the optimizer, but it seems harmless
4605 to just avoid panicing. */
4609 /* Emit the reference label of the braf where it belongs, right after
4610 the casesi_jump_2 (i.e. braf). */
4611 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
4612 emit_label_after (braf_label, prev);
4614 /* Fix up the ADDR_DIF_VEC to be relative
4615 to the reference address of the braf. */
4616 XEXP (XEXP (pat, 0), 0) = braf_label;
4620 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
4621 a barrier. Return the base 2 logarithm of the desired alignment. */
4623 barrier_align (rtx barrier_or_label)
4625 rtx next = next_real_insn (barrier_or_label), pat, prev;
4626 int slot, credit, jump_to_next = 0;
4631 pat = PATTERN (next);
4633 if (GET_CODE (pat) == ADDR_DIFF_VEC)
4636 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
4637 /* This is a barrier in front of a constant table. */
4640 prev = prev_real_insn (barrier_or_label);
4641 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
4643 pat = PATTERN (prev);
4644 /* If this is a very small table, we want to keep the alignment after
4645 the table to the minimum for proper code alignment. */
4646 return ((TARGET_SMALLCODE
4647 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
4648 <= (unsigned) 1 << (CACHE_LOG - 2)))
4649 ? 1 << TARGET_SHMEDIA : align_jumps_log);
4652 if (TARGET_SMALLCODE)
4655 if (! TARGET_SH2 || ! optimize)
4656 return align_jumps_log;
4658 /* When fixing up pcloads, a constant table might be inserted just before
4659 the basic block that ends with the barrier. Thus, we can't trust the
4660 instruction lengths before that. */
4661 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
4663 /* Check if there is an immediately preceding branch to the insn beyond
4664 the barrier. We must weight the cost of discarding useful information
4665 from the current cache line when executing this branch and there is
4666 an alignment, against that of fetching unneeded insn in front of the
4667 branch target when there is no alignment. */
4669 /* There are two delay_slot cases to consider. One is the simple case
4670 where the preceding branch is to the insn beyond the barrier (simple
4671 delay slot filling), and the other is where the preceding branch has
4672 a delay slot that is a duplicate of the insn after the barrier
4673 (fill_eager_delay_slots) and the branch is to the insn after the insn
4674 after the barrier. */
4676 /* PREV is presumed to be the JUMP_INSN for the barrier under
4677 investigation. Skip to the insn before it. */
4678 prev = prev_real_insn (prev);
4680 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
4681 credit >= 0 && prev && GET_CODE (prev) == INSN;
4682 prev = prev_real_insn (prev))
4685 if (GET_CODE (PATTERN (prev)) == USE
4686 || GET_CODE (PATTERN (prev)) == CLOBBER)
4688 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
4690 prev = XVECEXP (PATTERN (prev), 0, 1);
4691 if (INSN_UID (prev) == INSN_UID (next))
4693 /* Delay slot was filled with insn at jump target. */
4700 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4702 credit -= get_attr_length (prev);
4705 && GET_CODE (prev) == JUMP_INSN
4706 && JUMP_LABEL (prev))
4710 || next_real_insn (JUMP_LABEL (prev)) == next
4711 /* If relax_delay_slots() decides NEXT was redundant
4712 with some previous instruction, it will have
4713 redirected PREV's jump to the following insn. */
4714 || JUMP_LABEL (prev) == next_nonnote_insn (next)
4715 /* There is no upper bound on redundant instructions
4716 that might have been skipped, but we must not put an
4717 alignment where none had been before. */
4718 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
4720 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
4721 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
4722 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
4724 rtx pat = PATTERN (prev);
4725 if (GET_CODE (pat) == PARALLEL)
4726 pat = XVECEXP (pat, 0, 0);
4727 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
4733 return align_jumps_log;
4736 /* If we are inside a phony loop, almost any kind of label can turn up as the
4737 first one in the loop. Aligning a braf label causes incorrect switch
4738 destination addresses; we can detect braf labels because they are
4739 followed by a BARRIER.
4740 Applying loop alignment to small constant or switch tables is a waste
4741 of space, so we suppress this too. */
4743 sh_loop_align (rtx label)
4748 next = next_nonnote_insn (next);
4749 while (next && GET_CODE (next) == CODE_LABEL);
4753 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
4754 || recog_memoized (next) == CODE_FOR_consttable_2)
4757 return align_loops_log;
4760 /* Do a final pass over the function, just before delayed branch
4766 rtx first, insn, mova = NULL_RTX;
4768 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
4769 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
4771 first = get_insns ();
4772 max_labelno_before_reorg = max_label_num ();
4774 /* We must split call insns before introducing `mova's. If we're
4775 optimizing, they'll have already been split. Otherwise, make
4776 sure we don't split them too late. */
4778 split_all_insns_noflow ();
4783 /* If relaxing, generate pseudo-ops to associate function calls with
4784 the symbols they call. It does no harm to not generate these
4785 pseudo-ops. However, when we can generate them, it enables to
4786 linker to potentially relax the jsr to a bsr, and eliminate the
4787 register load and, possibly, the constant pool entry. */
4789 mdep_reorg_phase = SH_INSERT_USES_LABELS;
4792 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
4793 own purposes. This works because none of the remaining passes
4794 need to look at them.
4796 ??? But it may break in the future. We should use a machine
4797 dependent REG_NOTE, or some other approach entirely. */
4798 for (insn = first; insn; insn = NEXT_INSN (insn))
4804 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
4806 remove_note (insn, note);
4810 for (insn = first; insn; insn = NEXT_INSN (insn))
4812 rtx pattern, reg, link, set, scan, dies, label;
4813 int rescan = 0, foundinsn = 0;
4815 if (GET_CODE (insn) == CALL_INSN)
4817 pattern = PATTERN (insn);
4819 if (GET_CODE (pattern) == PARALLEL)
4820 pattern = XVECEXP (pattern, 0, 0);
4821 if (GET_CODE (pattern) == SET)
4822 pattern = SET_SRC (pattern);
4824 if (GET_CODE (pattern) != CALL
4825 || GET_CODE (XEXP (pattern, 0)) != MEM)
4828 reg = XEXP (XEXP (pattern, 0), 0);
4832 reg = sfunc_uses_reg (insn);
4837 if (GET_CODE (reg) != REG)
4840 /* Try scanning backward to find where the register is set. */
4842 for (scan = PREV_INSN (insn);
4843 scan && GET_CODE (scan) != CODE_LABEL;
4844 scan = PREV_INSN (scan))
4846 if (! INSN_P (scan))
4849 if (! reg_mentioned_p (reg, scan))
4852 if (noncall_uses_reg (reg, scan, &set))
4865 /* The register is set at LINK. */
4867 /* We can only optimize the function call if the register is
4868 being set to a symbol. In theory, we could sometimes
4869 optimize calls to a constant location, but the assembler
4870 and linker do not support that at present. */
4871 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
4872 && GET_CODE (SET_SRC (set)) != LABEL_REF)
4875 /* Scan forward from LINK to the place where REG dies, and
4876 make sure that the only insns which use REG are
4877 themselves function calls. */
4879 /* ??? This doesn't work for call targets that were allocated
4880 by reload, since there may not be a REG_DEAD note for the
4884 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
4888 /* Don't try to trace forward past a CODE_LABEL if we haven't
4889 seen INSN yet. Ordinarily, we will only find the setting insn
4890 if it is in the same basic block. However,
4891 cross-jumping can insert code labels in between the load and
4892 the call, and can result in situations where a single call
4893 insn may have two targets depending on where we came from. */
4895 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
4898 if (! INSN_P (scan))
4901 /* Don't try to trace forward past a JUMP. To optimize
4902 safely, we would have to check that all the
4903 instructions at the jump destination did not use REG. */
4905 if (GET_CODE (scan) == JUMP_INSN)
4908 if (! reg_mentioned_p (reg, scan))
4911 if (noncall_uses_reg (reg, scan, &scanset))
4918 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
4920 /* There is a function call to this register other
4921 than the one we are checking. If we optimize
4922 this call, we need to rescan again below. */
4926 /* ??? We shouldn't have to worry about SCANSET here.
4927 We should just be able to check for a REG_DEAD note
4928 on a function call. However, the REG_DEAD notes are
4929 apparently not dependable around libcalls; c-torture
4930 execute/920501-2 is a test case. If SCANSET is set,
4931 then this insn sets the register, so it must have
4932 died earlier. Unfortunately, this will only handle
4933 the cases in which the register is, in fact, set in a
4936 /* ??? We shouldn't have to use FOUNDINSN here.
4937 This dates back to when we used LOG_LINKS to find
4938 the most recent insn which sets the register. */
4942 || find_reg_note (scan, REG_DEAD, reg)))
4951 /* Either there was a branch, or some insn used REG
4952 other than as a function call address. */
4956 /* Create a code label, and put it in a REG_LABEL_OPERAND note
4957 on the insn which sets the register, and on each call insn
4958 which uses the register. In final_prescan_insn we look for
4959 the REG_LABEL_OPERAND notes, and output the appropriate label
4962 label = gen_label_rtx ();
4963 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL_OPERAND, label,
4965 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL_OPERAND, label,
4974 scan = NEXT_INSN (scan);
4976 && ((GET_CODE (scan) == CALL_INSN
4977 && reg_mentioned_p (reg, scan))
4978 || ((reg2 = sfunc_uses_reg (scan))
4979 && REGNO (reg2) == REGNO (reg))))
4981 = gen_rtx_INSN_LIST (REG_LABEL_OPERAND, label,
4984 while (scan != dies);
4990 fixup_addr_diff_vecs (first);
4994 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
4995 shorten_branches (first);
4998 /* Scan the function looking for move instructions which have to be
4999 changed to pc-relative loads and insert the literal tables. */
5000 label_ref_list_pool = create_alloc_pool ("label references list",
5001 sizeof (struct label_ref_list_d),
5003 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5004 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5008 /* ??? basic block reordering can move a switch table dispatch
5009 below the switch table. Check if that has happened.
5010 We only have the addresses available when optimizing; but then,
5011 this check shouldn't be needed when not optimizing. */
5012 if (!untangle_mova (&num_mova, &mova, insn))
5018 else if (GET_CODE (insn) == JUMP_INSN
5019 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5021 /* ??? loop invariant motion can also move a mova out of a
5022 loop. Since loop does this code motion anyway, maybe we
5023 should wrap UNSPEC_MOVA into a CONST, so that reload can
5026 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5027 || (prev_nonnote_insn (insn)
5028 == XEXP (MOVA_LABELREF (mova), 0))))
5035 /* Some code might have been inserted between the mova and
5036 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5037 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5038 total += get_attr_length (scan);
5040 /* range of mova is 1020, add 4 because pc counts from address of
5041 second instruction after this one, subtract 2 in case pc is 2
5042 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5043 cancels out with alignment effects of the mova itself. */
5046 /* Change the mova into a load, and restart scanning
5047 there. broken_move will then return true for mova. */
5052 if (broken_move (insn)
5053 || (GET_CODE (insn) == INSN
5054 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5057 /* Scan ahead looking for a barrier to stick the constant table
5059 rtx barrier = find_barrier (num_mova, mova, insn);
5060 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5061 int need_aligned_label = 0;
5063 if (num_mova && ! mova_p (mova))
5065 /* find_barrier had to change the first mova into a
5066 pcload; thus, we have to start with this new pcload. */
5070 /* Now find all the moves between the points and modify them. */
5071 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5073 if (GET_CODE (scan) == CODE_LABEL)
5075 if (GET_CODE (scan) == INSN
5076 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5077 need_aligned_label = 1;
5078 if (broken_move (scan))
5080 rtx *patp = &PATTERN (scan), pat = *patp;
5084 enum machine_mode mode;
5086 if (GET_CODE (pat) == PARALLEL)
5087 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5088 src = SET_SRC (pat);
5089 dst = SET_DEST (pat);
5090 mode = GET_MODE (dst);
5092 if (mode == SImode && hi_const (src)
5093 && REGNO (dst) != FPUL_REG)
5098 while (GET_CODE (dst) == SUBREG)
5100 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5101 GET_MODE (SUBREG_REG (dst)),
5104 dst = SUBREG_REG (dst);
5106 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5108 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
5110 /* This must be an insn that clobbers r0. */
5111 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5112 XVECLEN (PATTERN (scan), 0)
5114 rtx clobber = *clobberp;
5116 gcc_assert (GET_CODE (clobber) == CLOBBER
5117 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5120 && reg_set_between_p (r0_rtx, last_float_move, scan))
5124 && GET_MODE_SIZE (mode) != 4
5125 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5127 lab = add_constant (src, mode, last_float);
5129 emit_insn_before (gen_mova (lab), scan);
5132 /* There will be a REG_UNUSED note for r0 on
5133 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5134 lest reorg:mark_target_live_regs will not
5135 consider r0 to be used, and we end up with delay
5136 slot insn in front of SCAN that clobbers r0. */
5138 = find_regno_note (last_float_move, REG_UNUSED, 0);
5140 /* If we are not optimizing, then there may not be
5143 PUT_MODE (note, REG_INC);
5145 *last_float_addr = r0_inc_rtx;
5147 last_float_move = scan;
5149 newsrc = gen_const_mem (mode,
5150 (((TARGET_SH4 && ! TARGET_FMOVD)
5151 || REGNO (dst) == FPUL_REG)
5154 last_float_addr = &XEXP (newsrc, 0);
5156 /* Remove the clobber of r0. */
5157 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5158 gen_rtx_SCRATCH (Pmode));
5160 /* This is a mova needing a label. Create it. */
5161 else if (GET_CODE (src) == UNSPEC
5162 && XINT (src, 1) == UNSPEC_MOVA
5163 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5165 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5166 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5167 newsrc = gen_rtx_UNSPEC (SImode,
5168 gen_rtvec (1, newsrc),
5173 lab = add_constant (src, mode, 0);
5174 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5175 newsrc = gen_const_mem (mode, newsrc);
5177 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5178 INSN_CODE (scan) = -1;
5181 dump_table (need_aligned_label ? insn : 0, barrier);
5185 free_alloc_pool (label_ref_list_pool);
5186 for (insn = first; insn; insn = NEXT_INSN (insn))
5187 PUT_MODE (insn, VOIDmode);
5189 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5190 INSN_ADDRESSES_FREE ();
5191 split_branches (first);
5193 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5194 also has an effect on the register that holds the address of the sfunc.
5195 Insert an extra dummy insn in front of each sfunc that pretends to
5196 use this register. */
5197 if (flag_delayed_branch)
5199 for (insn = first; insn; insn = NEXT_INSN (insn))
5201 rtx reg = sfunc_uses_reg (insn);
5205 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5209 /* fpscr is not actually a user variable, but we pretend it is for the
5210 sake of the previous optimization passes, since we want it handled like
5211 one. However, we don't have any debugging information for it, so turn
5212 it into a non-user variable now. */
5214 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5216 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5220 get_dest_uid (rtx label, int max_uid)
5222 rtx dest = next_real_insn (label);
5225 /* This can happen for an undefined label. */
5227 dest_uid = INSN_UID (dest);
5228 /* If this is a newly created branch redirection blocking instruction,
5229 we cannot index the branch_uid or insn_addresses arrays with its
5230 uid. But then, we won't need to, because the actual destination is
5231 the following branch. */
5232 while (dest_uid >= max_uid)
5234 dest = NEXT_INSN (dest);
5235 dest_uid = INSN_UID (dest);
5237 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
5242 /* Split condbranches that are out of range. Also add clobbers for
5243 scratch registers that are needed in far jumps.
5244 We do this before delay slot scheduling, so that it can take our
5245 newly created instructions into account. It also allows us to
5246 find branches with common targets more easily. */
5249 split_branches (rtx first)
5252 struct far_branch **uid_branch, *far_branch_list = 0;
5253 int max_uid = get_max_uid ();
5256 /* Find out which branches are out of range. */
5257 shorten_branches (first);
5259 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5260 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5262 for (insn = first; insn; insn = NEXT_INSN (insn))
5263 if (! INSN_P (insn))
5265 else if (INSN_DELETED_P (insn))
5267 /* Shorten_branches would split this instruction again,
5268 so transform it into a note. */
5269 SET_INSN_DELETED (insn);
5271 else if (GET_CODE (insn) == JUMP_INSN
5272 /* Don't mess with ADDR_DIFF_VEC */
5273 && (GET_CODE (PATTERN (insn)) == SET
5274 || GET_CODE (PATTERN (insn)) == RETURN))
5276 enum attr_type type = get_attr_type (insn);
5277 if (type == TYPE_CBRANCH)
5281 if (get_attr_length (insn) > 4)
5283 rtx src = SET_SRC (PATTERN (insn));
5284 rtx olabel = XEXP (XEXP (src, 1), 0);
5285 int addr = INSN_ADDRESSES (INSN_UID (insn));
5287 int dest_uid = get_dest_uid (olabel, max_uid);
5288 struct far_branch *bp = uid_branch[dest_uid];
5290 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5291 the label if the LABEL_NUSES count drops to zero. There is
5292 always a jump_optimize pass that sets these values, but it
5293 proceeds to delete unreferenced code, and then if not
5294 optimizing, to un-delete the deleted instructions, thus
5295 leaving labels with too low uses counts. */
5298 JUMP_LABEL (insn) = olabel;
5299 LABEL_NUSES (olabel)++;
5303 bp = (struct far_branch *) alloca (sizeof *bp);
5304 uid_branch[dest_uid] = bp;
5305 bp->prev = far_branch_list;
5306 far_branch_list = bp;
5308 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5309 LABEL_NUSES (bp->far_label)++;
5313 label = bp->near_label;
5314 if (! label && bp->address - addr >= CONDJUMP_MIN)
5316 rtx block = bp->insert_place;
5318 if (GET_CODE (PATTERN (block)) == RETURN)
5319 block = PREV_INSN (block);
5321 block = gen_block_redirect (block,
5323 label = emit_label_after (gen_label_rtx (),
5325 bp->near_label = label;
5327 else if (label && ! NEXT_INSN (label))
5329 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5330 bp->insert_place = insn;
5332 gen_far_branch (bp);
5336 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5338 bp->near_label = label = gen_label_rtx ();
5339 bp->insert_place = insn;
5342 ok = redirect_jump (insn, label, 0);
5347 /* get_attr_length (insn) == 2 */
5348 /* Check if we have a pattern where reorg wants to redirect
5349 the branch to a label from an unconditional branch that
5351 /* We can't use JUMP_LABEL here because it might be undefined
5352 when not optimizing. */
5353 /* A syntax error might cause beyond to be NULL_RTX. */
5355 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5359 && (GET_CODE (beyond) == JUMP_INSN
5360 || ((beyond = next_active_insn (beyond))
5361 && GET_CODE (beyond) == JUMP_INSN))
5362 && GET_CODE (PATTERN (beyond)) == SET
5363 && recog_memoized (beyond) == CODE_FOR_jump_compact
5365 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5366 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5368 gen_block_redirect (beyond,
5369 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5372 next = next_active_insn (insn);
5374 if ((GET_CODE (next) == JUMP_INSN
5375 || ((next = next_active_insn (next))
5376 && GET_CODE (next) == JUMP_INSN))
5377 && GET_CODE (PATTERN (next)) == SET
5378 && recog_memoized (next) == CODE_FOR_jump_compact
5380 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5381 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5383 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5385 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5387 int addr = INSN_ADDRESSES (INSN_UID (insn));
5390 struct far_branch *bp;
5392 if (type == TYPE_JUMP)
5394 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5395 dest_uid = get_dest_uid (far_label, max_uid);
5398 /* Parse errors can lead to labels outside
5400 if (! NEXT_INSN (far_label))
5405 JUMP_LABEL (insn) = far_label;
5406 LABEL_NUSES (far_label)++;
5408 redirect_jump (insn, NULL_RTX, 1);
5412 bp = uid_branch[dest_uid];
5415 bp = (struct far_branch *) alloca (sizeof *bp);
5416 uid_branch[dest_uid] = bp;
5417 bp->prev = far_branch_list;
5418 far_branch_list = bp;
5420 bp->far_label = far_label;
5422 LABEL_NUSES (far_label)++;
5424 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5425 if (addr - bp->address <= CONDJUMP_MAX)
5426 emit_label_after (bp->near_label, PREV_INSN (insn));
5429 gen_far_branch (bp);
5435 bp->insert_place = insn;
5437 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5439 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5442 /* Generate all pending far branches,
5443 and free our references to the far labels. */
5444 while (far_branch_list)
5446 if (far_branch_list->near_label
5447 && ! NEXT_INSN (far_branch_list->near_label))
5448 gen_far_branch (far_branch_list);
5450 && far_branch_list->far_label
5451 && ! --LABEL_NUSES (far_branch_list->far_label))
5452 delete_insn (far_branch_list->far_label);
5453 far_branch_list = far_branch_list->prev;
5456 /* Instruction length information is no longer valid due to the new
5457 instructions that have been generated. */
5458 init_insn_lengths ();
5461 /* Dump out instruction addresses, which is useful for debugging the
5462 constant pool table stuff.
5464 If relaxing, output the label and pseudo-ops used to link together
5465 calls and the instruction which set the registers. */
5467 /* ??? The addresses printed by this routine for insns are nonsense for
5468 insns which are inside of a sequence where none of the inner insns have
5469 variable length. This is because the second pass of shorten_branches
5470 does not bother to update them. */
5473 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5474 int noperands ATTRIBUTE_UNUSED)
5476 if (TARGET_DUMPISIZE)
5477 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5483 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
5488 pattern = PATTERN (insn);
5489 if (GET_CODE (pattern) == PARALLEL)
5490 pattern = XVECEXP (pattern, 0, 0);
5491 switch (GET_CODE (pattern))
5494 if (GET_CODE (SET_SRC (pattern)) != CALL
5495 && get_attr_type (insn) != TYPE_SFUNC)
5497 targetm.asm_out.internal_label
5498 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5501 /* else FALLTHROUGH */
5503 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5504 CODE_LABEL_NUMBER (XEXP (note, 0)));
5514 /* Dump out any constants accumulated in the final pass. These will
5518 output_jump_label_table (void)
5524 fprintf (asm_out_file, "\t.align 2\n");
5525 for (i = 0; i < pool_size; i++)
5527 pool_node *p = &pool_vector[i];
5529 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5530 CODE_LABEL_NUMBER (p->label));
5531 output_asm_insn (".long %O0", &p->value);
5539 /* A full frame looks like:
5543 [ if current_function_anonymous_args
5556 local-0 <- fp points here. */
5558 /* Number of bytes pushed for anonymous args, used to pass information
5559 between expand_prologue and expand_epilogue. */
5561 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
5562 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
5563 for an epilogue and a negative value means that it's for a sibcall
5564 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
5565 all the registers that are about to be restored, and hence dead. */
5568 output_stack_adjust (int size, rtx reg, int epilogue_p,
5569 HARD_REG_SET *live_regs_mask)
5571 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
5574 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
5576 /* This test is bogus, as output_stack_adjust is used to re-align the
5579 gcc_assert (!(size % align));
5582 if (CONST_OK_FOR_ADD (size))
5583 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
5584 /* Try to do it with two partial adjustments; however, we must make
5585 sure that the stack is properly aligned at all times, in case
5586 an interrupt occurs between the two partial adjustments. */
5587 else if (CONST_OK_FOR_ADD (size / 2 & -align)
5588 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
5590 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
5591 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
5597 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
5600 /* If TEMP is invalid, we could temporarily save a general
5601 register to MACL. However, there is currently no need
5602 to handle this case, so just die when we see it. */
5604 || current_function_interrupt
5605 || ! call_really_used_regs[temp] || fixed_regs[temp])
5607 if (temp < 0 && ! current_function_interrupt
5608 && (TARGET_SHMEDIA || epilogue_p >= 0))
5611 COPY_HARD_REG_SET (temps, call_used_reg_set);
5612 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
5616 if (current_function_return_rtx)
5618 enum machine_mode mode;
5619 mode = GET_MODE (current_function_return_rtx);
5620 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
5621 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
5623 for (i = 0; i < nreg; i++)
5624 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
5625 if (current_function_calls_eh_return)
5627 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
5628 for (i = 0; i <= 3; i++)
5629 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
5632 if (TARGET_SHMEDIA && epilogue_p < 0)
5633 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
5634 CLEAR_HARD_REG_BIT (temps, i);
5635 if (epilogue_p <= 0)
5637 for (i = FIRST_PARM_REG;
5638 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
5639 CLEAR_HARD_REG_BIT (temps, i);
5640 if (cfun->static_chain_decl != NULL)
5641 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
5643 temp = scavenge_reg (&temps);
5645 if (temp < 0 && live_regs_mask)
5649 COPY_HARD_REG_SET (temps, *live_regs_mask);
5650 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
5651 temp = scavenge_reg (&temps);
5655 rtx adj_reg, tmp_reg, mem;
5657 /* If we reached here, the most likely case is the (sibcall)
5658 epilogue for non SHmedia. Put a special push/pop sequence
5659 for such case as the last resort. This looks lengthy but
5660 would not be problem because it seems to be very
5663 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
5666 /* ??? There is still the slight possibility that r4 or
5667 r5 have been reserved as fixed registers or assigned
5668 as global registers, and they change during an
5669 interrupt. There are possible ways to handle this:
5671 - If we are adjusting the frame pointer (r14), we can do
5672 with a single temp register and an ordinary push / pop
5674 - Grab any call-used or call-saved registers (i.e. not
5675 fixed or globals) for the temps we need. We might
5676 also grab r14 if we are adjusting the stack pointer.
5677 If we can't find enough available registers, issue
5678 a diagnostic and die - the user must have reserved
5679 way too many registers.
5680 But since all this is rather unlikely to happen and
5681 would require extra testing, we just die if r4 / r5
5682 are not available. */
5683 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
5684 && !global_regs[4] && !global_regs[5]);
5686 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
5687 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
5688 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
5689 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
5690 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
5691 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5692 emit_move_insn (mem, tmp_reg);
5693 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
5694 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5695 emit_move_insn (mem, tmp_reg);
5696 emit_move_insn (reg, adj_reg);
5697 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5698 emit_move_insn (adj_reg, mem);
5699 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5700 emit_move_insn (tmp_reg, mem);
5701 /* Tell flow the insns that pop r4/r5 aren't dead. */
5702 emit_insn (gen_rtx_USE (VOIDmode, tmp_reg));
5703 emit_insn (gen_rtx_USE (VOIDmode, adj_reg));
5706 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
5708 /* If SIZE is negative, subtract the positive value.
5709 This sometimes allows a constant pool entry to be shared
5710 between prologue and epilogue code. */
5713 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
5714 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
5718 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
5719 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
5723 = (gen_rtx_EXPR_LIST
5724 (REG_FRAME_RELATED_EXPR,
5725 gen_rtx_SET (VOIDmode, reg,
5726 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
5736 RTX_FRAME_RELATED_P (x) = 1;
5740 /* Output RTL to push register RN onto the stack. */
5747 x = gen_push_fpul ();
5748 else if (rn == FPSCR_REG)
5749 x = gen_push_fpscr ();
5750 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5751 && FP_OR_XD_REGISTER_P (rn))
5753 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5755 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
5757 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5758 x = gen_push_e (gen_rtx_REG (SFmode, rn));
5760 x = gen_push (gen_rtx_REG (SImode, rn));
5764 = gen_rtx_EXPR_LIST (REG_INC,
5765 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
5769 /* Output RTL to pop register RN from the stack. */
5776 x = gen_pop_fpul ();
5777 else if (rn == FPSCR_REG)
5778 x = gen_pop_fpscr ();
5779 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5780 && FP_OR_XD_REGISTER_P (rn))
5782 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5784 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
5786 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5787 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
5789 x = gen_pop (gen_rtx_REG (SImode, rn));
5793 = gen_rtx_EXPR_LIST (REG_INC,
5794 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
5797 /* Generate code to push the regs specified in the mask. */
5800 push_regs (HARD_REG_SET *mask, int interrupt_handler)
5802 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
5805 /* Push PR last; this gives better latencies after the prologue, and
5806 candidates for the return delay slot when there are no general
5807 registers pushed. */
5808 for (; i < FIRST_PSEUDO_REGISTER; i++)
5810 /* If this is an interrupt handler, and the SZ bit varies,
5811 and we have to push any floating point register, we need
5812 to switch to the correct precision first. */
5813 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
5814 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
5816 HARD_REG_SET unsaved;
5819 COMPL_HARD_REG_SET (unsaved, *mask);
5820 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
5824 && (i != FPSCR_REG || ! skip_fpscr)
5825 && TEST_HARD_REG_BIT (*mask, i))
5827 /* If the ISR has RESBANK attribute assigned, don't push any of
5828 the following registers - R0-R14, MACH, MACL and GBR. */
5829 if (! (sh_cfun_resbank_handler_p ()
5830 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
5838 /* Push banked registers last to improve delay slot opportunities. */
5839 if (interrupt_handler)
5840 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
5841 if (TEST_HARD_REG_BIT (*mask, i))
5844 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
5845 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
5849 /* Calculate how much extra space is needed to save all callee-saved
5851 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5854 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
5857 int stack_space = 0;
5858 int interrupt_handler = sh_cfun_interrupt_handler_p ();
5860 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
5861 if ((! call_really_used_regs[reg] || interrupt_handler)
5862 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
5863 /* Leave space to save this target register on the stack,
5864 in case target register allocation wants to use it. */
5865 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5869 /* Decide whether we should reserve space for callee-save target registers,
5870 in case target register allocation wants to use them. REGS_SAVED is
5871 the space, in bytes, that is already required for register saves.
5872 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5875 shmedia_reserve_space_for_target_registers_p (int regs_saved,
5876 HARD_REG_SET *live_regs_mask)
5880 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
5883 /* Decide how much space to reserve for callee-save target registers
5884 in case target register allocation wants to use them.
5885 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5888 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
5890 if (shmedia_space_reserved_for_target_registers)
5891 return shmedia_target_regs_stack_space (live_regs_mask);
5896 /* Work out the registers which need to be saved, both as a mask and a
5897 count of saved words. Return the count.
5899 If doing a pragma interrupt function, then push all regs used by the
5900 function, and if we call another function (we can tell by looking at PR),
5901 make sure that all the regs it clobbers are safe too. */
5904 calc_live_regs (HARD_REG_SET *live_regs_mask)
5909 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
5910 bool nosave_low_regs;
5911 int pr_live, has_call;
5913 attrs = DECL_ATTRIBUTES (current_function_decl);
5914 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
5915 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
5916 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
5917 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
5919 CLEAR_HARD_REG_SET (*live_regs_mask);
5920 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
5921 && df_regs_ever_live_p (FPSCR_REG))
5922 target_flags &= ~MASK_FPU_SINGLE;
5923 /* If we can save a lot of saves by switching to double mode, do that. */
5924 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
5925 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
5926 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
5927 && (! call_really_used_regs[reg]
5928 || interrupt_handler)
5931 target_flags &= ~MASK_FPU_SINGLE;
5934 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
5935 knows how to use it. That means the pseudo originally allocated for
5936 the initial value can become the PR_MEDIA_REG hard register, as seen for
5937 execute/20010122-1.c:test9. */
5939 /* ??? this function is called from initial_elimination_offset, hence we
5940 can't use the result of sh_media_register_for_return here. */
5941 pr_live = sh_pr_n_sets ();
5944 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
5945 pr_live = (pr_initial
5946 ? (GET_CODE (pr_initial) != REG
5947 || REGNO (pr_initial) != (PR_REG))
5948 : df_regs_ever_live_p (PR_REG));
5949 /* For Shcompact, if not optimizing, we end up with a memory reference
5950 using the return address pointer for __builtin_return_address even
5951 though there is no actual need to put the PR register on the stack. */
5952 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
5954 /* Force PR to be live if the prologue has to call the SHmedia
5955 argument decoder or register saver. */
5956 if (TARGET_SHCOMPACT
5957 && ((current_function_args_info.call_cookie
5958 & ~ CALL_COOKIE_RET_TRAMP (1))
5959 || current_function_saves_all_registers))
5961 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
5962 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
5964 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
5967 ? (/* Need to save all the regs ever live. */
5968 (df_regs_ever_live_p (reg)
5969 || (call_really_used_regs[reg]
5970 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
5971 || reg == PIC_OFFSET_TABLE_REGNUM)
5973 || (TARGET_SHMEDIA && has_call
5974 && REGISTER_NATURAL_MODE (reg) == SImode
5975 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
5976 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
5977 && reg != RETURN_ADDRESS_POINTER_REGNUM
5978 && reg != T_REG && reg != GBR_REG
5979 /* Push fpscr only on targets which have FPU */
5980 && (reg != FPSCR_REG || TARGET_FPU_ANY))
5981 : (/* Only push those regs which are used and need to be saved. */
5984 && current_function_args_info.call_cookie
5985 && reg == PIC_OFFSET_TABLE_REGNUM)
5986 || (df_regs_ever_live_p (reg)
5987 && (!call_really_used_regs[reg]
5988 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
5989 || (current_function_calls_eh_return
5990 && (reg == EH_RETURN_DATA_REGNO (0)
5991 || reg == EH_RETURN_DATA_REGNO (1)
5992 || reg == EH_RETURN_DATA_REGNO (2)
5993 || reg == EH_RETURN_DATA_REGNO (3)))
5994 || ((reg == MACL_REG || reg == MACH_REG)
5995 && df_regs_ever_live_p (reg)
5996 && sh_cfun_attr_renesas_p ())
5999 SET_HARD_REG_BIT (*live_regs_mask, reg);
6000 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6002 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6003 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6005 if (FP_REGISTER_P (reg))
6007 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6009 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6010 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6013 else if (XD_REGISTER_P (reg))
6015 /* Must switch to double mode to access these registers. */
6016 target_flags &= ~MASK_FPU_SINGLE;
6020 if (nosave_low_regs && reg == R8_REG)
6023 /* If we have a target register optimization pass after prologue / epilogue
6024 threading, we need to assume all target registers will be live even if
6026 if (flag_branch_target_load_optimize2
6027 && TARGET_SAVE_ALL_TARGET_REGS
6028 && shmedia_space_reserved_for_target_registers)
6029 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6030 if ((! call_really_used_regs[reg] || interrupt_handler)
6031 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6033 SET_HARD_REG_BIT (*live_regs_mask, reg);
6034 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6036 /* If this is an interrupt handler, we don't have any call-clobbered
6037 registers we can conveniently use for target register save/restore.
6038 Make sure we save at least one general purpose register when we need
6039 to save target registers. */
6040 if (interrupt_handler
6041 && hard_reg_set_intersect_p (*live_regs_mask,
6042 reg_class_contents[TARGET_REGS])
6043 && ! hard_reg_set_intersect_p (*live_regs_mask,
6044 reg_class_contents[GENERAL_REGS]))
6046 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6047 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6053 /* Code to generate prologue and epilogue sequences */
6055 /* PUSHED is the number of bytes that are being pushed on the
6056 stack for register saves. Return the frame size, padded
6057 appropriately so that the stack stays properly aligned. */
6058 static HOST_WIDE_INT
6059 rounded_frame_size (int pushed)
6061 HOST_WIDE_INT size = get_frame_size ();
6062 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6064 return ((size + pushed + align - 1) & -align) - pushed;
6067 /* Choose a call-clobbered target-branch register that remains
6068 unchanged along the whole function. We set it up as the return
6069 value in the prologue. */
6071 sh_media_register_for_return (void)
6076 if (! current_function_is_leaf)
6078 if (lookup_attribute ("interrupt_handler",
6079 DECL_ATTRIBUTES (current_function_decl)))
6081 if (sh_cfun_interrupt_handler_p ())
6084 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6086 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6087 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6093 /* The maximum registers we need to save are:
6094 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6095 - 32 floating point registers (for each pair, we save none,
6096 one single precision value, or a double precision value).
6097 - 8 target registers
6098 - add 1 entry for a delimiter. */
6099 #define MAX_SAVED_REGS (62+32+8)
6101 typedef struct save_entry_s
6110 /* There will be a delimiter entry with VOIDmode both at the start and the
6111 end of a filled in schedule. The end delimiter has the offset of the
6112 save with the smallest (i.e. most negative) offset. */
6113 typedef struct save_schedule_s
6115 save_entry entries[MAX_SAVED_REGS + 2];
6116 int temps[MAX_TEMPS+1];
6119 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6120 use reverse order. Returns the last entry written to (not counting
6121 the delimiter). OFFSET_BASE is a number to be added to all offset
6125 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6129 save_entry *entry = schedule->entries;
6133 if (! current_function_interrupt)
6134 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6135 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6136 && ! FUNCTION_ARG_REGNO_P (i)
6137 && i != FIRST_RET_REG
6138 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6139 && ! (current_function_calls_eh_return
6140 && (i == EH_RETURN_STACKADJ_REGNO
6141 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6142 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6143 schedule->temps[tmpx++] = i;
6145 entry->mode = VOIDmode;
6146 entry->offset = offset_base;
6148 /* We loop twice: first, we save 8-byte aligned registers in the
6149 higher addresses, that are known to be aligned. Then, we
6150 proceed to saving 32-bit registers that don't need 8-byte
6152 If this is an interrupt function, all registers that need saving
6153 need to be saved in full. moreover, we need to postpone saving
6154 target registers till we have saved some general purpose registers
6155 we can then use as scratch registers. */
6156 offset = offset_base;
6157 for (align = 1; align >= 0; align--)
6159 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6160 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6162 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6165 if (current_function_interrupt)
6167 if (TARGET_REGISTER_P (i))
6169 if (GENERAL_REGISTER_P (i))
6172 if (mode == SFmode && (i % 2) == 1
6173 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6174 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6181 /* If we're doing the aligned pass and this is not aligned,
6182 or we're doing the unaligned pass and this is aligned,
6184 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6188 if (current_function_interrupt
6189 && GENERAL_REGISTER_P (i)
6190 && tmpx < MAX_TEMPS)
6191 schedule->temps[tmpx++] = i;
6193 offset -= GET_MODE_SIZE (mode);
6196 entry->offset = offset;
6199 if (align && current_function_interrupt)
6200 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6201 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6203 offset -= GET_MODE_SIZE (DImode);
6205 entry->mode = DImode;
6206 entry->offset = offset;
6211 entry->mode = VOIDmode;
6212 entry->offset = offset;
6213 schedule->temps[tmpx] = -1;
6218 sh_expand_prologue (void)
6220 HARD_REG_SET live_regs_mask;
6223 int save_flags = target_flags;
6226 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6228 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6230 /* We have pretend args if we had an object sent partially in registers
6231 and partially on the stack, e.g. a large structure. */
6232 pretend_args = current_function_pretend_args_size;
6233 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6234 && (NPARM_REGS(SImode)
6235 > current_function_args_info.arg_count[(int) SH_ARG_INT]))
6237 output_stack_adjust (-pretend_args
6238 - current_function_args_info.stack_regs * 8,
6239 stack_pointer_rtx, 0, NULL);
6241 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
6242 /* We're going to use the PIC register to load the address of the
6243 incoming-argument decoder and/or of the return trampoline from
6244 the GOT, so make sure the PIC register is preserved and
6246 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6248 if (TARGET_SHCOMPACT
6249 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6253 /* First, make all registers with incoming arguments that will
6254 be pushed onto the stack live, so that register renaming
6255 doesn't overwrite them. */
6256 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6257 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
6258 >= NPARM_REGS (SImode) - reg)
6259 for (; reg < NPARM_REGS (SImode); reg++)
6260 emit_insn (gen_shcompact_preserve_incoming_args
6261 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6262 else if (CALL_COOKIE_INT_REG_GET
6263 (current_function_args_info.call_cookie, reg) == 1)
6264 emit_insn (gen_shcompact_preserve_incoming_args
6265 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6267 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6269 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6270 GEN_INT (current_function_args_info.call_cookie));
6271 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6272 gen_rtx_REG (SImode, R0_REG));
6274 else if (TARGET_SHMEDIA)
6276 int tr = sh_media_register_for_return ();
6279 emit_move_insn (gen_rtx_REG (DImode, tr),
6280 gen_rtx_REG (DImode, PR_MEDIA_REG));
6283 /* Emit the code for SETUP_VARARGS. */
6284 if (current_function_stdarg)
6286 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6288 /* Push arg regs as if they'd been provided by caller in stack. */
6289 for (i = 0; i < NPARM_REGS(SImode); i++)
6291 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6294 if (i >= (NPARM_REGS(SImode)
6295 - current_function_args_info.arg_count[(int) SH_ARG_INT]
6299 RTX_FRAME_RELATED_P (insn) = 0;
6304 /* If we're supposed to switch stacks at function entry, do so now. */
6307 /* The argument specifies a variable holding the address of the
6308 stack the interrupt function should switch to/from at entry/exit. */
6310 = ggc_strdup (TREE_STRING_POINTER (TREE_VALUE (sp_switch_attr)));
6311 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6313 emit_insn (gen_sp_switch_1 (sp_switch));
6316 d = calc_live_regs (&live_regs_mask);
6317 /* ??? Maybe we could save some switching if we can move a mode switch
6318 that already happens to be at the function start into the prologue. */
6319 if (target_flags != save_flags && ! current_function_interrupt)
6320 emit_insn (gen_toggle_sz ());
6324 int offset_base, offset;
6326 int offset_in_r0 = -1;
6328 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6329 int total_size, save_size;
6330 save_schedule schedule;
6334 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6335 && ! current_function_interrupt)
6336 r0 = gen_rtx_REG (Pmode, R0_REG);
6338 /* D is the actual number of bytes that we need for saving registers,
6339 however, in initial_elimination_offset we have committed to using
6340 an additional TREGS_SPACE amount of bytes - in order to keep both
6341 addresses to arguments supplied by the caller and local variables
6342 valid, we must keep this gap. Place it between the incoming
6343 arguments and the actually saved registers in a bid to optimize
6344 locality of reference. */
6345 total_size = d + tregs_space;
6346 total_size += rounded_frame_size (total_size);
6347 save_size = total_size - rounded_frame_size (d);
6348 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6349 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6350 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6352 /* If adjusting the stack in a single step costs nothing extra, do so.
6353 I.e. either if a single addi is enough, or we need a movi anyway,
6354 and we don't exceed the maximum offset range (the test for the
6355 latter is conservative for simplicity). */
6357 && (CONST_OK_FOR_I10 (-total_size)
6358 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6359 && total_size <= 2044)))
6360 d_rounding = total_size - save_size;
6362 offset_base = d + d_rounding;
6364 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6367 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6368 tmp_pnt = schedule.temps;
6369 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6371 enum machine_mode mode = entry->mode;
6372 unsigned int reg = entry->reg;
6373 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6376 offset = entry->offset;
6378 reg_rtx = gen_rtx_REG (mode, reg);
6380 mem_rtx = gen_frame_mem (mode,
6381 gen_rtx_PLUS (Pmode,
6385 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
6392 if (HAVE_PRE_DECREMENT
6393 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6394 || mem_rtx == NULL_RTX
6395 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6397 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6399 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
6408 offset += GET_MODE_SIZE (mode);
6412 if (mem_rtx != NULL_RTX)
6415 if (offset_in_r0 == -1)
6417 emit_move_insn (r0, GEN_INT (offset));
6418 offset_in_r0 = offset;
6420 else if (offset != offset_in_r0)
6425 GEN_INT (offset - offset_in_r0)));
6426 offset_in_r0 += offset - offset_in_r0;
6429 if (pre_dec != NULL_RTX)
6435 (Pmode, r0, stack_pointer_rtx));
6439 offset -= GET_MODE_SIZE (mode);
6440 offset_in_r0 -= GET_MODE_SIZE (mode);
6445 mem_rtx = gen_frame_mem (mode, r0);
6447 mem_rtx = gen_frame_mem (mode,
6448 gen_rtx_PLUS (Pmode,
6452 /* We must not use an r0-based address for target-branch
6453 registers or for special registers without pre-dec
6454 memory addresses, since we store their values in r0
6456 gcc_assert (!TARGET_REGISTER_P (reg)
6457 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6458 || mem_rtx == pre_dec));
6461 orig_reg_rtx = reg_rtx;
6462 if (TARGET_REGISTER_P (reg)
6463 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6464 && mem_rtx != pre_dec))
6466 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6468 emit_move_insn (tmp_reg, reg_rtx);
6470 if (REGNO (tmp_reg) == R0_REG)
6474 gcc_assert (!refers_to_regno_p
6475 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6478 if (*++tmp_pnt <= 0)
6479 tmp_pnt = schedule.temps;
6486 /* Mark as interesting for dwarf cfi generator */
6487 insn = emit_move_insn (mem_rtx, reg_rtx);
6488 RTX_FRAME_RELATED_P (insn) = 1;
6489 /* If we use an intermediate register for the save, we can't
6490 describe this exactly in cfi as a copy of the to-be-saved
6491 register into the temporary register and then the temporary
6492 register on the stack, because the temporary register can
6493 have a different natural size than the to-be-saved register.
6494 Thus, we gloss over the intermediate copy and pretend we do
6495 a direct save from the to-be-saved register. */
6496 if (REGNO (reg_rtx) != reg)
6500 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6501 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
6503 REG_NOTES (insn) = note_rtx;
6506 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6508 rtx reg_rtx = gen_rtx_REG (mode, reg);
6510 rtx mem_rtx = gen_frame_mem (mode,
6511 gen_rtx_PLUS (Pmode,
6515 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6516 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
6518 REG_NOTES (insn) = note_rtx;
6523 gcc_assert (entry->offset == d_rounding);
6526 push_regs (&live_regs_mask, current_function_interrupt);
6528 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
6529 emit_insn (gen_GOTaddr2picreg ());
6531 if (SHMEDIA_REGS_STACK_ADJUST ())
6533 /* This must NOT go through the PLT, otherwise mach and macl
6534 may be clobbered. */
6535 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6537 ? "__GCC_push_shmedia_regs"
6538 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
6539 emit_insn (gen_shmedia_save_restore_regs_compact
6540 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
6543 if (target_flags != save_flags && ! current_function_interrupt)
6544 emit_insn (gen_toggle_sz ());
6546 target_flags = save_flags;
6548 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
6549 stack_pointer_rtx, 0, NULL);
6551 if (frame_pointer_needed)
6552 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
6554 if (TARGET_SHCOMPACT
6555 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6557 /* This must NOT go through the PLT, otherwise mach and macl
6558 may be clobbered. */
6559 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6560 "__GCC_shcompact_incoming_args", SFUNC_GOT);
6561 emit_insn (gen_shcompact_incoming_args ());
6566 sh_expand_epilogue (bool sibcall_p)
6568 HARD_REG_SET live_regs_mask;
6572 int save_flags = target_flags;
6573 int frame_size, save_size;
6574 int fpscr_deferred = 0;
6575 int e = sibcall_p ? -1 : 1;
6577 d = calc_live_regs (&live_regs_mask);
6580 frame_size = rounded_frame_size (d);
6584 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6586 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
6587 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6588 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
6590 total_size = d + tregs_space;
6591 total_size += rounded_frame_size (total_size);
6592 save_size = total_size - frame_size;
6594 /* If adjusting the stack in a single step costs nothing extra, do so.
6595 I.e. either if a single addi is enough, or we need a movi anyway,
6596 and we don't exceed the maximum offset range (the test for the
6597 latter is conservative for simplicity). */
6599 && ! frame_pointer_needed
6600 && (CONST_OK_FOR_I10 (total_size)
6601 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
6602 && total_size <= 2044)))
6603 d_rounding = frame_size;
6605 frame_size -= d_rounding;
6608 if (frame_pointer_needed)
6610 /* We must avoid scheduling the epilogue with previous basic blocks
6611 when exception handling is enabled. See PR/18032. */
6612 if (flag_exceptions)
6613 emit_insn (gen_blockage ());
6614 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
6617 /* We must avoid moving the stack pointer adjustment past code
6618 which reads from the local frame, else an interrupt could
6619 occur after the SP adjustment and clobber data in the local
6621 emit_insn (gen_blockage ());
6622 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
6624 else if (frame_size)
6626 /* We must avoid moving the stack pointer adjustment past code
6627 which reads from the local frame, else an interrupt could
6628 occur after the SP adjustment and clobber data in the local
6630 emit_insn (gen_blockage ());
6631 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
6634 if (SHMEDIA_REGS_STACK_ADJUST ())
6636 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6638 ? "__GCC_pop_shmedia_regs"
6639 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
6640 /* This must NOT go through the PLT, otherwise mach and macl
6641 may be clobbered. */
6642 emit_insn (gen_shmedia_save_restore_regs_compact
6643 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
6646 /* Pop all the registers. */
6648 if (target_flags != save_flags && ! current_function_interrupt)
6649 emit_insn (gen_toggle_sz ());
6652 int offset_base, offset;
6653 int offset_in_r0 = -1;
6655 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
6656 save_schedule schedule;
6660 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
6661 offset_base = -entry[1].offset + d_rounding;
6662 tmp_pnt = schedule.temps;
6663 for (; entry->mode != VOIDmode; entry--)
6665 enum machine_mode mode = entry->mode;
6666 int reg = entry->reg;
6667 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
6669 offset = offset_base + entry->offset;
6670 reg_rtx = gen_rtx_REG (mode, reg);
6672 mem_rtx = gen_frame_mem (mode,
6673 gen_rtx_PLUS (Pmode,
6677 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
6683 if (HAVE_POST_INCREMENT
6684 && (offset == offset_in_r0
6685 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
6686 && mem_rtx == NULL_RTX)
6687 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6689 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
6691 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
6694 post_inc = NULL_RTX;
6703 if (mem_rtx != NULL_RTX)
6706 if (offset_in_r0 == -1)
6708 emit_move_insn (r0, GEN_INT (offset));
6709 offset_in_r0 = offset;
6711 else if (offset != offset_in_r0)
6716 GEN_INT (offset - offset_in_r0)));
6717 offset_in_r0 += offset - offset_in_r0;
6720 if (post_inc != NULL_RTX)
6726 (Pmode, r0, stack_pointer_rtx));
6732 offset_in_r0 += GET_MODE_SIZE (mode);
6735 mem_rtx = gen_frame_mem (mode, r0);
6737 mem_rtx = gen_frame_mem (mode,
6738 gen_rtx_PLUS (Pmode,
6742 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6743 || mem_rtx == post_inc);
6746 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6747 && mem_rtx != post_inc)
6749 insn = emit_move_insn (r0, mem_rtx);
6752 else if (TARGET_REGISTER_P (reg))
6754 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
6756 /* Give the scheduler a bit of freedom by using up to
6757 MAX_TEMPS registers in a round-robin fashion. */
6758 insn = emit_move_insn (tmp_reg, mem_rtx);
6761 tmp_pnt = schedule.temps;
6764 insn = emit_move_insn (reg_rtx, mem_rtx);
6767 gcc_assert (entry->offset + offset_base == d + d_rounding);
6769 else /* ! TARGET_SH5 */
6774 /* For an ISR with RESBANK attribute assigned, don't pop PR
6776 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
6777 && !sh_cfun_resbank_handler_p ())
6779 if (!frame_pointer_needed)
6780 emit_insn (gen_blockage ());
6784 /* Banked registers are poped first to avoid being scheduled in the
6785 delay slot. RTE switches banks before the ds instruction. */
6786 if (current_function_interrupt)
6788 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6789 if (TEST_HARD_REG_BIT (live_regs_mask, i))
6790 pop (LAST_BANKED_REG - i);
6792 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
6795 last_reg = FIRST_PSEUDO_REGISTER;
6797 for (i = 0; i < last_reg; i++)
6799 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
6801 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
6802 && hard_reg_set_intersect_p (live_regs_mask,
6803 reg_class_contents[DF_REGS]))
6805 /* For an ISR with RESBANK attribute assigned, don't pop
6806 following registers, R0-R14, MACH, MACL and GBR. */
6807 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
6808 && ! (sh_cfun_resbank_handler_p ()
6809 && ((j >= FIRST_GENERAL_REG
6810 && j < LAST_GENERAL_REG)
6816 if (j == FIRST_FP_REG && fpscr_deferred)
6820 if (target_flags != save_flags && ! current_function_interrupt)
6821 emit_insn (gen_toggle_sz ());
6822 target_flags = save_flags;
6824 output_stack_adjust (current_function_pretend_args_size
6825 + save_size + d_rounding
6826 + current_function_args_info.stack_regs * 8,
6827 stack_pointer_rtx, e, NULL);
6829 if (current_function_calls_eh_return)
6830 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
6831 EH_RETURN_STACKADJ_RTX));
6833 /* Switch back to the normal stack if necessary. */
6834 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
6835 emit_insn (gen_sp_switch_2 ());
6837 /* Tell flow the insn that pops PR isn't dead. */
6838 /* PR_REG will never be live in SHmedia mode, and we don't need to
6839 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
6840 by the return pattern. */
6841 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
6842 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
6845 static int sh_need_epilogue_known = 0;
6848 sh_need_epilogue (void)
6850 if (! sh_need_epilogue_known)
6855 sh_expand_epilogue (0);
6856 epilogue = get_insns ();
6858 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
6860 return sh_need_epilogue_known > 0;
6863 /* Emit code to change the current function's return address to RA.
6864 TEMP is available as a scratch register, if needed. */
6867 sh_set_return_address (rtx ra, rtx tmp)
6869 HARD_REG_SET live_regs_mask;
6871 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
6874 d = calc_live_regs (&live_regs_mask);
6876 /* If pr_reg isn't life, we can set it (or the register given in
6877 sh_media_register_for_return) directly. */
6878 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
6884 int rr_regno = sh_media_register_for_return ();
6889 rr = gen_rtx_REG (DImode, rr_regno);
6892 rr = gen_rtx_REG (SImode, pr_reg);
6894 emit_insn (GEN_MOV (rr, ra));
6895 /* Tell flow the register for return isn't dead. */
6896 emit_insn (gen_rtx_USE (VOIDmode, rr));
6903 save_schedule schedule;
6906 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
6907 offset = entry[1].offset;
6908 for (; entry->mode != VOIDmode; entry--)
6909 if (entry->reg == pr_reg)
6912 /* We can't find pr register. */
6916 offset = entry->offset - offset;
6917 pr_offset = (rounded_frame_size (d) + offset
6918 + SHMEDIA_REGS_STACK_ADJUST ());
6921 pr_offset = rounded_frame_size (d);
6923 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
6924 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
6926 tmp = gen_frame_mem (Pmode, tmp);
6927 emit_insn (GEN_MOV (tmp, ra));
6930 /* Clear variables at function end. */
6933 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6934 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6936 sh_need_epilogue_known = 0;
6940 sh_builtin_saveregs (void)
6942 /* First unnamed integer register. */
6943 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
6944 /* Number of integer registers we need to save. */
6945 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
6946 /* First unnamed SFmode float reg */
6947 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
6948 /* Number of SFmode float regs to save. */
6949 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
6952 alias_set_type alias_set;
6958 int pushregs = n_intregs;
6960 while (pushregs < NPARM_REGS (SImode) - 1
6961 && (CALL_COOKIE_INT_REG_GET
6962 (current_function_args_info.call_cookie,
6963 NPARM_REGS (SImode) - pushregs)
6966 current_function_args_info.call_cookie
6967 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
6972 if (pushregs == NPARM_REGS (SImode))
6973 current_function_args_info.call_cookie
6974 |= (CALL_COOKIE_INT_REG (0, 1)
6975 | CALL_COOKIE_STACKSEQ (pushregs - 1));
6977 current_function_args_info.call_cookie
6978 |= CALL_COOKIE_STACKSEQ (pushregs);
6980 current_function_pretend_args_size += 8 * n_intregs;
6982 if (TARGET_SHCOMPACT)
6986 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
6988 error ("__builtin_saveregs not supported by this subtarget");
6995 /* Allocate block of memory for the regs. */
6996 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
6997 Or can assign_stack_local accept a 0 SIZE argument? */
6998 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7001 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7002 else if (n_floatregs & 1)
7006 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7007 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7008 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7009 regbuf = change_address (regbuf, BLKmode, addr);
7011 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7015 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7016 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7017 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7018 emit_insn (gen_andsi3 (addr, addr, mask));
7019 regbuf = change_address (regbuf, BLKmode, addr);
7022 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7023 alias_set = get_varargs_alias_set ();
7024 set_mem_alias_set (regbuf, alias_set);
7027 This is optimized to only save the regs that are necessary. Explicitly
7028 named args need not be saved. */
7030 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7031 adjust_address (regbuf, BLKmode,
7032 n_floatregs * UNITS_PER_WORD),
7036 /* Return the address of the regbuf. */
7037 return XEXP (regbuf, 0);
7040 This is optimized to only save the regs that are necessary. Explicitly
7041 named args need not be saved.
7042 We explicitly build a pointer to the buffer because it halves the insn
7043 count when not optimizing (otherwise the pointer is built for each reg
7045 We emit the moves in reverse order so that we can use predecrement. */
7047 fpregs = copy_to_mode_reg (Pmode,
7048 plus_constant (XEXP (regbuf, 0),
7049 n_floatregs * UNITS_PER_WORD));
7050 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7053 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7055 emit_insn (gen_addsi3 (fpregs, fpregs,
7056 GEN_INT (-2 * UNITS_PER_WORD)));
7057 mem = change_address (regbuf, DFmode, fpregs);
7058 emit_move_insn (mem,
7059 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7061 regno = first_floatreg;
7064 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7065 mem = change_address (regbuf, SFmode, fpregs);
7066 emit_move_insn (mem,
7067 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7068 - (TARGET_LITTLE_ENDIAN != 0)));
7072 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7076 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7077 mem = change_address (regbuf, SFmode, fpregs);
7078 emit_move_insn (mem,
7079 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7082 /* Return the address of the regbuf. */
7083 return XEXP (regbuf, 0);
7086 /* Define the `__builtin_va_list' type for the ABI. */
7089 sh_build_builtin_va_list (void)
7091 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7094 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7095 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7096 return ptr_type_node;
7098 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7100 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
7102 f_next_o_limit = build_decl (FIELD_DECL,
7103 get_identifier ("__va_next_o_limit"),
7105 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
7107 f_next_fp_limit = build_decl (FIELD_DECL,
7108 get_identifier ("__va_next_fp_limit"),
7110 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
7113 DECL_FIELD_CONTEXT (f_next_o) = record;
7114 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7115 DECL_FIELD_CONTEXT (f_next_fp) = record;
7116 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7117 DECL_FIELD_CONTEXT (f_next_stack) = record;
7119 TYPE_FIELDS (record) = f_next_o;
7120 TREE_CHAIN (f_next_o) = f_next_o_limit;
7121 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7122 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7123 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7125 layout_type (record);
7130 /* Implement `va_start' for varargs and stdarg. */
7133 sh_va_start (tree valist, rtx nextarg)
7135 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7136 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7142 expand_builtin_saveregs ();
7143 std_expand_builtin_va_start (valist, nextarg);
7147 if ((! TARGET_SH2E && ! TARGET_SH4)
7148 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7150 std_expand_builtin_va_start (valist, nextarg);
7154 f_next_o = TYPE_FIELDS (va_list_type_node);
7155 f_next_o_limit = TREE_CHAIN (f_next_o);
7156 f_next_fp = TREE_CHAIN (f_next_o_limit);
7157 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7158 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7160 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7162 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7163 valist, f_next_o_limit, NULL_TREE);
7164 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7166 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7167 valist, f_next_fp_limit, NULL_TREE);
7168 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7169 valist, f_next_stack, NULL_TREE);
7171 /* Call __builtin_saveregs. */
7172 u = make_tree (sizetype, expand_builtin_saveregs ());
7173 u = fold_convert (ptr_type_node, u);
7174 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_fp, u);
7175 TREE_SIDE_EFFECTS (t) = 1;
7176 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7178 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
7183 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7184 size_int (UNITS_PER_WORD * nfp));
7185 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_fp_limit, u);
7186 TREE_SIDE_EFFECTS (t) = 1;
7187 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7189 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_o, u);
7190 TREE_SIDE_EFFECTS (t) = 1;
7191 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7193 nint = current_function_args_info.arg_count[SH_ARG_INT];
7198 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7199 size_int (UNITS_PER_WORD * nint));
7200 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_o_limit, u);
7201 TREE_SIDE_EFFECTS (t) = 1;
7202 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7204 u = make_tree (ptr_type_node, nextarg);
7205 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_stack, u);
7206 TREE_SIDE_EFFECTS (t) = 1;
7207 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7210 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7211 member, return it. */
7213 find_sole_member (tree type)
7215 tree field, member = NULL_TREE;
7217 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7219 if (TREE_CODE (field) != FIELD_DECL)
7221 if (!DECL_SIZE (field))
7223 if (integer_zerop (DECL_SIZE (field)))
7231 /* Implement `va_arg'. */
7234 sh_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p,
7235 tree *post_p ATTRIBUTE_UNUSED)
7237 HOST_WIDE_INT size, rsize;
7238 tree tmp, pptr_type_node;
7239 tree addr, lab_over = NULL, result = NULL;
7240 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7244 type = build_pointer_type (type);
7246 size = int_size_in_bytes (type);
7247 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7248 pptr_type_node = build_pointer_type (ptr_type_node);
7250 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7251 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7253 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7254 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7259 f_next_o = TYPE_FIELDS (va_list_type_node);
7260 f_next_o_limit = TREE_CHAIN (f_next_o);
7261 f_next_fp = TREE_CHAIN (f_next_o_limit);
7262 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7263 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7265 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7267 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7268 valist, f_next_o_limit, NULL_TREE);
7269 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7270 valist, f_next_fp, NULL_TREE);
7271 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7272 valist, f_next_fp_limit, NULL_TREE);
7273 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7274 valist, f_next_stack, NULL_TREE);
7276 /* Structures with a single member with a distinct mode are passed
7277 like their member. This is relevant if the latter has a REAL_TYPE
7278 or COMPLEX_TYPE type. */
7280 while (TREE_CODE (eff_type) == RECORD_TYPE
7281 && (member = find_sole_member (eff_type))
7282 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7283 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7284 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7286 tree field_type = TREE_TYPE (member);
7288 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7289 eff_type = field_type;
7292 gcc_assert ((TYPE_ALIGN (eff_type)
7293 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7294 || (TYPE_ALIGN (eff_type)
7295 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7300 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7302 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7303 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7304 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7309 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7312 addr = create_tmp_var (pptr_type_node, NULL);
7313 lab_false = create_artificial_label ();
7314 lab_over = create_artificial_label ();
7316 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7320 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7322 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7324 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
7325 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, tmp);
7326 gimplify_and_add (tmp, pre_p);
7328 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_fp_tmp, valist);
7329 gimplify_and_add (tmp, pre_p);
7330 tmp = next_fp_limit;
7331 if (size > 4 && !is_double)
7332 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp), tmp,
7333 size_int (4 - size));
7334 tmp = build2 (GE_EXPR, boolean_type_node, next_fp_tmp, tmp);
7335 cmp = build3 (COND_EXPR, void_type_node, tmp,
7336 build1 (GOTO_EXPR, void_type_node, lab_false),
7339 gimplify_and_add (cmp, pre_p);
7341 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7342 || (is_double || size == 16))
7344 tmp = fold_convert (sizetype, next_fp_tmp);
7345 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7346 size_int (UNITS_PER_WORD));
7347 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7349 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node,
7351 gimplify_and_add (tmp, pre_p);
7354 gimplify_and_add (cmp, pre_p);
7356 #ifdef FUNCTION_ARG_SCmode_WART
7357 if (TYPE_MODE (eff_type) == SCmode
7358 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7360 tree subtype = TREE_TYPE (eff_type);
7364 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7365 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7368 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7369 real = get_initialized_tmp_var (real, pre_p, NULL);
7371 result = build2 (COMPLEX_EXPR, type, real, imag);
7372 result = get_initialized_tmp_var (result, pre_p, NULL);
7374 #endif /* FUNCTION_ARG_SCmode_WART */
7376 tmp = build1 (GOTO_EXPR, void_type_node, lab_over);
7377 gimplify_and_add (tmp, pre_p);
7379 tmp = build1 (LABEL_EXPR, void_type_node, lab_false);
7380 gimplify_and_add (tmp, pre_p);
7382 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
7383 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, tmp);
7384 gimplify_and_add (tmp, pre_p);
7385 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_fp_tmp, valist);
7386 gimplify_and_add (tmp, pre_p);
7388 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, valist, next_fp_tmp);
7389 gimplify_and_add (tmp, post_p);
7390 valist = next_fp_tmp;
7394 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node, next_o,
7396 tmp = build2 (GT_EXPR, boolean_type_node, tmp, next_o_limit);
7397 tmp = build3 (COND_EXPR, void_type_node, tmp,
7398 build1 (GOTO_EXPR, void_type_node, lab_false),
7400 gimplify_and_add (tmp, pre_p);
7402 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
7403 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, tmp);
7404 gimplify_and_add (tmp, pre_p);
7406 tmp = build1 (GOTO_EXPR, void_type_node, lab_over);
7407 gimplify_and_add (tmp, pre_p);
7409 tmp = build1 (LABEL_EXPR, void_type_node, lab_false);
7410 gimplify_and_add (tmp, pre_p);
7412 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7414 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node,
7415 next_o, next_o_limit);
7416 gimplify_and_add (tmp, pre_p);
7419 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
7420 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, tmp);
7421 gimplify_and_add (tmp, pre_p);
7426 tmp = build1 (LABEL_EXPR, void_type_node, lab_over);
7427 gimplify_and_add (tmp, pre_p);
7431 /* ??? In va-sh.h, there had been code to make values larger than
7432 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7434 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7437 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, result, tmp);
7438 gimplify_and_add (tmp, pre_p);
7440 tmp = build1 (LABEL_EXPR, void_type_node, lab_over);
7441 gimplify_and_add (tmp, pre_p);
7447 result = build_va_arg_indirect_ref (result);
7453 sh_promote_prototypes (const_tree type)
7459 return ! sh_attr_renesas_p (type);
7462 /* Whether an argument must be passed by reference. On SHcompact, we
7463 pretend arguments wider than 32-bits that would have been passed in
7464 registers are passed by reference, so that an SHmedia trampoline
7465 loads them into the full 64-bits registers. */
7468 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7469 const_tree type, bool named)
7471 unsigned HOST_WIDE_INT size;
7474 size = int_size_in_bytes (type);
7476 size = GET_MODE_SIZE (mode);
7478 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7480 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7481 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7482 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7484 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7485 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7492 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7493 const_tree type, bool named)
7495 if (targetm.calls.must_pass_in_stack (mode, type))
7498 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7499 wants to know about pass-by-reference semantics for incoming
7504 if (TARGET_SHCOMPACT)
7506 cum->byref = shcompact_byref (cum, mode, type, named);
7507 return cum->byref != 0;
7514 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7515 const_tree type, bool named ATTRIBUTE_UNUSED)
7517 /* ??? How can it possibly be correct to return true only on the
7518 caller side of the equation? Is there someplace else in the
7519 sh backend that's magically producing the copies? */
7520 return (cum->outgoing
7521 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7522 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7526 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7527 tree type, bool named ATTRIBUTE_UNUSED)
7532 && PASS_IN_REG_P (*cum, mode, type)
7533 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7534 && (ROUND_REG (*cum, mode)
7536 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7537 : ROUND_ADVANCE (int_size_in_bytes (type)))
7538 > NPARM_REGS (mode)))
7539 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
7541 else if (!TARGET_SHCOMPACT
7542 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7543 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
7545 return words * UNITS_PER_WORD;
7549 /* Define where to put the arguments to a function.
7550 Value is zero to push the argument on the stack,
7551 or a hard register in which to store the argument.
7553 MODE is the argument's machine mode.
7554 TYPE is the data type of the argument (as a tree).
7555 This is null for libcalls where that information may
7557 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7558 the preceding args and about the function being called.
7559 NAMED is nonzero if this argument is a named parameter
7560 (otherwise it is an extra parameter matching an ellipsis).
7562 On SH the first args are normally in registers
7563 and the rest are pushed. Any arg that starts within the first
7564 NPARM_REGS words is at least partially passed in a register unless
7565 its data type forbids. */
7569 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7570 tree type, int named)
7572 if (! TARGET_SH5 && mode == VOIDmode)
7573 return GEN_INT (ca->renesas_abi ? 1 : 0);
7576 && PASS_IN_REG_P (*ca, mode, type)
7577 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
7581 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
7582 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
7584 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
7585 gen_rtx_REG (SFmode,
7587 + (ROUND_REG (*ca, mode) ^ 1)),
7589 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
7590 gen_rtx_REG (SFmode,
7592 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
7594 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
7597 /* If the alignment of a DF value causes an SF register to be
7598 skipped, we will use that skipped register for the next SF
7600 if ((TARGET_HITACHI || ca->renesas_abi)
7601 && ca->free_single_fp_reg
7603 return gen_rtx_REG (mode, ca->free_single_fp_reg);
7605 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
7606 ^ (mode == SFmode && TARGET_SH4
7607 && TARGET_LITTLE_ENDIAN != 0
7608 && ! TARGET_HITACHI && ! ca->renesas_abi);
7609 return gen_rtx_REG (mode, regno);
7615 if (mode == VOIDmode && TARGET_SHCOMPACT)
7616 return GEN_INT (ca->call_cookie);
7618 /* The following test assumes unnamed arguments are promoted to
7620 if (mode == SFmode && ca->free_single_fp_reg)
7621 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
7623 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
7624 && (named || ! ca->prototype_p)
7625 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
7627 if (! ca->prototype_p && TARGET_SHMEDIA)
7628 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
7630 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
7632 + ca->arg_count[(int) SH_ARG_FLOAT]);
7635 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
7636 && (! TARGET_SHCOMPACT
7637 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
7638 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
7641 return gen_rtx_REG (mode, (FIRST_PARM_REG
7642 + ca->arg_count[(int) SH_ARG_INT]));
7651 /* Update the data in CUM to advance over an argument
7652 of mode MODE and data type TYPE.
7653 (TYPE is null for libcalls where that information may not be
7657 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7658 tree type, int named)
7662 else if (TARGET_SH5)
7664 tree type2 = (ca->byref && type
7667 enum machine_mode mode2 = (ca->byref && type
7670 int dwords = ((ca->byref
7673 ? int_size_in_bytes (type2)
7674 : GET_MODE_SIZE (mode2)) + 7) / 8;
7675 int numregs = MIN (dwords, NPARM_REGS (SImode)
7676 - ca->arg_count[(int) SH_ARG_INT]);
7680 ca->arg_count[(int) SH_ARG_INT] += numregs;
7681 if (TARGET_SHCOMPACT
7682 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
7685 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7687 /* N.B. We want this also for outgoing. */
7688 ca->stack_regs += numregs;
7693 ca->stack_regs += numregs;
7694 ca->byref_regs += numregs;
7698 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7702 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7705 else if (dwords > numregs)
7707 int pushregs = numregs;
7709 if (TARGET_SHCOMPACT)
7710 ca->stack_regs += numregs;
7711 while (pushregs < NPARM_REGS (SImode) - 1
7712 && (CALL_COOKIE_INT_REG_GET
7714 NPARM_REGS (SImode) - pushregs)
7718 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7722 if (numregs == NPARM_REGS (SImode))
7724 |= CALL_COOKIE_INT_REG (0, 1)
7725 | CALL_COOKIE_STACKSEQ (numregs - 1);
7728 |= CALL_COOKIE_STACKSEQ (numregs);
7731 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
7732 && (named || ! ca->prototype_p))
7734 if (mode2 == SFmode && ca->free_single_fp_reg)
7735 ca->free_single_fp_reg = 0;
7736 else if (ca->arg_count[(int) SH_ARG_FLOAT]
7737 < NPARM_REGS (SFmode))
7740 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
7742 - ca->arg_count[(int) SH_ARG_FLOAT]);
7744 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
7746 if (TARGET_SHCOMPACT && ! ca->prototype_p)
7748 if (ca->outgoing && numregs > 0)
7752 |= (CALL_COOKIE_INT_REG
7753 (ca->arg_count[(int) SH_ARG_INT]
7754 - numregs + ((numfpregs - 2) / 2),
7755 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
7758 while (numfpregs -= 2);
7760 else if (mode2 == SFmode && (named)
7761 && (ca->arg_count[(int) SH_ARG_FLOAT]
7762 < NPARM_REGS (SFmode)))
7763 ca->free_single_fp_reg
7764 = FIRST_FP_PARM_REG - numfpregs
7765 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
7771 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
7773 /* Note that we've used the skipped register. */
7774 if (mode == SFmode && ca->free_single_fp_reg)
7776 ca->free_single_fp_reg = 0;
7779 /* When we have a DF after an SF, there's an SF register that get
7780 skipped in order to align the DF value. We note this skipped
7781 register, because the next SF value will use it, and not the
7782 SF that follows the DF. */
7784 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
7786 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
7787 + BASE_ARG_REG (mode));
7791 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
7792 || PASS_IN_REG_P (*ca, mode, type))
7793 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
7794 = (ROUND_REG (*ca, mode)
7796 ? ROUND_ADVANCE (int_size_in_bytes (type))
7797 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
7800 /* The Renesas calling convention doesn't quite fit into this scheme since
7801 the address is passed like an invisible argument, but one that is always
7802 passed in memory. */
7804 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
7806 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7808 return gen_rtx_REG (Pmode, 2);
7811 /* Worker function for TARGET_RETURN_IN_MEMORY. */
7814 sh_return_in_memory (const_tree type, const_tree fndecl)
7818 if (TYPE_MODE (type) == BLKmode)
7819 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
7821 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
7825 return (TYPE_MODE (type) == BLKmode
7826 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7827 && TREE_CODE (type) == RECORD_TYPE));
7831 /* We actually emit the code in sh_expand_prologue. We used to use
7832 a static variable to flag that we need to emit this code, but that
7833 doesn't when inlining, when functions are deferred and then emitted
7834 later. Fortunately, we already have two flags that are part of struct
7835 function that tell if a function uses varargs or stdarg. */
7837 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
7838 enum machine_mode mode,
7840 int *pretend_arg_size,
7841 int second_time ATTRIBUTE_UNUSED)
7843 gcc_assert (current_function_stdarg);
7844 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
7846 int named_parm_regs, anon_parm_regs;
7848 named_parm_regs = (ROUND_REG (*ca, mode)
7850 ? ROUND_ADVANCE (int_size_in_bytes (type))
7851 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
7852 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
7853 if (anon_parm_regs > 0)
7854 *pretend_arg_size = anon_parm_regs * 4;
7859 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
7865 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
7867 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
7871 /* Define the offset between two registers, one to be eliminated, and
7872 the other its replacement, at the start of a routine. */
7875 initial_elimination_offset (int from, int to)
7878 int regs_saved_rounding = 0;
7879 int total_saved_regs_space;
7880 int total_auto_space;
7881 int save_flags = target_flags;
7883 HARD_REG_SET live_regs_mask;
7885 shmedia_space_reserved_for_target_registers = false;
7886 regs_saved = calc_live_regs (&live_regs_mask);
7887 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
7889 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
7891 shmedia_space_reserved_for_target_registers = true;
7892 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
7895 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
7896 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7897 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
7899 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
7900 copy_flags = target_flags;
7901 target_flags = save_flags;
7903 total_saved_regs_space = regs_saved + regs_saved_rounding;
7905 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7906 return total_saved_regs_space + total_auto_space
7907 + current_function_args_info.byref_regs * 8;
7909 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7910 return total_saved_regs_space + total_auto_space
7911 + current_function_args_info.byref_regs * 8;
7913 /* Initial gap between fp and sp is 0. */
7914 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7917 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7918 return rounded_frame_size (0);
7920 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7921 return rounded_frame_size (0);
7923 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
7924 && (to == HARD_FRAME_POINTER_REGNUM
7925 || to == STACK_POINTER_REGNUM));
7928 int n = total_saved_regs_space;
7929 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7930 save_schedule schedule;
7933 n += total_auto_space;
7935 /* If it wasn't saved, there's not much we can do. */
7936 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7939 target_flags = copy_flags;
7941 sh5_schedule_saves (&live_regs_mask, &schedule, n);
7942 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
7943 if (entry->reg == pr_reg)
7945 target_flags = save_flags;
7946 return entry->offset;
7951 return total_auto_space;
7954 /* Insert any deferred function attributes from earlier pragmas. */
7956 sh_insert_attributes (tree node, tree *attributes)
7960 if (TREE_CODE (node) != FUNCTION_DECL)
7963 /* We are only interested in fields. */
7967 /* Append the attributes to the deferred attributes. */
7968 *sh_deferred_function_attributes_tail = *attributes;
7969 attrs = sh_deferred_function_attributes;
7973 /* Some attributes imply or require the interrupt attribute. */
7974 if (!lookup_attribute ("interrupt_handler", attrs)
7975 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
7977 /* If we have a trapa_handler, but no interrupt_handler attribute,
7978 insert an interrupt_handler attribute. */
7979 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
7980 /* We can't use sh_pr_interrupt here because that's not in the
7983 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
7984 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
7985 if the interrupt attribute is missing, we ignore the attribute
7987 else if (lookup_attribute ("sp_switch", attrs)
7988 || lookup_attribute ("trap_exit", attrs)
7989 || lookup_attribute ("nosave_low_regs", attrs)
7990 || lookup_attribute ("resbank", attrs))
7994 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
7996 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
7997 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
7998 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
7999 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8000 warning (OPT_Wattributes,
8001 "%qs attribute only applies to interrupt functions",
8002 IDENTIFIER_POINTER (TREE_PURPOSE (attrs)));
8005 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8007 tail = &TREE_CHAIN (*tail);
8010 attrs = *attributes;
8014 /* Install the processed list. */
8015 *attributes = attrs;
8017 /* Clear deferred attributes. */
8018 sh_deferred_function_attributes = NULL_TREE;
8019 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8024 /* Supported attributes:
8026 interrupt_handler -- specifies this function is an interrupt handler.
8028 trapa_handler - like above, but don't save all registers.
8030 sp_switch -- specifies an alternate stack for an interrupt handler
8033 trap_exit -- use a trapa to exit an interrupt function instead of
8036 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8037 This is useful on the SH3 and upwards,
8038 which has a separate set of low regs for User and Supervisor modes.
8039 This should only be used for the lowest level of interrupts. Higher levels
8040 of interrupts must save the registers in case they themselves are
8043 renesas -- use Renesas calling/layout conventions (functions and
8046 resbank -- In case of an ISR, use a register bank to save registers
8047 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8050 const struct attribute_spec sh_attribute_table[] =
8052 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8053 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8054 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
8055 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
8056 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
8057 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8058 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8059 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
8060 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
8062 /* Symbian support adds three new attributes:
8063 dllexport - for exporting a function/variable that will live in a dll
8064 dllimport - for importing a function/variable from a dll
8066 Microsoft allows multiple declspecs in one __declspec, separating
8067 them with spaces. We do NOT support this. Instead, use __declspec
8069 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8070 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8072 { NULL, 0, 0, false, false, false, NULL }
8075 /* Handle a 'resbank' attribute. */
8077 sh_handle_resbank_handler_attribute (tree * node, tree name,
8078 tree args ATTRIBUTE_UNUSED,
8079 int flags ATTRIBUTE_UNUSED,
8080 bool * no_add_attrs)
8084 warning (OPT_Wattributes, "%qs attribute is supported only for SH2A",
8085 IDENTIFIER_POINTER (name));
8086 *no_add_attrs = true;
8088 if (TREE_CODE (*node) != FUNCTION_DECL)
8090 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8091 IDENTIFIER_POINTER (name));
8092 *no_add_attrs = true;
8098 /* Handle an "interrupt_handler" attribute; arguments as in
8099 struct attribute_spec.handler. */
8101 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8102 tree args ATTRIBUTE_UNUSED,
8103 int flags ATTRIBUTE_UNUSED,
8106 if (TREE_CODE (*node) != FUNCTION_DECL)
8108 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8109 IDENTIFIER_POINTER (name));
8110 *no_add_attrs = true;
8112 else if (TARGET_SHCOMPACT)
8114 error ("attribute interrupt_handler is not compatible with -m5-compact");
8115 *no_add_attrs = true;
8121 /* Handle an 'function_vector' attribute; arguments as in
8122 struct attribute_spec.handler. */
8124 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8125 tree args ATTRIBUTE_UNUSED,
8126 int flags ATTRIBUTE_UNUSED,
8127 bool * no_add_attrs)
8131 warning (OPT_Wattributes, "%qs attribute only applies to SH2A",
8132 IDENTIFIER_POINTER (name));
8133 *no_add_attrs = true;
8135 else if (TREE_CODE (*node) != FUNCTION_DECL)
8137 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8138 IDENTIFIER_POINTER (name));
8139 *no_add_attrs = true;
8141 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8143 /* The argument must be a constant integer. */
8144 warning (OPT_Wattributes,
8145 "`%s' attribute argument not an integer constant",
8146 IDENTIFIER_POINTER (name));
8147 *no_add_attrs = true;
8149 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8151 /* The argument value must be between 0 to 255. */
8152 warning (OPT_Wattributes,
8153 "`%s' attribute argument should be between 0 to 255",
8154 IDENTIFIER_POINTER (name));
8155 *no_add_attrs = true;
8160 /* Returns 1 if current function has been assigned the attribute
8161 'function_vector'. */
8163 sh2a_is_function_vector_call (rtx x)
8165 if (GET_CODE (x) == SYMBOL_REF
8166 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8168 tree tr = SYMBOL_REF_DECL (x);
8170 if (sh2a_function_vector_p (tr))
8177 /* Returns the function vector number, if the the attribute
8178 'function_vector' is assigned, otherwise returns zero. */
8180 sh2a_get_function_vector_number (rtx x)
8185 if ((GET_CODE (x) == SYMBOL_REF)
8186 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8188 t = SYMBOL_REF_DECL (x);
8190 if (TREE_CODE (t) != FUNCTION_DECL)
8193 list = SH_ATTRIBUTES (t);
8196 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8198 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8202 list = TREE_CHAIN (list);
8211 /* Handle an "sp_switch" attribute; arguments as in
8212 struct attribute_spec.handler. */
8214 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8215 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8217 if (TREE_CODE (*node) != FUNCTION_DECL)
8219 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8220 IDENTIFIER_POINTER (name));
8221 *no_add_attrs = true;
8223 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8225 /* The argument must be a constant string. */
8226 warning (OPT_Wattributes, "%qs attribute argument not a string constant",
8227 IDENTIFIER_POINTER (name));
8228 *no_add_attrs = true;
8234 /* Handle an "trap_exit" attribute; arguments as in
8235 struct attribute_spec.handler. */
8237 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8238 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8240 if (TREE_CODE (*node) != FUNCTION_DECL)
8242 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8243 IDENTIFIER_POINTER (name));
8244 *no_add_attrs = true;
8246 /* The argument specifies a trap number to be used in a trapa instruction
8247 at function exit (instead of an rte instruction). */
8248 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8250 /* The argument must be a constant integer. */
8251 warning (OPT_Wattributes, "%qs attribute argument not an "
8252 "integer constant", IDENTIFIER_POINTER (name));
8253 *no_add_attrs = true;
8260 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8261 tree name ATTRIBUTE_UNUSED,
8262 tree args ATTRIBUTE_UNUSED,
8263 int flags ATTRIBUTE_UNUSED,
8264 bool *no_add_attrs ATTRIBUTE_UNUSED)
8269 /* True if __attribute__((renesas)) or -mrenesas. */
8271 sh_attr_renesas_p (const_tree td)
8278 td = TREE_TYPE (td);
8279 if (td == error_mark_node)
8281 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8285 /* True if __attribute__((renesas)) or -mrenesas, for the current
8288 sh_cfun_attr_renesas_p (void)
8290 return sh_attr_renesas_p (current_function_decl);
8294 sh_cfun_interrupt_handler_p (void)
8296 return (lookup_attribute ("interrupt_handler",
8297 DECL_ATTRIBUTES (current_function_decl))
8301 /* Returns 1 if FUNC has been assigned the attribute
8302 "function_vector". */
8304 sh2a_function_vector_p (tree func)
8307 if (TREE_CODE (func) != FUNCTION_DECL)
8310 list = SH_ATTRIBUTES (func);
8313 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8316 list = TREE_CHAIN (list);
8321 /* Returns TRUE if given tree has the "resbank" attribute. */
8324 sh_cfun_resbank_handler_p (void)
8326 return ((lookup_attribute ("resbank",
8327 DECL_ATTRIBUTES (current_function_decl))
8329 && (lookup_attribute ("interrupt_handler",
8330 DECL_ATTRIBUTES (current_function_decl))
8331 != NULL_TREE) && TARGET_SH2A);
8334 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8337 sh_check_pch_target_flags (int old_flags)
8339 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8340 | MASK_SH_E | MASK_HARD_SH4
8341 | MASK_FPU_SINGLE | MASK_SH4))
8342 return _("created and used with different architectures / ABIs");
8343 if ((old_flags ^ target_flags) & MASK_HITACHI)
8344 return _("created and used with different ABIs");
8345 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8346 return _("created and used with different endianness");
8350 /* Predicates used by the templates. */
8352 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8353 Used only in general_movsrc_operand. */
8356 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8368 /* Nonzero if OP is a floating point value with value 0.0. */
8371 fp_zero_operand (rtx op)
8375 if (GET_MODE (op) != SFmode)
8378 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8379 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8382 /* Nonzero if OP is a floating point value with value 1.0. */
8385 fp_one_operand (rtx op)
8389 if (GET_MODE (op) != SFmode)
8392 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8393 return REAL_VALUES_EQUAL (r, dconst1);
8396 /* For -m4 and -m4-single-only, mode switching is used. If we are
8397 compiling without -mfmovd, movsf_ie isn't taken into account for
8398 mode switching. We could check in machine_dependent_reorg for
8399 cases where we know we are in single precision mode, but there is
8400 interface to find that out during reload, so we must avoid
8401 choosing an fldi alternative during reload and thus failing to
8402 allocate a scratch register for the constant loading. */
8406 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
8410 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8412 enum rtx_code code = GET_CODE (op);
8413 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8416 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8418 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8420 if (GET_CODE (op) != SYMBOL_REF)
8422 return SYMBOL_REF_TLS_MODEL (op);
8425 /* Return the destination address of a branch. */
8428 branch_dest (rtx branch)
8430 rtx dest = SET_SRC (PATTERN (branch));
8433 if (GET_CODE (dest) == IF_THEN_ELSE)
8434 dest = XEXP (dest, 1);
8435 dest = XEXP (dest, 0);
8436 dest_uid = INSN_UID (dest);
8437 return INSN_ADDRESSES (dest_uid);
8440 /* Return nonzero if REG is not used after INSN.
8441 We assume REG is a reload reg, and therefore does
8442 not live past labels. It may live past calls or jumps though. */
8444 reg_unused_after (rtx reg, rtx insn)
8449 /* If the reg is set by this instruction, then it is safe for our
8450 case. Disregard the case where this is a store to memory, since
8451 we are checking a register used in the store address. */
8452 set = single_set (insn);
8453 if (set && GET_CODE (SET_DEST (set)) != MEM
8454 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8457 while ((insn = NEXT_INSN (insn)))
8463 code = GET_CODE (insn);
8466 /* If this is a label that existed before reload, then the register
8467 if dead here. However, if this is a label added by reorg, then
8468 the register may still be live here. We can't tell the difference,
8469 so we just ignore labels completely. */
8470 if (code == CODE_LABEL)
8475 if (code == JUMP_INSN)
8478 /* If this is a sequence, we must handle them all at once.
8479 We could have for instance a call that sets the target register,
8480 and an insn in a delay slot that uses the register. In this case,
8481 we must return 0. */
8482 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8487 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8489 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
8490 rtx set = single_set (this_insn);
8492 if (GET_CODE (this_insn) == CALL_INSN)
8494 else if (GET_CODE (this_insn) == JUMP_INSN)
8496 if (INSN_ANNULLED_BRANCH_P (this_insn))
8501 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8503 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8505 if (GET_CODE (SET_DEST (set)) != MEM)
8511 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8516 else if (code == JUMP_INSN)
8520 set = single_set (insn);
8521 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8523 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8524 return GET_CODE (SET_DEST (set)) != MEM;
8525 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8528 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
8536 static GTY(()) rtx fpscr_rtx;
8538 get_fpscr_rtx (void)
8542 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
8543 REG_USERVAR_P (fpscr_rtx) = 1;
8544 mark_user_reg (fpscr_rtx);
8546 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
8547 mark_user_reg (fpscr_rtx);
8551 static GTY(()) tree fpscr_values;
8554 emit_fpu_switch (rtx scratch, int index)
8558 if (fpscr_values == NULL)
8562 t = build_index_type (integer_one_node);
8563 t = build_array_type (integer_type_node, t);
8564 t = build_decl (VAR_DECL, get_identifier ("__fpscr_values"), t);
8565 DECL_ARTIFICIAL (t) = 1;
8566 DECL_IGNORED_P (t) = 1;
8567 DECL_EXTERNAL (t) = 1;
8568 TREE_STATIC (t) = 1;
8569 TREE_PUBLIC (t) = 1;
8575 src = DECL_RTL (fpscr_values);
8576 if (!can_create_pseudo_p ())
8578 emit_move_insn (scratch, XEXP (src, 0));
8580 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
8581 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
8584 src = adjust_address (src, PSImode, index * 4);
8586 dst = get_fpscr_rtx ();
8587 emit_move_insn (dst, src);
8591 emit_sf_insn (rtx pat)
8597 emit_df_insn (rtx pat)
8603 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8605 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8609 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8611 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
8616 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8618 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8622 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8624 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
8628 static rtx get_free_reg (HARD_REG_SET);
8630 /* This function returns a register to use to load the address to load
8631 the fpscr from. Currently it always returns r1 or r7, but when we are
8632 able to use pseudo registers after combine, or have a better mechanism
8633 for choosing a register, it should be done here. */
8634 /* REGS_LIVE is the liveness information for the point for which we
8635 need this allocation. In some bare-bones exit blocks, r1 is live at the
8636 start. We can even have all of r0..r3 being live:
8637 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
8638 INSN before which new insns are placed with will clobber the register
8639 we return. If a basic block consists only of setting the return value
8640 register to a pseudo and using that register, the return value is not
8641 live before or after this block, yet we we'll insert our insns right in
8645 get_free_reg (HARD_REG_SET regs_live)
8647 if (! TEST_HARD_REG_BIT (regs_live, 1))
8648 return gen_rtx_REG (Pmode, 1);
8650 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
8651 there shouldn't be anything but a jump before the function end. */
8652 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
8653 return gen_rtx_REG (Pmode, 7);
8656 /* This function will set the fpscr from memory.
8657 MODE is the mode we are setting it to. */
8659 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
8661 enum attr_fp_mode fp_mode = mode;
8662 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
8665 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
8666 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
8669 /* Is the given character a logical line separator for the assembler? */
8670 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
8671 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
8675 sh_insn_length_adjustment (rtx insn)
8677 /* Instructions with unfilled delay slots take up an extra two bytes for
8678 the nop in the delay slot. */
8679 if (((GET_CODE (insn) == INSN
8680 && GET_CODE (PATTERN (insn)) != USE
8681 && GET_CODE (PATTERN (insn)) != CLOBBER)
8682 || GET_CODE (insn) == CALL_INSN
8683 || (GET_CODE (insn) == JUMP_INSN
8684 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8685 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
8686 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
8687 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
8690 /* SH2e has a bug that prevents the use of annulled branches, so if
8691 the delay slot is not filled, we'll have to put a NOP in it. */
8692 if (sh_cpu == CPU_SH2E
8693 && GET_CODE (insn) == JUMP_INSN
8694 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8695 && GET_CODE (PATTERN (insn)) != ADDR_VEC
8696 && get_attr_type (insn) == TYPE_CBRANCH
8697 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
8700 /* sh-dsp parallel processing insn take four bytes instead of two. */
8702 if (GET_CODE (insn) == INSN)
8705 rtx body = PATTERN (insn);
8706 const char *template;
8708 int maybe_label = 1;
8710 if (GET_CODE (body) == ASM_INPUT)
8711 template = XSTR (body, 0);
8712 else if (asm_noperands (body) >= 0)
8714 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
8723 while (c == ' ' || c == '\t');
8724 /* all sh-dsp parallel-processing insns start with p.
8725 The only non-ppi sh insn starting with p is pref.
8726 The only ppi starting with pr is prnd. */
8727 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
8729 /* The repeat pseudo-insn expands two three insns, a total of
8730 six bytes in size. */
8731 else if ((c == 'r' || c == 'R')
8732 && ! strncasecmp ("epeat", template, 5))
8734 while (c && c != '\n'
8735 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, template))
8737 /* If this is a label, it is obviously not a ppi insn. */
8738 if (c == ':' && maybe_label)
8743 else if (c == '\'' || c == '"')
8748 maybe_label = c != ':';
8756 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
8757 isn't protected by a PIC unspec. */
8759 nonpic_symbol_mentioned_p (rtx x)
8761 register const char *fmt;
8764 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
8765 || GET_CODE (x) == PC)
8768 /* We don't want to look into the possible MEM location of a
8769 CONST_DOUBLE, since we're not going to use it, in general. */
8770 if (GET_CODE (x) == CONST_DOUBLE)
8773 if (GET_CODE (x) == UNSPEC
8774 && (XINT (x, 1) == UNSPEC_PIC
8775 || XINT (x, 1) == UNSPEC_GOT
8776 || XINT (x, 1) == UNSPEC_GOTOFF
8777 || XINT (x, 1) == UNSPEC_GOTPLT
8778 || XINT (x, 1) == UNSPEC_GOTTPOFF
8779 || XINT (x, 1) == UNSPEC_DTPOFF
8780 || XINT (x, 1) == UNSPEC_PLT))
8783 fmt = GET_RTX_FORMAT (GET_CODE (x));
8784 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8790 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8791 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
8794 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
8801 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
8802 @GOTOFF in `reg'. */
8804 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
8807 if (tls_symbolic_operand (orig, Pmode))
8810 if (GET_CODE (orig) == LABEL_REF
8811 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
8814 reg = gen_reg_rtx (Pmode);
8816 emit_insn (gen_symGOTOFF2reg (reg, orig));
8819 else if (GET_CODE (orig) == SYMBOL_REF)
8822 reg = gen_reg_rtx (Pmode);
8824 emit_insn (gen_symGOT2reg (reg, orig));
8830 /* Mark the use of a constant in the literal table. If the constant
8831 has multiple labels, make it unique. */
8833 mark_constant_pool_use (rtx x)
8835 rtx insn, lab, pattern;
8840 switch (GET_CODE (x))
8850 /* Get the first label in the list of labels for the same constant
8851 and delete another labels in the list. */
8853 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
8855 if (GET_CODE (insn) != CODE_LABEL
8856 || LABEL_REFS (insn) != NEXT_INSN (insn))
8861 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
8862 INSN_DELETED_P (insn) = 1;
8864 /* Mark constants in a window. */
8865 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
8867 if (GET_CODE (insn) != INSN)
8870 pattern = PATTERN (insn);
8871 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
8874 switch (XINT (pattern, 1))
8876 case UNSPECV_CONST2:
8877 case UNSPECV_CONST4:
8878 case UNSPECV_CONST8:
8879 XVECEXP (pattern, 0, 1) = const1_rtx;
8881 case UNSPECV_WINDOW_END:
8882 if (XVECEXP (pattern, 0, 0) == x)
8885 case UNSPECV_CONST_END:
8895 /* Return true if it's possible to redirect BRANCH1 to the destination
8896 of an unconditional jump BRANCH2. We only want to do this if the
8897 resulting branch will have a short displacement. */
8899 sh_can_redirect_branch (rtx branch1, rtx branch2)
8901 if (flag_expensive_optimizations && simplejump_p (branch2))
8903 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
8907 for (distance = 0, insn = NEXT_INSN (branch1);
8908 insn && distance < 256;
8909 insn = PREV_INSN (insn))
8914 distance += get_attr_length (insn);
8916 for (distance = 0, insn = NEXT_INSN (branch1);
8917 insn && distance < 256;
8918 insn = NEXT_INSN (insn))
8923 distance += get_attr_length (insn);
8929 /* Return nonzero if register old_reg can be renamed to register new_reg. */
8931 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
8932 unsigned int new_reg)
8934 /* Interrupt functions can only use registers that have already been
8935 saved by the prologue, even if they would normally be
8938 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
8944 /* Function to update the integer COST
8945 based on the relationship between INSN that is dependent on
8946 DEP_INSN through the dependence LINK. The default is to make no
8947 adjustment to COST. This can be used for example to specify to
8948 the scheduler that an output- or anti-dependence does not incur
8949 the same cost as a data-dependence. The return value should be
8950 the new value for COST. */
8952 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
8958 /* On SHmedia, if the dependence is an anti-dependence or
8959 output-dependence, there is no cost. */
8960 if (REG_NOTE_KIND (link) != 0)
8962 /* However, dependencies between target register loads and
8963 uses of the register in a subsequent block that are separated
8964 by a conditional branch are not modelled - we have to do with
8965 the anti-dependency between the target register load and the
8966 conditional branch that ends the current block. */
8967 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
8968 && GET_CODE (PATTERN (dep_insn)) == SET
8969 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
8970 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
8971 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
8973 int orig_cost = cost;
8974 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
8975 rtx target = ((! note
8976 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
8977 ? insn : JUMP_LABEL (insn));
8978 /* On the likely path, the branch costs 1, on the unlikely path,
8982 target = next_active_insn (target);
8983 while (target && ! flow_dependent_p (target, dep_insn)
8985 /* If two branches are executed in immediate succession, with the
8986 first branch properly predicted, this causes a stall at the
8987 second branch, hence we won't need the target for the
8988 second branch for two cycles after the launch of the first
8990 if (cost > orig_cost - 2)
8991 cost = orig_cost - 2;
8997 else if (get_attr_is_mac_media (insn)
8998 && get_attr_is_mac_media (dep_insn))
9001 else if (! reload_completed
9002 && GET_CODE (PATTERN (insn)) == SET
9003 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9004 && GET_CODE (PATTERN (dep_insn)) == SET
9005 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9008 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9009 that is needed at the target. */
9010 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9011 && ! flow_dependent_p (insn, dep_insn))
9014 else if (REG_NOTE_KIND (link) == 0)
9016 enum attr_type type;
9019 if (recog_memoized (insn) < 0
9020 || recog_memoized (dep_insn) < 0)
9023 dep_set = single_set (dep_insn);
9025 /* The latency that we specify in the scheduling description refers
9026 to the actual output, not to an auto-increment register; for that,
9027 the latency is one. */
9028 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9030 rtx set = single_set (insn);
9033 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9034 && (!MEM_P (SET_DEST (set))
9035 || !reg_mentioned_p (SET_DEST (dep_set),
9036 XEXP (SET_DEST (set), 0))))
9039 /* The only input for a call that is timing-critical is the
9040 function's address. */
9041 if (GET_CODE (insn) == CALL_INSN)
9043 rtx call = PATTERN (insn);
9045 if (GET_CODE (call) == PARALLEL)
9046 call = XVECEXP (call, 0 ,0);
9047 if (GET_CODE (call) == SET)
9048 call = SET_SRC (call);
9049 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
9050 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9051 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9052 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9053 cost -= TARGET_SH4_300 ? 3 : 6;
9055 /* Likewise, the most timing critical input for an sfuncs call
9056 is the function address. However, sfuncs typically start
9057 using their arguments pretty quickly.
9058 Assume a four cycle delay for SH4 before they are needed.
9059 Cached ST40-300 calls are quicker, so assume only a one
9061 ??? Maybe we should encode the delays till input registers
9062 are needed by sfuncs into the sfunc call insn. */
9063 /* All sfunc calls are parallels with at least four components.
9064 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9065 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9066 && XVECLEN (PATTERN (insn), 0) >= 4
9067 && (reg = sfunc_uses_reg (insn)))
9069 if (! reg_set_p (reg, dep_insn))
9070 cost -= TARGET_SH4_300 ? 1 : 4;
9072 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9074 enum attr_type dep_type = get_attr_type (dep_insn);
9076 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9078 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9079 && (type = get_attr_type (insn)) != TYPE_CALL
9080 && type != TYPE_SFUNC)
9082 /* When the preceding instruction loads the shift amount of
9083 the following SHAD/SHLD, the latency of the load is increased
9085 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9086 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9087 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9088 XEXP (SET_SRC (single_set (insn)),
9091 /* When an LS group instruction with a latency of less than
9092 3 cycles is followed by a double-precision floating-point
9093 instruction, FIPR, or FTRV, the latency of the first
9094 instruction is increased to 3 cycles. */
9096 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9097 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9099 /* The lsw register of a double-precision computation is ready one
9101 else if (reload_completed
9102 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9103 && (use_pat = single_set (insn))
9104 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9108 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9109 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9112 else if (TARGET_SH4_300)
9114 /* Stores need their input register two cycles later. */
9115 if (dep_set && cost >= 1
9116 && ((type = get_attr_type (insn)) == TYPE_STORE
9117 || type == TYPE_PSTORE
9118 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9120 rtx set = single_set (insn);
9122 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9123 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9126 /* But don't reduce the cost below 1 if the address depends
9127 on a side effect of dep_insn. */
9129 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9135 /* An anti-dependence penalty of two applies if the first insn is a double
9136 precision fadd / fsub / fmul. */
9137 else if (!TARGET_SH4_300
9138 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9139 && recog_memoized (dep_insn) >= 0
9140 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9141 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9142 /* A lot of alleged anti-flow dependences are fake,
9143 so check this one is real. */
9144 && flow_dependent_p (dep_insn, insn))
9150 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9151 if DEP_INSN is anti-flow dependent on INSN. */
9153 flow_dependent_p (rtx insn, rtx dep_insn)
9155 rtx tmp = PATTERN (insn);
9157 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9158 return tmp == NULL_RTX;
9161 /* A helper function for flow_dependent_p called through note_stores. */
9163 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9165 rtx * pinsn = (rtx *) data;
9167 if (*pinsn && reg_referenced_p (x, *pinsn))
9171 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9172 'special function' patterns (type sfunc) that clobber pr, but that
9173 do not look like function calls to leaf_function_p. Hence we must
9174 do this extra check. */
9178 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9181 /* Return where to allocate pseudo for a given hard register initial
9184 sh_allocate_initial_value (rtx hard_reg)
9188 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9190 if (current_function_is_leaf
9191 && ! sh_pr_n_sets ()
9192 && ! (TARGET_SHCOMPACT
9193 && ((current_function_args_info.call_cookie
9194 & ~ CALL_COOKIE_RET_TRAMP (1))
9195 || current_function_saves_all_registers)))
9198 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9206 /* This function returns "2" to indicate dual issue for the SH4
9207 processor. To be used by the DFA pipeline description. */
9209 sh_issue_rate (void)
9211 if (TARGET_SUPERSCALAR)
9217 /* Functions for ready queue reordering for sched1. */
9219 /* Get weight for mode for a set x. */
9221 find_set_regmode_weight (rtx x, enum machine_mode mode)
9223 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9225 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9227 if (GET_CODE (SET_DEST (x)) == REG)
9229 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9239 /* Get regmode weight for insn. */
9241 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9243 short reg_weight = 0;
9246 /* Increment weight for each register born here. */
9248 reg_weight += find_set_regmode_weight (x, mode);
9249 if (GET_CODE (x) == PARALLEL)
9252 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9254 x = XVECEXP (PATTERN (insn), 0, j);
9255 reg_weight += find_set_regmode_weight (x, mode);
9258 /* Decrement weight for each register that dies here. */
9259 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9261 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9263 rtx note = XEXP (x, 0);
9264 if (GET_CODE (note) == REG && GET_MODE (note) == mode)
9271 /* Calculate regmode weights for all insns of a basic block. */
9273 find_regmode_weight (basic_block b, enum machine_mode mode)
9275 rtx insn, next_tail, head, tail;
9277 get_ebb_head_tail (b, b, &head, &tail);
9278 next_tail = NEXT_INSN (tail);
9280 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9282 /* Handle register life information. */
9287 INSN_REGMODE_WEIGHT (insn, mode) =
9288 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9289 else if (mode == SImode)
9290 INSN_REGMODE_WEIGHT (insn, mode) =
9291 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9295 /* Comparison function for ready queue sorting. */
9297 rank_for_reorder (const void *x, const void *y)
9299 rtx tmp = *(const rtx *) y;
9300 rtx tmp2 = *(const rtx *) x;
9302 /* The insn in a schedule group should be issued the first. */
9303 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9304 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9306 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9307 minimizes instruction movement, thus minimizing sched's effect on
9308 register pressure. */
9309 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9312 /* Resort the array A in which only element at index N may be out of order. */
9314 swap_reorder (rtx *a, int n)
9316 rtx insn = a[n - 1];
9319 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9327 #define SCHED_REORDER(READY, N_READY) \
9330 if ((N_READY) == 2) \
9331 swap_reorder (READY, N_READY); \
9332 else if ((N_READY) > 2) \
9333 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
9337 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
9340 ready_reorder (rtx *ready, int nready)
9342 SCHED_REORDER (ready, nready);
9345 /* Count life regions of r0 for a block. */
9347 find_r0_life_regions (basic_block b)
9356 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
9369 r0_reg = gen_rtx_REG (SImode, R0_REG);
9374 if (find_regno_note (insn, REG_DEAD, R0_REG))
9380 && (pset = single_set (insn))
9381 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
9382 && !find_regno_note (insn, REG_UNUSED, R0_REG))
9390 insn = NEXT_INSN (insn);
9395 /* Calculate regmode weights for all insns of all basic block. */
9397 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
9398 int verbose ATTRIBUTE_UNUSED,
9403 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
9404 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
9405 r0_life_regions = 0;
9407 FOR_EACH_BB_REVERSE (b)
9409 find_regmode_weight (b, SImode);
9410 find_regmode_weight (b, SFmode);
9411 if (!reload_completed)
9412 r0_life_regions += find_r0_life_regions (b);
9415 CURR_REGMODE_PRESSURE (SImode) = 0;
9416 CURR_REGMODE_PRESSURE (SFmode) = 0;
9422 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
9423 int verbose ATTRIBUTE_UNUSED)
9425 if (regmode_weight[0])
9427 free (regmode_weight[0]);
9428 regmode_weight[0] = NULL;
9430 if (regmode_weight[1])
9432 free (regmode_weight[1]);
9433 regmode_weight[1] = NULL;
9437 /* The scalar modes supported differs from the default version in TImode
9438 for 32-bit SHMEDIA. */
9440 sh_scalar_mode_supported_p (enum machine_mode mode)
9442 if (TARGET_SHMEDIA32 && mode == TImode)
9445 return default_scalar_mode_supported_p (mode);
9448 /* Cache the can_issue_more so that we can return it from reorder2. Also,
9449 keep count of register pressures on SImode and SFmode. */
9451 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
9452 int sched_verbose ATTRIBUTE_UNUSED,
9456 if (GET_CODE (PATTERN (insn)) != USE
9457 && GET_CODE (PATTERN (insn)) != CLOBBER)
9458 cached_can_issue_more = can_issue_more - 1;
9460 cached_can_issue_more = can_issue_more;
9462 if (reload_completed)
9463 return cached_can_issue_more;
9465 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
9466 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
9468 return cached_can_issue_more;
9472 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
9473 int verbose ATTRIBUTE_UNUSED,
9474 int veclen ATTRIBUTE_UNUSED)
9476 CURR_REGMODE_PRESSURE (SImode) = 0;
9477 CURR_REGMODE_PRESSURE (SFmode) = 0;
9480 /* Some magic numbers. */
9481 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9482 functions that already have high pressure on r0. */
9483 #define R0_MAX_LIFE_REGIONS 2
9484 /* Register Pressure thresholds for SImode and SFmode registers. */
9485 #define SIMODE_MAX_WEIGHT 5
9486 #define SFMODE_MAX_WEIGHT 10
9488 /* Return true if the pressure is high for MODE. */
9490 high_pressure (enum machine_mode mode)
9492 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9493 functions that already have high pressure on r0. */
9494 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
9498 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
9500 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
9503 /* Reorder ready queue if register pressure is high. */
9505 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
9506 int sched_verbose ATTRIBUTE_UNUSED,
9509 int clock_var ATTRIBUTE_UNUSED)
9511 if (reload_completed)
9512 return sh_issue_rate ();
9514 if (high_pressure (SFmode) || high_pressure (SImode))
9516 ready_reorder (ready, *n_readyp);
9519 return sh_issue_rate ();
9522 /* Skip cycles if the current register pressure is high. */
9524 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
9525 int sched_verbose ATTRIBUTE_UNUSED,
9526 rtx *ready ATTRIBUTE_UNUSED,
9527 int *n_readyp ATTRIBUTE_UNUSED,
9528 int clock_var ATTRIBUTE_UNUSED)
9530 if (reload_completed)
9531 return cached_can_issue_more;
9533 if (high_pressure(SFmode) || high_pressure (SImode))
9536 return cached_can_issue_more;
9539 /* Skip cycles without sorting the ready queue. This will move insn from
9540 Q->R. If this is the last cycle we are skipping; allow sorting of ready
9541 queue by sh_reorder. */
9543 /* Generally, skipping these many cycles are sufficient for all insns to move
9548 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
9549 int sched_verbose ATTRIBUTE_UNUSED,
9550 rtx insn ATTRIBUTE_UNUSED,
9555 if (reload_completed)
9560 if ((clock_var - last_clock_var) < MAX_SKIPS)
9565 /* If this is the last cycle we are skipping, allow reordering of R. */
9566 if ((clock_var - last_clock_var) == MAX_SKIPS)
9578 /* SHmedia requires registers for branches, so we can't generate new
9579 branches past reload. */
9581 sh_cannot_modify_jumps_p (void)
9583 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
9587 sh_target_reg_class (void)
9589 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
9593 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
9600 if (! shmedia_space_reserved_for_target_registers)
9602 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
9604 if (calc_live_regs (&dummy) >= 6 * 8)
9610 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
9612 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
9616 On the SH1..SH4, the trampoline looks like
9617 2 0002 D202 mov.l l2,r2
9618 1 0000 D301 mov.l l1,r3
9621 5 0008 00000000 l1: .long area
9622 6 000c 00000000 l2: .long function
9624 SH5 (compact) uses r1 instead of r3 for the static chain. */
9627 /* Emit RTL insns to initialize the variable parts of a trampoline.
9628 FNADDR is an RTX for the address of the function's pure code.
9629 CXT is an RTX for the static chain value for the function. */
9632 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
9634 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
9636 if (TARGET_SHMEDIA64)
9641 rtx movi1 = GEN_INT (0xcc000010);
9642 rtx shori1 = GEN_INT (0xc8000010);
9645 /* The following trampoline works within a +- 128 KB range for cxt:
9646 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
9647 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
9648 gettr tr1,r1; blink tr0,r63 */
9649 /* Address rounding makes it hard to compute the exact bounds of the
9650 offset for this trampoline, but we have a rather generous offset
9651 range, so frame_offset should do fine as an upper bound. */
9652 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
9654 /* ??? could optimize this trampoline initialization
9655 by writing DImode words with two insns each. */
9656 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
9657 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
9658 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
9659 insn = gen_rtx_AND (DImode, insn, mask);
9660 /* Or in ptb/u .,tr1 pattern */
9661 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
9662 insn = force_operand (insn, NULL_RTX);
9663 insn = gen_lowpart (SImode, insn);
9664 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
9665 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
9666 insn = gen_rtx_AND (DImode, insn, mask);
9667 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
9668 insn = gen_lowpart (SImode, insn);
9669 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
9670 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
9671 insn = gen_rtx_AND (DImode, insn, mask);
9672 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9673 insn = gen_lowpart (SImode, insn);
9674 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
9675 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
9676 insn = gen_rtx_AND (DImode, insn, mask);
9677 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9678 insn = gen_lowpart (SImode, insn);
9679 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
9680 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
9681 insn = gen_rtx_AND (DImode, insn, mask);
9682 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9683 insn = gen_lowpart (SImode, insn);
9684 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
9685 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
9686 GEN_INT (0x6bf10600));
9687 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
9688 GEN_INT (0x4415fc10));
9689 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
9690 GEN_INT (0x4401fff0));
9691 emit_insn (gen_ic_invalidate_line (tramp));
9694 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
9695 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
9697 tramp_templ = gen_datalabel_ref (tramp_templ);
9699 src = gen_const_mem (BLKmode, tramp_templ);
9700 set_mem_align (dst, 256);
9701 set_mem_align (src, 64);
9702 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
9704 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
9705 emit_move_insn (adjust_address (tramp_mem, Pmode,
9706 fixed_len + GET_MODE_SIZE (Pmode)),
9708 emit_insn (gen_ic_invalidate_line (tramp));
9711 else if (TARGET_SHMEDIA)
9713 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
9714 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
9715 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
9716 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
9717 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
9718 rotated 10 right, and higher 16 bit of every 32 selected. */
9720 = force_reg (V2HImode, (simplify_gen_subreg
9721 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
9722 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
9723 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
9725 tramp = force_reg (Pmode, tramp);
9726 fnaddr = force_reg (SImode, fnaddr);
9727 cxt = force_reg (SImode, cxt);
9728 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
9729 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
9731 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
9732 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
9733 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
9734 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
9735 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
9736 gen_rtx_SUBREG (V2HImode, cxt, 0),
9738 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
9739 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
9740 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
9741 if (TARGET_LITTLE_ENDIAN)
9743 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
9744 emit_insn (gen_mextr4 (quad2, cxtload, blink));
9748 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
9749 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
9751 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
9752 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
9753 emit_insn (gen_ic_invalidate_line (tramp));
9756 else if (TARGET_SHCOMPACT)
9758 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
9761 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
9762 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
9764 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
9765 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
9767 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
9768 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
9771 if (!TARGET_INLINE_IC_INVALIDATE
9772 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
9773 emit_library_call (function_symbol (NULL, "__ic_invalidate",
9775 0, VOIDmode, 1, tramp, SImode);
9777 emit_insn (gen_ic_invalidate_line (tramp));
9781 /* FIXME: This is overly conservative. A SHcompact function that
9782 receives arguments ``by reference'' will have them stored in its
9783 own stack frame, so it must not pass pointers or references to
9784 these arguments to other functions by means of sibling calls. */
9785 /* If PIC, we cannot make sibling calls to global functions
9786 because the PLT requires r12 to be live. */
9788 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
9791 && (! TARGET_SHCOMPACT
9792 || current_function_args_info.stack_regs == 0)
9793 && ! sh_cfun_interrupt_handler_p ()
9795 || (decl && ! TREE_PUBLIC (decl))
9796 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
9799 /* Machine specific built-in functions. */
9801 struct builtin_description
9803 const enum insn_code icode;
9804 const char *const name;
9808 /* describe number and signedness of arguments; arg[0] == result
9809 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
9810 /* 9: 64-bit pointer, 10: 32-bit pointer */
9811 static const char signature_args[][4] =
9813 #define SH_BLTIN_V2SI2 0
9815 #define SH_BLTIN_V4HI2 1
9817 #define SH_BLTIN_V2SI3 2
9819 #define SH_BLTIN_V4HI3 3
9821 #define SH_BLTIN_V8QI3 4
9823 #define SH_BLTIN_MAC_HISI 5
9825 #define SH_BLTIN_SH_HI 6
9827 #define SH_BLTIN_SH_SI 7
9829 #define SH_BLTIN_V4HI2V2SI 8
9831 #define SH_BLTIN_V4HI2V8QI 9
9833 #define SH_BLTIN_SISF 10
9835 #define SH_BLTIN_LDUA_L 11
9837 #define SH_BLTIN_LDUA_Q 12
9839 #define SH_BLTIN_STUA_L 13
9841 #define SH_BLTIN_STUA_Q 14
9843 #define SH_BLTIN_LDUA_L64 15
9845 #define SH_BLTIN_LDUA_Q64 16
9847 #define SH_BLTIN_STUA_L64 17
9849 #define SH_BLTIN_STUA_Q64 18
9851 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
9852 #define SH_BLTIN_2 19
9853 #define SH_BLTIN_SU 19
9855 #define SH_BLTIN_3 20
9856 #define SH_BLTIN_SUS 20
9858 #define SH_BLTIN_PSSV 21
9860 #define SH_BLTIN_XXUU 22
9861 #define SH_BLTIN_UUUU 22
9863 #define SH_BLTIN_PV 23
9866 /* mcmv: operands considered unsigned. */
9867 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
9868 /* mperm: control value considered unsigned int. */
9869 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
9870 /* mshards_q: returns signed short. */
9871 /* nsb: takes long long arg, returns unsigned char. */
9872 static const struct builtin_description bdesc[] =
9874 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
9875 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
9876 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
9877 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
9878 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
9879 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
9880 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
9881 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
9882 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
9883 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
9884 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
9885 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
9886 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
9887 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
9888 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
9889 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
9890 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
9891 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
9892 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
9893 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
9894 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
9895 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
9896 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
9897 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
9898 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
9899 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
9900 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
9901 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
9902 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
9903 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
9904 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
9905 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
9906 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
9907 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
9908 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
9909 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
9910 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
9911 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
9912 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
9913 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
9914 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
9915 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
9916 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
9917 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
9918 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
9919 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
9920 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
9921 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
9922 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
9923 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
9924 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
9925 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
9926 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
9927 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
9928 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
9929 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
9930 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
9931 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
9932 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
9933 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
9934 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
9935 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
9936 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
9937 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
9938 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
9939 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
9940 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
9941 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
9942 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
9943 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
9944 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
9945 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
9946 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
9947 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
9948 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
9949 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
9950 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
9951 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
9952 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
9953 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
9954 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
9955 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
9956 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
9957 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
9961 sh_media_init_builtins (void)
9963 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
9964 const struct builtin_description *d;
9966 memset (shared, 0, sizeof shared);
9967 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
9969 tree type, arg_type = 0;
9970 int signature = d->signature;
9973 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
9974 type = shared[signature];
9977 int has_result = signature_args[signature][0] != 0;
9979 if ((signature_args[signature][1] & 8)
9980 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
9981 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
9983 if (! TARGET_FPU_ANY
9984 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
9986 type = void_list_node;
9989 int arg = signature_args[signature][i];
9990 int opno = i - 1 + has_result;
9993 arg_type = ptr_type_node;
9995 arg_type = (*lang_hooks.types.type_for_mode)
9996 (insn_data[d->icode].operand[opno].mode,
10001 arg_type = void_type_node;
10004 type = tree_cons (NULL_TREE, arg_type, type);
10006 type = build_function_type (arg_type, type);
10007 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10008 shared[signature] = type;
10010 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10015 /* Implements target hook vector_mode_supported_p. */
10017 sh_vector_mode_supported_p (enum machine_mode mode)
10020 && ((mode == V2SFmode)
10021 || (mode == V4SFmode)
10022 || (mode == V16SFmode)))
10025 else if (TARGET_SHMEDIA
10026 && ((mode == V8QImode)
10027 || (mode == V2HImode)
10028 || (mode == V4HImode)
10029 || (mode == V2SImode)))
10035 /* Implements target hook dwarf_calling_convention. Return an enum
10036 of dwarf_calling_convention. */
10038 sh_dwarf_calling_convention (const_tree func)
10040 if (sh_attr_renesas_p (func))
10041 return DW_CC_GNU_renesas_sh;
10043 return DW_CC_normal;
10047 sh_init_builtins (void)
10049 if (TARGET_SHMEDIA)
10050 sh_media_init_builtins ();
10053 /* Expand an expression EXP that calls a built-in function,
10054 with result going to TARGET if that's convenient
10055 (and in mode MODE if that's convenient).
10056 SUBTARGET may be used as the target for computing one of EXP's operands.
10057 IGNORE is nonzero if the value is to be ignored. */
10060 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10061 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10063 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10064 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10065 const struct builtin_description *d = &bdesc[fcode];
10066 enum insn_code icode = d->icode;
10067 int signature = d->signature;
10068 enum machine_mode tmode = VOIDmode;
10073 if (signature_args[signature][0])
10078 tmode = insn_data[icode].operand[0].mode;
10080 || GET_MODE (target) != tmode
10081 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10082 target = gen_reg_rtx (tmode);
10083 op[nop++] = target;
10088 for (i = 1; i <= 3; i++, nop++)
10091 enum machine_mode opmode, argmode;
10094 if (! signature_args[signature][i])
10096 arg = CALL_EXPR_ARG (exp, i - 1);
10097 if (arg == error_mark_node)
10099 if (signature_args[signature][i] & 8)
10102 optype = ptr_type_node;
10106 opmode = insn_data[icode].operand[nop].mode;
10107 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10109 argmode = TYPE_MODE (TREE_TYPE (arg));
10110 if (argmode != opmode)
10111 arg = build1 (NOP_EXPR, optype, arg);
10112 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
10113 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10114 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10120 pat = (*insn_data[d->icode].genfun) (op[0]);
10123 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10126 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10129 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10132 gcc_unreachable ();
10141 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
10143 rtx sel0 = const0_rtx;
10144 rtx sel1 = const1_rtx;
10145 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
10146 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10148 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10149 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10153 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
10155 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10157 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10158 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
10161 /* Return the class of registers for which a mode change from FROM to TO
10164 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
10165 enum reg_class class)
10167 /* We want to enable the use of SUBREGs as a means to
10168 VEC_SELECT a single element of a vector. */
10169 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10170 return (reg_classes_intersect_p (GENERAL_REGS, class));
10172 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10174 if (TARGET_LITTLE_ENDIAN)
10176 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10177 return reg_classes_intersect_p (DF_REGS, class);
10181 if (GET_MODE_SIZE (from) < 8)
10182 return reg_classes_intersect_p (DF_HI_REGS, class);
10189 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10190 that label is used. */
10193 sh_mark_label (rtx address, int nuses)
10195 if (GOTOFF_P (address))
10197 /* Extract the label or symbol. */
10198 address = XEXP (address, 0);
10199 if (GET_CODE (address) == PLUS)
10200 address = XEXP (address, 0);
10201 address = XVECEXP (address, 0, 0);
10203 if (GET_CODE (address) == LABEL_REF
10204 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
10205 LABEL_NUSES (XEXP (address, 0)) += nuses;
10208 /* Compute extra cost of moving data between one register class
10211 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10212 uses this information. Hence, the general register <-> floating point
10213 register information here is not used for SFmode. */
10216 sh_register_move_cost (enum machine_mode mode,
10217 enum reg_class srcclass, enum reg_class dstclass)
10219 if (dstclass == T_REGS || dstclass == PR_REGS)
10222 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10225 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
10226 && REGCLASS_HAS_FP_REG (srcclass)
10227 && REGCLASS_HAS_FP_REG (dstclass))
10230 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10231 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10233 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
10234 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
10237 if ((REGCLASS_HAS_FP_REG (dstclass)
10238 && REGCLASS_HAS_GENERAL_REG (srcclass))
10239 || (REGCLASS_HAS_GENERAL_REG (dstclass)
10240 && REGCLASS_HAS_FP_REG (srcclass)))
10241 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
10242 * ((GET_MODE_SIZE (mode) + 7) / 8U));
10244 if ((dstclass == FPUL_REGS
10245 && REGCLASS_HAS_GENERAL_REG (srcclass))
10246 || (srcclass == FPUL_REGS
10247 && REGCLASS_HAS_GENERAL_REG (dstclass)))
10250 if ((dstclass == FPUL_REGS
10251 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
10252 || (srcclass == FPUL_REGS
10253 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
10256 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10257 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10260 /* ??? ptabs faults on (value & 0x3) == 0x3 */
10262 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
10264 if (sh_gettrcost >= 0)
10265 return sh_gettrcost;
10266 else if (!TARGET_PT_FIXED)
10270 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10271 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10276 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
10277 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
10278 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
10280 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
10283 static rtx emit_load_ptr (rtx, rtx);
10286 emit_load_ptr (rtx reg, rtx addr)
10288 rtx mem = gen_const_mem (ptr_mode, addr);
10290 if (Pmode != ptr_mode)
10291 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
10292 return emit_move_insn (reg, mem);
10296 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10297 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10300 CUMULATIVE_ARGS cum;
10301 int structure_value_byref = 0;
10302 rtx this, this_value, sibcall, insns, funexp;
10303 tree funtype = TREE_TYPE (function);
10304 int simple_add = CONST_OK_FOR_ADD (delta);
10306 rtx scratch0, scratch1, scratch2;
10309 reload_completed = 1;
10310 epilogue_completed = 1;
10311 current_function_uses_only_leaf_regs = 1;
10313 emit_note (NOTE_INSN_PROLOGUE_END);
10315 /* Find the "this" pointer. We have such a wide range of ABIs for the
10316 SH that it's best to do this completely machine independently.
10317 "this" is passed as first argument, unless a structure return pointer
10318 comes first, in which case "this" comes second. */
10319 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
10320 #ifndef PCC_STATIC_STRUCT_RETURN
10321 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10322 structure_value_byref = 1;
10323 #endif /* not PCC_STATIC_STRUCT_RETURN */
10324 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
10326 tree ptype = build_pointer_type (TREE_TYPE (funtype));
10328 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
10330 this = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
10332 /* For SHcompact, we only have r0 for a scratch register: r1 is the
10333 static chain pointer (even if you can't have nested virtual functions
10334 right now, someone might implement them sometime), and the rest of the
10335 registers are used for argument passing, are callee-saved, or reserved. */
10336 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
10337 -ffixed-reg has been used. */
10338 if (! call_used_regs[0] || fixed_regs[0])
10339 error ("r0 needs to be available as a call-clobbered register");
10340 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
10343 if (call_used_regs[1] && ! fixed_regs[1])
10344 scratch1 = gen_rtx_REG (ptr_mode, 1);
10345 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
10346 pointing where to return struct values. */
10347 if (call_used_regs[3] && ! fixed_regs[3])
10348 scratch2 = gen_rtx_REG (Pmode, 3);
10350 else if (TARGET_SHMEDIA)
10352 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
10353 if (i != REGNO (scratch0) &&
10354 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
10356 scratch1 = gen_rtx_REG (ptr_mode, i);
10359 if (scratch1 == scratch0)
10360 error ("Need a second call-clobbered general purpose register");
10361 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
10362 if (call_used_regs[i] && ! fixed_regs[i])
10364 scratch2 = gen_rtx_REG (Pmode, i);
10367 if (scratch2 == scratch0)
10368 error ("Need a call-clobbered target register");
10371 this_value = plus_constant (this, delta);
10373 && (simple_add || scratch0 != scratch1)
10374 && strict_memory_address_p (ptr_mode, this_value))
10376 emit_load_ptr (scratch0, this_value);
10381 ; /* Do nothing. */
10382 else if (simple_add)
10383 emit_move_insn (this, this_value);
10386 emit_move_insn (scratch1, GEN_INT (delta));
10387 emit_insn (gen_add2_insn (this, scratch1));
10395 emit_load_ptr (scratch0, this);
10397 offset_addr = plus_constant (scratch0, vcall_offset);
10398 if (strict_memory_address_p (ptr_mode, offset_addr))
10399 ; /* Do nothing. */
10400 else if (! TARGET_SH5 && scratch0 != scratch1)
10402 /* scratch0 != scratch1, and we have indexed loads. Get better
10403 schedule by loading the offset into r1 and using an indexed
10404 load - then the load of r1 can issue before the load from
10405 (this + delta) finishes. */
10406 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10407 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
10409 else if (CONST_OK_FOR_ADD (vcall_offset))
10411 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
10412 offset_addr = scratch0;
10414 else if (scratch0 != scratch1)
10416 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10417 emit_insn (gen_add2_insn (scratch0, scratch1));
10418 offset_addr = scratch0;
10421 gcc_unreachable (); /* FIXME */
10422 emit_load_ptr (scratch0, offset_addr);
10424 if (Pmode != ptr_mode)
10425 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
10426 emit_insn (gen_add2_insn (this, scratch0));
10429 /* Generate a tail call to the target function. */
10430 if (! TREE_USED (function))
10432 assemble_external (function);
10433 TREE_USED (function) = 1;
10435 funexp = XEXP (DECL_RTL (function), 0);
10436 /* If the function is overridden, so is the thunk, hence we don't
10437 need GOT addressing even if this is a public symbol. */
10439 if (TARGET_SH1 && ! flag_weak)
10440 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
10443 if (TARGET_SH2 && flag_pic)
10445 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
10446 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
10450 if (TARGET_SHMEDIA && flag_pic)
10452 funexp = gen_sym2PIC (funexp);
10453 PUT_MODE (funexp, Pmode);
10455 emit_move_insn (scratch2, funexp);
10456 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
10457 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
10459 sibcall = emit_call_insn (sibcall);
10460 SIBLING_CALL_P (sibcall) = 1;
10461 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this);
10464 /* Run just enough of rest_of_compilation to do scheduling and get
10465 the insns emitted. Note that use_thunk calls
10466 assemble_start_function and assemble_end_function. */
10468 insn_locators_alloc ();
10469 insns = get_insns ();
10474 /* Initialize the bitmap obstacks. */
10475 bitmap_obstack_initialize (NULL);
10476 bitmap_obstack_initialize (®_obstack);
10479 rtl_register_cfg_hooks ();
10480 init_rtl_bb_info (ENTRY_BLOCK_PTR);
10481 init_rtl_bb_info (EXIT_BLOCK_PTR);
10482 ENTRY_BLOCK_PTR->flags |= BB_RTL;
10483 EXIT_BLOCK_PTR->flags |= BB_RTL;
10484 find_basic_blocks (insns);
10486 if (flag_schedule_insns_after_reload)
10488 life_analysis (PROP_FINAL);
10490 split_all_insns (1);
10494 /* We must split jmp insn in PIC case. */
10496 split_all_insns_noflow ();
10503 split_all_insns_noflow ();
10509 if (optimize > 0 && flag_delayed_branch)
10510 dbr_schedule (insns);
10512 shorten_branches (insns);
10513 final_start_function (insns, file, 1);
10514 final (insns, file, 1);
10515 final_end_function ();
10517 reload_completed = 0;
10518 epilogue_completed = 0;
10522 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
10526 /* If this is not an ordinary function, the name usually comes from a
10527 string literal or an sprintf buffer. Make sure we use the same
10528 string consistently, so that cse will be able to unify address loads. */
10529 if (kind != FUNCTION_ORDINARY)
10530 name = IDENTIFIER_POINTER (get_identifier (name));
10531 sym = gen_rtx_SYMBOL_REF (Pmode, name);
10532 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
10536 case FUNCTION_ORDINARY:
10540 rtx reg = target ? target : gen_reg_rtx (Pmode);
10542 emit_insn (gen_symGOT2reg (reg, sym));
10548 /* ??? To allow cse to work, we use GOTOFF relocations.
10549 we could add combiner patterns to transform this into
10550 straight pc-relative calls with sym2PIC / bsrf when
10551 label load and function call are still 1:1 and in the
10552 same basic block during combine. */
10553 rtx reg = target ? target : gen_reg_rtx (Pmode);
10555 emit_insn (gen_symGOTOFF2reg (reg, sym));
10560 if (target && sym != target)
10562 emit_move_insn (target, sym);
10568 /* Find the number of a general purpose register in S. */
10570 scavenge_reg (HARD_REG_SET *s)
10573 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
10574 if (TEST_HARD_REG_BIT (*s, r))
10580 sh_get_pr_initial_val (void)
10584 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
10585 PR register on SHcompact, because it might be clobbered by the prologue.
10586 We check first if that is known to be the case. */
10587 if (TARGET_SHCOMPACT
10588 && ((current_function_args_info.call_cookie
10589 & ~ CALL_COOKIE_RET_TRAMP (1))
10590 || current_function_saves_all_registers))
10591 return gen_frame_mem (SImode, return_address_pointer_rtx);
10593 /* If we haven't finished rtl generation, there might be a nonlocal label
10594 that we haven't seen yet.
10595 ??? get_hard_reg_initial_val fails if it is called after register
10596 allocation has started, unless it has been called before for the
10597 same register. And even then, we end in trouble if we didn't use
10598 the register in the same basic block before. So call
10599 get_hard_reg_initial_val now and wrap it in an unspec if we might
10600 need to replace it. */
10601 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
10602 combine can put the pseudo returned by get_hard_reg_initial_val into
10603 instructions that need a general purpose registers, which will fail to
10604 be recognized when the pseudo becomes allocated to PR. */
10606 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
10608 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
10613 sh_expand_t_scc (enum rtx_code code, rtx target)
10615 rtx result = target;
10618 if (GET_CODE (sh_compare_op0) != REG || REGNO (sh_compare_op0) != T_REG
10619 || GET_CODE (sh_compare_op1) != CONST_INT)
10621 if (GET_CODE (result) != REG)
10622 result = gen_reg_rtx (SImode);
10623 val = INTVAL (sh_compare_op1);
10624 if ((code == EQ && val == 1) || (code == NE && val == 0))
10625 emit_insn (gen_movt (result));
10626 else if (TARGET_SH2A && ((code == EQ && val == 0)
10627 || (code == NE && val == 1)))
10628 emit_insn (gen_movrt (result));
10629 else if ((code == EQ && val == 0) || (code == NE && val == 1))
10631 emit_insn (gen_rtx_CLOBBER (VOIDmode, result));
10632 emit_insn (gen_subc (result, result, result));
10633 emit_insn (gen_addsi3 (result, result, const1_rtx));
10635 else if (code == EQ || code == NE)
10636 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
10639 if (result != target)
10640 emit_move_insn (target, result);
10644 /* INSN is an sfunc; return the rtx that describes the address used. */
10646 extract_sfunc_addr (rtx insn)
10648 rtx pattern, part = NULL_RTX;
10651 pattern = PATTERN (insn);
10652 len = XVECLEN (pattern, 0);
10653 for (i = 0; i < len; i++)
10655 part = XVECEXP (pattern, 0, i);
10656 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
10657 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
10658 return XEXP (part, 0);
10660 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
10661 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
10664 /* Verify that the register in use_sfunc_addr still agrees with the address
10665 used in the sfunc. This prevents fill_slots_from_thread from changing
10667 INSN is the use_sfunc_addr instruction, and REG is the register it
10670 check_use_sfunc_addr (rtx insn, rtx reg)
10672 /* Search for the sfunc. It should really come right after INSN. */
10673 while ((insn = NEXT_INSN (insn)))
10675 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
10677 if (! INSN_P (insn))
10680 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
10681 insn = XVECEXP (PATTERN (insn), 0, 0);
10682 if (GET_CODE (PATTERN (insn)) != PARALLEL
10683 || get_attr_type (insn) != TYPE_SFUNC)
10685 return rtx_equal_p (extract_sfunc_addr (insn), reg);
10687 gcc_unreachable ();
10690 /* This function returns a constant rtx that represents pi / 2**15 in
10691 SFmode. it's used to scale SFmode angles, in radians, to a
10692 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
10693 maps to 0x10000). */
10695 static GTY(()) rtx sh_fsca_sf2int_rtx;
10698 sh_fsca_sf2int (void)
10700 if (! sh_fsca_sf2int_rtx)
10702 REAL_VALUE_TYPE rv;
10704 real_from_string (&rv, "10430.378350470453");
10705 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
10708 return sh_fsca_sf2int_rtx;
10711 /* This function returns a constant rtx that represents pi / 2**15 in
10712 DFmode. it's used to scale DFmode angles, in radians, to a
10713 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
10714 maps to 0x10000). */
10716 static GTY(()) rtx sh_fsca_df2int_rtx;
10719 sh_fsca_df2int (void)
10721 if (! sh_fsca_df2int_rtx)
10723 REAL_VALUE_TYPE rv;
10725 real_from_string (&rv, "10430.378350470453");
10726 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
10729 return sh_fsca_df2int_rtx;
10732 /* This function returns a constant rtx that represents 2**15 / pi in
10733 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
10734 of a full circle back to a SFmode value, i.e., 0x10000 maps to
10737 static GTY(()) rtx sh_fsca_int2sf_rtx;
10740 sh_fsca_int2sf (void)
10742 if (! sh_fsca_int2sf_rtx)
10744 REAL_VALUE_TYPE rv;
10746 real_from_string (&rv, "9.587379924285257e-5");
10747 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
10750 return sh_fsca_int2sf_rtx;
10753 /* Initialize the CUMULATIVE_ARGS structure. */
10756 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
10758 rtx libname ATTRIBUTE_UNUSED,
10760 signed int n_named_args,
10761 enum machine_mode mode)
10763 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
10764 pcum->free_single_fp_reg = 0;
10765 pcum->stack_regs = 0;
10766 pcum->byref_regs = 0;
10768 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
10770 /* XXX - Should we check TARGET_HITACHI here ??? */
10771 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
10775 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
10776 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
10777 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
10778 pcum->arg_count [(int) SH_ARG_INT]
10779 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
10782 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
10783 && pcum->arg_count [(int) SH_ARG_INT] == 0
10784 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
10785 ? int_size_in_bytes (TREE_TYPE (fntype))
10786 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
10787 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
10788 == FIRST_RET_REG));
10792 pcum->arg_count [(int) SH_ARG_INT] = 0;
10793 pcum->prototype_p = FALSE;
10794 if (mode != VOIDmode)
10796 pcum->call_cookie =
10797 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
10798 && GET_MODE_SIZE (mode) > 4
10799 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
10801 /* If the default ABI is the Renesas ABI then all library
10802 calls must assume that the library will be using the
10803 Renesas ABI. So if the function would return its result
10804 in memory then we must force the address of this memory
10805 block onto the stack. Ideally we would like to call
10806 targetm.calls.return_in_memory() here but we do not have
10807 the TYPE or the FNDECL available so we synthesize the
10808 contents of that function as best we can. */
10810 (TARGET_DEFAULT & MASK_HITACHI)
10811 && (mode == BLKmode
10812 || (GET_MODE_SIZE (mode) > 4
10813 && !(mode == DFmode
10814 && TARGET_FPU_DOUBLE)));
10818 pcum->call_cookie = 0;
10819 pcum->force_mem = FALSE;
10824 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
10825 not enter into CONST_DOUBLE for the replace.
10827 Note that copying is not done so X must not be shared unless all copies
10828 are to be modified.
10830 This is like replace_rtx, except that we operate on N_REPLACEMENTS
10831 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
10832 replacements[n*2+1] - and that we take mode changes into account.
10834 If a replacement is ambiguous, return NULL_RTX.
10836 If MODIFY is zero, don't modify any rtl in place,
10837 just return zero or nonzero for failure / success. */
10840 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
10845 /* The following prevents loops occurrence when we change MEM in
10846 CONST_DOUBLE onto the same CONST_DOUBLE. */
10847 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
10850 for (i = n_replacements - 1; i >= 0 ; i--)
10851 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
10852 return replacements[i*2+1];
10854 /* Allow this function to make replacements in EXPR_LISTs. */
10858 if (GET_CODE (x) == SUBREG)
10860 rtx new = replace_n_hard_rtx (SUBREG_REG (x), replacements,
10861 n_replacements, modify);
10863 if (GET_CODE (new) == CONST_INT)
10865 x = simplify_subreg (GET_MODE (x), new,
10866 GET_MODE (SUBREG_REG (x)),
10872 SUBREG_REG (x) = new;
10876 else if (GET_CODE (x) == REG)
10878 unsigned regno = REGNO (x);
10879 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
10880 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10881 rtx result = NULL_RTX;
10883 for (i = n_replacements - 1; i >= 0; i--)
10885 rtx from = replacements[i*2];
10886 rtx to = replacements[i*2+1];
10887 unsigned from_regno, from_nregs, to_regno, new_regno;
10889 if (GET_CODE (from) != REG)
10891 from_regno = REGNO (from);
10892 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
10893 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
10894 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
10896 if (regno < from_regno
10897 || regno + nregs > from_regno + nregs
10898 || GET_CODE (to) != REG
10901 to_regno = REGNO (to);
10902 if (to_regno < FIRST_PSEUDO_REGISTER)
10904 new_regno = regno + to_regno - from_regno;
10905 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
10908 result = gen_rtx_REG (GET_MODE (x), new_regno);
10910 else if (GET_MODE (x) <= GET_MODE (to))
10911 result = gen_lowpart_common (GET_MODE (x), to);
10913 result = gen_lowpart_SUBREG (GET_MODE (x), to);
10916 return result ? result : x;
10918 else if (GET_CODE (x) == ZERO_EXTEND)
10920 rtx new = replace_n_hard_rtx (XEXP (x, 0), replacements,
10921 n_replacements, modify);
10923 if (GET_CODE (new) == CONST_INT)
10925 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
10926 new, GET_MODE (XEXP (x, 0)));
10936 fmt = GET_RTX_FORMAT (GET_CODE (x));
10937 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
10943 new = replace_n_hard_rtx (XEXP (x, i), replacements,
10944 n_replacements, modify);
10950 else if (fmt[i] == 'E')
10951 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10953 new = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
10954 n_replacements, modify);
10958 XVECEXP (x, i, j) = new;
10966 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
10968 enum rtx_code code = TRUNCATE;
10970 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
10972 rtx inner = XEXP (x, 0);
10973 enum machine_mode inner_mode = GET_MODE (inner);
10975 if (inner_mode == mode)
10977 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
10979 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
10980 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
10982 code = GET_CODE (x);
10986 return gen_rtx_fmt_e (code, mode, x);
10989 /* called via for_each_rtx after reload, to clean up truncates of
10990 registers that span multiple actual hard registers. */
10992 shmedia_cleanup_truncate (rtx *p, void *n_changes)
10996 if (GET_CODE (x) != TRUNCATE)
10999 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && GET_CODE (reg) == REG)
11001 enum machine_mode reg_mode = GET_MODE (reg);
11002 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
11003 subreg_lowpart_offset (DImode, reg_mode));
11004 *(int*) n_changes += 1;
11010 /* Load and store depend on the highpart of the address. However,
11011 set_attr_alternative does not give well-defined results before reload,
11012 so we must look at the rtl ourselves to see if any of the feeding
11013 registers is used in a memref. */
11015 /* Called by sh_contains_memref_p via for_each_rtx. */
11017 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
11019 return (GET_CODE (*loc) == MEM);
11022 /* Return nonzero iff INSN contains a MEM. */
11024 sh_contains_memref_p (rtx insn)
11026 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11029 /* Return nonzero iff INSN loads a banked register. */
11031 sh_loads_bankedreg_p (rtx insn)
11033 if (GET_CODE (PATTERN (insn)) == SET)
11035 rtx op = SET_DEST (PATTERN(insn));
11036 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11043 /* FNADDR is the MEM expression from a call expander. Return an address
11044 to use in an SHmedia insn pattern. */
11046 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11050 fnaddr = XEXP (fnaddr, 0);
11051 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11052 if (flag_pic && is_sym)
11054 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11056 rtx reg = gen_reg_rtx (Pmode);
11058 /* We must not use GOTPLT for sibcalls, because PIC_REG
11059 must be restored before the PLT code gets to run. */
11061 emit_insn (gen_symGOT2reg (reg, fnaddr));
11063 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11068 fnaddr = gen_sym2PIC (fnaddr);
11069 PUT_MODE (fnaddr, Pmode);
11072 /* If ptabs might trap, make this visible to the rest of the compiler.
11073 We generally assume that symbols pertain to valid locations, but
11074 it is possible to generate invalid symbols with asm or linker tricks.
11075 In a list of functions where each returns its successor, an invalid
11076 symbol might denote an empty list. */
11077 if (!TARGET_PT_FIXED
11078 && (!is_sym || TARGET_INVALID_SYMBOLS)
11079 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11081 rtx tr = gen_reg_rtx (PDImode);
11083 emit_insn (gen_ptabs (tr, fnaddr));
11086 else if (! target_reg_operand (fnaddr, Pmode))
11087 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11092 sh_secondary_reload (bool in_p, rtx x, enum reg_class class,
11093 enum machine_mode mode, secondary_reload_info *sri)
11097 if (REGCLASS_HAS_FP_REG (class)
11098 && ! TARGET_SHMEDIA
11099 && immediate_operand ((x), mode)
11100 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11101 && mode == SFmode && fldi_ok ()))
11105 sri->icode = CODE_FOR_reload_insf__frn;
11108 sri->icode = CODE_FOR_reload_indf__frn;
11111 /* ??? If we knew that we are in the appropriate mode -
11112 single precision - we could use a reload pattern directly. */
11117 if (class == FPUL_REGS
11118 && ((GET_CODE (x) == REG
11119 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11120 || REGNO (x) == T_REG))
11121 || GET_CODE (x) == PLUS))
11122 return GENERAL_REGS;
11123 if (class == FPUL_REGS && immediate_operand (x, mode))
11125 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11126 return GENERAL_REGS;
11127 else if (mode == SFmode)
11129 sri->icode = CODE_FOR_reload_insi__i_fpul;
11132 if (class == FPSCR_REGS
11133 && ((GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11134 || (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PLUS)))
11135 return GENERAL_REGS;
11136 if (REGCLASS_HAS_FP_REG (class)
11138 && immediate_operand (x, mode)
11139 && x != CONST0_RTX (GET_MODE (x))
11140 && GET_MODE (x) != V4SFmode)
11141 return GENERAL_REGS;
11142 if ((mode == QImode || mode == HImode)
11143 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11145 sri->icode = ((mode == QImode)
11146 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11149 if (TARGET_SHMEDIA && class == GENERAL_REGS
11150 && (GET_CODE (x) == LABEL_REF || PIC_DIRECT_ADDR_P (x)))
11151 return TARGET_REGS;
11152 } /* end of input-only processing. */
11154 if (((REGCLASS_HAS_FP_REG (class)
11155 && (GET_CODE (x) == REG
11156 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11157 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11158 && TARGET_FMOVD))))
11159 || (REGCLASS_HAS_GENERAL_REG (class)
11160 && GET_CODE (x) == REG
11161 && FP_REGISTER_P (REGNO (x))))
11162 && ! TARGET_SHMEDIA
11163 && (mode == SFmode || mode == SImode))
11165 if ((class == FPUL_REGS
11166 || (REGCLASS_HAS_FP_REG (class)
11167 && ! TARGET_SHMEDIA && mode == SImode))
11168 && (GET_CODE (x) == MEM
11169 || (GET_CODE (x) == REG
11170 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11171 || REGNO (x) == T_REG
11172 || system_reg_operand (x, VOIDmode)))))
11174 if (class == FPUL_REGS)
11175 return GENERAL_REGS;
11178 if ((class == TARGET_REGS
11179 || (TARGET_SHMEDIA && class == SIBCALL_REGS))
11180 && !satisfies_constraint_Csy (x)
11181 && (GET_CODE (x) != REG || ! GENERAL_REGISTER_P (REGNO (x))))
11182 return GENERAL_REGS;
11183 if ((class == MAC_REGS || class == PR_REGS)
11184 && GET_CODE (x) == REG && ! GENERAL_REGISTER_P (REGNO (x))
11185 && class != REGNO_REG_CLASS (REGNO (x)))
11186 return GENERAL_REGS;
11187 if (class != GENERAL_REGS && GET_CODE (x) == REG
11188 && TARGET_REGISTER_P (REGNO (x)))
11189 return GENERAL_REGS;
11193 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;