1 /* Output routines for GCC for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
33 #include "hard-reg-set.h"
35 #include "insn-attr.h"
41 #include "target-def.h"
43 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
45 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
46 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
48 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
49 int current_function_interrupt;
51 /* ??? The pragma interrupt support will not work for SH3. */
52 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
53 output code for the next function appropriate for an interrupt handler. */
56 /* This is set by the trap_exit attribute for functions. It specifies
57 a trap number to be used in a trapa instruction at function exit
58 (instead of an rte instruction). */
61 /* This is used by the sp_switch attribute for functions. It specifies
62 a variable holding the address of the stack the interrupt function
63 should switch to/from at entry/exit. */
66 /* This is set by #pragma trapa, and is similar to the above, except that
67 the compiler doesn't emit code to preserve all registers. */
68 static int pragma_trapa;
70 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
71 which has a separate set of low regs for User and Supervisor modes.
72 This should only be used for the lowest level of interrupts. Higher levels
73 of interrupts must save the registers in case they themselves are
75 int pragma_nosave_low_regs;
77 /* This is used for communication between SETUP_INCOMING_VARARGS and
78 sh_expand_prologue. */
79 int current_function_anonymous_args;
81 /* Global variables for machine-dependent things. */
83 /* Which cpu are we scheduling for. */
84 enum processor_type sh_cpu;
86 /* Saved operands from the last compare to use when we generate an scc
92 /* Provides the class number of the smallest class containing
95 int regno_reg_class[FIRST_PSEUDO_REGISTER] =
97 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
98 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
99 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
100 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
101 GENERAL_REGS, PR_REGS, T_REGS, NO_REGS,
102 MAC_REGS, MAC_REGS, FPUL_REGS, GENERAL_REGS,
103 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
104 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
105 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
106 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
107 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
108 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
112 char fp_reg_names[][5] =
114 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
115 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
117 "xd0","xd2","xd4", "xd6", "xd8", "xd10", "xd12", "xd14",
120 /* Provide reg_class from a letter such as appears in the machine
123 enum reg_class reg_class_from_letter[] =
125 /* a */ ALL_REGS, /* b */ NO_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
126 /* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
127 /* i */ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
128 /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
129 /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
130 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
131 /* y */ FPUL_REGS, /* z */ R0_REGS
134 int assembler_dialect;
136 static void split_branches PARAMS ((rtx));
137 static int branch_dest PARAMS ((rtx));
138 static void force_into PARAMS ((rtx, rtx));
139 static void print_slot PARAMS ((rtx));
140 static rtx add_constant PARAMS ((rtx, enum machine_mode, rtx));
141 static void dump_table PARAMS ((rtx));
142 static int hi_const PARAMS ((rtx));
143 static int broken_move PARAMS ((rtx));
144 static int mova_p PARAMS ((rtx));
145 static rtx find_barrier PARAMS ((int, rtx, rtx));
146 static int noncall_uses_reg PARAMS ((rtx, rtx, rtx *));
147 static rtx gen_block_redirect PARAMS ((rtx, int, int));
148 static void output_stack_adjust PARAMS ((int, rtx, int));
149 static void push PARAMS ((int));
150 static void pop PARAMS ((int));
151 static void push_regs PARAMS ((int, int));
152 static int calc_live_regs PARAMS ((int *, int *));
153 static void mark_use PARAMS ((rtx, rtx *));
154 static HOST_WIDE_INT rounded_frame_size PARAMS ((int));
155 static rtx mark_constant_pool_use PARAMS ((rtx));
156 static int sh_valid_decl_attribute PARAMS ((tree, tree, tree, tree));
158 /* Initialize the GCC target structure. */
159 #undef TARGET_VALID_DECL_ATTRIBUTE
160 #define TARGET_VALID_DECL_ATTRIBUTE sh_valid_decl_attribute
162 struct gcc_target target = TARGET_INITIALIZER;
164 /* Print the operand address in x to the stream. */
167 print_operand_address (stream, x)
171 switch (GET_CODE (x))
175 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
180 rtx base = XEXP (x, 0);
181 rtx index = XEXP (x, 1);
183 switch (GET_CODE (index))
186 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
187 reg_names[true_regnum (base)]);
193 int base_num = true_regnum (base);
194 int index_num = true_regnum (index);
196 fprintf (stream, "@(r0,%s)",
197 reg_names[MAX (base_num, index_num)]);
209 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
213 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
217 x = mark_constant_pool_use (x);
218 output_addr_const (stream, x);
223 /* Print operand x (an rtx) in assembler syntax to file stream
224 according to modifier code.
226 '.' print a .s if insn needs delay slot
227 ',' print LOCAL_LABEL_PREFIX
228 '@' print trap, rte or rts depending upon pragma interruptness
229 '#' output a nop if there is nothing to put in the delay slot
230 'O' print a constant without the #
231 'R' print the LSW of a dp value - changes if in little endian
232 'S' print the MSW of a dp value - changes if in little endian
233 'T' print the next word of a dp value - same as 'R' in big endian mode.
234 'o' output an operator. */
237 print_operand (stream, x, code)
246 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
247 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
250 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
254 int interrupt_handler;
256 if ((lookup_attribute
257 ("interrupt_handler",
258 DECL_MACHINE_ATTRIBUTES (current_function_decl)))
260 interrupt_handler = 1;
262 interrupt_handler = 0;
265 fprintf (stream, "trapa #%d", trap_exit);
266 else if (interrupt_handler)
267 fprintf (stream, "rte");
269 fprintf (stream, "rts");
273 /* Output a nop if there's nothing in the delay slot. */
274 if (dbr_sequence_length () == 0)
275 fprintf (stream, "\n\tnop");
278 x = mark_constant_pool_use (x);
279 output_addr_const (stream, x);
282 fputs (reg_names[REGNO (x) + LSW], (stream));
285 fputs (reg_names[REGNO (x) + MSW], (stream));
288 /* Next word of a double. */
289 switch (GET_CODE (x))
292 fputs (reg_names[REGNO (x) + 1], (stream));
295 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
296 && GET_CODE (XEXP (x, 0)) != POST_INC)
297 x = adj_offsettable_operand (x, 4);
298 print_operand_address (stream, XEXP (x, 0));
305 switch (GET_CODE (x))
307 case PLUS: fputs ("add", stream); break;
308 case MINUS: fputs ("sub", stream); break;
309 case MULT: fputs ("mul", stream); break;
310 case DIV: fputs ("div", stream); break;
316 switch (GET_CODE (x))
319 if (FP_REGISTER_P (REGNO (x))
320 && GET_MODE_SIZE (GET_MODE (x)) > 4)
321 fprintf ((stream), "d%s", reg_names[REGNO (x)]+1);
323 fputs (reg_names[REGNO (x)], (stream));
326 output_address (XEXP (x, 0));
330 output_addr_const (stream, x);
337 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
339 force_into (value, target)
342 value = force_operand (value, target);
343 if (! rtx_equal_p (value, target))
344 emit_insn (gen_move_insn (target, value));
347 /* Emit code to perform a block move. Choose the best method.
349 OPERANDS[0] is the destination.
350 OPERANDS[1] is the source.
351 OPERANDS[2] is the size.
352 OPERANDS[3] is the alignment safe to use. */
355 expand_block_move (operands)
358 int align = INTVAL (operands[3]);
359 int constp = (GET_CODE (operands[2]) == CONST_INT);
360 int bytes = (constp ? INTVAL (operands[2]) : 0);
362 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
363 alignment, or if it isn't a multiple of 4 bytes, then fail. */
364 if (! constp || align < 4 || (bytes % 4 != 0))
371 else if (bytes == 12)
376 rtx r4 = gen_rtx (REG, SImode, 4);
377 rtx r5 = gen_rtx (REG, SImode, 5);
379 entry_name = get_identifier ("__movstrSI12_i4");
381 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
382 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
383 force_into (XEXP (operands[0], 0), r4);
384 force_into (XEXP (operands[1], 0), r5);
385 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
388 else if (! TARGET_SMALLCODE)
394 rtx r4 = gen_rtx (REG, SImode, 4);
395 rtx r5 = gen_rtx (REG, SImode, 5);
396 rtx r6 = gen_rtx (REG, SImode, 6);
398 entry_name = get_identifier (bytes & 4
400 : "__movstr_i4_even");
401 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
402 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
403 force_into (XEXP (operands[0], 0), r4);
404 force_into (XEXP (operands[1], 0), r5);
407 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
408 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
420 rtx r4 = gen_rtx_REG (SImode, 4);
421 rtx r5 = gen_rtx_REG (SImode, 5);
423 sprintf (entry, "__movstrSI%d", bytes);
424 entry_name = get_identifier (entry);
425 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
426 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
427 force_into (XEXP (operands[0], 0), r4);
428 force_into (XEXP (operands[1], 0), r5);
429 emit_insn (gen_block_move_real (func_addr_rtx));
433 /* This is the same number of bytes as a memcpy call, but to a different
434 less common function name, so this will occasionally use more space. */
435 if (! TARGET_SMALLCODE)
440 int final_switch, while_loop;
441 rtx r4 = gen_rtx_REG (SImode, 4);
442 rtx r5 = gen_rtx_REG (SImode, 5);
443 rtx r6 = gen_rtx_REG (SImode, 6);
445 entry_name = get_identifier ("__movstr");
446 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
447 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
448 force_into (XEXP (operands[0], 0), r4);
449 force_into (XEXP (operands[1], 0), r5);
451 /* r6 controls the size of the move. 16 is decremented from it
452 for each 64 bytes moved. Then the negative bit left over is used
453 as an index into a list of move instructions. e.g., a 72 byte move
454 would be set up with size(r6) = 14, for one iteration through the
455 big while loop, and a switch of -2 for the last part. */
457 final_switch = 16 - ((bytes / 4) % 16);
458 while_loop = ((bytes / 4) / 16 - 1) * 16;
459 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
460 emit_insn (gen_block_lump_real (func_addr_rtx));
467 /* Prepare operands for a move define_expand; specifically, one of the
468 operands must be in a register. */
471 prepare_move_operands (operands, mode)
473 enum machine_mode mode;
475 if (mode == SImode && flag_pic)
478 if (SYMBOLIC_CONST_P (operands[1]))
480 if (GET_CODE (operands[0]) == MEM)
481 operands[1] = force_reg (Pmode, operands[1]);
484 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
485 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
488 else if (GET_CODE (operands[1]) == CONST
489 && GET_CODE (XEXP (operands[1], 0)) == PLUS
490 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
492 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
493 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
495 operands[1] = expand_binop (SImode, add_optab, temp,
496 XEXP (XEXP (operands[1], 0), 1),
497 no_new_pseudos ? temp
498 : gen_reg_rtx (Pmode),
503 if (! reload_in_progress && ! reload_completed)
505 /* Copy the source to a register if both operands aren't registers. */
506 if (! register_operand (operands[0], mode)
507 && ! register_operand (operands[1], mode))
508 operands[1] = copy_to_mode_reg (mode, operands[1]);
510 /* This case can happen while generating code to move the result
511 of a library call to the target. Reject `st r0,@(rX,rY)' because
512 reload will fail to find a spill register for rX, since r0 is already
513 being used for the source. */
514 else if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 0
515 && GET_CODE (operands[0]) == MEM
516 && GET_CODE (XEXP (operands[0], 0)) == PLUS
517 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
518 operands[1] = copy_to_mode_reg (mode, operands[1]);
524 /* Prepare the operands for an scc instruction; make sure that the
525 compare has been done. */
527 prepare_scc_operands (code)
530 rtx t_reg = gen_rtx_REG (SImode, T_REG);
531 enum rtx_code oldcode = code;
532 enum machine_mode mode;
534 /* First need a compare insn. */
538 /* It isn't possible to handle this case. */
557 rtx tmp = sh_compare_op0;
558 sh_compare_op0 = sh_compare_op1;
559 sh_compare_op1 = tmp;
562 mode = GET_MODE (sh_compare_op0);
563 if (mode == VOIDmode)
564 mode = GET_MODE (sh_compare_op1);
566 sh_compare_op0 = force_reg (mode, sh_compare_op0);
567 if ((code != EQ && code != NE
568 && (sh_compare_op1 != const0_rtx
569 || code == GTU || code == GEU || code == LTU || code == LEU))
570 || (mode == DImode && sh_compare_op1 != const0_rtx)
571 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
572 sh_compare_op1 = force_reg (mode, sh_compare_op1);
574 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
575 (mode == SFmode ? emit_sf_insn : emit_df_insn)
576 (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
577 gen_rtx (SET, VOIDmode, t_reg,
578 gen_rtx (code, SImode,
579 sh_compare_op0, sh_compare_op1)),
580 gen_rtx (USE, VOIDmode, get_fpscr_rtx ()))));
582 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
583 gen_rtx (code, SImode, sh_compare_op0,
589 /* Called from the md file, set up the operands of a compare instruction. */
592 from_compare (operands, code)
596 enum machine_mode mode = GET_MODE (sh_compare_op0);
598 if (mode == VOIDmode)
599 mode = GET_MODE (sh_compare_op1);
602 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
604 /* Force args into regs, since we can't use constants here. */
605 sh_compare_op0 = force_reg (mode, sh_compare_op0);
606 if (sh_compare_op1 != const0_rtx
607 || code == GTU || code == GEU
608 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
609 sh_compare_op1 = force_reg (mode, sh_compare_op1);
611 if (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
613 from_compare (operands, GT);
614 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
617 insn = gen_rtx_SET (VOIDmode,
618 gen_rtx_REG (SImode, T_REG),
619 gen_rtx (code, SImode, sh_compare_op0,
621 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
623 insn = gen_rtx (PARALLEL, VOIDmode,
625 gen_rtx (USE, VOIDmode, get_fpscr_rtx ())));
626 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
632 /* Functions to output assembly code. */
634 /* Return a sequence of instructions to perform DI or DF move.
636 Since the SH cannot move a DI or DF in one instruction, we have
637 to take care when we see overlapping source and dest registers. */
640 output_movedouble (insn, operands, mode)
641 rtx insn ATTRIBUTE_UNUSED;
643 enum machine_mode mode;
645 rtx dst = operands[0];
646 rtx src = operands[1];
648 if (GET_CODE (dst) == MEM
649 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
650 return "mov.l %T1,%0\n\tmov.l %1,%0";
652 if (register_operand (dst, mode)
653 && register_operand (src, mode))
655 if (REGNO (src) == MACH_REG)
656 return "sts mach,%S0\n\tsts macl,%R0";
658 /* When mov.d r1,r2 do r2->r3 then r1->r2;
659 when mov.d r1,r0 do r1->r0 then r2->r1. */
661 if (REGNO (src) + 1 == REGNO (dst))
662 return "mov %T1,%T0\n\tmov %1,%0";
664 return "mov %1,%0\n\tmov %T1,%T0";
666 else if (GET_CODE (src) == CONST_INT)
668 if (INTVAL (src) < 0)
669 output_asm_insn ("mov #-1,%S0", operands);
671 output_asm_insn ("mov #0,%S0", operands);
675 else if (GET_CODE (src) == MEM)
678 int dreg = REGNO (dst);
679 rtx inside = XEXP (src, 0);
681 if (GET_CODE (inside) == REG)
682 ptrreg = REGNO (inside);
683 else if (GET_CODE (inside) == SUBREG)
684 ptrreg = subreg_regno (inside);
685 else if (GET_CODE (inside) == PLUS)
687 ptrreg = REGNO (XEXP (inside, 0));
688 /* ??? A r0+REG address shouldn't be possible here, because it isn't
689 an offsettable address. Unfortunately, offsettable addresses use
690 QImode to check the offset, and a QImode offsettable address
691 requires r0 for the other operand, which is not currently
692 supported, so we can't use the 'o' constraint.
693 Thus we must check for and handle r0+REG addresses here.
694 We punt for now, since this is likely very rare. */
695 if (GET_CODE (XEXP (inside, 1)) == REG)
698 else if (GET_CODE (inside) == LABEL_REF)
699 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
700 else if (GET_CODE (inside) == POST_INC)
701 return "mov.l %1,%0\n\tmov.l %1,%T0";
705 /* Work out the safe way to copy. Copy into the second half first. */
707 return "mov.l %T1,%T0\n\tmov.l %1,%0";
710 return "mov.l %1,%0\n\tmov.l %T1,%T0";
713 /* Print an instruction which would have gone into a delay slot after
714 another instruction, but couldn't because the other instruction expanded
715 into a sequence where putting the slot insn at the end wouldn't work. */
721 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
723 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
727 output_far_jump (insn, op)
731 struct { rtx lab, reg, op; } this;
735 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
737 this.lab = gen_label_rtx ();
741 && offset - get_attr_length (insn) <= 32766)
744 jump = "mov.w %O0,%1; braf %1";
752 jump = "mov.l %O0,%1; braf %1";
754 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
757 jump = "mov.l %O0,%1; jmp @%1";
759 /* If we have a scratch register available, use it. */
760 if (GET_CODE (PREV_INSN (insn)) == INSN
761 && INSN_CODE (PREV_INSN (insn)) == CODE_FOR_indirect_jump_scratch)
763 this.reg = SET_DEST (PATTERN (PREV_INSN (insn)));
764 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
765 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
766 output_asm_insn (jump, &this.lab);
767 if (dbr_sequence_length ())
768 print_slot (final_sequence);
770 output_asm_insn ("nop", 0);
774 /* Output the delay slot insn first if any. */
775 if (dbr_sequence_length ())
776 print_slot (final_sequence);
778 this.reg = gen_rtx_REG (SImode, 13);
779 output_asm_insn ("mov.l r13,@-r15", 0);
780 output_asm_insn (jump, &this.lab);
781 output_asm_insn ("mov.l @r15+,r13", 0);
783 if (far && flag_pic && TARGET_SH2)
785 braf_base_lab = gen_label_rtx ();
786 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
787 CODE_LABEL_NUMBER (braf_base_lab));
790 output_asm_insn (".align 2", 0);
791 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
796 this.lab = braf_base_lab;
797 output_asm_insn (".long %O2-%O0", &this.lab);
800 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
804 /* Local label counter, used for constants in the pool and inside
809 /* Output code for ordinary branches. */
812 output_branch (logic, insn, operands)
817 switch (get_attr_length (insn))
820 /* This can happen if filling the delay slot has caused a forward
821 branch to exceed its range (we could reverse it, but only
822 when we know we won't overextend other branches; this should
823 best be handled by relaxation).
824 It can also happen when other condbranches hoist delay slot insn
825 from their destination, thus leading to code size increase.
826 But the branch will still be in the range -4092..+4098 bytes. */
831 /* The call to print_slot will clobber the operands. */
832 rtx op0 = operands[0];
834 /* If the instruction in the delay slot is annulled (true), then
835 there is no delay slot where we can put it now. The only safe
836 place for it is after the label. final will do that by default. */
839 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
841 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
842 ASSEMBLER_DIALECT ? "/" : ".", label);
843 print_slot (final_sequence);
846 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
848 output_asm_insn ("bra\t%l0", &op0);
849 fprintf (asm_out_file, "\tnop\n");
850 ASM_OUTPUT_INTERNAL_LABEL(asm_out_file, "LF", label);
854 /* When relaxing, handle this like a short branch. The linker
855 will fix it up if it still doesn't fit after relaxation. */
857 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
859 /* There should be no longer branches now - that would
860 indicate that something has destroyed the branches set
861 up in machine_dependent_reorg. */
867 output_branchy_insn (code, template, insn, operands)
869 const char *template;
873 rtx next_insn = NEXT_INSN (insn);
875 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
877 rtx src = SET_SRC (PATTERN (next_insn));
878 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
880 /* Following branch not taken */
881 operands[9] = gen_label_rtx ();
882 emit_label_after (operands[9], next_insn);
883 INSN_ADDRESSES_NEW (operands[9],
884 INSN_ADDRESSES (INSN_UID (next_insn))
885 + get_attr_length (next_insn));
890 int offset = (branch_dest (next_insn)
891 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
892 if (offset >= -252 && offset <= 258)
894 if (GET_CODE (src) == IF_THEN_ELSE)
902 operands[9] = gen_label_rtx ();
903 emit_label_after (operands[9], insn);
904 INSN_ADDRESSES_NEW (operands[9],
905 INSN_ADDRESSES (INSN_UID (insn))
906 + get_attr_length (insn));
911 output_ieee_ccmpeq (insn, operands)
914 return output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
917 /* Output to FILE the start of the assembler file. */
920 output_file_start (file)
923 output_file_directive (file, main_input_filename);
925 /* Switch to the data section so that the coffsem symbol
926 isn't in the text section. */
929 if (TARGET_LITTLE_ENDIAN)
930 fprintf (file, "\t.little\n");
933 /* Actual number of instructions used to make a shift by N. */
934 static char ashiftrt_insns[] =
935 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
937 /* Left shift and logical right shift are the same. */
938 static char shift_insns[] =
939 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
941 /* Individual shift amounts needed to get the above length sequences.
942 One bit right shifts clobber the T bit, so when possible, put one bit
943 shifts in the middle of the sequence, so the ends are eligible for
944 branch delay slots. */
945 static short shift_amounts[32][5] = {
946 {0}, {1}, {2}, {2, 1},
947 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
948 {8}, {8, 1}, {8, 2}, {8, 1, 2},
949 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
950 {16}, {16, 1}, {16, 2}, {16, 1, 2},
951 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
952 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
953 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
955 /* Likewise, but for shift amounts < 16, up to three highmost bits
956 might be clobbered. This is typically used when combined with some
957 kind of sign or zero extension. */
959 static char ext_shift_insns[] =
960 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
962 static short ext_shift_amounts[32][4] = {
963 {0}, {1}, {2}, {2, 1},
964 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
965 {8}, {8, 1}, {8, 2}, {8, 1, 2},
966 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
967 {16}, {16, 1}, {16, 2}, {16, 1, 2},
968 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
969 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
970 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
972 /* Assuming we have a value that has been sign-extended by at least one bit,
973 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
974 to shift it by N without data loss, and quicker than by other means? */
975 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
977 /* This is used in length attributes in sh.md to help compute the length
978 of arbitrary constant shift instructions. */
981 shift_insns_rtx (insn)
984 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
985 int shift_count = INTVAL (XEXP (set_src, 1));
986 enum rtx_code shift_code = GET_CODE (set_src);
991 return ashiftrt_insns[shift_count];
994 return shift_insns[shift_count];
1000 /* Return the cost of a shift. */
1008 /* If shift by a non constant, then this will be expensive. */
1009 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1010 return SH_DYNAMIC_SHIFT_COST;
1012 value = INTVAL (XEXP (x, 1));
1014 /* Otherwise, return the true cost in instructions. */
1015 if (GET_CODE (x) == ASHIFTRT)
1017 int cost = ashiftrt_insns[value];
1018 /* If SH3, then we put the constant in a reg and use shad. */
1019 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
1020 cost = 1 + SH_DYNAMIC_SHIFT_COST;
1024 return shift_insns[value];
1027 /* Return the cost of an AND operation. */
1035 /* Anding with a register is a single cycle and instruction. */
1036 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1039 i = INTVAL (XEXP (x, 1));
1040 /* These constants are single cycle extu.[bw] instructions. */
1041 if (i == 0xff || i == 0xffff)
1043 /* Constants that can be used in an and immediate instruction is a single
1044 cycle, but this requires r0, so make it a little more expensive. */
1045 if (CONST_OK_FOR_L (i))
1047 /* Constants that can be loaded with a mov immediate and an and.
1048 This case is probably unnecessary. */
1049 if (CONST_OK_FOR_I (i))
1051 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1052 This case is probably unnecessary. */
1056 /* Return the cost of an addition or a subtraction. */
1062 /* Adding a register is a single cycle insn. */
1063 if (GET_CODE (XEXP (x, 1)) == REG
1064 || GET_CODE (XEXP (x, 1)) == SUBREG)
1067 /* Likewise for small constants. */
1068 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1069 && CONST_OK_FOR_I (INTVAL (XEXP (x, 1))))
1072 /* Any other constant requires a 2 cycle pc-relative load plus an
1077 /* Return the cost of a multiply. */
1080 rtx x ATTRIBUTE_UNUSED;
1084 /* We have a mul insn, so we can never take more than the mul and the
1085 read of the mac reg, but count more because of the latency and extra
1087 if (TARGET_SMALLCODE)
1092 /* If we're aiming at small code, then just count the number of
1093 insns in a multiply call sequence. */
1094 if (TARGET_SMALLCODE)
1097 /* Otherwise count all the insns in the routine we'd be calling too. */
1101 /* Code to expand a shift. */
1104 gen_ashift (type, n, reg)
1109 /* Negative values here come from the shift_amounts array. */
1122 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
1126 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
1128 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
1131 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
1136 /* Same for HImode */
1139 gen_ashift_hi (type, n, reg)
1144 /* Negative values here come from the shift_amounts array. */
1158 /* We don't have HImode right shift operations because using the
1159 ordinary 32 bit shift instructions for that doesn't generate proper
1160 zero/sign extension.
1161 gen_ashift_hi is only called in contexts where we know that the
1162 sign extension works out correctly. */
1165 if (GET_CODE (reg) == SUBREG)
1167 offset = SUBREG_BYTE (reg);
1168 reg = SUBREG_REG (reg);
1170 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
1174 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
1179 /* Output RTL to split a constant shift into its component SH constant
1180 shift instructions. */
1183 gen_shifty_op (code, operands)
1187 int value = INTVAL (operands[2]);
1190 /* Truncate the shift count in case it is out of bounds. */
1191 value = value & 0x1f;
1195 if (code == LSHIFTRT)
1197 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1198 emit_insn (gen_movt (operands[0]));
1201 else if (code == ASHIFT)
1203 /* There is a two instruction sequence for 31 bit left shifts,
1204 but it requires r0. */
1205 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
1207 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
1208 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1213 else if (value == 0)
1215 /* This can happen when not optimizing. We must output something here
1216 to prevent the compiler from aborting in final.c after the try_split
1218 emit_insn (gen_nop ());
1222 max = shift_insns[value];
1223 for (i = 0; i < max; i++)
1224 gen_ashift (code, shift_amounts[value][i], operands[0]);
1227 /* Same as above, but optimized for values where the topmost bits don't
1231 gen_shifty_hi_op (code, operands)
1235 int value = INTVAL (operands[2]);
1237 void (*gen_fun) PARAMS ((int, int, rtx));
1239 /* This operation is used by and_shl for SImode values with a few
1240 high bits known to be cleared. */
1244 emit_insn (gen_nop ());
1248 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
1251 max = ext_shift_insns[value];
1252 for (i = 0; i < max; i++)
1253 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1256 /* When shifting right, emit the shifts in reverse order, so that
1257 solitary negative values come first. */
1258 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
1259 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1262 /* Output RTL for an arithmetic right shift. */
1264 /* ??? Rewrite to use super-optimizer sequences. */
1267 expand_ashiftrt (operands)
1278 if (GET_CODE (operands[2]) != CONST_INT)
1280 rtx count = copy_to_mode_reg (SImode, operands[2]);
1281 emit_insn (gen_negsi2 (count, count));
1282 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1285 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
1286 > 1 + SH_DYNAMIC_SHIFT_COST)
1289 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
1290 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1294 if (GET_CODE (operands[2]) != CONST_INT)
1297 value = INTVAL (operands[2]) & 31;
1301 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
1304 else if (value >= 16 && value <= 19)
1306 wrk = gen_reg_rtx (SImode);
1307 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
1310 gen_ashift (ASHIFTRT, 1, wrk);
1311 emit_move_insn (operands[0], wrk);
1314 /* Expand a short sequence inline, longer call a magic routine. */
1315 else if (value <= 5)
1317 wrk = gen_reg_rtx (SImode);
1318 emit_move_insn (wrk, operands[1]);
1320 gen_ashift (ASHIFTRT, 1, wrk);
1321 emit_move_insn (operands[0], wrk);
1325 wrk = gen_reg_rtx (Pmode);
1327 /* Load the value into an arg reg and call a helper. */
1328 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1329 sprintf (func, "__ashiftrt_r4_%d", value);
1330 func_name = get_identifier (func);
1331 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (func_name));
1332 emit_move_insn (wrk, sym);
1333 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1334 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
1339 sh_dynamicalize_shift_p (count)
1342 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
1345 /* Try to find a good way to implement the combiner pattern
1346 [(set (match_operand:SI 0 "register_operand" "r")
1347 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1348 (match_operand:SI 2 "const_int_operand" "n"))
1349 (match_operand:SI 3 "const_int_operand" "n"))) .
1350 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1351 return 0 for simple right / left or left/right shift combination.
1352 return 1 for a combination of shifts with zero_extend.
1353 return 2 for a combination of shifts with an AND that needs r0.
1354 return 3 for a combination of shifts with an AND that needs an extra
1355 scratch register, when the three highmost bits of the AND mask are clear.
1356 return 4 for a combination of shifts with an AND that needs an extra
1357 scratch register, when any of the three highmost bits of the AND mask
1359 If ATTRP is set, store an initial right shift width in ATTRP[0],
1360 and the instruction length in ATTRP[1] . These values are not valid
1362 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1363 shift_amounts for the last shift value that is to be used before the
1366 shl_and_kind (left_rtx, mask_rtx, attrp)
1367 rtx left_rtx, mask_rtx;
1370 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
1371 int left = INTVAL (left_rtx), right;
1373 int cost, best_cost = 10000;
1374 int best_right = 0, best_len = 0;
1378 if (left < 0 || left > 31)
1380 if (GET_CODE (mask_rtx) == CONST_INT)
1381 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
1383 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
1384 /* Can this be expressed as a right shift / left shift pair ? */
1385 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
1386 right = exact_log2 (lsb);
1387 mask2 = ~(mask + lsb - 1);
1388 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
1389 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1391 best_cost = shift_insns[right] + shift_insns[right + left];
1392 /* mask has no trailing zeroes <==> ! right */
1393 else if (! right && mask2 == ~(lsb2 - 1))
1395 int late_right = exact_log2 (lsb2);
1396 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
1398 /* Try to use zero extend */
1399 if (mask2 == ~(lsb2 - 1))
1403 for (width = 8; width <= 16; width += 8)
1405 /* Can we zero-extend right away? */
1406 if (lsb2 == (unsigned HOST_WIDE_INT)1 << width)
1409 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
1410 if (cost < best_cost)
1421 /* ??? Could try to put zero extend into initial right shift,
1422 or even shift a bit left before the right shift. */
1423 /* Determine value of first part of left shift, to get to the
1424 zero extend cut-off point. */
1425 first = width - exact_log2 (lsb2) + right;
1426 if (first >= 0 && right + left - first >= 0)
1428 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
1429 + ext_shift_insns[right + left - first];
1430 if (cost < best_cost)
1442 /* Try to use r0 AND pattern */
1443 for (i = 0; i <= 2; i++)
1447 if (! CONST_OK_FOR_L (mask >> i))
1449 cost = (i != 0) + 2 + ext_shift_insns[left + i];
1450 if (cost < best_cost)
1455 best_len = cost - 1;
1458 /* Try to use a scratch register to hold the AND operand. */
1459 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT)3 << 30)) == 0;
1460 for (i = 0; i <= 2; i++)
1464 cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3)
1465 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
1466 if (cost < best_cost)
1471 best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i);
1477 attrp[0] = best_right;
1478 attrp[1] = best_len;
1483 /* This is used in length attributes of the unnamed instructions
1484 corresponding to shl_and_kind return values of 1 and 2. */
1486 shl_and_length (insn)
1489 rtx set_src, left_rtx, mask_rtx;
1492 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1493 left_rtx = XEXP (XEXP (set_src, 0), 1);
1494 mask_rtx = XEXP (set_src, 1);
1495 shl_and_kind (left_rtx, mask_rtx, attributes);
1496 return attributes[1];
1499 /* This is used in length attribute of the and_shl_scratch instruction. */
1502 shl_and_scr_length (insn)
1505 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1506 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
1507 rtx op = XEXP (set_src, 0);
1508 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
1509 op = XEXP (XEXP (op, 0), 0);
1510 return len + shift_insns[INTVAL (XEXP (op, 1))];
1513 /* Generating rtl? */
1514 extern int rtx_equal_function_value_matters;
1516 /* Generate rtl for instructions for which shl_and_kind advised a particular
1517 method of generating them, i.e. returned zero. */
1520 gen_shl_and (dest, left_rtx, mask_rtx, source)
1521 rtx dest, left_rtx, mask_rtx, source;
1524 unsigned HOST_WIDE_INT mask;
1525 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
1526 int right, total_shift;
1527 void (*shift_gen_fun) PARAMS ((int, rtx*)) = gen_shifty_hi_op;
1529 right = attributes[0];
1530 total_shift = INTVAL (left_rtx) + right;
1531 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
1538 int first = attributes[2];
1543 emit_insn ((mask << right) <= 0xff
1544 ? gen_zero_extendqisi2(dest,
1545 gen_lowpart (QImode, source))
1546 : gen_zero_extendhisi2(dest,
1547 gen_lowpart (HImode, source)));
1551 emit_insn (gen_movsi (dest, source));
1555 operands[2] = GEN_INT (right);
1556 gen_shifty_hi_op (LSHIFTRT, operands);
1560 operands[2] = GEN_INT (first);
1561 gen_shifty_hi_op (ASHIFT, operands);
1562 total_shift -= first;
1566 emit_insn (mask <= 0xff
1567 ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
1568 : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
1569 if (total_shift > 0)
1571 operands[2] = GEN_INT (total_shift);
1572 gen_shifty_hi_op (ASHIFT, operands);
1577 shift_gen_fun = gen_shifty_op;
1579 /* If the topmost bit that matters is set, set the topmost bits
1580 that don't matter. This way, we might be able to get a shorter
1582 if (mask & ((HOST_WIDE_INT)1 << (31 - total_shift)))
1583 mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
1585 /* Don't expand fine-grained when combining, because that will
1586 make the pattern fail. */
1587 if (rtx_equal_function_value_matters
1588 || reload_in_progress || reload_completed)
1592 /* Cases 3 and 4 should be handled by this split
1593 only while combining */
1598 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
1601 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
1606 operands[2] = GEN_INT (total_shift);
1607 shift_gen_fun (ASHIFT, operands);
1614 if (kind != 4 && total_shift < 16)
1616 neg = -ext_shift_amounts[total_shift][1];
1618 neg -= ext_shift_amounts[total_shift][2];
1622 emit_insn (gen_and_shl_scratch (dest, source,
1625 GEN_INT (total_shift + neg),
1627 emit_insn (gen_movsi (dest, dest));
1634 /* Try to find a good way to implement the combiner pattern
1635 [(set (match_operand:SI 0 "register_operand" "=r")
1636 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1637 (match_operand:SI 2 "const_int_operand" "n")
1638 (match_operand:SI 3 "const_int_operand" "n")
1640 (clobber (reg:SI T_REG))]
1641 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
1642 return 0 for simple left / right shift combination.
1643 return 1 for left shift / 8 bit sign extend / left shift.
1644 return 2 for left shift / 16 bit sign extend / left shift.
1645 return 3 for left shift / 8 bit sign extend / shift / sign extend.
1646 return 4 for left shift / 16 bit sign extend / shift / sign extend.
1647 return 5 for left shift / 16 bit sign extend / right shift
1648 return 6 for < 8 bit sign extend / left shift.
1649 return 7 for < 8 bit sign extend / left shift / single right shift.
1650 If COSTP is nonzero, assign the calculated cost to *COSTP. */
1653 shl_sext_kind (left_rtx, size_rtx, costp)
1654 rtx left_rtx, size_rtx;
1657 int left, size, insize, ext;
1658 int cost, best_cost;
1661 left = INTVAL (left_rtx);
1662 size = INTVAL (size_rtx);
1663 insize = size - left;
1666 /* Default to left / right shift. */
1668 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
1671 /* 16 bit shift / sign extend / 16 bit shift */
1672 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
1673 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
1674 below, by alternative 3 or something even better. */
1675 if (cost < best_cost)
1681 /* Try a plain sign extend between two shifts. */
1682 for (ext = 16; ext >= insize; ext -= 8)
1686 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
1687 if (cost < best_cost)
1693 /* Check if we can do a sloppy shift with a final signed shift
1694 restoring the sign. */
1695 if (EXT_SHIFT_SIGNED (size - ext))
1696 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
1697 /* If not, maybe it's still cheaper to do the second shift sloppy,
1698 and do a final sign extend? */
1699 else if (size <= 16)
1700 cost = ext_shift_insns[ext - insize] + 1
1701 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
1704 if (cost < best_cost)
1706 kind = ext / 8U + 2;
1710 /* Check if we can sign extend in r0 */
1713 cost = 3 + shift_insns[left];
1714 if (cost < best_cost)
1719 /* Try the same with a final signed shift. */
1722 cost = 3 + ext_shift_insns[left + 1] + 1;
1723 if (cost < best_cost)
1732 /* Try to use a dynamic shift. */
1733 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
1734 if (cost < best_cost)
1745 /* Function to be used in the length attribute of the instructions
1746 implementing this pattern. */
1749 shl_sext_length (insn)
1752 rtx set_src, left_rtx, size_rtx;
1755 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1756 left_rtx = XEXP (XEXP (set_src, 0), 1);
1757 size_rtx = XEXP (set_src, 1);
1758 shl_sext_kind (left_rtx, size_rtx, &cost);
1762 /* Generate rtl for this pattern */
1765 gen_shl_sext (dest, left_rtx, size_rtx, source)
1766 rtx dest, left_rtx, size_rtx, source;
1769 int left, size, insize, cost;
1772 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
1773 left = INTVAL (left_rtx);
1774 size = INTVAL (size_rtx);
1775 insize = size - left;
1783 int ext = kind & 1 ? 8 : 16;
1784 int shift2 = size - ext;
1786 /* Don't expand fine-grained when combining, because that will
1787 make the pattern fail. */
1788 if (! rtx_equal_function_value_matters
1789 && ! reload_in_progress && ! reload_completed)
1791 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
1792 emit_insn (gen_movsi (dest, source));
1796 emit_insn (gen_movsi (dest, source));
1800 operands[2] = GEN_INT (ext - insize);
1801 gen_shifty_hi_op (ASHIFT, operands);
1804 ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
1805 : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
1810 operands[2] = GEN_INT (shift2);
1811 gen_shifty_op (ASHIFT, operands);
1818 if (EXT_SHIFT_SIGNED (shift2))
1820 operands[2] = GEN_INT (shift2 + 1);
1821 gen_shifty_op (ASHIFT, operands);
1822 operands[2] = GEN_INT (1);
1823 gen_shifty_op (ASHIFTRT, operands);
1826 operands[2] = GEN_INT (shift2);
1827 gen_shifty_hi_op (ASHIFT, operands);
1831 operands[2] = GEN_INT (-shift2);
1832 gen_shifty_hi_op (LSHIFTRT, operands);
1834 emit_insn (size <= 8
1835 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
1836 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
1843 if (! rtx_equal_function_value_matters
1844 && ! reload_in_progress && ! reload_completed)
1845 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
1849 operands[2] = GEN_INT (16 - insize);
1850 gen_shifty_hi_op (ASHIFT, operands);
1851 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
1853 /* Don't use gen_ashrsi3 because it generates new pseudos. */
1855 gen_ashift (ASHIFTRT, 1, dest);
1860 /* Don't expand fine-grained when combining, because that will
1861 make the pattern fail. */
1862 if (! rtx_equal_function_value_matters
1863 && ! reload_in_progress && ! reload_completed)
1865 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
1866 emit_insn (gen_movsi (dest, source));
1869 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
1870 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
1871 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
1873 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
1874 gen_shifty_op (ASHIFT, operands);
1876 emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
1884 /* The SH cannot load a large constant into a register, constants have to
1885 come from a pc relative load. The reference of a pc relative load
1886 instruction must be less than 1k infront of the instruction. This
1887 means that we often have to dump a constant inside a function, and
1888 generate code to branch around it.
1890 It is important to minimize this, since the branches will slow things
1891 down and make things bigger.
1893 Worst case code looks like:
1911 We fix this by performing a scan before scheduling, which notices which
1912 instructions need to have their operands fetched from the constant table
1913 and builds the table.
1917 scan, find an instruction which needs a pcrel move. Look forward, find the
1918 last barrier which is within MAX_COUNT bytes of the requirement.
1919 If there isn't one, make one. Process all the instructions between
1920 the find and the barrier.
1922 In the above example, we can tell that L3 is within 1k of L1, so
1923 the first move can be shrunk from the 3 insn+constant sequence into
1924 just 1 insn, and the constant moved to L3 to make:
1935 Then the second move becomes the target for the shortening process. */
1939 rtx value; /* Value in table. */
1940 rtx label; /* Label of value. */
1941 rtx wend; /* End of window. */
1942 enum machine_mode mode; /* Mode of value. */
1945 /* The maximum number of constants that can fit into one pool, since
1946 the pc relative range is 0...1020 bytes and constants are at least 4
1949 #define MAX_POOL_SIZE (1020/4)
1950 static pool_node pool_vector[MAX_POOL_SIZE];
1951 static int pool_size;
1952 static rtx pool_window_label;
1953 static int pool_window_last;
1955 /* ??? If we need a constant in HImode which is the truncated value of a
1956 constant we need in SImode, we could combine the two entries thus saving
1957 two bytes. Is this common enough to be worth the effort of implementing
1960 /* ??? This stuff should be done at the same time that we shorten branches.
1961 As it is now, we must assume that all branches are the maximum size, and
1962 this causes us to almost always output constant pools sooner than
1965 /* Add a constant to the pool and return its label. */
1968 add_constant (x, mode, last_value)
1970 enum machine_mode mode;
1974 rtx lab, new, ref, newref;
1976 /* First see if we've already got it. */
1977 for (i = 0; i < pool_size; i++)
1979 if (x->code == pool_vector[i].value->code
1980 && mode == pool_vector[i].mode)
1982 if (x->code == CODE_LABEL)
1984 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
1987 if (rtx_equal_p (x, pool_vector[i].value))
1992 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
1994 new = gen_label_rtx ();
1995 LABEL_REFS (new) = pool_vector[i].label;
1996 pool_vector[i].label = lab = new;
1998 if (lab && pool_window_label)
2000 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2001 ref = pool_vector[pool_window_last].wend;
2002 LABEL_NEXTREF (newref) = ref;
2003 pool_vector[pool_window_last].wend = newref;
2006 pool_window_label = new;
2007 pool_window_last = i;
2013 /* Need a new one. */
2014 pool_vector[pool_size].value = x;
2015 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
2018 lab = gen_label_rtx ();
2019 pool_vector[pool_size].mode = mode;
2020 pool_vector[pool_size].label = lab;
2021 pool_vector[pool_size].wend = NULL_RTX;
2022 if (lab && pool_window_label)
2024 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2025 ref = pool_vector[pool_window_last].wend;
2026 LABEL_NEXTREF (newref) = ref;
2027 pool_vector[pool_window_last].wend = newref;
2030 pool_window_label = lab;
2031 pool_window_last = pool_size;
2036 /* Output the literal table. */
2046 /* Do two passes, first time dump out the HI sized constants. */
2048 for (i = 0; i < pool_size; i++)
2050 pool_node *p = &pool_vector[i];
2052 if (p->mode == HImode)
2056 scan = emit_insn_after (gen_align_2 (), scan);
2059 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2060 scan = emit_label_after (lab, scan);
2061 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
2063 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2065 lab = XEXP (ref, 0);
2066 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2073 for (i = 0; i < pool_size; i++)
2075 pool_node *p = &pool_vector[i];
2086 scan = emit_label_after (gen_label_rtx (), scan);
2087 scan = emit_insn_after (gen_align_4 (), scan);
2089 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2090 scan = emit_label_after (lab, scan);
2091 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
2099 scan = emit_label_after (gen_label_rtx (), scan);
2100 scan = emit_insn_after (gen_align_4 (), scan);
2102 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2103 scan = emit_label_after (lab, scan);
2104 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2112 if (p->mode != HImode)
2114 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2116 lab = XEXP (ref, 0);
2117 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2122 scan = emit_insn_after (gen_consttable_end (), scan);
2123 scan = emit_barrier_after (scan);
2125 pool_window_label = NULL_RTX;
2126 pool_window_last = 0;
2129 /* Return non-zero if constant would be an ok source for a
2130 mov.w instead of a mov.l. */
2136 return (GET_CODE (src) == CONST_INT
2137 && INTVAL (src) >= -32768
2138 && INTVAL (src) <= 32767);
2141 /* Non-zero if the insn is a move instruction which needs to be fixed. */
2143 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2144 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
2145 need to fix it if the input value is CONST_OK_FOR_I. */
2151 if (GET_CODE (insn) == INSN)
2153 rtx pat = PATTERN (insn);
2154 if (GET_CODE (pat) == PARALLEL)
2155 pat = XVECEXP (pat, 0, 0);
2156 if (GET_CODE (pat) == SET
2157 /* We can load any 8 bit value if we don't care what the high
2158 order bits end up as. */
2159 && GET_MODE (SET_DEST (pat)) != QImode
2160 && (CONSTANT_P (SET_SRC (pat))
2161 /* Match mova_const. */
2162 || (GET_CODE (SET_SRC (pat)) == UNSPEC
2163 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
2164 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
2166 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
2167 && (fp_zero_operand (SET_SRC (pat))
2168 || fp_one_operand (SET_SRC (pat)))
2169 /* ??? If this is a -m4 or -m4-single compilation, we don't
2170 know the current setting of fpscr, so disable fldi. */
2171 && (! TARGET_SH4 || TARGET_FMOVD)
2172 && GET_CODE (SET_DEST (pat)) == REG
2173 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
2174 && (GET_CODE (SET_SRC (pat)) != CONST_INT
2175 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat)))))
2186 return (GET_CODE (insn) == INSN
2187 && GET_CODE (PATTERN (insn)) == SET
2188 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
2189 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
2190 /* Don't match mova_const. */
2191 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn)), 0, 0)) == LABEL_REF);
2194 /* Find the last barrier from insn FROM which is close enough to hold the
2195 constant pool. If we can't find one, then create one near the end of
2199 find_barrier (num_mova, mova, from)
2209 int leading_mova = num_mova;
2210 rtx barrier_before_mova, found_barrier = 0, good_barrier = 0;
2214 /* For HImode: range is 510, add 4 because pc counts from address of
2215 second instruction after this one, subtract 2 for the jump instruction
2216 that we may need to emit before the table, subtract 2 for the instruction
2217 that fills the jump delay slot (in very rare cases, reorg will take an
2218 instruction from after the constant pool or will leave the delay slot
2219 empty). This gives 510.
2220 For SImode: range is 1020, add 4 because pc counts from address of
2221 second instruction after this one, subtract 2 in case pc is 2 byte
2222 aligned, subtract 2 for the jump instruction that we may need to emit
2223 before the table, subtract 2 for the instruction that fills the jump
2224 delay slot. This gives 1018. */
2226 /* The branch will always be shortened now that the reference address for
2227 forward branches is the successor address, thus we need no longer make
2228 adjustments to the [sh]i_limit for -O0. */
2233 while (from && count_si < si_limit && count_hi < hi_limit)
2235 int inc = get_attr_length (from);
2238 if (GET_CODE (from) == CODE_LABEL)
2241 new_align = 1 << label_to_alignment (from);
2242 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
2243 new_align = 1 << barrier_align (from);
2249 if (GET_CODE (from) == BARRIER)
2252 found_barrier = from;
2254 /* If we are at the end of the function, or in front of an alignment
2255 instruction, we need not insert an extra alignment. We prefer
2256 this kind of barrier. */
2257 if (barrier_align (from) > 2)
2258 good_barrier = from;
2261 if (broken_move (from))
2264 enum machine_mode mode;
2266 pat = PATTERN (from);
2267 if (GET_CODE (pat) == PARALLEL)
2268 pat = XVECEXP (pat, 0, 0);
2269 src = SET_SRC (pat);
2270 dst = SET_DEST (pat);
2271 mode = GET_MODE (dst);
2273 /* We must explicitly check the mode, because sometimes the
2274 front end will generate code to load unsigned constants into
2275 HImode targets without properly sign extending them. */
2277 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
2280 /* We put the short constants before the long constants, so
2281 we must count the length of short constants in the range
2282 for the long constants. */
2283 /* ??? This isn't optimal, but is easy to do. */
2288 while (si_align > 2 && found_si + si_align - 2 > count_si)
2290 if (found_si > count_si)
2291 count_si = found_si;
2292 found_si += GET_MODE_SIZE (mode);
2294 si_limit -= GET_MODE_SIZE (mode);
2297 /* See the code in machine_dependent_reorg, which has a similar if
2298 statement that generates a new mova insn in many cases. */
2299 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
2309 barrier_before_mova = good_barrier ? good_barrier : found_barrier;
2311 if (found_si > count_si)
2312 count_si = found_si;
2314 else if (GET_CODE (from) == JUMP_INSN
2315 && (GET_CODE (PATTERN (from)) == ADDR_VEC
2316 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
2320 if (barrier_align (next_real_insn (from)) == CACHE_LOG)
2322 /* We have just passed the barrier in front of the
2323 ADDR_DIFF_VEC, which is stored in found_barrier. Since
2324 the ADDR_DIFF_VEC is accessed as data, just like our pool
2325 constants, this is a good opportunity to accommodate what
2326 we have gathered so far.
2327 If we waited any longer, we could end up at a barrier in
2328 front of code, which gives worse cache usage for separated
2329 instruction / data caches. */
2330 good_barrier = found_barrier;
2335 rtx body = PATTERN (from);
2336 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
2339 /* For the SH1, we generate alignments even after jumps-around-jumps. */
2340 else if (GET_CODE (from) == JUMP_INSN
2342 && ! TARGET_SMALLCODE)
2348 if (new_align > si_align)
2350 si_limit -= (count_si - 1) & (new_align - si_align);
2351 si_align = new_align;
2353 count_si = (count_si + new_align - 1) & -new_align;
2358 if (new_align > hi_align)
2360 hi_limit -= (count_hi - 1) & (new_align - hi_align);
2361 hi_align = new_align;
2363 count_hi = (count_hi + new_align - 1) & -new_align;
2365 from = NEXT_INSN (from);
2372 /* Try as we might, the leading mova is out of range. Change
2373 it into a load (which will become a pcload) and retry. */
2374 SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
2375 INSN_CODE (mova) = -1;
2376 return find_barrier (0, 0, mova);
2380 /* Insert the constant pool table before the mova instruction,
2381 to prevent the mova label reference from going out of range. */
2383 good_barrier = found_barrier = barrier_before_mova;
2389 if (good_barrier && next_real_insn (found_barrier))
2390 found_barrier = good_barrier;
2394 /* We didn't find a barrier in time to dump our stuff,
2395 so we'll make one. */
2396 rtx label = gen_label_rtx ();
2398 /* If we exceeded the range, then we must back up over the last
2399 instruction we looked at. Otherwise, we just need to undo the
2400 NEXT_INSN at the end of the loop. */
2401 if (count_hi > hi_limit || count_si > si_limit)
2402 from = PREV_INSN (PREV_INSN (from));
2404 from = PREV_INSN (from);
2406 /* Walk back to be just before any jump or label.
2407 Putting it before a label reduces the number of times the branch
2408 around the constant pool table will be hit. Putting it before
2409 a jump makes it more likely that the bra delay slot will be
2411 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
2412 || GET_CODE (from) == CODE_LABEL)
2413 from = PREV_INSN (from);
2415 from = emit_jump_insn_after (gen_jump (label), from);
2416 JUMP_LABEL (from) = label;
2417 LABEL_NUSES (label) = 1;
2418 found_barrier = emit_barrier_after (from);
2419 emit_label_after (label, found_barrier);
2422 return found_barrier;
2425 /* If the instruction INSN is implemented by a special function, and we can
2426 positively find the register that is used to call the sfunc, and this
2427 register is not used anywhere else in this instruction - except as the
2428 destination of a set, return this register; else, return 0. */
2430 sfunc_uses_reg (insn)
2434 rtx pattern, part, reg_part, reg;
2436 if (GET_CODE (insn) != INSN)
2438 pattern = PATTERN (insn);
2439 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
2442 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
2444 part = XVECEXP (pattern, 0, i);
2445 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
2450 reg = XEXP (reg_part, 0);
2451 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
2453 part = XVECEXP (pattern, 0, i);
2454 if (part == reg_part || GET_CODE (part) == CLOBBER)
2456 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
2457 && GET_CODE (SET_DEST (part)) == REG)
2458 ? SET_SRC (part) : part)))
2464 /* See if the only way in which INSN uses REG is by calling it, or by
2465 setting it while calling it. Set *SET to a SET rtx if the register
2469 noncall_uses_reg (reg, insn, set)
2478 reg2 = sfunc_uses_reg (insn);
2479 if (reg2 && REGNO (reg2) == REGNO (reg))
2481 pattern = single_set (insn);
2483 && GET_CODE (SET_DEST (pattern)) == REG
2484 && REGNO (reg) == REGNO (SET_DEST (pattern)))
2488 if (GET_CODE (insn) != CALL_INSN)
2490 /* We don't use rtx_equal_p because we don't care if the mode is
2492 pattern = single_set (insn);
2494 && GET_CODE (SET_DEST (pattern)) == REG
2495 && REGNO (reg) == REGNO (SET_DEST (pattern)))
2501 par = PATTERN (insn);
2502 if (GET_CODE (par) == PARALLEL)
2503 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
2505 part = XVECEXP (par, 0, i);
2506 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
2509 return reg_mentioned_p (reg, SET_SRC (pattern));
2515 pattern = PATTERN (insn);
2517 if (GET_CODE (pattern) == PARALLEL)
2521 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
2522 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
2524 pattern = XVECEXP (pattern, 0, 0);
2527 if (GET_CODE (pattern) == SET)
2529 if (reg_mentioned_p (reg, SET_DEST (pattern)))
2531 /* We don't use rtx_equal_p, because we don't care if the
2532 mode is different. */
2533 if (GET_CODE (SET_DEST (pattern)) != REG
2534 || REGNO (reg) != REGNO (SET_DEST (pattern)))
2540 pattern = SET_SRC (pattern);
2543 if (GET_CODE (pattern) != CALL
2544 || GET_CODE (XEXP (pattern, 0)) != MEM
2545 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
2551 /* Given a X, a pattern of an insn or a part of it, return a mask of used
2552 general registers. Bits 0..15 mean that the respective registers
2553 are used as inputs in the instruction. Bits 16..31 mean that the
2554 registers 0..15, respectively, are used as outputs, or are clobbered.
2555 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
2557 regs_used (x, is_dest)
2566 code = GET_CODE (x);
2571 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
2572 << (REGNO (x) + is_dest));
2576 rtx y = SUBREG_REG (x);
2578 if (GET_CODE (y) != REG)
2581 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
2583 subreg_regno_offset (REGNO (y),
2586 GET_MODE (x)) + is_dest));
2590 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
2592 /* If there was a return value, it must have been indicated with USE. */
2607 fmt = GET_RTX_FORMAT (code);
2609 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2614 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2615 used |= regs_used (XVECEXP (x, i, j), is_dest);
2617 else if (fmt[i] == 'e')
2618 used |= regs_used (XEXP (x, i), is_dest);
2623 /* Create an instruction that prevents redirection of a conditional branch
2624 to the destination of the JUMP with address ADDR.
2625 If the branch needs to be implemented as an indirect jump, try to find
2626 a scratch register for it.
2627 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
2628 If any preceding insn that doesn't fit into a delay slot is good enough,
2629 pass 1. Pass 2 if a definite blocking insn is needed.
2630 -1 is used internally to avoid deep recursion.
2631 If a blocking instruction is made or recognized, return it. */
2634 gen_block_redirect (jump, addr, need_block)
2636 int addr, need_block;
2639 rtx prev = prev_nonnote_insn (jump);
2642 /* First, check if we already have an instruction that satisfies our need. */
2643 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
2645 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2647 if (GET_CODE (PATTERN (prev)) == USE
2648 || GET_CODE (PATTERN (prev)) == CLOBBER
2649 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
2651 else if ((need_block &= ~1) < 0)
2653 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
2656 /* We can't use JUMP_LABEL here because it might be undefined
2657 when not optimizing. */
2658 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
2659 /* If the branch is out of range, try to find a scratch register for it. */
2661 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + 4092U > 4092 + 4098))
2664 /* Don't look for the stack pointer as a scratch register,
2665 it would cause trouble if an interrupt occurred. */
2666 unsigned try = 0x7fff, used;
2667 int jump_left = flag_expensive_optimizations + 1;
2669 /* It is likely that the most recent eligible instruction is wanted for
2670 the delay slot. Therefore, find out which registers it uses, and
2671 try to avoid using them. */
2673 for (scan = jump; (scan = PREV_INSN (scan)); )
2677 if (INSN_DELETED_P (scan))
2679 code = GET_CODE (scan);
2680 if (code == CODE_LABEL || code == JUMP_INSN)
2683 && GET_CODE (PATTERN (scan)) != USE
2684 && GET_CODE (PATTERN (scan)) != CLOBBER
2685 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
2687 try &= ~regs_used (PATTERN (scan), 0);
2691 for (used = dead = 0, scan = JUMP_LABEL (jump);
2692 (scan = NEXT_INSN (scan)); )
2696 if (INSN_DELETED_P (scan))
2698 code = GET_CODE (scan);
2699 if (GET_RTX_CLASS (code) == 'i')
2701 used |= regs_used (PATTERN (scan), 0);
2702 if (code == CALL_INSN)
2703 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
2704 dead |= (used >> 16) & ~used;
2710 if (code == JUMP_INSN)
2712 if (jump_left-- && simplejump_p (scan))
2713 scan = JUMP_LABEL (scan);
2719 /* Mask out the stack pointer again, in case it was
2720 the only 'free' register we have found. */
2723 /* If the immediate destination is still in range, check for possible
2724 threading with a jump beyond the delay slot insn.
2725 Don't check if we are called recursively; the jump has been or will be
2726 checked in a different invocation then. */
2728 else if (optimize && need_block >= 0)
2730 rtx next = next_active_insn (next_active_insn (dest));
2731 if (next && GET_CODE (next) == JUMP_INSN
2732 && GET_CODE (PATTERN (next)) == SET
2733 && recog_memoized (next) == CODE_FOR_jump)
2735 dest = JUMP_LABEL (next);
2737 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + 4092U
2739 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
2745 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
2747 /* It would be nice if we could convert the jump into an indirect
2748 jump / far branch right now, and thus exposing all constituent
2749 instructions to further optimization. However, reorg uses
2750 simplejump_p to determine if there is an unconditional jump where
2751 it should try to schedule instructions from the target of the
2752 branch; simplejump_p fails for indirect jumps even if they have
2754 rtx insn = emit_insn_before (gen_indirect_jump_scratch
2755 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
2757 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
2760 else if (need_block)
2761 /* We can't use JUMP_LABEL here because it might be undefined
2762 when not optimizing. */
2763 return emit_insn_before (gen_block_branch_redirect
2764 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
2769 #define CONDJUMP_MIN -252
2770 #define CONDJUMP_MAX 262
2773 /* A label (to be placed) in front of the jump
2774 that jumps to our ultimate destination. */
2776 /* Where we are going to insert it if we cannot move the jump any farther,
2777 or the jump itself if we have picked up an existing jump. */
2779 /* The ultimate destination. */
2781 struct far_branch *prev;
2782 /* If the branch has already been created, its address;
2783 else the address of its first prospective user. */
2787 static void gen_far_branch PARAMS ((struct far_branch *));
2788 enum mdep_reorg_phase_e mdep_reorg_phase;
2791 struct far_branch *bp;
2793 rtx insn = bp->insert_place;
2795 rtx label = gen_label_rtx ();
2797 emit_label_after (label, insn);
2800 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
2801 LABEL_NUSES (bp->far_label)++;
2804 jump = emit_jump_insn_after (gen_return (), insn);
2805 /* Emit a barrier so that reorg knows that any following instructions
2806 are not reachable via a fall-through path.
2807 But don't do this when not optimizing, since we wouldn't supress the
2808 alignment for the barrier then, and could end up with out-of-range
2809 pc-relative loads. */
2811 emit_barrier_after (jump);
2812 emit_label_after (bp->near_label, insn);
2813 JUMP_LABEL (jump) = bp->far_label;
2814 if (! invert_jump (insn, label, 1))
2816 /* Prevent reorg from undoing our splits. */
2817 gen_block_redirect (jump, bp->address += 2, 2);
2820 /* Fix up ADDR_DIFF_VECs. */
2822 fixup_addr_diff_vecs (first)
2827 for (insn = first; insn; insn = NEXT_INSN (insn))
2829 rtx vec_lab, pat, prev, prevpat, x, braf_label;
2831 if (GET_CODE (insn) != JUMP_INSN
2832 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
2834 pat = PATTERN (insn);
2835 vec_lab = XEXP (XEXP (pat, 0), 0);
2837 /* Search the matching casesi_jump_2. */
2838 for (prev = vec_lab; ; prev = PREV_INSN (prev))
2840 if (GET_CODE (prev) != JUMP_INSN)
2842 prevpat = PATTERN (prev);
2843 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
2845 x = XVECEXP (prevpat, 0, 1);
2846 if (GET_CODE (x) != USE)
2849 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
2853 /* Emit the reference label of the braf where it belongs, right after
2854 the casesi_jump_2 (i.e. braf). */
2855 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
2856 emit_label_after (braf_label, prev);
2858 /* Fix up the ADDR_DIF_VEC to be relative
2859 to the reference address of the braf. */
2860 XEXP (XEXP (pat, 0), 0) = braf_label;
2864 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
2865 a barrier. Return the base 2 logarithm of the desired alignment. */
2867 barrier_align (barrier_or_label)
2868 rtx barrier_or_label;
2870 rtx next = next_real_insn (barrier_or_label), pat, prev;
2871 int slot, credit, jump_to_next;
2876 pat = PATTERN (next);
2878 if (GET_CODE (pat) == ADDR_DIFF_VEC)
2881 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
2882 /* This is a barrier in front of a constant table. */
2885 prev = prev_real_insn (barrier_or_label);
2886 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
2888 pat = PATTERN (prev);
2889 /* If this is a very small table, we want to keep the alignment after
2890 the table to the minimum for proper code alignment. */
2891 return ((TARGET_SMALLCODE
2892 || (XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
2893 <= (unsigned)1 << (CACHE_LOG - 2)))
2897 if (TARGET_SMALLCODE)
2900 if (! TARGET_SH2 || ! optimize)
2903 /* When fixing up pcloads, a constant table might be inserted just before
2904 the basic block that ends with the barrier. Thus, we can't trust the
2905 instruction lengths before that. */
2906 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
2908 /* Check if there is an immediately preceding branch to the insn beyond
2909 the barrier. We must weight the cost of discarding useful information
2910 from the current cache line when executing this branch and there is
2911 an alignment, against that of fetching unneeded insn in front of the
2912 branch target when there is no alignment. */
2914 /* There are two delay_slot cases to consider. One is the simple case
2915 where the preceding branch is to the insn beyond the barrier (simple
2916 delay slot filling), and the other is where the preceding branch has
2917 a delay slot that is a duplicate of the insn after the barrier
2918 (fill_eager_delay_slots) and the branch is to the insn after the insn
2919 after the barrier. */
2921 /* PREV is presumed to be the JUMP_INSN for the barrier under
2922 investigation. Skip to the insn before it. */
2923 prev = prev_real_insn (prev);
2925 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
2926 credit >= 0 && prev && GET_CODE (prev) == INSN;
2927 prev = prev_real_insn (prev))
2930 if (GET_CODE (PATTERN (prev)) == USE
2931 || GET_CODE (PATTERN (prev)) == CLOBBER)
2933 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
2935 prev = XVECEXP (PATTERN (prev), 0, 1);
2936 if (INSN_UID (prev) == INSN_UID (next))
2938 /* Delay slot was filled with insn at jump target. */
2945 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
2947 credit -= get_attr_length (prev);
2950 && GET_CODE (prev) == JUMP_INSN
2951 && JUMP_LABEL (prev)
2952 && (jump_to_next || next_real_insn (JUMP_LABEL (prev)) == next
2953 /* If relax_delay_slots() decides NEXT was redundant
2954 with some previous instruction, it will have
2955 redirected PREV's jump to the following insn. */
2956 || JUMP_LABEL (prev) == next_nonnote_insn (next)
2957 /* There is no upper bound on redundant instructions that
2958 might have been skipped, but we must not put an alignment
2959 where none had been before. */
2960 || (INSN_CODE (NEXT_INSN (NEXT_INSN (PREV_INSN (prev))))
2961 == CODE_FOR_block_branch_redirect)
2962 || (INSN_CODE (NEXT_INSN (NEXT_INSN (PREV_INSN (prev))))
2963 == CODE_FOR_indirect_jump_scratch)))
2965 rtx pat = PATTERN (prev);
2966 if (GET_CODE (pat) == PARALLEL)
2967 pat = XVECEXP (pat, 0, 0);
2968 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
2976 /* If we are inside a phony loop, almost any kind of label can turn up as the
2977 first one in the loop. Aligning a braf label causes incorrect switch
2978 destination addresses; we can detect braf labels because they are
2979 followed by a BARRIER.
2980 Applying loop alignment to small constant or switch tables is a waste
2981 of space, so we suppress this too. */
2983 sh_loop_align (label)
2989 next = next_nonnote_insn (next);
2990 while (next && GET_CODE (next) == CODE_LABEL);
2994 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
2995 || recog_memoized (next) == CODE_FOR_consttable_2)
3000 /* Exported to toplev.c.
3002 Do a final pass over the function, just before delayed branch
3006 machine_dependent_reorg (first)
3011 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
3012 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
3014 /* We must split call insns before introducing `mova's. If we're
3015 optimizing, they'll have already been split. Otherwise, make
3016 sure we don't split them too late. */
3018 split_all_insns (0);
3020 /* If relaxing, generate pseudo-ops to associate function calls with
3021 the symbols they call. It does no harm to not generate these
3022 pseudo-ops. However, when we can generate them, it enables to
3023 linker to potentially relax the jsr to a bsr, and eliminate the
3024 register load and, possibly, the constant pool entry. */
3026 mdep_reorg_phase = SH_INSERT_USES_LABELS;
3029 /* Remove all REG_LABEL notes. We want to use them for our own
3030 purposes. This works because none of the remaining passes
3031 need to look at them.
3033 ??? But it may break in the future. We should use a machine
3034 dependent REG_NOTE, or some other approach entirely. */
3035 for (insn = first; insn; insn = NEXT_INSN (insn))
3041 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
3042 remove_note (insn, note);
3046 for (insn = first; insn; insn = NEXT_INSN (insn))
3048 rtx pattern, reg, link, set, scan, dies, label;
3049 int rescan = 0, foundinsn = 0;
3051 if (GET_CODE (insn) == CALL_INSN)
3053 pattern = PATTERN (insn);
3055 if (GET_CODE (pattern) == PARALLEL)
3056 pattern = XVECEXP (pattern, 0, 0);
3057 if (GET_CODE (pattern) == SET)
3058 pattern = SET_SRC (pattern);
3060 if (GET_CODE (pattern) != CALL
3061 || GET_CODE (XEXP (pattern, 0)) != MEM)
3064 reg = XEXP (XEXP (pattern, 0), 0);
3068 reg = sfunc_uses_reg (insn);
3073 if (GET_CODE (reg) != REG)
3076 /* This is a function call via REG. If the only uses of REG
3077 between the time that it is set and the time that it dies
3078 are in function calls, then we can associate all the
3079 function calls with the setting of REG. */
3081 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
3083 if (REG_NOTE_KIND (link) != 0)
3085 set = single_set (XEXP (link, 0));
3086 if (set && rtx_equal_p (reg, SET_DEST (set)))
3088 link = XEXP (link, 0);
3095 /* ??? Sometimes global register allocation will have
3096 deleted the insn pointed to by LOG_LINKS. Try
3097 scanning backward to find where the register is set. */
3098 for (scan = PREV_INSN (insn);
3099 scan && GET_CODE (scan) != CODE_LABEL;
3100 scan = PREV_INSN (scan))
3102 if (! INSN_P (scan))
3105 if (! reg_mentioned_p (reg, scan))
3108 if (noncall_uses_reg (reg, scan, &set))
3122 /* The register is set at LINK. */
3124 /* We can only optimize the function call if the register is
3125 being set to a symbol. In theory, we could sometimes
3126 optimize calls to a constant location, but the assembler
3127 and linker do not support that at present. */
3128 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
3129 && GET_CODE (SET_SRC (set)) != LABEL_REF)
3132 /* Scan forward from LINK to the place where REG dies, and
3133 make sure that the only insns which use REG are
3134 themselves function calls. */
3136 /* ??? This doesn't work for call targets that were allocated
3137 by reload, since there may not be a REG_DEAD note for the
3141 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
3145 /* Don't try to trace forward past a CODE_LABEL if we haven't
3146 seen INSN yet. Ordinarily, we will only find the setting insn
3147 in LOG_LINKS if it is in the same basic block. However,
3148 cross-jumping can insert code labels in between the load and
3149 the call, and can result in situations where a single call
3150 insn may have two targets depending on where we came from. */
3152 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
3155 if (! INSN_P (scan))
3158 /* Don't try to trace forward past a JUMP. To optimize
3159 safely, we would have to check that all the
3160 instructions at the jump destination did not use REG. */
3162 if (GET_CODE (scan) == JUMP_INSN)
3165 if (! reg_mentioned_p (reg, scan))
3168 if (noncall_uses_reg (reg, scan, &scanset))
3175 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
3177 /* There is a function call to this register other
3178 than the one we are checking. If we optimize
3179 this call, we need to rescan again below. */
3183 /* ??? We shouldn't have to worry about SCANSET here.
3184 We should just be able to check for a REG_DEAD note
3185 on a function call. However, the REG_DEAD notes are
3186 apparently not dependable around libcalls; c-torture
3187 execute/920501-2 is a test case. If SCANSET is set,
3188 then this insn sets the register, so it must have
3189 died earlier. Unfortunately, this will only handle
3190 the cases in which the register is, in fact, set in a
3193 /* ??? We shouldn't have to use FOUNDINSN here.
3194 However, the LOG_LINKS fields are apparently not
3195 entirely reliable around libcalls;
3196 newlib/libm/math/e_pow.c is a test case. Sometimes
3197 an insn will appear in LOG_LINKS even though it is
3198 not the most recent insn which sets the register. */
3202 || find_reg_note (scan, REG_DEAD, reg)))
3211 /* Either there was a branch, or some insn used REG
3212 other than as a function call address. */
3216 /* Create a code label, and put it in a REG_LABEL note on
3217 the insn which sets the register, and on each call insn
3218 which uses the register. In final_prescan_insn we look
3219 for the REG_LABEL notes, and output the appropriate label
3222 label = gen_label_rtx ();
3223 REG_NOTES (link) = gen_rtx_EXPR_LIST (REG_LABEL, label,
3225 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_LABEL, label,
3234 scan = NEXT_INSN (scan);
3236 && ((GET_CODE (scan) == CALL_INSN
3237 && reg_mentioned_p (reg, scan))
3238 || ((reg2 = sfunc_uses_reg (scan))
3239 && REGNO (reg2) == REGNO (reg))))
3241 = gen_rtx_EXPR_LIST (REG_LABEL, label, REG_NOTES (scan));
3243 while (scan != dies);
3249 fixup_addr_diff_vecs (first);
3253 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
3254 shorten_branches (first);
3256 /* Scan the function looking for move instructions which have to be
3257 changed to pc-relative loads and insert the literal tables. */
3259 mdep_reorg_phase = SH_FIXUP_PCLOAD;
3260 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
3267 else if (GET_CODE (insn) == JUMP_INSN
3268 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3276 /* Some code might have been inserted between the mova and
3277 its ADDR_DIFF_VEC. Check if the mova is still in range. */
3278 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
3279 total += get_attr_length (scan);
3281 /* range of mova is 1020, add 4 because pc counts from address of
3282 second instruction after this one, subtract 2 in case pc is 2
3283 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
3284 cancels out with alignment effects of the mova itself. */
3287 /* Change the mova into a load, and restart scanning
3288 there. broken_move will then return true for mova. */
3289 SET_SRC (PATTERN (mova))
3290 = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3291 INSN_CODE (mova) = -1;
3295 if (broken_move (insn))
3298 /* Scan ahead looking for a barrier to stick the constant table
3300 rtx barrier = find_barrier (num_mova, mova, insn);
3301 rtx last_float_move, last_float = 0, *last_float_addr;
3303 if (num_mova && ! mova_p (mova))
3305 /* find_barrier had to change the first mova into a
3306 pcload; thus, we have to start with this new pcload. */
3310 /* Now find all the moves between the points and modify them. */
3311 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
3313 if (GET_CODE (scan) == CODE_LABEL)
3315 if (broken_move (scan))
3317 rtx *patp = &PATTERN (scan), pat = *patp;
3321 enum machine_mode mode;
3323 if (GET_CODE (pat) == PARALLEL)
3324 patp = &XVECEXP (pat, 0, 0), pat = *patp;
3325 src = SET_SRC (pat);
3326 dst = SET_DEST (pat);
3327 mode = GET_MODE (dst);
3329 if (mode == SImode && hi_const (src)
3330 && REGNO (dst) != FPUL_REG)
3335 while (GET_CODE (dst) == SUBREG)
3337 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
3338 GET_MODE (SUBREG_REG (dst)),
3341 dst = SUBREG_REG (dst);
3343 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
3346 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
3348 /* This must be an insn that clobbers r0. */
3349 rtx clobber = XVECEXP (PATTERN (scan), 0,
3350 XVECLEN (PATTERN (scan), 0) - 1);
3352 if (GET_CODE (clobber) != CLOBBER
3353 || ! rtx_equal_p (XEXP (clobber, 0), r0_rtx))
3357 && reg_set_between_p (r0_rtx, last_float_move, scan))
3359 lab = add_constant (src, mode, last_float);
3361 emit_insn_before (gen_mova (lab), scan);
3364 /* There will be a REG_UNUSED note for r0 on
3365 LAST_FLOAT_MOVE; we have to change it to REG_INC,
3366 lest reorg:mark_target_live_regs will not
3367 consider r0 to be used, and we end up with delay
3368 slot insn in front of SCAN that clobbers r0. */
3370 = find_regno_note (last_float_move, REG_UNUSED, 0);
3372 /* If we are not optimizing, then there may not be
3375 PUT_MODE (note, REG_INC);
3377 *last_float_addr = r0_inc_rtx;
3379 last_float_move = scan;
3381 newsrc = gen_rtx (MEM, mode,
3382 (((TARGET_SH4 && ! TARGET_FMOVD)
3383 || REGNO (dst) == FPUL_REG)
3386 last_float_addr = &XEXP (newsrc, 0);
3388 /* Remove the clobber of r0. */
3389 XEXP (clobber, 0) = gen_rtx_SCRATCH (Pmode);
3391 /* This is a mova needing a label. Create it. */
3392 else if (GET_CODE (src) == UNSPEC
3393 && XINT (src, 1) == UNSPEC_MOVA
3394 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
3396 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
3397 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
3398 newsrc = gen_rtx_UNSPEC (VOIDmode,
3399 gen_rtvec (1, newsrc),
3404 lab = add_constant (src, mode, 0);
3405 newsrc = gen_rtx_MEM (mode,
3406 gen_rtx_LABEL_REF (VOIDmode, lab));
3408 RTX_UNCHANGING_P (newsrc) = 1;
3409 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
3410 INSN_CODE (scan) = -1;
3413 dump_table (barrier);
3418 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
3419 INSN_ADDRESSES_FREE ();
3420 split_branches (first);
3422 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
3423 also has an effect on the register that holds the addres of the sfunc.
3424 Insert an extra dummy insn in front of each sfunc that pretends to
3425 use this register. */
3426 if (flag_delayed_branch)
3428 for (insn = first; insn; insn = NEXT_INSN (insn))
3430 rtx reg = sfunc_uses_reg (insn);
3434 emit_insn_before (gen_use_sfunc_addr (reg), insn);
3438 /* fpscr is not actually a user variable, but we pretend it is for the
3439 sake of the previous optimization passes, since we want it handled like
3440 one. However, we don't have any debugging information for it, so turn
3441 it into a non-user variable now. */
3443 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
3445 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
3449 get_dest_uid (label, max_uid)
3453 rtx dest = next_real_insn (label);
3456 /* This can happen for an undefined label. */
3458 dest_uid = INSN_UID (dest);
3459 /* If this is a newly created branch redirection blocking instruction,
3460 we cannot index the branch_uid or insn_addresses arrays with its
3461 uid. But then, we won't need to, because the actual destination is
3462 the following branch. */
3463 while (dest_uid >= max_uid)
3465 dest = NEXT_INSN (dest);
3466 dest_uid = INSN_UID (dest);
3468 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
3473 /* Split condbranches that are out of range. Also add clobbers for
3474 scratch registers that are needed in far jumps.
3475 We do this before delay slot scheduling, so that it can take our
3476 newly created instructions into account. It also allows us to
3477 find branches with common targets more easily. */
3480 split_branches (first)
3484 struct far_branch **uid_branch, *far_branch_list = 0;
3485 int max_uid = get_max_uid ();
3487 /* Find out which branches are out of range. */
3488 shorten_branches (first);
3490 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
3491 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
3493 for (insn = first; insn; insn = NEXT_INSN (insn))
3494 if (! INSN_P (insn))
3496 else if (INSN_DELETED_P (insn))
3498 /* Shorten_branches would split this instruction again,
3499 so transform it into a note. */
3500 PUT_CODE (insn, NOTE);
3501 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
3502 NOTE_SOURCE_FILE (insn) = 0;
3504 else if (GET_CODE (insn) == JUMP_INSN
3505 /* Don't mess with ADDR_DIFF_VEC */
3506 && (GET_CODE (PATTERN (insn)) == SET
3507 || GET_CODE (PATTERN (insn)) == RETURN))
3509 enum attr_type type = get_attr_type (insn);
3510 if (type == TYPE_CBRANCH)
3514 if (get_attr_length (insn) > 4)
3516 rtx src = SET_SRC (PATTERN (insn));
3517 rtx olabel = XEXP (XEXP (src, 1), 0);
3518 int addr = INSN_ADDRESSES (INSN_UID (insn));
3520 int dest_uid = get_dest_uid (olabel, max_uid);
3521 struct far_branch *bp = uid_branch[dest_uid];
3523 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
3524 the label if the LABEL_NUSES count drops to zero. There is
3525 always a jump_optimize pass that sets these values, but it
3526 proceeds to delete unreferenced code, and then if not
3527 optimizing, to un-delete the deleted instructions, thus
3528 leaving labels with too low uses counts. */
3531 JUMP_LABEL (insn) = olabel;
3532 LABEL_NUSES (olabel)++;
3536 bp = (struct far_branch *) alloca (sizeof *bp);
3537 uid_branch[dest_uid] = bp;
3538 bp->prev = far_branch_list;
3539 far_branch_list = bp;
3541 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
3542 LABEL_NUSES (bp->far_label)++;
3546 label = bp->near_label;
3547 if (! label && bp->address - addr >= CONDJUMP_MIN)
3549 rtx block = bp->insert_place;
3551 if (GET_CODE (PATTERN (block)) == RETURN)
3552 block = PREV_INSN (block);
3554 block = gen_block_redirect (block,
3556 label = emit_label_after (gen_label_rtx (),
3558 bp->near_label = label;
3560 else if (label && ! NEXT_INSN (label))
3562 if (addr + 2 - bp->address <= CONDJUMP_MAX)
3563 bp->insert_place = insn;
3565 gen_far_branch (bp);
3569 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
3571 bp->near_label = label = gen_label_rtx ();
3572 bp->insert_place = insn;
3575 if (! redirect_jump (insn, label, 1))
3580 /* get_attr_length (insn) == 2 */
3581 /* Check if we have a pattern where reorg wants to redirect
3582 the branch to a label from an unconditional branch that
3584 /* We can't use JUMP_LABEL here because it might be undefined
3585 when not optimizing. */
3586 /* A syntax error might cause beyond to be NULL_RTX. */
3588 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
3592 && (GET_CODE (beyond) == JUMP_INSN
3593 || ((beyond = next_active_insn (beyond))
3594 && GET_CODE (beyond) == JUMP_INSN))
3595 && GET_CODE (PATTERN (beyond)) == SET
3596 && recog_memoized (beyond) == CODE_FOR_jump
3598 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
3599 - INSN_ADDRESSES (INSN_UID (insn)) + 252U)
3601 gen_block_redirect (beyond,
3602 INSN_ADDRESSES (INSN_UID (beyond)), 1);
3605 next = next_active_insn (insn);
3607 if ((GET_CODE (next) == JUMP_INSN
3608 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
3609 && GET_CODE (PATTERN (next)) == SET
3610 && recog_memoized (next) == CODE_FOR_jump
3612 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
3613 - INSN_ADDRESSES (INSN_UID (insn)) + 252U)
3615 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
3617 else if (type == TYPE_JUMP || type == TYPE_RETURN)
3619 int addr = INSN_ADDRESSES (INSN_UID (insn));
3622 struct far_branch *bp;
3624 if (type == TYPE_JUMP)
3626 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
3627 dest_uid = get_dest_uid (far_label, max_uid);
3630 /* Parse errors can lead to labels outside
3632 if (! NEXT_INSN (far_label))
3637 JUMP_LABEL (insn) = far_label;
3638 LABEL_NUSES (far_label)++;
3640 redirect_jump (insn, NULL_RTX, 1);
3644 bp = uid_branch[dest_uid];
3647 bp = (struct far_branch *) alloca (sizeof *bp);
3648 uid_branch[dest_uid] = bp;
3649 bp->prev = far_branch_list;
3650 far_branch_list = bp;
3652 bp->far_label = far_label;
3654 LABEL_NUSES (far_label)++;
3656 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
3657 if (addr - bp->address <= CONDJUMP_MAX)
3658 emit_label_after (bp->near_label, PREV_INSN (insn));
3661 gen_far_branch (bp);
3667 bp->insert_place = insn;
3669 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
3671 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
3674 /* Generate all pending far branches,
3675 and free our references to the far labels. */
3676 while (far_branch_list)
3678 if (far_branch_list->near_label
3679 && ! NEXT_INSN (far_branch_list->near_label))
3680 gen_far_branch (far_branch_list);
3682 && far_branch_list->far_label
3683 && ! --LABEL_NUSES (far_branch_list->far_label))
3684 delete_insn (far_branch_list->far_label);
3685 far_branch_list = far_branch_list->prev;
3688 /* Instruction length information is no longer valid due to the new
3689 instructions that have been generated. */
3690 init_insn_lengths ();
3693 /* Dump out instruction addresses, which is useful for debugging the
3694 constant pool table stuff.
3696 If relaxing, output the label and pseudo-ops used to link together
3697 calls and the instruction which set the registers. */
3699 /* ??? This is unnecessary, and probably should be deleted. This makes
3700 the insn_addresses declaration above unnecessary. */
3702 /* ??? The addresses printed by this routine for insns are nonsense for
3703 insns which are inside of a sequence where none of the inner insns have
3704 variable length. This is because the second pass of shorten_branches
3705 does not bother to update them. */
3708 final_prescan_insn (insn, opvec, noperands)
3710 rtx *opvec ATTRIBUTE_UNUSED;
3711 int noperands ATTRIBUTE_UNUSED;
3713 if (TARGET_DUMPISIZE)
3714 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
3720 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
3725 pattern = PATTERN (insn);
3726 if (GET_CODE (pattern) == PARALLEL)
3727 pattern = XVECEXP (pattern, 0, 0);
3728 if (GET_CODE (pattern) == CALL
3729 || (GET_CODE (pattern) == SET
3730 && (GET_CODE (SET_SRC (pattern)) == CALL
3731 || get_attr_type (insn) == TYPE_SFUNC)))
3732 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
3733 CODE_LABEL_NUMBER (XEXP (note, 0)));
3734 else if (GET_CODE (pattern) == SET)
3735 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
3736 CODE_LABEL_NUMBER (XEXP (note, 0)));
3743 /* Dump out any constants accumulated in the final pass. These will
3747 output_jump_label_table ()
3753 fprintf (asm_out_file, "\t.align 2\n");
3754 for (i = 0; i < pool_size; i++)
3756 pool_node *p = &pool_vector[i];
3758 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
3759 CODE_LABEL_NUMBER (p->label));
3760 output_asm_insn (".long %O0", &p->value);
3768 /* A full frame looks like:
3772 [ if current_function_anonymous_args
3785 local-0 <- fp points here. */
3787 /* Number of bytes pushed for anonymous args, used to pass information
3788 between expand_prologue and expand_epilogue. */
3790 static int extra_push;
3792 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
3793 to be adjusted, and TEMP, if nonnegative, holds the register number
3794 of a general register that we may clobber. */
3797 output_stack_adjust (size, reg, temp)
3804 if (CONST_OK_FOR_I (size))
3805 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
3806 /* Try to do it with two partial adjustments; however, we must make
3807 sure that the stack is properly aligned at all times, in case
3808 an interrupt occurs between the two partial adjustments. */
3809 else if (CONST_OK_FOR_I (size / 2 & -4)
3810 && CONST_OK_FOR_I (size - (size / 2 & -4)))
3812 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size / 2 & -4)));
3813 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size - (size / 2 & -4))));
3819 /* If TEMP is invalid, we could temporarily save a general
3820 register to MACL. However, there is currently no need
3821 to handle this case, so just abort when we see it. */
3824 const_reg = gen_rtx_REG (SImode, temp);
3826 /* If SIZE is negative, subtract the positive value.
3827 This sometimes allows a constant pool entry to be shared
3828 between prologue and epilogue code. */
3831 emit_insn (gen_movsi (const_reg, GEN_INT (-size)));
3832 emit_insn (gen_subsi3 (reg, reg, const_reg));
3836 emit_insn (gen_movsi (const_reg, GEN_INT (size)));
3837 emit_insn (gen_addsi3 (reg, reg, const_reg));
3843 /* Output RTL to push register RN onto the stack. */
3851 x = gen_push_fpul ();
3852 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
3853 && FP_OR_XD_REGISTER_P (rn))
3855 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
3857 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
3859 else if (TARGET_SH3E && FP_REGISTER_P (rn))
3860 x = gen_push_e (gen_rtx_REG (SFmode, rn));
3862 x = gen_push (gen_rtx_REG (SImode, rn));
3866 = gen_rtx_EXPR_LIST (REG_INC,
3867 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
3870 /* Output RTL to pop register RN from the stack. */
3878 x = gen_pop_fpul ();
3879 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
3880 && FP_OR_XD_REGISTER_P (rn))
3882 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
3884 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
3886 else if (TARGET_SH3E && FP_REGISTER_P (rn))
3887 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
3889 x = gen_pop (gen_rtx_REG (SImode, rn));
3893 = gen_rtx_EXPR_LIST (REG_INC,
3894 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
3897 /* Generate code to push the regs specified in the mask. */
3900 push_regs (mask, mask2)
3905 /* Push PR last; this gives better latencies after the prologue, and
3906 candidates for the return delay slot when there are no general
3907 registers pushed. */
3908 for (i = 0; i < 32; i++)
3909 if (mask & (1 << i) && i != PR_REG)
3911 for (i = 32; i < FIRST_PSEUDO_REGISTER; i++)
3912 if (mask2 & (1 << (i - 32)))
3914 if (mask & (1 << PR_REG))
3918 /* Work out the registers which need to be saved, both as a mask and a
3919 count of saved words.
3921 If doing a pragma interrupt function, then push all regs used by the
3922 function, and if we call another function (we can tell by looking at PR),
3923 make sure that all the regs it clobbers are safe too. */
3926 calc_live_regs (count_ptr, live_regs_mask2)
3928 int *live_regs_mask2;
3931 int live_regs_mask = 0;
3933 int interrupt_handler;
3935 if ((lookup_attribute
3936 ("interrupt_handler",
3937 DECL_MACHINE_ATTRIBUTES (current_function_decl)))
3939 interrupt_handler = 1;
3941 interrupt_handler = 0;
3943 *live_regs_mask2 = 0;
3944 /* If we can save a lot of saves by switching to double mode, do that. */
3945 if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
3946 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
3947 if (regs_ever_live[reg] && regs_ever_live[reg+1]
3948 && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa))
3951 target_flags &= ~FPU_SINGLE_BIT;
3954 for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
3956 if ((interrupt_handler && ! pragma_trapa)
3957 ? (/* Need to save all the regs ever live. */
3958 (regs_ever_live[reg]
3959 || (call_used_regs[reg]
3960 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
3961 && regs_ever_live[PR_REG]))
3962 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
3963 && reg != RETURN_ADDRESS_POINTER_REGNUM
3964 && reg != T_REG && reg != GBR_REG && reg != FPSCR_REG)
3965 : (/* Only push those regs which are used and need to be saved. */
3966 regs_ever_live[reg] && ! call_used_regs[reg]))
3969 *live_regs_mask2 |= 1 << (reg - 32);
3971 live_regs_mask |= 1 << reg;
3973 if (TARGET_SH4 && TARGET_FMOVD && FP_OR_XD_REGISTER_P (reg))
3975 if (FP_REGISTER_P (reg))
3977 if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
3980 *live_regs_mask2 |= 1 << ((reg ^ 1) - 32);
3982 live_regs_mask |= 1 << (reg ^ 1);
3986 else /* if (XD_REGISTER_P (reg)) */
3988 /* Must switch to double mode to access these registers. */
3989 target_flags &= ~FPU_SINGLE_BIT;
3996 *count_ptr = count * UNITS_PER_WORD;
3997 return live_regs_mask;
4000 /* Code to generate prologue and epilogue sequences */
4002 /* PUSHED is the number of bytes that are bing pushed on the
4003 stack for register saves. Return the frame size, padded
4004 appropriately so that the stack stays properly aligned. */
4005 static HOST_WIDE_INT
4006 rounded_frame_size (pushed)
4009 HOST_WIDE_INT size = get_frame_size ();
4010 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4012 return ((size + pushed + align - 1) & -align) - pushed;
4016 sh_expand_prologue ()
4020 int live_regs_mask2;
4021 int save_flags = target_flags;
4023 current_function_interrupt
4024 = lookup_attribute ("interrupt_handler",
4025 DECL_MACHINE_ATTRIBUTES (current_function_decl))
4028 /* We have pretend args if we had an object sent partially in registers
4029 and partially on the stack, e.g. a large structure. */
4030 output_stack_adjust (-current_function_pretend_args_size,
4031 stack_pointer_rtx, 1);
4035 /* This is set by SETUP_VARARGS to indicate that this is a varargs
4036 routine. Clear it here so that the next function isn't affected. */
4037 if (current_function_anonymous_args)
4039 current_function_anonymous_args = 0;
4041 /* This is not used by the SH3E calling convention */
4042 if (! TARGET_SH3E && ! TARGET_HITACHI)
4044 /* Push arg regs as if they'd been provided by caller in stack. */
4045 for (i = 0; i < NPARM_REGS(SImode); i++)
4047 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
4048 if (i >= (NPARM_REGS(SImode)
4049 - current_function_args_info.arg_count[(int) SH_ARG_INT]
4058 /* If we're supposed to switch stacks at function entry, do so now. */
4060 emit_insn (gen_sp_switch_1 ());
4062 live_regs_mask = calc_live_regs (&d, &live_regs_mask2);
4063 /* ??? Maybe we could save some switching if we can move a mode switch
4064 that already happens to be at the function start into the prologue. */
4065 if (target_flags != save_flags)
4066 emit_insn (gen_toggle_sz ());
4068 push_regs (live_regs_mask, live_regs_mask2);
4070 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
4072 rtx insn = get_last_insn ();
4073 rtx last = emit_insn (gen_GOTaddr2picreg ());
4075 /* Mark these insns as possibly dead. Sometimes, flow2 may
4076 delete all uses of the PIC register. In this case, let it
4077 delete the initialization too. */
4080 insn = NEXT_INSN (insn);
4082 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4086 while (insn != last);
4089 if (target_flags != save_flags)
4091 rtx insn = emit_insn (gen_toggle_sz ());
4093 /* If we're lucky, a mode switch in the function body will
4094 overwrite fpscr, turning this insn dead. Tell flow this
4095 insn is ok to delete. */
4096 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4101 target_flags = save_flags;
4103 output_stack_adjust (-rounded_frame_size (d),
4104 stack_pointer_rtx, 1);
4106 if (frame_pointer_needed)
4107 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
4111 sh_expand_epilogue ()
4116 int live_regs_mask2;
4117 int save_flags = target_flags;
4120 live_regs_mask = calc_live_regs (&d, &live_regs_mask2);
4122 frame_size = rounded_frame_size (d);
4124 if (frame_pointer_needed)
4126 output_stack_adjust (frame_size, frame_pointer_rtx, 7);
4128 /* We must avoid moving the stack pointer adjustment past code
4129 which reads from the local frame, else an interrupt could
4130 occur after the SP adjustment and clobber data in the local
4132 emit_insn (gen_blockage ());
4133 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
4135 else if (frame_size)
4137 /* We must avoid moving the stack pointer adjustment past code
4138 which reads from the local frame, else an interrupt could
4139 occur after the SP adjustment and clobber data in the local
4141 emit_insn (gen_blockage ());
4142 output_stack_adjust (frame_size, stack_pointer_rtx, 7);
4145 /* Pop all the registers. */
4147 if (target_flags != save_flags)
4148 emit_insn (gen_toggle_sz ());
4149 if (live_regs_mask & (1 << PR_REG))
4151 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4153 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
4154 if (j < 32 && (live_regs_mask & (1 << j)) && j != PR_REG)
4156 else if (j >= 32 && (live_regs_mask2 & (1 << (j - 32))))
4159 if (target_flags != save_flags)
4160 emit_insn (gen_toggle_sz ());
4161 target_flags = save_flags;
4163 output_stack_adjust (extra_push + current_function_pretend_args_size,
4164 stack_pointer_rtx, 7);
4166 /* Switch back to the normal stack if necessary. */
4168 emit_insn (gen_sp_switch_2 ());
4170 /* Tell flow the insn that pops PR isn't dead. */
4171 if (live_regs_mask & (1 << PR_REG))
4172 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
4175 static int sh_need_epilogue_known = 0;
4180 if (! sh_need_epilogue_known)
4185 sh_expand_epilogue ();
4186 epilogue = gen_sequence ();
4188 sh_need_epilogue_known
4189 = (GET_CODE (epilogue) == SEQUENCE && XVECLEN (epilogue, 0) == 0
4192 return sh_need_epilogue_known > 0;
4195 /* Clear variables at function end. */
4198 function_epilogue (stream, size)
4199 FILE *stream ATTRIBUTE_UNUSED;
4200 int size ATTRIBUTE_UNUSED;
4202 trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
4203 sh_need_epilogue_known = 0;
4204 sp_switch = NULL_RTX;
4208 sh_builtin_saveregs ()
4210 /* First unnamed integer register. */
4211 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
4212 /* Number of integer registers we need to save. */
4213 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
4214 /* First unnamed SFmode float reg */
4215 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
4216 /* Number of SFmode float regs to save. */
4217 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
4219 int bufsize, regno, alias_set;
4221 /* Allocate block of memory for the regs. */
4222 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
4223 Or can assign_stack_local accept a 0 SIZE argument? */
4224 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
4226 regbuf = assign_stack_local (BLKmode, bufsize, 0);
4227 alias_set = get_varargs_alias_set ();
4228 MEM_ALIAS_SET (regbuf) = alias_set;
4231 This is optimized to only save the regs that are necessary. Explicitly
4232 named args need not be saved. */
4234 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
4235 change_address (regbuf, BLKmode,
4236 plus_constant (XEXP (regbuf, 0),
4238 * UNITS_PER_WORD))),
4239 n_intregs, n_intregs * UNITS_PER_WORD);
4242 This is optimized to only save the regs that are necessary. Explicitly
4243 named args need not be saved.
4244 We explicitly build a pointer to the buffer because it halves the insn
4245 count when not optimizing (otherwise the pointer is built for each reg
4247 We emit the moves in reverse order so that we can use predecrement. */
4249 fpregs = gen_reg_rtx (Pmode);
4250 emit_move_insn (fpregs, XEXP (regbuf, 0));
4251 emit_insn (gen_addsi3 (fpregs, fpregs,
4252 GEN_INT (n_floatregs * UNITS_PER_WORD)));
4256 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
4258 emit_insn (gen_addsi3 (fpregs, fpregs,
4259 GEN_INT (-2 * UNITS_PER_WORD)));
4260 mem = gen_rtx_MEM (DFmode, fpregs);
4261 MEM_ALIAS_SET (mem) = alias_set;
4262 emit_move_insn (mem,
4263 gen_rtx (REG, DFmode, BASE_ARG_REG (DFmode) + regno));
4265 regno = first_floatreg;
4268 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
4269 mem = gen_rtx_MEM (SFmode, fpregs);
4270 MEM_ALIAS_SET (mem) = alias_set;
4271 emit_move_insn (mem,
4272 gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno
4273 - (TARGET_LITTLE_ENDIAN != 0)));
4277 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
4280 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
4281 mem = gen_rtx_MEM (SFmode, fpregs);
4282 MEM_ALIAS_SET (mem) = alias_set;
4283 emit_move_insn (mem,
4284 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
4287 /* Return the address of the regbuf. */
4288 return XEXP (regbuf, 0);
4291 /* Define the `__builtin_va_list' type for the ABI. */
4296 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
4299 if ((! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI)
4300 return ptr_type_node;
4302 record = make_node (RECORD_TYPE);
4304 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
4306 f_next_o_limit = build_decl (FIELD_DECL,
4307 get_identifier ("__va_next_o_limit"),
4309 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
4311 f_next_fp_limit = build_decl (FIELD_DECL,
4312 get_identifier ("__va_next_fp_limit"),
4314 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
4317 DECL_FIELD_CONTEXT (f_next_o) = record;
4318 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
4319 DECL_FIELD_CONTEXT (f_next_fp) = record;
4320 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
4321 DECL_FIELD_CONTEXT (f_next_stack) = record;
4323 TYPE_FIELDS (record) = f_next_o;
4324 TREE_CHAIN (f_next_o) = f_next_o_limit;
4325 TREE_CHAIN (f_next_o_limit) = f_next_fp;
4326 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
4327 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
4329 layout_type (record);
4334 /* Implement `va_start' for varargs and stdarg. */
4337 sh_va_start (stdarg_p, valist, nextarg)
4342 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
4343 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
4347 if ((! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI)
4349 std_expand_builtin_va_start (stdarg_p, valist, nextarg);
4353 f_next_o = TYPE_FIELDS (va_list_type_node);
4354 f_next_o_limit = TREE_CHAIN (f_next_o);
4355 f_next_fp = TREE_CHAIN (f_next_o_limit);
4356 f_next_fp_limit = TREE_CHAIN (f_next_fp);
4357 f_next_stack = TREE_CHAIN (f_next_fp_limit);
4359 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
4360 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
4361 valist, f_next_o_limit);
4362 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp);
4363 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
4364 valist, f_next_fp_limit);
4365 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
4366 valist, f_next_stack);
4368 /* Call __builtin_saveregs. */
4369 u = make_tree (ptr_type_node, expand_builtin_saveregs ());
4370 t = build (MODIFY_EXPR, ptr_type_node, next_fp, u);
4371 TREE_SIDE_EFFECTS (t) = 1;
4372 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4374 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
4379 u = fold (build (PLUS_EXPR, ptr_type_node, u,
4380 build_int_2 (UNITS_PER_WORD * nfp, 0)));
4381 t = build (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
4382 TREE_SIDE_EFFECTS (t) = 1;
4383 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4385 t = build (MODIFY_EXPR, ptr_type_node, next_o, u);
4386 TREE_SIDE_EFFECTS (t) = 1;
4387 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4389 nint = current_function_args_info.arg_count[SH_ARG_INT];
4394 u = fold (build (PLUS_EXPR, ptr_type_node, u,
4395 build_int_2 (UNITS_PER_WORD * nint, 0)));
4396 t = build (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
4397 TREE_SIDE_EFFECTS (t) = 1;
4398 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4400 u = make_tree (ptr_type_node, nextarg);
4401 if (! stdarg_p && (nint == 0 || nfp == 0))
4403 u = fold (build (PLUS_EXPR, ptr_type_node, u,
4404 build_int_2 (-UNITS_PER_WORD, -1)));
4406 t = build (MODIFY_EXPR, ptr_type_node, next_stack, u);
4407 TREE_SIDE_EFFECTS (t) = 1;
4408 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4411 /* Implement `va_arg'. */
4414 sh_va_arg (valist, type)
4417 HOST_WIDE_INT size, rsize;
4418 tree tmp, pptr_type_node;
4421 size = int_size_in_bytes (type);
4422 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4423 pptr_type_node = build_pointer_type (ptr_type_node);
4425 if ((TARGET_SH3E || TARGET_SH4) && ! TARGET_HITACHI)
4427 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
4428 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
4430 rtx lab_false, lab_over;
4432 f_next_o = TYPE_FIELDS (va_list_type_node);
4433 f_next_o_limit = TREE_CHAIN (f_next_o);
4434 f_next_fp = TREE_CHAIN (f_next_o_limit);
4435 f_next_fp_limit = TREE_CHAIN (f_next_fp);
4436 f_next_stack = TREE_CHAIN (f_next_fp_limit);
4438 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
4439 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
4440 valist, f_next_o_limit);
4441 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp),
4443 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
4444 valist, f_next_fp_limit);
4445 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
4446 valist, f_next_stack);
4450 pass_as_float = ((TREE_CODE (type) == REAL_TYPE && size <= 8)
4451 || (TREE_CODE (type) == COMPLEX_TYPE
4452 && TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
4457 pass_as_float = (TREE_CODE (type) == REAL_TYPE && size == 4);
4460 addr_rtx = gen_reg_rtx (Pmode);
4461 lab_false = gen_label_rtx ();
4462 lab_over = gen_label_rtx ();
4466 emit_cmp_and_jump_insns (expand_expr (next_fp, NULL_RTX, Pmode,
4468 expand_expr (next_fp_limit, NULL_RTX,
4469 Pmode, EXPAND_NORMAL),
4470 GE, const1_rtx, Pmode, 1, 1, lab_false);
4472 if (TYPE_ALIGN (type) > BITS_PER_WORD)
4474 tmp = build (BIT_AND_EXPR, ptr_type_node, next_fp,
4475 build_int_2 (UNITS_PER_WORD, 0));
4476 tmp = build (PLUS_EXPR, ptr_type_node, next_fp, tmp);
4477 tmp = build (MODIFY_EXPR, ptr_type_node, next_fp, tmp);
4478 TREE_SIDE_EFFECTS (tmp) = 1;
4479 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
4482 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
4483 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
4485 emit_move_insn (addr_rtx, r);
4487 emit_jump_insn (gen_jump (lab_over));
4489 emit_label (lab_false);
4491 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
4492 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
4494 emit_move_insn (addr_rtx, r);
4498 tmp = build (PLUS_EXPR, ptr_type_node, next_o,
4499 build_int_2 (rsize, 0));
4501 emit_cmp_and_jump_insns (expand_expr (tmp, NULL_RTX, Pmode,
4503 expand_expr (next_o_limit, NULL_RTX,
4504 Pmode, EXPAND_NORMAL),
4505 GT, const1_rtx, Pmode, 1, 1, lab_false);
4507 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
4508 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
4510 emit_move_insn (addr_rtx, r);
4512 emit_jump_insn (gen_jump (lab_over));
4514 emit_label (lab_false);
4516 if (size > 4 && ! TARGET_SH4)
4518 tmp = build (MODIFY_EXPR, ptr_type_node, next_o, next_o_limit);
4519 TREE_SIDE_EFFECTS (tmp) = 1;
4520 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
4523 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
4524 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
4526 emit_move_insn (addr_rtx, r);
4529 emit_label (lab_over);
4531 tmp = make_tree (pptr_type_node, addr_rtx);
4532 valist = build1 (INDIRECT_REF, ptr_type_node, tmp);
4535 /* ??? In va-sh.h, there had been code to make values larger than
4536 size 8 indirect. This does not match the FUNCTION_ARG macros. */
4538 return std_expand_builtin_va_arg (valist, type);
4541 /* Define the offset between two registers, one to be eliminated, and
4542 the other its replacement, at the start of a routine. */
4545 initial_elimination_offset (from, to)
4550 int total_saved_regs_space;
4551 int total_auto_space;
4552 int save_flags = target_flags;
4554 int live_regs_mask, live_regs_mask2;
4555 live_regs_mask = calc_live_regs (®s_saved, &live_regs_mask2);
4556 total_auto_space = rounded_frame_size (regs_saved);
4557 target_flags = save_flags;
4559 total_saved_regs_space = regs_saved;
4561 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
4562 return total_saved_regs_space + total_auto_space;
4564 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
4565 return total_saved_regs_space + total_auto_space;
4567 /* Initial gap between fp and sp is 0. */
4568 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
4571 if (from == RETURN_ADDRESS_POINTER_REGNUM
4572 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
4573 return UNITS_PER_WORD + total_auto_space;
4578 /* Handle machine specific pragmas to be semi-compatible with Hitachi
4582 sh_pr_interrupt (pfile)
4583 cpp_reader *pfile ATTRIBUTE_UNUSED;
4585 pragma_interrupt = 1;
4590 cpp_reader *pfile ATTRIBUTE_UNUSED;
4592 pragma_interrupt = pragma_trapa = 1;
4596 sh_pr_nosave_low_regs (pfile)
4597 cpp_reader *pfile ATTRIBUTE_UNUSED;
4599 pragma_nosave_low_regs = 1;
4602 /* Generate 'handle_interrupt' attribute for decls */
4605 sh_pragma_insert_attributes (node, attributes, prefix)
4608 tree * prefix ATTRIBUTE_UNUSED;
4610 if (! pragma_interrupt
4611 || TREE_CODE (node) != FUNCTION_DECL)
4614 /* We are only interested in fields. */
4615 if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd')
4618 /* Add a 'handle_interrupt' attribute. */
4619 * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes);
4624 /* Return nonzero if ATTR is a valid attribute for DECL.
4625 ATTRIBUTES are any existing attributes and ARGS are the arguments
4628 Supported attributes:
4630 interrupt_handler -- specifies this function is an interrupt handler.
4632 sp_switch -- specifies an alternate stack for an interrupt handler
4635 trap_exit -- use a trapa to exit an interrupt function instead of
4636 an rte instruction. */
4639 sh_valid_decl_attribute (decl, attributes, attr, args)
4641 tree attributes ATTRIBUTE_UNUSED;
4645 if (TREE_CODE (decl) != FUNCTION_DECL)
4648 if (is_attribute_p ("interrupt_handler", attr))
4653 if (is_attribute_p ("sp_switch", attr))
4655 /* The sp_switch attribute only has meaning for interrupt functions. */
4656 if (!pragma_interrupt)
4659 /* sp_switch must have an argument. */
4660 if (!args || TREE_CODE (args) != TREE_LIST)
4663 /* The argument must be a constant string. */
4664 if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
4667 sp_switch = gen_rtx_SYMBOL_REF (VOIDmode,
4668 TREE_STRING_POINTER (TREE_VALUE (args)));
4672 if (is_attribute_p ("trap_exit", attr))
4674 /* The trap_exit attribute only has meaning for interrupt functions. */
4675 if (!pragma_interrupt)
4678 /* trap_exit must have an argument. */
4679 if (!args || TREE_CODE (args) != TREE_LIST)
4682 /* The argument must be a constant integer. */
4683 if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
4686 trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
4694 /* Predicates used by the templates. */
4696 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
4697 Used only in general_movsrc_operand. */
4700 system_reg_operand (op, mode)
4702 enum machine_mode mode ATTRIBUTE_UNUSED;
4714 /* Returns 1 if OP can be source of a simple move operation.
4715 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
4716 invalid as are subregs of system registers. */
4719 general_movsrc_operand (op, mode)
4721 enum machine_mode mode;
4723 if (GET_CODE (op) == MEM)
4725 rtx inside = XEXP (op, 0);
4726 if (GET_CODE (inside) == CONST)
4727 inside = XEXP (inside, 0);
4729 if (GET_CODE (inside) == LABEL_REF)
4732 if (GET_CODE (inside) == PLUS
4733 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
4734 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
4737 /* Only post inc allowed. */
4738 if (GET_CODE (inside) == PRE_DEC)
4742 if ((mode == QImode || mode == HImode)
4743 && (GET_CODE (op) == SUBREG
4744 && GET_CODE (XEXP (op, 0)) == REG
4745 && system_reg_operand (XEXP (op, 0), mode)))
4748 return general_operand (op, mode);
4751 /* Returns 1 if OP can be a destination of a move.
4752 Same as general_operand, but no preinc allowed. */
4755 general_movdst_operand (op, mode)
4757 enum machine_mode mode;
4759 /* Only pre dec allowed. */
4760 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
4763 return general_operand (op, mode);
4766 /* Returns 1 if OP is a normal arithmetic register. */
4769 arith_reg_operand (op, mode)
4771 enum machine_mode mode;
4773 if (register_operand (op, mode))
4777 if (GET_CODE (op) == REG)
4779 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
4780 regno = REGNO (SUBREG_REG (op));
4784 return (regno != T_REG && regno != PR_REG
4785 && (regno != FPUL_REG || TARGET_SH4)
4786 && regno != MACH_REG && regno != MACL_REG);
4792 fp_arith_reg_operand (op, mode)
4794 enum machine_mode mode;
4796 if (register_operand (op, mode))
4800 if (GET_CODE (op) == REG)
4802 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
4803 regno = REGNO (SUBREG_REG (op));
4807 return (regno >= FIRST_PSEUDO_REGISTER
4808 || FP_REGISTER_P (regno));
4813 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
4816 arith_operand (op, mode)
4818 enum machine_mode mode;
4820 if (arith_reg_operand (op, mode))
4823 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
4829 /* Returns 1 if OP is a valid source operand for a compare insn. */
4832 arith_reg_or_0_operand (op, mode)
4834 enum machine_mode mode;
4836 if (arith_reg_operand (op, mode))
4839 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_N (INTVAL (op)))
4845 /* Returns 1 if OP is a valid source operand for a logical operation. */
4848 logical_operand (op, mode)
4850 enum machine_mode mode;
4852 if (arith_reg_operand (op, mode))
4855 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
4861 /* Nonzero if OP is a floating point value with value 0.0. */
4864 fp_zero_operand (op)
4869 if (GET_MODE (op) != SFmode)
4872 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
4873 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
4876 /* Nonzero if OP is a floating point value with value 1.0. */
4884 if (GET_MODE (op) != SFmode)
4887 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
4888 return REAL_VALUES_EQUAL (r, dconst1);
4891 /* For -m4 and -m4-single-only, mode switching is used. If we are
4892 compiling without -mfmovd, movsf_ie isn't taken into account for
4893 mode switching. We could check in machine_dependent_reorg for
4894 cases where we know we are in single precision mode, but there is
4895 interface to find that out during reload, so we must avoid
4896 choosing an fldi alternative during reload and thus failing to
4897 allocate a scratch register for the constant loading. */
4901 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
4905 tertiary_reload_operand (op, mode)
4907 enum machine_mode mode ATTRIBUTE_UNUSED;
4909 enum rtx_code code = GET_CODE (op);
4910 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
4914 fpscr_operand (op, mode)
4916 enum machine_mode mode ATTRIBUTE_UNUSED;
4918 return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG
4919 && GET_MODE (op) == PSImode);
4923 fpul_operand (op, mode)
4925 enum machine_mode mode;
4927 return (GET_CODE (op) == REG
4928 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
4929 && GET_MODE (op) == mode);
4933 symbol_ref_operand (op, mode)
4935 enum machine_mode mode ATTRIBUTE_UNUSED;
4937 return (GET_CODE (op) == SYMBOL_REF);
4941 commutative_float_operator (op, mode)
4943 enum machine_mode mode;
4945 if (GET_MODE (op) != mode)
4947 switch (GET_CODE (op))
4959 noncommutative_float_operator (op, mode)
4961 enum machine_mode mode;
4963 if (GET_MODE (op) != mode)
4965 switch (GET_CODE (op))
4977 binary_float_operator (op, mode)
4979 enum machine_mode mode;
4981 if (GET_MODE (op) != mode)
4983 switch (GET_CODE (op))
4996 /* Return the destination address of a branch. */
4999 branch_dest (branch)
5002 rtx dest = SET_SRC (PATTERN (branch));
5005 if (GET_CODE (dest) == IF_THEN_ELSE)
5006 dest = XEXP (dest, 1);
5007 dest = XEXP (dest, 0);
5008 dest_uid = INSN_UID (dest);
5009 return INSN_ADDRESSES (dest_uid);
5012 /* Return non-zero if REG is not used after INSN.
5013 We assume REG is a reload reg, and therefore does
5014 not live past labels. It may live past calls or jumps though. */
5016 reg_unused_after (reg, insn)
5023 /* If the reg is set by this instruction, then it is safe for our
5024 case. Disregard the case where this is a store to memory, since
5025 we are checking a register used in the store address. */
5026 set = single_set (insn);
5027 if (set && GET_CODE (SET_DEST (set)) != MEM
5028 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
5031 while ((insn = NEXT_INSN (insn)))
5033 code = GET_CODE (insn);
5036 /* If this is a label that existed before reload, then the register
5037 if dead here. However, if this is a label added by reorg, then
5038 the register may still be live here. We can't tell the difference,
5039 so we just ignore labels completely. */
5040 if (code == CODE_LABEL)
5045 if (code == JUMP_INSN)
5048 /* If this is a sequence, we must handle them all at once.
5049 We could have for instance a call that sets the target register,
5050 and a insn in a delay slot that uses the register. In this case,
5051 we must return 0. */
5052 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
5057 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
5059 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
5060 rtx set = single_set (this_insn);
5062 if (GET_CODE (this_insn) == CALL_INSN)
5064 else if (GET_CODE (this_insn) == JUMP_INSN)
5066 if (INSN_ANNULLED_BRANCH_P (this_insn))
5071 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
5073 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
5075 if (GET_CODE (SET_DEST (set)) != MEM)
5081 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
5086 else if (code == JUMP_INSN)
5089 else if (GET_RTX_CLASS (code) == 'i')
5091 rtx set = single_set (insn);
5093 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
5095 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
5096 return GET_CODE (SET_DEST (set)) != MEM;
5097 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
5101 if (code == CALL_INSN && call_used_regs[REGNO (reg)])
5112 static rtx fpscr_rtx;
5116 fpscr_rtx = gen_rtx (REG, PSImode, FPSCR_REG);
5117 REG_USERVAR_P (fpscr_rtx) = 1;
5118 ggc_add_rtx_root (&fpscr_rtx, 1);
5119 mark_user_reg (fpscr_rtx);
5121 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
5122 mark_user_reg (fpscr_rtx);
5141 expand_sf_unop (fun, operands)
5142 rtx (*fun) PARAMS ((rtx, rtx, rtx));
5145 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
5149 expand_sf_binop (fun, operands)
5150 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
5153 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
5158 expand_df_unop (fun, operands)
5159 rtx (*fun) PARAMS ((rtx, rtx, rtx));
5162 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
5166 expand_df_binop (fun, operands)
5167 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
5170 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
5174 /* ??? gcc does flow analysis strictly after common subexpression
5175 elimination. As a result, common subespression elimination fails
5176 when there are some intervening statements setting the same register.
5177 If we did nothing about this, this would hurt the precision switching
5178 for SH4 badly. There is some cse after reload, but it is unable to
5179 undo the extra register pressure from the unused instructions, and
5180 it cannot remove auto-increment loads.
5182 A C code example that shows this flow/cse weakness for (at least) SH
5183 and sparc (as of gcc ss-970706) is this:
5197 So we add another pass before common subexpression elimination, to
5198 remove assignments that are dead due to a following assignment in the
5199 same basic block. */
5202 mark_use (x, reg_set_block)
5203 rtx x, *reg_set_block;
5209 code = GET_CODE (x);
5214 int regno = REGNO (x);
5215 int nregs = (regno < FIRST_PSEUDO_REGISTER
5216 ? HARD_REGNO_NREGS (regno, GET_MODE (x))
5220 reg_set_block[regno + nregs - 1] = 0;
5227 rtx dest = SET_DEST (x);
5229 if (GET_CODE (dest) == SUBREG)
5230 dest = SUBREG_REG (dest);
5231 if (GET_CODE (dest) != REG)
5232 mark_use (dest, reg_set_block);
5233 mark_use (SET_SRC (x), reg_set_block);
5240 const char *fmt = GET_RTX_FORMAT (code);
5242 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5245 mark_use (XEXP (x, i), reg_set_block);
5246 else if (fmt[i] == 'E')
5247 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5248 mark_use (XVECEXP (x, i, j), reg_set_block);
5255 static rtx get_free_reg PARAMS ((HARD_REG_SET));
5257 /* This function returns a register to use to load the address to load
5258 the fpscr from. Currently it always returns r1 or r7, but when we are
5259 able to use pseudo registers after combine, or have a better mechanism
5260 for choosing a register, it should be done here. */
5261 /* REGS_LIVE is the liveness information for the point for which we
5262 need this allocation. In some bare-bones exit blocks, r1 is live at the
5263 start. We can even have all of r0..r3 being live:
5264 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
5265 INSN before which new insns are placed with will clobber the register
5266 we return. If a basic block consists only of setting the return value
5267 register to a pseudo and using that register, the return value is not
5268 live before or after this block, yet we we'll insert our insns right in
5272 get_free_reg (regs_live)
5273 HARD_REG_SET regs_live;
5275 if (! TEST_HARD_REG_BIT (regs_live, 1))
5276 return gen_rtx_REG (Pmode, 1);
5278 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
5279 there shouldn't be anything but a jump before the function end. */
5280 if (! TEST_HARD_REG_BIT (regs_live, 7))
5281 return gen_rtx_REG (Pmode, 7);
5286 /* This function will set the fpscr from memory.
5287 MODE is the mode we are setting it to. */
5289 fpscr_set_from_mem (mode, regs_live)
5291 HARD_REG_SET regs_live;
5293 enum attr_fp_mode fp_mode = mode;
5294 rtx addr_reg = get_free_reg (regs_live);
5296 if (fp_mode == (enum attr_fp_mode) NORMAL_MODE (FP_MODE))
5297 emit_insn (gen_fpu_switch1 (addr_reg));
5299 emit_insn (gen_fpu_switch0 (addr_reg));
5302 /* Is the given character a logical line separator for the assembler? */
5303 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
5304 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
5308 sh_insn_length_adjustment (insn)
5311 /* Instructions with unfilled delay slots take up an extra two bytes for
5312 the nop in the delay slot. */
5313 if (((GET_CODE (insn) == INSN
5314 && GET_CODE (PATTERN (insn)) != USE
5315 && GET_CODE (PATTERN (insn)) != CLOBBER)
5316 || GET_CODE (insn) == CALL_INSN
5317 || (GET_CODE (insn) == JUMP_INSN
5318 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
5319 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
5320 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
5321 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
5324 /* sh-dsp parallel processing insn take four bytes instead of two. */
5326 if (GET_CODE (insn) == INSN)
5329 rtx body = PATTERN (insn);
5330 const char *template;
5332 int maybe_label = 1;
5334 if (GET_CODE (body) == ASM_INPUT)
5335 template = XSTR (body, 0);
5336 else if (asm_noperands (body) >= 0)
5338 = decode_asm_operands (body, NULL, NULL, NULL, NULL);
5347 while (c == ' ' || c == '\t');
5348 /* all sh-dsp parallel-processing insns start with p.
5349 The only non-ppi sh insn starting with p is pref.
5350 The only ppi starting with pr is prnd. */
5351 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
5353 /* The repeat pseudo-insn expands two three insns, a total of
5354 six bytes in size. */
5355 else if ((c == 'r' || c == 'R')
5356 && ! strncasecmp ("epeat", template, 5))
5358 while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c))
5360 /* If this is a label, it is obviously not a ppi insn. */
5361 if (c == ':' && maybe_label)
5366 else if (c == '\'' || c == '"')
5371 maybe_label = c != ':';
5379 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
5380 isn't protected by a PIC unspec. */
5382 nonpic_symbol_mentioned_p (x)
5385 register const char *fmt;
5388 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
5391 if (GET_CODE (x) == UNSPEC
5392 && (XINT (x, 1) == UNSPEC_PIC
5393 || XINT (x, 1) == UNSPEC_GOT
5394 || XINT (x, 1) == UNSPEC_GOTOFF
5395 || XINT (x, 1) == UNSPEC_PLT))
5398 fmt = GET_RTX_FORMAT (GET_CODE (x));
5399 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5405 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5406 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
5409 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
5416 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
5417 @GOTOFF in `reg'. */
5419 legitimize_pic_address (orig, mode, reg)
5421 enum machine_mode mode ATTRIBUTE_UNUSED;
5424 if (GET_CODE (orig) == LABEL_REF
5425 || (GET_CODE (orig) == SYMBOL_REF
5426 && (CONSTANT_POOL_ADDRESS_P (orig)
5427 /* SYMBOL_REF_FLAG is set on static symbols. */
5428 || SYMBOL_REF_FLAG (orig))))
5431 reg = gen_reg_rtx (Pmode);
5433 emit_insn (gen_symGOTOFF2reg (reg, orig));
5436 else if (GET_CODE (orig) == SYMBOL_REF)
5439 reg = gen_reg_rtx (Pmode);
5441 emit_insn (gen_symGOT2reg (reg, orig));
5447 /* Mark the use of a constant in the literal table. If the constant
5448 has multiple labels, make it unique. */
5449 static rtx mark_constant_pool_use (x)
5452 rtx insn, lab, pattern;
5457 switch (GET_CODE (x))
5467 /* Get the first label in the list of labels for the same constant
5468 and delete another labels in the list. */
5470 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
5472 if (GET_CODE (insn) != CODE_LABEL
5473 || LABEL_REFS (insn) != NEXT_INSN (insn))
5478 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
5479 INSN_DELETED_P (insn) = 1;
5481 /* Mark constants in a window. */
5482 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
5484 if (GET_CODE (insn) != INSN)
5487 pattern = PATTERN (insn);
5488 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
5491 switch (XINT (pattern, 1))
5493 case UNSPECV_CONST2:
5494 case UNSPECV_CONST4:
5495 case UNSPECV_CONST8:
5496 XVECEXP (pattern, 0, 1) = const1_rtx;
5498 case UNSPECV_WINDOW_END:
5499 if (XVECEXP (pattern, 0, 0) == x)
5502 case UNSPECV_CONST_END: