1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
28 #include "insn-config.h"
36 #include "hard-reg-set.h"
38 #include "insn-attr.h"
42 #include "integrate.h"
45 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
53 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
55 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
56 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
58 /* These are some macros to abstract register modes. */
59 #define CONST_OK_FOR_ADD(size) \
60 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
61 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
62 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
63 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
65 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
66 int current_function_interrupt;
68 /* ??? The pragma interrupt support will not work for SH3. */
69 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
70 output code for the next function appropriate for an interrupt handler. */
73 /* This is set by the trap_exit attribute for functions. It specifies
74 a trap number to be used in a trapa instruction at function exit
75 (instead of an rte instruction). */
78 /* This is used by the sp_switch attribute for functions. It specifies
79 a variable holding the address of the stack the interrupt function
80 should switch to/from at entry/exit. */
83 /* This is set by #pragma trapa, and is similar to the above, except that
84 the compiler doesn't emit code to preserve all registers. */
85 static int pragma_trapa;
87 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
88 which has a separate set of low regs for User and Supervisor modes.
89 This should only be used for the lowest level of interrupts. Higher levels
90 of interrupts must save the registers in case they themselves are
92 int pragma_nosave_low_regs;
94 /* This is used for communication between SETUP_INCOMING_VARARGS and
95 sh_expand_prologue. */
96 int current_function_anonymous_args;
98 /* Global variables for machine-dependent things. */
100 /* Which cpu are we scheduling for. */
101 enum processor_type sh_cpu;
103 /* Saved operands from the last compare to use when we generate an scc
109 /* Provides the class number of the smallest class containing
112 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
114 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
147 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
148 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
149 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
150 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
151 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
155 char sh_register_names[FIRST_PSEUDO_REGISTER] \
156 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
158 char sh_additional_register_names[ADDREGNAMES_SIZE] \
159 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
160 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
162 /* Provide reg_class from a letter such as appears in the machine
163 description. *: target independently reserved letter.
164 reg_class_from_letter['e' - 'a'] is set to NO_REGS for TARGET_FMOVD. */
166 enum reg_class reg_class_from_letter[] =
168 /* a */ ALL_REGS, /* b */ TARGET_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
169 /* e */ FP_REGS, /* f */ FP_REGS, /* g **/ NO_REGS, /* h */ NO_REGS,
170 /* i **/ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
171 /* m **/ NO_REGS, /* n **/ NO_REGS, /* o **/ NO_REGS, /* p **/ NO_REGS,
172 /* q */ NO_REGS, /* r **/ NO_REGS, /* s **/ NO_REGS, /* t */ T_REGS,
173 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
174 /* y */ FPUL_REGS, /* z */ R0_REGS
177 int assembler_dialect;
179 static bool shmedia_space_reserved_for_target_registers;
181 static void split_branches (rtx);
182 static int branch_dest (rtx);
183 static void force_into (rtx, rtx);
184 static void print_slot (rtx);
185 static rtx add_constant (rtx, enum machine_mode, rtx);
186 static void dump_table (rtx);
187 static int hi_const (rtx);
188 static int broken_move (rtx);
189 static int mova_p (rtx);
190 static rtx find_barrier (int, rtx, rtx);
191 static int noncall_uses_reg (rtx, rtx, rtx *);
192 static rtx gen_block_redirect (rtx, int, int);
193 static void sh_reorg (void);
194 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
195 static rtx frame_insn (rtx);
196 static rtx push (int);
197 static void pop (int);
198 static void push_regs (HARD_REG_SET *, int);
199 static int calc_live_regs (HARD_REG_SET *);
200 static void mark_use (rtx, rtx *);
201 static HOST_WIDE_INT rounded_frame_size (int);
202 static rtx mark_constant_pool_use (rtx);
203 const struct attribute_spec sh_attribute_table[];
204 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
205 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
206 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
207 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
208 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
209 static void sh_insert_attributes (tree, tree *);
210 static int sh_adjust_cost (rtx, rtx, rtx, int);
211 static int sh_use_dfa_interface (void);
212 static int sh_issue_rate (void);
213 static bool sh_function_ok_for_sibcall (tree, tree);
215 static bool sh_cannot_modify_jumps_p (void);
216 static int sh_target_reg_class (void);
217 static bool sh_optimize_target_register_callee_saved (bool);
218 static bool sh_ms_bitfield_layout_p (tree);
220 static void sh_init_builtins (void);
221 static void sh_media_init_builtins (void);
222 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
223 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
224 static void sh_file_start (void);
225 static int flow_dependent_p (rtx, rtx);
226 static void flow_dependent_p_1 (rtx, rtx, void *);
227 static int shiftcosts (rtx);
228 static int andcosts (rtx);
229 static int addsubcosts (rtx);
230 static int multcosts (rtx);
231 static bool unspec_caller_rtx_p (rtx);
232 static bool sh_cannot_copy_insn_p (rtx);
233 static bool sh_rtx_costs (rtx, int, int, int *);
234 static int sh_address_cost (rtx);
235 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
236 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
237 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
238 static int scavenge_reg (HARD_REG_SET *s);
239 struct save_schedule_s;
240 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
241 struct save_schedule_s *, int);
243 static bool sh_promote_prototypes (tree);
244 static rtx sh_struct_value_rtx (tree, int);
245 static bool sh_return_in_memory (tree, tree);
246 static rtx sh_builtin_saveregs (void);
247 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
248 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
249 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
250 static tree sh_build_builtin_va_list (void);
253 /* Initialize the GCC target structure. */
254 #undef TARGET_ATTRIBUTE_TABLE
255 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
257 /* The next two are used for debug info when compiling with -gdwarf. */
258 #undef TARGET_ASM_UNALIGNED_HI_OP
259 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
260 #undef TARGET_ASM_UNALIGNED_SI_OP
261 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
263 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
264 #undef TARGET_ASM_UNALIGNED_DI_OP
265 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
266 #undef TARGET_ASM_ALIGNED_DI_OP
267 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
269 #undef TARGET_ASM_FUNCTION_EPILOGUE
270 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
272 #undef TARGET_ASM_OUTPUT_MI_THUNK
273 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
275 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
276 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
278 #undef TARGET_ASM_FILE_START
279 #define TARGET_ASM_FILE_START sh_file_start
280 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
281 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
283 #undef TARGET_INSERT_ATTRIBUTES
284 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
286 #undef TARGET_SCHED_ADJUST_COST
287 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
289 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
290 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
292 #undef TARGET_SCHED_ISSUE_RATE
293 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
295 #undef TARGET_CANNOT_MODIFY_JUMPS_P
296 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
297 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
298 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
299 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
300 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
301 sh_optimize_target_register_callee_saved
303 #undef TARGET_MS_BITFIELD_LAYOUT_P
304 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
306 #undef TARGET_INIT_BUILTINS
307 #define TARGET_INIT_BUILTINS sh_init_builtins
308 #undef TARGET_EXPAND_BUILTIN
309 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
311 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
312 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
314 #undef TARGET_CANNOT_COPY_INSN_P
315 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
316 #undef TARGET_RTX_COSTS
317 #define TARGET_RTX_COSTS sh_rtx_costs
318 #undef TARGET_ADDRESS_COST
319 #define TARGET_ADDRESS_COST sh_address_cost
321 #undef TARGET_MACHINE_DEPENDENT_REORG
322 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
325 #undef TARGET_HAVE_TLS
326 #define TARGET_HAVE_TLS true
329 #undef TARGET_PROMOTE_PROTOTYPES
330 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
331 #undef TARGET_PROMOTE_FUNCTION_ARGS
332 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
333 #undef TARGET_PROMOTE_FUNCTION_RETURN
334 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
336 #undef TARGET_STRUCT_VALUE_RTX
337 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
338 #undef TARGET_RETURN_IN_MEMORY
339 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
341 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
342 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
343 #undef TARGET_SETUP_INCOMING_VARARGS
344 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
345 #undef TARGET_STRICT_ARGUMENT_NAMING
346 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
347 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
348 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
350 #undef TARGET_BUILD_BUILTIN_VA_LIST
351 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
353 #undef TARGET_PCH_VALID_P
354 #define TARGET_PCH_VALID_P sh_pch_valid_p
356 struct gcc_target targetm = TARGET_INITIALIZER;
358 /* Print the operand address in x to the stream. */
361 print_operand_address (FILE *stream, rtx x)
363 switch (GET_CODE (x))
367 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
372 rtx base = XEXP (x, 0);
373 rtx index = XEXP (x, 1);
375 switch (GET_CODE (index))
378 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
379 reg_names[true_regnum (base)]);
385 int base_num = true_regnum (base);
386 int index_num = true_regnum (index);
388 fprintf (stream, "@(r0,%s)",
389 reg_names[MAX (base_num, index_num)]);
401 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
405 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
409 x = mark_constant_pool_use (x);
410 output_addr_const (stream, x);
415 /* Print operand x (an rtx) in assembler syntax to file stream
416 according to modifier code.
418 '.' print a .s if insn needs delay slot
419 ',' print LOCAL_LABEL_PREFIX
420 '@' print trap, rte or rts depending upon pragma interruptness
421 '#' output a nop if there is nothing to put in the delay slot
422 ''' print likelihood suffix (/u for unlikely).
423 'O' print a constant without the #
424 'R' print the LSW of a dp value - changes if in little endian
425 'S' print the MSW of a dp value - changes if in little endian
426 'T' print the next word of a dp value - same as 'R' in big endian mode.
427 'M' print an `x' if `m' will print `base,index'.
428 'N' print 'r63' if the operand is (const_int 0).
429 'm' print a pair `base,offset' or `base,index', for LD and ST.
430 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
431 'o' output an operator. */
434 print_operand (FILE *stream, rtx x, int code)
440 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
441 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
442 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
445 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
449 fprintf (stream, "trapa #%d", trap_exit);
450 else if (sh_cfun_interrupt_handler_p ())
451 fprintf (stream, "rte");
453 fprintf (stream, "rts");
456 /* Output a nop if there's nothing in the delay slot. */
457 if (dbr_sequence_length () == 0)
458 fprintf (stream, "\n\tnop");
462 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
464 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
465 fputs ("/u", stream);
469 x = mark_constant_pool_use (x);
470 output_addr_const (stream, x);
473 fputs (reg_names[REGNO (x) + LSW], (stream));
476 fputs (reg_names[REGNO (x) + MSW], (stream));
479 /* Next word of a double. */
480 switch (GET_CODE (x))
483 fputs (reg_names[REGNO (x) + 1], (stream));
486 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
487 && GET_CODE (XEXP (x, 0)) != POST_INC)
488 x = adjust_address (x, SImode, 4);
489 print_operand_address (stream, XEXP (x, 0));
496 switch (GET_CODE (x))
498 case PLUS: fputs ("add", stream); break;
499 case MINUS: fputs ("sub", stream); break;
500 case MULT: fputs ("mul", stream); break;
501 case DIV: fputs ("div", stream); break;
502 case EQ: fputs ("eq", stream); break;
503 case NE: fputs ("ne", stream); break;
504 case GT: case LT: fputs ("gt", stream); break;
505 case GE: case LE: fputs ("ge", stream); break;
506 case GTU: case LTU: fputs ("gtu", stream); break;
507 case GEU: case LEU: fputs ("geu", stream); break;
513 if (GET_CODE (x) == MEM
514 && GET_CODE (XEXP (x, 0)) == PLUS
515 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
516 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
521 if (GET_CODE (x) != MEM)
524 switch (GET_CODE (x))
528 print_operand (stream, x, 0);
529 fputs (", 0", stream);
533 print_operand (stream, XEXP (x, 0), 0);
534 fputs (", ", stream);
535 print_operand (stream, XEXP (x, 1), 0);
544 if (x == CONST0_RTX (GET_MODE (x)))
546 fprintf ((stream), "r63");
551 if (GET_CODE (x) == CONST_INT)
553 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
560 switch (GET_CODE (x))
562 /* FIXME: We need this on SHmedia32 because reload generates
563 some sign-extended HI or QI loads into DImode registers
564 but, because Pmode is SImode, the address ends up with a
565 subreg:SI of the DImode register. Maybe reload should be
566 fixed so as to apply alter_subreg to such loads? */
568 if (SUBREG_BYTE (x) != 0
569 || GET_CODE (SUBREG_REG (x)) != REG)
576 if (FP_REGISTER_P (REGNO (x))
577 && GET_MODE (x) == V16SFmode)
578 fprintf ((stream), "mtrx%s", reg_names[REGNO (x)] + 2);
579 else if (FP_REGISTER_P (REGNO (x))
580 && GET_MODE (x) == V4SFmode)
581 fprintf ((stream), "fv%s", reg_names[REGNO (x)] + 2);
582 else if (GET_CODE (x) == REG
583 && GET_MODE (x) == V2SFmode)
584 fprintf ((stream), "fp%s", reg_names[REGNO (x)] + 2);
585 else if (FP_REGISTER_P (REGNO (x))
586 && GET_MODE_SIZE (GET_MODE (x)) > 4)
587 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
589 fputs (reg_names[REGNO (x)], (stream));
593 output_address (XEXP (x, 0));
598 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
599 && GET_MODE (XEXP (x, 0)) == DImode
600 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
601 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
603 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
606 if (GET_CODE (val) == ASHIFTRT)
609 if (GET_CODE (XEXP (val, 0)) == CONST)
611 output_addr_const (stream, XEXP (val, 0));
612 if (GET_CODE (XEXP (val, 0)) == CONST)
614 fputs (" >> ", stream);
615 output_addr_const (stream, XEXP (val, 1));
620 if (GET_CODE (val) == CONST)
622 output_addr_const (stream, val);
623 if (GET_CODE (val) == CONST)
626 fputs (" & 65535)", stream);
634 output_addr_const (stream, x);
641 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
643 force_into (rtx value, rtx target)
645 value = force_operand (value, target);
646 if (! rtx_equal_p (value, target))
647 emit_insn (gen_move_insn (target, value));
650 /* Emit code to perform a block move. Choose the best method.
652 OPERANDS[0] is the destination.
653 OPERANDS[1] is the source.
654 OPERANDS[2] is the size.
655 OPERANDS[3] is the alignment safe to use. */
658 expand_block_move (rtx *operands)
660 int align = INTVAL (operands[3]);
661 int constp = (GET_CODE (operands[2]) == CONST_INT);
662 int bytes = (constp ? INTVAL (operands[2]) : 0);
664 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
665 alignment, or if it isn't a multiple of 4 bytes, then fail. */
666 if (! constp || align < 4 || (bytes % 4 != 0))
673 else if (bytes == 12)
678 rtx r4 = gen_rtx (REG, SImode, 4);
679 rtx r5 = gen_rtx (REG, SImode, 5);
681 entry_name = get_identifier ("__movstrSI12_i4");
683 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
684 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
685 force_into (XEXP (operands[0], 0), r4);
686 force_into (XEXP (operands[1], 0), r5);
687 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
690 else if (! TARGET_SMALLCODE)
696 rtx r4 = gen_rtx (REG, SImode, 4);
697 rtx r5 = gen_rtx (REG, SImode, 5);
698 rtx r6 = gen_rtx (REG, SImode, 6);
700 entry_name = get_identifier (bytes & 4
702 : "__movstr_i4_even");
703 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
704 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
705 force_into (XEXP (operands[0], 0), r4);
706 force_into (XEXP (operands[1], 0), r5);
709 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
710 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
722 rtx r4 = gen_rtx_REG (SImode, 4);
723 rtx r5 = gen_rtx_REG (SImode, 5);
725 sprintf (entry, "__movstrSI%d", bytes);
726 entry_name = get_identifier (entry);
727 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
728 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
729 force_into (XEXP (operands[0], 0), r4);
730 force_into (XEXP (operands[1], 0), r5);
731 emit_insn (gen_block_move_real (func_addr_rtx));
735 /* This is the same number of bytes as a memcpy call, but to a different
736 less common function name, so this will occasionally use more space. */
737 if (! TARGET_SMALLCODE)
742 int final_switch, while_loop;
743 rtx r4 = gen_rtx_REG (SImode, 4);
744 rtx r5 = gen_rtx_REG (SImode, 5);
745 rtx r6 = gen_rtx_REG (SImode, 6);
747 entry_name = get_identifier ("__movstr");
748 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
749 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
750 force_into (XEXP (operands[0], 0), r4);
751 force_into (XEXP (operands[1], 0), r5);
753 /* r6 controls the size of the move. 16 is decremented from it
754 for each 64 bytes moved. Then the negative bit left over is used
755 as an index into a list of move instructions. e.g., a 72 byte move
756 would be set up with size(r6) = 14, for one iteration through the
757 big while loop, and a switch of -2 for the last part. */
759 final_switch = 16 - ((bytes / 4) % 16);
760 while_loop = ((bytes / 4) / 16 - 1) * 16;
761 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
762 emit_insn (gen_block_lump_real (func_addr_rtx));
769 /* Prepare operands for a move define_expand; specifically, one of the
770 operands must be in a register. */
773 prepare_move_operands (rtx operands[], enum machine_mode mode)
775 if ((mode == SImode || mode == DImode)
777 && ! ((mode == Pmode || mode == ptr_mode)
778 && tls_symbolic_operand (operands[1], Pmode) != 0))
781 if (SYMBOLIC_CONST_P (operands[1]))
783 if (GET_CODE (operands[0]) == MEM)
784 operands[1] = force_reg (Pmode, operands[1]);
785 else if (TARGET_SHMEDIA
786 && GET_CODE (operands[1]) == LABEL_REF
787 && target_reg_operand (operands[0], mode))
791 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
792 operands[1] = legitimize_pic_address (operands[1], mode, temp);
795 else if (GET_CODE (operands[1]) == CONST
796 && GET_CODE (XEXP (operands[1], 0)) == PLUS
797 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
799 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
800 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
802 operands[1] = expand_binop (mode, add_optab, temp,
803 XEXP (XEXP (operands[1], 0), 1),
804 no_new_pseudos ? temp
805 : gen_reg_rtx (Pmode),
810 if (! reload_in_progress && ! reload_completed)
812 /* Copy the source to a register if both operands aren't registers. */
813 if (! register_operand (operands[0], mode)
814 && ! sh_register_operand (operands[1], mode))
815 operands[1] = copy_to_mode_reg (mode, operands[1]);
817 if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode))
819 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
820 except that we can't use that function because it is static. */
821 rtx new = change_address (operands[0], mode, 0);
822 MEM_COPY_ATTRIBUTES (new, operands[0]);
826 /* This case can happen while generating code to move the result
827 of a library call to the target. Reject `st r0,@(rX,rY)' because
828 reload will fail to find a spill register for rX, since r0 is already
829 being used for the source. */
830 else if (refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
831 && GET_CODE (operands[0]) == MEM
832 && GET_CODE (XEXP (operands[0], 0)) == PLUS
833 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
834 operands[1] = copy_to_mode_reg (mode, operands[1]);
837 if (mode == Pmode || mode == ptr_mode)
840 enum tls_model tls_kind;
844 if ((tls_kind = tls_symbolic_operand (op1, Pmode)))
846 rtx tga_op1, tga_ret, tmp, tmp2;
851 case TLS_MODEL_GLOBAL_DYNAMIC:
852 tga_ret = gen_rtx_REG (Pmode, R0_REG);
853 emit_insn (gen_tls_global_dynamic (tga_ret, op1));
857 case TLS_MODEL_LOCAL_DYNAMIC:
858 tga_ret = gen_rtx_REG (Pmode, R0_REG);
859 emit_insn (gen_tls_local_dynamic (tga_ret, op1));
861 tmp = gen_reg_rtx (Pmode);
862 emit_move_insn (tmp, tga_ret);
864 if (register_operand (op0, Pmode))
867 tmp2 = gen_reg_rtx (Pmode);
869 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
873 case TLS_MODEL_INITIAL_EXEC:
875 emit_insn (gen_GOTaddr2picreg ());
876 tga_op1 = gen_reg_rtx (Pmode);
877 tmp = gen_sym2GOTTPOFF (op1);
878 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
882 case TLS_MODEL_LOCAL_EXEC:
883 tmp2 = gen_reg_rtx (Pmode);
884 emit_insn (gen_load_gbr (tmp2));
885 tmp = gen_reg_rtx (Pmode);
886 emit_insn (gen_symTPOFF2reg (tmp, op1));
887 RTX_UNCHANGING_P (tmp) = 1;
889 if (register_operand (op0, Pmode))
892 op1 = gen_reg_rtx (Pmode);
894 emit_insn (gen_addsi3 (op1, tmp, tmp2));
907 /* Prepare the operands for an scc instruction; make sure that the
908 compare has been done. */
910 prepare_scc_operands (enum rtx_code code)
912 rtx t_reg = gen_rtx_REG (SImode, T_REG);
913 enum rtx_code oldcode = code;
914 enum machine_mode mode;
916 /* First need a compare insn. */
920 /* It isn't possible to handle this case. */
939 rtx tmp = sh_compare_op0;
940 sh_compare_op0 = sh_compare_op1;
941 sh_compare_op1 = tmp;
944 mode = GET_MODE (sh_compare_op0);
945 if (mode == VOIDmode)
946 mode = GET_MODE (sh_compare_op1);
948 sh_compare_op0 = force_reg (mode, sh_compare_op0);
949 if ((code != EQ && code != NE
950 && (sh_compare_op1 != const0_rtx
951 || code == GTU || code == GEU || code == LTU || code == LEU))
952 || (mode == DImode && sh_compare_op1 != const0_rtx)
953 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
954 sh_compare_op1 = force_reg (mode, sh_compare_op1);
956 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
957 (mode == SFmode ? emit_sf_insn : emit_df_insn)
958 (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
959 gen_rtx (SET, VOIDmode, t_reg,
960 gen_rtx (code, SImode,
961 sh_compare_op0, sh_compare_op1)),
962 gen_rtx (USE, VOIDmode, get_fpscr_rtx ()))));
964 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
965 gen_rtx (code, SImode, sh_compare_op0,
971 /* Called from the md file, set up the operands of a compare instruction. */
974 from_compare (rtx *operands, int code)
976 enum machine_mode mode = GET_MODE (sh_compare_op0);
978 if (mode == VOIDmode)
979 mode = GET_MODE (sh_compare_op1);
982 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
984 /* Force args into regs, since we can't use constants here. */
985 sh_compare_op0 = force_reg (mode, sh_compare_op0);
986 if (sh_compare_op1 != const0_rtx
987 || code == GTU || code == GEU
988 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
989 sh_compare_op1 = force_reg (mode, sh_compare_op1);
991 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
993 from_compare (operands, GT);
994 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
997 insn = gen_rtx_SET (VOIDmode,
998 gen_rtx_REG (SImode, T_REG),
999 gen_rtx (code, SImode, sh_compare_op0,
1001 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
1003 insn = gen_rtx (PARALLEL, VOIDmode,
1005 gen_rtx (USE, VOIDmode, get_fpscr_rtx ())));
1006 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1012 /* Functions to output assembly code. */
1014 /* Return a sequence of instructions to perform DI or DF move.
1016 Since the SH cannot move a DI or DF in one instruction, we have
1017 to take care when we see overlapping source and dest registers. */
1020 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1021 enum machine_mode mode)
1023 rtx dst = operands[0];
1024 rtx src = operands[1];
1026 if (GET_CODE (dst) == MEM
1027 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
1028 return "mov.l %T1,%0\n\tmov.l %1,%0";
1030 if (register_operand (dst, mode)
1031 && register_operand (src, mode))
1033 if (REGNO (src) == MACH_REG)
1034 return "sts mach,%S0\n\tsts macl,%R0";
1036 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1037 when mov.d r1,r0 do r1->r0 then r2->r1. */
1039 if (REGNO (src) + 1 == REGNO (dst))
1040 return "mov %T1,%T0\n\tmov %1,%0";
1042 return "mov %1,%0\n\tmov %T1,%T0";
1044 else if (GET_CODE (src) == CONST_INT)
1046 if (INTVAL (src) < 0)
1047 output_asm_insn ("mov #-1,%S0", operands);
1049 output_asm_insn ("mov #0,%S0", operands);
1051 return "mov %1,%R0";
1053 else if (GET_CODE (src) == MEM)
1056 int dreg = REGNO (dst);
1057 rtx inside = XEXP (src, 0);
1059 if (GET_CODE (inside) == REG)
1060 ptrreg = REGNO (inside);
1061 else if (GET_CODE (inside) == SUBREG)
1062 ptrreg = subreg_regno (inside);
1063 else if (GET_CODE (inside) == PLUS)
1065 ptrreg = REGNO (XEXP (inside, 0));
1066 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1067 an offsettable address. Unfortunately, offsettable addresses use
1068 QImode to check the offset, and a QImode offsettable address
1069 requires r0 for the other operand, which is not currently
1070 supported, so we can't use the 'o' constraint.
1071 Thus we must check for and handle r0+REG addresses here.
1072 We punt for now, since this is likely very rare. */
1073 if (GET_CODE (XEXP (inside, 1)) == REG)
1076 else if (GET_CODE (inside) == LABEL_REF)
1077 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1078 else if (GET_CODE (inside) == POST_INC)
1079 return "mov.l %1,%0\n\tmov.l %1,%T0";
1083 /* Work out the safe way to copy. Copy into the second half first. */
1085 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1088 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1091 /* Print an instruction which would have gone into a delay slot after
1092 another instruction, but couldn't because the other instruction expanded
1093 into a sequence where putting the slot insn at the end wouldn't work. */
1096 print_slot (rtx insn)
1098 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
1100 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1104 output_far_jump (rtx insn, rtx op)
1106 struct { rtx lab, reg, op; } this;
1107 rtx braf_base_lab = NULL_RTX;
1110 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
1113 this.lab = gen_label_rtx ();
1117 && offset - get_attr_length (insn) <= 32766)
1120 jump = "mov.w %O0,%1; braf %1";
1128 jump = "mov.l %O0,%1; braf %1";
1130 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1133 jump = "mov.l %O0,%1; jmp @%1";
1135 /* If we have a scratch register available, use it. */
1136 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
1137 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1139 this.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
1140 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1141 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1142 output_asm_insn (jump, &this.lab);
1143 if (dbr_sequence_length ())
1144 print_slot (final_sequence);
1146 output_asm_insn ("nop", 0);
1150 /* Output the delay slot insn first if any. */
1151 if (dbr_sequence_length ())
1152 print_slot (final_sequence);
1154 this.reg = gen_rtx_REG (SImode, 13);
1155 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1156 Fortunately, MACL is fixed and call-clobbered, and we never
1157 need its value across jumps, so save r13 in it instead of in
1160 output_asm_insn ("lds r13, macl", 0);
1162 output_asm_insn ("mov.l r13,@-r15", 0);
1163 output_asm_insn (jump, &this.lab);
1165 output_asm_insn ("sts macl, r13", 0);
1167 output_asm_insn ("mov.l @r15+,r13", 0);
1169 if (far && flag_pic && TARGET_SH2)
1171 braf_base_lab = gen_label_rtx ();
1172 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1173 CODE_LABEL_NUMBER (braf_base_lab));
1176 output_asm_insn (".align 2", 0);
1177 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
1179 if (far && flag_pic)
1182 this.lab = braf_base_lab;
1183 output_asm_insn (".long %O2-%O0", &this.lab);
1186 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
1190 /* Local label counter, used for constants in the pool and inside
1191 pattern branches. */
1193 static int lf = 100;
1195 /* Output code for ordinary branches. */
1198 output_branch (int logic, rtx insn, rtx *operands)
1200 switch (get_attr_length (insn))
1203 /* This can happen if filling the delay slot has caused a forward
1204 branch to exceed its range (we could reverse it, but only
1205 when we know we won't overextend other branches; this should
1206 best be handled by relaxation).
1207 It can also happen when other condbranches hoist delay slot insn
1208 from their destination, thus leading to code size increase.
1209 But the branch will still be in the range -4092..+4098 bytes. */
1214 /* The call to print_slot will clobber the operands. */
1215 rtx op0 = operands[0];
1217 /* If the instruction in the delay slot is annulled (true), then
1218 there is no delay slot where we can put it now. The only safe
1219 place for it is after the label. final will do that by default. */
1222 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1224 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
1225 ASSEMBLER_DIALECT ? "/" : ".", label);
1226 print_slot (final_sequence);
1229 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
1231 output_asm_insn ("bra\t%l0", &op0);
1232 fprintf (asm_out_file, "\tnop\n");
1233 (*targetm.asm_out.internal_label)(asm_out_file, "LF", label);
1237 /* When relaxing, handle this like a short branch. The linker
1238 will fix it up if it still doesn't fit after relaxation. */
1240 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
1242 /* These are for SH2e, in which we have to account for the
1243 extra nop because of the hardware bug in annulled branches. */
1250 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1252 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
1254 ASSEMBLER_DIALECT ? "/" : ".", label);
1255 fprintf (asm_out_file, "\tnop\n");
1256 output_asm_insn ("bra\t%l0", operands);
1257 fprintf (asm_out_file, "\tnop\n");
1258 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
1262 /* When relaxing, fall through. */
1267 sprintf (buffer, "b%s%ss\t%%l0",
1269 ASSEMBLER_DIALECT ? "/" : ".");
1270 output_asm_insn (buffer, &operands[0]);
1275 /* There should be no longer branches now - that would
1276 indicate that something has destroyed the branches set
1277 up in machine_dependent_reorg. */
1283 output_branchy_insn (enum rtx_code code, const char *template,
1284 rtx insn, rtx *operands)
1286 rtx next_insn = NEXT_INSN (insn);
1288 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
1290 rtx src = SET_SRC (PATTERN (next_insn));
1291 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
1293 /* Following branch not taken */
1294 operands[9] = gen_label_rtx ();
1295 emit_label_after (operands[9], next_insn);
1296 INSN_ADDRESSES_NEW (operands[9],
1297 INSN_ADDRESSES (INSN_UID (next_insn))
1298 + get_attr_length (next_insn));
1303 int offset = (branch_dest (next_insn)
1304 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
1305 if (offset >= -252 && offset <= 258)
1307 if (GET_CODE (src) == IF_THEN_ELSE)
1309 src = XEXP (src, 1);
1315 operands[9] = gen_label_rtx ();
1316 emit_label_after (operands[9], insn);
1317 INSN_ADDRESSES_NEW (operands[9],
1318 INSN_ADDRESSES (INSN_UID (insn))
1319 + get_attr_length (insn));
1324 output_ieee_ccmpeq (rtx insn, rtx *operands)
1326 return output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
1329 /* Output the start of the assembler file. */
1332 sh_file_start (void)
1334 default_file_start ();
1337 /* We need to show the text section with the proper
1338 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
1339 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
1340 will complain. We can teach GAS specifically about the
1341 default attributes for our choice of text section, but
1342 then we would have to change GAS again if/when we change
1343 the text section name. */
1344 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
1346 /* Switch to the data section so that the coffsem symbol
1347 isn't in the text section. */
1350 if (TARGET_LITTLE_ENDIAN)
1351 fputs ("\t.little\n", asm_out_file);
1355 if (TARGET_SHCOMPACT)
1356 fputs ("\t.mode\tSHcompact\n", asm_out_file);
1357 else if (TARGET_SHMEDIA)
1358 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1359 TARGET_SHMEDIA64 ? 64 : 32);
1363 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
1366 unspec_caller_rtx_p (rtx pat)
1368 switch (GET_CODE (pat))
1371 return unspec_caller_rtx_p (XEXP (pat, 0));
1374 if (unspec_caller_rtx_p (XEXP (pat, 0)))
1376 return unspec_caller_rtx_p (XEXP (pat, 1));
1378 if (XINT (pat, 1) == UNSPEC_CALLER)
1387 /* Indicate that INSN cannot be duplicated. This is true for insn
1388 that generates an unique label. */
1391 sh_cannot_copy_insn_p (rtx insn)
1395 if (!reload_completed || !flag_pic)
1398 if (GET_CODE (insn) != INSN)
1400 if (asm_noperands (insn) >= 0)
1403 pat = PATTERN (insn);
1404 if (GET_CODE (pat) != SET)
1406 pat = SET_SRC (pat);
1408 if (unspec_caller_rtx_p (pat))
1414 /* Actual number of instructions used to make a shift by N. */
1415 static const char ashiftrt_insns[] =
1416 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1418 /* Left shift and logical right shift are the same. */
1419 static const char shift_insns[] =
1420 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1422 /* Individual shift amounts needed to get the above length sequences.
1423 One bit right shifts clobber the T bit, so when possible, put one bit
1424 shifts in the middle of the sequence, so the ends are eligible for
1425 branch delay slots. */
1426 static const short shift_amounts[32][5] = {
1427 {0}, {1}, {2}, {2, 1},
1428 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1429 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1430 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1431 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1432 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1433 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1434 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1436 /* Likewise, but for shift amounts < 16, up to three highmost bits
1437 might be clobbered. This is typically used when combined with some
1438 kind of sign or zero extension. */
1440 static const char ext_shift_insns[] =
1441 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1443 static const short ext_shift_amounts[32][4] = {
1444 {0}, {1}, {2}, {2, 1},
1445 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1446 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1447 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1448 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1449 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1450 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1451 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1453 /* Assuming we have a value that has been sign-extended by at least one bit,
1454 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1455 to shift it by N without data loss, and quicker than by other means? */
1456 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1458 /* This is used in length attributes in sh.md to help compute the length
1459 of arbitrary constant shift instructions. */
1462 shift_insns_rtx (rtx insn)
1464 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1465 int shift_count = INTVAL (XEXP (set_src, 1));
1466 enum rtx_code shift_code = GET_CODE (set_src);
1471 return ashiftrt_insns[shift_count];
1474 return shift_insns[shift_count];
1480 /* Return the cost of a shift. */
1490 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
1492 if (GET_MODE (x) == DImode
1493 && GET_CODE (XEXP (x, 1)) == CONST_INT
1494 && INTVAL (XEXP (x, 1)) == 1)
1497 /* Everything else is invalid, because there is no pattern for it. */
1500 /* If shift by a non constant, then this will be expensive. */
1501 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1502 return SH_DYNAMIC_SHIFT_COST;
1504 value = INTVAL (XEXP (x, 1));
1506 /* Otherwise, return the true cost in instructions. */
1507 if (GET_CODE (x) == ASHIFTRT)
1509 int cost = ashiftrt_insns[value];
1510 /* If SH3, then we put the constant in a reg and use shad. */
1511 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
1512 cost = 1 + SH_DYNAMIC_SHIFT_COST;
1516 return shift_insns[value];
1519 /* Return the cost of an AND operation. */
1526 /* Anding with a register is a single cycle and instruction. */
1527 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1530 i = INTVAL (XEXP (x, 1));
1534 if ((GET_CODE (XEXP (x, 1)) == CONST_INT
1535 && CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
1536 || EXTRA_CONSTRAINT_C16 (XEXP (x, 1)))
1542 /* These constants are single cycle extu.[bw] instructions. */
1543 if (i == 0xff || i == 0xffff)
1545 /* Constants that can be used in an and immediate instruction in a single
1546 cycle, but this requires r0, so make it a little more expensive. */
1547 if (CONST_OK_FOR_K08 (i))
1549 /* Constants that can be loaded with a mov immediate and an and.
1550 This case is probably unnecessary. */
1551 if (CONST_OK_FOR_I08 (i))
1553 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1554 This case is probably unnecessary. */
1558 /* Return the cost of an addition or a subtraction. */
1563 /* Adding a register is a single cycle insn. */
1564 if (GET_CODE (XEXP (x, 1)) == REG
1565 || GET_CODE (XEXP (x, 1)) == SUBREG)
1568 /* Likewise for small constants. */
1569 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1570 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
1574 switch (GET_CODE (XEXP (x, 1)))
1579 return TARGET_SHMEDIA64 ? 5 : 3;
1582 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
1584 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
1586 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
1594 /* Any other constant requires a 2 cycle pc-relative load plus an
1599 /* Return the cost of a multiply. */
1601 multcosts (rtx x ATTRIBUTE_UNUSED)
1608 /* We have a mul insn, so we can never take more than the mul and the
1609 read of the mac reg, but count more because of the latency and extra
1611 if (TARGET_SMALLCODE)
1616 /* If we're aiming at small code, then just count the number of
1617 insns in a multiply call sequence. */
1618 if (TARGET_SMALLCODE)
1621 /* Otherwise count all the insns in the routine we'd be calling too. */
1625 /* Compute a (partial) cost for rtx X. Return true if the complete
1626 cost has been computed, and false if subexpressions should be
1627 scanned. In either case, *TOTAL contains the cost result. */
1630 sh_rtx_costs (rtx x, int code, int outer_code, int *total)
1637 if (INTVAL (x) == 0)
1639 else if (outer_code == AND && and_operand ((x), DImode))
1641 else if ((outer_code == IOR || outer_code == XOR
1642 || outer_code == PLUS)
1643 && CONST_OK_FOR_I10 (INTVAL (x)))
1645 else if (CONST_OK_FOR_I16 (INTVAL (x)))
1646 *total = COSTS_N_INSNS (outer_code != SET);
1647 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
1648 *total = COSTS_N_INSNS (2);
1649 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
1650 *total = COSTS_N_INSNS (3);
1652 *total = COSTS_N_INSNS (4);
1655 if (CONST_OK_FOR_I08 (INTVAL (x)))
1657 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
1658 && CONST_OK_FOR_K08 (INTVAL (x)))
1667 if (TARGET_SHMEDIA64)
1668 *total = COSTS_N_INSNS (4);
1669 else if (TARGET_SHMEDIA32)
1670 *total = COSTS_N_INSNS (2);
1677 *total = COSTS_N_INSNS (4);
1683 *total = COSTS_N_INSNS (addsubcosts (x));
1687 *total = COSTS_N_INSNS (andcosts (x));
1691 *total = COSTS_N_INSNS (multcosts (x));
1697 *total = COSTS_N_INSNS (shiftcosts (x));
1704 *total = COSTS_N_INSNS (20);
1717 /* Compute the cost of an address. For the SH, all valid addresses are
1718 the same cost. Use a slightly higher cost for reg + reg addressing,
1719 since it increases pressure on r0. */
1722 sh_address_cost (rtx X)
1724 return (GET_CODE (X) == PLUS
1725 && ! CONSTANT_P (XEXP (X, 1))
1726 && ! TARGET_SHMEDIA ? 1 : 0);
1729 /* Code to expand a shift. */
1732 gen_ashift (int type, int n, rtx reg)
1734 /* Negative values here come from the shift_amounts array. */
1747 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
1751 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
1753 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
1756 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
1761 /* Same for HImode */
1764 gen_ashift_hi (int type, int n, rtx reg)
1766 /* Negative values here come from the shift_amounts array. */
1780 /* We don't have HImode right shift operations because using the
1781 ordinary 32 bit shift instructions for that doesn't generate proper
1782 zero/sign extension.
1783 gen_ashift_hi is only called in contexts where we know that the
1784 sign extension works out correctly. */
1787 if (GET_CODE (reg) == SUBREG)
1789 offset = SUBREG_BYTE (reg);
1790 reg = SUBREG_REG (reg);
1792 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
1796 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
1801 /* Output RTL to split a constant shift into its component SH constant
1802 shift instructions. */
1805 gen_shifty_op (int code, rtx *operands)
1807 int value = INTVAL (operands[2]);
1810 /* Truncate the shift count in case it is out of bounds. */
1811 value = value & 0x1f;
1815 if (code == LSHIFTRT)
1817 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1818 emit_insn (gen_movt (operands[0]));
1821 else if (code == ASHIFT)
1823 /* There is a two instruction sequence for 31 bit left shifts,
1824 but it requires r0. */
1825 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
1827 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
1828 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1833 else if (value == 0)
1835 /* This can happen when not optimizing. We must output something here
1836 to prevent the compiler from aborting in final.c after the try_split
1838 emit_insn (gen_nop ());
1842 max = shift_insns[value];
1843 for (i = 0; i < max; i++)
1844 gen_ashift (code, shift_amounts[value][i], operands[0]);
1847 /* Same as above, but optimized for values where the topmost bits don't
1851 gen_shifty_hi_op (int code, rtx *operands)
1853 int value = INTVAL (operands[2]);
1855 void (*gen_fun) (int, int, rtx);
1857 /* This operation is used by and_shl for SImode values with a few
1858 high bits known to be cleared. */
1862 emit_insn (gen_nop ());
1866 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
1869 max = ext_shift_insns[value];
1870 for (i = 0; i < max; i++)
1871 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1874 /* When shifting right, emit the shifts in reverse order, so that
1875 solitary negative values come first. */
1876 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
1877 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1880 /* Output RTL for an arithmetic right shift. */
1882 /* ??? Rewrite to use super-optimizer sequences. */
1885 expand_ashiftrt (rtx *operands)
1895 if (GET_CODE (operands[2]) != CONST_INT)
1897 rtx count = copy_to_mode_reg (SImode, operands[2]);
1898 emit_insn (gen_negsi2 (count, count));
1899 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1902 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
1903 > 1 + SH_DYNAMIC_SHIFT_COST)
1906 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
1907 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1911 if (GET_CODE (operands[2]) != CONST_INT)
1914 value = INTVAL (operands[2]) & 31;
1918 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
1921 else if (value >= 16 && value <= 19)
1923 wrk = gen_reg_rtx (SImode);
1924 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
1927 gen_ashift (ASHIFTRT, 1, wrk);
1928 emit_move_insn (operands[0], wrk);
1931 /* Expand a short sequence inline, longer call a magic routine. */
1932 else if (value <= 5)
1934 wrk = gen_reg_rtx (SImode);
1935 emit_move_insn (wrk, operands[1]);
1937 gen_ashift (ASHIFTRT, 1, wrk);
1938 emit_move_insn (operands[0], wrk);
1942 wrk = gen_reg_rtx (Pmode);
1944 /* Load the value into an arg reg and call a helper. */
1945 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1946 sprintf (func, "__ashiftrt_r4_%d", value);
1947 func_name = get_identifier (func);
1948 sym = function_symbol (IDENTIFIER_POINTER (func_name));
1949 emit_move_insn (wrk, sym);
1950 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1951 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
1956 sh_dynamicalize_shift_p (rtx count)
1958 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
1961 /* Try to find a good way to implement the combiner pattern
1962 [(set (match_operand:SI 0 "register_operand" "r")
1963 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1964 (match_operand:SI 2 "const_int_operand" "n"))
1965 (match_operand:SI 3 "const_int_operand" "n"))) .
1966 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1967 return 0 for simple right / left or left/right shift combination.
1968 return 1 for a combination of shifts with zero_extend.
1969 return 2 for a combination of shifts with an AND that needs r0.
1970 return 3 for a combination of shifts with an AND that needs an extra
1971 scratch register, when the three highmost bits of the AND mask are clear.
1972 return 4 for a combination of shifts with an AND that needs an extra
1973 scratch register, when any of the three highmost bits of the AND mask
1975 If ATTRP is set, store an initial right shift width in ATTRP[0],
1976 and the instruction length in ATTRP[1] . These values are not valid
1978 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1979 shift_amounts for the last shift value that is to be used before the
1982 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
1984 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
1985 int left = INTVAL (left_rtx), right;
1987 int cost, best_cost = 10000;
1988 int best_right = 0, best_len = 0;
1992 if (left < 0 || left > 31)
1994 if (GET_CODE (mask_rtx) == CONST_INT)
1995 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
1997 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
1998 /* Can this be expressed as a right shift / left shift pair ? */
1999 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
2000 right = exact_log2 (lsb);
2001 mask2 = ~(mask + lsb - 1);
2002 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
2003 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
2005 best_cost = shift_insns[right] + shift_insns[right + left];
2006 /* mask has no trailing zeroes <==> ! right */
2007 else if (! right && mask2 == ~(lsb2 - 1))
2009 int late_right = exact_log2 (lsb2);
2010 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
2012 /* Try to use zero extend */
2013 if (mask2 == ~(lsb2 - 1))
2017 for (width = 8; width <= 16; width += 8)
2019 /* Can we zero-extend right away? */
2020 if (lsb2 == (unsigned HOST_WIDE_INT)1 << width)
2023 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
2024 if (cost < best_cost)
2035 /* ??? Could try to put zero extend into initial right shift,
2036 or even shift a bit left before the right shift. */
2037 /* Determine value of first part of left shift, to get to the
2038 zero extend cut-off point. */
2039 first = width - exact_log2 (lsb2) + right;
2040 if (first >= 0 && right + left - first >= 0)
2042 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
2043 + ext_shift_insns[right + left - first];
2044 if (cost < best_cost)
2056 /* Try to use r0 AND pattern */
2057 for (i = 0; i <= 2; i++)
2061 if (! CONST_OK_FOR_K08 (mask >> i))
2063 cost = (i != 0) + 2 + ext_shift_insns[left + i];
2064 if (cost < best_cost)
2069 best_len = cost - 1;
2072 /* Try to use a scratch register to hold the AND operand. */
2073 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT)3 << 30)) == 0;
2074 for (i = 0; i <= 2; i++)
2078 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
2079 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
2080 if (cost < best_cost)
2085 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
2091 attrp[0] = best_right;
2092 attrp[1] = best_len;
2097 /* This is used in length attributes of the unnamed instructions
2098 corresponding to shl_and_kind return values of 1 and 2. */
2100 shl_and_length (rtx insn)
2102 rtx set_src, left_rtx, mask_rtx;
2105 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2106 left_rtx = XEXP (XEXP (set_src, 0), 1);
2107 mask_rtx = XEXP (set_src, 1);
2108 shl_and_kind (left_rtx, mask_rtx, attributes);
2109 return attributes[1];
2112 /* This is used in length attribute of the and_shl_scratch instruction. */
2115 shl_and_scr_length (rtx insn)
2117 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2118 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
2119 rtx op = XEXP (set_src, 0);
2120 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
2121 op = XEXP (XEXP (op, 0), 0);
2122 return len + shift_insns[INTVAL (XEXP (op, 1))];
2125 /* Generating rtl? */
2126 extern int rtx_equal_function_value_matters;
2128 /* Generate rtl for instructions for which shl_and_kind advised a particular
2129 method of generating them, i.e. returned zero. */
2132 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
2135 unsigned HOST_WIDE_INT mask;
2136 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
2137 int right, total_shift;
2138 void (*shift_gen_fun) (int, rtx*) = gen_shifty_hi_op;
2140 right = attributes[0];
2141 total_shift = INTVAL (left_rtx) + right;
2142 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
2149 int first = attributes[2];
2154 emit_insn ((mask << right) <= 0xff
2155 ? gen_zero_extendqisi2(dest,
2156 gen_lowpart (QImode, source))
2157 : gen_zero_extendhisi2(dest,
2158 gen_lowpart (HImode, source)));
2162 emit_insn (gen_movsi (dest, source));
2166 operands[2] = GEN_INT (right);
2167 gen_shifty_hi_op (LSHIFTRT, operands);
2171 operands[2] = GEN_INT (first);
2172 gen_shifty_hi_op (ASHIFT, operands);
2173 total_shift -= first;
2177 emit_insn (mask <= 0xff
2178 ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
2179 : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
2180 if (total_shift > 0)
2182 operands[2] = GEN_INT (total_shift);
2183 gen_shifty_hi_op (ASHIFT, operands);
2188 shift_gen_fun = gen_shifty_op;
2190 /* If the topmost bit that matters is set, set the topmost bits
2191 that don't matter. This way, we might be able to get a shorter
2193 if (mask & ((HOST_WIDE_INT)1 << (31 - total_shift)))
2194 mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
2196 /* Don't expand fine-grained when combining, because that will
2197 make the pattern fail. */
2198 if (rtx_equal_function_value_matters
2199 || reload_in_progress || reload_completed)
2203 /* Cases 3 and 4 should be handled by this split
2204 only while combining */
2209 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
2212 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
2217 operands[2] = GEN_INT (total_shift);
2218 shift_gen_fun (ASHIFT, operands);
2225 if (kind != 4 && total_shift < 16)
2227 neg = -ext_shift_amounts[total_shift][1];
2229 neg -= ext_shift_amounts[total_shift][2];
2233 emit_insn (gen_and_shl_scratch (dest, source,
2236 GEN_INT (total_shift + neg),
2238 emit_insn (gen_movsi (dest, dest));
2245 /* Try to find a good way to implement the combiner pattern
2246 [(set (match_operand:SI 0 "register_operand" "=r")
2247 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2248 (match_operand:SI 2 "const_int_operand" "n")
2249 (match_operand:SI 3 "const_int_operand" "n")
2251 (clobber (reg:SI T_REG))]
2252 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
2253 return 0 for simple left / right shift combination.
2254 return 1 for left shift / 8 bit sign extend / left shift.
2255 return 2 for left shift / 16 bit sign extend / left shift.
2256 return 3 for left shift / 8 bit sign extend / shift / sign extend.
2257 return 4 for left shift / 16 bit sign extend / shift / sign extend.
2258 return 5 for left shift / 16 bit sign extend / right shift
2259 return 6 for < 8 bit sign extend / left shift.
2260 return 7 for < 8 bit sign extend / left shift / single right shift.
2261 If COSTP is nonzero, assign the calculated cost to *COSTP. */
2264 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
2266 int left, size, insize, ext;
2267 int cost = 0, best_cost;
2270 left = INTVAL (left_rtx);
2271 size = INTVAL (size_rtx);
2272 insize = size - left;
2275 /* Default to left / right shift. */
2277 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
2280 /* 16 bit shift / sign extend / 16 bit shift */
2281 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
2282 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
2283 below, by alternative 3 or something even better. */
2284 if (cost < best_cost)
2290 /* Try a plain sign extend between two shifts. */
2291 for (ext = 16; ext >= insize; ext -= 8)
2295 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
2296 if (cost < best_cost)
2298 kind = ext / (unsigned) 8;
2302 /* Check if we can do a sloppy shift with a final signed shift
2303 restoring the sign. */
2304 if (EXT_SHIFT_SIGNED (size - ext))
2305 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
2306 /* If not, maybe it's still cheaper to do the second shift sloppy,
2307 and do a final sign extend? */
2308 else if (size <= 16)
2309 cost = ext_shift_insns[ext - insize] + 1
2310 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
2313 if (cost < best_cost)
2315 kind = ext / (unsigned) 8 + 2;
2319 /* Check if we can sign extend in r0 */
2322 cost = 3 + shift_insns[left];
2323 if (cost < best_cost)
2328 /* Try the same with a final signed shift. */
2331 cost = 3 + ext_shift_insns[left + 1] + 1;
2332 if (cost < best_cost)
2341 /* Try to use a dynamic shift. */
2342 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
2343 if (cost < best_cost)
2354 /* Function to be used in the length attribute of the instructions
2355 implementing this pattern. */
2358 shl_sext_length (rtx insn)
2360 rtx set_src, left_rtx, size_rtx;
2363 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2364 left_rtx = XEXP (XEXP (set_src, 0), 1);
2365 size_rtx = XEXP (set_src, 1);
2366 shl_sext_kind (left_rtx, size_rtx, &cost);
2370 /* Generate rtl for this pattern */
2373 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
2376 int left, size, insize, cost;
2379 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
2380 left = INTVAL (left_rtx);
2381 size = INTVAL (size_rtx);
2382 insize = size - left;
2390 int ext = kind & 1 ? 8 : 16;
2391 int shift2 = size - ext;
2393 /* Don't expand fine-grained when combining, because that will
2394 make the pattern fail. */
2395 if (! rtx_equal_function_value_matters
2396 && ! reload_in_progress && ! reload_completed)
2398 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2399 emit_insn (gen_movsi (dest, source));
2403 emit_insn (gen_movsi (dest, source));
2407 operands[2] = GEN_INT (ext - insize);
2408 gen_shifty_hi_op (ASHIFT, operands);
2411 ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
2412 : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
2417 operands[2] = GEN_INT (shift2);
2418 gen_shifty_op (ASHIFT, operands);
2425 if (EXT_SHIFT_SIGNED (shift2))
2427 operands[2] = GEN_INT (shift2 + 1);
2428 gen_shifty_op (ASHIFT, operands);
2429 operands[2] = GEN_INT (1);
2430 gen_shifty_op (ASHIFTRT, operands);
2433 operands[2] = GEN_INT (shift2);
2434 gen_shifty_hi_op (ASHIFT, operands);
2438 operands[2] = GEN_INT (-shift2);
2439 gen_shifty_hi_op (LSHIFTRT, operands);
2441 emit_insn (size <= 8
2442 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
2443 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2450 if (! rtx_equal_function_value_matters
2451 && ! reload_in_progress && ! reload_completed)
2452 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2456 operands[2] = GEN_INT (16 - insize);
2457 gen_shifty_hi_op (ASHIFT, operands);
2458 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2460 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2462 gen_ashift (ASHIFTRT, 1, dest);
2467 /* Don't expand fine-grained when combining, because that will
2468 make the pattern fail. */
2469 if (! rtx_equal_function_value_matters
2470 && ! reload_in_progress && ! reload_completed)
2472 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2473 emit_insn (gen_movsi (dest, source));
2476 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
2477 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
2478 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
2480 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
2481 gen_shifty_op (ASHIFT, operands);
2483 emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
2491 /* Prefix a symbol_ref name with "datalabel". */
2494 gen_datalabel_ref (rtx sym)
2496 if (GET_CODE (sym) == LABEL_REF)
2497 return gen_rtx_CONST (GET_MODE (sym),
2498 gen_rtx_UNSPEC (GET_MODE (sym),
2502 if (GET_CODE (sym) != SYMBOL_REF)
2509 /* The SH cannot load a large constant into a register, constants have to
2510 come from a pc relative load. The reference of a pc relative load
2511 instruction must be less than 1k infront of the instruction. This
2512 means that we often have to dump a constant inside a function, and
2513 generate code to branch around it.
2515 It is important to minimize this, since the branches will slow things
2516 down and make things bigger.
2518 Worst case code looks like:
2536 We fix this by performing a scan before scheduling, which notices which
2537 instructions need to have their operands fetched from the constant table
2538 and builds the table.
2542 scan, find an instruction which needs a pcrel move. Look forward, find the
2543 last barrier which is within MAX_COUNT bytes of the requirement.
2544 If there isn't one, make one. Process all the instructions between
2545 the find and the barrier.
2547 In the above example, we can tell that L3 is within 1k of L1, so
2548 the first move can be shrunk from the 3 insn+constant sequence into
2549 just 1 insn, and the constant moved to L3 to make:
2560 Then the second move becomes the target for the shortening process. */
2564 rtx value; /* Value in table. */
2565 rtx label; /* Label of value. */
2566 rtx wend; /* End of window. */
2567 enum machine_mode mode; /* Mode of value. */
2569 /* True if this constant is accessed as part of a post-increment
2570 sequence. Note that HImode constants are never accessed in this way. */
2571 bool part_of_sequence_p;
2574 /* The maximum number of constants that can fit into one pool, since
2575 the pc relative range is 0...1020 bytes and constants are at least 4
2578 #define MAX_POOL_SIZE (1020/4)
2579 static pool_node pool_vector[MAX_POOL_SIZE];
2580 static int pool_size;
2581 static rtx pool_window_label;
2582 static int pool_window_last;
2584 /* ??? If we need a constant in HImode which is the truncated value of a
2585 constant we need in SImode, we could combine the two entries thus saving
2586 two bytes. Is this common enough to be worth the effort of implementing
2589 /* ??? This stuff should be done at the same time that we shorten branches.
2590 As it is now, we must assume that all branches are the maximum size, and
2591 this causes us to almost always output constant pools sooner than
2594 /* Add a constant to the pool and return its label. */
2597 add_constant (rtx x, enum machine_mode mode, rtx last_value)
2600 rtx lab, new, ref, newref;
2602 /* First see if we've already got it. */
2603 for (i = 0; i < pool_size; i++)
2605 if (x->code == pool_vector[i].value->code
2606 && mode == pool_vector[i].mode)
2608 if (x->code == CODE_LABEL)
2610 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
2613 if (rtx_equal_p (x, pool_vector[i].value))
2618 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
2620 new = gen_label_rtx ();
2621 LABEL_REFS (new) = pool_vector[i].label;
2622 pool_vector[i].label = lab = new;
2624 if (lab && pool_window_label)
2626 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2627 ref = pool_vector[pool_window_last].wend;
2628 LABEL_NEXTREF (newref) = ref;
2629 pool_vector[pool_window_last].wend = newref;
2632 pool_window_label = new;
2633 pool_window_last = i;
2639 /* Need a new one. */
2640 pool_vector[pool_size].value = x;
2641 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
2644 pool_vector[pool_size - 1].part_of_sequence_p = true;
2647 lab = gen_label_rtx ();
2648 pool_vector[pool_size].mode = mode;
2649 pool_vector[pool_size].label = lab;
2650 pool_vector[pool_size].wend = NULL_RTX;
2651 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
2652 if (lab && pool_window_label)
2654 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2655 ref = pool_vector[pool_window_last].wend;
2656 LABEL_NEXTREF (newref) = ref;
2657 pool_vector[pool_window_last].wend = newref;
2660 pool_window_label = lab;
2661 pool_window_last = pool_size;
2666 /* Output the literal table. */
2669 dump_table (rtx scan)
2676 /* Do two passes, first time dump out the HI sized constants. */
2678 for (i = 0; i < pool_size; i++)
2680 pool_node *p = &pool_vector[i];
2682 if (p->mode == HImode)
2686 scan = emit_insn_after (gen_align_2 (), scan);
2689 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2690 scan = emit_label_after (lab, scan);
2691 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
2693 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2695 lab = XEXP (ref, 0);
2696 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2699 else if (p->mode == DFmode)
2705 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
2707 rtx align_insn = NULL_RTX;
2709 scan = emit_label_after (gen_label_rtx (), scan);
2710 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2713 for (i = 0; i < pool_size; i++)
2715 pool_node *p = &pool_vector[i];
2723 if (align_insn && !p->part_of_sequence_p)
2725 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2726 emit_label_before (lab, align_insn);
2727 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
2729 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2731 lab = XEXP (ref, 0);
2732 emit_insn_before (gen_consttable_window_end (lab),
2735 delete_insn (align_insn);
2736 align_insn = NULL_RTX;
2741 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2742 scan = emit_label_after (lab, scan);
2743 scan = emit_insn_after (gen_consttable_4 (p->value,
2745 need_align = ! need_align;
2751 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2756 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2757 scan = emit_label_after (lab, scan);
2758 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2766 if (p->mode != HImode)
2768 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2770 lab = XEXP (ref, 0);
2771 scan = emit_insn_after (gen_consttable_window_end (lab),
2780 for (i = 0; i < pool_size; i++)
2782 pool_node *p = &pool_vector[i];
2793 scan = emit_label_after (gen_label_rtx (), scan);
2794 scan = emit_insn_after (gen_align_4 (), scan);
2796 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2797 scan = emit_label_after (lab, scan);
2798 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
2806 scan = emit_label_after (gen_label_rtx (), scan);
2807 scan = emit_insn_after (gen_align_4 (), scan);
2809 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2810 scan = emit_label_after (lab, scan);
2811 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2819 if (p->mode != HImode)
2821 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2823 lab = XEXP (ref, 0);
2824 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2829 scan = emit_insn_after (gen_consttable_end (), scan);
2830 scan = emit_barrier_after (scan);
2832 pool_window_label = NULL_RTX;
2833 pool_window_last = 0;
2836 /* Return nonzero if constant would be an ok source for a
2837 mov.w instead of a mov.l. */
2842 return (GET_CODE (src) == CONST_INT
2843 && INTVAL (src) >= -32768
2844 && INTVAL (src) <= 32767);
2847 /* Nonzero if the insn is a move instruction which needs to be fixed. */
2849 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2850 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
2851 need to fix it if the input value is CONST_OK_FOR_I08. */
2854 broken_move (rtx insn)
2856 if (GET_CODE (insn) == INSN)
2858 rtx pat = PATTERN (insn);
2859 if (GET_CODE (pat) == PARALLEL)
2860 pat = XVECEXP (pat, 0, 0);
2861 if (GET_CODE (pat) == SET
2862 /* We can load any 8 bit value if we don't care what the high
2863 order bits end up as. */
2864 && GET_MODE (SET_DEST (pat)) != QImode
2865 && (CONSTANT_P (SET_SRC (pat))
2866 /* Match mova_const. */
2867 || (GET_CODE (SET_SRC (pat)) == UNSPEC
2868 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
2869 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
2871 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
2872 && (fp_zero_operand (SET_SRC (pat))
2873 || fp_one_operand (SET_SRC (pat)))
2874 /* ??? If this is a -m4 or -m4-single compilation, in general
2875 we don't know the current setting of fpscr, so disable fldi.
2876 There is an exception if this was a register-register move
2877 before reload - and hence it was ascertained that we have
2878 single precision setting - and in a post-reload optimization
2879 we changed this to do a constant load. In that case
2880 we don't have an r0 clobber, hence we must use fldi. */
2881 && (! TARGET_SH4 || TARGET_FMOVD
2882 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
2884 && GET_CODE (SET_DEST (pat)) == REG
2885 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
2886 && (GET_CODE (SET_SRC (pat)) != CONST_INT
2887 || ! CONST_OK_FOR_I08 (INTVAL (SET_SRC (pat)))))
2897 return (GET_CODE (insn) == INSN
2898 && GET_CODE (PATTERN (insn)) == SET
2899 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
2900 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
2901 /* Don't match mova_const. */
2902 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn)), 0, 0)) == LABEL_REF);
2905 /* Find the last barrier from insn FROM which is close enough to hold the
2906 constant pool. If we can't find one, then create one near the end of
2910 find_barrier (int num_mova, rtx mova, rtx from)
2919 int leading_mova = num_mova;
2920 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
2924 /* For HImode: range is 510, add 4 because pc counts from address of
2925 second instruction after this one, subtract 2 for the jump instruction
2926 that we may need to emit before the table, subtract 2 for the instruction
2927 that fills the jump delay slot (in very rare cases, reorg will take an
2928 instruction from after the constant pool or will leave the delay slot
2929 empty). This gives 510.
2930 For SImode: range is 1020, add 4 because pc counts from address of
2931 second instruction after this one, subtract 2 in case pc is 2 byte
2932 aligned, subtract 2 for the jump instruction that we may need to emit
2933 before the table, subtract 2 for the instruction that fills the jump
2934 delay slot. This gives 1018. */
2936 /* The branch will always be shortened now that the reference address for
2937 forward branches is the successor address, thus we need no longer make
2938 adjustments to the [sh]i_limit for -O0. */
2943 while (from && count_si < si_limit && count_hi < hi_limit)
2945 int inc = get_attr_length (from);
2948 if (GET_CODE (from) == CODE_LABEL)
2951 new_align = 1 << label_to_alignment (from);
2952 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
2953 new_align = 1 << barrier_align (from);
2959 if (GET_CODE (from) == BARRIER)
2962 found_barrier = from;
2964 /* If we are at the end of the function, or in front of an alignment
2965 instruction, we need not insert an extra alignment. We prefer
2966 this kind of barrier. */
2967 if (barrier_align (from) > 2)
2968 good_barrier = from;
2971 if (broken_move (from))
2974 enum machine_mode mode;
2976 pat = PATTERN (from);
2977 if (GET_CODE (pat) == PARALLEL)
2978 pat = XVECEXP (pat, 0, 0);
2979 src = SET_SRC (pat);
2980 dst = SET_DEST (pat);
2981 mode = GET_MODE (dst);
2983 /* We must explicitly check the mode, because sometimes the
2984 front end will generate code to load unsigned constants into
2985 HImode targets without properly sign extending them. */
2987 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
2990 /* We put the short constants before the long constants, so
2991 we must count the length of short constants in the range
2992 for the long constants. */
2993 /* ??? This isn't optimal, but is easy to do. */
2998 /* We dump DF/DI constants before SF/SI ones, because
2999 the limit is the same, but the alignment requirements
3000 are higher. We may waste up to 4 additional bytes
3001 for alignment, and the DF/DI constant may have
3002 another SF/SI constant placed before it. */
3003 if (TARGET_SHCOMPACT
3005 && (mode == DFmode || mode == DImode))
3010 while (si_align > 2 && found_si + si_align - 2 > count_si)
3012 if (found_si > count_si)
3013 count_si = found_si;
3014 found_si += GET_MODE_SIZE (mode);
3016 si_limit -= GET_MODE_SIZE (mode);
3019 /* See the code in machine_dependent_reorg, which has a similar if
3020 statement that generates a new mova insn in many cases. */
3021 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
3031 barrier_before_mova = good_barrier ? good_barrier : found_barrier;
3033 if (found_si > count_si)
3034 count_si = found_si;
3036 else if (GET_CODE (from) == JUMP_INSN
3037 && (GET_CODE (PATTERN (from)) == ADDR_VEC
3038 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
3042 if (barrier_align (next_real_insn (from)) == align_jumps_log)
3044 /* We have just passed the barrier in front of the
3045 ADDR_DIFF_VEC, which is stored in found_barrier. Since
3046 the ADDR_DIFF_VEC is accessed as data, just like our pool
3047 constants, this is a good opportunity to accommodate what
3048 we have gathered so far.
3049 If we waited any longer, we could end up at a barrier in
3050 front of code, which gives worse cache usage for separated
3051 instruction / data caches. */
3052 good_barrier = found_barrier;
3057 rtx body = PATTERN (from);
3058 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
3061 /* For the SH1, we generate alignments even after jumps-around-jumps. */
3062 else if (GET_CODE (from) == JUMP_INSN
3064 && ! TARGET_SMALLCODE)
3070 if (new_align > si_align)
3072 si_limit -= (count_si - 1) & (new_align - si_align);
3073 si_align = new_align;
3075 count_si = (count_si + new_align - 1) & -new_align;
3080 if (new_align > hi_align)
3082 hi_limit -= (count_hi - 1) & (new_align - hi_align);
3083 hi_align = new_align;
3085 count_hi = (count_hi + new_align - 1) & -new_align;
3087 from = NEXT_INSN (from);
3094 /* Try as we might, the leading mova is out of range. Change
3095 it into a load (which will become a pcload) and retry. */
3096 SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3097 INSN_CODE (mova) = -1;
3098 return find_barrier (0, 0, mova);
3102 /* Insert the constant pool table before the mova instruction,
3103 to prevent the mova label reference from going out of range. */
3105 good_barrier = found_barrier = barrier_before_mova;
3111 if (good_barrier && next_real_insn (found_barrier))
3112 found_barrier = good_barrier;
3116 /* We didn't find a barrier in time to dump our stuff,
3117 so we'll make one. */
3118 rtx label = gen_label_rtx ();
3120 /* If we exceeded the range, then we must back up over the last
3121 instruction we looked at. Otherwise, we just need to undo the
3122 NEXT_INSN at the end of the loop. */
3123 if (count_hi > hi_limit || count_si > si_limit)
3124 from = PREV_INSN (PREV_INSN (from));
3126 from = PREV_INSN (from);
3128 /* Walk back to be just before any jump or label.
3129 Putting it before a label reduces the number of times the branch
3130 around the constant pool table will be hit. Putting it before
3131 a jump makes it more likely that the bra delay slot will be
3133 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
3134 || GET_CODE (from) == CODE_LABEL)
3135 from = PREV_INSN (from);
3137 from = emit_jump_insn_after (gen_jump (label), from);
3138 JUMP_LABEL (from) = label;
3139 LABEL_NUSES (label) = 1;
3140 found_barrier = emit_barrier_after (from);
3141 emit_label_after (label, found_barrier);
3144 return found_barrier;
3147 /* If the instruction INSN is implemented by a special function, and we can
3148 positively find the register that is used to call the sfunc, and this
3149 register is not used anywhere else in this instruction - except as the
3150 destination of a set, return this register; else, return 0. */
3152 sfunc_uses_reg (rtx insn)
3155 rtx pattern, part, reg_part, reg;
3157 if (GET_CODE (insn) != INSN)
3159 pattern = PATTERN (insn);
3160 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
3163 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3165 part = XVECEXP (pattern, 0, i);
3166 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
3171 reg = XEXP (reg_part, 0);
3172 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
3174 part = XVECEXP (pattern, 0, i);
3175 if (part == reg_part || GET_CODE (part) == CLOBBER)
3177 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
3178 && GET_CODE (SET_DEST (part)) == REG)
3179 ? SET_SRC (part) : part)))
3185 /* See if the only way in which INSN uses REG is by calling it, or by
3186 setting it while calling it. Set *SET to a SET rtx if the register
3190 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
3196 reg2 = sfunc_uses_reg (insn);
3197 if (reg2 && REGNO (reg2) == REGNO (reg))
3199 pattern = single_set (insn);
3201 && GET_CODE (SET_DEST (pattern)) == REG
3202 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3206 if (GET_CODE (insn) != CALL_INSN)
3208 /* We don't use rtx_equal_p because we don't care if the mode is
3210 pattern = single_set (insn);
3212 && GET_CODE (SET_DEST (pattern)) == REG
3213 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3219 par = PATTERN (insn);
3220 if (GET_CODE (par) == PARALLEL)
3221 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
3223 part = XVECEXP (par, 0, i);
3224 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
3227 return reg_mentioned_p (reg, SET_SRC (pattern));
3233 pattern = PATTERN (insn);
3235 if (GET_CODE (pattern) == PARALLEL)
3239 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3240 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
3242 pattern = XVECEXP (pattern, 0, 0);
3245 if (GET_CODE (pattern) == SET)
3247 if (reg_mentioned_p (reg, SET_DEST (pattern)))
3249 /* We don't use rtx_equal_p, because we don't care if the
3250 mode is different. */
3251 if (GET_CODE (SET_DEST (pattern)) != REG
3252 || REGNO (reg) != REGNO (SET_DEST (pattern)))
3258 pattern = SET_SRC (pattern);
3261 if (GET_CODE (pattern) != CALL
3262 || GET_CODE (XEXP (pattern, 0)) != MEM
3263 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
3269 /* Given a X, a pattern of an insn or a part of it, return a mask of used
3270 general registers. Bits 0..15 mean that the respective registers
3271 are used as inputs in the instruction. Bits 16..31 mean that the
3272 registers 0..15, respectively, are used as outputs, or are clobbered.
3273 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
3275 regs_used (rtx x, int is_dest)
3283 code = GET_CODE (x);
3288 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3289 << (REGNO (x) + is_dest));
3293 rtx y = SUBREG_REG (x);
3295 if (GET_CODE (y) != REG)
3298 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3300 subreg_regno_offset (REGNO (y),
3303 GET_MODE (x)) + is_dest));
3307 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
3309 /* If there was a return value, it must have been indicated with USE. */
3324 fmt = GET_RTX_FORMAT (code);
3326 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3331 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3332 used |= regs_used (XVECEXP (x, i, j), is_dest);
3334 else if (fmt[i] == 'e')
3335 used |= regs_used (XEXP (x, i), is_dest);
3340 /* Create an instruction that prevents redirection of a conditional branch
3341 to the destination of the JUMP with address ADDR.
3342 If the branch needs to be implemented as an indirect jump, try to find
3343 a scratch register for it.
3344 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3345 If any preceding insn that doesn't fit into a delay slot is good enough,
3346 pass 1. Pass 2 if a definite blocking insn is needed.
3347 -1 is used internally to avoid deep recursion.
3348 If a blocking instruction is made or recognized, return it. */
3351 gen_block_redirect (rtx jump, int addr, int need_block)
3354 rtx prev = prev_nonnote_insn (jump);
3357 /* First, check if we already have an instruction that satisfies our need. */
3358 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
3360 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
3362 if (GET_CODE (PATTERN (prev)) == USE
3363 || GET_CODE (PATTERN (prev)) == CLOBBER
3364 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3366 else if ((need_block &= ~1) < 0)
3368 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
3371 if (GET_CODE (PATTERN (jump)) == RETURN)
3375 /* Reorg even does nasty things with return insns that cause branches
3376 to go out of range - see find_end_label and callers. */
3377 return emit_insn_before (gen_block_branch_redirect (GEN_INT (0)) , jump);
3379 /* We can't use JUMP_LABEL here because it might be undefined
3380 when not optimizing. */
3381 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
3382 /* If the branch is out of range, try to find a scratch register for it. */
3384 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3388 /* Don't look for the stack pointer as a scratch register,
3389 it would cause trouble if an interrupt occurred. */
3390 unsigned try = 0x7fff, used;
3391 int jump_left = flag_expensive_optimizations + 1;
3393 /* It is likely that the most recent eligible instruction is wanted for
3394 the delay slot. Therefore, find out which registers it uses, and
3395 try to avoid using them. */
3397 for (scan = jump; (scan = PREV_INSN (scan)); )
3401 if (INSN_DELETED_P (scan))
3403 code = GET_CODE (scan);
3404 if (code == CODE_LABEL || code == JUMP_INSN)
3407 && GET_CODE (PATTERN (scan)) != USE
3408 && GET_CODE (PATTERN (scan)) != CLOBBER
3409 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
3411 try &= ~regs_used (PATTERN (scan), 0);
3415 for (used = dead = 0, scan = JUMP_LABEL (jump);
3416 (scan = NEXT_INSN (scan)); )
3420 if (INSN_DELETED_P (scan))
3422 code = GET_CODE (scan);
3423 if (GET_RTX_CLASS (code) == 'i')
3425 used |= regs_used (PATTERN (scan), 0);
3426 if (code == CALL_INSN)
3427 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
3428 dead |= (used >> 16) & ~used;
3434 if (code == JUMP_INSN)
3436 if (jump_left-- && simplejump_p (scan))
3437 scan = JUMP_LABEL (scan);
3443 /* Mask out the stack pointer again, in case it was
3444 the only 'free' register we have found. */
3447 /* If the immediate destination is still in range, check for possible
3448 threading with a jump beyond the delay slot insn.
3449 Don't check if we are called recursively; the jump has been or will be
3450 checked in a different invocation then. */
3452 else if (optimize && need_block >= 0)
3454 rtx next = next_active_insn (next_active_insn (dest));
3455 if (next && GET_CODE (next) == JUMP_INSN
3456 && GET_CODE (PATTERN (next)) == SET
3457 && recog_memoized (next) == CODE_FOR_jump_compact)
3459 dest = JUMP_LABEL (next);
3461 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3463 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
3469 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
3471 /* It would be nice if we could convert the jump into an indirect
3472 jump / far branch right now, and thus exposing all constituent
3473 instructions to further optimization. However, reorg uses
3474 simplejump_p to determine if there is an unconditional jump where
3475 it should try to schedule instructions from the target of the
3476 branch; simplejump_p fails for indirect jumps even if they have
3478 rtx insn = emit_insn_before (gen_indirect_jump_scratch
3479 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
3481 /* ??? We would like this to have the scope of the jump, but that
3482 scope will change when a delay slot insn of an inner scope is added.
3483 Hence, after delay slot scheduling, we'll have to expect
3484 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
3487 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
3488 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
3491 else if (need_block)
3492 /* We can't use JUMP_LABEL here because it might be undefined
3493 when not optimizing. */
3494 return emit_insn_before (gen_block_branch_redirect
3495 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
3500 #define CONDJUMP_MIN -252
3501 #define CONDJUMP_MAX 262
3504 /* A label (to be placed) in front of the jump
3505 that jumps to our ultimate destination. */
3507 /* Where we are going to insert it if we cannot move the jump any farther,
3508 or the jump itself if we have picked up an existing jump. */
3510 /* The ultimate destination. */
3512 struct far_branch *prev;
3513 /* If the branch has already been created, its address;
3514 else the address of its first prospective user. */
3518 static void gen_far_branch (struct far_branch *);
3519 enum mdep_reorg_phase_e mdep_reorg_phase;
3521 gen_far_branch (struct far_branch *bp)
3523 rtx insn = bp->insert_place;
3525 rtx label = gen_label_rtx ();
3527 emit_label_after (label, insn);
3530 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
3531 LABEL_NUSES (bp->far_label)++;
3534 jump = emit_jump_insn_after (gen_return (), insn);
3535 /* Emit a barrier so that reorg knows that any following instructions
3536 are not reachable via a fall-through path.
3537 But don't do this when not optimizing, since we wouldn't suppress the
3538 alignment for the barrier then, and could end up with out-of-range
3539 pc-relative loads. */
3541 emit_barrier_after (jump);
3542 emit_label_after (bp->near_label, insn);
3543 JUMP_LABEL (jump) = bp->far_label;
3544 if (! invert_jump (insn, label, 1))
3546 /* If we are branching around a jump (rather than a return), prevent
3547 reorg from using an insn from the jump target as the delay slot insn -
3548 when reorg did this, it pessimized code (we rather hide the delay slot)
3549 and it could cause branches to go out of range. */
3552 (gen_stuff_delay_slot
3553 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
3554 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
3556 /* Prevent reorg from undoing our splits. */
3557 gen_block_redirect (jump, bp->address += 2, 2);
3560 /* Fix up ADDR_DIFF_VECs. */
3562 fixup_addr_diff_vecs (rtx first)
3566 for (insn = first; insn; insn = NEXT_INSN (insn))
3568 rtx vec_lab, pat, prev, prevpat, x, braf_label;
3570 if (GET_CODE (insn) != JUMP_INSN
3571 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
3573 pat = PATTERN (insn);
3574 vec_lab = XEXP (XEXP (pat, 0), 0);
3576 /* Search the matching casesi_jump_2. */
3577 for (prev = vec_lab; ; prev = PREV_INSN (prev))
3579 if (GET_CODE (prev) != JUMP_INSN)
3581 prevpat = PATTERN (prev);
3582 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
3584 x = XVECEXP (prevpat, 0, 1);
3585 if (GET_CODE (x) != USE)
3588 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
3592 /* Emit the reference label of the braf where it belongs, right after
3593 the casesi_jump_2 (i.e. braf). */
3594 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
3595 emit_label_after (braf_label, prev);
3597 /* Fix up the ADDR_DIF_VEC to be relative
3598 to the reference address of the braf. */
3599 XEXP (XEXP (pat, 0), 0) = braf_label;
3603 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3604 a barrier. Return the base 2 logarithm of the desired alignment. */
3606 barrier_align (rtx barrier_or_label)
3608 rtx next = next_real_insn (barrier_or_label), pat, prev;
3609 int slot, credit, jump_to_next = 0;
3614 pat = PATTERN (next);
3616 if (GET_CODE (pat) == ADDR_DIFF_VEC)
3619 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
3620 /* This is a barrier in front of a constant table. */
3623 prev = prev_real_insn (barrier_or_label);
3624 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
3626 pat = PATTERN (prev);
3627 /* If this is a very small table, we want to keep the alignment after
3628 the table to the minimum for proper code alignment. */
3629 return ((TARGET_SMALLCODE
3630 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
3631 <= (unsigned)1 << (CACHE_LOG - 2)))
3632 ? 1 << TARGET_SHMEDIA : align_jumps_log);
3635 if (TARGET_SMALLCODE)
3638 if (! TARGET_SH2 || ! optimize)
3639 return align_jumps_log;
3641 /* When fixing up pcloads, a constant table might be inserted just before
3642 the basic block that ends with the barrier. Thus, we can't trust the
3643 instruction lengths before that. */
3644 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
3646 /* Check if there is an immediately preceding branch to the insn beyond
3647 the barrier. We must weight the cost of discarding useful information
3648 from the current cache line when executing this branch and there is
3649 an alignment, against that of fetching unneeded insn in front of the
3650 branch target when there is no alignment. */
3652 /* There are two delay_slot cases to consider. One is the simple case
3653 where the preceding branch is to the insn beyond the barrier (simple
3654 delay slot filling), and the other is where the preceding branch has
3655 a delay slot that is a duplicate of the insn after the barrier
3656 (fill_eager_delay_slots) and the branch is to the insn after the insn
3657 after the barrier. */
3659 /* PREV is presumed to be the JUMP_INSN for the barrier under
3660 investigation. Skip to the insn before it. */
3661 prev = prev_real_insn (prev);
3663 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
3664 credit >= 0 && prev && GET_CODE (prev) == INSN;
3665 prev = prev_real_insn (prev))
3668 if (GET_CODE (PATTERN (prev)) == USE
3669 || GET_CODE (PATTERN (prev)) == CLOBBER)
3671 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
3673 prev = XVECEXP (PATTERN (prev), 0, 1);
3674 if (INSN_UID (prev) == INSN_UID (next))
3676 /* Delay slot was filled with insn at jump target. */
3683 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3685 credit -= get_attr_length (prev);
3688 && GET_CODE (prev) == JUMP_INSN
3689 && JUMP_LABEL (prev))
3693 || next_real_insn (JUMP_LABEL (prev)) == next
3694 /* If relax_delay_slots() decides NEXT was redundant
3695 with some previous instruction, it will have
3696 redirected PREV's jump to the following insn. */
3697 || JUMP_LABEL (prev) == next_nonnote_insn (next)
3698 /* There is no upper bound on redundant instructions
3699 that might have been skipped, but we must not put an
3700 alignment where none had been before. */
3701 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
3703 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
3704 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
3705 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
3707 rtx pat = PATTERN (prev);
3708 if (GET_CODE (pat) == PARALLEL)
3709 pat = XVECEXP (pat, 0, 0);
3710 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
3716 return align_jumps_log;
3719 /* If we are inside a phony loop, almost any kind of label can turn up as the
3720 first one in the loop. Aligning a braf label causes incorrect switch
3721 destination addresses; we can detect braf labels because they are
3722 followed by a BARRIER.
3723 Applying loop alignment to small constant or switch tables is a waste
3724 of space, so we suppress this too. */
3726 sh_loop_align (rtx label)
3731 next = next_nonnote_insn (next);
3732 while (next && GET_CODE (next) == CODE_LABEL);
3736 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
3737 || recog_memoized (next) == CODE_FOR_consttable_2)
3740 return align_loops_log;
3743 /* Do a final pass over the function, just before delayed branch
3749 rtx first, insn, mova = NULL_RTX;
3751 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
3752 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
3754 first = get_insns ();
3756 /* We must split call insns before introducing `mova's. If we're
3757 optimizing, they'll have already been split. Otherwise, make
3758 sure we don't split them too late. */
3760 split_all_insns_noflow ();
3765 /* If relaxing, generate pseudo-ops to associate function calls with
3766 the symbols they call. It does no harm to not generate these
3767 pseudo-ops. However, when we can generate them, it enables to
3768 linker to potentially relax the jsr to a bsr, and eliminate the
3769 register load and, possibly, the constant pool entry. */
3771 mdep_reorg_phase = SH_INSERT_USES_LABELS;
3774 /* Remove all REG_LABEL notes. We want to use them for our own
3775 purposes. This works because none of the remaining passes
3776 need to look at them.
3778 ??? But it may break in the future. We should use a machine
3779 dependent REG_NOTE, or some other approach entirely. */
3780 for (insn = first; insn; insn = NEXT_INSN (insn))
3786 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
3787 remove_note (insn, note);
3791 for (insn = first; insn; insn = NEXT_INSN (insn))
3793 rtx pattern, reg, link, set, scan, dies, label;
3794 int rescan = 0, foundinsn = 0;
3796 if (GET_CODE (insn) == CALL_INSN)
3798 pattern = PATTERN (insn);
3800 if (GET_CODE (pattern) == PARALLEL)
3801 pattern = XVECEXP (pattern, 0, 0);
3802 if (GET_CODE (pattern) == SET)
3803 pattern = SET_SRC (pattern);
3805 if (GET_CODE (pattern) != CALL
3806 || GET_CODE (XEXP (pattern, 0)) != MEM)
3809 reg = XEXP (XEXP (pattern, 0), 0);
3813 reg = sfunc_uses_reg (insn);
3818 if (GET_CODE (reg) != REG)
3821 /* This is a function call via REG. If the only uses of REG
3822 between the time that it is set and the time that it dies
3823 are in function calls, then we can associate all the
3824 function calls with the setting of REG. */
3826 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
3828 if (REG_NOTE_KIND (link) != 0)
3830 set = single_set (XEXP (link, 0));
3831 if (set && rtx_equal_p (reg, SET_DEST (set)))
3833 link = XEXP (link, 0);
3840 /* ??? Sometimes global register allocation will have
3841 deleted the insn pointed to by LOG_LINKS. Try
3842 scanning backward to find where the register is set. */
3843 for (scan = PREV_INSN (insn);
3844 scan && GET_CODE (scan) != CODE_LABEL;
3845 scan = PREV_INSN (scan))
3847 if (! INSN_P (scan))
3850 if (! reg_mentioned_p (reg, scan))
3853 if (noncall_uses_reg (reg, scan, &set))
3867 /* The register is set at LINK. */
3869 /* We can only optimize the function call if the register is
3870 being set to a symbol. In theory, we could sometimes
3871 optimize calls to a constant location, but the assembler
3872 and linker do not support that at present. */
3873 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
3874 && GET_CODE (SET_SRC (set)) != LABEL_REF)
3877 /* Scan forward from LINK to the place where REG dies, and
3878 make sure that the only insns which use REG are
3879 themselves function calls. */
3881 /* ??? This doesn't work for call targets that were allocated
3882 by reload, since there may not be a REG_DEAD note for the
3886 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
3890 /* Don't try to trace forward past a CODE_LABEL if we haven't
3891 seen INSN yet. Ordinarily, we will only find the setting insn
3892 in LOG_LINKS if it is in the same basic block. However,
3893 cross-jumping can insert code labels in between the load and
3894 the call, and can result in situations where a single call
3895 insn may have two targets depending on where we came from. */
3897 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
3900 if (! INSN_P (scan))
3903 /* Don't try to trace forward past a JUMP. To optimize
3904 safely, we would have to check that all the
3905 instructions at the jump destination did not use REG. */
3907 if (GET_CODE (scan) == JUMP_INSN)
3910 if (! reg_mentioned_p (reg, scan))
3913 if (noncall_uses_reg (reg, scan, &scanset))
3920 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
3922 /* There is a function call to this register other
3923 than the one we are checking. If we optimize
3924 this call, we need to rescan again below. */
3928 /* ??? We shouldn't have to worry about SCANSET here.
3929 We should just be able to check for a REG_DEAD note
3930 on a function call. However, the REG_DEAD notes are
3931 apparently not dependable around libcalls; c-torture
3932 execute/920501-2 is a test case. If SCANSET is set,
3933 then this insn sets the register, so it must have
3934 died earlier. Unfortunately, this will only handle
3935 the cases in which the register is, in fact, set in a
3938 /* ??? We shouldn't have to use FOUNDINSN here.
3939 However, the LOG_LINKS fields are apparently not
3940 entirely reliable around libcalls;
3941 newlib/libm/math/e_pow.c is a test case. Sometimes
3942 an insn will appear in LOG_LINKS even though it is
3943 not the most recent insn which sets the register. */
3947 || find_reg_note (scan, REG_DEAD, reg)))
3956 /* Either there was a branch, or some insn used REG
3957 other than as a function call address. */
3961 /* Create a code label, and put it in a REG_LABEL note on
3962 the insn which sets the register, and on each call insn
3963 which uses the register. In final_prescan_insn we look
3964 for the REG_LABEL notes, and output the appropriate label
3967 label = gen_label_rtx ();
3968 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL, label,
3970 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, label,
3979 scan = NEXT_INSN (scan);
3981 && ((GET_CODE (scan) == CALL_INSN
3982 && reg_mentioned_p (reg, scan))
3983 || ((reg2 = sfunc_uses_reg (scan))
3984 && REGNO (reg2) == REGNO (reg))))
3986 = gen_rtx_INSN_LIST (REG_LABEL, label, REG_NOTES (scan));
3988 while (scan != dies);
3994 fixup_addr_diff_vecs (first);
3998 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
3999 shorten_branches (first);
4001 /* Scan the function looking for move instructions which have to be
4002 changed to pc-relative loads and insert the literal tables. */
4004 mdep_reorg_phase = SH_FIXUP_PCLOAD;
4005 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
4012 else if (GET_CODE (insn) == JUMP_INSN
4013 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
4021 /* Some code might have been inserted between the mova and
4022 its ADDR_DIFF_VEC. Check if the mova is still in range. */
4023 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
4024 total += get_attr_length (scan);
4026 /* range of mova is 1020, add 4 because pc counts from address of
4027 second instruction after this one, subtract 2 in case pc is 2
4028 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
4029 cancels out with alignment effects of the mova itself. */
4032 /* Change the mova into a load, and restart scanning
4033 there. broken_move will then return true for mova. */
4034 SET_SRC (PATTERN (mova))
4035 = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4036 INSN_CODE (mova) = -1;
4040 if (broken_move (insn))
4043 /* Scan ahead looking for a barrier to stick the constant table
4045 rtx barrier = find_barrier (num_mova, mova, insn);
4046 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
4048 if (num_mova && ! mova_p (mova))
4050 /* find_barrier had to change the first mova into a
4051 pcload; thus, we have to start with this new pcload. */
4055 /* Now find all the moves between the points and modify them. */
4056 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
4058 if (GET_CODE (scan) == CODE_LABEL)
4060 if (broken_move (scan))
4062 rtx *patp = &PATTERN (scan), pat = *patp;
4066 enum machine_mode mode;
4068 if (GET_CODE (pat) == PARALLEL)
4069 patp = &XVECEXP (pat, 0, 0), pat = *patp;
4070 src = SET_SRC (pat);
4071 dst = SET_DEST (pat);
4072 mode = GET_MODE (dst);
4074 if (mode == SImode && hi_const (src)
4075 && REGNO (dst) != FPUL_REG)
4080 while (GET_CODE (dst) == SUBREG)
4082 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
4083 GET_MODE (SUBREG_REG (dst)),
4086 dst = SUBREG_REG (dst);
4088 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
4091 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
4093 /* This must be an insn that clobbers r0. */
4094 rtx clobber = XVECEXP (PATTERN (scan), 0,
4095 XVECLEN (PATTERN (scan), 0) - 1);
4097 if (GET_CODE (clobber) != CLOBBER
4098 || ! rtx_equal_p (XEXP (clobber, 0), r0_rtx))
4102 && reg_set_between_p (r0_rtx, last_float_move, scan))
4106 && GET_MODE_SIZE (mode) != 4
4107 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
4109 lab = add_constant (src, mode, last_float);
4111 emit_insn_before (gen_mova (lab), scan);
4114 /* There will be a REG_UNUSED note for r0 on
4115 LAST_FLOAT_MOVE; we have to change it to REG_INC,
4116 lest reorg:mark_target_live_regs will not
4117 consider r0 to be used, and we end up with delay
4118 slot insn in front of SCAN that clobbers r0. */
4120 = find_regno_note (last_float_move, REG_UNUSED, 0);
4122 /* If we are not optimizing, then there may not be
4125 PUT_MODE (note, REG_INC);
4127 *last_float_addr = r0_inc_rtx;
4129 last_float_move = scan;
4131 newsrc = gen_rtx (MEM, mode,
4132 (((TARGET_SH4 && ! TARGET_FMOVD)
4133 || REGNO (dst) == FPUL_REG)
4136 last_float_addr = &XEXP (newsrc, 0);
4138 /* Remove the clobber of r0. */
4139 XEXP (clobber, 0) = gen_rtx_SCRATCH (Pmode);
4140 RTX_UNCHANGING_P (newsrc) = 1;
4142 /* This is a mova needing a label. Create it. */
4143 else if (GET_CODE (src) == UNSPEC
4144 && XINT (src, 1) == UNSPEC_MOVA
4145 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
4147 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
4148 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
4149 newsrc = gen_rtx_UNSPEC (SImode,
4150 gen_rtvec (1, newsrc),
4155 lab = add_constant (src, mode, 0);
4156 newsrc = gen_rtx_MEM (mode,
4157 gen_rtx_LABEL_REF (VOIDmode, lab));
4158 RTX_UNCHANGING_P (newsrc) = 1;
4160 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
4161 INSN_CODE (scan) = -1;
4164 dump_table (barrier);
4169 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
4170 INSN_ADDRESSES_FREE ();
4171 split_branches (first);
4173 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
4174 also has an effect on the register that holds the address of the sfunc.
4175 Insert an extra dummy insn in front of each sfunc that pretends to
4176 use this register. */
4177 if (flag_delayed_branch)
4179 for (insn = first; insn; insn = NEXT_INSN (insn))
4181 rtx reg = sfunc_uses_reg (insn);
4185 emit_insn_before (gen_use_sfunc_addr (reg), insn);
4189 /* fpscr is not actually a user variable, but we pretend it is for the
4190 sake of the previous optimization passes, since we want it handled like
4191 one. However, we don't have any debugging information for it, so turn
4192 it into a non-user variable now. */
4194 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
4196 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
4200 get_dest_uid (rtx label, int max_uid)
4202 rtx dest = next_real_insn (label);
4205 /* This can happen for an undefined label. */
4207 dest_uid = INSN_UID (dest);
4208 /* If this is a newly created branch redirection blocking instruction,
4209 we cannot index the branch_uid or insn_addresses arrays with its
4210 uid. But then, we won't need to, because the actual destination is
4211 the following branch. */
4212 while (dest_uid >= max_uid)
4214 dest = NEXT_INSN (dest);
4215 dest_uid = INSN_UID (dest);
4217 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
4222 /* Split condbranches that are out of range. Also add clobbers for
4223 scratch registers that are needed in far jumps.
4224 We do this before delay slot scheduling, so that it can take our
4225 newly created instructions into account. It also allows us to
4226 find branches with common targets more easily. */
4229 split_branches (rtx first)
4232 struct far_branch **uid_branch, *far_branch_list = 0;
4233 int max_uid = get_max_uid ();
4235 /* Find out which branches are out of range. */
4236 shorten_branches (first);
4238 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
4239 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
4241 for (insn = first; insn; insn = NEXT_INSN (insn))
4242 if (! INSN_P (insn))
4244 else if (INSN_DELETED_P (insn))
4246 /* Shorten_branches would split this instruction again,
4247 so transform it into a note. */
4248 PUT_CODE (insn, NOTE);
4249 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4250 NOTE_SOURCE_FILE (insn) = 0;
4252 else if (GET_CODE (insn) == JUMP_INSN
4253 /* Don't mess with ADDR_DIFF_VEC */
4254 && (GET_CODE (PATTERN (insn)) == SET
4255 || GET_CODE (PATTERN (insn)) == RETURN))
4257 enum attr_type type = get_attr_type (insn);
4258 if (type == TYPE_CBRANCH)
4262 if (get_attr_length (insn) > 4)
4264 rtx src = SET_SRC (PATTERN (insn));
4265 rtx olabel = XEXP (XEXP (src, 1), 0);
4266 int addr = INSN_ADDRESSES (INSN_UID (insn));
4268 int dest_uid = get_dest_uid (olabel, max_uid);
4269 struct far_branch *bp = uid_branch[dest_uid];
4271 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
4272 the label if the LABEL_NUSES count drops to zero. There is
4273 always a jump_optimize pass that sets these values, but it
4274 proceeds to delete unreferenced code, and then if not
4275 optimizing, to un-delete the deleted instructions, thus
4276 leaving labels with too low uses counts. */
4279 JUMP_LABEL (insn) = olabel;
4280 LABEL_NUSES (olabel)++;
4284 bp = (struct far_branch *) alloca (sizeof *bp);
4285 uid_branch[dest_uid] = bp;
4286 bp->prev = far_branch_list;
4287 far_branch_list = bp;
4289 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
4290 LABEL_NUSES (bp->far_label)++;
4294 label = bp->near_label;
4295 if (! label && bp->address - addr >= CONDJUMP_MIN)
4297 rtx block = bp->insert_place;
4299 if (GET_CODE (PATTERN (block)) == RETURN)
4300 block = PREV_INSN (block);
4302 block = gen_block_redirect (block,
4304 label = emit_label_after (gen_label_rtx (),
4306 bp->near_label = label;
4308 else if (label && ! NEXT_INSN (label))
4310 if (addr + 2 - bp->address <= CONDJUMP_MAX)
4311 bp->insert_place = insn;
4313 gen_far_branch (bp);
4317 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
4319 bp->near_label = label = gen_label_rtx ();
4320 bp->insert_place = insn;
4323 if (! redirect_jump (insn, label, 1))
4328 /* get_attr_length (insn) == 2 */
4329 /* Check if we have a pattern where reorg wants to redirect
4330 the branch to a label from an unconditional branch that
4332 /* We can't use JUMP_LABEL here because it might be undefined
4333 when not optimizing. */
4334 /* A syntax error might cause beyond to be NULL_RTX. */
4336 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
4340 && (GET_CODE (beyond) == JUMP_INSN
4341 || ((beyond = next_active_insn (beyond))
4342 && GET_CODE (beyond) == JUMP_INSN))
4343 && GET_CODE (PATTERN (beyond)) == SET
4344 && recog_memoized (beyond) == CODE_FOR_jump_compact
4346 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
4347 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4349 gen_block_redirect (beyond,
4350 INSN_ADDRESSES (INSN_UID (beyond)), 1);
4353 next = next_active_insn (insn);
4355 if ((GET_CODE (next) == JUMP_INSN
4356 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
4357 && GET_CODE (PATTERN (next)) == SET
4358 && recog_memoized (next) == CODE_FOR_jump_compact
4360 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
4361 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4363 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
4365 else if (type == TYPE_JUMP || type == TYPE_RETURN)
4367 int addr = INSN_ADDRESSES (INSN_UID (insn));
4370 struct far_branch *bp;
4372 if (type == TYPE_JUMP)
4374 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
4375 dest_uid = get_dest_uid (far_label, max_uid);
4378 /* Parse errors can lead to labels outside
4380 if (! NEXT_INSN (far_label))
4385 JUMP_LABEL (insn) = far_label;
4386 LABEL_NUSES (far_label)++;
4388 redirect_jump (insn, NULL_RTX, 1);
4392 bp = uid_branch[dest_uid];
4395 bp = (struct far_branch *) alloca (sizeof *bp);
4396 uid_branch[dest_uid] = bp;
4397 bp->prev = far_branch_list;
4398 far_branch_list = bp;
4400 bp->far_label = far_label;
4402 LABEL_NUSES (far_label)++;
4404 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
4405 if (addr - bp->address <= CONDJUMP_MAX)
4406 emit_label_after (bp->near_label, PREV_INSN (insn));
4409 gen_far_branch (bp);
4415 bp->insert_place = insn;
4417 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
4419 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
4422 /* Generate all pending far branches,
4423 and free our references to the far labels. */
4424 while (far_branch_list)
4426 if (far_branch_list->near_label
4427 && ! NEXT_INSN (far_branch_list->near_label))
4428 gen_far_branch (far_branch_list);
4430 && far_branch_list->far_label
4431 && ! --LABEL_NUSES (far_branch_list->far_label))
4432 delete_insn (far_branch_list->far_label);
4433 far_branch_list = far_branch_list->prev;
4436 /* Instruction length information is no longer valid due to the new
4437 instructions that have been generated. */
4438 init_insn_lengths ();
4441 /* Dump out instruction addresses, which is useful for debugging the
4442 constant pool table stuff.
4444 If relaxing, output the label and pseudo-ops used to link together
4445 calls and the instruction which set the registers. */
4447 /* ??? The addresses printed by this routine for insns are nonsense for
4448 insns which are inside of a sequence where none of the inner insns have
4449 variable length. This is because the second pass of shorten_branches
4450 does not bother to update them. */
4453 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
4454 int noperands ATTRIBUTE_UNUSED)
4456 if (TARGET_DUMPISIZE)
4457 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
4463 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
4468 pattern = PATTERN (insn);
4469 if (GET_CODE (pattern) == PARALLEL)
4470 pattern = XVECEXP (pattern, 0, 0);
4471 if (GET_CODE (pattern) == CALL
4472 || (GET_CODE (pattern) == SET
4473 && (GET_CODE (SET_SRC (pattern)) == CALL
4474 || get_attr_type (insn) == TYPE_SFUNC)))
4475 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
4476 CODE_LABEL_NUMBER (XEXP (note, 0)));
4477 else if (GET_CODE (pattern) == SET)
4478 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4479 CODE_LABEL_NUMBER (XEXP (note, 0)));
4486 /* Dump out any constants accumulated in the final pass. These will
4490 output_jump_label_table (void)
4496 fprintf (asm_out_file, "\t.align 2\n");
4497 for (i = 0; i < pool_size; i++)
4499 pool_node *p = &pool_vector[i];
4501 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4502 CODE_LABEL_NUMBER (p->label));
4503 output_asm_insn (".long %O0", &p->value);
4511 /* A full frame looks like:
4515 [ if current_function_anonymous_args
4528 local-0 <- fp points here. */
4530 /* Number of bytes pushed for anonymous args, used to pass information
4531 between expand_prologue and expand_epilogue. */
4533 static int extra_push;
4535 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
4536 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
4537 for an epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET
4538 of all the registers that are about to be restored, and hence dead. */
4541 output_stack_adjust (int size, rtx reg, int epilogue_p,
4542 HARD_REG_SET *live_regs_mask)
4544 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
4547 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4552 if (CONST_OK_FOR_ADD (size))
4553 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
4554 /* Try to do it with two partial adjustments; however, we must make
4555 sure that the stack is properly aligned at all times, in case
4556 an interrupt occurs between the two partial adjustments. */
4557 else if (CONST_OK_FOR_ADD (size / 2 & -align)
4558 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
4560 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
4561 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
4567 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
4570 /* If TEMP is invalid, we could temporarily save a general
4571 register to MACL. However, there is currently no need
4572 to handle this case, so just abort when we see it. */
4573 if (current_function_interrupt
4574 || ! call_used_regs[temp] || fixed_regs[temp])
4576 if (temp < 0 && ! current_function_interrupt)
4579 COPY_HARD_REG_SET (temps, call_used_reg_set);
4580 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
4583 for (i = 0; i < HARD_REGNO_NREGS (FIRST_RET_REG, DImode); i++)
4584 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
4585 if (current_function_calls_eh_return)
4587 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
4588 for (i = 0; i <= 3; i++)
4589 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
4594 for (i = FIRST_PARM_REG;
4595 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
4596 CLEAR_HARD_REG_BIT (temps, i);
4597 if (current_function_needs_context)
4598 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
4600 temp = scavenge_reg (&temps);
4602 if (temp < 0 && live_regs_mask)
4603 temp = scavenge_reg (live_regs_mask);
4606 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
4608 /* If SIZE is negative, subtract the positive value.
4609 This sometimes allows a constant pool entry to be shared
4610 between prologue and epilogue code. */
4613 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
4614 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
4618 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
4619 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
4623 = (gen_rtx_EXPR_LIST
4624 (REG_FRAME_RELATED_EXPR,
4625 gen_rtx_SET (VOIDmode, reg,
4626 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
4636 RTX_FRAME_RELATED_P (x) = 1;
4640 /* Output RTL to push register RN onto the stack. */
4647 x = gen_push_fpul ();
4648 else if (rn == FPSCR_REG)
4649 x = gen_push_fpscr ();
4650 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4651 && FP_OR_XD_REGISTER_P (rn))
4653 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4655 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
4657 else if (TARGET_SH2E && FP_REGISTER_P (rn))
4658 x = gen_push_e (gen_rtx_REG (SFmode, rn));
4660 x = gen_push (gen_rtx_REG (SImode, rn));
4664 = gen_rtx_EXPR_LIST (REG_INC,
4665 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4669 /* Output RTL to pop register RN from the stack. */
4676 x = gen_pop_fpul ();
4677 else if (rn == FPSCR_REG)
4678 x = gen_pop_fpscr ();
4679 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4680 && FP_OR_XD_REGISTER_P (rn))
4682 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4684 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
4686 else if (TARGET_SH2E && FP_REGISTER_P (rn))
4687 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
4689 x = gen_pop (gen_rtx_REG (SImode, rn));
4693 = gen_rtx_EXPR_LIST (REG_INC,
4694 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4697 /* Generate code to push the regs specified in the mask. */
4700 push_regs (HARD_REG_SET *mask, int interrupt_handler)
4705 /* Push PR last; this gives better latencies after the prologue, and
4706 candidates for the return delay slot when there are no general
4707 registers pushed. */
4708 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4710 /* If this is an interrupt handler, and the SZ bit varies,
4711 and we have to push any floating point register, we need
4712 to switch to the correct precision first. */
4713 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
4714 && hard_regs_intersect_p (mask, ®_class_contents[DF_REGS]))
4716 HARD_REG_SET unsaved;
4719 COMPL_HARD_REG_SET(unsaved, *mask);
4720 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
4724 && (i != FPSCR_REG || ! skip_fpscr)
4725 && TEST_HARD_REG_BIT (*mask, i))
4728 if (TEST_HARD_REG_BIT (*mask, PR_REG))
4732 /* Calculate how much extra space is needed to save all callee-saved
4734 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4737 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
4740 int stack_space = 0;
4741 int interrupt_handler = sh_cfun_interrupt_handler_p ();
4743 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
4744 if ((! call_used_regs[reg] || interrupt_handler)
4745 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
4746 /* Leave space to save this target register on the stack,
4747 in case target register allocation wants to use it. */
4748 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4752 /* Decide whether we should reserve space for callee-save target registers,
4753 in case target register allocation wants to use them. REGS_SAVED is
4754 the space, in bytes, that is already required for register saves.
4755 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4758 shmedia_reserve_space_for_target_registers_p (int regs_saved,
4759 HARD_REG_SET *live_regs_mask)
4763 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
4766 /* Decide how much space to reserve for callee-save target registers
4767 in case target register allocation wants to use them.
4768 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4771 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
4773 if (shmedia_space_reserved_for_target_registers)
4774 return shmedia_target_regs_stack_space (live_regs_mask);
4779 /* Work out the registers which need to be saved, both as a mask and a
4780 count of saved words. Return the count.
4782 If doing a pragma interrupt function, then push all regs used by the
4783 function, and if we call another function (we can tell by looking at PR),
4784 make sure that all the regs it clobbers are safe too. */
4787 calc_live_regs (HARD_REG_SET *live_regs_mask)
4791 int interrupt_handler;
4792 int pr_live, has_call;
4794 interrupt_handler = sh_cfun_interrupt_handler_p ();
4796 CLEAR_HARD_REG_SET (*live_regs_mask);
4797 if (TARGET_SH4 && TARGET_FMOVD && interrupt_handler
4798 && regs_ever_live[FPSCR_REG])
4799 target_flags &= ~FPU_SINGLE_BIT;
4800 /* If we can save a lot of saves by switching to double mode, do that. */
4801 else if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
4802 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
4803 if (regs_ever_live[reg] && regs_ever_live[reg+1]
4804 && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa))
4807 target_flags &= ~FPU_SINGLE_BIT;
4810 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
4811 knows how to use it. That means the pseudo originally allocated for
4812 the initial value can become the PR_MEDIA_REG hard register, as seen for
4813 execute/20010122-1.c:test9. */
4815 /* ??? this function is called from initial_elimination_offset, hence we
4816 can't use the result of sh_media_register_for_return here. */
4817 pr_live = sh_pr_n_sets ();
4820 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
4821 pr_live = (pr_initial
4822 ? (GET_CODE (pr_initial) != REG
4823 || REGNO (pr_initial) != (PR_REG))
4824 : regs_ever_live[PR_REG]);
4825 /* For Shcompact, if not optimizing, we end up with a memory reference
4826 using the return address pointer for __builtin_return_address even
4827 though there is no actual need to put the PR register on the stack. */
4828 pr_live |= regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM];
4830 /* Force PR to be live if the prologue has to call the SHmedia
4831 argument decoder or register saver. */
4832 if (TARGET_SHCOMPACT
4833 && ((current_function_args_info.call_cookie
4834 & ~ CALL_COOKIE_RET_TRAMP (1))
4835 || current_function_has_nonlocal_label))
4837 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
4838 for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
4840 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
4842 : (interrupt_handler && ! pragma_trapa)
4843 ? (/* Need to save all the regs ever live. */
4844 (regs_ever_live[reg]
4845 || (call_used_regs[reg]
4846 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
4848 || (has_call && REGISTER_NATURAL_MODE (reg) == SImode
4849 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
4850 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
4851 && reg != RETURN_ADDRESS_POINTER_REGNUM
4852 && reg != T_REG && reg != GBR_REG
4853 /* Push fpscr only on targets which have FPU */
4854 && (reg != FPSCR_REG || TARGET_FPU_ANY))
4855 : (/* Only push those regs which are used and need to be saved. */
4858 && current_function_args_info.call_cookie
4859 && reg == (int) PIC_OFFSET_TABLE_REGNUM)
4860 || (regs_ever_live[reg] && ! call_used_regs[reg])
4861 || (current_function_calls_eh_return
4862 && (reg == (int) EH_RETURN_DATA_REGNO (0)
4863 || reg == (int) EH_RETURN_DATA_REGNO (1)
4864 || reg == (int) EH_RETURN_DATA_REGNO (2)
4865 || reg == (int) EH_RETURN_DATA_REGNO (3)))
4866 || ((reg == MACL_REG || reg == MACH_REG)
4867 && regs_ever_live[reg]
4868 && sh_cfun_attr_renesas_p ())
4871 SET_HARD_REG_BIT (*live_regs_mask, reg);
4872 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4874 if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD
4875 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
4877 if (FP_REGISTER_P (reg))
4879 if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
4881 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
4882 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
4885 else if (XD_REGISTER_P (reg))
4887 /* Must switch to double mode to access these registers. */
4888 target_flags &= ~FPU_SINGLE_BIT;
4893 /* If we have a target register optimization pass after prologue / epilogue
4894 threading, we need to assume all target registers will be live even if
4896 if (flag_branch_target_load_optimize2
4897 && TARGET_SAVE_ALL_TARGET_REGS
4898 && shmedia_space_reserved_for_target_registers)
4899 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
4900 if ((! call_used_regs[reg] || interrupt_handler)
4901 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
4903 SET_HARD_REG_BIT (*live_regs_mask, reg);
4904 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4906 /* If this is an interrupt handler, we don't have any call-clobbered
4907 registers we can conveniently use for target register save/restore.
4908 Make sure we save at least one general purpose register when we need
4909 to save target registers. */
4910 if (interrupt_handler
4911 && hard_regs_intersect_p (live_regs_mask,
4912 ®_class_contents[TARGET_REGS])
4913 && ! hard_regs_intersect_p (live_regs_mask,
4914 ®_class_contents[GENERAL_REGS]))
4916 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
4917 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
4923 /* Code to generate prologue and epilogue sequences */
4925 /* PUSHED is the number of bytes that are being pushed on the
4926 stack for register saves. Return the frame size, padded
4927 appropriately so that the stack stays properly aligned. */
4928 static HOST_WIDE_INT
4929 rounded_frame_size (int pushed)
4931 HOST_WIDE_INT size = get_frame_size ();
4932 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4934 return ((size + pushed + align - 1) & -align) - pushed;
4937 /* Choose a call-clobbered target-branch register that remains
4938 unchanged along the whole function. We set it up as the return
4939 value in the prologue. */
4941 sh_media_register_for_return (void)
4946 if (! current_function_is_leaf)
4948 if (lookup_attribute ("interrupt_handler",
4949 DECL_ATTRIBUTES (current_function_decl)))
4952 tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
4954 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
4955 if (call_used_regs[regno] && ! regs_ever_live[regno])
4961 /* The maximum registers we need to save are:
4962 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
4963 - 32 floating point registers (for each pair, we save none,
4964 one single precision value, or a double precision value).
4965 - 8 target registers
4966 - add 1 entry for a delimiter. */
4967 #define MAX_SAVED_REGS (62+32+8)
4969 typedef struct save_entry_s
4978 /* There will be a delimiter entry with VOIDmode both at the start and the
4979 end of a filled in schedule. The end delimiter has the offset of the
4980 save with the smallest (i.e. most negative) offset. */
4981 typedef struct save_schedule_s
4983 save_entry entries[MAX_SAVED_REGS + 2];
4984 int temps[MAX_TEMPS+1];
4987 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
4988 use reverse order. Returns the last entry written to (not counting
4989 the delimiter). OFFSET_BASE is a number to be added to all offset
4993 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
4997 save_entry *entry = schedule->entries;
5001 if (! current_function_interrupt)
5002 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
5003 if (call_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
5004 && ! FUNCTION_ARG_REGNO_P (i)
5005 && i != FIRST_RET_REG
5006 && ! (current_function_needs_context && i == STATIC_CHAIN_REGNUM)
5007 && ! (current_function_calls_eh_return
5008 && (i == EH_RETURN_STACKADJ_REGNO
5009 || ((unsigned)i <= EH_RETURN_DATA_REGNO (0)
5010 && (unsigned)i >= EH_RETURN_DATA_REGNO (3)))))
5011 schedule->temps[tmpx++] = i;
5013 entry->mode = VOIDmode;
5014 entry->offset = offset_base;
5016 /* We loop twice: first, we save 8-byte aligned registers in the
5017 higher addresses, that are known to be aligned. Then, we
5018 proceed to saving 32-bit registers that don't need 8-byte
5020 If this is an interrupt function, all registers that need saving
5021 need to be saved in full. moreover, we need to postpone saving
5022 target registers till we have saved some general purpose registers
5023 we can then use as scratch registers. */
5024 offset = offset_base;
5025 for (align = 1; align >= 0; align--)
5027 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
5028 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
5030 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5033 if (current_function_interrupt)
5035 if (TARGET_REGISTER_P (i))
5037 if (GENERAL_REGISTER_P (i))
5040 if (mode == SFmode && (i % 2) == 1
5041 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5042 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
5049 /* If we're doing the aligned pass and this is not aligned,
5050 or we're doing the unaligned pass and this is aligned,
5052 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
5056 if (current_function_interrupt
5057 && GENERAL_REGISTER_P (i)
5058 && tmpx < MAX_TEMPS)
5059 schedule->temps[tmpx++] = i;
5061 offset -= GET_MODE_SIZE (mode);
5064 entry->offset = offset;
5067 if (align && current_function_interrupt)
5068 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
5069 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
5071 offset -= GET_MODE_SIZE (DImode);
5073 entry->mode = DImode;
5074 entry->offset = offset;
5079 entry->mode = VOIDmode;
5080 entry->offset = offset;
5081 schedule->temps[tmpx] = -1;
5086 sh_expand_prologue (void)
5088 HARD_REG_SET live_regs_mask;
5091 int save_flags = target_flags;
5093 current_function_interrupt = sh_cfun_interrupt_handler_p ();
5095 /* We have pretend args if we had an object sent partially in registers
5096 and partially on the stack, e.g. a large structure. */
5097 output_stack_adjust (-current_function_pretend_args_size
5098 - current_function_args_info.stack_regs * 8,
5099 stack_pointer_rtx, 0, NULL);
5103 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
5104 /* We're going to use the PIC register to load the address of the
5105 incoming-argument decoder and/or of the return trampoline from
5106 the GOT, so make sure the PIC register is preserved and
5108 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
5110 if (TARGET_SHCOMPACT
5111 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
5115 /* First, make all registers with incoming arguments that will
5116 be pushed onto the stack live, so that register renaming
5117 doesn't overwrite them. */
5118 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
5119 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
5120 >= NPARM_REGS (SImode) - reg)
5121 for (; reg < NPARM_REGS (SImode); reg++)
5122 emit_insn (gen_shcompact_preserve_incoming_args
5123 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
5124 else if (CALL_COOKIE_INT_REG_GET
5125 (current_function_args_info.call_cookie, reg) == 1)
5126 emit_insn (gen_shcompact_preserve_incoming_args
5127 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
5129 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
5131 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
5132 GEN_INT (current_function_args_info.call_cookie));
5133 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
5134 gen_rtx_REG (SImode, R0_REG));
5136 else if (TARGET_SHMEDIA)
5138 int tr = sh_media_register_for_return ();
5142 rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr),
5143 gen_rtx_REG (DImode, PR_MEDIA_REG));
5145 /* ??? We should suppress saving pr when we don't need it, but this
5146 is tricky because of builtin_return_address. */
5148 /* If this function only exits with sibcalls, this copy
5149 will be flagged as dead. */
5150 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5156 /* Emit the code for SETUP_VARARGS. */
5157 if (current_function_stdarg)
5159 /* This is not used by the SH2E calling convention */
5160 if (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5
5161 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
5163 /* Push arg regs as if they'd been provided by caller in stack. */
5164 for (i = 0; i < NPARM_REGS(SImode); i++)
5166 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
5169 if (i >= (NPARM_REGS(SImode)
5170 - current_function_args_info.arg_count[(int) SH_ARG_INT]
5174 RTX_FRAME_RELATED_P (insn) = 0;
5180 /* If we're supposed to switch stacks at function entry, do so now. */
5182 emit_insn (gen_sp_switch_1 ());
5184 d = calc_live_regs (&live_regs_mask);
5185 /* ??? Maybe we could save some switching if we can move a mode switch
5186 that already happens to be at the function start into the prologue. */
5187 if (target_flags != save_flags && ! current_function_interrupt)
5188 emit_insn (gen_toggle_sz ());
5192 int offset_base, offset;
5194 int offset_in_r0 = -1;
5196 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
5197 int total_size, save_size;
5198 save_schedule schedule;
5202 if (call_used_regs[R0_REG] && ! fixed_regs[R0_REG]
5203 && ! current_function_interrupt)
5204 r0 = gen_rtx_REG (Pmode, R0_REG);
5206 /* D is the actual number of bytes that we need for saving registers,
5207 however, in initial_elimination_offset we have committed to using
5208 an additional TREGS_SPACE amount of bytes - in order to keep both
5209 addresses to arguments supplied by the caller and local variables
5210 valid, we must keep this gap. Place it between the incoming
5211 arguments and the actually saved registers in a bid to optimize
5212 locality of reference. */
5213 total_size = d + tregs_space;
5214 total_size += rounded_frame_size (total_size);
5215 save_size = total_size - rounded_frame_size (d);
5216 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
5217 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5218 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
5220 /* If adjusting the stack in a single step costs nothing extra, do so.
5221 I.e. either if a single addi is enough, or we need a movi anyway,
5222 and we don't exceed the maximum offset range (the test for the
5223 latter is conservative for simplicity). */
5225 && (CONST_OK_FOR_I10 (-total_size)
5226 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
5227 && total_size <= 2044)))
5228 d_rounding = total_size - save_size;
5230 offset_base = d + d_rounding;
5232 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
5235 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
5236 tmp_pnt = schedule.temps;
5237 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
5239 enum machine_mode mode = entry->mode;
5240 int reg = entry->reg;
5241 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
5243 offset = entry->offset;
5245 reg_rtx = gen_rtx_REG (mode, reg);
5247 mem_rtx = gen_rtx_MEM (mode,
5248 gen_rtx_PLUS (Pmode,
5252 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
5260 if (HAVE_PRE_DECREMENT
5261 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
5262 || mem_rtx == NULL_RTX
5263 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
5265 pre_dec = gen_rtx_MEM (mode,
5266 gen_rtx_PRE_DEC (Pmode, r0));
5268 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
5277 offset += GET_MODE_SIZE (mode);
5281 if (mem_rtx != NULL_RTX)
5284 if (offset_in_r0 == -1)
5286 emit_move_insn (r0, GEN_INT (offset));
5287 offset_in_r0 = offset;
5289 else if (offset != offset_in_r0)
5294 GEN_INT (offset - offset_in_r0)));
5295 offset_in_r0 += offset - offset_in_r0;
5298 if (pre_dec != NULL_RTX)
5304 (Pmode, r0, stack_pointer_rtx));
5308 offset -= GET_MODE_SIZE (mode);
5309 offset_in_r0 -= GET_MODE_SIZE (mode);
5314 mem_rtx = gen_rtx_MEM (mode, r0);
5316 mem_rtx = gen_rtx_MEM (mode,
5317 gen_rtx_PLUS (Pmode,
5321 /* We must not use an r0-based address for target-branch
5322 registers or for special registers without pre-dec
5323 memory addresses, since we store their values in r0
5325 if (TARGET_REGISTER_P (reg)
5326 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5327 && mem_rtx != pre_dec))
5331 if (TARGET_REGISTER_P (reg)
5332 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5333 && mem_rtx != pre_dec))
5335 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
5337 emit_move_insn (tmp_reg, reg_rtx);
5339 if (REGNO (tmp_reg) == R0_REG)
5343 if (refers_to_regno_p (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0))
5347 if (*++tmp_pnt <= 0)
5348 tmp_pnt = schedule.temps;
5355 /* Mark as interesting for dwarf cfi generator */
5356 insn = emit_move_insn (mem_rtx, reg_rtx);
5357 RTX_FRAME_RELATED_P (insn) = 1;
5359 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
5361 rtx reg_rtx = gen_rtx_REG (mode, reg);
5363 rtx mem_rtx = gen_rtx_MEM (mode,
5364 gen_rtx_PLUS (Pmode,
5368 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
5369 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
5371 REG_NOTES (insn) = note_rtx;
5376 if (entry->offset != d_rounding)
5380 push_regs (&live_regs_mask, current_function_interrupt);
5382 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5384 rtx insn = get_last_insn ();
5385 rtx last = emit_insn (gen_GOTaddr2picreg ());
5387 /* Mark these insns as possibly dead. Sometimes, flow2 may
5388 delete all uses of the PIC register. In this case, let it
5389 delete the initialization too. */
5392 insn = NEXT_INSN (insn);
5394 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5398 while (insn != last);
5401 if (SHMEDIA_REGS_STACK_ADJUST ())
5403 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5404 function_symbol (TARGET_FPU_ANY
5405 ? "__GCC_push_shmedia_regs"
5406 : "__GCC_push_shmedia_regs_nofpu"));
5407 /* This must NOT go through the PLT, otherwise mach and macl
5408 may be clobbered. */
5409 emit_insn (gen_shmedia_save_restore_regs_compact
5410 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
5413 if (target_flags != save_flags && ! current_function_interrupt)
5415 rtx insn = emit_insn (gen_toggle_sz ());
5417 /* If we're lucky, a mode switch in the function body will
5418 overwrite fpscr, turning this insn dead. Tell flow this
5419 insn is ok to delete. */
5420 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5425 target_flags = save_flags;
5427 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
5428 stack_pointer_rtx, 0, NULL);
5430 if (frame_pointer_needed)
5431 frame_insn (GEN_MOV (frame_pointer_rtx, stack_pointer_rtx));
5433 if (TARGET_SHCOMPACT
5434 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
5436 /* This must NOT go through the PLT, otherwise mach and macl
5437 may be clobbered. */
5438 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5439 function_symbol ("__GCC_shcompact_incoming_args"));
5440 emit_insn (gen_shcompact_incoming_args ());
5445 sh_expand_epilogue (void)
5447 HARD_REG_SET live_regs_mask;
5451 int save_flags = target_flags;
5452 int frame_size, save_size;
5453 int fpscr_deferred = 0;
5455 d = calc_live_regs (&live_regs_mask);
5458 frame_size = rounded_frame_size (d);
5462 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
5464 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
5465 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5466 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
5468 total_size = d + tregs_space;
5469 total_size += rounded_frame_size (total_size);
5470 save_size = total_size - frame_size;
5472 /* If adjusting the stack in a single step costs nothing extra, do so.
5473 I.e. either if a single addi is enough, or we need a movi anyway,
5474 and we don't exceed the maximum offset range (the test for the
5475 latter is conservative for simplicity). */
5477 && ! frame_pointer_needed
5478 && (CONST_OK_FOR_I10 (total_size)
5479 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
5480 && total_size <= 2044)))
5481 d_rounding = frame_size;
5483 frame_size -= d_rounding;
5486 if (frame_pointer_needed)
5488 output_stack_adjust (frame_size, frame_pointer_rtx, 1, &live_regs_mask);
5490 /* We must avoid moving the stack pointer adjustment past code
5491 which reads from the local frame, else an interrupt could
5492 occur after the SP adjustment and clobber data in the local
5494 emit_insn (gen_blockage ());
5495 emit_insn (GEN_MOV (stack_pointer_rtx, frame_pointer_rtx));
5497 else if (frame_size)
5499 /* We must avoid moving the stack pointer adjustment past code
5500 which reads from the local frame, else an interrupt could
5501 occur after the SP adjustment and clobber data in the local
5503 emit_insn (gen_blockage ());
5504 output_stack_adjust (frame_size, stack_pointer_rtx, 1, &live_regs_mask);
5507 if (SHMEDIA_REGS_STACK_ADJUST ())
5509 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5510 function_symbol (TARGET_FPU_ANY
5511 ? "__GCC_pop_shmedia_regs"
5512 : "__GCC_pop_shmedia_regs_nofpu"));
5513 /* This must NOT go through the PLT, otherwise mach and macl
5514 may be clobbered. */
5515 emit_insn (gen_shmedia_save_restore_regs_compact
5516 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
5519 /* Pop all the registers. */
5521 if (target_flags != save_flags && ! current_function_interrupt)
5522 emit_insn (gen_toggle_sz ());
5525 int offset_base, offset;
5526 int offset_in_r0 = -1;
5528 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
5529 save_schedule schedule;
5533 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
5534 offset_base = -entry[1].offset + d_rounding;
5535 tmp_pnt = schedule.temps;
5536 for (; entry->mode != VOIDmode; entry--)
5538 enum machine_mode mode = entry->mode;
5539 int reg = entry->reg;
5540 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
5542 offset = offset_base + entry->offset;
5543 reg_rtx = gen_rtx_REG (mode, reg);
5545 mem_rtx = gen_rtx_MEM (mode,
5546 gen_rtx_PLUS (Pmode,
5550 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
5556 if (HAVE_POST_INCREMENT
5557 && (offset == offset_in_r0
5558 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
5559 && mem_rtx == NULL_RTX)
5560 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
5562 post_inc = gen_rtx_MEM (mode,
5563 gen_rtx_POST_INC (Pmode, r0));
5565 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
5568 post_inc = NULL_RTX;
5577 if (mem_rtx != NULL_RTX)
5580 if (offset_in_r0 == -1)
5582 emit_move_insn (r0, GEN_INT (offset));
5583 offset_in_r0 = offset;
5585 else if (offset != offset_in_r0)
5590 GEN_INT (offset - offset_in_r0)));
5591 offset_in_r0 += offset - offset_in_r0;
5594 if (post_inc != NULL_RTX)
5600 (Pmode, r0, stack_pointer_rtx));
5606 offset_in_r0 += GET_MODE_SIZE (mode);
5609 mem_rtx = gen_rtx_MEM (mode, r0);
5611 mem_rtx = gen_rtx_MEM (mode,
5612 gen_rtx_PLUS (Pmode,
5616 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5617 && mem_rtx != post_inc)
5621 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5622 && mem_rtx != post_inc)
5624 insn = emit_move_insn (r0, mem_rtx);
5627 else if (TARGET_REGISTER_P (reg))
5629 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
5631 /* Give the scheduler a bit of freedom by using up to
5632 MAX_TEMPS registers in a round-robin fashion. */
5633 insn = emit_move_insn (tmp_reg, mem_rtx);
5636 tmp_pnt = schedule.temps;
5639 insn = emit_move_insn (reg_rtx, mem_rtx);
5640 if (reg == PR_MEDIA_REG && sh_media_register_for_return () >= 0)
5641 /* This is dead, unless we return with a sibcall. */
5642 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5647 if (entry->offset + offset_base != d + d_rounding)
5650 else /* ! TARGET_SH5 */
5653 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
5655 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5657 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
5659 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
5660 && hard_regs_intersect_p (&live_regs_mask,
5661 ®_class_contents[DF_REGS]))
5663 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j))
5665 if (j == FIRST_FP_REG && fpscr_deferred)
5670 if (target_flags != save_flags && ! current_function_interrupt)
5671 emit_insn (gen_toggle_sz ());
5672 target_flags = save_flags;
5674 output_stack_adjust (extra_push + current_function_pretend_args_size
5675 + save_size + d_rounding
5676 + current_function_args_info.stack_regs * 8,
5677 stack_pointer_rtx, 1, NULL);
5679 if (current_function_calls_eh_return)
5680 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
5681 EH_RETURN_STACKADJ_RTX));
5683 /* Switch back to the normal stack if necessary. */
5685 emit_insn (gen_sp_switch_2 ());
5687 /* Tell flow the insn that pops PR isn't dead. */
5688 /* PR_REG will never be live in SHmedia mode, and we don't need to
5689 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
5690 by the return pattern. */
5691 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
5692 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
5695 static int sh_need_epilogue_known = 0;
5698 sh_need_epilogue (void)
5700 if (! sh_need_epilogue_known)
5705 sh_expand_epilogue ();
5706 epilogue = get_insns ();
5708 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
5710 return sh_need_epilogue_known > 0;
5713 /* Emit code to change the current function's return address to RA.
5714 TEMP is available as a scratch register, if needed. */
5717 sh_set_return_address (rtx ra, rtx tmp)
5719 HARD_REG_SET live_regs_mask;
5721 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
5724 d = calc_live_regs (&live_regs_mask);
5726 /* If pr_reg isn't life, we can set it (or the register given in
5727 sh_media_register_for_return) directly. */
5728 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
5734 int rr_regno = sh_media_register_for_return ();
5739 rr = gen_rtx_REG (DImode, rr_regno);
5742 rr = gen_rtx_REG (SImode, pr_reg);
5744 emit_insn (GEN_MOV (rr, ra));
5745 /* Tell flow the register for return isn't dead. */
5746 emit_insn (gen_rtx_USE (VOIDmode, rr));
5753 save_schedule schedule;
5756 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
5757 offset = entry[1].offset;
5758 for (; entry->mode != VOIDmode; entry--)
5759 if (entry->reg == pr_reg)
5762 /* We can't find pr register. */
5766 offset = entry->offset - offset;
5767 pr_offset = (rounded_frame_size (d) + offset
5768 + SHMEDIA_REGS_STACK_ADJUST ());
5771 pr_offset = rounded_frame_size (d);
5773 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
5774 emit_insn (GEN_ADD3 (tmp, tmp, frame_pointer_rtx));
5776 tmp = gen_rtx_MEM (Pmode, tmp);
5777 emit_insn (GEN_MOV (tmp, ra));
5780 /* Clear variables at function end. */
5783 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
5784 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5786 trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
5787 sh_need_epilogue_known = 0;
5788 sp_switch = NULL_RTX;
5792 sh_builtin_saveregs (void)
5794 /* First unnamed integer register. */
5795 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
5796 /* Number of integer registers we need to save. */
5797 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
5798 /* First unnamed SFmode float reg */
5799 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5800 /* Number of SFmode float regs to save. */
5801 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5804 HOST_WIDE_INT alias_set;
5810 int pushregs = n_intregs;
5812 while (pushregs < NPARM_REGS (SImode) - 1
5813 && (CALL_COOKIE_INT_REG_GET
5814 (current_function_args_info.call_cookie,
5815 NPARM_REGS (SImode) - pushregs)
5818 current_function_args_info.call_cookie
5819 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
5824 if (pushregs == NPARM_REGS (SImode))
5825 current_function_args_info.call_cookie
5826 |= (CALL_COOKIE_INT_REG (0, 1)
5827 | CALL_COOKIE_STACKSEQ (pushregs - 1));
5829 current_function_args_info.call_cookie
5830 |= CALL_COOKIE_STACKSEQ (pushregs);
5832 current_function_pretend_args_size += 8 * n_intregs;
5834 if (TARGET_SHCOMPACT)
5838 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
5840 error ("__builtin_saveregs not supported by this subtarget");
5847 /* Allocate block of memory for the regs. */
5848 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5849 Or can assign_stack_local accept a 0 SIZE argument? */
5850 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
5853 regbuf = gen_rtx_MEM (BLKmode,
5854 gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
5855 else if (n_floatregs & 1)
5859 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
5860 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
5861 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
5862 regbuf = change_address (regbuf, BLKmode, addr);
5865 regbuf = assign_stack_local (BLKmode, bufsize, 0);
5866 alias_set = get_varargs_alias_set ();
5867 set_mem_alias_set (regbuf, alias_set);
5870 This is optimized to only save the regs that are necessary. Explicitly
5871 named args need not be saved. */
5873 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
5874 adjust_address (regbuf, BLKmode,
5875 n_floatregs * UNITS_PER_WORD),
5879 /* Return the address of the regbuf. */
5880 return XEXP (regbuf, 0);
5883 This is optimized to only save the regs that are necessary. Explicitly
5884 named args need not be saved.
5885 We explicitly build a pointer to the buffer because it halves the insn
5886 count when not optimizing (otherwise the pointer is built for each reg
5888 We emit the moves in reverse order so that we can use predecrement. */
5890 fpregs = gen_reg_rtx (Pmode);
5891 emit_move_insn (fpregs, XEXP (regbuf, 0));
5892 emit_insn (gen_addsi3 (fpregs, fpregs,
5893 GEN_INT (n_floatregs * UNITS_PER_WORD)));
5897 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
5899 emit_insn (gen_addsi3 (fpregs, fpregs,
5900 GEN_INT (-2 * UNITS_PER_WORD)));
5901 mem = gen_rtx_MEM (DFmode, fpregs);
5902 set_mem_alias_set (mem, alias_set);
5903 emit_move_insn (mem,
5904 gen_rtx (REG, DFmode, BASE_ARG_REG (DFmode) + regno));
5906 regno = first_floatreg;
5909 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5910 mem = gen_rtx_MEM (SFmode, fpregs);
5911 set_mem_alias_set (mem, alias_set);
5912 emit_move_insn (mem,
5913 gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno
5914 - (TARGET_LITTLE_ENDIAN != 0)));
5918 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
5922 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5923 mem = gen_rtx_MEM (SFmode, fpregs);
5924 set_mem_alias_set (mem, alias_set);
5925 emit_move_insn (mem,
5926 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
5929 /* Return the address of the regbuf. */
5930 return XEXP (regbuf, 0);
5933 /* Define the `__builtin_va_list' type for the ABI. */
5936 sh_build_builtin_va_list (void)
5938 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5941 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
5942 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
5943 return ptr_type_node;
5945 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5947 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
5949 f_next_o_limit = build_decl (FIELD_DECL,
5950 get_identifier ("__va_next_o_limit"),
5952 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
5954 f_next_fp_limit = build_decl (FIELD_DECL,
5955 get_identifier ("__va_next_fp_limit"),
5957 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
5960 DECL_FIELD_CONTEXT (f_next_o) = record;
5961 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
5962 DECL_FIELD_CONTEXT (f_next_fp) = record;
5963 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
5964 DECL_FIELD_CONTEXT (f_next_stack) = record;
5966 TYPE_FIELDS (record) = f_next_o;
5967 TREE_CHAIN (f_next_o) = f_next_o_limit;
5968 TREE_CHAIN (f_next_o_limit) = f_next_fp;
5969 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
5970 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
5972 layout_type (record);
5977 /* Implement `va_start' for varargs and stdarg. */
5980 sh_va_start (tree valist, rtx nextarg)
5982 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5983 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
5989 expand_builtin_saveregs ();
5990 std_expand_builtin_va_start (valist, nextarg);
5994 if ((! TARGET_SH2E && ! TARGET_SH4)
5995 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
5997 std_expand_builtin_va_start (valist, nextarg);
6001 f_next_o = TYPE_FIELDS (va_list_type_node);
6002 f_next_o_limit = TREE_CHAIN (f_next_o);
6003 f_next_fp = TREE_CHAIN (f_next_o_limit);
6004 f_next_fp_limit = TREE_CHAIN (f_next_fp);
6005 f_next_stack = TREE_CHAIN (f_next_fp_limit);
6007 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
6008 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
6009 valist, f_next_o_limit);
6010 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp);
6011 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
6012 valist, f_next_fp_limit);
6013 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
6014 valist, f_next_stack);
6016 /* Call __builtin_saveregs. */
6017 u = make_tree (ptr_type_node, expand_builtin_saveregs ());
6018 t = build (MODIFY_EXPR, ptr_type_node, next_fp, u);
6019 TREE_SIDE_EFFECTS (t) = 1;
6020 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6022 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
6027 u = fold (build (PLUS_EXPR, ptr_type_node, u,
6028 build_int_2 (UNITS_PER_WORD * nfp, 0)));
6029 t = build (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
6030 TREE_SIDE_EFFECTS (t) = 1;
6031 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6033 t = build (MODIFY_EXPR, ptr_type_node, next_o, u);
6034 TREE_SIDE_EFFECTS (t) = 1;
6035 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6037 nint = current_function_args_info.arg_count[SH_ARG_INT];
6042 u = fold (build (PLUS_EXPR, ptr_type_node, u,
6043 build_int_2 (UNITS_PER_WORD * nint, 0)));
6044 t = build (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
6045 TREE_SIDE_EFFECTS (t) = 1;
6046 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6048 u = make_tree (ptr_type_node, nextarg);
6049 t = build (MODIFY_EXPR, ptr_type_node, next_stack, u);
6050 TREE_SIDE_EFFECTS (t) = 1;
6051 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6054 /* Implement `va_arg'. */
6057 sh_va_arg (tree valist, tree type)
6059 HOST_WIDE_INT size, rsize;
6060 tree tmp, pptr_type_node;
6062 rtx result_ptr, result = NULL_RTX;
6063 int pass_by_ref = MUST_PASS_IN_STACK (TYPE_MODE (type), type);
6066 size = int_size_in_bytes (type);
6067 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6068 pptr_type_node = build_pointer_type (ptr_type_node);
6071 type = build_pointer_type (type);
6073 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
6074 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
6076 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
6077 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
6081 f_next_o = TYPE_FIELDS (va_list_type_node);
6082 f_next_o_limit = TREE_CHAIN (f_next_o);
6083 f_next_fp = TREE_CHAIN (f_next_o_limit);
6084 f_next_fp_limit = TREE_CHAIN (f_next_fp);
6085 f_next_stack = TREE_CHAIN (f_next_fp_limit);
6087 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
6088 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
6089 valist, f_next_o_limit);
6090 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp),
6092 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
6093 valist, f_next_fp_limit);
6094 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
6095 valist, f_next_stack);
6097 /* Structures with a single member with a distinct mode are passed
6098 like their member. This is relevant if the latter has a REAL_TYPE
6099 or COMPLEX_TYPE type. */
6100 if (TREE_CODE (type) == RECORD_TYPE
6101 && TYPE_FIELDS (type)
6102 && TREE_CODE (TYPE_FIELDS (type)) == FIELD_DECL
6103 && (TREE_CODE (TREE_TYPE (TYPE_FIELDS (type))) == REAL_TYPE
6104 || TREE_CODE (TREE_TYPE (TYPE_FIELDS (type))) == COMPLEX_TYPE)
6105 && TREE_CHAIN (TYPE_FIELDS (type)) == NULL_TREE)
6106 type = TREE_TYPE (TYPE_FIELDS (type));
6109 pass_as_float = ((TREE_CODE (type) == REAL_TYPE && size <= 8)
6110 || (TREE_CODE (type) == COMPLEX_TYPE
6111 && TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
6116 pass_as_float = (TREE_CODE (type) == REAL_TYPE && size == 4);
6119 addr_rtx = gen_reg_rtx (Pmode);
6120 lab_false = gen_label_rtx ();
6121 lab_over = gen_label_rtx ();
6123 tmp = make_tree (pptr_type_node, addr_rtx);
6124 valist = build1 (INDIRECT_REF, ptr_type_node, tmp);
6129 = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
6130 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
6132 emit_cmp_and_jump_insns (expand_expr (next_fp, NULL_RTX, Pmode,
6134 expand_expr (next_fp_limit, NULL_RTX,
6135 Pmode, EXPAND_NORMAL),
6136 GE, const1_rtx, Pmode, 1, lab_false);
6138 if (TYPE_ALIGN (type) > BITS_PER_WORD
6139 || (((TREE_CODE (type) == REAL_TYPE && size == 8) || size == 16)
6140 && (n_floatregs & 1)))
6142 tmp = build (BIT_AND_EXPR, ptr_type_node, next_fp,
6143 build_int_2 (UNITS_PER_WORD, 0));
6144 tmp = build (PLUS_EXPR, ptr_type_node, next_fp, tmp);
6145 tmp = build (MODIFY_EXPR, ptr_type_node, next_fp, tmp);
6146 TREE_SIDE_EFFECTS (tmp) = 1;
6147 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
6150 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
6151 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6153 emit_move_insn (addr_rtx, r);
6155 #ifdef FUNCTION_ARG_SCmode_WART
6156 if (TYPE_MODE (type) == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
6158 rtx addr, real, imag, result_value, slot;
6159 tree subtype = TREE_TYPE (type);
6161 addr = std_expand_builtin_va_arg (valist, subtype);
6162 #ifdef POINTERS_EXTEND_UNSIGNED
6163 if (GET_MODE (addr) != Pmode)
6164 addr = convert_memory_address (Pmode, addr);
6166 imag = gen_rtx_MEM (TYPE_MODE (type), addr);
6167 set_mem_alias_set (imag, get_varargs_alias_set ());
6169 addr = std_expand_builtin_va_arg (valist, subtype);
6170 #ifdef POINTERS_EXTEND_UNSIGNED
6171 if (GET_MODE (addr) != Pmode)
6172 addr = convert_memory_address (Pmode, addr);
6174 real = gen_rtx_MEM (TYPE_MODE (type), addr);
6175 set_mem_alias_set (real, get_varargs_alias_set ());
6177 result_value = gen_rtx_CONCAT (SCmode, real, imag);
6178 /* ??? this interface is stupid - why require a pointer? */
6179 result = gen_reg_rtx (Pmode);
6180 slot = assign_stack_temp (SCmode, 8, 0);
6181 emit_move_insn (slot, result_value);
6182 emit_move_insn (result, XEXP (slot, 0));
6184 #endif /* FUNCTION_ARG_SCmode_WART */
6186 emit_jump_insn (gen_jump (lab_over));
6188 emit_label (lab_false);
6190 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
6191 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6193 emit_move_insn (addr_rtx, r);
6197 tmp = build (PLUS_EXPR, ptr_type_node, next_o,
6198 build_int_2 (rsize, 0));
6200 emit_cmp_and_jump_insns (expand_expr (tmp, NULL_RTX, Pmode,
6202 expand_expr (next_o_limit, NULL_RTX,
6203 Pmode, EXPAND_NORMAL),
6204 GT, const1_rtx, Pmode, 1, lab_false);
6206 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
6207 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6209 emit_move_insn (addr_rtx, r);
6211 emit_jump_insn (gen_jump (lab_over));
6213 emit_label (lab_false);
6215 if (size > 4 && ! TARGET_SH4)
6217 tmp = build (MODIFY_EXPR, ptr_type_node, next_o, next_o_limit);
6218 TREE_SIDE_EFFECTS (tmp) = 1;
6219 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
6222 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
6223 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6225 emit_move_insn (addr_rtx, r);
6229 emit_label (lab_over);
6232 /* ??? In va-sh.h, there had been code to make values larger than
6233 size 8 indirect. This does not match the FUNCTION_ARG macros. */
6235 result_ptr = std_expand_builtin_va_arg (valist, type);
6238 emit_move_insn (result, result_ptr);
6239 emit_label (lab_over);
6242 result = result_ptr;
6246 #ifdef POINTERS_EXTEND_UNSIGNED
6247 if (GET_MODE (addr) != Pmode)
6248 addr = convert_memory_address (Pmode, result);
6250 result = gen_rtx_MEM (ptr_mode, force_reg (Pmode, result));
6251 set_mem_alias_set (result, get_varargs_alias_set ());
6253 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
6254 argument to the varargs alias set. */
6259 sh_promote_prototypes (tree type)
6265 return ! sh_attr_renesas_p (type);
6268 /* Define where to put the arguments to a function.
6269 Value is zero to push the argument on the stack,
6270 or a hard register in which to store the argument.
6272 MODE is the argument's machine mode.
6273 TYPE is the data type of the argument (as a tree).
6274 This is null for libcalls where that information may
6276 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6277 the preceding args and about the function being called.
6278 NAMED is nonzero if this argument is a named parameter
6279 (otherwise it is an extra parameter matching an ellipsis).
6281 On SH the first args are normally in registers
6282 and the rest are pushed. Any arg that starts within the first
6283 NPARM_REGS words is at least partially passed in a register unless
6284 its data type forbids. */
6288 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
6289 tree type, int named)
6291 if (! TARGET_SH5 && mode == VOIDmode)
6292 return GEN_INT (ca->renesas_abi ? 1 : 0);
6295 && PASS_IN_REG_P (*ca, mode, type)
6296 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
6300 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
6301 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
6303 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
6304 gen_rtx_REG (SFmode,
6306 + (ROUND_REG (*ca, mode) ^ 1)),
6308 rtx r2 = gen_rtx_EXPR_LIST(VOIDmode,
6309 gen_rtx_REG (SFmode,
6311 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
6313 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
6316 /* If the alignment of a DF value causes an SF register to be
6317 skipped, we will use that skipped register for the next SF
6319 if ((TARGET_HITACHI || ca->renesas_abi)
6320 && ca->free_single_fp_reg
6322 return gen_rtx_REG (mode, ca->free_single_fp_reg);
6324 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
6325 ^ (mode == SFmode && TARGET_SH4
6326 && TARGET_LITTLE_ENDIAN != 0
6327 && ! TARGET_HITACHI && ! ca->renesas_abi);
6328 return gen_rtx_REG (mode, regno);
6334 if (mode == VOIDmode && TARGET_SHCOMPACT)
6335 return GEN_INT (ca->call_cookie);
6337 /* The following test assumes unnamed arguments are promoted to
6339 if (mode == SFmode && ca->free_single_fp_reg)
6340 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
6342 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
6343 && (named || ! ca->prototype_p)
6344 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
6346 if (! ca->prototype_p && TARGET_SHMEDIA)
6347 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
6349 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
6351 + ca->arg_count[(int) SH_ARG_FLOAT]);
6354 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
6355 && (! TARGET_SHCOMPACT
6356 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
6357 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
6360 return gen_rtx_REG (mode, (FIRST_PARM_REG
6361 + ca->arg_count[(int) SH_ARG_INT]));
6370 /* Update the data in CUM to advance over an argument
6371 of mode MODE and data type TYPE.
6372 (TYPE is null for libcalls where that information may not be
6376 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
6377 tree type, int named)
6381 else if (TARGET_SH5)
6383 tree type2 = (ca->byref && type
6386 enum machine_mode mode2 = (ca->byref && type
6389 int dwords = ((ca->byref
6392 ? int_size_in_bytes (type2)
6393 : GET_MODE_SIZE (mode2)) + 7) / 8;
6394 int numregs = MIN (dwords, NPARM_REGS (SImode)
6395 - ca->arg_count[(int) SH_ARG_INT]);
6399 ca->arg_count[(int) SH_ARG_INT] += numregs;
6400 if (TARGET_SHCOMPACT
6401 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
6404 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
6406 /* N.B. We want this also for outgoing. */
6407 ca->stack_regs += numregs;
6412 ca->stack_regs += numregs;
6413 ca->byref_regs += numregs;
6417 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
6421 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
6424 else if (dwords > numregs)
6426 int pushregs = numregs;
6428 if (TARGET_SHCOMPACT)
6429 ca->stack_regs += numregs;
6430 while (pushregs < NPARM_REGS (SImode) - 1
6431 && (CALL_COOKIE_INT_REG_GET
6433 NPARM_REGS (SImode) - pushregs)
6437 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
6441 if (numregs == NPARM_REGS (SImode))
6443 |= CALL_COOKIE_INT_REG (0, 1)
6444 | CALL_COOKIE_STACKSEQ (numregs - 1);
6447 |= CALL_COOKIE_STACKSEQ (numregs);
6450 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
6451 && (named || ! ca->prototype_p))
6453 if (mode2 == SFmode && ca->free_single_fp_reg)
6454 ca->free_single_fp_reg = 0;
6455 else if (ca->arg_count[(int) SH_ARG_FLOAT]
6456 < NPARM_REGS (SFmode))
6459 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
6461 - ca->arg_count[(int) SH_ARG_FLOAT]);
6463 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
6465 if (TARGET_SHCOMPACT && ! ca->prototype_p)
6467 if (ca->outgoing && numregs > 0)
6471 |= (CALL_COOKIE_INT_REG
6472 (ca->arg_count[(int) SH_ARG_INT]
6473 - numregs + ((numfpregs - 2) / 2),
6474 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
6477 while (numfpregs -= 2);
6479 else if (mode2 == SFmode && (named)
6480 && (ca->arg_count[(int) SH_ARG_FLOAT]
6481 < NPARM_REGS (SFmode)))
6482 ca->free_single_fp_reg
6483 = FIRST_FP_PARM_REG - numfpregs
6484 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
6490 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
6492 /* Note that we've used the skipped register. */
6493 if (mode == SFmode && ca->free_single_fp_reg)
6495 ca->free_single_fp_reg = 0;
6498 /* When we have a DF after an SF, there's an SF register that get
6499 skipped in order to align the DF value. We note this skipped
6500 register, because the next SF value will use it, and not the
6501 SF that follows the DF. */
6503 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
6505 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
6506 + BASE_ARG_REG (mode));
6510 if (! (TARGET_SH4 || ca->renesas_abi)
6511 || PASS_IN_REG_P (*ca, mode, type))
6512 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
6513 = (ROUND_REG (*ca, mode)
6515 ? ROUND_ADVANCE (int_size_in_bytes (type))
6516 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
6519 /* If the structure value address is not passed in a register, define
6520 `STRUCT_VALUE' as an expression returning an RTX for the place
6521 where the address is passed. If it returns 0, the address is
6522 passed as an "invisible" first argument. */
6523 /* The Renesas calling convention doesn't quite fit into this scheme since
6524 the address is passed like an invisible argument, but one that is always
6525 passed in memory. */
6527 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
6529 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
6531 return gen_rtx_REG (Pmode, 2);
6535 sh_return_in_memory (tree type, tree fndecl)
6539 if (TYPE_MODE (type) == BLKmode)
6540 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
6542 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
6546 return (TYPE_MODE (type) == BLKmode
6547 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
6548 && TREE_CODE (type) == RECORD_TYPE));
6552 /* We actually emit the code in sh_expand_prologue. We used to use
6553 a static variable to flag that we need to emit this code, but that
6554 doesn't when inlining, when functions are deferred and then emitted
6555 later. Fortunately, we already have two flags that are part of struct
6556 function that tell if a function uses varargs or stdarg. */
6558 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
6559 enum machine_mode mode ATTRIBUTE_UNUSED,
6560 tree type ATTRIBUTE_UNUSED,
6561 int *pretend_arg_size ATTRIBUTE_UNUSED,
6562 int second_time ATTRIBUTE_UNUSED)
6564 if (! current_function_stdarg)
6569 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
6575 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
6577 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
6581 /* Define the offset between two registers, one to be eliminated, and
6582 the other its replacement, at the start of a routine. */
6585 initial_elimination_offset (int from, int to)
6588 int regs_saved_rounding = 0;
6589 int total_saved_regs_space;
6590 int total_auto_space;
6591 int save_flags = target_flags;
6593 HARD_REG_SET live_regs_mask;
6595 shmedia_space_reserved_for_target_registers = false;
6596 regs_saved = calc_live_regs (&live_regs_mask);
6597 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
6599 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
6601 shmedia_space_reserved_for_target_registers = true;
6602 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
6605 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
6606 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6607 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
6609 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
6610 copy_flags = target_flags;
6611 target_flags = save_flags;
6613 total_saved_regs_space = regs_saved + regs_saved_rounding;
6615 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
6616 return total_saved_regs_space + total_auto_space
6617 + current_function_args_info.byref_regs * 8;
6619 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
6620 return total_saved_regs_space + total_auto_space
6621 + current_function_args_info.byref_regs * 8;
6623 /* Initial gap between fp and sp is 0. */
6624 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
6627 if (from == RETURN_ADDRESS_POINTER_REGNUM
6628 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
6632 int n = total_saved_regs_space;
6633 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
6634 save_schedule schedule;
6637 n += total_auto_space;
6639 /* If it wasn't saved, there's not much we can do. */
6640 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
6643 target_flags = copy_flags;
6645 sh5_schedule_saves (&live_regs_mask, &schedule, n);
6646 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6647 if (entry->reg == pr_reg)
6649 target_flags = save_flags;
6650 return entry->offset;
6655 return total_auto_space;
6661 /* Handle machine specific pragmas to be semi-compatible with Renesas
6665 sh_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
6667 pragma_interrupt = 1;
6671 sh_pr_trapa (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
6673 pragma_interrupt = pragma_trapa = 1;
6677 sh_pr_nosave_low_regs (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
6679 pragma_nosave_low_regs = 1;
6682 /* Generate 'handle_interrupt' attribute for decls */
6685 sh_insert_attributes (tree node, tree *attributes)
6687 if (! pragma_interrupt
6688 || TREE_CODE (node) != FUNCTION_DECL)
6691 /* We are only interested in fields. */
6692 if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd')
6695 /* Add a 'handle_interrupt' attribute. */
6696 * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes);
6701 /* Supported attributes:
6703 interrupt_handler -- specifies this function is an interrupt handler.
6705 sp_switch -- specifies an alternate stack for an interrupt handler
6708 trap_exit -- use a trapa to exit an interrupt function instead of
6711 renesas -- use Renesas calling/layout conventions (functions and
6716 const struct attribute_spec sh_attribute_table[] =
6718 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6719 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
6720 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
6721 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
6722 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
6723 { NULL, 0, 0, false, false, false, NULL }
6726 /* Handle an "interrupt_handler" attribute; arguments as in
6727 struct attribute_spec.handler. */
6729 sh_handle_interrupt_handler_attribute (tree *node, tree name,
6730 tree args ATTRIBUTE_UNUSED,
6731 int flags ATTRIBUTE_UNUSED,
6734 if (TREE_CODE (*node) != FUNCTION_DECL)
6736 warning ("`%s' attribute only applies to functions",
6737 IDENTIFIER_POINTER (name));
6738 *no_add_attrs = true;
6740 else if (TARGET_SHCOMPACT)
6742 error ("attribute interrupt_handler is not compatible with -m5-compact");
6743 *no_add_attrs = true;
6749 /* Handle an "sp_switch" attribute; arguments as in
6750 struct attribute_spec.handler. */
6752 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
6753 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
6755 if (TREE_CODE (*node) != FUNCTION_DECL)
6757 warning ("`%s' attribute only applies to functions",
6758 IDENTIFIER_POINTER (name));
6759 *no_add_attrs = true;
6761 else if (!pragma_interrupt)
6763 /* The sp_switch attribute only has meaning for interrupt functions. */
6764 warning ("`%s' attribute only applies to interrupt functions",
6765 IDENTIFIER_POINTER (name));
6766 *no_add_attrs = true;
6768 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
6770 /* The argument must be a constant string. */
6771 warning ("`%s' attribute argument not a string constant",
6772 IDENTIFIER_POINTER (name));
6773 *no_add_attrs = true;
6777 sp_switch = gen_rtx_SYMBOL_REF (VOIDmode,
6778 TREE_STRING_POINTER (TREE_VALUE (args)));
6784 /* Handle an "trap_exit" attribute; arguments as in
6785 struct attribute_spec.handler. */
6787 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
6788 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
6790 if (TREE_CODE (*node) != FUNCTION_DECL)
6792 warning ("`%s' attribute only applies to functions",
6793 IDENTIFIER_POINTER (name));
6794 *no_add_attrs = true;
6796 else if (!pragma_interrupt)
6798 /* The trap_exit attribute only has meaning for interrupt functions. */
6799 warning ("`%s' attribute only applies to interrupt functions",
6800 IDENTIFIER_POINTER (name));
6801 *no_add_attrs = true;
6803 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
6805 /* The argument must be a constant integer. */
6806 warning ("`%s' attribute argument not an integer constant",
6807 IDENTIFIER_POINTER (name));
6808 *no_add_attrs = true;
6812 trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
6819 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
6820 tree name ATTRIBUTE_UNUSED,
6821 tree args ATTRIBUTE_UNUSED,
6822 int flags ATTRIBUTE_UNUSED,
6823 bool *no_add_attrs ATTRIBUTE_UNUSED)
6828 /* True if __attribute__((renesas)) or -mrenesas. */
6830 sh_attr_renesas_p (tree td)
6837 td = TREE_TYPE (td);
6838 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
6842 /* True if __attribute__((renesas)) or -mrenesas, for the current
6845 sh_cfun_attr_renesas_p (void)
6847 return sh_attr_renesas_p (current_function_decl);
6851 sh_cfun_interrupt_handler_p (void)
6853 return (lookup_attribute ("interrupt_handler",
6854 DECL_ATTRIBUTES (current_function_decl))
6858 /* ??? target_switches in toplev.c is static, hence we have to duplicate it. */
6861 const char *const name;
6863 const char *const description;
6865 sh_target_switches[] = TARGET_SWITCHES;
6866 #define target_switches sh_target_switches
6868 /* Like default_pch_valid_p, but take flag_mask into account. */
6870 sh_pch_valid_p (const void *data_p, size_t len)
6872 const char *data = (const char *)data_p;
6873 const char *flag_that_differs = NULL;
6877 = (SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT
6878 | SH4_BIT | HITACHI_BIT | LITTLE_ENDIAN_BIT);
6880 /* -fpic and -fpie also usually make a PCH invalid. */
6881 if (data[0] != flag_pic)
6882 return _("created and used with different settings of -fpic");
6883 if (data[1] != flag_pie)
6884 return _("created and used with different settings of -fpie");
6887 /* Check target_flags. */
6888 memcpy (&old_flags, data, sizeof (target_flags));
6889 if (((old_flags ^ target_flags) & flag_mask) != 0)
6891 for (i = 0; i < ARRAY_SIZE (target_switches); i++)
6895 bits = target_switches[i].value;
6899 if ((target_flags & bits) != (old_flags & bits))
6901 flag_that_differs = target_switches[i].name;
6907 data += sizeof (target_flags);
6908 len -= sizeof (target_flags);
6910 /* Check string options. */
6911 #ifdef TARGET_OPTIONS
6912 for (i = 0; i < ARRAY_SIZE (target_options); i++)
6914 const char *str = *target_options[i].variable;
6918 l = strlen (str) + 1;
6919 if (len < l || memcmp (data, str, l) != 0)
6921 flag_that_differs = target_options[i].prefix;
6934 asprintf (&r, _("created and used with differing settings of `-m%s'"),
6937 return _("out of memory");
6942 /* Predicates used by the templates. */
6944 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
6945 Used only in general_movsrc_operand. */
6948 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
6960 /* Returns 1 if OP can be source of a simple move operation.
6961 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
6962 invalid as are subregs of system registers. */
6965 general_movsrc_operand (rtx op, enum machine_mode mode)
6967 if (GET_CODE (op) == MEM)
6969 rtx inside = XEXP (op, 0);
6970 if (GET_CODE (inside) == CONST)
6971 inside = XEXP (inside, 0);
6973 if (GET_CODE (inside) == LABEL_REF)
6976 if (GET_CODE (inside) == PLUS
6977 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
6978 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
6981 /* Only post inc allowed. */
6982 if (GET_CODE (inside) == PRE_DEC)
6986 if ((mode == QImode || mode == HImode)
6987 && (GET_CODE (op) == SUBREG
6988 && GET_CODE (XEXP (op, 0)) == REG
6989 && system_reg_operand (XEXP (op, 0), mode)))
6992 return general_operand (op, mode);
6995 /* Returns 1 if OP can be a destination of a move.
6996 Same as general_operand, but no preinc allowed. */
6999 general_movdst_operand (rtx op, enum machine_mode mode)
7001 /* Only pre dec allowed. */
7002 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
7005 return general_operand (op, mode);
7008 /* Returns 1 if OP is a normal arithmetic register. */
7011 arith_reg_operand (rtx op, enum machine_mode mode)
7013 if (register_operand (op, mode))
7017 if (GET_CODE (op) == REG)
7019 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
7020 regno = REGNO (SUBREG_REG (op));
7024 return (regno != T_REG && regno != PR_REG
7025 && ! TARGET_REGISTER_P (regno)
7026 && (regno != FPUL_REG || TARGET_SH4)
7027 && regno != MACH_REG && regno != MACL_REG);
7032 /* Like above, but for DImode destinations: forbid paradoxical DImode subregs,
7033 because this would lead to missing sign extensions when truncating from
7034 DImode to SImode. */
7036 arith_reg_dest (rtx op, enum machine_mode mode)
7038 if (mode == DImode && GET_CODE (op) == SUBREG
7039 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
7041 return arith_reg_operand (op, mode);
7045 int_gpr_dest (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7047 enum machine_mode op_mode = GET_MODE (op);
7049 if (GET_MODE_CLASS (op_mode) != MODE_INT
7050 || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
7052 if (! reload_completed)
7054 return true_regnum (op) <= LAST_GENERAL_REG;
7058 fp_arith_reg_operand (rtx op, enum machine_mode mode)
7060 if (register_operand (op, mode))
7064 if (GET_CODE (op) == REG)
7066 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
7067 regno = REGNO (SUBREG_REG (op));
7071 return (regno >= FIRST_PSEUDO_REGISTER
7072 || FP_REGISTER_P (regno));
7077 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
7080 arith_operand (rtx op, enum machine_mode mode)
7082 if (arith_reg_operand (op, mode))
7087 /* FIXME: We should be checking whether the CONST_INT fits in a
7088 CONST_OK_FOR_I16 here, but this causes reload_cse to crash when
7089 attempting to transform a sequence of two 64-bit sets of the
7090 same register from literal constants into a set and an add,
7091 when the difference is too wide for an add. */
7092 if (GET_CODE (op) == CONST_INT
7093 || EXTRA_CONSTRAINT_C16 (op))
7098 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (op)))
7104 /* Returns 1 if OP is a valid source operand for a compare insn. */
7107 arith_reg_or_0_operand (rtx op, enum machine_mode mode)
7109 if (arith_reg_operand (op, mode))
7112 if (EXTRA_CONSTRAINT_Z (op))
7118 /* Return 1 if OP is a valid source operand for an SHmedia operation
7119 that takes either a register or a 6-bit immediate. */
7122 shmedia_6bit_operand (rtx op, enum machine_mode mode)
7124 return (arith_reg_operand (op, mode)
7125 || (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I06 (INTVAL (op))));
7128 /* Returns 1 if OP is a valid source operand for a logical operation. */
7131 logical_operand (rtx op, enum machine_mode mode)
7133 if (arith_reg_operand (op, mode))
7138 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I10 (INTVAL (op)))
7143 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K08 (INTVAL (op)))
7150 and_operand (rtx op, enum machine_mode mode)
7152 if (logical_operand (op, mode))
7155 /* Check mshflo.l / mshflhi.l opportunities. */
7158 && GET_CODE (op) == CONST_INT
7159 && CONST_OK_FOR_J16 (INTVAL (op)))
7165 /* Nonzero if OP is a floating point value with value 0.0. */
7168 fp_zero_operand (rtx op)
7172 if (GET_MODE (op) != SFmode)
7175 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
7176 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
7179 /* Nonzero if OP is a floating point value with value 1.0. */
7182 fp_one_operand (rtx op)
7186 if (GET_MODE (op) != SFmode)
7189 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
7190 return REAL_VALUES_EQUAL (r, dconst1);
7193 /* For -m4 and -m4-single-only, mode switching is used. If we are
7194 compiling without -mfmovd, movsf_ie isn't taken into account for
7195 mode switching. We could check in machine_dependent_reorg for
7196 cases where we know we are in single precision mode, but there is
7197 interface to find that out during reload, so we must avoid
7198 choosing an fldi alternative during reload and thus failing to
7199 allocate a scratch register for the constant loading. */
7203 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
7207 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7209 enum rtx_code code = GET_CODE (op);
7210 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
7214 fpscr_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7216 return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG
7217 && GET_MODE (op) == PSImode);
7221 fpul_operand (rtx op, enum machine_mode mode)
7224 return fp_arith_reg_operand (op, mode);
7226 return (GET_CODE (op) == REG
7227 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
7228 && GET_MODE (op) == mode);
7232 symbol_ref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7234 return (GET_CODE (op) == SYMBOL_REF);
7237 /* Return the TLS type for TLS symbols, 0 for otherwise. */
7239 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7241 if (GET_CODE (op) != SYMBOL_REF)
7243 return SYMBOL_REF_TLS_MODEL (op);
7247 commutative_float_operator (rtx op, enum machine_mode mode)
7249 if (GET_MODE (op) != mode)
7251 switch (GET_CODE (op))
7263 noncommutative_float_operator (rtx op, enum machine_mode mode)
7265 if (GET_MODE (op) != mode)
7267 switch (GET_CODE (op))
7279 unary_float_operator (rtx op, enum machine_mode mode)
7281 if (GET_MODE (op) != mode)
7283 switch (GET_CODE (op))
7296 binary_float_operator (rtx op, enum machine_mode mode)
7298 if (GET_MODE (op) != mode)
7300 switch (GET_CODE (op))
7314 binary_logical_operator (rtx op, enum machine_mode mode)
7316 if (GET_MODE (op) != mode)
7318 switch (GET_CODE (op))
7331 equality_comparison_operator (rtx op, enum machine_mode mode)
7333 return ((mode == VOIDmode || GET_MODE (op) == mode)
7334 && (GET_CODE (op) == EQ || GET_CODE (op) == NE));
7337 int greater_comparison_operator (rtx op, enum machine_mode mode)
7339 if (mode != VOIDmode && GET_MODE (op) == mode)
7341 switch (GET_CODE (op))
7353 int less_comparison_operator (rtx op, enum machine_mode mode)
7355 if (mode != VOIDmode && GET_MODE (op) == mode)
7357 switch (GET_CODE (op))
7369 /* Accept pseudos and branch target registers. */
7371 target_reg_operand (rtx op, enum machine_mode mode)
7374 || GET_MODE (op) != DImode)
7377 if (GET_CODE (op) == SUBREG)
7380 if (GET_CODE (op) != REG)
7383 /* We must protect ourselves from matching pseudos that are virtual
7384 register, because they will eventually be replaced with hardware
7385 registers that aren't branch-target registers. */
7386 if (REGNO (op) > LAST_VIRTUAL_REGISTER
7387 || TARGET_REGISTER_P (REGNO (op)))
7393 /* Same as target_reg_operand, except that label_refs and symbol_refs
7394 are accepted before reload. */
7396 target_operand (rtx op, enum machine_mode mode)
7401 if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode)
7402 && EXTRA_CONSTRAINT_Csy (op))
7403 return ! reload_completed;
7405 return target_reg_operand (op, mode);
7409 mextr_bit_offset (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7413 if (GET_CODE (op) != CONST_INT)
7416 return i >= 1*8 && i <= 7*8 && (i & 7) == 0;
7420 extend_reg_operand (rtx op, enum machine_mode mode)
7422 return (GET_CODE (op) == TRUNCATE
7424 : arith_reg_operand) (op, mode);
7428 trunc_hi_operand (rtx op, enum machine_mode mode)
7430 enum machine_mode op_mode = GET_MODE (op);
7432 if (op_mode != SImode && op_mode != DImode
7433 && op_mode != V4HImode && op_mode != V2SImode)
7435 return extend_reg_operand (op, mode);
7439 extend_reg_or_0_operand (rtx op, enum machine_mode mode)
7441 return (GET_CODE (op) == TRUNCATE
7443 : arith_reg_or_0_operand) (op, mode);
7447 general_extend_operand (rtx op, enum machine_mode mode)
7449 return (GET_CODE (op) == TRUNCATE
7451 : nonimmediate_operand) (op, mode);
7455 inqhi_operand (rtx op, enum machine_mode mode)
7457 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
7460 /* Can't use true_regnum here because copy_cost wants to know about
7461 SECONDARY_INPUT_RELOAD_CLASS. */
7462 return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
7466 sh_rep_vec (rtx v, enum machine_mode mode)
7471 if ((GET_CODE (v) != CONST_VECTOR && GET_CODE (v) != PARALLEL)
7472 || (GET_MODE (v) != mode && mode != VOIDmode))
7474 i = XVECLEN (v, 0) - 2;
7475 x = XVECEXP (v, 0, i + 1);
7476 if (GET_MODE_UNIT_SIZE (mode) == 1)
7478 y = XVECEXP (v, 0, i);
7479 for (i -= 2 ; i >= 0; i -= 2)
7480 if (! rtx_equal_p (XVECEXP (v, 0, i + 1), x)
7481 || ! rtx_equal_p (XVECEXP (v, 0, i), y))
7486 if (XVECEXP (v, 0, i) != x)
7491 /* Determine if V is a constant vector matching MODE with only one element
7492 that is not a sign extension. Two byte-sized elements count as one. */
7494 sh_1el_vec (rtx v, enum machine_mode mode)
7497 int i, last, least, sign_ix;
7500 if (GET_CODE (v) != CONST_VECTOR
7501 || (GET_MODE (v) != mode && mode != VOIDmode))
7503 /* Determine numbers of last and of least significant elements. */
7504 last = XVECLEN (v, 0) - 1;
7505 least = TARGET_LITTLE_ENDIAN ? 0 : last;
7506 if (GET_CODE (XVECEXP (v, 0, least)) != CONST_INT)
7509 if (GET_MODE_UNIT_SIZE (mode) == 1)
7510 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
7511 if (GET_CODE (XVECEXP (v, 0, sign_ix)) != CONST_INT)
7513 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (v));
7514 sign = (INTVAL (XVECEXP (v, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
7515 ? constm1_rtx : const0_rtx);
7516 i = XVECLEN (v, 0) - 1;
7518 if (i != least && i != sign_ix && XVECEXP (v, 0, i) != sign)
7525 sh_const_vec (rtx v, enum machine_mode mode)
7529 if (GET_CODE (v) != CONST_VECTOR
7530 || (GET_MODE (v) != mode && mode != VOIDmode))
7532 i = XVECLEN (v, 0) - 1;
7534 if (GET_CODE (XVECEXP (v, 0, i)) != CONST_INT)
7539 /* Return the destination address of a branch. */
7542 branch_dest (rtx branch)
7544 rtx dest = SET_SRC (PATTERN (branch));
7547 if (GET_CODE (dest) == IF_THEN_ELSE)
7548 dest = XEXP (dest, 1);
7549 dest = XEXP (dest, 0);
7550 dest_uid = INSN_UID (dest);
7551 return INSN_ADDRESSES (dest_uid);
7554 /* Return nonzero if REG is not used after INSN.
7555 We assume REG is a reload reg, and therefore does
7556 not live past labels. It may live past calls or jumps though. */
7558 reg_unused_after (rtx reg, rtx insn)
7563 /* If the reg is set by this instruction, then it is safe for our
7564 case. Disregard the case where this is a store to memory, since
7565 we are checking a register used in the store address. */
7566 set = single_set (insn);
7567 if (set && GET_CODE (SET_DEST (set)) != MEM
7568 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7571 while ((insn = NEXT_INSN (insn)))
7573 code = GET_CODE (insn);
7576 /* If this is a label that existed before reload, then the register
7577 if dead here. However, if this is a label added by reorg, then
7578 the register may still be live here. We can't tell the difference,
7579 so we just ignore labels completely. */
7580 if (code == CODE_LABEL)
7585 if (code == JUMP_INSN)
7588 /* If this is a sequence, we must handle them all at once.
7589 We could have for instance a call that sets the target register,
7590 and an insn in a delay slot that uses the register. In this case,
7591 we must return 0. */
7592 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
7597 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7599 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
7600 rtx set = single_set (this_insn);
7602 if (GET_CODE (this_insn) == CALL_INSN)
7604 else if (GET_CODE (this_insn) == JUMP_INSN)
7606 if (INSN_ANNULLED_BRANCH_P (this_insn))
7611 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
7613 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7615 if (GET_CODE (SET_DEST (set)) != MEM)
7621 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
7626 else if (code == JUMP_INSN)
7629 else if (GET_RTX_CLASS (code) == 'i')
7631 rtx set = single_set (insn);
7633 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
7635 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7636 return GET_CODE (SET_DEST (set)) != MEM;
7637 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
7641 if (code == CALL_INSN && call_used_regs[REGNO (reg)])
7649 static GTY(()) rtx fpscr_rtx;
7651 get_fpscr_rtx (void)
7655 fpscr_rtx = gen_rtx (REG, PSImode, FPSCR_REG);
7656 REG_USERVAR_P (fpscr_rtx) = 1;
7657 mark_user_reg (fpscr_rtx);
7659 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
7660 mark_user_reg (fpscr_rtx);
7665 emit_sf_insn (rtx pat)
7671 emit_df_insn (rtx pat)
7677 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
7679 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
7683 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
7685 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
7690 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
7692 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
7696 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
7698 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
7702 /* ??? gcc does flow analysis strictly after common subexpression
7703 elimination. As a result, common subexpression elimination fails
7704 when there are some intervening statements setting the same register.
7705 If we did nothing about this, this would hurt the precision switching
7706 for SH4 badly. There is some cse after reload, but it is unable to
7707 undo the extra register pressure from the unused instructions, and
7708 it cannot remove auto-increment loads.
7710 A C code example that shows this flow/cse weakness for (at least) SH
7711 and sparc (as of gcc ss-970706) is this:
7725 So we add another pass before common subexpression elimination, to
7726 remove assignments that are dead due to a following assignment in the
7727 same basic block. */
7730 mark_use (rtx x, rtx *reg_set_block)
7736 code = GET_CODE (x);
7741 int regno = REGNO (x);
7742 int nregs = (regno < FIRST_PSEUDO_REGISTER
7743 ? HARD_REGNO_NREGS (regno, GET_MODE (x))
7747 reg_set_block[regno + nregs - 1] = 0;
7754 rtx dest = SET_DEST (x);
7756 if (GET_CODE (dest) == SUBREG)
7757 dest = SUBREG_REG (dest);
7758 if (GET_CODE (dest) != REG)
7759 mark_use (dest, reg_set_block);
7760 mark_use (SET_SRC (x), reg_set_block);
7767 const char *fmt = GET_RTX_FORMAT (code);
7769 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7772 mark_use (XEXP (x, i), reg_set_block);
7773 else if (fmt[i] == 'E')
7774 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7775 mark_use (XVECEXP (x, i, j), reg_set_block);
7782 static rtx get_free_reg (HARD_REG_SET);
7784 /* This function returns a register to use to load the address to load
7785 the fpscr from. Currently it always returns r1 or r7, but when we are
7786 able to use pseudo registers after combine, or have a better mechanism
7787 for choosing a register, it should be done here. */
7788 /* REGS_LIVE is the liveness information for the point for which we
7789 need this allocation. In some bare-bones exit blocks, r1 is live at the
7790 start. We can even have all of r0..r3 being live:
7791 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
7792 INSN before which new insns are placed with will clobber the register
7793 we return. If a basic block consists only of setting the return value
7794 register to a pseudo and using that register, the return value is not
7795 live before or after this block, yet we we'll insert our insns right in
7799 get_free_reg (HARD_REG_SET regs_live)
7801 if (! TEST_HARD_REG_BIT (regs_live, 1))
7802 return gen_rtx_REG (Pmode, 1);
7804 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
7805 there shouldn't be anything but a jump before the function end. */
7806 if (! TEST_HARD_REG_BIT (regs_live, 7))
7807 return gen_rtx_REG (Pmode, 7);
7812 /* This function will set the fpscr from memory.
7813 MODE is the mode we are setting it to. */
7815 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
7817 enum attr_fp_mode fp_mode = mode;
7818 rtx addr_reg = get_free_reg (regs_live);
7820 if (fp_mode == (enum attr_fp_mode) ACTUAL_NORMAL_MODE (FP_MODE))
7821 emit_insn (gen_fpu_switch1 (addr_reg));
7823 emit_insn (gen_fpu_switch0 (addr_reg));
7826 /* Is the given character a logical line separator for the assembler? */
7827 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
7828 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
7832 sh_insn_length_adjustment (rtx insn)
7834 /* Instructions with unfilled delay slots take up an extra two bytes for
7835 the nop in the delay slot. */
7836 if (((GET_CODE (insn) == INSN
7837 && GET_CODE (PATTERN (insn)) != USE
7838 && GET_CODE (PATTERN (insn)) != CLOBBER)
7839 || GET_CODE (insn) == CALL_INSN
7840 || (GET_CODE (insn) == JUMP_INSN
7841 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
7842 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
7843 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
7844 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
7847 /* SH2e has a bug that prevents the use of annulled branches, so if
7848 the delay slot is not filled, we'll have to put a NOP in it. */
7849 if (sh_cpu == CPU_SH2E
7850 && GET_CODE (insn) == JUMP_INSN
7851 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
7852 && GET_CODE (PATTERN (insn)) != ADDR_VEC
7853 && get_attr_type (insn) == TYPE_CBRANCH
7854 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
7857 /* sh-dsp parallel processing insn take four bytes instead of two. */
7859 if (GET_CODE (insn) == INSN)
7862 rtx body = PATTERN (insn);
7863 const char *template;
7865 int maybe_label = 1;
7867 if (GET_CODE (body) == ASM_INPUT)
7868 template = XSTR (body, 0);
7869 else if (asm_noperands (body) >= 0)
7871 = decode_asm_operands (body, NULL, NULL, NULL, NULL);
7880 while (c == ' ' || c == '\t');
7881 /* all sh-dsp parallel-processing insns start with p.
7882 The only non-ppi sh insn starting with p is pref.
7883 The only ppi starting with pr is prnd. */
7884 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
7886 /* The repeat pseudo-insn expands two three insns, a total of
7887 six bytes in size. */
7888 else if ((c == 'r' || c == 'R')
7889 && ! strncasecmp ("epeat", template, 5))
7891 while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c))
7893 /* If this is a label, it is obviously not a ppi insn. */
7894 if (c == ':' && maybe_label)
7899 else if (c == '\'' || c == '"')
7904 maybe_label = c != ':';
7912 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
7913 isn't protected by a PIC unspec. */
7915 nonpic_symbol_mentioned_p (rtx x)
7917 register const char *fmt;
7920 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
7921 || GET_CODE (x) == PC)
7924 /* We don't want to look into the possible MEM location of a
7925 CONST_DOUBLE, since we're not going to use it, in general. */
7926 if (GET_CODE (x) == CONST_DOUBLE)
7929 if (GET_CODE (x) == UNSPEC
7930 && (XINT (x, 1) == UNSPEC_PIC
7931 || XINT (x, 1) == UNSPEC_GOT
7932 || XINT (x, 1) == UNSPEC_GOTOFF
7933 || XINT (x, 1) == UNSPEC_GOTPLT
7934 || XINT (x, 1) == UNSPEC_GOTTPOFF
7935 || XINT (x, 1) == UNSPEC_DTPOFF
7936 || XINT (x, 1) == UNSPEC_PLT))
7939 fmt = GET_RTX_FORMAT (GET_CODE (x));
7940 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
7946 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7947 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
7950 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
7957 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
7958 @GOTOFF in `reg'. */
7960 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
7963 if (tls_symbolic_operand (orig, Pmode))
7966 if (GET_CODE (orig) == LABEL_REF
7967 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
7970 reg = gen_reg_rtx (Pmode);
7972 emit_insn (gen_symGOTOFF2reg (reg, orig));
7975 else if (GET_CODE (orig) == SYMBOL_REF)
7978 reg = gen_reg_rtx (Pmode);
7980 emit_insn (gen_symGOT2reg (reg, orig));
7986 /* Mark the use of a constant in the literal table. If the constant
7987 has multiple labels, make it unique. */
7989 mark_constant_pool_use (rtx x)
7991 rtx insn, lab, pattern;
7996 switch (GET_CODE (x))
8006 /* Get the first label in the list of labels for the same constant
8007 and delete another labels in the list. */
8009 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
8011 if (GET_CODE (insn) != CODE_LABEL
8012 || LABEL_REFS (insn) != NEXT_INSN (insn))
8017 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
8018 INSN_DELETED_P (insn) = 1;
8020 /* Mark constants in a window. */
8021 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
8023 if (GET_CODE (insn) != INSN)
8026 pattern = PATTERN (insn);
8027 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
8030 switch (XINT (pattern, 1))
8032 case UNSPECV_CONST2:
8033 case UNSPECV_CONST4:
8034 case UNSPECV_CONST8:
8035 XVECEXP (pattern, 0, 1) = const1_rtx;
8037 case UNSPECV_WINDOW_END:
8038 if (XVECEXP (pattern, 0, 0) == x)
8041 case UNSPECV_CONST_END:
8051 /* Return true if it's possible to redirect BRANCH1 to the destination
8052 of an unconditional jump BRANCH2. We only want to do this if the
8053 resulting branch will have a short displacement. */
8055 sh_can_redirect_branch (rtx branch1, rtx branch2)
8057 if (flag_expensive_optimizations && simplejump_p (branch2))
8059 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
8063 for (distance = 0, insn = NEXT_INSN (branch1);
8064 insn && distance < 256;
8065 insn = PREV_INSN (insn))
8070 distance += get_attr_length (insn);
8072 for (distance = 0, insn = NEXT_INSN (branch1);
8073 insn && distance < 256;
8074 insn = NEXT_INSN (insn))
8079 distance += get_attr_length (insn);
8085 /* Return nonzero if register old_reg can be renamed to register new_reg. */
8087 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
8088 unsigned int new_reg)
8091 /* Interrupt functions can only use registers that have already been
8092 saved by the prologue, even if they would normally be
8095 if (sh_cfun_interrupt_handler_p () && !regs_ever_live[new_reg])
8101 /* Function to update the integer COST
8102 based on the relationship between INSN that is dependent on
8103 DEP_INSN through the dependence LINK. The default is to make no
8104 adjustment to COST. This can be used for example to specify to
8105 the scheduler that an output- or anti-dependence does not incur
8106 the same cost as a data-dependence. The return value should be
8107 the new value for COST. */
8109 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
8115 /* On SHmedia, if the dependence is an anti-dependence or
8116 output-dependence, there is no cost. */
8117 if (REG_NOTE_KIND (link) != 0)
8120 if (get_attr_is_mac_media (insn)
8121 && get_attr_is_mac_media (dep_insn))
8124 else if (REG_NOTE_KIND (link) == 0)
8126 enum attr_type dep_type, type;
8128 if (recog_memoized (insn) < 0
8129 || recog_memoized (dep_insn) < 0)
8132 dep_type = get_attr_type (dep_insn);
8133 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
8135 if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
8136 && (type = get_attr_type (insn)) != TYPE_CALL
8137 && type != TYPE_SFUNC)
8140 /* The only input for a call that is timing-critical is the
8141 function's address. */
8142 if (GET_CODE(insn) == CALL_INSN)
8144 rtx call = PATTERN (insn);
8146 if (GET_CODE (call) == PARALLEL)
8147 call = XVECEXP (call, 0 ,0);
8148 if (GET_CODE (call) == SET)
8149 call = SET_SRC (call);
8150 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
8151 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))
8154 /* Likewise, the most timing critical input for an sfuncs call
8155 is the function address. However, sfuncs typically start
8156 using their arguments pretty quickly.
8157 Assume a four cycle delay before they are needed. */
8158 /* All sfunc calls are parallels with at least four components.
8159 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
8160 else if (GET_CODE (PATTERN (insn)) == PARALLEL
8161 && XVECLEN (PATTERN (insn), 0) >= 4
8162 && (reg = sfunc_uses_reg (insn)))
8164 if (! reg_set_p (reg, dep_insn))
8167 /* When the preceding instruction loads the shift amount of
8168 the following SHAD/SHLD, the latency of the load is increased
8171 && get_attr_type (insn) == TYPE_DYN_SHIFT
8172 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
8173 && reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
8174 XEXP (SET_SRC (single_set(insn)),
8177 /* When an LS group instruction with a latency of less than
8178 3 cycles is followed by a double-precision floating-point
8179 instruction, FIPR, or FTRV, the latency of the first
8180 instruction is increased to 3 cycles. */
8182 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
8183 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
8185 /* The lsw register of a double-precision computation is ready one
8187 else if (reload_completed
8188 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
8189 && (use_pat = single_set (insn))
8190 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
8194 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
8195 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
8198 /* An anti-dependence penalty of two applies if the first insn is a double
8199 precision fadd / fsub / fmul. */
8200 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI
8201 && recog_memoized (dep_insn) >= 0
8202 && get_attr_type (dep_insn) == TYPE_DFP_ARITH
8203 /* A lot of alleged anti-flow dependences are fake,
8204 so check this one is real. */
8205 && flow_dependent_p (dep_insn, insn))
8212 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
8213 if DEP_INSN is anti-flow dependent on INSN. */
8215 flow_dependent_p (rtx insn, rtx dep_insn)
8217 rtx tmp = PATTERN (insn);
8219 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
8220 return tmp == NULL_RTX;
8223 /* A helper function for flow_dependent_p called through note_stores. */
8225 flow_dependent_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8227 rtx * pinsn = (rtx *) data;
8229 if (*pinsn && reg_referenced_p (x, *pinsn))
8233 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
8234 'special function' patterns (type sfunc) that clobber pr, but that
8235 do not look like function calls to leaf_function_p. Hence we must
8236 do this extra check. */
8240 return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
8243 /* This Function returns nonzero if the DFA based scheduler interface
8244 is to be used. At present this is supported for the SH4 only. */
8246 sh_use_dfa_interface(void)
8248 if (TARGET_HARD_SH4)
8254 /* This function returns "2" to indicate dual issue for the SH4
8255 processor. To be used by the DFA pipeline description. */
8259 if (TARGET_SUPERSCALAR)
8265 /* SHmedia requires registers for branches, so we can't generate new
8266 branches past reload. */
8268 sh_cannot_modify_jumps_p (void)
8270 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
8274 sh_target_reg_class (void)
8276 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
8280 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
8282 return (shmedia_space_reserved_for_target_registers
8283 && (! after_prologue_epilogue_gen || TARGET_SAVE_ALL_TARGET_REGS));
8287 sh_ms_bitfield_layout_p (record_type)
8288 tree record_type ATTRIBUTE_UNUSED;
8290 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
8294 On the SH1..SH4, the trampoline looks like
8295 2 0002 D202 mov.l l2,r2
8296 1 0000 D301 mov.l l1,r3
8299 5 0008 00000000 l1: .long area
8300 6 000c 00000000 l2: .long function
8302 SH5 (compact) uses r1 instead of r3 for the static chain. */
8305 /* Emit RTL insns to initialize the variable parts of a trampoline.
8306 FNADDR is an RTX for the address of the function's pure code.
8307 CXT is an RTX for the static chain value for the function. */
8310 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
8312 if (TARGET_SHMEDIA64)
8317 rtx movi1 = GEN_INT (0xcc000010);
8318 rtx shori1 = GEN_INT (0xc8000010);
8321 /* The following trampoline works within a +- 128 KB range for cxt:
8322 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
8323 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
8324 gettr tr1,r1; blink tr0,r63 */
8325 /* Address rounding makes it hard to compute the exact bounds of the
8326 offset for this trampoline, but we have a rather generous offset
8327 range, so frame_offset should do fine as an upper bound. */
8328 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
8330 /* ??? could optimize this trampoline initialization
8331 by writing DImode words with two insns each. */
8332 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
8333 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
8334 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
8335 insn = gen_rtx_AND (DImode, insn, mask);
8336 /* Or in ptb/u .,tr1 pattern */
8337 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
8338 insn = force_operand (insn, NULL_RTX);
8339 insn = gen_lowpart (SImode, insn);
8340 emit_move_insn (gen_rtx_MEM (SImode, tramp), insn);
8341 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
8342 insn = gen_rtx_AND (DImode, insn, mask);
8343 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
8344 insn = gen_lowpart (SImode, insn);
8345 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), insn);
8346 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
8347 insn = gen_rtx_AND (DImode, insn, mask);
8348 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8349 insn = gen_lowpart (SImode, insn);
8350 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), insn);
8351 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
8352 insn = gen_rtx_AND (DImode, insn, mask);
8353 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8354 insn = gen_lowpart (SImode, insn);
8355 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
8357 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
8358 insn = gen_rtx_AND (DImode, insn, mask);
8359 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8360 insn = gen_lowpart (SImode, insn);
8361 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 16)),
8363 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 20)),
8364 GEN_INT (0x6bf10600));
8365 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 24)),
8366 GEN_INT (0x4415fc10));
8367 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 28)),
8368 GEN_INT (0x4401fff0));
8369 emit_insn (gen_ic_invalidate_line (tramp));
8372 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
8373 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
8375 tramp_templ = gen_datalabel_ref (tramp_templ);
8376 dst = gen_rtx_MEM (BLKmode, tramp);
8377 src = gen_rtx_MEM (BLKmode, tramp_templ);
8378 set_mem_align (dst, 256);
8379 set_mem_align (src, 64);
8380 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
8382 emit_move_insn (gen_rtx_MEM (Pmode, plus_constant (tramp, fixed_len)),
8384 emit_move_insn (gen_rtx_MEM (Pmode,
8385 plus_constant (tramp,
8387 + GET_MODE_SIZE (Pmode))),
8389 emit_insn (gen_ic_invalidate_line (tramp));
8392 else if (TARGET_SHMEDIA)
8394 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
8395 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
8396 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
8397 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
8398 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
8399 rotated 10 right, and higher 16 bit of every 32 selected. */
8401 = force_reg (V2HImode, (simplify_gen_subreg
8402 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
8403 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
8404 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
8406 tramp = force_reg (Pmode, tramp);
8407 fnaddr = force_reg (SImode, fnaddr);
8408 cxt = force_reg (SImode, cxt);
8409 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
8410 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
8412 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
8413 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
8414 emit_insn (gen_ashldi3_media (quad0, quad0, GEN_INT (2)));
8415 emit_move_insn (gen_rtx_MEM (DImode, tramp), quad0);
8416 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
8417 gen_rtx_SUBREG (V2HImode, cxt, 0),
8419 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
8420 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
8421 emit_insn (gen_ashldi3_media (cxtload, cxtload, GEN_INT (2)));
8422 if (TARGET_LITTLE_ENDIAN)
8424 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
8425 emit_insn (gen_mextr4 (quad2, cxtload, blink));
8429 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
8430 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
8432 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 8)), quad1);
8433 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), quad2);
8434 emit_insn (gen_ic_invalidate_line (tramp));
8437 else if (TARGET_SHCOMPACT)
8439 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
8442 emit_move_insn (gen_rtx_MEM (SImode, tramp),
8443 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
8445 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
8446 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
8448 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
8450 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
8454 if (TARGET_USERMODE)
8455 emit_library_call (function_symbol ("__ic_invalidate"),
8456 0, VOIDmode, 1, tramp, SImode);
8458 emit_insn (gen_ic_invalidate_line (tramp));
8462 /* FIXME: This is overly conservative. A SHcompact function that
8463 receives arguments ``by reference'' will have them stored in its
8464 own stack frame, so it must not pass pointers or references to
8465 these arguments to other functions by means of sibling calls. */
8467 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8470 && (! TARGET_SHCOMPACT
8471 || current_function_args_info.stack_regs == 0)
8472 && ! sh_cfun_interrupt_handler_p ());
8475 /* Machine specific built-in functions. */
8477 struct builtin_description
8479 const enum insn_code icode;
8480 const char *const name;
8484 /* describe number and signedness of arguments; arg[0] == result
8485 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
8486 static const char signature_args[][4] =
8488 #define SH_BLTIN_V2SI2 0
8490 #define SH_BLTIN_V4HI2 1
8492 #define SH_BLTIN_V2SI3 2
8494 #define SH_BLTIN_V4HI3 3
8496 #define SH_BLTIN_V8QI3 4
8498 #define SH_BLTIN_MAC_HISI 5
8500 #define SH_BLTIN_SH_HI 6
8502 #define SH_BLTIN_SH_SI 7
8504 #define SH_BLTIN_V4HI2V2SI 8
8506 #define SH_BLTIN_V4HI2V8QI 9
8508 #define SH_BLTIN_SISF 10
8510 #define SH_BLTIN_LDUA_L 11
8512 #define SH_BLTIN_LDUA_Q 12
8514 #define SH_BLTIN_STUA_L 13
8516 #define SH_BLTIN_STUA_Q 14
8518 #define SH_BLTIN_UDI 15
8520 #define SH_BLTIN_NUM_SHARED_SIGNATURES 16
8521 #define SH_BLTIN_2 16
8522 #define SH_BLTIN_SU 16
8524 #define SH_BLTIN_3 17
8525 #define SH_BLTIN_SUS 17
8527 #define SH_BLTIN_PSSV 18
8529 #define SH_BLTIN_XXUU 19
8530 #define SH_BLTIN_UUUU 19
8532 #define SH_BLTIN_PV 20
8535 /* mcmv: operands considered unsigned. */
8536 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
8537 /* mperm: control value considered unsigned int. */
8538 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
8539 /* mshards_q: returns signed short. */
8540 /* nsb: takes long long arg, returns unsigned char. */
8541 static const struct builtin_description bdesc[] =
8543 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
8544 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
8545 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
8546 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
8547 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
8548 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
8549 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
8551 { CODE_FOR_alloco32, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
8552 { CODE_FOR_alloco64, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
8554 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
8555 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
8556 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
8557 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
8558 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
8559 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
8560 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
8561 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
8562 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
8563 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
8564 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI },
8565 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI },
8566 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI },
8567 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI },
8568 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI },
8569 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI },
8570 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI },
8571 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
8572 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
8573 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
8574 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
8575 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
8576 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
8577 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
8578 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
8579 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
8580 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
8581 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
8582 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
8583 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
8584 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
8585 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
8586 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
8587 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
8588 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
8589 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
8590 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
8591 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
8592 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
8593 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
8594 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
8595 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
8596 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
8597 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
8598 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
8599 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
8600 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
8601 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
8602 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
8603 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
8604 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
8605 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
8606 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
8607 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
8609 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
8610 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
8611 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
8612 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
8613 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
8614 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
8615 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
8616 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
8617 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
8618 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
8619 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
8620 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
8621 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
8622 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
8623 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
8624 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
8626 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
8627 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
8629 { CODE_FOR_prefetch32,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
8630 { CODE_FOR_prefetch64,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV }
8635 sh_media_init_builtins (void)
8637 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
8638 const struct builtin_description *d;
8640 memset (shared, 0, sizeof shared);
8641 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
8643 tree type, arg_type;
8644 int signature = d->signature;
8647 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
8648 type = shared[signature];
8651 int has_result = signature_args[signature][0] != 0;
8653 if (signature_args[signature][1] == 8
8654 && (insn_data[d->icode].operand[has_result].mode != Pmode))
8656 if (! TARGET_FPU_ANY
8657 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
8659 type = void_list_node;
8662 int arg = signature_args[signature][i];
8663 int opno = i - 1 + has_result;
8666 arg_type = ptr_type_node;
8668 arg_type = ((*lang_hooks.types.type_for_mode)
8669 (insn_data[d->icode].operand[opno].mode,
8674 arg_type = void_type_node;
8677 type = tree_cons (NULL_TREE, arg_type, type);
8679 type = build_function_type (arg_type, type);
8680 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
8681 shared[signature] = type;
8683 builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
8689 sh_init_builtins (void)
8692 sh_media_init_builtins ();
8695 /* Expand an expression EXP that calls a built-in function,
8696 with result going to TARGET if that's convenient
8697 (and in mode MODE if that's convenient).
8698 SUBTARGET may be used as the target for computing one of EXP's operands.
8699 IGNORE is nonzero if the value is to be ignored. */
8702 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8703 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
8705 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8706 tree arglist = TREE_OPERAND (exp, 1);
8707 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8708 const struct builtin_description *d = &bdesc[fcode];
8709 enum insn_code icode = d->icode;
8710 int signature = d->signature;
8711 enum machine_mode tmode = VOIDmode;
8716 if (signature_args[signature][0])
8721 tmode = insn_data[icode].operand[0].mode;
8723 || GET_MODE (target) != tmode
8724 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8725 target = gen_reg_rtx (tmode);
8731 for (i = 1; i <= 3; i++, nop++)
8734 enum machine_mode opmode, argmode;
8736 if (! signature_args[signature][i])
8738 arg = TREE_VALUE (arglist);
8739 if (arg == error_mark_node)
8741 arglist = TREE_CHAIN (arglist);
8742 opmode = insn_data[icode].operand[nop].mode;
8743 argmode = TYPE_MODE (TREE_TYPE (arg));
8744 if (argmode != opmode)
8745 arg = build1 (NOP_EXPR,
8746 (*lang_hooks.types.type_for_mode) (opmode, 0), arg);
8747 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
8748 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
8749 op[nop] = copy_to_mode_reg (opmode, op[nop]);
8755 pat = (*insn_data[d->icode].genfun) (op[0]);
8758 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
8761 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
8764 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
8776 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
8778 rtx sel0 = const0_rtx;
8779 rtx sel1 = const1_rtx;
8780 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
8781 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
8783 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
8784 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
8788 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
8790 rtx sel0 = const0_rtx;
8791 rtx sel1 = const1_rtx;
8792 rtx (*fn) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx)
8794 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
8796 emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0, sel1));
8797 emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1, sel0));
8800 /* Return the class of registers for which a mode change from FROM to TO
8803 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
8804 enum reg_class class)
8806 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
8808 if (TARGET_LITTLE_ENDIAN)
8810 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
8811 return reg_classes_intersect_p (DF_REGS, class);
8815 if (GET_MODE_SIZE (from) < 8)
8816 return reg_classes_intersect_p (DF_HI_REGS, class);
8823 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
8824 that label is used. */
8827 sh_mark_label (rtx address, int nuses)
8829 if (GOTOFF_P (address))
8831 /* Extract the label or symbol. */
8832 address = XEXP (address, 0);
8833 if (GET_CODE (address) == PLUS)
8834 address = XEXP (address, 0);
8835 address = XVECEXP (address, 0, 0);
8837 if (GET_CODE (address) == LABEL_REF
8838 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
8839 LABEL_NUSES (XEXP (address, 0)) += nuses;
8842 /* Compute extra cost of moving data between one register class
8845 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
8846 uses this information. Hence, the general register <-> floating point
8847 register information here is not used for SFmode. */
8850 sh_register_move_cost (enum machine_mode mode,
8851 enum reg_class srcclass, enum reg_class dstclass)
8853 if (dstclass == T_REGS || dstclass == PR_REGS)
8856 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
8859 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
8860 && REGCLASS_HAS_FP_REG (srcclass)
8861 && REGCLASS_HAS_FP_REG (dstclass))
8864 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
8865 || (dstclass== MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
8868 if ((REGCLASS_HAS_FP_REG (dstclass)
8869 && REGCLASS_HAS_GENERAL_REG (srcclass))
8870 || (REGCLASS_HAS_GENERAL_REG (dstclass)
8871 && REGCLASS_HAS_FP_REG (srcclass)))
8872 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
8873 * ((GET_MODE_SIZE (mode) + 7) / 8U));
8875 if ((dstclass == FPUL_REGS
8876 && REGCLASS_HAS_GENERAL_REG (srcclass))
8877 || (srcclass == FPUL_REGS
8878 && REGCLASS_HAS_GENERAL_REG (dstclass)))
8881 if ((dstclass == FPUL_REGS
8882 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
8883 || (srcclass == FPUL_REGS
8884 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
8887 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
8888 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
8891 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
8892 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
8897 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
8898 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
8899 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
8901 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
8904 /* Like register_operand, but take into account that SHMEDIA can use
8905 the constant zero like a general register. */
8907 sh_register_operand (rtx op, enum machine_mode mode)
8909 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
8911 return register_operand (op, mode);
8915 cmpsi_operand (rtx op, enum machine_mode mode)
8917 if (GET_CODE (op) == REG && REGNO (op) == T_REG
8918 && GET_MODE (op) == SImode)
8920 return arith_operand (op, mode);
8923 static rtx emit_load_ptr (rtx, rtx);
8926 emit_load_ptr (rtx reg, rtx addr)
8928 rtx mem = gen_rtx_MEM (ptr_mode, addr);
8930 if (Pmode != ptr_mode)
8931 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
8932 return emit_move_insn (reg, mem);
8936 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8937 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8940 CUMULATIVE_ARGS cum;
8941 int structure_value_byref = 0;
8942 rtx this, this_value, sibcall, insns, funexp;
8943 tree funtype = TREE_TYPE (function);
8944 int simple_add = CONST_OK_FOR_ADD (delta);
8946 rtx scratch0, scratch1, scratch2;
8948 reload_completed = 1;
8949 epilogue_completed = 1;
8951 current_function_uses_only_leaf_regs = 1;
8953 emit_note (NOTE_INSN_PROLOGUE_END);
8955 /* Find the "this" pointer. We have such a wide range of ABIs for the
8956 SH that it's best to do this completely machine independently.
8957 "this" is passed as first argument, unless a structure return pointer
8958 comes first, in which case "this" comes second. */
8959 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0);
8960 #ifndef PCC_STATIC_STRUCT_RETURN
8961 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8962 structure_value_byref = 1;
8963 #endif /* not PCC_STATIC_STRUCT_RETURN */
8964 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
8966 tree ptype = build_pointer_type (TREE_TYPE (funtype));
8968 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
8970 this = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
8972 /* For SHcompact, we only have r0 for a scratch register: r1 is the
8973 static chain pointer (even if you can't have nested virtual functions
8974 right now, someone might implement them sometime), and the rest of the
8975 registers are used for argument passing, are callee-saved, or reserved. */
8976 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
8979 scratch1 = gen_rtx_REG (ptr_mode, 1);
8980 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
8981 pointing where to return struct values. */
8982 scratch2 = gen_rtx_REG (Pmode, 3);
8984 else if (TARGET_SHMEDIA)
8986 scratch1 = gen_rtx_REG (ptr_mode, 21);
8987 scratch2 = gen_rtx_REG (Pmode, TR0_REG);
8990 this_value = plus_constant (this, delta);
8992 && (simple_add || scratch0 != scratch1)
8993 && strict_memory_address_p (ptr_mode, this_value))
8995 emit_load_ptr (scratch0, this_value);
9001 else if (simple_add)
9002 emit_move_insn (this, this_value);
9005 emit_move_insn (scratch1, GEN_INT (delta));
9006 emit_insn (gen_add2_insn (this, scratch1));
9014 emit_load_ptr (scratch0, this);
9016 offset_addr = plus_constant (scratch0, vcall_offset);
9017 if (strict_memory_address_p (ptr_mode, offset_addr))
9019 else if (! TARGET_SH5)
9021 /* scratch0 != scratch1, and we have indexed loads. Get better
9022 schedule by loading the offset into r1 and using an indexed
9023 load - then the load of r1 can issue before the load from
9024 (this + delta) finishes. */
9025 emit_move_insn (scratch1, GEN_INT (vcall_offset));
9026 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
9028 else if (CONST_OK_FOR_ADD (vcall_offset))
9030 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
9031 offset_addr = scratch0;
9033 else if (scratch0 != scratch1)
9035 emit_move_insn (scratch1, GEN_INT (vcall_offset));
9036 emit_insn (gen_add2_insn (scratch0, scratch1));
9037 offset_addr = scratch0;
9040 abort (); /* FIXME */
9041 emit_load_ptr (scratch0, offset_addr);
9043 if (Pmode != ptr_mode)
9044 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
9045 emit_insn (gen_add2_insn (this, scratch0));
9048 /* Generate a tail call to the target function. */
9049 if (! TREE_USED (function))
9051 assemble_external (function);
9052 TREE_USED (function) = 1;
9054 funexp = XEXP (DECL_RTL (function), 0);
9055 emit_move_insn (scratch2, funexp);
9056 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
9057 sibcall = emit_call_insn (gen_sibcall (funexp, const0_rtx, NULL_RTX));
9058 SIBLING_CALL_P (sibcall) = 1;
9059 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this);
9062 /* Run just enough of rest_of_compilation to do scheduling and get
9063 the insns emitted. Note that use_thunk calls
9064 assemble_start_function and assemble_end_function. */
9066 insn_locators_initialize ();
9067 insns = get_insns ();
9069 if (optimize > 0 && flag_schedule_insns_after_reload)
9072 find_basic_blocks (insns, max_reg_num (), rtl_dump_file);
9073 life_analysis (insns, rtl_dump_file, PROP_FINAL);
9075 split_all_insns (1);
9077 schedule_insns (rtl_dump_file);
9082 if (optimize > 0 && flag_delayed_branch)
9083 dbr_schedule (insns, rtl_dump_file);
9084 shorten_branches (insns);
9085 final_start_function (insns, file, 1);
9086 final (insns, file, 1, 0);
9087 final_end_function ();
9089 if (optimize > 0 && flag_schedule_insns_after_reload)
9091 /* Release all memory allocated by flow. */
9092 free_basic_block_vars (0);
9094 /* Release all memory held by regsets now. */
9095 regset_release_memory ();
9098 reload_completed = 0;
9099 epilogue_completed = 0;
9104 function_symbol (const char *name)
9106 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
9107 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
9111 /* Find the number of a general purpose register in S. */
9113 scavenge_reg (HARD_REG_SET *s)
9116 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
9117 if (TEST_HARD_REG_BIT (*s, r))
9123 sh_get_pr_initial_val (void)
9127 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
9128 PR register on SHcompact, because it might be clobbered by the prologue.
9129 We check first if that is known to be the case. */
9130 if (TARGET_SHCOMPACT
9131 && ((current_function_args_info.call_cookie
9132 & ~ CALL_COOKIE_RET_TRAMP (1))
9133 || current_function_has_nonlocal_label))
9134 return gen_rtx_MEM (SImode, return_address_pointer_rtx);
9136 /* If we haven't finished rtl generation, there might be a nonlocal label
9137 that we haven't seen yet.
9138 ??? get_hard_reg_initial_val fails if it is called while no_new_pseudos
9139 is set, unless it has been called before for the same register. And even
9140 then, we end in trouble if we didn't use the register in the same
9141 basic block before. So call get_hard_reg_initial_val now and wrap it
9142 in an unspec if we might need to replace it. */
9143 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
9144 combine can put the pseudo returned by get_hard_reg_initial_val into
9145 instructions that need a general purpose registers, which will fail to
9146 be recognized when the pseudo becomes allocated to PR. */
9148 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9150 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
9155 sh_expand_t_scc (enum rtx_code code, rtx target)
9157 rtx result = target;
9160 if (GET_CODE (sh_compare_op0) != REG || REGNO (sh_compare_op0) != T_REG
9161 || GET_CODE (sh_compare_op1) != CONST_INT)
9163 if (GET_CODE (result) != REG)
9164 result = gen_reg_rtx (SImode);
9165 val = INTVAL (sh_compare_op1);
9166 if ((code == EQ && val == 1) || (code == NE && val == 0))
9167 emit_insn (gen_movt (result));
9168 else if ((code == EQ && val == 0) || (code == NE && val == 1))
9170 emit_insn (gen_rtx_CLOBBER (VOIDmode, result));
9171 emit_insn (gen_subc (result, result, result));
9172 emit_insn (gen_addsi3 (result, result, GEN_INT (1)));
9174 else if (code == EQ || code == NE)
9175 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
9178 if (result != target)
9179 emit_move_insn (target, result);
9183 /* INSN is an sfunc; return the rtx that describes the address used. */
9185 extract_sfunc_addr (rtx insn)
9187 rtx pattern, part = NULL_RTX;
9190 pattern = PATTERN (insn);
9191 len = XVECLEN (pattern, 0);
9192 for (i = 0; i < len; i++)
9194 part = XVECEXP (pattern, 0, i);
9195 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
9196 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
9197 return XEXP (part, 0);
9199 if (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE)
9200 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
9204 /* Verify that the register in use_sfunc_addr still agrees with the address
9205 used in the sfunc. This prevents fill_slots_from_thread from changing
9207 INSN is the use_sfunc_addr instruction, and REG is the register it
9210 check_use_sfunc_addr (rtx insn, rtx reg)
9212 /* Search for the sfunc. It should really come right after INSN. */
9213 while ((insn = NEXT_INSN (insn)))
9215 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
9217 if (! INSN_P (insn))
9220 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9221 insn = XVECEXP (PATTERN (insn), 0, 0);
9222 if (GET_CODE (PATTERN (insn)) != PARALLEL
9223 || get_attr_type (insn) != TYPE_SFUNC)
9225 return rtx_equal_p (extract_sfunc_addr (insn), reg);