1 /* Output routines for GCC for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
34 #include "hard-reg-set.h"
36 #include "insn-attr.h"
40 #include "integrate.h"
43 #include "target-def.h"
46 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
48 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
49 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
51 /* These are some macros to abstract register modes. */
52 #define CONST_OK_FOR_ADD(size) \
53 (TARGET_SHMEDIA ? CONST_OK_FOR_P (size) : CONST_OK_FOR_I (size))
54 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
55 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
56 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
58 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
59 int current_function_interrupt;
61 /* ??? The pragma interrupt support will not work for SH3. */
62 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
63 output code for the next function appropriate for an interrupt handler. */
66 /* This is set by the trap_exit attribute for functions. It specifies
67 a trap number to be used in a trapa instruction at function exit
68 (instead of an rte instruction). */
71 /* This is used by the sp_switch attribute for functions. It specifies
72 a variable holding the address of the stack the interrupt function
73 should switch to/from at entry/exit. */
76 /* This is set by #pragma trapa, and is similar to the above, except that
77 the compiler doesn't emit code to preserve all registers. */
78 static int pragma_trapa;
80 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
81 which has a separate set of low regs for User and Supervisor modes.
82 This should only be used for the lowest level of interrupts. Higher levels
83 of interrupts must save the registers in case they themselves are
85 int pragma_nosave_low_regs;
87 /* This is used for communication between SETUP_INCOMING_VARARGS and
88 sh_expand_prologue. */
89 int current_function_anonymous_args;
91 /* Global variables for machine-dependent things. */
93 /* Which cpu are we scheduling for. */
94 enum processor_type sh_cpu;
96 /* Saved operands from the last compare to use when we generate an scc
102 /* Provides the class number of the smallest class containing
105 int regno_reg_class[FIRST_PSEUDO_REGISTER] =
107 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
108 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
109 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
110 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
111 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
112 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
113 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
114 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
124 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
125 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
126 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
127 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
128 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
129 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
130 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
140 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
141 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
142 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
143 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
144 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
148 char sh_register_names[FIRST_PSEUDO_REGISTER] \
149 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
151 char sh_additional_register_names[ADDREGNAMES_SIZE] \
152 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
153 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
155 /* Provide reg_class from a letter such as appears in the machine
158 const enum reg_class reg_class_from_letter[] =
160 /* a */ ALL_REGS, /* b */ TARGET_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
161 /* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
162 /* i */ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
163 /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
164 /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
165 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
166 /* y */ FPUL_REGS, /* z */ R0_REGS
169 int assembler_dialect;
171 static void split_branches PARAMS ((rtx));
172 static int branch_dest PARAMS ((rtx));
173 static void force_into PARAMS ((rtx, rtx));
174 static void print_slot PARAMS ((rtx));
175 static rtx add_constant PARAMS ((rtx, enum machine_mode, rtx));
176 static void dump_table PARAMS ((rtx));
177 static int hi_const PARAMS ((rtx));
178 static int broken_move PARAMS ((rtx));
179 static int mova_p PARAMS ((rtx));
180 static rtx find_barrier PARAMS ((int, rtx, rtx));
181 static int noncall_uses_reg PARAMS ((rtx, rtx, rtx *));
182 static rtx gen_block_redirect PARAMS ((rtx, int, int));
183 static void output_stack_adjust PARAMS ((int, rtx, int));
184 static void push PARAMS ((int));
185 static void pop PARAMS ((int));
186 static void push_regs PARAMS ((HOST_WIDE_INT *));
187 static void calc_live_regs PARAMS ((int *, HOST_WIDE_INT *));
188 static void mark_use PARAMS ((rtx, rtx *));
189 static HOST_WIDE_INT rounded_frame_size PARAMS ((int));
190 static rtx mark_constant_pool_use PARAMS ((rtx));
191 const struct attribute_spec sh_attribute_table[];
192 static tree sh_handle_interrupt_handler_attribute PARAMS ((tree *, tree, tree, int, bool *));
193 static tree sh_handle_sp_switch_attribute PARAMS ((tree *, tree, tree, int, bool *));
194 static tree sh_handle_trap_exit_attribute PARAMS ((tree *, tree, tree, int, bool *));
195 static void sh_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
196 static void sh_insert_attributes PARAMS ((tree, tree *));
197 static int sh_adjust_cost PARAMS ((rtx, rtx, rtx, int));
198 static int sh_use_dfa_interface PARAMS ((void));
199 static int sh_issue_rate PARAMS ((void));
201 static bool sh_cannot_modify_jumps_p PARAMS ((void));
202 static bool sh_ms_bitfield_layout_p PARAMS ((tree));
204 static void sh_encode_section_info PARAMS ((tree, int));
205 static const char *sh_strip_name_encoding PARAMS ((const char *));
207 /* Initialize the GCC target structure. */
208 #undef TARGET_ATTRIBUTE_TABLE
209 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
211 /* The next two are used for debug info when compiling with -gdwarf. */
212 #undef TARGET_ASM_UNALIGNED_HI_OP
213 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
214 #undef TARGET_ASM_UNALIGNED_SI_OP
215 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
217 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
218 #undef TARGET_ASM_UNALIGNED_DI_OP
219 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
220 #undef TARGET_ASM_ALIGNED_DI_OP
221 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
223 #undef TARGET_ASM_FUNCTION_EPILOGUE
224 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
226 #undef TARGET_INSERT_ATTRIBUTES
227 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
229 #undef TARGET_SCHED_ADJUST_COST
230 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
232 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
233 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
235 #undef TARGET_SCHED_ISSUE_RATE
236 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
238 #undef TARGET_CANNOT_MODIFY_JUMPS_P
239 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
241 #undef TARGET_MS_BITFIELD_LAYOUT_P
242 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
244 #undef TARGET_ENCODE_SECTION_INFO
245 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
246 #undef TARGET_STRIP_NAME_ENCODING
247 #define TARGET_STRIP_NAME_ENCODING sh_strip_name_encoding
249 struct gcc_target targetm = TARGET_INITIALIZER;
251 /* Print the operand address in x to the stream. */
254 print_operand_address (stream, x)
258 switch (GET_CODE (x))
262 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
267 rtx base = XEXP (x, 0);
268 rtx index = XEXP (x, 1);
270 switch (GET_CODE (index))
273 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
274 reg_names[true_regnum (base)]);
280 int base_num = true_regnum (base);
281 int index_num = true_regnum (index);
283 fprintf (stream, "@(r0,%s)",
284 reg_names[MAX (base_num, index_num)]);
296 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
300 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
304 x = mark_constant_pool_use (x);
305 output_addr_const (stream, x);
310 /* Print operand x (an rtx) in assembler syntax to file stream
311 according to modifier code.
313 '.' print a .s if insn needs delay slot
314 ',' print LOCAL_LABEL_PREFIX
315 '@' print trap, rte or rts depending upon pragma interruptness
316 '#' output a nop if there is nothing to put in the delay slot
317 'O' print a constant without the #
318 'R' print the LSW of a dp value - changes if in little endian
319 'S' print the MSW of a dp value - changes if in little endian
320 'T' print the next word of a dp value - same as 'R' in big endian mode.
321 'M' print an `x' if `m' will print `base,index'.
322 'm' print a pair `base,offset' or `base,index', for LD and ST.
323 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
324 'o' output an operator. */
327 print_operand (stream, x, code)
336 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
337 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
340 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
344 int interrupt_handler;
346 if ((lookup_attribute
347 ("interrupt_handler",
348 DECL_ATTRIBUTES (current_function_decl)))
350 interrupt_handler = 1;
352 interrupt_handler = 0;
355 fprintf (stream, "trapa #%d", trap_exit);
356 else if (interrupt_handler)
357 fprintf (stream, "rte");
359 fprintf (stream, "rts");
363 /* Output a nop if there's nothing in the delay slot. */
364 if (dbr_sequence_length () == 0)
365 fprintf (stream, "\n\tnop");
368 x = mark_constant_pool_use (x);
369 output_addr_const (stream, x);
372 fputs (reg_names[REGNO (x) + LSW], (stream));
375 fputs (reg_names[REGNO (x) + MSW], (stream));
378 /* Next word of a double. */
379 switch (GET_CODE (x))
382 fputs (reg_names[REGNO (x) + 1], (stream));
385 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
386 && GET_CODE (XEXP (x, 0)) != POST_INC)
387 x = adjust_address (x, SImode, 4);
388 print_operand_address (stream, XEXP (x, 0));
395 switch (GET_CODE (x))
397 case PLUS: fputs ("add", stream); break;
398 case MINUS: fputs ("sub", stream); break;
399 case MULT: fputs ("mul", stream); break;
400 case DIV: fputs ("div", stream); break;
406 if (GET_CODE (x) == MEM
407 && GET_CODE (XEXP (x, 0)) == PLUS
408 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
409 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
414 if (GET_CODE (x) != MEM)
417 switch (GET_CODE (x))
421 print_operand (stream, x, 0);
422 fputs (", 0", stream);
426 print_operand (stream, XEXP (x, 0), 0);
427 fputs (", ", stream);
428 print_operand (stream, XEXP (x, 1), 0);
437 if (GET_CODE (x) == CONST_INT)
439 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
445 switch (GET_CODE (x))
447 /* FIXME: We need this on SHmedia32 because reload generates
448 some sign-extended HI or QI loads into DImode registers
449 but, because Pmode is SImode, the address ends up with a
450 subreg:SI of the DImode register. Maybe reload should be
451 fixed so as to apply alter_subreg to such loads? */
453 if (SUBREG_BYTE (x) != 0
454 || GET_CODE (SUBREG_REG (x)) != REG)
461 if (FP_REGISTER_P (REGNO (x))
462 && GET_MODE (x) == V16SFmode)
463 fprintf ((stream), "mtrx%s", reg_names[REGNO (x)] + 2);
464 else if (FP_REGISTER_P (REGNO (x))
465 && GET_MODE (x) == V4SFmode)
466 fprintf ((stream), "fv%s", reg_names[REGNO (x)] + 2);
467 else if (GET_CODE (x) == REG
468 && GET_MODE (x) == V2SFmode)
469 fprintf ((stream), "fp%s", reg_names[REGNO (x)] + 2);
470 else if (FP_REGISTER_P (REGNO (x))
471 && GET_MODE_SIZE (GET_MODE (x)) > 4)
472 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
474 fputs (reg_names[REGNO (x)], (stream));
478 output_address (XEXP (x, 0));
483 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
484 && GET_MODE (XEXP (x, 0)) == DImode
485 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
486 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
488 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
491 if (GET_CODE (val) == ASHIFTRT)
494 if (GET_CODE (XEXP (val, 0)) == CONST)
496 output_addr_const (stream, XEXP (val, 0));
497 if (GET_CODE (XEXP (val, 0)) == CONST)
499 fputs (" >> ", stream);
500 output_addr_const (stream, XEXP (val, 1));
505 if (GET_CODE (val) == CONST)
507 output_addr_const (stream, val);
508 if (GET_CODE (val) == CONST)
511 fputs (" & 65535)", stream);
519 output_addr_const (stream, x);
526 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
528 force_into (value, target)
531 value = force_operand (value, target);
532 if (! rtx_equal_p (value, target))
533 emit_insn (gen_move_insn (target, value));
536 /* Emit code to perform a block move. Choose the best method.
538 OPERANDS[0] is the destination.
539 OPERANDS[1] is the source.
540 OPERANDS[2] is the size.
541 OPERANDS[3] is the alignment safe to use. */
544 expand_block_move (operands)
547 int align = INTVAL (operands[3]);
548 int constp = (GET_CODE (operands[2]) == CONST_INT);
549 int bytes = (constp ? INTVAL (operands[2]) : 0);
551 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
552 alignment, or if it isn't a multiple of 4 bytes, then fail. */
553 if (! constp || align < 4 || (bytes % 4 != 0))
560 else if (bytes == 12)
565 rtx r4 = gen_rtx (REG, SImode, 4);
566 rtx r5 = gen_rtx (REG, SImode, 5);
568 entry_name = get_identifier ("__movstrSI12_i4");
570 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
571 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
572 force_into (XEXP (operands[0], 0), r4);
573 force_into (XEXP (operands[1], 0), r5);
574 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
577 else if (! TARGET_SMALLCODE)
583 rtx r4 = gen_rtx (REG, SImode, 4);
584 rtx r5 = gen_rtx (REG, SImode, 5);
585 rtx r6 = gen_rtx (REG, SImode, 6);
587 entry_name = get_identifier (bytes & 4
589 : "__movstr_i4_even");
590 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
591 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
592 force_into (XEXP (operands[0], 0), r4);
593 force_into (XEXP (operands[1], 0), r5);
596 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
597 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
609 rtx r4 = gen_rtx_REG (SImode, 4);
610 rtx r5 = gen_rtx_REG (SImode, 5);
612 sprintf (entry, "__movstrSI%d", bytes);
613 entry_name = get_identifier (entry);
614 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
615 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
616 force_into (XEXP (operands[0], 0), r4);
617 force_into (XEXP (operands[1], 0), r5);
618 emit_insn (gen_block_move_real (func_addr_rtx));
622 /* This is the same number of bytes as a memcpy call, but to a different
623 less common function name, so this will occasionally use more space. */
624 if (! TARGET_SMALLCODE)
629 int final_switch, while_loop;
630 rtx r4 = gen_rtx_REG (SImode, 4);
631 rtx r5 = gen_rtx_REG (SImode, 5);
632 rtx r6 = gen_rtx_REG (SImode, 6);
634 entry_name = get_identifier ("__movstr");
635 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
636 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
637 force_into (XEXP (operands[0], 0), r4);
638 force_into (XEXP (operands[1], 0), r5);
640 /* r6 controls the size of the move. 16 is decremented from it
641 for each 64 bytes moved. Then the negative bit left over is used
642 as an index into a list of move instructions. e.g., a 72 byte move
643 would be set up with size(r6) = 14, for one iteration through the
644 big while loop, and a switch of -2 for the last part. */
646 final_switch = 16 - ((bytes / 4) % 16);
647 while_loop = ((bytes / 4) / 16 - 1) * 16;
648 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
649 emit_insn (gen_block_lump_real (func_addr_rtx));
656 /* Prepare operands for a move define_expand; specifically, one of the
657 operands must be in a register. */
660 prepare_move_operands (operands, mode)
662 enum machine_mode mode;
664 if ((mode == SImode || mode == DImode) && flag_pic)
667 if (SYMBOLIC_CONST_P (operands[1]))
669 if (GET_CODE (operands[0]) == MEM)
670 operands[1] = force_reg (Pmode, operands[1]);
671 else if (GET_CODE (operands[1]) == LABEL_REF
672 && target_reg_operand (operands[0], mode))
676 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
677 operands[1] = legitimize_pic_address (operands[1], mode, temp);
680 else if (GET_CODE (operands[1]) == CONST
681 && GET_CODE (XEXP (operands[1], 0)) == PLUS
682 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
684 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
685 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
687 operands[1] = expand_binop (mode, add_optab, temp,
688 XEXP (XEXP (operands[1], 0), 1),
689 no_new_pseudos ? temp
690 : gen_reg_rtx (Pmode),
695 if (! reload_in_progress && ! reload_completed)
697 /* Copy the source to a register if both operands aren't registers. */
698 if (! register_operand (operands[0], mode)
699 && ! register_operand (operands[1], mode))
700 operands[1] = copy_to_mode_reg (mode, operands[1]);
702 /* This case can happen while generating code to move the result
703 of a library call to the target. Reject `st r0,@(rX,rY)' because
704 reload will fail to find a spill register for rX, since r0 is already
705 being used for the source. */
706 else if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 0
707 && GET_CODE (operands[0]) == MEM
708 && GET_CODE (XEXP (operands[0], 0)) == PLUS
709 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
710 operands[1] = copy_to_mode_reg (mode, operands[1]);
716 /* Prepare the operands for an scc instruction; make sure that the
717 compare has been done. */
719 prepare_scc_operands (code)
722 rtx t_reg = gen_rtx_REG (SImode, T_REG);
723 enum rtx_code oldcode = code;
724 enum machine_mode mode;
726 /* First need a compare insn. */
730 /* It isn't possible to handle this case. */
749 rtx tmp = sh_compare_op0;
750 sh_compare_op0 = sh_compare_op1;
751 sh_compare_op1 = tmp;
754 mode = GET_MODE (sh_compare_op0);
755 if (mode == VOIDmode)
756 mode = GET_MODE (sh_compare_op1);
758 sh_compare_op0 = force_reg (mode, sh_compare_op0);
759 if ((code != EQ && code != NE
760 && (sh_compare_op1 != const0_rtx
761 || code == GTU || code == GEU || code == LTU || code == LEU))
762 || (mode == DImode && sh_compare_op1 != const0_rtx)
763 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
764 sh_compare_op1 = force_reg (mode, sh_compare_op1);
766 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
767 (mode == SFmode ? emit_sf_insn : emit_df_insn)
768 (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
769 gen_rtx (SET, VOIDmode, t_reg,
770 gen_rtx (code, SImode,
771 sh_compare_op0, sh_compare_op1)),
772 gen_rtx (USE, VOIDmode, get_fpscr_rtx ()))));
774 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
775 gen_rtx (code, SImode, sh_compare_op0,
781 /* Called from the md file, set up the operands of a compare instruction. */
784 from_compare (operands, code)
788 enum machine_mode mode = GET_MODE (sh_compare_op0);
790 if (mode == VOIDmode)
791 mode = GET_MODE (sh_compare_op1);
794 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
796 /* Force args into regs, since we can't use constants here. */
797 sh_compare_op0 = force_reg (mode, sh_compare_op0);
798 if (sh_compare_op1 != const0_rtx
799 || code == GTU || code == GEU
800 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
801 sh_compare_op1 = force_reg (mode, sh_compare_op1);
803 if (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
805 from_compare (operands, GT);
806 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
809 insn = gen_rtx_SET (VOIDmode,
810 gen_rtx_REG (SImode, T_REG),
811 gen_rtx (code, SImode, sh_compare_op0,
813 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
815 insn = gen_rtx (PARALLEL, VOIDmode,
817 gen_rtx (USE, VOIDmode, get_fpscr_rtx ())));
818 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
824 /* Functions to output assembly code. */
826 /* Return a sequence of instructions to perform DI or DF move.
828 Since the SH cannot move a DI or DF in one instruction, we have
829 to take care when we see overlapping source and dest registers. */
832 output_movedouble (insn, operands, mode)
833 rtx insn ATTRIBUTE_UNUSED;
835 enum machine_mode mode;
837 rtx dst = operands[0];
838 rtx src = operands[1];
840 if (GET_CODE (dst) == MEM
841 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
842 return "mov.l %T1,%0\n\tmov.l %1,%0";
844 if (register_operand (dst, mode)
845 && register_operand (src, mode))
847 if (REGNO (src) == MACH_REG)
848 return "sts mach,%S0\n\tsts macl,%R0";
850 /* When mov.d r1,r2 do r2->r3 then r1->r2;
851 when mov.d r1,r0 do r1->r0 then r2->r1. */
853 if (REGNO (src) + 1 == REGNO (dst))
854 return "mov %T1,%T0\n\tmov %1,%0";
856 return "mov %1,%0\n\tmov %T1,%T0";
858 else if (GET_CODE (src) == CONST_INT)
860 if (INTVAL (src) < 0)
861 output_asm_insn ("mov #-1,%S0", operands);
863 output_asm_insn ("mov #0,%S0", operands);
867 else if (GET_CODE (src) == MEM)
870 int dreg = REGNO (dst);
871 rtx inside = XEXP (src, 0);
873 if (GET_CODE (inside) == REG)
874 ptrreg = REGNO (inside);
875 else if (GET_CODE (inside) == SUBREG)
876 ptrreg = subreg_regno (inside);
877 else if (GET_CODE (inside) == PLUS)
879 ptrreg = REGNO (XEXP (inside, 0));
880 /* ??? A r0+REG address shouldn't be possible here, because it isn't
881 an offsettable address. Unfortunately, offsettable addresses use
882 QImode to check the offset, and a QImode offsettable address
883 requires r0 for the other operand, which is not currently
884 supported, so we can't use the 'o' constraint.
885 Thus we must check for and handle r0+REG addresses here.
886 We punt for now, since this is likely very rare. */
887 if (GET_CODE (XEXP (inside, 1)) == REG)
890 else if (GET_CODE (inside) == LABEL_REF)
891 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
892 else if (GET_CODE (inside) == POST_INC)
893 return "mov.l %1,%0\n\tmov.l %1,%T0";
897 /* Work out the safe way to copy. Copy into the second half first. */
899 return "mov.l %T1,%T0\n\tmov.l %1,%0";
902 return "mov.l %1,%0\n\tmov.l %T1,%T0";
905 /* Print an instruction which would have gone into a delay slot after
906 another instruction, but couldn't because the other instruction expanded
907 into a sequence where putting the slot insn at the end wouldn't work. */
913 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
915 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
919 output_far_jump (insn, op)
923 struct { rtx lab, reg, op; } this;
924 rtx braf_base_lab = NULL_RTX;
927 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
929 this.lab = gen_label_rtx ();
933 && offset - get_attr_length (insn) <= 32766)
936 jump = "mov.w %O0,%1; braf %1";
944 jump = "mov.l %O0,%1; braf %1";
946 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
949 jump = "mov.l %O0,%1; jmp @%1";
951 /* If we have a scratch register available, use it. */
952 if (GET_CODE (PREV_INSN (insn)) == INSN
953 && INSN_CODE (PREV_INSN (insn)) == CODE_FOR_indirect_jump_scratch)
955 this.reg = SET_DEST (PATTERN (PREV_INSN (insn)));
956 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
957 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
958 output_asm_insn (jump, &this.lab);
959 if (dbr_sequence_length ())
960 print_slot (final_sequence);
962 output_asm_insn ("nop", 0);
966 /* Output the delay slot insn first if any. */
967 if (dbr_sequence_length ())
968 print_slot (final_sequence);
970 this.reg = gen_rtx_REG (SImode, 13);
971 /* We must keep the stack aligned to 8-byte boundaries on SH5.
972 Fortunately, MACL is fixed and call-clobbered, and we never
973 need its value across jumps, so save r13 in it instead of in
976 output_asm_insn ("lds r13, macl", 0);
978 output_asm_insn ("mov.l r13,@-r15", 0);
979 output_asm_insn (jump, &this.lab);
981 output_asm_insn ("sts macl, r13", 0);
983 output_asm_insn ("mov.l @r15+,r13", 0);
985 if (far && flag_pic && TARGET_SH2)
987 braf_base_lab = gen_label_rtx ();
988 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
989 CODE_LABEL_NUMBER (braf_base_lab));
992 output_asm_insn (".align 2", 0);
993 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
998 this.lab = braf_base_lab;
999 output_asm_insn (".long %O2-%O0", &this.lab);
1002 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
1006 /* Local label counter, used for constants in the pool and inside
1007 pattern branches. */
1009 static int lf = 100;
1011 /* Output code for ordinary branches. */
1014 output_branch (logic, insn, operands)
1019 switch (get_attr_length (insn))
1022 /* This can happen if filling the delay slot has caused a forward
1023 branch to exceed its range (we could reverse it, but only
1024 when we know we won't overextend other branches; this should
1025 best be handled by relaxation).
1026 It can also happen when other condbranches hoist delay slot insn
1027 from their destination, thus leading to code size increase.
1028 But the branch will still be in the range -4092..+4098 bytes. */
1033 /* The call to print_slot will clobber the operands. */
1034 rtx op0 = operands[0];
1036 /* If the instruction in the delay slot is annulled (true), then
1037 there is no delay slot where we can put it now. The only safe
1038 place for it is after the label. final will do that by default. */
1041 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1043 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
1044 ASSEMBLER_DIALECT ? "/" : ".", label);
1045 print_slot (final_sequence);
1048 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
1050 output_asm_insn ("bra\t%l0", &op0);
1051 fprintf (asm_out_file, "\tnop\n");
1052 ASM_OUTPUT_INTERNAL_LABEL(asm_out_file, "LF", label);
1056 /* When relaxing, handle this like a short branch. The linker
1057 will fix it up if it still doesn't fit after relaxation. */
1059 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
1061 /* There should be no longer branches now - that would
1062 indicate that something has destroyed the branches set
1063 up in machine_dependent_reorg. */
1069 output_branchy_insn (code, template, insn, operands)
1071 const char *template;
1075 rtx next_insn = NEXT_INSN (insn);
1077 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
1079 rtx src = SET_SRC (PATTERN (next_insn));
1080 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
1082 /* Following branch not taken */
1083 operands[9] = gen_label_rtx ();
1084 emit_label_after (operands[9], next_insn);
1085 INSN_ADDRESSES_NEW (operands[9],
1086 INSN_ADDRESSES (INSN_UID (next_insn))
1087 + get_attr_length (next_insn));
1092 int offset = (branch_dest (next_insn)
1093 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
1094 if (offset >= -252 && offset <= 258)
1096 if (GET_CODE (src) == IF_THEN_ELSE)
1098 src = XEXP (src, 1);
1104 operands[9] = gen_label_rtx ();
1105 emit_label_after (operands[9], insn);
1106 INSN_ADDRESSES_NEW (operands[9],
1107 INSN_ADDRESSES (INSN_UID (insn))
1108 + get_attr_length (insn));
1113 output_ieee_ccmpeq (insn, operands)
1114 rtx insn, *operands;
1116 return output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
1119 /* Output to FILE the start of the assembler file. */
1122 output_file_start (file)
1125 output_file_directive (file, main_input_filename);
1127 /* Switch to the data section so that the coffsem symbol
1128 isn't in the text section. */
1131 if (TARGET_LITTLE_ENDIAN)
1132 fprintf (file, "\t.little\n");
1134 if (TARGET_SHCOMPACT)
1135 fprintf (file, "\t.mode\tSHcompact\n");
1136 else if (TARGET_SHMEDIA)
1137 fprintf (file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1138 TARGET_SHMEDIA64 ? 64 : 32);
1141 /* Actual number of instructions used to make a shift by N. */
1142 static const char ashiftrt_insns[] =
1143 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1145 /* Left shift and logical right shift are the same. */
1146 static const char shift_insns[] =
1147 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1149 /* Individual shift amounts needed to get the above length sequences.
1150 One bit right shifts clobber the T bit, so when possible, put one bit
1151 shifts in the middle of the sequence, so the ends are eligible for
1152 branch delay slots. */
1153 static const short shift_amounts[32][5] = {
1154 {0}, {1}, {2}, {2, 1},
1155 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1156 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1157 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1158 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1159 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1160 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1161 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1163 /* Likewise, but for shift amounts < 16, up to three highmost bits
1164 might be clobbered. This is typically used when combined with some
1165 kind of sign or zero extension. */
1167 static const char ext_shift_insns[] =
1168 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1170 static const short ext_shift_amounts[32][4] = {
1171 {0}, {1}, {2}, {2, 1},
1172 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1173 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1174 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1175 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1176 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1177 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1178 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1180 /* Assuming we have a value that has been sign-extended by at least one bit,
1181 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1182 to shift it by N without data loss, and quicker than by other means? */
1183 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1185 /* This is used in length attributes in sh.md to help compute the length
1186 of arbitrary constant shift instructions. */
1189 shift_insns_rtx (insn)
1192 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1193 int shift_count = INTVAL (XEXP (set_src, 1));
1194 enum rtx_code shift_code = GET_CODE (set_src);
1199 return ashiftrt_insns[shift_count];
1202 return shift_insns[shift_count];
1208 /* Return the cost of a shift. */
1219 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
1221 if (GET_MODE (x) == DImode
1222 && GET_CODE (XEXP (x, 1)) == CONST_INT
1223 && INTVAL (XEXP (x, 1)) == 1)
1226 /* Everything else is invalid, because there is no pattern for it. */
1229 /* If shift by a non constant, then this will be expensive. */
1230 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1231 return SH_DYNAMIC_SHIFT_COST;
1233 value = INTVAL (XEXP (x, 1));
1235 /* Otherwise, return the true cost in instructions. */
1236 if (GET_CODE (x) == ASHIFTRT)
1238 int cost = ashiftrt_insns[value];
1239 /* If SH3, then we put the constant in a reg and use shad. */
1240 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
1241 cost = 1 + SH_DYNAMIC_SHIFT_COST;
1245 return shift_insns[value];
1248 /* Return the cost of an AND operation. */
1256 /* Anding with a register is a single cycle and instruction. */
1257 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1260 i = INTVAL (XEXP (x, 1));
1264 if ((GET_CODE (XEXP (x, 1)) == CONST_INT
1265 && CONST_OK_FOR_J (INTVAL (XEXP (x, 1))))
1266 || EXTRA_CONSTRAINT_S (XEXP (x, 1)))
1272 /* These constants are single cycle extu.[bw] instructions. */
1273 if (i == 0xff || i == 0xffff)
1275 /* Constants that can be used in an and immediate instruction is a single
1276 cycle, but this requires r0, so make it a little more expensive. */
1277 if (CONST_OK_FOR_L (i))
1279 /* Constants that can be loaded with a mov immediate and an and.
1280 This case is probably unnecessary. */
1281 if (CONST_OK_FOR_I (i))
1283 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1284 This case is probably unnecessary. */
1288 /* Return the cost of an addition or a subtraction. */
1294 /* Adding a register is a single cycle insn. */
1295 if (GET_CODE (XEXP (x, 1)) == REG
1296 || GET_CODE (XEXP (x, 1)) == SUBREG)
1299 /* Likewise for small constants. */
1300 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1301 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
1305 switch (GET_CODE (XEXP (x, 1)))
1310 return TARGET_SHMEDIA64 ? 5 : 3;
1313 if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1))))
1315 else if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1)) >> 16))
1317 else if (CONST_OK_FOR_J ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
1325 /* Any other constant requires a 2 cycle pc-relative load plus an
1330 /* Return the cost of a multiply. */
1333 rtx x ATTRIBUTE_UNUSED;
1340 /* We have a mul insn, so we can never take more than the mul and the
1341 read of the mac reg, but count more because of the latency and extra
1343 if (TARGET_SMALLCODE)
1348 /* If we're aiming at small code, then just count the number of
1349 insns in a multiply call sequence. */
1350 if (TARGET_SMALLCODE)
1353 /* Otherwise count all the insns in the routine we'd be calling too. */
1357 /* Code to expand a shift. */
1360 gen_ashift (type, n, reg)
1365 /* Negative values here come from the shift_amounts array. */
1378 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
1382 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
1384 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
1387 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
1392 /* Same for HImode */
1395 gen_ashift_hi (type, n, reg)
1400 /* Negative values here come from the shift_amounts array. */
1414 /* We don't have HImode right shift operations because using the
1415 ordinary 32 bit shift instructions for that doesn't generate proper
1416 zero/sign extension.
1417 gen_ashift_hi is only called in contexts where we know that the
1418 sign extension works out correctly. */
1421 if (GET_CODE (reg) == SUBREG)
1423 offset = SUBREG_BYTE (reg);
1424 reg = SUBREG_REG (reg);
1426 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
1430 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
1435 /* Output RTL to split a constant shift into its component SH constant
1436 shift instructions. */
1439 gen_shifty_op (code, operands)
1443 int value = INTVAL (operands[2]);
1446 /* Truncate the shift count in case it is out of bounds. */
1447 value = value & 0x1f;
1451 if (code == LSHIFTRT)
1453 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1454 emit_insn (gen_movt (operands[0]));
1457 else if (code == ASHIFT)
1459 /* There is a two instruction sequence for 31 bit left shifts,
1460 but it requires r0. */
1461 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
1463 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
1464 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1469 else if (value == 0)
1471 /* This can happen when not optimizing. We must output something here
1472 to prevent the compiler from aborting in final.c after the try_split
1474 emit_insn (gen_nop ());
1478 max = shift_insns[value];
1479 for (i = 0; i < max; i++)
1480 gen_ashift (code, shift_amounts[value][i], operands[0]);
1483 /* Same as above, but optimized for values where the topmost bits don't
1487 gen_shifty_hi_op (code, operands)
1491 int value = INTVAL (operands[2]);
1493 void (*gen_fun) PARAMS ((int, int, rtx));
1495 /* This operation is used by and_shl for SImode values with a few
1496 high bits known to be cleared. */
1500 emit_insn (gen_nop ());
1504 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
1507 max = ext_shift_insns[value];
1508 for (i = 0; i < max; i++)
1509 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1512 /* When shifting right, emit the shifts in reverse order, so that
1513 solitary negative values come first. */
1514 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
1515 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1518 /* Output RTL for an arithmetic right shift. */
1520 /* ??? Rewrite to use super-optimizer sequences. */
1523 expand_ashiftrt (operands)
1534 if (GET_CODE (operands[2]) != CONST_INT)
1536 rtx count = copy_to_mode_reg (SImode, operands[2]);
1537 emit_insn (gen_negsi2 (count, count));
1538 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1541 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
1542 > 1 + SH_DYNAMIC_SHIFT_COST)
1545 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
1546 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1550 if (GET_CODE (operands[2]) != CONST_INT)
1553 value = INTVAL (operands[2]) & 31;
1557 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
1560 else if (value >= 16 && value <= 19)
1562 wrk = gen_reg_rtx (SImode);
1563 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
1566 gen_ashift (ASHIFTRT, 1, wrk);
1567 emit_move_insn (operands[0], wrk);
1570 /* Expand a short sequence inline, longer call a magic routine. */
1571 else if (value <= 5)
1573 wrk = gen_reg_rtx (SImode);
1574 emit_move_insn (wrk, operands[1]);
1576 gen_ashift (ASHIFTRT, 1, wrk);
1577 emit_move_insn (operands[0], wrk);
1581 wrk = gen_reg_rtx (Pmode);
1583 /* Load the value into an arg reg and call a helper. */
1584 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1585 sprintf (func, "__ashiftrt_r4_%d", value);
1586 func_name = get_identifier (func);
1587 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (func_name));
1588 emit_move_insn (wrk, sym);
1589 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1590 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
1595 sh_dynamicalize_shift_p (count)
1598 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
1601 /* Try to find a good way to implement the combiner pattern
1602 [(set (match_operand:SI 0 "register_operand" "r")
1603 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1604 (match_operand:SI 2 "const_int_operand" "n"))
1605 (match_operand:SI 3 "const_int_operand" "n"))) .
1606 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1607 return 0 for simple right / left or left/right shift combination.
1608 return 1 for a combination of shifts with zero_extend.
1609 return 2 for a combination of shifts with an AND that needs r0.
1610 return 3 for a combination of shifts with an AND that needs an extra
1611 scratch register, when the three highmost bits of the AND mask are clear.
1612 return 4 for a combination of shifts with an AND that needs an extra
1613 scratch register, when any of the three highmost bits of the AND mask
1615 If ATTRP is set, store an initial right shift width in ATTRP[0],
1616 and the instruction length in ATTRP[1] . These values are not valid
1618 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1619 shift_amounts for the last shift value that is to be used before the
1622 shl_and_kind (left_rtx, mask_rtx, attrp)
1623 rtx left_rtx, mask_rtx;
1626 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
1627 int left = INTVAL (left_rtx), right;
1629 int cost, best_cost = 10000;
1630 int best_right = 0, best_len = 0;
1634 if (left < 0 || left > 31)
1636 if (GET_CODE (mask_rtx) == CONST_INT)
1637 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
1639 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
1640 /* Can this be expressed as a right shift / left shift pair ? */
1641 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
1642 right = exact_log2 (lsb);
1643 mask2 = ~(mask + lsb - 1);
1644 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
1645 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1647 best_cost = shift_insns[right] + shift_insns[right + left];
1648 /* mask has no trailing zeroes <==> ! right */
1649 else if (! right && mask2 == ~(lsb2 - 1))
1651 int late_right = exact_log2 (lsb2);
1652 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
1654 /* Try to use zero extend */
1655 if (mask2 == ~(lsb2 - 1))
1659 for (width = 8; width <= 16; width += 8)
1661 /* Can we zero-extend right away? */
1662 if (lsb2 == (unsigned HOST_WIDE_INT)1 << width)
1665 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
1666 if (cost < best_cost)
1677 /* ??? Could try to put zero extend into initial right shift,
1678 or even shift a bit left before the right shift. */
1679 /* Determine value of first part of left shift, to get to the
1680 zero extend cut-off point. */
1681 first = width - exact_log2 (lsb2) + right;
1682 if (first >= 0 && right + left - first >= 0)
1684 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
1685 + ext_shift_insns[right + left - first];
1686 if (cost < best_cost)
1698 /* Try to use r0 AND pattern */
1699 for (i = 0; i <= 2; i++)
1703 if (! CONST_OK_FOR_L (mask >> i))
1705 cost = (i != 0) + 2 + ext_shift_insns[left + i];
1706 if (cost < best_cost)
1711 best_len = cost - 1;
1714 /* Try to use a scratch register to hold the AND operand. */
1715 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT)3 << 30)) == 0;
1716 for (i = 0; i <= 2; i++)
1720 cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3)
1721 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
1722 if (cost < best_cost)
1727 best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i);
1733 attrp[0] = best_right;
1734 attrp[1] = best_len;
1739 /* This is used in length attributes of the unnamed instructions
1740 corresponding to shl_and_kind return values of 1 and 2. */
1742 shl_and_length (insn)
1745 rtx set_src, left_rtx, mask_rtx;
1748 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1749 left_rtx = XEXP (XEXP (set_src, 0), 1);
1750 mask_rtx = XEXP (set_src, 1);
1751 shl_and_kind (left_rtx, mask_rtx, attributes);
1752 return attributes[1];
1755 /* This is used in length attribute of the and_shl_scratch instruction. */
1758 shl_and_scr_length (insn)
1761 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1762 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
1763 rtx op = XEXP (set_src, 0);
1764 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
1765 op = XEXP (XEXP (op, 0), 0);
1766 return len + shift_insns[INTVAL (XEXP (op, 1))];
1769 /* Generating rtl? */
1770 extern int rtx_equal_function_value_matters;
1772 /* Generate rtl for instructions for which shl_and_kind advised a particular
1773 method of generating them, i.e. returned zero. */
1776 gen_shl_and (dest, left_rtx, mask_rtx, source)
1777 rtx dest, left_rtx, mask_rtx, source;
1780 unsigned HOST_WIDE_INT mask;
1781 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
1782 int right, total_shift;
1783 void (*shift_gen_fun) PARAMS ((int, rtx*)) = gen_shifty_hi_op;
1785 right = attributes[0];
1786 total_shift = INTVAL (left_rtx) + right;
1787 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
1794 int first = attributes[2];
1799 emit_insn ((mask << right) <= 0xff
1800 ? gen_zero_extendqisi2(dest,
1801 gen_lowpart (QImode, source))
1802 : gen_zero_extendhisi2(dest,
1803 gen_lowpart (HImode, source)));
1807 emit_insn (gen_movsi (dest, source));
1811 operands[2] = GEN_INT (right);
1812 gen_shifty_hi_op (LSHIFTRT, operands);
1816 operands[2] = GEN_INT (first);
1817 gen_shifty_hi_op (ASHIFT, operands);
1818 total_shift -= first;
1822 emit_insn (mask <= 0xff
1823 ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
1824 : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
1825 if (total_shift > 0)
1827 operands[2] = GEN_INT (total_shift);
1828 gen_shifty_hi_op (ASHIFT, operands);
1833 shift_gen_fun = gen_shifty_op;
1835 /* If the topmost bit that matters is set, set the topmost bits
1836 that don't matter. This way, we might be able to get a shorter
1838 if (mask & ((HOST_WIDE_INT)1 << (31 - total_shift)))
1839 mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
1841 /* Don't expand fine-grained when combining, because that will
1842 make the pattern fail. */
1843 if (rtx_equal_function_value_matters
1844 || reload_in_progress || reload_completed)
1848 /* Cases 3 and 4 should be handled by this split
1849 only while combining */
1854 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
1857 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
1862 operands[2] = GEN_INT (total_shift);
1863 shift_gen_fun (ASHIFT, operands);
1870 if (kind != 4 && total_shift < 16)
1872 neg = -ext_shift_amounts[total_shift][1];
1874 neg -= ext_shift_amounts[total_shift][2];
1878 emit_insn (gen_and_shl_scratch (dest, source,
1881 GEN_INT (total_shift + neg),
1883 emit_insn (gen_movsi (dest, dest));
1890 /* Try to find a good way to implement the combiner pattern
1891 [(set (match_operand:SI 0 "register_operand" "=r")
1892 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1893 (match_operand:SI 2 "const_int_operand" "n")
1894 (match_operand:SI 3 "const_int_operand" "n")
1896 (clobber (reg:SI T_REG))]
1897 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
1898 return 0 for simple left / right shift combination.
1899 return 1 for left shift / 8 bit sign extend / left shift.
1900 return 2 for left shift / 16 bit sign extend / left shift.
1901 return 3 for left shift / 8 bit sign extend / shift / sign extend.
1902 return 4 for left shift / 16 bit sign extend / shift / sign extend.
1903 return 5 for left shift / 16 bit sign extend / right shift
1904 return 6 for < 8 bit sign extend / left shift.
1905 return 7 for < 8 bit sign extend / left shift / single right shift.
1906 If COSTP is nonzero, assign the calculated cost to *COSTP. */
1909 shl_sext_kind (left_rtx, size_rtx, costp)
1910 rtx left_rtx, size_rtx;
1913 int left, size, insize, ext;
1914 int cost, best_cost;
1917 left = INTVAL (left_rtx);
1918 size = INTVAL (size_rtx);
1919 insize = size - left;
1922 /* Default to left / right shift. */
1924 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
1927 /* 16 bit shift / sign extend / 16 bit shift */
1928 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
1929 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
1930 below, by alternative 3 or something even better. */
1931 if (cost < best_cost)
1937 /* Try a plain sign extend between two shifts. */
1938 for (ext = 16; ext >= insize; ext -= 8)
1942 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
1943 if (cost < best_cost)
1945 kind = ext / (unsigned) 8;
1949 /* Check if we can do a sloppy shift with a final signed shift
1950 restoring the sign. */
1951 if (EXT_SHIFT_SIGNED (size - ext))
1952 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
1953 /* If not, maybe it's still cheaper to do the second shift sloppy,
1954 and do a final sign extend? */
1955 else if (size <= 16)
1956 cost = ext_shift_insns[ext - insize] + 1
1957 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
1960 if (cost < best_cost)
1962 kind = ext / (unsigned) 8 + 2;
1966 /* Check if we can sign extend in r0 */
1969 cost = 3 + shift_insns[left];
1970 if (cost < best_cost)
1975 /* Try the same with a final signed shift. */
1978 cost = 3 + ext_shift_insns[left + 1] + 1;
1979 if (cost < best_cost)
1988 /* Try to use a dynamic shift. */
1989 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
1990 if (cost < best_cost)
2001 /* Function to be used in the length attribute of the instructions
2002 implementing this pattern. */
2005 shl_sext_length (insn)
2008 rtx set_src, left_rtx, size_rtx;
2011 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2012 left_rtx = XEXP (XEXP (set_src, 0), 1);
2013 size_rtx = XEXP (set_src, 1);
2014 shl_sext_kind (left_rtx, size_rtx, &cost);
2018 /* Generate rtl for this pattern */
2021 gen_shl_sext (dest, left_rtx, size_rtx, source)
2022 rtx dest, left_rtx, size_rtx, source;
2025 int left, size, insize, cost;
2028 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
2029 left = INTVAL (left_rtx);
2030 size = INTVAL (size_rtx);
2031 insize = size - left;
2039 int ext = kind & 1 ? 8 : 16;
2040 int shift2 = size - ext;
2042 /* Don't expand fine-grained when combining, because that will
2043 make the pattern fail. */
2044 if (! rtx_equal_function_value_matters
2045 && ! reload_in_progress && ! reload_completed)
2047 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2048 emit_insn (gen_movsi (dest, source));
2052 emit_insn (gen_movsi (dest, source));
2056 operands[2] = GEN_INT (ext - insize);
2057 gen_shifty_hi_op (ASHIFT, operands);
2060 ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
2061 : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
2066 operands[2] = GEN_INT (shift2);
2067 gen_shifty_op (ASHIFT, operands);
2074 if (EXT_SHIFT_SIGNED (shift2))
2076 operands[2] = GEN_INT (shift2 + 1);
2077 gen_shifty_op (ASHIFT, operands);
2078 operands[2] = GEN_INT (1);
2079 gen_shifty_op (ASHIFTRT, operands);
2082 operands[2] = GEN_INT (shift2);
2083 gen_shifty_hi_op (ASHIFT, operands);
2087 operands[2] = GEN_INT (-shift2);
2088 gen_shifty_hi_op (LSHIFTRT, operands);
2090 emit_insn (size <= 8
2091 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
2092 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2099 if (! rtx_equal_function_value_matters
2100 && ! reload_in_progress && ! reload_completed)
2101 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2105 operands[2] = GEN_INT (16 - insize);
2106 gen_shifty_hi_op (ASHIFT, operands);
2107 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2109 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2111 gen_ashift (ASHIFTRT, 1, dest);
2116 /* Don't expand fine-grained when combining, because that will
2117 make the pattern fail. */
2118 if (! rtx_equal_function_value_matters
2119 && ! reload_in_progress && ! reload_completed)
2121 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2122 emit_insn (gen_movsi (dest, source));
2125 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
2126 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
2127 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
2129 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
2130 gen_shifty_op (ASHIFT, operands);
2132 emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
2140 /* Prefix a symbol_ref name with "datalabel". */
2143 gen_datalabel_ref (sym)
2146 if (GET_CODE (sym) == LABEL_REF)
2147 return gen_rtx_CONST (GET_MODE (sym),
2148 gen_rtx_UNSPEC (GET_MODE (sym),
2152 if (GET_CODE (sym) != SYMBOL_REF)
2155 XSTR (sym, 0) = concat (SH_DATALABEL_ENCODING, XSTR (sym, 0), NULL);
2161 /* The SH cannot load a large constant into a register, constants have to
2162 come from a pc relative load. The reference of a pc relative load
2163 instruction must be less than 1k infront of the instruction. This
2164 means that we often have to dump a constant inside a function, and
2165 generate code to branch around it.
2167 It is important to minimize this, since the branches will slow things
2168 down and make things bigger.
2170 Worst case code looks like:
2188 We fix this by performing a scan before scheduling, which notices which
2189 instructions need to have their operands fetched from the constant table
2190 and builds the table.
2194 scan, find an instruction which needs a pcrel move. Look forward, find the
2195 last barrier which is within MAX_COUNT bytes of the requirement.
2196 If there isn't one, make one. Process all the instructions between
2197 the find and the barrier.
2199 In the above example, we can tell that L3 is within 1k of L1, so
2200 the first move can be shrunk from the 3 insn+constant sequence into
2201 just 1 insn, and the constant moved to L3 to make:
2212 Then the second move becomes the target for the shortening process. */
2216 rtx value; /* Value in table. */
2217 rtx label; /* Label of value. */
2218 rtx wend; /* End of window. */
2219 enum machine_mode mode; /* Mode of value. */
2222 /* The maximum number of constants that can fit into one pool, since
2223 the pc relative range is 0...1020 bytes and constants are at least 4
2226 #define MAX_POOL_SIZE (1020/4)
2227 static pool_node pool_vector[MAX_POOL_SIZE];
2228 static int pool_size;
2229 static rtx pool_window_label;
2230 static int pool_window_last;
2232 /* ??? If we need a constant in HImode which is the truncated value of a
2233 constant we need in SImode, we could combine the two entries thus saving
2234 two bytes. Is this common enough to be worth the effort of implementing
2237 /* ??? This stuff should be done at the same time that we shorten branches.
2238 As it is now, we must assume that all branches are the maximum size, and
2239 this causes us to almost always output constant pools sooner than
2242 /* Add a constant to the pool and return its label. */
2245 add_constant (x, mode, last_value)
2247 enum machine_mode mode;
2251 rtx lab, new, ref, newref;
2253 /* First see if we've already got it. */
2254 for (i = 0; i < pool_size; i++)
2256 if (x->code == pool_vector[i].value->code
2257 && mode == pool_vector[i].mode)
2259 if (x->code == CODE_LABEL)
2261 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
2264 if (rtx_equal_p (x, pool_vector[i].value))
2269 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
2271 new = gen_label_rtx ();
2272 LABEL_REFS (new) = pool_vector[i].label;
2273 pool_vector[i].label = lab = new;
2275 if (lab && pool_window_label)
2277 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2278 ref = pool_vector[pool_window_last].wend;
2279 LABEL_NEXTREF (newref) = ref;
2280 pool_vector[pool_window_last].wend = newref;
2283 pool_window_label = new;
2284 pool_window_last = i;
2290 /* Need a new one. */
2291 pool_vector[pool_size].value = x;
2292 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
2295 lab = gen_label_rtx ();
2296 pool_vector[pool_size].mode = mode;
2297 pool_vector[pool_size].label = lab;
2298 pool_vector[pool_size].wend = NULL_RTX;
2299 if (lab && pool_window_label)
2301 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2302 ref = pool_vector[pool_window_last].wend;
2303 LABEL_NEXTREF (newref) = ref;
2304 pool_vector[pool_window_last].wend = newref;
2307 pool_window_label = lab;
2308 pool_window_last = pool_size;
2313 /* Output the literal table. */
2324 /* Do two passes, first time dump out the HI sized constants. */
2326 for (i = 0; i < pool_size; i++)
2328 pool_node *p = &pool_vector[i];
2330 if (p->mode == HImode)
2334 scan = emit_insn_after (gen_align_2 (), scan);
2337 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2338 scan = emit_label_after (lab, scan);
2339 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
2341 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2343 lab = XEXP (ref, 0);
2344 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2347 else if (p->mode == DImode || p->mode == DFmode)
2353 if (TARGET_SHCOMPACT && have_di)
2355 rtx align_insn = NULL_RTX;
2357 scan = emit_label_after (gen_label_rtx (), scan);
2358 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2361 for (i = 0; i < pool_size; i++)
2363 pool_node *p = &pool_vector[i];
2373 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2374 emit_label_before (lab, align_insn);
2375 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
2377 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2379 lab = XEXP (ref, 0);
2380 emit_insn_before (gen_consttable_window_end (lab),
2383 delete_insn (align_insn);
2384 align_insn = NULL_RTX;
2389 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2390 scan = emit_label_after (lab, scan);
2391 scan = emit_insn_after (gen_consttable_4 (p->value,
2393 need_align = ! need_align;
2400 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2404 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2405 scan = emit_label_after (lab, scan);
2406 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2414 if (p->mode != HImode)
2416 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2418 lab = XEXP (ref, 0);
2419 scan = emit_insn_after (gen_consttable_window_end (lab),
2428 for (i = 0; i < pool_size; i++)
2430 pool_node *p = &pool_vector[i];
2441 scan = emit_label_after (gen_label_rtx (), scan);
2442 scan = emit_insn_after (gen_align_4 (), scan);
2444 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2445 scan = emit_label_after (lab, scan);
2446 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
2454 scan = emit_label_after (gen_label_rtx (), scan);
2455 scan = emit_insn_after (gen_align_4 (), scan);
2457 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2458 scan = emit_label_after (lab, scan);
2459 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2467 if (p->mode != HImode)
2469 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2471 lab = XEXP (ref, 0);
2472 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2477 scan = emit_insn_after (gen_consttable_end (), scan);
2478 scan = emit_barrier_after (scan);
2480 pool_window_label = NULL_RTX;
2481 pool_window_last = 0;
2484 /* Return non-zero if constant would be an ok source for a
2485 mov.w instead of a mov.l. */
2491 return (GET_CODE (src) == CONST_INT
2492 && INTVAL (src) >= -32768
2493 && INTVAL (src) <= 32767);
2496 /* Non-zero if the insn is a move instruction which needs to be fixed. */
2498 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2499 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
2500 need to fix it if the input value is CONST_OK_FOR_I. */
2506 if (GET_CODE (insn) == INSN)
2508 rtx pat = PATTERN (insn);
2509 if (GET_CODE (pat) == PARALLEL)
2510 pat = XVECEXP (pat, 0, 0);
2511 if (GET_CODE (pat) == SET
2512 /* We can load any 8 bit value if we don't care what the high
2513 order bits end up as. */
2514 && GET_MODE (SET_DEST (pat)) != QImode
2515 && (CONSTANT_P (SET_SRC (pat))
2516 /* Match mova_const. */
2517 || (GET_CODE (SET_SRC (pat)) == UNSPEC
2518 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
2519 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
2521 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
2522 && (fp_zero_operand (SET_SRC (pat))
2523 || fp_one_operand (SET_SRC (pat)))
2524 /* ??? If this is a -m4 or -m4-single compilation, in general
2525 we don't know the current setting of fpscr, so disable fldi.
2526 There is an exception if this was a register-register move
2527 before reload - and hence it was ascertained that we have
2528 single precision setting - and in a post-reload optimization
2529 we changed this to do a constant load. In that case
2530 we don't have an r0 clobber, hence we must use fldi. */
2531 && (! TARGET_SH4 || TARGET_FMOVD
2532 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
2534 && GET_CODE (SET_DEST (pat)) == REG
2535 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
2536 && (GET_CODE (SET_SRC (pat)) != CONST_INT
2537 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat)))))
2548 return (GET_CODE (insn) == INSN
2549 && GET_CODE (PATTERN (insn)) == SET
2550 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
2551 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
2552 /* Don't match mova_const. */
2553 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn)), 0, 0)) == LABEL_REF);
2556 /* Find the last barrier from insn FROM which is close enough to hold the
2557 constant pool. If we can't find one, then create one near the end of
2561 find_barrier (num_mova, mova, from)
2572 int leading_mova = num_mova;
2573 rtx barrier_before_mova, found_barrier = 0, good_barrier = 0;
2577 /* For HImode: range is 510, add 4 because pc counts from address of
2578 second instruction after this one, subtract 2 for the jump instruction
2579 that we may need to emit before the table, subtract 2 for the instruction
2580 that fills the jump delay slot (in very rare cases, reorg will take an
2581 instruction from after the constant pool or will leave the delay slot
2582 empty). This gives 510.
2583 For SImode: range is 1020, add 4 because pc counts from address of
2584 second instruction after this one, subtract 2 in case pc is 2 byte
2585 aligned, subtract 2 for the jump instruction that we may need to emit
2586 before the table, subtract 2 for the instruction that fills the jump
2587 delay slot. This gives 1018. */
2589 /* The branch will always be shortened now that the reference address for
2590 forward branches is the successor address, thus we need no longer make
2591 adjustments to the [sh]i_limit for -O0. */
2596 while (from && count_si < si_limit && count_hi < hi_limit)
2598 int inc = get_attr_length (from);
2601 if (GET_CODE (from) == CODE_LABEL)
2604 new_align = 1 << label_to_alignment (from);
2605 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
2606 new_align = 1 << barrier_align (from);
2612 if (GET_CODE (from) == BARRIER)
2615 found_barrier = from;
2617 /* If we are at the end of the function, or in front of an alignment
2618 instruction, we need not insert an extra alignment. We prefer
2619 this kind of barrier. */
2620 if (barrier_align (from) > 2)
2621 good_barrier = from;
2624 if (broken_move (from))
2627 enum machine_mode mode;
2629 pat = PATTERN (from);
2630 if (GET_CODE (pat) == PARALLEL)
2631 pat = XVECEXP (pat, 0, 0);
2632 src = SET_SRC (pat);
2633 dst = SET_DEST (pat);
2634 mode = GET_MODE (dst);
2636 /* We must explicitly check the mode, because sometimes the
2637 front end will generate code to load unsigned constants into
2638 HImode targets without properly sign extending them. */
2640 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
2643 /* We put the short constants before the long constants, so
2644 we must count the length of short constants in the range
2645 for the long constants. */
2646 /* ??? This isn't optimal, but is easy to do. */
2651 /* We dump DF/DI constants before SF/SI ones, because
2652 the limit is the same, but the alignment requirements
2653 are higher. We may waste up to 4 additional bytes
2654 for alignment, and the DF/DI constant may have
2655 another SF/SI constant placed before it. */
2656 if (TARGET_SHCOMPACT
2658 && (mode == DFmode || mode == DImode))
2663 while (si_align > 2 && found_si + si_align - 2 > count_si)
2665 if (found_si > count_si)
2666 count_si = found_si;
2667 found_si += GET_MODE_SIZE (mode);
2669 si_limit -= GET_MODE_SIZE (mode);
2672 /* See the code in machine_dependent_reorg, which has a similar if
2673 statement that generates a new mova insn in many cases. */
2674 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
2684 barrier_before_mova = good_barrier ? good_barrier : found_barrier;
2686 if (found_si > count_si)
2687 count_si = found_si;
2689 else if (GET_CODE (from) == JUMP_INSN
2690 && (GET_CODE (PATTERN (from)) == ADDR_VEC
2691 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
2695 if (barrier_align (next_real_insn (from)) == CACHE_LOG)
2697 /* We have just passed the barrier in front of the
2698 ADDR_DIFF_VEC, which is stored in found_barrier. Since
2699 the ADDR_DIFF_VEC is accessed as data, just like our pool
2700 constants, this is a good opportunity to accommodate what
2701 we have gathered so far.
2702 If we waited any longer, we could end up at a barrier in
2703 front of code, which gives worse cache usage for separated
2704 instruction / data caches. */
2705 good_barrier = found_barrier;
2710 rtx body = PATTERN (from);
2711 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
2714 /* For the SH1, we generate alignments even after jumps-around-jumps. */
2715 else if (GET_CODE (from) == JUMP_INSN
2717 && ! TARGET_SMALLCODE)
2723 if (new_align > si_align)
2725 si_limit -= (count_si - 1) & (new_align - si_align);
2726 si_align = new_align;
2728 count_si = (count_si + new_align - 1) & -new_align;
2733 if (new_align > hi_align)
2735 hi_limit -= (count_hi - 1) & (new_align - hi_align);
2736 hi_align = new_align;
2738 count_hi = (count_hi + new_align - 1) & -new_align;
2740 from = NEXT_INSN (from);
2747 /* Try as we might, the leading mova is out of range. Change
2748 it into a load (which will become a pcload) and retry. */
2749 SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
2750 INSN_CODE (mova) = -1;
2751 return find_barrier (0, 0, mova);
2755 /* Insert the constant pool table before the mova instruction,
2756 to prevent the mova label reference from going out of range. */
2758 good_barrier = found_barrier = barrier_before_mova;
2764 if (good_barrier && next_real_insn (found_barrier))
2765 found_barrier = good_barrier;
2769 /* We didn't find a barrier in time to dump our stuff,
2770 so we'll make one. */
2771 rtx label = gen_label_rtx ();
2773 /* If we exceeded the range, then we must back up over the last
2774 instruction we looked at. Otherwise, we just need to undo the
2775 NEXT_INSN at the end of the loop. */
2776 if (count_hi > hi_limit || count_si > si_limit)
2777 from = PREV_INSN (PREV_INSN (from));
2779 from = PREV_INSN (from);
2781 /* Walk back to be just before any jump or label.
2782 Putting it before a label reduces the number of times the branch
2783 around the constant pool table will be hit. Putting it before
2784 a jump makes it more likely that the bra delay slot will be
2786 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
2787 || GET_CODE (from) == CODE_LABEL)
2788 from = PREV_INSN (from);
2790 from = emit_jump_insn_after (gen_jump (label), from);
2791 JUMP_LABEL (from) = label;
2792 LABEL_NUSES (label) = 1;
2793 found_barrier = emit_barrier_after (from);
2794 emit_label_after (label, found_barrier);
2797 return found_barrier;
2800 /* If the instruction INSN is implemented by a special function, and we can
2801 positively find the register that is used to call the sfunc, and this
2802 register is not used anywhere else in this instruction - except as the
2803 destination of a set, return this register; else, return 0. */
2805 sfunc_uses_reg (insn)
2809 rtx pattern, part, reg_part, reg;
2811 if (GET_CODE (insn) != INSN)
2813 pattern = PATTERN (insn);
2814 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
2817 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
2819 part = XVECEXP (pattern, 0, i);
2820 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
2825 reg = XEXP (reg_part, 0);
2826 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
2828 part = XVECEXP (pattern, 0, i);
2829 if (part == reg_part || GET_CODE (part) == CLOBBER)
2831 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
2832 && GET_CODE (SET_DEST (part)) == REG)
2833 ? SET_SRC (part) : part)))
2839 /* See if the only way in which INSN uses REG is by calling it, or by
2840 setting it while calling it. Set *SET to a SET rtx if the register
2844 noncall_uses_reg (reg, insn, set)
2853 reg2 = sfunc_uses_reg (insn);
2854 if (reg2 && REGNO (reg2) == REGNO (reg))
2856 pattern = single_set (insn);
2858 && GET_CODE (SET_DEST (pattern)) == REG
2859 && REGNO (reg) == REGNO (SET_DEST (pattern)))
2863 if (GET_CODE (insn) != CALL_INSN)
2865 /* We don't use rtx_equal_p because we don't care if the mode is
2867 pattern = single_set (insn);
2869 && GET_CODE (SET_DEST (pattern)) == REG
2870 && REGNO (reg) == REGNO (SET_DEST (pattern)))
2876 par = PATTERN (insn);
2877 if (GET_CODE (par) == PARALLEL)
2878 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
2880 part = XVECEXP (par, 0, i);
2881 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
2884 return reg_mentioned_p (reg, SET_SRC (pattern));
2890 pattern = PATTERN (insn);
2892 if (GET_CODE (pattern) == PARALLEL)
2896 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
2897 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
2899 pattern = XVECEXP (pattern, 0, 0);
2902 if (GET_CODE (pattern) == SET)
2904 if (reg_mentioned_p (reg, SET_DEST (pattern)))
2906 /* We don't use rtx_equal_p, because we don't care if the
2907 mode is different. */
2908 if (GET_CODE (SET_DEST (pattern)) != REG
2909 || REGNO (reg) != REGNO (SET_DEST (pattern)))
2915 pattern = SET_SRC (pattern);
2918 if (GET_CODE (pattern) != CALL
2919 || GET_CODE (XEXP (pattern, 0)) != MEM
2920 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
2926 /* Given a X, a pattern of an insn or a part of it, return a mask of used
2927 general registers. Bits 0..15 mean that the respective registers
2928 are used as inputs in the instruction. Bits 16..31 mean that the
2929 registers 0..15, respectively, are used as outputs, or are clobbered.
2930 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
2932 regs_used (x, is_dest)
2941 code = GET_CODE (x);
2946 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
2947 << (REGNO (x) + is_dest));
2951 rtx y = SUBREG_REG (x);
2953 if (GET_CODE (y) != REG)
2956 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
2958 subreg_regno_offset (REGNO (y),
2961 GET_MODE (x)) + is_dest));
2965 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
2967 /* If there was a return value, it must have been indicated with USE. */
2982 fmt = GET_RTX_FORMAT (code);
2984 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2989 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2990 used |= regs_used (XVECEXP (x, i, j), is_dest);
2992 else if (fmt[i] == 'e')
2993 used |= regs_used (XEXP (x, i), is_dest);
2998 /* Create an instruction that prevents redirection of a conditional branch
2999 to the destination of the JUMP with address ADDR.
3000 If the branch needs to be implemented as an indirect jump, try to find
3001 a scratch register for it.
3002 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3003 If any preceding insn that doesn't fit into a delay slot is good enough,
3004 pass 1. Pass 2 if a definite blocking insn is needed.
3005 -1 is used internally to avoid deep recursion.
3006 If a blocking instruction is made or recognized, return it. */
3009 gen_block_redirect (jump, addr, need_block)
3011 int addr, need_block;
3014 rtx prev = prev_nonnote_insn (jump);
3017 /* First, check if we already have an instruction that satisfies our need. */
3018 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
3020 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
3022 if (GET_CODE (PATTERN (prev)) == USE
3023 || GET_CODE (PATTERN (prev)) == CLOBBER
3024 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3026 else if ((need_block &= ~1) < 0)
3028 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
3031 /* We can't use JUMP_LABEL here because it might be undefined
3032 when not optimizing. */
3033 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
3034 /* If the branch is out of range, try to find a scratch register for it. */
3036 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3040 /* Don't look for the stack pointer as a scratch register,
3041 it would cause trouble if an interrupt occurred. */
3042 unsigned try = 0x7fff, used;
3043 int jump_left = flag_expensive_optimizations + 1;
3045 /* It is likely that the most recent eligible instruction is wanted for
3046 the delay slot. Therefore, find out which registers it uses, and
3047 try to avoid using them. */
3049 for (scan = jump; (scan = PREV_INSN (scan)); )
3053 if (INSN_DELETED_P (scan))
3055 code = GET_CODE (scan);
3056 if (code == CODE_LABEL || code == JUMP_INSN)
3059 && GET_CODE (PATTERN (scan)) != USE
3060 && GET_CODE (PATTERN (scan)) != CLOBBER
3061 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
3063 try &= ~regs_used (PATTERN (scan), 0);
3067 for (used = dead = 0, scan = JUMP_LABEL (jump);
3068 (scan = NEXT_INSN (scan)); )
3072 if (INSN_DELETED_P (scan))
3074 code = GET_CODE (scan);
3075 if (GET_RTX_CLASS (code) == 'i')
3077 used |= regs_used (PATTERN (scan), 0);
3078 if (code == CALL_INSN)
3079 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
3080 dead |= (used >> 16) & ~used;
3086 if (code == JUMP_INSN)
3088 if (jump_left-- && simplejump_p (scan))
3089 scan = JUMP_LABEL (scan);
3095 /* Mask out the stack pointer again, in case it was
3096 the only 'free' register we have found. */
3099 /* If the immediate destination is still in range, check for possible
3100 threading with a jump beyond the delay slot insn.
3101 Don't check if we are called recursively; the jump has been or will be
3102 checked in a different invocation then. */
3104 else if (optimize && need_block >= 0)
3106 rtx next = next_active_insn (next_active_insn (dest));
3107 if (next && GET_CODE (next) == JUMP_INSN
3108 && GET_CODE (PATTERN (next)) == SET
3109 && recog_memoized (next) == CODE_FOR_jump)
3111 dest = JUMP_LABEL (next);
3113 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3115 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
3121 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
3123 /* It would be nice if we could convert the jump into an indirect
3124 jump / far branch right now, and thus exposing all constituent
3125 instructions to further optimization. However, reorg uses
3126 simplejump_p to determine if there is an unconditional jump where
3127 it should try to schedule instructions from the target of the
3128 branch; simplejump_p fails for indirect jumps even if they have
3130 rtx insn = emit_insn_before (gen_indirect_jump_scratch
3131 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
3133 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
3136 else if (need_block)
3137 /* We can't use JUMP_LABEL here because it might be undefined
3138 when not optimizing. */
3139 return emit_insn_before (gen_block_branch_redirect
3140 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
3145 #define CONDJUMP_MIN -252
3146 #define CONDJUMP_MAX 262
3149 /* A label (to be placed) in front of the jump
3150 that jumps to our ultimate destination. */
3152 /* Where we are going to insert it if we cannot move the jump any farther,
3153 or the jump itself if we have picked up an existing jump. */
3155 /* The ultimate destination. */
3157 struct far_branch *prev;
3158 /* If the branch has already been created, its address;
3159 else the address of its first prospective user. */
3163 static void gen_far_branch PARAMS ((struct far_branch *));
3164 enum mdep_reorg_phase_e mdep_reorg_phase;
3167 struct far_branch *bp;
3169 rtx insn = bp->insert_place;
3171 rtx label = gen_label_rtx ();
3173 emit_label_after (label, insn);
3176 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
3177 LABEL_NUSES (bp->far_label)++;
3180 jump = emit_jump_insn_after (gen_return (), insn);
3181 /* Emit a barrier so that reorg knows that any following instructions
3182 are not reachable via a fall-through path.
3183 But don't do this when not optimizing, since we wouldn't supress the
3184 alignment for the barrier then, and could end up with out-of-range
3185 pc-relative loads. */
3187 emit_barrier_after (jump);
3188 emit_label_after (bp->near_label, insn);
3189 JUMP_LABEL (jump) = bp->far_label;
3190 if (! invert_jump (insn, label, 1))
3192 /* Prevent reorg from undoing our splits. */
3193 gen_block_redirect (jump, bp->address += 2, 2);
3196 /* Fix up ADDR_DIFF_VECs. */
3198 fixup_addr_diff_vecs (first)
3203 for (insn = first; insn; insn = NEXT_INSN (insn))
3205 rtx vec_lab, pat, prev, prevpat, x, braf_label;
3207 if (GET_CODE (insn) != JUMP_INSN
3208 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
3210 pat = PATTERN (insn);
3211 vec_lab = XEXP (XEXP (pat, 0), 0);
3213 /* Search the matching casesi_jump_2. */
3214 for (prev = vec_lab; ; prev = PREV_INSN (prev))
3216 if (GET_CODE (prev) != JUMP_INSN)
3218 prevpat = PATTERN (prev);
3219 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
3221 x = XVECEXP (prevpat, 0, 1);
3222 if (GET_CODE (x) != USE)
3225 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
3229 /* Emit the reference label of the braf where it belongs, right after
3230 the casesi_jump_2 (i.e. braf). */
3231 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
3232 emit_label_after (braf_label, prev);
3234 /* Fix up the ADDR_DIF_VEC to be relative
3235 to the reference address of the braf. */
3236 XEXP (XEXP (pat, 0), 0) = braf_label;
3240 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3241 a barrier. Return the base 2 logarithm of the desired alignment. */
3243 barrier_align (barrier_or_label)
3244 rtx barrier_or_label;
3246 rtx next = next_real_insn (barrier_or_label), pat, prev;
3247 int slot, credit, jump_to_next;
3252 pat = PATTERN (next);
3254 if (GET_CODE (pat) == ADDR_DIFF_VEC)
3257 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
3258 /* This is a barrier in front of a constant table. */
3261 prev = prev_real_insn (barrier_or_label);
3262 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
3264 pat = PATTERN (prev);
3265 /* If this is a very small table, we want to keep the alignment after
3266 the table to the minimum for proper code alignment. */
3267 return ((TARGET_SMALLCODE
3268 || (XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
3269 <= (unsigned)1 << (CACHE_LOG - 2)))
3270 ? 1 << TARGET_SHMEDIA : CACHE_LOG);
3273 if (TARGET_SMALLCODE)
3276 if (! TARGET_SH2 || ! optimize)
3279 /* When fixing up pcloads, a constant table might be inserted just before
3280 the basic block that ends with the barrier. Thus, we can't trust the
3281 instruction lengths before that. */
3282 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
3284 /* Check if there is an immediately preceding branch to the insn beyond
3285 the barrier. We must weight the cost of discarding useful information
3286 from the current cache line when executing this branch and there is
3287 an alignment, against that of fetching unneeded insn in front of the
3288 branch target when there is no alignment. */
3290 /* There are two delay_slot cases to consider. One is the simple case
3291 where the preceding branch is to the insn beyond the barrier (simple
3292 delay slot filling), and the other is where the preceding branch has
3293 a delay slot that is a duplicate of the insn after the barrier
3294 (fill_eager_delay_slots) and the branch is to the insn after the insn
3295 after the barrier. */
3297 /* PREV is presumed to be the JUMP_INSN for the barrier under
3298 investigation. Skip to the insn before it. */
3299 prev = prev_real_insn (prev);
3301 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
3302 credit >= 0 && prev && GET_CODE (prev) == INSN;
3303 prev = prev_real_insn (prev))
3306 if (GET_CODE (PATTERN (prev)) == USE
3307 || GET_CODE (PATTERN (prev)) == CLOBBER)
3309 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
3311 prev = XVECEXP (PATTERN (prev), 0, 1);
3312 if (INSN_UID (prev) == INSN_UID (next))
3314 /* Delay slot was filled with insn at jump target. */
3321 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3323 credit -= get_attr_length (prev);
3326 && GET_CODE (prev) == JUMP_INSN
3327 && JUMP_LABEL (prev))
3331 || next_real_insn (JUMP_LABEL (prev)) == next
3332 /* If relax_delay_slots() decides NEXT was redundant
3333 with some previous instruction, it will have
3334 redirected PREV's jump to the following insn. */
3335 || JUMP_LABEL (prev) == next_nonnote_insn (next)
3336 /* There is no upper bound on redundant instructions
3337 that might have been skipped, but we must not put an
3338 alignment where none had been before. */
3339 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
3341 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
3342 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch))))
3344 rtx pat = PATTERN (prev);
3345 if (GET_CODE (pat) == PARALLEL)
3346 pat = XVECEXP (pat, 0, 0);
3347 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
3356 /* If we are inside a phony loop, almost any kind of label can turn up as the
3357 first one in the loop. Aligning a braf label causes incorrect switch
3358 destination addresses; we can detect braf labels because they are
3359 followed by a BARRIER.
3360 Applying loop alignment to small constant or switch tables is a waste
3361 of space, so we suppress this too. */
3363 sh_loop_align (label)
3369 next = next_nonnote_insn (next);
3370 while (next && GET_CODE (next) == CODE_LABEL);
3374 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
3375 || recog_memoized (next) == CODE_FOR_consttable_2)
3384 /* Exported to toplev.c.
3386 Do a final pass over the function, just before delayed branch
3390 machine_dependent_reorg (first)
3395 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
3396 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
3398 /* We must split call insns before introducing `mova's. If we're
3399 optimizing, they'll have already been split. Otherwise, make
3400 sure we don't split them too late. */
3402 split_all_insns_noflow ();
3407 /* If relaxing, generate pseudo-ops to associate function calls with
3408 the symbols they call. It does no harm to not generate these
3409 pseudo-ops. However, when we can generate them, it enables to
3410 linker to potentially relax the jsr to a bsr, and eliminate the
3411 register load and, possibly, the constant pool entry. */
3413 mdep_reorg_phase = SH_INSERT_USES_LABELS;
3416 /* Remove all REG_LABEL notes. We want to use them for our own
3417 purposes. This works because none of the remaining passes
3418 need to look at them.
3420 ??? But it may break in the future. We should use a machine
3421 dependent REG_NOTE, or some other approach entirely. */
3422 for (insn = first; insn; insn = NEXT_INSN (insn))
3428 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
3429 remove_note (insn, note);
3433 for (insn = first; insn; insn = NEXT_INSN (insn))
3435 rtx pattern, reg, link, set, scan, dies, label;
3436 int rescan = 0, foundinsn = 0;
3438 if (GET_CODE (insn) == CALL_INSN)
3440 pattern = PATTERN (insn);
3442 if (GET_CODE (pattern) == PARALLEL)
3443 pattern = XVECEXP (pattern, 0, 0);
3444 if (GET_CODE (pattern) == SET)
3445 pattern = SET_SRC (pattern);
3447 if (GET_CODE (pattern) != CALL
3448 || GET_CODE (XEXP (pattern, 0)) != MEM)
3451 reg = XEXP (XEXP (pattern, 0), 0);
3455 reg = sfunc_uses_reg (insn);
3460 if (GET_CODE (reg) != REG)
3463 /* This is a function call via REG. If the only uses of REG
3464 between the time that it is set and the time that it dies
3465 are in function calls, then we can associate all the
3466 function calls with the setting of REG. */
3468 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
3470 if (REG_NOTE_KIND (link) != 0)
3472 set = single_set (XEXP (link, 0));
3473 if (set && rtx_equal_p (reg, SET_DEST (set)))
3475 link = XEXP (link, 0);
3482 /* ??? Sometimes global register allocation will have
3483 deleted the insn pointed to by LOG_LINKS. Try
3484 scanning backward to find where the register is set. */
3485 for (scan = PREV_INSN (insn);
3486 scan && GET_CODE (scan) != CODE_LABEL;
3487 scan = PREV_INSN (scan))
3489 if (! INSN_P (scan))
3492 if (! reg_mentioned_p (reg, scan))
3495 if (noncall_uses_reg (reg, scan, &set))
3509 /* The register is set at LINK. */
3511 /* We can only optimize the function call if the register is
3512 being set to a symbol. In theory, we could sometimes
3513 optimize calls to a constant location, but the assembler
3514 and linker do not support that at present. */
3515 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
3516 && GET_CODE (SET_SRC (set)) != LABEL_REF)
3519 /* Scan forward from LINK to the place where REG dies, and
3520 make sure that the only insns which use REG are
3521 themselves function calls. */
3523 /* ??? This doesn't work for call targets that were allocated
3524 by reload, since there may not be a REG_DEAD note for the
3528 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
3532 /* Don't try to trace forward past a CODE_LABEL if we haven't
3533 seen INSN yet. Ordinarily, we will only find the setting insn
3534 in LOG_LINKS if it is in the same basic block. However,
3535 cross-jumping can insert code labels in between the load and
3536 the call, and can result in situations where a single call
3537 insn may have two targets depending on where we came from. */
3539 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
3542 if (! INSN_P (scan))
3545 /* Don't try to trace forward past a JUMP. To optimize
3546 safely, we would have to check that all the
3547 instructions at the jump destination did not use REG. */
3549 if (GET_CODE (scan) == JUMP_INSN)
3552 if (! reg_mentioned_p (reg, scan))
3555 if (noncall_uses_reg (reg, scan, &scanset))
3562 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
3564 /* There is a function call to this register other
3565 than the one we are checking. If we optimize
3566 this call, we need to rescan again below. */
3570 /* ??? We shouldn't have to worry about SCANSET here.
3571 We should just be able to check for a REG_DEAD note
3572 on a function call. However, the REG_DEAD notes are
3573 apparently not dependable around libcalls; c-torture
3574 execute/920501-2 is a test case. If SCANSET is set,
3575 then this insn sets the register, so it must have
3576 died earlier. Unfortunately, this will only handle
3577 the cases in which the register is, in fact, set in a
3580 /* ??? We shouldn't have to use FOUNDINSN here.
3581 However, the LOG_LINKS fields are apparently not
3582 entirely reliable around libcalls;
3583 newlib/libm/math/e_pow.c is a test case. Sometimes
3584 an insn will appear in LOG_LINKS even though it is
3585 not the most recent insn which sets the register. */
3589 || find_reg_note (scan, REG_DEAD, reg)))
3598 /* Either there was a branch, or some insn used REG
3599 other than as a function call address. */
3603 /* Create a code label, and put it in a REG_LABEL note on
3604 the insn which sets the register, and on each call insn
3605 which uses the register. In final_prescan_insn we look
3606 for the REG_LABEL notes, and output the appropriate label
3609 label = gen_label_rtx ();
3610 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL, label,
3612 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, label,
3621 scan = NEXT_INSN (scan);
3623 && ((GET_CODE (scan) == CALL_INSN
3624 && reg_mentioned_p (reg, scan))
3625 || ((reg2 = sfunc_uses_reg (scan))
3626 && REGNO (reg2) == REGNO (reg))))
3628 = gen_rtx_INSN_LIST (REG_LABEL, label, REG_NOTES (scan));
3630 while (scan != dies);
3636 fixup_addr_diff_vecs (first);
3640 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
3641 shorten_branches (first);
3643 /* Scan the function looking for move instructions which have to be
3644 changed to pc-relative loads and insert the literal tables. */
3646 mdep_reorg_phase = SH_FIXUP_PCLOAD;
3647 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
3654 else if (GET_CODE (insn) == JUMP_INSN
3655 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3663 /* Some code might have been inserted between the mova and
3664 its ADDR_DIFF_VEC. Check if the mova is still in range. */
3665 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
3666 total += get_attr_length (scan);
3668 /* range of mova is 1020, add 4 because pc counts from address of
3669 second instruction after this one, subtract 2 in case pc is 2
3670 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
3671 cancels out with alignment effects of the mova itself. */
3674 /* Change the mova into a load, and restart scanning
3675 there. broken_move will then return true for mova. */
3676 SET_SRC (PATTERN (mova))
3677 = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3678 INSN_CODE (mova) = -1;
3682 if (broken_move (insn))
3685 /* Scan ahead looking for a barrier to stick the constant table
3687 rtx barrier = find_barrier (num_mova, mova, insn);
3688 rtx last_float_move, last_float = 0, *last_float_addr;
3689 int may_need_align = 1;
3691 if (num_mova && ! mova_p (mova))
3693 /* find_barrier had to change the first mova into a
3694 pcload; thus, we have to start with this new pcload. */
3698 /* Now find all the moves between the points and modify them. */
3699 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
3701 if (GET_CODE (scan) == CODE_LABEL)
3703 if (broken_move (scan))
3705 rtx *patp = &PATTERN (scan), pat = *patp;
3709 enum machine_mode mode;
3711 if (GET_CODE (pat) == PARALLEL)
3712 patp = &XVECEXP (pat, 0, 0), pat = *patp;
3713 src = SET_SRC (pat);
3714 dst = SET_DEST (pat);
3715 mode = GET_MODE (dst);
3717 if (mode == SImode && hi_const (src)
3718 && REGNO (dst) != FPUL_REG)
3723 while (GET_CODE (dst) == SUBREG)
3725 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
3726 GET_MODE (SUBREG_REG (dst)),
3729 dst = SUBREG_REG (dst);
3731 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
3734 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
3736 /* This must be an insn that clobbers r0. */
3737 rtx clobber = XVECEXP (PATTERN (scan), 0,
3738 XVECLEN (PATTERN (scan), 0) - 1);
3740 if (GET_CODE (clobber) != CLOBBER
3741 || ! rtx_equal_p (XEXP (clobber, 0), r0_rtx))
3745 && reg_set_between_p (r0_rtx, last_float_move, scan))
3747 if (TARGET_SHCOMPACT)
3749 /* The first SFmode constant after a DFmode
3750 constant may be pulled before a sequence
3751 of DFmode constants, so the second SFmode
3752 needs a label, just in case. */
3753 if (GET_MODE_SIZE (mode) == 4)
3755 if (last_float && may_need_align)
3760 && (GET_MODE_SIZE (GET_MODE (last_float))
3761 != GET_MODE_SIZE (mode)))
3764 if (GET_MODE_SIZE (mode) == 4)
3768 lab = add_constant (src, mode, last_float);
3770 emit_insn_before (gen_mova (lab), scan);
3773 /* There will be a REG_UNUSED note for r0 on
3774 LAST_FLOAT_MOVE; we have to change it to REG_INC,
3775 lest reorg:mark_target_live_regs will not
3776 consider r0 to be used, and we end up with delay
3777 slot insn in front of SCAN that clobbers r0. */
3779 = find_regno_note (last_float_move, REG_UNUSED, 0);
3781 /* If we are not optimizing, then there may not be
3784 PUT_MODE (note, REG_INC);
3786 *last_float_addr = r0_inc_rtx;
3788 last_float_move = scan;
3790 newsrc = gen_rtx (MEM, mode,
3791 (((TARGET_SH4 && ! TARGET_FMOVD)
3792 || REGNO (dst) == FPUL_REG)
3795 last_float_addr = &XEXP (newsrc, 0);
3797 /* Remove the clobber of r0. */
3798 XEXP (clobber, 0) = gen_rtx_SCRATCH (Pmode);
3800 /* This is a mova needing a label. Create it. */
3801 else if (GET_CODE (src) == UNSPEC
3802 && XINT (src, 1) == UNSPEC_MOVA
3803 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
3805 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
3806 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
3807 newsrc = gen_rtx_UNSPEC (VOIDmode,
3808 gen_rtvec (1, newsrc),
3813 lab = add_constant (src, mode, 0);
3814 newsrc = gen_rtx_MEM (mode,
3815 gen_rtx_LABEL_REF (VOIDmode, lab));
3817 RTX_UNCHANGING_P (newsrc) = 1;
3818 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
3819 INSN_CODE (scan) = -1;
3822 dump_table (barrier);
3827 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
3828 INSN_ADDRESSES_FREE ();
3829 split_branches (first);
3831 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
3832 also has an effect on the register that holds the addres of the sfunc.
3833 Insert an extra dummy insn in front of each sfunc that pretends to
3834 use this register. */
3835 if (flag_delayed_branch)
3837 for (insn = first; insn; insn = NEXT_INSN (insn))
3839 rtx reg = sfunc_uses_reg (insn);
3843 emit_insn_before (gen_use_sfunc_addr (reg), insn);
3847 /* fpscr is not actually a user variable, but we pretend it is for the
3848 sake of the previous optimization passes, since we want it handled like
3849 one. However, we don't have any debugging information for it, so turn
3850 it into a non-user variable now. */
3852 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
3854 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
3858 get_dest_uid (label, max_uid)
3862 rtx dest = next_real_insn (label);
3865 /* This can happen for an undefined label. */
3867 dest_uid = INSN_UID (dest);
3868 /* If this is a newly created branch redirection blocking instruction,
3869 we cannot index the branch_uid or insn_addresses arrays with its
3870 uid. But then, we won't need to, because the actual destination is
3871 the following branch. */
3872 while (dest_uid >= max_uid)
3874 dest = NEXT_INSN (dest);
3875 dest_uid = INSN_UID (dest);
3877 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
3882 /* Split condbranches that are out of range. Also add clobbers for
3883 scratch registers that are needed in far jumps.
3884 We do this before delay slot scheduling, so that it can take our
3885 newly created instructions into account. It also allows us to
3886 find branches with common targets more easily. */
3889 split_branches (first)
3893 struct far_branch **uid_branch, *far_branch_list = 0;
3894 int max_uid = get_max_uid ();
3896 /* Find out which branches are out of range. */
3897 shorten_branches (first);
3899 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
3900 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
3902 for (insn = first; insn; insn = NEXT_INSN (insn))
3903 if (! INSN_P (insn))
3905 else if (INSN_DELETED_P (insn))
3907 /* Shorten_branches would split this instruction again,
3908 so transform it into a note. */
3909 PUT_CODE (insn, NOTE);
3910 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
3911 NOTE_SOURCE_FILE (insn) = 0;
3913 else if (GET_CODE (insn) == JUMP_INSN
3914 /* Don't mess with ADDR_DIFF_VEC */
3915 && (GET_CODE (PATTERN (insn)) == SET
3916 || GET_CODE (PATTERN (insn)) == RETURN))
3918 enum attr_type type = get_attr_type (insn);
3919 if (type == TYPE_CBRANCH)
3923 if (get_attr_length (insn) > 4)
3925 rtx src = SET_SRC (PATTERN (insn));
3926 rtx olabel = XEXP (XEXP (src, 1), 0);
3927 int addr = INSN_ADDRESSES (INSN_UID (insn));
3929 int dest_uid = get_dest_uid (olabel, max_uid);
3930 struct far_branch *bp = uid_branch[dest_uid];
3932 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
3933 the label if the LABEL_NUSES count drops to zero. There is
3934 always a jump_optimize pass that sets these values, but it
3935 proceeds to delete unreferenced code, and then if not
3936 optimizing, to un-delete the deleted instructions, thus
3937 leaving labels with too low uses counts. */
3940 JUMP_LABEL (insn) = olabel;
3941 LABEL_NUSES (olabel)++;
3945 bp = (struct far_branch *) alloca (sizeof *bp);
3946 uid_branch[dest_uid] = bp;
3947 bp->prev = far_branch_list;
3948 far_branch_list = bp;
3950 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
3951 LABEL_NUSES (bp->far_label)++;
3955 label = bp->near_label;
3956 if (! label && bp->address - addr >= CONDJUMP_MIN)
3958 rtx block = bp->insert_place;
3960 if (GET_CODE (PATTERN (block)) == RETURN)
3961 block = PREV_INSN (block);
3963 block = gen_block_redirect (block,
3965 label = emit_label_after (gen_label_rtx (),
3967 bp->near_label = label;
3969 else if (label && ! NEXT_INSN (label))
3971 if (addr + 2 - bp->address <= CONDJUMP_MAX)
3972 bp->insert_place = insn;
3974 gen_far_branch (bp);
3978 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
3980 bp->near_label = label = gen_label_rtx ();
3981 bp->insert_place = insn;
3984 if (! redirect_jump (insn, label, 1))
3989 /* get_attr_length (insn) == 2 */
3990 /* Check if we have a pattern where reorg wants to redirect
3991 the branch to a label from an unconditional branch that
3993 /* We can't use JUMP_LABEL here because it might be undefined
3994 when not optimizing. */
3995 /* A syntax error might cause beyond to be NULL_RTX. */
3997 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
4001 && (GET_CODE (beyond) == JUMP_INSN
4002 || ((beyond = next_active_insn (beyond))
4003 && GET_CODE (beyond) == JUMP_INSN))
4004 && GET_CODE (PATTERN (beyond)) == SET
4005 && recog_memoized (beyond) == CODE_FOR_jump
4007 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
4008 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4010 gen_block_redirect (beyond,
4011 INSN_ADDRESSES (INSN_UID (beyond)), 1);
4014 next = next_active_insn (insn);
4016 if ((GET_CODE (next) == JUMP_INSN
4017 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
4018 && GET_CODE (PATTERN (next)) == SET
4019 && recog_memoized (next) == CODE_FOR_jump
4021 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
4022 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4024 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
4026 else if (type == TYPE_JUMP || type == TYPE_RETURN)
4028 int addr = INSN_ADDRESSES (INSN_UID (insn));
4031 struct far_branch *bp;
4033 if (type == TYPE_JUMP)
4035 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
4036 dest_uid = get_dest_uid (far_label, max_uid);
4039 /* Parse errors can lead to labels outside
4041 if (! NEXT_INSN (far_label))
4046 JUMP_LABEL (insn) = far_label;
4047 LABEL_NUSES (far_label)++;
4049 redirect_jump (insn, NULL_RTX, 1);
4053 bp = uid_branch[dest_uid];
4056 bp = (struct far_branch *) alloca (sizeof *bp);
4057 uid_branch[dest_uid] = bp;
4058 bp->prev = far_branch_list;
4059 far_branch_list = bp;
4061 bp->far_label = far_label;
4063 LABEL_NUSES (far_label)++;
4065 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
4066 if (addr - bp->address <= CONDJUMP_MAX)
4067 emit_label_after (bp->near_label, PREV_INSN (insn));
4070 gen_far_branch (bp);
4076 bp->insert_place = insn;
4078 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
4080 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
4083 /* Generate all pending far branches,
4084 and free our references to the far labels. */
4085 while (far_branch_list)
4087 if (far_branch_list->near_label
4088 && ! NEXT_INSN (far_branch_list->near_label))
4089 gen_far_branch (far_branch_list);
4091 && far_branch_list->far_label
4092 && ! --LABEL_NUSES (far_branch_list->far_label))
4093 delete_insn (far_branch_list->far_label);
4094 far_branch_list = far_branch_list->prev;
4097 /* Instruction length information is no longer valid due to the new
4098 instructions that have been generated. */
4099 init_insn_lengths ();
4102 /* Dump out instruction addresses, which is useful for debugging the
4103 constant pool table stuff.
4105 If relaxing, output the label and pseudo-ops used to link together
4106 calls and the instruction which set the registers. */
4108 /* ??? This is unnecessary, and probably should be deleted. This makes
4109 the insn_addresses declaration above unnecessary. */
4111 /* ??? The addresses printed by this routine for insns are nonsense for
4112 insns which are inside of a sequence where none of the inner insns have
4113 variable length. This is because the second pass of shorten_branches
4114 does not bother to update them. */
4117 final_prescan_insn (insn, opvec, noperands)
4119 rtx *opvec ATTRIBUTE_UNUSED;
4120 int noperands ATTRIBUTE_UNUSED;
4122 if (TARGET_DUMPISIZE)
4123 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
4129 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
4134 pattern = PATTERN (insn);
4135 if (GET_CODE (pattern) == PARALLEL)
4136 pattern = XVECEXP (pattern, 0, 0);
4137 if (GET_CODE (pattern) == CALL
4138 || (GET_CODE (pattern) == SET
4139 && (GET_CODE (SET_SRC (pattern)) == CALL
4140 || get_attr_type (insn) == TYPE_SFUNC)))
4141 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
4142 CODE_LABEL_NUMBER (XEXP (note, 0)));
4143 else if (GET_CODE (pattern) == SET)
4144 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4145 CODE_LABEL_NUMBER (XEXP (note, 0)));
4152 /* Dump out any constants accumulated in the final pass. These will
4156 output_jump_label_table ()
4162 fprintf (asm_out_file, "\t.align 2\n");
4163 for (i = 0; i < pool_size; i++)
4165 pool_node *p = &pool_vector[i];
4167 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4168 CODE_LABEL_NUMBER (p->label));
4169 output_asm_insn (".long %O0", &p->value);
4177 /* A full frame looks like:
4181 [ if current_function_anonymous_args
4194 local-0 <- fp points here. */
4196 /* Number of bytes pushed for anonymous args, used to pass information
4197 between expand_prologue and expand_epilogue. */
4199 static int extra_push;
4201 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
4202 to be adjusted, and TEMP, if nonnegative, holds the register number
4203 of a general register that we may clobber. */
4206 output_stack_adjust (size, reg, temp)
4213 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4218 if (CONST_OK_FOR_ADD (size))
4219 emit_insn (GEN_ADD3 (reg, reg, GEN_INT (size)));
4220 /* Try to do it with two partial adjustments; however, we must make
4221 sure that the stack is properly aligned at all times, in case
4222 an interrupt occurs between the two partial adjustments. */
4223 else if (CONST_OK_FOR_ADD (size / 2 & -align)
4224 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
4226 emit_insn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
4227 emit_insn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
4233 /* If TEMP is invalid, we could temporarily save a general
4234 register to MACL. However, there is currently no need
4235 to handle this case, so just abort when we see it. */
4238 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
4240 /* If SIZE is negative, subtract the positive value.
4241 This sometimes allows a constant pool entry to be shared
4242 between prologue and epilogue code. */
4245 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
4246 emit_insn (GEN_SUB3 (reg, reg, const_reg));
4250 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
4251 emit_insn (GEN_ADD3 (reg, reg, const_reg));
4257 /* Output RTL to push register RN onto the stack. */
4265 x = gen_push_fpul ();
4266 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4267 && FP_OR_XD_REGISTER_P (rn))
4269 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4271 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
4273 else if (TARGET_SH3E && FP_REGISTER_P (rn))
4274 x = gen_push_e (gen_rtx_REG (SFmode, rn));
4276 x = gen_push (gen_rtx_REG (SImode, rn));
4280 = gen_rtx_EXPR_LIST (REG_INC,
4281 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4284 /* Output RTL to pop register RN from the stack. */
4292 x = gen_pop_fpul ();
4293 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4294 && FP_OR_XD_REGISTER_P (rn))
4296 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4298 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
4300 else if (TARGET_SH3E && FP_REGISTER_P (rn))
4301 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
4303 x = gen_pop (gen_rtx_REG (SImode, rn));
4307 = gen_rtx_EXPR_LIST (REG_INC,
4308 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4311 /* Generate code to push the regs specified in the mask. */
4315 HOST_WIDE_INT *mask;
4319 /* Push PR last; this gives better latencies after the prologue, and
4320 candidates for the return delay slot when there are no general
4321 registers pushed. */
4322 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4323 if (i != PR_REG && mask[i / 32] & (1 << (i % 32)))
4325 if (mask[PR_REG / 32] & (1 << (PR_REG % 32)))
4329 /* Work out the registers which need to be saved, both as a mask and a
4330 count of saved words.
4332 If doing a pragma interrupt function, then push all regs used by the
4333 function, and if we call another function (we can tell by looking at PR),
4334 make sure that all the regs it clobbers are safe too. */
4337 calc_live_regs (count_ptr, live_regs_mask)
4339 HOST_WIDE_INT *live_regs_mask;
4343 int interrupt_handler;
4347 if ((lookup_attribute
4348 ("interrupt_handler",
4349 DECL_ATTRIBUTES (current_function_decl)))
4351 interrupt_handler = 1;
4353 interrupt_handler = 0;
4355 for (count = 0; 32 * count < FIRST_PSEUDO_REGISTER; count++)
4356 live_regs_mask[count] = 0;
4357 /* If we can save a lot of saves by switching to double mode, do that. */
4358 if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
4359 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
4360 if (regs_ever_live[reg] && regs_ever_live[reg+1]
4361 && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa))
4364 target_flags &= ~FPU_SINGLE_BIT;
4367 pr_initial = has_hard_reg_initial_val (Pmode,
4369 ? PR_MEDIA_REG : PR_REG);
4370 pr_live = (pr_initial
4371 ? REGNO (pr_initial) != (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
4372 : regs_ever_live[TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG]);
4373 /* Force PR to be live if the prologue has to call the SHmedia
4374 argument decoder or register saver. */
4375 if (TARGET_SHCOMPACT
4376 && ((current_function_args_info.call_cookie
4377 & ~ CALL_COOKIE_RET_TRAMP (1))
4378 || current_function_has_nonlocal_label))
4380 for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
4382 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
4384 : (interrupt_handler && ! pragma_trapa)
4385 ? (/* Need to save all the regs ever live. */
4386 (regs_ever_live[reg]
4387 || (call_used_regs[reg]
4388 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
4390 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
4391 && reg != RETURN_ADDRESS_POINTER_REGNUM
4392 && reg != T_REG && reg != GBR_REG && reg != FPSCR_REG)
4393 : (/* Only push those regs which are used and need to be saved. */
4394 regs_ever_live[reg] && ! call_used_regs[reg]))
4396 live_regs_mask[reg / 32] |= 1 << (reg % 32);
4397 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4399 if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD
4400 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
4402 if (FP_REGISTER_P (reg))
4404 if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
4406 live_regs_mask[(reg ^ 1) / 32] |= 1 << ((reg ^ 1) % 32);
4407 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
4410 else if (XD_REGISTER_P (reg))
4412 /* Must switch to double mode to access these registers. */
4413 target_flags &= ~FPU_SINGLE_BIT;
4422 /* Code to generate prologue and epilogue sequences */
4424 /* PUSHED is the number of bytes that are bing pushed on the
4425 stack for register saves. Return the frame size, padded
4426 appropriately so that the stack stays properly aligned. */
4427 static HOST_WIDE_INT
4428 rounded_frame_size (pushed)
4431 HOST_WIDE_INT size = get_frame_size ();
4432 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4434 return ((size + pushed + align - 1) & -align) - pushed;
4437 /* Choose a call-clobbered target-branch register that remains
4438 unchanged along the whole function. We set it up as the return
4439 value in the prologue. */
4441 sh_media_register_for_return ()
4446 if (! current_function_is_leaf)
4449 tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
4451 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
4452 if (call_used_regs[regno] && ! regs_ever_live[regno])
4459 sh_expand_prologue ()
4461 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
4464 int save_flags = target_flags;
4466 current_function_interrupt
4467 = lookup_attribute ("interrupt_handler",
4468 DECL_ATTRIBUTES (current_function_decl))
4471 /* We have pretend args if we had an object sent partially in registers
4472 and partially on the stack, e.g. a large structure. */
4473 output_stack_adjust (-current_function_pretend_args_size
4474 - current_function_args_info.stack_regs * 8,
4475 stack_pointer_rtx, TARGET_SH5 ? 0 : 1);
4479 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
4480 /* We're going to use the PIC register to load the address of the
4481 incoming-argument decoder and/or of the return trampoline from
4482 the GOT, so make sure the PIC register is preserved and
4484 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
4486 if (TARGET_SHCOMPACT
4487 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
4491 /* First, make all registers with incoming arguments that will
4492 be pushed onto the stack live, so that register renaming
4493 doesn't overwrite them. */
4494 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
4495 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
4496 >= NPARM_REGS (SImode) - reg)
4497 for (; reg < NPARM_REGS (SImode); reg++)
4498 emit_insn (gen_shcompact_preserve_incoming_args
4499 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
4500 else if (CALL_COOKIE_INT_REG_GET
4501 (current_function_args_info.call_cookie, reg) == 1)
4502 emit_insn (gen_shcompact_preserve_incoming_args
4503 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
4505 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
4507 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
4508 GEN_INT (current_function_args_info.call_cookie));
4509 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
4510 gen_rtx_REG (SImode, R0_REG));
4512 else if (TARGET_SHMEDIA)
4514 int tr = sh_media_register_for_return ();
4518 rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr),
4519 gen_rtx_REG (DImode, PR_MEDIA_REG));
4521 /* If this function only exits with sibcalls, this copy
4522 will be flagged as dead. */
4523 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4529 /* Emit the code for SETUP_VARARGS. */
4530 if (current_function_varargs || current_function_stdarg)
4532 /* This is not used by the SH3E calling convention */
4533 if (TARGET_SH1 && ! TARGET_SH3E && ! TARGET_SH5 && ! TARGET_HITACHI)
4535 /* Push arg regs as if they'd been provided by caller in stack. */
4536 for (i = 0; i < NPARM_REGS(SImode); i++)
4538 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
4539 if (i >= (NPARM_REGS(SImode)
4540 - current_function_args_info.arg_count[(int) SH_ARG_INT]
4549 /* If we're supposed to switch stacks at function entry, do so now. */
4551 emit_insn (gen_sp_switch_1 ());
4553 calc_live_regs (&d, live_regs_mask);
4554 /* ??? Maybe we could save some switching if we can move a mode switch
4555 that already happens to be at the function start into the prologue. */
4556 if (target_flags != save_flags)
4557 emit_insn (gen_toggle_sz ());
4564 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
4565 int offset_in_r0 = -1;
4568 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
4569 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
4570 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
4572 offset = d + d_rounding;
4573 output_stack_adjust (-offset, stack_pointer_rtx, 1);
4575 /* We loop twice: first, we save 8-byte aligned registers in the
4576 higher addresses, that are known to be aligned. Then, we
4577 proceed to saving 32-bit registers that don't need 8-byte
4579 for (align = 1; align >= 0; align--)
4580 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
4581 if (live_regs_mask[i/32] & (1 << (i % 32)))
4583 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
4585 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
4587 if (mode == SFmode && (i % 2) == 1
4588 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
4589 && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
4596 /* If we're doing the aligned pass and this is not aligned,
4597 or we're doing the unaligned pass and this is aligned,
4599 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
4603 offset -= GET_MODE_SIZE (mode);
4605 reg_rtx = gen_rtx_REG (mode, reg);
4607 mem_rtx = gen_rtx_MEM (mode,
4608 gen_rtx_PLUS (Pmode,
4612 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
4618 if (HAVE_PRE_DECREMENT
4619 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
4620 || mem_rtx == NULL_RTX
4621 || i == PR_REG || SPECIAL_REGISTER_P (i)))
4623 pre_dec = gen_rtx_MEM (mode,
4624 gen_rtx_PRE_DEC (Pmode, r0));
4626 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
4635 offset += GET_MODE_SIZE (mode);
4639 if (mem_rtx != NULL_RTX)
4642 if (offset_in_r0 == -1)
4644 emit_move_insn (r0, GEN_INT (offset));
4645 offset_in_r0 = offset;
4647 else if (offset != offset_in_r0)
4652 GEN_INT (offset - offset_in_r0)));
4653 offset_in_r0 += offset - offset_in_r0;
4656 if (pre_dec != NULL_RTX)
4662 (Pmode, r0, stack_pointer_rtx));
4666 offset -= GET_MODE_SIZE (mode);
4667 offset_in_r0 -= GET_MODE_SIZE (mode);
4672 mem_rtx = gen_rtx_MEM (mode, r0);
4674 mem_rtx = gen_rtx_MEM (mode,
4675 gen_rtx_PLUS (Pmode,
4679 /* We must not use an r0-based address for target-branch
4680 registers or for special registers without pre-dec
4681 memory addresses, since we store their values in r0
4683 if (TARGET_REGISTER_P (i)
4684 || ((i == PR_REG || SPECIAL_REGISTER_P (i))
4685 && mem_rtx != pre_dec))
4689 if (TARGET_REGISTER_P (i)
4690 || ((i == PR_REG || SPECIAL_REGISTER_P (i))
4691 && mem_rtx != pre_dec))
4693 rtx r0mode = gen_rtx_REG (GET_MODE (reg_rtx), R0_REG);
4695 emit_move_insn (r0mode, reg_rtx);
4703 emit_move_insn (mem_rtx, reg_rtx);
4706 if (offset != d_rounding)
4710 push_regs (live_regs_mask);
4712 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
4714 rtx insn = get_last_insn ();
4715 rtx last = emit_insn (gen_GOTaddr2picreg ());
4717 /* Mark these insns as possibly dead. Sometimes, flow2 may
4718 delete all uses of the PIC register. In this case, let it
4719 delete the initialization too. */
4722 insn = NEXT_INSN (insn);
4724 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4728 while (insn != last);
4731 if (SHMEDIA_REGS_STACK_ADJUST ())
4733 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
4734 gen_rtx_SYMBOL_REF (Pmode,
4736 ? "__GCC_push_shmedia_regs"
4737 : "__GCC_push_shmedia_regs_nofpu"));
4738 /* This must NOT go through the PLT, otherwise mach and macl
4739 may be clobbered. */
4740 emit_insn (gen_shmedia_save_restore_regs_compact
4741 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
4744 if (target_flags != save_flags)
4746 rtx insn = emit_insn (gen_toggle_sz ());
4748 /* If we're lucky, a mode switch in the function body will
4749 overwrite fpscr, turning this insn dead. Tell flow this
4750 insn is ok to delete. */
4751 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4756 target_flags = save_flags;
4758 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
4759 stack_pointer_rtx, TARGET_SH5 ? 0 : 1);
4761 if (frame_pointer_needed)
4762 emit_insn (GEN_MOV (frame_pointer_rtx, stack_pointer_rtx));
4764 if (TARGET_SHCOMPACT
4765 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
4767 /* This must NOT go through the PLT, otherwise mach and macl
4768 may be clobbered. */
4769 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
4770 gen_rtx_SYMBOL_REF (Pmode,
4771 "__GCC_shcompact_incoming_args"));
4772 emit_insn (gen_shcompact_incoming_args ());
4777 sh_expand_epilogue ()
4779 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
4783 int save_flags = target_flags;
4786 calc_live_regs (&d, live_regs_mask);
4788 if (TARGET_SH5 && d % (STACK_BOUNDARY / BITS_PER_UNIT))
4789 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
4790 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
4792 frame_size = rounded_frame_size (d) - d_rounding;
4794 if (frame_pointer_needed)
4796 output_stack_adjust (frame_size, frame_pointer_rtx, 7);
4798 /* We must avoid moving the stack pointer adjustment past code
4799 which reads from the local frame, else an interrupt could
4800 occur after the SP adjustment and clobber data in the local
4802 emit_insn (gen_blockage ());
4803 emit_insn (GEN_MOV (stack_pointer_rtx, frame_pointer_rtx));
4805 else if (frame_size)
4807 /* We must avoid moving the stack pointer adjustment past code
4808 which reads from the local frame, else an interrupt could
4809 occur after the SP adjustment and clobber data in the local
4811 emit_insn (gen_blockage ());
4812 output_stack_adjust (frame_size, stack_pointer_rtx, 7);
4815 if (SHMEDIA_REGS_STACK_ADJUST ())
4817 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
4818 gen_rtx_SYMBOL_REF (Pmode,
4820 ? "__GCC_pop_shmedia_regs"
4821 : "__GCC_pop_shmedia_regs_nofpu"));
4822 /* This must NOT go through the PLT, otherwise mach and macl
4823 may be clobbered. */
4824 emit_insn (gen_shmedia_save_restore_regs_compact
4825 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
4828 /* Pop all the registers. */
4830 if (target_flags != save_flags)
4831 emit_insn (gen_toggle_sz ());
4834 int offset = d_rounding;
4835 int offset_in_r0 = -1;
4838 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
4840 /* We loop twice: first, we save 8-byte aligned registers in the
4841 higher addresses, that are known to be aligned. Then, we
4842 proceed to saving 32-bit registers that don't need 8-byte
4844 for (align = 0; align <= 1; align++)
4845 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4846 if (live_regs_mask[i/32] & (1 << (i % 32)))
4848 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
4850 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
4852 if (mode == SFmode && (i % 2) == 0
4853 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
4854 && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
4860 /* If we're doing the aligned pass and this is not aligned,
4861 or we're doing the unaligned pass and this is aligned,
4863 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
4867 reg_rtx = gen_rtx_REG (mode, reg);
4869 mem_rtx = gen_rtx_MEM (mode,
4870 gen_rtx_PLUS (Pmode,
4874 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
4880 if (HAVE_POST_INCREMENT
4881 && (offset == offset_in_r0
4882 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
4883 && mem_rtx == NULL_RTX)
4884 || i == PR_REG || SPECIAL_REGISTER_P (i)))
4886 post_inc = gen_rtx_MEM (mode,
4887 gen_rtx_POST_INC (Pmode, r0));
4889 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
4892 post_inc = NULL_RTX;
4901 if (mem_rtx != NULL_RTX)
4904 if (offset_in_r0 == -1)
4906 emit_move_insn (r0, GEN_INT (offset));
4907 offset_in_r0 = offset;
4909 else if (offset != offset_in_r0)
4914 GEN_INT (offset - offset_in_r0)));
4915 offset_in_r0 += offset - offset_in_r0;
4918 if (post_inc != NULL_RTX)
4924 (Pmode, r0, stack_pointer_rtx));
4930 offset_in_r0 += GET_MODE_SIZE (mode);
4933 mem_rtx = gen_rtx_MEM (mode, r0);
4935 mem_rtx = gen_rtx_MEM (mode,
4936 gen_rtx_PLUS (Pmode,
4940 if ((i == PR_REG || SPECIAL_REGISTER_P (i))
4941 && mem_rtx != post_inc)
4945 if ((i == PR_REG || SPECIAL_REGISTER_P (i))
4946 && mem_rtx != post_inc)
4948 insn = emit_move_insn (r0, mem_rtx);
4951 else if (TARGET_REGISTER_P (i))
4953 rtx r1 = gen_rtx_REG (mode, R1_REG);
4955 insn = emit_move_insn (r1, mem_rtx);
4959 insn = emit_move_insn (reg_rtx, mem_rtx);
4961 offset += GET_MODE_SIZE (mode);
4964 if (offset != d + d_rounding)
4971 if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32)))
4973 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4975 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
4977 if (j != PR_REG && live_regs_mask[j / 32] & (1 << (j % 32)))
4981 if (target_flags != save_flags)
4982 emit_insn (gen_toggle_sz ());
4983 target_flags = save_flags;
4985 output_stack_adjust (extra_push + current_function_pretend_args_size
4987 + current_function_args_info.stack_regs * 8,
4988 stack_pointer_rtx, 7);
4990 /* Switch back to the normal stack if necessary. */
4992 emit_insn (gen_sp_switch_2 ());
4994 /* Tell flow the insn that pops PR isn't dead. */
4995 /* PR_REG will never be live in SHmedia mode, and we don't need to
4996 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
4997 by the return pattern. */
4998 if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32)))
4999 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
5002 static int sh_need_epilogue_known = 0;
5007 if (! sh_need_epilogue_known)
5012 sh_expand_epilogue ();
5013 epilogue = gen_sequence ();
5015 sh_need_epilogue_known
5016 = (GET_CODE (epilogue) == SEQUENCE && XVECLEN (epilogue, 0) == 0
5019 return sh_need_epilogue_known > 0;
5022 /* Clear variables at function end. */
5025 sh_output_function_epilogue (file, size)
5026 FILE *file ATTRIBUTE_UNUSED;
5027 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
5029 trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
5030 sh_need_epilogue_known = 0;
5031 sp_switch = NULL_RTX;
5035 sh_builtin_saveregs ()
5037 /* First unnamed integer register. */
5038 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
5039 /* Number of integer registers we need to save. */
5040 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
5041 /* First unnamed SFmode float reg */
5042 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5043 /* Number of SFmode float regs to save. */
5044 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5047 HOST_WIDE_INT alias_set;
5053 int pushregs = n_intregs;
5055 while (pushregs < NPARM_REGS (SImode) - 1
5056 && (CALL_COOKIE_INT_REG_GET
5057 (current_function_args_info.call_cookie,
5058 NPARM_REGS (SImode) - pushregs)
5061 current_function_args_info.call_cookie
5062 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
5067 if (pushregs == NPARM_REGS (SImode))
5068 current_function_args_info.call_cookie
5069 |= (CALL_COOKIE_INT_REG (0, 1)
5070 | CALL_COOKIE_STACKSEQ (pushregs - 1));
5072 current_function_args_info.call_cookie
5073 |= CALL_COOKIE_STACKSEQ (pushregs);
5075 current_function_pretend_args_size += 8 * n_intregs;
5077 if (TARGET_SHCOMPACT)
5081 if (! TARGET_SH3E && ! TARGET_SH4 && ! TARGET_SH5)
5083 error ("__builtin_saveregs not supported by this subtarget");
5090 /* Allocate block of memory for the regs. */
5091 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5092 Or can assign_stack_local accept a 0 SIZE argument? */
5093 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
5096 regbuf = gen_rtx_MEM (BLKmode,
5097 gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
5098 else if (n_floatregs & 1)
5102 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
5103 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
5104 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
5105 regbuf = change_address (regbuf, BLKmode, addr);
5108 regbuf = assign_stack_local (BLKmode, bufsize, 0);
5109 alias_set = get_varargs_alias_set ();
5110 set_mem_alias_set (regbuf, alias_set);
5113 This is optimized to only save the regs that are necessary. Explicitly
5114 named args need not be saved. */
5116 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
5117 adjust_address (regbuf, BLKmode,
5118 n_floatregs * UNITS_PER_WORD),
5119 n_intregs, n_intregs * UNITS_PER_WORD);
5122 /* Return the address of the regbuf. */
5123 return XEXP (regbuf, 0);
5126 This is optimized to only save the regs that are necessary. Explicitly
5127 named args need not be saved.
5128 We explicitly build a pointer to the buffer because it halves the insn
5129 count when not optimizing (otherwise the pointer is built for each reg
5131 We emit the moves in reverse order so that we can use predecrement. */
5133 fpregs = gen_reg_rtx (Pmode);
5134 emit_move_insn (fpregs, XEXP (regbuf, 0));
5135 emit_insn (gen_addsi3 (fpregs, fpregs,
5136 GEN_INT (n_floatregs * UNITS_PER_WORD)));
5140 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
5142 emit_insn (gen_addsi3 (fpregs, fpregs,
5143 GEN_INT (-2 * UNITS_PER_WORD)));
5144 mem = gen_rtx_MEM (DFmode, fpregs);
5145 set_mem_alias_set (mem, alias_set);
5146 emit_move_insn (mem,
5147 gen_rtx (REG, DFmode, BASE_ARG_REG (DFmode) + regno));
5149 regno = first_floatreg;
5152 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5153 mem = gen_rtx_MEM (SFmode, fpregs);
5154 set_mem_alias_set (mem, alias_set);
5155 emit_move_insn (mem,
5156 gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno
5157 - (TARGET_LITTLE_ENDIAN != 0)));
5161 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
5165 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5166 mem = gen_rtx_MEM (SFmode, fpregs);
5167 set_mem_alias_set (mem, alias_set);
5168 emit_move_insn (mem,
5169 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
5172 /* Return the address of the regbuf. */
5173 return XEXP (regbuf, 0);
5176 /* Define the `__builtin_va_list' type for the ABI. */
5181 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5184 if (TARGET_SH5 || (! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI)
5185 return ptr_type_node;
5187 record = make_node (RECORD_TYPE);
5189 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
5191 f_next_o_limit = build_decl (FIELD_DECL,
5192 get_identifier ("__va_next_o_limit"),
5194 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
5196 f_next_fp_limit = build_decl (FIELD_DECL,
5197 get_identifier ("__va_next_fp_limit"),
5199 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
5202 DECL_FIELD_CONTEXT (f_next_o) = record;
5203 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
5204 DECL_FIELD_CONTEXT (f_next_fp) = record;
5205 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
5206 DECL_FIELD_CONTEXT (f_next_stack) = record;
5208 TYPE_FIELDS (record) = f_next_o;
5209 TREE_CHAIN (f_next_o) = f_next_o_limit;
5210 TREE_CHAIN (f_next_o_limit) = f_next_fp;
5211 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
5212 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
5214 layout_type (record);
5219 /* Implement `va_start' for varargs and stdarg. */
5222 sh_va_start (stdarg_p, valist, nextarg)
5227 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5228 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
5234 expand_builtin_saveregs ();
5235 /* When the varargs dummy argument is ``passed'' on a register,
5236 we don't want std_expand_builtin_va_start() to apply any
5237 correction for it, so set stdarg_p so as to pretend there's
5238 no such dummy argument. */
5239 if (current_function_args_info.arg_count[(int) SH_ARG_INT]
5240 < NPARM_REGS (SImode))
5242 std_expand_builtin_va_start (stdarg_p, valist, nextarg);
5246 if ((! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI)
5248 std_expand_builtin_va_start (stdarg_p, valist, nextarg);
5252 f_next_o = TYPE_FIELDS (va_list_type_node);
5253 f_next_o_limit = TREE_CHAIN (f_next_o);
5254 f_next_fp = TREE_CHAIN (f_next_o_limit);
5255 f_next_fp_limit = TREE_CHAIN (f_next_fp);
5256 f_next_stack = TREE_CHAIN (f_next_fp_limit);
5258 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
5259 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
5260 valist, f_next_o_limit);
5261 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp);
5262 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
5263 valist, f_next_fp_limit);
5264 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
5265 valist, f_next_stack);
5267 /* Call __builtin_saveregs. */
5268 u = make_tree (ptr_type_node, expand_builtin_saveregs ());
5269 t = build (MODIFY_EXPR, ptr_type_node, next_fp, u);
5270 TREE_SIDE_EFFECTS (t) = 1;
5271 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5273 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
5278 u = fold (build (PLUS_EXPR, ptr_type_node, u,
5279 build_int_2 (UNITS_PER_WORD * nfp, 0)));
5280 t = build (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
5281 TREE_SIDE_EFFECTS (t) = 1;
5282 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5284 t = build (MODIFY_EXPR, ptr_type_node, next_o, u);
5285 TREE_SIDE_EFFECTS (t) = 1;
5286 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5288 nint = current_function_args_info.arg_count[SH_ARG_INT];
5293 u = fold (build (PLUS_EXPR, ptr_type_node, u,
5294 build_int_2 (UNITS_PER_WORD * nint, 0)));
5295 t = build (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
5296 TREE_SIDE_EFFECTS (t) = 1;
5297 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5299 u = make_tree (ptr_type_node, nextarg);
5300 if (! stdarg_p && (nint == 0 || nfp == 0))
5302 u = fold (build (PLUS_EXPR, ptr_type_node, u,
5303 build_int_2 (-UNITS_PER_WORD, -1)));
5305 t = build (MODIFY_EXPR, ptr_type_node, next_stack, u);
5306 TREE_SIDE_EFFECTS (t) = 1;
5307 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5310 /* Implement `va_arg'. */
5313 sh_va_arg (valist, type)
5316 HOST_WIDE_INT size, rsize;
5317 tree tmp, pptr_type_node;
5320 int pass_by_ref = MUST_PASS_IN_STACK (TYPE_MODE (type), type);
5322 size = int_size_in_bytes (type);
5323 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5324 pptr_type_node = build_pointer_type (ptr_type_node);
5327 type = build_pointer_type (type);
5329 if (! TARGET_SH5 && (TARGET_SH3E || TARGET_SH4) && ! TARGET_HITACHI)
5331 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5332 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
5334 rtx lab_false, lab_over;
5336 f_next_o = TYPE_FIELDS (va_list_type_node);
5337 f_next_o_limit = TREE_CHAIN (f_next_o);
5338 f_next_fp = TREE_CHAIN (f_next_o_limit);
5339 f_next_fp_limit = TREE_CHAIN (f_next_fp);
5340 f_next_stack = TREE_CHAIN (f_next_fp_limit);
5342 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
5343 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
5344 valist, f_next_o_limit);
5345 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp),
5347 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
5348 valist, f_next_fp_limit);
5349 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
5350 valist, f_next_stack);
5354 pass_as_float = ((TREE_CODE (type) == REAL_TYPE && size <= 8)
5355 || (TREE_CODE (type) == COMPLEX_TYPE
5356 && TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
5361 pass_as_float = (TREE_CODE (type) == REAL_TYPE && size == 4);
5364 addr_rtx = gen_reg_rtx (Pmode);
5365 lab_false = gen_label_rtx ();
5366 lab_over = gen_label_rtx ();
5371 = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5372 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5374 emit_cmp_and_jump_insns (expand_expr (next_fp, NULL_RTX, Pmode,
5376 expand_expr (next_fp_limit, NULL_RTX,
5377 Pmode, EXPAND_NORMAL),
5378 GE, const1_rtx, Pmode, 1, lab_false);
5380 if (TYPE_ALIGN (type) > BITS_PER_WORD
5381 || (((TREE_CODE (type) == REAL_TYPE && size == 8) || size == 16)
5382 && (n_floatregs & 1)))
5384 tmp = build (BIT_AND_EXPR, ptr_type_node, next_fp,
5385 build_int_2 (UNITS_PER_WORD, 0));
5386 tmp = build (PLUS_EXPR, ptr_type_node, next_fp, tmp);
5387 tmp = build (MODIFY_EXPR, ptr_type_node, next_fp, tmp);
5388 TREE_SIDE_EFFECTS (tmp) = 1;
5389 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
5392 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
5393 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5395 emit_move_insn (addr_rtx, r);
5397 emit_jump_insn (gen_jump (lab_over));
5399 emit_label (lab_false);
5401 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
5402 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5404 emit_move_insn (addr_rtx, r);
5408 tmp = build (PLUS_EXPR, ptr_type_node, next_o,
5409 build_int_2 (rsize, 0));
5411 emit_cmp_and_jump_insns (expand_expr (tmp, NULL_RTX, Pmode,
5413 expand_expr (next_o_limit, NULL_RTX,
5414 Pmode, EXPAND_NORMAL),
5415 GT, const1_rtx, Pmode, 1, lab_false);
5417 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
5418 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5420 emit_move_insn (addr_rtx, r);
5422 emit_jump_insn (gen_jump (lab_over));
5424 emit_label (lab_false);
5426 if (size > 4 && ! TARGET_SH4)
5428 tmp = build (MODIFY_EXPR, ptr_type_node, next_o, next_o_limit);
5429 TREE_SIDE_EFFECTS (tmp) = 1;
5430 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
5433 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
5434 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5436 emit_move_insn (addr_rtx, r);
5439 emit_label (lab_over);
5441 tmp = make_tree (pptr_type_node, addr_rtx);
5442 valist = build1 (INDIRECT_REF, ptr_type_node, tmp);
5445 /* ??? In va-sh.h, there had been code to make values larger than
5446 size 8 indirect. This does not match the FUNCTION_ARG macros. */
5448 result = std_expand_builtin_va_arg (valist, type);
5451 #ifdef POINTERS_EXTEND_UNSIGNED
5452 if (GET_MODE (addr) != Pmode)
5453 addr = convert_memory_address (Pmode, result);
5455 result = gen_rtx_MEM (ptr_mode, force_reg (Pmode, result));
5456 set_mem_alias_set (result, get_varargs_alias_set ());
5458 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
5459 argument to the varargs alias set. */
5463 /* Define the offset between two registers, one to be eliminated, and
5464 the other its replacement, at the start of a routine. */
5467 initial_elimination_offset (from, to)
5472 int regs_saved_rounding = 0;
5473 int total_saved_regs_space;
5474 int total_auto_space;
5475 int save_flags = target_flags;
5478 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
5479 calc_live_regs (®s_saved, live_regs_mask);
5480 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
5481 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
5482 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5483 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
5485 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
5486 copy_flags = target_flags;
5487 target_flags = save_flags;
5489 total_saved_regs_space = regs_saved + regs_saved_rounding;
5491 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
5492 return total_saved_regs_space + total_auto_space
5493 + current_function_args_info.byref_regs * 8;
5495 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
5496 return total_saved_regs_space + total_auto_space
5497 + current_function_args_info.byref_regs * 8;
5499 /* Initial gap between fp and sp is 0. */
5500 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
5503 if (from == RETURN_ADDRESS_POINTER_REGNUM
5504 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
5507 int i, n = total_saved_regs_space;
5509 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
5511 n += total_auto_space;
5513 /* If it wasn't saved, there's not much we can do. */
5514 if ((live_regs_mask[pr_reg / 32] & (1 << (pr_reg % 32))) == 0)
5517 target_flags = copy_flags;
5519 /* We loop twice: first, check 8-byte aligned registers,
5520 that are stored in the higher addresses, that are known
5521 to be aligned. Then, check 32-bit registers that don't
5522 need 8-byte alignment. */
5523 for (align = 1; align >= 0; align--)
5524 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
5525 if (live_regs_mask[i/32] & (1 << (i % 32)))
5527 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5529 if (mode == SFmode && (i % 2) == 1
5530 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5531 && (live_regs_mask[(i ^ 1) / 32]
5532 & (1 << ((i ^ 1) % 32))))
5538 /* If we're doing the aligned pass and this is not aligned,
5539 or we're doing the unaligned pass and this is aligned,
5541 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
5545 n -= GET_MODE_SIZE (mode);
5549 target_flags = save_flags;
5557 return total_auto_space;
5562 /* Handle machine specific pragmas to be semi-compatible with Hitachi
5566 sh_pr_interrupt (pfile)
5567 cpp_reader *pfile ATTRIBUTE_UNUSED;
5569 pragma_interrupt = 1;
5574 cpp_reader *pfile ATTRIBUTE_UNUSED;
5576 pragma_interrupt = pragma_trapa = 1;
5580 sh_pr_nosave_low_regs (pfile)
5581 cpp_reader *pfile ATTRIBUTE_UNUSED;
5583 pragma_nosave_low_regs = 1;
5586 /* Generate 'handle_interrupt' attribute for decls */
5589 sh_insert_attributes (node, attributes)
5593 if (! pragma_interrupt
5594 || TREE_CODE (node) != FUNCTION_DECL)
5597 /* We are only interested in fields. */
5598 if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd')
5601 /* Add a 'handle_interrupt' attribute. */
5602 * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes);
5607 /* Supported attributes:
5609 interrupt_handler -- specifies this function is an interrupt handler.
5611 sp_switch -- specifies an alternate stack for an interrupt handler
5614 trap_exit -- use a trapa to exit an interrupt function instead of
5615 an rte instruction. */
5617 const struct attribute_spec sh_attribute_table[] =
5619 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5620 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
5621 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
5622 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
5623 { NULL, 0, 0, false, false, false, NULL }
5626 /* Handle an "interrupt_handler" attribute; arguments as in
5627 struct attribute_spec.handler. */
5629 sh_handle_interrupt_handler_attribute (node, name, args, flags, no_add_attrs)
5632 tree args ATTRIBUTE_UNUSED;
5633 int flags ATTRIBUTE_UNUSED;
5636 if (TREE_CODE (*node) != FUNCTION_DECL)
5638 warning ("`%s' attribute only applies to functions",
5639 IDENTIFIER_POINTER (name));
5640 *no_add_attrs = true;
5646 /* Handle an "sp_switch" attribute; arguments as in
5647 struct attribute_spec.handler. */
5649 sh_handle_sp_switch_attribute (node, name, args, flags, no_add_attrs)
5653 int flags ATTRIBUTE_UNUSED;
5656 if (TREE_CODE (*node) != FUNCTION_DECL)
5658 warning ("`%s' attribute only applies to functions",
5659 IDENTIFIER_POINTER (name));
5660 *no_add_attrs = true;
5662 else if (!pragma_interrupt)
5664 /* The sp_switch attribute only has meaning for interrupt functions. */
5665 warning ("`%s' attribute only applies to interrupt functions",
5666 IDENTIFIER_POINTER (name));
5667 *no_add_attrs = true;
5669 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
5671 /* The argument must be a constant string. */
5672 warning ("`%s' attribute argument not a string constant",
5673 IDENTIFIER_POINTER (name));
5674 *no_add_attrs = true;
5678 sp_switch = gen_rtx_SYMBOL_REF (VOIDmode,
5679 TREE_STRING_POINTER (TREE_VALUE (args)));
5685 /* Handle an "trap_exit" attribute; arguments as in
5686 struct attribute_spec.handler. */
5688 sh_handle_trap_exit_attribute (node, name, args, flags, no_add_attrs)
5692 int flags ATTRIBUTE_UNUSED;
5695 if (TREE_CODE (*node) != FUNCTION_DECL)
5697 warning ("`%s' attribute only applies to functions",
5698 IDENTIFIER_POINTER (name));
5699 *no_add_attrs = true;
5701 else if (!pragma_interrupt)
5703 /* The trap_exit attribute only has meaning for interrupt functions. */
5704 warning ("`%s' attribute only applies to interrupt functions",
5705 IDENTIFIER_POINTER (name));
5706 *no_add_attrs = true;
5708 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
5710 /* The argument must be a constant integer. */
5711 warning ("`%s' attribute argument not an integer constant",
5712 IDENTIFIER_POINTER (name));
5713 *no_add_attrs = true;
5717 trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
5724 /* Predicates used by the templates. */
5726 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
5727 Used only in general_movsrc_operand. */
5730 system_reg_operand (op, mode)
5732 enum machine_mode mode ATTRIBUTE_UNUSED;
5744 /* Returns 1 if OP can be source of a simple move operation.
5745 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
5746 invalid as are subregs of system registers. */
5749 general_movsrc_operand (op, mode)
5751 enum machine_mode mode;
5753 if (GET_CODE (op) == MEM)
5755 rtx inside = XEXP (op, 0);
5756 if (GET_CODE (inside) == CONST)
5757 inside = XEXP (inside, 0);
5759 if (GET_CODE (inside) == LABEL_REF)
5762 if (GET_CODE (inside) == PLUS
5763 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
5764 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
5767 /* Only post inc allowed. */
5768 if (GET_CODE (inside) == PRE_DEC)
5772 if ((mode == QImode || mode == HImode)
5773 && (GET_CODE (op) == SUBREG
5774 && GET_CODE (XEXP (op, 0)) == REG
5775 && system_reg_operand (XEXP (op, 0), mode)))
5778 return general_operand (op, mode);
5781 /* Returns 1 if OP can be a destination of a move.
5782 Same as general_operand, but no preinc allowed. */
5785 general_movdst_operand (op, mode)
5787 enum machine_mode mode;
5789 /* Only pre dec allowed. */
5790 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
5793 return general_operand (op, mode);
5796 /* Accept a register, but not a subreg of any kind. This allows us to
5797 avoid pathological cases in reload wrt data movement common in
5798 int->fp conversion. */
5801 reg_no_subreg_operand (op, mode)
5803 enum machine_mode mode;
5805 if (GET_CODE (op) == SUBREG)
5807 return register_operand (op, mode);
5810 /* Returns 1 if OP is a normal arithmetic register. */
5813 arith_reg_operand (op, mode)
5815 enum machine_mode mode;
5817 if (register_operand (op, mode))
5821 if (GET_CODE (op) == REG)
5823 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
5824 regno = REGNO (SUBREG_REG (op));
5828 return (regno != T_REG && regno != PR_REG
5829 && ! TARGET_REGISTER_P (regno)
5830 && (regno != FPUL_REG || TARGET_SH4)
5831 && regno != MACH_REG && regno != MACL_REG);
5837 fp_arith_reg_operand (op, mode)
5839 enum machine_mode mode;
5841 if (register_operand (op, mode))
5845 if (GET_CODE (op) == REG)
5847 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
5848 regno = REGNO (SUBREG_REG (op));
5852 return (regno >= FIRST_PSEUDO_REGISTER
5853 || FP_REGISTER_P (regno));
5858 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
5861 arith_operand (op, mode)
5863 enum machine_mode mode;
5865 if (arith_reg_operand (op, mode))
5870 /* FIXME: We should be checking whether the CONST_INT fits in a
5871 CONST_OK_FOR_J here, but this causes reload_cse to crash when
5872 attempting to transform a sequence of two 64-bit sets of the
5873 same register from literal constants into a set and an add,
5874 when the difference is too wide for an add. */
5875 if (GET_CODE (op) == CONST_INT
5876 || EXTRA_CONSTRAINT_S (op))
5881 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
5887 /* Returns 1 if OP is a valid source operand for a compare insn. */
5890 arith_reg_or_0_operand (op, mode)
5892 enum machine_mode mode;
5894 if (arith_reg_operand (op, mode))
5897 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_N (INTVAL (op)))
5903 /* Return 1 if OP is a valid source operand for an SHmedia operation
5904 that takes either a register or a 6-bit immediate. */
5907 shmedia_6bit_operand (op, mode)
5909 enum machine_mode mode;
5911 return (arith_reg_operand (op, mode)
5912 || (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op))));
5915 /* Returns 1 if OP is a valid source operand for a logical operation. */
5918 logical_operand (op, mode)
5920 enum machine_mode mode;
5922 if (arith_reg_operand (op, mode))
5927 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_P (INTVAL (op)))
5932 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
5938 /* Nonzero if OP is a floating point value with value 0.0. */
5941 fp_zero_operand (op)
5946 if (GET_MODE (op) != SFmode)
5949 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
5950 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
5953 /* Nonzero if OP is a floating point value with value 1.0. */
5961 if (GET_MODE (op) != SFmode)
5964 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
5965 return REAL_VALUES_EQUAL (r, dconst1);
5968 /* For -m4 and -m4-single-only, mode switching is used. If we are
5969 compiling without -mfmovd, movsf_ie isn't taken into account for
5970 mode switching. We could check in machine_dependent_reorg for
5971 cases where we know we are in single precision mode, but there is
5972 interface to find that out during reload, so we must avoid
5973 choosing an fldi alternative during reload and thus failing to
5974 allocate a scratch register for the constant loading. */
5978 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
5982 tertiary_reload_operand (op, mode)
5984 enum machine_mode mode ATTRIBUTE_UNUSED;
5986 enum rtx_code code = GET_CODE (op);
5987 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
5991 fpscr_operand (op, mode)
5993 enum machine_mode mode ATTRIBUTE_UNUSED;
5995 return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG
5996 && GET_MODE (op) == PSImode);
6000 fpul_operand (op, mode)
6002 enum machine_mode mode;
6005 return fp_arith_reg_operand (op, mode);
6007 return (GET_CODE (op) == REG
6008 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
6009 && GET_MODE (op) == mode);
6013 symbol_ref_operand (op, mode)
6015 enum machine_mode mode ATTRIBUTE_UNUSED;
6017 return (GET_CODE (op) == SYMBOL_REF);
6021 commutative_float_operator (op, mode)
6023 enum machine_mode mode;
6025 if (GET_MODE (op) != mode)
6027 switch (GET_CODE (op))
6039 noncommutative_float_operator (op, mode)
6041 enum machine_mode mode;
6043 if (GET_MODE (op) != mode)
6045 switch (GET_CODE (op))
6057 binary_float_operator (op, mode)
6059 enum machine_mode mode;
6061 if (GET_MODE (op) != mode)
6063 switch (GET_CODE (op))
6076 /* Accept pseudos and branch target registers. */
6078 target_reg_operand (op, mode)
6080 enum machine_mode mode;
6083 || GET_MODE (op) != DImode)
6086 if (GET_CODE (op) == SUBREG)
6089 if (GET_CODE (op) != REG)
6092 /* We must protect ourselves from matching pseudos that are virtual
6093 register, because they will eventually be replaced with hardware
6094 registers that aren't branch-target registers. */
6095 if (REGNO (op) > LAST_VIRTUAL_REGISTER
6096 || TARGET_REGISTER_P (REGNO (op)))
6102 /* Same as target_reg_operand, except that label_refs and symbol_refs
6103 are accepted before reload. */
6105 target_operand (op, mode)
6107 enum machine_mode mode;
6112 if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode)
6113 && EXTRA_CONSTRAINT_T (op))
6114 return ! reload_completed;
6116 return target_reg_operand (op, mode);
6120 /* Return the destination address of a branch. */
6123 branch_dest (branch)
6126 rtx dest = SET_SRC (PATTERN (branch));
6129 if (GET_CODE (dest) == IF_THEN_ELSE)
6130 dest = XEXP (dest, 1);
6131 dest = XEXP (dest, 0);
6132 dest_uid = INSN_UID (dest);
6133 return INSN_ADDRESSES (dest_uid);
6136 /* Return non-zero if REG is not used after INSN.
6137 We assume REG is a reload reg, and therefore does
6138 not live past labels. It may live past calls or jumps though. */
6140 reg_unused_after (reg, insn)
6147 /* If the reg is set by this instruction, then it is safe for our
6148 case. Disregard the case where this is a store to memory, since
6149 we are checking a register used in the store address. */
6150 set = single_set (insn);
6151 if (set && GET_CODE (SET_DEST (set)) != MEM
6152 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6155 while ((insn = NEXT_INSN (insn)))
6157 code = GET_CODE (insn);
6160 /* If this is a label that existed before reload, then the register
6161 if dead here. However, if this is a label added by reorg, then
6162 the register may still be live here. We can't tell the difference,
6163 so we just ignore labels completely. */
6164 if (code == CODE_LABEL)
6169 if (code == JUMP_INSN)
6172 /* If this is a sequence, we must handle them all at once.
6173 We could have for instance a call that sets the target register,
6174 and an insn in a delay slot that uses the register. In this case,
6175 we must return 0. */
6176 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
6181 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
6183 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
6184 rtx set = single_set (this_insn);
6186 if (GET_CODE (this_insn) == CALL_INSN)
6188 else if (GET_CODE (this_insn) == JUMP_INSN)
6190 if (INSN_ANNULLED_BRANCH_P (this_insn))
6195 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
6197 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6199 if (GET_CODE (SET_DEST (set)) != MEM)
6205 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
6210 else if (code == JUMP_INSN)
6213 else if (GET_RTX_CLASS (code) == 'i')
6215 rtx set = single_set (insn);
6217 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
6219 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6220 return GET_CODE (SET_DEST (set)) != MEM;
6221 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
6225 if (code == CALL_INSN && call_used_regs[REGNO (reg)])
6236 static rtx fpscr_rtx;
6240 fpscr_rtx = gen_rtx (REG, PSImode, FPSCR_REG);
6241 REG_USERVAR_P (fpscr_rtx) = 1;
6242 ggc_add_rtx_root (&fpscr_rtx, 1);
6243 mark_user_reg (fpscr_rtx);
6245 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
6246 mark_user_reg (fpscr_rtx);
6265 expand_sf_unop (fun, operands)
6266 rtx (*fun) PARAMS ((rtx, rtx, rtx));
6269 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
6273 expand_sf_binop (fun, operands)
6274 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
6277 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
6282 expand_df_unop (fun, operands)
6283 rtx (*fun) PARAMS ((rtx, rtx, rtx));
6286 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
6290 expand_df_binop (fun, operands)
6291 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
6294 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
6298 /* ??? gcc does flow analysis strictly after common subexpression
6299 elimination. As a result, common subespression elimination fails
6300 when there are some intervening statements setting the same register.
6301 If we did nothing about this, this would hurt the precision switching
6302 for SH4 badly. There is some cse after reload, but it is unable to
6303 undo the extra register pressure from the unused instructions, and
6304 it cannot remove auto-increment loads.
6306 A C code example that shows this flow/cse weakness for (at least) SH
6307 and sparc (as of gcc ss-970706) is this:
6321 So we add another pass before common subexpression elimination, to
6322 remove assignments that are dead due to a following assignment in the
6323 same basic block. */
6326 mark_use (x, reg_set_block)
6327 rtx x, *reg_set_block;
6333 code = GET_CODE (x);
6338 int regno = REGNO (x);
6339 int nregs = (regno < FIRST_PSEUDO_REGISTER
6340 ? HARD_REGNO_NREGS (regno, GET_MODE (x))
6344 reg_set_block[regno + nregs - 1] = 0;
6351 rtx dest = SET_DEST (x);
6353 if (GET_CODE (dest) == SUBREG)
6354 dest = SUBREG_REG (dest);
6355 if (GET_CODE (dest) != REG)
6356 mark_use (dest, reg_set_block);
6357 mark_use (SET_SRC (x), reg_set_block);
6364 const char *fmt = GET_RTX_FORMAT (code);
6366 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6369 mark_use (XEXP (x, i), reg_set_block);
6370 else if (fmt[i] == 'E')
6371 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6372 mark_use (XVECEXP (x, i, j), reg_set_block);
6379 static rtx get_free_reg PARAMS ((HARD_REG_SET));
6381 /* This function returns a register to use to load the address to load
6382 the fpscr from. Currently it always returns r1 or r7, but when we are
6383 able to use pseudo registers after combine, or have a better mechanism
6384 for choosing a register, it should be done here. */
6385 /* REGS_LIVE is the liveness information for the point for which we
6386 need this allocation. In some bare-bones exit blocks, r1 is live at the
6387 start. We can even have all of r0..r3 being live:
6388 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
6389 INSN before which new insns are placed with will clobber the register
6390 we return. If a basic block consists only of setting the return value
6391 register to a pseudo and using that register, the return value is not
6392 live before or after this block, yet we we'll insert our insns right in
6396 get_free_reg (regs_live)
6397 HARD_REG_SET regs_live;
6399 if (! TEST_HARD_REG_BIT (regs_live, 1))
6400 return gen_rtx_REG (Pmode, 1);
6402 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
6403 there shouldn't be anything but a jump before the function end. */
6404 if (! TEST_HARD_REG_BIT (regs_live, 7))
6405 return gen_rtx_REG (Pmode, 7);
6410 /* This function will set the fpscr from memory.
6411 MODE is the mode we are setting it to. */
6413 fpscr_set_from_mem (mode, regs_live)
6415 HARD_REG_SET regs_live;
6417 enum attr_fp_mode fp_mode = mode;
6418 rtx addr_reg = get_free_reg (regs_live);
6420 if (fp_mode == (enum attr_fp_mode) NORMAL_MODE (FP_MODE))
6421 emit_insn (gen_fpu_switch1 (addr_reg));
6423 emit_insn (gen_fpu_switch0 (addr_reg));
6426 /* Is the given character a logical line separator for the assembler? */
6427 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
6428 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
6432 sh_insn_length_adjustment (insn)
6435 /* Instructions with unfilled delay slots take up an extra two bytes for
6436 the nop in the delay slot. */
6437 if (((GET_CODE (insn) == INSN
6438 && GET_CODE (PATTERN (insn)) != USE
6439 && GET_CODE (PATTERN (insn)) != CLOBBER)
6440 || GET_CODE (insn) == CALL_INSN
6441 || (GET_CODE (insn) == JUMP_INSN
6442 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
6443 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
6444 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
6445 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
6448 /* sh-dsp parallel processing insn take four bytes instead of two. */
6450 if (GET_CODE (insn) == INSN)
6453 rtx body = PATTERN (insn);
6454 const char *template;
6456 int maybe_label = 1;
6458 if (GET_CODE (body) == ASM_INPUT)
6459 template = XSTR (body, 0);
6460 else if (asm_noperands (body) >= 0)
6462 = decode_asm_operands (body, NULL, NULL, NULL, NULL);
6471 while (c == ' ' || c == '\t');
6472 /* all sh-dsp parallel-processing insns start with p.
6473 The only non-ppi sh insn starting with p is pref.
6474 The only ppi starting with pr is prnd. */
6475 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
6477 /* The repeat pseudo-insn expands two three insns, a total of
6478 six bytes in size. */
6479 else if ((c == 'r' || c == 'R')
6480 && ! strncasecmp ("epeat", template, 5))
6482 while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c))
6484 /* If this is a label, it is obviously not a ppi insn. */
6485 if (c == ':' && maybe_label)
6490 else if (c == '\'' || c == '"')
6495 maybe_label = c != ':';
6503 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
6504 isn't protected by a PIC unspec. */
6506 nonpic_symbol_mentioned_p (x)
6509 register const char *fmt;
6512 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
6513 || GET_CODE (x) == PC)
6516 /* We don't want to look into the possible MEM location of a
6517 CONST_DOUBLE, since we're not going to use it, in general. */
6518 if (GET_CODE (x) == CONST_DOUBLE)
6521 if (GET_CODE (x) == UNSPEC
6522 && (XINT (x, 1) == UNSPEC_PIC
6523 || XINT (x, 1) == UNSPEC_GOT
6524 || XINT (x, 1) == UNSPEC_GOTOFF
6525 || XINT (x, 1) == UNSPEC_GOTPLT
6526 || XINT (x, 1) == UNSPEC_PLT))
6529 fmt = GET_RTX_FORMAT (GET_CODE (x));
6530 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6536 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6537 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
6540 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
6547 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
6548 @GOTOFF in `reg'. */
6550 legitimize_pic_address (orig, mode, reg)
6552 enum machine_mode mode ATTRIBUTE_UNUSED;
6555 if (GET_CODE (orig) == LABEL_REF
6556 || (GET_CODE (orig) == SYMBOL_REF
6557 && (CONSTANT_POOL_ADDRESS_P (orig)
6558 /* SYMBOL_REF_FLAG is set on static symbols. */
6559 || SYMBOL_REF_FLAG (orig))))
6562 reg = gen_reg_rtx (Pmode);
6564 emit_insn (gen_symGOTOFF2reg (reg, orig));
6567 else if (GET_CODE (orig) == SYMBOL_REF)
6570 reg = gen_reg_rtx (Pmode);
6572 emit_insn (gen_symGOT2reg (reg, orig));
6578 /* Mark the use of a constant in the literal table. If the constant
6579 has multiple labels, make it unique. */
6580 static rtx mark_constant_pool_use (x)
6583 rtx insn, lab, pattern;
6588 switch (GET_CODE (x))
6598 /* Get the first label in the list of labels for the same constant
6599 and delete another labels in the list. */
6601 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
6603 if (GET_CODE (insn) != CODE_LABEL
6604 || LABEL_REFS (insn) != NEXT_INSN (insn))
6609 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
6610 INSN_DELETED_P (insn) = 1;
6612 /* Mark constants in a window. */
6613 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
6615 if (GET_CODE (insn) != INSN)
6618 pattern = PATTERN (insn);
6619 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
6622 switch (XINT (pattern, 1))
6624 case UNSPECV_CONST2:
6625 case UNSPECV_CONST4:
6626 case UNSPECV_CONST8:
6627 XVECEXP (pattern, 0, 1) = const1_rtx;
6629 case UNSPECV_WINDOW_END:
6630 if (XVECEXP (pattern, 0, 0) == x)
6633 case UNSPECV_CONST_END:
6643 /* Return true if it's possible to redirect BRANCH1 to the destination
6644 of an unconditional jump BRANCH2. We only want to do this if the
6645 resulting branch will have a short displacement. */
6647 sh_can_redirect_branch (branch1, branch2)
6651 if (flag_expensive_optimizations && simplejump_p (branch2))
6653 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
6657 for (distance = 0, insn = NEXT_INSN (branch1);
6658 insn && distance < 256;
6659 insn = PREV_INSN (insn))
6664 distance += get_attr_length (insn);
6666 for (distance = 0, insn = NEXT_INSN (branch1);
6667 insn && distance < 256;
6668 insn = NEXT_INSN (insn))
6673 distance += get_attr_length (insn);
6679 /* A C statement (sans semicolon) to update the integer variable COST
6680 based on the relationship between INSN that is dependent on
6681 DEP_INSN through the dependence LINK. The default is to make no
6682 adjustment to COST. This can be used for example to specify to
6683 the scheduler that an output- or anti-dependence does not incur
6684 the same cost as a data-dependence. */
6686 sh_adjust_cost (insn, link, dep_insn, cost)
6688 rtx link ATTRIBUTE_UNUSED;
6694 if (GET_CODE(insn) == CALL_INSN)
6696 /* The only input for a call that is timing-critical is the
6697 function's address. */
6698 rtx call = PATTERN (insn);
6700 if (GET_CODE (call) == PARALLEL)
6701 call = XVECEXP (call, 0 ,0);
6702 if (GET_CODE (call) == SET)
6703 call = SET_SRC (call);
6704 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
6705 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))
6708 /* All sfunc calls are parallels with at least four components.
6709 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
6710 else if (GET_CODE (PATTERN (insn)) == PARALLEL
6711 && XVECLEN (PATTERN (insn), 0) >= 4
6712 && (reg = sfunc_uses_reg (insn)))
6714 /* Likewise, the most timing critical input for an sfuncs call
6715 is the function address. However, sfuncs typically start
6716 using their arguments pretty quickly.
6717 Assume a four cycle delay before they are needed. */
6718 if (! reg_set_p (reg, dep_insn))
6719 cost -= TARGET_SUPERSCALAR ? 40 : 4;
6721 /* Adjust load_si / pcload_si type insns latency. Use the known
6722 nominal latency and form of the insn to speed up the check. */
6724 && GET_CODE (PATTERN (dep_insn)) == SET
6725 /* Latency for dmpy type insns is also 3, so check the that
6726 it's actually a move insn. */
6727 && general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode))
6730 && GET_CODE (PATTERN (dep_insn)) == SET
6731 && GET_MODE (SET_SRC (PATTERN (dep_insn))) == SImode)
6737 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
6738 'special function' patterns (type sfunc) that clobber pr, but that
6739 do not look like function calls to leaf_function_p. Hence we must
6740 do this extra check. */
6744 return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
6747 /* This Function Returns non zero if DFA based scheduler
6748 interface is to be used.At present supported only for
6751 sh_use_dfa_interface()
6759 /* This function returns "2" that signifies dual issue
6760 for SH4 processor.To be used by DFA pipeline description. */
6770 /* SHmedia requires registers for branches, so we can't generate new
6771 branches past reload. */
6773 sh_cannot_modify_jumps_p ()
6775 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
6779 sh_ms_bitfield_layout_p (record_type)
6780 tree record_type ATTRIBUTE_UNUSED;
6785 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
6786 may access it using GOTOFF instead of GOT. */
6789 sh_encode_section_info (decl, first)
6796 rtl = DECL_RTL (decl);
6798 rtl = TREE_CST_RTL (decl);
6799 if (GET_CODE (rtl) != MEM)
6801 symbol = XEXP (rtl, 0);
6802 if (GET_CODE (symbol) != SYMBOL_REF)
6806 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
6808 if (TARGET_SH5 && first && TREE_CODE (decl) != FUNCTION_DECL)
6809 XEXP (rtl, 0) = gen_datalabel_ref (symbol);
6812 /* Undo the effects of the above. */
6815 sh_strip_name_encoding (str)
6818 STRIP_DATALABEL_ENCODING (str, str);