1 ;; Predicate definitions for Renesas / SuperH SH.
2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; TODO: Add a comment here.
22 (define_predicate "trapping_target_operand"
23 (match_code "if_then_else")
25 rtx cond, mem, res, tar, and;
27 if (GET_MODE (op) != PDImode)
32 if (GET_CODE (mem) != MEM
33 || (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE))
36 if (!rtx_equal_p (XEXP (mem, 0), tar)
37 || GET_MODE (tar) != Pmode)
39 if (GET_CODE (cond) == CONST)
41 cond = XEXP (cond, 0);
42 if (!satisfies_constraint_Csy (tar))
44 if (GET_CODE (tar) == CONST)
47 else if (!arith_reg_operand (tar, VOIDmode)
48 && ! satisfies_constraint_Csy (tar))
50 if (GET_CODE (cond) != EQ)
53 return (GET_CODE (and) == AND
54 && rtx_equal_p (XEXP (and, 0), tar)
55 && GET_CODE (XEXP (and, 1)) == CONST_INT
56 && GET_CODE (XEXP (cond, 1)) == CONST_INT
57 && INTVAL (XEXP (and, 1)) == 3
58 && INTVAL (XEXP (cond, 1)) == 3);
61 ;; TODO: Add a comment here.
63 (define_predicate "and_operand"
64 (match_code "subreg,reg,const_int")
66 if (logical_operand (op, mode))
69 /* Check mshflo.l / mshflhi.l opportunities. */
72 && satisfies_constraint_J16 (op))
78 ;; Like arith_reg_dest, but this predicate is defined with
79 ;; define_special_predicate, not define_predicate.
81 (define_special_predicate "any_arith_reg_dest"
82 (match_code "subreg,reg")
84 return arith_reg_dest (op, mode);
87 ;; Like register_operand, but this predicate is defined with
88 ;; define_special_predicate, not define_predicate.
90 (define_special_predicate "any_register_operand"
91 (match_code "subreg,reg")
93 return register_operand (op, mode);
96 ;; Returns 1 if OP is a valid source operand for an arithmetic insn.
98 (define_predicate "arith_operand"
99 (match_code "subreg,reg,const_int,truncate")
101 if (arith_reg_operand (op, mode))
106 /* FIXME: We should be checking whether the CONST_INT fits in a
107 signed 16-bit here, but this causes reload_cse to crash when
108 attempting to transform a sequence of two 64-bit sets of the
109 same register from literal constants into a set and an add,
110 when the difference is too wide for an add. */
111 if (GET_CODE (op) == CONST_INT
112 || satisfies_constraint_Css (op))
114 else if (GET_CODE (op) == TRUNCATE
115 && GET_CODE (XEXP (op, 0)) == REG
116 && ! system_reg_operand (XEXP (op, 0), VOIDmode)
117 && (mode == VOIDmode || mode == GET_MODE (op))
118 && (GET_MODE_SIZE (GET_MODE (op))
119 < GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
120 && (! FP_REGISTER_P (REGNO (XEXP (op, 0)))
121 || GET_MODE_SIZE (GET_MODE (op)) == 4))
122 return register_operand (XEXP (op, 0), VOIDmode);
126 else if (satisfies_constraint_I08 (op))
132 ;; Like above, but for DImode destinations: forbid paradoxical DImode
133 ;; subregs, because this would lead to missing sign extensions when
134 ;; truncating from DImode to SImode.
136 (define_predicate "arith_reg_dest"
137 (match_code "subreg,reg")
139 if (mode == DImode && GET_CODE (op) == SUBREG
140 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
143 return arith_reg_operand (op, mode);
146 ;; Returns 1 if OP is a normal arithmetic register.
148 (define_predicate "arith_reg_operand"
149 (match_code "subreg,reg,sign_extend")
151 if (register_operand (op, mode))
155 if (GET_CODE (op) == REG)
157 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
158 regno = REGNO (SUBREG_REG (op));
162 return (regno != T_REG && regno != PR_REG
163 && ! TARGET_REGISTER_P (regno)
164 && (regno != FPUL_REG || TARGET_SH4)
165 && regno != MACH_REG && regno != MACL_REG);
167 /* Allow a no-op sign extension - compare LOAD_EXTEND_OP.
168 We allow SImode here, as not using an FP register is just a matter of
169 proper register allocation. */
171 && GET_MODE (op) == DImode && GET_CODE (op) == SIGN_EXTEND
172 && GET_MODE (XEXP (op, 0)) == SImode
173 && GET_CODE (XEXP (op, 0)) != SUBREG)
174 return register_operand (XEXP (op, 0), VOIDmode);
175 #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */
176 if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND
177 && GET_MODE (XEXP (op, 0)) == HImode
178 && GET_CODE (XEXP (op, 0)) == REG
179 && REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG)
180 return register_operand (XEXP (op, 0), VOIDmode);
182 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT
183 && GET_CODE (op) == SUBREG
184 && GET_MODE (SUBREG_REG (op)) == DImode
185 && GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND
186 && GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode
187 && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG)
188 return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode);
192 ;; Returns 1 if OP is a valid source operand for a compare insn.
194 (define_predicate "arith_reg_or_0_operand"
195 (match_code "subreg,reg,const_int,const_vector")
197 if (arith_reg_operand (op, mode))
200 if (satisfies_constraint_Z (op))
206 ;; TODO: Add a comment here.
208 (define_predicate "binary_float_operator"
209 (and (match_code "plus,minus,mult,div")
210 (match_test "GET_MODE (op) == mode")))
212 ;; TODO: Add a comment here.
214 (define_predicate "binary_logical_operator"
215 (and (match_code "and,ior,xor")
216 (match_test "GET_MODE (op) == mode")))
218 ;; Return 1 of OP is an address suitable for a cache manipulation operation.
219 ;; MODE has the meaning as in address_operand.
221 (define_special_predicate "cache_address_operand"
222 (match_code "plus,reg")
224 if (GET_CODE (op) == PLUS)
226 if (GET_CODE (XEXP (op, 0)) != REG)
228 if (GET_CODE (XEXP (op, 1)) != CONST_INT
229 || (INTVAL (XEXP (op, 1)) & 31))
232 else if (GET_CODE (op) != REG)
234 return address_operand (op, mode);
237 ;; Return 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu.
239 (define_predicate "cmp_operand"
240 (match_code "subreg,reg,const_int")
242 if (satisfies_constraint_N (op))
245 && mode != DImode && GET_CODE (op) == SUBREG
246 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
248 return arith_reg_operand (op, mode);
251 ;; TODO: Add a comment here.
253 (define_predicate "cmpsi_operand"
254 (match_code "subreg,reg,const_int")
256 if (GET_CODE (op) == REG && REGNO (op) == T_REG
257 && GET_MODE (op) == SImode
260 return arith_operand (op, mode);
263 ;; TODO: Add a comment here.
265 (define_predicate "commutative_float_operator"
266 (and (match_code "plus,mult")
267 (match_test "GET_MODE (op) == mode")))
269 ;; TODO: Add a comment here.
271 (define_predicate "equality_comparison_operator"
272 (match_code "eq,ne"))
274 ;; TODO: Add a comment here.
276 (define_predicate "extend_reg_operand"
277 (match_code "subreg,reg,truncate")
279 return (GET_CODE (op) == TRUNCATE
281 : arith_reg_operand) (op, mode);
284 ;; TODO: Add a comment here.
286 (define_predicate "extend_reg_or_0_operand"
287 (match_code "subreg,reg,truncate,const_int")
289 return (GET_CODE (op) == TRUNCATE
291 : arith_reg_or_0_operand) (op, mode);
294 ;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND.
296 (define_predicate "ext_dest_operand"
297 (match_code "subreg,reg")
299 return arith_reg_operand (op, mode);
302 ;; TODO: Add a comment here.
304 (define_predicate "fp_arith_reg_dest"
305 (match_code "subreg,reg")
307 if (mode == DImode && GET_CODE (op) == SUBREG
308 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
310 return fp_arith_reg_operand (op, mode);
313 ;; TODO: Add a comment here.
315 (define_predicate "fp_arith_reg_operand"
316 (match_code "subreg,reg")
318 if (register_operand (op, mode))
322 if (GET_CODE (op) == REG)
324 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
325 regno = REGNO (SUBREG_REG (op));
329 return (regno >= FIRST_PSEUDO_REGISTER
330 || FP_REGISTER_P (regno));
335 ;; TODO: Add a comment here.
337 (define_predicate "fpscr_operand"
340 return (GET_CODE (op) == REG
341 && (REGNO (op) == FPSCR_REG
342 || (REGNO (op) >= FIRST_PSEUDO_REGISTER
343 && !(reload_in_progress || reload_completed)))
344 && GET_MODE (op) == PSImode);
347 ;; TODO: Add a comment here.
349 (define_predicate "fpul_operand"
353 return fp_arith_reg_operand (op, mode);
355 return (GET_CODE (op) == REG
356 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
357 && GET_MODE (op) == mode);
360 ;; TODO: Add a comment here.
362 (define_predicate "general_extend_operand"
363 (match_code "subreg,reg,mem,truncate")
365 return (GET_CODE (op) == TRUNCATE
367 : nonimmediate_operand) (op, mode);
370 ;; Returns 1 if OP can be source of a simple move operation. Same as
371 ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as
372 ;; are subregs of system registers.
374 (define_predicate "general_movsrc_operand"
375 (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector")
377 if (GET_CODE (op) == MEM)
379 rtx inside = XEXP (op, 0);
380 if (GET_CODE (inside) == CONST)
381 inside = XEXP (inside, 0);
383 if (GET_CODE (inside) == LABEL_REF)
386 if (GET_CODE (inside) == PLUS
387 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
388 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
391 /* Only post inc allowed. */
392 if (GET_CODE (inside) == PRE_DEC)
397 && (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR)
398 && sh_rep_vec (op, mode))
400 if (TARGET_SHMEDIA && 1
401 && GET_CODE (op) == SUBREG && GET_MODE (op) == mode
402 && SUBREG_REG (op) == const0_rtx && subreg_lowpart_p (op))
403 /* FIXME */ abort (); /* return 1; */
404 return general_operand (op, mode);
407 ;; Returns 1 if OP can be a destination of a move. Same as
408 ;; general_operand, but no preinc allowed.
410 (define_predicate "general_movdst_operand"
411 (match_code "subreg,reg,mem")
413 /* Only pre dec allowed. */
414 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
416 if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG
417 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
418 && ! (high_life_started || reload_completed))
421 return general_operand (op, mode);
424 ;; Returns 1 if OP is a MEM that can be source of a simple move operation.
426 (define_predicate "unaligned_load_operand"
431 if (GET_CODE (op) != MEM || GET_MODE (op) != mode)
434 inside = XEXP (op, 0);
436 if (GET_CODE (inside) == POST_INC)
437 inside = XEXP (inside, 0);
439 if (GET_CODE (inside) == REG)
445 ;; TODO: Add a comment here.
447 (define_predicate "greater_comparison_operator"
448 (match_code "gt,ge,gtu,geu"))
450 ;; TODO: Add a comment here.
452 (define_predicate "inqhi_operand"
453 (match_code "truncate")
455 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
458 /* Can't use true_regnum here because copy_cost wants to know about
459 SECONDARY_INPUT_RELOAD_CLASS. */
460 return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
463 ;; TODO: Add a comment here.
465 (define_special_predicate "int_gpr_dest"
466 (match_code "subreg,reg")
468 enum machine_mode op_mode = GET_MODE (op);
470 if (GET_MODE_CLASS (op_mode) != MODE_INT
471 || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
473 if (! reload_completed)
475 return true_regnum (op) <= LAST_GENERAL_REG;
478 ;; TODO: Add a comment here.
480 (define_predicate "less_comparison_operator"
481 (match_code "lt,le,ltu,leu"))
483 ;; Returns 1 if OP is a valid source operand for a logical operation.
485 (define_predicate "logical_operand"
486 (match_code "subreg,reg,const_int")
489 && mode != DImode && GET_CODE (op) == SUBREG
490 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
493 if (arith_reg_operand (op, mode))
498 if (satisfies_constraint_I10 (op))
503 else if (satisfies_constraint_K08 (op))
509 ;; TODO: Add a comment here.
511 (define_predicate "logical_operator"
512 (match_code "and,ior,xor"))
514 ;; Like arith_reg_operand, but for register source operands of narrow
515 ;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs.
517 (define_predicate "logical_reg_operand"
518 (match_code "subreg,reg")
521 && GET_CODE (op) == SUBREG
522 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4
525 return arith_reg_operand (op, mode);
528 ;; TODO: Add a comment here.
530 (define_predicate "mextr_bit_offset"
531 (match_code "const_int")
535 if (GET_CODE (op) != CONST_INT)
538 return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
541 ;; TODO: Add a comment here.
543 (define_predicate "minuend_operand"
544 (match_code "subreg,reg,truncate,const_int")
546 return op == constm1_rtx || extend_reg_or_0_operand (op, mode);
549 ;; TODO: Add a comment here.
551 (define_predicate "noncommutative_float_operator"
552 (and (match_code "minus,div")
553 (match_test "GET_MODE (op) == mode")))
555 ;; TODO: Add a comment here.
557 (define_predicate "sh_const_vec"
558 (match_code "const_vector")
562 if (GET_CODE (op) != CONST_VECTOR
563 || (GET_MODE (op) != mode && mode != VOIDmode))
565 i = XVECLEN (op, 0) - 1;
567 if (GET_CODE (XVECEXP (op, 0, i)) != CONST_INT)
572 ;; Determine if OP is a constant vector matching MODE with only one
573 ;; element that is not a sign extension. Two byte-sized elements
576 (define_predicate "sh_1el_vec"
577 (match_code "const_vector")
580 int i, last, least, sign_ix;
583 if (GET_CODE (op) != CONST_VECTOR
584 || (GET_MODE (op) != mode && mode != VOIDmode))
586 /* Determine numbers of last and of least significant elements. */
587 last = XVECLEN (op, 0) - 1;
588 least = TARGET_LITTLE_ENDIAN ? 0 : last;
589 if (GET_CODE (XVECEXP (op, 0, least)) != CONST_INT)
592 if (GET_MODE_UNIT_SIZE (mode) == 1)
593 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
594 if (GET_CODE (XVECEXP (op, 0, sign_ix)) != CONST_INT)
596 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op));
597 sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
598 ? constm1_rtx : const0_rtx);
599 i = XVECLEN (op, 0) - 1;
601 if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign)
607 ;; Like register_operand, but take into account that SHMEDIA can use
608 ;; the constant zero like a general register.
610 (define_predicate "sh_register_operand"
611 (match_code "reg,subreg,const_int,const_double")
613 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
615 return register_operand (op, mode);
618 ;; TODO: Add a comment here.
620 (define_predicate "sh_rep_vec"
621 (match_code "const_vector,parallel")
626 if ((GET_CODE (op) != CONST_VECTOR && GET_CODE (op) != PARALLEL)
627 || (GET_MODE (op) != mode && mode != VOIDmode))
629 i = XVECLEN (op, 0) - 2;
630 x = XVECEXP (op, 0, i + 1);
631 if (GET_MODE_UNIT_SIZE (mode) == 1)
633 y = XVECEXP (op, 0, i);
634 for (i -= 2; i >= 0; i -= 2)
635 if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x)
636 || ! rtx_equal_p (XVECEXP (op, 0, i), y))
641 if (XVECEXP (op, 0, i) != x)
646 ;; TODO: Add a comment here.
648 (define_predicate "shift_count_operand"
649 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,zero_extend,sign_extend")
651 return (CONSTANT_P (op)
652 ? (GET_CODE (op) == CONST_INT
653 ? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode)
654 : nonmemory_operand (op, mode))
655 : shift_count_reg_operand (op, mode));
658 ;; TODO: Add a comment here.
660 (define_predicate "shift_count_reg_operand"
661 (match_code "subreg,reg,zero_extend,sign_extend")
663 if ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
664 || (GET_CODE (op) == SUBREG && SUBREG_BYTE (op) == 0))
665 && (mode == VOIDmode || mode == GET_MODE (op))
666 && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
667 && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT)
672 while ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
673 || GET_CODE (op) == TRUNCATE)
674 && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
675 && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT);
678 return arith_reg_operand (op, mode);
681 ;; TODO: Add a comment here.
683 (define_predicate "shift_operator"
684 (match_code "ashift,ashiftrt,lshiftrt"))
686 ;; TODO: Add a comment here.
688 (define_predicate "symbol_ref_operand"
689 (match_code "symbol_ref"))
691 ;; Same as target_reg_operand, except that label_refs and symbol_refs
692 ;; are accepted before reload.
694 (define_special_predicate "target_operand"
695 (match_code "subreg,reg,label_ref,symbol_ref,const,unspec")
697 if (mode != VOIDmode && mode != Pmode)
700 if ((GET_MODE (op) == Pmode || GET_MODE (op) == VOIDmode)
701 && satisfies_constraint_Csy (op))
702 return ! reload_completed;
704 return target_reg_operand (op, mode);
707 ;; Accept pseudos and branch target registers.
709 (define_special_predicate "target_reg_operand"
710 (match_code "subreg,reg")
713 ? GET_MODE (op) != Pmode && GET_MODE (op) != PDImode
714 : mode != GET_MODE (op))
717 if (GET_CODE (op) == SUBREG)
720 if (GET_CODE (op) != REG)
723 /* We must protect ourselves from matching pseudos that are virtual
724 register, because they will eventually be replaced with hardware
725 registers that aren't branch-target registers. */
726 if (REGNO (op) > LAST_VIRTUAL_REGISTER
727 || TARGET_REGISTER_P (REGNO (op)))
733 ;; TODO: Add a comment here.
735 (define_special_predicate "trunc_hi_operand"
736 (match_code "subreg,reg,truncate")
738 enum machine_mode op_mode = GET_MODE (op);
740 if (op_mode != SImode && op_mode != DImode
741 && op_mode != V4HImode && op_mode != V2SImode)
743 return extend_reg_operand (op, mode);
746 ;; Return 1 of OP is an address suitable for an unaligned access instruction.
748 (define_special_predicate "ua_address_operand"
749 (match_code "subreg,reg,plus")
751 if (GET_CODE (op) == PLUS
752 && (! satisfies_constraint_I06 (XEXP (op, 1))))
754 return address_operand (op, QImode);
757 ;; TODO: Add a comment here.
759 (define_predicate "ua_offset"
760 (match_code "const_int")
762 return satisfies_constraint_I06 (op);
765 ;; TODO: Add a comment here.
767 (define_predicate "unary_float_operator"
768 (and (match_code "abs,neg,sqrt")
769 (match_test "GET_MODE (op) == mode")))
771 ;; Return 1 if OP is a valid source operand for xor.
773 (define_predicate "xor_operand"
774 (match_code "subreg,reg,const_int")
776 if (GET_CODE (op) == CONST_INT)
777 return (TARGET_SHMEDIA
778 ? (satisfies_constraint_I06 (op)
779 || (!can_create_pseudo_p () && INTVAL (op) == 0xff))
780 : satisfies_constraint_K08 (op));
782 && mode != DImode && GET_CODE (op) == SUBREG
783 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
785 return arith_reg_operand (op, mode);
788 (define_predicate "bitwise_memory_operand"
791 if (GET_CODE (op) == MEM)
793 if (REG_P (XEXP (op, 0)))
796 if (GET_CODE (XEXP (op, 0)) == PLUS
797 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
798 && satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1)))