1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;; Special constraints for s/390 machine description:
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
33 ;; Special formats used for outputting 390 instructions.
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
42 ;; We have a special constraint for pattern matching.
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
52 [; TLS relocation specifiers
57 (UNSPEC_GOTNTPOFF 504)
58 (UNSPEC_INDNTPOFF 505)
62 (UNSPEC_TLSLDM_NTPOFF 511)
67 ;; UNSPEC_VOLATILE usage
76 ;; Processor type. This attribute must exactly match the processor_type
77 ;; enumeration in s390.h.
79 (define_attr "cpu" "g5,g6,z900"
80 (const (symbol_ref "s390_cpu")))
82 ;; Define an insn type attribute. This is used in function unit delay
85 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
86 cs,vs,store,imul,idiv,
87 branch,jsr,fsimpd,fsimps,
88 floadd,floads,fstored, fstores,
89 fmuld,fmuls,fdivd,fdivs,
90 ftoi,itof,fsqrtd,fsqrts,
92 (const_string "integer"))
94 ;; Operand type. Used to default length attribute values
96 (define_attr "op_type"
97 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
100 ;; Insn are devide in two classes:
101 ;; agen: Insn using agen
102 ;; reg: Insn not using agen
104 (define_attr "atype" "agen,reg"
105 (cond [ (eq_attr "op_type" "E") (const_string "reg")
106 (eq_attr "op_type" "RR") (const_string "reg")
107 (eq_attr "op_type" "RX") (const_string "agen")
108 (eq_attr "op_type" "RI") (const_string "reg")
109 (eq_attr "op_type" "RRE") (const_string "reg")
110 (eq_attr "op_type" "RS") (const_string "agen")
111 (eq_attr "op_type" "RSI") (const_string "agen")
112 (eq_attr "op_type" "S") (const_string "agen")
113 (eq_attr "op_type" "SI") (const_string "agen")
114 (eq_attr "op_type" "SS") (const_string "agen")
115 (eq_attr "op_type" "SSE") (const_string "agen")
116 (eq_attr "op_type" "RXE") (const_string "agen")
117 (eq_attr "op_type" "RSE") (const_string "agen")
118 (eq_attr "op_type" "RIL") (const_string "agen")]
119 (const_string "reg")))
121 ;; Generic pipeline function unit.
123 (define_function_unit "integer" 1 0
124 (eq_attr "type" "none") 0 0)
126 (define_function_unit "integer" 1 0
127 (eq_attr "type" "integer") 1 1)
129 (define_function_unit "integer" 1 0
130 (eq_attr "type" "fsimpd") 1 1)
132 (define_function_unit "integer" 1 0
133 (eq_attr "type" "fsimps") 1 1)
135 (define_function_unit "integer" 1 0
136 (eq_attr "type" "load") 1 1)
138 (define_function_unit "integer" 1 0
139 (eq_attr "type" "floadd") 1 1)
141 (define_function_unit "integer" 1 0
142 (eq_attr "type" "floads") 1 1)
144 (define_function_unit "integer" 1 0
145 (eq_attr "type" "la") 1 1)
147 (define_function_unit "integer" 1 0
148 (eq_attr "type" "larl") 1 1)
150 (define_function_unit "integer" 1 0
151 (eq_attr "type" "lr") 1 1)
153 (define_function_unit "integer" 1 0
154 (eq_attr "type" "branch") 1 1)
156 (define_function_unit "integer" 1 0
157 (eq_attr "type" "store") 1 1)
159 (define_function_unit "integer" 1 0
160 (eq_attr "type" "fstored") 1 1)
162 (define_function_unit "integer" 1 0
163 (eq_attr "type" "fstores") 1 1)
165 (define_function_unit "integer" 1 0
166 (eq_attr "type" "lm") 2 2)
168 (define_function_unit "integer" 1 0
169 (eq_attr "type" "stm") 2 2)
171 (define_function_unit "integer" 1 0
172 (eq_attr "type" "cs") 5 5)
174 (define_function_unit "integer" 1 0
175 (eq_attr "type" "vs") 30 30)
177 (define_function_unit "integer" 1 0
178 (eq_attr "type" "jsr") 5 5)
180 (define_function_unit "integer" 1 0
181 (eq_attr "type" "imul") 7 7)
183 (define_function_unit "integer" 1 0
184 (eq_attr "type" "fmuld") 6 6)
186 (define_function_unit "integer" 1 0
187 (eq_attr "type" "fmuls") 6 6)
189 (define_function_unit "integer" 1 0
190 (eq_attr "type" "idiv") 33 33)
192 (define_function_unit "integer" 1 0
193 (eq_attr "type" "fdivd") 33 33)
195 (define_function_unit "integer" 1 0
196 (eq_attr "type" "fdivs") 33 33)
198 (define_function_unit "integer" 1 0
199 (eq_attr "type" "fsqrtd") 30 30)
201 (define_function_unit "integer" 1 0
202 (eq_attr "type" "fsqrts") 30 30)
204 (define_function_unit "integer" 1 0
205 (eq_attr "type" "ftoi") 2 2)
207 (define_function_unit "integer" 1 0
208 (eq_attr "type" "itof") 2 2)
210 (define_function_unit "integer" 1 0
211 (eq_attr "type" "o2") 2 2)
213 (define_function_unit "integer" 1 0
214 (eq_attr "type" "o3") 3 3)
216 (define_function_unit "integer" 1 0
217 (eq_attr "type" "other") 5 5)
219 ;; Pipeline description for z900
225 (define_attr "length" ""
226 (cond [ (eq_attr "op_type" "E") (const_int 2)
227 (eq_attr "op_type" "RR") (const_int 2)
228 (eq_attr "op_type" "RX") (const_int 4)
229 (eq_attr "op_type" "RI") (const_int 4)
230 (eq_attr "op_type" "RRE") (const_int 4)
231 (eq_attr "op_type" "RS") (const_int 4)
232 (eq_attr "op_type" "RSI") (const_int 4)
233 (eq_attr "op_type" "S") (const_int 4)
234 (eq_attr "op_type" "SI") (const_int 4)
235 (eq_attr "op_type" "SS") (const_int 6)
236 (eq_attr "op_type" "SSE") (const_int 6)
237 (eq_attr "op_type" "RXE") (const_int 6)
238 (eq_attr "op_type" "RSE") (const_int 6)
239 (eq_attr "op_type" "RIL") (const_int 6)]
242 ;; Define attributes for `asm' insns.
244 (define_asm_attributes [(set_attr "type" "other")
245 (set_attr "op_type" "NN")])
251 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
252 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
253 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
254 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
255 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
258 ; CCZ1 -> CCA/CCU/CCS/CCT
261 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
262 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
266 ;;- Compare instructions.
269 (define_expand "cmpdi"
271 (compare:CC (match_operand:DI 0 "register_operand" "")
272 (match_operand:DI 1 "general_operand" "")))]
276 s390_compare_op0 = operands[0];
277 s390_compare_op1 = operands[1];
281 (define_expand "cmpsi"
283 (compare:CC (match_operand:SI 0 "register_operand" "")
284 (match_operand:SI 1 "general_operand" "")))]
288 s390_compare_op0 = operands[0];
289 s390_compare_op1 = operands[1];
293 (define_expand "cmpdf"
295 (compare:CC (match_operand:DF 0 "register_operand" "")
296 (match_operand:DF 1 "general_operand" "")))]
300 s390_compare_op0 = operands[0];
301 s390_compare_op1 = operands[1];
305 (define_expand "cmpsf"
307 (compare:CC (match_operand:SF 0 "register_operand" "")
308 (match_operand:SF 1 "general_operand" "")))]
312 s390_compare_op0 = operands[0];
313 s390_compare_op1 = operands[1];
318 ; Test-under-Mask (zero_extract) instructions
320 (define_insn "*tmdi_ext"
322 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
323 (match_operand:DI 1 "const_int_operand" "n")
324 (match_operand:DI 2 "const_int_operand" "n"))
326 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
327 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
328 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
329 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
330 == INTVAL (operands[2]) >> 4"
333 int part = INTVAL (operands[2]) >> 4;
334 int block = (1 << INTVAL (operands[1])) - 1;
335 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
337 operands[2] = GEN_INT (block << shift);
341 case 0: return \"tmhh\\t%0,%x2\";
342 case 1: return \"tmhl\\t%0,%x2\";
343 case 2: return \"tmlh\\t%0,%x2\";
344 case 3: return \"tmll\\t%0,%x2\";
348 [(set_attr "op_type" "RI")])
350 (define_insn "*tmsi_ext"
352 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
353 (match_operand:SI 1 "const_int_operand" "n")
354 (match_operand:SI 2 "const_int_operand" "n"))
356 "s390_match_ccmode(insn, CCTmode)
357 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
358 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
359 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
360 == INTVAL (operands[2]) >> 4"
363 int part = INTVAL (operands[2]) >> 4;
364 int block = (1 << INTVAL (operands[1])) - 1;
365 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
367 operands[2] = GEN_INT (block << shift);
371 case 0: return \"tmh\\t%0,%x2\";
372 case 1: return \"tml\\t%0,%x2\";
376 [(set_attr "op_type" "RI")])
378 (define_insn "*tmqi_ext"
380 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
381 (match_operand:SI 1 "const_int_operand" "n")
382 (match_operand:SI 2 "const_int_operand" "n"))
384 "s390_match_ccmode(insn, CCTmode)
385 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
386 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
389 int block = (1 << INTVAL (operands[1])) - 1;
390 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
392 operands[2] = GEN_INT (block << shift);
393 return \"tm\\t%0,%b2\";
395 [(set_attr "op_type" "SI")])
397 ; Test-under-Mask instructions
399 (define_insn "*tmdi_mem"
401 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
402 (match_operand:DI 1 "immediate_operand" "n"))
403 (match_operand:DI 2 "immediate_operand" "n")))]
405 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
406 && s390_single_qi (operands[1], DImode, 0) >= 0"
409 int part = s390_single_qi (operands[1], DImode, 0);
410 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
412 operands[0] = gen_rtx_MEM (QImode,
413 plus_constant (XEXP (operands[0], 0), part));
414 return \"tm\\t%0,%b1\";
416 [(set_attr "op_type" "SI")])
418 (define_insn "*tmsi_mem"
420 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
421 (match_operand:SI 1 "immediate_operand" "n"))
422 (match_operand:SI 2 "immediate_operand" "n")))]
423 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
424 && s390_single_qi (operands[1], SImode, 0) >= 0"
427 int part = s390_single_qi (operands[1], SImode, 0);
428 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
430 operands[0] = gen_rtx_MEM (QImode,
431 plus_constant (XEXP (operands[0], 0), part));
432 return \"tm\\t%0,%b1\";
434 [(set_attr "op_type" "SI")])
436 (define_insn "*tmhi_mem"
438 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
439 (match_operand:SI 1 "immediate_operand" "n"))
440 (match_operand:SI 2 "immediate_operand" "n")))]
441 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
442 && s390_single_qi (operands[1], HImode, 0) >= 0"
445 int part = s390_single_qi (operands[1], HImode, 0);
446 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
448 operands[0] = gen_rtx_MEM (QImode,
449 plus_constant (XEXP (operands[0], 0), part));
450 return \"tm\\t%0,%b1\";
452 [(set_attr "op_type" "SI")])
454 (define_insn "*tmqi_mem"
456 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
457 (match_operand:SI 1 "immediate_operand" "n"))
458 (match_operand:SI 2 "immediate_operand" "n")))]
459 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
461 [(set_attr "op_type" "SI")])
463 (define_insn "*tmdi_reg"
465 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
466 (match_operand:DI 1 "immediate_operand" "n"))
467 (match_operand:DI 2 "immediate_operand" "n")))]
469 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
470 && s390_single_hi (operands[1], DImode, 0) >= 0"
473 int part = s390_single_hi (operands[1], DImode, 0);
474 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
478 case 0: return \"tmhh\\t%0,%x1\";
479 case 1: return \"tmhl\\t%0,%x1\";
480 case 2: return \"tmlh\\t%0,%x1\";
481 case 3: return \"tmll\\t%0,%x1\";
485 [(set_attr "op_type" "RI")])
487 (define_insn "*tmsi_reg"
489 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
490 (match_operand:SI 1 "immediate_operand" "n"))
491 (match_operand:SI 2 "immediate_operand" "n")))]
492 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
493 && s390_single_hi (operands[1], SImode, 0) >= 0"
496 int part = s390_single_hi (operands[1], SImode, 0);
497 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
501 case 0: return \"tmh\\t%0,%x1\";
502 case 1: return \"tml\\t%0,%x1\";
506 [(set_attr "op_type" "RI")])
508 (define_insn "*tmhi_full"
510 (compare (match_operand:HI 0 "register_operand" "d")
511 (match_operand:HI 1 "immediate_operand" "n")))]
512 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
514 [(set_attr "op_type" "RX")])
516 (define_insn "*tmqi_full"
518 (compare (match_operand:QI 0 "register_operand" "d")
519 (match_operand:QI 1 "immediate_operand" "n")))]
520 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
522 [(set_attr "op_type" "RI")])
525 ; Load-and-Test instructions
527 (define_insn "*tstdi_sign"
529 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
530 (const_int 32)) (const_int 32))
531 (match_operand:DI 1 "const0_operand" "")))
532 (set (match_operand:DI 2 "register_operand" "=d")
533 (sign_extend:DI (match_dup 0)))]
534 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
536 [(set_attr "op_type" "RRE")])
538 (define_insn "*tstdi"
540 (compare (match_operand:DI 0 "register_operand" "d")
541 (match_operand:DI 1 "const0_operand" "")))
542 (set (match_operand:DI 2 "register_operand" "=d")
544 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
546 [(set_attr "op_type" "RRE")])
548 (define_insn "*tstdi_cconly"
550 (compare (match_operand:DI 0 "register_operand" "d")
551 (match_operand:DI 1 "const0_operand" "")))]
552 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
554 [(set_attr "op_type" "RRE")])
556 (define_insn "*tstdi_cconly_31"
558 (compare (match_operand:DI 0 "register_operand" "d")
559 (match_operand:DI 1 "const0_operand" "")))]
560 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
562 [(set_attr "op_type" "RS")
563 (set_attr "atype" "reg")])
566 (define_insn "*tstsi"
568 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
569 (match_operand:SI 1 "const0_operand" "")))
570 (set (match_operand:SI 2 "register_operand" "=d,d")
572 "s390_match_ccmode(insn, CCSmode)"
576 [(set_attr "op_type" "RR,RS")])
578 (define_insn "*tstsi_cconly"
580 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
581 (match_operand:SI 1 "const0_operand" "")))
582 (clobber (match_scratch:SI 2 "=X,d"))]
583 "s390_match_ccmode(insn, CCSmode)"
587 [(set_attr "op_type" "RR,RS")])
589 (define_insn "*tstsi_cconly2"
591 (compare (match_operand:SI 0 "register_operand" "d")
592 (match_operand:SI 1 "const0_operand" "")))]
593 "s390_match_ccmode(insn, CCSmode)"
595 [(set_attr "op_type" "RR")])
597 (define_insn "*tsthiCCT"
599 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
600 (match_operand:HI 1 "const0_operand" "")))
601 (set (match_operand:HI 2 "register_operand" "=d,0")
603 "s390_match_ccmode(insn, CCTmode)"
607 [(set_attr "op_type" "RS,RI")])
609 (define_insn "*tsthiCCT_cconly"
611 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,d")
612 (match_operand:HI 1 "const0_operand" "")))
613 (clobber (match_scratch:HI 2 "=d,X"))]
614 "s390_match_ccmode(insn, CCTmode)"
618 [(set_attr "op_type" "RS,RI")])
620 (define_insn "*tsthi"
622 (compare (match_operand:HI 0 "s_operand" "Q")
623 (match_operand:HI 1 "const0_operand" "")))
624 (set (match_operand:HI 2 "register_operand" "=d")
626 "s390_match_ccmode(insn, CCSmode)"
628 [(set_attr "op_type" "RS")])
630 (define_insn "*tsthi_cconly"
632 (compare (match_operand:HI 0 "s_operand" "Q")
633 (match_operand:HI 1 "const0_operand" "")))
634 (clobber (match_scratch:HI 2 "=d"))]
635 "s390_match_ccmode(insn, CCSmode)"
637 [(set_attr "op_type" "RS")])
639 (define_insn "*tstqiCCT"
641 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
642 (match_operand:QI 1 "const0_operand" "")))
643 (set (match_operand:QI 2 "register_operand" "=d,0")
645 "s390_match_ccmode(insn, CCTmode)"
649 [(set_attr "op_type" "RS,RI")])
651 (define_insn "*tstqiCCT_cconly"
653 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
654 (match_operand:QI 1 "const0_operand" "")))]
655 "s390_match_ccmode(insn, CCTmode)"
659 [(set_attr "op_type" "SI,RI")])
661 (define_insn "*tstqi"
663 (compare (match_operand:QI 0 "s_operand" "Q")
664 (match_operand:QI 1 "const0_operand" "")))
665 (set (match_operand:QI 2 "register_operand" "=d")
667 "s390_match_ccmode(insn, CCSmode)"
669 [(set_attr "op_type" "RS")])
671 (define_insn "*tstqi_cconly"
673 (compare (match_operand:QI 0 "s_operand" "Q")
674 (match_operand:QI 1 "const0_operand" "")))
675 (clobber (match_scratch:QI 2 "=d"))]
676 "s390_match_ccmode(insn, CCSmode)"
678 [(set_attr "op_type" "RS")])
680 ; Compare (signed) instructions
682 (define_insn "*cmpdi_ccs_sign"
684 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
685 (match_operand:DI 0 "register_operand" "d,d")))]
686 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
690 [(set_attr "op_type" "RRE,RXE")])
692 (define_insn "*cmpdi_ccs"
694 (compare (match_operand:DI 0 "register_operand" "d,d,d")
695 (match_operand:DI 1 "general_operand" "d,K,m")))]
696 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
701 [(set_attr "op_type" "RRE,RI,RXE")])
703 (define_insn "*cmpsi_ccs_sign"
705 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
706 (match_operand:SI 0 "register_operand" "d")))]
707 "s390_match_ccmode(insn, CCSRmode)"
709 [(set_attr "op_type" "RX")])
711 (define_insn "*cmpsi_ccs"
713 (compare (match_operand:SI 0 "register_operand" "d,d,d")
714 (match_operand:SI 1 "general_operand" "d,K,m")))]
715 "s390_match_ccmode(insn, CCSmode)"
720 [(set_attr "op_type" "RR,RI,RX")])
723 ; Compare (unsigned) instructions
725 (define_insn "*cmpdi_ccu_zero"
727 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
728 (match_operand:DI 0 "register_operand" "d,d")))]
729 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
733 [(set_attr "op_type" "RRE,RXE")])
735 (define_insn "*cmpdi_ccu"
737 (compare (match_operand:DI 0 "register_operand" "d,d")
738 (match_operand:DI 1 "general_operand" "d,m")))]
739 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
743 [(set_attr "op_type" "RRE,RXE")])
745 (define_insn "*cmpsi_ccu"
747 (compare (match_operand:SI 0 "register_operand" "d,d")
748 (match_operand:SI 1 "general_operand" "d,m")))]
749 "s390_match_ccmode(insn, CCUmode)"
753 [(set_attr "op_type" "RR,RX")])
755 (define_insn "*cmphi_ccu"
757 (compare (match_operand:HI 0 "register_operand" "d")
758 (match_operand:HI 1 "s_imm_operand" "Q")))]
759 "s390_match_ccmode(insn, CCUmode)"
761 [(set_attr "op_type" "RS")])
763 (define_insn "*cmpqi_ccu"
765 (compare (match_operand:QI 0 "register_operand" "d")
766 (match_operand:QI 1 "s_imm_operand" "Q")))]
767 "s390_match_ccmode(insn, CCUmode)"
769 [(set_attr "op_type" "RS")])
773 (compare (match_operand:QI 0 "memory_operand" "Q")
774 (match_operand:QI 1 "immediate_operand" "n")))]
775 "s390_match_ccmode (insn, CCUmode)"
777 [(set_attr "op_type" "SI")])
779 (define_insn "*cmpdi_ccu_mem"
781 (compare (match_operand:DI 0 "s_operand" "Q")
782 (match_operand:DI 1 "s_imm_operand" "Q")))]
783 "s390_match_ccmode(insn, CCUmode)"
784 "clc\\t%O0(8,%R0),%1"
785 [(set_attr "op_type" "SS")])
787 (define_insn "*cmpsi_ccu_mem"
789 (compare (match_operand:SI 0 "s_operand" "Q")
790 (match_operand:SI 1 "s_imm_operand" "Q")))]
791 "s390_match_ccmode(insn, CCUmode)"
792 "clc\\t%O0(4,%R0),%1"
793 [(set_attr "op_type" "SS")])
795 (define_insn "*cmphi_ccu_mem"
797 (compare (match_operand:HI 0 "s_operand" "Q")
798 (match_operand:HI 1 "s_imm_operand" "Q")))]
799 "s390_match_ccmode(insn, CCUmode)"
800 "clc\\t%O0(2,%R0),%1"
801 [(set_attr "op_type" "SS")])
803 (define_insn "*cmpqi_ccu_mem"
805 (compare (match_operand:QI 0 "s_operand" "Q")
806 (match_operand:QI 1 "s_imm_operand" "Q")))]
807 "s390_match_ccmode(insn, CCUmode)"
808 "clc\\t%O0(1,%R0),%1"
809 [(set_attr "op_type" "SS")])
814 (define_insn "*cmpdf_ccs_0"
816 (compare (match_operand:DF 0 "register_operand" "f")
817 (match_operand:DF 1 "const0_operand" "")))]
818 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
820 [(set_attr "op_type" "RRE")
821 (set_attr "type" "fsimpd")])
823 (define_insn "*cmpdf_ccs_0_ibm"
825 (compare (match_operand:DF 0 "register_operand" "f")
826 (match_operand:DF 1 "const0_operand" "")))]
827 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
829 [(set_attr "op_type" "RR")
830 (set_attr "type" "fsimpd")])
832 (define_insn "*cmpdf_ccs"
834 (compare (match_operand:DF 0 "register_operand" "f,f")
835 (match_operand:DF 1 "general_operand" "f,m")))]
836 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
840 [(set_attr "op_type" "RRE,RXE")
841 (set_attr "type" "fsimpd")])
843 (define_insn "*cmpdf_ccs_ibm"
845 (compare (match_operand:DF 0 "register_operand" "f,f")
846 (match_operand:DF 1 "general_operand" "f,m")))]
847 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
851 [(set_attr "op_type" "RR,RX")
852 (set_attr "type" "fsimpd")])
857 (define_insn "*cmpsf_ccs_0"
859 (compare (match_operand:SF 0 "register_operand" "f")
860 (match_operand:SF 1 "const0_operand" "")))]
861 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
863 [(set_attr "op_type" "RRE")
864 (set_attr "type" "fsimps")])
866 (define_insn "*cmpsf_ccs_0_ibm"
868 (compare (match_operand:SF 0 "register_operand" "f")
869 (match_operand:SF 1 "const0_operand" "")))]
870 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
872 [(set_attr "op_type" "RR")
873 (set_attr "type" "fsimps")])
875 (define_insn "*cmpsf_ccs"
877 (compare (match_operand:SF 0 "register_operand" "f,f")
878 (match_operand:SF 1 "general_operand" "f,m")))]
879 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
883 [(set_attr "op_type" "RRE,RXE")
884 (set_attr "type" "fsimps")])
886 (define_insn "*cmpsf_ccs"
888 (compare (match_operand:SF 0 "register_operand" "f,f")
889 (match_operand:SF 1 "general_operand" "f,m")))]
890 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
894 [(set_attr "op_type" "RR,RX")
895 (set_attr "type" "fsimps")])
899 ;;- Move instructions.
903 ; movti instruction pattern(s).
907 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,o,Q")
908 (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
915 mvc\\t%O0(16,%R0),%1"
916 [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
917 (set_attr "type" "lm,stm,*,*,cs")])
920 [(set (match_operand:TI 0 "nonimmediate_operand" "")
921 (match_operand:TI 1 "general_operand" ""))]
922 "TARGET_64BIT && reload_completed
923 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
924 [(set (match_dup 2) (match_dup 4))
925 (set (match_dup 3) (match_dup 5))]
927 operands[2] = operand_subword (operands[0], 0, 0, TImode);
928 operands[3] = operand_subword (operands[0], 1, 0, TImode);
929 operands[4] = operand_subword (operands[1], 0, 0, TImode);
930 operands[5] = operand_subword (operands[1], 1, 0, TImode);
934 [(set (match_operand:TI 0 "nonimmediate_operand" "")
935 (match_operand:TI 1 "general_operand" ""))]
936 "TARGET_64BIT && reload_completed
937 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
938 [(set (match_dup 2) (match_dup 4))
939 (set (match_dup 3) (match_dup 5))]
941 operands[2] = operand_subword (operands[0], 1, 0, TImode);
942 operands[3] = operand_subword (operands[0], 0, 0, TImode);
943 operands[4] = operand_subword (operands[1], 1, 0, TImode);
944 operands[5] = operand_subword (operands[1], 0, 0, TImode);
948 [(set (match_operand:TI 0 "register_operand" "")
949 (match_operand:TI 1 "memory_operand" ""))]
950 "TARGET_64BIT && reload_completed
951 && !s_operand (operands[1], VOIDmode)"
952 [(set (match_dup 0) (match_dup 1))]
954 rtx addr = operand_subword (operands[0], 1, 0, TImode);
955 s390_load_address (addr, XEXP (operands[1], 0));
956 operands[1] = replace_equiv_address (operands[1], addr);
959 (define_expand "reload_outti"
960 [(parallel [(match_operand:TI 0 "memory_operand" "")
961 (match_operand:TI 1 "register_operand" "d")
962 (match_operand:DI 2 "register_operand" "=&a")])]
965 s390_load_address (operands[2], XEXP (operands[0], 0));
966 operands[0] = replace_equiv_address (operands[0], operands[2]);
967 emit_move_insn (operands[0], operands[1]);
972 ; movdi instruction pattern(s).
975 (define_expand "movdi"
976 [(set (match_operand:DI 0 "general_operand" "")
977 (match_operand:DI 1 "general_operand" ""))]
981 /* Handle symbolic constants. */
982 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
983 emit_symbolic_move (operands);
985 /* During and after reload, we need to force constants
986 to the literal pool ourselves, if necessary. */
987 if ((reload_in_progress || reload_completed)
988 && CONSTANT_P (operands[1])
989 && (!legitimate_reload_constant_p (operands[1])
990 || FP_REG_P (operands[0])))
991 operands[1] = force_const_mem (DImode, operands[1]);
994 (define_insn "*movdi_lhi"
995 [(set (match_operand:DI 0 "register_operand" "=d")
996 (match_operand:DI 1 "immediate_operand" "K"))]
998 && GET_CODE (operands[1]) == CONST_INT
999 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1000 && !FP_REG_P (operands[0])"
1002 [(set_attr "op_type" "RI")])
1004 (define_insn "*movdi_lli"
1005 [(set (match_operand:DI 0 "register_operand" "=d")
1006 (match_operand:DI 1 "immediate_operand" "n"))]
1007 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
1008 && !FP_REG_P (operands[0])"
1011 int part = s390_single_hi (operands[1], DImode, 0);
1012 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
1016 case 0: return \"llihh\\t%0,%x1\";
1017 case 1: return \"llihl\\t%0,%x1\";
1018 case 2: return \"llilh\\t%0,%x1\";
1019 case 3: return \"llill\\t%0,%x1\";
1023 [(set_attr "op_type" "RI")])
1025 (define_insn "*movdi_larl"
1026 [(set (match_operand:DI 0 "register_operand" "=d")
1027 (match_operand:DI 1 "larl_operand" "X"))]
1029 && !FP_REG_P (operands[0])"
1031 [(set_attr "op_type" "RIL")
1032 (set_attr "type" "larl")])
1034 (define_insn "*movdi_64"
1035 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q")
1036 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))]
1045 mvc\\t%O0(8,%R0),%1"
1046 [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS")
1047 (set_attr "type" "lr,load,store,floadd,floadd,fstored,cs")])
1049 (define_insn "*movdi_31"
1050 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!m,Q")
1051 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
1061 mvc\\t%O0(8,%R0),%1"
1062 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
1063 (set_attr "type" "lm,stm,*,*,floadd,floadd,fstored,cs")])
1066 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1067 (match_operand:DI 1 "general_operand" ""))]
1068 "!TARGET_64BIT && reload_completed
1069 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1070 [(set (match_dup 2) (match_dup 4))
1071 (set (match_dup 3) (match_dup 5))]
1073 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1074 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1075 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1076 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1080 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1081 (match_operand:DI 1 "general_operand" ""))]
1082 "!TARGET_64BIT && reload_completed
1083 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1084 [(set (match_dup 2) (match_dup 4))
1085 (set (match_dup 3) (match_dup 5))]
1087 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1088 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1089 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1090 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1094 [(set (match_operand:DI 0 "register_operand" "")
1095 (match_operand:DI 1 "memory_operand" ""))]
1096 "!TARGET_64BIT && reload_completed
1097 && !FP_REG_P (operands[0])
1098 && !s_operand (operands[1], VOIDmode)"
1099 [(set (match_dup 0) (match_dup 1))]
1101 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1102 s390_load_address (addr, XEXP (operands[1], 0));
1103 operands[1] = replace_equiv_address (operands[1], addr);
1106 (define_expand "reload_outdi"
1107 [(parallel [(match_operand:DI 0 "memory_operand" "")
1108 (match_operand:DI 1 "register_operand" "d")
1109 (match_operand:SI 2 "register_operand" "=&a")])]
1112 s390_load_address (operands[2], XEXP (operands[0], 0));
1113 operands[0] = replace_equiv_address (operands[0], operands[2]);
1114 emit_move_insn (operands[0], operands[1]);
1119 [(set (match_operand:DI 0 "register_operand" "")
1120 (mem:DI (match_operand 1 "address_operand" "")))]
1122 && !FP_REG_P (operands[0])
1123 && GET_CODE (operands[1]) == SYMBOL_REF
1124 && CONSTANT_POOL_ADDRESS_P (operands[1])
1125 && get_pool_mode (operands[1]) == DImode
1126 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1127 [(set (match_dup 0) (match_dup 2))]
1128 "operands[2] = get_pool_constant (operands[1]);")
1131 ; movsi instruction pattern(s).
1134 (define_expand "movsi"
1135 [(set (match_operand:SI 0 "general_operand" "")
1136 (match_operand:SI 1 "general_operand" ""))]
1140 /* Handle symbolic constants. */
1141 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1142 emit_symbolic_move (operands);
1144 /* expr.c tries to load an effective address using
1145 force_reg. This fails because we don't have a
1146 generic load_address pattern. Convert the move
1147 to a proper arithmetic operation instead, unless
1148 it is guaranteed to be OK. */
1149 if (GET_CODE (operands[1]) == PLUS
1150 && !legitimate_la_operand_p (operands[1]))
1152 operands[1] = force_operand (operands[1], operands[0]);
1153 if (operands[1] == operands[0])
1157 /* During and after reload, we need to force constants
1158 to the literal pool ourselves, if necessary. */
1159 if ((reload_in_progress || reload_completed)
1160 && CONSTANT_P (operands[1])
1161 && (!legitimate_reload_constant_p (operands[1])
1162 || FP_REG_P (operands[0])))
1163 operands[1] = force_const_mem (SImode, operands[1]);
1166 (define_insn "*movsi_lhi"
1167 [(set (match_operand:SI 0 "register_operand" "=d")
1168 (match_operand:SI 1 "immediate_operand" "K"))]
1169 "GET_CODE (operands[1]) == CONST_INT
1170 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1171 && !FP_REG_P (operands[0])"
1173 [(set_attr "op_type" "RI")])
1175 (define_insn "*movsi_lli"
1176 [(set (match_operand:SI 0 "register_operand" "=d")
1177 (match_operand:SI 1 "immediate_operand" "n"))]
1178 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1179 && !FP_REG_P (operands[0])"
1182 int part = s390_single_hi (operands[1], SImode, 0);
1183 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1187 case 0: return \"llilh\\t%0,%x1\";
1188 case 1: return \"llill\\t%0,%x1\";
1192 [(set_attr "op_type" "RI")])
1194 (define_insn "*movsi"
1195 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q")
1196 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))]
1205 mvc\\t%O0(4,%R0),%1"
1206 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1207 (set_attr "type" "lr,load,store,floads,floads,fstores,cs")])
1210 [(set (match_operand:SI 0 "register_operand" "")
1211 (mem:SI (match_operand 1 "address_operand" "")))]
1212 "!FP_REG_P (operands[0])
1213 && GET_CODE (operands[1]) == SYMBOL_REF
1214 && CONSTANT_POOL_ADDRESS_P (operands[1])
1215 && get_pool_mode (operands[1]) == SImode
1216 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1217 [(set (match_dup 0) (match_dup 2))]
1218 "operands[2] = get_pool_constant (operands[1]);")
1221 ; movhi instruction pattern(s).
1224 (define_insn "movhi"
1225 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,?Q")
1226 (match_operand:HI 1 "general_operand" "d,n,m,d,?Q"))]
1233 mvc\\t%O0(2,%R0),%1"
1234 [(set_attr "op_type" "RR,RI,RX,RX,SS")
1235 (set_attr "type" "lr,*,*,store,cs")])
1238 [(set (match_operand:HI 0 "register_operand" "")
1239 (mem:HI (match_operand 1 "address_operand" "")))]
1240 "GET_CODE (operands[1]) == SYMBOL_REF
1241 && CONSTANT_POOL_ADDRESS_P (operands[1])
1242 && get_pool_mode (operands[1]) == HImode
1243 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1244 [(set (match_dup 0) (match_dup 2))]
1245 "operands[2] = get_pool_constant (operands[1]);")
1248 ; movqi instruction pattern(s).
1251 (define_insn "movqi_64"
1252 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q")
1253 (match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))]
1261 mvc\\t%O0(1,%R0),%1"
1262 [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1263 (set_attr "type" "lr,*,*,store,store,cs")])
1265 (define_insn "movqi"
1266 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q")
1267 (match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))]
1275 mvc\\t%O0(1,%R0),%1"
1276 [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
1277 (set_attr "type" "lr,*,*,store,store,cs")])
1280 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1281 (mem:QI (match_operand 1 "address_operand" "")))]
1282 "GET_CODE (operands[1]) == SYMBOL_REF
1283 && CONSTANT_POOL_ADDRESS_P (operands[1])
1284 && get_pool_mode (operands[1]) == QImode
1285 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1286 [(set (match_dup 0) (match_dup 2))]
1287 "operands[2] = get_pool_constant (operands[1]);")
1290 ; movstrictqi instruction pattern(s).
1293 (define_insn "*movstrictqi"
1294 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1295 (match_operand:QI 1 "memory_operand" "m"))]
1298 [(set_attr "op_type" "RX")])
1301 ; movstricthi instruction pattern(s).
1304 (define_insn "*movstricthi"
1305 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1306 (match_operand:HI 1 "s_imm_operand" "Q"))
1307 (clobber (reg:CC 33))]
1310 [(set_attr "op_type" "RS")])
1314 ; movstrictsi instruction pattern(s).
1317 (define_insn "movstrictsi"
1318 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1319 (match_operand:SI 1 "general_operand" "d,m"))]
1324 [(set_attr "op_type" "RR,RS")
1325 (set_attr "type" "lr,load")])
1329 ; movdf instruction pattern(s).
1332 (define_expand "movdf"
1333 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1334 (match_operand:DF 1 "general_operand" ""))]
1338 /* During and after reload, we need to force constants
1339 to the literal pool ourselves, if necessary. */
1340 if ((reload_in_progress || reload_completed)
1341 && CONSTANT_P (operands[1]))
1342 operands[1] = force_const_mem (DFmode, operands[1]);
1345 (define_insn "*movdf_64"
1346 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q")
1347 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,?Q"))]
1356 mvc\\t%O0(8,%R0),%1"
1357 [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS")
1358 (set_attr "type" "floadd,floadd,fstored,lr,load,store,cs")])
1360 (define_insn "*movdf_31"
1361 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,o,Q")
1362 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
1372 mvc\\t%O0(8,%R0),%1"
1373 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1374 (set_attr "type" "floadd,floadd,fstored,lm,stm,*,*,cs")])
1377 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1378 (match_operand:DF 1 "general_operand" ""))]
1379 "!TARGET_64BIT && reload_completed
1380 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1381 [(set (match_dup 2) (match_dup 4))
1382 (set (match_dup 3) (match_dup 5))]
1384 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1385 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1386 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1387 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1391 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1392 (match_operand:DF 1 "general_operand" ""))]
1393 "!TARGET_64BIT && reload_completed
1394 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1395 [(set (match_dup 2) (match_dup 4))
1396 (set (match_dup 3) (match_dup 5))]
1398 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1399 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1400 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1401 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1405 [(set (match_operand:DF 0 "register_operand" "")
1406 (match_operand:DF 1 "memory_operand" ""))]
1407 "!TARGET_64BIT && reload_completed
1408 && !FP_REG_P (operands[0])
1409 && !s_operand (operands[1], VOIDmode)"
1410 [(set (match_dup 0) (match_dup 1))]
1412 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1413 s390_load_address (addr, XEXP (operands[1], 0));
1414 operands[1] = replace_equiv_address (operands[1], addr);
1417 (define_expand "reload_outdf"
1418 [(parallel [(match_operand:DF 0 "memory_operand" "")
1419 (match_operand:DF 1 "register_operand" "d")
1420 (match_operand:SI 2 "register_operand" "=&a")])]
1423 s390_load_address (operands[2], XEXP (operands[0], 0));
1424 operands[0] = replace_equiv_address (operands[0], operands[2]);
1425 emit_move_insn (operands[0], operands[1]);
1430 ; movsf instruction pattern(s).
1433 (define_expand "movsf"
1434 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1435 (match_operand:SF 1 "general_operand" ""))]
1439 /* During and after reload, we need to force constants
1440 to the literal pool ourselves, if necessary. */
1441 if ((reload_in_progress || reload_completed)
1442 && CONSTANT_P (operands[1]))
1443 operands[1] = force_const_mem (SFmode, operands[1]);
1446 (define_insn "*movsf"
1447 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q")
1448 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,?Q"))]
1457 mvc\\t%O0(4,%R0),%1"
1458 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1459 (set_attr "type" "floads,floads,fstores,lr,load,store,cs")])
1462 ; load_multiple pattern(s).
1465 (define_expand "load_multiple"
1466 [(match_par_dup 3 [(set (match_operand 0 "" "")
1467 (match_operand 1 "" ""))
1468 (use (match_operand 2 "" ""))])]
1477 /* Support only loading a constant number of fixed-point registers from
1478 memory and only bother with this if more than two */
1479 if (GET_CODE (operands[2]) != CONST_INT
1480 || INTVAL (operands[2]) < 2
1481 || INTVAL (operands[2]) > 16
1482 || GET_CODE (operands[1]) != MEM
1483 || GET_CODE (operands[0]) != REG
1484 || REGNO (operands[0]) >= 16)
1487 count = INTVAL (operands[2]);
1488 regno = REGNO (operands[0]);
1490 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1493 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1495 from = XEXP (operands[1], 0);
1498 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1499 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1500 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1502 from = XEXP (XEXP (operands[1], 0), 0);
1503 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1508 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1513 from = force_reg (Pmode, XEXP (operands[1], 0));
1517 for (i = 0; i < count; i++)
1518 XVECEXP (operands[3], 0, i)
1519 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1520 change_address (operands[1], Pmode,
1521 plus_constant (from,
1522 off + i * UNITS_PER_WORD)));
1525 (define_insn "*load_multiple_di"
1526 [(match_parallel 0 "load_multiple_operation"
1527 [(set (match_operand:DI 1 "register_operand" "=r")
1528 (match_operand:DI 2 "s_operand" "Q"))])]
1532 int words = XVECLEN (operands[0], 0);
1534 if (XVECLEN (operands[0], 0) == 1)
1535 return \"lg\\t%1,0(%2)\";
1537 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1538 return \"lmg\\t%1,%0,%2\";
1540 [(set_attr "op_type" "RXE")
1541 (set_attr "type" "lm")])
1543 (define_insn "*load_multiple_si"
1544 [(match_parallel 0 "load_multiple_operation"
1545 [(set (match_operand:SI 1 "register_operand" "=r")
1546 (match_operand:SI 2 "s_operand" "Q"))])]
1550 int words = XVECLEN (operands[0], 0);
1552 if (XVECLEN (operands[0], 0) == 1)
1553 return \"l\\t%1,0(%2)\";
1555 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1556 return \"lm\\t%1,%0,%2\";
1558 [(set_attr "op_type" "RXE")
1559 (set_attr "type" "lm")])
1562 ; store multiple pattern(s).
1565 (define_expand "store_multiple"
1566 [(match_par_dup 3 [(set (match_operand 0 "" "")
1567 (match_operand 1 "" ""))
1568 (use (match_operand 2 "" ""))])]
1577 /* Support only storing a constant number of fixed-point registers to
1578 memory and only bother with this if more than two. */
1579 if (GET_CODE (operands[2]) != CONST_INT
1580 || INTVAL (operands[2]) < 2
1581 || INTVAL (operands[2]) > 16
1582 || GET_CODE (operands[0]) != MEM
1583 || GET_CODE (operands[1]) != REG
1584 || REGNO (operands[1]) >= 16)
1587 count = INTVAL (operands[2]);
1588 regno = REGNO (operands[1]);
1590 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1594 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1596 to = XEXP (operands[0], 0);
1599 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1600 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1601 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1603 to = XEXP (XEXP (operands[0], 0), 0);
1604 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1609 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1614 to = force_reg (Pmode, XEXP (operands[0], 0));
1618 for (i = 0; i < count; i++)
1619 XVECEXP (operands[3], 0, i)
1620 = gen_rtx_SET (VOIDmode,
1621 change_address (operands[0], Pmode,
1623 off + i * UNITS_PER_WORD)),
1624 gen_rtx_REG (Pmode, regno + i));
1627 (define_insn "*store_multiple_di"
1628 [(match_parallel 0 "store_multiple_operation"
1629 [(set (match_operand:DI 1 "s_operand" "=Q")
1630 (match_operand:DI 2 "register_operand" "r"))])]
1634 int words = XVECLEN (operands[0], 0);
1636 if (XVECLEN (operands[0], 0) == 1)
1637 return \"stg\\t%1,0(%2)\";
1639 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1640 return \"stmg\\t%2,%0,%1\";
1642 [(set_attr "op_type" "RXE")
1643 (set_attr "type" "stm")])
1646 (define_insn "*store_multiple_si"
1647 [(match_parallel 0 "store_multiple_operation"
1648 [(set (match_operand:SI 1 "s_operand" "=Q")
1649 (match_operand:SI 2 "register_operand" "r"))])]
1653 int words = XVECLEN (operands[0], 0);
1655 if (XVECLEN (operands[0], 0) == 1)
1656 return \"st\\t%1,0(%2)\";
1658 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1659 return \"stm\\t%2,%0,%1\";
1661 [(set_attr "op_type" "RXE")
1662 (set_attr "type" "stm")])
1665 ;; String instructions.
1669 ; movstrM instruction pattern(s).
1672 (define_expand "movstrdi"
1673 [(set (match_operand:BLK 0 "memory_operand" "")
1674 (match_operand:BLK 1 "memory_operand" ""))
1675 (use (match_operand:DI 2 "general_operand" ""))
1676 (match_operand 3 "" "")]
1678 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1680 (define_expand "movstrsi"
1681 [(set (match_operand:BLK 0 "memory_operand" "")
1682 (match_operand:BLK 1 "memory_operand" ""))
1683 (use (match_operand:SI 2 "general_operand" ""))
1684 (match_operand 3 "" "")]
1686 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1688 ; Move a block that is up to 256 bytes in length.
1689 ; The block length is taken as (operands[2] % 256) + 1.
1691 (define_insn "movstr_short_64"
1692 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1693 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1694 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1695 (clobber (match_scratch:DI 3 "=X,&a"))]
1699 switch (which_alternative)
1702 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1705 output_asm_insn (\"bras\\t%3,.+10\", operands);
1706 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1707 return \"ex\\t%2,0(%3)\";
1713 [(set_attr "op_type" "SS,NN")
1714 (set_attr "type" "cs,cs")
1715 (set_attr "atype" "*,agen")
1716 (set_attr "length" "*,14")])
1718 (define_insn "movstr_short_31"
1719 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1720 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1721 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1722 (clobber (match_scratch:SI 3 "=X,&a"))]
1726 switch (which_alternative)
1729 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1732 output_asm_insn (\"bras\\t%3,.+10\", operands);
1733 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1734 return \"ex\\t%2,0(%3)\";
1740 [(set_attr "op_type" "SS,NN")
1741 (set_attr "type" "cs,cs")
1742 (set_attr "atype" "*,agen")
1743 (set_attr "length" "*,14")])
1745 ; Move a block of arbitrary length.
1747 (define_insn "movstr_long_64"
1748 [(set (match_operand:TI 0 "register_operand" "=d")
1749 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1750 (lshiftrt:TI (match_dup 2) (const_int 64)))
1752 (set (match_operand:TI 1 "register_operand" "=d")
1753 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1754 (lshiftrt:TI (match_dup 3) (const_int 64)))
1756 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1757 (mem:BLK (subreg:DI (match_dup 3) 0)))
1758 (clobber (reg:CC 33))]
1760 "mvcle\\t%0,%1,0\;jo\\t.-4"
1761 [(set_attr "op_type" "NN")
1762 (set_attr "type" "vs")
1763 (set_attr "length" "8")])
1765 (define_insn "movstr_long_31"
1766 [(set (match_operand:DI 0 "register_operand" "=d")
1767 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1768 (lshiftrt:DI (match_dup 2) (const_int 32)))
1770 (set (match_operand:DI 1 "register_operand" "=d")
1771 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1772 (lshiftrt:DI (match_dup 3) (const_int 32)))
1774 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1775 (mem:BLK (subreg:SI (match_dup 3) 0)))
1776 (clobber (reg:CC 33))]
1778 "mvcle\\t%0,%1,0\;jo\\t.-4"
1779 [(set_attr "op_type" "NN")
1780 (set_attr "type" "vs")
1781 (set_attr "length" "8")])
1784 ; clrstrM instruction pattern(s).
1787 (define_expand "clrstrdi"
1788 [(set (match_operand:BLK 0 "memory_operand" "")
1790 (use (match_operand:DI 1 "general_operand" ""))
1791 (match_operand 2 "" "")]
1793 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1795 (define_expand "clrstrsi"
1796 [(set (match_operand:BLK 0 "memory_operand" "")
1798 (use (match_operand:SI 1 "general_operand" ""))
1799 (match_operand 2 "" "")]
1801 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1803 ; Clear a block that is up to 256 bytes in length.
1804 ; The block length is taken as (operands[2] % 256) + 1.
1806 (define_insn "clrstr_short_64"
1807 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1809 (use (match_operand:DI 1 "nonmemory_operand" "n,a"))
1810 (clobber (match_scratch:DI 2 "=X,&a"))
1811 (clobber (reg:CC 33))]
1815 switch (which_alternative)
1818 return \"xc\\t%O0(%b1+1,%R0),%0\";
1821 output_asm_insn (\"bras\\t%2,.+10\", operands);
1822 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1823 return \"ex\\t%1,0(%2)\";
1829 [(set_attr "op_type" "SS,NN")
1830 (set_attr "type" "cs,cs")
1831 (set_attr "atype" "*,agen")
1832 (set_attr "length" "*,14")])
1834 (define_insn "clrstr_short_31"
1835 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1837 (use (match_operand:SI 1 "nonmemory_operand" "n,a"))
1838 (clobber (match_scratch:SI 2 "=X,&a"))
1839 (clobber (reg:CC 33))]
1843 switch (which_alternative)
1846 return \"xc\\t%O0(%b1+1,%R0),%0\";
1849 output_asm_insn (\"bras\\t%2,.+10\", operands);
1850 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1851 return \"ex\\t%1,0(%2)\";
1857 [(set_attr "op_type" "SS,NN")
1858 (set_attr "type" "cs,cs")
1859 (set_attr "atype" "*,agen")
1860 (set_attr "length" "*,14")])
1862 ; Clear a block of arbitrary length.
1864 (define_insn "clrstr_long_64"
1865 [(set (match_operand:TI 0 "register_operand" "=d")
1866 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1867 (lshiftrt:TI (match_dup 2) (const_int 64)))
1869 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1871 (use (match_operand:TI 1 "register_operand" "d"))
1872 (clobber (reg:CC 33))]
1874 "mvcle\\t%0,%1,0\;jo\\t.-4"
1875 [(set_attr "op_type" "NN")
1876 (set_attr "type" "vs")
1877 (set_attr "length" "8")])
1879 (define_insn "clrstr_long_31"
1880 [(set (match_operand:DI 0 "register_operand" "=d")
1881 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1882 (lshiftrt:DI (match_dup 2) (const_int 32)))
1884 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1886 (use (match_operand:DI 1 "register_operand" "d"))
1887 (clobber (reg:CC 33))]
1889 "mvcle\\t%0,%1,0\;jo\\t.-4"
1890 [(set_attr "op_type" "NN")
1891 (set_attr "type" "vs")
1892 (set_attr "length" "8")])
1895 ; cmpstrM instruction pattern(s).
1898 (define_expand "cmpstrdi"
1899 [(set (match_operand:DI 0 "register_operand" "")
1900 (compare:DI (match_operand:BLK 1 "memory_operand" "")
1901 (match_operand:BLK 2 "memory_operand" "") ) )
1902 (use (match_operand:DI 3 "general_operand" ""))
1903 (use (match_operand:DI 4 "" ""))]
1905 "s390_expand_cmpstr (operands[0], operands[1],
1906 operands[2], operands[3]); DONE;")
1908 (define_expand "cmpstrsi"
1909 [(set (match_operand:SI 0 "register_operand" "")
1910 (compare:SI (match_operand:BLK 1 "memory_operand" "")
1911 (match_operand:BLK 2 "memory_operand" "") ) )
1912 (use (match_operand:SI 3 "general_operand" ""))
1913 (use (match_operand:SI 4 "" ""))]
1915 "s390_expand_cmpstr (operands[0], operands[1],
1916 operands[2], operands[3]); DONE;")
1918 ; Compare a block that is up to 256 bytes in length.
1919 ; The block length is taken as (operands[2] % 256) + 1.
1921 (define_insn "cmpstr_short_64"
1923 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1924 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1925 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1926 (clobber (match_scratch:DI 3 "=X,&a"))]
1930 switch (which_alternative)
1933 return \"clc\\t%O0(%b2+1,%R0),%1\";
1936 output_asm_insn (\"bras\\t%3,.+10\", operands);
1937 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1938 return \"ex\\t%2,0(%3)\";
1944 [(set_attr "op_type" "SS,NN")
1945 (set_attr "type" "cs,cs")
1946 (set_attr "atype" "*,agen")
1947 (set_attr "length" "*,14")])
1949 (define_insn "cmpstr_short_31"
1951 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1952 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1953 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1954 (clobber (match_scratch:SI 3 "=X,&a"))]
1958 switch (which_alternative)
1961 return \"clc\\t%O0(%b2+1,%R0),%1\";
1964 output_asm_insn (\"bras\\t%3,.+10\", operands);
1965 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1966 return \"ex\\t%2,0(%3)\";
1972 [(set_attr "op_type" "SS,NN")
1973 (set_attr "type" "cs,cs")
1974 (set_attr "atype" "*,agen")
1975 (set_attr "length" "*,14")])
1977 ; Compare a block of arbitrary length.
1979 (define_insn "cmpstr_long_64"
1980 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1981 (clobber (match_operand:TI 1 "register_operand" "=d"))
1983 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1984 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
1986 (use (match_dup 3))]
1989 [(set_attr "op_type" "RR")
1990 (set_attr "type" "vs")])
1992 (define_insn "cmpstr_long_31"
1993 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1994 (clobber (match_operand:DI 1 "register_operand" "=d"))
1996 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1997 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
1999 (use (match_dup 3))]
2002 [(set_attr "op_type" "RR")
2003 (set_attr "type" "vs")])
2005 ; Convert condition code to integer in range (-1, 0, 1)
2007 (define_insn "cmpint_si"
2008 [(set (match_operand:SI 0 "register_operand" "=d")
2009 (compare:SI (reg:CCS 33) (const_int 0)))]
2013 output_asm_insn (\"lhi\\t%0,1\", operands);
2014 output_asm_insn (\"jh\\t.+12\", operands);
2015 output_asm_insn (\"jl\\t.+6\", operands);
2016 output_asm_insn (\"sr\\t%0,%0\", operands);
2017 return \"lcr\\t%0,%0\";
2019 [(set_attr "op_type" "NN")
2020 (set_attr "length" "16")
2021 (set_attr "type" "other")])
2023 (define_insn "cmpint_di"
2024 [(set (match_operand:DI 0 "register_operand" "=d")
2025 (compare:DI (reg:CCS 33) (const_int 0)))]
2029 output_asm_insn (\"lghi\\t%0,1\", operands);
2030 output_asm_insn (\"jh\\t.+12\", operands);
2031 output_asm_insn (\"jl\\t.+6\", operands);
2032 output_asm_insn (\"sgr\\t%0,%0\", operands);
2033 return \"lcgr\\t%0,%0\";
2035 [(set_attr "op_type" "NN")
2036 (set_attr "length" "22")
2037 (set_attr "type" "other")])
2041 ;;- Conversion instructions.
2044 (define_insn "*sethighqisi"
2045 [(set (match_operand:SI 0 "register_operand" "=d")
2046 (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
2047 (clobber (reg:CC 33))]
2050 [(set_attr "op_type" "RS")])
2052 (define_insn "*sethighhisi"
2053 [(set (match_operand:SI 0 "register_operand" "=d")
2054 (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
2055 (clobber (reg:CC 33))]
2058 [(set_attr "op_type" "RS")])
2060 (define_insn "*sethighqidi_64"
2061 [(set (match_operand:DI 0 "register_operand" "=d")
2062 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2063 (clobber (reg:CC 33))]
2066 [(set_attr "op_type" "RSE")])
2068 (define_insn "*sethighqidi_31"
2069 [(set (match_operand:DI 0 "register_operand" "=d")
2070 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2071 (clobber (reg:CC 33))]
2074 [(set_attr "op_type" "RS")])
2076 (define_insn_and_split "*extractqi"
2077 [(set (match_operand:SI 0 "register_operand" "=d")
2078 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2079 (match_operand 2 "const_int_operand" "n")
2081 (clobber (reg:CC 33))]
2083 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2085 "&& reload_completed"
2087 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2088 (clobber (reg:CC 33))])
2089 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2092 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2093 operands[1] = change_address (operands[1], QImode, 0);
2095 [(set_attr "atype" "agen")])
2097 (define_insn_and_split "*extracthi"
2098 [(set (match_operand:SI 0 "register_operand" "=d")
2099 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2100 (match_operand 2 "const_int_operand" "n")
2102 (clobber (reg:CC 33))]
2104 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2106 "&& reload_completed"
2108 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2109 (clobber (reg:CC 33))])
2110 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2113 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2114 operands[1] = change_address (operands[1], HImode, 0);
2116 [(set_attr "atype" "agen")])
2119 ; extendsidi2 instruction pattern(s).
2122 (define_expand "extendsidi2"
2123 [(set (match_operand:DI 0 "register_operand" "")
2124 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2130 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2131 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2132 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2133 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2139 (define_insn "*extendsidi2"
2140 [(set (match_operand:DI 0 "register_operand" "=d,d")
2141 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2146 [(set_attr "op_type" "RRE,RXE")])
2149 ; extendhidi2 instruction pattern(s).
2152 (define_expand "extendhidi2"
2153 [(set (match_operand:DI 0 "register_operand" "")
2154 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2160 rtx tmp = gen_reg_rtx (SImode);
2161 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2162 emit_insn (gen_extendsidi2 (operands[0], tmp));
2167 operands[1] = gen_lowpart (DImode, operands[1]);
2168 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2169 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2175 (define_insn "*extendhidi2"
2176 [(set (match_operand:DI 0 "register_operand" "=d")
2177 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2180 [(set_attr "op_type" "RXE")])
2183 ; extendqidi2 instruction pattern(s).
2186 (define_expand "extendqidi2"
2187 [(set (match_operand:DI 0 "register_operand" "")
2188 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2194 rtx tmp = gen_reg_rtx (SImode);
2195 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2196 emit_insn (gen_extendsidi2 (operands[0], tmp));
2201 operands[1] = gen_lowpart (DImode, operands[1]);
2202 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2203 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2210 [(set (match_operand:DI 0 "register_operand" "")
2211 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2212 "TARGET_64BIT && !reload_completed"
2214 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2215 (clobber (reg:CC 33))])
2217 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2218 (clobber (reg:CC 33))])]
2222 ; extendhisi2 instruction pattern(s).
2225 (define_expand "extendhisi2"
2226 [(set (match_operand:SI 0 "register_operand" "")
2227 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2231 operands[1] = gen_lowpart (SImode, operands[1]);
2232 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2233 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2238 (define_insn "*extendhisi2"
2239 [(set (match_operand:SI 0 "register_operand" "=d")
2240 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2243 [(set_attr "op_type" "RX")])
2246 ; extendqisi2 instruction pattern(s).
2249 (define_expand "extendqisi2"
2250 [(set (match_operand:SI 0 "register_operand" "")
2251 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2255 operands[1] = gen_lowpart (SImode, operands[1]);
2256 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2257 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2263 [(set (match_operand:SI 0 "register_operand" "")
2264 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2267 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2268 (clobber (reg:CC 33))])
2270 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2271 (clobber (reg:CC 33))])]
2275 ; extendqihi2 instruction pattern(s).
2280 ; zero_extendsidi2 instruction pattern(s).
2283 (define_expand "zero_extendsidi2"
2284 [(set (match_operand:DI 0 "register_operand" "")
2285 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2291 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2292 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2293 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2299 (define_insn "*zero_extendsidi2"
2300 [(set (match_operand:DI 0 "register_operand" "=d,d")
2301 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2306 [(set_attr "op_type" "RRE,RXE")])
2309 ; zero_extendhidi2 instruction pattern(s).
2312 (define_expand "zero_extendhidi2"
2313 [(set (match_operand:DI 0 "register_operand" "")
2314 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2320 rtx tmp = gen_reg_rtx (SImode);
2321 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2322 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2327 operands[1] = gen_lowpart (DImode, operands[1]);
2328 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2329 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2335 (define_insn "*zero_extendhidi2"
2336 [(set (match_operand:DI 0 "register_operand" "=d")
2337 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2340 [(set_attr "op_type" "RXE")])
2343 ; zero_extendqidi2 instruction pattern(s)
2346 (define_expand "zero_extendqidi2"
2347 [(set (match_operand:DI 0 "register_operand" "")
2348 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2354 rtx tmp = gen_reg_rtx (SImode);
2355 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2356 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2361 operands[1] = gen_lowpart (DImode, operands[1]);
2362 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2363 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2369 (define_insn "*zero_extendqidi2"
2370 [(set (match_operand:DI 0 "register_operand" "=d")
2371 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2374 [(set_attr "op_type" "RXE")])
2377 ; zero_extendhisi2 instruction pattern(s).
2380 (define_expand "zero_extendhisi2"
2381 [(set (match_operand:SI 0 "register_operand" "")
2382 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2386 operands[1] = gen_lowpart (SImode, operands[1]);
2387 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2392 (define_insn "*zero_extendhisi2_64"
2393 [(set (match_operand:SI 0 "register_operand" "=d")
2394 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2397 [(set_attr "op_type" "RXE")])
2399 (define_insn_and_split "*zero_extendhisi2_31"
2400 [(set (match_operand:SI 0 "register_operand" "=&d")
2401 (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q")))
2402 (clobber (reg:CC 33))]
2405 "&& reload_completed"
2406 [(set (match_dup 0) (const_int 0))
2408 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2409 (clobber (reg:CC 33))])]
2410 "operands[2] = gen_lowpart (HImode, operands[0]);"
2411 [(set_attr "atype" "agen")])
2414 ; zero_extendqisi2 instruction pattern(s).
2417 (define_expand "zero_extendqisi2"
2418 [(set (match_operand:SI 0 "register_operand" "")
2419 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2423 operands[1] = gen_lowpart (SImode, operands[1]);
2424 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2429 (define_insn "*zero_extendqisi2_64"
2430 [(set (match_operand:SI 0 "register_operand" "=d")
2431 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2434 [(set_attr "op_type" "RXE")])
2436 (define_insn_and_split "*zero_extendqisi2_31"
2437 [(set (match_operand:SI 0 "register_operand" "=&d")
2438 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2441 "&& reload_completed"
2442 [(set (match_dup 0) (const_int 0))
2443 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2444 "operands[2] = gen_lowpart (QImode, operands[0]);"
2445 [(set_attr "atype" "agen")])
2448 ; zero_extendqihi2 instruction pattern(s).
2451 (define_expand "zero_extendqihi2"
2452 [(set (match_operand:HI 0 "register_operand" "")
2453 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2457 operands[1] = gen_lowpart (HImode, operands[1]);
2458 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2463 (define_insn "*zero_extendqihi2_64"
2464 [(set (match_operand:HI 0 "register_operand" "=d")
2465 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2468 [(set_attr "op_type" "RXE")])
2470 (define_insn_and_split "*zero_extendqihi2_31"
2471 [(set (match_operand:HI 0 "register_operand" "=&d")
2472 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2475 "&& reload_completed"
2476 [(set (match_dup 0) (const_int 0))
2477 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2478 "operands[2] = gen_lowpart (QImode, operands[0]);"
2479 [(set_attr "atype" "agen")])
2483 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2486 (define_expand "fixuns_truncdfdi2"
2487 [(set (match_operand:DI 0 "register_operand" "")
2488 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2489 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2492 rtx label1 = gen_label_rtx ();
2493 rtx label2 = gen_label_rtx ();
2494 rtx temp = gen_reg_rtx (DFmode);
2495 operands[1] = force_reg (DFmode, operands[1]);
2497 emit_insn (gen_cmpdf (operands[1],
2498 CONST_DOUBLE_FROM_REAL_VALUE (
2499 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2500 emit_jump_insn (gen_blt (label1));
2501 emit_insn (gen_subdf3 (temp, operands[1],
2502 CONST_DOUBLE_FROM_REAL_VALUE (
2503 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2504 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2507 emit_label (label1);
2508 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2509 emit_label (label2);
2513 (define_expand "fix_truncdfdi2"
2514 [(set (match_operand:DI 0 "register_operand" "")
2515 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2516 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2519 operands[1] = force_reg (DFmode, operands[1]);
2520 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2524 (define_insn "fix_truncdfdi2_ieee"
2525 [(set (match_operand:DI 0 "register_operand" "=d")
2526 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2527 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2528 (clobber (reg:CC 33))]
2529 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2531 [(set_attr "op_type" "RRE")
2532 (set_attr "type" "ftoi")])
2535 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2538 (define_expand "fixuns_truncdfsi2"
2539 [(set (match_operand:SI 0 "register_operand" "")
2540 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2541 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2544 rtx label1 = gen_label_rtx ();
2545 rtx label2 = gen_label_rtx ();
2546 rtx temp = gen_reg_rtx (DFmode);
2548 operands[1] = force_reg (DFmode,operands[1]);
2549 emit_insn (gen_cmpdf (operands[1],
2550 CONST_DOUBLE_FROM_REAL_VALUE (
2551 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2552 emit_jump_insn (gen_blt (label1));
2553 emit_insn (gen_subdf3 (temp, operands[1],
2554 CONST_DOUBLE_FROM_REAL_VALUE (
2555 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2556 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2559 emit_label (label1);
2560 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2561 emit_label (label2);
2565 (define_expand "fix_truncdfsi2"
2566 [(set (match_operand:SI 0 "register_operand" "")
2567 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2571 if (TARGET_IBM_FLOAT)
2573 /* This is the algorithm from POP chapter A.5.7.2. */
2575 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2576 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2577 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2579 operands[1] = force_reg (DFmode, operands[1]);
2580 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2581 two31r, two32, temp));
2585 operands[1] = force_reg (DFmode, operands[1]);
2586 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2592 (define_insn "fix_truncdfsi2_ieee"
2593 [(set (match_operand:SI 0 "register_operand" "=d")
2594 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2595 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2596 (clobber (reg:CC 33))]
2597 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2599 [(set_attr "op_type" "RRE")
2600 (set_attr "type" "other" )])
2602 (define_insn "fix_truncdfsi2_ibm"
2603 [(set (match_operand:SI 0 "register_operand" "=d")
2604 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2605 (use (match_operand:DI 2 "immediate_operand" "m"))
2606 (use (match_operand:DI 3 "immediate_operand" "m"))
2607 (use (match_operand:BLK 4 "memory_operand" "m"))
2608 (clobber (reg:CC 33))]
2609 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2612 output_asm_insn (\"sd\\t%1,%2\", operands);
2613 output_asm_insn (\"aw\\t%1,%3\", operands);
2614 output_asm_insn (\"std\\t%1,%4\", operands);
2615 output_asm_insn (\"xi\\t%N4,128\", operands);
2616 return \"l\\t%0,%N4\";
2618 [(set_attr "op_type" "NN")
2619 (set_attr "type" "ftoi")
2620 (set_attr "atype" "agen")
2621 (set_attr "length" "20")])
2624 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2627 (define_expand "fixuns_truncsfdi2"
2628 [(set (match_operand:DI 0 "register_operand" "")
2629 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2630 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2633 rtx label1 = gen_label_rtx ();
2634 rtx label2 = gen_label_rtx ();
2635 rtx temp = gen_reg_rtx (SFmode);
2637 operands[1] = force_reg (SFmode, operands[1]);
2638 emit_insn (gen_cmpsf (operands[1],
2639 CONST_DOUBLE_FROM_REAL_VALUE (
2640 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2641 emit_jump_insn (gen_blt (label1));
2643 emit_insn (gen_subsf3 (temp, operands[1],
2644 CONST_DOUBLE_FROM_REAL_VALUE (
2645 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2646 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2649 emit_label (label1);
2650 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2651 emit_label (label2);
2655 (define_expand "fix_truncsfdi2"
2656 [(set (match_operand:DI 0 "register_operand" "")
2657 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2658 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2661 operands[1] = force_reg (SFmode, operands[1]);
2662 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2666 (define_insn "fix_truncsfdi2_ieee"
2667 [(set (match_operand:DI 0 "register_operand" "=d")
2668 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2669 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2670 (clobber (reg:CC 33))]
2671 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2673 [(set_attr "op_type" "RRE")
2674 (set_attr "type" "ftoi")])
2677 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2680 (define_expand "fixuns_truncsfsi2"
2681 [(set (match_operand:SI 0 "register_operand" "")
2682 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2683 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2686 rtx label1 = gen_label_rtx ();
2687 rtx label2 = gen_label_rtx ();
2688 rtx temp = gen_reg_rtx (SFmode);
2690 operands[1] = force_reg (SFmode, operands[1]);
2691 emit_insn (gen_cmpsf (operands[1],
2692 CONST_DOUBLE_FROM_REAL_VALUE (
2693 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2694 emit_jump_insn (gen_blt (label1));
2695 emit_insn (gen_subsf3 (temp, operands[1],
2696 CONST_DOUBLE_FROM_REAL_VALUE (
2697 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2698 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2701 emit_label (label1);
2702 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2703 emit_label (label2);
2707 (define_expand "fix_truncsfsi2"
2708 [(set (match_operand:SI 0 "register_operand" "")
2709 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2713 if (TARGET_IBM_FLOAT)
2715 /* Convert to DFmode and then use the POP algorithm. */
2716 rtx temp = gen_reg_rtx (DFmode);
2717 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2718 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2722 operands[1] = force_reg (SFmode, operands[1]);
2723 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2729 (define_insn "fix_truncsfsi2_ieee"
2730 [(set (match_operand:SI 0 "register_operand" "=d")
2731 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2732 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2733 (clobber (reg:CC 33))]
2734 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2736 [(set_attr "op_type" "RRE")
2737 (set_attr "type" "ftoi")])
2740 ; floatdidf2 instruction pattern(s).
2743 (define_insn "floatdidf2"
2744 [(set (match_operand:DF 0 "register_operand" "=f")
2745 (float:DF (match_operand:DI 1 "register_operand" "d")))
2746 (clobber (reg:CC 33))]
2747 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2749 [(set_attr "op_type" "RRE")
2750 (set_attr "type" "itof" )])
2753 ; floatdisf2 instruction pattern(s).
2756 (define_insn "floatdisf2"
2757 [(set (match_operand:SF 0 "register_operand" "=f")
2758 (float:SF (match_operand:DI 1 "register_operand" "d")))
2759 (clobber (reg:CC 33))]
2760 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2762 [(set_attr "op_type" "RRE")
2763 (set_attr "type" "itof" )])
2766 ; floatsidf2 instruction pattern(s).
2769 (define_expand "floatsidf2"
2771 [(set (match_operand:DF 0 "register_operand" "")
2772 (float:DF (match_operand:SI 1 "register_operand" "")))
2773 (clobber (reg:CC 33))])]
2777 if (TARGET_IBM_FLOAT)
2779 /* This is the algorithm from POP chapter A.5.7.1. */
2781 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2782 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2784 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2789 (define_insn "floatsidf2_ieee"
2790 [(set (match_operand:DF 0 "register_operand" "=f")
2791 (float:DF (match_operand:SI 1 "register_operand" "d")))
2792 (clobber (reg:CC 33))]
2793 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2795 [(set_attr "op_type" "RRE")
2796 (set_attr "type" "itof" )])
2798 (define_insn "floatsidf2_ibm"
2799 [(set (match_operand:DF 0 "register_operand" "=f")
2800 (float:DF (match_operand:SI 1 "register_operand" "d")))
2801 (use (match_operand:DI 2 "immediate_operand" "m"))
2802 (use (match_operand:BLK 3 "memory_operand" "m"))
2803 (clobber (reg:CC 33))]
2804 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2807 output_asm_insn (\"st\\t%1,%N3\", operands);
2808 output_asm_insn (\"xi\\t%N3,128\", operands);
2809 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2810 output_asm_insn (\"ld\\t%0,%3\", operands);
2811 return \"sd\\t%0,%2\";
2813 [(set_attr "op_type" "NN")
2814 (set_attr "type" "other" )
2815 (set_attr "atype" "agen")
2816 (set_attr "length" "20")])
2819 ; floatsisf2 instruction pattern(s).
2822 (define_expand "floatsisf2"
2824 [(set (match_operand:SF 0 "register_operand" "")
2825 (float:SF (match_operand:SI 1 "register_operand" "")))
2826 (clobber (reg:CC 33))])]
2830 if (TARGET_IBM_FLOAT)
2832 /* Use the POP algorithm to convert to DFmode and then truncate. */
2833 rtx temp = gen_reg_rtx (DFmode);
2834 emit_insn (gen_floatsidf2 (temp, operands[1]));
2835 emit_insn (gen_truncdfsf2 (operands[0], temp));
2840 (define_insn "floatsisf2_ieee"
2841 [(set (match_operand:SF 0 "register_operand" "=f")
2842 (float:SF (match_operand:SI 1 "register_operand" "d")))
2843 (clobber (reg:CC 33))]
2844 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2846 [(set_attr "op_type" "RRE")
2847 (set_attr "type" "itof" )])
2850 ; truncdfsf2 instruction pattern(s).
2853 (define_expand "truncdfsf2"
2854 [(set (match_operand:SF 0 "register_operand" "")
2855 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2859 (define_insn "truncdfsf2_ieee"
2860 [(set (match_operand:SF 0 "register_operand" "=f")
2861 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2862 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2864 [(set_attr "op_type" "RRE")])
2866 (define_insn "truncdfsf2_ibm"
2867 [(set (match_operand:SF 0 "register_operand" "=f,f")
2868 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2869 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2873 [(set_attr "op_type" "RR,RX")
2874 (set_attr "type" "floads,floads")])
2877 ; extendsfdf2 instruction pattern(s).
2880 (define_expand "extendsfdf2"
2881 [(set (match_operand:DF 0 "register_operand" "")
2882 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2886 if (TARGET_IBM_FLOAT)
2888 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2893 (define_insn "extendsfdf2_ieee"
2894 [(set (match_operand:DF 0 "register_operand" "=f,f")
2895 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2896 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2900 [(set_attr "op_type" "RRE,RXE")
2901 (set_attr "type" "floads,floads")])
2903 (define_insn "extendsfdf2_ibm"
2904 [(set (match_operand:DF 0 "register_operand" "=f,f")
2905 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2906 (clobber (reg:CC 33))]
2907 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2909 sdr\\t%0,%0\;ler\\t%0,%1
2910 sdr\\t%0,%0\;le\\t%0,%1"
2911 [(set_attr "op_type" "NN,NN")
2912 (set_attr "atype" "reg,agen")
2913 (set_attr "length" "4,6")
2914 (set_attr "type" "o2,o2")])
2918 ;; ARITHMETRIC OPERATIONS
2920 ; arithmetric operations set the ConditionCode,
2921 ; because of unpredictable Bits in Register for Halfword and Byte
2922 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2925 ;;- Add instructions.
2929 ; adddi3 instruction pattern(s).
2932 (define_insn "*adddi3_sign"
2933 [(set (match_operand:DI 0 "register_operand" "=d,d")
2934 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2935 (match_operand:DI 1 "register_operand" "0,0")))
2936 (clobber (reg:CC 33))]
2941 [(set_attr "op_type" "RRE,RXE")])
2943 (define_insn "*adddi3_zero_cc"
2945 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2946 (match_operand:DI 1 "register_operand" "0,0"))
2948 (set (match_operand:DI 0 "register_operand" "=d,d")
2949 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
2950 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2954 [(set_attr "op_type" "RRE,RXE")])
2956 (define_insn "*adddi3_zero_cconly"
2958 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2959 (match_operand:DI 1 "register_operand" "0,0"))
2961 (clobber (match_scratch:DI 0 "=d,d"))]
2962 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2966 [(set_attr "op_type" "RRE,RXE")])
2968 (define_insn "*adddi3_zero"
2969 [(set (match_operand:DI 0 "register_operand" "=d,d")
2970 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2971 (match_operand:DI 1 "register_operand" "0,0")))
2972 (clobber (reg:CC 33))]
2977 [(set_attr "op_type" "RRE,RXE")])
2979 (define_insn "*adddi3_imm_cc"
2981 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
2982 (match_operand:DI 2 "const_int_operand" "K"))
2984 (set (match_operand:DI 0 "register_operand" "=d")
2985 (plus:DI (match_dup 1) (match_dup 2)))]
2987 && s390_match_ccmode (insn, CCAmode)
2988 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
2990 [(set_attr "op_type" "RI")])
2992 (define_insn "*adddi3_cc"
2994 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2995 (match_operand:DI 2 "general_operand" "d,m"))
2997 (set (match_operand:DI 0 "register_operand" "=d,d")
2998 (plus:DI (match_dup 1) (match_dup 2)))]
2999 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3003 [(set_attr "op_type" "RRE,RXE")])
3005 (define_insn "*adddi3_cconly"
3007 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3008 (match_operand:DI 2 "general_operand" "d,m"))
3010 (clobber (match_scratch:DI 0 "=d,d"))]
3011 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3015 [(set_attr "op_type" "RRE,RXE")])
3017 (define_insn "*adddi3_cconly2"
3019 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3020 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3021 (clobber (match_scratch:DI 0 "=d,d"))]
3022 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3026 [(set_attr "op_type" "RRE,RXE")])
3028 (define_insn "*adddi3_64"
3029 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3030 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3031 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3032 (clobber (reg:CC 33))]
3038 [(set_attr "op_type" "RRE,RI,RXE")])
3040 (define_insn_and_split "*adddi3_31"
3041 [(set (match_operand:DI 0 "register_operand" "=&d")
3042 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3043 (match_operand:DI 2 "general_operand" "do") ) )
3044 (clobber (reg:CC 33))]
3047 "&& reload_completed"
3049 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3050 (clobber (reg:CC 33))])
3053 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3055 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3057 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3059 (label_ref (match_dup 9))))
3061 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3062 (clobber (reg:CC 33))])
3064 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3065 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3066 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3067 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3068 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3069 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3070 operands[9] = gen_label_rtx ();"
3071 [(set_attr "op_type" "NN")])
3073 (define_expand "adddi3"
3075 [(set (match_operand:DI 0 "register_operand" "")
3076 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3077 (match_operand:DI 2 "general_operand" "")))
3078 (clobber (reg:CC 33))])]
3082 (define_insn "*la_64"
3083 [(set (match_operand:DI 0 "register_operand" "=d")
3084 (match_operand:QI 1 "address_operand" "p"))]
3087 [(set_attr "op_type" "RX")
3088 (set_attr "type" "la")])
3092 [(set (match_operand:DI 0 "register_operand" "")
3093 (match_operand:QI 1 "address_operand" ""))
3094 (clobber (reg:CC 33))])]
3096 && strict_memory_address_p (VOIDmode, operands[1])
3097 && preferred_la_operand_p (operands[1])"
3098 [(set (match_dup 0) (match_dup 1))]
3102 [(set (match_operand:DI 0 "register_operand" "")
3103 (match_operand:DI 1 "register_operand" ""))
3106 (plus:DI (match_dup 0)
3107 (match_operand:DI 2 "nonmemory_operand" "")))
3108 (clobber (reg:CC 33))])]
3110 && !reg_overlap_mentioned_p (operands[0], operands[2])
3111 && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (DImode, operands[1], operands[2]))
3112 && preferred_la_operand_p (gen_rtx_PLUS (DImode, operands[1], operands[2]))"
3113 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3116 (define_expand "reload_indi"
3117 [(parallel [(match_operand:DI 0 "register_operand" "=a")
3118 (match_operand:DI 1 "s390_plus_operand" "")
3119 (match_operand:DI 2 "register_operand" "=&a")])]
3123 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3129 ; addsi3 instruction pattern(s).
3132 (define_insn "*addsi3_imm_cc"
3134 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3135 (match_operand:SI 2 "const_int_operand" "K"))
3137 (set (match_operand:SI 0 "register_operand" "=d")
3138 (plus:SI (match_dup 1) (match_dup 2)))]
3139 "s390_match_ccmode (insn, CCAmode)
3140 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
3142 [(set_attr "op_type" "RI")])
3144 (define_insn "*addsi3_carry1_cc"
3146 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3147 (match_operand:SI 2 "general_operand" "d,m"))
3149 (set (match_operand:SI 0 "register_operand" "=d,d")
3150 (plus:SI (match_dup 1) (match_dup 2)))]
3151 "s390_match_ccmode (insn, CCL1mode)"
3155 [(set_attr "op_type" "RR,RX")])
3157 (define_insn "*addsi3_carry1_cconly"
3159 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3160 (match_operand:SI 2 "general_operand" "d,m"))
3162 (clobber (match_scratch:SI 0 "=d,d"))]
3163 "s390_match_ccmode (insn, CCL1mode)"
3167 [(set_attr "op_type" "RR,RX")])
3169 (define_insn "*addsi3_carry2_cc"
3171 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3172 (match_operand:SI 2 "general_operand" "d,m"))
3174 (set (match_operand:SI 0 "register_operand" "=d,d")
3175 (plus:SI (match_dup 1) (match_dup 2)))]
3176 "s390_match_ccmode (insn, CCL1mode)"
3180 [(set_attr "op_type" "RR,RX")])
3182 (define_insn "*addsi3_carry2_cconly"
3184 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3185 (match_operand:SI 2 "general_operand" "d,m"))
3187 (clobber (match_scratch:SI 0 "=d,d"))]
3188 "s390_match_ccmode (insn, CCL1mode)"
3192 [(set_attr "op_type" "RR,RX")])
3194 (define_insn "*addsi3_cc"
3196 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3197 (match_operand:SI 2 "general_operand" "d,m"))
3199 (set (match_operand:SI 0 "register_operand" "=d,d")
3200 (plus:SI (match_dup 1) (match_dup 2)))]
3201 "s390_match_ccmode (insn, CCLmode)"
3205 [(set_attr "op_type" "RR,RX")])
3207 (define_insn "*addsi3_cconly"
3209 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3210 (match_operand:SI 2 "general_operand" "d,m"))
3212 (clobber (match_scratch:SI 0 "=d,d"))]
3213 "s390_match_ccmode (insn, CCLmode)"
3217 [(set_attr "op_type" "RR,RX")])
3219 (define_insn "*addsi3_cconly2"
3221 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3222 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3223 (clobber (match_scratch:SI 0 "=d,d"))]
3224 "s390_match_ccmode(insn, CCLmode)"
3228 [(set_attr "op_type" "RR,RX")])
3230 (define_insn "*addsi3_sign"
3231 [(set (match_operand:SI 0 "register_operand" "=d")
3232 (plus:SI (match_operand:SI 1 "register_operand" "0")
3233 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3234 (clobber (reg:CC 33))]
3237 [(set_attr "op_type" "RX")])
3239 (define_insn "*addsi3_sub"
3240 [(set (match_operand:SI 0 "register_operand" "=d")
3241 (plus:SI (match_operand:SI 1 "register_operand" "0")
3242 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3243 (clobber (reg:CC 33))]
3246 [(set_attr "op_type" "RX")])
3248 (define_insn "addsi3"
3249 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3250 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3251 (match_operand:SI 2 "general_operand" "d,K,m")))
3252 (clobber (reg:CC 33))]
3258 [(set_attr "op_type" "RR,RI,RX")])
3260 (define_insn "*la_31"
3261 [(set (match_operand:SI 0 "register_operand" "=d")
3262 (match_operand:QI 1 "address_operand" "p"))]
3263 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
3265 [(set_attr "op_type" "RX")
3266 (set_attr "type" "la")])
3270 [(set (match_operand:SI 0 "register_operand" "")
3271 (match_operand:QI 1 "address_operand" ""))
3272 (clobber (reg:CC 33))])]
3274 && strict_memory_address_p (VOIDmode, operands[1])
3275 && preferred_la_operand_p (operands[1])"
3276 [(set (match_dup 0) (match_dup 1))]
3280 [(set (match_operand:SI 0 "register_operand" "")
3281 (match_operand:SI 1 "register_operand" ""))
3284 (plus:SI (match_dup 0)
3285 (match_operand:SI 2 "nonmemory_operand" "")))
3286 (clobber (reg:CC 33))])]
3288 && !reg_overlap_mentioned_p (operands[0], operands[2])
3289 && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (SImode, operands[1], operands[2]))
3290 && preferred_la_operand_p (gen_rtx_PLUS (SImode, operands[1], operands[2]))"
3291 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3294 (define_insn "*la_31_and"
3295 [(set (match_operand:SI 0 "register_operand" "=d")
3296 (and:SI (match_operand:QI 1 "address_operand" "p")
3297 (const_int 2147483647)))]
3300 [(set_attr "op_type" "RX")
3301 (set_attr "type" "la")])
3303 (define_insn_and_split "*la_31_and_cc"
3304 [(set (match_operand:SI 0 "register_operand" "=d")
3305 (and:SI (match_operand:QI 1 "address_operand" "p")
3306 (const_int 2147483647)))
3307 (clobber (reg:CC 33))]
3310 "&& reload_completed"
3312 (and:SI (match_dup 1) (const_int 2147483647)))]
3314 [(set_attr "op_type" "RX")
3315 (set_attr "type" "la")])
3317 (define_insn "force_la_31"
3318 [(set (match_operand:SI 0 "register_operand" "=d")
3319 (match_operand:QI 1 "address_operand" "p"))
3320 (use (const_int 0))]
3323 [(set_attr "op_type" "RX")
3324 (set_attr "type" "la")])
3326 (define_expand "reload_insi"
3327 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3328 (match_operand:SI 1 "s390_plus_operand" "")
3329 (match_operand:SI 2 "register_operand" "=&a")])]
3333 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3339 ; adddf3 instruction pattern(s).
3342 (define_expand "adddf3"
3344 [(set (match_operand:DF 0 "register_operand" "=f,f")
3345 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3346 (match_operand:DF 2 "general_operand" "f,m")))
3347 (clobber (reg:CC 33))])]
3351 (define_insn "*adddf3"
3352 [(set (match_operand:DF 0 "register_operand" "=f,f")
3353 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3354 (match_operand:DF 2 "general_operand" "f,m")))
3355 (clobber (reg:CC 33))]
3356 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3360 [(set_attr "op_type" "RRE,RXE")
3361 (set_attr "type" "fsimpd,fsimpd")])
3363 (define_insn "*adddf3_ibm"
3364 [(set (match_operand:DF 0 "register_operand" "=f,f")
3365 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3366 (match_operand:DF 2 "general_operand" "f,m")))
3367 (clobber (reg:CC 33))]
3368 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3372 [(set_attr "op_type" "RR,RX")
3373 (set_attr "type" "fsimpd,fsimpd")])
3376 ; addsf3 instruction pattern(s).
3379 (define_expand "addsf3"
3381 [(set (match_operand:SF 0 "register_operand" "=f,f")
3382 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3383 (match_operand:SF 2 "general_operand" "f,m")))
3384 (clobber (reg:CC 33))])]
3388 (define_insn "*addsf3"
3389 [(set (match_operand:SF 0 "register_operand" "=f,f")
3390 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3391 (match_operand:SF 2 "general_operand" "f,m")))
3392 (clobber (reg:CC 33))]
3393 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3397 [(set_attr "op_type" "RRE,RXE")
3398 (set_attr "type" "fsimps,fsimps")])
3400 (define_insn "*addsf3"
3401 [(set (match_operand:SF 0 "register_operand" "=f,f")
3402 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3403 (match_operand:SF 2 "general_operand" "f,m")))
3404 (clobber (reg:CC 33))]
3405 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3409 [(set_attr "op_type" "RR,RX")
3410 (set_attr "type" "fsimps,fsimps")])
3414 ;;- Subtract instructions.
3418 ; subdi3 instruction pattern(s).
3421 (define_insn "*subdi3_sign"
3422 [(set (match_operand:DI 0 "register_operand" "=d,d")
3423 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3424 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3425 (clobber (reg:CC 33))]
3430 [(set_attr "op_type" "RRE,RXE")])
3432 (define_insn "*subdi3_zero_cc"
3434 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3435 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3437 (set (match_operand:DI 0 "register_operand" "=d,d")
3438 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3439 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3443 [(set_attr "op_type" "RRE,RXE")])
3445 (define_insn "*subdi3_zero_cconly"
3447 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3448 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3450 (clobber (match_scratch:DI 0 "=d,d"))]
3451 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3455 [(set_attr "op_type" "RRE,RXE")])
3457 (define_insn "*subdi3_zero"
3458 [(set (match_operand:DI 0 "register_operand" "=d,d")
3459 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3460 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3461 (clobber (reg:CC 33))]
3466 [(set_attr "op_type" "RRE,RXE")])
3468 (define_insn "*subdi3_cc"
3470 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3471 (match_operand:DI 2 "general_operand" "d,m"))
3473 (set (match_operand:DI 0 "register_operand" "=d,d")
3474 (minus:DI (match_dup 1) (match_dup 2)))]
3475 "s390_match_ccmode (insn, CCLmode)"
3479 [(set_attr "op_type" "RRE,RXE")])
3481 (define_insn "*subdi3_cconly"
3483 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3484 (match_operand:DI 2 "general_operand" "d,m"))
3486 (clobber (match_scratch:DI 0 "=d,d"))]
3487 "s390_match_ccmode (insn, CCLmode)"
3491 [(set_attr "op_type" "RRE,RXE")])
3493 (define_insn "*subdi3_64"
3494 [(set (match_operand:DI 0 "register_operand" "=d,d")
3495 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3496 (match_operand:DI 2 "general_operand" "d,m") ) )
3497 (clobber (reg:CC 33))]
3502 [(set_attr "op_type" "RRE,RRE")])
3504 (define_insn_and_split "*subdi3_31"
3505 [(set (match_operand:DI 0 "register_operand" "=&d")
3506 (minus:DI (match_operand:DI 1 "register_operand" "0")
3507 (match_operand:DI 2 "general_operand" "do") ) )
3508 (clobber (reg:CC 33))]
3511 "&& reload_completed"
3513 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3514 (clobber (reg:CC 33))])
3517 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3519 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3521 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3523 (label_ref (match_dup 9))))
3525 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3526 (clobber (reg:CC 33))])
3528 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3529 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3530 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3531 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3532 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3533 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3534 operands[9] = gen_label_rtx ();"
3535 [(set_attr "op_type" "NN")])
3537 (define_expand "subdi3"
3539 [(set (match_operand:DI 0 "register_operand" "")
3540 (minus:DI (match_operand:DI 1 "register_operand" "")
3541 (match_operand:DI 2 "general_operand" "")))
3542 (clobber (reg:CC 33))])]
3547 ; subsi3 instruction pattern(s).
3550 (define_insn "*subsi3_borrow_cc"
3552 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3553 (match_operand:SI 2 "general_operand" "d,m"))
3555 (set (match_operand:SI 0 "register_operand" "=d,d")
3556 (minus:SI (match_dup 1) (match_dup 2)))]
3557 "s390_match_ccmode(insn, CCL2mode)"
3561 [(set_attr "op_type" "RR,RX")])
3563 (define_insn "*subsi3_borrow_cconly"
3565 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3566 (match_operand:SI 2 "general_operand" "d,m"))
3568 (clobber (match_scratch:SI 0 "=d,d"))]
3569 "s390_match_ccmode(insn, CCL2mode)"
3573 [(set_attr "op_type" "RR,RX")])
3575 (define_insn "*subsi3_cc"
3577 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3578 (match_operand:SI 2 "general_operand" "d,m"))
3580 (set (match_operand:SI 0 "register_operand" "=d,d")
3581 (minus:SI (match_dup 1) (match_dup 2)))]
3582 "s390_match_ccmode(insn, CCLmode)"
3586 [(set_attr "op_type" "RR,RX")])
3588 (define_insn "*subsi3_cconly"
3590 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3591 (match_operand:SI 2 "general_operand" "d,m"))
3593 (clobber (match_scratch:SI 0 "=d,d"))]
3594 "s390_match_ccmode(insn, CCLmode)"
3598 [(set_attr "op_type" "RR,RX")])
3600 (define_insn "*subsi3_sign"
3601 [(set (match_operand:SI 0 "register_operand" "=d")
3602 (minus:SI (match_operand:SI 1 "register_operand" "0")
3603 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3604 (clobber (reg:CC 33))]
3607 [(set_attr "op_type" "RX")])
3609 (define_insn "*subsi3_sub"
3610 [(set (match_operand:SI 0 "register_operand" "=d")
3611 (minus:SI (match_operand:SI 1 "register_operand" "0")
3612 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3613 (clobber (reg:CC 33))]
3616 [(set_attr "op_type" "RX")])
3618 (define_insn "subsi3"
3619 [(set (match_operand:SI 0 "register_operand" "=d,d")
3620 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3621 (match_operand:SI 2 "general_operand" "d,m")))
3622 (clobber (reg:CC 33))]
3627 [(set_attr "op_type" "RR,RX")])
3631 ; subdf3 instruction pattern(s).
3634 (define_expand "subdf3"
3636 [(set (match_operand:DF 0 "register_operand" "=f,f")
3637 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3638 (match_operand:DF 2 "general_operand" "f,m")))
3639 (clobber (reg:CC 33))])]
3643 (define_insn "*subdf3"
3644 [(set (match_operand:DF 0 "register_operand" "=f,f")
3645 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3646 (match_operand:DF 2 "general_operand" "f,m")))
3647 (clobber (reg:CC 33))]
3648 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3652 [(set_attr "op_type" "RRE,RXE")
3653 (set_attr "type" "fsimpd,fsimpd")])
3655 (define_insn "*subdf3_ibm"
3656 [(set (match_operand:DF 0 "register_operand" "=f,f")
3657 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3658 (match_operand:DF 2 "general_operand" "f,m")))
3659 (clobber (reg:CC 33))]
3660 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3664 [(set_attr "op_type" "RR,RX")
3665 (set_attr "type" "fsimpd,fsimpd")])
3668 ; subsf3 instruction pattern(s).
3671 (define_expand "subsf3"
3673 [(set (match_operand:SF 0 "register_operand" "=f,f")
3674 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3675 (match_operand:SF 2 "general_operand" "f,m")))
3676 (clobber (reg:CC 33))])]
3680 (define_insn "*subsf3"
3681 [(set (match_operand:SF 0 "register_operand" "=f,f")
3682 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3683 (match_operand:SF 2 "general_operand" "f,m")))
3684 (clobber (reg:CC 33))]
3685 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3689 [(set_attr "op_type" "RRE,RXE")
3690 (set_attr "type" "fsimps,fsimps")])
3692 (define_insn "*subsf3_ibm"
3693 [(set (match_operand:SF 0 "register_operand" "=f,f")
3694 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3695 (match_operand:SF 2 "general_operand" "f,m")))
3696 (clobber (reg:CC 33))]
3697 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3701 [(set_attr "op_type" "RR,RX")
3702 (set_attr "type" "fsimps,fsimps")])
3706 ;;- Multiply instructions.
3710 ; muldi3 instruction pattern(s).
3713 (define_insn "*muldi3_sign"
3714 [(set (match_operand:DI 0 "register_operand" "=d,d")
3715 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3716 (match_operand:DI 1 "register_operand" "0,0")))]
3721 [(set_attr "op_type" "RRE,RXE")
3722 (set_attr "type" "imul")])
3725 (define_insn "muldi3"
3726 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3727 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3728 (match_operand:DI 2 "general_operand" "d,K,m")))]
3734 [(set_attr "op_type" "RRE,RI,RXE")
3735 (set_attr "type" "imul")])
3738 ; mulsi3 instruction pattern(s).
3741 (define_insn "mulsi3"
3742 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3743 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3744 (match_operand:SI 2 "general_operand" "d,K,m")))]
3750 [(set_attr "op_type" "RRE,RI,RX")
3751 (set_attr "type" "imul")])
3754 ; mulsidi3 instruction pattern(s).
3757 (define_expand "mulsidi3"
3758 [(set (match_operand:DI 0 "register_operand" "")
3759 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3760 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3766 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3767 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3770 gen_rtx_EXPR_LIST (REG_EQUAL,
3771 gen_rtx_MULT (DImode,
3772 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3773 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3778 (define_insn "mulsi_6432"
3779 [(set (match_operand:DI 0 "register_operand" "=d,d")
3780 (mult:DI (sign_extend:DI
3781 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3783 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3788 [(set_attr "op_type" "RR,RX")
3789 (set_attr "type" "imul")])
3792 ; muldf3 instruction pattern(s).
3795 (define_expand "muldf3"
3797 [(set (match_operand:DF 0 "register_operand" "=f,f")
3798 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3799 (match_operand:DF 2 "general_operand" "f,m")))
3800 (clobber (reg:CC 33))])]
3804 (define_insn "*muldf3"
3805 [(set (match_operand:DF 0 "register_operand" "=f,f")
3806 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3807 (match_operand:DF 2 "general_operand" "f,m")))
3808 (clobber (reg:CC 33))]
3809 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3813 [(set_attr "op_type" "RRE,RXE")
3814 (set_attr "type" "fmuld")])
3816 (define_insn "*muldf3_ibm"
3817 [(set (match_operand:DF 0 "register_operand" "=f,f")
3818 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3819 (match_operand:DF 2 "general_operand" "f,m")))
3820 (clobber (reg:CC 33))]
3821 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3825 [(set_attr "op_type" "RR,RX")
3826 (set_attr "type" "fmuld")])
3829 ; mulsf3 instruction pattern(s).
3832 (define_expand "mulsf3"
3834 [(set (match_operand:SF 0 "register_operand" "=f,f")
3835 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3836 (match_operand:SF 2 "general_operand" "f,m")))
3837 (clobber (reg:CC 33))])]
3841 (define_insn "*mulsf3"
3842 [(set (match_operand:SF 0 "register_operand" "=f,f")
3843 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3844 (match_operand:SF 2 "general_operand" "f,m")))
3845 (clobber (reg:CC 33))]
3846 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3850 [(set_attr "op_type" "RRE,RXE")
3851 (set_attr "type" "fmuls")])
3853 (define_insn "*mulsf3_ibm"
3854 [(set (match_operand:SF 0 "register_operand" "=f,f")
3855 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3856 (match_operand:SF 2 "general_operand" "f,m")))
3857 (clobber (reg:CC 33))]
3858 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3862 [(set_attr "op_type" "RR,RX")
3863 (set_attr "type" "fmuls")])
3867 ;;- Divide and modulo instructions.
3871 ; divmoddi4 instruction pattern(s).
3874 (define_expand "divmoddi4"
3875 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3876 (div:DI (match_operand:DI 1 "general_operand" "")
3877 (match_operand:DI 2 "general_operand" "")))
3878 (set (match_operand:DI 3 "general_operand" "")
3879 (mod:DI (match_dup 1) (match_dup 2)))])
3880 (clobber (match_dup 4))]
3884 rtx insn, div_equal, mod_equal, equal;
3886 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3887 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3888 equal = gen_rtx_IOR (TImode,
3889 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3890 gen_rtx_ASHIFT (TImode,
3891 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3894 operands[4] = gen_reg_rtx(TImode);
3895 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3896 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3897 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3898 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3900 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3902 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3904 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3906 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3908 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3913 (define_insn "divmodtidi3"
3914 [(set (match_operand:TI 0 "register_operand" "=d,d")
3917 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3918 (match_operand:DI 2 "general_operand" "d,m")))
3921 (mod:DI (truncate:DI (match_dup 1))
3928 [(set_attr "op_type" "RRE,RXE")
3929 (set_attr "type" "idiv")])
3931 (define_insn "divmodtisi3"
3932 [(set (match_operand:TI 0 "register_operand" "=d,d")
3935 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3936 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3939 (mod:DI (truncate:DI (match_dup 1))
3940 (sign_extend:DI (match_dup 2))))
3946 [(set_attr "op_type" "RRE,RXE")
3947 (set_attr "type" "idiv")])
3950 ; udivmoddi4 instruction pattern(s).
3953 (define_expand "udivmoddi4"
3954 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3955 (udiv:DI (match_operand:DI 1 "general_operand" "")
3956 (match_operand:DI 2 "nonimmediate_operand" "")))
3957 (set (match_operand:DI 3 "general_operand" "")
3958 (umod:DI (match_dup 1) (match_dup 2)))])
3959 (clobber (match_dup 4))]
3963 rtx insn, div_equal, mod_equal, equal;
3965 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3966 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3967 equal = gen_rtx_IOR (TImode,
3968 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3969 gen_rtx_ASHIFT (TImode,
3970 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3973 operands[4] = gen_reg_rtx(TImode);
3974 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3975 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3976 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3977 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3979 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3981 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3983 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3985 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3987 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3992 (define_insn "udivmodtidi3"
3993 [(set (match_operand:TI 0 "register_operand" "=d,d")
3994 (ior:TI (zero_extend:TI
3996 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3998 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4002 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
4008 [(set_attr "op_type" "RRE,RXE")
4009 (set_attr "type" "idiv")])
4012 ; divmodsi4 instruction pattern(s).
4015 (define_expand "divmodsi4"
4016 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4017 (div:SI (match_operand:SI 1 "general_operand" "")
4018 (match_operand:SI 2 "nonimmediate_operand" "")))
4019 (set (match_operand:SI 3 "general_operand" "")
4020 (mod:SI (match_dup 1) (match_dup 2)))])
4021 (clobber (match_dup 4))]
4025 rtx insn, div_equal, mod_equal, equal;
4027 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4028 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4029 equal = gen_rtx_IOR (DImode,
4030 gen_rtx_ZERO_EXTEND (DImode, div_equal),
4031 gen_rtx_ASHIFT (DImode,
4032 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4035 operands[4] = gen_reg_rtx(DImode);
4036 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4037 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4039 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4041 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4043 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4045 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4047 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4052 (define_insn "divmoddisi3"
4053 [(set (match_operand:DI 0 "register_operand" "=d,d")
4054 (ior:DI (zero_extend:DI
4056 (div:DI (match_operand:DI 1 "register_operand" "0,0")
4058 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4062 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
4068 [(set_attr "op_type" "RR,RX")
4069 (set_attr "type" "idiv")])
4072 ; udivsi3 and umodsi3 instruction pattern(s).
4076 (define_expand "udivsi3"
4077 [(set (match_operand:SI 0 "register_operand" "=d")
4078 (udiv:SI (match_operand:SI 1 "general_operand" "")
4079 (match_operand:SI 2 "general_operand" "")))
4080 (clobber (match_dup 3))]
4084 rtx insn, udiv_equal, umod_equal, equal;
4086 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4087 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4088 equal = gen_rtx_IOR (DImode,
4089 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4090 gen_rtx_ASHIFT (DImode,
4091 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4094 operands[3] = gen_reg_rtx (DImode);
4096 if (CONSTANT_P (operands[2]))
4098 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4100 rtx label1 = gen_label_rtx ();
4102 operands[1] = make_safe_from (operands[1], operands[0]);
4103 emit_move_insn (operands[0], const0_rtx);
4104 emit_insn (gen_cmpsi (operands[1], operands[2]));
4105 emit_jump_insn (gen_bltu (label1));
4106 emit_move_insn (operands[0], const1_rtx);
4107 emit_label (label1);
4111 operands[2] = force_reg (SImode, operands[2]);
4112 operands[2] = make_safe_from (operands[2], operands[0]);
4114 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4115 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4118 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4120 insn = emit_move_insn (operands[0],
4121 gen_lowpart (SImode, operands[3]));
4123 gen_rtx_EXPR_LIST (REG_EQUAL,
4124 udiv_equal, REG_NOTES (insn));
4129 rtx label1 = gen_label_rtx ();
4130 rtx label2 = gen_label_rtx ();
4131 rtx label3 = gen_label_rtx ();
4133 operands[1] = force_reg (SImode, operands[1]);
4134 operands[1] = make_safe_from (operands[1], operands[0]);
4135 operands[2] = force_reg (SImode, operands[2]);
4136 operands[2] = make_safe_from (operands[2], operands[0]);
4138 emit_move_insn (operands[0], const0_rtx);
4139 emit_insn (gen_cmpsi (operands[2], operands[1]));
4140 emit_jump_insn (gen_bgtu (label3));
4141 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4142 emit_jump_insn (gen_blt (label2));
4143 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4144 emit_jump_insn (gen_beq (label1));
4145 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4146 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4149 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4151 insn = emit_move_insn (operands[0],
4152 gen_lowpart (SImode, operands[3]));
4154 gen_rtx_EXPR_LIST (REG_EQUAL,
4155 udiv_equal, REG_NOTES (insn));
4157 emit_label (label1);
4158 emit_move_insn (operands[0], operands[1]);
4160 emit_label (label2);
4161 emit_move_insn (operands[0], const1_rtx);
4162 emit_label (label3);
4164 emit_move_insn (operands[0], operands[0]);
4168 (define_expand "umodsi3"
4169 [(set (match_operand:SI 0 "register_operand" "=d")
4170 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4171 (match_operand:SI 2 "nonimmediate_operand" "")))
4172 (clobber (match_dup 3))]
4176 rtx insn, udiv_equal, umod_equal, equal;
4178 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4179 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4180 equal = gen_rtx_IOR (DImode,
4181 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4182 gen_rtx_ASHIFT (DImode,
4183 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4186 operands[3] = gen_reg_rtx (DImode);
4188 if (CONSTANT_P (operands[2]))
4190 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4192 rtx label1 = gen_label_rtx ();
4194 operands[1] = make_safe_from (operands[1], operands[0]);
4195 emit_move_insn (operands[0], operands[1]);
4196 emit_insn (gen_cmpsi (operands[0], operands[2]));
4197 emit_jump_insn (gen_bltu (label1));
4198 emit_insn (gen_abssi2 (operands[0], operands[2]));
4199 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4200 emit_label (label1);
4204 operands[2] = force_reg (SImode, operands[2]);
4205 operands[2] = make_safe_from (operands[2], operands[0]);
4207 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4208 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4211 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4213 insn = emit_move_insn (operands[0],
4214 gen_highpart (SImode, operands[3]));
4216 gen_rtx_EXPR_LIST (REG_EQUAL,
4217 umod_equal, REG_NOTES (insn));
4222 rtx label1 = gen_label_rtx ();
4223 rtx label2 = gen_label_rtx ();
4224 rtx label3 = gen_label_rtx ();
4226 operands[1] = force_reg (SImode, operands[1]);
4227 operands[1] = make_safe_from (operands[1], operands[0]);
4228 operands[2] = force_reg (SImode, operands[2]);
4229 operands[2] = make_safe_from (operands[2], operands[0]);
4231 emit_move_insn(operands[0], operands[1]);
4232 emit_insn (gen_cmpsi (operands[2], operands[1]));
4233 emit_jump_insn (gen_bgtu (label3));
4234 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4235 emit_jump_insn (gen_blt (label2));
4236 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4237 emit_jump_insn (gen_beq (label1));
4238 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4239 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4242 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4244 insn = emit_move_insn (operands[0],
4245 gen_highpart (SImode, operands[3]));
4247 gen_rtx_EXPR_LIST (REG_EQUAL,
4248 umod_equal, REG_NOTES (insn));
4250 emit_label (label1);
4251 emit_move_insn (operands[0], const0_rtx);
4253 emit_label (label2);
4254 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4255 emit_label (label3);
4261 ; divdf3 instruction pattern(s).
4264 (define_expand "divdf3"
4266 [(set (match_operand:DF 0 "register_operand" "=f,f")
4267 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4268 (match_operand:DF 2 "general_operand" "f,m")))
4269 (clobber (reg:CC 33))])]
4273 (define_insn "*divdf3"
4274 [(set (match_operand:DF 0 "register_operand" "=f,f")
4275 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4276 (match_operand:DF 2 "general_operand" "f,m")))
4277 (clobber (reg:CC 33))]
4278 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4282 [(set_attr "op_type" "RRE,RXE")
4283 (set_attr "type" "fdivd")])
4285 (define_insn "*divdf3_ibm"
4286 [(set (match_operand:DF 0 "register_operand" "=f,f")
4287 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4288 (match_operand:DF 2 "general_operand" "f,m")))
4289 (clobber (reg:CC 33))]
4290 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4294 [(set_attr "op_type" "RR,RX")
4295 (set_attr "type" "fdivd")])
4298 ; divsf3 instruction pattern(s).
4301 (define_expand "divsf3"
4303 [(set (match_operand:SF 0 "register_operand" "=f,f")
4304 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4305 (match_operand:SF 2 "general_operand" "f,m")))
4306 (clobber (reg:CC 33))])]
4310 (define_insn "*divsf3"
4311 [(set (match_operand:SF 0 "register_operand" "=f,f")
4312 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4313 (match_operand:SF 2 "general_operand" "f,m")))
4314 (clobber (reg:CC 33))]
4315 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4319 [(set_attr "op_type" "RRE,RXE")
4320 (set_attr "type" "fdivs")])
4322 (define_insn "*divsf3"
4323 [(set (match_operand:SF 0 "register_operand" "=f,f")
4324 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4325 (match_operand:SF 2 "general_operand" "f,m")))
4326 (clobber (reg:CC 33))]
4327 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4331 [(set_attr "op_type" "RR,RX")
4332 (set_attr "type" "fdivs")])
4336 ;;- And instructions.
4340 ; anddi3 instruction pattern(s).
4343 (define_insn "*anddi3_cc"
4345 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4346 (match_operand:DI 2 "general_operand" "d,m"))
4348 (set (match_operand:DI 0 "register_operand" "=d,d")
4349 (and:DI (match_dup 1) (match_dup 2)))]
4350 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4354 [(set_attr "op_type" "RRE,RXE")])
4356 (define_insn "*anddi3_cconly"
4358 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4359 (match_operand:DI 2 "general_operand" "d,m"))
4361 (clobber (match_scratch:DI 0 "=d,d"))]
4362 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4366 [(set_attr "op_type" "RRE,RXE")])
4368 (define_insn "*anddi3_ni"
4369 [(set (match_operand:DI 0 "register_operand" "=d")
4370 (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4371 (match_operand:DI 2 "immediate_operand" "n")))
4372 (clobber (reg:CC 33))]
4373 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4376 int part = s390_single_hi (operands[2], DImode, -1);
4377 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4381 case 0: return \"nihh\\t%0,%x2\";
4382 case 1: return \"nihl\\t%0,%x2\";
4383 case 2: return \"nilh\\t%0,%x2\";
4384 case 3: return \"nill\\t%0,%x2\";
4388 [(set_attr "op_type" "RI")])
4390 (define_insn "anddi3"
4391 [(set (match_operand:DI 0 "register_operand" "=d,d")
4392 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4393 (match_operand:DI 2 "general_operand" "d,m")))
4394 (clobber (reg:CC 33))]
4399 [(set_attr "op_type" "RRE,RXE")])
4401 (define_insn "*anddi3_ss"
4402 [(set (match_operand:DI 0 "s_operand" "=Q")
4403 (and:DI (match_dup 0)
4404 (match_operand:DI 1 "s_imm_operand" "Q")))
4405 (clobber (reg:CC 33))]
4407 "nc\\t%O0(8,%R0),%1"
4408 [(set_attr "op_type" "SS")])
4410 (define_insn "*anddi3_ss_inv"
4411 [(set (match_operand:DI 0 "s_operand" "=Q")
4412 (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4414 (clobber (reg:CC 33))]
4416 "nc\\t%O0(8,%R0),%1"
4417 [(set_attr "op_type" "SS")])
4420 ; andsi3 instruction pattern(s).
4423 (define_insn "*andsi3_cc"
4425 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4426 (match_operand:SI 2 "general_operand" "d,m"))
4428 (set (match_operand:SI 0 "register_operand" "=d,d")
4429 (and:SI (match_dup 1) (match_dup 2)))]
4430 "s390_match_ccmode(insn, CCTmode)"
4434 [(set_attr "op_type" "RR,RX")])
4436 (define_insn "*andsi3_cconly"
4438 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4439 (match_operand:SI 2 "general_operand" "d,m"))
4441 (clobber (match_scratch:SI 0 "=d,d"))]
4442 "s390_match_ccmode(insn, CCTmode)"
4446 [(set_attr "op_type" "RR,RX")])
4448 (define_insn "*andsi3_ni"
4449 [(set (match_operand:SI 0 "register_operand" "=d")
4450 (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4451 (match_operand:SI 2 "immediate_operand" "n")))
4452 (clobber (reg:CC 33))]
4453 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4456 int part = s390_single_hi (operands[2], SImode, -1);
4457 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4461 case 0: return \"nilh\\t%0,%x2\";
4462 case 1: return \"nill\\t%0,%x2\";
4466 [(set_attr "op_type" "RI")])
4468 (define_insn "andsi3"
4469 [(set (match_operand:SI 0 "register_operand" "=d,d")
4470 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4471 (match_operand:SI 2 "general_operand" "d,m")))
4472 (clobber (reg:CC 33))]
4477 [(set_attr "op_type" "RR,RX")])
4479 (define_insn "*andsi3_ss"
4480 [(set (match_operand:SI 0 "s_operand" "=Q")
4481 (and:SI (match_dup 0)
4482 (match_operand:SI 1 "s_imm_operand" "Q")))
4483 (clobber (reg:CC 33))]
4485 "nc\\t%O0(4,%R0),%1"
4486 [(set_attr "op_type" "SS")])
4488 (define_insn "*andsi3_ss_inv"
4489 [(set (match_operand:SI 0 "s_operand" "=Q")
4490 (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4492 (clobber (reg:CC 33))]
4494 "nc\\t%O0(4,%R0),%1"
4495 [(set_attr "op_type" "SS")])
4498 ; andhi3 instruction pattern(s).
4501 (define_insn "*andhi3_ni"
4502 [(set (match_operand:HI 0 "register_operand" "=d,d")
4503 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4504 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4505 (clobber (reg:CC 33))]
4510 [(set_attr "op_type" "RR,RI")])
4512 (define_insn "andhi3"
4513 [(set (match_operand:HI 0 "register_operand" "=d")
4514 (and:HI (match_operand:HI 1 "register_operand" "%0")
4515 (match_operand:HI 2 "nonmemory_operand" "d")))
4516 (clobber (reg:CC 33))]
4519 [(set_attr "op_type" "RR")])
4521 (define_insn "*andhi3_ss"
4522 [(set (match_operand:HI 0 "s_operand" "=Q")
4523 (and:HI (match_dup 0)
4524 (match_operand:HI 1 "s_imm_operand" "Q")))
4525 (clobber (reg:CC 33))]
4527 "nc\\t%O0(2,%R0),%1"
4528 [(set_attr "op_type" "SS")])
4530 (define_insn "*andhi3_ss_inv"
4531 [(set (match_operand:HI 0 "s_operand" "=Q")
4532 (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4534 (clobber (reg:CC 33))]
4536 "nc\\t%O0(2,%R0),%1"
4537 [(set_attr "op_type" "SS")])
4540 ; andqi3 instruction pattern(s).
4543 (define_insn "*andqi3_ni"
4544 [(set (match_operand:QI 0 "register_operand" "=d,d")
4545 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4546 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4547 (clobber (reg:CC 33))]
4552 [(set_attr "op_type" "RR,RI")])
4554 (define_insn "andqi3"
4555 [(set (match_operand:QI 0 "register_operand" "=d")
4556 (and:QI (match_operand:QI 1 "register_operand" "%0")
4557 (match_operand:QI 2 "nonmemory_operand" "d")))
4558 (clobber (reg:CC 33))]
4561 [(set_attr "op_type" "RR")])
4563 (define_insn "*andqi3_ss"
4564 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4565 (and:QI (match_dup 0)
4566 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4567 (clobber (reg:CC 33))]
4572 [(set_attr "op_type" "SI,SS")])
4574 (define_insn "*andqi3_ss_inv"
4575 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4576 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4578 (clobber (reg:CC 33))]
4583 [(set_attr "op_type" "SI,SS")])
4587 ;;- Bit set (inclusive or) instructions.
4591 ; iordi3 instruction pattern(s).
4594 (define_insn "*iordi3_cc"
4596 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4597 (match_operand:DI 2 "general_operand" "d,m"))
4599 (set (match_operand:DI 0 "register_operand" "=d,d")
4600 (ior:DI (match_dup 1) (match_dup 2)))]
4601 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4605 [(set_attr "op_type" "RRE,RXE")])
4607 (define_insn "*iordi3_cconly"
4609 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4610 (match_operand:DI 2 "general_operand" "d,m"))
4612 (clobber (match_scratch:DI 0 "=d,d"))]
4613 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4617 [(set_attr "op_type" "RRE,RXE")])
4619 (define_insn "*iordi3_oi"
4620 [(set (match_operand:DI 0 "register_operand" "=d")
4621 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4622 (match_operand:DI 2 "immediate_operand" "n")))
4623 (clobber (reg:CC 33))]
4624 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4627 int part = s390_single_hi (operands[2], DImode, 0);
4628 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4632 case 0: return \"oihh\\t%0,%x2\";
4633 case 1: return \"oihl\\t%0,%x2\";
4634 case 2: return \"oilh\\t%0,%x2\";
4635 case 3: return \"oill\\t%0,%x2\";
4639 [(set_attr "op_type" "RI")])
4641 (define_insn "iordi3"
4642 [(set (match_operand:DI 0 "register_operand" "=d,d")
4643 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4644 (match_operand:DI 2 "general_operand" "d,m")))
4645 (clobber (reg:CC 33))]
4650 [(set_attr "op_type" "RRE,RXE")])
4652 (define_insn "*iordi3_ss"
4653 [(set (match_operand:DI 0 "s_operand" "=Q")
4654 (ior:DI (match_dup 0)
4655 (match_operand:DI 1 "s_imm_operand" "Q")))
4656 (clobber (reg:CC 33))]
4658 "oc\\t%O0(8,%R0),%1"
4659 [(set_attr "op_type" "SS")])
4661 (define_insn "*iordi3_ss_inv"
4662 [(set (match_operand:DI 0 "s_operand" "=Q")
4663 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4665 (clobber (reg:CC 33))]
4667 "oc\\t%O0(8,%R0),%1"
4668 [(set_attr "op_type" "SS")])
4671 ; iorsi3 instruction pattern(s).
4674 (define_insn "*iorsi3_cc"
4676 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4677 (match_operand:SI 2 "general_operand" "d,m"))
4679 (set (match_operand:SI 0 "register_operand" "=d,d")
4680 (ior:SI (match_dup 1) (match_dup 2)))]
4681 "s390_match_ccmode(insn, CCTmode)"
4685 [(set_attr "op_type" "RR,RX")])
4687 (define_insn "*iorsi3_cconly"
4689 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4690 (match_operand:SI 2 "general_operand" "d,m"))
4692 (clobber (match_scratch:SI 0 "=d,d"))]
4693 "s390_match_ccmode(insn, CCTmode)"
4697 [(set_attr "op_type" "RR,RX")])
4699 (define_insn "*iorsi3_oi"
4700 [(set (match_operand:SI 0 "register_operand" "=d")
4701 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4702 (match_operand:SI 2 "immediate_operand" "n")))
4703 (clobber (reg:CC 33))]
4704 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4707 int part = s390_single_hi (operands[2], SImode, 0);
4708 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4712 case 0: return \"oilh\\t%0,%x2\";
4713 case 1: return \"oill\\t%0,%x2\";
4717 [(set_attr "op_type" "RI")])
4719 (define_insn "iorsi3"
4720 [(set (match_operand:SI 0 "register_operand" "=d,d")
4721 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4722 (match_operand:SI 2 "general_operand" "d,m")))
4723 (clobber (reg:CC 33))]
4728 [(set_attr "op_type" "RR,RX")])
4730 (define_insn "*iorsi3_ss"
4731 [(set (match_operand:SI 0 "s_operand" "=Q")
4732 (ior:SI (match_dup 0)
4733 (match_operand:SI 1 "s_imm_operand" "Q")))
4734 (clobber (reg:CC 33))]
4736 "oc\\t%O0(4,%R0),%1"
4737 [(set_attr "op_type" "SS")])
4739 (define_insn "*iorsi3_ss_inv"
4740 [(set (match_operand:SI 0 "s_operand" "=Q")
4741 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4743 (clobber (reg:CC 33))]
4745 "oc\\t%O0(4,%R0),%1"
4746 [(set_attr "op_type" "SS")])
4749 ; iorhi3 instruction pattern(s).
4752 (define_insn "*iorhi3_oi"
4753 [(set (match_operand:HI 0 "register_operand" "=d,d")
4754 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4755 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4756 (clobber (reg:CC 33))]
4761 [(set_attr "op_type" "RR,RI")])
4763 (define_insn "iorhi3"
4764 [(set (match_operand:HI 0 "register_operand" "=d")
4765 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4766 (match_operand:HI 2 "nonmemory_operand" "d")))
4767 (clobber (reg:CC 33))]
4770 [(set_attr "op_type" "RR")])
4772 (define_insn "*iorhi3_ss"
4773 [(set (match_operand:HI 0 "s_operand" "=Q")
4774 (ior:HI (match_dup 0)
4775 (match_operand:HI 1 "s_imm_operand" "Q")))
4776 (clobber (reg:CC 33))]
4778 "oc\\t%O0(2,%R0),%1"
4779 [(set_attr "op_type" "SS")])
4781 (define_insn "*iorhi3_ss_inv"
4782 [(set (match_operand:HI 0 "s_operand" "=Q")
4783 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4785 (clobber (reg:CC 33))]
4787 "oc\\t%O0(2,%R0),%1"
4788 [(set_attr "op_type" "SS")])
4791 ; iorqi3 instruction pattern(s).
4794 (define_insn "*iorqi3_oi"
4795 [(set (match_operand:QI 0 "register_operand" "=d,d")
4796 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4797 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4798 (clobber (reg:CC 33))]
4803 [(set_attr "op_type" "RR,RI")])
4805 (define_insn "iorqi3"
4806 [(set (match_operand:QI 0 "register_operand" "=d")
4807 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4808 (match_operand:QI 2 "nonmemory_operand" "d")))
4809 (clobber (reg:CC 33))]
4812 [(set_attr "op_type" "RR")])
4814 (define_insn "*iorqi3_ss"
4815 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4816 (ior:QI (match_dup 0)
4817 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4818 (clobber (reg:CC 33))]
4823 [(set_attr "op_type" "SI,SS")])
4825 (define_insn "*iorqi3_ss_inv"
4826 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4827 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4829 (clobber (reg:CC 33))]
4834 [(set_attr "op_type" "SI,SS")])
4838 ;;- Xor instructions.
4842 ; xordi3 instruction pattern(s).
4845 (define_insn "*xordi3_cc"
4847 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4848 (match_operand:DI 2 "general_operand" "d,m"))
4850 (set (match_operand:DI 0 "register_operand" "=d,d")
4851 (xor:DI (match_dup 1) (match_dup 2)))]
4852 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4856 [(set_attr "op_type" "RRE,RXE")])
4858 (define_insn "*xordi3_cconly"
4860 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4861 (match_operand:DI 2 "general_operand" "d,m"))
4863 (clobber (match_scratch:DI 0 "=d,d"))]
4864 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4868 [(set_attr "op_type" "RRE,RXE")])
4870 (define_insn "xordi3"
4871 [(set (match_operand:DI 0 "register_operand" "=d,d")
4872 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4873 (match_operand:DI 2 "general_operand" "d,m")))
4874 (clobber (reg:CC 33))]
4879 [(set_attr "op_type" "RRE,RXE")])
4881 (define_insn "*xordi3_ss"
4882 [(set (match_operand:DI 0 "s_operand" "=Q")
4883 (xor:DI (match_dup 0)
4884 (match_operand:DI 1 "s_imm_operand" "Q")))
4885 (clobber (reg:CC 33))]
4887 "xc\\t%O0(8,%R0),%1"
4888 [(set_attr "op_type" "SS")])
4890 (define_insn "*xordi3_ss_inv"
4891 [(set (match_operand:DI 0 "s_operand" "=Q")
4892 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4894 (clobber (reg:CC 33))]
4896 "xc\\t%O0(8,%R0),%1"
4897 [(set_attr "op_type" "SS")])
4900 ; xorsi3 instruction pattern(s).
4903 (define_insn "*xorsi3_cc"
4905 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4906 (match_operand:SI 2 "general_operand" "d,m"))
4908 (set (match_operand:SI 0 "register_operand" "=d,d")
4909 (xor:SI (match_dup 1) (match_dup 2)))]
4910 "s390_match_ccmode(insn, CCTmode)"
4914 [(set_attr "op_type" "RR,RX")])
4916 (define_insn "*xorsi3_cconly"
4918 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4919 (match_operand:SI 2 "general_operand" "d,m"))
4921 (clobber (match_scratch:SI 0 "=d,d"))]
4922 "s390_match_ccmode(insn, CCTmode)"
4926 [(set_attr "op_type" "RR,RX")])
4928 (define_insn "xorsi3"
4929 [(set (match_operand:SI 0 "register_operand" "=d,d")
4930 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4931 (match_operand:SI 2 "general_operand" "d,m")))
4932 (clobber (reg:CC 33))]
4937 [(set_attr "op_type" "RR,RX")])
4939 (define_insn "*xorsi3_ss"
4940 [(set (match_operand:SI 0 "s_operand" "=Q")
4941 (xor:SI (match_dup 0)
4942 (match_operand:SI 1 "s_imm_operand" "Q")))
4943 (clobber (reg:CC 33))]
4945 "xc\\t%O0(4,%R0),%1"
4946 [(set_attr "op_type" "SS")])
4948 (define_insn "*xorsi3_ss_inv"
4949 [(set (match_operand:SI 0 "s_operand" "=Q")
4950 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
4952 (clobber (reg:CC 33))]
4954 "xc\\t%O0(4,%R0),%1"
4955 [(set_attr "op_type" "SS")])
4958 ; xorhi3 instruction pattern(s).
4961 (define_insn "xorhi3"
4962 [(set (match_operand:HI 0 "register_operand" "=d")
4963 (xor:HI (match_operand:HI 1 "register_operand" "%0")
4964 (match_operand:HI 2 "nonmemory_operand" "d")))
4965 (clobber (reg:CC 33))]
4968 [(set_attr "op_type" "RR")
4969 (set_attr "atype" "reg")])
4971 (define_insn "*xorhi3_ss"
4972 [(set (match_operand:HI 0 "s_operand" "=Q")
4973 (xor:HI (match_dup 0)
4974 (match_operand:HI 1 "s_imm_operand" "Q")))
4975 (clobber (reg:CC 33))]
4977 "xc\\t%O0(2,%R0),%1"
4978 [(set_attr "op_type" "SS")])
4980 (define_insn "*xorhi3_ss_inv"
4981 [(set (match_operand:HI 0 "s_operand" "=Q")
4982 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
4984 (clobber (reg:CC 33))]
4986 "xc\\t%O0(2,%R0),%1"
4987 [(set_attr "op_type" "SS")])
4990 ; xorqi3 instruction pattern(s).
4993 (define_insn "xorqi3"
4994 [(set (match_operand:QI 0 "register_operand" "=d")
4995 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4996 (match_operand:QI 2 "nonmemory_operand" "d")))
4997 (clobber (reg:CC 33))]
5000 [(set_attr "op_type" "RR")])
5002 (define_insn "*xorqi3_ss"
5003 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5004 (xor:QI (match_dup 0)
5005 (match_operand:QI 1 "s_imm_operand" "n,Q")))
5006 (clobber (reg:CC 33))]
5011 [(set_attr "op_type" "SI,SS")])
5013 (define_insn "*xorqi3_ss_inv"
5014 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5015 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
5017 (clobber (reg:CC 33))]
5022 [(set_attr "op_type" "SI,SS")])
5026 ;;- Negate instructions.
5030 ; negdi2 instruction pattern(s).
5033 (define_expand "negdi2"
5035 [(set (match_operand:DI 0 "register_operand" "=d")
5036 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5037 (clobber (reg:CC 33))])]
5041 (define_insn "*negdi2_64"
5042 [(set (match_operand:DI 0 "register_operand" "=d")
5043 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5044 (clobber (reg:CC 33))]
5047 [(set_attr "op_type" "RR")])
5049 (define_insn "*negdi2_31"
5050 [(set (match_operand:DI 0 "register_operand" "=d")
5051 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5052 (clobber (reg:CC 33))]
5057 xop[0] = gen_label_rtx ();
5058 output_asm_insn (\"lcr\\t%0,%1\", operands);
5059 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5060 output_asm_insn (\"je\\t%l0\", xop);
5061 output_asm_insn (\"bctr\\t%0,0\", operands);
5062 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5063 CODE_LABEL_NUMBER (xop[0]));
5066 [(set_attr "op_type" "NN")
5067 (set_attr "type" "other")
5068 (set_attr "length" "10")])
5071 ; negsi2 instruction pattern(s).
5074 (define_insn "negsi2"
5075 [(set (match_operand:SI 0 "register_operand" "=d")
5076 (neg:SI (match_operand:SI 1 "register_operand" "d")))
5077 (clobber (reg:CC 33))]
5080 [(set_attr "op_type" "RR")])
5083 ; negdf2 instruction pattern(s).
5086 (define_expand "negdf2"
5088 [(set (match_operand:DF 0 "register_operand" "=f")
5089 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5090 (clobber (reg:CC 33))])]
5094 (define_insn "*negdf2"
5095 [(set (match_operand:DF 0 "register_operand" "=f")
5096 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5097 (clobber (reg:CC 33))]
5098 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5100 [(set_attr "op_type" "RRE")
5101 (set_attr "type" "fsimpd")])
5103 (define_insn "*negdf2_ibm"
5104 [(set (match_operand:DF 0 "register_operand" "=f")
5105 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5106 (clobber (reg:CC 33))]
5107 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5109 [(set_attr "op_type" "RR")
5110 (set_attr "type" "fsimpd")])
5113 ; negsf2 instruction pattern(s).
5116 (define_expand "negsf2"
5118 [(set (match_operand:SF 0 "register_operand" "=f")
5119 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5120 (clobber (reg:CC 33))])]
5124 (define_insn "*negsf2"
5125 [(set (match_operand:SF 0 "register_operand" "=f")
5126 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5127 (clobber (reg:CC 33))]
5128 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5130 [(set_attr "op_type" "RRE")
5131 (set_attr "type" "fsimps")])
5133 (define_insn "*negsf2"
5134 [(set (match_operand:SF 0 "register_operand" "=f")
5135 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5136 (clobber (reg:CC 33))]
5137 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5139 [(set_attr "op_type" "RR")
5140 (set_attr "type" "fsimps")])
5144 ;;- Absolute value instructions.
5148 ; absdi2 instruction pattern(s).
5151 (define_insn "absdi2"
5152 [(set (match_operand:DI 0 "register_operand" "=d")
5153 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5154 (clobber (reg:CC 33))]
5157 [(set_attr "op_type" "RRE")])
5160 ; abssi2 instruction pattern(s).
5163 (define_insn "abssi2"
5164 [(set (match_operand:SI 0 "register_operand" "=d")
5165 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5166 (clobber (reg:CC 33))]
5169 [(set_attr "op_type" "RR")])
5172 ; absdf2 instruction pattern(s).
5175 (define_expand "absdf2"
5177 [(set (match_operand:DF 0 "register_operand" "=f")
5178 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5179 (clobber (reg:CC 33))])]
5183 (define_insn "*absdf2"
5184 [(set (match_operand:DF 0 "register_operand" "=f")
5185 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5186 (clobber (reg:CC 33))]
5187 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5189 [(set_attr "op_type" "RRE")
5190 (set_attr "type" "fsimpd")])
5192 (define_insn "*absdf2_ibm"
5193 [(set (match_operand:DF 0 "register_operand" "=f")
5194 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5195 (clobber (reg:CC 33))]
5196 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5198 [(set_attr "op_type" "RR")
5199 (set_attr "type" "fsimpd")])
5202 ; abssf2 instruction pattern(s).
5205 (define_expand "abssf2"
5207 [(set (match_operand:SF 0 "register_operand" "=f")
5208 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5209 (clobber (reg:CC 33))])]
5213 (define_insn "*abssf2"
5214 [(set (match_operand:SF 0 "register_operand" "=f")
5215 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5216 (clobber (reg:CC 33))]
5217 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5219 [(set_attr "op_type" "RRE")
5220 (set_attr "type" "fsimps")])
5222 (define_insn "*abssf2_ibm"
5223 [(set (match_operand:SF 0 "register_operand" "=f")
5224 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5225 (clobber (reg:CC 33))]
5226 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5228 [(set_attr "op_type" "RR")
5229 (set_attr "type" "fsimps")])
5232 ;;- Square root instructions.
5236 ; sqrtdf2 instruction pattern(s).
5239 (define_insn "sqrtdf2"
5240 [(set (match_operand:DF 0 "register_operand" "=f,f")
5241 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5242 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5246 [(set_attr "op_type" "RRE,RSE")
5247 (set_attr "type" "fsqrtd")])
5250 ; sqrtsf2 instruction pattern(s).
5253 (define_insn "sqrtsf2"
5254 [(set (match_operand:SF 0 "register_operand" "=f,f")
5255 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5256 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5260 [(set_attr "op_type" "RRE,RSE")
5261 (set_attr "type" "fsqrts")])
5264 ;;- One complement instructions.
5268 ; one_cmpldi2 instruction pattern(s).
5271 (define_expand "one_cmpldi2"
5273 [(set (match_operand:DI 0 "register_operand" "")
5274 (xor:DI (match_operand:DI 1 "register_operand" "")
5276 (clobber (reg:CC 33))])]
5281 ; one_cmplsi2 instruction pattern(s).
5284 (define_expand "one_cmplsi2"
5286 [(set (match_operand:SI 0 "register_operand" "")
5287 (xor:SI (match_operand:SI 1 "register_operand" "")
5289 (clobber (reg:CC 33))])]
5294 ; one_cmplhi2 instruction pattern(s).
5297 (define_expand "one_cmplhi2"
5299 [(set (match_operand:HI 0 "register_operand" "")
5300 (xor:HI (match_operand:HI 1 "register_operand" "")
5302 (clobber (reg:CC 33))])]
5307 ; one_cmplqi2 instruction pattern(s).
5310 (define_expand "one_cmplqi2"
5312 [(set (match_operand:QI 0 "register_operand" "")
5313 (xor:QI (match_operand:QI 1 "register_operand" "")
5315 (clobber (reg:CC 33))])]
5321 ;;- Rotate instructions.
5325 ; rotldi3 instruction pattern(s).
5328 (define_insn "rotldi3"
5329 [(set (match_operand:DI 0 "register_operand" "=d,d")
5330 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5331 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5336 [(set_attr "op_type" "RSE")
5337 (set_attr "atype" "reg")])
5340 ; rotlsi3 instruction pattern(s).
5343 (define_insn "rotlsi3"
5344 [(set (match_operand:SI 0 "register_operand" "=d,d")
5345 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5346 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5351 [(set_attr "op_type" "RSE")
5352 (set_attr "atype" "reg")])
5356 ;;- Arithmetic shift instructions.
5360 ; ashldi3 instruction pattern(s).
5363 (define_expand "ashldi3"
5364 [(set (match_operand:DI 0 "register_operand" "")
5365 (ashift:DI (match_operand:DI 1 "register_operand" "")
5366 (match_operand:SI 2 "nonmemory_operand" "")))]
5370 (define_insn "*ashldi3_31"
5371 [(set (match_operand:DI 0 "register_operand" "=d,d")
5372 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5373 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5378 [(set_attr "op_type" "RS")
5379 (set_attr "atype" "reg")])
5381 (define_insn "*ashldi3_64"
5382 [(set (match_operand:DI 0 "register_operand" "=d,d")
5383 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5384 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5389 [(set_attr "op_type" "RSE")
5390 (set_attr "atype" "reg")])
5393 ; ashrdi3 instruction pattern(s).
5396 (define_expand "ashrdi3"
5398 [(set (match_operand:DI 0 "register_operand" "")
5399 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5400 (match_operand:SI 2 "nonmemory_operand" "")))
5401 (clobber (reg:CC 33))])]
5405 (define_insn "*ashrdi3_cc_31"
5407 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5408 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5410 (set (match_operand:DI 0 "register_operand" "=d,d")
5411 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5412 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5416 [(set_attr "op_type" "RS")
5417 (set_attr "atype" "reg")])
5419 (define_insn "*ashrdi3_cconly_31"
5421 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5422 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5424 (clobber (match_scratch:DI 0 "=d,d"))]
5425 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5429 [(set_attr "op_type" "RS")
5430 (set_attr "atype" "reg")])
5432 (define_insn "*ashrdi3_31"
5433 [(set (match_operand:DI 0 "register_operand" "=d,d")
5434 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5435 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5436 (clobber (reg:CC 33))]
5441 [(set_attr "op_type" "RS")
5442 (set_attr "atype" "reg")])
5444 (define_insn "*ashrdi3_cc_64"
5446 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5447 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5449 (set (match_operand:DI 0 "register_operand" "=d,d")
5450 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5451 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5455 [(set_attr "op_type" "RSE")
5456 (set_attr "atype" "reg")])
5458 (define_insn "*ashrdi3_cconly_64"
5460 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5461 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5463 (clobber (match_scratch:DI 0 "=d,d"))]
5464 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5468 [(set_attr "op_type" "RSE")
5469 (set_attr "atype" "reg")])
5471 (define_insn "*ashrdi3_64"
5472 [(set (match_operand:DI 0 "register_operand" "=d,d")
5473 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5474 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5475 (clobber (reg:CC 33))]
5480 [(set_attr "op_type" "RSE")
5481 (set_attr "atype" "reg")])
5485 ; ashlsi3 instruction pattern(s).
5488 (define_insn "ashlsi3"
5489 [(set (match_operand:SI 0 "register_operand" "=d,d")
5490 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5491 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5496 [(set_attr "op_type" "RS")
5497 (set_attr "atype" "reg")])
5500 ; ashrsi3 instruction pattern(s).
5503 (define_insn "*ashrsi3_cc"
5505 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5506 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5508 (set (match_operand:SI 0 "register_operand" "=d,d")
5509 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5510 "s390_match_ccmode(insn, CCSmode)"
5514 [(set_attr "op_type" "RS")
5515 (set_attr "atype" "reg")])
5518 (define_insn "*ashrsi3_cconly"
5520 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5521 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5523 (clobber (match_scratch:SI 0 "=d,d"))]
5524 "s390_match_ccmode(insn, CCSmode)"
5528 [(set_attr "op_type" "RS")
5529 (set_attr "atype" "reg")])
5531 (define_insn "ashrsi3"
5532 [(set (match_operand:SI 0 "register_operand" "=d,d")
5533 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5534 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5535 (clobber (reg:CC 33))]
5540 [(set_attr "op_type" "RS")
5541 (set_attr "atype" "reg")])
5545 ;;- logical shift instructions.
5549 ; lshrdi3 instruction pattern(s).
5552 (define_expand "lshrdi3"
5553 [(set (match_operand:DI 0 "register_operand" "")
5554 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5555 (match_operand:SI 2 "nonmemory_operand" "")))]
5559 (define_insn "*lshrdi3_31"
5560 [(set (match_operand:DI 0 "register_operand" "=d,d")
5561 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5562 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5567 [(set_attr "op_type" "RS,RS")
5568 (set_attr "atype" "reg")])
5570 (define_insn "*lshrdi3_64"
5571 [(set (match_operand:DI 0 "register_operand" "=d,d")
5572 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5573 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5578 [(set_attr "op_type" "RSE,RSE")
5579 (set_attr "atype" "reg")])
5582 ; lshrsi3 instruction pattern(s).
5585 (define_insn "lshrsi3"
5586 [(set (match_operand:SI 0 "register_operand" "=d,d")
5587 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5588 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5593 [(set_attr "op_type" "RS")
5594 (set_attr "atype" "reg")])
5598 ;; Branch instruction patterns.
5601 (define_expand "beq"
5602 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5604 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5605 (label_ref (match_operand 0 "" ""))
5608 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5610 (define_expand "bne"
5611 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5613 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5614 (label_ref (match_operand 0 "" ""))
5617 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5619 (define_expand "bgt"
5620 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5622 (if_then_else (gt (reg:CCS 33) (const_int 0))
5623 (label_ref (match_operand 0 "" ""))
5626 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5628 (define_expand "bgtu"
5629 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5631 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5632 (label_ref (match_operand 0 "" ""))
5635 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5637 (define_expand "blt"
5638 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5640 (if_then_else (lt (reg:CCS 33) (const_int 0))
5641 (label_ref (match_operand 0 "" ""))
5644 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5646 (define_expand "bltu"
5647 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5649 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5650 (label_ref (match_operand 0 "" ""))
5653 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5655 (define_expand "bge"
5656 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5658 (if_then_else (ge (reg:CCS 33) (const_int 0))
5659 (label_ref (match_operand 0 "" ""))
5662 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5664 (define_expand "bgeu"
5665 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5667 (if_then_else (geu (reg:CCU 33) (const_int 0))
5668 (label_ref (match_operand 0 "" ""))
5671 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5673 (define_expand "ble"
5674 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5676 (if_then_else (le (reg:CCS 33) (const_int 0))
5677 (label_ref (match_operand 0 "" ""))
5680 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5682 (define_expand "bleu"
5683 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5685 (if_then_else (leu (reg:CCU 33) (const_int 0))
5686 (label_ref (match_operand 0 "" ""))
5689 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5691 (define_expand "bunordered"
5692 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5694 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5695 (label_ref (match_operand 0 "" ""))
5698 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5700 (define_expand "bordered"
5701 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5703 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5704 (label_ref (match_operand 0 "" ""))
5707 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5709 (define_expand "buneq"
5710 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5712 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5713 (label_ref (match_operand 0 "" ""))
5716 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5718 (define_expand "bungt"
5719 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5721 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5722 (label_ref (match_operand 0 "" ""))
5725 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5727 (define_expand "bunlt"
5728 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5730 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5731 (label_ref (match_operand 0 "" ""))
5734 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5736 (define_expand "bunge"
5737 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5739 (if_then_else (unge (reg:CCS 33) (const_int 0))
5740 (label_ref (match_operand 0 "" ""))
5743 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5745 (define_expand "bunle"
5746 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5748 (if_then_else (unle (reg:CCS 33) (const_int 0))
5749 (label_ref (match_operand 0 "" ""))
5752 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5754 (define_expand "bltgt"
5755 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5757 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5758 (label_ref (match_operand 0 "" ""))
5761 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5765 ;;- Conditional jump instructions.
5768 (define_insn "cjump"
5771 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5772 (label_ref (match_operand 0 "" ""))
5777 if (get_attr_length (insn) == 4)
5778 return \"j%C1\\t%l0\";
5779 else if (TARGET_64BIT)
5780 return \"jg%C1\\t%l0\";
5784 [(set_attr "op_type" "RI")
5785 (set_attr "type" "branch")
5786 (set (attr "length")
5787 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5789 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5791 (eq (symbol_ref "flag_pic") (const_int 0))
5792 (const_int 6)] (const_int 8)))])
5794 (define_insn "*cjump_long"
5797 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5798 (match_operand 0 "address_operand" "p")
5803 if (get_attr_op_type (insn) == OP_TYPE_RR)
5804 return \"b%C1r\\t%0\";
5806 return \"b%C1\\t%a0\";
5808 [(set (attr "op_type")
5809 (if_then_else (match_operand 0 "register_operand" "")
5810 (const_string "RR") (const_string "RX")))
5811 (set_attr "type" "branch")
5812 (set_attr "atype" "agen")])
5816 ;;- Negated conditional jump instructions.
5819 (define_insn "icjump"
5822 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5824 (label_ref (match_operand 0 "" ""))))]
5828 if (get_attr_length (insn) == 4)
5829 return \"j%D1\\t%l0\";
5830 else if (TARGET_64BIT)
5831 return \"jg%D1\\t%l0\";
5835 [(set_attr "op_type" "RI")
5836 (set_attr "type" "branch")
5837 (set (attr "length")
5838 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5840 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5842 (eq (symbol_ref "flag_pic") (const_int 0))
5843 (const_int 6)] (const_int 8)))])
5845 (define_insn "*icjump_long"
5848 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5850 (match_operand 0 "address_operand" "p")))]
5854 if (get_attr_op_type (insn) == OP_TYPE_RR)
5855 return \"b%D1r\\t%0\";
5857 return \"b%D1\\t%a0\";
5859 [(set (attr "op_type")
5860 (if_then_else (match_operand 0 "register_operand" "")
5861 (const_string "RR") (const_string "RX")))
5862 (set_attr "type" "branch")
5863 (set_attr "atype" "agen")])
5866 ;;- Trap instructions.
5870 [(trap_if (const_int 1) (const_int 0))]
5873 [(set_attr "op_type" "RX")
5874 (set_attr "type" "branch")])
5876 (define_expand "conditional_trap"
5877 [(set (match_dup 2) (match_dup 3))
5878 (trap_if (match_operator 0 "comparison_operator"
5879 [(match_dup 2) (const_int 0)])
5880 (match_operand:SI 1 "general_operand" ""))]
5884 enum machine_mode ccmode;
5886 if (operands[1] != const0_rtx) FAIL;
5888 ccmode = s390_select_ccmode (GET_CODE (operands[0]),
5889 s390_compare_op0, s390_compare_op1);
5890 operands[2] = gen_rtx_REG (ccmode, 33);
5891 operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
5894 (define_insn "*trap"
5895 [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
5899 [(set_attr "op_type" "RI")
5900 (set_attr "type" "branch")])
5903 ;;- Loop instructions.
5905 ;; This is all complicated by the fact that since this is a jump insn
5906 ;; we must handle our own output reloads.
5908 (define_expand "doloop_end"
5909 [(use (match_operand 0 "" "")) ; loop pseudo
5910 (use (match_operand 1 "" "")) ; iterations; zero if unknown
5911 (use (match_operand 2 "" "")) ; max iterations
5912 (use (match_operand 3 "" "")) ; loop level
5913 (use (match_operand 4 "" ""))] ; label
5917 if (GET_MODE (operands[0]) == SImode)
5918 emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
5919 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
5920 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
5927 (define_insn "doloop_si"
5930 (ne (match_operand:SI 1 "register_operand" "d,d")
5932 (label_ref (match_operand 0 "" ""))
5934 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5935 (plus:SI (match_dup 1) (const_int -1)))
5936 (clobber (match_scratch:SI 3 "=X,&d"))
5937 (clobber (reg:CC 33))]
5941 if (which_alternative != 0)
5943 else if (get_attr_length (insn) == 4)
5944 return \"brct\\t%1,%l0\";
5948 [(set_attr "op_type" "RI")
5949 (set_attr "type" "branch")
5950 (set (attr "length")
5951 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5953 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5955 (eq (symbol_ref "flag_pic") (const_int 0))
5956 (const_int 6)] (const_int 8)))])
5958 (define_insn "*doloop_si_long"
5961 (ne (match_operand:SI 1 "register_operand" "d,d")
5963 (match_operand 0 "address_operand" "p,p")
5965 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5966 (plus:SI (match_dup 1) (const_int -1)))
5967 (clobber (match_scratch:SI 3 "=X,&d"))
5968 (clobber (reg:CC 33))]
5972 if (get_attr_op_type (insn) == OP_TYPE_RR)
5973 return \"bctr\\t%1,%0\";
5975 return \"bct\\t%1,%a0\";
5977 [(set (attr "op_type")
5978 (if_then_else (match_operand 0 "register_operand" "")
5979 (const_string "RR") (const_string "RX")))
5980 (set_attr "type" "branch")
5981 (set_attr "atype" "agen")])
5985 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
5987 (match_operand 0 "" "")
5989 (set (match_operand:SI 2 "nonimmediate_operand" "")
5990 (plus:SI (match_dup 1) (const_int -1)))
5991 (clobber (match_scratch:SI 3 ""))
5992 (clobber (reg:CC 33))]
5994 && (! REG_P (operands[2])
5995 || ! rtx_equal_p (operands[1], operands[2]))"
5996 [(set (match_dup 3) (match_dup 1))
5997 (parallel [(set (reg:CCAN 33)
5998 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6000 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6001 (set (match_dup 2) (match_dup 3))
6002 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6007 (define_insn "doloop_di"
6010 (ne (match_operand:DI 1 "register_operand" "d,d")
6012 (label_ref (match_operand 0 "" ""))
6014 (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
6015 (plus:DI (match_dup 1) (const_int -1)))
6016 (clobber (match_scratch:DI 3 "=X,&d"))
6017 (clobber (reg:CC 33))]
6021 if (which_alternative != 0)
6023 else if (get_attr_length (insn) == 4)
6024 return \"brctg\\t%1,%l0\";
6028 [(set_attr "op_type" "RI")
6029 (set_attr "type" "branch")
6030 (set (attr "length")
6031 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6032 (const_int 4) (const_int 12)))])
6034 (define_insn "*doloop_di_long"
6037 (ne (match_operand:DI 1 "register_operand" "d,d")
6039 (match_operand 0 "address_operand" "p,p")
6041 (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
6042 (plus:DI (match_dup 1) (const_int -1)))
6043 (clobber (match_scratch:DI 3 "=X,&d"))
6044 (clobber (reg:CC 33))]
6048 if (get_attr_op_type (insn) == OP_TYPE_RRE)
6049 return \"bctgr\\t%1,%0\";
6051 return \"bctg\\t%1,%a0\";
6053 [(set (attr "op_type")
6054 (if_then_else (match_operand 0 "register_operand" "")
6055 (const_string "RRE") (const_string "RXE")))
6056 (set_attr "type" "branch")
6057 (set_attr "atype" "agen")])
6061 (if_then_else (ne (match_operand:DI 1 "register_operand" "")
6063 (match_operand 0 "" "")
6065 (set (match_operand:DI 2 "nonimmediate_operand" "")
6066 (plus:DI (match_dup 1) (const_int -1)))
6067 (clobber (match_scratch:DI 3 ""))
6068 (clobber (reg:CC 33))]
6070 && (! REG_P (operands[2])
6071 || ! rtx_equal_p (operands[1], operands[2]))"
6072 [(set (match_dup 3) (match_dup 1))
6073 (parallel [(set (reg:CCAN 33)
6074 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6076 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6077 (set (match_dup 2) (match_dup 3))
6078 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6084 ;;- Unconditional jump instructions.
6088 ; jump instruction pattern(s).
6092 [(set (pc) (label_ref (match_operand 0 "" "")))]
6096 if (get_attr_length (insn) == 4)
6098 else if (TARGET_64BIT)
6099 return \"jg\\t%l0\";
6103 [(set_attr "op_type" "RI")
6104 (set_attr "type" "branch")
6105 (set (attr "length")
6106 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6108 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6110 (eq (symbol_ref "flag_pic") (const_int 0))
6111 (const_int 6)] (const_int 8)))])
6114 ; indirect-jump instruction pattern(s).
6117 (define_insn "indirect_jump"
6118 [(set (pc) (match_operand 0 "address_operand" "p"))]
6122 if (get_attr_op_type (insn) == OP_TYPE_RR)
6127 [(set (attr "op_type")
6128 (if_then_else (match_operand 0 "register_operand" "")
6129 (const_string "RR") (const_string "RX")))
6130 (set_attr "type" "branch")
6131 (set_attr "atype" "agen")])
6134 ; casesi instruction pattern(s).
6137 (define_insn "casesi_jump"
6138 [(set (pc) (match_operand 0 "address_operand" "p"))
6139 (use (label_ref (match_operand 1 "" "")))]
6143 if (get_attr_op_type (insn) == OP_TYPE_RR)
6148 [(set (attr "op_type")
6149 (if_then_else (match_operand 0 "register_operand" "")
6150 (const_string "RR") (const_string "RX")))
6151 (set_attr "type" "branch")
6152 (set_attr "atype" "agen")])
6154 (define_expand "casesi"
6155 [(match_operand:SI 0 "general_operand" "")
6156 (match_operand:SI 1 "general_operand" "")
6157 (match_operand:SI 2 "general_operand" "")
6158 (label_ref (match_operand 3 "" ""))
6159 (label_ref (match_operand 4 "" ""))]
6163 rtx index = gen_reg_rtx (SImode);
6164 rtx base = gen_reg_rtx (Pmode);
6165 rtx target = gen_reg_rtx (Pmode);
6167 emit_move_insn (index, operands[0]);
6168 emit_insn (gen_subsi3 (index, index, operands[1]));
6169 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6172 if (Pmode != SImode)
6173 index = convert_to_mode (Pmode, index, 1);
6174 if (GET_CODE (index) != REG)
6175 index = copy_to_mode_reg (Pmode, index);
6178 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6180 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6182 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6184 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6185 emit_move_insn (target, index);
6188 target = gen_rtx_PLUS (Pmode, base, target);
6189 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6196 ;;- Jump to subroutine.
6201 ; untyped call instruction pattern(s).
6204 ;; Call subroutine returning any type.
6205 (define_expand "untyped_call"
6206 [(parallel [(call (match_operand 0 "" "")
6208 (match_operand 1 "" "")
6209 (match_operand 2 "" "")])]
6215 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6217 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6219 rtx set = XVECEXP (operands[2], 0, i);
6220 emit_move_insn (SET_DEST (set), SET_SRC (set));
6223 /* The optimizer does not know that the call sets the function value
6224 registers we stored in the result block. We avoid problems by
6225 claiming that all hard registers are used and clobbered at this
6227 emit_insn (gen_blockage ());
6232 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6233 ;; all of memory. This blocks insns from being moved across this point.
6235 (define_insn "blockage"
6236 [(unspec_volatile [(const_int 0)] 0)]
6239 [(set_attr "type" "none")
6240 (set_attr "length" "0")])
6245 ; call instruction pattern(s).
6248 (define_expand "call"
6249 [(call (match_operand 0 "" "")
6250 (match_operand 1 "" ""))
6251 (use (match_operand 2 "" ""))]
6258 /* Direct function calls need special treatment. */
6259 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6261 rtx sym = XEXP (operands[0], 0);
6263 /* When calling a global routine in PIC mode, we must
6264 replace the symbol itself with the PLT stub. */
6265 if (flag_pic && !SYMBOL_REF_LOCAL_P (sym))
6267 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6268 sym = gen_rtx_CONST (Pmode, sym);
6273 /* Unless we can use the bras(l) insn, force the
6274 routine address into a register. */
6275 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6277 rtx target = gen_reg_rtx (Pmode);
6278 emit_move_insn (target, sym);
6282 operands[0] = gen_rtx_MEM (QImode, sym);
6286 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6287 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6289 /* In 31-bit, we must load the GOT register even if the
6290 compiler doesn't know about it, because the PLT glue
6291 code uses it. In 64-bit, this is not necessary. */
6292 if (plt_call && !TARGET_64BIT)
6293 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6298 (define_expand "call_exp"
6299 [(parallel [(call (match_operand 0 "" "")
6300 (match_operand 1 "" ""))
6301 (clobber (match_operand 2 "" ""))])]
6305 (define_insn "brasl"
6306 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6307 (match_operand:SI 1 "const_int_operand" "n"))
6308 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6311 [(set_attr "op_type" "RIL")
6312 (set_attr "type" "jsr")])
6315 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6316 (match_operand:SI 1 "const_int_operand" "n"))
6317 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6320 [(set_attr "op_type" "RI")
6321 (set_attr "type" "jsr")])
6323 (define_insn "basr_64"
6324 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6325 (match_operand:SI 1 "const_int_operand" "n"))
6326 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6329 [(set_attr "op_type" "RR")
6330 (set_attr "type" "jsr")
6331 (set_attr "atype" "agen")])
6333 (define_insn "basr_31"
6334 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6335 (match_operand:SI 1 "const_int_operand" "n"))
6336 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6339 [(set_attr "op_type" "RR")
6340 (set_attr "type" "jsr")
6341 (set_attr "atype" "agen")])
6343 (define_insn "bas_64"
6344 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6345 (match_operand:SI 1 "const_int_operand" "n"))
6346 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6349 [(set_attr "op_type" "RX")
6350 (set_attr "type" "jsr")])
6352 (define_insn "bas_31"
6353 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6354 (match_operand:SI 1 "const_int_operand" "n"))
6355 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6358 [(set_attr "op_type" "RX")
6359 (set_attr "type" "jsr")])
6363 ; call_value instruction pattern(s).
6366 (define_expand "call_value"
6367 [(set (match_operand 0 "" "")
6368 (call (match_operand 1 "" "")
6369 (match_operand 2 "" "")))
6370 (use (match_operand 3 "" ""))]
6377 /* Direct function calls need special treatment. */
6378 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6380 rtx sym = XEXP (operands[1], 0);
6382 /* When calling a global routine in PIC mode, we must
6383 replace the symbol itself with the PLT stub. */
6384 if (flag_pic && !SYMBOL_REF_LOCAL_P (sym))
6386 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6387 sym = gen_rtx_CONST (Pmode, sym);
6392 /* Unless we can use the bras(l) insn, force the
6393 routine address into a register. */
6394 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6396 rtx target = gen_reg_rtx (Pmode);
6397 emit_move_insn (target, sym);
6401 operands[1] = gen_rtx_MEM (QImode, sym);
6405 insn = emit_call_insn (
6406 gen_call_value_exp (operands[0], operands[1], operands[2],
6407 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6409 /* In 31-bit, we must load the GOT register even if the
6410 compiler doesn't know about it, because the PLT glue
6411 code uses it. In 64-bit, this is not necessary. */
6412 if (plt_call && !TARGET_64BIT)
6413 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6418 (define_expand "call_value_exp"
6419 [(parallel [(set (match_operand 0 "" "")
6420 (call (match_operand 1 "" "")
6421 (match_operand 2 "" "")))
6422 (clobber (match_operand 3 "" ""))])]
6426 (define_insn "brasl_r"
6427 [(set (match_operand 0 "register_operand" "=df")
6428 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6429 (match_operand:SI 2 "const_int_operand" "n")))
6430 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6433 [(set_attr "op_type" "RIL")
6434 (set_attr "type" "jsr")])
6436 (define_insn "bras_r"
6437 [(set (match_operand 0 "register_operand" "=df")
6438 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6439 (match_operand:SI 2 "const_int_operand" "n")))
6440 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6443 [(set_attr "op_type" "RI")
6444 (set_attr "type" "jsr")])
6446 (define_insn "basr_r_64"
6447 [(set (match_operand 0 "register_operand" "=df")
6448 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6449 (match_operand:SI 2 "const_int_operand" "n")))
6450 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6453 [(set_attr "op_type" "RR")
6454 (set_attr "type" "jsr")
6455 (set_attr "atype" "agen")])
6457 (define_insn "basr_r_31"
6458 [(set (match_operand 0 "register_operand" "=df")
6459 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6460 (match_operand:SI 2 "const_int_operand" "n")))
6461 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6464 [(set_attr "op_type" "RR")
6465 (set_attr "type" "jsr")
6466 (set_attr "atype" "agen")])
6468 (define_insn "bas_r_64"
6469 [(set (match_operand 0 "register_operand" "=df")
6470 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6471 (match_operand:SI 2 "const_int_operand" "n")))
6472 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6475 [(set_attr "op_type" "RX")
6476 (set_attr "type" "jsr")])
6478 (define_insn "bas_r_31"
6479 [(set (match_operand 0 "register_operand" "=df")
6480 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6481 (match_operand:SI 2 "const_int_operand" "n")))
6482 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6485 [(set_attr "op_type" "RX")
6486 (set_attr "type" "jsr")])
6490 ;;- Thread-local storage support.
6493 (define_insn "get_tp_64"
6494 [(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q")
6495 (unspec:DI [(const_int 0)] UNSPEC_TP))]
6498 ear\\t%0,%%a0\;sllg\\t%0,%0,32\;ear\\t%0,%%a1
6499 stam\\t%%a0,%%a1,%0"
6500 [(set_attr "op_type" "NN,RS")
6501 (set_attr "atype" "reg,*")
6502 (set_attr "type" "o3,*")
6503 (set_attr "length" "14,*")])
6505 (define_insn "get_tp_31"
6506 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q")
6507 (unspec:SI [(const_int 0)] UNSPEC_TP))]
6511 stam\\t%%a0,%%a0,%0"
6512 [(set_attr "op_type" "RRE,RS")])
6514 (define_insn "set_tp_64"
6515 [(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP)
6516 (clobber (match_scratch:SI 1 "=d,X"))]
6519 sar\\t%%a1,%0\;srlg\\t%1,%0,32\;sar\\t%%a0,%1
6521 [(set_attr "op_type" "NN,RS")
6522 (set_attr "atype" "reg,*")
6523 (set_attr "type" "o3,*")
6524 (set_attr "length" "14,*")])
6526 (define_insn "set_tp_31"
6527 [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)]
6532 [(set_attr "op_type" "RRE,RS")])
6534 (define_insn "*tls_load_64"
6535 [(set (match_operand:DI 0 "register_operand" "=d")
6536 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6537 (match_operand:DI 2 "" "")]
6541 [(set_attr "op_type" "RXE")])
6543 (define_insn "*tls_load_31"
6544 [(set (match_operand:SI 0 "register_operand" "=d")
6545 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
6546 (match_operand:SI 2 "" "")]
6550 [(set_attr "op_type" "RX")])
6552 (define_expand "call_value_tls"
6553 [(set (match_operand 0 "" "")
6554 (call (const_int 0) (const_int 0)))
6555 (use (match_operand 1 "" ""))]
6564 sym = s390_tls_get_offset ();
6565 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6566 sym = gen_rtx_CONST (Pmode, sym);
6568 /* Unless we can use the bras(l) insn, force the
6569 routine address into a register. */
6570 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6572 rtx target = gen_reg_rtx (Pmode);
6573 emit_move_insn (target, sym);
6577 sym = gen_rtx_MEM (QImode, sym);
6580 insn = emit_call_insn (
6581 gen_call_value_tls_exp (operands[0], sym, const0_rtx,
6582 gen_rtx_REG (Pmode, RETURN_REGNUM),
6585 /* The calling convention of __tls_get_offset uses the
6586 GOT register implicitly. */
6587 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6588 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), operands[0]);
6589 CONST_OR_PURE_CALL_P (insn) = 1;
6594 (define_expand "call_value_tls_exp"
6595 [(parallel [(set (match_operand 0 "" "")
6596 (call (match_operand 1 "" "")
6597 (match_operand 2 "" "")))
6598 (clobber (match_operand 3 "" ""))
6599 (use (match_operand 4 "" ""))])]
6603 (define_insn "brasl_tls"
6604 [(set (match_operand 0 "register_operand" "=df")
6605 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6606 (match_operand:SI 2 "const_int_operand" "n")))
6607 (clobber (match_operand:DI 3 "register_operand" "=r"))
6608 (use (match_operand:DI 4 "" ""))]
6611 [(set_attr "op_type" "RIL")
6612 (set_attr "type" "jsr")])
6614 (define_insn "bras_tls"
6615 [(set (match_operand 0 "register_operand" "=df")
6616 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6617 (match_operand:SI 2 "const_int_operand" "n")))
6618 (clobber (match_operand:SI 3 "register_operand" "=r"))
6619 (use (match_operand:SI 4 "" ""))]
6622 [(set_attr "op_type" "RI")
6623 (set_attr "type" "jsr")])
6625 (define_insn "basr_tls_64"
6626 [(set (match_operand 0 "register_operand" "=df")
6627 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6628 (match_operand:SI 2 "const_int_operand" "n")))
6629 (clobber (match_operand:DI 3 "register_operand" "=r"))
6630 (use (match_operand:DI 4 "" ""))]
6633 [(set_attr "op_type" "RR")
6634 (set_attr "type" "jsr")])
6636 (define_insn "basr_tls_31"
6637 [(set (match_operand 0 "register_operand" "=df")
6638 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6639 (match_operand:SI 2 "const_int_operand" "n")))
6640 (clobber (match_operand:SI 3 "register_operand" "=r"))
6641 (use (match_operand:SI 4 "" ""))]
6644 [(set_attr "op_type" "RR")
6645 (set_attr "type" "jsr")
6646 (set_attr "atype" "agen")])
6648 (define_insn "bas_tls_64"
6649 [(set (match_operand 0 "register_operand" "=df")
6650 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6651 (match_operand:SI 2 "const_int_operand" "n")))
6652 (clobber (match_operand:DI 3 "register_operand" "=r"))
6653 (use (match_operand:DI 4 "" ""))]
6656 [(set_attr "op_type" "RX")
6657 (set_attr "type" "jsr")
6658 (set_attr "atype" "agen")])
6660 (define_insn "bas_tls_31"
6661 [(set (match_operand 0 "register_operand" "=df")
6662 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6663 (match_operand:SI 2 "const_int_operand" "n")))
6664 (clobber (match_operand:SI 3 "register_operand" "=r"))
6665 (use (match_operand:SI 4 "" ""))]
6668 [(set_attr "op_type" "RX")
6669 (set_attr "type" "jsr")
6670 (set_attr "atype" "agen")])
6673 ;;- Miscellaneous instructions.
6677 ; allocate stack instruction pattern(s).
6680 (define_expand "allocate_stack"
6682 (plus (reg 15) (match_operand 1 "general_operand" "")))
6683 (set (match_operand 0 "general_operand" "")
6688 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6689 rtx chain = gen_rtx (MEM, Pmode, stack);
6690 rtx temp = gen_reg_rtx (Pmode);
6692 emit_move_insn (temp, chain);
6695 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6697 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6699 emit_move_insn (chain, temp);
6701 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6707 ; setjmp/longjmp instruction pattern(s).
6710 (define_expand "builtin_setjmp_setup"
6711 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6715 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6716 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6718 emit_move_insn (base, basereg);
6722 (define_expand "builtin_setjmp_receiver"
6723 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6727 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6728 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6729 SYMBOL_REF_FLAGS (got) = SYMBOL_FLAG_LOCAL;
6731 emit_move_insn (gotreg, got);
6732 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6736 (define_expand "builtin_longjmp"
6737 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6741 /* The elements of the buffer are, in order: */
6742 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6743 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6744 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6745 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6746 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6747 rtx jmp = gen_rtx_REG (Pmode, 14);
6749 emit_move_insn (jmp, lab);
6750 emit_move_insn (basereg, base);
6751 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6752 emit_move_insn (hard_frame_pointer_rtx, fp);
6754 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6755 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6756 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6757 emit_indirect_jump (jmp);
6762 ;; These patterns say how to save and restore the stack pointer. We need not
6763 ;; save the stack pointer at function level since we are careful to
6764 ;; preserve the backchain. At block level, we have to restore the backchain
6765 ;; when we restore the stack pointer.
6767 ;; For nonlocal gotos, we must save both the stack pointer and its
6768 ;; backchain and restore both. Note that in the nonlocal case, the
6769 ;; save area is a memory location.
6771 (define_expand "save_stack_function"
6772 [(match_operand 0 "general_operand" "")
6773 (match_operand 1 "general_operand" "")]
6777 (define_expand "restore_stack_function"
6778 [(match_operand 0 "general_operand" "")
6779 (match_operand 1 "general_operand" "")]
6783 (define_expand "restore_stack_block"
6784 [(use (match_operand 0 "register_operand" ""))
6785 (set (match_dup 2) (match_dup 3))
6786 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6787 (set (match_dup 3) (match_dup 2))]
6791 operands[2] = gen_reg_rtx (Pmode);
6792 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6795 (define_expand "save_stack_nonlocal"
6796 [(match_operand 0 "memory_operand" "")
6797 (match_operand 1 "register_operand" "")]
6801 rtx temp = gen_reg_rtx (Pmode);
6803 /* Copy the backchain to the first word, sp to the second. */
6804 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6805 emit_move_insn (operand_subword (operands[0], 0, 0,
6806 TARGET_64BIT ? TImode : DImode),
6808 emit_move_insn (operand_subword (operands[0], 1, 0,
6809 TARGET_64BIT ? TImode : DImode),
6814 (define_expand "restore_stack_nonlocal"
6815 [(match_operand 0 "register_operand" "")
6816 (match_operand 1 "memory_operand" "")]
6820 rtx temp = gen_reg_rtx (Pmode);
6822 /* Restore the backchain from the first word, sp from the second. */
6823 emit_move_insn (temp,
6824 operand_subword (operands[1], 0, 0,
6825 TARGET_64BIT ? TImode : DImode));
6826 emit_move_insn (operands[0],
6827 operand_subword (operands[1], 1, 0,
6828 TARGET_64BIT ? TImode : DImode));
6829 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6835 ; nop instruction pattern(s).
6842 [(set_attr "op_type" "RR")])
6846 ; Special literal pool access instruction pattern(s).
6849 (define_insn "consttable_qi"
6850 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6854 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6857 [(set_attr "op_type" "NN")
6858 (set_attr "length" "1")])
6860 (define_insn "consttable_hi"
6861 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6865 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6868 [(set_attr "op_type" "NN")
6869 (set_attr "length" "2")])
6871 (define_insn "consttable_si"
6872 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6876 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6877 return \".long\\t%0\";
6879 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6882 [(set_attr "op_type" "NN")
6883 (set_attr "length" "4")])
6885 (define_insn "consttable_di"
6886 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6890 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6893 [(set_attr "op_type" "NN")
6894 (set_attr "length" "8")])
6896 (define_insn "consttable_sf"
6897 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6903 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6906 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6907 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6910 [(set_attr "op_type" "NN")
6911 (set_attr "length" "4")])
6913 (define_insn "consttable_df"
6914 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6920 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6923 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6924 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6927 [(set_attr "op_type" "NN")
6928 (set_attr "length" "8")])
6930 (define_insn "pool_start_31"
6931 [(unspec_volatile [(const_int 0)] 206)]
6934 [(set_attr "op_type" "NN")
6935 (set_attr "length" "2")])
6937 (define_insn "pool_end_31"
6938 [(unspec_volatile [(const_int 0)] 207)]
6941 [(set_attr "op_type" "NN")
6942 (set_attr "length" "2")])
6944 (define_insn "pool_start_64"
6945 [(unspec_volatile [(const_int 0)] 206)]
6947 ".section\\t.rodata\;.align\\t8"
6948 [(set_attr "op_type" "NN")
6949 (set_attr "length" "0")])
6951 (define_insn "pool_end_64"
6952 [(unspec_volatile [(const_int 0)] 207)]
6955 [(set_attr "op_type" "NN")
6956 (set_attr "length" "0")])
6958 (define_insn "reload_base_31"
6959 [(set (match_operand:SI 0 "register_operand" "=a")
6960 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6962 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6963 [(set_attr "op_type" "NN")
6964 (set_attr "type" "la")
6965 (set_attr "length" "6")])
6967 (define_insn "reload_base_64"
6968 [(set (match_operand:DI 0 "register_operand" "=a")
6969 (unspec:DI [(label_ref (match_operand 1 "" ""))] 210))]
6972 [(set_attr "op_type" "RIL")
6973 (set_attr "type" "larl")])
6975 (define_insn "reload_anchor"
6976 [(set (match_operand:SI 0 "register_operand" "=a")
6977 (unspec:SI [(match_operand:SI 1 "register_operand" "a")] 211))]
6979 "l\\t%0,0(%1)\;la\\t%0,0(%0,%1)"
6980 [(set_attr "op_type" "NN")
6981 (set_attr "type" "la")
6982 (set_attr "atype" "agen")
6983 (set_attr "length" "8")])
6986 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 220)]
6989 [(set_attr "op_type" "NN")
6990 (set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6993 ;; Insns related to generating the function prologue and epilogue.
6997 (define_expand "prologue"
6998 [(use (const_int 0))]
7002 s390_emit_prologue ();
7006 (define_expand "epilogue"
7007 [(use (const_int 1))]
7011 s390_emit_epilogue ();
7016 (define_insn "*return_si"
7018 (use (match_operand:SI 0 "register_operand" "a"))]
7021 [(set_attr "op_type" "RR")
7022 (set_attr "type" "jsr")
7023 (set_attr "atype" "agen")])
7025 (define_insn "*return_di"
7027 (use (match_operand:DI 0 "register_operand" "a"))]
7030 [(set_attr "op_type" "RR")
7031 (set_attr "type" "jsr")
7032 (set_attr "atype" "agen")])
7034 (define_insn "literal_pool_31"
7035 [(unspec_volatile [(const_int 0)] 300)
7036 (set (match_operand:SI 0 "register_operand" "=a")
7037 (label_ref (match_operand 1 "" "")))
7038 (use (label_ref (match_operand 2 "" "")))]
7041 if (s390_nr_constants)
7043 output_asm_insn ("bras\\t%0,%2", operands);
7044 s390_output_constant_pool (operands[1], operands[2]);
7048 /* We need the anchor label in any case. */
7049 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7050 CODE_LABEL_NUMBER (operands[1]));
7055 [(set_attr "op_type" "NN")
7056 (set_attr "type" "larl")])
7058 (define_insn "literal_pool_64"
7059 [(unspec_volatile [(const_int 0)] 300)
7060 (set (match_operand:DI 0 "register_operand" "=a")
7061 (label_ref (match_operand 1 "" "")))
7062 (use (label_ref (match_operand 2 "" "")))]
7065 if (s390_nr_constants)
7067 output_asm_insn ("larl\\t%0,%1", operands);
7068 s390_output_constant_pool (operands[1], operands[2]);
7073 [(set_attr "op_type" "NN")
7074 (set_attr "type" "larl")])