1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;; Special constraints for s/390 machine description:
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
33 ;; Special formats used for outputting 390 instructions.
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
42 ;; We have a special constraint for pattern matching.
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
48 ;; Define an insn type attribute. This is used in function unit delay
51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
52 (const_string "integer"))
54 ;; Insn are devide in two classes:
55 ;; mem: Insn accessing memory
56 ;; reg: Insn operands all in registers
58 (define_attr "atype" "reg,mem"
61 ;; Generic pipeline function unit.
63 (define_function_unit "integer" 1 0
64 (eq_attr "type" "none") 0 0)
66 (define_function_unit "integer" 1 0
67 (eq_attr "type" "integer") 1 1)
69 (define_function_unit "integer" 1 0
70 (eq_attr "type" "load") 1 1)
72 (define_function_unit "integer" 1 0
73 (eq_attr "type" "la") 1 1)
75 (define_function_unit "integer" 1 0
76 (eq_attr "type" "lr") 1 1)
78 (define_function_unit "integer" 1 0
79 (eq_attr "type" "store") 1 1)
81 (define_function_unit "integer" 1 0
82 (eq_attr "type" "lm") 2 2)
84 (define_function_unit "integer" 1 0
85 (eq_attr "type" "stm") 2 2)
87 (define_function_unit "integer" 1 0
88 (eq_attr "type" "cs") 5 5)
90 (define_function_unit "integer" 1 0
91 (eq_attr "type" "vs") 30 30)
93 (define_function_unit "integer" 1 0
94 (eq_attr "type" "jsr") 5 5)
96 (define_function_unit "integer" 1 0
97 (eq_attr "type" "imul") 7 7)
99 (define_function_unit "integer" 1 0
100 (eq_attr "type" "fmul") 6 6)
102 (define_function_unit "integer" 1 0
103 (eq_attr "type" "idiv") 33 33)
105 (define_function_unit "integer" 1 0
106 (eq_attr "type" "fdiv") 33 33)
108 (define_function_unit "integer" 1 0
109 (eq_attr "type" "o2") 2 2)
111 (define_function_unit "integer" 1 0
112 (eq_attr "type" "o3") 3 3)
114 (define_function_unit "integer" 1 0
115 (eq_attr "type" "other") 5 5)
117 ;; Operand type. Used to default length attribute values
119 (define_attr "op_type"
120 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
125 (define_attr "length" ""
126 (cond [ (eq_attr "op_type" "E") (const_int 2)
127 (eq_attr "op_type" "RR") (const_int 2)
128 (eq_attr "op_type" "RX") (const_int 4)
129 (eq_attr "op_type" "RI") (const_int 4)
130 (eq_attr "op_type" "RRE") (const_int 4)
131 (eq_attr "op_type" "RS") (const_int 4)
132 (eq_attr "op_type" "RSI") (const_int 4)
133 (eq_attr "op_type" "RX") (const_int 4)
134 (eq_attr "op_type" "S") (const_int 4)
135 (eq_attr "op_type" "SI") (const_int 4)
136 (eq_attr "op_type" "SS") (const_int 6)
137 (eq_attr "op_type" "SSE") (const_int 6)
138 (eq_attr "op_type" "RXE") (const_int 6)
139 (eq_attr "op_type" "RSE") (const_int 6)
140 (eq_attr "op_type" "RIL") (const_int 6)]
143 ;; Define attributes for `asm' insns.
145 (define_asm_attributes [(set_attr "type" "other")
146 (set_attr "op_type" "NN")])
152 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
153 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
154 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
155 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
156 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
159 ; CCZ1 -> CCA/CCU/CCS/CCT
162 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
163 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
167 ;;- Compare instructions.
170 (define_expand "cmpdi"
172 (compare:CC (match_operand:DI 0 "register_operand" "")
173 (match_operand:DI 1 "general_operand" "")))]
177 s390_compare_op0 = operands[0];
178 s390_compare_op1 = operands[1];
182 (define_expand "cmpsi"
184 (compare:CC (match_operand:SI 0 "register_operand" "")
185 (match_operand:SI 1 "general_operand" "")))]
189 s390_compare_op0 = operands[0];
190 s390_compare_op1 = operands[1];
194 (define_expand "cmpdf"
196 (compare:CC (match_operand:DF 0 "register_operand" "")
197 (match_operand:DF 1 "general_operand" "")))]
201 s390_compare_op0 = operands[0];
202 s390_compare_op1 = operands[1];
206 (define_expand "cmpsf"
208 (compare:CC (match_operand:SF 0 "register_operand" "")
209 (match_operand:SF 1 "general_operand" "")))]
213 s390_compare_op0 = operands[0];
214 s390_compare_op1 = operands[1];
219 ; Test-under-Mask (zero_extract) instructions
221 (define_insn "*tmdi_ext"
223 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
224 (match_operand:DI 1 "const_int_operand" "n")
225 (match_operand:DI 2 "const_int_operand" "n"))
227 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
228 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
229 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
230 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
231 == INTVAL (operands[2]) >> 4"
234 int part = INTVAL (operands[2]) >> 4;
235 int block = (1 << INTVAL (operands[1])) - 1;
236 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
238 operands[2] = GEN_INT (block << shift);
242 case 0: return \"tmhh\\t%0,%x2\";
243 case 1: return \"tmhl\\t%0,%x2\";
244 case 2: return \"tmlh\\t%0,%x2\";
245 case 3: return \"tmll\\t%0,%x2\";
249 [(set_attr "op_type" "RI")])
251 (define_insn "*tmsi_ext"
253 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
254 (match_operand:SI 1 "const_int_operand" "n")
255 (match_operand:SI 2 "const_int_operand" "n"))
257 "s390_match_ccmode(insn, CCTmode)
258 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
259 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
260 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
261 == INTVAL (operands[2]) >> 4"
264 int part = INTVAL (operands[2]) >> 4;
265 int block = (1 << INTVAL (operands[1])) - 1;
266 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
268 operands[2] = GEN_INT (block << shift);
272 case 0: return \"tmh\\t%0,%x2\";
273 case 1: return \"tml\\t%0,%x2\";
277 [(set_attr "op_type" "RI")])
279 (define_insn "*tmqi_ext"
281 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
282 (match_operand:SI 1 "const_int_operand" "n")
283 (match_operand:SI 2 "const_int_operand" "n"))
285 "s390_match_ccmode(insn, CCTmode)
286 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
287 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
290 int block = (1 << INTVAL (operands[1])) - 1;
291 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
293 operands[2] = GEN_INT (block << shift);
294 return \"tm\\t%0,%b2\";
296 [(set_attr "op_type" "SI")
297 (set_attr "atype" "mem")])
299 ; Test-under-Mask instructions
301 (define_insn "*tmdi_mem"
303 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
304 (match_operand:DI 1 "immediate_operand" "n"))
305 (match_operand:DI 2 "immediate_operand" "n")))]
307 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
308 && s390_single_qi (operands[1], DImode, 0) >= 0"
311 int part = s390_single_qi (operands[1], DImode, 0);
312 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
314 operands[0] = gen_rtx_MEM (QImode,
315 plus_constant (XEXP (operands[0], 0), part));
316 return \"tm\\t%0,%b1\";
318 [(set_attr "op_type" "SI")
319 (set_attr "atype" "mem")])
321 (define_insn "*tmsi_mem"
323 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
324 (match_operand:SI 1 "immediate_operand" "n"))
325 (match_operand:SI 2 "immediate_operand" "n")))]
326 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
327 && s390_single_qi (operands[1], SImode, 0) >= 0"
330 int part = s390_single_qi (operands[1], SImode, 0);
331 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
333 operands[0] = gen_rtx_MEM (QImode,
334 plus_constant (XEXP (operands[0], 0), part));
335 return \"tm\\t%0,%b1\";
337 [(set_attr "op_type" "SI")
338 (set_attr "atype" "mem")])
340 (define_insn "*tmhi_mem"
342 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
343 (match_operand:SI 1 "immediate_operand" "n"))
344 (match_operand:SI 2 "immediate_operand" "n")))]
345 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
346 && s390_single_qi (operands[1], HImode, 0) >= 0"
349 int part = s390_single_qi (operands[1], HImode, 0);
350 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
352 operands[0] = gen_rtx_MEM (QImode,
353 plus_constant (XEXP (operands[0], 0), part));
354 return \"tm\\t%0,%b1\";
356 [(set_attr "op_type" "SI")
357 (set_attr "atype" "mem")])
359 (define_insn "*tmqi_mem"
361 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
362 (match_operand:SI 1 "immediate_operand" "n"))
363 (match_operand:SI 2 "immediate_operand" "n")))]
364 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
366 [(set_attr "op_type" "SI")
367 (set_attr "atype" "mem")])
369 (define_insn "*tmdi_reg"
371 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
372 (match_operand:DI 1 "immediate_operand" "n"))
373 (match_operand:DI 2 "immediate_operand" "n")))]
375 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
376 && s390_single_hi (operands[1], DImode, 0) >= 0"
379 int part = s390_single_hi (operands[1], DImode, 0);
380 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
384 case 0: return \"tmhh\\t%0,%x1\";
385 case 1: return \"tmhl\\t%0,%x1\";
386 case 2: return \"tmlh\\t%0,%x1\";
387 case 3: return \"tmll\\t%0,%x1\";
391 [(set_attr "op_type" "RI")])
393 (define_insn "*tmsi_reg"
395 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
396 (match_operand:SI 1 "immediate_operand" "n"))
397 (match_operand:SI 2 "immediate_operand" "n")))]
398 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
399 && s390_single_hi (operands[1], SImode, 0) >= 0"
402 int part = s390_single_hi (operands[1], SImode, 0);
403 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
407 case 0: return \"tmh\\t%0,%x1\";
408 case 1: return \"tml\\t%0,%x1\";
412 [(set_attr "op_type" "RI")])
414 (define_insn "*tmhi_full"
416 (compare (match_operand:HI 0 "register_operand" "d")
417 (match_operand:HI 1 "immediate_operand" "n")))]
418 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
420 [(set_attr "op_type" "RX")])
422 (define_insn "*tmqi_full"
424 (compare (match_operand:QI 0 "register_operand" "d")
425 (match_operand:QI 1 "immediate_operand" "n")))]
426 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
428 [(set_attr "op_type" "RI")])
431 ; Load-and-Test instructions
433 (define_insn "*tstdi_sign"
435 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
436 (const_int 32)) (const_int 32))
437 (match_operand:DI 1 "const0_operand" "")))
438 (set (match_operand:DI 2 "register_operand" "=d")
439 (sign_extend:DI (match_dup 0)))]
440 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
442 [(set_attr "op_type" "RRE")])
444 (define_insn "*tstdi"
446 (compare (match_operand:DI 0 "register_operand" "d")
447 (match_operand:DI 1 "const0_operand" "")))
448 (set (match_operand:DI 2 "register_operand" "=d")
450 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
452 [(set_attr "op_type" "RRE")])
454 (define_insn "*tstdi_cconly"
456 (compare (match_operand:DI 0 "register_operand" "d")
457 (match_operand:DI 1 "const0_operand" "")))]
458 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
460 [(set_attr "op_type" "RRE")])
462 (define_insn "*tstdi_cconly_31"
464 (compare (match_operand:DI 0 "register_operand" "d")
465 (match_operand:DI 1 "const0_operand" "")))]
466 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
468 [(set_attr "op_type" "RS")])
470 (define_insn "*tstsi"
472 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
473 (match_operand:SI 1 "const0_operand" "")))
474 (set (match_operand:SI 2 "register_operand" "=d,d")
476 "s390_match_ccmode(insn, CCSmode)"
480 [(set_attr "op_type" "RR,RS")
481 (set_attr "atype" "reg,mem")])
483 (define_insn "*tstsi_cconly"
485 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
486 (match_operand:SI 1 "const0_operand" "")))
487 (clobber (match_scratch:SI 2 "=X,d"))]
488 "s390_match_ccmode(insn, CCSmode)"
492 [(set_attr "op_type" "RR,RS")
493 (set_attr "atype" "reg,mem")])
495 (define_insn "*tstsi_cconly2"
497 (compare (match_operand:SI 0 "register_operand" "d")
498 (match_operand:SI 1 "const0_operand" "")))]
499 "s390_match_ccmode(insn, CCSmode)"
501 [(set_attr "op_type" "RR")])
503 (define_insn "*tsthi"
505 (compare (match_operand:HI 0 "s_operand" "Q")
506 (match_operand:HI 1 "const0_operand" "")))
507 (set (match_operand:HI 2 "register_operand" "=d")
509 "s390_match_ccmode(insn, CCSmode)"
511 [(set_attr "op_type" "RS")
512 (set_attr "atype" "mem")])
514 (define_insn "*tsthi_cconly"
516 (compare (match_operand:HI 0 "s_operand" "Q")
517 (match_operand:HI 1 "const0_operand" "")))
518 (clobber (match_scratch:HI 2 "=d"))]
519 "s390_match_ccmode(insn, CCSmode)"
521 [(set_attr "op_type" "RS")
522 (set_attr "atype" "mem")])
524 (define_insn "*tstqi"
526 (compare (match_operand:QI 0 "s_operand" "Q")
527 (match_operand:QI 1 "const0_operand" "")))
528 (set (match_operand:QI 2 "register_operand" "=d")
530 "s390_match_ccmode(insn, CCSmode)"
532 [(set_attr "op_type" "RS")
533 (set_attr "atype" "mem")])
535 (define_insn "*tstqi_cconly"
537 (compare (match_operand:QI 0 "s_operand" "Q")
538 (match_operand:QI 1 "const0_operand" "")))
539 (clobber (match_scratch:QI 2 "=d"))]
540 "s390_match_ccmode(insn, CCSmode)"
542 [(set_attr "op_type" "RS")
543 (set_attr "atype" "mem")])
546 ; Compare (signed) instructions
548 (define_insn "*cmpdi_ccs_sign"
550 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
551 (match_operand:DI 0 "register_operand" "d,d")))]
552 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
556 [(set_attr "op_type" "RRE,RXE")
557 (set_attr "atype" "reg,mem")])
559 (define_insn "*cmpdi_ccs"
561 (compare (match_operand:DI 0 "register_operand" "d,d,d")
562 (match_operand:DI 1 "general_operand" "d,K,m")))]
563 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
568 [(set_attr "op_type" "RRE,RI,RXE")
569 (set_attr "atype" "reg,reg,mem")])
571 (define_insn "*cmpsi_ccs_sign"
573 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
574 (match_operand:SI 0 "register_operand" "d")))]
575 "s390_match_ccmode(insn, CCSRmode)"
577 [(set_attr "op_type" "RX")
578 (set_attr "atype" "mem")])
580 (define_insn "*cmpsi_ccs"
582 (compare (match_operand:SI 0 "register_operand" "d,d,d")
583 (match_operand:SI 1 "general_operand" "d,K,m")))]
584 "s390_match_ccmode(insn, CCSmode)"
589 [(set_attr "op_type" "RR,RI,RX")
590 (set_attr "atype" "reg,reg,mem")])
593 ; Compare (unsigned) instructions
595 (define_insn "*cmpdi_ccu_zero"
597 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
598 (match_operand:DI 0 "register_operand" "d,d")))]
599 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
603 [(set_attr "op_type" "RRE,RXE")
604 (set_attr "atype" "reg,mem")])
606 (define_insn "*cmpdi_ccu"
608 (compare (match_operand:DI 0 "register_operand" "d,d")
609 (match_operand:DI 1 "general_operand" "d,m")))]
610 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
614 [(set_attr "op_type" "RRE,RXE")
615 (set_attr "atype" "reg,mem")])
617 (define_insn "*cmpsi_ccu"
619 (compare (match_operand:SI 0 "register_operand" "d,d")
620 (match_operand:SI 1 "general_operand" "d,m")))]
621 "s390_match_ccmode(insn, CCUmode)"
625 [(set_attr "op_type" "RR,RX")
626 (set_attr "atype" "reg,mem")])
628 (define_insn "*cmphi_ccu"
630 (compare (match_operand:HI 0 "register_operand" "d")
631 (match_operand:HI 1 "s_imm_operand" "Q")))]
632 "s390_match_ccmode(insn, CCUmode)"
634 [(set_attr "op_type" "RS")
635 (set_attr "atype" "mem")])
637 (define_insn "*cmpqi_ccu"
639 (compare (match_operand:QI 0 "register_operand" "d")
640 (match_operand:QI 1 "s_imm_operand" "Q")))]
641 "s390_match_ccmode(insn, CCUmode)"
643 [(set_attr "op_type" "RS")
644 (set_attr "atype" "mem")])
648 (compare (match_operand:QI 0 "memory_operand" "Q")
649 (match_operand:QI 1 "immediate_operand" "n")))]
650 "s390_match_ccmode (insn, CCUmode)"
652 [(set_attr "op_type" "SI")
653 (set_attr "atype" "mem")])
655 (define_insn "*cmpdi_ccu_mem"
657 (compare (match_operand:DI 0 "s_operand" "Q")
658 (match_operand:DI 1 "s_imm_operand" "Q")))]
659 "s390_match_ccmode(insn, CCUmode)"
660 "clc\\t%O0(8,%R0),%1"
661 [(set_attr "op_type" "SS")
662 (set_attr "atype" "mem")])
664 (define_insn "*cmpsi_ccu_mem"
666 (compare (match_operand:SI 0 "s_operand" "Q")
667 (match_operand:SI 1 "s_imm_operand" "Q")))]
668 "s390_match_ccmode(insn, CCUmode)"
669 "clc\\t%O0(4,%R0),%1"
670 [(set_attr "op_type" "SS")
671 (set_attr "atype" "mem")])
673 (define_insn "*cmphi_ccu_mem"
675 (compare (match_operand:HI 0 "s_operand" "Q")
676 (match_operand:HI 1 "s_imm_operand" "Q")))]
677 "s390_match_ccmode(insn, CCUmode)"
678 "clc\\t%O0(2,%R0),%1"
679 [(set_attr "op_type" "SS")
680 (set_attr "atype" "mem")])
682 (define_insn "*cmpqi_ccu_mem"
684 (compare (match_operand:QI 0 "s_operand" "Q")
685 (match_operand:QI 1 "s_imm_operand" "Q")))]
686 "s390_match_ccmode(insn, CCUmode)"
687 "clc\\t%O0(1,%R0),%1"
688 [(set_attr "op_type" "SS")
689 (set_attr "atype" "mem")])
694 (define_insn "*cmpdf_ccs_0"
696 (compare (match_operand:DF 0 "register_operand" "f")
697 (match_operand:DF 1 "const0_operand" "")))]
698 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
700 [(set_attr "op_type" "RRE")])
702 (define_insn "*cmpdf_ccs_0_ibm"
704 (compare (match_operand:DF 0 "register_operand" "f")
705 (match_operand:DF 1 "const0_operand" "")))]
706 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
708 [(set_attr "op_type" "RR")])
710 (define_insn "*cmpdf_ccs"
712 (compare (match_operand:DF 0 "register_operand" "f,f")
713 (match_operand:DF 1 "general_operand" "f,m")))]
714 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
718 [(set_attr "op_type" "RRE,RXE")
719 (set_attr "atype" "reg,mem")])
721 (define_insn "*cmpdf_ccs_ibm"
723 (compare (match_operand:DF 0 "register_operand" "f,f")
724 (match_operand:DF 1 "general_operand" "f,m")))]
725 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
729 [(set_attr "op_type" "RR,RX")
730 (set_attr "atype" "reg,mem")])
735 (define_insn "*cmpsf_ccs_0"
737 (compare (match_operand:SF 0 "register_operand" "f")
738 (match_operand:SF 1 "const0_operand" "")))]
739 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
741 [(set_attr "op_type" "RRE")])
743 (define_insn "*cmpsf_ccs_0_ibm"
745 (compare (match_operand:SF 0 "register_operand" "f")
746 (match_operand:SF 1 "const0_operand" "")))]
747 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
749 [(set_attr "op_type" "RR")])
751 (define_insn "*cmpsf_ccs"
753 (compare (match_operand:SF 0 "register_operand" "f,f")
754 (match_operand:SF 1 "general_operand" "f,m")))]
755 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
759 [(set_attr "op_type" "RRE,RXE")
760 (set_attr "atype" "reg,mem")])
762 (define_insn "*cmpsf_ccs"
764 (compare (match_operand:SF 0 "register_operand" "f,f")
765 (match_operand:SF 1 "general_operand" "f,m")))]
766 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
770 [(set_attr "op_type" "RR,RX")
771 (set_attr "atype" "reg,mem")])
775 ;;- Move instructions.
779 ; movti instruction pattern(s).
783 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m,Q")
784 (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
791 mvc\\t%O0(16,%R0),%1"
792 [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
793 (set_attr "atype" "mem")])
796 [(set (match_operand:TI 0 "nonimmediate_operand" "")
797 (match_operand:TI 1 "general_operand" ""))]
798 "TARGET_64BIT && reload_completed
799 && !s_operand (operands[0], VOIDmode)
800 && !s_operand (operands[1], VOIDmode)
801 && (register_operand (operands[0], VOIDmode)
802 || register_operand (operands[1], VOIDmode))
803 && (!register_operand (operands[0], VOIDmode)
804 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
806 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
808 [(set (match_dup 2) (match_dup 4))
809 (set (match_dup 3) (match_dup 5))]
812 if (!register_operand (operands[0], VOIDmode)
813 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
816 operands[2] = operand_subword (operands[0], 0, 0, TImode);
817 operands[3] = operand_subword (operands[0], 1, 0, TImode);
818 operands[4] = operand_subword (operands[1], 0, 0, TImode);
819 operands[5] = operand_subword (operands[1], 1, 0, TImode);
823 operands[2] = operand_subword (operands[0], 1, 0, TImode);
824 operands[3] = operand_subword (operands[0], 0, 0, TImode);
825 operands[4] = operand_subword (operands[1], 1, 0, TImode);
826 operands[5] = operand_subword (operands[1], 0, 0, TImode);
831 [(set (match_operand:TI 0 "register_operand" "")
832 (match_operand:TI 1 "memory_operand" ""))]
833 "TARGET_64BIT && reload_completed
834 && !s_operand (operands[1], VOIDmode)"
835 [(set (match_dup 0) (match_dup 1))]
838 rtx addr = operand_subword (operands[0], 1, 0, TImode);
839 s390_load_address (addr, XEXP (operands[1], 0));
840 operands[1] = replace_equiv_address (operands[1], addr);
844 ; movdi instruction pattern(s).
847 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
848 ;; move to get the address of the symbolic object from the GOT.
850 (define_expand "movdi"
851 [(set (match_operand:DI 0 "general_operand" "")
852 (match_operand:DI 1 "general_operand" ""))]
856 /* Handle PIC symbolic constants. */
857 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
858 emit_pic_move (operands, DImode);
860 /* During and after reload, we need to force constants
861 to the literal pool ourselves, if necessary. */
862 if ((reload_in_progress || reload_completed)
863 && CONSTANT_P (operands[1])
864 && (!legitimate_reload_constant_p (operands[1])
865 || fp_operand (operands[0], VOIDmode)))
866 operands[1] = force_const_mem (DImode, operands[1]);
869 (define_insn "*movdi_lhi"
870 [(set (match_operand:DI 0 "register_operand" "=d")
871 (match_operand:DI 1 "immediate_operand" "K"))]
873 && GET_CODE (operands[1]) == CONST_INT
874 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
875 && !fp_operand (operands[0], VOIDmode)"
877 [(set_attr "op_type" "RI")
878 (set_attr "atype" "reg")])
880 (define_insn "*movdi_lli"
881 [(set (match_operand:DI 0 "register_operand" "=d")
882 (match_operand:DI 1 "immediate_operand" "n"))]
883 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
884 && !fp_operand (operands[0], VOIDmode)"
887 int part = s390_single_hi (operands[1], DImode, 0);
888 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
892 case 0: return \"llihh\\t%0,%x1\";
893 case 1: return \"llihl\\t%0,%x1\";
894 case 2: return \"llilh\\t%0,%x1\";
895 case 3: return \"llill\\t%0,%x1\";
899 [(set_attr "op_type" "RI")
900 (set_attr "atype" "reg")])
902 (define_insn "*movdi_larl"
903 [(set (match_operand:DI 0 "register_operand" "=d")
904 (match_operand:DI 1 "larl_operand" "X"))]
906 && !fp_operand (operands[0], VOIDmode)"
908 [(set_attr "op_type" "RIL")
909 (set_attr "atype" "reg")
910 (set_attr "type" "la")])
912 (define_insn "*movdi_64"
913 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
914 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
924 [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX,SS")
925 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
927 (define_insn "*movdi_31"
928 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
929 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
940 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
941 (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")])
944 [(set (match_operand:DI 0 "nonimmediate_operand" "")
945 (match_operand:DI 1 "general_operand" ""))]
946 "!TARGET_64BIT && reload_completed
947 && !fp_operand (operands[0], VOIDmode)
948 && !fp_operand (operands[1], VOIDmode)
949 && !s_operand (operands[0], VOIDmode)
950 && !s_operand (operands[1], VOIDmode)
951 && (register_operand (operands[0], VOIDmode)
952 || register_operand (operands[1], VOIDmode))
953 && (!register_operand (operands[0], VOIDmode)
954 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
956 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
958 [(set (match_dup 2) (match_dup 4))
959 (set (match_dup 3) (match_dup 5))]
962 if (!register_operand (operands[0], VOIDmode)
963 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
966 operands[2] = operand_subword (operands[0], 0, 0, DImode);
967 operands[3] = operand_subword (operands[0], 1, 0, DImode);
968 operands[4] = operand_subword (operands[1], 0, 0, DImode);
969 operands[5] = operand_subword (operands[1], 1, 0, DImode);
973 operands[2] = operand_subword (operands[0], 1, 0, DImode);
974 operands[3] = operand_subword (operands[0], 0, 0, DImode);
975 operands[4] = operand_subword (operands[1], 1, 0, DImode);
976 operands[5] = operand_subword (operands[1], 0, 0, DImode);
981 [(set (match_operand:DI 0 "register_operand" "")
982 (match_operand:DI 1 "memory_operand" ""))]
983 "!TARGET_64BIT && reload_completed
984 && !fp_operand (operands[0], VOIDmode)
985 && !fp_operand (operands[1], VOIDmode)
986 && !s_operand (operands[1], VOIDmode)"
987 [(set (match_dup 0) (match_dup 1))]
990 rtx addr = operand_subword (operands[0], 1, 0, DImode);
991 s390_load_address (addr, XEXP (operands[1], 0));
992 operands[1] = replace_equiv_address (operands[1], addr);
996 ; movsi instruction pattern(s).
999 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
1000 ;; move to get the address of the symbolic object from the GOT.
1002 (define_expand "movsi"
1003 [(set (match_operand:SI 0 "general_operand" "")
1004 (match_operand:SI 1 "general_operand" ""))]
1008 /* Handle PIC symbolic constants. */
1009 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1010 emit_pic_move (operands, SImode);
1012 /* expr.c tries to load an effective address using
1013 force_reg. This fails because we don't have a
1014 generic load_address pattern. Convert the move
1015 to a proper arithmetic operation instead, unless
1016 it is guaranteed to be OK. */
1017 if (GET_CODE (operands[1]) == PLUS
1018 && !legitimate_la_operand_p (operands[1]))
1020 operands[1] = force_operand (operands[1], operands[0]);
1021 if (operands[1] == operands[0])
1025 /* During and after reload, we need to force constants
1026 to the literal pool ourselves, if necessary. */
1027 if ((reload_in_progress || reload_completed)
1028 && CONSTANT_P (operands[1])
1029 && (!legitimate_reload_constant_p (operands[1])
1030 || fp_operand (operands[0], VOIDmode)))
1031 operands[1] = force_const_mem (SImode, operands[1]);
1034 (define_insn "*movsi_lhi"
1035 [(set (match_operand:SI 0 "register_operand" "=d")
1036 (match_operand:SI 1 "immediate_operand" "K"))]
1037 "GET_CODE (operands[1]) == CONST_INT
1038 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1039 && !fp_operand (operands[0], VOIDmode)"
1041 [(set_attr "op_type" "RI")])
1043 (define_insn "*movsi_lli"
1044 [(set (match_operand:SI 0 "register_operand" "=d")
1045 (match_operand:SI 1 "immediate_operand" "n"))]
1046 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1047 && !fp_operand (operands[0], VOIDmode)"
1050 int part = s390_single_hi (operands[1], SImode, 0);
1051 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1055 case 0: return \"llilh\\t%0,%x1\";
1056 case 1: return \"llill\\t%0,%x1\";
1060 [(set_attr "op_type" "RI")])
1062 (define_insn "*movsi"
1063 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1064 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1073 mvc\\t%O0(4,%R0),%1"
1074 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1075 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1079 ; movhi instruction pattern(s).
1082 (define_insn "movhi"
1083 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1084 (match_operand:HI 1 "general_operand" "d,n,m,d,Q"))]
1091 mvc\\t%O0(2,%R0),%1"
1092 [(set_attr "op_type" "RR,RI,RX,RX,SS")
1093 (set_attr "atype" "reg,reg,mem,mem,mem")])
1097 ; movqi instruction pattern(s).
1100 (define_insn "movqi_64"
1101 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1102 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1110 mvc\\t%O0(1,%R0),%1"
1111 [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1112 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1115 (define_insn "movqi"
1116 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1117 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1125 mvc\\t%O0(1,%R0),%1"
1126 [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
1127 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1131 ; movstrictqi instruction pattern(s).
1134 (define_insn "*movstrictqi"
1135 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1136 (match_operand:QI 1 "memory_operand" "m"))]
1139 [(set_attr "op_type" "RX")
1140 (set_attr "atype" "mem")])
1143 ; movstricthi instruction pattern(s).
1146 (define_insn "*movstricthi"
1147 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1148 (match_operand:HI 1 "s_imm_operand" "Q"))
1149 (clobber (reg:CC 33))]
1152 [(set_attr "op_type" "RS")
1153 (set_attr "atype" "mem")])
1157 ; movstrictsi instruction pattern(s).
1160 (define_insn "movstrictsi"
1161 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1162 (match_operand:SI 1 "general_operand" "d,m"))]
1167 [(set_attr "op_type" "RR,RS")
1168 (set_attr "atype" "reg,mem")])
1172 ; movdf instruction pattern(s).
1175 (define_expand "movdf"
1176 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1177 (match_operand:DF 1 "general_operand" ""))]
1181 /* During and after reload, we need to force constants
1182 to the literal pool ourselves, if necessary. */
1183 if ((reload_in_progress || reload_completed)
1184 && CONSTANT_P (operands[1]))
1185 operands[1] = force_const_mem (DFmode, operands[1]);
1188 (define_insn "*movdf_64"
1189 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1190 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1199 mvc\\t%O0(8,%R0),%1"
1200 [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE,SS")
1201 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1203 (define_insn "*movdf_31"
1204 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
1205 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
1215 mvc\\t%O0(8,%R0),%1"
1216 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1217 (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")])
1220 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1221 (match_operand:DF 1 "general_operand" ""))]
1222 "!TARGET_64BIT && reload_completed
1223 && !fp_operand (operands[0], VOIDmode)
1224 && !fp_operand (operands[1], VOIDmode)
1225 && !s_operand (operands[0], VOIDmode)
1226 && !s_operand (operands[1], VOIDmode)
1227 && (register_operand (operands[0], VOIDmode)
1228 || register_operand (operands[1], VOIDmode))
1229 && (!register_operand (operands[0], VOIDmode)
1230 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1232 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1234 [(set (match_dup 2) (match_dup 4))
1235 (set (match_dup 3) (match_dup 5))]
1238 if (!register_operand (operands[0], VOIDmode)
1239 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1242 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1243 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1244 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1245 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1249 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1250 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1251 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1252 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1257 [(set (match_operand:DF 0 "register_operand" "")
1258 (match_operand:DF 1 "memory_operand" ""))]
1259 "!TARGET_64BIT && reload_completed
1260 && !fp_operand (operands[0], VOIDmode)
1261 && !fp_operand (operands[1], VOIDmode)
1262 && !s_operand (operands[1], VOIDmode)"
1263 [(set (match_dup 0) (match_dup 1))]
1266 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1267 s390_load_address (addr, XEXP (operands[1], 0));
1268 operands[1] = replace_equiv_address (operands[1], addr);
1272 ; movsf instruction pattern(s).
1275 (define_expand "movsf"
1276 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1277 (match_operand:SF 1 "general_operand" ""))]
1281 /* During and after reload, we need to force constants
1282 to the literal pool ourselves, if necessary. */
1283 if ((reload_in_progress || reload_completed)
1284 && CONSTANT_P (operands[1]))
1285 operands[1] = force_const_mem (SFmode, operands[1]);
1288 (define_insn "*movsf"
1289 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1290 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1299 mvc\\t%O0(4,%R0),%1"
1300 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1301 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1304 ; load_multiple pattern(s).
1307 (define_expand "load_multiple"
1308 [(match_par_dup 3 [(set (match_operand 0 "" "")
1309 (match_operand 1 "" ""))
1310 (use (match_operand 2 "" ""))])]
1319 /* Support only loading a constant number of fixed-point registers from
1320 memory and only bother with this if more than two */
1321 if (GET_CODE (operands[2]) != CONST_INT
1322 || INTVAL (operands[2]) < 2
1323 || INTVAL (operands[2]) > 16
1324 || GET_CODE (operands[1]) != MEM
1325 || GET_CODE (operands[0]) != REG
1326 || REGNO (operands[0]) >= 16)
1329 count = INTVAL (operands[2]);
1330 regno = REGNO (operands[0]);
1332 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1335 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1337 from = XEXP (operands[1], 0);
1340 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1341 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1342 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1344 from = XEXP (XEXP (operands[1], 0), 0);
1345 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1350 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1355 from = force_reg (Pmode, XEXP (operands[1], 0));
1359 for (i = 0; i < count; i++)
1360 XVECEXP (operands[3], 0, i)
1361 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1362 change_address (operands[1], Pmode,
1363 plus_constant (from,
1364 off + i * UNITS_PER_WORD)));
1367 (define_insn "*load_multiple_di"
1368 [(match_parallel 0 "load_multiple_operation"
1369 [(set (match_operand:DI 1 "register_operand" "=r")
1370 (match_operand:DI 2 "s_operand" "Q"))])]
1374 int words = XVECLEN (operands[0], 0);
1376 if (XVECLEN (operands[0], 0) == 1)
1377 return \"lg\\t%1,0(%2)\";
1379 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1380 return \"lmg\\t%1,%0,%2\";
1382 [(set_attr "op_type" "RXE")
1383 (set_attr "atype" "mem")
1384 (set_attr "type" "lm")])
1386 (define_insn "*load_multiple_si"
1387 [(match_parallel 0 "load_multiple_operation"
1388 [(set (match_operand:SI 1 "register_operand" "=r")
1389 (match_operand:SI 2 "s_operand" "Q"))])]
1393 int words = XVECLEN (operands[0], 0);
1395 if (XVECLEN (operands[0], 0) == 1)
1396 return \"l\\t%1,0(%2)\";
1398 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1399 return \"lm\\t%1,%0,%2\";
1401 [(set_attr "op_type" "RXE")
1402 (set_attr "atype" "mem")
1403 (set_attr "type" "lm")])
1406 ; store multiple pattern(s).
1409 (define_expand "store_multiple"
1410 [(match_par_dup 3 [(set (match_operand 0 "" "")
1411 (match_operand 1 "" ""))
1412 (use (match_operand 2 "" ""))])]
1421 /* Support only storing a constant number of fixed-point registers to
1422 memory and only bother with this if more than two. */
1423 if (GET_CODE (operands[2]) != CONST_INT
1424 || INTVAL (operands[2]) < 2
1425 || INTVAL (operands[2]) > 16
1426 || GET_CODE (operands[0]) != MEM
1427 || GET_CODE (operands[1]) != REG
1428 || REGNO (operands[1]) >= 16)
1431 count = INTVAL (operands[2]);
1432 regno = REGNO (operands[1]);
1434 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1438 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1440 to = XEXP (operands[0], 0);
1443 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1444 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1445 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1447 to = XEXP (XEXP (operands[0], 0), 0);
1448 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1453 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1458 to = force_reg (Pmode, XEXP (operands[0], 0));
1462 for (i = 0; i < count; i++)
1463 XVECEXP (operands[3], 0, i)
1464 = gen_rtx_SET (VOIDmode,
1465 change_address (operands[0], Pmode,
1467 off + i * UNITS_PER_WORD)),
1468 gen_rtx_REG (Pmode, regno + i));
1471 (define_insn "*store_multiple_di"
1472 [(match_parallel 0 "store_multiple_operation"
1473 [(set (match_operand:DI 1 "s_operand" "=Q")
1474 (match_operand:DI 2 "register_operand" "r"))])]
1478 int words = XVECLEN (operands[0], 0);
1480 if (XVECLEN (operands[0], 0) == 1)
1481 return \"stg\\t%1,0(%2)\";
1483 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1484 return \"stmg\\t%2,%0,%1\";
1486 [(set_attr "op_type" "RXE")
1487 (set_attr "atype" "mem")
1488 (set_attr "type" "stm")])
1491 (define_insn "*store_multiple_si"
1492 [(match_parallel 0 "store_multiple_operation"
1493 [(set (match_operand:SI 1 "s_operand" "=Q")
1494 (match_operand:SI 2 "register_operand" "r"))])]
1498 int words = XVECLEN (operands[0], 0);
1500 if (XVECLEN (operands[0], 0) == 1)
1501 return \"st\\t%1,0(%2)\";
1503 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1504 return \"stm\\t%2,%0,%1\";
1506 [(set_attr "op_type" "RXE")
1507 (set_attr "atype" "mem")
1508 (set_attr "type" "stm")])
1511 ;; String instructions.
1515 ; movstrM instruction pattern(s).
1518 (define_expand "movstrdi"
1519 [(set (match_operand:BLK 0 "memory_operand" "")
1520 (match_operand:BLK 1 "memory_operand" ""))
1521 (use (match_operand:DI 2 "general_operand" ""))
1522 (match_operand 3 "" "")]
1524 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1526 (define_expand "movstrsi"
1527 [(set (match_operand:BLK 0 "memory_operand" "")
1528 (match_operand:BLK 1 "memory_operand" ""))
1529 (use (match_operand:SI 2 "general_operand" ""))
1530 (match_operand 3 "" "")]
1532 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1534 ; Move a block that is up to 256 bytes in length.
1535 ; The block length is taken as (operands[2] % 256) + 1.
1537 (define_insn "movstr_short_64"
1538 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1539 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1540 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1541 (clobber (match_scratch:DI 3 "=X,&a"))]
1545 switch (which_alternative)
1548 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1551 output_asm_insn (\"bras\\t%3,.+10\", operands);
1552 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1553 return \"ex\\t%2,0(%3)\";
1559 [(set_attr "op_type" "SS,NN")
1560 (set_attr "type" "cs,cs")
1561 (set_attr "atype" "mem,mem")
1562 (set_attr "length" "*,14")])
1564 (define_insn "movstr_short_31"
1565 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1566 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1567 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1568 (clobber (match_scratch:SI 3 "=X,&a"))]
1572 switch (which_alternative)
1575 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1578 output_asm_insn (\"bras\\t%3,.+10\", operands);
1579 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1580 return \"ex\\t%2,0(%3)\";
1586 [(set_attr "op_type" "SS,NN")
1587 (set_attr "type" "cs,cs")
1588 (set_attr "atype" "mem,mem")
1589 (set_attr "length" "*,14")])
1591 ; Move a block of arbitrary length.
1593 (define_insn "movstr_long_64"
1594 [(set (match_operand:TI 0 "register_operand" "=d")
1595 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1596 (lshiftrt:TI (match_dup 2) (const_int 64)))
1598 (set (match_operand:TI 1 "register_operand" "=d")
1599 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1600 (lshiftrt:TI (match_dup 3) (const_int 64)))
1602 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1603 (mem:BLK (subreg:DI (match_dup 3) 0)))
1604 (clobber (reg:CC 33))]
1606 "mvcle\\t%0,%1,0\;jo\\t.-4"
1607 [(set_attr "op_type" "NN")
1608 (set_attr "type" "vs")
1609 (set_attr "atype" "mem")
1610 (set_attr "length" "8")])
1612 (define_insn "movstr_long_31"
1613 [(set (match_operand:DI 0 "register_operand" "=d")
1614 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1615 (lshiftrt:DI (match_dup 2) (const_int 32)))
1617 (set (match_operand:DI 1 "register_operand" "=d")
1618 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1619 (lshiftrt:DI (match_dup 3) (const_int 32)))
1621 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1622 (mem:BLK (subreg:SI (match_dup 3) 0)))
1623 (clobber (reg:CC 33))]
1625 "mvcle\\t%0,%1,0\;jo\\t.-4"
1626 [(set_attr "op_type" "NN")
1627 (set_attr "type" "vs")
1628 (set_attr "atype" "mem")
1629 (set_attr "length" "8")])
1632 ; clrstrM instruction pattern(s).
1635 (define_expand "clrstrdi"
1636 [(set (match_operand:BLK 0 "memory_operand" "")
1638 (use (match_operand:DI 1 "general_operand" ""))
1639 (match_operand 2 "" "")]
1641 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1643 (define_expand "clrstrsi"
1644 [(set (match_operand:BLK 0 "memory_operand" "")
1646 (use (match_operand:SI 1 "general_operand" ""))
1647 (match_operand 2 "" "")]
1649 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1651 ; Clear a block that is up to 256 bytes in length.
1652 ; The block length is taken as (operands[2] % 256) + 1.
1654 (define_insn "clrstr_short_64"
1655 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1657 (use (match_operand:DI 1 "nonmemory_operand" "n,a"))
1658 (clobber (match_scratch:DI 2 "=X,&a"))
1659 (clobber (reg:CC 33))]
1663 switch (which_alternative)
1666 return \"xc\\t%O0(%b1+1,%R0),%0\";
1669 output_asm_insn (\"bras\\t%2,.+10\", operands);
1670 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1671 return \"ex\\t%1,0(%2)\";
1677 [(set_attr "op_type" "SS,NN")
1678 (set_attr "type" "cs,cs")
1679 (set_attr "atype" "mem,mem")
1680 (set_attr "length" "*,14")])
1682 (define_insn "clrstr_short_31"
1683 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1685 (use (match_operand:SI 1 "nonmemory_operand" "n,a"))
1686 (clobber (match_scratch:SI 2 "=X,&a"))
1687 (clobber (reg:CC 33))]
1691 switch (which_alternative)
1694 return \"xc\\t%O0(%b1+1,%R0),%0\";
1697 output_asm_insn (\"bras\\t%2,.+10\", operands);
1698 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1699 return \"ex\\t%1,0(%2)\";
1705 [(set_attr "op_type" "SS,NN")
1706 (set_attr "type" "cs,cs")
1707 (set_attr "atype" "mem,mem")
1708 (set_attr "length" "*,14")])
1710 ; Clear a block of arbitrary length.
1712 (define_insn "clrstr_long_64"
1713 [(set (match_operand:TI 0 "register_operand" "=d")
1714 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1715 (lshiftrt:TI (match_dup 2) (const_int 64)))
1717 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1719 (use (match_operand:TI 1 "register_operand" "d"))
1720 (clobber (reg:CC 33))]
1722 "mvcle\\t%0,%1,0\;jo\\t.-4"
1723 [(set_attr "op_type" "NN")
1724 (set_attr "atype" "mem")
1725 (set_attr "type" "vs")
1726 (set_attr "length" "8")])
1728 (define_insn "clrstr_long_31"
1729 [(set (match_operand:DI 0 "register_operand" "=d")
1730 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1731 (lshiftrt:DI (match_dup 2) (const_int 32)))
1733 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1735 (use (match_operand:DI 1 "register_operand" "d"))
1736 (clobber (reg:CC 33))]
1738 "mvcle\\t%0,%1,0\;jo\\t.-4"
1739 [(set_attr "op_type" "NN")
1740 (set_attr "atype" "mem")
1741 (set_attr "type" "vs")
1742 (set_attr "length" "8")])
1745 ; cmpstrM instruction pattern(s).
1748 (define_expand "cmpstrdi"
1749 [(set (match_operand:DI 0 "register_operand" "")
1750 (compare:DI (match_operand:BLK 1 "memory_operand" "")
1751 (match_operand:BLK 2 "memory_operand" "") ) )
1752 (use (match_operand:DI 3 "general_operand" ""))
1753 (use (match_operand:DI 4 "" ""))]
1755 "s390_expand_cmpstr (operands[0], operands[1],
1756 operands[2], operands[3]); DONE;")
1758 (define_expand "cmpstrsi"
1759 [(set (match_operand:SI 0 "register_operand" "")
1760 (compare:SI (match_operand:BLK 1 "memory_operand" "")
1761 (match_operand:BLK 2 "memory_operand" "") ) )
1762 (use (match_operand:SI 3 "general_operand" ""))
1763 (use (match_operand:SI 4 "" ""))]
1765 "s390_expand_cmpstr (operands[0], operands[1],
1766 operands[2], operands[3]); DONE;")
1768 ; Compare a block that is up to 256 bytes in length.
1769 ; The block length is taken as (operands[2] % 256) + 1.
1771 (define_insn "cmpstr_short_64"
1773 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1774 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1775 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1776 (clobber (match_scratch:DI 3 "=X,&a"))]
1780 switch (which_alternative)
1783 return \"clc\\t%O0(%b2+1,%R0),%1\";
1786 output_asm_insn (\"bras\\t%3,.+10\", operands);
1787 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1788 return \"ex\\t%2,0(%3)\";
1794 [(set_attr "op_type" "SS,NN")
1795 (set_attr "type" "cs,cs")
1796 (set_attr "atype" "mem,mem")
1797 (set_attr "length" "*,14")])
1799 (define_insn "cmpstr_short_31"
1801 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1802 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1803 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1804 (clobber (match_scratch:SI 3 "=X,&a"))]
1808 switch (which_alternative)
1811 return \"clc\\t%O0(%b2+1,%R0),%1\";
1814 output_asm_insn (\"bras\\t%3,.+10\", operands);
1815 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1816 return \"ex\\t%2,0(%3)\";
1822 [(set_attr "op_type" "SS,NN")
1823 (set_attr "type" "cs,cs")
1824 (set_attr "atype" "mem,mem")
1825 (set_attr "length" "*,14")])
1827 ; Compare a block of arbitrary length.
1829 (define_insn "cmpstr_long_64"
1830 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1831 (clobber (match_operand:TI 1 "register_operand" "=d"))
1833 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1834 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
1836 (use (match_dup 3))]
1839 [(set_attr "op_type" "RR")
1840 (set_attr "atype" "mem")
1841 (set_attr "type" "vs")])
1843 (define_insn "cmpstr_long_31"
1844 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1845 (clobber (match_operand:DI 1 "register_operand" "=d"))
1847 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1848 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
1850 (use (match_dup 3))]
1853 [(set_attr "op_type" "RR")
1854 (set_attr "atype" "mem")
1855 (set_attr "type" "vs")])
1857 ; Convert condition code to integer in range (-1, 0, 1)
1859 (define_insn "cmpint_si"
1860 [(set (match_operand:SI 0 "register_operand" "=d")
1861 (compare:SI (reg:CCS 33) (const_int 0)))]
1865 output_asm_insn (\"lhi\\t%0,1\", operands);
1866 output_asm_insn (\"jh\\t.+12\", operands);
1867 output_asm_insn (\"jl\\t.+6\", operands);
1868 output_asm_insn (\"sr\\t%0,%0\", operands);
1869 return \"lcr\\t%0,%0\";
1871 [(set_attr "op_type" "NN")
1872 (set_attr "length" "16")
1873 (set_attr "atype" "reg")
1874 (set_attr "type" "other")])
1876 (define_insn "cmpint_di"
1877 [(set (match_operand:DI 0 "register_operand" "=d")
1878 (compare:DI (reg:CCS 33) (const_int 0)))]
1882 output_asm_insn (\"lghi\\t%0,1\", operands);
1883 output_asm_insn (\"jh\\t.+12\", operands);
1884 output_asm_insn (\"jl\\t.+6\", operands);
1885 output_asm_insn (\"sgr\\t%0,%0\", operands);
1886 return \"lcgr\\t%0,%0\";
1888 [(set_attr "op_type" "NN")
1889 (set_attr "length" "22")
1890 (set_attr "atype" "reg")
1891 (set_attr "type" "other")])
1895 ;;- Conversion instructions.
1898 (define_insn "*sethighqisi"
1899 [(set (match_operand:SI 0 "register_operand" "=d")
1900 (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
1901 (clobber (reg:CC 33))]
1904 [(set_attr "op_type" "RS")
1905 (set_attr "atype" "mem")])
1907 (define_insn "*sethighhisi"
1908 [(set (match_operand:SI 0 "register_operand" "=d")
1909 (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
1910 (clobber (reg:CC 33))]
1913 [(set_attr "op_type" "RS")
1914 (set_attr "atype" "mem")])
1916 (define_insn "*sethighqidi_64"
1917 [(set (match_operand:DI 0 "register_operand" "=d")
1918 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
1919 (clobber (reg:CC 33))]
1922 [(set_attr "op_type" "RSE")
1923 (set_attr "atype" "mem")])
1925 (define_insn "*sethighqidi_31"
1926 [(set (match_operand:DI 0 "register_operand" "=d")
1927 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
1928 (clobber (reg:CC 33))]
1931 [(set_attr "op_type" "RS")
1932 (set_attr "atype" "mem")])
1935 [(set (match_operand:SI 0 "register_operand" "")
1936 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
1937 (match_operand 2 "const_int_operand" "")
1939 "!TARGET_64BIT && !reload_completed
1940 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
1942 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
1943 (clobber (reg:CC 33))])
1944 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
1947 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1948 operands[1] = change_address (operands[1], QImode, 0);
1952 [(set (match_operand:SI 0 "register_operand" "")
1953 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
1954 (match_operand 2 "const_int_operand" "")
1956 "!TARGET_64BIT && !reload_completed
1957 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
1959 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
1960 (clobber (reg:CC 33))])
1961 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
1964 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1965 operands[1] = change_address (operands[1], HImode, 0);
1969 ; extendsidi2 instruction pattern(s).
1972 (define_expand "extendsidi2"
1973 [(set (match_operand:DI 0 "register_operand" "")
1974 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
1980 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
1981 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
1982 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
1983 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
1989 (define_insn "*extendsidi2"
1990 [(set (match_operand:DI 0 "register_operand" "=d,d")
1991 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
1996 [(set_attr "op_type" "RRE,RXE")
1997 (set_attr "atype" "reg,mem")])
2000 ; extendhidi2 instruction pattern(s).
2003 (define_expand "extendhidi2"
2004 [(set (match_operand:DI 0 "register_operand" "")
2005 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2011 rtx tmp = gen_reg_rtx (SImode);
2012 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2013 emit_insn (gen_extendsidi2 (operands[0], tmp));
2018 operands[1] = gen_lowpart (DImode, operands[1]);
2019 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2020 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2026 (define_insn "*extendhidi2"
2027 [(set (match_operand:DI 0 "register_operand" "=d")
2028 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2031 [(set_attr "op_type" "RXE")
2032 (set_attr "atype" "mem")])
2035 ; extendqidi2 instruction pattern(s).
2038 (define_expand "extendqidi2"
2039 [(set (match_operand:DI 0 "register_operand" "")
2040 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2046 rtx tmp = gen_reg_rtx (SImode);
2047 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2048 emit_insn (gen_extendsidi2 (operands[0], tmp));
2053 operands[1] = gen_lowpart (DImode, operands[1]);
2054 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2055 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2062 [(set (match_operand:DI 0 "register_operand" "")
2063 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2064 "TARGET_64BIT && !reload_completed"
2066 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2067 (clobber (reg:CC 33))])
2069 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2070 (clobber (reg:CC 33))])]
2074 ; extendhisi2 instruction pattern(s).
2077 (define_expand "extendhisi2"
2078 [(set (match_operand:SI 0 "register_operand" "")
2079 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2083 operands[1] = gen_lowpart (SImode, operands[1]);
2084 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2085 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2090 (define_insn "*extendhisi2"
2091 [(set (match_operand:SI 0 "register_operand" "=d")
2092 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2095 [(set_attr "op_type" "RX")
2096 (set_attr "atype" "mem")])
2099 ; extendqisi2 instruction pattern(s).
2102 (define_expand "extendqisi2"
2103 [(set (match_operand:SI 0 "register_operand" "")
2104 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2108 operands[1] = gen_lowpart (SImode, operands[1]);
2109 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2110 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2116 [(set (match_operand:SI 0 "register_operand" "")
2117 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2120 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2121 (clobber (reg:CC 33))])
2123 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2124 (clobber (reg:CC 33))])]
2128 ; extendqihi2 instruction pattern(s).
2133 ; zero_extendsidi2 instruction pattern(s).
2136 (define_expand "zero_extendsidi2"
2137 [(set (match_operand:DI 0 "register_operand" "")
2138 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2144 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2145 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2146 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2152 (define_insn "*zero_extendsidi2"
2153 [(set (match_operand:DI 0 "register_operand" "=d,d")
2154 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2159 [(set_attr "op_type" "RRE,RXE")
2160 (set_attr "atype" "reg,mem")])
2163 ; zero_extendhidi2 instruction pattern(s).
2166 (define_expand "zero_extendhidi2"
2167 [(set (match_operand:DI 0 "register_operand" "")
2168 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2174 rtx tmp = gen_reg_rtx (SImode);
2175 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2176 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2181 operands[1] = gen_lowpart (DImode, operands[1]);
2182 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2183 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2189 (define_insn "*zero_extendhidi2"
2190 [(set (match_operand:DI 0 "register_operand" "=d")
2191 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2194 [(set_attr "op_type" "RXE")
2195 (set_attr "atype" "mem")])
2198 ; zero_extendqidi2 instruction pattern(s)
2201 (define_expand "zero_extendqidi2"
2202 [(set (match_operand:DI 0 "register_operand" "")
2203 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2209 rtx tmp = gen_reg_rtx (SImode);
2210 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2211 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2216 operands[1] = gen_lowpart (DImode, operands[1]);
2217 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2218 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2224 (define_insn "*zero_extendqidi2"
2225 [(set (match_operand:DI 0 "register_operand" "=d")
2226 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2229 [(set_attr "op_type" "RXE")
2230 (set_attr "atype" "mem")])
2233 ; zero_extendhisi2 instruction pattern(s).
2236 (define_expand "zero_extendhisi2"
2237 [(set (match_operand:SI 0 "register_operand" "")
2238 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2242 operands[1] = gen_lowpart (SImode, operands[1]);
2243 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2248 (define_insn "*zero_extendhisi2_64"
2249 [(set (match_operand:SI 0 "register_operand" "=d")
2250 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2253 [(set_attr "op_type" "RXE")
2254 (set_attr "atype" "mem")])
2257 ; zero_extendqisi2 instruction pattern(s).
2260 (define_expand "zero_extendqisi2"
2261 [(set (match_operand:SI 0 "register_operand" "")
2262 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2266 operands[1] = gen_lowpart (SImode, operands[1]);
2267 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2272 (define_insn "*zero_extendqisi2_64"
2273 [(set (match_operand:SI 0 "register_operand" "=d")
2274 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2277 [(set_attr "op_type" "RXE")
2278 (set_attr "atype" "mem")])
2281 ; zero_extendqihi2 instruction pattern(s).
2284 (define_expand "zero_extendqihi2"
2285 [(set (match_operand:HI 0 "register_operand" "")
2286 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2290 operands[1] = gen_lowpart (HImode, operands[1]);
2291 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2296 (define_insn "*zero_extendqihi2_64"
2297 [(set (match_operand:HI 0 "register_operand" "=d")
2298 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))
2299 (clobber (reg:CC 33))]
2302 [(set_attr "op_type" "RXE")
2303 (set_attr "atype" "mem")])
2306 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2309 (define_expand "fixuns_truncdfdi2"
2310 [(set (match_operand:DI 0 "register_operand" "")
2311 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2312 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2315 rtx label1 = gen_label_rtx ();
2316 rtx label2 = gen_label_rtx ();
2317 rtx temp = gen_reg_rtx (DFmode);
2318 operands[1] = force_reg (DFmode, operands[1]);
2320 emit_insn (gen_cmpdf (operands[1],
2321 CONST_DOUBLE_FROM_REAL_VALUE (
2322 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2323 emit_jump_insn (gen_blt (label1));
2324 emit_insn (gen_subdf3 (temp, operands[1],
2325 CONST_DOUBLE_FROM_REAL_VALUE (
2326 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2327 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2330 emit_label (label1);
2331 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2332 emit_label (label2);
2336 (define_expand "fix_truncdfdi2"
2337 [(set (match_operand:DI 0 "register_operand" "")
2338 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2339 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2342 operands[1] = force_reg (DFmode, operands[1]);
2343 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2347 (define_insn "fix_truncdfdi2_ieee"
2348 [(set (match_operand:DI 0 "register_operand" "=d")
2349 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2350 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2351 (clobber (reg:CC 33))]
2352 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2354 [(set_attr "op_type" "RRE")
2355 (set_attr "type" "other")])
2358 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2361 (define_expand "fixuns_truncdfsi2"
2362 [(set (match_operand:SI 0 "register_operand" "")
2363 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2364 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2367 rtx label1 = gen_label_rtx ();
2368 rtx label2 = gen_label_rtx ();
2369 rtx temp = gen_reg_rtx (DFmode);
2371 operands[1] = force_reg (DFmode,operands[1]);
2372 emit_insn (gen_cmpdf (operands[1],
2373 CONST_DOUBLE_FROM_REAL_VALUE (
2374 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2375 emit_jump_insn (gen_blt (label1));
2376 emit_insn (gen_subdf3 (temp, operands[1],
2377 CONST_DOUBLE_FROM_REAL_VALUE (
2378 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2379 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2382 emit_label (label1);
2383 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2384 emit_label (label2);
2388 (define_expand "fix_truncdfsi2"
2389 [(set (match_operand:SI 0 "register_operand" "")
2390 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2394 if (TARGET_IBM_FLOAT)
2396 /* This is the algorithm from POP chapter A.5.7.2. */
2398 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2399 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2400 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2402 operands[1] = force_reg (DFmode, operands[1]);
2403 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2404 two31r, two32, temp));
2408 operands[1] = force_reg (DFmode, operands[1]);
2409 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2415 (define_insn "fix_truncdfsi2_ieee"
2416 [(set (match_operand:SI 0 "register_operand" "=d")
2417 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2418 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2419 (clobber (reg:CC 33))]
2420 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2422 [(set_attr "op_type" "RRE")
2423 (set_attr "type" "other" )])
2425 (define_insn "fix_truncdfsi2_ibm"
2426 [(set (match_operand:SI 0 "register_operand" "=d")
2427 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2428 (use (match_operand:DI 2 "immediate_operand" "m"))
2429 (use (match_operand:DI 3 "immediate_operand" "m"))
2430 (use (match_operand:BLK 4 "memory_operand" "m"))
2431 (clobber (reg:CC 33))]
2432 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2435 output_asm_insn (\"sd\\t%1,%2\", operands);
2436 output_asm_insn (\"aw\\t%1,%3\", operands);
2437 output_asm_insn (\"std\\t%1,%4\", operands);
2438 output_asm_insn (\"xi\\t%N4,128\", operands);
2439 return \"l\\t%0,%N4\";
2441 [(set_attr "op_type" "NN")
2442 (set_attr "type" "other")
2443 (set_attr "length" "20")])
2446 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2449 (define_expand "fixuns_truncsfdi2"
2450 [(set (match_operand:DI 0 "register_operand" "")
2451 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2452 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2455 rtx label1 = gen_label_rtx ();
2456 rtx label2 = gen_label_rtx ();
2457 rtx temp = gen_reg_rtx (SFmode);
2459 operands[1] = force_reg (SFmode, operands[1]);
2460 emit_insn (gen_cmpsf (operands[1],
2461 CONST_DOUBLE_FROM_REAL_VALUE (
2462 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2463 emit_jump_insn (gen_blt (label1));
2465 emit_insn (gen_subsf3 (temp, operands[1],
2466 CONST_DOUBLE_FROM_REAL_VALUE (
2467 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2468 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2471 emit_label (label1);
2472 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2473 emit_label (label2);
2477 (define_expand "fix_truncsfdi2"
2478 [(set (match_operand:DI 0 "register_operand" "")
2479 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2480 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2483 operands[1] = force_reg (SFmode, operands[1]);
2484 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2488 (define_insn "fix_truncsfdi2_ieee"
2489 [(set (match_operand:DI 0 "register_operand" "=d")
2490 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2491 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2492 (clobber (reg:CC 33))]
2493 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2495 [(set_attr "op_type" "RRE")
2496 (set_attr "type" "other")])
2499 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2502 (define_expand "fixuns_truncsfsi2"
2503 [(set (match_operand:SI 0 "register_operand" "")
2504 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2505 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2508 rtx label1 = gen_label_rtx ();
2509 rtx label2 = gen_label_rtx ();
2510 rtx temp = gen_reg_rtx (SFmode);
2512 operands[1] = force_reg (SFmode, operands[1]);
2513 emit_insn (gen_cmpsf (operands[1],
2514 CONST_DOUBLE_FROM_REAL_VALUE (
2515 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2516 emit_jump_insn (gen_blt (label1));
2517 emit_insn (gen_subsf3 (temp, operands[1],
2518 CONST_DOUBLE_FROM_REAL_VALUE (
2519 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2520 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2523 emit_label (label1);
2524 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2525 emit_label (label2);
2529 (define_expand "fix_truncsfsi2"
2530 [(set (match_operand:SI 0 "register_operand" "")
2531 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2535 if (TARGET_IBM_FLOAT)
2537 /* Convert to DFmode and then use the POP algorithm. */
2538 rtx temp = gen_reg_rtx (DFmode);
2539 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2540 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2544 operands[1] = force_reg (SFmode, operands[1]);
2545 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2551 (define_insn "fix_truncsfsi2_ieee"
2552 [(set (match_operand:SI 0 "register_operand" "=d")
2553 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2554 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2555 (clobber (reg:CC 33))]
2556 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2558 [(set_attr "op_type" "RRE")
2559 (set_attr "type" "other")])
2562 ; floatdidf2 instruction pattern(s).
2565 (define_insn "floatdidf2"
2566 [(set (match_operand:DF 0 "register_operand" "=f")
2567 (float:DF (match_operand:DI 1 "register_operand" "d")))
2568 (clobber (reg:CC 33))]
2569 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2571 [(set_attr "op_type" "RRE")
2572 (set_attr "type" "other" )])
2575 ; floatdisf2 instruction pattern(s).
2578 (define_insn "floatdisf2"
2579 [(set (match_operand:SF 0 "register_operand" "=f")
2580 (float:SF (match_operand:DI 1 "register_operand" "d")))
2581 (clobber (reg:CC 33))]
2582 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2584 [(set_attr "op_type" "RRE")
2585 (set_attr "type" "other" )])
2588 ; floatsidf2 instruction pattern(s).
2591 (define_expand "floatsidf2"
2593 [(set (match_operand:DF 0 "register_operand" "")
2594 (float:DF (match_operand:SI 1 "register_operand" "")))
2595 (clobber (reg:CC 33))])]
2599 if (TARGET_IBM_FLOAT)
2601 /* This is the algorithm from POP chapter A.5.7.1. */
2603 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2604 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2606 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2611 (define_insn "floatsidf2_ieee"
2612 [(set (match_operand:DF 0 "register_operand" "=f")
2613 (float:DF (match_operand:SI 1 "register_operand" "d")))
2614 (clobber (reg:CC 33))]
2615 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2617 [(set_attr "op_type" "RRE")
2618 (set_attr "type" "other" )])
2620 (define_insn "floatsidf2_ibm"
2621 [(set (match_operand:DF 0 "register_operand" "=f")
2622 (float:DF (match_operand:SI 1 "register_operand" "d")))
2623 (use (match_operand:DI 2 "immediate_operand" "m"))
2624 (use (match_operand:BLK 3 "memory_operand" "m"))
2625 (clobber (reg:CC 33))]
2626 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2629 output_asm_insn (\"st\\t%1,%N3\", operands);
2630 output_asm_insn (\"xi\\t%N3,128\", operands);
2631 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2632 output_asm_insn (\"ld\\t%0,%3\", operands);
2633 return \"sd\\t%0,%2\";
2635 [(set_attr "op_type" "NN")
2636 (set_attr "type" "other" )
2637 (set_attr "length" "20")])
2640 ; floatsisf2 instruction pattern(s).
2643 (define_expand "floatsisf2"
2645 [(set (match_operand:SF 0 "register_operand" "")
2646 (float:SF (match_operand:SI 1 "register_operand" "")))
2647 (clobber (reg:CC 33))])]
2651 if (TARGET_IBM_FLOAT)
2653 /* Use the POP algorithm to convert to DFmode and then truncate. */
2654 rtx temp = gen_reg_rtx (DFmode);
2655 emit_insn (gen_floatsidf2 (temp, operands[1]));
2656 emit_insn (gen_truncdfsf2 (operands[0], temp));
2661 (define_insn "floatsisf2_ieee"
2662 [(set (match_operand:SF 0 "register_operand" "=f")
2663 (float:SF (match_operand:SI 1 "register_operand" "d")))
2664 (clobber (reg:CC 33))]
2665 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2667 [(set_attr "op_type" "RRE")
2668 (set_attr "type" "other" )])
2671 ; truncdfsf2 instruction pattern(s).
2674 (define_expand "truncdfsf2"
2675 [(set (match_operand:SF 0 "register_operand" "")
2676 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2680 (define_insn "truncdfsf2_ieee"
2681 [(set (match_operand:SF 0 "register_operand" "=f")
2682 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2683 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2685 [(set_attr "op_type" "RRE")])
2687 (define_insn "truncdfsf2_ibm"
2688 [(set (match_operand:SF 0 "register_operand" "=f,f")
2689 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2690 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2694 [(set_attr "op_type" "RR,RX")
2695 (set_attr "atype" "reg,mem")])
2698 ; extendsfdf2 instruction pattern(s).
2701 (define_expand "extendsfdf2"
2702 [(set (match_operand:DF 0 "register_operand" "")
2703 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2707 if (TARGET_IBM_FLOAT)
2709 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2714 (define_insn "extendsfdf2_ieee"
2715 [(set (match_operand:DF 0 "register_operand" "=f,f")
2716 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2717 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2721 [(set_attr "op_type" "RRE,RXE")])
2723 (define_insn "extendsfdf2_ibm"
2724 [(set (match_operand:DF 0 "register_operand" "=f,f")
2725 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2726 (clobber (reg:CC 33))]
2727 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2729 sdr\\t%0,%0\;ler\\t%0,%1
2730 sdr\\t%0,%0\;le\\t%0,%1"
2731 [(set_attr "op_type" "RRE,RXE")
2732 (set_attr "atype" "reg,mem")
2733 (set_attr "type" "o2,o2")])
2737 ;; ARITHMETRIC OPERATIONS
2739 ; arithmetric operations set the ConditionCode,
2740 ; because of unpredictable Bits in Register for Halfword and Byte
2741 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2744 ;;- Add instructions.
2748 ; adddi3 instruction pattern(s).
2751 (define_insn "addaddr_esame"
2752 [(set (match_operand:DI 0 "register_operand" "=a,a")
2753 (plus:DI (match_operand:DI 1 "register_operand" "%a,a")
2754 (match_operand:DI 2 "nonmemory_operand" "J,a")))]
2755 "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
2756 (REGNO (operands[1]) == BASE_REGISTER)) &&
2757 (GET_CODE (operands[2]) == REG ||
2758 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
2762 [(set_attr "op_type" "RX")
2763 (set_attr "atype" "mem")
2764 (set_attr "type" "la")])
2766 (define_insn "*adddi3_sign"
2767 [(set (match_operand:DI 0 "register_operand" "=d,d")
2768 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2769 (match_operand:DI 1 "register_operand" "0,0")))
2770 (clobber (reg:CC 33))]
2775 [(set_attr "op_type" "RRE,RXE")
2776 (set_attr "atype" "reg,mem")])
2778 (define_insn "*adddi3_zero_cc"
2780 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2781 (match_operand:DI 1 "register_operand" "0,0"))
2783 (set (match_operand:DI 0 "register_operand" "=d,d")
2784 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
2785 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2789 [(set_attr "op_type" "RRE,RXE")
2790 (set_attr "atype" "reg,mem")])
2792 (define_insn "*adddi3_zero_cconly"
2794 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2795 (match_operand:DI 1 "register_operand" "0,0"))
2797 (clobber (match_scratch:DI 0 "=d,d"))]
2798 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2802 [(set_attr "op_type" "RRE,RXE")
2803 (set_attr "atype" "reg,mem")])
2805 (define_insn "*adddi3_zero"
2806 [(set (match_operand:DI 0 "register_operand" "=d,d")
2807 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2808 (match_operand:DI 1 "register_operand" "0,0")))
2809 (clobber (reg:CC 33))]
2814 [(set_attr "op_type" "RRE,RXE")
2815 (set_attr "atype" "reg,mem")])
2817 (define_insn "*adddi3_imm_cc"
2819 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
2820 (match_operand:DI 2 "const_int_operand" "K"))
2822 (set (match_operand:DI 0 "register_operand" "=d")
2823 (plus:DI (match_dup 1) (match_dup 2)))]
2825 && s390_match_ccmode (insn, CCAmode)
2826 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
2828 [(set_attr "op_type" "RI")
2829 (set_attr "atype" "reg")])
2831 (define_insn "*adddi3_cc"
2833 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2834 (match_operand:DI 2 "general_operand" "d,m"))
2836 (set (match_operand:DI 0 "register_operand" "=d,d")
2837 (plus:DI (match_dup 1) (match_dup 2)))]
2838 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2842 [(set_attr "op_type" "RRE,RXE")
2843 (set_attr "atype" "reg,mem")])
2845 (define_insn "*adddi3_cconly"
2847 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2848 (match_operand:DI 2 "general_operand" "d,m"))
2850 (clobber (match_scratch:DI 0 "=d,d"))]
2851 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2855 [(set_attr "op_type" "RRE,RXE")
2856 (set_attr "atype" "reg,mem")])
2858 (define_insn "*adddi3_cconly2"
2860 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2861 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
2862 (clobber (match_scratch:DI 0 "=d,d"))]
2863 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
2867 [(set_attr "op_type" "RRE,RXE")
2868 (set_attr "atype" "reg,mem")])
2870 (define_insn "*adddi3_64"
2871 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2872 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
2873 (match_operand:DI 2 "general_operand" "d,K,m") ) )
2874 (clobber (reg:CC 33))]
2880 [(set_attr "op_type" "RRE,RI,RXE")
2881 (set_attr "atype" "reg,reg,mem")])
2883 (define_insn_and_split "*adddi3_31"
2884 [(set (match_operand:DI 0 "register_operand" "=&d")
2885 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
2886 (match_operand:DI 2 "general_operand" "dm") ) )
2887 (clobber (reg:CC 33))]
2890 "&& reload_completed"
2892 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
2893 (clobber (reg:CC 33))])
2896 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
2898 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
2900 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
2902 (label_ref (match_dup 9))))
2904 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
2905 (clobber (reg:CC 33))])
2907 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
2908 operands[4] = operand_subword (operands[1], 0, 1, DImode);
2909 operands[5] = operand_subword (operands[2], 0, 1, DImode);
2910 operands[6] = operand_subword (operands[0], 1, 1, DImode);
2911 operands[7] = operand_subword (operands[1], 1, 1, DImode);
2912 operands[8] = operand_subword (operands[2], 1, 1, DImode);
2913 operands[9] = gen_label_rtx ();"
2914 [(set_attr "op_type" "NN")
2915 (set_attr "type" "o3")])
2917 (define_expand "adddi3"
2919 [(set (match_operand:DI 0 "register_operand" "")
2920 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
2921 (match_operand:DI 2 "general_operand" "")))
2922 (clobber (reg:CC 33))])]
2926 (define_insn "*la_64"
2927 [(set (match_operand:DI 0 "register_operand" "=d")
2928 (match_operand:QI 1 "address_operand" "p"))]
2931 [(set_attr "op_type" "RX")
2932 (set_attr "atype" "mem")
2933 (set_attr "type" "la")])
2935 (define_expand "reload_indi"
2936 [(parallel [(match_operand:DI 0 "register_operand" "=a")
2937 (match_operand:DI 1 "s390_plus_operand" "")
2938 (match_operand:DI 2 "register_operand" "=&a")])]
2942 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
2948 ; addsi3 instruction pattern(s).
2951 (define_insn "*la_ccclobber"
2952 [(set (match_operand:SI 0 "register_operand" "=d")
2953 (match_operand:QI 1 "address_operand" "p"))
2954 (clobber (reg:CC 33))]
2955 "legitimate_la_operand_p (operands[1])"
2957 [(set_attr "op_type" "RX")
2958 (set_attr "atype" "mem")
2959 (set_attr "type" "la")])
2961 (define_insn "*addsi3_imm_cc"
2963 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
2964 (match_operand:SI 2 "const_int_operand" "K"))
2966 (set (match_operand:SI 0 "register_operand" "=d")
2967 (plus:SI (match_dup 1) (match_dup 2)))]
2968 "s390_match_ccmode (insn, CCAmode)
2969 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
2971 [(set_attr "op_type" "RI")
2972 (set_attr "atype" "reg")])
2974 (define_insn "*addsi3_carry1_cc"
2976 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
2977 (match_operand:SI 2 "general_operand" "d,m"))
2979 (set (match_operand:SI 0 "register_operand" "=d,d")
2980 (plus:SI (match_dup 1) (match_dup 2)))]
2981 "s390_match_ccmode (insn, CCL1mode)"
2985 [(set_attr "op_type" "RR,RX")
2986 (set_attr "atype" "reg,mem")])
2988 (define_insn "*addsi3_carry1_cconly"
2990 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
2991 (match_operand:SI 2 "general_operand" "d,m"))
2993 (clobber (match_scratch:SI 0 "=d,d"))]
2994 "s390_match_ccmode (insn, CCL1mode)"
2998 [(set_attr "op_type" "RR,RX")
2999 (set_attr "atype" "reg,mem")])
3001 (define_insn "*addsi3_carry2_cc"
3003 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3004 (match_operand:SI 2 "general_operand" "d,m"))
3006 (set (match_operand:SI 0 "register_operand" "=d,d")
3007 (plus:SI (match_dup 1) (match_dup 2)))]
3008 "s390_match_ccmode (insn, CCL1mode)"
3012 [(set_attr "op_type" "RR,RX")
3013 (set_attr "atype" "reg,mem")])
3015 (define_insn "*addsi3_carry2_cconly"
3017 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3018 (match_operand:SI 2 "general_operand" "d,m"))
3020 (clobber (match_scratch:SI 0 "=d,d"))]
3021 "s390_match_ccmode (insn, CCL1mode)"
3025 [(set_attr "op_type" "RR,RX")
3026 (set_attr "atype" "reg,mem")])
3028 (define_insn "*addsi3_cc"
3030 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3031 (match_operand:SI 2 "general_operand" "d,m"))
3033 (set (match_operand:SI 0 "register_operand" "=d,d")
3034 (plus:SI (match_dup 1) (match_dup 2)))]
3035 "s390_match_ccmode (insn, CCLmode)"
3039 [(set_attr "op_type" "RR,RX")
3040 (set_attr "atype" "reg,mem")])
3042 (define_insn "*addsi3_cconly"
3044 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3045 (match_operand:SI 2 "general_operand" "d,m"))
3047 (clobber (match_scratch:SI 0 "=d,d"))]
3048 "s390_match_ccmode (insn, CCLmode)"
3052 [(set_attr "op_type" "RR,RX")
3053 (set_attr "atype" "reg,mem")])
3055 (define_insn "*addsi3_cconly2"
3057 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3058 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3059 (clobber (match_scratch:SI 0 "=d,d"))]
3060 "s390_match_ccmode(insn, CCLmode)"
3064 [(set_attr "op_type" "RR,RX")
3065 (set_attr "atype" "reg,mem")])
3067 (define_insn "*addsi3_sign"
3068 [(set (match_operand:SI 0 "register_operand" "=d")
3069 (plus:SI (match_operand:SI 1 "register_operand" "0")
3070 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3071 (clobber (reg:CC 33))]
3074 [(set_attr "op_type" "RX")
3075 (set_attr "atype" "mem")])
3077 (define_insn "*addsi3_sub"
3078 [(set (match_operand:SI 0 "register_operand" "=d")
3079 (plus:SI (match_operand:SI 1 "register_operand" "0")
3080 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3081 (clobber (reg:CC 33))]
3084 [(set_attr "op_type" "RX")
3085 (set_attr "atype" "mem")])
3087 (define_insn "addsi3"
3088 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3089 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3090 (match_operand:SI 2 "general_operand" "d,K,m")))
3091 (clobber (reg:CC 33))]
3097 [(set_attr "op_type" "RR,RI,RX")
3098 (set_attr "atype" "reg,reg,mem")])
3100 (define_insn "*la_31"
3101 [(set (match_operand:SI 0 "register_operand" "=d")
3102 (match_operand:QI 1 "address_operand" "p"))]
3103 "legitimate_la_operand_p (operands[1])"
3105 [(set_attr "op_type" "RX")
3106 (set_attr "atype" "mem")
3107 (set_attr "type" "la")])
3109 (define_insn "force_la_31"
3110 [(set (match_operand:SI 0 "register_operand" "=d")
3111 (match_operand:QI 1 "address_operand" "p"))
3112 (use (const_int 0))]
3115 [(set_attr "op_type" "RX")
3116 (set_attr "atype" "mem")
3117 (set_attr "type" "la")])
3119 (define_expand "reload_insi"
3120 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3121 (match_operand:SI 1 "s390_plus_operand" "")
3122 (match_operand:SI 2 "register_operand" "=&a")])]
3126 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3132 ; adddf3 instruction pattern(s).
3135 (define_expand "adddf3"
3137 [(set (match_operand:DF 0 "register_operand" "=f,f")
3138 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3139 (match_operand:DF 2 "general_operand" "f,m")))
3140 (clobber (reg:CC 33))])]
3144 (define_insn "*adddf3"
3145 [(set (match_operand:DF 0 "register_operand" "=f,f")
3146 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3147 (match_operand:DF 2 "general_operand" "f,m")))
3148 (clobber (reg:CC 33))]
3149 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3153 [(set_attr "op_type" "RRE,RXE")
3154 (set_attr "atype" "reg,mem")])
3156 (define_insn "*adddf3_ibm"
3157 [(set (match_operand:DF 0 "register_operand" "=f,f")
3158 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3159 (match_operand:DF 2 "general_operand" "f,m")))
3160 (clobber (reg:CC 33))]
3161 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3165 [(set_attr "op_type" "RR,RX")
3166 (set_attr "atype" "reg,mem")])
3169 ; addsf3 instruction pattern(s).
3172 (define_expand "addsf3"
3174 [(set (match_operand:SF 0 "register_operand" "=f,f")
3175 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3176 (match_operand:SF 2 "general_operand" "f,m")))
3177 (clobber (reg:CC 33))])]
3181 (define_insn "*addsf3"
3182 [(set (match_operand:SF 0 "register_operand" "=f,f")
3183 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3184 (match_operand:SF 2 "general_operand" "f,m")))
3185 (clobber (reg:CC 33))]
3186 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3190 [(set_attr "op_type" "RRE,RXE")
3191 (set_attr "atype" "reg,mem")])
3193 (define_insn "*addsf3"
3194 [(set (match_operand:SF 0 "register_operand" "=f,f")
3195 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3196 (match_operand:SF 2 "general_operand" "f,m")))
3197 (clobber (reg:CC 33))]
3198 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3202 [(set_attr "op_type" "RR,RX")
3203 (set_attr "atype" "reg,mem")])
3207 ;;- Subtract instructions.
3211 ; subdi3 instruction pattern(s).
3214 (define_insn "*subdi3_sign"
3215 [(set (match_operand:DI 0 "register_operand" "=d,d")
3216 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3217 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3218 (clobber (reg:CC 33))]
3223 [(set_attr "op_type" "RRE,RXE")
3224 (set_attr "atype" "reg,mem")])
3226 (define_insn "*subdi3_zero_cc"
3228 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3229 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3231 (set (match_operand:DI 0 "register_operand" "=d,d")
3232 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3233 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3237 [(set_attr "op_type" "RRE,RXE")
3238 (set_attr "atype" "reg,mem")])
3240 (define_insn "*subdi3_zero_cconly"
3242 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3243 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3245 (clobber (match_scratch:DI 0 "=d,d"))]
3246 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3250 [(set_attr "op_type" "RRE,RXE")
3251 (set_attr "atype" "reg,mem")])
3253 (define_insn "*subdi3_zero"
3254 [(set (match_operand:DI 0 "register_operand" "=d,d")
3255 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3256 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3257 (clobber (reg:CC 33))]
3262 [(set_attr "op_type" "RRE,RXE")
3263 (set_attr "atype" "reg,mem")])
3265 (define_insn "*subdi3_cc"
3267 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3268 (match_operand:DI 2 "general_operand" "d,m"))
3270 (set (match_operand:DI 0 "register_operand" "=d,d")
3271 (minus:DI (match_dup 1) (match_dup 2)))]
3272 "s390_match_ccmode (insn, CCLmode)"
3276 [(set_attr "op_type" "RRE,RXE")
3277 (set_attr "atype" "reg,mem")])
3279 (define_insn "*subdi3_cconly"
3281 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3282 (match_operand:DI 2 "general_operand" "d,m"))
3284 (clobber (match_scratch:DI 0 "=d,d"))]
3285 "s390_match_ccmode (insn, CCLmode)"
3289 [(set_attr "op_type" "RRE,RXE")
3290 (set_attr "atype" "reg,mem")])
3292 (define_insn "*subdi3_64"
3293 [(set (match_operand:DI 0 "register_operand" "=d,d")
3294 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3295 (match_operand:DI 2 "general_operand" "d,m") ) )
3296 (clobber (reg:CC 33))]
3301 [(set_attr "op_type" "RRE,RRE")
3302 (set_attr "atype" "reg,mem")])
3304 (define_insn_and_split "*subdi3_31"
3305 [(set (match_operand:DI 0 "register_operand" "=&d")
3306 (minus:DI (match_operand:DI 1 "register_operand" "0")
3307 (match_operand:DI 2 "general_operand" "dm") ) )
3308 (clobber (reg:CC 33))]
3311 "&& reload_completed"
3313 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3314 (clobber (reg:CC 33))])
3317 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3319 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3321 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3323 (label_ref (match_dup 9))))
3325 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3326 (clobber (reg:CC 33))])
3328 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3329 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3330 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3331 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3332 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3333 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3334 operands[9] = gen_label_rtx ();"
3335 [(set_attr "op_type" "NN")
3336 (set_attr "type" "o3")])
3338 (define_expand "subdi3"
3340 [(set (match_operand:DI 0 "register_operand" "")
3341 (minus:DI (match_operand:DI 1 "register_operand" "")
3342 (match_operand:DI 2 "general_operand" "")))
3343 (clobber (reg:CC 33))])]
3348 ; subsi3 instruction pattern(s).
3351 (define_insn "*subsi3_borrow_cc"
3353 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3354 (match_operand:SI 2 "general_operand" "d,m"))
3356 (set (match_operand:SI 0 "register_operand" "=d,d")
3357 (minus:SI (match_dup 1) (match_dup 2)))]
3358 "s390_match_ccmode(insn, CCL2mode)"
3362 [(set_attr "op_type" "RR,RX")
3363 (set_attr "atype" "reg,mem")])
3365 (define_insn "*subsi3_borrow_cconly"
3367 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3368 (match_operand:SI 2 "general_operand" "d,m"))
3370 (clobber (match_scratch:SI 0 "=d,d"))]
3371 "s390_match_ccmode(insn, CCL2mode)"
3375 [(set_attr "op_type" "RR,RX")
3376 (set_attr "atype" "reg,mem")])
3378 (define_insn "*subsi3_cc"
3380 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3381 (match_operand:SI 2 "general_operand" "d,m"))
3383 (set (match_operand:SI 0 "register_operand" "=d,d")
3384 (minus:SI (match_dup 1) (match_dup 2)))]
3385 "s390_match_ccmode(insn, CCLmode)"
3389 [(set_attr "op_type" "RR,RX")
3390 (set_attr "atype" "reg,mem")])
3392 (define_insn "*subsi3_cconly"
3394 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3395 (match_operand:SI 2 "general_operand" "d,m"))
3397 (clobber (match_scratch:SI 0 "=d,d"))]
3398 "s390_match_ccmode(insn, CCLmode)"
3402 [(set_attr "op_type" "RR,RX")
3403 (set_attr "atype" "reg,mem")])
3405 (define_insn "*subsi3_sign"
3406 [(set (match_operand:SI 0 "register_operand" "=d")
3407 (minus:SI (match_operand:SI 1 "register_operand" "0")
3408 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3409 (clobber (reg:CC 33))]
3412 [(set_attr "op_type" "RX")
3413 (set_attr "atype" "mem")])
3415 (define_insn "*subsi3_sub"
3416 [(set (match_operand:SI 0 "register_operand" "=d")
3417 (minus:SI (match_operand:SI 1 "register_operand" "0")
3418 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3419 (clobber (reg:CC 33))]
3422 [(set_attr "op_type" "RX")
3423 (set_attr "atype" "mem")])
3425 (define_insn "subsi3"
3426 [(set (match_operand:SI 0 "register_operand" "=d,d")
3427 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3428 (match_operand:SI 2 "general_operand" "d,m")))
3429 (clobber (reg:CC 33))]
3434 [(set_attr "op_type" "RR,RX")
3435 (set_attr "atype" "reg,mem")])
3439 ; subdf3 instruction pattern(s).
3442 (define_expand "subdf3"
3444 [(set (match_operand:DF 0 "register_operand" "=f,f")
3445 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3446 (match_operand:DF 2 "general_operand" "f,m")))
3447 (clobber (reg:CC 33))])]
3451 (define_insn "*subdf3"
3452 [(set (match_operand:DF 0 "register_operand" "=f,f")
3453 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3454 (match_operand:DF 2 "general_operand" "f,m")))
3455 (clobber (reg:CC 33))]
3456 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3460 [(set_attr "op_type" "RRE,RXE")
3461 (set_attr "atype" "reg,mem")])
3463 (define_insn "*subdf3_ibm"
3464 [(set (match_operand:DF 0 "register_operand" "=f,f")
3465 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3466 (match_operand:DF 2 "general_operand" "f,m")))
3467 (clobber (reg:CC 33))]
3468 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3472 [(set_attr "op_type" "RR,RX")
3473 (set_attr "atype" "reg,mem")])
3476 ; subsf3 instruction pattern(s).
3479 (define_expand "subsf3"
3481 [(set (match_operand:SF 0 "register_operand" "=f,f")
3482 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3483 (match_operand:SF 2 "general_operand" "f,m")))
3484 (clobber (reg:CC 33))])]
3488 (define_insn "*subsf3"
3489 [(set (match_operand:SF 0 "register_operand" "=f,f")
3490 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3491 (match_operand:SF 2 "general_operand" "f,m")))
3492 (clobber (reg:CC 33))]
3493 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3497 [(set_attr "op_type" "RRE,RXE")
3498 (set_attr "atype" "reg,mem")])
3500 (define_insn "*subsf3_ibm"
3501 [(set (match_operand:SF 0 "register_operand" "=f,f")
3502 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3503 (match_operand:SF 2 "general_operand" "f,m")))
3504 (clobber (reg:CC 33))]
3505 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3509 [(set_attr "op_type" "RR,RX")
3510 (set_attr "atype" "reg,mem")])
3514 ;;- Multiply instructions.
3518 ; muldi3 instruction pattern(s).
3521 (define_insn "*muldi3_sign"
3522 [(set (match_operand:DI 0 "register_operand" "=d,d")
3523 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3524 (match_operand:DI 1 "register_operand" "0,0")))]
3529 [(set_attr "op_type" "RRE,RXE")
3530 (set_attr "atype" "reg,mem")
3531 (set_attr "type" "imul")])
3534 (define_insn "muldi3"
3535 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3536 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3537 (match_operand:DI 2 "general_operand" "d,K,m")))]
3543 [(set_attr "op_type" "RRE,RI,RXE")
3544 (set_attr "atype" "reg,reg,mem")
3545 (set_attr "type" "imul")])
3548 ; mulsi3 instruction pattern(s).
3551 (define_insn "mulsi3"
3552 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3553 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3554 (match_operand:SI 2 "general_operand" "d,K,m")))]
3560 [(set_attr "op_type" "RRE,RI,RX")
3561 (set_attr "atype" "reg,reg,mem")
3562 (set_attr "type" "imul")])
3565 ; mulsidi3 instruction pattern(s).
3568 (define_expand "mulsidi3"
3569 [(set (match_operand:DI 0 "register_operand" "")
3570 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3571 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3577 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3578 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3581 gen_rtx_EXPR_LIST (REG_EQUAL,
3582 gen_rtx_MULT (DImode,
3583 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3584 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3589 (define_insn "mulsi_6432"
3590 [(set (match_operand:DI 0 "register_operand" "=d,d")
3591 (mult:DI (sign_extend:DI
3592 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3594 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3599 [(set_attr "op_type" "RR,RX")
3600 (set_attr "atype" "reg,mem")
3601 (set_attr "type" "imul")])
3604 ; muldf3 instruction pattern(s).
3607 (define_expand "muldf3"
3609 [(set (match_operand:DF 0 "register_operand" "=f,f")
3610 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3611 (match_operand:DF 2 "general_operand" "f,m")))
3612 (clobber (reg:CC 33))])]
3616 (define_insn "*muldf3"
3617 [(set (match_operand:DF 0 "register_operand" "=f,f")
3618 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3619 (match_operand:DF 2 "general_operand" "f,m")))
3620 (clobber (reg:CC 33))]
3621 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3625 [(set_attr "op_type" "RRE,RXE")
3626 (set_attr "type" "fmul")
3627 (set_attr "atype" "reg,mem")])
3629 (define_insn "*muldf3_ibm"
3630 [(set (match_operand:DF 0 "register_operand" "=f,f")
3631 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3632 (match_operand:DF 2 "general_operand" "f,m")))
3633 (clobber (reg:CC 33))]
3634 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3638 [(set_attr "op_type" "RR,RX")
3639 (set_attr "type" "fmul")
3640 (set_attr "atype" "reg,mem")])
3643 ; mulsf3 instruction pattern(s).
3646 (define_expand "mulsf3"
3648 [(set (match_operand:SF 0 "register_operand" "=f,f")
3649 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3650 (match_operand:SF 2 "general_operand" "f,m")))
3651 (clobber (reg:CC 33))])]
3655 (define_insn "*mulsf3"
3656 [(set (match_operand:SF 0 "register_operand" "=f,f")
3657 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3658 (match_operand:SF 2 "general_operand" "f,m")))
3659 (clobber (reg:CC 33))]
3660 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3664 [(set_attr "op_type" "RRE,RXE")
3665 (set_attr "type" "fmul")
3666 (set_attr "atype" "reg,mem")])
3668 (define_insn "*mulsf3_ibm"
3669 [(set (match_operand:SF 0 "register_operand" "=f,f")
3670 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3671 (match_operand:SF 2 "general_operand" "f,m")))
3672 (clobber (reg:CC 33))]
3673 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3677 [(set_attr "op_type" "RR,RX")
3678 (set_attr "type" "fmul")
3679 (set_attr "atype" "reg,mem")])
3683 ;;- Divide and modulo instructions.
3687 ; divmoddi4 instruction pattern(s).
3690 (define_expand "divmoddi4"
3691 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3692 (div:DI (match_operand:DI 1 "general_operand" "")
3693 (match_operand:DI 2 "general_operand" "")))
3694 (set (match_operand:DI 3 "general_operand" "")
3695 (mod:DI (match_dup 1) (match_dup 2)))])
3696 (clobber (match_dup 4))]
3700 rtx insn, div_equal, mod_equal, equal;
3702 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3703 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3704 equal = gen_rtx_IOR (TImode,
3705 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3706 gen_rtx_ASHIFT (TImode,
3707 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3710 operands[4] = gen_reg_rtx(TImode);
3711 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3712 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3713 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3714 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3716 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3718 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3720 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3722 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3724 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3729 (define_insn "divmodtidi3"
3730 [(set (match_operand:TI 0 "register_operand" "=d,d")
3733 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3734 (match_operand:DI 2 "general_operand" "d,m")))
3737 (mod:DI (truncate:DI (match_dup 1))
3744 [(set_attr "op_type" "RRE,RXE")
3745 (set_attr "type" "idiv")
3746 (set_attr "atype" "reg,mem")])
3748 (define_insn "divmodtisi3"
3749 [(set (match_operand:TI 0 "register_operand" "=d,d")
3752 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3753 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3756 (mod:DI (truncate:DI (match_dup 1))
3757 (sign_extend:DI (match_dup 2))))
3763 [(set_attr "op_type" "RRE,RXE")
3764 (set_attr "type" "idiv")
3765 (set_attr "atype" "reg,mem")])
3768 ; udivmoddi4 instruction pattern(s).
3771 (define_expand "udivmoddi4"
3772 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3773 (udiv:DI (match_operand:DI 1 "general_operand" "")
3774 (match_operand:DI 2 "nonimmediate_operand" "")))
3775 (set (match_operand:DI 3 "general_operand" "")
3776 (umod:DI (match_dup 1) (match_dup 2)))])
3777 (clobber (match_dup 4))]
3781 rtx insn, div_equal, mod_equal, equal;
3783 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3784 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3785 equal = gen_rtx_IOR (TImode,
3786 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3787 gen_rtx_ASHIFT (TImode,
3788 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3791 operands[4] = gen_reg_rtx(TImode);
3792 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3793 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3794 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3795 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3797 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3799 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3801 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3803 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3805 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3810 (define_insn "udivmodtidi3"
3811 [(set (match_operand:TI 0 "register_operand" "=d,d")
3812 (ior:TI (zero_extend:TI
3814 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3816 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3820 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3826 [(set_attr "op_type" "RRE,RXE")
3827 (set_attr "type" "idiv")
3828 (set_attr "atype" "reg,mem")])
3831 ; divmodsi4 instruction pattern(s).
3834 (define_expand "divmodsi4"
3835 [(parallel [(set (match_operand:SI 0 "general_operand" "")
3836 (div:SI (match_operand:SI 1 "general_operand" "")
3837 (match_operand:SI 2 "nonimmediate_operand" "")))
3838 (set (match_operand:SI 3 "general_operand" "")
3839 (mod:SI (match_dup 1) (match_dup 2)))])
3840 (clobber (match_dup 4))]
3844 rtx insn, div_equal, mod_equal, equal;
3846 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
3847 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
3848 equal = gen_rtx_IOR (DImode,
3849 gen_rtx_ZERO_EXTEND (DImode, div_equal),
3850 gen_rtx_ASHIFT (DImode,
3851 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
3854 operands[4] = gen_reg_rtx(DImode);
3855 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
3856 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
3858 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3860 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
3862 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3864 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
3866 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3871 (define_insn "divmoddisi3"
3872 [(set (match_operand:DI 0 "register_operand" "=d,d")
3873 (ior:DI (zero_extend:DI
3875 (div:DI (match_operand:DI 1 "register_operand" "0,0")
3877 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
3881 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
3887 [(set_attr "op_type" "RR,RX")
3888 (set_attr "type" "idiv")
3889 (set_attr "atype" "reg,mem")])
3892 ; udivsi3 and umodsi3 instruction pattern(s).
3896 (define_expand "udivsi3"
3897 [(set (match_operand:SI 0 "register_operand" "=d")
3898 (udiv:SI (match_operand:SI 1 "general_operand" "")
3899 (match_operand:SI 2 "general_operand" "")))
3900 (clobber (match_dup 3))]
3904 rtx insn, udiv_equal, umod_equal, equal;
3906 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
3907 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
3908 equal = gen_rtx_IOR (DImode,
3909 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
3910 gen_rtx_ASHIFT (DImode,
3911 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
3914 operands[3] = gen_reg_rtx (DImode);
3916 if (CONSTANT_P (operands[2]))
3918 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3920 rtx label1 = gen_label_rtx ();
3922 operands[1] = make_safe_from (operands[1], operands[0]);
3923 emit_move_insn (operands[0], const0_rtx);
3924 emit_insn (gen_cmpsi (operands[1], operands[2]));
3925 emit_jump_insn (gen_bltu (label1));
3926 emit_move_insn (operands[0], const1_rtx);
3927 emit_label (label1);
3931 operands[2] = force_reg (SImode, operands[2]);
3932 operands[2] = make_safe_from (operands[2], operands[0]);
3934 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
3935 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
3938 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3940 insn = emit_move_insn (operands[0],
3941 gen_lowpart (SImode, operands[3]));
3943 gen_rtx_EXPR_LIST (REG_EQUAL,
3944 udiv_equal, REG_NOTES (insn));
3949 rtx label1 = gen_label_rtx ();
3950 rtx label2 = gen_label_rtx ();
3951 rtx label3 = gen_label_rtx ();
3953 operands[1] = force_reg (SImode, operands[1]);
3954 operands[1] = make_safe_from (operands[1], operands[0]);
3955 operands[2] = force_reg (SImode, operands[2]);
3956 operands[2] = make_safe_from (operands[2], operands[0]);
3958 emit_move_insn (operands[0], const0_rtx);
3959 emit_insn (gen_cmpsi (operands[2], operands[1]));
3960 emit_jump_insn (gen_bgtu (label3));
3961 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3962 emit_jump_insn (gen_blt (label2));
3963 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3964 emit_jump_insn (gen_beq (label1));
3965 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
3966 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
3969 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3971 insn = emit_move_insn (operands[0],
3972 gen_lowpart (SImode, operands[3]));
3974 gen_rtx_EXPR_LIST (REG_EQUAL,
3975 udiv_equal, REG_NOTES (insn));
3977 emit_label (label1);
3978 emit_move_insn (operands[0], operands[1]);
3980 emit_label (label2);
3981 emit_move_insn (operands[0], const1_rtx);
3982 emit_label (label3);
3984 emit_move_insn (operands[0], operands[0]);
3988 (define_expand "umodsi3"
3989 [(set (match_operand:SI 0 "register_operand" "=d")
3990 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
3991 (match_operand:SI 2 "nonimmediate_operand" "")))
3992 (clobber (match_dup 3))]
3996 rtx insn, udiv_equal, umod_equal, equal;
3998 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
3999 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4000 equal = gen_rtx_IOR (DImode,
4001 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4002 gen_rtx_ASHIFT (DImode,
4003 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4006 operands[3] = gen_reg_rtx (DImode);
4008 if (CONSTANT_P (operands[2]))
4010 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4012 rtx label1 = gen_label_rtx ();
4014 operands[1] = make_safe_from (operands[1], operands[0]);
4015 emit_move_insn (operands[0], operands[1]);
4016 emit_insn (gen_cmpsi (operands[0], operands[2]));
4017 emit_jump_insn (gen_bltu (label1));
4018 emit_insn (gen_abssi2 (operands[0], operands[2]));
4019 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4020 emit_label (label1);
4024 operands[2] = force_reg (SImode, operands[2]);
4025 operands[2] = make_safe_from (operands[2], operands[0]);
4027 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4028 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4031 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4033 insn = emit_move_insn (operands[0],
4034 gen_highpart (SImode, operands[3]));
4036 gen_rtx_EXPR_LIST (REG_EQUAL,
4037 umod_equal, REG_NOTES (insn));
4042 rtx label1 = gen_label_rtx ();
4043 rtx label2 = gen_label_rtx ();
4044 rtx label3 = gen_label_rtx ();
4046 operands[1] = force_reg (SImode, operands[1]);
4047 operands[1] = make_safe_from (operands[1], operands[0]);
4048 operands[2] = force_reg (SImode, operands[2]);
4049 operands[2] = make_safe_from (operands[2], operands[0]);
4051 emit_move_insn(operands[0], operands[1]);
4052 emit_insn (gen_cmpsi (operands[2], operands[1]));
4053 emit_jump_insn (gen_bgtu (label3));
4054 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4055 emit_jump_insn (gen_blt (label2));
4056 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4057 emit_jump_insn (gen_beq (label1));
4058 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4059 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4062 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4064 insn = emit_move_insn (operands[0],
4065 gen_highpart (SImode, operands[3]));
4067 gen_rtx_EXPR_LIST (REG_EQUAL,
4068 umod_equal, REG_NOTES (insn));
4070 emit_label (label1);
4071 emit_move_insn (operands[0], const0_rtx);
4073 emit_label (label2);
4074 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4075 emit_label (label3);
4081 ; divdf3 instruction pattern(s).
4084 (define_expand "divdf3"
4086 [(set (match_operand:DF 0 "register_operand" "=f,f")
4087 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4088 (match_operand:DF 2 "general_operand" "f,m")))
4089 (clobber (reg:CC 33))])]
4093 (define_insn "*divdf3"
4094 [(set (match_operand:DF 0 "register_operand" "=f,f")
4095 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4096 (match_operand:DF 2 "general_operand" "f,m")))
4097 (clobber (reg:CC 33))]
4098 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4102 [(set_attr "op_type" "RRE,RXE")
4103 (set_attr "type" "fdiv")
4104 (set_attr "atype" "reg,mem")])
4106 (define_insn "*divdf3_ibm"
4107 [(set (match_operand:DF 0 "register_operand" "=f,f")
4108 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4109 (match_operand:DF 2 "general_operand" "f,m")))
4110 (clobber (reg:CC 33))]
4111 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4115 [(set_attr "op_type" "RR,RX")
4116 (set_attr "type" "fdiv")
4117 (set_attr "atype" "reg,mem")])
4120 ; divsf3 instruction pattern(s).
4123 (define_expand "divsf3"
4125 [(set (match_operand:SF 0 "register_operand" "=f,f")
4126 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4127 (match_operand:SF 2 "general_operand" "f,m")))
4128 (clobber (reg:CC 33))])]
4132 (define_insn "*divsf3"
4133 [(set (match_operand:SF 0 "register_operand" "=f,f")
4134 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4135 (match_operand:SF 2 "general_operand" "f,m")))
4136 (clobber (reg:CC 33))]
4137 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4141 [(set_attr "op_type" "RRE,RXE")
4142 (set_attr "type" "fdiv")
4143 (set_attr "atype" "reg,mem")])
4145 (define_insn "*divsf3"
4146 [(set (match_operand:SF 0 "register_operand" "=f,f")
4147 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4148 (match_operand:SF 2 "general_operand" "f,m")))
4149 (clobber (reg:CC 33))]
4150 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4154 [(set_attr "op_type" "RR,RX")
4155 (set_attr "type" "fdiv")
4156 (set_attr "atype" "reg,mem")])
4160 ;;- And instructions.
4164 ; anddi3 instruction pattern(s).
4167 (define_insn "*anddi3_cc"
4169 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4170 (match_operand:DI 2 "general_operand" "d,m"))
4172 (set (match_operand:DI 0 "register_operand" "=d,d")
4173 (and:DI (match_dup 1) (match_dup 2)))]
4174 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4178 [(set_attr "op_type" "RRE,RXE")
4179 (set_attr "atype" "reg,mem")])
4181 (define_insn "*anddi3_cconly"
4183 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4184 (match_operand:DI 2 "general_operand" "d,m"))
4186 (clobber (match_scratch:DI 0 "=d,d"))]
4187 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4191 [(set_attr "op_type" "RRE,RXE")
4192 (set_attr "atype" "reg,mem")])
4194 (define_insn "*anddi3_ni"
4195 [(set (match_operand:DI 0 "register_operand" "=d")
4196 (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4197 (match_operand:DI 2 "immediate_operand" "n")))
4198 (clobber (reg:CC 33))]
4199 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4202 int part = s390_single_hi (operands[2], DImode, -1);
4203 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4207 case 0: return \"nihh\\t%0,%x2\";
4208 case 1: return \"nihl\\t%0,%x2\";
4209 case 2: return \"nilh\\t%0,%x2\";
4210 case 3: return \"nill\\t%0,%x2\";
4214 [(set_attr "op_type" "RI")
4215 (set_attr "atype" "reg")])
4217 (define_insn "anddi3"
4218 [(set (match_operand:DI 0 "register_operand" "=d,d")
4219 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4220 (match_operand:DI 2 "general_operand" "d,m")))
4221 (clobber (reg:CC 33))]
4226 [(set_attr "op_type" "RRE,RXE")
4227 (set_attr "atype" "reg,mem")])
4229 (define_insn "*anddi3_ss"
4230 [(set (match_operand:DI 0 "s_operand" "=Q")
4231 (and:DI (match_dup 0)
4232 (match_operand:DI 1 "s_imm_operand" "Q")))
4233 (clobber (reg:CC 33))]
4235 "nc\\t%O0(8,%R0),%1"
4236 [(set_attr "op_type" "SS")
4237 (set_attr "atype" "mem")])
4239 (define_insn "*anddi3_ss_inv"
4240 [(set (match_operand:DI 0 "s_operand" "=Q")
4241 (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4243 (clobber (reg:CC 33))]
4245 "nc\\t%O0(8,%R0),%1"
4246 [(set_attr "op_type" "SS")
4247 (set_attr "atype" "mem")])
4250 ; andsi3 instruction pattern(s).
4253 (define_insn "*andsi3_cc"
4255 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4256 (match_operand:SI 2 "general_operand" "d,m"))
4258 (set (match_operand:SI 0 "register_operand" "=d,d")
4259 (and:SI (match_dup 1) (match_dup 2)))]
4260 "s390_match_ccmode(insn, CCTmode)"
4264 [(set_attr "op_type" "RR,RX")
4265 (set_attr "atype" "reg,mem")])
4267 (define_insn "*andsi3_cconly"
4269 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4270 (match_operand:SI 2 "general_operand" "d,m"))
4272 (clobber (match_scratch:SI 0 "=d,d"))]
4273 "s390_match_ccmode(insn, CCTmode)"
4277 [(set_attr "op_type" "RR,RX")
4278 (set_attr "atype" "reg,mem")])
4280 (define_insn "*andsi3_ni"
4281 [(set (match_operand:SI 0 "register_operand" "=d")
4282 (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4283 (match_operand:SI 2 "immediate_operand" "n")))
4284 (clobber (reg:CC 33))]
4285 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4288 int part = s390_single_hi (operands[2], SImode, -1);
4289 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4293 case 0: return \"nilh\\t%0,%x2\";
4294 case 1: return \"nill\\t%0,%x2\";
4298 [(set_attr "op_type" "RI")
4299 (set_attr "atype" "reg")])
4301 (define_insn "andsi3"
4302 [(set (match_operand:SI 0 "register_operand" "=d,d")
4303 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4304 (match_operand:SI 2 "general_operand" "d,m")))
4305 (clobber (reg:CC 33))]
4310 [(set_attr "op_type" "RR,RX")
4311 (set_attr "atype" "reg,mem")])
4313 (define_insn "*andsi3_ss"
4314 [(set (match_operand:SI 0 "s_operand" "=Q")
4315 (and:SI (match_dup 0)
4316 (match_operand:SI 1 "s_imm_operand" "Q")))
4317 (clobber (reg:CC 33))]
4319 "nc\\t%O0(4,%R0),%1"
4320 [(set_attr "op_type" "SS")
4321 (set_attr "atype" "mem")])
4323 (define_insn "*andsi3_ss_inv"
4324 [(set (match_operand:SI 0 "s_operand" "=Q")
4325 (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4327 (clobber (reg:CC 33))]
4329 "nc\\t%O0(4,%R0),%1"
4330 [(set_attr "op_type" "SS")
4331 (set_attr "atype" "mem")])
4334 ; andhi3 instruction pattern(s).
4337 (define_insn "*andhi3_ni"
4338 [(set (match_operand:HI 0 "register_operand" "=d,d")
4339 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4340 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4341 (clobber (reg:CC 33))]
4346 [(set_attr "op_type" "RR,RI")
4347 (set_attr "atype" "reg")])
4349 (define_insn "andhi3"
4350 [(set (match_operand:HI 0 "register_operand" "=d")
4351 (and:HI (match_operand:HI 1 "register_operand" "%0")
4352 (match_operand:HI 2 "nonmemory_operand" "d")))
4353 (clobber (reg:CC 33))]
4356 [(set_attr "op_type" "RR")
4357 (set_attr "atype" "reg")])
4359 (define_insn "*andhi3_ss"
4360 [(set (match_operand:HI 0 "s_operand" "=Q")
4361 (and:HI (match_dup 0)
4362 (match_operand:HI 1 "s_imm_operand" "Q")))
4363 (clobber (reg:CC 33))]
4365 "nc\\t%O0(2,%R0),%1"
4366 [(set_attr "op_type" "SS")
4367 (set_attr "atype" "mem")])
4369 (define_insn "*andhi3_ss_inv"
4370 [(set (match_operand:HI 0 "s_operand" "=Q")
4371 (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4373 (clobber (reg:CC 33))]
4375 "nc\\t%O0(2,%R0),%1"
4376 [(set_attr "op_type" "SS")
4377 (set_attr "atype" "mem")])
4380 ; andqi3 instruction pattern(s).
4383 (define_insn "*andqi3_ni"
4384 [(set (match_operand:QI 0 "register_operand" "=d,d")
4385 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4386 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4387 (clobber (reg:CC 33))]
4392 [(set_attr "op_type" "RR,RI")
4393 (set_attr "atype" "reg")])
4395 (define_insn "andqi3"
4396 [(set (match_operand:QI 0 "register_operand" "=d")
4397 (and:QI (match_operand:QI 1 "register_operand" "%0")
4398 (match_operand:QI 2 "nonmemory_operand" "d")))
4399 (clobber (reg:CC 33))]
4402 [(set_attr "op_type" "RR")
4403 (set_attr "atype" "reg")])
4405 (define_insn "*andqi3_ss"
4406 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4407 (and:QI (match_dup 0)
4408 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4409 (clobber (reg:CC 33))]
4414 [(set_attr "op_type" "SI,SS")
4415 (set_attr "atype" "mem")])
4417 (define_insn "*andqi3_ss_inv"
4418 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4419 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4421 (clobber (reg:CC 33))]
4426 [(set_attr "op_type" "SI,SS")
4427 (set_attr "atype" "mem")])
4431 ;;- Bit set (inclusive or) instructions.
4435 ; iordi3 instruction pattern(s).
4438 (define_insn "*iordi3_cc"
4440 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4441 (match_operand:DI 2 "general_operand" "d,m"))
4443 (set (match_operand:DI 0 "register_operand" "=d,d")
4444 (ior:DI (match_dup 1) (match_dup 2)))]
4445 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4449 [(set_attr "op_type" "RRE,RXE")
4450 (set_attr "atype" "reg,mem")])
4452 (define_insn "*iordi3_cconly"
4454 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4455 (match_operand:DI 2 "general_operand" "d,m"))
4457 (clobber (match_scratch:DI 0 "=d,d"))]
4458 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4462 [(set_attr "op_type" "RRE,RXE")
4463 (set_attr "atype" "reg,mem")])
4465 (define_insn "*iordi3_oi"
4466 [(set (match_operand:DI 0 "register_operand" "=d")
4467 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4468 (match_operand:DI 2 "immediate_operand" "n")))
4469 (clobber (reg:CC 33))]
4470 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4473 int part = s390_single_hi (operands[2], DImode, 0);
4474 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4478 case 0: return \"oihh\\t%0,%x2\";
4479 case 1: return \"oihl\\t%0,%x2\";
4480 case 2: return \"oilh\\t%0,%x2\";
4481 case 3: return \"oill\\t%0,%x2\";
4485 [(set_attr "op_type" "RI")
4486 (set_attr "atype" "reg")])
4488 (define_insn "iordi3"
4489 [(set (match_operand:DI 0 "register_operand" "=d,d")
4490 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4491 (match_operand:DI 2 "general_operand" "d,m")))
4492 (clobber (reg:CC 33))]
4497 [(set_attr "op_type" "RRE,RXE")
4498 (set_attr "atype" "reg,mem")])
4500 (define_insn "*iordi3_ss"
4501 [(set (match_operand:DI 0 "s_operand" "=Q")
4502 (ior:DI (match_dup 0)
4503 (match_operand:DI 1 "s_imm_operand" "Q")))
4504 (clobber (reg:CC 33))]
4506 "oc\\t%O0(8,%R0),%1"
4507 [(set_attr "op_type" "SS")
4508 (set_attr "atype" "mem")])
4510 (define_insn "*iordi3_ss_inv"
4511 [(set (match_operand:DI 0 "s_operand" "=Q")
4512 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4514 (clobber (reg:CC 33))]
4516 "oc\\t%O0(8,%R0),%1"
4517 [(set_attr "op_type" "SS")
4518 (set_attr "atype" "mem")])
4521 ; iorsi3 instruction pattern(s).
4524 (define_insn "*iorsi3_cc"
4526 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4527 (match_operand:SI 2 "general_operand" "d,m"))
4529 (set (match_operand:SI 0 "register_operand" "=d,d")
4530 (ior:SI (match_dup 1) (match_dup 2)))]
4531 "s390_match_ccmode(insn, CCTmode)"
4535 [(set_attr "op_type" "RR,RX")
4536 (set_attr "atype" "reg,mem")])
4538 (define_insn "*iorsi3_cconly"
4540 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4541 (match_operand:SI 2 "general_operand" "d,m"))
4543 (clobber (match_scratch:SI 0 "=d,d"))]
4544 "s390_match_ccmode(insn, CCTmode)"
4548 [(set_attr "op_type" "RR,RX")
4549 (set_attr "atype" "reg,mem")])
4551 (define_insn "*iorsi3_oi"
4552 [(set (match_operand:SI 0 "register_operand" "=d")
4553 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
4554 (match_operand:SI 2 "immediate_operand" "n")))
4555 (clobber (reg:CC 33))]
4556 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4559 int part = s390_single_hi (operands[2], SImode, 0);
4560 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4564 case 0: return \"oilh\\t%0,%x2\";
4565 case 1: return \"oill\\t%0,%x2\";
4569 [(set_attr "op_type" "RI")
4570 (set_attr "atype" "reg")])
4572 (define_insn "iorsi3"
4573 [(set (match_operand:SI 0 "register_operand" "=d,d")
4574 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4575 (match_operand:SI 2 "general_operand" "d,m")))
4576 (clobber (reg:CC 33))]
4581 [(set_attr "op_type" "RR,RX")
4582 (set_attr "atype" "reg,mem")])
4584 (define_insn "*iorsi3_ss"
4585 [(set (match_operand:SI 0 "s_operand" "=Q")
4586 (ior:SI (match_dup 0)
4587 (match_operand:SI 1 "s_imm_operand" "Q")))
4588 (clobber (reg:CC 33))]
4590 "oc\\t%O0(4,%R0),%1"
4591 [(set_attr "op_type" "SS")
4592 (set_attr "atype" "mem")])
4594 (define_insn "*iorsi3_ss_inv"
4595 [(set (match_operand:SI 0 "s_operand" "=Q")
4596 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4598 (clobber (reg:CC 33))]
4600 "oc\\t%O0(4,%R0),%1"
4601 [(set_attr "op_type" "SS")
4602 (set_attr "atype" "mem")])
4605 ; iorhi3 instruction pattern(s).
4608 (define_insn "*iorhi3_oi"
4609 [(set (match_operand:HI 0 "register_operand" "=d,d")
4610 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4611 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4612 (clobber (reg:CC 33))]
4617 [(set_attr "op_type" "RR,RI")
4618 (set_attr "atype" "reg")])
4620 (define_insn "iorhi3"
4621 [(set (match_operand:HI 0 "register_operand" "=d")
4622 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4623 (match_operand:HI 2 "nonmemory_operand" "d")))
4624 (clobber (reg:CC 33))]
4627 [(set_attr "op_type" "RR")
4628 (set_attr "atype" "reg")])
4630 (define_insn "*iorhi3_ss"
4631 [(set (match_operand:HI 0 "s_operand" "=Q")
4632 (ior:HI (match_dup 0)
4633 (match_operand:HI 1 "s_imm_operand" "Q")))
4634 (clobber (reg:CC 33))]
4636 "oc\\t%O0(2,%R0),%1"
4637 [(set_attr "op_type" "SS")
4638 (set_attr "atype" "mem")])
4640 (define_insn "*iorhi3_ss_inv"
4641 [(set (match_operand:HI 0 "s_operand" "=Q")
4642 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4644 (clobber (reg:CC 33))]
4646 "oc\\t%O0(2,%R0),%1"
4647 [(set_attr "op_type" "SS")
4648 (set_attr "atype" "mem")])
4651 ; iorqi3 instruction pattern(s).
4654 (define_insn "*iorqi3_oi"
4655 [(set (match_operand:QI 0 "register_operand" "=d,d")
4656 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4657 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4658 (clobber (reg:CC 33))]
4663 [(set_attr "op_type" "RR,RI")
4664 (set_attr "atype" "reg")])
4666 (define_insn "iorqi3"
4667 [(set (match_operand:QI 0 "register_operand" "=d")
4668 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4669 (match_operand:QI 2 "nonmemory_operand" "d")))
4670 (clobber (reg:CC 33))]
4673 [(set_attr "op_type" "RR")
4674 (set_attr "atype" "reg")])
4676 (define_insn "*iorqi3_ss"
4677 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4678 (ior:QI (match_dup 0)
4679 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4680 (clobber (reg:CC 33))]
4685 [(set_attr "op_type" "SI,SS")
4686 (set_attr "atype" "reg,mem")])
4688 (define_insn "*iorqi3_ss_inv"
4689 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4690 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4692 (clobber (reg:CC 33))]
4697 [(set_attr "op_type" "SI,SS")
4698 (set_attr "atype" "reg,mem")])
4702 ;;- Xor instructions.
4706 ; xordi3 instruction pattern(s).
4709 (define_insn "*xordi3_cc"
4711 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4712 (match_operand:DI 2 "general_operand" "d,m"))
4714 (set (match_operand:DI 0 "register_operand" "=d,d")
4715 (xor:DI (match_dup 1) (match_dup 2)))]
4716 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4720 [(set_attr "op_type" "RRE,RXE")
4721 (set_attr "atype" "reg,mem")])
4723 (define_insn "*xordi3_cconly"
4725 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4726 (match_operand:DI 2 "general_operand" "d,m"))
4728 (clobber (match_scratch:DI 0 "=d,d"))]
4729 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4733 [(set_attr "op_type" "RRE,RXE")
4734 (set_attr "atype" "reg,mem")])
4736 (define_insn "xordi3"
4737 [(set (match_operand:DI 0 "register_operand" "=d,d")
4738 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4739 (match_operand:DI 2 "general_operand" "d,m")))
4740 (clobber (reg:CC 33))]
4745 [(set_attr "op_type" "RRE,RXE")
4746 (set_attr "atype" "reg,mem")])
4748 (define_insn "*xordi3_ss"
4749 [(set (match_operand:DI 0 "s_operand" "=Q")
4750 (xor:DI (match_dup 0)
4751 (match_operand:DI 1 "s_imm_operand" "Q")))
4752 (clobber (reg:CC 33))]
4754 "xc\\t%O0(8,%R0),%1"
4755 [(set_attr "op_type" "SS")
4756 (set_attr "atype" "mem")])
4758 (define_insn "*xordi3_ss_inv"
4759 [(set (match_operand:DI 0 "s_operand" "=Q")
4760 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4762 (clobber (reg:CC 33))]
4764 "xc\\t%O0(8,%R0),%1"
4765 [(set_attr "op_type" "SS")
4766 (set_attr "atype" "mem")])
4769 ; xorsi3 instruction pattern(s).
4772 (define_insn "*xorsi3_cc"
4774 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4775 (match_operand:SI 2 "general_operand" "d,m"))
4777 (set (match_operand:SI 0 "register_operand" "=d,d")
4778 (xor:SI (match_dup 1) (match_dup 2)))]
4779 "s390_match_ccmode(insn, CCTmode)"
4783 [(set_attr "op_type" "RR,RX")
4784 (set_attr "atype" "reg,mem")])
4786 (define_insn "*xorsi3_cconly"
4788 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4789 (match_operand:SI 2 "general_operand" "d,m"))
4791 (clobber (match_scratch:SI 0 "=d,d"))]
4792 "s390_match_ccmode(insn, CCTmode)"
4796 [(set_attr "op_type" "RR,RX")
4797 (set_attr "atype" "reg,mem")])
4799 (define_insn "xorsi3"
4800 [(set (match_operand:SI 0 "register_operand" "=d,d")
4801 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4802 (match_operand:SI 2 "general_operand" "d,m")))
4803 (clobber (reg:CC 33))]
4808 [(set_attr "op_type" "RR,RX")
4809 (set_attr "atype" "reg,mem")])
4811 (define_insn "*xorsi3_ss"
4812 [(set (match_operand:SI 0 "s_operand" "=Q")
4813 (xor:SI (match_dup 0)
4814 (match_operand:SI 1 "s_imm_operand" "Q")))
4815 (clobber (reg:CC 33))]
4817 "xc\\t%O0(4,%R0),%1"
4818 [(set_attr "op_type" "SS")
4819 (set_attr "atype" "mem")])
4821 (define_insn "*xorsi3_ss_inv"
4822 [(set (match_operand:SI 0 "s_operand" "=Q")
4823 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
4825 (clobber (reg:CC 33))]
4827 "xc\\t%O0(4,%R0),%1"
4828 [(set_attr "op_type" "SS")
4829 (set_attr "atype" "mem")])
4832 ; xorhi3 instruction pattern(s).
4835 (define_insn "xorhi3"
4836 [(set (match_operand:HI 0 "register_operand" "=d")
4837 (xor:HI (match_operand:HI 1 "register_operand" "%0")
4838 (match_operand:HI 2 "nonmemory_operand" "d")))
4839 (clobber (reg:CC 33))]
4842 [(set_attr "op_type" "RR")
4843 (set_attr "atype" "reg")])
4845 (define_insn "*xorhi3_ss"
4846 [(set (match_operand:HI 0 "s_operand" "=Q")
4847 (xor:HI (match_dup 0)
4848 (match_operand:HI 1 "s_imm_operand" "Q")))
4849 (clobber (reg:CC 33))]
4851 "xc\\t%O0(2,%R0),%1"
4852 [(set_attr "op_type" "SS")
4853 (set_attr "atype" "mem")])
4855 (define_insn "*xorhi3_ss_inv"
4856 [(set (match_operand:HI 0 "s_operand" "=Q")
4857 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
4859 (clobber (reg:CC 33))]
4861 "xc\\t%O0(2,%R0),%1"
4862 [(set_attr "op_type" "SS")
4863 (set_attr "atype" "mem")])
4866 ; xorqi3 instruction pattern(s).
4869 (define_insn "xorqi3"
4870 [(set (match_operand:QI 0 "register_operand" "=d")
4871 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4872 (match_operand:QI 2 "nonmemory_operand" "d")))
4873 (clobber (reg:CC 33))]
4876 [(set_attr "op_type" "RR")
4877 (set_attr "atype" "reg")])
4879 (define_insn "*xorqi3_ss"
4880 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4881 (xor:QI (match_dup 0)
4882 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4883 (clobber (reg:CC 33))]
4888 [(set_attr "op_type" "SI,SS")
4889 (set_attr "atype" "mem")])
4891 (define_insn "*xorqi3_ss_inv"
4892 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4893 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4895 (clobber (reg:CC 33))]
4900 [(set_attr "op_type" "SI,SS")
4901 (set_attr "atype" "mem")])
4905 ;;- Negate instructions.
4909 ; negdi2 instruction pattern(s).
4912 (define_expand "negdi2"
4914 [(set (match_operand:DI 0 "register_operand" "=d")
4915 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4916 (clobber (reg:CC 33))])]
4920 (define_insn "*negdi2_64"
4921 [(set (match_operand:DI 0 "register_operand" "=d")
4922 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4923 (clobber (reg:CC 33))]
4926 [(set_attr "op_type" "RR")])
4928 (define_insn "*negdi2_31"
4929 [(set (match_operand:DI 0 "register_operand" "=d")
4930 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4931 (clobber (reg:CC 33))]
4936 xop[0] = gen_label_rtx ();
4937 output_asm_insn (\"lcr\\t%0,%1\", operands);
4938 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
4939 output_asm_insn (\"je\\t%l0\", xop);
4940 output_asm_insn (\"bctr\\t%0,0\", operands);
4941 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
4942 CODE_LABEL_NUMBER (xop[0]));
4945 [(set_attr "op_type" "NN")
4946 (set_attr "type" "other")
4947 (set_attr "length" "10")])
4950 ; negsi2 instruction pattern(s).
4953 (define_insn "negsi2"
4954 [(set (match_operand:SI 0 "register_operand" "=d")
4955 (neg:SI (match_operand:SI 1 "register_operand" "d")))
4956 (clobber (reg:CC 33))]
4959 [(set_attr "op_type" "RR")])
4962 ; negdf2 instruction pattern(s).
4965 (define_expand "negdf2"
4967 [(set (match_operand:DF 0 "register_operand" "=f")
4968 (neg:DF (match_operand:DF 1 "register_operand" "f")))
4969 (clobber (reg:CC 33))])]
4973 (define_insn "*negdf2"
4974 [(set (match_operand:DF 0 "register_operand" "=f")
4975 (neg:DF (match_operand:DF 1 "register_operand" "f")))
4976 (clobber (reg:CC 33))]
4977 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4979 [(set_attr "op_type" "RRE")])
4981 (define_insn "*negdf2_ibm"
4982 [(set (match_operand:DF 0 "register_operand" "=f")
4983 (neg:DF (match_operand:DF 1 "register_operand" "f")))
4984 (clobber (reg:CC 33))]
4985 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4987 [(set_attr "op_type" "RR")])
4990 ; negsf2 instruction pattern(s).
4993 (define_expand "negsf2"
4995 [(set (match_operand:SF 0 "register_operand" "=f")
4996 (neg:SF (match_operand:SF 1 "register_operand" "f")))
4997 (clobber (reg:CC 33))])]
5001 (define_insn "*negsf2"
5002 [(set (match_operand:SF 0 "register_operand" "=f")
5003 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5004 (clobber (reg:CC 33))]
5005 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5007 [(set_attr "op_type" "RRE")])
5009 (define_insn "*negsf2"
5010 [(set (match_operand:SF 0 "register_operand" "=f")
5011 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5012 (clobber (reg:CC 33))]
5013 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5015 [(set_attr "op_type" "RR")])
5019 ;;- Absolute value instructions.
5023 ; absdi2 instruction pattern(s).
5026 (define_insn "absdi2"
5027 [(set (match_operand:DI 0 "register_operand" "=d")
5028 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5029 (clobber (reg:CC 33))]
5032 [(set_attr "op_type" "RRE")])
5035 ; abssi2 instruction pattern(s).
5038 (define_insn "abssi2"
5039 [(set (match_operand:SI 0 "register_operand" "=d")
5040 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5041 (clobber (reg:CC 33))]
5044 [(set_attr "op_type" "RR")])
5047 ; absdf2 instruction pattern(s).
5050 (define_expand "absdf2"
5052 [(set (match_operand:DF 0 "register_operand" "=f")
5053 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5054 (clobber (reg:CC 33))])]
5058 (define_insn "*absdf2"
5059 [(set (match_operand:DF 0 "register_operand" "=f")
5060 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5061 (clobber (reg:CC 33))]
5062 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5064 [(set_attr "op_type" "RRE")])
5066 (define_insn "*absdf2_ibm"
5067 [(set (match_operand:DF 0 "register_operand" "=f")
5068 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5069 (clobber (reg:CC 33))]
5070 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5072 [(set_attr "op_type" "RR")])
5075 ; abssf2 instruction pattern(s).
5078 (define_expand "abssf2"
5080 [(set (match_operand:SF 0 "register_operand" "=f")
5081 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5082 (clobber (reg:CC 33))])]
5086 (define_insn "*abssf2"
5087 [(set (match_operand:SF 0 "register_operand" "=f")
5088 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5089 (clobber (reg:CC 33))]
5090 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5092 [(set_attr "op_type" "RRE")])
5094 (define_insn "*abssf2_ibm"
5095 [(set (match_operand:SF 0 "register_operand" "=f")
5096 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5097 (clobber (reg:CC 33))]
5098 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5100 [(set_attr "op_type" "RR")])
5103 ;;- Square root instructions.
5107 ; sqrtdf2 instruction pattern(s).
5110 (define_insn "sqrtdf2"
5111 [(set (match_operand:DF 0 "register_operand" "=f,f")
5112 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5113 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5117 [(set_attr "op_type" "RRE,RSE")])
5120 ; sqrtsf2 instruction pattern(s).
5123 (define_insn "sqrtsf2"
5124 [(set (match_operand:SF 0 "register_operand" "=f,f")
5125 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5126 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5130 [(set_attr "op_type" "RRE,RSE")])
5133 ;;- One complement instructions.
5137 ; one_cmpldi2 instruction pattern(s).
5140 (define_expand "one_cmpldi2"
5142 [(set (match_operand:DI 0 "register_operand" "")
5143 (xor:DI (match_operand:DI 1 "register_operand" "")
5145 (clobber (reg:CC 33))])]
5150 ; one_cmplsi2 instruction pattern(s).
5153 (define_expand "one_cmplsi2"
5155 [(set (match_operand:SI 0 "register_operand" "")
5156 (xor:SI (match_operand:SI 1 "register_operand" "")
5158 (clobber (reg:CC 33))])]
5163 ; one_cmplhi2 instruction pattern(s).
5166 (define_expand "one_cmplhi2"
5168 [(set (match_operand:HI 0 "register_operand" "")
5169 (xor:HI (match_operand:HI 1 "register_operand" "")
5171 (clobber (reg:CC 33))])]
5176 ; one_cmplqi2 instruction pattern(s).
5179 (define_expand "one_cmplqi2"
5181 [(set (match_operand:QI 0 "register_operand" "")
5182 (xor:QI (match_operand:QI 1 "register_operand" "")
5184 (clobber (reg:CC 33))])]
5190 ;;- Rotate instructions.
5194 ; rotldi3 instruction pattern(s).
5197 (define_insn "rotldi3"
5198 [(set (match_operand:DI 0 "register_operand" "=d,d")
5199 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5200 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5205 [(set_attr "op_type" "RSE")])
5208 ; rotlsi3 instruction pattern(s).
5211 (define_insn "rotlsi3"
5212 [(set (match_operand:SI 0 "register_operand" "=d,d")
5213 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5214 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5219 [(set_attr "op_type" "RSE")])
5223 ;;- Arithmetic shift instructions.
5227 ; ashldi3 instruction pattern(s).
5230 (define_expand "ashldi3"
5231 [(set (match_operand:DI 0 "register_operand" "")
5232 (ashift:DI (match_operand:DI 1 "register_operand" "")
5233 (match_operand:SI 2 "nonmemory_operand" "")))]
5237 (define_insn "*ashldi3_31"
5238 [(set (match_operand:DI 0 "register_operand" "=d,d")
5239 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5240 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5245 [(set_attr "op_type" "RS")])
5247 (define_insn "*ashldi3_64"
5248 [(set (match_operand:DI 0 "register_operand" "=d,d")
5249 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5250 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5255 [(set_attr "op_type" "RSE")])
5258 ; ashrdi3 instruction pattern(s).
5261 (define_expand "ashrdi3"
5263 [(set (match_operand:DI 0 "register_operand" "")
5264 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5265 (match_operand:SI 2 "nonmemory_operand" "")))
5266 (clobber (reg:CC 33))])]
5270 (define_insn "*ashrdi3_cc_31"
5272 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5273 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5275 (set (match_operand:DI 0 "register_operand" "=d,d")
5276 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5277 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5281 [(set_attr "op_type" "RS")])
5283 (define_insn "*ashrdi3_cconly_31"
5285 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5286 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5288 (clobber (match_scratch:DI 0 "=d,d"))]
5289 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5293 [(set_attr "op_type" "RS")])
5295 (define_insn "*ashrdi3_31"
5296 [(set (match_operand:DI 0 "register_operand" "=d,d")
5297 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5298 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5299 (clobber (reg:CC 33))]
5304 [(set_attr "op_type" "RS")])
5306 (define_insn "*ashrdi3_cc_64"
5308 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5309 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5311 (set (match_operand:DI 0 "register_operand" "=d,d")
5312 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5313 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5317 [(set_attr "op_type" "RSE")])
5319 (define_insn "*ashrdi3_cconly_64"
5321 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5322 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5324 (clobber (match_scratch:DI 0 "=d,d"))]
5325 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5329 [(set_attr "op_type" "RSE")])
5331 (define_insn "*ashrdi3_64"
5332 [(set (match_operand:DI 0 "register_operand" "=d,d")
5333 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5334 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5335 (clobber (reg:CC 33))]
5340 [(set_attr "op_type" "RSE")])
5343 ; ashlsi3 instruction pattern(s).
5346 (define_insn "ashlsi3"
5347 [(set (match_operand:SI 0 "register_operand" "=d,d")
5348 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5349 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5354 [(set_attr "op_type" "RS")])
5357 ; ashrsi3 instruction pattern(s).
5360 (define_insn "*ashrsi3_cc"
5362 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5363 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5365 (set (match_operand:SI 0 "register_operand" "=d,d")
5366 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5367 "s390_match_ccmode(insn, CCSmode)"
5371 [(set_attr "op_type" "RS")])
5373 (define_insn "*ashrsi3_cconly"
5375 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5376 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5378 (clobber (match_scratch:SI 0 "=d,d"))]
5379 "s390_match_ccmode(insn, CCSmode)"
5383 [(set_attr "op_type" "RS")])
5385 (define_insn "ashrsi3"
5386 [(set (match_operand:SI 0 "register_operand" "=d,d")
5387 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5388 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5389 (clobber (reg:CC 33))]
5394 [(set_attr "op_type" "RS")])
5398 ;;- logical shift instructions.
5402 ; lshrdi3 instruction pattern(s).
5405 (define_expand "lshrdi3"
5406 [(set (match_operand:DI 0 "register_operand" "")
5407 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5408 (match_operand:SI 2 "nonmemory_operand" "")))]
5412 (define_insn "*lshrdi3_31"
5413 [(set (match_operand:DI 0 "register_operand" "=d,d")
5414 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5415 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5420 [(set_attr "op_type" "RS,RS")])
5422 (define_insn "*lshrdi3_64"
5423 [(set (match_operand:DI 0 "register_operand" "=d,d")
5424 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5425 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5430 [(set_attr "op_type" "RS,RS")])
5433 ; lshrsi3 instruction pattern(s).
5436 (define_insn "lshrsi3"
5437 [(set (match_operand:SI 0 "register_operand" "=d,d")
5438 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5439 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5444 [(set_attr "op_type" "RS")])
5448 ;; Branch instruction patterns.
5451 (define_expand "beq"
5452 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5454 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5455 (label_ref (match_operand 0 "" ""))
5458 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5460 (define_expand "bne"
5461 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5463 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5464 (label_ref (match_operand 0 "" ""))
5467 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5469 (define_expand "bgt"
5470 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5472 (if_then_else (gt (reg:CCS 33) (const_int 0))
5473 (label_ref (match_operand 0 "" ""))
5476 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5478 (define_expand "bgtu"
5479 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5481 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5482 (label_ref (match_operand 0 "" ""))
5485 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5487 (define_expand "blt"
5488 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5490 (if_then_else (lt (reg:CCS 33) (const_int 0))
5491 (label_ref (match_operand 0 "" ""))
5494 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5496 (define_expand "bltu"
5497 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5499 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5500 (label_ref (match_operand 0 "" ""))
5503 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5505 (define_expand "bge"
5506 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5508 (if_then_else (ge (reg:CCS 33) (const_int 0))
5509 (label_ref (match_operand 0 "" ""))
5512 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5514 (define_expand "bgeu"
5515 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5517 (if_then_else (geu (reg:CCU 33) (const_int 0))
5518 (label_ref (match_operand 0 "" ""))
5521 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5523 (define_expand "ble"
5524 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5526 (if_then_else (le (reg:CCS 33) (const_int 0))
5527 (label_ref (match_operand 0 "" ""))
5530 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5532 (define_expand "bleu"
5533 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5535 (if_then_else (leu (reg:CCU 33) (const_int 0))
5536 (label_ref (match_operand 0 "" ""))
5539 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5541 (define_expand "bunordered"
5542 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5544 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5545 (label_ref (match_operand 0 "" ""))
5548 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5550 (define_expand "bordered"
5551 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5553 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5554 (label_ref (match_operand 0 "" ""))
5557 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5559 (define_expand "buneq"
5560 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5562 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5563 (label_ref (match_operand 0 "" ""))
5566 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5568 (define_expand "bungt"
5569 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5571 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5572 (label_ref (match_operand 0 "" ""))
5575 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5577 (define_expand "bunlt"
5578 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5580 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5581 (label_ref (match_operand 0 "" ""))
5584 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5586 (define_expand "bunge"
5587 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5589 (if_then_else (unge (reg:CCS 33) (const_int 0))
5590 (label_ref (match_operand 0 "" ""))
5593 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5595 (define_expand "bunle"
5596 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5598 (if_then_else (unle (reg:CCS 33) (const_int 0))
5599 (label_ref (match_operand 0 "" ""))
5602 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5604 (define_expand "bltgt"
5605 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5607 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5608 (label_ref (match_operand 0 "" ""))
5611 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5615 ;;- Conditional jump instructions.
5618 (define_insn "cjump"
5621 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5622 (label_ref (match_operand 0 "" ""))
5627 if (get_attr_length (insn) == 4)
5628 return \"j%C1\\t%l0\";
5629 else if (TARGET_64BIT)
5630 return \"jg%C1\\t%l0\";
5634 [(set_attr "op_type" "RI")
5635 (set (attr "length")
5636 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5638 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5640 (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5641 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5642 (const_int 12) (const_int 14))
5643 (eq (symbol_ref "flag_pic") (const_int 0))
5644 (const_int 6)] (const_int 8)))])
5646 (define_insn "*cjump_long"
5649 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5650 (match_operand 0 "address_operand" "p")
5655 if (get_attr_op_type (insn) == OP_TYPE_RR)
5656 return \"b%C1r\\t%0\";
5658 return \"b%C1\\t%a0\";
5660 [(set (attr "op_type")
5661 (if_then_else (match_operand 0 "register_operand" "")
5662 (const_string "RR") (const_string "RX")))
5663 (set_attr "atype" "mem")])
5667 ;;- Negated conditional jump instructions.
5670 (define_insn "icjump"
5673 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5675 (label_ref (match_operand 0 "" ""))))]
5679 if (get_attr_length (insn) == 4)
5680 return \"j%D1\\t%l0\";
5681 else if (TARGET_64BIT)
5682 return \"jg%D1\\t%l0\";
5686 [(set_attr "op_type" "RI")
5687 (set (attr "length")
5688 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5690 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5692 (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5693 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5694 (const_int 12) (const_int 14))
5695 (eq (symbol_ref "flag_pic") (const_int 0))
5696 (const_int 6)] (const_int 8)))])
5698 (define_insn "*icjump_long"
5701 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5703 (match_operand 0 "address_operand" "p")))]
5707 if (get_attr_op_type (insn) == OP_TYPE_RR)
5708 return \"b%D1r\\t%0\";
5710 return \"b%D1\\t%a0\";
5712 [(set (attr "op_type")
5713 (if_then_else (match_operand 0 "register_operand" "")
5714 (const_string "RR") (const_string "RX")))
5715 (set_attr "atype" "mem")])
5718 ;;- Trap instructions.
5722 [(trap_if (const_int 1) (const_int 0))]
5725 [(set_attr "op_type" "RX")])
5727 (define_expand "conditional_trap"
5728 [(set (match_dup 2) (match_dup 3))
5729 (trap_if (match_operator 0 "comparison_operator"
5730 [(match_dup 2) (const_int 0)])
5731 (match_operand:SI 1 "general_operand" ""))]
5735 enum machine_mode ccmode;
5737 if (operands[1] != const0_rtx) FAIL;
5739 ccmode = s390_select_ccmode (GET_CODE (operands[0]),
5740 s390_compare_op0, s390_compare_op1);
5741 operands[2] = gen_rtx_REG (ccmode, 33);
5742 operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
5745 (define_insn "*trap"
5746 [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
5750 [(set_attr "op_type" "RX")])
5753 ;;- Loop instructions.
5755 ;; This is all complicated by the fact that since this is a jump insn
5756 ;; we must handle our own output reloads.
5758 (define_expand "doloop_end"
5759 [(use (match_operand 0 "" "")) ; loop pseudo
5760 (use (match_operand 1 "" "")) ; iterations; zero if unknown
5761 (use (match_operand 2 "" "")) ; max iterations
5762 (use (match_operand 3 "" "")) ; loop level
5763 (use (match_operand 4 "" ""))] ; label
5767 if (GET_MODE (operands[0]) == SImode)
5768 emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
5769 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
5770 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
5777 (define_insn "doloop_si"
5780 (ne (match_operand:SI 1 "register_operand" "d,d")
5782 (label_ref (match_operand 0 "" ""))
5784 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5785 (plus:SI (match_dup 1) (const_int -1)))
5786 (clobber (match_scratch:SI 3 "=X,&d"))
5787 (clobber (reg:CC 33))]
5791 if (which_alternative != 0)
5793 else if (get_attr_length (insn) == 4)
5794 return \"brct\\t%1,%l0\";
5798 [(set_attr "op_type" "RI")
5799 (set (attr "length")
5800 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5802 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5804 (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5805 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5806 (const_int 12) (const_int 14))
5807 (eq (symbol_ref "flag_pic") (const_int 0))
5808 (const_int 6)] (const_int 8)))])
5810 (define_insn "*doloop_si_long"
5813 (ne (match_operand:SI 1 "register_operand" "d,d")
5815 (match_operand 0 "address_operand" "p,p")
5817 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5818 (plus:SI (match_dup 1) (const_int -1)))
5819 (clobber (match_scratch:SI 3 "=X,&d"))
5820 (clobber (reg:CC 33))]
5824 if (get_attr_op_type (insn) == OP_TYPE_RR)
5825 return \"bctr\\t%0\";
5827 return \"bct\\t%a0\";
5829 [(set (attr "op_type")
5830 (if_then_else (match_operand 0 "register_operand" "")
5831 (const_string "RR") (const_string "RX")))
5832 (set_attr "atype" "mem")])
5836 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
5838 (match_operand 0 "" "")
5840 (set (match_operand:SI 2 "nonimmediate_operand" "")
5841 (plus:SI (match_dup 1) (const_int -1)))
5842 (clobber (match_scratch:SI 3 ""))
5843 (clobber (reg:CC 33))]
5845 && (! REG_P (operands[2])
5846 || ! rtx_equal_p (operands[1], operands[2]))"
5847 [(set (match_dup 3) (match_dup 1))
5848 (parallel [(set (reg:CCAN 33)
5849 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
5851 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
5852 (set (match_dup 2) (match_dup 3))
5853 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
5858 (define_insn "doloop_di"
5861 (ne (match_operand:DI 1 "register_operand" "d,d")
5863 (label_ref (match_operand 0 "" ""))
5865 (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
5866 (plus:DI (match_dup 1) (const_int -1)))
5867 (clobber (match_scratch:DI 3 "=X,&d"))
5868 (clobber (reg:CC 33))]
5872 if (which_alternative != 0)
5874 else if (get_attr_length (insn) == 4)
5875 return \"brctg\\t%1,%l0\";
5879 [(set_attr "op_type" "RI")
5880 (set (attr "length")
5881 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5882 (const_int 4) (const_int 12)))])
5884 (define_insn "*doloop_di_long"
5887 (ne (match_operand:DI 1 "register_operand" "d,d")
5889 (match_operand 0 "address_operand" "p,p")
5891 (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
5892 (plus:DI (match_dup 1) (const_int -1)))
5893 (clobber (match_scratch:DI 3 "=X,&d"))
5894 (clobber (reg:CC 33))]
5898 if (get_attr_op_type (insn) == OP_TYPE_RRE)
5899 return \"bctgr\\t%0\";
5901 return \"bctg\\t%a0\";
5903 [(set (attr "op_type")
5904 (if_then_else (match_operand 0 "register_operand" "")
5905 (const_string "RRE") (const_string "RXE")))
5906 (set_attr "atype" "mem")])
5910 (if_then_else (ne (match_operand:DI 1 "register_operand" "")
5912 (match_operand 0 "" "")
5914 (set (match_operand:DI 2 "nonimmediate_operand" "")
5915 (plus:DI (match_dup 1) (const_int -1)))
5916 (clobber (match_scratch:DI 3 ""))
5917 (clobber (reg:CC 33))]
5919 && (! REG_P (operands[2])
5920 || ! rtx_equal_p (operands[1], operands[2]))"
5921 [(set (match_dup 3) (match_dup 1))
5922 (parallel [(set (reg:CCAN 33)
5923 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
5925 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
5926 (set (match_dup 2) (match_dup 3))
5927 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
5933 ;;- Unconditional jump instructions.
5937 ; jump instruction pattern(s).
5941 [(set (pc) (label_ref (match_operand 0 "" "")))]
5945 if (get_attr_length (insn) == 4)
5947 else if (TARGET_64BIT)
5948 return \"jg\\t%l0\";
5952 [(set_attr "op_type" "RI")
5953 (set (attr "length")
5954 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5956 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5958 (eq (symbol_ref "flag_pic") (const_int 0))
5959 (const_int 6)] (const_int 8)))])
5962 ; indirect-jump instruction pattern(s).
5965 (define_insn "indirect_jump"
5966 [(set (pc) (match_operand 0 "address_operand" "p"))]
5970 if (get_attr_op_type (insn) == OP_TYPE_RR)
5975 [(set (attr "op_type")
5976 (if_then_else (match_operand 0 "register_operand" "")
5977 (const_string "RR") (const_string "RX")))
5978 (set_attr "atype" "mem")])
5981 ; casesi instruction pattern(s).
5984 (define_insn "casesi_jump"
5985 [(set (pc) (match_operand 0 "address_operand" "p"))
5986 (use (label_ref (match_operand 1 "" "")))]
5990 if (get_attr_op_type (insn) == OP_TYPE_RR)
5995 [(set (attr "op_type")
5996 (if_then_else (match_operand 0 "register_operand" "")
5997 (const_string "RR") (const_string "RX")))
5998 (set_attr "atype" "mem")])
6000 (define_expand "casesi"
6001 [(match_operand:SI 0 "general_operand" "")
6002 (match_operand:SI 1 "general_operand" "")
6003 (match_operand:SI 2 "general_operand" "")
6004 (label_ref (match_operand 3 "" ""))
6005 (label_ref (match_operand 4 "" ""))]
6009 rtx index = gen_reg_rtx (SImode);
6010 rtx base = gen_reg_rtx (Pmode);
6011 rtx target = gen_reg_rtx (Pmode);
6013 emit_move_insn (index, operands[0]);
6014 emit_insn (gen_subsi3 (index, index, operands[1]));
6015 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6018 if (Pmode != SImode)
6019 index = convert_to_mode (Pmode, index, 1);
6020 if (GET_CODE (index) != REG)
6021 index = copy_to_mode_reg (Pmode, index);
6024 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6026 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6028 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6030 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6031 emit_move_insn (target, index);
6034 target = gen_rtx_PLUS (Pmode, base, target);
6035 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6042 ;;- Jump to subroutine.
6047 ; untyped call instruction pattern(s).
6050 ;; Call subroutine returning any type.
6051 (define_expand "untyped_call"
6052 [(parallel [(call (match_operand 0 "" "")
6054 (match_operand 1 "" "")
6055 (match_operand 2 "" "")])]
6061 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6063 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6065 rtx set = XVECEXP (operands[2], 0, i);
6066 emit_move_insn (SET_DEST (set), SET_SRC (set));
6069 /* The optimizer does not know that the call sets the function value
6070 registers we stored in the result block. We avoid problems by
6071 claiming that all hard registers are used and clobbered at this
6073 emit_insn (gen_blockage ());
6078 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6079 ;; all of memory. This blocks insns from being moved across this point.
6081 (define_insn "blockage"
6082 [(unspec_volatile [(const_int 0)] 0)]
6085 [(set_attr "type" "none")])
6090 ; call instruction pattern(s).
6093 (define_expand "call"
6094 [(call (match_operand 0 "" "")
6095 (match_operand 1 "" ""))
6096 (use (match_operand 2 "" ""))]
6103 /* Direct function calls need special treatment. */
6104 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6106 rtx sym = XEXP (operands[0], 0);
6108 /* When calling a global routine in PIC mode, we must
6109 replace the symbol itself with the PLT stub. */
6110 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6112 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6113 sym = gen_rtx_CONST (Pmode, sym);
6118 /* Unless we can use the bras(l) insn, force the
6119 routine address into a register. */
6120 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6122 rtx target = gen_reg_rtx (Pmode);
6123 emit_move_insn (target, sym);
6127 operands[0] = gen_rtx_MEM (QImode, sym);
6131 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6132 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6134 /* In 31-bit, we must load the GOT register even if the
6135 compiler doesn't know about it, because the PLT glue
6136 code uses it. In 64-bit, this is not necessary. */
6137 if (plt_call && !TARGET_64BIT)
6138 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6143 (define_expand "call_exp"
6144 [(parallel [(call (match_operand 0 "" "")
6145 (match_operand 1 "" ""))
6146 (clobber (match_operand 2 "" ""))])]
6150 (define_insn "brasl"
6151 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6152 (match_operand:SI 1 "const_int_operand" "n"))
6153 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6156 [(set_attr "op_type" "RIL")
6157 (set_attr "type" "jsr")])
6160 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6161 (match_operand:SI 1 "const_int_operand" "n"))
6162 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6165 [(set_attr "op_type" "RI")
6166 (set_attr "type" "jsr")])
6168 (define_insn "basr_64"
6169 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6170 (match_operand:SI 1 "const_int_operand" "n"))
6171 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6174 [(set_attr "op_type" "RR")
6175 (set_attr "type" "jsr")
6176 (set_attr "atype" "mem")])
6178 (define_insn "basr_31"
6179 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6180 (match_operand:SI 1 "const_int_operand" "n"))
6181 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6184 [(set_attr "op_type" "RR")
6185 (set_attr "type" "jsr")
6186 (set_attr "atype" "mem")])
6188 (define_insn "bas_64"
6189 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6190 (match_operand:SI 1 "const_int_operand" "n"))
6191 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6194 [(set_attr "op_type" "RX")
6195 (set_attr "type" "jsr")
6196 (set_attr "atype" "mem")])
6198 (define_insn "bas_31"
6199 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6200 (match_operand:SI 1 "const_int_operand" "n"))
6201 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6204 [(set_attr "op_type" "RX")
6205 (set_attr "type" "jsr")
6206 (set_attr "atype" "mem")])
6210 ; call_value instruction pattern(s).
6213 (define_expand "call_value"
6214 [(set (match_operand 0 "" "")
6215 (call (match_operand 1 "" "")
6216 (match_operand 2 "" "")))
6217 (use (match_operand 3 "" ""))]
6224 /* Direct function calls need special treatment. */
6225 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6227 rtx sym = XEXP (operands[1], 0);
6229 /* When calling a global routine in PIC mode, we must
6230 replace the symbol itself with the PLT stub. */
6231 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6233 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6234 sym = gen_rtx_CONST (Pmode, sym);
6239 /* Unless we can use the bras(l) insn, force the
6240 routine address into a register. */
6241 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6243 rtx target = gen_reg_rtx (Pmode);
6244 emit_move_insn (target, sym);
6248 operands[1] = gen_rtx_MEM (QImode, sym);
6252 insn = emit_call_insn (
6253 gen_call_value_exp (operands[0], operands[1], operands[2],
6254 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6256 /* In 31-bit, we must load the GOT register even if the
6257 compiler doesn't know about it, because the PLT glue
6258 code uses it. In 64-bit, this is not necessary. */
6259 if (plt_call && !TARGET_64BIT)
6260 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6265 (define_expand "call_value_exp"
6266 [(parallel [(set (match_operand 0 "" "")
6267 (call (match_operand 1 "" "")
6268 (match_operand 2 "" "")))
6269 (clobber (match_operand 3 "" ""))])]
6273 (define_insn "brasl_r"
6274 [(set (match_operand 0 "register_operand" "=df")
6275 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6276 (match_operand:SI 2 "const_int_operand" "n")))
6277 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6280 [(set_attr "op_type" "RIL")
6281 (set_attr "type" "jsr")])
6283 (define_insn "bras_r"
6284 [(set (match_operand 0 "register_operand" "=df")
6285 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6286 (match_operand:SI 2 "const_int_operand" "n")))
6287 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6290 [(set_attr "op_type" "RI")
6291 (set_attr "type" "jsr")])
6293 (define_insn "basr_r_64"
6294 [(set (match_operand 0 "register_operand" "=df")
6295 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6296 (match_operand:SI 2 "const_int_operand" "n")))
6297 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6300 [(set_attr "op_type" "RR")
6301 (set_attr "type" "jsr")])
6303 (define_insn "basr_r_31"
6304 [(set (match_operand 0 "register_operand" "=df")
6305 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6306 (match_operand:SI 2 "const_int_operand" "n")))
6307 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6310 [(set_attr "op_type" "RR")
6311 (set_attr "type" "jsr")
6312 (set_attr "atype" "mem")])
6314 (define_insn "bas_r_64"
6315 [(set (match_operand 0 "register_operand" "=df")
6316 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6317 (match_operand:SI 2 "const_int_operand" "n")))
6318 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6321 [(set_attr "op_type" "RX")
6322 (set_attr "type" "jsr")
6323 (set_attr "atype" "mem")])
6325 (define_insn "bas_r_31"
6326 [(set (match_operand 0 "register_operand" "=df")
6327 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6328 (match_operand:SI 2 "const_int_operand" "n")))
6329 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6332 [(set_attr "op_type" "RX")
6333 (set_attr "type" "jsr")
6334 (set_attr "atype" "mem")])
6338 ;;- Miscellaneous instructions.
6342 ; allocate stack instruction pattern(s).
6345 (define_expand "allocate_stack"
6347 (plus (reg 15) (match_operand 1 "general_operand" "")))
6348 (set (match_operand 0 "general_operand" "")
6353 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6354 rtx chain = gen_rtx (MEM, Pmode, stack);
6355 rtx temp = gen_reg_rtx (Pmode);
6357 emit_move_insn (temp, chain);
6360 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6362 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6364 emit_move_insn (chain, temp);
6366 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6372 ; setjmp/longjmp instruction pattern(s).
6375 (define_expand "builtin_setjmp_setup"
6376 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6380 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6381 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6383 emit_move_insn (base, basereg);
6387 (define_expand "builtin_setjmp_receiver"
6388 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6392 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6393 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6394 SYMBOL_REF_FLAG (got) = 1;
6396 emit_move_insn (gotreg, got);
6397 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6401 (define_expand "builtin_longjmp"
6402 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6406 /* The elements of the buffer are, in order: */
6407 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6408 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6409 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6410 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6411 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6412 rtx jmp = gen_rtx_REG (Pmode, 14);
6414 emit_move_insn (jmp, lab);
6415 emit_move_insn (basereg, base);
6416 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6417 emit_move_insn (hard_frame_pointer_rtx, fp);
6419 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6420 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6421 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6422 emit_indirect_jump (jmp);
6427 ;; These patterns say how to save and restore the stack pointer. We need not
6428 ;; save the stack pointer at function level since we are careful to
6429 ;; preserve the backchain. At block level, we have to restore the backchain
6430 ;; when we restore the stack pointer.
6432 ;; For nonlocal gotos, we must save both the stack pointer and its
6433 ;; backchain and restore both. Note that in the nonlocal case, the
6434 ;; save area is a memory location.
6436 (define_expand "save_stack_function"
6437 [(match_operand 0 "general_operand" "")
6438 (match_operand 1 "general_operand" "")]
6442 (define_expand "restore_stack_function"
6443 [(match_operand 0 "general_operand" "")
6444 (match_operand 1 "general_operand" "")]
6448 (define_expand "restore_stack_block"
6449 [(use (match_operand 0 "register_operand" ""))
6450 (set (match_dup 2) (match_dup 3))
6451 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6452 (set (match_dup 3) (match_dup 2))]
6456 operands[2] = gen_reg_rtx (Pmode);
6457 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6460 (define_expand "save_stack_nonlocal"
6461 [(match_operand 0 "memory_operand" "")
6462 (match_operand 1 "register_operand" "")]
6466 rtx temp = gen_reg_rtx (Pmode);
6468 /* Copy the backchain to the first word, sp to the second. */
6469 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6470 emit_move_insn (operand_subword (operands[0], 0, 0,
6471 TARGET_64BIT ? TImode : DImode),
6473 emit_move_insn (operand_subword (operands[0], 1, 0,
6474 TARGET_64BIT ? TImode : DImode),
6479 (define_expand "restore_stack_nonlocal"
6480 [(match_operand 0 "register_operand" "")
6481 (match_operand 1 "memory_operand" "")]
6485 rtx temp = gen_reg_rtx (Pmode);
6487 /* Restore the backchain from the first word, sp from the second. */
6488 emit_move_insn (temp,
6489 operand_subword (operands[1], 0, 0,
6490 TARGET_64BIT ? TImode : DImode));
6491 emit_move_insn (operands[0],
6492 operand_subword (operands[1], 1, 0,
6493 TARGET_64BIT ? TImode : DImode));
6494 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6500 ; nop instruction pattern(s).
6507 [(set_attr "op_type" "RR")])
6511 ; Special literal pool access instruction pattern(s).
6514 (define_insn "consttable_qi"
6515 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6519 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6522 [(set_attr "op_type" "NN")
6523 (set_attr "length" "1")])
6525 (define_insn "consttable_hi"
6526 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6530 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6533 [(set_attr "op_type" "NN")
6534 (set_attr "length" "2")])
6536 (define_insn "consttable_si"
6537 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6541 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6542 return \".long\\t%0\";
6544 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6547 [(set_attr "op_type" "NN")
6548 (set_attr "length" "4")])
6550 (define_insn "consttable_di"
6551 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6555 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6558 [(set_attr "op_type" "NN")
6559 (set_attr "length" "8")])
6561 (define_insn "consttable_sf"
6562 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6568 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6571 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6572 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6575 [(set_attr "op_type" "NN")
6576 (set_attr "length" "4")])
6578 (define_insn "consttable_df"
6579 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6585 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6588 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6589 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6592 [(set_attr "op_type" "NN")
6593 (set_attr "length" "8")])
6595 (define_insn "pool_start_31"
6596 [(unspec_volatile [(const_int 0)] 206)]
6599 [(set_attr "op_type" "NN")
6600 (set_attr "length" "2")])
6602 (define_insn "pool_end_31"
6603 [(unspec_volatile [(const_int 0)] 207)]
6606 [(set_attr "op_type" "NN")
6607 (set_attr "length" "2")])
6609 (define_insn "pool_start_64"
6610 [(unspec_volatile [(const_int 0)] 206)]
6612 ".section\\t.rodata\;.align\\t8"
6613 [(set_attr "op_type" "NN")
6614 (set_attr "length" "0")])
6616 (define_insn "pool_end_64"
6617 [(unspec_volatile [(const_int 0)] 207)]
6620 [(set_attr "op_type" "NN")
6621 (set_attr "length" "0")])
6623 (define_insn "reload_base"
6624 [(set (match_operand:SI 0 "register_operand" "=a")
6625 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6627 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6628 [(set_attr "op_type" "NN")
6629 (set_attr "type" "la")
6630 (set_attr "length" "6")])
6632 (define_insn "reload_base2"
6633 [(set (match_operand:SI 0 "register_operand" "=a")
6634 (unspec:SI [(label_ref (match_operand 1 "" ""))] 211))]
6637 [(set_attr "op_type" "NN")
6638 (set_attr "type" "la")
6639 (set_attr "length" "4")])
6643 ;; Insns related to generating the function prologue and epilogue.
6647 (define_expand "prologue"
6648 [(use (const_int 0))]
6652 s390_emit_prologue ();
6656 (define_expand "epilogue"
6657 [(use (const_int 1))]
6661 s390_emit_epilogue ();
6666 (define_insn "*return_si"
6668 (use (match_operand:SI 0 "register_operand" "a"))]
6671 [(set_attr "op_type" "RR")
6672 (set_attr "type" "jsr")
6673 (set_attr "atype" "mem")])
6675 (define_insn "*return_di"
6677 (use (match_operand:DI 0 "register_operand" "a"))]
6680 [(set_attr "op_type" "RR")
6681 (set_attr "type" "jsr")
6682 (set_attr "atype" "mem")])
6686 [(set (reg 13) (pc))
6687 (unspec_volatile [(const_int 0)] 200)]
6691 s390_output_constant_pool (asm_out_file);
6694 [(set_attr "op_type" "NN")
6695 (set_attr "type" "integer")])
6699 ;; Peephole optimization patterns.
6703 [(set (match_operand:SI 0 "memory_operand" "m")
6704 (match_operand:SI 1 "register_operand" "d"))
6711 [(set (match_operand:SI 0 "memory_operand" "m")
6712 (match_operand:SI 1 "register_operand" "d"))
6719 [(set (match_operand:SI 0 "register_operand" "")
6720 (match_operand:SI 1 "register_operand" ""))
6723 (plus:SI (match_dup 0)
6724 (match_operand:SI 2 "immediate_operand" "")))
6725 (clobber (reg:CC 33))])]
6726 "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
6727 REGNO (operands[1]) == STACK_POINTER_REGNUM ||
6728 REGNO (operands[0]) == BASE_REGISTER ||
6729 REGNO (operands[1]) == BASE_REGISTER) &&
6730 INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
6734 ; peepholes for fast char instructions
6738 ; [(set (match_operand:QI 0 "register_operand" "d")
6739 ; (match_operand:QI 1 "s_operand" "Q"))
6740 ; (set (match_operand:SI 2 "register_operand" "0")
6741 ; (zero_extend:SI (match_dup 0)))]
6742 ; "REGNO(operands[0]) == REGNO(operands[2])"
6743 ; "icm\\t%0,8,%1\;srl\\t%0,24")
6746 ; [(set (match_operand:QI 0 "register_operand" "d")
6747 ; (match_operand:QI 1 "s_operand" "Q"))
6748 ; (set (match_operand:SI 2 "register_operand" "0")
6749 ; (sign_extend:SI (match_dup 0)))]
6750 ; "REGNO(operands[0]) == REGNO(operands[2])"
6751 ; "icm\\t%0,8,%1\;sra\\t%0,24")
6754 [(set (match_operand:QI 0 "register_operand" "d")
6755 (match_operand:QI 1 "immediate_operand" "J"))
6756 (set (match_operand:SI 2 "register_operand" "0" )
6757 (sign_extend:SI (match_dup 0) ) )]
6758 "REGNO(operands[0]) == REGNO(operands[2])"
6762 ; peepholes for fast short instructions
6766 ; [(set (match_operand:HI 0 "register_operand" "d")
6767 ; (match_operand:HI 1 "s_operand" "Q"))
6768 ; (set (match_operand:SI 2 "register_operand" "0" )
6769 ; (zero_extend:SI (match_dup 0)))]
6770 ; "REGNO(operands[0]) == REGNO(operands[2])"
6771 ; "icm\\t%0,12,%1\;srl\\t%0,16")
6774 [(set (match_operand:HI 0 "register_operand" "d")
6775 (match_operand:HI 1 "memory_operand" "m"))
6776 (set (match_operand:SI 2 "register_operand" "0" )
6777 (sign_extend:SI (match_dup 0)))]
6778 "REGNO(operands[0]) == REGNO(operands[2])"
6782 [(set (match_operand:HI 0 "register_operand" "d")
6783 (match_operand:HI 1 "immediate_operand" "K"))
6784 (set (match_operand:SI 2 "register_operand" "0" )
6785 (sign_extend:SI (match_dup 0) ) )]
6786 "REGNO(operands[0]) == REGNO(operands[2])"
6790 ; peepholes for divide instructions
6794 [(set (match_operand:DI 0 "register_operand" "d")
6795 (match_operand:DI 1 "memory_operand" "m"))
6797 (lshiftrt:DI (match_dup 0)
6798 (match_operand:SI 2 "immediate_operand" "J")))
6800 (div:SI (match_dup 0)
6801 (match_operand:SI 3 "nonimmediate_operand" "g")))
6807 output_asm_insn (\"l\\t%0,%1\", operands);
6808 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6810 if (REG_P (operands[3]))
6811 output_asm_insn (\"dr\\t%0,%3\", operands);
6813 output_asm_insn (\"d\\t%0,%3\", operands);
6815 return \"st\\t%N0,%N1\";
6819 [(set (match_operand:DI 0 "register_operand" "d")
6820 (match_operand:DI 1 "memory_operand" "m"))
6822 (lshiftrt:DI (match_dup 0)
6823 (match_operand:SI 2 "immediate_operand" "J")))
6825 (mod:SI (match_dup 0)
6826 (match_operand:SI 3 "nonimmediate_operand" "g")))
6832 output_asm_insn (\"l\\t%0,%1\", operands);
6833 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6835 if (REG_P (operands[3]))
6836 output_asm_insn (\"dr\\t%0,%3\", operands);
6838 output_asm_insn (\"d\\t%0,%3\", operands);
6840 return \"st\\t%0,%1\";