1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; I -- An 8-bit constant (0..255).
31 ;; J -- A 12-bit constant (0..4095).
32 ;; K -- A 16-bit constant (-32768..32767).
33 ;; L -- Value appropriate as displacement.
34 ;; (0..4095) for short displacement
35 ;; (-524288..524287) for long displacement
36 ;; M -- Constant integer with a value of 0x7fffffff.
37 ;; N -- Multiple letter constraint followed by 4 parameter letters.
38 ;; 0..9,x: number of the part counting from most to least significant
39 ;; H,Q: mode of the part
40 ;; D,S,H: mode of the containing operand
41 ;; 0,F: value of the other parts (F - all bits set)
43 ;; The constraint matches if the specified part of a constant
44 ;; has a value different from its other parts. If the letter x
45 ;; is specified instead of a part number, the constraint matches
46 ;; if there is any single part with non-default value.
47 ;; Q -- Memory reference without index register and with short displacement.
48 ;; R -- Memory reference with index register and short displacement.
49 ;; S -- Memory reference without index register but with long displacement.
50 ;; T -- Memory reference with index register and long displacement.
51 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
52 ;; Offsettable memory reference of type specified by second letter.
53 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
54 ;; Memory reference of the type specified by second letter that
55 ;; does *not* refer to a literal pool entry.
56 ;; U -- Pointer with short displacement.
57 ;; W -- Pointer with long displacement.
58 ;; Y -- Shift count operand.
60 ;; Special formats used for outputting 390 instructions.
62 ;; %C: print opcode suffix for branch condition.
63 ;; %D: print opcode suffix for inverse branch condition.
64 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
65 ;; %O: print only the displacement of a memory reference.
66 ;; %R: print only the base register of a memory reference.
67 ;; %S: print S-type memory reference (base+displacement).
68 ;; %N: print the second word of a DImode operand.
69 ;; %M: print the second word of a TImode operand.
71 ;; %b: print integer X as if it's an unsigned byte.
72 ;; %x: print integer X as if it's an unsigned word.
73 ;; %h: print integer X as if it's a signed word.
74 ;; %i: print the first nonzero HImode part of X
75 ;; %j: print the first HImode part unequal to 0xffff of X
78 ;; We have a special constraint for pattern matching.
80 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
93 ; GOT/PLT and lt-relative accesses
94 (UNSPEC_LTREL_OFFSET 100)
95 (UNSPEC_LTREL_BASE 101)
103 (UNSPEC_RELOAD_BASE 210)
104 (UNSPEC_MAIN_BASE 211)
109 ; TLS relocation specifiers
114 (UNSPEC_GOTNTPOFF 504)
115 (UNSPEC_INDNTPOFF 505)
118 (UNSPEC_TLSLDM_NTPOFF 511)
119 (UNSPEC_TLS_LOAD 512)
126 ;; UNSPEC_VOLATILE usage
134 (UNSPECV_TPF_PROLOGUE 20)
135 (UNSPECV_TPF_EPILOGUE 21)
139 (UNSPECV_POOL_SECTION 201)
140 (UNSPECV_POOL_ALIGN 202)
141 (UNSPECV_POOL_ENTRY 203)
142 (UNSPECV_MAIN_POOL 300)
154 ; Sibling call register.
156 ; Literal pool base register.
158 ; Return address register.
160 ; Condition code register.
162 ; Thread local storage pointer register.
167 ;; Instruction operand type as used in the Principles of Operation.
168 ;; Used to determine defaults for length and other attribute values.
170 (define_attr "op_type"
171 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
174 ;; Instruction type attribute used for scheduling.
176 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
178 imulhi,imulsi,imuldi,
179 branch,jsr,fsimpdf,fsimpsf,
180 floaddf,floadsf,fstoredf,fstoresf,
181 fmuldf,fmulsf,fdivdf,fdivsf,
182 ftoi,itof,fsqrtdf,fsqrtsf,
184 (cond [(eq_attr "op_type" "NN") (const_string "other")
185 (eq_attr "op_type" "SS") (const_string "cs")]
186 (const_string "integer")))
188 ;; Another attribute used for scheduling purposes:
189 ;; agen: Instruction uses the address generation unit
190 ;; reg: Instruction does not use the agen unit
192 (define_attr "atype" "agen,reg"
193 (cond [(eq_attr "op_type" "E") (const_string "reg")
194 (eq_attr "op_type" "RR") (const_string "reg")
195 (eq_attr "op_type" "RX") (const_string "agen")
196 (eq_attr "op_type" "RI") (const_string "reg")
197 (eq_attr "op_type" "RRE") (const_string "reg")
198 (eq_attr "op_type" "RS") (const_string "agen")
199 (eq_attr "op_type" "RSI") (const_string "agen")
200 (eq_attr "op_type" "S") (const_string "agen")
201 (eq_attr "op_type" "SI") (const_string "agen")
202 (eq_attr "op_type" "SS") (const_string "agen")
203 (eq_attr "op_type" "SSE") (const_string "agen")
204 (eq_attr "op_type" "RXE") (const_string "agen")
205 (eq_attr "op_type" "RSE") (const_string "agen")
206 (eq_attr "op_type" "RIL") (const_string "agen")
207 (eq_attr "op_type" "RXY") (const_string "agen")
208 (eq_attr "op_type" "RSY") (const_string "agen")
209 (eq_attr "op_type" "SIY") (const_string "agen")]
210 (const_string "agen")))
214 (define_attr "length" ""
215 (cond [(eq_attr "op_type" "E") (const_int 2)
216 (eq_attr "op_type" "RR") (const_int 2)
217 (eq_attr "op_type" "RX") (const_int 4)
218 (eq_attr "op_type" "RI") (const_int 4)
219 (eq_attr "op_type" "RRE") (const_int 4)
220 (eq_attr "op_type" "RS") (const_int 4)
221 (eq_attr "op_type" "RSI") (const_int 4)
222 (eq_attr "op_type" "S") (const_int 4)
223 (eq_attr "op_type" "SI") (const_int 4)
224 (eq_attr "op_type" "SS") (const_int 6)
225 (eq_attr "op_type" "SSE") (const_int 6)
226 (eq_attr "op_type" "RXE") (const_int 6)
227 (eq_attr "op_type" "RSE") (const_int 6)
228 (eq_attr "op_type" "RIL") (const_int 6)
229 (eq_attr "op_type" "RXY") (const_int 6)
230 (eq_attr "op_type" "RSY") (const_int 6)
231 (eq_attr "op_type" "SIY") (const_int 6)]
235 ;; Processor type. This attribute must exactly match the processor_type
236 ;; enumeration in s390.h. The current machine description does not
237 ;; distinguish between g5 and g6, but there are differences between the two
238 ;; CPUs could in theory be modeled.
240 (define_attr "cpu" "g5,g6,z900,z990"
241 (const (symbol_ref "s390_tune")))
243 ;; Pipeline description for z900. For lack of anything better,
244 ;; this description is also used for the g5 and g6.
247 ;; Pipeline description for z990.
251 (include "predicates.md")
256 ;; This mode macro allows DF and SF patterns to be generated from the
258 (define_mode_macro FPR [DF SF])
260 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
261 ;; from the same template.
262 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
263 (define_mode_macro DSI [DI SI])
265 ;; This mode macro allows :P to be used for patterns that operate on
266 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
267 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
269 ;; This mode macro allows the QI and HI patterns to be defined from
270 ;; the same template.
271 (define_mode_macro HQI [HI QI])
273 ;; This mode macro allows the integer patterns to be defined from the
275 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
277 ;; This macro allows to unify all 'bCOND' expander patterns.
278 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
279 ordered uneq unlt ungt unle unge ltgt])
281 ;; This macro allows to unify all 'sCOND' patterns.
282 (define_code_macro SCOND [ltu gtu leu geu])
284 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
285 ;; the same template.
286 (define_code_macro SHIFT [ashift lshiftrt])
289 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
290 ;; and "ltebr" in SFmode.
291 (define_mode_attr de [(DF "d") (SF "e")])
293 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
294 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
295 (define_mode_attr dee [(DF "d") (SF "ee")])
297 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
298 ;; 'ashift' and "srdl" in 'lshiftrt'.
299 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
301 ;; In SHIFT templates, this attribute holds the correct standard name for the
302 ;; pattern itself and the corresponding function calls.
303 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
305 ;; This attribute handles differences in the instruction 'type' and will result
306 ;; in "RRE" for DImode and "RR" for SImode.
307 (define_mode_attr E [(DI "E") (SI "")])
309 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
310 ;; and "lcr" in SImode.
311 (define_mode_attr g [(DI "g") (SI "")])
313 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
314 ;; and "cfdbr" in SImode.
315 (define_mode_attr gf [(DI "g") (SI "f")])
317 ;; ICM mask required to load MODE value into the highest subreg
318 ;; of a SImode register.
319 (define_mode_attr icm_hi [(HI "12") (QI "8")])
321 ;; ICM mask required to load MODE value into the lowest subreg
322 ;; of a SImode register.
323 (define_mode_attr icm_lo [(HI "3") (QI "1")])
325 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
326 ;; HImode and "llgc" in QImode.
327 (define_mode_attr hc [(HI "h") (QI "c")])
329 ;; Maximum unsigned integer that fits in MODE.
330 (define_mode_attr max_uint [(HI "65535") (QI "255")])
334 ;;- Compare instructions.
337 (define_expand "cmp<mode>"
338 [(set (reg:CC CC_REGNUM)
339 (compare:CC (match_operand:GPR 0 "register_operand" "")
340 (match_operand:GPR 1 "general_operand" "")))]
343 s390_compare_op0 = operands[0];
344 s390_compare_op1 = operands[1];
348 (define_expand "cmp<mode>"
349 [(set (reg:CC CC_REGNUM)
350 (compare:CC (match_operand:FPR 0 "register_operand" "")
351 (match_operand:FPR 1 "general_operand" "")))]
354 s390_compare_op0 = operands[0];
355 s390_compare_op1 = operands[1];
360 ; Test-under-Mask instructions
362 (define_insn "*tmqi_mem"
363 [(set (reg CC_REGNUM)
364 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
365 (match_operand:QI 1 "immediate_operand" "n,n"))
366 (match_operand:QI 2 "immediate_operand" "n,n")))]
367 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
371 [(set_attr "op_type" "SI,SIY")])
373 (define_insn "*tmdi_reg"
374 [(set (reg CC_REGNUM)
375 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
376 (match_operand:DI 1 "immediate_operand"
377 "N0HD0,N1HD0,N2HD0,N3HD0"))
378 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
380 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
381 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
387 [(set_attr "op_type" "RI")])
389 (define_insn "*tmsi_reg"
390 [(set (reg CC_REGNUM)
391 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
392 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
393 (match_operand:SI 2 "immediate_operand" "n,n")))]
394 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
395 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
399 [(set_attr "op_type" "RI")])
401 (define_insn "*tm<mode>_full"
402 [(set (reg CC_REGNUM)
403 (compare (match_operand:HQI 0 "register_operand" "d")
404 (match_operand:HQI 1 "immediate_operand" "n")))]
405 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
407 [(set_attr "op_type" "RI")])
410 ; Load-and-Test instructions
412 (define_insn "*tstdi_sign"
413 [(set (reg CC_REGNUM)
414 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
415 (const_int 32)) (const_int 32))
416 (match_operand:DI 1 "const0_operand" "")))
417 (set (match_operand:DI 2 "register_operand" "=d")
418 (sign_extend:DI (match_dup 0)))]
419 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
421 [(set_attr "op_type" "RRE")])
423 (define_insn "*tstdi"
424 [(set (reg CC_REGNUM)
425 (compare (match_operand:DI 0 "register_operand" "d")
426 (match_operand:DI 1 "const0_operand" "")))
427 (set (match_operand:DI 2 "register_operand" "=d")
429 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
431 [(set_attr "op_type" "RRE")])
433 (define_insn "*tstdi_cconly"
434 [(set (reg CC_REGNUM)
435 (compare (match_operand:DI 0 "register_operand" "d")
436 (match_operand:DI 1 "const0_operand" "")))]
437 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
439 [(set_attr "op_type" "RRE")])
441 (define_insn "*tstdi_cconly_31"
442 [(set (reg CC_REGNUM)
443 (compare (match_operand:DI 0 "register_operand" "d")
444 (match_operand:DI 1 "const0_operand" "")))]
445 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
447 [(set_attr "op_type" "RS")
448 (set_attr "atype" "reg")])
451 (define_insn "*tstsi"
452 [(set (reg CC_REGNUM)
453 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
454 (match_operand:SI 1 "const0_operand" "")))
455 (set (match_operand:SI 2 "register_operand" "=d,d,d")
457 "s390_match_ccmode(insn, CCSmode)"
462 [(set_attr "op_type" "RR,RS,RSY")])
464 (define_insn "*tstsi_cconly"
465 [(set (reg CC_REGNUM)
466 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
467 (match_operand:SI 1 "const0_operand" "")))
468 (clobber (match_scratch:SI 2 "=X,d,d"))]
469 "s390_match_ccmode(insn, CCSmode)"
474 [(set_attr "op_type" "RR,RS,RSY")])
476 (define_insn "*tstsi_cconly2"
477 [(set (reg CC_REGNUM)
478 (compare (match_operand:SI 0 "register_operand" "d")
479 (match_operand:SI 1 "const0_operand" "")))]
480 "s390_match_ccmode(insn, CCSmode)"
482 [(set_attr "op_type" "RR")])
484 (define_insn "*tst<mode>CCT"
485 [(set (reg CC_REGNUM)
486 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
487 (match_operand:HQI 1 "const0_operand" "")))
488 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
490 "s390_match_ccmode(insn, CCTmode)"
493 icmy\t%2,<icm_lo>,%S0
495 [(set_attr "op_type" "RS,RSY,RI")])
497 (define_insn "*tsthiCCT_cconly"
498 [(set (reg CC_REGNUM)
499 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
500 (match_operand:HI 1 "const0_operand" "")))
501 (clobber (match_scratch:HI 2 "=d,d,X"))]
502 "s390_match_ccmode(insn, CCTmode)"
507 [(set_attr "op_type" "RS,RSY,RI")])
509 (define_insn "*tstqiCCT_cconly"
510 [(set (reg CC_REGNUM)
511 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
512 (match_operand:QI 1 "const0_operand" "")))]
513 "s390_match_ccmode(insn, CCTmode)"
518 [(set_attr "op_type" "SI,SIY,RI")])
520 (define_insn "*tst<mode>"
521 [(set (reg CC_REGNUM)
522 (compare (match_operand:HQI 0 "s_operand" "Q,S")
523 (match_operand:HQI 1 "const0_operand" "")))
524 (set (match_operand:HQI 2 "register_operand" "=d,d")
526 "s390_match_ccmode(insn, CCSmode)"
529 icmy\t%2,<icm_lo>,%S0"
530 [(set_attr "op_type" "RS,RSY")])
532 (define_insn "*tst<mode>_cconly"
533 [(set (reg CC_REGNUM)
534 (compare (match_operand:HQI 0 "s_operand" "Q,S")
535 (match_operand:HQI 1 "const0_operand" "")))
536 (clobber (match_scratch:HQI 2 "=d,d"))]
537 "s390_match_ccmode(insn, CCSmode)"
540 icmy\t%2,<icm_lo>,%S0"
541 [(set_attr "op_type" "RS,RSY")])
544 ; Compare (equality) instructions
546 (define_insn "*cmpdi_cct"
547 [(set (reg CC_REGNUM)
548 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
549 (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
550 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
556 [(set_attr "op_type" "RRE,RI,RXY,SS")])
558 (define_insn "*cmpsi_cct"
559 [(set (reg CC_REGNUM)
560 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
561 (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
562 "s390_match_ccmode (insn, CCTmode)"
569 [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
572 ; Compare (signed) instructions
574 (define_insn "*cmpdi_ccs_sign"
575 [(set (reg CC_REGNUM)
576 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
577 (match_operand:DI 0 "register_operand" "d,d")))]
578 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
582 [(set_attr "op_type" "RRE,RXY")])
584 (define_insn "*cmpdi_ccs"
585 [(set (reg CC_REGNUM)
586 (compare (match_operand:DI 0 "register_operand" "d,d,d")
587 (match_operand:DI 1 "general_operand" "d,K,m")))]
588 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
593 [(set_attr "op_type" "RRE,RI,RXY")])
595 (define_insn "*cmpsi_ccs_sign"
596 [(set (reg CC_REGNUM)
597 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
598 (match_operand:SI 0 "register_operand" "d,d")))]
599 "s390_match_ccmode(insn, CCSRmode)"
603 [(set_attr "op_type" "RX,RXY")])
605 (define_insn "*cmpsi_ccs"
606 [(set (reg CC_REGNUM)
607 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
608 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
609 "s390_match_ccmode(insn, CCSmode)"
615 [(set_attr "op_type" "RR,RI,RX,RXY")])
618 ; Compare (unsigned) instructions
620 (define_insn "*cmpdi_ccu_zero"
621 [(set (reg CC_REGNUM)
622 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
623 (match_operand:DI 0 "register_operand" "d,d")))]
624 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
628 [(set_attr "op_type" "RRE,RXY")])
630 (define_insn "*cmpdi_ccu"
631 [(set (reg CC_REGNUM)
632 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
633 (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
634 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
640 [(set_attr "op_type" "RRE,RXY,SS,SS")])
642 (define_insn "*cmpsi_ccu"
643 [(set (reg CC_REGNUM)
644 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
645 (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
646 "s390_match_ccmode (insn, CCUmode)"
653 [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
655 (define_insn "*cmphi_ccu"
656 [(set (reg CC_REGNUM)
657 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
658 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
659 "s390_match_ccmode (insn, CCUmode)
660 && !register_operand (operands[1], HImode)"
666 [(set_attr "op_type" "RS,RSY,SS,SS")])
668 (define_insn "*cmpqi_ccu"
669 [(set (reg CC_REGNUM)
670 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
671 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
672 "s390_match_ccmode (insn, CCUmode)
673 && !register_operand (operands[1], QImode)"
681 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
684 ; Block compare (CLC) instruction patterns.
687 [(set (reg CC_REGNUM)
688 (compare (match_operand:BLK 0 "memory_operand" "Q")
689 (match_operand:BLK 1 "memory_operand" "Q")))
690 (use (match_operand 2 "const_int_operand" "n"))]
691 "s390_match_ccmode (insn, CCUmode)
692 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
693 "clc\t%O0(%2,%R0),%S1"
694 [(set_attr "op_type" "SS")])
697 [(set (reg CC_REGNUM)
698 (compare (match_operand 0 "memory_operand" "")
699 (match_operand 1 "memory_operand" "")))]
701 && s390_match_ccmode (insn, CCUmode)
702 && GET_MODE (operands[0]) == GET_MODE (operands[1])
703 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
705 [(set (match_dup 0) (match_dup 1))
706 (use (match_dup 2))])]
708 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
709 operands[0] = adjust_address (operands[0], BLKmode, 0);
710 operands[1] = adjust_address (operands[1], BLKmode, 0);
712 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
713 operands[0], operands[1]);
714 operands[0] = SET_DEST (PATTERN (curr_insn));
718 ; (DF|SF) instructions
720 (define_insn "*cmp<mode>_ccs_0"
721 [(set (reg CC_REGNUM)
722 (compare (match_operand:FPR 0 "register_operand" "f")
723 (match_operand:FPR 1 "const0_operand" "")))]
724 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
726 [(set_attr "op_type" "RRE")
727 (set_attr "type" "fsimp<mode>")])
729 (define_insn "*cmp<mode>_ccs_0_ibm"
730 [(set (reg CC_REGNUM)
731 (compare (match_operand:FPR 0 "register_operand" "f")
732 (match_operand:FPR 1 "const0_operand" "")))]
733 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
735 [(set_attr "op_type" "RR")
736 (set_attr "type" "fsimp<mode>")])
738 (define_insn "*cmp<mode>_ccs"
739 [(set (reg CC_REGNUM)
740 (compare (match_operand:FPR 0 "register_operand" "f,f")
741 (match_operand:FPR 1 "general_operand" "f,R")))]
742 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
746 [(set_attr "op_type" "RRE,RXE")
747 (set_attr "type" "fsimp<mode>")])
749 (define_insn "*cmp<mode>_ccs_ibm"
750 [(set (reg CC_REGNUM)
751 (compare (match_operand:FPR 0 "register_operand" "f,f")
752 (match_operand:FPR 1 "general_operand" "f,R")))]
753 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
757 [(set_attr "op_type" "RR,RX")
758 (set_attr "type" "fsimp<mode>")])
762 ;;- Move instructions.
766 ; movti instruction pattern(s).
770 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
771 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
779 [(set_attr "op_type" "RSY,RSY,*,*,SS")
780 (set_attr "type" "lm,stm,*,*,*")])
783 [(set (match_operand:TI 0 "nonimmediate_operand" "")
784 (match_operand:TI 1 "general_operand" ""))]
785 "TARGET_64BIT && reload_completed
786 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
787 [(set (match_dup 2) (match_dup 4))
788 (set (match_dup 3) (match_dup 5))]
790 operands[2] = operand_subword (operands[0], 0, 0, TImode);
791 operands[3] = operand_subword (operands[0], 1, 0, TImode);
792 operands[4] = operand_subword (operands[1], 0, 0, TImode);
793 operands[5] = operand_subword (operands[1], 1, 0, TImode);
797 [(set (match_operand:TI 0 "nonimmediate_operand" "")
798 (match_operand:TI 1 "general_operand" ""))]
799 "TARGET_64BIT && reload_completed
800 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
801 [(set (match_dup 2) (match_dup 4))
802 (set (match_dup 3) (match_dup 5))]
804 operands[2] = operand_subword (operands[0], 1, 0, TImode);
805 operands[3] = operand_subword (operands[0], 0, 0, TImode);
806 operands[4] = operand_subword (operands[1], 1, 0, TImode);
807 operands[5] = operand_subword (operands[1], 0, 0, TImode);
811 [(set (match_operand:TI 0 "register_operand" "")
812 (match_operand:TI 1 "memory_operand" ""))]
813 "TARGET_64BIT && reload_completed
814 && !s_operand (operands[1], VOIDmode)"
815 [(set (match_dup 0) (match_dup 1))]
817 rtx addr = operand_subword (operands[0], 1, 0, TImode);
818 s390_load_address (addr, XEXP (operands[1], 0));
819 operands[1] = replace_equiv_address (operands[1], addr);
822 (define_expand "reload_outti"
823 [(parallel [(match_operand:TI 0 "" "")
824 (match_operand:TI 1 "register_operand" "d")
825 (match_operand:DI 2 "register_operand" "=&a")])]
828 gcc_assert (MEM_P (operands[0]));
829 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
830 operands[0] = replace_equiv_address (operands[0], operands[2]);
831 emit_move_insn (operands[0], operands[1]);
836 ; movdi instruction pattern(s).
839 (define_expand "movdi"
840 [(set (match_operand:DI 0 "general_operand" "")
841 (match_operand:DI 1 "general_operand" ""))]
844 /* Handle symbolic constants. */
845 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
846 emit_symbolic_move (operands);
849 (define_insn "*movdi_larl"
850 [(set (match_operand:DI 0 "register_operand" "=d")
851 (match_operand:DI 1 "larl_operand" "X"))]
853 && !FP_REG_P (operands[0])"
855 [(set_attr "op_type" "RIL")
856 (set_attr "type" "larl")])
858 (define_insn "*movdi_64"
859 [(set (match_operand:DI 0 "nonimmediate_operand"
860 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
861 (match_operand:DI 1 "general_operand"
862 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
884 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
885 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
886 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
887 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
890 [(set (match_operand:DI 0 "register_operand" "")
891 (match_operand:DI 1 "register_operand" ""))]
892 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
893 [(set (match_dup 2) (match_dup 3))
894 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
895 (set (strict_low_part (match_dup 2)) (match_dup 4))]
896 "operands[2] = gen_lowpart (SImode, operands[0]);
897 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
900 [(set (match_operand:DI 0 "register_operand" "")
901 (match_operand:DI 1 "register_operand" ""))]
902 "TARGET_64BIT && ACCESS_REG_P (operands[0])
903 && dead_or_set_p (insn, operands[1])"
904 [(set (match_dup 3) (match_dup 2))
905 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
906 (set (match_dup 4) (match_dup 2))]
907 "operands[2] = gen_lowpart (SImode, operands[1]);
908 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
911 [(set (match_operand:DI 0 "register_operand" "")
912 (match_operand:DI 1 "register_operand" ""))]
913 "TARGET_64BIT && ACCESS_REG_P (operands[0])
914 && !dead_or_set_p (insn, operands[1])"
915 [(set (match_dup 3) (match_dup 2))
916 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
917 (set (match_dup 4) (match_dup 2))
918 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
919 "operands[2] = gen_lowpart (SImode, operands[1]);
920 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
922 (define_insn "*movdi_31"
923 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
924 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
937 [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
938 (set_attr "type" "lm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
941 [(set (match_operand:DI 0 "nonimmediate_operand" "")
942 (match_operand:DI 1 "general_operand" ""))]
943 "!TARGET_64BIT && reload_completed
944 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
945 [(set (match_dup 2) (match_dup 4))
946 (set (match_dup 3) (match_dup 5))]
948 operands[2] = operand_subword (operands[0], 0, 0, DImode);
949 operands[3] = operand_subword (operands[0], 1, 0, DImode);
950 operands[4] = operand_subword (operands[1], 0, 0, DImode);
951 operands[5] = operand_subword (operands[1], 1, 0, DImode);
955 [(set (match_operand:DI 0 "nonimmediate_operand" "")
956 (match_operand:DI 1 "general_operand" ""))]
957 "!TARGET_64BIT && reload_completed
958 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
959 [(set (match_dup 2) (match_dup 4))
960 (set (match_dup 3) (match_dup 5))]
962 operands[2] = operand_subword (operands[0], 1, 0, DImode);
963 operands[3] = operand_subword (operands[0], 0, 0, DImode);
964 operands[4] = operand_subword (operands[1], 1, 0, DImode);
965 operands[5] = operand_subword (operands[1], 0, 0, DImode);
969 [(set (match_operand:DI 0 "register_operand" "")
970 (match_operand:DI 1 "memory_operand" ""))]
971 "!TARGET_64BIT && reload_completed
972 && !FP_REG_P (operands[0])
973 && !s_operand (operands[1], VOIDmode)"
974 [(set (match_dup 0) (match_dup 1))]
976 rtx addr = operand_subword (operands[0], 1, 0, DImode);
977 s390_load_address (addr, XEXP (operands[1], 0));
978 operands[1] = replace_equiv_address (operands[1], addr);
981 (define_expand "reload_outdi"
982 [(parallel [(match_operand:DI 0 "" "")
983 (match_operand:DI 1 "register_operand" "d")
984 (match_operand:SI 2 "register_operand" "=&a")])]
987 gcc_assert (MEM_P (operands[0]));
988 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
989 operands[0] = replace_equiv_address (operands[0], operands[2]);
990 emit_move_insn (operands[0], operands[1]);
995 [(set (match_operand:DI 0 "register_operand" "")
996 (mem:DI (match_operand 1 "address_operand" "")))]
998 && !FP_REG_P (operands[0])
999 && GET_CODE (operands[1]) == SYMBOL_REF
1000 && CONSTANT_POOL_ADDRESS_P (operands[1])
1001 && get_pool_mode (operands[1]) == DImode
1002 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1003 [(set (match_dup 0) (match_dup 2))]
1004 "operands[2] = get_pool_constant (operands[1]);")
1006 (define_insn "*la_64"
1007 [(set (match_operand:DI 0 "register_operand" "=d,d")
1008 (match_operand:QI 1 "address_operand" "U,W"))]
1013 [(set_attr "op_type" "RX,RXY")
1014 (set_attr "type" "la")])
1018 [(set (match_operand:DI 0 "register_operand" "")
1019 (match_operand:QI 1 "address_operand" ""))
1020 (clobber (reg:CC CC_REGNUM))])]
1022 && preferred_la_operand_p (operands[1], const0_rtx)"
1023 [(set (match_dup 0) (match_dup 1))]
1027 [(set (match_operand:DI 0 "register_operand" "")
1028 (match_operand:DI 1 "register_operand" ""))
1031 (plus:DI (match_dup 0)
1032 (match_operand:DI 2 "nonmemory_operand" "")))
1033 (clobber (reg:CC CC_REGNUM))])]
1035 && !reg_overlap_mentioned_p (operands[0], operands[2])
1036 && preferred_la_operand_p (operands[1], operands[2])"
1037 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1040 (define_expand "reload_indi"
1041 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1042 (match_operand:DI 1 "s390_plus_operand" "")
1043 (match_operand:DI 2 "register_operand" "=&a")])]
1046 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1051 ; movsi instruction pattern(s).
1054 (define_expand "movsi"
1055 [(set (match_operand:SI 0 "general_operand" "")
1056 (match_operand:SI 1 "general_operand" ""))]
1059 /* Handle symbolic constants. */
1060 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1061 emit_symbolic_move (operands);
1064 (define_insn "*movsi_larl"
1065 [(set (match_operand:SI 0 "register_operand" "=d")
1066 (match_operand:SI 1 "larl_operand" "X"))]
1067 "!TARGET_64BIT && TARGET_CPU_ZARCH
1068 && !FP_REG_P (operands[0])"
1070 [(set_attr "op_type" "RIL")
1071 (set_attr "type" "larl")])
1073 (define_insn "*movsi_zarch"
1074 [(set (match_operand:SI 0 "nonimmediate_operand"
1075 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1076 (match_operand:SI 1 "general_operand"
1077 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1099 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
1100 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1101 (set_attr "type" "*,*,*,la,lr,load,load,store,store,
1102 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1104 (define_insn "*movsi_esa"
1105 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1106 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1121 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1122 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1125 [(set (match_operand:SI 0 "register_operand" "")
1126 (mem:SI (match_operand 1 "address_operand" "")))]
1127 "!FP_REG_P (operands[0])
1128 && GET_CODE (operands[1]) == SYMBOL_REF
1129 && CONSTANT_POOL_ADDRESS_P (operands[1])
1130 && get_pool_mode (operands[1]) == SImode
1131 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1132 [(set (match_dup 0) (match_dup 2))]
1133 "operands[2] = get_pool_constant (operands[1]);")
1135 (define_insn "*la_31"
1136 [(set (match_operand:SI 0 "register_operand" "=d,d")
1137 (match_operand:QI 1 "address_operand" "U,W"))]
1138 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1142 [(set_attr "op_type" "RX,RXY")
1143 (set_attr "type" "la")])
1147 [(set (match_operand:SI 0 "register_operand" "")
1148 (match_operand:QI 1 "address_operand" ""))
1149 (clobber (reg:CC CC_REGNUM))])]
1151 && preferred_la_operand_p (operands[1], const0_rtx)"
1152 [(set (match_dup 0) (match_dup 1))]
1156 [(set (match_operand:SI 0 "register_operand" "")
1157 (match_operand:SI 1 "register_operand" ""))
1160 (plus:SI (match_dup 0)
1161 (match_operand:SI 2 "nonmemory_operand" "")))
1162 (clobber (reg:CC CC_REGNUM))])]
1164 && !reg_overlap_mentioned_p (operands[0], operands[2])
1165 && preferred_la_operand_p (operands[1], operands[2])"
1166 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1169 (define_insn "*la_31_and"
1170 [(set (match_operand:SI 0 "register_operand" "=d,d")
1171 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1172 (const_int 2147483647)))]
1177 [(set_attr "op_type" "RX,RXY")
1178 (set_attr "type" "la")])
1180 (define_insn_and_split "*la_31_and_cc"
1181 [(set (match_operand:SI 0 "register_operand" "=d")
1182 (and:SI (match_operand:QI 1 "address_operand" "p")
1183 (const_int 2147483647)))
1184 (clobber (reg:CC CC_REGNUM))]
1187 "&& reload_completed"
1189 (and:SI (match_dup 1) (const_int 2147483647)))]
1191 [(set_attr "op_type" "RX")
1192 (set_attr "type" "la")])
1194 (define_insn "force_la_31"
1195 [(set (match_operand:SI 0 "register_operand" "=d,d")
1196 (match_operand:QI 1 "address_operand" "U,W"))
1197 (use (const_int 0))]
1202 [(set_attr "op_type" "RX")
1203 (set_attr "type" "la")])
1205 (define_expand "reload_insi"
1206 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1207 (match_operand:SI 1 "s390_plus_operand" "")
1208 (match_operand:SI 2 "register_operand" "=&a")])]
1211 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1216 ; movhi instruction pattern(s).
1219 (define_expand "movhi"
1220 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1221 (match_operand:HI 1 "general_operand" ""))]
1224 /* Make it explicit that loading a register from memory
1225 always sign-extends (at least) to SImode. */
1226 if (optimize && !no_new_pseudos
1227 && register_operand (operands[0], VOIDmode)
1228 && GET_CODE (operands[1]) == MEM)
1230 rtx tmp = gen_reg_rtx (SImode);
1231 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1232 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1233 operands[1] = gen_lowpart (HImode, tmp);
1237 (define_insn "*movhi"
1238 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1239 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1249 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1250 (set_attr "type" "lr,*,*,*,store,store,*")])
1253 [(set (match_operand:HI 0 "register_operand" "")
1254 (mem:HI (match_operand 1 "address_operand" "")))]
1255 "GET_CODE (operands[1]) == SYMBOL_REF
1256 && CONSTANT_POOL_ADDRESS_P (operands[1])
1257 && get_pool_mode (operands[1]) == HImode
1258 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1259 [(set (match_dup 0) (match_dup 2))]
1260 "operands[2] = get_pool_constant (operands[1]);")
1263 ; movqi instruction pattern(s).
1266 (define_expand "movqi"
1267 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1268 (match_operand:QI 1 "general_operand" ""))]
1271 /* On z/Architecture, zero-extending from memory to register
1272 is just as fast as a QImode load. */
1273 if (TARGET_ZARCH && optimize && !no_new_pseudos
1274 && register_operand (operands[0], VOIDmode)
1275 && GET_CODE (operands[1]) == MEM)
1277 rtx tmp = gen_reg_rtx (word_mode);
1278 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1279 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1280 operands[1] = gen_lowpart (QImode, tmp);
1284 (define_insn "*movqi"
1285 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1286 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1298 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1299 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1302 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1303 (mem:QI (match_operand 1 "address_operand" "")))]
1304 "GET_CODE (operands[1]) == SYMBOL_REF
1305 && CONSTANT_POOL_ADDRESS_P (operands[1])
1306 && get_pool_mode (operands[1]) == QImode
1307 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1308 [(set (match_dup 0) (match_dup 2))]
1309 "operands[2] = get_pool_constant (operands[1]);")
1312 ; movstrictqi instruction pattern(s).
1315 (define_insn "*movstrictqi"
1316 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1317 (match_operand:QI 1 "memory_operand" "R,T"))]
1322 [(set_attr "op_type" "RX,RXY")])
1325 ; movstricthi instruction pattern(s).
1328 (define_insn "*movstricthi"
1329 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1330 (match_operand:HI 1 "memory_operand" "Q,S"))
1331 (clobber (reg:CC CC_REGNUM))]
1336 [(set_attr "op_type" "RS,RSY")])
1339 ; movstrictsi instruction pattern(s).
1342 (define_insn "movstrictsi"
1343 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1344 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1351 [(set_attr "op_type" "RR,RX,RXY,RRE")
1352 (set_attr "type" "lr,load,load,*")])
1355 ; movdf instruction pattern(s).
1358 (define_expand "movdf"
1359 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1360 (match_operand:DF 1 "general_operand" ""))]
1364 (define_insn "*movdf_64"
1365 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
1366 (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
1378 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1379 (set_attr "type" "floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1381 (define_insn "*movdf_31"
1382 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
1383 (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
1396 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
1397 (set_attr "type" "floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
1400 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1401 (match_operand:DF 1 "general_operand" ""))]
1402 "!TARGET_64BIT && reload_completed
1403 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1404 [(set (match_dup 2) (match_dup 4))
1405 (set (match_dup 3) (match_dup 5))]
1407 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1408 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1409 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1410 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1414 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1415 (match_operand:DF 1 "general_operand" ""))]
1416 "!TARGET_64BIT && reload_completed
1417 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1418 [(set (match_dup 2) (match_dup 4))
1419 (set (match_dup 3) (match_dup 5))]
1421 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1422 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1423 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1424 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1428 [(set (match_operand:DF 0 "register_operand" "")
1429 (match_operand:DF 1 "memory_operand" ""))]
1430 "!TARGET_64BIT && reload_completed
1431 && !FP_REG_P (operands[0])
1432 && !s_operand (operands[1], VOIDmode)"
1433 [(set (match_dup 0) (match_dup 1))]
1435 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1436 s390_load_address (addr, XEXP (operands[1], 0));
1437 operands[1] = replace_equiv_address (operands[1], addr);
1440 (define_expand "reload_outdf"
1441 [(parallel [(match_operand:DF 0 "" "")
1442 (match_operand:DF 1 "register_operand" "d")
1443 (match_operand:SI 2 "register_operand" "=&a")])]
1446 gcc_assert (MEM_P (operands[0]));
1447 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1448 operands[0] = replace_equiv_address (operands[0], operands[2]);
1449 emit_move_insn (operands[0], operands[1]);
1454 ; movsf instruction pattern(s).
1457 (define_insn "movsf"
1458 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
1459 (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
1473 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1474 (set_attr "type" "floadsf,floadsf,floadsf,fstoresf,fstoresf,
1475 lr,load,load,store,store,*")])
1478 ; movcc instruction pattern
1481 (define_insn "movcc"
1482 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1483 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1493 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1494 (set_attr "type" "lr,*,*,store,store,load,load")])
1497 ; Block move (MVC) patterns.
1501 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1502 (match_operand:BLK 1 "memory_operand" "Q"))
1503 (use (match_operand 2 "const_int_operand" "n"))]
1504 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1505 "mvc\t%O0(%2,%R0),%S1"
1506 [(set_attr "op_type" "SS")])
1509 [(set (match_operand 0 "memory_operand" "")
1510 (match_operand 1 "memory_operand" ""))]
1512 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1513 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1515 [(set (match_dup 0) (match_dup 1))
1516 (use (match_dup 2))])]
1518 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1519 operands[0] = adjust_address (operands[0], BLKmode, 0);
1520 operands[1] = adjust_address (operands[1], BLKmode, 0);
1525 [(set (match_operand:BLK 0 "memory_operand" "")
1526 (match_operand:BLK 1 "memory_operand" ""))
1527 (use (match_operand 2 "const_int_operand" ""))])
1529 [(set (match_operand:BLK 3 "memory_operand" "")
1530 (match_operand:BLK 4 "memory_operand" ""))
1531 (use (match_operand 5 "const_int_operand" ""))])]
1532 "s390_offset_p (operands[0], operands[3], operands[2])
1533 && s390_offset_p (operands[1], operands[4], operands[2])
1534 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1536 [(set (match_dup 6) (match_dup 7))
1537 (use (match_dup 8))])]
1538 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1539 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1540 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1544 ; load_multiple pattern(s).
1546 ; ??? Due to reload problems with replacing registers inside match_parallel
1547 ; we currently support load_multiple/store_multiple only after reload.
1550 (define_expand "load_multiple"
1551 [(match_par_dup 3 [(set (match_operand 0 "" "")
1552 (match_operand 1 "" ""))
1553 (use (match_operand 2 "" ""))])]
1556 enum machine_mode mode;
1562 /* Support only loading a constant number of fixed-point registers from
1563 memory and only bother with this if more than two */
1564 if (GET_CODE (operands[2]) != CONST_INT
1565 || INTVAL (operands[2]) < 2
1566 || INTVAL (operands[2]) > 16
1567 || GET_CODE (operands[1]) != MEM
1568 || GET_CODE (operands[0]) != REG
1569 || REGNO (operands[0]) >= 16)
1572 count = INTVAL (operands[2]);
1573 regno = REGNO (operands[0]);
1574 mode = GET_MODE (operands[0]);
1575 if (mode != SImode && mode != word_mode)
1578 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1581 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1583 from = XEXP (operands[1], 0);
1586 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1587 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1588 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1590 from = XEXP (XEXP (operands[1], 0), 0);
1591 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1598 from = force_reg (Pmode, XEXP (operands[1], 0));
1602 for (i = 0; i < count; i++)
1603 XVECEXP (operands[3], 0, i)
1604 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1605 change_address (operands[1], mode,
1606 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1609 (define_insn "*load_multiple_di"
1610 [(match_parallel 0 "load_multiple_operation"
1611 [(set (match_operand:DI 1 "register_operand" "=r")
1612 (match_operand:DI 2 "s_operand" "QS"))])]
1613 "reload_completed && word_mode == DImode"
1615 int words = XVECLEN (operands[0], 0);
1616 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1617 return "lmg\t%1,%0,%S2";
1619 [(set_attr "op_type" "RSY")
1620 (set_attr "type" "lm")])
1622 (define_insn "*load_multiple_si"
1623 [(match_parallel 0 "load_multiple_operation"
1624 [(set (match_operand:SI 1 "register_operand" "=r,r")
1625 (match_operand:SI 2 "s_operand" "Q,S"))])]
1628 int words = XVECLEN (operands[0], 0);
1629 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1630 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1632 [(set_attr "op_type" "RS,RSY")
1633 (set_attr "type" "lm")])
1636 ; store multiple pattern(s).
1639 (define_expand "store_multiple"
1640 [(match_par_dup 3 [(set (match_operand 0 "" "")
1641 (match_operand 1 "" ""))
1642 (use (match_operand 2 "" ""))])]
1645 enum machine_mode mode;
1651 /* Support only storing a constant number of fixed-point registers to
1652 memory and only bother with this if more than two. */
1653 if (GET_CODE (operands[2]) != CONST_INT
1654 || INTVAL (operands[2]) < 2
1655 || INTVAL (operands[2]) > 16
1656 || GET_CODE (operands[0]) != MEM
1657 || GET_CODE (operands[1]) != REG
1658 || REGNO (operands[1]) >= 16)
1661 count = INTVAL (operands[2]);
1662 regno = REGNO (operands[1]);
1663 mode = GET_MODE (operands[1]);
1664 if (mode != SImode && mode != word_mode)
1667 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1671 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1673 to = XEXP (operands[0], 0);
1676 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1677 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1678 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1680 to = XEXP (XEXP (operands[0], 0), 0);
1681 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1688 to = force_reg (Pmode, XEXP (operands[0], 0));
1692 for (i = 0; i < count; i++)
1693 XVECEXP (operands[3], 0, i)
1694 = gen_rtx_SET (VOIDmode,
1695 change_address (operands[0], mode,
1696 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1697 gen_rtx_REG (mode, regno + i));
1700 (define_insn "*store_multiple_di"
1701 [(match_parallel 0 "store_multiple_operation"
1702 [(set (match_operand:DI 1 "s_operand" "=QS")
1703 (match_operand:DI 2 "register_operand" "r"))])]
1704 "reload_completed && word_mode == DImode"
1706 int words = XVECLEN (operands[0], 0);
1707 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1708 return "stmg\t%2,%0,%S1";
1710 [(set_attr "op_type" "RSY")
1711 (set_attr "type" "stm")])
1714 (define_insn "*store_multiple_si"
1715 [(match_parallel 0 "store_multiple_operation"
1716 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1717 (match_operand:SI 2 "register_operand" "r,r"))])]
1720 int words = XVECLEN (operands[0], 0);
1721 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1722 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1724 [(set_attr "op_type" "RS,RSY")
1725 (set_attr "type" "stm")])
1728 ;; String instructions.
1731 (define_insn "*execute"
1732 [(match_parallel 0 ""
1733 [(unspec [(match_operand 1 "register_operand" "a")
1734 (match_operand:BLK 2 "memory_operand" "R")
1735 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1736 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1737 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1739 [(set_attr "op_type" "RX")
1740 (set_attr "type" "cs")])
1744 ; strlenM instruction pattern(s).
1747 (define_expand "strlen<mode>"
1748 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1751 (unspec:P [(const_int 0)
1752 (match_operand:BLK 1 "memory_operand" "")
1754 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1755 (clobber (scratch:P))
1756 (clobber (reg:CC CC_REGNUM))])
1758 [(set (match_operand:P 0 "register_operand" "")
1759 (minus:P (match_dup 4) (match_dup 5)))
1760 (clobber (reg:CC CC_REGNUM))])]
1763 operands[4] = gen_reg_rtx (Pmode);
1764 operands[5] = gen_reg_rtx (Pmode);
1765 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1766 operands[1] = replace_equiv_address (operands[1], operands[5]);
1769 (define_insn "*strlen<mode>"
1770 [(set (match_operand:P 0 "register_operand" "=a")
1771 (unspec:P [(match_operand:P 2 "general_operand" "0")
1772 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1774 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1775 (clobber (match_scratch:P 1 "=a"))
1776 (clobber (reg:CC CC_REGNUM))]
1778 "srst\t%0,%1\;jo\t.-4"
1779 [(set_attr "length" "8")
1780 (set_attr "type" "vs")])
1783 ; movmemM instruction pattern(s).
1786 (define_expand "movmem<mode>"
1787 [(set (match_operand:BLK 0 "memory_operand" "")
1788 (match_operand:BLK 1 "memory_operand" ""))
1789 (use (match_operand:GPR 2 "general_operand" ""))
1790 (match_operand 3 "" "")]
1792 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1794 ; Move a block that is up to 256 bytes in length.
1795 ; The block length is taken as (operands[2] % 256) + 1.
1797 (define_expand "movmem_short"
1799 [(set (match_operand:BLK 0 "memory_operand" "")
1800 (match_operand:BLK 1 "memory_operand" ""))
1801 (use (match_operand 2 "nonmemory_operand" ""))
1802 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1803 (clobber (match_dup 3))])]
1805 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1807 (define_insn "*movmem_short"
1808 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1809 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1810 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1811 (use (match_operand 3 "immediate_operand" "X,R,X"))
1812 (clobber (match_scratch 4 "=X,X,&a"))]
1813 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1814 && GET_MODE (operands[4]) == Pmode"
1816 [(set_attr "type" "cs")])
1819 [(set (match_operand:BLK 0 "memory_operand" "")
1820 (match_operand:BLK 1 "memory_operand" ""))
1821 (use (match_operand 2 "const_int_operand" ""))
1822 (use (match_operand 3 "immediate_operand" ""))
1823 (clobber (scratch))]
1826 [(set (match_dup 0) (match_dup 1))
1827 (use (match_dup 2))])]
1828 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1831 [(set (match_operand:BLK 0 "memory_operand" "")
1832 (match_operand:BLK 1 "memory_operand" ""))
1833 (use (match_operand 2 "register_operand" ""))
1834 (use (match_operand 3 "memory_operand" ""))
1835 (clobber (scratch))]
1838 [(unspec [(match_dup 2) (match_dup 3)
1839 (const_int 0)] UNSPEC_EXECUTE)
1840 (set (match_dup 0) (match_dup 1))
1841 (use (const_int 1))])]
1845 [(set (match_operand:BLK 0 "memory_operand" "")
1846 (match_operand:BLK 1 "memory_operand" ""))
1847 (use (match_operand 2 "register_operand" ""))
1848 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1849 (clobber (match_operand 3 "register_operand" ""))]
1850 "reload_completed && TARGET_CPU_ZARCH"
1851 [(set (match_dup 3) (label_ref (match_dup 4)))
1853 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1854 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1855 (set (match_dup 0) (match_dup 1))
1856 (use (const_int 1))])]
1857 "operands[4] = gen_label_rtx ();")
1859 ; Move a block of arbitrary length.
1861 (define_expand "movmem_long"
1863 [(clobber (match_dup 2))
1864 (clobber (match_dup 3))
1865 (set (match_operand:BLK 0 "memory_operand" "")
1866 (match_operand:BLK 1 "memory_operand" ""))
1867 (use (match_operand 2 "general_operand" ""))
1869 (clobber (reg:CC CC_REGNUM))])]
1872 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1873 rtx reg0 = gen_reg_rtx (dword_mode);
1874 rtx reg1 = gen_reg_rtx (dword_mode);
1875 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1876 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1877 rtx len0 = gen_lowpart (Pmode, reg0);
1878 rtx len1 = gen_lowpart (Pmode, reg1);
1880 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1881 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1882 emit_move_insn (len0, operands[2]);
1884 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1885 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1886 emit_move_insn (len1, operands[2]);
1888 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1889 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1894 (define_insn "*movmem_long_64"
1895 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1896 (clobber (match_operand:TI 1 "register_operand" "=d"))
1897 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1898 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
1901 (clobber (reg:CC CC_REGNUM))]
1903 "mvcle\t%0,%1,0\;jo\t.-4"
1904 [(set_attr "length" "8")
1905 (set_attr "type" "vs")])
1907 (define_insn "*movmem_long_31"
1908 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1909 (clobber (match_operand:DI 1 "register_operand" "=d"))
1910 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1911 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
1914 (clobber (reg:CC CC_REGNUM))]
1916 "mvcle\t%0,%1,0\;jo\t.-4"
1917 [(set_attr "length" "8")
1918 (set_attr "type" "vs")])
1921 ; clrmemM instruction pattern(s).
1924 (define_expand "clrmem<mode>"
1925 [(set (match_operand:BLK 0 "memory_operand" "")
1927 (use (match_operand:GPR 1 "general_operand" ""))
1928 (match_operand 2 "" "")]
1930 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
1932 ; Clear a block that is up to 256 bytes in length.
1933 ; The block length is taken as (operands[1] % 256) + 1.
1935 (define_expand "clrmem_short"
1937 [(set (match_operand:BLK 0 "memory_operand" "")
1939 (use (match_operand 1 "nonmemory_operand" ""))
1940 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1941 (clobber (match_dup 2))
1942 (clobber (reg:CC CC_REGNUM))])]
1944 "operands[2] = gen_rtx_SCRATCH (Pmode);")
1946 (define_insn "*clrmem_short"
1947 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1949 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
1950 (use (match_operand 2 "immediate_operand" "X,R,X"))
1951 (clobber (match_scratch 3 "=X,X,&a"))
1952 (clobber (reg:CC CC_REGNUM))]
1953 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
1954 && GET_MODE (operands[3]) == Pmode"
1956 [(set_attr "type" "cs")])
1959 [(set (match_operand:BLK 0 "memory_operand" "")
1961 (use (match_operand 1 "const_int_operand" ""))
1962 (use (match_operand 2 "immediate_operand" ""))
1964 (clobber (reg:CC CC_REGNUM))]
1967 [(set (match_dup 0) (const_int 0))
1969 (clobber (reg:CC CC_REGNUM))])]
1970 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
1973 [(set (match_operand:BLK 0 "memory_operand" "")
1975 (use (match_operand 1 "register_operand" ""))
1976 (use (match_operand 2 "memory_operand" ""))
1978 (clobber (reg:CC CC_REGNUM))]
1981 [(unspec [(match_dup 1) (match_dup 2)
1982 (const_int 0)] UNSPEC_EXECUTE)
1983 (set (match_dup 0) (const_int 0))
1985 (clobber (reg:CC CC_REGNUM))])]
1989 [(set (match_operand:BLK 0 "memory_operand" "")
1991 (use (match_operand 1 "register_operand" ""))
1992 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1993 (clobber (match_operand 2 "register_operand" ""))
1994 (clobber (reg:CC CC_REGNUM))]
1995 "reload_completed && TARGET_CPU_ZARCH"
1996 [(set (match_dup 2) (label_ref (match_dup 3)))
1998 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
1999 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2000 (set (match_dup 0) (const_int 0))
2002 (clobber (reg:CC CC_REGNUM))])]
2003 "operands[3] = gen_label_rtx ();")
2005 ; Clear a block of arbitrary length.
2007 (define_expand "clrmem_long"
2009 [(clobber (match_dup 1))
2010 (set (match_operand:BLK 0 "memory_operand" "")
2012 (use (match_operand 1 "general_operand" ""))
2014 (clobber (reg:CC CC_REGNUM))])]
2017 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2018 rtx reg0 = gen_reg_rtx (dword_mode);
2019 rtx reg1 = gen_reg_rtx (dword_mode);
2020 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2021 rtx len0 = gen_lowpart (Pmode, reg0);
2023 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2024 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2025 emit_move_insn (len0, operands[1]);
2027 emit_move_insn (reg1, const0_rtx);
2029 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2034 (define_insn "*clrmem_long_64"
2035 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2036 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2039 (use (match_operand:TI 1 "register_operand" "d"))
2040 (clobber (reg:CC CC_REGNUM))]
2042 "mvcle\t%0,%1,0\;jo\t.-4"
2043 [(set_attr "length" "8")
2044 (set_attr "type" "vs")])
2046 (define_insn "*clrmem_long_31"
2047 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2048 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2051 (use (match_operand:DI 1 "register_operand" "d"))
2052 (clobber (reg:CC CC_REGNUM))]
2054 "mvcle\t%0,%1,0\;jo\t.-4"
2055 [(set_attr "length" "8")
2056 (set_attr "type" "vs")])
2059 ; cmpmemM instruction pattern(s).
2062 (define_expand "cmpmemsi"
2063 [(set (match_operand:SI 0 "register_operand" "")
2064 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2065 (match_operand:BLK 2 "memory_operand" "") ) )
2066 (use (match_operand:SI 3 "general_operand" ""))
2067 (use (match_operand:SI 4 "" ""))]
2069 "s390_expand_cmpmem (operands[0], operands[1],
2070 operands[2], operands[3]); DONE;")
2072 ; Compare a block that is up to 256 bytes in length.
2073 ; The block length is taken as (operands[2] % 256) + 1.
2075 (define_expand "cmpmem_short"
2077 [(set (reg:CCU CC_REGNUM)
2078 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2079 (match_operand:BLK 1 "memory_operand" "")))
2080 (use (match_operand 2 "nonmemory_operand" ""))
2081 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2082 (clobber (match_dup 3))])]
2084 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2086 (define_insn "*cmpmem_short"
2087 [(set (reg:CCU CC_REGNUM)
2088 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2089 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2090 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2091 (use (match_operand 3 "immediate_operand" "X,R,X"))
2092 (clobber (match_scratch 4 "=X,X,&a"))]
2093 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2094 && GET_MODE (operands[4]) == Pmode"
2096 [(set_attr "type" "cs")])
2099 [(set (reg:CCU CC_REGNUM)
2100 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2101 (match_operand:BLK 1 "memory_operand" "")))
2102 (use (match_operand 2 "const_int_operand" ""))
2103 (use (match_operand 3 "immediate_operand" ""))
2104 (clobber (scratch))]
2107 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2108 (use (match_dup 2))])]
2109 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2112 [(set (reg:CCU CC_REGNUM)
2113 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2114 (match_operand:BLK 1 "memory_operand" "")))
2115 (use (match_operand 2 "register_operand" ""))
2116 (use (match_operand 3 "memory_operand" ""))
2117 (clobber (scratch))]
2120 [(unspec [(match_dup 2) (match_dup 3)
2121 (const_int 0)] UNSPEC_EXECUTE)
2122 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2123 (use (const_int 1))])]
2127 [(set (reg:CCU CC_REGNUM)
2128 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2129 (match_operand:BLK 1 "memory_operand" "")))
2130 (use (match_operand 2 "register_operand" ""))
2131 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2132 (clobber (match_operand 3 "register_operand" ""))]
2133 "reload_completed && TARGET_CPU_ZARCH"
2134 [(set (match_dup 3) (label_ref (match_dup 4)))
2136 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2137 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2138 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2139 (use (const_int 1))])]
2140 "operands[4] = gen_label_rtx ();")
2142 ; Compare a block of arbitrary length.
2144 (define_expand "cmpmem_long"
2146 [(clobber (match_dup 2))
2147 (clobber (match_dup 3))
2148 (set (reg:CCU CC_REGNUM)
2149 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2150 (match_operand:BLK 1 "memory_operand" "")))
2151 (use (match_operand 2 "general_operand" ""))
2152 (use (match_dup 3))])]
2155 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2156 rtx reg0 = gen_reg_rtx (dword_mode);
2157 rtx reg1 = gen_reg_rtx (dword_mode);
2158 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2159 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2160 rtx len0 = gen_lowpart (Pmode, reg0);
2161 rtx len1 = gen_lowpart (Pmode, reg1);
2163 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2164 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2165 emit_move_insn (len0, operands[2]);
2167 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2168 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2169 emit_move_insn (len1, operands[2]);
2171 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2172 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2177 (define_insn "*cmpmem_long_64"
2178 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2179 (clobber (match_operand:TI 1 "register_operand" "=d"))
2180 (set (reg:CCU CC_REGNUM)
2181 (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2182 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2184 (use (match_dup 3))]
2186 "clcle\t%0,%1,0\;jo\t.-4"
2187 [(set_attr "length" "8")
2188 (set_attr "type" "vs")])
2190 (define_insn "*cmpmem_long_31"
2191 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2192 (clobber (match_operand:DI 1 "register_operand" "=d"))
2193 (set (reg:CCU CC_REGNUM)
2194 (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2195 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2197 (use (match_dup 3))]
2199 "clcle\t%0,%1,0\;jo\t.-4"
2200 [(set_attr "length" "8")
2201 (set_attr "type" "vs")])
2203 ; Convert CCUmode condition code to integer.
2204 ; Result is zero if EQ, positive if LTU, negative if GTU.
2206 (define_insn_and_split "cmpint"
2207 [(set (match_operand:SI 0 "register_operand" "=d")
2208 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2210 (clobber (reg:CC CC_REGNUM))]
2214 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2216 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2217 (clobber (reg:CC CC_REGNUM))])])
2219 (define_insn_and_split "*cmpint_cc"
2220 [(set (reg CC_REGNUM)
2221 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2224 (set (match_operand:SI 0 "register_operand" "=d")
2225 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2226 "s390_match_ccmode (insn, CCSmode)"
2228 "&& reload_completed"
2229 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2231 [(set (match_dup 2) (match_dup 3))
2232 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2234 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2235 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2236 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2239 (define_insn_and_split "*cmpint_sign"
2240 [(set (match_operand:DI 0 "register_operand" "=d")
2241 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2243 (clobber (reg:CC CC_REGNUM))]
2246 "&& reload_completed"
2247 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2249 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2250 (clobber (reg:CC CC_REGNUM))])])
2252 (define_insn_and_split "*cmpint_sign_cc"
2253 [(set (reg CC_REGNUM)
2254 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2255 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2257 (const_int 32)) (const_int 32))
2259 (set (match_operand:DI 0 "register_operand" "=d")
2260 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2261 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2263 "&& reload_completed"
2264 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2266 [(set (match_dup 2) (match_dup 3))
2267 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2269 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2270 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2271 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2276 ;;- Conversion instructions.
2280 (define_insn "*sethigh<mode>si"
2281 [(set (match_operand:SI 0 "register_operand" "=d,d")
2282 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2283 (clobber (reg:CC CC_REGNUM))]
2286 icm\t%0,<icm_hi>,%S1
2287 icmy\t%0,<icm_hi>,%S1"
2288 [(set_attr "op_type" "RS,RSY")])
2290 (define_insn "*sethighqidi_64"
2291 [(set (match_operand:DI 0 "register_operand" "=d")
2292 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2293 (clobber (reg:CC CC_REGNUM))]
2296 [(set_attr "op_type" "RSY")])
2298 (define_insn "*sethighqidi_31"
2299 [(set (match_operand:DI 0 "register_operand" "=d,d")
2300 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2301 (clobber (reg:CC CC_REGNUM))]
2306 [(set_attr "op_type" "RS,RSY")])
2308 (define_insn_and_split "*extractqi"
2309 [(set (match_operand:SI 0 "register_operand" "=d")
2310 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2311 (match_operand 2 "const_int_operand" "n")
2313 (clobber (reg:CC CC_REGNUM))]
2315 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2317 "&& reload_completed"
2319 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2320 (clobber (reg:CC CC_REGNUM))])
2321 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2323 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2324 operands[1] = change_address (operands[1], QImode, 0);
2327 (define_insn_and_split "*extracthi"
2328 [(set (match_operand:SI 0 "register_operand" "=d")
2329 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2330 (match_operand 2 "const_int_operand" "n")
2332 (clobber (reg:CC CC_REGNUM))]
2334 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2336 "&& reload_completed"
2338 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2339 (clobber (reg:CC CC_REGNUM))])
2340 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2342 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2343 operands[1] = change_address (operands[1], HImode, 0);
2347 ; extendsidi2 instruction pattern(s).
2350 (define_expand "extendsidi2"
2351 [(set (match_operand:DI 0 "register_operand" "")
2352 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2358 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2359 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2360 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2361 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2367 (define_insn "*extendsidi2"
2368 [(set (match_operand:DI 0 "register_operand" "=d,d")
2369 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2374 [(set_attr "op_type" "RRE,RXY")])
2377 ; extend(hi|qi)di2 instruction pattern(s).
2380 (define_expand "extend<mode>di2"
2381 [(set (match_operand:DI 0 "register_operand" "")
2382 (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2388 rtx tmp = gen_reg_rtx (SImode);
2389 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2390 emit_insn (gen_extendsidi2 (operands[0], tmp));
2395 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2396 GET_MODE_BITSIZE (<MODE>mode));
2397 operands[1] = gen_lowpart (DImode, operands[1]);
2398 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2399 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2405 (define_insn "*extendhidi2"
2406 [(set (match_operand:DI 0 "register_operand" "=d")
2407 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2410 [(set_attr "op_type" "RXY")])
2412 (define_insn "*extendqidi2"
2413 [(set (match_operand:DI 0 "register_operand" "=d")
2414 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2415 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2417 [(set_attr "op_type" "RXY")])
2419 (define_insn_and_split "*extendqidi2_short_displ"
2420 [(set (match_operand:DI 0 "register_operand" "=d")
2421 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2422 (clobber (reg:CC CC_REGNUM))]
2423 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2425 "&& reload_completed"
2427 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2428 (clobber (reg:CC CC_REGNUM))])
2430 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2431 (clobber (reg:CC CC_REGNUM))])]
2435 ; extend(hi|qi)si2 instruction pattern(s).
2438 (define_expand "extend<mode>si2"
2439 [(set (match_operand:SI 0 "register_operand" "")
2440 (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2444 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2445 GET_MODE_BITSIZE(<MODE>mode));
2446 operands[1] = gen_lowpart (SImode, operands[1]);
2447 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2448 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2453 (define_insn "*extendhisi2"
2454 [(set (match_operand:SI 0 "register_operand" "=d,d")
2455 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2460 [(set_attr "op_type" "RX,RXY")])
2462 (define_insn "*extendqisi2"
2463 [(set (match_operand:SI 0 "register_operand" "=d")
2464 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2465 "TARGET_LONG_DISPLACEMENT"
2467 [(set_attr "op_type" "RXY")])
2469 (define_insn_and_split "*extendqisi2_short_displ"
2470 [(set (match_operand:SI 0 "register_operand" "=d")
2471 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2472 (clobber (reg:CC CC_REGNUM))]
2473 "!TARGET_LONG_DISPLACEMENT"
2475 "&& reload_completed"
2477 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2478 (clobber (reg:CC CC_REGNUM))])
2480 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2481 (clobber (reg:CC CC_REGNUM))])]
2485 ; extendqihi2 instruction pattern(s).
2490 ; zero_extendsidi2 instruction pattern(s).
2493 (define_expand "zero_extendsidi2"
2494 [(set (match_operand:DI 0 "register_operand" "")
2495 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2501 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2502 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2503 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2509 (define_insn "*zero_extendsidi2"
2510 [(set (match_operand:DI 0 "register_operand" "=d,d")
2511 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2516 [(set_attr "op_type" "RRE,RXY")])
2519 ; zero_extend(hi|qi)di2 instruction pattern(s).
2522 (define_expand "zero_extend<mode>di2"
2523 [(set (match_operand:DI 0 "register_operand" "")
2524 (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2530 rtx tmp = gen_reg_rtx (SImode);
2531 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2532 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2537 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2538 GET_MODE_BITSIZE(<MODE>mode));
2539 operands[1] = gen_lowpart (DImode, operands[1]);
2540 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2541 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2547 (define_insn "*zero_extend<mode>di2"
2548 [(set (match_operand:DI 0 "register_operand" "=d")
2549 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2552 [(set_attr "op_type" "RXY")])
2555 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2558 (define_insn "*llgt_sidi"
2559 [(set (match_operand:DI 0 "register_operand" "=d")
2560 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2561 (const_int 2147483647)))]
2564 [(set_attr "op_type" "RXE")])
2566 (define_insn_and_split "*llgt_sidi_split"
2567 [(set (match_operand:DI 0 "register_operand" "=d")
2568 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2569 (const_int 2147483647)))
2570 (clobber (reg:CC CC_REGNUM))]
2573 "&& reload_completed"
2575 (and:DI (subreg:DI (match_dup 1) 0)
2576 (const_int 2147483647)))]
2579 (define_insn "*llgt_sisi"
2580 [(set (match_operand:SI 0 "register_operand" "=d,d")
2581 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2582 (const_int 2147483647)))]
2587 [(set_attr "op_type" "RRE,RXE")])
2589 (define_insn "*llgt_didi"
2590 [(set (match_operand:DI 0 "register_operand" "=d,d")
2591 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2592 (const_int 2147483647)))]
2597 [(set_attr "op_type" "RRE,RXE")])
2600 [(set (match_operand:GPR 0 "register_operand" "")
2601 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2602 (const_int 2147483647)))
2603 (clobber (reg:CC CC_REGNUM))]
2604 "TARGET_64BIT && reload_completed"
2606 (and:GPR (match_dup 1)
2607 (const_int 2147483647)))]
2611 ; zero_extend(hi|qi)si2 instruction pattern(s).
2614 (define_expand "zero_extend<mode>si2"
2615 [(set (match_operand:SI 0 "register_operand" "")
2616 (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2620 operands[1] = gen_lowpart (SImode, operands[1]);
2621 emit_insn (gen_andsi3 (operands[0], operands[1],
2622 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2627 (define_insn "*zero_extend<mode>si2_64"
2628 [(set (match_operand:SI 0 "register_operand" "=d")
2629 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2632 [(set_attr "op_type" "RXY")])
2634 (define_insn_and_split "*zero_extendhisi2_31"
2635 [(set (match_operand:SI 0 "register_operand" "=&d")
2636 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2637 (clobber (reg:CC CC_REGNUM))]
2640 "&& reload_completed"
2641 [(set (match_dup 0) (const_int 0))
2643 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2644 (clobber (reg:CC CC_REGNUM))])]
2645 "operands[2] = gen_lowpart (HImode, operands[0]);")
2647 (define_insn_and_split "*zero_extendqisi2_31"
2648 [(set (match_operand:SI 0 "register_operand" "=&d")
2649 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2652 "&& reload_completed"
2653 [(set (match_dup 0) (const_int 0))
2654 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2655 "operands[2] = gen_lowpart (QImode, operands[0]);")
2658 ; zero_extendqihi2 instruction pattern(s).
2661 (define_expand "zero_extendqihi2"
2662 [(set (match_operand:HI 0 "register_operand" "")
2663 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2667 operands[1] = gen_lowpart (HImode, operands[1]);
2668 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2673 (define_insn "*zero_extendqihi2_64"
2674 [(set (match_operand:HI 0 "register_operand" "=d")
2675 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2678 [(set_attr "op_type" "RXY")])
2680 (define_insn_and_split "*zero_extendqihi2_31"
2681 [(set (match_operand:HI 0 "register_operand" "=&d")
2682 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2685 "&& reload_completed"
2686 [(set (match_dup 0) (const_int 0))
2687 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2688 "operands[2] = gen_lowpart (QImode, operands[0]);")
2692 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
2695 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
2696 [(set (match_operand:GPR 0 "register_operand" "")
2697 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
2698 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2700 rtx label1 = gen_label_rtx ();
2701 rtx label2 = gen_label_rtx ();
2702 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
2703 REAL_VALUE_TYPE cmp, sub;
2705 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2706 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
2707 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
2709 emit_insn (gen_cmp<FPR:mode> (operands[1],
2710 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
2711 emit_jump_insn (gen_blt (label1));
2712 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
2713 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
2714 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
2718 emit_label (label1);
2719 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
2720 operands[1], GEN_INT(5)));
2721 emit_label (label2);
2725 (define_expand "fix_trunc<FPR:mode>di2"
2726 [(set (match_operand:DI 0 "register_operand" "")
2727 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
2728 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2730 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2731 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
2736 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
2737 [(set (match_operand:GPR 0 "register_operand" "=d")
2738 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
2739 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
2740 (clobber (reg:CC CC_REGNUM))]
2741 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2742 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
2743 [(set_attr "op_type" "RRE")
2744 (set_attr "type" "ftoi")])
2747 ; fix_truncdfsi2 instruction pattern(s).
2750 (define_expand "fix_truncdfsi2"
2751 [(set (match_operand:SI 0 "register_operand" "")
2752 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2755 if (TARGET_IBM_FLOAT)
2757 /* This is the algorithm from POP chapter A.5.7.2. */
2759 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2760 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2761 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2763 operands[1] = force_reg (DFmode, operands[1]);
2764 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2765 two31r, two32, temp));
2769 operands[1] = force_reg (DFmode, operands[1]);
2770 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2776 (define_insn "fix_truncdfsi2_ibm"
2777 [(set (match_operand:SI 0 "register_operand" "=d")
2778 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2779 (use (match_operand:DI 2 "immediate_operand" "m"))
2780 (use (match_operand:DI 3 "immediate_operand" "m"))
2781 (use (match_operand:BLK 4 "memory_operand" "m"))
2782 (clobber (reg:CC CC_REGNUM))]
2783 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2785 output_asm_insn ("sd\t%1,%2", operands);
2786 output_asm_insn ("aw\t%1,%3", operands);
2787 output_asm_insn ("std\t%1,%4", operands);
2788 output_asm_insn ("xi\t%N4,128", operands);
2791 [(set_attr "length" "20")])
2794 ; fix_truncsfsi2 instruction pattern(s).
2797 (define_expand "fix_truncsfsi2"
2798 [(set (match_operand:SI 0 "register_operand" "")
2799 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2802 if (TARGET_IBM_FLOAT)
2804 /* Convert to DFmode and then use the POP algorithm. */
2805 rtx temp = gen_reg_rtx (DFmode);
2806 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2807 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2811 operands[1] = force_reg (SFmode, operands[1]);
2812 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2819 ; floatdi(df|sf)2 instruction pattern(s).
2822 (define_insn "floatdi<mode>2"
2823 [(set (match_operand:FPR 0 "register_operand" "=f")
2824 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
2825 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2827 [(set_attr "op_type" "RRE")
2828 (set_attr "type" "itof" )])
2831 ; floatsidf2 instruction pattern(s).
2834 (define_expand "floatsidf2"
2835 [(set (match_operand:DF 0 "register_operand" "")
2836 (float:DF (match_operand:SI 1 "register_operand" "")))]
2839 if (TARGET_IBM_FLOAT)
2841 /* This is the algorithm from POP chapter A.5.7.1. */
2843 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2844 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2846 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2851 (define_insn "floatsidf2_ieee"
2852 [(set (match_operand:DF 0 "register_operand" "=f")
2853 (float:DF (match_operand:SI 1 "register_operand" "d")))]
2854 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2856 [(set_attr "op_type" "RRE")
2857 (set_attr "type" "itof" )])
2859 (define_insn "floatsidf2_ibm"
2860 [(set (match_operand:DF 0 "register_operand" "=f")
2861 (float:DF (match_operand:SI 1 "register_operand" "d")))
2862 (use (match_operand:DI 2 "immediate_operand" "m"))
2863 (use (match_operand:BLK 3 "memory_operand" "m"))
2864 (clobber (reg:CC CC_REGNUM))]
2865 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2867 output_asm_insn ("st\t%1,%N3", operands);
2868 output_asm_insn ("xi\t%N3,128", operands);
2869 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
2870 output_asm_insn ("ld\t%0,%3", operands);
2873 [(set_attr "length" "20")])
2876 ; floatsisf2 instruction pattern(s).
2879 (define_expand "floatsisf2"
2880 [(set (match_operand:SF 0 "register_operand" "")
2881 (float:SF (match_operand:SI 1 "register_operand" "")))]
2884 if (TARGET_IBM_FLOAT)
2886 /* Use the POP algorithm to convert to DFmode and then truncate. */
2887 rtx temp = gen_reg_rtx (DFmode);
2888 emit_insn (gen_floatsidf2 (temp, operands[1]));
2889 emit_insn (gen_truncdfsf2 (operands[0], temp));
2894 (define_insn "floatsisf2_ieee"
2895 [(set (match_operand:SF 0 "register_operand" "=f")
2896 (float:SF (match_operand:SI 1 "register_operand" "d")))]
2897 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2899 [(set_attr "op_type" "RRE")
2900 (set_attr "type" "itof" )])
2903 ; truncdfsf2 instruction pattern(s).
2906 (define_expand "truncdfsf2"
2907 [(set (match_operand:SF 0 "register_operand" "")
2908 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
2912 (define_insn "truncdfsf2_ieee"
2913 [(set (match_operand:SF 0 "register_operand" "=f")
2914 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2915 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2917 [(set_attr "op_type" "RRE")])
2919 (define_insn "truncdfsf2_ibm"
2920 [(set (match_operand:SF 0 "register_operand" "=f,f")
2921 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
2922 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2926 [(set_attr "op_type" "RR,RX")
2927 (set_attr "type" "floadsf")])
2930 ; extendsfdf2 instruction pattern(s).
2933 (define_expand "extendsfdf2"
2934 [(set (match_operand:DF 0 "register_operand" "")
2935 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2938 if (TARGET_IBM_FLOAT)
2940 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2945 (define_insn "extendsfdf2_ieee"
2946 [(set (match_operand:DF 0 "register_operand" "=f,f")
2947 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
2948 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2952 [(set_attr "op_type" "RRE,RXE")
2953 (set_attr "type" "floadsf")])
2955 (define_insn "extendsfdf2_ibm"
2956 [(set (match_operand:DF 0 "register_operand" "=f,f")
2957 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
2958 (clobber (reg:CC CC_REGNUM))]
2959 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2961 sdr\t%0,%0\;ler\t%0,%1
2962 sdr\t%0,%0\;le\t%0,%1"
2963 [(set_attr "length" "4,6")
2964 (set_attr "type" "floadsf")])
2968 ;; ARITHMETIC OPERATIONS
2970 ; arithmetic operations set the ConditionCode,
2971 ; because of unpredictable Bits in Register for Halfword and Byte
2972 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2975 ;;- Add instructions.
2979 ; addti3 instruction pattern(s).
2982 (define_insn_and_split "addti3"
2983 [(set (match_operand:TI 0 "register_operand" "=&d")
2984 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
2985 (match_operand:TI 2 "general_operand" "do") ) )
2986 (clobber (reg:CC CC_REGNUM))]
2989 "&& reload_completed"
2991 [(set (reg:CCL1 CC_REGNUM)
2992 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
2994 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
2996 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
2997 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
2998 (clobber (reg:CC CC_REGNUM))])]
2999 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3000 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3001 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3002 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3003 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3004 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3007 ; adddi3 instruction pattern(s).
3010 (define_insn "*adddi3_sign"
3011 [(set (match_operand:DI 0 "register_operand" "=d,d")
3012 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3013 (match_operand:DI 1 "register_operand" "0,0")))
3014 (clobber (reg:CC CC_REGNUM))]
3019 [(set_attr "op_type" "RRE,RXY")])
3021 (define_insn "*adddi3_zero_cc"
3022 [(set (reg CC_REGNUM)
3023 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3024 (match_operand:DI 1 "register_operand" "0,0"))
3026 (set (match_operand:DI 0 "register_operand" "=d,d")
3027 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3028 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3032 [(set_attr "op_type" "RRE,RXY")])
3034 (define_insn "*adddi3_zero_cconly"
3035 [(set (reg CC_REGNUM)
3036 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3037 (match_operand:DI 1 "register_operand" "0,0"))
3039 (clobber (match_scratch:DI 0 "=d,d"))]
3040 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3044 [(set_attr "op_type" "RRE,RXY")])
3046 (define_insn "*adddi3_zero"
3047 [(set (match_operand:DI 0 "register_operand" "=d,d")
3048 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3049 (match_operand:DI 1 "register_operand" "0,0")))
3050 (clobber (reg:CC CC_REGNUM))]
3055 [(set_attr "op_type" "RRE,RXY")])
3057 (define_insn "*adddi3_imm_cc"
3058 [(set (reg CC_REGNUM)
3059 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3060 (match_operand:DI 2 "const_int_operand" "K"))
3062 (set (match_operand:DI 0 "register_operand" "=d")
3063 (plus:DI (match_dup 1) (match_dup 2)))]
3065 && s390_match_ccmode (insn, CCAmode)
3066 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3068 [(set_attr "op_type" "RI")])
3070 (define_insn "*adddi3_carry1_cc"
3071 [(set (reg CC_REGNUM)
3072 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3073 (match_operand:DI 2 "general_operand" "d,m"))
3075 (set (match_operand:DI 0 "register_operand" "=d,d")
3076 (plus:DI (match_dup 1) (match_dup 2)))]
3077 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3081 [(set_attr "op_type" "RRE,RXY")])
3083 (define_insn "*adddi3_carry1_cconly"
3084 [(set (reg CC_REGNUM)
3085 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3086 (match_operand:DI 2 "general_operand" "d,m"))
3088 (clobber (match_scratch:DI 0 "=d,d"))]
3089 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3093 [(set_attr "op_type" "RRE,RXY")])
3095 (define_insn "*adddi3_carry2_cc"
3096 [(set (reg CC_REGNUM)
3097 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3098 (match_operand:DI 2 "general_operand" "d,m"))
3100 (set (match_operand:DI 0 "register_operand" "=d,d")
3101 (plus:DI (match_dup 1) (match_dup 2)))]
3102 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3106 [(set_attr "op_type" "RRE,RXY")])
3108 (define_insn "*adddi3_carry2_cconly"
3109 [(set (reg CC_REGNUM)
3110 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3111 (match_operand:DI 2 "general_operand" "d,m"))
3113 (clobber (match_scratch:DI 0 "=d,d"))]
3114 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3118 [(set_attr "op_type" "RRE,RXY")])
3120 (define_insn "*adddi3_cc"
3121 [(set (reg CC_REGNUM)
3122 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3123 (match_operand:DI 2 "general_operand" "d,m"))
3125 (set (match_operand:DI 0 "register_operand" "=d,d")
3126 (plus:DI (match_dup 1) (match_dup 2)))]
3127 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3131 [(set_attr "op_type" "RRE,RXY")])
3133 (define_insn "*adddi3_cconly"
3134 [(set (reg CC_REGNUM)
3135 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3136 (match_operand:DI 2 "general_operand" "d,m"))
3138 (clobber (match_scratch:DI 0 "=d,d"))]
3139 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3143 [(set_attr "op_type" "RRE,RXY")])
3145 (define_insn "*adddi3_cconly2"
3146 [(set (reg CC_REGNUM)
3147 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3148 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3149 (clobber (match_scratch:DI 0 "=d,d"))]
3150 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3154 [(set_attr "op_type" "RRE,RXY")])
3156 (define_insn "*adddi3_64"
3157 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3158 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3159 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3160 (clobber (reg:CC CC_REGNUM))]
3166 [(set_attr "op_type" "RRE,RI,RXY")])
3168 (define_insn_and_split "*adddi3_31z"
3169 [(set (match_operand:DI 0 "register_operand" "=&d")
3170 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3171 (match_operand:DI 2 "general_operand" "do") ) )
3172 (clobber (reg:CC CC_REGNUM))]
3173 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3175 "&& reload_completed"
3177 [(set (reg:CCL1 CC_REGNUM)
3178 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3180 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3182 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3183 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3184 (clobber (reg:CC CC_REGNUM))])]
3185 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3186 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3187 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3188 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3189 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3190 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3192 (define_insn_and_split "*adddi3_31"
3193 [(set (match_operand:DI 0 "register_operand" "=&d")
3194 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3195 (match_operand:DI 2 "general_operand" "do") ) )
3196 (clobber (reg:CC CC_REGNUM))]
3199 "&& reload_completed"
3201 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3202 (clobber (reg:CC CC_REGNUM))])
3204 [(set (reg:CCL1 CC_REGNUM)
3205 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3207 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3209 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3211 (label_ref (match_dup 9))))
3213 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3214 (clobber (reg:CC CC_REGNUM))])
3216 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3217 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3218 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3219 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3220 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3221 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3222 operands[9] = gen_label_rtx ();")
3224 (define_expand "adddi3"
3226 [(set (match_operand:DI 0 "register_operand" "")
3227 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3228 (match_operand:DI 2 "general_operand" "")))
3229 (clobber (reg:CC CC_REGNUM))])]
3234 ; addsi3 instruction pattern(s).
3237 (define_insn "*addsi3_imm_cc"
3238 [(set (reg CC_REGNUM)
3239 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3240 (match_operand:SI 2 "const_int_operand" "K"))
3242 (set (match_operand:SI 0 "register_operand" "=d")
3243 (plus:SI (match_dup 1) (match_dup 2)))]
3244 "s390_match_ccmode (insn, CCAmode)
3245 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3247 [(set_attr "op_type" "RI")])
3249 (define_insn "*addsi3_carry1_cc"
3250 [(set (reg CC_REGNUM)
3251 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3252 (match_operand:SI 2 "general_operand" "d,R,T"))
3254 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3255 (plus:SI (match_dup 1) (match_dup 2)))]
3256 "s390_match_ccmode (insn, CCL1mode)"
3261 [(set_attr "op_type" "RR,RX,RXY")])
3263 (define_insn "*addsi3_carry1_cconly"
3264 [(set (reg CC_REGNUM)
3265 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3266 (match_operand:SI 2 "general_operand" "d,R,T"))
3268 (clobber (match_scratch:SI 0 "=d,d,d"))]
3269 "s390_match_ccmode (insn, CCL1mode)"
3274 [(set_attr "op_type" "RR,RX,RXY")])
3276 (define_insn "*addsi3_carry2_cc"
3277 [(set (reg CC_REGNUM)
3278 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3279 (match_operand:SI 2 "general_operand" "d,R,T"))
3281 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3282 (plus:SI (match_dup 1) (match_dup 2)))]
3283 "s390_match_ccmode (insn, CCL1mode)"
3288 [(set_attr "op_type" "RR,RX,RXY")])
3290 (define_insn "*addsi3_carry2_cconly"
3291 [(set (reg CC_REGNUM)
3292 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3293 (match_operand:SI 2 "general_operand" "d,R,T"))
3295 (clobber (match_scratch:SI 0 "=d,d,d"))]
3296 "s390_match_ccmode (insn, CCL1mode)"
3301 [(set_attr "op_type" "RR,RX,RXY")])
3303 (define_insn "*addsi3_cc"
3304 [(set (reg CC_REGNUM)
3305 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3306 (match_operand:SI 2 "general_operand" "d,R,T"))
3308 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3309 (plus:SI (match_dup 1) (match_dup 2)))]
3310 "s390_match_ccmode (insn, CCLmode)"
3315 [(set_attr "op_type" "RR,RX,RXY")])
3317 (define_insn "*addsi3_cconly"
3318 [(set (reg CC_REGNUM)
3319 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3320 (match_operand:SI 2 "general_operand" "d,R,T"))
3322 (clobber (match_scratch:SI 0 "=d,d,d"))]
3323 "s390_match_ccmode (insn, CCLmode)"
3328 [(set_attr "op_type" "RR,RX,RXY")])
3330 (define_insn "*addsi3_cconly2"
3331 [(set (reg CC_REGNUM)
3332 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3333 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3334 (clobber (match_scratch:SI 0 "=d,d,d"))]
3335 "s390_match_ccmode (insn, CCLmode)"
3340 [(set_attr "op_type" "RR,RX,RXY")])
3342 (define_insn "*addsi3_sign"
3343 [(set (match_operand:SI 0 "register_operand" "=d,d")
3344 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3345 (match_operand:SI 1 "register_operand" "0,0")))
3346 (clobber (reg:CC CC_REGNUM))]
3351 [(set_attr "op_type" "RX,RXY")])
3353 (define_insn "addsi3"
3354 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3355 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3356 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3357 (clobber (reg:CC CC_REGNUM))]
3364 [(set_attr "op_type" "RR,RI,RX,RXY")])
3367 ; add(df|sf)3 instruction pattern(s).
3370 (define_expand "add<mode>3"
3372 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3373 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3374 (match_operand:FPR 2 "general_operand" "f,R")))
3375 (clobber (reg:CC CC_REGNUM))])]
3379 (define_insn "*add<mode>3"
3380 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3381 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3382 (match_operand:FPR 2 "general_operand" "f,R")))
3383 (clobber (reg:CC CC_REGNUM))]
3384 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3388 [(set_attr "op_type" "RRE,RXE")
3389 (set_attr "type" "fsimp<mode>")])
3391 (define_insn "*add<mode>3_cc"
3392 [(set (reg CC_REGNUM)
3393 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3394 (match_operand:FPR 2 "general_operand" "f,R"))
3395 (match_operand:FPR 3 "const0_operand" "")))
3396 (set (match_operand:FPR 0 "register_operand" "=f,f")
3397 (plus:FPR (match_dup 1) (match_dup 2)))]
3398 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3402 [(set_attr "op_type" "RRE,RXE")
3403 (set_attr "type" "fsimp<mode>")])
3405 (define_insn "*add<mode>3_cconly"
3406 [(set (reg CC_REGNUM)
3407 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3408 (match_operand:FPR 2 "general_operand" "f,R"))
3409 (match_operand:FPR 3 "const0_operand" "")))
3410 (clobber (match_scratch:FPR 0 "=f,f"))]
3411 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3415 [(set_attr "op_type" "RRE,RXE")
3416 (set_attr "type" "fsimp<mode>")])
3418 (define_insn "*add<mode>3_ibm"
3419 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3420 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3421 (match_operand:FPR 2 "general_operand" "f,R")))
3422 (clobber (reg:CC CC_REGNUM))]
3423 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3427 [(set_attr "op_type" "RR,RX")
3428 (set_attr "type" "fsimp<mode>")])
3432 ;;- Subtract instructions.
3436 ; subti3 instruction pattern(s).
3439 (define_insn_and_split "subti3"
3440 [(set (match_operand:TI 0 "register_operand" "=&d")
3441 (minus:TI (match_operand:TI 1 "register_operand" "0")
3442 (match_operand:TI 2 "general_operand" "do") ) )
3443 (clobber (reg:CC CC_REGNUM))]
3446 "&& reload_completed"
3448 [(set (reg:CCL2 CC_REGNUM)
3449 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3451 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3453 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3454 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3455 (clobber (reg:CC CC_REGNUM))])]
3456 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3457 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3458 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3459 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3460 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3461 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3464 ; subdi3 instruction pattern(s).
3467 (define_insn "*subdi3_sign"
3468 [(set (match_operand:DI 0 "register_operand" "=d,d")
3469 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3470 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3471 (clobber (reg:CC CC_REGNUM))]
3476 [(set_attr "op_type" "RRE,RXY")])
3478 (define_insn "*subdi3_zero_cc"
3479 [(set (reg CC_REGNUM)
3480 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3481 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3483 (set (match_operand:DI 0 "register_operand" "=d,d")
3484 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3485 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3489 [(set_attr "op_type" "RRE,RXY")])
3491 (define_insn "*subdi3_zero_cconly"
3492 [(set (reg CC_REGNUM)
3493 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3494 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3496 (clobber (match_scratch:DI 0 "=d,d"))]
3497 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3501 [(set_attr "op_type" "RRE,RXY")])
3503 (define_insn "*subdi3_zero"
3504 [(set (match_operand:DI 0 "register_operand" "=d,d")
3505 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3506 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3507 (clobber (reg:CC CC_REGNUM))]
3512 [(set_attr "op_type" "RRE,RXY")])
3514 (define_insn "*subdi3_borrow_cc"
3515 [(set (reg CC_REGNUM)
3516 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3517 (match_operand:DI 2 "general_operand" "d,m"))
3519 (set (match_operand:DI 0 "register_operand" "=d,d")
3520 (minus:DI (match_dup 1) (match_dup 2)))]
3521 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3525 [(set_attr "op_type" "RRE,RXY")])
3527 (define_insn "*subdi3_borrow_cconly"
3528 [(set (reg CC_REGNUM)
3529 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3530 (match_operand:DI 2 "general_operand" "d,m"))
3532 (clobber (match_scratch:DI 0 "=d,d"))]
3533 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3537 [(set_attr "op_type" "RRE,RXY")])
3539 (define_insn "*subdi3_cc"
3540 [(set (reg CC_REGNUM)
3541 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3542 (match_operand:DI 2 "general_operand" "d,m"))
3544 (set (match_operand:DI 0 "register_operand" "=d,d")
3545 (minus:DI (match_dup 1) (match_dup 2)))]
3546 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3550 [(set_attr "op_type" "RRE,RXY")])
3552 (define_insn "*subdi3_cc2"
3553 [(set (reg CC_REGNUM)
3554 (compare (match_operand:DI 1 "register_operand" "0,0")
3555 (match_operand:DI 2 "general_operand" "d,m")))
3556 (set (match_operand:DI 0 "register_operand" "=d,d")
3557 (minus:DI (match_dup 1) (match_dup 2)))]
3558 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3562 [(set_attr "op_type" "RRE,RXY")])
3564 (define_insn "*subdi3_cconly"
3565 [(set (reg CC_REGNUM)
3566 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3567 (match_operand:DI 2 "general_operand" "d,m"))
3569 (clobber (match_scratch:DI 0 "=d,d"))]
3570 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3574 [(set_attr "op_type" "RRE,RXY")])
3576 (define_insn "*subdi3_cconly2"
3577 [(set (reg CC_REGNUM)
3578 (compare (match_operand:DI 1 "register_operand" "0,0")
3579 (match_operand:DI 2 "general_operand" "d,m")))
3580 (clobber (match_scratch:DI 0 "=d,d"))]
3581 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3585 [(set_attr "op_type" "RRE,RXY")])
3587 (define_insn "*subdi3_64"
3588 [(set (match_operand:DI 0 "register_operand" "=d,d")
3589 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3590 (match_operand:DI 2 "general_operand" "d,m") ) )
3591 (clobber (reg:CC CC_REGNUM))]
3596 [(set_attr "op_type" "RRE,RRE")])
3598 (define_insn_and_split "*subdi3_31z"
3599 [(set (match_operand:DI 0 "register_operand" "=&d")
3600 (minus:DI (match_operand:DI 1 "register_operand" "0")
3601 (match_operand:DI 2 "general_operand" "do") ) )
3602 (clobber (reg:CC CC_REGNUM))]
3603 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3605 "&& reload_completed"
3607 [(set (reg:CCL2 CC_REGNUM)
3608 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3610 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3612 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3613 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3614 (clobber (reg:CC CC_REGNUM))])]
3615 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3616 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3617 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3618 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3619 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3620 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3622 (define_insn_and_split "*subdi3_31"
3623 [(set (match_operand:DI 0 "register_operand" "=&d")
3624 (minus:DI (match_operand:DI 1 "register_operand" "0")
3625 (match_operand:DI 2 "general_operand" "do") ) )
3626 (clobber (reg:CC CC_REGNUM))]
3629 "&& reload_completed"
3631 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3632 (clobber (reg:CC CC_REGNUM))])
3634 [(set (reg:CCL2 CC_REGNUM)
3635 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3637 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3639 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
3641 (label_ref (match_dup 9))))
3643 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3644 (clobber (reg:CC CC_REGNUM))])
3646 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3647 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3648 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3649 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3650 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3651 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3652 operands[9] = gen_label_rtx ();")
3654 (define_expand "subdi3"
3656 [(set (match_operand:DI 0 "register_operand" "")
3657 (minus:DI (match_operand:DI 1 "register_operand" "")
3658 (match_operand:DI 2 "general_operand" "")))
3659 (clobber (reg:CC CC_REGNUM))])]
3664 ; subsi3 instruction pattern(s).
3667 (define_insn "*subsi3_borrow_cc"
3668 [(set (reg CC_REGNUM)
3669 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3670 (match_operand:SI 2 "general_operand" "d,R,T"))
3672 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3673 (minus:SI (match_dup 1) (match_dup 2)))]
3674 "s390_match_ccmode (insn, CCL2mode)"
3679 [(set_attr "op_type" "RR,RX,RXY")])
3681 (define_insn "*subsi3_borrow_cconly"
3682 [(set (reg CC_REGNUM)
3683 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3684 (match_operand:SI 2 "general_operand" "d,R,T"))
3686 (clobber (match_scratch:SI 0 "=d,d,d"))]
3687 "s390_match_ccmode (insn, CCL2mode)"
3692 [(set_attr "op_type" "RR,RX,RXY")])
3694 (define_insn "*subsi3_cc"
3695 [(set (reg CC_REGNUM)
3696 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3697 (match_operand:SI 2 "general_operand" "d,R,T"))
3699 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3700 (minus:SI (match_dup 1) (match_dup 2)))]
3701 "s390_match_ccmode (insn, CCLmode)"
3706 [(set_attr "op_type" "RR,RX,RXY")])
3708 (define_insn "*subsi3_cc2"
3709 [(set (reg CC_REGNUM)
3710 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3711 (match_operand:SI 2 "general_operand" "d,R,T")))
3712 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3713 (minus:SI (match_dup 1) (match_dup 2)))]
3714 "s390_match_ccmode (insn, CCL3mode)"
3719 [(set_attr "op_type" "RR,RX,RXY")])
3721 (define_insn "*subsi3_cconly"
3722 [(set (reg CC_REGNUM)
3723 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3724 (match_operand:SI 2 "general_operand" "d,R,T"))
3726 (clobber (match_scratch:SI 0 "=d,d,d"))]
3727 "s390_match_ccmode (insn, CCLmode)"
3732 [(set_attr "op_type" "RR,RX,RXY")])
3734 (define_insn "*subsi3_cconly2"
3735 [(set (reg CC_REGNUM)
3736 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3737 (match_operand:SI 2 "general_operand" "d,R,T")))
3738 (clobber (match_scratch:SI 0 "=d,d,d"))]
3739 "s390_match_ccmode (insn, CCL3mode)"
3744 [(set_attr "op_type" "RR,RX,RXY")])
3746 (define_insn "*subsi3_sign"
3747 [(set (match_operand:SI 0 "register_operand" "=d,d")
3748 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3749 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3750 (clobber (reg:CC CC_REGNUM))]
3755 [(set_attr "op_type" "RX,RXY")])
3757 (define_insn "subsi3"
3758 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3759 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3760 (match_operand:SI 2 "general_operand" "d,R,T")))
3761 (clobber (reg:CC CC_REGNUM))]
3767 [(set_attr "op_type" "RR,RX,RXY")])
3771 ; sub(df|sf)3 instruction pattern(s).
3774 (define_expand "sub<mode>3"
3776 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3777 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3778 (match_operand:FPR 2 "general_operand" "f,R")))
3779 (clobber (reg:CC CC_REGNUM))])]
3783 (define_insn "*sub<mode>3"
3784 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3785 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3786 (match_operand:FPR 2 "general_operand" "f,R")))
3787 (clobber (reg:CC CC_REGNUM))]
3788 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3792 [(set_attr "op_type" "RRE,RXE")
3793 (set_attr "type" "fsimp<mode>")])
3795 (define_insn "*sub<mode>3_cc"
3796 [(set (reg CC_REGNUM)
3797 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3798 (match_operand:FPR 2 "general_operand" "f,R"))
3799 (match_operand:FPR 3 "const0_operand" "")))
3800 (set (match_operand:FPR 0 "register_operand" "=f,f")
3801 (minus:FPR (match_dup 1) (match_dup 2)))]
3802 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3806 [(set_attr "op_type" "RRE,RXE")
3807 (set_attr "type" "fsimp<mode>")])
3809 (define_insn "*sub<mode>3_cconly"
3810 [(set (reg CC_REGNUM)
3811 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3812 (match_operand:FPR 2 "general_operand" "f,R"))
3813 (match_operand:FPR 3 "const0_operand" "")))
3814 (clobber (match_scratch:FPR 0 "=f,f"))]
3815 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3819 [(set_attr "op_type" "RRE,RXE")
3820 (set_attr "type" "fsimp<mode>")])
3822 (define_insn "*sub<mode>3_ibm"
3823 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3824 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3825 (match_operand:FPR 2 "general_operand" "f,R")))
3826 (clobber (reg:CC CC_REGNUM))]
3827 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3831 [(set_attr "op_type" "RR,RX")
3832 (set_attr "type" "fsimp<mode>")])
3836 ;;- Conditional add/subtract instructions.
3840 ; add(di|si)cc instruction pattern(s).
3843 (define_insn "*add<mode>3_alc_cc"
3844 [(set (reg CC_REGNUM)
3846 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3847 (match_operand:GPR 2 "general_operand" "d,m"))
3848 (match_operand:GPR 3 "s390_alc_comparison" ""))
3850 (set (match_operand:GPR 0 "register_operand" "=d,d")
3851 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3852 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3856 [(set_attr "op_type" "RRE,RXY")])
3858 (define_insn "*add<mode>3_alc"
3859 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3860 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3861 (match_operand:GPR 2 "general_operand" "d,m"))
3862 (match_operand:GPR 3 "s390_alc_comparison" "")))
3863 (clobber (reg:CC CC_REGNUM))]
3868 [(set_attr "op_type" "RRE,RXY")])
3870 (define_insn "*sub<mode>3_slb_cc"
3871 [(set (reg CC_REGNUM)
3873 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3874 (match_operand:GPR 2 "general_operand" "d,m"))
3875 (match_operand:GPR 3 "s390_slb_comparison" ""))
3877 (set (match_operand:GPR 0 "register_operand" "=d,d")
3878 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3879 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3883 [(set_attr "op_type" "RRE,RXY")])
3885 (define_insn "*sub<mode>3_slb"
3886 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3887 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3888 (match_operand:GPR 2 "general_operand" "d,m"))
3889 (match_operand:GPR 3 "s390_slb_comparison" "")))
3890 (clobber (reg:CC CC_REGNUM))]
3895 [(set_attr "op_type" "RRE,RXY")])
3897 (define_expand "add<mode>cc"
3898 [(match_operand:GPR 0 "register_operand" "")
3899 (match_operand 1 "comparison_operator" "")
3900 (match_operand:GPR 2 "register_operand" "")
3901 (match_operand:GPR 3 "const_int_operand" "")]
3903 "if (!s390_expand_addcc (GET_CODE (operands[1]),
3904 s390_compare_op0, s390_compare_op1,
3905 operands[0], operands[2],
3906 operands[3])) FAIL; DONE;")
3909 ; scond instruction pattern(s).
3912 (define_insn_and_split "*scond<mode>"
3913 [(set (match_operand:GPR 0 "register_operand" "=&d")
3914 (match_operand:GPR 1 "s390_alc_comparison" ""))
3915 (clobber (reg:CC CC_REGNUM))]
3918 "&& reload_completed"
3919 [(set (match_dup 0) (const_int 0))
3921 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
3923 (clobber (reg:CC CC_REGNUM))])]
3926 (define_insn_and_split "*scond<mode>_neg"
3927 [(set (match_operand:GPR 0 "register_operand" "=&d")
3928 (match_operand:GPR 1 "s390_slb_comparison" ""))
3929 (clobber (reg:CC CC_REGNUM))]
3932 "&& reload_completed"
3933 [(set (match_dup 0) (const_int 0))
3935 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
3937 (clobber (reg:CC CC_REGNUM))])
3939 [(set (match_dup 0) (neg:GPR (match_dup 0)))
3940 (clobber (reg:CC CC_REGNUM))])]
3944 (define_expand "s<code>"
3945 [(set (match_operand:SI 0 "register_operand" "")
3946 (SCOND (match_dup 0)
3949 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
3950 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
3954 ;;- Multiply instructions.
3958 ; muldi3 instruction pattern(s).
3961 (define_insn "*muldi3_sign"
3962 [(set (match_operand:DI 0 "register_operand" "=d,d")
3963 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3964 (match_operand:DI 1 "register_operand" "0,0")))]
3969 [(set_attr "op_type" "RRE,RXY")
3970 (set_attr "type" "imuldi")])
3972 (define_insn "muldi3"
3973 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3974 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3975 (match_operand:DI 2 "general_operand" "d,K,m")))]
3981 [(set_attr "op_type" "RRE,RI,RXY")
3982 (set_attr "type" "imuldi")])
3985 ; mulsi3 instruction pattern(s).
3988 (define_insn "*mulsi3_sign"
3989 [(set (match_operand:SI 0 "register_operand" "=d")
3990 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
3991 (match_operand:SI 1 "register_operand" "0")))]
3994 [(set_attr "op_type" "RX")
3995 (set_attr "type" "imulhi")])
3997 (define_insn "mulsi3"
3998 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3999 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4000 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4007 [(set_attr "op_type" "RRE,RI,RX,RXY")
4008 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4011 ; mulsidi3 instruction pattern(s).
4014 (define_insn "mulsidi3"
4015 [(set (match_operand:DI 0 "register_operand" "=d,d")
4016 (mult:DI (sign_extend:DI
4017 (match_operand:SI 1 "register_operand" "%0,0"))
4019 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4024 [(set_attr "op_type" "RR,RX")
4025 (set_attr "type" "imulsi")])
4028 ; umulsidi3 instruction pattern(s).
4031 (define_insn "umulsidi3"
4032 [(set (match_operand:DI 0 "register_operand" "=d,d")
4033 (mult:DI (zero_extend:DI
4034 (match_operand:SI 1 "register_operand" "%0,0"))
4036 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4037 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4041 [(set_attr "op_type" "RRE,RXY")
4042 (set_attr "type" "imulsi")])
4045 ; mul(df|sf)3 instruction pattern(s).
4048 (define_expand "mul<mode>3"
4049 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4050 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4051 (match_operand:FPR 2 "general_operand" "f,R")))]
4055 (define_insn "*mul<mode>3"
4056 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4057 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4058 (match_operand:FPR 2 "general_operand" "f,R")))]
4059 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4063 [(set_attr "op_type" "RRE,RXE")
4064 (set_attr "type" "fmul<mode>")])
4066 (define_insn "*mul<mode>3_ibm"
4067 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4068 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4069 (match_operand:FPR 2 "general_operand" "f,R")))]
4070 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4074 [(set_attr "op_type" "RR,RX")
4075 (set_attr "type" "fmul<mode>")])
4077 (define_insn "*fmadd<mode>"
4078 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4079 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4080 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4081 (match_operand:FPR 3 "register_operand" "0,0")))]
4082 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4086 [(set_attr "op_type" "RRE,RXE")
4087 (set_attr "type" "fmul<mode>")])
4089 (define_insn "*fmsub<mode>"
4090 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4091 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4092 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4093 (match_operand:FPR 3 "register_operand" "0,0")))]
4094 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4098 [(set_attr "op_type" "RRE,RXE")
4099 (set_attr "type" "fmul<mode>")])
4102 ;;- Divide and modulo instructions.
4106 ; divmoddi4 instruction pattern(s).
4109 (define_expand "divmoddi4"
4110 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4111 (div:DI (match_operand:DI 1 "register_operand" "")
4112 (match_operand:DI 2 "general_operand" "")))
4113 (set (match_operand:DI 3 "general_operand" "")
4114 (mod:DI (match_dup 1) (match_dup 2)))])
4115 (clobber (match_dup 4))]
4118 rtx insn, div_equal, mod_equal;
4120 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4121 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4123 operands[4] = gen_reg_rtx(TImode);
4124 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4126 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4128 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4130 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4132 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4137 (define_insn "divmodtidi3"
4138 [(set (match_operand:TI 0 "register_operand" "=d,d")
4142 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4143 (match_operand:DI 2 "general_operand" "d,m")))
4145 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4150 [(set_attr "op_type" "RRE,RXY")
4151 (set_attr "type" "idiv")])
4153 (define_insn "divmodtisi3"
4154 [(set (match_operand:TI 0 "register_operand" "=d,d")
4158 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4160 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4163 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4168 [(set_attr "op_type" "RRE,RXY")
4169 (set_attr "type" "idiv")])
4172 ; udivmoddi4 instruction pattern(s).
4175 (define_expand "udivmoddi4"
4176 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4177 (udiv:DI (match_operand:DI 1 "general_operand" "")
4178 (match_operand:DI 2 "nonimmediate_operand" "")))
4179 (set (match_operand:DI 3 "general_operand" "")
4180 (umod:DI (match_dup 1) (match_dup 2)))])
4181 (clobber (match_dup 4))]
4184 rtx insn, div_equal, mod_equal, equal;
4186 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4187 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4188 equal = gen_rtx_IOR (TImode,
4189 gen_rtx_ASHIFT (TImode,
4190 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4192 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4194 operands[4] = gen_reg_rtx(TImode);
4195 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4196 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4197 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4198 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4200 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4202 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4204 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4206 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4208 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4213 (define_insn "udivmodtidi3"
4214 [(set (match_operand:TI 0 "register_operand" "=d,d")
4219 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4221 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4225 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4230 [(set_attr "op_type" "RRE,RXY")
4231 (set_attr "type" "idiv")])
4234 ; divmodsi4 instruction pattern(s).
4237 (define_expand "divmodsi4"
4238 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4239 (div:SI (match_operand:SI 1 "general_operand" "")
4240 (match_operand:SI 2 "nonimmediate_operand" "")))
4241 (set (match_operand:SI 3 "general_operand" "")
4242 (mod:SI (match_dup 1) (match_dup 2)))])
4243 (clobber (match_dup 4))]
4246 rtx insn, div_equal, mod_equal, equal;
4248 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4249 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4250 equal = gen_rtx_IOR (DImode,
4251 gen_rtx_ASHIFT (DImode,
4252 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4254 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4256 operands[4] = gen_reg_rtx(DImode);
4257 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4258 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4260 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4262 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4264 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4266 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4268 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4273 (define_insn "divmoddisi3"
4274 [(set (match_operand:DI 0 "register_operand" "=d,d")
4279 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4281 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4285 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4290 [(set_attr "op_type" "RR,RX")
4291 (set_attr "type" "idiv")])
4294 ; udivsi3 and umodsi3 instruction pattern(s).
4297 (define_expand "udivmodsi4"
4298 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4299 (udiv:SI (match_operand:SI 1 "general_operand" "")
4300 (match_operand:SI 2 "nonimmediate_operand" "")))
4301 (set (match_operand:SI 3 "general_operand" "")
4302 (umod:SI (match_dup 1) (match_dup 2)))])
4303 (clobber (match_dup 4))]
4304 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4306 rtx insn, div_equal, mod_equal, equal;
4308 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4309 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4310 equal = gen_rtx_IOR (DImode,
4311 gen_rtx_ASHIFT (DImode,
4312 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4314 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4316 operands[4] = gen_reg_rtx(DImode);
4317 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4318 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4319 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4320 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4322 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4324 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4326 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4328 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4330 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4335 (define_insn "udivmoddisi3"
4336 [(set (match_operand:DI 0 "register_operand" "=d,d")
4341 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4343 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4347 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4348 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4352 [(set_attr "op_type" "RRE,RXY")
4353 (set_attr "type" "idiv")])
4355 (define_expand "udivsi3"
4356 [(set (match_operand:SI 0 "register_operand" "=d")
4357 (udiv:SI (match_operand:SI 1 "general_operand" "")
4358 (match_operand:SI 2 "general_operand" "")))
4359 (clobber (match_dup 3))]
4360 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4362 rtx insn, udiv_equal, umod_equal, equal;
4364 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4365 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4366 equal = gen_rtx_IOR (DImode,
4367 gen_rtx_ASHIFT (DImode,
4368 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4370 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4372 operands[3] = gen_reg_rtx (DImode);
4374 if (CONSTANT_P (operands[2]))
4376 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4378 rtx label1 = gen_label_rtx ();
4380 operands[1] = make_safe_from (operands[1], operands[0]);
4381 emit_move_insn (operands[0], const0_rtx);
4382 emit_insn (gen_cmpsi (operands[1], operands[2]));
4383 emit_jump_insn (gen_bltu (label1));
4384 emit_move_insn (operands[0], const1_rtx);
4385 emit_label (label1);
4389 operands[2] = force_reg (SImode, operands[2]);
4390 operands[2] = make_safe_from (operands[2], operands[0]);
4392 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4393 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4396 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4398 insn = emit_move_insn (operands[0],
4399 gen_lowpart (SImode, operands[3]));
4401 gen_rtx_EXPR_LIST (REG_EQUAL,
4402 udiv_equal, REG_NOTES (insn));
4407 rtx label1 = gen_label_rtx ();
4408 rtx label2 = gen_label_rtx ();
4409 rtx label3 = gen_label_rtx ();
4411 operands[1] = force_reg (SImode, operands[1]);
4412 operands[1] = make_safe_from (operands[1], operands[0]);
4413 operands[2] = force_reg (SImode, operands[2]);
4414 operands[2] = make_safe_from (operands[2], operands[0]);
4416 emit_move_insn (operands[0], const0_rtx);
4417 emit_insn (gen_cmpsi (operands[2], operands[1]));
4418 emit_jump_insn (gen_bgtu (label3));
4419 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4420 emit_jump_insn (gen_blt (label2));
4421 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4422 emit_jump_insn (gen_beq (label1));
4423 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4424 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4427 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4429 insn = emit_move_insn (operands[0],
4430 gen_lowpart (SImode, operands[3]));
4432 gen_rtx_EXPR_LIST (REG_EQUAL,
4433 udiv_equal, REG_NOTES (insn));
4435 emit_label (label1);
4436 emit_move_insn (operands[0], operands[1]);
4438 emit_label (label2);
4439 emit_move_insn (operands[0], const1_rtx);
4440 emit_label (label3);
4442 emit_move_insn (operands[0], operands[0]);
4446 (define_expand "umodsi3"
4447 [(set (match_operand:SI 0 "register_operand" "=d")
4448 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4449 (match_operand:SI 2 "nonimmediate_operand" "")))
4450 (clobber (match_dup 3))]
4451 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4453 rtx insn, udiv_equal, umod_equal, equal;
4455 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4456 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4457 equal = gen_rtx_IOR (DImode,
4458 gen_rtx_ASHIFT (DImode,
4459 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4461 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4463 operands[3] = gen_reg_rtx (DImode);
4465 if (CONSTANT_P (operands[2]))
4467 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4469 rtx label1 = gen_label_rtx ();
4471 operands[1] = make_safe_from (operands[1], operands[0]);
4472 emit_move_insn (operands[0], operands[1]);
4473 emit_insn (gen_cmpsi (operands[0], operands[2]));
4474 emit_jump_insn (gen_bltu (label1));
4475 emit_insn (gen_abssi2 (operands[0], operands[2]));
4476 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4477 emit_label (label1);
4481 operands[2] = force_reg (SImode, operands[2]);
4482 operands[2] = make_safe_from (operands[2], operands[0]);
4484 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4485 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4488 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4490 insn = emit_move_insn (operands[0],
4491 gen_highpart (SImode, operands[3]));
4493 gen_rtx_EXPR_LIST (REG_EQUAL,
4494 umod_equal, REG_NOTES (insn));
4499 rtx label1 = gen_label_rtx ();
4500 rtx label2 = gen_label_rtx ();
4501 rtx label3 = gen_label_rtx ();
4503 operands[1] = force_reg (SImode, operands[1]);
4504 operands[1] = make_safe_from (operands[1], operands[0]);
4505 operands[2] = force_reg (SImode, operands[2]);
4506 operands[2] = make_safe_from (operands[2], operands[0]);
4508 emit_move_insn(operands[0], operands[1]);
4509 emit_insn (gen_cmpsi (operands[2], operands[1]));
4510 emit_jump_insn (gen_bgtu (label3));
4511 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4512 emit_jump_insn (gen_blt (label2));
4513 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4514 emit_jump_insn (gen_beq (label1));
4515 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4516 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4519 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4521 insn = emit_move_insn (operands[0],
4522 gen_highpart (SImode, operands[3]));
4524 gen_rtx_EXPR_LIST (REG_EQUAL,
4525 umod_equal, REG_NOTES (insn));
4527 emit_label (label1);
4528 emit_move_insn (operands[0], const0_rtx);
4530 emit_label (label2);
4531 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4532 emit_label (label3);
4538 ; div(df|sf)3 instruction pattern(s).
4541 (define_expand "div<mode>3"
4542 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4543 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4544 (match_operand:FPR 2 "general_operand" "f,R")))]
4548 (define_insn "*div<mode>3"
4549 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4550 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4551 (match_operand:FPR 2 "general_operand" "f,R")))]
4552 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4556 [(set_attr "op_type" "RRE,RXE")
4557 (set_attr "type" "fdiv<mode>")])
4559 (define_insn "*div<mode>3_ibm"
4560 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4561 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4562 (match_operand:FPR 2 "general_operand" "f,R")))]
4563 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4567 [(set_attr "op_type" "RR,RX")
4568 (set_attr "type" "fdiv<mode>")])
4572 ;;- And instructions.
4575 (define_expand "and<mode>3"
4576 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4577 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4578 (match_operand:INT 2 "general_operand" "")))
4579 (clobber (reg:CC CC_REGNUM))]
4581 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4584 ; anddi3 instruction pattern(s).
4587 (define_insn "*anddi3_cc"
4588 [(set (reg CC_REGNUM)
4589 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4590 (match_operand:DI 2 "general_operand" "d,m"))
4592 (set (match_operand:DI 0 "register_operand" "=d,d")
4593 (and:DI (match_dup 1) (match_dup 2)))]
4594 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4598 [(set_attr "op_type" "RRE,RXY")])
4600 (define_insn "*anddi3_cconly"
4601 [(set (reg CC_REGNUM)
4602 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4603 (match_operand:DI 2 "general_operand" "d,m"))
4605 (clobber (match_scratch:DI 0 "=d,d"))]
4606 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4607 /* Do not steal TM patterns. */
4608 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4612 [(set_attr "op_type" "RRE,RXY")])
4614 (define_insn "*anddi3"
4615 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4616 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4617 "%d,o,0,0,0,0,0,0,0,0")
4618 (match_operand:DI 2 "general_operand"
4619 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4620 (clobber (reg:CC CC_REGNUM))]
4621 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4633 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4636 [(set (match_operand:DI 0 "s_operand" "")
4637 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4638 (clobber (reg:CC CC_REGNUM))]
4641 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4642 (clobber (reg:CC CC_REGNUM))])]
4643 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4647 ; andsi3 instruction pattern(s).
4650 (define_insn "*andsi3_cc"
4651 [(set (reg CC_REGNUM)
4652 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4653 (match_operand:SI 2 "general_operand" "d,R,T"))
4655 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4656 (and:SI (match_dup 1) (match_dup 2)))]
4657 "s390_match_ccmode(insn, CCTmode)"
4662 [(set_attr "op_type" "RR,RX,RXY")])
4664 (define_insn "*andsi3_cconly"
4665 [(set (reg CC_REGNUM)
4666 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4667 (match_operand:SI 2 "general_operand" "d,R,T"))
4669 (clobber (match_scratch:SI 0 "=d,d,d"))]
4670 "s390_match_ccmode(insn, CCTmode)
4671 /* Do not steal TM patterns. */
4672 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
4677 [(set_attr "op_type" "RR,RX,RXY")])
4679 (define_insn "*andsi3_zarch"
4680 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
4681 (and:SI (match_operand:SI 1 "nonimmediate_operand"
4682 "%d,o,0,0,0,0,0,0,0")
4683 (match_operand:SI 2 "general_operand"
4684 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
4685 (clobber (reg:CC CC_REGNUM))]
4686 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4697 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
4699 (define_insn "*andsi3_esa"
4700 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4701 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4702 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
4703 (clobber (reg:CC CC_REGNUM))]
4704 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4710 [(set_attr "op_type" "RR,RX,SI,SS")])
4713 [(set (match_operand:SI 0 "s_operand" "")
4714 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4715 (clobber (reg:CC CC_REGNUM))]
4718 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4719 (clobber (reg:CC CC_REGNUM))])]
4720 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4723 ; andhi3 instruction pattern(s).
4726 (define_insn "*andhi3_zarch"
4727 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4728 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4729 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
4730 (clobber (reg:CC CC_REGNUM))]
4731 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4737 [(set_attr "op_type" "RR,RI,SI,SS")])
4739 (define_insn "*andhi3_esa"
4740 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
4741 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
4742 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
4743 (clobber (reg:CC CC_REGNUM))]
4744 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4749 [(set_attr "op_type" "RR,SI,SS")])
4752 [(set (match_operand:HI 0 "s_operand" "")
4753 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
4754 (clobber (reg:CC CC_REGNUM))]
4757 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4758 (clobber (reg:CC CC_REGNUM))])]
4759 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4762 ; andqi3 instruction pattern(s).
4765 (define_insn "*andqi3_zarch"
4766 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
4767 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
4768 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
4769 (clobber (reg:CC CC_REGNUM))]
4770 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4777 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
4779 (define_insn "*andqi3_esa"
4780 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
4781 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
4782 (match_operand:QI 2 "general_operand" "d,n,Q")))
4783 (clobber (reg:CC CC_REGNUM))]
4784 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4789 [(set_attr "op_type" "RR,SI,SS")])
4792 ; Block and (NC) patterns.
4796 [(set (match_operand:BLK 0 "memory_operand" "=Q")
4797 (and:BLK (match_dup 0)
4798 (match_operand:BLK 1 "memory_operand" "Q")))
4799 (use (match_operand 2 "const_int_operand" "n"))
4800 (clobber (reg:CC CC_REGNUM))]
4801 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
4802 "nc\t%O0(%2,%R0),%S1"
4803 [(set_attr "op_type" "SS")])
4806 [(set (match_operand 0 "memory_operand" "")
4808 (match_operand 1 "memory_operand" "")))
4809 (clobber (reg:CC CC_REGNUM))]
4811 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4812 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
4814 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
4816 (clobber (reg:CC CC_REGNUM))])]
4818 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
4819 operands[0] = adjust_address (operands[0], BLKmode, 0);
4820 operands[1] = adjust_address (operands[1], BLKmode, 0);
4825 [(set (match_operand:BLK 0 "memory_operand" "")
4826 (and:BLK (match_dup 0)
4827 (match_operand:BLK 1 "memory_operand" "")))
4828 (use (match_operand 2 "const_int_operand" ""))
4829 (clobber (reg:CC CC_REGNUM))])
4831 [(set (match_operand:BLK 3 "memory_operand" "")
4832 (and:BLK (match_dup 3)
4833 (match_operand:BLK 4 "memory_operand" "")))
4834 (use (match_operand 5 "const_int_operand" ""))
4835 (clobber (reg:CC CC_REGNUM))])]
4836 "s390_offset_p (operands[0], operands[3], operands[2])
4837 && s390_offset_p (operands[1], operands[4], operands[2])
4838 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
4840 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
4842 (clobber (reg:CC CC_REGNUM))])]
4843 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
4844 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
4845 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
4849 ;;- Bit set (inclusive or) instructions.
4852 (define_expand "ior<mode>3"
4853 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4854 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
4855 (match_operand:INT 2 "general_operand" "")))
4856 (clobber (reg:CC CC_REGNUM))]
4858 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
4861 ; iordi3 instruction pattern(s).
4864 (define_insn "*iordi3_cc"
4865 [(set (reg CC_REGNUM)
4866 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4867 (match_operand:DI 2 "general_operand" "d,m"))
4869 (set (match_operand:DI 0 "register_operand" "=d,d")
4870 (ior:DI (match_dup 1) (match_dup 2)))]
4871 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4875 [(set_attr "op_type" "RRE,RXY")])
4877 (define_insn "*iordi3_cconly"
4878 [(set (reg CC_REGNUM)
4879 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4880 (match_operand:DI 2 "general_operand" "d,m"))
4882 (clobber (match_scratch:DI 0 "=d,d"))]
4883 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4887 [(set_attr "op_type" "RRE,RXY")])
4889 (define_insn "*iordi3"
4890 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
4891 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
4892 (match_operand:DI 2 "general_operand"
4893 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
4894 (clobber (reg:CC CC_REGNUM))]
4895 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4905 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
4908 [(set (match_operand:DI 0 "s_operand" "")
4909 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4910 (clobber (reg:CC CC_REGNUM))]
4913 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
4914 (clobber (reg:CC CC_REGNUM))])]
4915 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
4918 ; iorsi3 instruction pattern(s).
4921 (define_insn "*iorsi3_cc"
4922 [(set (reg CC_REGNUM)
4923 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4924 (match_operand:SI 2 "general_operand" "d,R,T"))
4926 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4927 (ior:SI (match_dup 1) (match_dup 2)))]
4928 "s390_match_ccmode(insn, CCTmode)"
4933 [(set_attr "op_type" "RR,RX,RXY")])
4935 (define_insn "*iorsi3_cconly"
4936 [(set (reg CC_REGNUM)
4937 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4938 (match_operand:SI 2 "general_operand" "d,R,T"))
4940 (clobber (match_scratch:SI 0 "=d,d,d"))]
4941 "s390_match_ccmode(insn, CCTmode)"
4946 [(set_attr "op_type" "RR,RX,RXY")])
4948 (define_insn "*iorsi3_zarch"
4949 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
4950 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
4951 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
4952 (clobber (reg:CC CC_REGNUM))]
4953 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4962 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
4964 (define_insn "*iorsi3_esa"
4965 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4966 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4967 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
4968 (clobber (reg:CC CC_REGNUM))]
4969 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4975 [(set_attr "op_type" "RR,RX,SI,SS")])
4978 [(set (match_operand:SI 0 "s_operand" "")
4979 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4980 (clobber (reg:CC CC_REGNUM))]
4983 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
4984 (clobber (reg:CC CC_REGNUM))])]
4985 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
4988 ; iorhi3 instruction pattern(s).
4991 (define_insn "*iorhi3_zarch"
4992 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4993 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4994 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
4995 (clobber (reg:CC CC_REGNUM))]
4996 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5002 [(set_attr "op_type" "RR,RI,SI,SS")])
5004 (define_insn "*iorhi3_esa"
5005 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5006 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5007 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5008 (clobber (reg:CC CC_REGNUM))]
5009 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5014 [(set_attr "op_type" "RR,SI,SS")])
5017 [(set (match_operand:HI 0 "s_operand" "")
5018 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5019 (clobber (reg:CC CC_REGNUM))]
5022 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5023 (clobber (reg:CC CC_REGNUM))])]
5024 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5027 ; iorqi3 instruction pattern(s).
5030 (define_insn "*iorqi3_zarch"
5031 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5032 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5033 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5034 (clobber (reg:CC CC_REGNUM))]
5035 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5042 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5044 (define_insn "*iorqi3_esa"
5045 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5046 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5047 (match_operand:QI 2 "general_operand" "d,n,Q")))
5048 (clobber (reg:CC CC_REGNUM))]
5049 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5054 [(set_attr "op_type" "RR,SI,SS")])
5057 ; Block inclusive or (OC) patterns.
5061 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5062 (ior:BLK (match_dup 0)
5063 (match_operand:BLK 1 "memory_operand" "Q")))
5064 (use (match_operand 2 "const_int_operand" "n"))
5065 (clobber (reg:CC CC_REGNUM))]
5066 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5067 "oc\t%O0(%2,%R0),%S1"
5068 [(set_attr "op_type" "SS")])
5071 [(set (match_operand 0 "memory_operand" "")
5073 (match_operand 1 "memory_operand" "")))
5074 (clobber (reg:CC CC_REGNUM))]
5076 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5077 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5079 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5081 (clobber (reg:CC CC_REGNUM))])]
5083 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5084 operands[0] = adjust_address (operands[0], BLKmode, 0);
5085 operands[1] = adjust_address (operands[1], BLKmode, 0);
5090 [(set (match_operand:BLK 0 "memory_operand" "")
5091 (ior:BLK (match_dup 0)
5092 (match_operand:BLK 1 "memory_operand" "")))
5093 (use (match_operand 2 "const_int_operand" ""))
5094 (clobber (reg:CC CC_REGNUM))])
5096 [(set (match_operand:BLK 3 "memory_operand" "")
5097 (ior:BLK (match_dup 3)
5098 (match_operand:BLK 4 "memory_operand" "")))
5099 (use (match_operand 5 "const_int_operand" ""))
5100 (clobber (reg:CC CC_REGNUM))])]
5101 "s390_offset_p (operands[0], operands[3], operands[2])
5102 && s390_offset_p (operands[1], operands[4], operands[2])
5103 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5105 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5107 (clobber (reg:CC CC_REGNUM))])]
5108 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5109 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5110 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5114 ;;- Xor instructions.
5117 (define_expand "xor<mode>3"
5118 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5119 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5120 (match_operand:INT 2 "general_operand" "")))
5121 (clobber (reg:CC CC_REGNUM))]
5123 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5126 ; xordi3 instruction pattern(s).
5129 (define_insn "*xordi3_cc"
5130 [(set (reg CC_REGNUM)
5131 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5132 (match_operand:DI 2 "general_operand" "d,m"))
5134 (set (match_operand:DI 0 "register_operand" "=d,d")
5135 (xor:DI (match_dup 1) (match_dup 2)))]
5136 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5140 [(set_attr "op_type" "RRE,RXY")])
5142 (define_insn "*xordi3_cconly"
5143 [(set (reg CC_REGNUM)
5144 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5145 (match_operand:DI 2 "general_operand" "d,m"))
5147 (clobber (match_scratch:DI 0 "=d,d"))]
5148 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5152 [(set_attr "op_type" "RRE,RXY")])
5154 (define_insn "*xordi3"
5155 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5156 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5157 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5158 (clobber (reg:CC CC_REGNUM))]
5159 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5165 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5168 [(set (match_operand:DI 0 "s_operand" "")
5169 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5170 (clobber (reg:CC CC_REGNUM))]
5173 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5174 (clobber (reg:CC CC_REGNUM))])]
5175 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5178 ; xorsi3 instruction pattern(s).
5181 (define_insn "*xorsi3_cc"
5182 [(set (reg CC_REGNUM)
5183 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5184 (match_operand:SI 2 "general_operand" "d,R,T"))
5186 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5187 (xor:SI (match_dup 1) (match_dup 2)))]
5188 "s390_match_ccmode(insn, CCTmode)"
5193 [(set_attr "op_type" "RR,RX,RXY")])
5195 (define_insn "*xorsi3_cconly"
5196 [(set (reg CC_REGNUM)
5197 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5198 (match_operand:SI 2 "general_operand" "d,R,T"))
5200 (clobber (match_scratch:SI 0 "=d,d,d"))]
5201 "s390_match_ccmode(insn, CCTmode)"
5206 [(set_attr "op_type" "RR,RX,RXY")])
5208 (define_insn "*xorsi3"
5209 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5210 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5211 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5212 (clobber (reg:CC CC_REGNUM))]
5213 "s390_logical_operator_ok_p (operands)"
5220 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5223 [(set (match_operand:SI 0 "s_operand" "")
5224 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5225 (clobber (reg:CC CC_REGNUM))]
5228 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5229 (clobber (reg:CC CC_REGNUM))])]
5230 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5233 ; xorhi3 instruction pattern(s).
5236 (define_insn "*xorhi3"
5237 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5238 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5239 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5240 (clobber (reg:CC CC_REGNUM))]
5241 "s390_logical_operator_ok_p (operands)"
5246 [(set_attr "op_type" "RR,SI,SS")])
5249 [(set (match_operand:HI 0 "s_operand" "")
5250 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5251 (clobber (reg:CC CC_REGNUM))]
5254 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5255 (clobber (reg:CC CC_REGNUM))])]
5256 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5259 ; xorqi3 instruction pattern(s).
5262 (define_insn "*xorqi3"
5263 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5264 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5265 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5266 (clobber (reg:CC CC_REGNUM))]
5267 "s390_logical_operator_ok_p (operands)"
5273 [(set_attr "op_type" "RR,SI,SIY,SS")])
5276 ; Block exclusive or (XC) patterns.
5280 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5281 (xor:BLK (match_dup 0)
5282 (match_operand:BLK 1 "memory_operand" "Q")))
5283 (use (match_operand 2 "const_int_operand" "n"))
5284 (clobber (reg:CC CC_REGNUM))]
5285 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5286 "xc\t%O0(%2,%R0),%S1"
5287 [(set_attr "op_type" "SS")])
5290 [(set (match_operand 0 "memory_operand" "")
5292 (match_operand 1 "memory_operand" "")))
5293 (clobber (reg:CC CC_REGNUM))]
5295 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5296 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5298 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5300 (clobber (reg:CC CC_REGNUM))])]
5302 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5303 operands[0] = adjust_address (operands[0], BLKmode, 0);
5304 operands[1] = adjust_address (operands[1], BLKmode, 0);
5309 [(set (match_operand:BLK 0 "memory_operand" "")
5310 (xor:BLK (match_dup 0)
5311 (match_operand:BLK 1 "memory_operand" "")))
5312 (use (match_operand 2 "const_int_operand" ""))
5313 (clobber (reg:CC CC_REGNUM))])
5315 [(set (match_operand:BLK 3 "memory_operand" "")
5316 (xor:BLK (match_dup 3)
5317 (match_operand:BLK 4 "memory_operand" "")))
5318 (use (match_operand 5 "const_int_operand" ""))
5319 (clobber (reg:CC CC_REGNUM))])]
5320 "s390_offset_p (operands[0], operands[3], operands[2])
5321 && s390_offset_p (operands[1], operands[4], operands[2])
5322 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5324 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5326 (clobber (reg:CC CC_REGNUM))])]
5327 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5328 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5329 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5332 ; Block xor (XC) patterns with src == dest.
5335 (define_insn "*xc_zero"
5336 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5338 (use (match_operand 1 "const_int_operand" "n"))
5339 (clobber (reg:CC CC_REGNUM))]
5340 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5341 "xc\t%O0(%1,%R0),%S0"
5342 [(set_attr "op_type" "SS")])
5346 [(set (match_operand:BLK 0 "memory_operand" "")
5348 (use (match_operand 1 "const_int_operand" ""))
5349 (clobber (reg:CC CC_REGNUM))])
5351 [(set (match_operand:BLK 2 "memory_operand" "")
5353 (use (match_operand 3 "const_int_operand" ""))
5354 (clobber (reg:CC CC_REGNUM))])]
5355 "s390_offset_p (operands[0], operands[2], operands[1])
5356 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5358 [(set (match_dup 4) (const_int 0))
5360 (clobber (reg:CC CC_REGNUM))])]
5361 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5362 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5366 ;;- Negate instructions.
5370 ; neg(di|si)2 instruction pattern(s).
5373 (define_expand "neg<mode>2"
5375 [(set (match_operand:DSI 0 "register_operand" "=d")
5376 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5377 (clobber (reg:CC CC_REGNUM))])]
5381 (define_insn "*negdi2_sign_cc"
5382 [(set (reg CC_REGNUM)
5383 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5384 (match_operand:SI 1 "register_operand" "d") 0)
5385 (const_int 32)) (const_int 32)))
5387 (set (match_operand:DI 0 "register_operand" "=d")
5388 (neg:DI (sign_extend:DI (match_dup 1))))]
5389 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5391 [(set_attr "op_type" "RRE")])
5393 (define_insn "*negdi2_sign"
5394 [(set (match_operand:DI 0 "register_operand" "=d")
5395 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5396 (clobber (reg:CC CC_REGNUM))]
5399 [(set_attr "op_type" "RRE")])
5401 (define_insn "*neg<mode>2_cc"
5402 [(set (reg CC_REGNUM)
5403 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5405 (set (match_operand:GPR 0 "register_operand" "=d")
5406 (neg:GPR (match_dup 1)))]
5407 "s390_match_ccmode (insn, CCAmode)"
5409 [(set_attr "op_type" "RR<E>")])
5411 (define_insn "*neg<mode>2_cconly"
5412 [(set (reg CC_REGNUM)
5413 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5415 (clobber (match_scratch:GPR 0 "=d"))]
5416 "s390_match_ccmode (insn, CCAmode)"
5418 [(set_attr "op_type" "RR<E>")])
5420 (define_insn "*neg<mode>2"
5421 [(set (match_operand:GPR 0 "register_operand" "=d")
5422 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5423 (clobber (reg:CC CC_REGNUM))]
5426 [(set_attr "op_type" "RR<E>")])
5428 (define_insn_and_split "*negdi2_31"
5429 [(set (match_operand:DI 0 "register_operand" "=d")
5430 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5431 (clobber (reg:CC CC_REGNUM))]
5434 "&& reload_completed"
5436 [(set (match_dup 2) (neg:SI (match_dup 3)))
5437 (clobber (reg:CC CC_REGNUM))])
5439 [(set (reg:CCAP CC_REGNUM)
5440 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5441 (set (match_dup 4) (neg:SI (match_dup 5)))])
5443 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5445 (label_ref (match_dup 6))))
5447 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5448 (clobber (reg:CC CC_REGNUM))])
5450 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5451 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5452 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5453 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5454 operands[6] = gen_label_rtx ();")
5457 ; neg(df|sf)2 instruction pattern(s).
5460 (define_expand "neg<mode>2"
5462 [(set (match_operand:FPR 0 "register_operand" "=f")
5463 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5464 (clobber (reg:CC CC_REGNUM))])]
5468 (define_insn "*neg<mode>2_cc"
5469 [(set (reg CC_REGNUM)
5470 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5471 (match_operand:FPR 2 "const0_operand" "")))
5472 (set (match_operand:FPR 0 "register_operand" "=f")
5473 (neg:FPR (match_dup 1)))]
5474 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5476 [(set_attr "op_type" "RRE")
5477 (set_attr "type" "fsimp<mode>")])
5479 (define_insn "*neg<mode>2_cconly"
5480 [(set (reg CC_REGNUM)
5481 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5482 (match_operand:FPR 2 "const0_operand" "")))
5483 (clobber (match_scratch:FPR 0 "=f"))]
5484 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5486 [(set_attr "op_type" "RRE")
5487 (set_attr "type" "fsimp<mode>")])
5489 (define_insn "*neg<mode>2"
5490 [(set (match_operand:FPR 0 "register_operand" "=f")
5491 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5492 (clobber (reg:CC CC_REGNUM))]
5493 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5495 [(set_attr "op_type" "RRE")
5496 (set_attr "type" "fsimp<mode>")])
5498 (define_insn "*neg<mode>2_ibm"
5499 [(set (match_operand:FPR 0 "register_operand" "=f")
5500 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5501 (clobber (reg:CC CC_REGNUM))]
5502 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5504 [(set_attr "op_type" "RR")
5505 (set_attr "type" "fsimp<mode>")])
5509 ;;- Absolute value instructions.
5513 ; abs(di|si)2 instruction pattern(s).
5516 (define_insn "*absdi2_sign_cc"
5517 [(set (reg CC_REGNUM)
5518 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5519 (match_operand:SI 1 "register_operand" "d") 0)
5520 (const_int 32)) (const_int 32)))
5522 (set (match_operand:DI 0 "register_operand" "=d")
5523 (abs:DI (sign_extend:DI (match_dup 1))))]
5524 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5526 [(set_attr "op_type" "RRE")])
5528 (define_insn "*absdi2_sign"
5529 [(set (match_operand:DI 0 "register_operand" "=d")
5530 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5531 (clobber (reg:CC CC_REGNUM))]
5534 [(set_attr "op_type" "RRE")])
5536 (define_insn "*abs<mode>2_cc"
5537 [(set (reg CC_REGNUM)
5538 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5540 (set (match_operand:GPR 0 "register_operand" "=d")
5541 (abs:GPR (match_dup 1)))]
5542 "s390_match_ccmode (insn, CCAmode)"
5544 [(set_attr "op_type" "RR<E>")])
5546 (define_insn "*abs<mode>2_cconly"
5547 [(set (reg CC_REGNUM)
5548 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5550 (clobber (match_scratch:GPR 0 "=d"))]
5551 "s390_match_ccmode (insn, CCAmode)"
5553 [(set_attr "op_type" "RR<E>")])
5555 (define_insn "abs<mode>2"
5556 [(set (match_operand:GPR 0 "register_operand" "=d")
5557 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5558 (clobber (reg:CC CC_REGNUM))]
5561 [(set_attr "op_type" "RR<E>")])
5564 ; abs(df|sf)2 instruction pattern(s).
5567 (define_expand "abs<mode>2"
5569 [(set (match_operand:FPR 0 "register_operand" "=f")
5570 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5571 (clobber (reg:CC CC_REGNUM))])]
5575 (define_insn "*abs<mode>2_cc"
5576 [(set (reg CC_REGNUM)
5577 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5578 (match_operand:FPR 2 "const0_operand" "")))
5579 (set (match_operand:FPR 0 "register_operand" "=f")
5580 (abs:FPR (match_dup 1)))]
5581 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5583 [(set_attr "op_type" "RRE")
5584 (set_attr "type" "fsimp<mode>")])
5586 (define_insn "*abs<mode>2_cconly"
5587 [(set (reg CC_REGNUM)
5588 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5589 (match_operand:FPR 2 "const0_operand" "")))
5590 (clobber (match_scratch:FPR 0 "=f"))]
5591 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5593 [(set_attr "op_type" "RRE")
5594 (set_attr "type" "fsimp<mode>")])
5596 (define_insn "*abs<mode>2"
5597 [(set (match_operand:FPR 0 "register_operand" "=f")
5598 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5599 (clobber (reg:CC CC_REGNUM))]
5600 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5602 [(set_attr "op_type" "RRE")
5603 (set_attr "type" "fsimp<mode>")])
5605 (define_insn "*abs<mode>2_ibm"
5606 [(set (match_operand:FPR 0 "register_operand" "=f")
5607 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5608 (clobber (reg:CC CC_REGNUM))]
5609 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5611 [(set_attr "op_type" "RR")
5612 (set_attr "type" "fsimp<mode>")])
5615 ;;- Negated absolute value instructions
5622 (define_insn "*negabsdi2_sign_cc"
5623 [(set (reg CC_REGNUM)
5624 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5625 (match_operand:SI 1 "register_operand" "d") 0)
5626 (const_int 32)) (const_int 32))))
5628 (set (match_operand:DI 0 "register_operand" "=d")
5629 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
5630 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5632 [(set_attr "op_type" "RRE")])
5634 (define_insn "*negabsdi2_sign"
5635 [(set (match_operand:DI 0 "register_operand" "=d")
5636 (neg:DI (abs:DI (sign_extend:DI
5637 (match_operand:SI 1 "register_operand" "d")))))
5638 (clobber (reg:CC CC_REGNUM))]
5641 [(set_attr "op_type" "RRE")])
5643 (define_insn "*negabs<mode>2_cc"
5644 [(set (reg CC_REGNUM)
5645 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5647 (set (match_operand:GPR 0 "register_operand" "=d")
5648 (neg:GPR (abs:GPR (match_dup 1))))]
5649 "s390_match_ccmode (insn, CCAmode)"
5651 [(set_attr "op_type" "RR<E>")])
5653 (define_insn "*negabs<mode>2_cconly"
5654 [(set (reg CC_REGNUM)
5655 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5657 (clobber (match_scratch:GPR 0 "=d"))]
5658 "s390_match_ccmode (insn, CCAmode)"
5660 [(set_attr "op_type" "RR<E>")])
5662 (define_insn "*negabs<mode>2"
5663 [(set (match_operand:GPR 0 "register_operand" "=d")
5664 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
5665 (clobber (reg:CC CC_REGNUM))]
5668 [(set_attr "op_type" "RR<E>")])
5674 (define_insn "*negabs<mode>2_cc"
5675 [(set (reg CC_REGNUM)
5676 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5677 (match_operand:FPR 2 "const0_operand" "")))
5678 (set (match_operand:FPR 0 "register_operand" "=f")
5679 (neg:FPR (abs:FPR (match_dup 1))))]
5680 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5682 [(set_attr "op_type" "RRE")
5683 (set_attr "type" "fsimp<mode>")])
5685 (define_insn "*negabs<mode>2_cconly"
5686 [(set (reg CC_REGNUM)
5687 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5688 (match_operand:FPR 2 "const0_operand" "")))
5689 (clobber (match_scratch:FPR 0 "=f"))]
5690 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5692 [(set_attr "op_type" "RRE")
5693 (set_attr "type" "fsimp<mode>")])
5695 (define_insn "*negabs<mode>2"
5696 [(set (match_operand:FPR 0 "register_operand" "=f")
5697 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
5698 (clobber (reg:CC CC_REGNUM))]
5699 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5701 [(set_attr "op_type" "RRE")
5702 (set_attr "type" "fsimp<mode>")])
5705 ;;- Square root instructions.
5709 ; sqrt(df|sf)2 instruction pattern(s).
5712 (define_insn "sqrt<mode>2"
5713 [(set (match_operand:FPR 0 "register_operand" "=f,f")
5714 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
5715 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5719 [(set_attr "op_type" "RRE,RXE")
5720 (set_attr "type" "fsqrt<mode>")])
5724 ;;- One complement instructions.
5728 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
5731 (define_expand "one_cmpl<mode>2"
5733 [(set (match_operand:INT 0 "register_operand" "")
5734 (xor:INT (match_operand:INT 1 "register_operand" "")
5736 (clobber (reg:CC CC_REGNUM))])]
5742 ;;- Rotate instructions.
5746 ; rotl(di|si)3 instruction pattern(s).
5749 (define_insn "rotl<mode>3"
5750 [(set (match_operand:GPR 0 "register_operand" "=d")
5751 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
5752 (match_operand:SI 2 "shift_count_operand" "Y")))]
5755 [(set_attr "op_type" "RSE")
5756 (set_attr "atype" "reg")])
5760 ;;- Shift instructions.
5764 ; (ashl|lshr)di3 instruction pattern(s).
5767 (define_expand "<shift>di3"
5768 [(set (match_operand:DI 0 "register_operand" "")
5769 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
5770 (match_operand:SI 2 "shift_count_operand" "")))]
5774 (define_insn "*<shift>di3_31"
5775 [(set (match_operand:DI 0 "register_operand" "=d")
5776 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
5777 (match_operand:SI 2 "shift_count_operand" "Y")))]
5780 [(set_attr "op_type" "RS")
5781 (set_attr "atype" "reg")])
5783 (define_insn "*<shift>di3_64"
5784 [(set (match_operand:DI 0 "register_operand" "=d")
5785 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
5786 (match_operand:SI 2 "shift_count_operand" "Y")))]
5788 "s<lr>lg\t%0,%1,%Y2"
5789 [(set_attr "op_type" "RSE")
5790 (set_attr "atype" "reg")])
5793 ; ashrdi3 instruction pattern(s).
5796 (define_expand "ashrdi3"
5798 [(set (match_operand:DI 0 "register_operand" "")
5799 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5800 (match_operand:SI 2 "shift_count_operand" "")))
5801 (clobber (reg:CC CC_REGNUM))])]
5805 (define_insn "*ashrdi3_cc_31"
5806 [(set (reg CC_REGNUM)
5807 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5808 (match_operand:SI 2 "shift_count_operand" "Y"))
5810 (set (match_operand:DI 0 "register_operand" "=d")
5811 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5812 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5814 [(set_attr "op_type" "RS")
5815 (set_attr "atype" "reg")])
5817 (define_insn "*ashrdi3_cconly_31"
5818 [(set (reg CC_REGNUM)
5819 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5820 (match_operand:SI 2 "shift_count_operand" "Y"))
5822 (clobber (match_scratch:DI 0 "=d"))]
5823 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5825 [(set_attr "op_type" "RS")
5826 (set_attr "atype" "reg")])
5828 (define_insn "*ashrdi3_31"
5829 [(set (match_operand:DI 0 "register_operand" "=d")
5830 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5831 (match_operand:SI 2 "shift_count_operand" "Y")))
5832 (clobber (reg:CC CC_REGNUM))]
5835 [(set_attr "op_type" "RS")
5836 (set_attr "atype" "reg")])
5838 (define_insn "*ashrdi3_cc_64"
5839 [(set (reg CC_REGNUM)
5840 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5841 (match_operand:SI 2 "shift_count_operand" "Y"))
5843 (set (match_operand:DI 0 "register_operand" "=d")
5844 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5845 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5847 [(set_attr "op_type" "RSE")
5848 (set_attr "atype" "reg")])
5850 (define_insn "*ashrdi3_cconly_64"
5851 [(set (reg CC_REGNUM)
5852 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5853 (match_operand:SI 2 "shift_count_operand" "Y"))
5855 (clobber (match_scratch:DI 0 "=d"))]
5856 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5858 [(set_attr "op_type" "RSE")
5859 (set_attr "atype" "reg")])
5861 (define_insn "*ashrdi3_64"
5862 [(set (match_operand:DI 0 "register_operand" "=d")
5863 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5864 (match_operand:SI 2 "shift_count_operand" "Y")))
5865 (clobber (reg:CC CC_REGNUM))]
5868 [(set_attr "op_type" "RSE")
5869 (set_attr "atype" "reg")])
5873 ; (ashl|lshr)si3 instruction pattern(s).
5876 (define_insn "<shift>si3"
5877 [(set (match_operand:SI 0 "register_operand" "=d")
5878 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
5879 (match_operand:SI 2 "shift_count_operand" "Y")))]
5882 [(set_attr "op_type" "RS")
5883 (set_attr "atype" "reg")])
5886 ; ashrsi3 instruction pattern(s).
5889 (define_insn "*ashrsi3_cc"
5890 [(set (reg CC_REGNUM)
5891 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5892 (match_operand:SI 2 "shift_count_operand" "Y"))
5894 (set (match_operand:SI 0 "register_operand" "=d")
5895 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5896 "s390_match_ccmode(insn, CCSmode)"
5898 [(set_attr "op_type" "RS")
5899 (set_attr "atype" "reg")])
5902 (define_insn "*ashrsi3_cconly"
5903 [(set (reg CC_REGNUM)
5904 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5905 (match_operand:SI 2 "shift_count_operand" "Y"))
5907 (clobber (match_scratch:SI 0 "=d"))]
5908 "s390_match_ccmode(insn, CCSmode)"
5910 [(set_attr "op_type" "RS")
5911 (set_attr "atype" "reg")])
5913 (define_insn "ashrsi3"
5914 [(set (match_operand:SI 0 "register_operand" "=d")
5915 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5916 (match_operand:SI 2 "shift_count_operand" "Y")))
5917 (clobber (reg:CC CC_REGNUM))]
5920 [(set_attr "op_type" "RS")
5921 (set_attr "atype" "reg")])
5925 ;; Branch instruction patterns.
5928 (define_expand "b<code>"
5930 (if_then_else (COMPARE (match_operand 0 "" "")
5935 "s390_emit_jump (operands[0],
5936 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
5940 ;;- Conditional jump instructions.
5943 (define_insn "*cjump_64"
5946 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5947 (label_ref (match_operand 0 "" ""))
5951 if (get_attr_length (insn) == 4)
5954 return "jg%C1\t%l0";
5956 [(set_attr "op_type" "RI")
5957 (set_attr "type" "branch")
5958 (set (attr "length")
5959 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5960 (const_int 4) (const_int 6)))])
5962 (define_insn "*cjump_31"
5965 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5966 (label_ref (match_operand 0 "" ""))
5970 gcc_assert (get_attr_length (insn) == 4);
5973 [(set_attr "op_type" "RI")
5974 (set_attr "type" "branch")
5975 (set (attr "length")
5976 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5977 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5978 (const_int 4) (const_int 6))
5979 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5980 (const_int 4) (const_int 8))))])
5982 (define_insn "*cjump_long"
5985 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5986 (match_operand 0 "address_operand" "U")
5990 if (get_attr_op_type (insn) == OP_TYPE_RR)
5995 [(set (attr "op_type")
5996 (if_then_else (match_operand 0 "register_operand" "")
5997 (const_string "RR") (const_string "RX")))
5998 (set_attr "type" "branch")
5999 (set_attr "atype" "agen")])
6003 ;;- Negated conditional jump instructions.
6006 (define_insn "*icjump_64"
6009 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6011 (label_ref (match_operand 0 "" ""))))]
6014 if (get_attr_length (insn) == 4)
6017 return "jg%D1\t%l0";
6019 [(set_attr "op_type" "RI")
6020 (set_attr "type" "branch")
6021 (set (attr "length")
6022 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6023 (const_int 4) (const_int 6)))])
6025 (define_insn "*icjump_31"
6028 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6030 (label_ref (match_operand 0 "" ""))))]
6033 gcc_assert (get_attr_length (insn) == 4);
6036 [(set_attr "op_type" "RI")
6037 (set_attr "type" "branch")
6038 (set (attr "length")
6039 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6040 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6041 (const_int 4) (const_int 6))
6042 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6043 (const_int 4) (const_int 8))))])
6045 (define_insn "*icjump_long"
6048 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6050 (match_operand 0 "address_operand" "U")))]
6053 if (get_attr_op_type (insn) == OP_TYPE_RR)
6058 [(set (attr "op_type")
6059 (if_then_else (match_operand 0 "register_operand" "")
6060 (const_string "RR") (const_string "RX")))
6061 (set_attr "type" "branch")
6062 (set_attr "atype" "agen")])
6065 ;;- Trap instructions.
6069 [(trap_if (const_int 1) (const_int 0))]
6072 [(set_attr "op_type" "RI")
6073 (set_attr "type" "branch")])
6075 (define_expand "conditional_trap"
6076 [(trap_if (match_operand 0 "comparison_operator" "")
6077 (match_operand 1 "general_operand" ""))]
6080 if (operands[1] != const0_rtx) FAIL;
6081 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6082 s390_compare_op0, s390_compare_op1);
6085 (define_insn "*trap"
6086 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6090 [(set_attr "op_type" "RI")
6091 (set_attr "type" "branch")])
6094 ;;- Loop instructions.
6096 ;; This is all complicated by the fact that since this is a jump insn
6097 ;; we must handle our own output reloads.
6099 (define_expand "doloop_end"
6100 [(use (match_operand 0 "" "")) ; loop pseudo
6101 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6102 (use (match_operand 2 "" "")) ; max iterations
6103 (use (match_operand 3 "" "")) ; loop level
6104 (use (match_operand 4 "" ""))] ; label
6107 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6108 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6109 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6110 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6111 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6112 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6119 (define_insn_and_split "doloop_si64"
6122 (ne (match_operand:SI 1 "register_operand" "d,d")
6124 (label_ref (match_operand 0 "" ""))
6126 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6127 (plus:SI (match_dup 1) (const_int -1)))
6128 (clobber (match_scratch:SI 3 "=X,&1"))
6129 (clobber (reg:CC CC_REGNUM))]
6132 if (which_alternative != 0)
6134 else if (get_attr_length (insn) == 4)
6135 return "brct\t%1,%l0";
6137 return "ahi\t%1,-1\;jgne\t%l0";
6139 "&& reload_completed
6140 && (! REG_P (operands[2])
6141 || ! rtx_equal_p (operands[1], operands[2]))"
6142 [(parallel [(set (reg:CCAN CC_REGNUM)
6143 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6145 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6146 (set (match_dup 2) (match_dup 3))
6147 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6148 (label_ref (match_dup 0))
6151 [(set_attr "op_type" "RI")
6152 (set_attr "type" "branch")
6153 (set (attr "length")
6154 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6155 (const_int 4) (const_int 10)))])
6157 (define_insn_and_split "doloop_si31"
6160 (ne (match_operand:SI 1 "register_operand" "d,d")
6162 (label_ref (match_operand 0 "" ""))
6164 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6165 (plus:SI (match_dup 1) (const_int -1)))
6166 (clobber (match_scratch:SI 3 "=X,&1"))
6167 (clobber (reg:CC CC_REGNUM))]
6170 if (which_alternative != 0)
6172 else if (get_attr_length (insn) == 4)
6173 return "brct\t%1,%l0";
6177 "&& reload_completed
6178 && (! REG_P (operands[2])
6179 || ! rtx_equal_p (operands[1], operands[2]))"
6180 [(parallel [(set (reg:CCAN CC_REGNUM)
6181 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6183 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6184 (set (match_dup 2) (match_dup 3))
6185 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6186 (label_ref (match_dup 0))
6189 [(set_attr "op_type" "RI")
6190 (set_attr "type" "branch")
6191 (set (attr "length")
6192 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6193 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6194 (const_int 4) (const_int 6))
6195 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6196 (const_int 4) (const_int 8))))])
6198 (define_insn "*doloop_si_long"
6201 (ne (match_operand:SI 1 "register_operand" "d,d")
6203 (match_operand 0 "address_operand" "U,U")
6205 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6206 (plus:SI (match_dup 1) (const_int -1)))
6207 (clobber (match_scratch:SI 3 "=X,&1"))
6208 (clobber (reg:CC CC_REGNUM))]
6211 if (get_attr_op_type (insn) == OP_TYPE_RR)
6212 return "bctr\t%1,%0";
6214 return "bct\t%1,%a0";
6216 [(set (attr "op_type")
6217 (if_then_else (match_operand 0 "register_operand" "")
6218 (const_string "RR") (const_string "RX")))
6219 (set_attr "type" "branch")
6220 (set_attr "atype" "agen")])
6222 (define_insn_and_split "doloop_di"
6225 (ne (match_operand:DI 1 "register_operand" "d,d")
6227 (label_ref (match_operand 0 "" ""))
6229 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6230 (plus:DI (match_dup 1) (const_int -1)))
6231 (clobber (match_scratch:DI 3 "=X,&1"))
6232 (clobber (reg:CC CC_REGNUM))]
6235 if (which_alternative != 0)
6237 else if (get_attr_length (insn) == 4)
6238 return "brctg\t%1,%l0";
6240 return "aghi\t%1,-1\;jgne\t%l0";
6242 "&& reload_completed
6243 && (! REG_P (operands[2])
6244 || ! rtx_equal_p (operands[1], operands[2]))"
6245 [(parallel [(set (reg:CCAN CC_REGNUM)
6246 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6248 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6249 (set (match_dup 2) (match_dup 3))
6250 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6251 (label_ref (match_dup 0))
6254 [(set_attr "op_type" "RI")
6255 (set_attr "type" "branch")
6256 (set (attr "length")
6257 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6258 (const_int 4) (const_int 10)))])
6261 ;;- Unconditional jump instructions.
6265 ; jump instruction pattern(s).
6268 (define_expand "jump"
6269 [(match_operand 0 "" "")]
6271 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6273 (define_insn "*jump64"
6274 [(set (pc) (label_ref (match_operand 0 "" "")))]
6277 if (get_attr_length (insn) == 4)
6282 [(set_attr "op_type" "RI")
6283 (set_attr "type" "branch")
6284 (set (attr "length")
6285 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6286 (const_int 4) (const_int 6)))])
6288 (define_insn "*jump31"
6289 [(set (pc) (label_ref (match_operand 0 "" "")))]
6292 gcc_assert (get_attr_length (insn) == 4);
6295 [(set_attr "op_type" "RI")
6296 (set_attr "type" "branch")
6297 (set (attr "length")
6298 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6299 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6300 (const_int 4) (const_int 6))
6301 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6302 (const_int 4) (const_int 8))))])
6305 ; indirect-jump instruction pattern(s).
6308 (define_insn "indirect_jump"
6309 [(set (pc) (match_operand 0 "address_operand" "U"))]
6312 if (get_attr_op_type (insn) == OP_TYPE_RR)
6317 [(set (attr "op_type")
6318 (if_then_else (match_operand 0 "register_operand" "")
6319 (const_string "RR") (const_string "RX")))
6320 (set_attr "type" "branch")
6321 (set_attr "atype" "agen")])
6324 ; casesi instruction pattern(s).
6327 (define_insn "casesi_jump"
6328 [(set (pc) (match_operand 0 "address_operand" "U"))
6329 (use (label_ref (match_operand 1 "" "")))]
6332 if (get_attr_op_type (insn) == OP_TYPE_RR)
6337 [(set (attr "op_type")
6338 (if_then_else (match_operand 0 "register_operand" "")
6339 (const_string "RR") (const_string "RX")))
6340 (set_attr "type" "branch")
6341 (set_attr "atype" "agen")])
6343 (define_expand "casesi"
6344 [(match_operand:SI 0 "general_operand" "")
6345 (match_operand:SI 1 "general_operand" "")
6346 (match_operand:SI 2 "general_operand" "")
6347 (label_ref (match_operand 3 "" ""))
6348 (label_ref (match_operand 4 "" ""))]
6351 rtx index = gen_reg_rtx (SImode);
6352 rtx base = gen_reg_rtx (Pmode);
6353 rtx target = gen_reg_rtx (Pmode);
6355 emit_move_insn (index, operands[0]);
6356 emit_insn (gen_subsi3 (index, index, operands[1]));
6357 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6360 if (Pmode != SImode)
6361 index = convert_to_mode (Pmode, index, 1);
6362 if (GET_CODE (index) != REG)
6363 index = copy_to_mode_reg (Pmode, index);
6366 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6368 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6370 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6372 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6373 emit_move_insn (target, index);
6376 target = gen_rtx_PLUS (Pmode, base, target);
6377 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6384 ;;- Jump to subroutine.
6389 ; untyped call instruction pattern(s).
6392 ;; Call subroutine returning any type.
6393 (define_expand "untyped_call"
6394 [(parallel [(call (match_operand 0 "" "")
6396 (match_operand 1 "" "")
6397 (match_operand 2 "" "")])]
6402 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6404 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6406 rtx set = XVECEXP (operands[2], 0, i);
6407 emit_move_insn (SET_DEST (set), SET_SRC (set));
6410 /* The optimizer does not know that the call sets the function value
6411 registers we stored in the result block. We avoid problems by
6412 claiming that all hard registers are used and clobbered at this
6414 emit_insn (gen_blockage ());
6419 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6420 ;; all of memory. This blocks insns from being moved across this point.
6422 (define_insn "blockage"
6423 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6426 [(set_attr "type" "none")
6427 (set_attr "length" "0")])
6433 (define_expand "sibcall"
6434 [(call (match_operand 0 "" "")
6435 (match_operand 1 "" ""))]
6438 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6442 (define_insn "*sibcall_br"
6443 [(call (mem:QI (reg SIBCALL_REGNUM))
6444 (match_operand 0 "const_int_operand" "n"))]
6445 "SIBLING_CALL_P (insn)
6446 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6448 [(set_attr "op_type" "RR")
6449 (set_attr "type" "branch")
6450 (set_attr "atype" "agen")])
6452 (define_insn "*sibcall_brc"
6453 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6454 (match_operand 1 "const_int_operand" "n"))]
6455 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6457 [(set_attr "op_type" "RI")
6458 (set_attr "type" "branch")])
6460 (define_insn "*sibcall_brcl"
6461 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6462 (match_operand 1 "const_int_operand" "n"))]
6463 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6465 [(set_attr "op_type" "RIL")
6466 (set_attr "type" "branch")])
6469 ; sibcall_value patterns
6472 (define_expand "sibcall_value"
6473 [(set (match_operand 0 "" "")
6474 (call (match_operand 1 "" "")
6475 (match_operand 2 "" "")))]
6478 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6482 (define_insn "*sibcall_value_br"
6483 [(set (match_operand 0 "" "")
6484 (call (mem:QI (reg SIBCALL_REGNUM))
6485 (match_operand 1 "const_int_operand" "n")))]
6486 "SIBLING_CALL_P (insn)
6487 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6489 [(set_attr "op_type" "RR")
6490 (set_attr "type" "branch")
6491 (set_attr "atype" "agen")])
6493 (define_insn "*sibcall_value_brc"
6494 [(set (match_operand 0 "" "")
6495 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6496 (match_operand 2 "const_int_operand" "n")))]
6497 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6499 [(set_attr "op_type" "RI")
6500 (set_attr "type" "branch")])
6502 (define_insn "*sibcall_value_brcl"
6503 [(set (match_operand 0 "" "")
6504 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6505 (match_operand 2 "const_int_operand" "n")))]
6506 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6508 [(set_attr "op_type" "RIL")
6509 (set_attr "type" "branch")])
6513 ; call instruction pattern(s).
6516 (define_expand "call"
6517 [(call (match_operand 0 "" "")
6518 (match_operand 1 "" ""))
6519 (use (match_operand 2 "" ""))]
6522 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
6523 gen_rtx_REG (Pmode, RETURN_REGNUM));
6527 (define_insn "*bras"
6528 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6529 (match_operand 1 "const_int_operand" "n"))
6530 (clobber (match_operand 2 "register_operand" "=r"))]
6531 "!SIBLING_CALL_P (insn)
6532 && TARGET_SMALL_EXEC
6533 && GET_MODE (operands[2]) == Pmode"
6535 [(set_attr "op_type" "RI")
6536 (set_attr "type" "jsr")])
6538 (define_insn "*brasl"
6539 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6540 (match_operand 1 "const_int_operand" "n"))
6541 (clobber (match_operand 2 "register_operand" "=r"))]
6542 "!SIBLING_CALL_P (insn)
6544 && GET_MODE (operands[2]) == Pmode"
6546 [(set_attr "op_type" "RIL")
6547 (set_attr "type" "jsr")])
6549 (define_insn "*basr"
6550 [(call (mem:QI (match_operand 0 "address_operand" "U"))
6551 (match_operand 1 "const_int_operand" "n"))
6552 (clobber (match_operand 2 "register_operand" "=r"))]
6553 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
6555 if (get_attr_op_type (insn) == OP_TYPE_RR)
6556 return "basr\t%2,%0";
6558 return "bas\t%2,%a0";
6560 [(set (attr "op_type")
6561 (if_then_else (match_operand 0 "register_operand" "")
6562 (const_string "RR") (const_string "RX")))
6563 (set_attr "type" "jsr")
6564 (set_attr "atype" "agen")])
6567 ; call_value instruction pattern(s).
6570 (define_expand "call_value"
6571 [(set (match_operand 0 "" "")
6572 (call (match_operand 1 "" "")
6573 (match_operand 2 "" "")))
6574 (use (match_operand 3 "" ""))]
6577 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
6578 gen_rtx_REG (Pmode, RETURN_REGNUM));
6582 (define_insn "*bras_r"
6583 [(set (match_operand 0 "" "")
6584 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6585 (match_operand:SI 2 "const_int_operand" "n")))
6586 (clobber (match_operand 3 "register_operand" "=r"))]
6587 "!SIBLING_CALL_P (insn)
6588 && TARGET_SMALL_EXEC
6589 && GET_MODE (operands[3]) == Pmode"
6591 [(set_attr "op_type" "RI")
6592 (set_attr "type" "jsr")])
6594 (define_insn "*brasl_r"
6595 [(set (match_operand 0 "" "")
6596 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6597 (match_operand 2 "const_int_operand" "n")))
6598 (clobber (match_operand 3 "register_operand" "=r"))]
6599 "!SIBLING_CALL_P (insn)
6601 && GET_MODE (operands[3]) == Pmode"
6603 [(set_attr "op_type" "RIL")
6604 (set_attr "type" "jsr")])
6606 (define_insn "*basr_r"
6607 [(set (match_operand 0 "" "")
6608 (call (mem:QI (match_operand 1 "address_operand" "U"))
6609 (match_operand 2 "const_int_operand" "n")))
6610 (clobber (match_operand 3 "register_operand" "=r"))]
6611 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6613 if (get_attr_op_type (insn) == OP_TYPE_RR)
6614 return "basr\t%3,%1";
6616 return "bas\t%3,%a1";
6618 [(set (attr "op_type")
6619 (if_then_else (match_operand 1 "register_operand" "")
6620 (const_string "RR") (const_string "RX")))
6621 (set_attr "type" "jsr")
6622 (set_attr "atype" "agen")])
6625 ;;- Thread-local storage support.
6628 (define_expand "get_tp_64"
6629 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
6633 (define_expand "get_tp_31"
6634 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
6638 (define_expand "set_tp_64"
6639 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
6640 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
6644 (define_expand "set_tp_31"
6645 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
6646 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
6650 (define_insn "*set_tp"
6651 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
6654 [(set_attr "type" "none")
6655 (set_attr "length" "0")])
6657 (define_insn "*tls_load_64"
6658 [(set (match_operand:DI 0 "register_operand" "=d")
6659 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6660 (match_operand:DI 2 "" "")]
6664 [(set_attr "op_type" "RXE")])
6666 (define_insn "*tls_load_31"
6667 [(set (match_operand:SI 0 "register_operand" "=d,d")
6668 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
6669 (match_operand:SI 2 "" "")]
6675 [(set_attr "op_type" "RX,RXY")])
6677 (define_insn "*bras_tls"
6678 [(set (match_operand 0 "" "")
6679 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6680 (match_operand 2 "const_int_operand" "n")))
6681 (clobber (match_operand 3 "register_operand" "=r"))
6682 (use (match_operand 4 "" ""))]
6683 "!SIBLING_CALL_P (insn)
6684 && TARGET_SMALL_EXEC
6685 && GET_MODE (operands[3]) == Pmode"
6687 [(set_attr "op_type" "RI")
6688 (set_attr "type" "jsr")])
6690 (define_insn "*brasl_tls"
6691 [(set (match_operand 0 "" "")
6692 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6693 (match_operand 2 "const_int_operand" "n")))
6694 (clobber (match_operand 3 "register_operand" "=r"))
6695 (use (match_operand 4 "" ""))]
6696 "!SIBLING_CALL_P (insn)
6698 && GET_MODE (operands[3]) == Pmode"
6700 [(set_attr "op_type" "RIL")
6701 (set_attr "type" "jsr")])
6703 (define_insn "*basr_tls"
6704 [(set (match_operand 0 "" "")
6705 (call (mem:QI (match_operand 1 "address_operand" "U"))
6706 (match_operand 2 "const_int_operand" "n")))
6707 (clobber (match_operand 3 "register_operand" "=r"))
6708 (use (match_operand 4 "" ""))]
6709 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6711 if (get_attr_op_type (insn) == OP_TYPE_RR)
6712 return "basr\t%3,%1%J4";
6714 return "bas\t%3,%a1%J4";
6716 [(set (attr "op_type")
6717 (if_then_else (match_operand 1 "register_operand" "")
6718 (const_string "RR") (const_string "RX")))
6719 (set_attr "type" "jsr")
6720 (set_attr "atype" "agen")])
6723 ;;- Miscellaneous instructions.
6727 ; allocate stack instruction pattern(s).
6730 (define_expand "allocate_stack"
6731 [(match_operand 0 "general_operand" "")
6732 (match_operand 1 "general_operand" "")]
6735 rtx temp = gen_reg_rtx (Pmode);
6737 emit_move_insn (temp, s390_back_chain_rtx ());
6738 anti_adjust_stack (operands[1]);
6739 emit_move_insn (s390_back_chain_rtx (), temp);
6741 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6747 ; setjmp instruction pattern.
6750 (define_expand "builtin_setjmp_receiver"
6751 [(match_operand 0 "" "")]
6754 emit_insn (s390_load_got ());
6755 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
6759 ;; These patterns say how to save and restore the stack pointer. We need not
6760 ;; save the stack pointer at function level since we are careful to
6761 ;; preserve the backchain. At block level, we have to restore the backchain
6762 ;; when we restore the stack pointer.
6764 ;; For nonlocal gotos, we must save both the stack pointer and its
6765 ;; backchain and restore both. Note that in the nonlocal case, the
6766 ;; save area is a memory location.
6768 (define_expand "save_stack_function"
6769 [(match_operand 0 "general_operand" "")
6770 (match_operand 1 "general_operand" "")]
6774 (define_expand "restore_stack_function"
6775 [(match_operand 0 "general_operand" "")
6776 (match_operand 1 "general_operand" "")]
6780 (define_expand "restore_stack_block"
6781 [(match_operand 0 "register_operand" "")
6782 (match_operand 1 "register_operand" "")]
6785 rtx temp = gen_reg_rtx (Pmode);
6787 emit_move_insn (temp, s390_back_chain_rtx ());
6788 emit_move_insn (operands[0], operands[1]);
6789 emit_move_insn (s390_back_chain_rtx (), temp);
6794 (define_expand "save_stack_nonlocal"
6795 [(match_operand 0 "memory_operand" "")
6796 (match_operand 1 "register_operand" "")]
6799 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6800 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6802 /* Copy the backchain to the first word, sp to the second and the
6803 literal pool base to the third. */
6805 if (TARGET_BACKCHAIN)
6807 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
6808 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
6811 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
6812 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
6817 (define_expand "restore_stack_nonlocal"
6818 [(match_operand 0 "register_operand" "")
6819 (match_operand 1 "memory_operand" "")]
6822 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6823 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6824 rtx temp = NULL_RTX;
6826 /* Restore the backchain from the first word, sp from the second and the
6827 literal pool base from the third. */
6829 if (TARGET_BACKCHAIN)
6830 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
6832 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
6833 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
6836 emit_move_insn (s390_back_chain_rtx (), temp);
6838 emit_insn (gen_rtx_USE (VOIDmode, base));
6844 ; nop instruction pattern(s).
6851 [(set_attr "op_type" "RR")])
6855 ; Special literal pool access instruction pattern(s).
6858 (define_insn "*pool_entry"
6859 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
6860 UNSPECV_POOL_ENTRY)]
6863 enum machine_mode mode = GET_MODE (PATTERN (insn));
6864 unsigned int align = GET_MODE_BITSIZE (mode);
6865 s390_output_pool_entry (operands[0], mode, align);
6868 [(set (attr "length")
6869 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
6871 (define_insn "pool_align"
6872 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
6873 UNSPECV_POOL_ALIGN)]
6876 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6878 (define_insn "pool_section_start"
6879 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
6882 [(set_attr "length" "0")])
6884 (define_insn "pool_section_end"
6885 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
6888 [(set_attr "length" "0")])
6890 (define_insn "main_base_31_small"
6891 [(set (match_operand 0 "register_operand" "=a")
6892 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
6893 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6895 [(set_attr "op_type" "RR")
6896 (set_attr "type" "la")])
6898 (define_insn "main_base_31_large"
6899 [(set (match_operand 0 "register_operand" "=a")
6900 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
6901 (set (pc) (label_ref (match_operand 2 "" "")))]
6902 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6904 [(set_attr "op_type" "RI")])
6906 (define_insn "main_base_64"
6907 [(set (match_operand 0 "register_operand" "=a")
6908 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
6909 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6911 [(set_attr "op_type" "RIL")
6912 (set_attr "type" "larl")])
6914 (define_insn "main_pool"
6915 [(set (match_operand 0 "register_operand" "=a")
6916 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
6917 "GET_MODE (operands[0]) == Pmode"
6922 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
6923 (const_string "larl") (const_string "la")))])
6925 (define_insn "reload_base_31"
6926 [(set (match_operand 0 "register_operand" "=a")
6927 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
6928 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6929 "basr\t%0,0\;la\t%0,%1-.(%0)"
6930 [(set_attr "length" "6")
6931 (set_attr "type" "la")])
6933 (define_insn "reload_base_64"
6934 [(set (match_operand 0 "register_operand" "=a")
6935 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
6936 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6938 [(set_attr "op_type" "RIL")
6939 (set_attr "type" "larl")])
6942 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
6947 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6950 ;; Insns related to generating the function prologue and epilogue.
6954 (define_expand "prologue"
6955 [(use (const_int 0))]
6957 "s390_emit_prologue (); DONE;")
6959 (define_insn "prologue_tpf"
6960 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
6961 (clobber (reg:DI 1))]
6962 "TARGET_TPF_PROFILING"
6963 "larl\t%%r1,.+14\;tm\t4065,255\;bnz\t4064"
6964 [(set_attr "length" "14")])
6966 (define_expand "epilogue"
6967 [(use (const_int 1))]
6969 "s390_emit_epilogue (false); DONE;")
6971 (define_insn "epilogue_tpf"
6972 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
6973 (clobber (reg:DI 1))]
6974 "TARGET_TPF_PROFILING"
6975 "larl\t%%r1,.+14\;tm\t4071,255\;bnz\t4070"
6976 [(set_attr "length" "14")])
6978 (define_expand "sibcall_epilogue"
6979 [(use (const_int 0))]
6981 "s390_emit_epilogue (true); DONE;")
6983 (define_insn "*return"
6985 (use (match_operand 0 "register_operand" "a"))]
6986 "GET_MODE (operands[0]) == Pmode"
6988 [(set_attr "op_type" "RR")
6989 (set_attr "type" "jsr")
6990 (set_attr "atype" "agen")])
6993 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
6994 ;; pointer. This is used for compatibility.
6996 (define_expand "ptr_extend"
6997 [(set (match_operand:DI 0 "register_operand" "=r")
6998 (match_operand:SI 1 "register_operand" "r"))]
7001 emit_insn (gen_anddi3 (operands[0],
7002 gen_lowpart (DImode, operands[1]),
7003 GEN_INT (0x7fffffff)));
7007 ;; Instruction definition to expand eh_return macro to support
7008 ;; swapping in special linkage return addresses.
7010 (define_expand "eh_return"
7011 [(use (match_operand 0 "register_operand" ""))]
7014 s390_emit_tpf_eh_return (operands[0]);