1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
66 ; GOT/PLT and lt-relative accesses
67 (UNSPEC_LTREL_OFFSET 100)
68 (UNSPEC_LTREL_BASE 101)
76 (UNSPEC_RELOAD_BASE 210)
77 (UNSPEC_MAIN_BASE 211)
82 ; TLS relocation specifiers
87 (UNSPEC_GOTNTPOFF 504)
88 (UNSPEC_INDNTPOFF 505)
91 (UNSPEC_TLSLDM_NTPOFF 511)
98 ; Stack Smashing Protector
102 ; Copy sign instructions
103 (UNSPEC_COPYSIGN 800)
105 ; Test Data Class (TDC)
106 (UNSPEC_TDC_INSN 900)
110 ;; UNSPEC_VOLATILE usage
118 (UNSPECV_TPF_PROLOGUE 20)
119 (UNSPECV_TPF_EPILOGUE 21)
123 (UNSPECV_POOL_SECTION 201)
124 (UNSPECV_POOL_ALIGN 202)
125 (UNSPECV_POOL_ENTRY 203)
126 (UNSPECV_MAIN_POOL 300)
140 ; Registers with special meaning
144 ; Sibling call register.
146 ; Literal pool base register.
148 ; Return address register.
150 ; Condition code register.
152 ; Thread local storage pointer register.
156 ; Hardware register names
160 ; General purpose registers
162 ; Floating point registers.
168 ;; PFPO GPR0 argument format
173 ; PFPO operation type
174 (PFPO_CONVERT 0x1000000)
176 (PFPO_OP_TYPE_SF 0x5)
177 (PFPO_OP_TYPE_DF 0x6)
178 (PFPO_OP_TYPE_TF 0x7)
179 (PFPO_OP_TYPE_SD 0x8)
180 (PFPO_OP_TYPE_DD 0x9)
181 (PFPO_OP_TYPE_TD 0xa)
182 ; Bitposition of operand types
183 (PFPO_OP0_TYPE_SHIFT 16)
184 (PFPO_OP1_TYPE_SHIFT 8)
188 ;; Instruction operand type as used in the Principles of Operation.
189 ;; Used to determine defaults for length and other attribute values.
191 (define_attr "op_type"
192 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR"
195 ;; Instruction type attribute used for scheduling.
197 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
198 cs,vs,store,sem,idiv,
199 imulhi,imulsi,imuldi,
200 branch,jsr,fsimptf,fsimpdf,fsimpsf,
201 floadtf,floaddf,floadsf,fstoredf,fstoresf,
202 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
203 ftoi,itof,fsqrttf,fsqrtdf,fsqrtsf,
204 ftrunctf,ftruncdf,other"
205 (cond [(eq_attr "op_type" "NN") (const_string "other")
206 (eq_attr "op_type" "SS") (const_string "cs")]
207 (const_string "integer")))
209 ;; Another attribute used for scheduling purposes:
210 ;; agen: Instruction uses the address generation unit
211 ;; reg: Instruction does not use the agen unit
213 (define_attr "atype" "agen,reg"
214 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
216 (const_string "agen")))
220 (define_attr "length" ""
221 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
222 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)]
226 ;; Processor type. This attribute must exactly match the processor_type
227 ;; enumeration in s390.h. The current machine description does not
228 ;; distinguish between g5 and g6, but there are differences between the two
229 ;; CPUs could in theory be modeled.
231 (define_attr "cpu" "g5,g6,z900,z990,z9_109"
232 (const (symbol_ref "s390_tune")))
234 ;; Pipeline description for z900. For lack of anything better,
235 ;; this description is also used for the g5 and g6.
238 ;; Pipeline description for z990, z9-109 and z9-ec.
242 (include "predicates.md")
244 ;; Constraint definitions
245 (include "constraints.md")
252 ;; This mode macro allows floating point patterns to be generated from the
254 (define_mode_macro FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
255 (define_mode_macro BFP [TF DF SF])
256 (define_mode_macro DFP [TD DD])
257 (define_mode_macro DFP_ALL [TD DD SD])
258 (define_mode_macro DSF [DF SF])
259 (define_mode_macro SD_SF [SF SD])
260 (define_mode_macro DD_DF [DF DD])
261 (define_mode_macro TD_TF [TF TD])
263 ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
264 ;; from the same template.
265 (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
267 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
268 ;; from the same template.
269 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
270 (define_mode_macro DSI [DI SI])
272 ;; This mode macro allows :P to be used for patterns that operate on
273 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
274 (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
275 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
277 ;; This mode macro allows the QI and HI patterns to be defined from
278 ;; the same template.
279 (define_mode_macro HQI [HI QI])
281 ;; This mode macro allows the integer patterns to be defined from the
283 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
285 ;; This macro allows to unify all 'bCOND' expander patterns.
286 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
287 ordered uneq unlt ungt unle unge ltgt])
289 ;; This macro allows to unify all 'sCOND' patterns.
290 (define_code_macro SCOND [ltu gtu leu geu])
292 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
293 ;; the same template.
294 (define_code_macro SHIFT [ashift lshiftrt])
296 ;; These macros allow to combine most atomic operations.
297 (define_code_macro ATOMIC [and ior xor plus minus mult])
298 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
299 (plus "add") (minus "sub") (mult "nand")])
301 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
302 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
303 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
305 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
306 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
308 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
310 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
311 ;; Likewise for "<RXe>".
312 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
313 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
315 ;; The decimal floating point variants of add, sub, div and mul support 3
316 ;; fp register operands. The following macros allow to merge the bfp and
317 ;; dfp variants in a single insn definition.
319 ;; This macro is used to set op_type accordingly.
320 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
321 (DD "RRR") (SD "RRR")])
323 ;; This macro is used in the operand constraint list in order to have the
324 ;; first and the second operand match for bfp modes.
325 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
327 ;; This macro is used in the operand list of the instruction to have an
328 ;; additional operand for the dfp instructions.
329 (define_mode_attr op1 [(TF "") (DF "") (SF "")
330 (TD "%1,") (DD "%1,") (SD "%1,")])
333 ;; This attribute is used in the operand constraint list
334 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
335 ;; TFmode values are represented by a fp register pair. Since the
336 ;; sign bit instructions only handle single source and target fp registers
337 ;; these instructions can only be used for TFmode values if the source and
338 ;; target operand uses the same fp register.
339 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
341 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
342 ;; This is used to disable the memory alternative in TFmode patterns.
343 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
345 ;; This macro adds b for bfp instructions and t for dfp instructions and is used
346 ;; within instruction mnemonics.
347 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
349 ;; Although it is imprecise for z9-ec we handle all dfp instructions like
350 ;; bfp regarding the pipeline description.
351 (define_mode_attr bfp [(TF "tf") (DF "df") (SF "sf")
352 (TD "tf") (DD "df") (SD "sf")])
355 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
356 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
357 ;; version only operates on one register.
358 (define_mode_attr d0 [(DI "d") (SI "0")])
360 ;; In combination with d0 this allows to combine instructions of which the 31bit
361 ;; version only operates on one register. The DImode version needs an additional
362 ;; register for the assembler output.
363 (define_mode_attr 1 [(DI "%1,") (SI "")])
365 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
366 ;; 'ashift' and "srdl" in 'lshiftrt'.
367 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
369 ;; In SHIFT templates, this attribute holds the correct standard name for the
370 ;; pattern itself and the corresponding function calls.
371 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
373 ;; This attribute handles differences in the instruction 'type' and will result
374 ;; in "RRE" for DImode and "RR" for SImode.
375 (define_mode_attr E [(DI "E") (SI "")])
377 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
378 ;; to result in "RXY" for DImode and "RX" for SImode.
379 (define_mode_attr Y [(DI "Y") (SI "")])
381 ;; This attribute handles differences in the instruction 'type' and will result
382 ;; in "RSE" for TImode and "RS" for DImode.
383 (define_mode_attr TE [(TI "E") (DI "")])
385 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
386 ;; and "lcr" in SImode.
387 (define_mode_attr g [(DI "g") (SI "")])
389 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
390 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
391 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
392 ;; variant for long displacements.
393 (define_mode_attr y [(DI "g") (SI "y")])
395 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
396 ;; and "cds" in DImode.
397 (define_mode_attr tg [(TI "g") (DI "")])
399 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
400 ;; and "cfdbr" in SImode.
401 (define_mode_attr gf [(DI "g") (SI "f")])
403 ;; ICM mask required to load MODE value into the lowest subreg
404 ;; of a SImode register.
405 (define_mode_attr icm_lo [(HI "3") (QI "1")])
407 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
408 ;; HImode and "llgc" in QImode.
409 (define_mode_attr hc [(HI "h") (QI "c")])
411 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
413 (define_mode_attr DBL [(DI "TI") (SI "DI")])
415 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
416 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
417 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
419 ;; Maximum unsigned integer that fits in MODE.
420 (define_mode_attr max_uint [(HI "65535") (QI "255")])
424 ;;- Compare instructions.
427 (define_expand "cmp<mode>"
428 [(set (reg:CC CC_REGNUM)
429 (compare:CC (match_operand:GPR 0 "register_operand" "")
430 (match_operand:GPR 1 "general_operand" "")))]
433 s390_compare_op0 = operands[0];
434 s390_compare_op1 = operands[1];
438 (define_expand "cmp<mode>"
439 [(set (reg:CC CC_REGNUM)
440 (compare:CC (match_operand:FP 0 "register_operand" "")
441 (match_operand:FP 1 "general_operand" "")))]
444 s390_compare_op0 = operands[0];
445 s390_compare_op1 = operands[1];
450 ; Test-under-Mask instructions
452 (define_insn "*tmqi_mem"
453 [(set (reg CC_REGNUM)
454 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
455 (match_operand:QI 1 "immediate_operand" "n,n"))
456 (match_operand:QI 2 "immediate_operand" "n,n")))]
457 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
461 [(set_attr "op_type" "SI,SIY")])
463 (define_insn "*tmdi_reg"
464 [(set (reg CC_REGNUM)
465 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
466 (match_operand:DI 1 "immediate_operand"
467 "N0HD0,N1HD0,N2HD0,N3HD0"))
468 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
470 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
471 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
477 [(set_attr "op_type" "RI")])
479 (define_insn "*tmsi_reg"
480 [(set (reg CC_REGNUM)
481 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
482 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
483 (match_operand:SI 2 "immediate_operand" "n,n")))]
484 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
485 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
489 [(set_attr "op_type" "RI")])
491 (define_insn "*tm<mode>_full"
492 [(set (reg CC_REGNUM)
493 (compare (match_operand:HQI 0 "register_operand" "d")
494 (match_operand:HQI 1 "immediate_operand" "n")))]
495 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
497 [(set_attr "op_type" "RI")])
501 ; Load-and-Test instructions
504 ; tst(di|si) instruction pattern(s).
506 (define_insn "*tstdi_sign"
507 [(set (reg CC_REGNUM)
508 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
509 (const_int 32)) (const_int 32))
510 (match_operand:DI 1 "const0_operand" "")))
511 (set (match_operand:DI 2 "register_operand" "=d")
512 (sign_extend:DI (match_dup 0)))]
513 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
515 [(set_attr "op_type" "RRE")])
518 (define_insn "*tst<mode>_extimm"
519 [(set (reg CC_REGNUM)
520 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
521 (match_operand:GPR 1 "const0_operand" "")))
522 (set (match_operand:GPR 2 "register_operand" "=d,d")
524 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
528 [(set_attr "op_type" "RR<E>,RXY")])
531 (define_insn "*tst<mode>_cconly_extimm"
532 [(set (reg CC_REGNUM)
533 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
534 (match_operand:GPR 1 "const0_operand" "")))
535 (clobber (match_scratch:GPR 2 "=X,d"))]
536 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
540 [(set_attr "op_type" "RR<E>,RXY")])
542 (define_insn "*tstdi"
543 [(set (reg CC_REGNUM)
544 (compare (match_operand:DI 0 "register_operand" "d")
545 (match_operand:DI 1 "const0_operand" "")))
546 (set (match_operand:DI 2 "register_operand" "=d")
548 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
550 [(set_attr "op_type" "RRE")])
552 (define_insn "*tstsi"
553 [(set (reg CC_REGNUM)
554 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
555 (match_operand:SI 1 "const0_operand" "")))
556 (set (match_operand:SI 2 "register_operand" "=d,d,d")
558 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
563 [(set_attr "op_type" "RR,RS,RSY")])
565 (define_insn "*tstsi_cconly"
566 [(set (reg CC_REGNUM)
567 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
568 (match_operand:SI 1 "const0_operand" "")))
569 (clobber (match_scratch:SI 2 "=X,d,d"))]
570 "s390_match_ccmode(insn, CCSmode)"
575 [(set_attr "op_type" "RR,RS,RSY")])
577 (define_insn "*tstdi_cconly_31"
578 [(set (reg CC_REGNUM)
579 (compare (match_operand:DI 0 "register_operand" "d")
580 (match_operand:DI 1 "const0_operand" "")))]
581 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
583 [(set_attr "op_type" "RS")
584 (set_attr "atype" "reg")])
587 (define_insn "*tst<mode>_cconly2"
588 [(set (reg CC_REGNUM)
589 (compare (match_operand:GPR 0 "register_operand" "d")
590 (match_operand:GPR 1 "const0_operand" "")))]
591 "s390_match_ccmode(insn, CCSmode)"
593 [(set_attr "op_type" "RR<E>")])
595 ; tst(hi|qi) instruction pattern(s).
597 (define_insn "*tst<mode>CCT"
598 [(set (reg CC_REGNUM)
599 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
600 (match_operand:HQI 1 "const0_operand" "")))
601 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
603 "s390_match_ccmode(insn, CCTmode)"
606 icmy\t%2,<icm_lo>,%S0
608 [(set_attr "op_type" "RS,RSY,RI")])
610 (define_insn "*tsthiCCT_cconly"
611 [(set (reg CC_REGNUM)
612 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
613 (match_operand:HI 1 "const0_operand" "")))
614 (clobber (match_scratch:HI 2 "=d,d,X"))]
615 "s390_match_ccmode(insn, CCTmode)"
620 [(set_attr "op_type" "RS,RSY,RI")])
622 (define_insn "*tstqiCCT_cconly"
623 [(set (reg CC_REGNUM)
624 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
625 (match_operand:QI 1 "const0_operand" "")))]
626 "s390_match_ccmode(insn, CCTmode)"
631 [(set_attr "op_type" "SI,SIY,RI")])
633 (define_insn "*tst<mode>"
634 [(set (reg CC_REGNUM)
635 (compare (match_operand:HQI 0 "s_operand" "Q,S")
636 (match_operand:HQI 1 "const0_operand" "")))
637 (set (match_operand:HQI 2 "register_operand" "=d,d")
639 "s390_match_ccmode(insn, CCSmode)"
642 icmy\t%2,<icm_lo>,%S0"
643 [(set_attr "op_type" "RS,RSY")])
645 (define_insn "*tst<mode>_cconly"
646 [(set (reg CC_REGNUM)
647 (compare (match_operand:HQI 0 "s_operand" "Q,S")
648 (match_operand:HQI 1 "const0_operand" "")))
649 (clobber (match_scratch:HQI 2 "=d,d"))]
650 "s390_match_ccmode(insn, CCSmode)"
653 icmy\t%2,<icm_lo>,%S0"
654 [(set_attr "op_type" "RS,RSY")])
657 ; Compare (equality) instructions
659 (define_insn "*cmpdi_cct"
660 [(set (reg CC_REGNUM)
661 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
662 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
663 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
670 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
672 (define_insn "*cmpsi_cct"
673 [(set (reg CC_REGNUM)
674 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
675 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
676 "s390_match_ccmode (insn, CCTmode)"
684 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
687 ; Compare (signed) instructions
689 (define_insn "*cmpdi_ccs_sign"
690 [(set (reg CC_REGNUM)
691 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
692 (match_operand:DI 0 "register_operand" "d,d")))]
693 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
697 [(set_attr "op_type" "RRE,RXY")])
699 (define_insn "*cmpsi_ccs_sign"
700 [(set (reg CC_REGNUM)
701 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
702 (match_operand:SI 0 "register_operand" "d,d")))]
703 "s390_match_ccmode(insn, CCSRmode)"
707 [(set_attr "op_type" "RX,RXY")])
709 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg
710 (define_insn "*cmp<mode>_ccs"
711 [(set (reg CC_REGNUM)
712 (compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d")
713 (match_operand:GPR 1 "general_operand" "d,K,Os,R,T")))]
714 "s390_match_ccmode(insn, CCSmode)"
721 [(set_attr "op_type" "RR<E>,RI,RIL,RX<Y>,RXY")])
724 ; Compare (unsigned) instructions
726 (define_insn "*cmpdi_ccu_zero"
727 [(set (reg CC_REGNUM)
728 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
729 (match_operand:DI 0 "register_operand" "d,d")))]
730 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
734 [(set_attr "op_type" "RRE,RXY")])
736 (define_insn "*cmpdi_ccu"
737 [(set (reg CC_REGNUM)
738 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
739 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
740 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
747 [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
749 (define_insn "*cmpsi_ccu"
750 [(set (reg CC_REGNUM)
751 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
752 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
753 "s390_match_ccmode (insn, CCUmode)"
761 [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
763 (define_insn "*cmphi_ccu"
764 [(set (reg CC_REGNUM)
765 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
766 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
767 "s390_match_ccmode (insn, CCUmode)
768 && !register_operand (operands[1], HImode)"
774 [(set_attr "op_type" "RS,RSY,SS,SS")])
776 (define_insn "*cmpqi_ccu"
777 [(set (reg CC_REGNUM)
778 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
779 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
780 "s390_match_ccmode (insn, CCUmode)
781 && !register_operand (operands[1], QImode)"
789 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
792 ; Block compare (CLC) instruction patterns.
795 [(set (reg CC_REGNUM)
796 (compare (match_operand:BLK 0 "memory_operand" "Q")
797 (match_operand:BLK 1 "memory_operand" "Q")))
798 (use (match_operand 2 "const_int_operand" "n"))]
799 "s390_match_ccmode (insn, CCUmode)
800 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
801 "clc\t%O0(%2,%R0),%S1"
802 [(set_attr "op_type" "SS")])
805 [(set (reg CC_REGNUM)
806 (compare (match_operand 0 "memory_operand" "")
807 (match_operand 1 "memory_operand" "")))]
809 && s390_match_ccmode (insn, CCUmode)
810 && GET_MODE (operands[0]) == GET_MODE (operands[1])
811 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
813 [(set (match_dup 0) (match_dup 1))
814 (use (match_dup 2))])]
816 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
817 operands[0] = adjust_address (operands[0], BLKmode, 0);
818 operands[1] = adjust_address (operands[1], BLKmode, 0);
820 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
821 operands[0], operands[1]);
822 operands[0] = SET_DEST (PATTERN (curr_insn));
826 ; (TF|DF|SF|TD|DD|SD) instructions
828 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
829 (define_insn "*cmp<mode>_ccs_0"
830 [(set (reg CC_REGNUM)
831 (compare (match_operand:FP 0 "register_operand" "f")
832 (match_operand:FP 1 "const0_operand" "")))]
833 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
834 "lt<xde><bt>r\t%0,%0"
835 [(set_attr "op_type" "RRE")
836 (set_attr "type" "fsimp<bfp>")])
838 ; cxtr, cxbr, cdbr, cebr, cxb, cdb, ceb, cxbtr, cdbtr
839 (define_insn "*cmp<mode>_ccs"
840 [(set (reg CC_REGNUM)
841 (compare (match_operand:FP 0 "register_operand" "f,f")
842 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
843 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
847 [(set_attr "op_type" "RRE,RXE")
848 (set_attr "type" "fsimp<bfp>")])
851 ;;- Move instructions.
855 ; movti instruction pattern(s).
859 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
860 (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
868 [(set_attr "op_type" "RSY,RSY,*,*,SS")
869 (set_attr "type" "lm,stm,*,*,*")])
872 [(set (match_operand:TI 0 "nonimmediate_operand" "")
873 (match_operand:TI 1 "general_operand" ""))]
874 "TARGET_64BIT && reload_completed
875 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
876 [(set (match_dup 2) (match_dup 4))
877 (set (match_dup 3) (match_dup 5))]
879 operands[2] = operand_subword (operands[0], 0, 0, TImode);
880 operands[3] = operand_subword (operands[0], 1, 0, TImode);
881 operands[4] = operand_subword (operands[1], 0, 0, TImode);
882 operands[5] = operand_subword (operands[1], 1, 0, TImode);
886 [(set (match_operand:TI 0 "nonimmediate_operand" "")
887 (match_operand:TI 1 "general_operand" ""))]
888 "TARGET_64BIT && reload_completed
889 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
890 [(set (match_dup 2) (match_dup 4))
891 (set (match_dup 3) (match_dup 5))]
893 operands[2] = operand_subword (operands[0], 1, 0, TImode);
894 operands[3] = operand_subword (operands[0], 0, 0, TImode);
895 operands[4] = operand_subword (operands[1], 1, 0, TImode);
896 operands[5] = operand_subword (operands[1], 0, 0, TImode);
900 [(set (match_operand:TI 0 "register_operand" "")
901 (match_operand:TI 1 "memory_operand" ""))]
902 "TARGET_64BIT && reload_completed
903 && !s_operand (operands[1], VOIDmode)"
904 [(set (match_dup 0) (match_dup 1))]
906 rtx addr = operand_subword (operands[0], 1, 0, TImode);
907 s390_load_address (addr, XEXP (operands[1], 0));
908 operands[1] = replace_equiv_address (operands[1], addr);
913 ; Patterns used for secondary reloads
916 ; Handles loading a PLUS (load address) expression
918 (define_expand "reload<mode>_plus"
919 [(parallel [(match_operand:P 0 "register_operand" "=a")
920 (match_operand:P 1 "s390_plus_operand" "")
921 (match_operand:P 2 "register_operand" "=&a")])]
924 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
928 ; Handles assessing a non-offsetable memory address
930 (define_expand "reload<mode>_nonoffmem_in"
931 [(parallel [(match_operand 0 "register_operand" "")
932 (match_operand 1 "" "")
933 (match_operand:P 2 "register_operand" "=&a")])]
936 gcc_assert (MEM_P (operands[1]));
937 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
938 operands[1] = replace_equiv_address (operands[1], operands[2]);
939 emit_move_insn (operands[0], operands[1]);
943 (define_expand "reload<mode>_nonoffmem_out"
944 [(parallel [(match_operand 0 "" "")
945 (match_operand 1 "register_operand" "")
946 (match_operand:P 2 "register_operand" "=&a")])]
949 gcc_assert (MEM_P (operands[0]));
950 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
951 operands[0] = replace_equiv_address (operands[0], operands[2]);
952 emit_move_insn (operands[0], operands[1]);
957 ; movdi instruction pattern(s).
960 (define_expand "movdi"
961 [(set (match_operand:DI 0 "general_operand" "")
962 (match_operand:DI 1 "general_operand" ""))]
965 /* Handle symbolic constants. */
967 && (SYMBOLIC_CONST (operands[1])
968 || (GET_CODE (operands[1]) == PLUS
969 && XEXP (operands[1], 0) == pic_offset_table_rtx
970 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
971 emit_symbolic_move (operands);
974 (define_insn "*movdi_larl"
975 [(set (match_operand:DI 0 "register_operand" "=d")
976 (match_operand:DI 1 "larl_operand" "X"))]
978 && !FP_REG_P (operands[0])"
980 [(set_attr "op_type" "RIL")
981 (set_attr "type" "larl")])
983 (define_insn "*movdi_64dfp"
984 [(set (match_operand:DI 0 "nonimmediate_operand"
985 "=d,d,d,d,d,d,d,d,f,d,d,d,d,
986 m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
987 (match_operand:DI 1 "general_operand"
988 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,d,m,
989 d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
990 "TARGET_64BIT && TARGET_DFP"
1016 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RRE,RXY,RXY,
1017 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
1018 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,lr,load,store,
1019 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
1021 (define_insn "*movdi_64extimm"
1022 [(set (match_operand:DI 0 "nonimmediate_operand"
1023 "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1024 (match_operand:DI 1 "general_operand"
1025 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1026 "TARGET_64BIT && TARGET_EXTIMM"
1050 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
1051 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
1052 (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
1053 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
1055 (define_insn "*movdi_64"
1056 [(set (match_operand:DI 0 "nonimmediate_operand"
1057 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1058 (match_operand:DI 1 "general_operand"
1059 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1060 "TARGET_64BIT && !TARGET_EXTIMM"
1081 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
1082 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
1083 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
1084 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
1087 [(set (match_operand:DI 0 "register_operand" "")
1088 (match_operand:DI 1 "register_operand" ""))]
1089 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1090 [(set (match_dup 2) (match_dup 3))
1091 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1092 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1093 "operands[2] = gen_lowpart (SImode, operands[0]);
1094 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1097 [(set (match_operand:DI 0 "register_operand" "")
1098 (match_operand:DI 1 "register_operand" ""))]
1099 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1100 && dead_or_set_p (insn, operands[1])"
1101 [(set (match_dup 3) (match_dup 2))
1102 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1103 (set (match_dup 4) (match_dup 2))]
1104 "operands[2] = gen_lowpart (SImode, operands[1]);
1105 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1108 [(set (match_operand:DI 0 "register_operand" "")
1109 (match_operand:DI 1 "register_operand" ""))]
1110 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1111 && !dead_or_set_p (insn, operands[1])"
1112 [(set (match_dup 3) (match_dup 2))
1113 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1114 (set (match_dup 4) (match_dup 2))
1115 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1116 "operands[2] = gen_lowpart (SImode, operands[1]);
1117 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1119 (define_insn "*movdi_31"
1120 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
1121 (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1136 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1137 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1140 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1141 (match_operand:DI 1 "general_operand" ""))]
1142 "!TARGET_64BIT && reload_completed
1143 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1144 [(set (match_dup 2) (match_dup 4))
1145 (set (match_dup 3) (match_dup 5))]
1147 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1148 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1149 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1150 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1154 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1155 (match_operand:DI 1 "general_operand" ""))]
1156 "!TARGET_64BIT && reload_completed
1157 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1158 [(set (match_dup 2) (match_dup 4))
1159 (set (match_dup 3) (match_dup 5))]
1161 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1162 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1163 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1164 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1168 [(set (match_operand:DI 0 "register_operand" "")
1169 (match_operand:DI 1 "memory_operand" ""))]
1170 "!TARGET_64BIT && reload_completed
1171 && !FP_REG_P (operands[0])
1172 && !s_operand (operands[1], VOIDmode)"
1173 [(set (match_dup 0) (match_dup 1))]
1175 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1176 s390_load_address (addr, XEXP (operands[1], 0));
1177 operands[1] = replace_equiv_address (operands[1], addr);
1181 [(set (match_operand:DI 0 "register_operand" "")
1182 (mem:DI (match_operand 1 "address_operand" "")))]
1184 && !FP_REG_P (operands[0])
1185 && GET_CODE (operands[1]) == SYMBOL_REF
1186 && CONSTANT_POOL_ADDRESS_P (operands[1])
1187 && get_pool_mode (operands[1]) == DImode
1188 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1189 [(set (match_dup 0) (match_dup 2))]
1190 "operands[2] = get_pool_constant (operands[1]);")
1192 (define_insn "*la_64"
1193 [(set (match_operand:DI 0 "register_operand" "=d,d")
1194 (match_operand:QI 1 "address_operand" "U,W"))]
1199 [(set_attr "op_type" "RX,RXY")
1200 (set_attr "type" "la")])
1204 [(set (match_operand:DI 0 "register_operand" "")
1205 (match_operand:QI 1 "address_operand" ""))
1206 (clobber (reg:CC CC_REGNUM))])]
1208 && preferred_la_operand_p (operands[1], const0_rtx)"
1209 [(set (match_dup 0) (match_dup 1))]
1213 [(set (match_operand:DI 0 "register_operand" "")
1214 (match_operand:DI 1 "register_operand" ""))
1217 (plus:DI (match_dup 0)
1218 (match_operand:DI 2 "nonmemory_operand" "")))
1219 (clobber (reg:CC CC_REGNUM))])]
1221 && !reg_overlap_mentioned_p (operands[0], operands[2])
1222 && preferred_la_operand_p (operands[1], operands[2])"
1223 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1227 ; movsi instruction pattern(s).
1230 (define_expand "movsi"
1231 [(set (match_operand:SI 0 "general_operand" "")
1232 (match_operand:SI 1 "general_operand" ""))]
1235 /* Handle symbolic constants. */
1237 && (SYMBOLIC_CONST (operands[1])
1238 || (GET_CODE (operands[1]) == PLUS
1239 && XEXP (operands[1], 0) == pic_offset_table_rtx
1240 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1241 emit_symbolic_move (operands);
1244 (define_insn "*movsi_larl"
1245 [(set (match_operand:SI 0 "register_operand" "=d")
1246 (match_operand:SI 1 "larl_operand" "X"))]
1247 "!TARGET_64BIT && TARGET_CPU_ZARCH
1248 && !FP_REG_P (operands[0])"
1250 [(set_attr "op_type" "RIL")
1251 (set_attr "type" "larl")])
1253 (define_insn "*movsi_zarch"
1254 [(set (match_operand:SI 0 "nonimmediate_operand"
1255 "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1256 (match_operand:SI 1 "general_operand"
1257 "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1280 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1281 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1282 (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1283 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1285 (define_insn "*movsi_esa"
1286 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1287 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1302 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1303 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1306 [(set (match_operand:SI 0 "register_operand" "")
1307 (mem:SI (match_operand 1 "address_operand" "")))]
1308 "!FP_REG_P (operands[0])
1309 && GET_CODE (operands[1]) == SYMBOL_REF
1310 && CONSTANT_POOL_ADDRESS_P (operands[1])
1311 && get_pool_mode (operands[1]) == SImode
1312 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1313 [(set (match_dup 0) (match_dup 2))]
1314 "operands[2] = get_pool_constant (operands[1]);")
1316 (define_insn "*la_31"
1317 [(set (match_operand:SI 0 "register_operand" "=d,d")
1318 (match_operand:QI 1 "address_operand" "U,W"))]
1319 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1323 [(set_attr "op_type" "RX,RXY")
1324 (set_attr "type" "la")])
1328 [(set (match_operand:SI 0 "register_operand" "")
1329 (match_operand:QI 1 "address_operand" ""))
1330 (clobber (reg:CC CC_REGNUM))])]
1332 && preferred_la_operand_p (operands[1], const0_rtx)"
1333 [(set (match_dup 0) (match_dup 1))]
1337 [(set (match_operand:SI 0 "register_operand" "")
1338 (match_operand:SI 1 "register_operand" ""))
1341 (plus:SI (match_dup 0)
1342 (match_operand:SI 2 "nonmemory_operand" "")))
1343 (clobber (reg:CC CC_REGNUM))])]
1345 && !reg_overlap_mentioned_p (operands[0], operands[2])
1346 && preferred_la_operand_p (operands[1], operands[2])"
1347 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1350 (define_insn "*la_31_and"
1351 [(set (match_operand:SI 0 "register_operand" "=d,d")
1352 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1353 (const_int 2147483647)))]
1358 [(set_attr "op_type" "RX,RXY")
1359 (set_attr "type" "la")])
1361 (define_insn_and_split "*la_31_and_cc"
1362 [(set (match_operand:SI 0 "register_operand" "=d")
1363 (and:SI (match_operand:QI 1 "address_operand" "p")
1364 (const_int 2147483647)))
1365 (clobber (reg:CC CC_REGNUM))]
1368 "&& reload_completed"
1370 (and:SI (match_dup 1) (const_int 2147483647)))]
1372 [(set_attr "op_type" "RX")
1373 (set_attr "type" "la")])
1375 (define_insn "force_la_31"
1376 [(set (match_operand:SI 0 "register_operand" "=d,d")
1377 (match_operand:QI 1 "address_operand" "U,W"))
1378 (use (const_int 0))]
1383 [(set_attr "op_type" "RX")
1384 (set_attr "type" "la")])
1387 ; movhi instruction pattern(s).
1390 (define_expand "movhi"
1391 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1392 (match_operand:HI 1 "general_operand" ""))]
1395 /* Make it explicit that loading a register from memory
1396 always sign-extends (at least) to SImode. */
1397 if (optimize && !no_new_pseudos
1398 && register_operand (operands[0], VOIDmode)
1399 && GET_CODE (operands[1]) == MEM)
1401 rtx tmp = gen_reg_rtx (SImode);
1402 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1403 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1404 operands[1] = gen_lowpart (HImode, tmp);
1408 (define_insn "*movhi"
1409 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1410 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1420 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1421 (set_attr "type" "lr,*,*,*,store,store,*")])
1424 [(set (match_operand:HI 0 "register_operand" "")
1425 (mem:HI (match_operand 1 "address_operand" "")))]
1426 "GET_CODE (operands[1]) == SYMBOL_REF
1427 && CONSTANT_POOL_ADDRESS_P (operands[1])
1428 && get_pool_mode (operands[1]) == HImode
1429 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1430 [(set (match_dup 0) (match_dup 2))]
1431 "operands[2] = get_pool_constant (operands[1]);")
1434 ; movqi instruction pattern(s).
1437 (define_expand "movqi"
1438 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1439 (match_operand:QI 1 "general_operand" ""))]
1442 /* On z/Architecture, zero-extending from memory to register
1443 is just as fast as a QImode load. */
1444 if (TARGET_ZARCH && optimize && !no_new_pseudos
1445 && register_operand (operands[0], VOIDmode)
1446 && GET_CODE (operands[1]) == MEM)
1448 rtx tmp = gen_reg_rtx (word_mode);
1449 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1450 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1451 operands[1] = gen_lowpart (QImode, tmp);
1455 (define_insn "*movqi"
1456 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1457 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1469 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1470 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1473 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1474 (mem:QI (match_operand 1 "address_operand" "")))]
1475 "GET_CODE (operands[1]) == SYMBOL_REF
1476 && CONSTANT_POOL_ADDRESS_P (operands[1])
1477 && get_pool_mode (operands[1]) == QImode
1478 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1479 [(set (match_dup 0) (match_dup 2))]
1480 "operands[2] = get_pool_constant (operands[1]);")
1483 ; movstrictqi instruction pattern(s).
1486 (define_insn "*movstrictqi"
1487 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1488 (match_operand:QI 1 "memory_operand" "R,T"))]
1493 [(set_attr "op_type" "RX,RXY")])
1496 ; movstricthi instruction pattern(s).
1499 (define_insn "*movstricthi"
1500 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1501 (match_operand:HI 1 "memory_operand" "Q,S"))
1502 (clobber (reg:CC CC_REGNUM))]
1507 [(set_attr "op_type" "RS,RSY")])
1510 ; movstrictsi instruction pattern(s).
1513 (define_insn "movstrictsi"
1514 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1515 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1522 [(set_attr "op_type" "RR,RX,RXY,RRE")
1523 (set_attr "type" "lr,load,load,*")])
1526 ; mov(tf|td) instruction pattern(s).
1529 (define_expand "mov<mode>"
1530 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1531 (match_operand:TD_TF 1 "general_operand" ""))]
1535 (define_insn "*mov<mode>_64"
1536 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o,Q")
1537 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dm,d,Q"))]
1549 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*,*")
1550 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*,*")])
1552 (define_insn "*mov<mode>_31"
1553 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,Q")
1554 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,Q"))]
1562 [(set_attr "op_type" "RRE,RRE,*,*,*")
1563 (set_attr "type" "fsimptf,fsimptf,*,*,*")])
1565 ; TFmode in GPRs splitters
1568 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1569 (match_operand:TD_TF 1 "general_operand" ""))]
1570 "TARGET_64BIT && reload_completed
1571 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1572 [(set (match_dup 2) (match_dup 4))
1573 (set (match_dup 3) (match_dup 5))]
1575 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1576 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
1577 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
1578 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
1582 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1583 (match_operand:TD_TF 1 "general_operand" ""))]
1584 "TARGET_64BIT && reload_completed
1585 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1586 [(set (match_dup 2) (match_dup 4))
1587 (set (match_dup 3) (match_dup 5))]
1589 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1590 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
1591 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
1592 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
1596 [(set (match_operand:TD_TF 0 "register_operand" "")
1597 (match_operand:TD_TF 1 "memory_operand" ""))]
1598 "TARGET_64BIT && reload_completed
1599 && !FP_REG_P (operands[0])
1600 && !s_operand (operands[1], VOIDmode)"
1601 [(set (match_dup 0) (match_dup 1))]
1603 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
1604 s390_load_address (addr, XEXP (operands[1], 0));
1605 operands[1] = replace_equiv_address (operands[1], addr);
1608 ; TFmode in BFPs splitters
1611 [(set (match_operand:TD_TF 0 "register_operand" "")
1612 (match_operand:TD_TF 1 "memory_operand" ""))]
1613 "reload_completed && offsettable_memref_p (operands[1])
1614 && FP_REG_P (operands[0])"
1615 [(set (match_dup 2) (match_dup 4))
1616 (set (match_dup 3) (match_dup 5))]
1618 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
1620 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
1622 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
1623 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
1627 [(set (match_operand:TD_TF 0 "memory_operand" "")
1628 (match_operand:TD_TF 1 "register_operand" ""))]
1629 "reload_completed && offsettable_memref_p (operands[0])
1630 && FP_REG_P (operands[1])"
1631 [(set (match_dup 2) (match_dup 4))
1632 (set (match_dup 3) (match_dup 5))]
1634 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
1635 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
1636 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
1638 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
1643 ; mov(df|dd) instruction pattern(s).
1646 (define_expand "mov<mode>"
1647 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
1648 (match_operand:DD_DF 1 "general_operand" ""))]
1652 (define_insn "*mov<mode>_64dfp"
1653 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
1654 "=f,f,f,d,f,f,R,T,d,d,m,?Q")
1655 (match_operand:DD_DF 1 "general_operand"
1656 "G,f,d,f,R,T,f,f,d,m,d,?Q"))]
1657 "TARGET_64BIT && TARGET_DFP"
1671 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1672 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
1673 fstoredf,fstoredf,lr,load,store,*")])
1675 (define_insn "*mov<mode>_64"
1676 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1677 (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1690 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1691 (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>,
1692 fstore<bfp>,fstore<bfp>,lr,load,store,*")])
1694 (define_insn "*mov<mode>_31"
1695 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
1696 "=f,f,f,f,R,T,d,d,Q,S, d,o,Q")
1697 (match_operand:DD_DF 1 "general_operand"
1698 " G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1714 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1715 (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>,
1716 fstore<bfp>,fstore<bfp>,lm,lm,stm,stm,*,*,*")])
1719 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
1720 (match_operand:DD_DF 1 "general_operand" ""))]
1721 "!TARGET_64BIT && reload_completed
1722 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1723 [(set (match_dup 2) (match_dup 4))
1724 (set (match_dup 3) (match_dup 5))]
1726 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1727 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
1728 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
1729 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
1733 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
1734 (match_operand:DD_DF 1 "general_operand" ""))]
1735 "!TARGET_64BIT && reload_completed
1736 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1737 [(set (match_dup 2) (match_dup 4))
1738 (set (match_dup 3) (match_dup 5))]
1740 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1741 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
1742 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
1743 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
1747 [(set (match_operand:DD_DF 0 "register_operand" "")
1748 (match_operand:DD_DF 1 "memory_operand" ""))]
1749 "!TARGET_64BIT && reload_completed
1750 && !FP_REG_P (operands[0])
1751 && !s_operand (operands[1], VOIDmode)"
1752 [(set (match_dup 0) (match_dup 1))]
1754 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
1755 s390_load_address (addr, XEXP (operands[1], 0));
1756 operands[1] = replace_equiv_address (operands[1], addr);
1760 ; mov(sf|sd) instruction pattern(s).
1763 (define_insn "mov<mode>"
1764 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
1765 "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1766 (match_operand:SD_SF 1 "general_operand"
1767 " G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1782 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1783 (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>,
1784 fstore<bfp>,fstore<bfp>,lr,load,load,store,store,*")])
1787 ; movcc instruction pattern
1790 (define_insn "movcc"
1791 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1792 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1802 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1803 (set_attr "type" "lr,*,*,store,store,load,load")])
1806 ; Block move (MVC) patterns.
1810 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1811 (match_operand:BLK 1 "memory_operand" "Q"))
1812 (use (match_operand 2 "const_int_operand" "n"))]
1813 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1814 "mvc\t%O0(%2,%R0),%S1"
1815 [(set_attr "op_type" "SS")])
1818 [(set (match_operand 0 "memory_operand" "")
1819 (match_operand 1 "memory_operand" ""))]
1821 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1822 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1824 [(set (match_dup 0) (match_dup 1))
1825 (use (match_dup 2))])]
1827 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1828 operands[0] = adjust_address (operands[0], BLKmode, 0);
1829 operands[1] = adjust_address (operands[1], BLKmode, 0);
1834 [(set (match_operand:BLK 0 "memory_operand" "")
1835 (match_operand:BLK 1 "memory_operand" ""))
1836 (use (match_operand 2 "const_int_operand" ""))])
1838 [(set (match_operand:BLK 3 "memory_operand" "")
1839 (match_operand:BLK 4 "memory_operand" ""))
1840 (use (match_operand 5 "const_int_operand" ""))])]
1841 "s390_offset_p (operands[0], operands[3], operands[2])
1842 && s390_offset_p (operands[1], operands[4], operands[2])
1843 && !s390_overlap_p (operands[0], operands[1],
1844 INTVAL (operands[2]) + INTVAL (operands[5]))
1845 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1847 [(set (match_dup 6) (match_dup 7))
1848 (use (match_dup 8))])]
1849 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1850 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1851 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1855 ; load_multiple pattern(s).
1857 ; ??? Due to reload problems with replacing registers inside match_parallel
1858 ; we currently support load_multiple/store_multiple only after reload.
1861 (define_expand "load_multiple"
1862 [(match_par_dup 3 [(set (match_operand 0 "" "")
1863 (match_operand 1 "" ""))
1864 (use (match_operand 2 "" ""))])]
1867 enum machine_mode mode;
1873 /* Support only loading a constant number of fixed-point registers from
1874 memory and only bother with this if more than two */
1875 if (GET_CODE (operands[2]) != CONST_INT
1876 || INTVAL (operands[2]) < 2
1877 || INTVAL (operands[2]) > 16
1878 || GET_CODE (operands[1]) != MEM
1879 || GET_CODE (operands[0]) != REG
1880 || REGNO (operands[0]) >= 16)
1883 count = INTVAL (operands[2]);
1884 regno = REGNO (operands[0]);
1885 mode = GET_MODE (operands[0]);
1886 if (mode != SImode && mode != word_mode)
1889 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1892 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1894 from = XEXP (operands[1], 0);
1897 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1898 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1899 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1901 from = XEXP (XEXP (operands[1], 0), 0);
1902 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1909 from = force_reg (Pmode, XEXP (operands[1], 0));
1913 for (i = 0; i < count; i++)
1914 XVECEXP (operands[3], 0, i)
1915 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1916 change_address (operands[1], mode,
1917 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1920 (define_insn "*load_multiple_di"
1921 [(match_parallel 0 "load_multiple_operation"
1922 [(set (match_operand:DI 1 "register_operand" "=r")
1923 (match_operand:DI 2 "s_operand" "QS"))])]
1924 "reload_completed && word_mode == DImode"
1926 int words = XVECLEN (operands[0], 0);
1927 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1928 return "lmg\t%1,%0,%S2";
1930 [(set_attr "op_type" "RSY")
1931 (set_attr "type" "lm")])
1933 (define_insn "*load_multiple_si"
1934 [(match_parallel 0 "load_multiple_operation"
1935 [(set (match_operand:SI 1 "register_operand" "=r,r")
1936 (match_operand:SI 2 "s_operand" "Q,S"))])]
1939 int words = XVECLEN (operands[0], 0);
1940 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1941 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1943 [(set_attr "op_type" "RS,RSY")
1944 (set_attr "type" "lm")])
1947 ; store multiple pattern(s).
1950 (define_expand "store_multiple"
1951 [(match_par_dup 3 [(set (match_operand 0 "" "")
1952 (match_operand 1 "" ""))
1953 (use (match_operand 2 "" ""))])]
1956 enum machine_mode mode;
1962 /* Support only storing a constant number of fixed-point registers to
1963 memory and only bother with this if more than two. */
1964 if (GET_CODE (operands[2]) != CONST_INT
1965 || INTVAL (operands[2]) < 2
1966 || INTVAL (operands[2]) > 16
1967 || GET_CODE (operands[0]) != MEM
1968 || GET_CODE (operands[1]) != REG
1969 || REGNO (operands[1]) >= 16)
1972 count = INTVAL (operands[2]);
1973 regno = REGNO (operands[1]);
1974 mode = GET_MODE (operands[1]);
1975 if (mode != SImode && mode != word_mode)
1978 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1982 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1984 to = XEXP (operands[0], 0);
1987 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1988 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1989 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1991 to = XEXP (XEXP (operands[0], 0), 0);
1992 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1999 to = force_reg (Pmode, XEXP (operands[0], 0));
2003 for (i = 0; i < count; i++)
2004 XVECEXP (operands[3], 0, i)
2005 = gen_rtx_SET (VOIDmode,
2006 change_address (operands[0], mode,
2007 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
2008 gen_rtx_REG (mode, regno + i));
2011 (define_insn "*store_multiple_di"
2012 [(match_parallel 0 "store_multiple_operation"
2013 [(set (match_operand:DI 1 "s_operand" "=QS")
2014 (match_operand:DI 2 "register_operand" "r"))])]
2015 "reload_completed && word_mode == DImode"
2017 int words = XVECLEN (operands[0], 0);
2018 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2019 return "stmg\t%2,%0,%S1";
2021 [(set_attr "op_type" "RSY")
2022 (set_attr "type" "stm")])
2025 (define_insn "*store_multiple_si"
2026 [(match_parallel 0 "store_multiple_operation"
2027 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2028 (match_operand:SI 2 "register_operand" "r,r"))])]
2031 int words = XVECLEN (operands[0], 0);
2032 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2033 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2035 [(set_attr "op_type" "RS,RSY")
2036 (set_attr "type" "stm")])
2039 ;; String instructions.
2042 (define_insn "*execute"
2043 [(match_parallel 0 ""
2044 [(unspec [(match_operand 1 "register_operand" "a")
2045 (match_operand:BLK 2 "memory_operand" "R")
2046 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2047 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2048 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2050 [(set_attr "op_type" "RX")
2051 (set_attr "type" "cs")])
2055 ; strlenM instruction pattern(s).
2058 (define_expand "strlen<mode>"
2059 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2062 (unspec:P [(const_int 0)
2063 (match_operand:BLK 1 "memory_operand" "")
2065 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2066 (clobber (scratch:P))
2067 (clobber (reg:CC CC_REGNUM))])
2069 [(set (match_operand:P 0 "register_operand" "")
2070 (minus:P (match_dup 4) (match_dup 5)))
2071 (clobber (reg:CC CC_REGNUM))])]
2074 operands[4] = gen_reg_rtx (Pmode);
2075 operands[5] = gen_reg_rtx (Pmode);
2076 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2077 operands[1] = replace_equiv_address (operands[1], operands[5]);
2080 (define_insn "*strlen<mode>"
2081 [(set (match_operand:P 0 "register_operand" "=a")
2082 (unspec:P [(match_operand:P 2 "general_operand" "0")
2083 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2085 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2086 (clobber (match_scratch:P 1 "=a"))
2087 (clobber (reg:CC CC_REGNUM))]
2089 "srst\t%0,%1\;jo\t.-4"
2090 [(set_attr "length" "8")
2091 (set_attr "type" "vs")])
2094 ; cmpstrM instruction pattern(s).
2097 (define_expand "cmpstrsi"
2098 [(set (reg:SI 0) (const_int 0))
2100 [(clobber (match_operand 3 "" ""))
2101 (clobber (match_dup 4))
2102 (set (reg:CCU CC_REGNUM)
2103 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2104 (match_operand:BLK 2 "memory_operand" "")))
2107 [(set (match_operand:SI 0 "register_operand" "=d")
2108 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2109 (clobber (reg:CC CC_REGNUM))])]
2112 /* As the result of CMPINT is inverted compared to what we need,
2113 we have to swap the operands. */
2114 rtx op1 = operands[2];
2115 rtx op2 = operands[1];
2116 rtx addr1 = gen_reg_rtx (Pmode);
2117 rtx addr2 = gen_reg_rtx (Pmode);
2119 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2120 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2121 operands[1] = replace_equiv_address_nv (op1, addr1);
2122 operands[2] = replace_equiv_address_nv (op2, addr2);
2123 operands[3] = addr1;
2124 operands[4] = addr2;
2127 (define_insn "*cmpstr<mode>"
2128 [(clobber (match_operand:P 0 "register_operand" "=d"))
2129 (clobber (match_operand:P 1 "register_operand" "=d"))
2130 (set (reg:CCU CC_REGNUM)
2131 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2132 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2135 "clst\t%0,%1\;jo\t.-4"
2136 [(set_attr "length" "8")
2137 (set_attr "type" "vs")])
2140 ; movstr instruction pattern.
2143 (define_expand "movstr"
2144 [(set (reg:SI 0) (const_int 0))
2146 [(clobber (match_dup 3))
2147 (set (match_operand:BLK 1 "memory_operand" "")
2148 (match_operand:BLK 2 "memory_operand" ""))
2149 (set (match_operand 0 "register_operand" "")
2150 (unspec [(match_dup 1)
2152 (reg:SI 0)] UNSPEC_MVST))
2153 (clobber (reg:CC CC_REGNUM))])]
2156 rtx addr1 = gen_reg_rtx (Pmode);
2157 rtx addr2 = gen_reg_rtx (Pmode);
2159 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2160 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2161 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2162 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2163 operands[3] = addr2;
2166 (define_insn "*movstr"
2167 [(clobber (match_operand:P 2 "register_operand" "=d"))
2168 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2169 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2170 (set (match_operand:P 0 "register_operand" "=d")
2171 (unspec [(mem:BLK (match_dup 1))
2172 (mem:BLK (match_dup 3))
2173 (reg:SI 0)] UNSPEC_MVST))
2174 (clobber (reg:CC CC_REGNUM))]
2176 "mvst\t%1,%2\;jo\t.-4"
2177 [(set_attr "length" "8")
2178 (set_attr "type" "vs")])
2182 ; movmemM instruction pattern(s).
2185 (define_expand "movmem<mode>"
2186 [(set (match_operand:BLK 0 "memory_operand" "")
2187 (match_operand:BLK 1 "memory_operand" ""))
2188 (use (match_operand:GPR 2 "general_operand" ""))
2189 (match_operand 3 "" "")]
2191 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2193 ; Move a block that is up to 256 bytes in length.
2194 ; The block length is taken as (operands[2] % 256) + 1.
2196 (define_expand "movmem_short"
2198 [(set (match_operand:BLK 0 "memory_operand" "")
2199 (match_operand:BLK 1 "memory_operand" ""))
2200 (use (match_operand 2 "nonmemory_operand" ""))
2201 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2202 (clobber (match_dup 3))])]
2204 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2206 (define_insn "*movmem_short"
2207 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2208 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
2209 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2210 (use (match_operand 3 "immediate_operand" "X,R,X"))
2211 (clobber (match_scratch 4 "=X,X,&a"))]
2212 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2213 && GET_MODE (operands[4]) == Pmode"
2215 [(set_attr "type" "cs")])
2218 [(set (match_operand:BLK 0 "memory_operand" "")
2219 (match_operand:BLK 1 "memory_operand" ""))
2220 (use (match_operand 2 "const_int_operand" ""))
2221 (use (match_operand 3 "immediate_operand" ""))
2222 (clobber (scratch))]
2225 [(set (match_dup 0) (match_dup 1))
2226 (use (match_dup 2))])]
2227 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2230 [(set (match_operand:BLK 0 "memory_operand" "")
2231 (match_operand:BLK 1 "memory_operand" ""))
2232 (use (match_operand 2 "register_operand" ""))
2233 (use (match_operand 3 "memory_operand" ""))
2234 (clobber (scratch))]
2237 [(unspec [(match_dup 2) (match_dup 3)
2238 (const_int 0)] UNSPEC_EXECUTE)
2239 (set (match_dup 0) (match_dup 1))
2240 (use (const_int 1))])]
2244 [(set (match_operand:BLK 0 "memory_operand" "")
2245 (match_operand:BLK 1 "memory_operand" ""))
2246 (use (match_operand 2 "register_operand" ""))
2247 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2248 (clobber (match_operand 3 "register_operand" ""))]
2249 "reload_completed && TARGET_CPU_ZARCH"
2250 [(set (match_dup 3) (label_ref (match_dup 4)))
2252 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2253 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2254 (set (match_dup 0) (match_dup 1))
2255 (use (const_int 1))])]
2256 "operands[4] = gen_label_rtx ();")
2258 ; Move a block of arbitrary length.
2260 (define_expand "movmem_long"
2262 [(clobber (match_dup 2))
2263 (clobber (match_dup 3))
2264 (set (match_operand:BLK 0 "memory_operand" "")
2265 (match_operand:BLK 1 "memory_operand" ""))
2266 (use (match_operand 2 "general_operand" ""))
2268 (clobber (reg:CC CC_REGNUM))])]
2271 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2272 rtx reg0 = gen_reg_rtx (dword_mode);
2273 rtx reg1 = gen_reg_rtx (dword_mode);
2274 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2275 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2276 rtx len0 = gen_lowpart (Pmode, reg0);
2277 rtx len1 = gen_lowpart (Pmode, reg1);
2279 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2280 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2281 emit_move_insn (len0, operands[2]);
2283 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2284 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2285 emit_move_insn (len1, operands[2]);
2287 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2288 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2293 (define_insn "*movmem_long"
2294 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2295 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2296 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2297 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2300 (clobber (reg:CC CC_REGNUM))]
2302 "mvcle\t%0,%1,0\;jo\t.-4"
2303 [(set_attr "length" "8")
2304 (set_attr "type" "vs")])
2311 (define_expand "isinf<mode>2"
2312 [(set (reg:CCZ CC_REGNUM)
2313 (unspec:CCZ [(match_operand:BFP 1 "register_operand" "f")
2316 (set (match_operand:SI 0 "register_operand" "=d")
2317 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2320 operands[2] = GEN_INT (S390_TDC_INFINITY);
2323 ; This insn is used to generate all variants of the Test Data Class
2324 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2325 ; is the register to be tested and the second one is the bit mask
2326 ; specifying the required test(s).
2328 (define_insn "*TDC_insn_<mode>"
2329 [(set (reg:CCZ CC_REGNUM)
2330 (unspec:CCZ [(match_operand:BFP 0 "register_operand" "f")
2331 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2334 [(set_attr "op_type" "RXE")
2335 (set_attr "type" "fsimp<mode>")])
2337 (define_insn_and_split "*ccz_to_int"
2338 [(set (match_operand:SI 0 "register_operand" "=d")
2339 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2340 UNSPEC_CCZ_TO_INT))]
2344 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2348 ; setmemM instruction pattern(s).
2351 (define_expand "setmem<mode>"
2352 [(set (match_operand:BLK 0 "memory_operand" "")
2353 (match_operand:QI 2 "general_operand" ""))
2354 (use (match_operand:GPR 1 "general_operand" ""))
2355 (match_operand 3 "" "")]
2357 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2359 ; Clear a block that is up to 256 bytes in length.
2360 ; The block length is taken as (operands[1] % 256) + 1.
2362 (define_expand "clrmem_short"
2364 [(set (match_operand:BLK 0 "memory_operand" "")
2366 (use (match_operand 1 "nonmemory_operand" ""))
2367 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2368 (clobber (match_dup 2))
2369 (clobber (reg:CC CC_REGNUM))])]
2371 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2373 (define_insn "*clrmem_short"
2374 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2376 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2377 (use (match_operand 2 "immediate_operand" "X,R,X"))
2378 (clobber (match_scratch 3 "=X,X,&a"))
2379 (clobber (reg:CC CC_REGNUM))]
2380 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2381 && GET_MODE (operands[3]) == Pmode"
2383 [(set_attr "type" "cs")])
2386 [(set (match_operand:BLK 0 "memory_operand" "")
2388 (use (match_operand 1 "const_int_operand" ""))
2389 (use (match_operand 2 "immediate_operand" ""))
2391 (clobber (reg:CC CC_REGNUM))]
2394 [(set (match_dup 0) (const_int 0))
2396 (clobber (reg:CC CC_REGNUM))])]
2397 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2400 [(set (match_operand:BLK 0 "memory_operand" "")
2402 (use (match_operand 1 "register_operand" ""))
2403 (use (match_operand 2 "memory_operand" ""))
2405 (clobber (reg:CC CC_REGNUM))]
2408 [(unspec [(match_dup 1) (match_dup 2)
2409 (const_int 0)] UNSPEC_EXECUTE)
2410 (set (match_dup 0) (const_int 0))
2412 (clobber (reg:CC CC_REGNUM))])]
2416 [(set (match_operand:BLK 0 "memory_operand" "")
2418 (use (match_operand 1 "register_operand" ""))
2419 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2420 (clobber (match_operand 2 "register_operand" ""))
2421 (clobber (reg:CC CC_REGNUM))]
2422 "reload_completed && TARGET_CPU_ZARCH"
2423 [(set (match_dup 2) (label_ref (match_dup 3)))
2425 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2426 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2427 (set (match_dup 0) (const_int 0))
2429 (clobber (reg:CC CC_REGNUM))])]
2430 "operands[3] = gen_label_rtx ();")
2432 ; Initialize a block of arbitrary length with (operands[2] % 256).
2434 (define_expand "setmem_long"
2436 [(clobber (match_dup 1))
2437 (set (match_operand:BLK 0 "memory_operand" "")
2438 (match_operand 2 "shift_count_or_setmem_operand" ""))
2439 (use (match_operand 1 "general_operand" ""))
2441 (clobber (reg:CC CC_REGNUM))])]
2444 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2445 rtx reg0 = gen_reg_rtx (dword_mode);
2446 rtx reg1 = gen_reg_rtx (dword_mode);
2447 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2448 rtx len0 = gen_lowpart (Pmode, reg0);
2450 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2451 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2452 emit_move_insn (len0, operands[1]);
2454 emit_move_insn (reg1, const0_rtx);
2456 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2461 (define_insn "*setmem_long"
2462 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2463 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2464 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2466 (use (match_operand:<DBL> 1 "register_operand" "d"))
2467 (clobber (reg:CC CC_REGNUM))]
2469 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2470 [(set_attr "length" "8")
2471 (set_attr "type" "vs")])
2473 (define_insn "*setmem_long_and"
2474 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2475 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2476 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2477 (match_operand 4 "const_int_operand" "n")))
2479 (use (match_operand:<DBL> 1 "register_operand" "d"))
2480 (clobber (reg:CC CC_REGNUM))]
2481 "(INTVAL (operands[4]) & 255) == 255"
2482 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2483 [(set_attr "length" "8")
2484 (set_attr "type" "vs")])
2486 ; cmpmemM instruction pattern(s).
2489 (define_expand "cmpmemsi"
2490 [(set (match_operand:SI 0 "register_operand" "")
2491 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2492 (match_operand:BLK 2 "memory_operand" "") ) )
2493 (use (match_operand:SI 3 "general_operand" ""))
2494 (use (match_operand:SI 4 "" ""))]
2496 "s390_expand_cmpmem (operands[0], operands[1],
2497 operands[2], operands[3]); DONE;")
2499 ; Compare a block that is up to 256 bytes in length.
2500 ; The block length is taken as (operands[2] % 256) + 1.
2502 (define_expand "cmpmem_short"
2504 [(set (reg:CCU CC_REGNUM)
2505 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2506 (match_operand:BLK 1 "memory_operand" "")))
2507 (use (match_operand 2 "nonmemory_operand" ""))
2508 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2509 (clobber (match_dup 3))])]
2511 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2513 (define_insn "*cmpmem_short"
2514 [(set (reg:CCU CC_REGNUM)
2515 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2516 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2517 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2518 (use (match_operand 3 "immediate_operand" "X,R,X"))
2519 (clobber (match_scratch 4 "=X,X,&a"))]
2520 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2521 && GET_MODE (operands[4]) == Pmode"
2523 [(set_attr "type" "cs")])
2526 [(set (reg:CCU CC_REGNUM)
2527 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2528 (match_operand:BLK 1 "memory_operand" "")))
2529 (use (match_operand 2 "const_int_operand" ""))
2530 (use (match_operand 3 "immediate_operand" ""))
2531 (clobber (scratch))]
2534 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2535 (use (match_dup 2))])]
2536 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2539 [(set (reg:CCU CC_REGNUM)
2540 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2541 (match_operand:BLK 1 "memory_operand" "")))
2542 (use (match_operand 2 "register_operand" ""))
2543 (use (match_operand 3 "memory_operand" ""))
2544 (clobber (scratch))]
2547 [(unspec [(match_dup 2) (match_dup 3)
2548 (const_int 0)] UNSPEC_EXECUTE)
2549 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2550 (use (const_int 1))])]
2554 [(set (reg:CCU CC_REGNUM)
2555 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2556 (match_operand:BLK 1 "memory_operand" "")))
2557 (use (match_operand 2 "register_operand" ""))
2558 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2559 (clobber (match_operand 3 "register_operand" ""))]
2560 "reload_completed && TARGET_CPU_ZARCH"
2561 [(set (match_dup 3) (label_ref (match_dup 4)))
2563 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2564 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2565 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2566 (use (const_int 1))])]
2567 "operands[4] = gen_label_rtx ();")
2569 ; Compare a block of arbitrary length.
2571 (define_expand "cmpmem_long"
2573 [(clobber (match_dup 2))
2574 (clobber (match_dup 3))
2575 (set (reg:CCU CC_REGNUM)
2576 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2577 (match_operand:BLK 1 "memory_operand" "")))
2578 (use (match_operand 2 "general_operand" ""))
2579 (use (match_dup 3))])]
2582 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2583 rtx reg0 = gen_reg_rtx (dword_mode);
2584 rtx reg1 = gen_reg_rtx (dword_mode);
2585 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2586 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2587 rtx len0 = gen_lowpart (Pmode, reg0);
2588 rtx len1 = gen_lowpart (Pmode, reg1);
2590 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2591 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2592 emit_move_insn (len0, operands[2]);
2594 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2595 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2596 emit_move_insn (len1, operands[2]);
2598 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2599 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2604 (define_insn "*cmpmem_long"
2605 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2606 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2607 (set (reg:CCU CC_REGNUM)
2608 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2609 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2611 (use (match_dup 3))]
2613 "clcle\t%0,%1,0\;jo\t.-4"
2614 [(set_attr "length" "8")
2615 (set_attr "type" "vs")])
2617 ; Convert CCUmode condition code to integer.
2618 ; Result is zero if EQ, positive if LTU, negative if GTU.
2620 (define_insn_and_split "cmpint"
2621 [(set (match_operand:SI 0 "register_operand" "=d")
2622 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2624 (clobber (reg:CC CC_REGNUM))]
2628 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2630 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2631 (clobber (reg:CC CC_REGNUM))])])
2633 (define_insn_and_split "*cmpint_cc"
2634 [(set (reg CC_REGNUM)
2635 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2638 (set (match_operand:SI 0 "register_operand" "=d")
2639 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
2640 "s390_match_ccmode (insn, CCSmode)"
2642 "&& reload_completed"
2643 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2645 [(set (match_dup 2) (match_dup 3))
2646 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2648 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2649 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2650 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2653 (define_insn_and_split "*cmpint_sign"
2654 [(set (match_operand:DI 0 "register_operand" "=d")
2655 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2656 UNSPEC_CCU_TO_INT)))
2657 (clobber (reg:CC CC_REGNUM))]
2660 "&& reload_completed"
2661 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2663 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2664 (clobber (reg:CC CC_REGNUM))])])
2666 (define_insn_and_split "*cmpint_sign_cc"
2667 [(set (reg CC_REGNUM)
2668 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2669 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2670 UNSPEC_CCU_TO_INT) 0)
2671 (const_int 32)) (const_int 32))
2673 (set (match_operand:DI 0 "register_operand" "=d")
2674 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
2675 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2677 "&& reload_completed"
2678 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2680 [(set (match_dup 2) (match_dup 3))
2681 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2683 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2684 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2685 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2690 ;;- Conversion instructions.
2693 (define_insn "*sethighpartsi"
2694 [(set (match_operand:SI 0 "register_operand" "=d,d")
2695 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
2696 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2697 (clobber (reg:CC CC_REGNUM))]
2702 [(set_attr "op_type" "RS,RSY")])
2704 (define_insn "*sethighpartdi_64"
2705 [(set (match_operand:DI 0 "register_operand" "=d")
2706 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
2707 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
2708 (clobber (reg:CC CC_REGNUM))]
2711 [(set_attr "op_type" "RSY")])
2713 (define_insn "*sethighpartdi_31"
2714 [(set (match_operand:DI 0 "register_operand" "=d,d")
2715 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
2716 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2717 (clobber (reg:CC CC_REGNUM))]
2722 [(set_attr "op_type" "RS,RSY")])
2724 (define_insn_and_split "*extzv<mode>"
2725 [(set (match_operand:GPR 0 "register_operand" "=d")
2726 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2727 (match_operand 2 "const_int_operand" "n")
2729 (clobber (reg:CC CC_REGNUM))]
2730 "INTVAL (operands[2]) > 0
2731 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2733 "&& reload_completed"
2735 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2736 (clobber (reg:CC CC_REGNUM))])
2737 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
2739 int bitsize = INTVAL (operands[2]);
2740 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2741 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2743 operands[1] = adjust_address (operands[1], BLKmode, 0);
2744 set_mem_size (operands[1], GEN_INT (size));
2745 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2746 operands[3] = GEN_INT (mask);
2749 (define_insn_and_split "*extv<mode>"
2750 [(set (match_operand:GPR 0 "register_operand" "=d")
2751 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2752 (match_operand 2 "const_int_operand" "n")
2754 (clobber (reg:CC CC_REGNUM))]
2755 "INTVAL (operands[2]) > 0
2756 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2758 "&& reload_completed"
2760 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2761 (clobber (reg:CC CC_REGNUM))])
2763 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2764 (clobber (reg:CC CC_REGNUM))])]
2766 int bitsize = INTVAL (operands[2]);
2767 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2768 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2770 operands[1] = adjust_address (operands[1], BLKmode, 0);
2771 set_mem_size (operands[1], GEN_INT (size));
2772 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2773 operands[3] = GEN_INT (mask);
2777 ; insv instruction patterns
2780 (define_expand "insv"
2781 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2782 (match_operand 1 "const_int_operand" "")
2783 (match_operand 2 "const_int_operand" ""))
2784 (match_operand 3 "general_operand" ""))]
2787 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
2792 (define_insn "*insv<mode>_mem_reg"
2793 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
2794 (match_operand 1 "const_int_operand" "n,n")
2796 (match_operand:P 2 "register_operand" "d,d"))]
2797 "INTVAL (operands[1]) > 0
2798 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2799 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2801 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2803 operands[1] = GEN_INT ((1ul << size) - 1);
2804 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
2805 : "stcmy\t%2,%1,%S0";
2807 [(set_attr "op_type" "RS,RSY")])
2809 (define_insn "*insvdi_mem_reghigh"
2810 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
2811 (match_operand 1 "const_int_operand" "n")
2813 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
2816 && INTVAL (operands[1]) > 0
2817 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2818 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2820 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2822 operands[1] = GEN_INT ((1ul << size) - 1);
2823 return "stcmh\t%2,%1,%S0";
2825 [(set_attr "op_type" "RSY")])
2827 (define_insn "*insv<mode>_reg_imm"
2828 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2830 (match_operand 1 "const_int_operand" "n"))
2831 (match_operand:P 2 "const_int_operand" "n"))]
2833 && INTVAL (operands[1]) >= 0
2834 && INTVAL (operands[1]) < BITS_PER_WORD
2835 && INTVAL (operands[1]) % 16 == 0"
2837 switch (BITS_PER_WORD - INTVAL (operands[1]))
2839 case 64: return "iihh\t%0,%x2"; break;
2840 case 48: return "iihl\t%0,%x2"; break;
2841 case 32: return "iilh\t%0,%x2"; break;
2842 case 16: return "iill\t%0,%x2"; break;
2843 default: gcc_unreachable();
2846 [(set_attr "op_type" "RI")])
2848 (define_insn "*insv<mode>_reg_extimm"
2849 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2851 (match_operand 1 "const_int_operand" "n"))
2852 (match_operand:P 2 "const_int_operand" "n"))]
2854 && INTVAL (operands[1]) >= 0
2855 && INTVAL (operands[1]) < BITS_PER_WORD
2856 && INTVAL (operands[1]) % 32 == 0"
2858 switch (BITS_PER_WORD - INTVAL (operands[1]))
2860 case 64: return "iihf\t%0,%o2"; break;
2861 case 32: return "iilf\t%0,%o2"; break;
2862 default: gcc_unreachable();
2865 [(set_attr "op_type" "RIL")])
2868 ; extendsidi2 instruction pattern(s).
2871 (define_expand "extendsidi2"
2872 [(set (match_operand:DI 0 "register_operand" "")
2873 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2878 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2879 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2880 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2881 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2886 (define_insn "*extendsidi2"
2887 [(set (match_operand:DI 0 "register_operand" "=d,d")
2888 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2893 [(set_attr "op_type" "RRE,RXY")])
2896 ; extend(hi|qi)(si|di)2 instruction pattern(s).
2899 (define_expand "extend<HQI:mode><DSI:mode>2"
2900 [(set (match_operand:DSI 0 "register_operand" "")
2901 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2904 if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
2906 rtx tmp = gen_reg_rtx (SImode);
2907 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
2908 emit_insn (gen_extendsidi2 (operands[0], tmp));
2911 else if (!TARGET_EXTIMM)
2913 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
2914 GET_MODE_BITSIZE (<HQI:MODE>mode));
2916 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
2917 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
2918 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
2924 ; extendhidi2 instruction pattern(s).
2927 (define_insn "*extendhidi2_extimm"
2928 [(set (match_operand:DI 0 "register_operand" "=d,d")
2929 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2930 "TARGET_64BIT && TARGET_EXTIMM"
2934 [(set_attr "op_type" "RRE,RXY")])
2936 (define_insn "*extendhidi2"
2937 [(set (match_operand:DI 0 "register_operand" "=d")
2938 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2941 [(set_attr "op_type" "RXY")])
2944 ; extendhisi2 instruction pattern(s).
2947 (define_insn "*extendhisi2_extimm"
2948 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2949 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2955 [(set_attr "op_type" "RRE,RX,RXY")])
2957 (define_insn "*extendhisi2"
2958 [(set (match_operand:SI 0 "register_operand" "=d,d")
2959 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2964 [(set_attr "op_type" "RX,RXY")])
2967 ; extendqi(si|di)2 instruction pattern(s).
2970 ; lbr, lgbr, lb, lgb
2971 (define_insn "*extendqi<mode>2_extimm"
2972 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2973 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2978 [(set_attr "op_type" "RRE,RXY")])
2981 (define_insn "*extendqi<mode>2"
2982 [(set (match_operand:GPR 0 "register_operand" "=d")
2983 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))]
2984 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
2986 [(set_attr "op_type" "RXY")])
2988 (define_insn_and_split "*extendqi<mode>2_short_displ"
2989 [(set (match_operand:GPR 0 "register_operand" "=d")
2990 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
2991 (clobber (reg:CC CC_REGNUM))]
2992 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
2994 "&& reload_completed"
2996 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
2997 (clobber (reg:CC CC_REGNUM))])
2999 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3000 (clobber (reg:CC CC_REGNUM))])]
3002 operands[1] = adjust_address (operands[1], BLKmode, 0);
3003 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
3004 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3005 - GET_MODE_BITSIZE (QImode));
3009 ; zero_extendsidi2 instruction pattern(s).
3012 (define_expand "zero_extendsidi2"
3013 [(set (match_operand:DI 0 "register_operand" "")
3014 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3019 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
3020 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3021 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3026 (define_insn "*zero_extendsidi2"
3027 [(set (match_operand:DI 0 "register_operand" "=d,d")
3028 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
3033 [(set_attr "op_type" "RRE,RXY")])
3036 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3039 (define_insn "*llgt_sidi"
3040 [(set (match_operand:DI 0 "register_operand" "=d")
3041 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
3042 (const_int 2147483647)))]
3045 [(set_attr "op_type" "RXE")])
3047 (define_insn_and_split "*llgt_sidi_split"
3048 [(set (match_operand:DI 0 "register_operand" "=d")
3049 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
3050 (const_int 2147483647)))
3051 (clobber (reg:CC CC_REGNUM))]
3054 "&& reload_completed"
3056 (and:DI (subreg:DI (match_dup 1) 0)
3057 (const_int 2147483647)))]
3060 (define_insn "*llgt_sisi"
3061 [(set (match_operand:SI 0 "register_operand" "=d,d")
3062 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
3063 (const_int 2147483647)))]
3068 [(set_attr "op_type" "RRE,RXE")])
3070 (define_insn "*llgt_didi"
3071 [(set (match_operand:DI 0 "register_operand" "=d,d")
3072 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3073 (const_int 2147483647)))]
3078 [(set_attr "op_type" "RRE,RXE")])
3081 [(set (match_operand:GPR 0 "register_operand" "")
3082 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3083 (const_int 2147483647)))
3084 (clobber (reg:CC CC_REGNUM))]
3085 "TARGET_ZARCH && reload_completed"
3087 (and:GPR (match_dup 1)
3088 (const_int 2147483647)))]
3092 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3095 (define_expand "zero_extend<mode>di2"
3096 [(set (match_operand:DI 0 "register_operand" "")
3097 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3102 rtx tmp = gen_reg_rtx (SImode);
3103 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3104 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3107 else if (!TARGET_EXTIMM)
3109 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3110 GET_MODE_BITSIZE(<MODE>mode));
3111 operands[1] = gen_lowpart (DImode, operands[1]);
3112 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3113 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3118 (define_expand "zero_extend<mode>si2"
3119 [(set (match_operand:SI 0 "register_operand" "")
3120 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3125 operands[1] = gen_lowpart (SImode, operands[1]);
3126 emit_insn (gen_andsi3 (operands[0], operands[1],
3127 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3132 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3133 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3134 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3135 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
3140 [(set_attr "op_type" "RRE,RXY")])
3143 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3144 [(set (match_operand:GPR 0 "register_operand" "=d")
3145 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))]
3146 "TARGET_ZARCH && !TARGET_EXTIMM"
3148 [(set_attr "op_type" "RXY")])
3150 (define_insn_and_split "*zero_extendhisi2_31"
3151 [(set (match_operand:SI 0 "register_operand" "=&d")
3152 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3153 (clobber (reg:CC CC_REGNUM))]
3156 "&& reload_completed"
3157 [(set (match_dup 0) (const_int 0))
3159 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3160 (clobber (reg:CC CC_REGNUM))])]
3161 "operands[2] = gen_lowpart (HImode, operands[0]);")
3163 (define_insn_and_split "*zero_extendqisi2_31"
3164 [(set (match_operand:SI 0 "register_operand" "=&d")
3165 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
3168 "&& reload_completed"
3169 [(set (match_dup 0) (const_int 0))
3170 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3171 "operands[2] = gen_lowpart (QImode, operands[0]);")
3174 ; zero_extendqihi2 instruction pattern(s).
3177 (define_expand "zero_extendqihi2"
3178 [(set (match_operand:HI 0 "register_operand" "")
3179 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3180 "TARGET_ZARCH && !TARGET_EXTIMM"
3182 operands[1] = gen_lowpart (HImode, operands[1]);
3183 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3187 (define_insn "*zero_extendqihi2_64"
3188 [(set (match_operand:HI 0 "register_operand" "=d")
3189 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3190 "TARGET_ZARCH && !TARGET_EXTIMM"
3192 [(set_attr "op_type" "RXY")])
3194 (define_insn_and_split "*zero_extendqihi2_31"
3195 [(set (match_operand:HI 0 "register_operand" "=&d")
3196 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3199 "&& reload_completed"
3200 [(set (match_dup 0) (const_int 0))
3201 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3202 "operands[2] = gen_lowpart (QImode, operands[0]);")
3205 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3208 (define_expand "fixuns_truncdddi2"
3210 [(set (match_operand:DI 0 "register_operand" "")
3211 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3212 (clobber (match_scratch:TD 2 "=f"))])]
3214 "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3216 rtx label1 = gen_label_rtx ();
3217 rtx label2 = gen_label_rtx ();
3218 rtx temp = gen_reg_rtx (TDmode);
3219 REAL_VALUE_TYPE cmp, sub;
3221 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3222 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3224 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3225 solution is doing the check and the subtraction in TD mode and using a
3226 TD -> DI convert afterwards. */
3227 emit_insn (gen_extendddtd2 (temp, operands[1]));
3228 temp = force_reg (TDmode, temp);
3229 emit_insn (gen_cmptd (temp,
3230 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
3231 emit_jump_insn (gen_blt (label1));
3232 emit_insn (gen_subtd3 (temp, temp,
3233 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3234 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3237 emit_label (label1);
3238 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3239 emit_label (label2);
3243 (define_expand "fixuns_trunctddi2"
3244 [(set (match_operand:DI 0 "register_operand" "")
3245 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
3246 "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3248 rtx label1 = gen_label_rtx ();
3249 rtx label2 = gen_label_rtx ();
3250 rtx temp = gen_reg_rtx (TDmode);
3251 REAL_VALUE_TYPE cmp, sub;
3253 operands[1] = force_reg (TDmode, operands[1]);
3254 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3255 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3257 emit_insn (gen_cmptd (operands[1],
3258 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
3259 emit_jump_insn (gen_blt (label1));
3260 emit_insn (gen_subtd3 (temp, operands[1],
3261 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3262 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3265 emit_label (label1);
3266 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3267 emit_label (label2);
3272 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
3273 ; instruction pattern(s).
3276 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3277 [(set (match_operand:GPR 0 "register_operand" "")
3278 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
3281 rtx label1 = gen_label_rtx ();
3282 rtx label2 = gen_label_rtx ();
3283 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3284 REAL_VALUE_TYPE cmp, sub;
3286 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3287 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
3288 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
3290 emit_insn (gen_cmp<BFP:mode> (operands[1],
3291 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode)));
3292 emit_jump_insn (gen_blt (label1));
3293 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
3294 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
3295 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
3299 emit_label (label1);
3300 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
3301 operands[1], GEN_INT (5)));
3302 emit_label (label2);
3306 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
3307 [(set (match_operand:GPR 0 "register_operand" "")
3308 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
3311 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
3316 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
3317 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
3318 [(set (match_operand:GPR 0 "register_operand" "=d")
3319 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
3320 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3321 (clobber (reg:CC CC_REGNUM))]
3323 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
3324 [(set_attr "op_type" "RRE")
3325 (set_attr "type" "ftoi")])
3329 ; fix_trunc(td|dd)di2 instruction pattern(s).
3332 (define_expand "fix_trunc<mode>di2"
3333 [(set (match_operand:DI 0 "register_operand" "")
3334 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
3335 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3337 operands[1] = force_reg (<MODE>mode, operands[1]);
3338 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
3344 (define_insn "fix_trunc<DFP:mode>di2_dfp"
3345 [(set (match_operand:DI 0 "register_operand" "=d")
3346 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
3347 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3348 (clobber (reg:CC CC_REGNUM))]
3349 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3350 "cg<DFP:xde>tr\t%0,%h2,%1"
3351 [(set_attr "op_type" "RRF")
3352 (set_attr "type" "ftoi")])
3356 ; fix_trunctf(si|di)2 instruction pattern(s).
3359 (define_expand "fix_trunctf<mode>2"
3360 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3361 (fix:GPR (match_operand:TF 1 "register_operand" "")))
3362 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3363 (clobber (reg:CC CC_REGNUM))])]
3369 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
3372 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
3373 (define_insn "floatdi<mode>2"
3374 [(set (match_operand:FP 0 "register_operand" "=f")
3375 (float:FP (match_operand:DI 1 "register_operand" "d")))]
3376 "TARGET_64BIT && TARGET_HARD_FLOAT"
3377 "c<xde>g<bt>r\t%0,%1"
3378 [(set_attr "op_type" "RRE")
3379 (set_attr "type" "itof" )])
3381 ; cxfbr, cdfbr, cefbr
3382 (define_insn "floatsi<mode>2"
3383 [(set (match_operand:BFP 0 "register_operand" "=f")
3384 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
3387 [(set_attr "op_type" "RRE")
3388 (set_attr "type" "itof" )])
3392 ; truncdfsf2 instruction pattern(s).
3395 (define_insn "truncdfsf2"
3396 [(set (match_operand:SF 0 "register_operand" "=f")
3397 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3400 [(set_attr "op_type" "RRE")
3401 (set_attr "type" "ftruncdf")])
3404 ; trunctf(df|sf)2 instruction pattern(s).
3408 (define_insn "trunctf<mode>2"
3409 [(set (match_operand:DSF 0 "register_operand" "=f")
3410 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
3411 (clobber (match_scratch:TF 2 "=f"))]
3413 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
3414 [(set_attr "length" "6")
3415 (set_attr "type" "ftrunctf")])
3418 ; trunctddd2 and truncddsd2 instruction pattern(s).
3421 (define_insn "trunctddd2"
3422 [(set (match_operand:DD 0 "register_operand" "=f")
3423 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
3424 (clobber (match_scratch:TD 2 "=f"))]
3425 "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3426 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
3427 [(set_attr "length" "6")
3428 (set_attr "type" "ftrunctf")])
3430 (define_insn "truncddsd2"
3431 [(set (match_operand:SD 0 "register_operand" "=f")
3432 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
3433 "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3435 [(set_attr "op_type" "RRF")
3436 (set_attr "type" "fsimptf")])
3439 ; extend(sf|df)(df|tf)2 instruction pattern(s).
3442 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
3443 (define_insn "extend<DSF:mode><BFP:mode>2"
3444 [(set (match_operand:BFP 0 "register_operand" "=f,f")
3445 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
3447 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
3449 l<BFP:xde><DSF:xde>br\t%0,%1
3450 l<BFP:xde><DSF:xde>b\t%0,%1"
3451 [(set_attr "op_type" "RRE,RXE")
3452 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
3455 ; extendddtd2 and extendsddd2 instruction pattern(s).
3458 (define_insn "extendddtd2"
3459 [(set (match_operand:TD 0 "register_operand" "=f")
3460 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
3461 "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3463 [(set_attr "op_type" "RRF")
3464 (set_attr "type" "fsimptf")])
3466 (define_insn "extendsddd2"
3467 [(set (match_operand:DD 0 "register_operand" "=f")
3468 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
3469 "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3471 [(set_attr "op_type" "RRF")
3472 (set_attr "type" "fsimptf")])
3474 ; Binary <-> Decimal floating point trunc patterns
3477 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
3478 [(set (reg:DFP_ALL FPR0_REGNUM)
3479 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
3480 (use (reg:SI GPR0_REGNUM))
3481 (clobber (reg:CC CC_REGNUM))]
3482 "TARGET_HARD_FLOAT && TARGET_DFP"
3485 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
3486 [(set (reg:BFP FPR0_REGNUM)
3487 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
3488 (use (reg:SI GPR0_REGNUM))
3489 (clobber (reg:CC CC_REGNUM))]
3490 "TARGET_HARD_FLOAT && TARGET_DFP"
3493 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
3494 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
3495 (set (reg:SI GPR0_REGNUM) (match_dup 2))
3497 [(set (reg:DFP_ALL FPR0_REGNUM)
3498 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
3499 (use (reg:SI GPR0_REGNUM))
3500 (clobber (reg:CC CC_REGNUM))])
3501 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
3502 (reg:DFP_ALL FPR0_REGNUM))]
3503 "TARGET_HARD_FLOAT && TARGET_DFP
3504 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
3506 HOST_WIDE_INT flags;
3508 flags = (PFPO_CONVERT |
3509 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
3510 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
3512 operands[2] = GEN_INT (flags);
3515 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
3516 [(set (reg:DFP_ALL FPR2_REGNUM)
3517 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
3518 (set (reg:SI GPR0_REGNUM) (match_dup 2))
3520 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
3521 (use (reg:SI GPR0_REGNUM))
3522 (clobber (reg:CC CC_REGNUM))])
3523 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
3524 "TARGET_HARD_FLOAT && TARGET_DFP
3525 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
3527 HOST_WIDE_INT flags;
3529 flags = (PFPO_CONVERT |
3530 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
3531 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
3533 operands[2] = GEN_INT (flags);
3537 ; Binary <-> Decimal floating point extend patterns
3540 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
3541 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
3542 (use (reg:SI GPR0_REGNUM))
3543 (clobber (reg:CC CC_REGNUM))]
3544 "TARGET_HARD_FLOAT && TARGET_DFP"
3547 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
3548 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
3549 (use (reg:SI GPR0_REGNUM))
3550 (clobber (reg:CC CC_REGNUM))]
3551 "TARGET_HARD_FLOAT && TARGET_DFP"
3554 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
3555 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
3556 (set (reg:SI GPR0_REGNUM) (match_dup 2))
3558 [(set (reg:DFP_ALL FPR0_REGNUM)
3559 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
3560 (use (reg:SI GPR0_REGNUM))
3561 (clobber (reg:CC CC_REGNUM))])
3562 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
3563 (reg:DFP_ALL FPR0_REGNUM))]
3564 "TARGET_HARD_FLOAT && TARGET_DFP
3565 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
3567 HOST_WIDE_INT flags;
3569 flags = (PFPO_CONVERT |
3570 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
3571 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
3573 operands[2] = GEN_INT (flags);
3576 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
3577 [(set (reg:DFP_ALL FPR2_REGNUM)
3578 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
3579 (set (reg:SI GPR0_REGNUM) (match_dup 2))
3581 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
3582 (use (reg:SI GPR0_REGNUM))
3583 (clobber (reg:CC CC_REGNUM))])
3584 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
3585 "TARGET_HARD_FLOAT && TARGET_DFP
3586 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
3588 HOST_WIDE_INT flags;
3590 flags = (PFPO_CONVERT |
3591 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
3592 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
3594 operands[2] = GEN_INT (flags);
3599 ;; ARITHMETIC OPERATIONS
3601 ; arithmetic operations set the ConditionCode,
3602 ; because of unpredictable Bits in Register for Halfword and Byte
3603 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3606 ;;- Add instructions.
3610 ; addti3 instruction pattern(s).
3613 (define_insn_and_split "addti3"
3614 [(set (match_operand:TI 0 "register_operand" "=&d")
3615 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3616 (match_operand:TI 2 "general_operand" "do") ) )
3617 (clobber (reg:CC CC_REGNUM))]
3620 "&& reload_completed"
3622 [(set (reg:CCL1 CC_REGNUM)
3623 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3625 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3627 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3628 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3629 (clobber (reg:CC CC_REGNUM))])]
3630 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3631 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3632 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3633 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3634 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3635 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3638 ; adddi3 instruction pattern(s).
3641 (define_expand "adddi3"
3643 [(set (match_operand:DI 0 "register_operand" "")
3644 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3645 (match_operand:DI 2 "general_operand" "")))
3646 (clobber (reg:CC CC_REGNUM))])]
3650 (define_insn "*adddi3_sign"
3651 [(set (match_operand:DI 0 "register_operand" "=d,d")
3652 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3653 (match_operand:DI 1 "register_operand" "0,0")))
3654 (clobber (reg:CC CC_REGNUM))]
3659 [(set_attr "op_type" "RRE,RXY")])
3661 (define_insn "*adddi3_zero_cc"
3662 [(set (reg CC_REGNUM)
3663 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3664 (match_operand:DI 1 "register_operand" "0,0"))
3666 (set (match_operand:DI 0 "register_operand" "=d,d")
3667 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3668 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3672 [(set_attr "op_type" "RRE,RXY")])
3674 (define_insn "*adddi3_zero_cconly"
3675 [(set (reg CC_REGNUM)
3676 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3677 (match_operand:DI 1 "register_operand" "0,0"))
3679 (clobber (match_scratch:DI 0 "=d,d"))]
3680 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3684 [(set_attr "op_type" "RRE,RXY")])
3686 (define_insn "*adddi3_zero"
3687 [(set (match_operand:DI 0 "register_operand" "=d,d")
3688 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3689 (match_operand:DI 1 "register_operand" "0,0")))
3690 (clobber (reg:CC CC_REGNUM))]
3695 [(set_attr "op_type" "RRE,RXY")])
3697 (define_insn_and_split "*adddi3_31z"
3698 [(set (match_operand:DI 0 "register_operand" "=&d")
3699 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3700 (match_operand:DI 2 "general_operand" "do") ) )
3701 (clobber (reg:CC CC_REGNUM))]
3702 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3704 "&& reload_completed"
3706 [(set (reg:CCL1 CC_REGNUM)
3707 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3709 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3711 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3712 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3713 (clobber (reg:CC CC_REGNUM))])]
3714 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3715 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3716 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3717 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3718 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3719 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3721 (define_insn_and_split "*adddi3_31"
3722 [(set (match_operand:DI 0 "register_operand" "=&d")
3723 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3724 (match_operand:DI 2 "general_operand" "do") ) )
3725 (clobber (reg:CC CC_REGNUM))]
3728 "&& reload_completed"
3730 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3731 (clobber (reg:CC CC_REGNUM))])
3733 [(set (reg:CCL1 CC_REGNUM)
3734 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3736 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3738 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3740 (label_ref (match_dup 9))))
3742 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3743 (clobber (reg:CC CC_REGNUM))])
3745 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3746 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3747 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3748 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3749 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3750 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3751 operands[9] = gen_label_rtx ();")
3754 ; addsi3 instruction pattern(s).
3757 (define_expand "addsi3"
3759 [(set (match_operand:SI 0 "register_operand" "")
3760 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
3761 (match_operand:SI 2 "general_operand" "")))
3762 (clobber (reg:CC CC_REGNUM))])]
3766 (define_insn "*addsi3_sign"
3767 [(set (match_operand:SI 0 "register_operand" "=d,d")
3768 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3769 (match_operand:SI 1 "register_operand" "0,0")))
3770 (clobber (reg:CC CC_REGNUM))]
3775 [(set_attr "op_type" "RX,RXY")])
3778 ; add(di|si)3 instruction pattern(s).
3781 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag
3782 (define_insn "*add<mode>3"
3783 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d")
3784 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
3785 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T") ) )
3786 (clobber (reg:CC CC_REGNUM))]
3795 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY")])
3797 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
3798 (define_insn "*add<mode>3_carry1_cc"
3799 [(set (reg CC_REGNUM)
3800 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3801 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3803 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3804 (plus:GPR (match_dup 1) (match_dup 2)))]
3805 "s390_match_ccmode (insn, CCL1mode)"
3812 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3814 ; alr, al, aly, algr, alg
3815 (define_insn "*add<mode>3_carry1_cconly"
3816 [(set (reg CC_REGNUM)
3817 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3818 (match_operand:GPR 2 "general_operand" "d,R,T"))
3820 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3821 "s390_match_ccmode (insn, CCL1mode)"
3826 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3828 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
3829 (define_insn "*add<mode>3_carry2_cc"
3830 [(set (reg CC_REGNUM)
3831 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3832 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3834 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3835 (plus:GPR (match_dup 1) (match_dup 2)))]
3836 "s390_match_ccmode (insn, CCL1mode)"
3843 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3845 ; alr, al, aly, algr, alg
3846 (define_insn "*add<mode>3_carry2_cconly"
3847 [(set (reg CC_REGNUM)
3848 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3849 (match_operand:GPR 2 "general_operand" "d,R,T"))
3851 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3852 "s390_match_ccmode (insn, CCL1mode)"
3857 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3859 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
3860 (define_insn "*add<mode>3_cc"
3861 [(set (reg CC_REGNUM)
3862 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3863 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3865 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3866 (plus:GPR (match_dup 1) (match_dup 2)))]
3867 "s390_match_ccmode (insn, CCLmode)"
3874 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3876 ; alr, al, aly, algr, alg
3877 (define_insn "*add<mode>3_cconly"
3878 [(set (reg CC_REGNUM)
3879 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3880 (match_operand:GPR 2 "general_operand" "d,R,T"))
3882 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3883 "s390_match_ccmode (insn, CCLmode)"
3888 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3890 ; alr, al, aly, algr, alg
3891 (define_insn "*add<mode>3_cconly2"
3892 [(set (reg CC_REGNUM)
3893 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3894 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
3895 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3896 "s390_match_ccmode(insn, CCLmode)"
3901 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3903 ; ahi, afi, aghi, agfi
3904 (define_insn "*add<mode>3_imm_cc"
3905 [(set (reg CC_REGNUM)
3906 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3907 (match_operand:GPR 2 "const_int_operand" "K,Os"))
3909 (set (match_operand:GPR 0 "register_operand" "=d,d")
3910 (plus:GPR (match_dup 1) (match_dup 2)))]
3911 "s390_match_ccmode (insn, CCAmode)
3912 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3913 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3914 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
3918 [(set_attr "op_type" "RI,RIL")])
3921 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
3924 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
3925 (define_insn "add<mode>3"
3926 [(set (match_operand:FP 0 "register_operand" "=f, f")
3927 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
3928 (match_operand:FP 2 "general_operand" " f,<Rf>")))
3929 (clobber (reg:CC CC_REGNUM))]
3932 a<xde><bt>r\t%0,<op1>%2
3934 [(set_attr "op_type" "<RRer>,RXE")
3935 (set_attr "type" "fsimp<bfp>")])
3937 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
3938 (define_insn "*add<mode>3_cc"
3939 [(set (reg CC_REGNUM)
3940 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
3941 (match_operand:FP 2 "general_operand" " f,<Rf>"))
3942 (match_operand:FP 3 "const0_operand" "")))
3943 (set (match_operand:FP 0 "register_operand" "=f,f")
3944 (plus:FP (match_dup 1) (match_dup 2)))]
3945 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
3947 a<xde><bt>r\t%0,<op1>%2
3949 [(set_attr "op_type" "<RRer>,RXE")
3950 (set_attr "type" "fsimp<bfp>")])
3952 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
3953 (define_insn "*add<mode>3_cconly"
3954 [(set (reg CC_REGNUM)
3955 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
3956 (match_operand:FP 2 "general_operand" " f,<Rf>"))
3957 (match_operand:FP 3 "const0_operand" "")))
3958 (clobber (match_scratch:FP 0 "=f,f"))]
3959 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
3961 a<xde><bt>r\t%0,<op1>%2
3963 [(set_attr "op_type" "<RRer>,RXE")
3964 (set_attr "type" "fsimp<bfp>")])
3968 ;;- Subtract instructions.
3972 ; subti3 instruction pattern(s).
3975 (define_insn_and_split "subti3"
3976 [(set (match_operand:TI 0 "register_operand" "=&d")
3977 (minus:TI (match_operand:TI 1 "register_operand" "0")
3978 (match_operand:TI 2 "general_operand" "do") ) )
3979 (clobber (reg:CC CC_REGNUM))]
3982 "&& reload_completed"
3984 [(set (reg:CCL2 CC_REGNUM)
3985 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3987 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3989 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3990 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3991 (clobber (reg:CC CC_REGNUM))])]
3992 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3993 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3994 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3995 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3996 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3997 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4000 ; subdi3 instruction pattern(s).
4003 (define_expand "subdi3"
4005 [(set (match_operand:DI 0 "register_operand" "")
4006 (minus:DI (match_operand:DI 1 "register_operand" "")
4007 (match_operand:DI 2 "general_operand" "")))
4008 (clobber (reg:CC CC_REGNUM))])]
4012 (define_insn "*subdi3_sign"
4013 [(set (match_operand:DI 0 "register_operand" "=d,d")
4014 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4015 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
4016 (clobber (reg:CC CC_REGNUM))]
4021 [(set_attr "op_type" "RRE,RXY")])
4023 (define_insn "*subdi3_zero_cc"
4024 [(set (reg CC_REGNUM)
4025 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4026 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
4028 (set (match_operand:DI 0 "register_operand" "=d,d")
4029 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4030 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4034 [(set_attr "op_type" "RRE,RXY")])
4036 (define_insn "*subdi3_zero_cconly"
4037 [(set (reg CC_REGNUM)
4038 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4039 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
4041 (clobber (match_scratch:DI 0 "=d,d"))]
4042 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4046 [(set_attr "op_type" "RRE,RXY")])
4048 (define_insn "*subdi3_zero"
4049 [(set (match_operand:DI 0 "register_operand" "=d,d")
4050 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4051 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
4052 (clobber (reg:CC CC_REGNUM))]
4057 [(set_attr "op_type" "RRE,RXY")])
4059 (define_insn_and_split "*subdi3_31z"
4060 [(set (match_operand:DI 0 "register_operand" "=&d")
4061 (minus:DI (match_operand:DI 1 "register_operand" "0")
4062 (match_operand:DI 2 "general_operand" "do") ) )
4063 (clobber (reg:CC CC_REGNUM))]
4064 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4066 "&& reload_completed"
4068 [(set (reg:CCL2 CC_REGNUM)
4069 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4071 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4073 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4074 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4075 (clobber (reg:CC CC_REGNUM))])]
4076 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4077 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4078 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4079 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4080 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4081 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4083 (define_insn_and_split "*subdi3_31"
4084 [(set (match_operand:DI 0 "register_operand" "=&d")
4085 (minus:DI (match_operand:DI 1 "register_operand" "0")
4086 (match_operand:DI 2 "general_operand" "do") ) )
4087 (clobber (reg:CC CC_REGNUM))]
4090 "&& reload_completed"
4092 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4093 (clobber (reg:CC CC_REGNUM))])
4095 [(set (reg:CCL2 CC_REGNUM)
4096 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4098 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4100 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4102 (label_ref (match_dup 9))))
4104 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4105 (clobber (reg:CC CC_REGNUM))])
4107 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4108 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4109 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4110 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4111 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4112 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4113 operands[9] = gen_label_rtx ();")
4116 ; subsi3 instruction pattern(s).
4119 (define_expand "subsi3"
4121 [(set (match_operand:SI 0 "register_operand" "")
4122 (minus:SI (match_operand:SI 1 "register_operand" "")
4123 (match_operand:SI 2 "general_operand" "")))
4124 (clobber (reg:CC CC_REGNUM))])]
4128 (define_insn "*subsi3_sign"
4129 [(set (match_operand:SI 0 "register_operand" "=d,d")
4130 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4131 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4132 (clobber (reg:CC CC_REGNUM))]
4137 [(set_attr "op_type" "RX,RXY")])
4140 ; sub(di|si)3 instruction pattern(s).
4143 ; sr, s, sy, sgr, sg
4144 (define_insn "*sub<mode>3"
4145 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4146 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4147 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4148 (clobber (reg:CC CC_REGNUM))]
4154 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4156 ; slr, sl, sly, slgr, slg
4157 (define_insn "*sub<mode>3_borrow_cc"
4158 [(set (reg CC_REGNUM)
4159 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4160 (match_operand:GPR 2 "general_operand" "d,R,T"))
4162 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4163 (minus:GPR (match_dup 1) (match_dup 2)))]
4164 "s390_match_ccmode (insn, CCL2mode)"
4169 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4171 ; slr, sl, sly, slgr, slg
4172 (define_insn "*sub<mode>3_borrow_cconly"
4173 [(set (reg CC_REGNUM)
4174 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4175 (match_operand:GPR 2 "general_operand" "d,R,T"))
4177 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4178 "s390_match_ccmode (insn, CCL2mode)"
4183 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4185 ; slr, sl, sly, slgr, slg
4186 (define_insn "*sub<mode>3_cc"
4187 [(set (reg CC_REGNUM)
4188 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4189 (match_operand:GPR 2 "general_operand" "d,R,T"))
4191 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4192 (minus:GPR (match_dup 1) (match_dup 2)))]
4193 "s390_match_ccmode (insn, CCLmode)"
4198 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4200 ; slr, sl, sly, slgr, slg
4201 (define_insn "*sub<mode>3_cc2"
4202 [(set (reg CC_REGNUM)
4203 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4204 (match_operand:GPR 2 "general_operand" "d,R,T")))
4205 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4206 (minus:GPR (match_dup 1) (match_dup 2)))]
4207 "s390_match_ccmode (insn, CCL3mode)"
4212 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4214 ; slr, sl, sly, slgr, slg
4215 (define_insn "*sub<mode>3_cconly"
4216 [(set (reg CC_REGNUM)
4217 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4218 (match_operand:GPR 2 "general_operand" "d,R,T"))
4220 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4221 "s390_match_ccmode (insn, CCLmode)"
4226 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4228 ; slr, sl, sly, slgr, slg
4229 (define_insn "*sub<mode>3_cconly2"
4230 [(set (reg CC_REGNUM)
4231 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4232 (match_operand:GPR 2 "general_operand" "d,R,T")))
4233 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4234 "s390_match_ccmode (insn, CCL3mode)"
4239 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4242 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
4245 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
4246 (define_insn "sub<mode>3"
4247 [(set (match_operand:FP 0 "register_operand" "=f, f")
4248 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
4249 (match_operand:FP 2 "general_operand" "f,<Rf>")))
4250 (clobber (reg:CC CC_REGNUM))]
4253 s<xde><bt>r\t%0,<op1>%2
4255 [(set_attr "op_type" "<RRer>,RXE")
4256 (set_attr "type" "fsimp<bfp>")])
4258 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
4259 (define_insn "*sub<mode>3_cc"
4260 [(set (reg CC_REGNUM)
4261 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4262 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4263 (match_operand:FP 3 "const0_operand" "")))
4264 (set (match_operand:FP 0 "register_operand" "=f,f")
4265 (minus:FP (match_dup 1) (match_dup 2)))]
4266 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4268 s<xde><bt>r\t%0,<op1>%2
4270 [(set_attr "op_type" "<RRer>,RXE")
4271 (set_attr "type" "fsimp<bfp>")])
4273 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
4274 (define_insn "*sub<mode>3_cconly"
4275 [(set (reg CC_REGNUM)
4276 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4277 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4278 (match_operand:FP 3 "const0_operand" "")))
4279 (clobber (match_scratch:FP 0 "=f,f"))]
4280 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4282 s<xde><bt>r\t%0,<op1>%2
4284 [(set_attr "op_type" "<RRer>,RXE")
4285 (set_attr "type" "fsimp<bfp>")])
4289 ;;- Conditional add/subtract instructions.
4293 ; add(di|si)cc instruction pattern(s).
4296 ; alcr, alc, alcgr, alcg
4297 (define_insn "*add<mode>3_alc_cc"
4298 [(set (reg CC_REGNUM)
4300 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4301 (match_operand:GPR 2 "general_operand" "d,m"))
4302 (match_operand:GPR 3 "s390_alc_comparison" ""))
4304 (set (match_operand:GPR 0 "register_operand" "=d,d")
4305 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4306 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4310 [(set_attr "op_type" "RRE,RXY")])
4312 ; alcr, alc, alcgr, alcg
4313 (define_insn "*add<mode>3_alc"
4314 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4315 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4316 (match_operand:GPR 2 "general_operand" "d,m"))
4317 (match_operand:GPR 3 "s390_alc_comparison" "")))
4318 (clobber (reg:CC CC_REGNUM))]
4323 [(set_attr "op_type" "RRE,RXY")])
4325 ; slbr, slb, slbgr, slbg
4326 (define_insn "*sub<mode>3_slb_cc"
4327 [(set (reg CC_REGNUM)
4329 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4330 (match_operand:GPR 2 "general_operand" "d,m"))
4331 (match_operand:GPR 3 "s390_slb_comparison" ""))
4333 (set (match_operand:GPR 0 "register_operand" "=d,d")
4334 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4335 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4339 [(set_attr "op_type" "RRE,RXY")])
4341 ; slbr, slb, slbgr, slbg
4342 (define_insn "*sub<mode>3_slb"
4343 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4344 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4345 (match_operand:GPR 2 "general_operand" "d,m"))
4346 (match_operand:GPR 3 "s390_slb_comparison" "")))
4347 (clobber (reg:CC CC_REGNUM))]
4352 [(set_attr "op_type" "RRE,RXY")])
4354 (define_expand "add<mode>cc"
4355 [(match_operand:GPR 0 "register_operand" "")
4356 (match_operand 1 "comparison_operator" "")
4357 (match_operand:GPR 2 "register_operand" "")
4358 (match_operand:GPR 3 "const_int_operand" "")]
4360 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4361 s390_compare_op0, s390_compare_op1,
4362 operands[0], operands[2],
4363 operands[3])) FAIL; DONE;")
4366 ; scond instruction pattern(s).
4369 (define_insn_and_split "*scond<mode>"
4370 [(set (match_operand:GPR 0 "register_operand" "=&d")
4371 (match_operand:GPR 1 "s390_alc_comparison" ""))
4372 (clobber (reg:CC CC_REGNUM))]
4375 "&& reload_completed"
4376 [(set (match_dup 0) (const_int 0))
4378 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4380 (clobber (reg:CC CC_REGNUM))])]
4383 (define_insn_and_split "*scond<mode>_neg"
4384 [(set (match_operand:GPR 0 "register_operand" "=&d")
4385 (match_operand:GPR 1 "s390_slb_comparison" ""))
4386 (clobber (reg:CC CC_REGNUM))]
4389 "&& reload_completed"
4390 [(set (match_dup 0) (const_int 0))
4392 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4394 (clobber (reg:CC CC_REGNUM))])
4396 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4397 (clobber (reg:CC CC_REGNUM))])]
4401 (define_expand "s<code>"
4402 [(set (match_operand:SI 0 "register_operand" "")
4403 (SCOND (match_dup 0)
4406 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4407 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4409 (define_expand "seq"
4411 [(set (match_operand:SI 0 "register_operand" "=d")
4413 (clobber (reg:CC CC_REGNUM))])
4415 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4416 (clobber (reg:CC CC_REGNUM))])]
4419 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4421 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4422 PUT_MODE (operands[1], SImode);
4425 (define_insn_and_split "*sne"
4426 [(set (match_operand:SI 0 "register_operand" "=d")
4427 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4429 (clobber (reg:CC CC_REGNUM))]
4434 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4435 (clobber (reg:CC CC_REGNUM))])])
4439 ;;- Multiply instructions.
4443 ; muldi3 instruction pattern(s).
4446 (define_insn "*muldi3_sign"
4447 [(set (match_operand:DI 0 "register_operand" "=d,d")
4448 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4449 (match_operand:DI 1 "register_operand" "0,0")))]
4454 [(set_attr "op_type" "RRE,RXY")
4455 (set_attr "type" "imuldi")])
4457 (define_insn "muldi3"
4458 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4459 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4460 (match_operand:DI 2 "general_operand" "d,K,m")))]
4466 [(set_attr "op_type" "RRE,RI,RXY")
4467 (set_attr "type" "imuldi")])
4470 ; mulsi3 instruction pattern(s).
4473 (define_insn "*mulsi3_sign"
4474 [(set (match_operand:SI 0 "register_operand" "=d")
4475 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4476 (match_operand:SI 1 "register_operand" "0")))]
4479 [(set_attr "op_type" "RX")
4480 (set_attr "type" "imulhi")])
4482 (define_insn "mulsi3"
4483 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4484 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4485 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4492 [(set_attr "op_type" "RRE,RI,RX,RXY")
4493 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4496 ; mulsidi3 instruction pattern(s).
4499 (define_insn "mulsidi3"
4500 [(set (match_operand:DI 0 "register_operand" "=d,d")
4501 (mult:DI (sign_extend:DI
4502 (match_operand:SI 1 "register_operand" "%0,0"))
4504 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4509 [(set_attr "op_type" "RR,RX")
4510 (set_attr "type" "imulsi")])
4513 ; umulsidi3 instruction pattern(s).
4516 (define_insn "umulsidi3"
4517 [(set (match_operand:DI 0 "register_operand" "=d,d")
4518 (mult:DI (zero_extend:DI
4519 (match_operand:SI 1 "register_operand" "%0,0"))
4521 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4522 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4526 [(set_attr "op_type" "RRE,RXY")
4527 (set_attr "type" "imulsi")])
4530 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
4533 ; mxbr mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
4534 (define_insn "mul<mode>3"
4535 [(set (match_operand:FP 0 "register_operand" "=f,f")
4536 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4537 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
4540 m<xdee><bt>r\t%0,<op1>%2
4542 [(set_attr "op_type" "<RRer>,RXE")
4543 (set_attr "type" "fmul<bfp>")])
4545 ; maxbr, madbr, maebr, maxb, madb, maeb
4546 (define_insn "*fmadd<mode>"
4547 [(set (match_operand:DSF 0 "register_operand" "=f,f")
4548 (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
4549 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
4550 (match_operand:DSF 3 "register_operand" "0,0")))]
4551 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4555 [(set_attr "op_type" "RRE,RXE")
4556 (set_attr "type" "fmul<mode>")])
4558 ; msxbr, msdbr, msebr, msxb, msdb, mseb
4559 (define_insn "*fmsub<mode>"
4560 [(set (match_operand:DSF 0 "register_operand" "=f,f")
4561 (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
4562 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
4563 (match_operand:DSF 3 "register_operand" "0,0")))]
4564 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4568 [(set_attr "op_type" "RRE,RXE")
4569 (set_attr "type" "fmul<mode>")])
4572 ;;- Divide and modulo instructions.
4576 ; divmoddi4 instruction pattern(s).
4579 (define_expand "divmoddi4"
4580 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4581 (div:DI (match_operand:DI 1 "register_operand" "")
4582 (match_operand:DI 2 "general_operand" "")))
4583 (set (match_operand:DI 3 "general_operand" "")
4584 (mod:DI (match_dup 1) (match_dup 2)))])
4585 (clobber (match_dup 4))]
4588 rtx insn, div_equal, mod_equal;
4590 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4591 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4593 operands[4] = gen_reg_rtx(TImode);
4594 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4596 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4597 set_unique_reg_note (insn, REG_EQUAL, div_equal);
4599 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4600 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
4605 (define_insn "divmodtidi3"
4606 [(set (match_operand:TI 0 "register_operand" "=d,d")
4610 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4611 (match_operand:DI 2 "general_operand" "d,m")))
4613 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4618 [(set_attr "op_type" "RRE,RXY")
4619 (set_attr "type" "idiv")])
4621 (define_insn "divmodtisi3"
4622 [(set (match_operand:TI 0 "register_operand" "=d,d")
4626 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4628 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4631 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4636 [(set_attr "op_type" "RRE,RXY")
4637 (set_attr "type" "idiv")])
4640 ; udivmoddi4 instruction pattern(s).
4643 (define_expand "udivmoddi4"
4644 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4645 (udiv:DI (match_operand:DI 1 "general_operand" "")
4646 (match_operand:DI 2 "nonimmediate_operand" "")))
4647 (set (match_operand:DI 3 "general_operand" "")
4648 (umod:DI (match_dup 1) (match_dup 2)))])
4649 (clobber (match_dup 4))]
4652 rtx insn, div_equal, mod_equal, equal;
4654 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4655 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4656 equal = gen_rtx_IOR (TImode,
4657 gen_rtx_ASHIFT (TImode,
4658 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4660 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4662 operands[4] = gen_reg_rtx(TImode);
4663 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4664 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4665 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4667 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4668 set_unique_reg_note (insn, REG_EQUAL, equal);
4670 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4671 set_unique_reg_note (insn, REG_EQUAL, div_equal);
4673 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4674 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
4679 (define_insn "udivmodtidi3"
4680 [(set (match_operand:TI 0 "register_operand" "=d,d")
4685 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4687 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4691 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4696 [(set_attr "op_type" "RRE,RXY")
4697 (set_attr "type" "idiv")])
4700 ; divmodsi4 instruction pattern(s).
4703 (define_expand "divmodsi4"
4704 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4705 (div:SI (match_operand:SI 1 "general_operand" "")
4706 (match_operand:SI 2 "nonimmediate_operand" "")))
4707 (set (match_operand:SI 3 "general_operand" "")
4708 (mod:SI (match_dup 1) (match_dup 2)))])
4709 (clobber (match_dup 4))]
4712 rtx insn, div_equal, mod_equal, equal;
4714 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4715 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4716 equal = gen_rtx_IOR (DImode,
4717 gen_rtx_ASHIFT (DImode,
4718 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4720 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4722 operands[4] = gen_reg_rtx(DImode);
4723 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4725 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4726 set_unique_reg_note (insn, REG_EQUAL, equal);
4728 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4729 set_unique_reg_note (insn, REG_EQUAL, div_equal);
4731 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4732 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
4737 (define_insn "divmoddisi3"
4738 [(set (match_operand:DI 0 "register_operand" "=d,d")
4743 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4745 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4749 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4754 [(set_attr "op_type" "RR,RX")
4755 (set_attr "type" "idiv")])
4758 ; udivsi3 and umodsi3 instruction pattern(s).
4761 (define_expand "udivmodsi4"
4762 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4763 (udiv:SI (match_operand:SI 1 "general_operand" "")
4764 (match_operand:SI 2 "nonimmediate_operand" "")))
4765 (set (match_operand:SI 3 "general_operand" "")
4766 (umod:SI (match_dup 1) (match_dup 2)))])
4767 (clobber (match_dup 4))]
4768 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4770 rtx insn, div_equal, mod_equal, equal;
4772 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4773 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4774 equal = gen_rtx_IOR (DImode,
4775 gen_rtx_ASHIFT (DImode,
4776 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4778 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4780 operands[4] = gen_reg_rtx(DImode);
4781 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4782 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4783 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4785 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4786 set_unique_reg_note (insn, REG_EQUAL, equal);
4788 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4789 set_unique_reg_note (insn, REG_EQUAL, div_equal);
4791 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4792 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
4797 (define_insn "udivmoddisi3"
4798 [(set (match_operand:DI 0 "register_operand" "=d,d")
4803 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4805 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4809 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4810 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4814 [(set_attr "op_type" "RRE,RXY")
4815 (set_attr "type" "idiv")])
4817 (define_expand "udivsi3"
4818 [(set (match_operand:SI 0 "register_operand" "=d")
4819 (udiv:SI (match_operand:SI 1 "general_operand" "")
4820 (match_operand:SI 2 "general_operand" "")))
4821 (clobber (match_dup 3))]
4822 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4824 rtx insn, udiv_equal, umod_equal, equal;
4826 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4827 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4828 equal = gen_rtx_IOR (DImode,
4829 gen_rtx_ASHIFT (DImode,
4830 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4832 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4834 operands[3] = gen_reg_rtx (DImode);
4836 if (CONSTANT_P (operands[2]))
4838 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4840 rtx label1 = gen_label_rtx ();
4842 operands[1] = make_safe_from (operands[1], operands[0]);
4843 emit_move_insn (operands[0], const0_rtx);
4844 emit_insn (gen_cmpsi (operands[1], operands[2]));
4845 emit_jump_insn (gen_bltu (label1));
4846 emit_move_insn (operands[0], const1_rtx);
4847 emit_label (label1);
4851 operands[2] = force_reg (SImode, operands[2]);
4852 operands[2] = make_safe_from (operands[2], operands[0]);
4854 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4855 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4857 set_unique_reg_note (insn, REG_EQUAL, equal);
4859 insn = emit_move_insn (operands[0],
4860 gen_lowpart (SImode, operands[3]));
4861 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
4866 rtx label1 = gen_label_rtx ();
4867 rtx label2 = gen_label_rtx ();
4868 rtx label3 = gen_label_rtx ();
4870 operands[1] = force_reg (SImode, operands[1]);
4871 operands[1] = make_safe_from (operands[1], operands[0]);
4872 operands[2] = force_reg (SImode, operands[2]);
4873 operands[2] = make_safe_from (operands[2], operands[0]);
4875 emit_move_insn (operands[0], const0_rtx);
4876 emit_insn (gen_cmpsi (operands[2], operands[1]));
4877 emit_jump_insn (gen_bgtu (label3));
4878 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4879 emit_jump_insn (gen_blt (label2));
4880 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4881 emit_jump_insn (gen_beq (label1));
4882 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4883 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4885 set_unique_reg_note (insn, REG_EQUAL, equal);
4887 insn = emit_move_insn (operands[0],
4888 gen_lowpart (SImode, operands[3]));
4889 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
4892 emit_label (label1);
4893 emit_move_insn (operands[0], operands[1]);
4895 emit_label (label2);
4896 emit_move_insn (operands[0], const1_rtx);
4897 emit_label (label3);
4899 emit_move_insn (operands[0], operands[0]);
4903 (define_expand "umodsi3"
4904 [(set (match_operand:SI 0 "register_operand" "=d")
4905 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4906 (match_operand:SI 2 "nonimmediate_operand" "")))
4907 (clobber (match_dup 3))]
4908 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4910 rtx insn, udiv_equal, umod_equal, equal;
4912 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4913 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4914 equal = gen_rtx_IOR (DImode,
4915 gen_rtx_ASHIFT (DImode,
4916 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4918 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4920 operands[3] = gen_reg_rtx (DImode);
4922 if (CONSTANT_P (operands[2]))
4924 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4926 rtx label1 = gen_label_rtx ();
4928 operands[1] = make_safe_from (operands[1], operands[0]);
4929 emit_move_insn (operands[0], operands[1]);
4930 emit_insn (gen_cmpsi (operands[0], operands[2]));
4931 emit_jump_insn (gen_bltu (label1));
4932 emit_insn (gen_abssi2 (operands[0], operands[2]));
4933 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4934 emit_label (label1);
4938 operands[2] = force_reg (SImode, operands[2]);
4939 operands[2] = make_safe_from (operands[2], operands[0]);
4941 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4942 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4944 set_unique_reg_note (insn, REG_EQUAL, equal);
4946 insn = emit_move_insn (operands[0],
4947 gen_highpart (SImode, operands[3]));
4948 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
4953 rtx label1 = gen_label_rtx ();
4954 rtx label2 = gen_label_rtx ();
4955 rtx label3 = gen_label_rtx ();
4957 operands[1] = force_reg (SImode, operands[1]);
4958 operands[1] = make_safe_from (operands[1], operands[0]);
4959 operands[2] = force_reg (SImode, operands[2]);
4960 operands[2] = make_safe_from (operands[2], operands[0]);
4962 emit_move_insn(operands[0], operands[1]);
4963 emit_insn (gen_cmpsi (operands[2], operands[1]));
4964 emit_jump_insn (gen_bgtu (label3));
4965 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4966 emit_jump_insn (gen_blt (label2));
4967 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4968 emit_jump_insn (gen_beq (label1));
4969 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4970 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4972 set_unique_reg_note (insn, REG_EQUAL, equal);
4974 insn = emit_move_insn (operands[0],
4975 gen_highpart (SImode, operands[3]));
4976 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
4979 emit_label (label1);
4980 emit_move_insn (operands[0], const0_rtx);
4982 emit_label (label2);
4983 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4984 emit_label (label3);
4990 ; div(df|sf)3 instruction pattern(s).
4993 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
4994 (define_insn "div<mode>3"
4995 [(set (match_operand:FP 0 "register_operand" "=f,f")
4996 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
4997 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5000 d<xde><bt>r\t%0,<op1>%2
5002 [(set_attr "op_type" "<RRer>,RXE")
5003 (set_attr "type" "fdiv<bfp>")])
5007 ;;- And instructions.
5010 (define_expand "and<mode>3"
5011 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5012 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5013 (match_operand:INT 2 "general_operand" "")))
5014 (clobber (reg:CC CC_REGNUM))]
5016 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5019 ; anddi3 instruction pattern(s).
5022 (define_insn "*anddi3_cc"
5023 [(set (reg CC_REGNUM)
5024 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5025 (match_operand:DI 2 "general_operand" "d,m"))
5027 (set (match_operand:DI 0 "register_operand" "=d,d")
5028 (and:DI (match_dup 1) (match_dup 2)))]
5029 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5033 [(set_attr "op_type" "RRE,RXY")])
5035 (define_insn "*anddi3_cconly"
5036 [(set (reg CC_REGNUM)
5037 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5038 (match_operand:DI 2 "general_operand" "d,m"))
5040 (clobber (match_scratch:DI 0 "=d,d"))]
5041 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5042 /* Do not steal TM patterns. */
5043 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5047 [(set_attr "op_type" "RRE,RXY")])
5049 (define_insn "*anddi3_extimm"
5050 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5051 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5052 "%d,o,0,0,0,0,0,0,0,0,0,0")
5053 (match_operand:DI 2 "general_operand"
5054 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
5055 (clobber (reg:CC CC_REGNUM))]
5056 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5070 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5072 (define_insn "*anddi3"
5073 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5074 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5075 "%d,o,0,0,0,0,0,0,0,0")
5076 (match_operand:DI 2 "general_operand"
5077 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5078 (clobber (reg:CC CC_REGNUM))]
5079 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5091 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5094 [(set (match_operand:DI 0 "s_operand" "")
5095 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5096 (clobber (reg:CC CC_REGNUM))]
5099 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5100 (clobber (reg:CC CC_REGNUM))])]
5101 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5105 ; andsi3 instruction pattern(s).
5108 (define_insn "*andsi3_cc"
5109 [(set (reg CC_REGNUM)
5110 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5111 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5113 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5114 (and:SI (match_dup 1) (match_dup 2)))]
5115 "s390_match_ccmode(insn, CCTmode)"
5121 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5123 (define_insn "*andsi3_cconly"
5124 [(set (reg CC_REGNUM)
5125 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5126 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5128 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5129 "s390_match_ccmode(insn, CCTmode)
5130 /* Do not steal TM patterns. */
5131 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5137 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5139 (define_insn "*andsi3_zarch"
5140 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5141 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5142 "%d,o,0,0,0,0,0,0,0,0")
5143 (match_operand:SI 2 "general_operand"
5144 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5145 (clobber (reg:CC CC_REGNUM))]
5146 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5158 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
5160 (define_insn "*andsi3_esa"
5161 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5162 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5163 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5164 (clobber (reg:CC CC_REGNUM))]
5165 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5171 [(set_attr "op_type" "RR,RX,SI,SS")])
5174 [(set (match_operand:SI 0 "s_operand" "")
5175 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5176 (clobber (reg:CC CC_REGNUM))]
5179 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5180 (clobber (reg:CC CC_REGNUM))])]
5181 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5184 ; andhi3 instruction pattern(s).
5187 (define_insn "*andhi3_zarch"
5188 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5189 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5190 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5191 (clobber (reg:CC CC_REGNUM))]
5192 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5198 [(set_attr "op_type" "RR,RI,SI,SS")])
5200 (define_insn "*andhi3_esa"
5201 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5202 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5203 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5204 (clobber (reg:CC CC_REGNUM))]
5205 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5210 [(set_attr "op_type" "RR,SI,SS")])
5213 [(set (match_operand:HI 0 "s_operand" "")
5214 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5215 (clobber (reg:CC CC_REGNUM))]
5218 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5219 (clobber (reg:CC CC_REGNUM))])]
5220 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5223 ; andqi3 instruction pattern(s).
5226 (define_insn "*andqi3_zarch"
5227 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5228 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5229 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5230 (clobber (reg:CC CC_REGNUM))]
5231 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5238 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5240 (define_insn "*andqi3_esa"
5241 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5242 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5243 (match_operand:QI 2 "general_operand" "d,n,Q")))
5244 (clobber (reg:CC CC_REGNUM))]
5245 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5250 [(set_attr "op_type" "RR,SI,SS")])
5253 ; Block and (NC) patterns.
5257 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5258 (and:BLK (match_dup 0)
5259 (match_operand:BLK 1 "memory_operand" "Q")))
5260 (use (match_operand 2 "const_int_operand" "n"))
5261 (clobber (reg:CC CC_REGNUM))]
5262 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5263 "nc\t%O0(%2,%R0),%S1"
5264 [(set_attr "op_type" "SS")])
5267 [(set (match_operand 0 "memory_operand" "")
5269 (match_operand 1 "memory_operand" "")))
5270 (clobber (reg:CC CC_REGNUM))]
5272 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5273 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5275 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5277 (clobber (reg:CC CC_REGNUM))])]
5279 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5280 operands[0] = adjust_address (operands[0], BLKmode, 0);
5281 operands[1] = adjust_address (operands[1], BLKmode, 0);
5286 [(set (match_operand:BLK 0 "memory_operand" "")
5287 (and:BLK (match_dup 0)
5288 (match_operand:BLK 1 "memory_operand" "")))
5289 (use (match_operand 2 "const_int_operand" ""))
5290 (clobber (reg:CC CC_REGNUM))])
5292 [(set (match_operand:BLK 3 "memory_operand" "")
5293 (and:BLK (match_dup 3)
5294 (match_operand:BLK 4 "memory_operand" "")))
5295 (use (match_operand 5 "const_int_operand" ""))
5296 (clobber (reg:CC CC_REGNUM))])]
5297 "s390_offset_p (operands[0], operands[3], operands[2])
5298 && s390_offset_p (operands[1], operands[4], operands[2])
5299 && !s390_overlap_p (operands[0], operands[1],
5300 INTVAL (operands[2]) + INTVAL (operands[5]))
5301 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5303 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5305 (clobber (reg:CC CC_REGNUM))])]
5306 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5307 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5308 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5312 ;;- Bit set (inclusive or) instructions.
5315 (define_expand "ior<mode>3"
5316 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5317 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5318 (match_operand:INT 2 "general_operand" "")))
5319 (clobber (reg:CC CC_REGNUM))]
5321 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
5324 ; iordi3 instruction pattern(s).
5327 (define_insn "*iordi3_cc"
5328 [(set (reg CC_REGNUM)
5329 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5330 (match_operand:DI 2 "general_operand" "d,m"))
5332 (set (match_operand:DI 0 "register_operand" "=d,d")
5333 (ior:DI (match_dup 1) (match_dup 2)))]
5334 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5338 [(set_attr "op_type" "RRE,RXY")])
5340 (define_insn "*iordi3_cconly"
5341 [(set (reg CC_REGNUM)
5342 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5343 (match_operand:DI 2 "general_operand" "d,m"))
5345 (clobber (match_scratch:DI 0 "=d,d"))]
5346 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5350 [(set_attr "op_type" "RRE,RXY")])
5352 (define_insn "*iordi3_extimm"
5353 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5354 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5355 (match_operand:DI 2 "general_operand"
5356 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5357 (clobber (reg:CC CC_REGNUM))]
5358 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5370 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5372 (define_insn "*iordi3"
5373 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5374 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5375 (match_operand:DI 2 "general_operand"
5376 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5377 (clobber (reg:CC CC_REGNUM))]
5378 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5388 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5391 [(set (match_operand:DI 0 "s_operand" "")
5392 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5393 (clobber (reg:CC CC_REGNUM))]
5396 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5397 (clobber (reg:CC CC_REGNUM))])]
5398 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5401 ; iorsi3 instruction pattern(s).
5404 (define_insn "*iorsi3_cc"
5405 [(set (reg CC_REGNUM)
5406 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5407 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5409 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5410 (ior:SI (match_dup 1) (match_dup 2)))]
5411 "s390_match_ccmode(insn, CCTmode)"
5417 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5419 (define_insn "*iorsi3_cconly"
5420 [(set (reg CC_REGNUM)
5421 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5422 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5424 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5425 "s390_match_ccmode(insn, CCTmode)"
5431 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5433 (define_insn "*iorsi3_zarch"
5434 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5435 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5436 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5437 (clobber (reg:CC CC_REGNUM))]
5438 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5448 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5450 (define_insn "*iorsi3_esa"
5451 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5452 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5453 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5454 (clobber (reg:CC CC_REGNUM))]
5455 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5461 [(set_attr "op_type" "RR,RX,SI,SS")])
5464 [(set (match_operand:SI 0 "s_operand" "")
5465 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5466 (clobber (reg:CC CC_REGNUM))]
5469 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5470 (clobber (reg:CC CC_REGNUM))])]
5471 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5474 ; iorhi3 instruction pattern(s).
5477 (define_insn "*iorhi3_zarch"
5478 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5479 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5480 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5481 (clobber (reg:CC CC_REGNUM))]
5482 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5488 [(set_attr "op_type" "RR,RI,SI,SS")])
5490 (define_insn "*iorhi3_esa"
5491 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5492 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5493 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5494 (clobber (reg:CC CC_REGNUM))]
5495 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5500 [(set_attr "op_type" "RR,SI,SS")])
5503 [(set (match_operand:HI 0 "s_operand" "")
5504 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5505 (clobber (reg:CC CC_REGNUM))]
5508 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5509 (clobber (reg:CC CC_REGNUM))])]
5510 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5513 ; iorqi3 instruction pattern(s).
5516 (define_insn "*iorqi3_zarch"
5517 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5518 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5519 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5520 (clobber (reg:CC CC_REGNUM))]
5521 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5528 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5530 (define_insn "*iorqi3_esa"
5531 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5532 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5533 (match_operand:QI 2 "general_operand" "d,n,Q")))
5534 (clobber (reg:CC CC_REGNUM))]
5535 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5540 [(set_attr "op_type" "RR,SI,SS")])
5543 ; Block inclusive or (OC) patterns.
5547 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5548 (ior:BLK (match_dup 0)
5549 (match_operand:BLK 1 "memory_operand" "Q")))
5550 (use (match_operand 2 "const_int_operand" "n"))
5551 (clobber (reg:CC CC_REGNUM))]
5552 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5553 "oc\t%O0(%2,%R0),%S1"
5554 [(set_attr "op_type" "SS")])
5557 [(set (match_operand 0 "memory_operand" "")
5559 (match_operand 1 "memory_operand" "")))
5560 (clobber (reg:CC CC_REGNUM))]
5562 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5563 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5565 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5567 (clobber (reg:CC CC_REGNUM))])]
5569 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5570 operands[0] = adjust_address (operands[0], BLKmode, 0);
5571 operands[1] = adjust_address (operands[1], BLKmode, 0);
5576 [(set (match_operand:BLK 0 "memory_operand" "")
5577 (ior:BLK (match_dup 0)
5578 (match_operand:BLK 1 "memory_operand" "")))
5579 (use (match_operand 2 "const_int_operand" ""))
5580 (clobber (reg:CC CC_REGNUM))])
5582 [(set (match_operand:BLK 3 "memory_operand" "")
5583 (ior:BLK (match_dup 3)
5584 (match_operand:BLK 4 "memory_operand" "")))
5585 (use (match_operand 5 "const_int_operand" ""))
5586 (clobber (reg:CC CC_REGNUM))])]
5587 "s390_offset_p (operands[0], operands[3], operands[2])
5588 && s390_offset_p (operands[1], operands[4], operands[2])
5589 && !s390_overlap_p (operands[0], operands[1],
5590 INTVAL (operands[2]) + INTVAL (operands[5]))
5591 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5593 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5595 (clobber (reg:CC CC_REGNUM))])]
5596 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5597 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5598 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5602 ;;- Xor instructions.
5605 (define_expand "xor<mode>3"
5606 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5607 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5608 (match_operand:INT 2 "general_operand" "")))
5609 (clobber (reg:CC CC_REGNUM))]
5611 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5614 ; xordi3 instruction pattern(s).
5617 (define_insn "*xordi3_cc"
5618 [(set (reg CC_REGNUM)
5619 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5620 (match_operand:DI 2 "general_operand" "d,m"))
5622 (set (match_operand:DI 0 "register_operand" "=d,d")
5623 (xor:DI (match_dup 1) (match_dup 2)))]
5624 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5628 [(set_attr "op_type" "RRE,RXY")])
5630 (define_insn "*xordi3_cconly"
5631 [(set (reg CC_REGNUM)
5632 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5633 (match_operand:DI 2 "general_operand" "d,m"))
5635 (clobber (match_scratch:DI 0 "=d,d"))]
5636 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5640 [(set_attr "op_type" "RRE,RXY")])
5642 (define_insn "*xordi3_extimm"
5643 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5644 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5645 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5646 (clobber (reg:CC CC_REGNUM))]
5647 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5655 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
5657 (define_insn "*xordi3"
5658 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5659 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5660 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5661 (clobber (reg:CC CC_REGNUM))]
5662 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5668 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5671 [(set (match_operand:DI 0 "s_operand" "")
5672 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5673 (clobber (reg:CC CC_REGNUM))]
5676 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5677 (clobber (reg:CC CC_REGNUM))])]
5678 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5681 ; xorsi3 instruction pattern(s).
5684 (define_insn "*xorsi3_cc"
5685 [(set (reg CC_REGNUM)
5686 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5687 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5689 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5690 (xor:SI (match_dup 1) (match_dup 2)))]
5691 "s390_match_ccmode(insn, CCTmode)"
5697 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5699 (define_insn "*xorsi3_cconly"
5700 [(set (reg CC_REGNUM)
5701 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5702 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5704 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5705 "s390_match_ccmode(insn, CCTmode)"
5711 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5713 (define_insn "*xorsi3"
5714 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5715 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5716 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5717 (clobber (reg:CC CC_REGNUM))]
5718 "s390_logical_operator_ok_p (operands)"
5726 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
5729 [(set (match_operand:SI 0 "s_operand" "")
5730 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5731 (clobber (reg:CC CC_REGNUM))]
5734 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5735 (clobber (reg:CC CC_REGNUM))])]
5736 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5739 ; xorhi3 instruction pattern(s).
5742 (define_insn "*xorhi3"
5743 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5744 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5745 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
5746 (clobber (reg:CC CC_REGNUM))]
5747 "s390_logical_operator_ok_p (operands)"
5753 [(set_attr "op_type" "RIL,RR,SI,SS")])
5756 [(set (match_operand:HI 0 "s_operand" "")
5757 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5758 (clobber (reg:CC CC_REGNUM))]
5761 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5762 (clobber (reg:CC CC_REGNUM))])]
5763 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5766 ; xorqi3 instruction pattern(s).
5769 (define_insn "*xorqi3"
5770 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5771 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5772 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
5773 (clobber (reg:CC CC_REGNUM))]
5774 "s390_logical_operator_ok_p (operands)"
5781 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
5784 ; Block exclusive or (XC) patterns.
5788 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5789 (xor:BLK (match_dup 0)
5790 (match_operand:BLK 1 "memory_operand" "Q")))
5791 (use (match_operand 2 "const_int_operand" "n"))
5792 (clobber (reg:CC CC_REGNUM))]
5793 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5794 "xc\t%O0(%2,%R0),%S1"
5795 [(set_attr "op_type" "SS")])
5798 [(set (match_operand 0 "memory_operand" "")
5800 (match_operand 1 "memory_operand" "")))
5801 (clobber (reg:CC CC_REGNUM))]
5803 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5804 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5806 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5808 (clobber (reg:CC CC_REGNUM))])]
5810 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5811 operands[0] = adjust_address (operands[0], BLKmode, 0);
5812 operands[1] = adjust_address (operands[1], BLKmode, 0);
5817 [(set (match_operand:BLK 0 "memory_operand" "")
5818 (xor:BLK (match_dup 0)
5819 (match_operand:BLK 1 "memory_operand" "")))
5820 (use (match_operand 2 "const_int_operand" ""))
5821 (clobber (reg:CC CC_REGNUM))])
5823 [(set (match_operand:BLK 3 "memory_operand" "")
5824 (xor:BLK (match_dup 3)
5825 (match_operand:BLK 4 "memory_operand" "")))
5826 (use (match_operand 5 "const_int_operand" ""))
5827 (clobber (reg:CC CC_REGNUM))])]
5828 "s390_offset_p (operands[0], operands[3], operands[2])
5829 && s390_offset_p (operands[1], operands[4], operands[2])
5830 && !s390_overlap_p (operands[0], operands[1],
5831 INTVAL (operands[2]) + INTVAL (operands[5]))
5832 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5834 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5836 (clobber (reg:CC CC_REGNUM))])]
5837 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5838 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5839 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5842 ; Block xor (XC) patterns with src == dest.
5845 (define_insn "*xc_zero"
5846 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5848 (use (match_operand 1 "const_int_operand" "n"))
5849 (clobber (reg:CC CC_REGNUM))]
5850 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5851 "xc\t%O0(%1,%R0),%S0"
5852 [(set_attr "op_type" "SS")])
5856 [(set (match_operand:BLK 0 "memory_operand" "")
5858 (use (match_operand 1 "const_int_operand" ""))
5859 (clobber (reg:CC CC_REGNUM))])
5861 [(set (match_operand:BLK 2 "memory_operand" "")
5863 (use (match_operand 3 "const_int_operand" ""))
5864 (clobber (reg:CC CC_REGNUM))])]
5865 "s390_offset_p (operands[0], operands[2], operands[1])
5866 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5868 [(set (match_dup 4) (const_int 0))
5870 (clobber (reg:CC CC_REGNUM))])]
5871 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5872 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5876 ;;- Negate instructions.
5880 ; neg(di|si)2 instruction pattern(s).
5883 (define_expand "neg<mode>2"
5885 [(set (match_operand:DSI 0 "register_operand" "=d")
5886 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5887 (clobber (reg:CC CC_REGNUM))])]
5891 (define_insn "*negdi2_sign_cc"
5892 [(set (reg CC_REGNUM)
5893 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5894 (match_operand:SI 1 "register_operand" "d") 0)
5895 (const_int 32)) (const_int 32)))
5897 (set (match_operand:DI 0 "register_operand" "=d")
5898 (neg:DI (sign_extend:DI (match_dup 1))))]
5899 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5901 [(set_attr "op_type" "RRE")])
5903 (define_insn "*negdi2_sign"
5904 [(set (match_operand:DI 0 "register_operand" "=d")
5905 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5906 (clobber (reg:CC CC_REGNUM))]
5909 [(set_attr "op_type" "RRE")])
5912 (define_insn "*neg<mode>2_cc"
5913 [(set (reg CC_REGNUM)
5914 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5916 (set (match_operand:GPR 0 "register_operand" "=d")
5917 (neg:GPR (match_dup 1)))]
5918 "s390_match_ccmode (insn, CCAmode)"
5920 [(set_attr "op_type" "RR<E>")])
5923 (define_insn "*neg<mode>2_cconly"
5924 [(set (reg CC_REGNUM)
5925 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5927 (clobber (match_scratch:GPR 0 "=d"))]
5928 "s390_match_ccmode (insn, CCAmode)"
5930 [(set_attr "op_type" "RR<E>")])
5933 (define_insn "*neg<mode>2"
5934 [(set (match_operand:GPR 0 "register_operand" "=d")
5935 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5936 (clobber (reg:CC CC_REGNUM))]
5939 [(set_attr "op_type" "RR<E>")])
5941 (define_insn_and_split "*negdi2_31"
5942 [(set (match_operand:DI 0 "register_operand" "=d")
5943 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5944 (clobber (reg:CC CC_REGNUM))]
5947 "&& reload_completed"
5949 [(set (match_dup 2) (neg:SI (match_dup 3)))
5950 (clobber (reg:CC CC_REGNUM))])
5952 [(set (reg:CCAP CC_REGNUM)
5953 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5954 (set (match_dup 4) (neg:SI (match_dup 5)))])
5956 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5958 (label_ref (match_dup 6))))
5960 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5961 (clobber (reg:CC CC_REGNUM))])
5963 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5964 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5965 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5966 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5967 operands[6] = gen_label_rtx ();")
5970 ; neg(df|sf)2 instruction pattern(s).
5973 (define_expand "neg<mode>2"
5975 [(set (match_operand:BFP 0 "register_operand" "=f")
5976 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
5977 (clobber (reg:CC CC_REGNUM))])]
5981 ; lcxbr, lcdbr, lcebr
5982 (define_insn "*neg<mode>2_cc"
5983 [(set (reg CC_REGNUM)
5984 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
5985 (match_operand:BFP 2 "const0_operand" "")))
5986 (set (match_operand:BFP 0 "register_operand" "=f")
5987 (neg:BFP (match_dup 1)))]
5988 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5990 [(set_attr "op_type" "RRE")
5991 (set_attr "type" "fsimp<mode>")])
5993 ; lcxbr, lcdbr, lcebr
5994 (define_insn "*neg<mode>2_cconly"
5995 [(set (reg CC_REGNUM)
5996 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
5997 (match_operand:BFP 2 "const0_operand" "")))
5998 (clobber (match_scratch:BFP 0 "=f"))]
5999 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6001 [(set_attr "op_type" "RRE")
6002 (set_attr "type" "fsimp<mode>")])
6005 (define_insn "*neg<mode>2_nocc"
6006 [(set (match_operand:FP 0 "register_operand" "=f")
6007 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6008 "TARGET_HARD_FLOAT && TARGET_DFP"
6010 [(set_attr "op_type" "RRE")
6011 (set_attr "type" "fsimp<bfp>")])
6013 ; lcxbr, lcdbr, lcebr
6014 (define_insn "*neg<mode>2"
6015 [(set (match_operand:BFP 0 "register_operand" "=f")
6016 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6017 (clobber (reg:CC CC_REGNUM))]
6020 [(set_attr "op_type" "RRE")
6021 (set_attr "type" "fsimp<mode>")])
6025 ;;- Absolute value instructions.
6029 ; abs(di|si)2 instruction pattern(s).
6032 (define_insn "*absdi2_sign_cc"
6033 [(set (reg CC_REGNUM)
6034 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6035 (match_operand:SI 1 "register_operand" "d") 0)
6036 (const_int 32)) (const_int 32)))
6038 (set (match_operand:DI 0 "register_operand" "=d")
6039 (abs:DI (sign_extend:DI (match_dup 1))))]
6040 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6042 [(set_attr "op_type" "RRE")])
6044 (define_insn "*absdi2_sign"
6045 [(set (match_operand:DI 0 "register_operand" "=d")
6046 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6047 (clobber (reg:CC CC_REGNUM))]
6050 [(set_attr "op_type" "RRE")])
6053 (define_insn "*abs<mode>2_cc"
6054 [(set (reg CC_REGNUM)
6055 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6057 (set (match_operand:GPR 0 "register_operand" "=d")
6058 (abs:GPR (match_dup 1)))]
6059 "s390_match_ccmode (insn, CCAmode)"
6061 [(set_attr "op_type" "RR<E>")])
6064 (define_insn "*abs<mode>2_cconly"
6065 [(set (reg CC_REGNUM)
6066 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6068 (clobber (match_scratch:GPR 0 "=d"))]
6069 "s390_match_ccmode (insn, CCAmode)"
6071 [(set_attr "op_type" "RR<E>")])
6074 (define_insn "abs<mode>2"
6075 [(set (match_operand:GPR 0 "register_operand" "=d")
6076 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6077 (clobber (reg:CC CC_REGNUM))]
6080 [(set_attr "op_type" "RR<E>")])
6083 ; abs(df|sf)2 instruction pattern(s).
6086 (define_expand "abs<mode>2"
6088 [(set (match_operand:BFP 0 "register_operand" "=f")
6089 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6090 (clobber (reg:CC CC_REGNUM))])]
6094 ; lpxbr, lpdbr, lpebr
6095 (define_insn "*abs<mode>2_cc"
6096 [(set (reg CC_REGNUM)
6097 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6098 (match_operand:BFP 2 "const0_operand" "")))
6099 (set (match_operand:BFP 0 "register_operand" "=f")
6100 (abs:BFP (match_dup 1)))]
6101 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6103 [(set_attr "op_type" "RRE")
6104 (set_attr "type" "fsimp<mode>")])
6106 ; lpxbr, lpdbr, lpebr
6107 (define_insn "*abs<mode>2_cconly"
6108 [(set (reg CC_REGNUM)
6109 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6110 (match_operand:BFP 2 "const0_operand" "")))
6111 (clobber (match_scratch:BFP 0 "=f"))]
6112 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6114 [(set_attr "op_type" "RRE")
6115 (set_attr "type" "fsimp<mode>")])
6118 (define_insn "*abs<mode>2_nocc"
6119 [(set (match_operand:FP 0 "register_operand" "=f")
6120 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6121 "TARGET_HARD_FLOAT && TARGET_DFP"
6123 [(set_attr "op_type" "RRE")
6124 (set_attr "type" "fsimp<bfp>")])
6126 ; lpxbr, lpdbr, lpebr
6127 (define_insn "*abs<mode>2"
6128 [(set (match_operand:BFP 0 "register_operand" "=f")
6129 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6130 (clobber (reg:CC CC_REGNUM))]
6133 [(set_attr "op_type" "RRE")
6134 (set_attr "type" "fsimp<mode>")])
6138 ;;- Negated absolute value instructions
6145 (define_insn "*negabsdi2_sign_cc"
6146 [(set (reg CC_REGNUM)
6147 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6148 (match_operand:SI 1 "register_operand" "d") 0)
6149 (const_int 32)) (const_int 32))))
6151 (set (match_operand:DI 0 "register_operand" "=d")
6152 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6153 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6155 [(set_attr "op_type" "RRE")])
6157 (define_insn "*negabsdi2_sign"
6158 [(set (match_operand:DI 0 "register_operand" "=d")
6159 (neg:DI (abs:DI (sign_extend:DI
6160 (match_operand:SI 1 "register_operand" "d")))))
6161 (clobber (reg:CC CC_REGNUM))]
6164 [(set_attr "op_type" "RRE")])
6167 (define_insn "*negabs<mode>2_cc"
6168 [(set (reg CC_REGNUM)
6169 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6171 (set (match_operand:GPR 0 "register_operand" "=d")
6172 (neg:GPR (abs:GPR (match_dup 1))))]
6173 "s390_match_ccmode (insn, CCAmode)"
6175 [(set_attr "op_type" "RR<E>")])
6178 (define_insn "*negabs<mode>2_cconly"
6179 [(set (reg CC_REGNUM)
6180 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6182 (clobber (match_scratch:GPR 0 "=d"))]
6183 "s390_match_ccmode (insn, CCAmode)"
6185 [(set_attr "op_type" "RR<E>")])
6188 (define_insn "*negabs<mode>2"
6189 [(set (match_operand:GPR 0 "register_operand" "=d")
6190 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6191 (clobber (reg:CC CC_REGNUM))]
6194 [(set_attr "op_type" "RR<E>")])
6200 ; lnxbr, lndbr, lnebr
6201 (define_insn "*negabs<mode>2_cc"
6202 [(set (reg CC_REGNUM)
6203 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6204 (match_operand:BFP 2 "const0_operand" "")))
6205 (set (match_operand:BFP 0 "register_operand" "=f")
6206 (neg:BFP (abs:BFP (match_dup 1))))]
6207 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6209 [(set_attr "op_type" "RRE")
6210 (set_attr "type" "fsimp<mode>")])
6212 ; lnxbr, lndbr, lnebr
6213 (define_insn "*negabs<mode>2_cconly"
6214 [(set (reg CC_REGNUM)
6215 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6216 (match_operand:BFP 2 "const0_operand" "")))
6217 (clobber (match_scratch:BFP 0 "=f"))]
6218 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6220 [(set_attr "op_type" "RRE")
6221 (set_attr "type" "fsimp<mode>")])
6224 (define_insn "*negabs<mode>2_nocc"
6225 [(set (match_operand:FP 0 "register_operand" "=f")
6226 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
6227 "TARGET_HARD_FLOAT && TARGET_DFP"
6229 [(set_attr "op_type" "RRE")
6230 (set_attr "type" "fsimp<bfp>")])
6232 ; lnxbr, lndbr, lnebr
6233 (define_insn "*negabs<mode>2"
6234 [(set (match_operand:BFP 0 "register_operand" "=f")
6235 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
6236 (clobber (reg:CC CC_REGNUM))]
6239 [(set_attr "op_type" "RRE")
6240 (set_attr "type" "fsimp<mode>")])
6243 ;;- Copy sign instructions
6247 (define_insn "copysign<mode>3"
6248 [(set (match_operand:FP 0 "register_operand" "=f")
6249 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
6250 (match_operand:FP 2 "register_operand" "f")]
6252 "TARGET_HARD_FLOAT && TARGET_DFP"
6254 [(set_attr "op_type" "RRF")
6255 (set_attr "type" "fsimp<bfp>")])
6258 ;;- Square root instructions.
6262 ; sqrt(df|sf)2 instruction pattern(s).
6265 ; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb
6266 (define_insn "sqrt<mode>2"
6267 [(set (match_operand:BFP 0 "register_operand" "=f,f")
6268 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
6273 [(set_attr "op_type" "RRE,RXE")
6274 (set_attr "type" "fsqrt<mode>")])
6278 ;;- One complement instructions.
6282 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
6285 (define_expand "one_cmpl<mode>2"
6287 [(set (match_operand:INT 0 "register_operand" "")
6288 (xor:INT (match_operand:INT 1 "register_operand" "")
6290 (clobber (reg:CC CC_REGNUM))])]
6296 ;; Find leftmost bit instructions.
6299 (define_expand "clzdi2"
6300 [(set (match_operand:DI 0 "register_operand" "=d")
6301 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
6302 "TARGET_EXTIMM && TARGET_64BIT"
6304 rtx insn, clz_equal;
6305 rtx wide_reg = gen_reg_rtx (TImode);
6306 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
6308 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
6310 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
6312 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
6313 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
6318 (define_insn "clztidi2"
6319 [(set (match_operand:TI 0 "register_operand" "=d")
6323 (xor:DI (match_operand:DI 1 "register_operand" "d")
6324 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
6325 (subreg:SI (clz:DI (match_dup 1)) 4))))
6328 (zero_extend:TI (clz:DI (match_dup 1)))))
6329 (clobber (reg:CC CC_REGNUM))]
6330 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
6331 == (unsigned HOST_WIDE_INT) 1 << 63
6332 && TARGET_EXTIMM && TARGET_64BIT"
6334 [(set_attr "op_type" "RRE")])
6338 ;;- Rotate instructions.
6342 ; rotl(di|si)3 instruction pattern(s).
6346 (define_insn "rotl<mode>3"
6347 [(set (match_operand:GPR 0 "register_operand" "=d")
6348 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6349 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6352 [(set_attr "op_type" "RSE")
6353 (set_attr "atype" "reg")])
6356 (define_insn "*rotl<mode>3_and"
6357 [(set (match_operand:GPR 0 "register_operand" "=d")
6358 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6359 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6360 (match_operand:SI 3 "const_int_operand" "n"))))]
6361 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
6363 [(set_attr "op_type" "RSE")
6364 (set_attr "atype" "reg")])
6368 ;;- Shift instructions.
6372 ; (ashl|lshr)(di|si)3 instruction pattern(s).
6375 (define_expand "<shift><mode>3"
6376 [(set (match_operand:DSI 0 "register_operand" "")
6377 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
6378 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
6383 (define_insn "*<shift>di3_31"
6384 [(set (match_operand:DI 0 "register_operand" "=d")
6385 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6386 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6389 [(set_attr "op_type" "RS")
6390 (set_attr "atype" "reg")])
6392 ; sll, srl, sllg, srlg
6393 (define_insn "*<shift><mode>3"
6394 [(set (match_operand:GPR 0 "register_operand" "=d")
6395 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6396 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6398 "s<lr>l<g>\t%0,<1>%Y2"
6399 [(set_attr "op_type" "RS<E>")
6400 (set_attr "atype" "reg")])
6403 (define_insn "*<shift>di3_31_and"
6404 [(set (match_operand:DI 0 "register_operand" "=d")
6405 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6406 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6407 (match_operand:SI 3 "const_int_operand" "n"))))]
6408 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6410 [(set_attr "op_type" "RS")
6411 (set_attr "atype" "reg")])
6413 ; sll, srl, sllg, srlg
6414 (define_insn "*<shift><mode>3_and"
6415 [(set (match_operand:GPR 0 "register_operand" "=d")
6416 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6417 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6418 (match_operand:SI 3 "const_int_operand" "n"))))]
6419 "(INTVAL (operands[3]) & 63) == 63"
6420 "s<lr>l<g>\t%0,<1>%Y2"
6421 [(set_attr "op_type" "RS<E>")
6422 (set_attr "atype" "reg")])
6425 ; ashr(di|si)3 instruction pattern(s).
6428 (define_expand "ashr<mode>3"
6430 [(set (match_operand:DSI 0 "register_operand" "")
6431 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
6432 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
6433 (clobber (reg:CC CC_REGNUM))])]
6437 (define_insn "*ashrdi3_cc_31"
6438 [(set (reg CC_REGNUM)
6439 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6440 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6442 (set (match_operand:DI 0 "register_operand" "=d")
6443 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6444 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6446 [(set_attr "op_type" "RS")
6447 (set_attr "atype" "reg")])
6449 (define_insn "*ashrdi3_cconly_31"
6450 [(set (reg CC_REGNUM)
6451 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6452 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6454 (clobber (match_scratch:DI 0 "=d"))]
6455 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6457 [(set_attr "op_type" "RS")
6458 (set_attr "atype" "reg")])
6460 (define_insn "*ashrdi3_31"
6461 [(set (match_operand:DI 0 "register_operand" "=d")
6462 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6463 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6464 (clobber (reg:CC CC_REGNUM))]
6467 [(set_attr "op_type" "RS")
6468 (set_attr "atype" "reg")])
6471 (define_insn "*ashr<mode>3_cc"
6472 [(set (reg CC_REGNUM)
6473 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6474 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6476 (set (match_operand:GPR 0 "register_operand" "=d")
6477 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
6478 "s390_match_ccmode(insn, CCSmode)"
6480 [(set_attr "op_type" "RS<E>")
6481 (set_attr "atype" "reg")])
6484 (define_insn "*ashr<mode>3_cconly"
6485 [(set (reg CC_REGNUM)
6486 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6487 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6489 (clobber (match_scratch:GPR 0 "=d"))]
6490 "s390_match_ccmode(insn, CCSmode)"
6492 [(set_attr "op_type" "RS<E>")
6493 (set_attr "atype" "reg")])
6496 (define_insn "*ashr<mode>3"
6497 [(set (match_operand:GPR 0 "register_operand" "=d")
6498 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6499 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6500 (clobber (reg:CC CC_REGNUM))]
6503 [(set_attr "op_type" "RS<E>")
6504 (set_attr "atype" "reg")])
6507 ; shift pattern with implicit ANDs
6509 (define_insn "*ashrdi3_cc_31_and"
6510 [(set (reg CC_REGNUM)
6511 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6512 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6513 (match_operand:SI 3 "const_int_operand" "n")))
6515 (set (match_operand:DI 0 "register_operand" "=d")
6516 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6517 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6518 && (INTVAL (operands[3]) & 63) == 63"
6520 [(set_attr "op_type" "RS")
6521 (set_attr "atype" "reg")])
6523 (define_insn "*ashrdi3_cconly_31_and"
6524 [(set (reg CC_REGNUM)
6525 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6526 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6527 (match_operand:SI 3 "const_int_operand" "n")))
6529 (clobber (match_scratch:DI 0 "=d"))]
6530 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6531 && (INTVAL (operands[3]) & 63) == 63"
6533 [(set_attr "op_type" "RS")
6534 (set_attr "atype" "reg")])
6536 (define_insn "*ashrdi3_31_and"
6537 [(set (match_operand:DI 0 "register_operand" "=d")
6538 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6539 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6540 (match_operand:SI 3 "const_int_operand" "n"))))
6541 (clobber (reg:CC CC_REGNUM))]
6542 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6544 [(set_attr "op_type" "RS")
6545 (set_attr "atype" "reg")])
6548 (define_insn "*ashr<mode>3_cc_and"
6549 [(set (reg CC_REGNUM)
6550 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6551 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6552 (match_operand:SI 3 "const_int_operand" "n")))
6554 (set (match_operand:GPR 0 "register_operand" "=d")
6555 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6556 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6558 [(set_attr "op_type" "RS<E>")
6559 (set_attr "atype" "reg")])
6562 (define_insn "*ashr<mode>3_cconly_and"
6563 [(set (reg CC_REGNUM)
6564 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6565 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6566 (match_operand:SI 3 "const_int_operand" "n")))
6568 (clobber (match_scratch:GPR 0 "=d"))]
6569 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6571 [(set_attr "op_type" "RS<E>")
6572 (set_attr "atype" "reg")])
6575 (define_insn "*ashr<mode>3_and"
6576 [(set (match_operand:GPR 0 "register_operand" "=d")
6577 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6578 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6579 (match_operand:SI 3 "const_int_operand" "n"))))
6580 (clobber (reg:CC CC_REGNUM))]
6581 "(INTVAL (operands[3]) & 63) == 63"
6583 [(set_attr "op_type" "RS<E>")
6584 (set_attr "atype" "reg")])
6588 ;; Branch instruction patterns.
6591 (define_expand "b<code>"
6593 (if_then_else (COMPARE (match_operand 0 "" "")
6598 "s390_emit_jump (operands[0],
6599 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6603 ;;- Conditional jump instructions.
6606 (define_insn "*cjump_64"
6609 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6610 (label_ref (match_operand 0 "" ""))
6614 if (get_attr_length (insn) == 4)
6617 return "jg%C1\t%l0";
6619 [(set_attr "op_type" "RI")
6620 (set_attr "type" "branch")
6621 (set (attr "length")
6622 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6623 (const_int 4) (const_int 6)))])
6625 (define_insn "*cjump_31"
6628 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6629 (label_ref (match_operand 0 "" ""))
6633 gcc_assert (get_attr_length (insn) == 4);
6636 [(set_attr "op_type" "RI")
6637 (set_attr "type" "branch")
6638 (set (attr "length")
6639 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6640 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6641 (const_int 4) (const_int 6))
6642 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6643 (const_int 4) (const_int 8))))])
6645 (define_insn "*cjump_long"
6648 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6649 (match_operand 0 "address_operand" "U")
6653 if (get_attr_op_type (insn) == OP_TYPE_RR)
6658 [(set (attr "op_type")
6659 (if_then_else (match_operand 0 "register_operand" "")
6660 (const_string "RR") (const_string "RX")))
6661 (set_attr "type" "branch")
6662 (set_attr "atype" "agen")])
6666 ;;- Negated conditional jump instructions.
6669 (define_insn "*icjump_64"
6672 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6674 (label_ref (match_operand 0 "" ""))))]
6677 if (get_attr_length (insn) == 4)
6680 return "jg%D1\t%l0";
6682 [(set_attr "op_type" "RI")
6683 (set_attr "type" "branch")
6684 (set (attr "length")
6685 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6686 (const_int 4) (const_int 6)))])
6688 (define_insn "*icjump_31"
6691 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6693 (label_ref (match_operand 0 "" ""))))]
6696 gcc_assert (get_attr_length (insn) == 4);
6699 [(set_attr "op_type" "RI")
6700 (set_attr "type" "branch")
6701 (set (attr "length")
6702 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6703 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6704 (const_int 4) (const_int 6))
6705 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6706 (const_int 4) (const_int 8))))])
6708 (define_insn "*icjump_long"
6711 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6713 (match_operand 0 "address_operand" "U")))]
6716 if (get_attr_op_type (insn) == OP_TYPE_RR)
6721 [(set (attr "op_type")
6722 (if_then_else (match_operand 0 "register_operand" "")
6723 (const_string "RR") (const_string "RX")))
6724 (set_attr "type" "branch")
6725 (set_attr "atype" "agen")])
6728 ;;- Trap instructions.
6732 [(trap_if (const_int 1) (const_int 0))]
6735 [(set_attr "op_type" "RI")
6736 (set_attr "type" "branch")])
6738 (define_expand "conditional_trap"
6739 [(trap_if (match_operand 0 "comparison_operator" "")
6740 (match_operand 1 "general_operand" ""))]
6743 if (operands[1] != const0_rtx) FAIL;
6744 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6745 s390_compare_op0, s390_compare_op1);
6748 (define_insn "*trap"
6749 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6753 [(set_attr "op_type" "RI")
6754 (set_attr "type" "branch")])
6757 ;;- Loop instructions.
6759 ;; This is all complicated by the fact that since this is a jump insn
6760 ;; we must handle our own output reloads.
6762 (define_expand "doloop_end"
6763 [(use (match_operand 0 "" "")) ; loop pseudo
6764 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6765 (use (match_operand 2 "" "")) ; max iterations
6766 (use (match_operand 3 "" "")) ; loop level
6767 (use (match_operand 4 "" ""))] ; label
6770 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6771 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6772 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6773 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6774 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6775 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6782 (define_insn_and_split "doloop_si64"
6785 (ne (match_operand:SI 1 "register_operand" "d,d,d")
6787 (label_ref (match_operand 0 "" ""))
6789 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
6790 (plus:SI (match_dup 1) (const_int -1)))
6791 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
6792 (clobber (reg:CC CC_REGNUM))]
6795 if (which_alternative != 0)
6797 else if (get_attr_length (insn) == 4)
6798 return "brct\t%1,%l0";
6800 return "ahi\t%1,-1\;jgne\t%l0";
6802 "&& reload_completed
6803 && (! REG_P (operands[2])
6804 || ! rtx_equal_p (operands[1], operands[2]))"
6805 [(set (match_dup 3) (match_dup 1))
6806 (parallel [(set (reg:CCAN CC_REGNUM)
6807 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6809 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6810 (set (match_dup 2) (match_dup 3))
6811 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6812 (label_ref (match_dup 0))
6815 [(set_attr "op_type" "RI")
6816 (set_attr "type" "branch")
6817 (set (attr "length")
6818 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6819 (const_int 4) (const_int 10)))])
6821 (define_insn_and_split "doloop_si31"
6824 (ne (match_operand:SI 1 "register_operand" "d,d,d")
6826 (label_ref (match_operand 0 "" ""))
6828 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
6829 (plus:SI (match_dup 1) (const_int -1)))
6830 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
6831 (clobber (reg:CC CC_REGNUM))]
6834 if (which_alternative != 0)
6836 else if (get_attr_length (insn) == 4)
6837 return "brct\t%1,%l0";
6841 "&& reload_completed
6842 && (! REG_P (operands[2])
6843 || ! rtx_equal_p (operands[1], operands[2]))"
6844 [(set (match_dup 3) (match_dup 1))
6845 (parallel [(set (reg:CCAN CC_REGNUM)
6846 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6848 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6849 (set (match_dup 2) (match_dup 3))
6850 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6851 (label_ref (match_dup 0))
6854 [(set_attr "op_type" "RI")
6855 (set_attr "type" "branch")
6856 (set (attr "length")
6857 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6858 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6859 (const_int 4) (const_int 6))
6860 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6861 (const_int 4) (const_int 8))))])
6863 (define_insn "*doloop_si_long"
6866 (ne (match_operand:SI 1 "register_operand" "d")
6868 (match_operand 0 "address_operand" "U")
6870 (set (match_operand:SI 2 "register_operand" "=1")
6871 (plus:SI (match_dup 1) (const_int -1)))
6872 (clobber (match_scratch:SI 3 "=X"))
6873 (clobber (reg:CC CC_REGNUM))]
6876 if (get_attr_op_type (insn) == OP_TYPE_RR)
6877 return "bctr\t%1,%0";
6879 return "bct\t%1,%a0";
6881 [(set (attr "op_type")
6882 (if_then_else (match_operand 0 "register_operand" "")
6883 (const_string "RR") (const_string "RX")))
6884 (set_attr "type" "branch")
6885 (set_attr "atype" "agen")])
6887 (define_insn_and_split "doloop_di"
6890 (ne (match_operand:DI 1 "register_operand" "d,d,d")
6892 (label_ref (match_operand 0 "" ""))
6894 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
6895 (plus:DI (match_dup 1) (const_int -1)))
6896 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
6897 (clobber (reg:CC CC_REGNUM))]
6900 if (which_alternative != 0)
6902 else if (get_attr_length (insn) == 4)
6903 return "brctg\t%1,%l0";
6905 return "aghi\t%1,-1\;jgne\t%l0";
6907 "&& reload_completed
6908 && (! REG_P (operands[2])
6909 || ! rtx_equal_p (operands[1], operands[2]))"
6910 [(set (match_dup 3) (match_dup 1))
6911 (parallel [(set (reg:CCAN CC_REGNUM)
6912 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6914 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6915 (set (match_dup 2) (match_dup 3))
6916 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6917 (label_ref (match_dup 0))
6920 [(set_attr "op_type" "RI")
6921 (set_attr "type" "branch")
6922 (set (attr "length")
6923 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6924 (const_int 4) (const_int 10)))])
6927 ;;- Unconditional jump instructions.
6931 ; jump instruction pattern(s).
6934 (define_expand "jump"
6935 [(match_operand 0 "" "")]
6937 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6939 (define_insn "*jump64"
6940 [(set (pc) (label_ref (match_operand 0 "" "")))]
6943 if (get_attr_length (insn) == 4)
6948 [(set_attr "op_type" "RI")
6949 (set_attr "type" "branch")
6950 (set (attr "length")
6951 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6952 (const_int 4) (const_int 6)))])
6954 (define_insn "*jump31"
6955 [(set (pc) (label_ref (match_operand 0 "" "")))]
6958 gcc_assert (get_attr_length (insn) == 4);
6961 [(set_attr "op_type" "RI")
6962 (set_attr "type" "branch")
6963 (set (attr "length")
6964 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6965 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6966 (const_int 4) (const_int 6))
6967 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6968 (const_int 4) (const_int 8))))])
6971 ; indirect-jump instruction pattern(s).
6974 (define_insn "indirect_jump"
6975 [(set (pc) (match_operand 0 "address_operand" "U"))]
6978 if (get_attr_op_type (insn) == OP_TYPE_RR)
6983 [(set (attr "op_type")
6984 (if_then_else (match_operand 0 "register_operand" "")
6985 (const_string "RR") (const_string "RX")))
6986 (set_attr "type" "branch")
6987 (set_attr "atype" "agen")])
6990 ; casesi instruction pattern(s).
6993 (define_insn "casesi_jump"
6994 [(set (pc) (match_operand 0 "address_operand" "U"))
6995 (use (label_ref (match_operand 1 "" "")))]
6998 if (get_attr_op_type (insn) == OP_TYPE_RR)
7003 [(set (attr "op_type")
7004 (if_then_else (match_operand 0 "register_operand" "")
7005 (const_string "RR") (const_string "RX")))
7006 (set_attr "type" "branch")
7007 (set_attr "atype" "agen")])
7009 (define_expand "casesi"
7010 [(match_operand:SI 0 "general_operand" "")
7011 (match_operand:SI 1 "general_operand" "")
7012 (match_operand:SI 2 "general_operand" "")
7013 (label_ref (match_operand 3 "" ""))
7014 (label_ref (match_operand 4 "" ""))]
7017 rtx index = gen_reg_rtx (SImode);
7018 rtx base = gen_reg_rtx (Pmode);
7019 rtx target = gen_reg_rtx (Pmode);
7021 emit_move_insn (index, operands[0]);
7022 emit_insn (gen_subsi3 (index, index, operands[1]));
7023 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7026 if (Pmode != SImode)
7027 index = convert_to_mode (Pmode, index, 1);
7028 if (GET_CODE (index) != REG)
7029 index = copy_to_mode_reg (Pmode, index);
7032 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7034 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7036 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7038 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7039 emit_move_insn (target, index);
7042 target = gen_rtx_PLUS (Pmode, base, target);
7043 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7050 ;;- Jump to subroutine.
7055 ; untyped call instruction pattern(s).
7058 ;; Call subroutine returning any type.
7059 (define_expand "untyped_call"
7060 [(parallel [(call (match_operand 0 "" "")
7062 (match_operand 1 "" "")
7063 (match_operand 2 "" "")])]
7068 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7070 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7072 rtx set = XVECEXP (operands[2], 0, i);
7073 emit_move_insn (SET_DEST (set), SET_SRC (set));
7076 /* The optimizer does not know that the call sets the function value
7077 registers we stored in the result block. We avoid problems by
7078 claiming that all hard registers are used and clobbered at this
7080 emit_insn (gen_blockage ());
7085 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7086 ;; all of memory. This blocks insns from being moved across this point.
7088 (define_insn "blockage"
7089 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7092 [(set_attr "type" "none")
7093 (set_attr "length" "0")])
7099 (define_expand "sibcall"
7100 [(call (match_operand 0 "" "")
7101 (match_operand 1 "" ""))]
7104 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7108 (define_insn "*sibcall_br"
7109 [(call (mem:QI (reg SIBCALL_REGNUM))
7110 (match_operand 0 "const_int_operand" "n"))]
7111 "SIBLING_CALL_P (insn)
7112 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7114 [(set_attr "op_type" "RR")
7115 (set_attr "type" "branch")
7116 (set_attr "atype" "agen")])
7118 (define_insn "*sibcall_brc"
7119 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7120 (match_operand 1 "const_int_operand" "n"))]
7121 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7123 [(set_attr "op_type" "RI")
7124 (set_attr "type" "branch")])
7126 (define_insn "*sibcall_brcl"
7127 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7128 (match_operand 1 "const_int_operand" "n"))]
7129 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7131 [(set_attr "op_type" "RIL")
7132 (set_attr "type" "branch")])
7135 ; sibcall_value patterns
7138 (define_expand "sibcall_value"
7139 [(set (match_operand 0 "" "")
7140 (call (match_operand 1 "" "")
7141 (match_operand 2 "" "")))]
7144 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7148 (define_insn "*sibcall_value_br"
7149 [(set (match_operand 0 "" "")
7150 (call (mem:QI (reg SIBCALL_REGNUM))
7151 (match_operand 1 "const_int_operand" "n")))]
7152 "SIBLING_CALL_P (insn)
7153 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7155 [(set_attr "op_type" "RR")
7156 (set_attr "type" "branch")
7157 (set_attr "atype" "agen")])
7159 (define_insn "*sibcall_value_brc"
7160 [(set (match_operand 0 "" "")
7161 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7162 (match_operand 2 "const_int_operand" "n")))]
7163 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7165 [(set_attr "op_type" "RI")
7166 (set_attr "type" "branch")])
7168 (define_insn "*sibcall_value_brcl"
7169 [(set (match_operand 0 "" "")
7170 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7171 (match_operand 2 "const_int_operand" "n")))]
7172 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7174 [(set_attr "op_type" "RIL")
7175 (set_attr "type" "branch")])
7179 ; call instruction pattern(s).
7182 (define_expand "call"
7183 [(call (match_operand 0 "" "")
7184 (match_operand 1 "" ""))
7185 (use (match_operand 2 "" ""))]
7188 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7189 gen_rtx_REG (Pmode, RETURN_REGNUM));
7193 (define_insn "*bras"
7194 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7195 (match_operand 1 "const_int_operand" "n"))
7196 (clobber (match_operand 2 "register_operand" "=r"))]
7197 "!SIBLING_CALL_P (insn)
7198 && TARGET_SMALL_EXEC
7199 && GET_MODE (operands[2]) == Pmode"
7201 [(set_attr "op_type" "RI")
7202 (set_attr "type" "jsr")])
7204 (define_insn "*brasl"
7205 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7206 (match_operand 1 "const_int_operand" "n"))
7207 (clobber (match_operand 2 "register_operand" "=r"))]
7208 "!SIBLING_CALL_P (insn)
7210 && GET_MODE (operands[2]) == Pmode"
7212 [(set_attr "op_type" "RIL")
7213 (set_attr "type" "jsr")])
7215 (define_insn "*basr"
7216 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7217 (match_operand 1 "const_int_operand" "n"))
7218 (clobber (match_operand 2 "register_operand" "=r"))]
7219 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7221 if (get_attr_op_type (insn) == OP_TYPE_RR)
7222 return "basr\t%2,%0";
7224 return "bas\t%2,%a0";
7226 [(set (attr "op_type")
7227 (if_then_else (match_operand 0 "register_operand" "")
7228 (const_string "RR") (const_string "RX")))
7229 (set_attr "type" "jsr")
7230 (set_attr "atype" "agen")])
7233 ; call_value instruction pattern(s).
7236 (define_expand "call_value"
7237 [(set (match_operand 0 "" "")
7238 (call (match_operand 1 "" "")
7239 (match_operand 2 "" "")))
7240 (use (match_operand 3 "" ""))]
7243 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7244 gen_rtx_REG (Pmode, RETURN_REGNUM));
7248 (define_insn "*bras_r"
7249 [(set (match_operand 0 "" "")
7250 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7251 (match_operand:SI 2 "const_int_operand" "n")))
7252 (clobber (match_operand 3 "register_operand" "=r"))]
7253 "!SIBLING_CALL_P (insn)
7254 && TARGET_SMALL_EXEC
7255 && GET_MODE (operands[3]) == Pmode"
7257 [(set_attr "op_type" "RI")
7258 (set_attr "type" "jsr")])
7260 (define_insn "*brasl_r"
7261 [(set (match_operand 0 "" "")
7262 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7263 (match_operand 2 "const_int_operand" "n")))
7264 (clobber (match_operand 3 "register_operand" "=r"))]
7265 "!SIBLING_CALL_P (insn)
7267 && GET_MODE (operands[3]) == Pmode"
7269 [(set_attr "op_type" "RIL")
7270 (set_attr "type" "jsr")])
7272 (define_insn "*basr_r"
7273 [(set (match_operand 0 "" "")
7274 (call (mem:QI (match_operand 1 "address_operand" "U"))
7275 (match_operand 2 "const_int_operand" "n")))
7276 (clobber (match_operand 3 "register_operand" "=r"))]
7277 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7279 if (get_attr_op_type (insn) == OP_TYPE_RR)
7280 return "basr\t%3,%1";
7282 return "bas\t%3,%a1";
7284 [(set (attr "op_type")
7285 (if_then_else (match_operand 1 "register_operand" "")
7286 (const_string "RR") (const_string "RX")))
7287 (set_attr "type" "jsr")
7288 (set_attr "atype" "agen")])
7291 ;;- Thread-local storage support.
7294 (define_expand "get_tp_64"
7295 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
7299 (define_expand "get_tp_31"
7300 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
7304 (define_expand "set_tp_64"
7305 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
7306 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
7310 (define_expand "set_tp_31"
7311 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
7312 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
7316 (define_insn "*set_tp"
7317 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
7320 [(set_attr "type" "none")
7321 (set_attr "length" "0")])
7323 (define_insn "*tls_load_64"
7324 [(set (match_operand:DI 0 "register_operand" "=d")
7325 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7326 (match_operand:DI 2 "" "")]
7330 [(set_attr "op_type" "RXE")])
7332 (define_insn "*tls_load_31"
7333 [(set (match_operand:SI 0 "register_operand" "=d,d")
7334 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7335 (match_operand:SI 2 "" "")]
7341 [(set_attr "op_type" "RX,RXY")])
7343 (define_insn "*bras_tls"
7344 [(set (match_operand 0 "" "")
7345 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7346 (match_operand 2 "const_int_operand" "n")))
7347 (clobber (match_operand 3 "register_operand" "=r"))
7348 (use (match_operand 4 "" ""))]
7349 "!SIBLING_CALL_P (insn)
7350 && TARGET_SMALL_EXEC
7351 && GET_MODE (operands[3]) == Pmode"
7353 [(set_attr "op_type" "RI")
7354 (set_attr "type" "jsr")])
7356 (define_insn "*brasl_tls"
7357 [(set (match_operand 0 "" "")
7358 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7359 (match_operand 2 "const_int_operand" "n")))
7360 (clobber (match_operand 3 "register_operand" "=r"))
7361 (use (match_operand 4 "" ""))]
7362 "!SIBLING_CALL_P (insn)
7364 && GET_MODE (operands[3]) == Pmode"
7366 [(set_attr "op_type" "RIL")
7367 (set_attr "type" "jsr")])
7369 (define_insn "*basr_tls"
7370 [(set (match_operand 0 "" "")
7371 (call (mem:QI (match_operand 1 "address_operand" "U"))
7372 (match_operand 2 "const_int_operand" "n")))
7373 (clobber (match_operand 3 "register_operand" "=r"))
7374 (use (match_operand 4 "" ""))]
7375 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7377 if (get_attr_op_type (insn) == OP_TYPE_RR)
7378 return "basr\t%3,%1%J4";
7380 return "bas\t%3,%a1%J4";
7382 [(set (attr "op_type")
7383 (if_then_else (match_operand 1 "register_operand" "")
7384 (const_string "RR") (const_string "RX")))
7385 (set_attr "type" "jsr")
7386 (set_attr "atype" "agen")])
7389 ;;- Atomic operations
7393 ; memory barrier pattern.
7396 (define_expand "memory_barrier"
7397 [(set (mem:BLK (match_dup 0))
7398 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7401 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7402 MEM_VOLATILE_P (operands[0]) = 1;
7405 (define_insn "*memory_barrier"
7406 [(set (match_operand:BLK 0 "" "")
7407 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7410 [(set_attr "op_type" "RR")])
7413 ; compare and swap patterns.
7416 (define_expand "sync_compare_and_swap<mode>"
7418 [(set (match_operand:TDSI 0 "register_operand" "")
7419 (match_operand:TDSI 1 "memory_operand" ""))
7421 (unspec_volatile:TDSI
7423 (match_operand:TDSI 2 "register_operand" "")
7424 (match_operand:TDSI 3 "register_operand" "")]
7426 (set (reg:CCZ1 CC_REGNUM)
7427 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7430 (define_expand "sync_compare_and_swap<mode>"
7432 [(set (match_operand:HQI 0 "register_operand" "")
7433 (match_operand:HQI 1 "memory_operand" ""))
7435 (unspec_volatile:HQI
7437 (match_operand:HQI 2 "general_operand" "")
7438 (match_operand:HQI 3 "general_operand" "")]
7440 (set (reg:CCZ1 CC_REGNUM)
7441 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7443 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
7444 operands[2], operands[3]); DONE;")
7446 (define_expand "sync_compare_and_swap_cc<mode>"
7448 [(set (match_operand:TDSI 0 "register_operand" "")
7449 (match_operand:TDSI 1 "memory_operand" ""))
7451 (unspec_volatile:TDSI
7453 (match_operand:TDSI 2 "register_operand" "")
7454 (match_operand:TDSI 3 "register_operand" "")]
7457 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7460 /* Emulate compare. */
7461 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7462 s390_compare_op0 = operands[1];
7463 s390_compare_op1 = operands[2];
7464 s390_compare_emitted = operands[4];
7468 (define_insn "*sync_compare_and_swap<mode>"
7469 [(set (match_operand:DP 0 "register_operand" "=r")
7470 (match_operand:DP 1 "memory_operand" "+Q"))
7474 (match_operand:DP 2 "register_operand" "0")
7475 (match_operand:DP 3 "register_operand" "r")]
7477 (set (reg:CCZ1 CC_REGNUM)
7478 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7480 "cds<tg>\t%0,%3,%S1"
7481 [(set_attr "op_type" "RS<TE>")
7482 (set_attr "type" "sem")])
7485 (define_insn "*sync_compare_and_swap<mode>"
7486 [(set (match_operand:GPR 0 "register_operand" "=r")
7487 (match_operand:GPR 1 "memory_operand" "+Q"))
7489 (unspec_volatile:GPR
7491 (match_operand:GPR 2 "register_operand" "0")
7492 (match_operand:GPR 3 "register_operand" "r")]
7494 (set (reg:CCZ1 CC_REGNUM)
7495 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7498 [(set_attr "op_type" "RS<E>")
7499 (set_attr "type" "sem")])
7503 ; Other atomic instruction patterns.
7506 (define_expand "sync_lock_test_and_set<mode>"
7507 [(match_operand:HQI 0 "register_operand")
7508 (match_operand:HQI 1 "memory_operand")
7509 (match_operand:HQI 2 "general_operand")]
7511 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
7512 operands[2], false); DONE;")
7514 (define_expand "sync_<atomic><mode>"
7515 [(set (match_operand:HQI 0 "memory_operand")
7516 (ATOMIC:HQI (match_dup 0)
7517 (match_operand:HQI 1 "general_operand")))]
7519 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
7520 operands[1], false); DONE;")
7522 (define_expand "sync_old_<atomic><mode>"
7523 [(set (match_operand:HQI 0 "register_operand")
7524 (match_operand:HQI 1 "memory_operand"))
7526 (ATOMIC:HQI (match_dup 1)
7527 (match_operand:HQI 2 "general_operand")))]
7529 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7530 operands[2], false); DONE;")
7532 (define_expand "sync_new_<atomic><mode>"
7533 [(set (match_operand:HQI 0 "register_operand")
7534 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
7535 (match_operand:HQI 2 "general_operand")))
7536 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
7538 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7539 operands[2], true); DONE;")
7542 ;;- Miscellaneous instructions.
7546 ; allocate stack instruction pattern(s).
7549 (define_expand "allocate_stack"
7550 [(match_operand 0 "general_operand" "")
7551 (match_operand 1 "general_operand" "")]
7554 rtx temp = gen_reg_rtx (Pmode);
7556 emit_move_insn (temp, s390_back_chain_rtx ());
7557 anti_adjust_stack (operands[1]);
7558 emit_move_insn (s390_back_chain_rtx (), temp);
7560 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7566 ; setjmp instruction pattern.
7569 (define_expand "builtin_setjmp_receiver"
7570 [(match_operand 0 "" "")]
7573 emit_insn (s390_load_got ());
7574 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7578 ;; These patterns say how to save and restore the stack pointer. We need not
7579 ;; save the stack pointer at function level since we are careful to
7580 ;; preserve the backchain. At block level, we have to restore the backchain
7581 ;; when we restore the stack pointer.
7583 ;; For nonlocal gotos, we must save both the stack pointer and its
7584 ;; backchain and restore both. Note that in the nonlocal case, the
7585 ;; save area is a memory location.
7587 (define_expand "save_stack_function"
7588 [(match_operand 0 "general_operand" "")
7589 (match_operand 1 "general_operand" "")]
7593 (define_expand "restore_stack_function"
7594 [(match_operand 0 "general_operand" "")
7595 (match_operand 1 "general_operand" "")]
7599 (define_expand "restore_stack_block"
7600 [(match_operand 0 "register_operand" "")
7601 (match_operand 1 "register_operand" "")]
7604 rtx temp = gen_reg_rtx (Pmode);
7606 emit_move_insn (temp, s390_back_chain_rtx ());
7607 emit_move_insn (operands[0], operands[1]);
7608 emit_move_insn (s390_back_chain_rtx (), temp);
7613 (define_expand "save_stack_nonlocal"
7614 [(match_operand 0 "memory_operand" "")
7615 (match_operand 1 "register_operand" "")]
7618 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7619 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7621 /* Copy the backchain to the first word, sp to the second and the
7622 literal pool base to the third. */
7624 if (TARGET_BACKCHAIN)
7626 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7627 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7630 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7631 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7636 (define_expand "restore_stack_nonlocal"
7637 [(match_operand 0 "register_operand" "")
7638 (match_operand 1 "memory_operand" "")]
7641 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7642 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7643 rtx temp = NULL_RTX;
7645 /* Restore the backchain from the first word, sp from the second and the
7646 literal pool base from the third. */
7648 if (TARGET_BACKCHAIN)
7649 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7651 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7652 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7655 emit_move_insn (s390_back_chain_rtx (), temp);
7657 emit_insn (gen_rtx_USE (VOIDmode, base));
7661 (define_expand "exception_receiver"
7665 s390_set_has_landing_pad_p (true);
7670 ; nop instruction pattern(s).
7677 [(set_attr "op_type" "RR")])
7681 ; Special literal pool access instruction pattern(s).
7684 (define_insn "*pool_entry"
7685 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7686 UNSPECV_POOL_ENTRY)]
7689 enum machine_mode mode = GET_MODE (PATTERN (insn));
7690 unsigned int align = GET_MODE_BITSIZE (mode);
7691 s390_output_pool_entry (operands[0], mode, align);
7694 [(set (attr "length")
7695 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7697 (define_insn "pool_align"
7698 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7699 UNSPECV_POOL_ALIGN)]
7702 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7704 (define_insn "pool_section_start"
7705 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7708 [(set_attr "length" "0")])
7710 (define_insn "pool_section_end"
7711 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7714 [(set_attr "length" "0")])
7716 (define_insn "main_base_31_small"
7717 [(set (match_operand 0 "register_operand" "=a")
7718 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7719 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7721 [(set_attr "op_type" "RR")
7722 (set_attr "type" "la")])
7724 (define_insn "main_base_31_large"
7725 [(set (match_operand 0 "register_operand" "=a")
7726 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7727 (set (pc) (label_ref (match_operand 2 "" "")))]
7728 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7730 [(set_attr "op_type" "RI")])
7732 (define_insn "main_base_64"
7733 [(set (match_operand 0 "register_operand" "=a")
7734 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7735 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7737 [(set_attr "op_type" "RIL")
7738 (set_attr "type" "larl")])
7740 (define_insn "main_pool"
7741 [(set (match_operand 0 "register_operand" "=a")
7742 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7743 "GET_MODE (operands[0]) == Pmode"
7748 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7749 (const_string "larl") (const_string "la")))])
7751 (define_insn "reload_base_31"
7752 [(set (match_operand 0 "register_operand" "=a")
7753 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7754 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7755 "basr\t%0,0\;la\t%0,%1-.(%0)"
7756 [(set_attr "length" "6")
7757 (set_attr "type" "la")])
7759 (define_insn "reload_base_64"
7760 [(set (match_operand 0 "register_operand" "=a")
7761 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7762 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7764 [(set_attr "op_type" "RIL")
7765 (set_attr "type" "larl")])
7768 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7773 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7776 ;; Insns related to generating the function prologue and epilogue.
7780 (define_expand "prologue"
7781 [(use (const_int 0))]
7783 "s390_emit_prologue (); DONE;")
7785 (define_expand "epilogue"
7786 [(use (const_int 1))]
7788 "s390_emit_epilogue (false); DONE;")
7790 (define_expand "sibcall_epilogue"
7791 [(use (const_int 0))]
7793 "s390_emit_epilogue (true); DONE;")
7795 (define_insn "*return"
7797 (use (match_operand 0 "register_operand" "a"))]
7798 "GET_MODE (operands[0]) == Pmode"
7800 [(set_attr "op_type" "RR")
7801 (set_attr "type" "jsr")
7802 (set_attr "atype" "agen")])
7805 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7806 ;; pointer. This is used for compatibility.
7808 (define_expand "ptr_extend"
7809 [(set (match_operand:DI 0 "register_operand" "=r")
7810 (match_operand:SI 1 "register_operand" "r"))]
7813 emit_insn (gen_anddi3 (operands[0],
7814 gen_lowpart (DImode, operands[1]),
7815 GEN_INT (0x7fffffff)));
7819 ;; Instruction definition to expand eh_return macro to support
7820 ;; swapping in special linkage return addresses.
7822 (define_expand "eh_return"
7823 [(use (match_operand 0 "register_operand" ""))]
7826 s390_emit_tpf_eh_return (operands[0]);
7831 ; Stack Protector Patterns
7834 (define_expand "stack_protect_set"
7835 [(set (match_operand 0 "memory_operand" "")
7836 (match_operand 1 "memory_operand" ""))]
7839 #ifdef TARGET_THREAD_SSP_OFFSET
7841 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7842 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7845 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7847 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7852 (define_insn "stack_protect_set<mode>"
7853 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7854 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7856 "mvc\t%O0(%G0,%R0),%S1"
7857 [(set_attr "op_type" "SS")])
7859 (define_expand "stack_protect_test"
7860 [(set (reg:CC CC_REGNUM)
7861 (compare (match_operand 0 "memory_operand" "")
7862 (match_operand 1 "memory_operand" "")))
7863 (match_operand 2 "" "")]
7866 #ifdef TARGET_THREAD_SSP_OFFSET
7868 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7869 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7871 s390_compare_op0 = operands[0];
7872 s390_compare_op1 = operands[1];
7873 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7876 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7878 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7880 emit_jump_insn (gen_beq (operands[2]));
7885 (define_insn "stack_protect_test<mode>"
7886 [(set (reg:CCZ CC_REGNUM)
7887 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7888 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7890 "clc\t%O0(%G0,%R0),%S1"
7891 [(set_attr "op_type" "SS")])