1 ; Options for the rs6000 port of the compiler
3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
6 ; This file is part of GCC.
8 ; GCC is free software; you can redistribute it and/or modify it under
9 ; the terms of the GNU General Public License as published by the Free
10 ; Software Foundation; either version 3, or (at your option) any later
13 ; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ; License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with GCC; see the file COPYING3. If not see
20 ; <http://www.gnu.org/licenses/>.
23 Target Report RejectNegative Mask(POWER)
24 Use POWER instruction set
27 Target Report RejectNegative
28 Do not use POWER instruction set
31 Target Report Mask(POWER2)
32 Use POWER2 instruction set
35 Target Report RejectNegative Mask(POWERPC)
36 Use PowerPC instruction set
39 Target Report RejectNegative
40 Do not use PowerPC instruction set
43 Target Report Mask(POWERPC64)
44 Use PowerPC-64 instruction set
47 Target Report Mask(PPC_GPOPT)
48 Use PowerPC General Purpose group optional instructions
51 Target Report Mask(PPC_GFXOPT)
52 Use PowerPC Graphics group optional instructions
55 Target Report Mask(MFCRF)
56 Use PowerPC V2.01 single field mfcr instruction
59 Target Report Mask(POPCNTB)
60 Use PowerPC V2.02 popcntb instruction
63 Target Report Mask(FPRND)
64 Use PowerPC V2.02 floating point rounding instructions
67 Target Report Mask(CMPB)
68 Use PowerPC V2.05 compare bytes instruction
71 Target Report Mask(MFPGPR)
72 Use extended PowerPC V2.05 move floating point to/from GPR instructions
75 Target Report Mask(ALTIVEC)
76 Use AltiVec instructions
79 Target Report Mask(DFP)
80 Use decimal floating point instructions
83 Target Report Mask(MULHW)
84 Use 4xx half-word multiply instructions
87 Target Report Mask(DLMZB)
88 Use 4xx string-search dlmzb instruction
91 Target Report Mask(MULTIPLE)
92 Generate load/store multiple instructions
95 Target Report Mask(STRING)
96 Generate string instructions for block moves
99 Target Report RejectNegative Mask(NEW_MNEMONICS)
100 Use new mnemonics for PowerPC architecture
103 Target Report RejectNegative InverseMask(NEW_MNEMONICS)
104 Use old mnemonics for PowerPC architecture
107 Target Report RejectNegative Mask(SOFT_FLOAT)
108 Do not use hardware floating point
111 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
112 Use hardware floating point
115 Target Report Mask(POPCNTD)
116 Use PowerPC V2.06 popcntd instruction
119 Target Report Var(TARGET_MASS) Init(0)
120 Use the Mathematical Acceleration Subsystem library high performance math libraries.
123 Target Report Mask(VSX)
124 Use vector/scalar (VSX) instructions
127 Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1)
128 ; If -mvsx, use VSX arithmetic instructions for scalar double (on by default)
131 Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY)
132 ; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default)
135 Target Undocumented Report Var(TARGET_VSX_ALIGN_128)
136 ; If -mvsx, set alignment to 128 bits instead of 32/64
139 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1)
140 ; Allow/disallow the movmisalign in DF/DI vectors
143 Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE)
144 ; Allow/disallow permutation of DF/DI vectors
147 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1)
148 ; Explicitly set/unset whether rs6000_sched_groups is set
151 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1)
152 ; Explicitly set/unset whether rs6000_always_hint is set
154 malign-branch-targets
155 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1)
156 ; Explicitly set/unset whether rs6000_align_branch_targets is set
159 Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1)
160 ; Explicitly control whether we vectorize the builtins or not.
163 Target Report RejectNegative Mask(NO_UPDATE)
164 Do not generate load/store with update instructions
167 Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE)
168 Generate load/store with update instructions
170 mavoid-indexed-addresses
171 Target Report Var(TARGET_AVOID_XFORM) Init(-1)
172 Avoid generation of indexed load/store instructions when possible
175 Target Report Var(TARGET_FUSED_MADD) Init(1)
176 Generate fused multiply/add instructions
179 Target Report Var(tls_markers) Init(1)
180 Mark __tls_get_addr calls with argument info
183 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1)
186 Target Report Var(TARGET_SCHED_PROLOG) VarExists
187 Schedule the start and end of the procedure
190 Target Report RejectNegative Var(aix_struct_return)
191 Return all structures in memory (AIX default)
194 Target Report RejectNegative Var(aix_struct_return,0) VarExists
195 Return small structures in registers (SVR4 default)
198 Target Report Var(TARGET_XL_COMPAT)
199 Conform more closely to IBM XLC semantics
203 Generate software reciprocal divide and square root for better throughput.
206 Target Report RejectNegative Joined
207 Generate software reciprocal divide and square root for better throughput.
210 Target Report Mask(RECIP_PRECISION)
211 Assume that the reciprocal estimate instructions provide more accuracy.
214 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC)
215 Do not place floating point constants in TOC
218 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0)
219 Place floating point constants in TOC
222 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC)
223 Do not place symbol+offset constants in TOC
226 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) VarExists
227 Place symbol+offset constants in TOC
229 ; Output only one TOC entry per module. Normally linking fails if
230 ; there are more than 16K unique variables/constants in an executable. With
231 ; this option, linking fails only if there are more than 16K modules, or
232 ; if there are more than 16K unique variables/constant in a single module.
234 ; This is at the cost of having 2 extra loads and one extra store per
235 ; function, and one less allocable register.
237 Target Report Mask(MINIMAL_TOC)
238 Use only one TOC entry per procedure
242 Put everything in the regular TOC
245 Target Report Var(TARGET_ALTIVEC_VRSAVE)
246 Generate VRSAVE instructions when generating AltiVec code
249 Target RejectNegative Joined
250 -mvrsave=yes/no Deprecated option. Use -mvrsave/-mno-vrsave instead
252 mblock-move-inline-limit=
253 Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger
254 Specify how many bytes should be moved inline before calling out to memcpy/memmove
257 Target Report Mask(ISEL)
258 Generate isel instructions
261 Target RejectNegative Joined
262 -misel=yes/no Deprecated option. Use -misel/-mno-isel instead
266 Generate SPE SIMD instructions on E500
269 Target Var(rs6000_paired_float)
270 Generate PPC750CL paired-single instructions
273 Target RejectNegative Joined
274 -mspe=yes/no Deprecated option. Use -mspe/-mno-spe instead
277 Target RejectNegative Joined
278 -mdebug= Enable debug output
281 Target RejectNegative Joined
282 -mabi= Specify ABI to use
285 Target RejectNegative Joined
286 -mcpu= Use features of and schedule code for given CPU
289 Target RejectNegative Joined
290 -mtune= Schedule code for given CPU
293 Target RejectNegative Joined
294 -mtraceback= Select full, part, or no traceback table
297 Target Report Var(rs6000_default_long_calls)
298 Avoid all range limits on call instructions
301 Target Report Var(rs6000_gen_cell_microcode) Init(-1)
302 Generate Cell microcode
305 Target Var(rs6000_warn_cell_microcode) Init(0) Warning
306 Warn when a Cell microcoded instruction is emitted
309 Target Var(rs6000_warn_altivec_long) Init(1)
310 Warn about deprecated 'vector long ...' AltiVec type usage
313 Target RejectNegative Joined
314 -mfloat-gprs= Select GPR floating point method
317 Target RejectNegative Joined UInteger
318 -mlong-double-<n> Specify size of long double (64 or 128 bits)
321 Target RejectNegative Joined
322 Determine which dependences between insns are considered costly
325 Target RejectNegative Joined
326 Specify which post scheduling nop insertion scheme to apply
329 Target RejectNegative Joined
330 Specify alignment of structure fields default/natural
332 mprioritize-restricted-insns=
333 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority)
334 Specify scheduling priority for dispatch slot restricted insns
337 Target RejectNegative Var(rs6000_single_float)
338 Single-precision floating point unit
341 Target RejectNegative Var(rs6000_double_float)
342 Double-precision floating point unit
345 Target RejectNegative Var(rs6000_simple_fpu)
346 Floating point unit does not support divide & sqrt
349 Target RejectNegative Joined
350 -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu)
353 Target Var(rs6000_xilinx_fpu)