1 ;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;; Define an insn type attribute. This is used in function unit delay
25 (define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare,mtlr,branch"
26 (const_string "integer"))
29 (define_attr "length" ""
30 (if_then_else (eq_attr "type" "branch")
31 (if_then_else (and (ge (minus (pc) (match_dup 0))
33 (lt (minus (pc) (match_dup 0))
39 ;; Memory delivers its result in two cycles.
40 (define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0)
42 ;; We consider floating-point insns to deliver their result in two cycles
43 ;; to try to intersperse integer and FP operations.
44 (define_function_unit "fp" 1 0 (eq_attr "type" "fp,fpcompare") 2 0)
46 ;; Most integer comparisons are ready in four cycles (a stall of three).
47 (define_function_unit "compare" 1 0 (eq_attr "type" "compare") 4 0)
49 ;; Some integer comparisons aren't ready for five cycles (a stall of four).
50 (define_function_unit "compare" 1 0 (eq_attr "type" "delayed_compare") 5 0)
52 ;; Floating-point comparisons take eight cycles.
53 (define_function_unit "compare" 1 0 (eq_attr "type" "fpcompare") 8 0)
55 ;; Branches on LR cannot be done until five cycles after LR is set.
56 (define_function_unit "branch" 1 0 (eq_attr "type" "mtlr") 5 0)
58 ;; Start with fixed-point load and store insns. Here we put only the more
59 ;; complex forms. Basic data transfer is done later.
61 (define_expand "zero_extendqisi2"
62 [(set (match_operand:SI 0 "gpc_reg_operand" "")
63 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
68 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
69 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
73 rlinm %0,%1,0,0x000000FF"
74 [(set_attr "type" "load,*")])
77 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
78 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
80 (clobber (match_scratch:SI 2 "=r"))]
83 [(set_attr "type" "compare")])
86 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
87 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
89 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
90 (zero_extend:SI (match_dup 1)))]
93 [(set_attr "type" "compare")])
95 (define_expand "zero_extendqihi2"
96 [(set (match_operand:HI 0 "gpc_reg_operand" "")
97 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
102 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
103 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
107 rlinm %0,%1,0,0x000000FF"
108 [(set_attr "type" "load,*")])
110 (define_expand "zero_extendhisi2"
111 [(set (match_operand:SI 0 "gpc_reg_operand" "")
112 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
117 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
118 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
122 rlinm %0,%1,0,0x0000FFFF"
123 [(set_attr "type" "load,*")])
126 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
127 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
129 (clobber (match_scratch:SI 2 "=r"))]
131 "andil. %2,%1,0xFFFF"
132 [(set_attr "type" "compare")])
135 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
136 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
138 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
139 (zero_extend:SI (match_dup 1)))]
141 "andil. %0,%1,0xFFFF"
142 [(set_attr "type" "compare")])
144 (define_expand "extendhisi2"
145 [(set (match_operand:SI 0 "gpc_reg_operand" "")
146 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
151 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
152 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
157 [(set_attr "type" "load,*")])
160 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
161 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
163 (clobber (match_scratch:SI 2 "=r"))]
166 [(set_attr "type" "compare")])
169 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
170 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
172 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
173 (sign_extend:SI (match_dup 1)))]
176 [(set_attr "type" "compare")])
178 ;; Fixed-point arithmetic insns.
179 (define_insn "addsi3"
180 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
181 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b")
182 (match_operand:SI 2 "add_operand" "rI,J")))]
189 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
190 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
191 (match_operand:SI 2 "reg_or_short_operand" "rI"))
193 (clobber (match_scratch:SI 3 "=r"))]
196 [(set_attr "type" "compare")])
199 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
200 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
201 (match_operand:SI 2 "reg_or_short_operand" "rI"))
203 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
204 (plus:SI (match_dup 1) (match_dup 2)))]
207 [(set_attr "type" "compare")])
209 ;; Split an add that we can't do in one insn into two insns, each of which
210 ;; does one 16-bit part. This is used by combine. Note that the low-order
211 ;; add should be last in case the result gets used in an address.
214 [(set (match_operand:SI 0 "gpc_reg_operand" "")
215 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
216 (match_operand:SI 2 "non_add_cint_operand" "")))]
218 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
219 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
222 int low = INTVAL (operands[2]) & 0xffff;
223 int high = (unsigned) INTVAL (operands[2]) >> 16;
226 high++, low |= 0xffff0000;
228 operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
229 operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
232 (define_insn "one_cmplsi2"
233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
234 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
239 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
240 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
241 (match_operand:SI 2 "gpc_reg_operand" "r")))]
246 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
247 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
248 (match_operand:SI 2 "gpc_reg_operand" "r"))
250 (clobber (match_scratch:SI 3 "=r"))]
253 [(set_attr "type" "compare")])
256 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
257 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
258 (match_operand:SI 2 "gpc_reg_operand" "r"))
260 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
261 (minus:SI (match_dup 1) (match_dup 2)))]
264 [(set_attr "type" "compare")])
266 (define_expand "subsi3"
267 [(set (match_operand:SI 0 "gpc_reg_operand" "")
268 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
269 (match_operand:SI 2 "reg_or_cint_operand" "")))]
273 if (GET_CODE (operands[2]) == CONST_INT)
275 emit_insn (gen_addsi3 (operands[0], operands[1],
276 negate_rtx (SImode, operands[2])));
281 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
282 ;; instruction and some auxiliary computations. Then we just have a single
283 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
286 (define_expand "sminsi3"
288 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
289 (match_operand:SI 2 "reg_or_short_operand" ""))
291 (minus:SI (match_dup 2) (match_dup 1))))
292 (set (match_operand:SI 0 "gpc_reg_operand" "")
293 (minus:SI (match_dup 2) (match_dup 3)))]
296 { operands[3] = gen_reg_rtx (SImode); }")
299 [(set (match_operand:SI 0 "gpc_reg_operand" "")
300 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
301 (match_operand:SI 2 "reg_or_short_operand" "")))
302 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
305 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
307 (minus:SI (match_dup 2) (match_dup 1))))
308 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
311 (define_expand "smaxsi3"
313 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
314 (match_operand:SI 2 "reg_or_short_operand" ""))
316 (minus:SI (match_dup 2) (match_dup 1))))
317 (set (match_operand:SI 0 "gpc_reg_operand" "")
318 (plus:SI (match_dup 3) (match_dup 1)))]
321 { operands[3] = gen_reg_rtx (SImode); }")
324 [(set (match_operand:SI 0 "gpc_reg_operand" "")
325 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
326 (match_operand:SI 2 "reg_or_short_operand" "")))
327 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
330 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
332 (minus:SI (match_dup 2) (match_dup 1))))
333 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
336 (define_expand "uminsi3"
337 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
338 (const_int -2147483648)))
339 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
340 (const_int -2147483648)))
341 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
343 (minus:SI (match_dup 4) (match_dup 3))))
344 (set (match_operand:SI 0 "gpc_reg_operand" "")
345 (minus:SI (match_dup 2) (match_dup 3)))]
348 { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
350 (define_expand "umaxsi3"
351 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
352 (const_int -2147483648)))
353 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
354 (const_int -2147483648)))
355 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
357 (minus:SI (match_dup 4) (match_dup 3))))
358 (set (match_operand:SI 0 "gpc_reg_operand" "")
359 (plus:SI (match_dup 3) (match_dup 1)))]
362 { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
366 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
367 (match_operand:SI 2 "reg_or_short_operand" "rI"))
369 (minus:SI (match_dup 2) (match_dup 1))))]
374 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
376 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
377 (match_operand:SI 2 "reg_or_short_operand" "rI"))
379 (minus:SI (match_dup 2) (match_dup 1)))
381 (clobber (match_scratch:SI 3 "=r"))]
384 [(set_attr "type" "delayed_compare")])
387 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
389 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
390 (match_operand:SI 2 "reg_or_short_operand" "rI"))
392 (minus:SI (match_dup 2) (match_dup 1)))
394 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
395 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
397 (minus:SI (match_dup 2) (match_dup 1))))]
400 [(set_attr "type" "delayed_compare")])
402 ;; We don't need abs with condition code because such comparisons should
404 (define_insn "abssi2"
405 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
406 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
411 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
412 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
416 (define_insn "negsi2"
417 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
418 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
423 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
424 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
426 (clobber (match_scratch:SI 2 "=r"))]
429 [(set_attr "type" "compare")])
432 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
433 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
435 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
436 (neg:SI (match_dup 1)))]
439 [(set_attr "type" "compare")])
441 (define_insn "ffssi2"
442 [(set (match_operand:SI 0 "register_operand" "=&r")
443 (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
445 "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi %0,%0,32"
446 [(set_attr "length" "16")])
448 (define_insn "mulsi3"
449 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
450 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
451 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
452 (clobber (match_scratch:SI 3 "=q,q"))]
459 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
460 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
461 (match_operand:SI 2 "gpc_reg_operand" "r"))
463 (clobber (match_scratch:SI 3 "=r"))
464 (clobber (match_scratch:SI 4 "=q"))]
467 [(set_attr "type" "delayed_compare")])
470 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
471 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
472 (match_operand:SI 2 "gpc_reg_operand" "r"))
474 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
475 (mult:SI (match_dup 1) (match_dup 2)))
476 (clobber (match_scratch:SI 4 "=q"))]
479 [(set_attr "type" "delayed_compare")])
481 ;; Operand 1 is divided by operand 2; quotient goes to operand
482 ;; 0 and remainder to operand 3.
483 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
485 (define_insn "divmodsi4"
486 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
487 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
488 (match_operand:SI 2 "gpc_reg_operand" "r")))
489 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
490 (mod:SI (match_dup 1) (match_dup 2)))]
494 ;; For powers of two we can do srai/aze for divide and then adjust for
495 ;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used.
496 (define_expand "divsi3"
497 [(set (match_operand:SI 0 "gpc_reg_operand" "")
498 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
499 (match_operand:SI 2 "reg_or_cint_operand" "")))]
503 if (GET_CODE (operands[2]) != CONST_INT
504 || exact_log2 (INTVAL (operands[2])) < 0)
508 (define_expand "modsi3"
510 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
511 (match_operand:SI 2 "reg_or_cint_operand" "")))
512 (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5)))
513 (clobber (scratch:SI))])
514 (set (match_operand:SI 0 "gpc_reg_operand" "")
515 (minus:SI (match_dup 1) (match_dup 4)))]
519 int i = exact_log2 (INTVAL (operands[2]));
521 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
524 operands[3] = gen_reg_rtx (SImode);
525 operands[4] = gen_reg_rtx (SImode);
526 operands[5] = gen_rtx (CONST_INT, VOIDmode, i);
530 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
531 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
532 (match_operand:SI 2 "const_int_operand" "N")))]
533 "exact_log2 (INTVAL (operands[2])) >= 0"
534 "srai %0,%1,%p2\;aze %0,%0"
535 [(set_attr "length" "8")])
538 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
539 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
540 (match_operand:SI 2 "const_int_operand" "N")))
541 (clobber (match_scratch:SI 3 "=r"))]
542 "exact_log2 (INTVAL (operands[2])) >= 0"
543 "srai %3,%1,%p2\;aze. %3,%3"
544 [(set_attr "type" "compare")
545 (set_attr "length" "8")])
548 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
549 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
550 (match_operand:SI 2 "const_int_operand" "N")))
551 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
552 (div:SI (match_dup 1) (match_dup 2)))]
553 "exact_log2 (INTVAL (operands[2])) >= 0"
554 "srai %0,%1,%p2\;aze. %0,%0"
555 [(set_attr "type" "compare")
556 (set_attr "length" "8")])
559 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
562 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
564 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
565 (match_operand:SI 3 "gpc_reg_operand" "r")))
566 (set (match_operand:SI 2 "register_operand" "=*q")
569 (zero_extend:DI (match_dup 1)) (const_int 32))
570 (zero_extend:DI (match_dup 4)))
576 ;; To do unsigned divide we handle the cases of the divisor looking like a
577 ;; negative number. If it is a constant that is less than 2**31, we don't
578 ;; have to worry about the branches. So make a few subroutines here.
580 ;; First comes the normal case.
581 (define_expand "udivmodsi4_normal"
582 [(set (match_dup 4) (const_int 0))
583 (parallel [(set (match_operand:SI 0 "" "")
584 (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
586 (zero_extend:DI (match_operand:SI 1 "" "")))
587 (match_operand:SI 2 "" "")))
588 (set (match_operand:SI 3 "" "")
589 (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
591 (zero_extend:DI (match_dup 1)))
595 { operands[4] = gen_reg_rtx (SImode); }")
597 ;; This handles the branches.
598 (define_expand "udivmodsi4_tests"
599 [(set (match_operand:SI 0 "" "") (const_int 0))
600 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
601 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
602 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
603 (label_ref (match_operand:SI 4 "" "")) (pc)))
604 (set (match_dup 0) (const_int 1))
605 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
606 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
607 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
608 (label_ref (match_dup 4)) (pc)))]
611 { operands[5] = gen_reg_rtx (CCUNSmode);
612 operands[6] = gen_reg_rtx (CCmode);
615 (define_expand "udivmodsi4"
616 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
617 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
618 (match_operand:SI 2 "reg_or_cint_operand" "")))
619 (set (match_operand:SI 3 "gpc_reg_operand" "")
620 (umod:SI (match_dup 1) (match_dup 2)))])]
626 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
628 operands[2] = force_reg (SImode, operands[2]);
629 label = gen_label_rtx ();
630 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
631 operands[3], label));
634 operands[2] = force_reg (SImode, operands[2]);
636 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
644 (define_insn "andsi3"
645 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
646 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
647 (match_operand:SI 2 "and_operand" "?r,L,K,J")))
648 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
652 rlinm %0,%1,0,%m2,%M2
657 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
658 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
659 (match_operand:SI 2 "and_operand" "r,K,J,L"))
661 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
667 rlinm. %3,%1,0,%m2,%M2"
668 [(set_attr "type" "compare,compare,compare,delayed_compare")])
671 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
672 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
673 (match_operand:SI 2 "and_operand" "r,K,J,L"))
675 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
676 (and:SI (match_dup 1) (match_dup 2)))]
682 rlinm. %0,%1,0,%m2,%M2"
683 [(set_attr "type" "compare,compare,compare,delayed_compare")])
685 ;; Take a AND with a constant that cannot be done in a single insn and try to
686 ;; split it into two insns. This does not verify that the insns are valid
687 ;; since this need not be done as combine will do it.
690 [(set (match_operand:SI 0 "gpc_reg_operand" "")
691 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
692 (match_operand:SI 2 "non_and_cint_operand" "")))]
694 [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
695 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
698 int maskval = INTVAL (operands[2]);
699 int i, transitions, last_bit_value;
700 int orig = maskval, first_c = maskval, second_c;
702 /* We know that MASKVAL must have more than 2 bit-transitions. Start at
703 the low-order bit and count for the third transition. When we get there,
704 make a first mask that has everything to the left of that position
705 a one. Then make the second mask to turn off whatever else is needed. */
707 for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
709 if (((maskval >>= 1) & 1) != last_bit_value)
710 last_bit_value ^= 1, transitions++;
714 first_c |= (~0) << i;
719 second_c = orig | ~ first_c;
721 operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
722 operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
725 (define_insn "iorsi3"
726 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
727 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
728 (match_operand:SI 2 "logical_operand" "r,K,J")))]
736 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
737 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
738 (match_operand:SI 2 "gpc_reg_operand" "r"))
740 (clobber (match_scratch:SI 3 "=r"))]
743 [(set_attr "type" "compare")])
746 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
747 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
748 (match_operand:SI 2 "gpc_reg_operand" "r"))
750 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
751 (ior:SI (match_dup 1) (match_dup 2)))]
754 [(set_attr "type" "compare")])
756 ;; Split an IOR that we can't do in one insn into two insns, each of which
757 ;; does one 16-bit part. This is used by combine.
760 [(set (match_operand:SI 0 "gpc_reg_operand" "")
761 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
762 (match_operand:SI 2 "non_logical_cint_operand" "")))]
764 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
765 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
768 operands[3] = gen_rtx (CONST_INT, VOIDmode,
769 INTVAL (operands[2]) & 0xffff0000);
770 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
773 (define_insn "xorsi3"
774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
775 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
776 (match_operand:SI 2 "logical_operand" "r,K,J")))]
784 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
785 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
786 (match_operand:SI 2 "gpc_reg_operand" "r"))
788 (clobber (match_scratch:SI 3 "=r"))]
791 [(set_attr "type" "compare")])
794 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
795 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
796 (match_operand:SI 2 "gpc_reg_operand" "r"))
798 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
799 (xor:SI (match_dup 1) (match_dup 2)))]
802 [(set_attr "type" "compare")])
804 ;; Split an XOR that we can't do in one insn into two insns, each of which
805 ;; does one 16-bit part. This is used by combine.
808 [(set (match_operand:SI 0 "gpc_reg_operand" "")
809 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
810 (match_operand:SI 2 "non_logical_cint_operand" "")))]
812 [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
813 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
816 operands[3] = gen_rtx (CONST_INT, VOIDmode,
817 INTVAL (operands[2]) & 0xffff0000);
818 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
822 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
823 (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
824 (match_operand:SI 2 "gpc_reg_operand" "r"))))]
829 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
830 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
831 (match_operand:SI 2 "gpc_reg_operand" "r")))
833 (clobber (match_scratch:SI 3 "=r"))]
836 [(set_attr "type" "compare")])
839 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
840 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
841 (match_operand:SI 2 "gpc_reg_operand" "r")))
843 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
844 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
847 [(set_attr "type" "compare")])
850 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
851 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
852 (match_operand:SI 2 "gpc_reg_operand" "r")))]
857 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
858 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
859 (match_operand:SI 2 "gpc_reg_operand" "r"))
861 (clobber (match_scratch:SI 3 "=r"))]
864 [(set_attr "type" "compare")])
867 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
868 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
869 (match_operand:SI 2 "gpc_reg_operand" "r"))
871 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
872 (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
875 [(set_attr "type" "compare")])
878 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
879 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
880 (match_operand:SI 2 "gpc_reg_operand" "r")))]
885 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
886 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
887 (match_operand:SI 2 "gpc_reg_operand" "r"))
889 (clobber (match_scratch:SI 3 "=r"))]
892 [(set_attr "type" "compare")])
895 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
896 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
897 (match_operand:SI 2 "gpc_reg_operand" "r"))
899 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
900 (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
903 [(set_attr "type" "compare")])
906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
907 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
908 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
913 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
914 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
915 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
917 (clobber (match_scratch:SI 3 "=r"))]
920 [(set_attr "type" "compare")])
923 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
924 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
925 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
927 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
928 (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
931 [(set_attr "type" "compare")])
934 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
935 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
936 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
941 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
942 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
943 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
945 (clobber (match_scratch:SI 3 "=r"))]
948 [(set_attr "type" "compare")])
951 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
952 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
953 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
955 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
956 (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
959 [(set_attr "type" "compare")])
961 ;; maskir insn. We need four forms because things might be in arbitrary
962 ;; orders. Don't define forms that only set CR fields because these
963 ;; would modify an input register.
966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
967 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
968 (match_operand:SI 1 "gpc_reg_operand" "0"))
969 (and:SI (match_dup 2)
970 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
975 [(set (match_operand:SI 0 "register_operand" "=r")
976 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
977 (match_operand:SI 1 "gpc_reg_operand" "0"))
978 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
984 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
985 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
986 (match_operand:SI 3 "gpc_reg_operand" "r"))
987 (and:SI (not:SI (match_dup 2))
988 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
993 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
994 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
995 (match_operand:SI 2 "gpc_reg_operand" "r"))
996 (and:SI (not:SI (match_dup 2))
997 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
1002 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1004 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1005 (match_operand:SI 1 "gpc_reg_operand" "0"))
1006 (and:SI (match_dup 2)
1007 (match_operand:SI 3 "gpc_reg_operand" "r")))
1009 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1010 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
1011 (and:SI (match_dup 2) (match_dup 3))))]
1014 [(set_attr "type" "compare")])
1017 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1019 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1020 (match_operand:SI 1 "gpc_reg_operand" "0"))
1021 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1024 (set (match_operand:SI 0 "register_operand" "=r")
1025 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
1026 (and:SI (match_dup 3) (match_dup 2))))]
1029 [(set_attr "type" "compare")])
1032 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1034 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1035 (match_operand:SI 3 "gpc_reg_operand" "r"))
1036 (and:SI (not:SI (match_dup 2))
1037 (match_operand:SI 1 "gpc_reg_operand" "0")))
1039 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1040 (ior:SI (and:SI (match_dup 2) (match_dup 3))
1041 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
1044 [(set_attr "type" "compare")])
1047 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1049 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1050 (match_operand:SI 2 "gpc_reg_operand" "r"))
1051 (and:SI (not:SI (match_dup 2))
1052 (match_operand:SI 1 "gpc_reg_operand" "0")))
1054 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1055 (ior:SI (and:SI (match_dup 3) (match_dup 2))
1056 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
1059 [(set_attr "type" "compare")])
1061 ;; Rotate and shift insns, in all their variants. These support shifts,
1062 ;; field inserts and extracts, and various combinations thereof.
1064 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1065 (match_operand:SI 1 "const_int_operand" "i")
1066 (match_operand:SI 2 "const_int_operand" "i"))
1067 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1071 int start = INTVAL (operands[2]) & 31;
1072 int size = INTVAL (operands[1]) & 31;
1074 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
1075 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1076 return \"rlimi %0,%3,%4,%h2,%h1\";
1079 (define_insn "extzv"
1080 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1081 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1082 (match_operand:SI 2 "const_int_operand" "i")
1083 (match_operand:SI 3 "const_int_operand" "i")))]
1087 int start = INTVAL (operands[3]) & 31;
1088 int size = INTVAL (operands[2]) & 31;
1090 if (start + size >= 32)
1091 operands[3] = const0_rtx;
1093 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1094 return \"rlinm %0,%1,%3,%s2,31\";
1098 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1099 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1100 (match_operand:SI 2 "const_int_operand" "i")
1101 (match_operand:SI 3 "const_int_operand" "i"))
1103 (clobber (match_scratch:SI 4 "=r"))]
1107 int start = INTVAL (operands[3]) & 31;
1108 int size = INTVAL (operands[2]) & 31;
1110 /* If the bitfield being tested fits in the upper or lower half of a
1111 word, it is possible to use andiu. or andil. to test it. This is
1112 useful because the condition register set-use delay is smaller for
1113 andi[ul]. than for rlinm. This doesn't work when the starting bit
1114 position is 0 because the LT and GT bits may be set wrong. */
1116 if ((start > 0 && start + size <= 16) || start >= 16)
1118 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1119 ((1 << (16 - (start & 15)))
1120 - (1 << (16 - (start & 15) - size))));
1122 return \"andiu. %4,%1,%3\";
1124 return \"andil. %4,%1,%3\";
1127 if (start + size >= 32)
1128 operands[3] = const0_rtx;
1130 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1131 return \"rlinm. %4,%1,%3,%s2,31\";
1133 [(set_attr "type" "compare")])
1136 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1137 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1138 (match_operand:SI 2 "const_int_operand" "i")
1139 (match_operand:SI 3 "const_int_operand" "i"))
1141 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1142 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
1146 int start = INTVAL (operands[3]) & 31;
1147 int size = INTVAL (operands[2]) & 31;
1149 if (start >= 16 && start + size == 32)
1151 operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
1152 return \"andil. %0,%1,%3\";
1155 if (start + size >= 32)
1156 operands[3] = const0_rtx;
1158 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1159 return \"rlinm. %0,%1,%3,%s2,31\";
1161 [(set_attr "type" "delayed_compare")])
1163 (define_insn "rotlsi3"
1164 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1165 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1166 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
1168 "rl%I2nm %0,%1,%h2,0xFFFFFFFF")
1171 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1172 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1173 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1175 (clobber (match_scratch:SI 3 "=r"))]
1177 "rl%I2nm. %3,%1,%h2,0xFFFFFFFF"
1178 [(set_attr "type" "delayed_compare")])
1181 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1182 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1183 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1185 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1186 (rotate:SI (match_dup 1) (match_dup 2)))]
1188 "rl%I2nm. %0,%1,%h2,0xFFFFFFFF"
1189 [(set_attr "type" "delayed_compare")])
1192 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1193 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1194 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1195 (match_operand:SI 3 "mask_operand" "L")))]
1197 "rl%I2nm %0,%1,%h2,%m3,%M3")
1200 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1202 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1203 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1204 (match_operand:SI 3 "mask_operand" "L"))
1206 (clobber (match_scratch:SI 4 "=r"))]
1208 "rl%I2nm. %4,%1,%h2,%m3,%M3"
1209 [(set_attr "type" "delayed_compare")])
1212 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1214 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1215 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1216 (match_operand:SI 3 "mask_operand" "L"))
1218 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1219 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1221 "rl%I2nm. %0,%1,%h2,%m3,%M3"
1222 [(set_attr "type" "delayed_compare")])
1225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1228 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1229 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1231 "rl%I2nm %0,%1,%h2,0x000000FF")
1234 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1235 (compare:CC (zero_extend:SI
1237 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1238 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1240 (clobber (match_scratch:SI 3 "=r"))]
1242 "rl%I2nm. %3,%1,%h2,0x000000FF"
1243 [(set_attr "type" "delayed_compare")])
1246 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1247 (compare:CC (zero_extend:SI
1249 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1250 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1252 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1253 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1255 "rl%I2nm. %0,%1,%h2,0x000000FF"
1256 [(set_attr "type" "delayed_compare")])
1259 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1262 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1263 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1265 "rl%I2nm %0,%1,%h2,0x0000FFFF")
1268 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1269 (compare:CC (zero_extend:SI
1271 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1272 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1274 (clobber (match_scratch:SI 3 "=r"))]
1276 "rl%I2nm. %3,%1,%h2,0x0000FFFF"
1277 [(set_attr "type" "delayed_compare")])
1280 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1281 (compare:CC (zero_extend:SI
1283 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1284 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1286 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1287 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1289 "rl%I2nm. %0,%1,%h2,0x0000FFFF"
1290 [(set_attr "type" "delayed_compare")])
1292 ;; Note that we use "sle." instead of "sl." so that we can set
1293 ;; SHIFT_COUNT_TRUNCATED.
1295 (define_insn "ashlsi3"
1296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1297 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1298 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1299 (clobber (match_scratch:SI 3 "=q,X"))]
1304 [(set_attr "length" "8")])
1307 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1308 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1309 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1311 (clobber (match_scratch:SI 3 "=r,r"))
1312 (clobber (match_scratch:SI 4 "=q,X"))]
1317 [(set_attr "type" "delayed_compare")])
1320 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1321 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1322 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1324 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1325 (ashift:SI (match_dup 1) (match_dup 2)))
1326 (clobber (match_scratch:SI 4 "=q,X"))]
1331 [(set_attr "type" "delayed_compare")])
1334 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1335 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1336 (match_operand:SI 2 "const_int_operand" "i"))
1337 (match_operand:SI 3 "mask_operand" "L")))]
1338 "includes_lshift_p (operands[2], operands[3])"
1339 "rlinm %0,%h1,%h2,%m3,%M3")
1342 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1344 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1345 (match_operand:SI 2 "const_int_operand" "i"))
1346 (match_operand:SI 3 "mask_operand" "L"))
1348 (clobber (match_scratch:SI 4 "=r"))]
1349 "includes_lshift_p (operands[2], operands[3])"
1350 "rlinm. %4,%h1,%h2,%m3,%M3"
1351 [(set_attr "type" "delayed_compare")])
1354 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1356 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1357 (match_operand:SI 2 "const_int_operand" "i"))
1358 (match_operand:SI 3 "mask_operand" "L"))
1360 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1361 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1362 "includes_lshift_p (operands[2], operands[3])"
1363 "rlinm. %0,%h1,%h2,%m3,%M3"
1364 [(set_attr "type" "delayed_compare")])
1366 ;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as
1368 (define_insn "lshrsi3"
1369 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1370 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1371 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1372 (clobber (match_scratch:SI 3 "=q,X"))]
1379 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1380 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1381 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1383 (clobber (match_scratch:SI 3 "=r,r"))
1384 (clobber (match_scratch:SI 4 "=q,X"))]
1389 [(set_attr "type" "delayed_compare")])
1392 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1393 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1394 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1396 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1397 (lshiftrt:SI (match_dup 1) (match_dup 2)))
1398 (clobber (match_scratch:SI 4 "=q,X"))]
1403 [(set_attr "type" "delayed_compare")])
1406 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1407 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1408 (match_operand:SI 2 "const_int_operand" "i"))
1409 (match_operand:SI 3 "mask_operand" "L")))]
1410 "includes_rshift_p (operands[2], operands[3])"
1411 "rlinm %0,%1,%s2,%m3,%M3")
1414 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1416 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1417 (match_operand:SI 2 "const_int_operand" "i"))
1418 (match_operand:SI 3 "mask_operand" "L"))
1420 (clobber (match_scratch:SI 4 "=r"))]
1421 "includes_rshift_p (operands[2], operands[3])"
1422 "rlinm. %4,%1,%s2,%m3,%M3"
1423 [(set_attr "type" "delayed_compare")])
1426 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1428 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1429 (match_operand:SI 2 "const_int_operand" "i"))
1430 (match_operand:SI 3 "mask_operand" "L"))
1432 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1433 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1434 "includes_rshift_p (operands[2], operands[3])"
1435 "rlinm. %0,%1,%s2,%m3,%M3"
1436 [(set_attr "type" "delayed_compare")])
1439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1442 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1443 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1444 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1445 "rlinm %0,%1,%s2,0x000000FF")
1448 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1452 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1453 (match_operand:SI 2 "const_int_operand" "i")) 0))
1455 (clobber (match_scratch:SI 3 "=r"))]
1456 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1457 "rlinm. %3,%1,%s2,0x000000FF"
1458 [(set_attr "type" "delayed_compare")])
1461 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1465 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1466 (match_operand:SI 2 "const_int_operand" "i")) 0))
1468 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1469 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1470 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1471 "rlinm. %0,%1,%s2,0x000000FF"
1472 [(set_attr "type" "delayed_compare")])
1475 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1478 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1479 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1480 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1481 "rlinm %0,%1,%s2,0x0000FFFF")
1484 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1488 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1489 (match_operand:SI 2 "const_int_operand" "i")) 0))
1491 (clobber (match_scratch:SI 3 "=r"))]
1492 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1493 "rlinm. %3,%1,%s2,0x0000FFFF"
1494 [(set_attr "type" "delayed_compare")])
1497 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1501 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1502 (match_operand:SI 2 "const_int_operand" "i")) 0))
1504 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1505 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1506 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1507 "rlinm. %0,%1,%s2,0x0000FFFF"
1508 [(set_attr "type" "delayed_compare")])
1511 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1513 (match_operand:SI 1 "gpc_reg_operand" "r"))
1514 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1520 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1522 (match_operand:SI 1 "gpc_reg_operand" "r"))
1523 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1529 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1531 (match_operand:SI 1 "gpc_reg_operand" "r"))
1532 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1538 (define_insn "ashrsi3"
1539 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1540 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1541 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1542 (clobber (match_scratch:SI 3 "=q,X"))]
1549 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1550 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1551 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1553 (clobber (match_scratch:SI 3 "=r,r"))
1554 (clobber (match_scratch:SI 4 "=q,X"))]
1559 [(set_attr "type" "delayed_compare")])
1562 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1563 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1564 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1566 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1567 (ashiftrt:SI (match_dup 1) (match_dup 2)))
1568 (clobber (match_scratch:SI 4 "=q,X"))]
1573 [(set_attr "type" "delayed_compare")])
1575 (define_expand "extendqisi2"
1576 [(parallel [(set (match_dup 2)
1577 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1579 (clobber (scratch:SI))])
1580 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1581 (ashiftrt:SI (match_dup 2)
1583 (clobber (scratch:SI))])]
1586 { operands[1] = gen_lowpart (SImode, operands[1]);
1587 operands[2] = gen_reg_rtx (SImode); }")
1589 (define_expand "extendqihi2"
1590 [(parallel [(set (match_dup 2)
1591 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1593 (clobber (scratch:SI))])
1594 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
1595 (ashiftrt:SI (match_dup 2)
1597 (clobber (scratch:SI))])]
1600 { operands[0] = gen_lowpart (SImode, operands[0]);
1601 operands[1] = gen_lowpart (SImode, operands[1]);
1602 operands[2] = gen_reg_rtx (SImode); }")
1604 ;; Floating-point insns, excluding normal data motion.
1606 ;; We pretend that we have both SFmode and DFmode insns, while, in fact,
1607 ;; all fp insns are actually done in double. The only conversions we will
1608 ;; do will be when storing to memory. In that case, we will use the "frsp"
1609 ;; instruction before storing.
1611 ;; Note that when we store into a single-precision memory location, we need to
1612 ;; use the frsp insn first. If the register being stored isn't dead, we
1613 ;; need a scratch register for the frsp. But this is difficult when the store
1614 ;; is done by reload. It is not incorrect to do the frsp on the register in
1615 ;; this case, we just lose precision that we would have otherwise gotten but
1616 ;; is not guaranteed. Perhaps this should be tightened up at some point.
1618 (define_insn "extendsfdf2"
1619 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1620 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
1624 if (REGNO (operands[0]) == REGNO (operands[1]))
1627 return \"fmr %0,%1\";
1629 [(set_attr "type" "fp")])
1631 (define_insn "truncdfsf2"
1632 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1633 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
1637 if (REGNO (operands[0]) == REGNO (operands[1]))
1640 return \"fmr %0,%1\";
1642 [(set_attr "type" "fp")])
1644 (define_insn "negsf2"
1645 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1646 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
1649 [(set_attr "type" "fp")])
1651 (define_insn "abssf2"
1652 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1653 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
1656 [(set_attr "type" "fp")])
1659 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1660 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
1663 [(set_attr "type" "fp")])
1665 (define_insn "addsf3"
1666 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1667 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
1668 (match_operand:SF 2 "gpc_reg_operand" "f")))]
1671 [(set_attr "type" "fp")])
1673 (define_insn "subsf3"
1674 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1675 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
1676 (match_operand:SF 2 "gpc_reg_operand" "f")))]
1679 [(set_attr "type" "fp")])
1681 (define_insn "mulsf3"
1682 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1683 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
1684 (match_operand:SF 2 "gpc_reg_operand" "f")))]
1687 [(set_attr "type" "fp")])
1689 (define_insn "divsf3"
1690 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1691 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
1692 (match_operand:SF 2 "gpc_reg_operand" "f")))]
1695 [(set_attr "type" "fp")])
1698 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1699 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
1700 (match_operand:SF 2 "gpc_reg_operand" "f"))
1701 (match_operand:SF 3 "gpc_reg_operand" "f")))]
1704 [(set_attr "type" "fp")])
1707 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1708 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
1709 (match_operand:SF 2 "gpc_reg_operand" "f"))
1710 (match_operand:SF 3 "gpc_reg_operand" "f")))]
1713 [(set_attr "type" "fp")])
1716 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1717 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
1718 (match_operand:SF 2 "gpc_reg_operand" "f"))
1719 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
1722 [(set_attr "type" "fp")])
1725 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1726 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
1727 (match_operand:SF 2 "gpc_reg_operand" "f"))
1728 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
1731 [(set_attr "type" "fp")])
1733 (define_insn "negdf2"
1734 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1735 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
1738 [(set_attr "type" "fp")])
1740 (define_insn "absdf2"
1741 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1742 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
1745 [(set_attr "type" "fp")])
1748 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1749 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
1752 [(set_attr "type" "fp")])
1754 (define_insn "adddf3"
1755 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1756 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
1757 (match_operand:DF 2 "gpc_reg_operand" "f")))]
1760 [(set_attr "type" "fp")])
1762 (define_insn "subdf3"
1763 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1764 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
1765 (match_operand:DF 2 "gpc_reg_operand" "f")))]
1768 [(set_attr "type" "fp")])
1770 (define_insn "muldf3"
1771 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1772 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
1773 (match_operand:DF 2 "gpc_reg_operand" "f")))]
1776 [(set_attr "type" "fp")])
1778 (define_insn "divdf3"
1779 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1780 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
1781 (match_operand:DF 2 "gpc_reg_operand" "f")))]
1784 [(set_attr "type" "fp")])
1787 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1788 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
1789 (match_operand:DF 2 "gpc_reg_operand" "f"))
1790 (match_operand:DF 3 "gpc_reg_operand" "f")))]
1793 [(set_attr "type" "fp")])
1796 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1797 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
1798 (match_operand:DF 2 "gpc_reg_operand" "f"))
1799 (match_operand:DF 3 "gpc_reg_operand" "f")))]
1802 [(set_attr "type" "fp")])
1805 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1806 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
1807 (match_operand:DF 2 "gpc_reg_operand" "f"))
1808 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
1811 [(set_attr "type" "fp")])
1814 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1815 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
1816 (match_operand:DF 2 "gpc_reg_operand" "f"))
1817 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
1820 [(set_attr "type" "fp")])
1822 ;; Conversions to and from floating-point.
1823 (define_expand "floatsidf2"
1825 (plus:DI (zero_extend:DI
1826 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1829 (set (match_operand:DF 0 "gpc_reg_operand" "")
1830 (minus:DF (subreg:DF (match_dup 2) 0)
1835 #if HOST_BITS_PER_INT != BITS_PER_WORD
1836 /* Maybe someone can figure out how to do this in that case. I don't
1837 want to right now. */
1841 operands[2] = gen_reg_rtx (DImode);
1842 operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
1843 operands[4] = immed_double_const (0, 0x43300000, DImode);
1844 operands[5] = force_reg (DFmode, immed_double_const (0x43300000,
1845 0x80000000, DFmode));
1848 (define_expand "floatunssidf2"
1850 (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1852 (set (match_operand:DF 0 "gpc_reg_operand" "")
1853 (minus:DF (subreg:DF (match_dup 2) 0)
1858 #if HOST_BITS_PER_INT != BITS_PER_WORD
1859 /* Maybe someone can figure out how to do this in that case. I don't
1860 want to right now. */
1864 operands[2] = gen_reg_rtx (DImode);
1865 operands[3] = immed_double_const (0, 0x43300000, DImode);
1866 operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode));
1869 ;; For the above two cases, we always split.
1871 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1872 (plus:DI (zero_extend:DI
1873 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1874 (match_operand:SI 2 "logical_operand" "")))
1875 (match_operand:DI 3 "immediate_operand" "")))]
1876 "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1877 && GET_CODE (operands[3]) == CONST_DOUBLE
1878 && CONST_DOUBLE_LOW (operands[3]) == 0"
1879 [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2)))
1880 (set (match_dup 4) (match_dup 5))]
1882 { operands[4] = operand_subword (operands[0], 0, 0, DImode);
1883 operands[5] = operand_subword (operands[3], 0, 0, DImode);
1884 operands[6] = operand_subword (operands[0], 1, 0, DImode);
1888 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1889 (plus:DI (zero_extend:DI
1890 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1891 (match_operand:SI 2 "logical_operand" "rKJ")))
1892 (match_operand:DI 3 "immediate_operand" "n")))]
1893 "HOST_BITS_PER_INT == BITS_PER_WORD
1894 && GET_CODE (operands[3]) == CONST_DOUBLE
1895 && CONST_DOUBLE_LOW (operands[3]) == 0"
1899 [(set (match_operand:DI 0 "gpc_reg_operand" "=")
1900 (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1901 (match_operand:DI 2 "immediate_operand" "")))]
1902 "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1903 && GET_CODE (operands[2]) == CONST_DOUBLE
1904 && CONST_DOUBLE_LOW (operands[2]) == 0"
1905 [(set (match_dup 3) (match_dup 4))
1906 (set (match_dup 5) (match_dup 1))]
1908 { operands[3] = operand_subword (operands[0], 0, 0, DImode);
1909 operands[4] = operand_subword (operands[2], 0, 0, DImode);
1910 operands[5] = operand_subword (operands[0], 1, 0, DImode);
1912 if (rtx_equal_p (operands[1], operands[5]))
1914 emit_move_insn (operands[3], operands[4]);
1918 if (rtx_equal_p (operands[1], operands[3]))
1922 temp = operands[3]; operands[3] = operands[5]; operands[5] = temp;
1923 temp = operands[4]; operands[4] = operands[1]; operands[1] = temp;
1928 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1929 (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1930 (match_operand:DI 2 "immediate_operand" "n")))]
1931 "HOST_BITS_PER_INT == BITS_PER_WORD
1932 && GET_CODE (operands[2]) == CONST_DOUBLE
1933 && CONST_DOUBLE_LOW (operands[2]) == 0"
1936 (define_expand "fix_truncdfsi2"
1937 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1938 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
1942 emit_insn (gen_trunc_call (operands[0], operands[1],
1943 gen_rtx (SYMBOL_REF, Pmode, \"itrunc\")));
1947 (define_expand "fixuns_truncdfsi2"
1948 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1949 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
1953 emit_insn (gen_trunc_call (operands[0], operands[1],
1954 gen_rtx (SYMBOL_REF, Pmode, \"uitrunc\")));
1959 (define_expand "trunc_call"
1960 [(parallel [(set (match_operand:SI 0 "" "")
1961 (fix:SI (match_operand:DF 1 "" "")))
1962 (use (match_operand:SI 2 "" ""))])]
1966 rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
1967 rtx first = XVECEXP (insns, 0, 0);
1968 rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1970 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1972 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
1978 (define_expand "trunc_call_rtl"
1979 [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
1981 (parallel [(set (reg:SI 3)
1982 (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
1983 (clobber (scratch:SI))])
1984 (set (match_operand:SI 0 "gpc_reg_operand" "")
1989 rs6000_trunc_used = 1;
1992 ;; Define the DImode operations that can be done in a small number
1994 (define_insn "adddi3"
1995 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1996 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
1997 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
2000 a %L0,%L1,%L2\;ae %0,%1,%2
2001 ai %L0,%L1,%2\;a%G2e %0,%1"
2002 [(set_attr "length" "8")])
2004 (define_insn "subdi3"
2005 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
2006 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
2007 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
2010 sf %L0,%L2,%L1\;sfe %0,%2,%1
2011 sfi %L0,%L2,%1\;sf%G1e %0,%2"
2012 [(set_attr "length" "8")])
2014 (define_insn "negdi2"
2015 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2016 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
2018 "sfi %L0,%L1,0\;sfze %0,%1"
2019 [(set_attr "length" "8")])
2021 (define_insn "mulsidi3"
2022 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2023 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2024 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
2025 (clobber (match_scratch:SI 3 "=q"))]
2027 "mul %0,%1,%2\;mfmq %L0"
2028 [(set_attr "length" "8")])
2030 ;; If operands 0 and 2 are in the same register, we have a problem. But
2031 ;; operands 0 and 1 (the usual case) can be in the same register. That's
2032 ;; why we have the strange constraints below.
2033 (define_insn "ashldi3"
2034 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
2035 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
2036 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
2037 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
2040 sli %0,%L1,%h2\;cal %L0,0(0)
2041 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
2042 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
2043 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
2044 [(set_attr "length" "8")])
2046 (define_insn "lshrdi3"
2047 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
2048 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
2049 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
2050 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
2053 cal %0,0(0)\;s%A2i %L0,%1,%h2
2054 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
2055 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
2056 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
2057 [(set_attr "length" "8")])
2059 ;; Shift by a variable amount is too complex to be worth open-coding. We
2060 ;; just handle shifts by constants.
2062 (define_expand "ashrdi3"
2063 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=")
2064 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
2065 (match_operand:SI 2 "general_operand" "")))
2066 (clobber (match_scratch:SI 3 ""))])]
2069 { if (GET_CODE (operands[2]) != CONST_INT)
2074 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
2075 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
2076 (match_operand:SI 2 "const_int_operand" "M,i")))
2077 (clobber (match_scratch:SI 3 "=X,q"))]
2080 srai %0,%1,31\;srai %L0,%1,%h2
2081 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
2082 [(set_attr "length" "8")])
2084 ;; Now define ways of moving data around.
2086 ;; For SI, we special-case integers that can't be loaded in one insn. We
2087 ;; do the load 16-bits at a time. We could do this by loading from memory,
2088 ;; and this is even supposed to be faster, but it is simpler not to get
2089 ;; integers in the TOC.
2090 (define_expand "movsi"
2091 [(set (match_operand:SI 0 "general_operand" "")
2092 (match_operand:SI 1 "any_operand" ""))]
2096 if (GET_CODE (operands[0]) != REG)
2097 operands[1] = force_reg (SImode, operands[1]);
2099 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2101 operands[1] = force_const_mem (SImode, operands[1]);
2102 if (! memory_address_p (SImode, XEXP (operands[1], 0))
2103 && ! reload_in_progress)
2104 operands[1] = change_address (operands[1], SImode,
2105 XEXP (operands[1], 0));
2108 if (GET_CODE (operands[1]) == CONST_INT
2109 && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
2110 && (INTVAL (operands[1]) & 0xffff) != 0)
2112 emit_move_insn (operands[0],
2113 gen_rtx (CONST_INT, VOIDmode,
2114 INTVAL (operands[1]) & 0xffff0000));
2115 emit_insn (gen_iorsi3 (operands[0], operands[0],
2116 gen_rtx (CONST_INT, VOIDmode,
2117 INTVAL (operands[1]) & 0xffff)));
2123 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l,*h")
2124 (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r,0"))]
2125 "gpc_reg_operand (operands[0], SImode)
2126 || gpc_reg_operand (operands[1], SImode)"
2137 [(set_attr "type" "*,load,*,*,*,*,*,mtlr,*")])
2139 ;; Split a load of a large constant into the appropriate two-insn
2143 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2144 (match_operand:SI 1 "const_int_operand" ""))]
2145 "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
2146 && (INTVAL (operands[1]) & 0xffff) != 0"
2150 (ior:SI (match_dup 0)
2154 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2155 INTVAL (operands[1]) & 0xffff0000);
2156 operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
2160 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
2161 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
2163 (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
2166 [(set_attr "type" "compare")])
2168 (define_expand "movhi"
2169 [(set (match_operand:HI 0 "general_operand" "")
2170 (match_operand:HI 1 "any_operand" ""))]
2174 if (GET_CODE (operands[0]) != REG)
2175 operands[1] = force_reg (HImode, operands[1]);
2177 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2179 operands[1] = force_const_mem (HImode, operands[1]);
2180 if (! memory_address_p (HImode, XEXP (operands[1], 0))
2181 && ! reload_in_progress)
2182 operands[1] = change_address (operands[1], HImode,
2183 XEXP (operands[1], 0));
2188 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
2189 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
2190 "gpc_reg_operand (operands[0], HImode)
2191 || gpc_reg_operand (operands[1], HImode)"
2200 [(set_attr "type" "*,load,*,*,*,*,*")])
2202 (define_expand "movqi"
2203 [(set (match_operand:QI 0 "general_operand" "")
2204 (match_operand:QI 1 "any_operand" ""))]
2208 if (GET_CODE (operands[0]) != REG)
2209 operands[1] = force_reg (QImode, operands[1]);
2211 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2213 operands[1] = force_const_mem (QImode, operands[1]);
2214 if (! memory_address_p (QImode, XEXP (operands[1], 0))
2215 && ! reload_in_progress)
2216 operands[1] = change_address (operands[1], QImode,
2217 XEXP (operands[1], 0));
2222 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
2223 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
2224 "gpc_reg_operand (operands[0], QImode)
2225 || gpc_reg_operand (operands[1], QImode)"
2234 [(set_attr "type" "*,load,*,*,*,*,*")])
2236 ;; Here is how to move condition codes around. When we store CC data in
2237 ;; an integer register or memory, we store just the high-order 4 bits.
2238 ;; This lets us not shift in the most common case of CR0.
2239 (define_expand "movcc"
2240 [(set (match_operand:CC 0 "nonimmediate_operand" "")
2241 (match_operand:CC 1 "nonimmediate_operand" ""))]
2246 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
2247 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
2248 "register_operand (operands[0], CCmode)
2249 || register_operand (operands[1], CCmode)"
2253 rlinm %1,%1,%F0,0xFFFFFFFF\;mtcrf %R0,%1\;rlinm %1,%1,%f0,0xFFFFFFFF
2255 mfcr %0\;rlinm %0,%0,%f1,0xF0000000
2259 [(set_attr "type" "*,*,*,compare,*,*,load,*")
2260 (set_attr "length" "*,*,12,*,8,*,*,*")])
2262 ;; For floating-point, we normally deal with the floating-point registers.
2263 ;; The sole exception is that parameter passing can produce floating-point
2264 ;; values in fixed-point registers. Unless the value is a simple constant
2265 ;; or already in memory, we deal with this by allocating memory and copying
2266 ;; the value explicitly via that memory location.
2267 (define_expand "movsf"
2268 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2269 (match_operand:SF 1 "any_operand" ""))]
2273 /* If we are called from reload, we might be getting a SUBREG of a hard
2274 reg. So expand it. */
2275 if (GET_CODE (operands[0]) == SUBREG
2276 && GET_CODE (SUBREG_REG (operands[0])) == REG
2277 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2278 operands[0] = alter_subreg (operands[0]);
2279 if (GET_CODE (operands[1]) == SUBREG
2280 && GET_CODE (SUBREG_REG (operands[1])) == REG
2281 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2282 operands[1] = alter_subreg (operands[1]);
2284 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2288 /* If this is a store to memory or another integer register do the
2289 move directly. Otherwise store to a temporary stack slot and
2290 load from there into a floating point register. */
2292 if (GET_CODE (operands[0]) == MEM
2293 || (GET_CODE (operands[0]) == REG
2294 && (REGNO (operands[0]) < 32
2295 || (reload_in_progress
2296 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
2298 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2299 operand_subword (operands[1], 0, 0, SFmode));
2303 stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4));
2304 emit_move_insn (stack_slot, operands[1]);
2305 emit_move_insn (operands[0], stack_slot);
2309 if (GET_CODE (operands[0]) == MEM)
2310 operands[1] = force_reg (SFmode, operands[1]);
2312 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2316 if (GET_CODE (operands[1]) == MEM
2317 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2318 || GET_CODE (operands[1]) == CONST_DOUBLE
2320 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2321 || (reload_in_progress && GET_CODE (operands[1]) == REG
2322 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2324 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2325 operand_subword (operands[1], 0, 0, SFmode));
2329 if (reload_in_progress)
2330 stack_slot = gen_rtx (MEM, SFmode,
2331 plus_constant (stack_pointer_rtx, 4));
2333 stack_slot = assign_stack_temp (SFmode, 4, 0);
2334 emit_move_insn (stack_slot, operands[1]);
2335 emit_move_insn (operands[0], stack_slot);
2339 if (CONSTANT_P (operands[1]))
2341 operands[1] = force_const_mem (SFmode, operands[1]);
2342 if (! memory_address_p (SFmode, XEXP (operands[1], 0))
2343 && ! reload_in_progress)
2344 operands[1] = change_address (operands[1], SFmode,
2345 XEXP (operands[1], 0));
2350 [(set (match_operand:SF 0 "gpc_reg_operand" "=r,r")
2351 (match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))]
2352 "REGNO (operands[0]) <= 31"
2356 [(set_attr "type" "*,load")])
2359 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2360 (match_operand:SF 1 "easy_fp_constant" ""))]
2361 "reload_completed && REGNO (operands[0]) <= 31"
2362 [(set (match_dup 2) (match_dup 3))]
2364 { operands[2] = operand_subword (operands[0], 0, 0, SFmode);
2365 operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
2368 [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
2369 (match_operand:SF 1 "input_operand" "f,m,f"))]
2370 "gpc_reg_operand (operands[0], SFmode)
2371 || gpc_reg_operand (operands[1], SFmode)"
2375 frsp %1,%1\;stfs%U0%X0 %1,%0"
2376 [(set_attr "type" "fp,load,*")
2377 (set_attr "length" "*,*,8")])
2379 (define_expand "movdf"
2380 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2381 (match_operand:DF 1 "any_operand" ""))]
2385 /* If we are called from reload, we might be getting a SUBREG of a hard
2386 reg. So expand it. */
2387 if (GET_CODE (operands[0]) == SUBREG
2388 && GET_CODE (SUBREG_REG (operands[0])) == REG
2389 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2390 operands[0] = alter_subreg (operands[0]);
2391 if (GET_CODE (operands[1]) == SUBREG
2392 && GET_CODE (SUBREG_REG (operands[1])) == REG
2393 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2394 operands[1] = alter_subreg (operands[1]);
2396 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2400 /* If this is a store to memory or another integer register do the
2401 move directly. Otherwise store to a temporary stack slot and
2402 load from there into a floating point register. */
2404 if (GET_CODE (operands[0]) == MEM
2405 || (GET_CODE (operands[0]) == REG
2406 && (REGNO (operands[0]) < 32
2407 || (reload_in_progress
2408 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
2410 emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2411 operand_subword (operands[1], 0, 0, DFmode));
2412 emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2413 operand_subword (operands[1], 1, 0, DFmode));
2417 stack_slot = gen_rtx (MEM, DFmode, plus_constant (stack_pointer_rtx, 8));
2418 emit_move_insn (stack_slot, operands[1]);
2419 emit_move_insn (operands[0], stack_slot);
2423 if (GET_CODE (operands[0]) == MEM)
2425 if (GET_CODE (operands[1]) == MEM)
2427 emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2428 operand_subword (operands[1], 0, 0, DFmode));
2429 emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2430 operand_subword (operands[1], 1, 0, DFmode));
2434 operands[1] = force_reg (DFmode, operands[1]);
2437 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2441 if (GET_CODE (operands[1]) == MEM
2442 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2443 || GET_CODE (operands[1]) == CONST_DOUBLE
2445 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2446 || (reload_in_progress && GET_CODE (operands[1]) == REG
2447 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2449 emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2450 operand_subword (operands[1], 0, 0, DFmode));
2451 emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2452 operand_subword (operands[1], 1, 0, DFmode));
2456 if (reload_in_progress)
2457 stack_slot = gen_rtx (MEM, DFmode,
2458 plus_constant (stack_pointer_rtx, 8));
2460 stack_slot = assign_stack_temp (DFmode, 8, 0);
2461 emit_move_insn (stack_slot, operands[1]);
2462 emit_move_insn (operands[0], stack_slot);
2466 if (CONSTANT_P (operands[1]))
2468 operands[1] = force_const_mem (DFmode, operands[1]);
2469 if (! memory_address_p (DFmode, XEXP (operands[1], 0))
2470 && ! reload_in_progress)
2471 operands[1] = change_address (operands[1], DFmode,
2472 XEXP (operands[1], 0));
2477 [(set (match_operand:DF 0 "gpc_reg_operand" "=r,r")
2478 (match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))]
2479 "REGNO (operands[0]) <= 31"
2483 [(set_attr "type" "*,load")
2484 (set_attr "length" "*,8")])
2487 [(set (match_operand:DF 0 "gpc_reg_operand" "")
2488 (match_operand:DF 1 "easy_fp_constant" ""))]
2489 "reload_completed && REGNO (operands[0]) <= 31"
2490 [(set (match_dup 2) (match_dup 3))
2491 (set (match_dup 4) (match_dup 5))]
2493 { operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2494 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2495 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2496 operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
2499 [(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m")
2500 (match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))]
2501 "gpc_reg_operand (operands[0], DFmode)
2502 || gpc_reg_operand (operands[1], DFmode)"
2507 [(set_attr "type" "fp,load,*")])
2509 ;; Next come the multi-word integer load and store and the load and store
2511 (define_expand "movdi"
2512 [(set (match_operand:DI 0 "general_operand" "")
2513 (match_operand:DI 1 "general_operand" ""))]
2517 if (GET_CODE (operands[1]) == CONST_DOUBLE
2518 || GET_CODE (operands[1]) == CONST_INT)
2520 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
2521 operand_subword (operands[1], 0, 0, DImode));
2522 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
2523 operand_subword (operands[1], 1, 0, DImode));
2527 if (GET_CODE (operands[0]) == MEM)
2528 operands[1] = force_reg (DImode, operands[1]);
2532 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
2533 (match_operand:DI 1 "input_operand" "r,m,r"))]
2534 "gpc_reg_operand (operands[0], DImode)
2535 || gpc_reg_operand (operands[1], DImode)"
2538 switch (which_alternative)
2541 /* We normally copy the low-numbered register first. However, if
2542 the first register operand 0 is the same as the second register of
2543 operand 1, we must copy in the opposite order. */
2544 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
2545 return \"oril %L0,%L1,0\;oril %0,%1,0\";
2547 return \"oril %0,%1,0\;oril %L0,%L1,0\";
2549 /* If the low-address word is used in the address, we must load it
2550 last. Otherwise, load it first. Note that we cannot have
2551 auto-increment in that case since the address register is known to be
2553 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2555 return \"l %L0,%L1\;l %0,%1\";
2557 return \"l%U1 %0,%1\;l %L0,%L1\";
2559 return \"st%U0 %1,%0\;st %L1,%L0\";
2562 [(set_attr "type" "*,load,*")
2563 (set_attr "length" "8")])
2565 ;; TImode is similar, except that we usually want to compute the address into
2566 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
2567 ;; clobbered in stsi, so we need a SCRATCH for it.
2568 (define_expand "movti"
2569 [(parallel [(set (match_operand:TI 0 "general_operand" "")
2570 (match_operand:TI 1 "general_operand" ""))
2571 (clobber (scratch:SI))])]
2575 if (GET_CODE (operands[0]) == MEM)
2576 operands[1] = force_reg (TImode, operands[1]);
2578 if (GET_CODE (operands[0]) == MEM
2579 && GET_CODE (XEXP (operands[0], 0)) != REG
2580 && ! reload_in_progress)
2581 operands[0] = change_address (operands[0], TImode,
2582 copy_addr_to_reg (XEXP (operands[0], 0)));
2584 if (GET_CODE (operands[1]) == MEM
2585 && GET_CODE (XEXP (operands[1], 0)) != REG
2586 && ! reload_in_progress)
2587 operands[1] = change_address (operands[1], TImode,
2588 copy_addr_to_reg (XEXP (operands[1], 0)));
2591 ;; We say that MQ is clobbered in the last alternative because the first
2592 ;; alternative would never get used otherwise since it would need a reload
2593 ;; while the 2nd alternative would not. We put memory cases first so they
2594 ;; are preferred. Otherwise, we'd try to reload the output instead of
2595 ;; giving the SCRATCH mq.
2597 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r")
2598 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
2599 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
2600 "gpc_reg_operand (operands[0], TImode)
2601 || gpc_reg_operand (operands[1], TImode)"
2604 switch (which_alternative)
2607 return \"stsi %1,%P0,16\";
2610 return \"st%U0 %1,%0\;st %L1,%L0\;st %Y1,%Y0\;st %Z1,%Z0\";
2613 /* Normally copy registers with lowest numbered register copied first.
2614 But copy in the other order if the first register of the output
2615 is the second, third, or fourth register in the input. */
2616 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
2617 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
2618 return \"oril %Z0,%Z1,0\;oril %Y0,%Y1,0\;oril %L0,%L1,0\;oril %0,%1,0\";
2620 return \"oril %0,%1,0\;oril %L0,%L1,0\;oril %Y0,%Y1,0\;oril %Z0,%Z1,0\";
2622 /* If the address is not used in the output, we can use lsi. Otherwise,
2623 fall through to generating four loads. */
2624 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
2625 return \"lsi %0,%P1,16\";
2626 /* ... fall through ... */
2628 /* If the address register is the same as the register for the lowest-
2629 addressed word, load it last. Similarly for the next two words.
2630 Otherwise load lowest address to highest. */
2631 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2633 return \"l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\;l %0,%1\";
2634 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
2635 REGNO (operands[0]) + 2, operands[1], 0))
2636 return \"l %0,%1\;l %Y0,%Y1\;l %Z0,%Z1\;l %L0,%L1\";
2637 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
2638 REGNO (operands[0]) + 3, operands[1], 0))
2639 return \"l %0,%1\;l %L0,%L1\;l %Z0,%Z1\;l %Y0,%Y1\";
2641 return \"l%U1 %0,%1\;l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\";
2644 [(set_attr "type" "*,load,load,*,*")
2645 (set_attr "length" "*,16,16,*,16")])
2647 (define_expand "load_multiple"
2648 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
2649 (match_operand:SI 1 "" ""))
2650 (use (match_operand:SI 2 "" ""))])]
2659 /* Support only loading a constant number of fixed-point registers from
2660 memory and only bother with this if more than two; the machine
2661 doesn't support more than eight. */
2662 if (GET_CODE (operands[2]) != CONST_INT
2663 || INTVAL (operands[2]) <= 2
2664 || INTVAL (operands[2]) > 8
2665 || GET_CODE (operands[1]) != MEM
2666 || GET_CODE (operands[0]) != REG
2667 || REGNO (operands[0]) >= 32)
2670 count = INTVAL (operands[2]);
2671 regno = REGNO (operands[0]);
2673 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
2674 from = force_reg (SImode, XEXP (operands[1], 0));
2676 for (i = 0; i < count; i++)
2677 XVECEXP (operands[3], 0, i)
2678 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
2679 gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
2683 [(match_parallel 0 "load_multiple_operation"
2684 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
2685 (match_operand:SI 2 "indirect_operand" "Q"))])]
2689 /* We have to handle the case where the pseudo used to contain the address
2690 is assigned to one of the output registers. In that case, do the
2691 lsi, but then load the correct value. This is a bit of a mess, but is
2693 We set the length attribute to the maximum possible size (8 bytes). */
2694 static char result[100];
2698 strcpy (result, \"lsi %1,%P2,%N0\");
2699 for (i = 0; i < XVECLEN (operands[0], 0); i++)
2700 if (refers_to_regno_p (REGNO (operands[1]) + i,
2701 REGNO (operands[1]) + i + 1, operands[2], 0))
2703 sprintf (newload, \"\;l %d,%d(%d)\",
2704 REGNO (operands[1]) + i,
2705 i * 4, REGNO (XEXP (operands[2], 0)));
2706 strcat (result, newload);
2711 [(set_attr "type" "load")
2712 (set_attr "length" "8")])
2715 (define_expand "store_multiple"
2716 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
2717 (match_operand:SI 1 "" ""))
2718 (clobber (scratch:SI))
2719 (use (match_operand:SI 2 "" ""))])]
2728 /* Support only storing a constant number of fixed-point registers to
2729 memory and only bother with this if more than two; the machine
2730 doesn't support more than eight. */
2731 if (GET_CODE (operands[2]) != CONST_INT
2732 || INTVAL (operands[2]) <= 2
2733 || INTVAL (operands[2]) > 8
2734 || GET_CODE (operands[0]) != MEM
2735 || GET_CODE (operands[1]) != REG
2736 || REGNO (operands[1]) >= 32)
2739 count = INTVAL (operands[2]);
2740 regno = REGNO (operands[1]);
2742 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
2743 to = force_reg (SImode, XEXP (operands[0], 0));
2745 XVECEXP (operands[3], 0, 0)
2746 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]);
2747 XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
2748 gen_rtx (SCRATCH, SImode));
2750 for (i = 1; i < count; i++)
2751 XVECEXP (operands[3], 0, i + 1)
2752 = gen_rtx (SET, VOIDmode,
2753 gen_rtx (MEM, SImode, plus_constant (to, i * 4)),
2754 gen_rtx (REG, SImode, regno + i));
2758 [(match_parallel 0 "store_multiple_operation"
2759 [(set (match_operand:SI 1 "indirect_operand" "=Q")
2760 (match_operand:SI 2 "gpc_reg_operand" "r"))
2761 (clobber (match_scratch:SI 3 "=q"))])]
2765 ;; Define insns that do load or store with update. Some of these we can
2766 ;; get by using pre-decrement or pre-increment, but the hardware can also
2767 ;; do cases where the increment is not the size of the object.
2769 ;; In all these cases, we use operands 0 and 1 for the register being
2770 ;; incremented because those are the operands that local-alloc will
2771 ;; tie and these are the pair most likely to be tieable (and the ones
2772 ;; that will benefit the most).
2775 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
2776 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2777 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2778 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2779 (plus:SI (match_dup 1) (match_dup 2)))]
2784 [(set_attr "type" "load,load")])
2787 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2788 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2789 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2790 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2791 (plus:SI (match_dup 1) (match_dup 2)))]
2798 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
2799 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2800 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2801 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2802 (plus:SI (match_dup 1) (match_dup 2)))]
2807 [(set_attr "type" "load,load")])
2810 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
2812 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2813 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2814 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2815 (plus:SI (match_dup 1) (match_dup 2)))]
2820 [(set_attr "type" "load,load")])
2823 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
2825 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2826 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2827 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2828 (plus:SI (match_dup 1) (match_dup 2)))]
2833 [(set_attr "type" "load,load")])
2836 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2837 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2838 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
2839 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2840 (plus:SI (match_dup 1) (match_dup 2)))]
2845 [(set_attr "type" "load,load")])
2848 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
2849 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2850 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2851 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2852 (plus:SI (match_dup 1) (match_dup 2)))]
2857 [(set_attr "type" "load,load")])
2860 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
2862 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2863 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2864 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2865 (plus:SI (match_dup 1) (match_dup 2)))]
2870 [(set_attr "type" "load,load")])
2873 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2874 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2875 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
2876 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2877 (plus:SI (match_dup 1) (match_dup 2)))]
2884 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
2885 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2886 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2887 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2888 (plus:SI (match_dup 1) (match_dup 2)))]
2893 [(set_attr "type" "load,load")])
2896 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2897 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2898 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
2899 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2900 (plus:SI (match_dup 1) (match_dup 2)))]
2903 frsp %3,%3\;stfsux %3,%0,%2
2904 frsp %3,%3\;stfsu %3,%2(%0)")
2907 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
2908 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2909 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2910 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2911 (plus:SI (match_dup 1) (match_dup 2)))]
2916 [(set_attr "type" "load,load")])
2919 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
2920 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2921 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
2922 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
2923 (plus:SI (match_dup 1) (match_dup 2)))]
2929 ;; Next come insns related to the calling sequence.
2931 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
2932 ;; We move the back-chain and decrement the stack pointer.
2934 (define_expand "allocate_stack"
2936 (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))]
2939 { rtx chain = gen_reg_rtx (SImode);
2940 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
2942 emit_move_insn (chain, stack_bot);
2943 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0]));
2944 emit_move_insn (stack_bot, chain);
2948 ;; These patterns say how to save and restore the stack pointer. We need not
2949 ;; save the stack pointer at function level since we are careful to
2950 ;; preserve the backchain. At block level, we have to restore the backchain
2951 ;; when we restore the stack pointer.
2953 ;; For nonlocal gotos, we must save both the stack pointer and its
2954 ;; backchain and restore both. Note that in the nonlocal case, the
2955 ;; save area is a memory location.
2957 (define_expand "save_stack_function"
2958 [(use (const_int 0))]
2962 (define_expand "restore_stack_function"
2963 [(use (const_int 0))]
2967 (define_expand "restore_stack_block"
2968 [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" "")))
2969 (set (match_dup 0) (match_operand:SI 1 "register_operand" ""))
2970 (set (mem:SI (match_dup 0)) (match_dup 2))]
2973 { operands[2] = gen_reg_rtx (SImode); }")
2975 (define_expand "save_stack_nonlocal"
2976 [(match_operand:DI 0 "memory_operand" "")
2977 (match_operand:SI 1 "register_operand" "")]
2981 rtx temp = gen_reg_rtx (SImode);
2983 /* Copy the backchain to the first word, sp to the second. */
2984 emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1]));
2985 emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp);
2986 emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]);
2990 (define_expand "restore_stack_nonlocal"
2991 [(match_operand:SI 0 "register_operand" "")
2992 (match_operand:DI 1 "memory_operand" "")]
2996 rtx temp = gen_reg_rtx (SImode);
2998 /* Restore the backchain from the first word, sp from the second. */
2999 emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode));
3000 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode));
3001 emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp);
3005 ;; A function pointer is a pointer to a data area whose first word contains
3006 ;; the actual address of the function, whose second word contains a pointer
3007 ;; to its TOC, and whose third word contains a value to place in the static
3008 ;; chain register (r11). Note that if we load the static chain, our
3009 ;; "trampoline" need not have any executable code.
3011 ;; operands[0] is an SImode pseudo in which we place the address of the
3013 ;; operands[1] is the address of data area of the function to call
3015 (define_expand "call_via_ptr"
3016 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3017 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
3018 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
3021 (mem:SI (plus:SI (match_dup 1)
3024 (mem:SI (plus:SI (match_dup 1)
3031 (define_expand "call"
3032 [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
3033 (match_operand 1 "" ""))
3034 (clobber (scratch:SI))])]
3038 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
3041 operands[0] = XEXP (operands[0], 0);
3042 if (GET_CODE (operands[0]) != SYMBOL_REF)
3044 rtx temp = gen_reg_rtx (SImode);
3046 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0])));
3051 (define_expand "call_value"
3052 [(parallel [(set (match_operand 0 "" "")
3053 (call (mem:SI (match_operand:SI 1 "address_operand" ""))
3054 (match_operand 2 "" "")))
3055 (clobber (scratch:SI))])]
3059 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
3062 operands[1] = XEXP (operands[1], 0);
3063 if (GET_CODE (operands[1]) != SYMBOL_REF)
3065 rtx temp = gen_reg_rtx (SImode);
3067 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1])));
3072 ;; Call to function in current module. No TOC pointer reload needed.
3075 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s"))
3076 (match_operand 1 "" "g"))
3077 (clobber (match_scratch:SI 2 "=l"))]
3081 ;; Call to function which may be in another module. Restore the TOC
3082 ;; pointer (r2) after the call.
3085 [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s"))
3086 (match_operand 1 "" "fg,fg"))
3087 (clobber (match_scratch:SI 2 "=l,l"))]
3091 bl %z0\;cror %.,%.,%."
3092 [(set_attr "length" "8")])
3095 [(set (match_operand 0 "" "=fg")
3096 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s"))
3097 (match_operand 2 "" "g")))
3098 (clobber (match_scratch:SI 3 "=l"))]
3103 [(set (match_operand 0 "" "=fg,fg")
3104 (call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
3105 (match_operand 2 "" "fg,fg")))
3106 (clobber (match_scratch:SI 3 "=l,l"))]
3110 bl %z1\;cror %.,%.,%."
3111 [(set_attr "length" "8")])
3113 ;; Call subroutine returning any type.
3115 (define_expand "untyped_call"
3116 [(parallel [(call (match_operand 0 "" "")
3118 (match_operand 1 "" "")
3119 (match_operand 2 "" "")])]
3125 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
3127 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3129 rtx set = XVECEXP (operands[2], 0, i);
3130 emit_move_insn (SET_DEST (set), SET_SRC (set));
3133 /* The optimizer does not know that the call sets the function value
3134 registers we stored in the result block. We avoid problems by
3135 claiming that all hard registers are used and clobbered at this
3137 emit_insn (gen_blockage ());
3142 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
3143 ;; all of memory. This blocks insns from being moved across this point.
3145 (define_insn "blockage"
3146 [(unspec_volatile [(const_int 0)] 0)]
3150 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
3151 ;; signed & unsigned, and one type of branch.
3153 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
3154 ;; insns, and branches. We store the operands of compares until we see
3156 (define_expand "cmpsi"
3158 (compare (match_operand:SI 0 "gpc_reg_operand" "")
3159 (match_operand:SI 1 "reg_or_short_operand" "")))]
3163 /* Take care of the possibility that operands[1] might be negative but
3164 this might be a logical operation. That insn doesn't exist. */
3165 if (GET_CODE (operands[1]) == CONST_INT
3166 && INTVAL (operands[1]) < 0)
3167 operands[1] = force_reg (SImode, operands[1]);
3169 rs6000_compare_op0 = operands[0];
3170 rs6000_compare_op1 = operands[1];
3171 rs6000_compare_fp_p = 0;
3175 (define_expand "cmpsf"
3176 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
3177 (match_operand:SF 1 "gpc_reg_operand" "")))]
3181 rs6000_compare_op0 = operands[0];
3182 rs6000_compare_op1 = operands[1];
3183 rs6000_compare_fp_p = 1;
3187 (define_expand "cmpdf"
3188 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
3189 (match_operand:DF 1 "gpc_reg_operand" "")))]
3193 rs6000_compare_op0 = operands[0];
3194 rs6000_compare_op1 = operands[1];
3195 rs6000_compare_fp_p = 1;
3199 (define_expand "beq"
3200 [(set (match_dup 2) (match_dup 1))
3202 (if_then_else (eq (match_dup 2)
3204 (label_ref (match_operand 0 "" ""))
3208 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3209 operands[1] = gen_rtx (COMPARE, mode,
3210 rs6000_compare_op0, rs6000_compare_op1);
3211 operands[2] = gen_reg_rtx (mode);
3214 (define_expand "bne"
3215 [(set (match_dup 2) (match_dup 1))
3217 (if_then_else (ne (match_dup 2)
3219 (label_ref (match_operand 0 "" ""))
3223 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3224 operands[1] = gen_rtx (COMPARE, mode,
3225 rs6000_compare_op0, rs6000_compare_op1);
3226 operands[2] = gen_reg_rtx (mode);
3229 (define_expand "blt"
3230 [(set (match_dup 2) (match_dup 1))
3232 (if_then_else (lt (match_dup 2)
3234 (label_ref (match_operand 0 "" ""))
3238 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3239 operands[1] = gen_rtx (COMPARE, mode,
3240 rs6000_compare_op0, rs6000_compare_op1);
3241 operands[2] = gen_reg_rtx (mode);
3244 (define_expand "bgt"
3245 [(set (match_dup 2) (match_dup 1))
3247 (if_then_else (gt (match_dup 2)
3249 (label_ref (match_operand 0 "" ""))
3253 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3254 operands[1] = gen_rtx (COMPARE, mode,
3255 rs6000_compare_op0, rs6000_compare_op1);
3256 operands[2] = gen_reg_rtx (mode);
3259 (define_expand "ble"
3260 [(set (match_dup 2) (match_dup 1))
3262 (if_then_else (le (match_dup 2)
3264 (label_ref (match_operand 0 "" ""))
3268 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3269 operands[1] = gen_rtx (COMPARE, mode,
3270 rs6000_compare_op0, rs6000_compare_op1);
3271 operands[2] = gen_reg_rtx (mode);
3274 (define_expand "bge"
3275 [(set (match_dup 2) (match_dup 1))
3277 (if_then_else (ge (match_dup 2)
3279 (label_ref (match_operand 0 "" ""))
3283 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3284 operands[1] = gen_rtx (COMPARE, mode,
3285 rs6000_compare_op0, rs6000_compare_op1);
3286 operands[2] = gen_reg_rtx (mode);
3289 (define_expand "bgtu"
3290 [(set (match_dup 2) (match_dup 1))
3292 (if_then_else (gtu (match_dup 2)
3294 (label_ref (match_operand 0 "" ""))
3298 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3299 rs6000_compare_op0, rs6000_compare_op1);
3300 operands[2] = gen_reg_rtx (CCUNSmode);
3303 (define_expand "bltu"
3304 [(set (match_dup 2) (match_dup 1))
3306 (if_then_else (ltu (match_dup 2)
3308 (label_ref (match_operand 0 "" ""))
3312 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3313 rs6000_compare_op0, rs6000_compare_op1);
3314 operands[2] = gen_reg_rtx (CCUNSmode);
3317 (define_expand "bgeu"
3318 [(set (match_dup 2) (match_dup 1))
3320 (if_then_else (geu (match_dup 2)
3322 (label_ref (match_operand 0 "" ""))
3326 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3327 rs6000_compare_op0, rs6000_compare_op1);
3328 operands[2] = gen_reg_rtx (CCUNSmode);
3331 (define_expand "bleu"
3332 [(set (match_dup 2) (match_dup 1))
3334 (if_then_else (leu (match_dup 2)
3336 (label_ref (match_operand 0 "" ""))
3340 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3341 rs6000_compare_op0, rs6000_compare_op1);
3342 operands[2] = gen_reg_rtx (CCUNSmode);
3345 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
3346 ;; For SEQ, likewise, except that comparisons with zero should be done
3347 ;; with an scc insns. However, due to the order that combine see the
3348 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
3349 ;; the cases we don't want to handle.
3350 (define_expand "seq"
3351 [(set (match_dup 2) (match_dup 1))
3352 (set (match_operand:SI 0 "gpc_reg_operand" "")
3353 (eq:SI (match_dup 2) (const_int 0)))]
3356 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3357 operands[1] = gen_rtx (COMPARE, mode,
3358 rs6000_compare_op0, rs6000_compare_op1);
3359 operands[2] = gen_reg_rtx (mode);
3362 (define_expand "sne"
3363 [(set (match_dup 2) (match_dup 1))
3364 (set (match_operand:SI 0 "gpc_reg_operand" "")
3365 (ne:SI (match_dup 2) (const_int 0)))]
3368 { if (! rs6000_compare_fp_p)
3371 operands[1] = gen_rtx (COMPARE, CCFPmode,
3372 rs6000_compare_op0, rs6000_compare_op1);
3373 operands[2] = gen_reg_rtx (CCFPmode);
3376 ;; A > 0 is best done using the portable sequence, so fail in that case.
3377 (define_expand "sgt"
3378 [(set (match_dup 2) (match_dup 1))
3379 (set (match_operand:SI 0 "gpc_reg_operand" "")
3380 (gt:SI (match_dup 2) (const_int 0)))]
3383 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3385 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3388 operands[1] = gen_rtx (COMPARE, mode,
3389 rs6000_compare_op0, rs6000_compare_op1);
3390 operands[2] = gen_reg_rtx (mode);
3393 ;; A < 0 is best done in the portable way for A an integer.
3394 (define_expand "slt"
3395 [(set (match_dup 2) (match_dup 1))
3396 (set (match_operand:SI 0 "gpc_reg_operand" "")
3397 (lt:SI (match_dup 2) (const_int 0)))]
3400 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3402 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3405 operands[1] = gen_rtx (COMPARE, mode,
3406 rs6000_compare_op0, rs6000_compare_op1);
3407 operands[2] = gen_reg_rtx (mode);
3410 (define_expand "sge"
3411 [(set (match_dup 2) (match_dup 1))
3412 (set (match_operand:SI 0 "gpc_reg_operand" "")
3413 (ge:SI (match_dup 2) (const_int 0)))]
3416 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3417 operands[1] = gen_rtx (COMPARE, mode,
3418 rs6000_compare_op0, rs6000_compare_op1);
3419 operands[2] = gen_reg_rtx (mode);
3422 ;; A <= 0 is best done the portable way for A an integer.
3423 (define_expand "sle"
3424 [(set (match_dup 2) (match_dup 1))
3425 (set (match_operand:SI 0 "gpc_reg_operand" "")
3426 (le:SI (match_dup 2) (const_int 0)))]
3429 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3431 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3434 operands[1] = gen_rtx (COMPARE, mode,
3435 rs6000_compare_op0, rs6000_compare_op1);
3436 operands[2] = gen_reg_rtx (mode);
3439 (define_expand "sgtu"
3440 [(set (match_dup 2) (match_dup 1))
3441 (set (match_operand:SI 0 "gpc_reg_operand" "")
3442 (gtu:SI (match_dup 2) (const_int 0)))]
3445 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3446 rs6000_compare_op0, rs6000_compare_op1);
3447 operands[2] = gen_reg_rtx (CCUNSmode);
3450 (define_expand "sltu"
3451 [(set (match_dup 2) (match_dup 1))
3452 (set (match_operand:SI 0 "gpc_reg_operand" "")
3453 (ltu:SI (match_dup 2) (const_int 0)))]
3456 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3457 rs6000_compare_op0, rs6000_compare_op1);
3458 operands[2] = gen_reg_rtx (CCUNSmode);
3461 (define_expand "sgeu"
3462 [(set (match_dup 2) (match_dup 1))
3463 (set (match_operand:SI 0 "gpc_reg_operand" "")
3464 (geu:SI (match_dup 2) (const_int 0)))]
3467 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3468 rs6000_compare_op0, rs6000_compare_op1);
3469 operands[2] = gen_reg_rtx (CCUNSmode);
3472 (define_expand "sleu"
3473 [(set (match_dup 2) (match_dup 1))
3474 (set (match_operand:SI 0 "gpc_reg_operand" "")
3475 (leu:SI (match_dup 2) (const_int 0)))]
3478 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3479 rs6000_compare_op0, rs6000_compare_op1);
3480 operands[2] = gen_reg_rtx (CCUNSmode);
3483 ;; Here are the actual compare insns.
3485 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
3486 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
3487 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3490 [(set_attr "type" "compare")])
3492 ;; If we are comparing a register for equality with a large constant,
3493 ;; we can do this with an XOR followed by a compare. But we need a scratch
3494 ;; register for the result of the XOR.
3497 [(set (match_operand:CC 0 "cc_reg_operand" "")
3498 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
3499 (match_operand:SI 2 "non_short_cint_operand" "")))
3500 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
3501 "find_single_use (operands[0], insn, 0)
3502 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
3503 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
3504 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
3505 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
3508 /* Get the constant we are comparing against, C, and see what it looks like
3509 sign-extended to 16 bits. Then see what constant could be XOR'ed
3510 with C to get the sign-extended value. */
3512 int c = INTVAL (operands[2]);
3513 int sextc = (c << 16) >> 16;
3514 int xorv = c ^ sextc;
3516 operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
3517 operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
3521 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
3522 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
3523 (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
3526 [(set_attr "type" "compare")])
3528 ;; The following two insns don't exist as single insns, but if we provide
3529 ;; them, we can swap an add and compare, which will enable us to overlap more
3530 ;; of the required delay between a compare and branch. We generate code for
3531 ;; them by splitting.
3534 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
3535 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
3536 (match_operand:SI 2 "short_cint_operand" "i")))
3537 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3538 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3543 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
3544 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
3545 (match_operand:SI 2 "u_short_cint_operand" "i")))
3546 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3547 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3552 [(set (match_operand:CC 3 "cc_reg_operand" "")
3553 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
3554 (match_operand:SI 2 "short_cint_operand" "")))
3555 (set (match_operand:SI 0 "gpc_reg_operand" "")
3556 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3558 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
3559 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3562 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
3563 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
3564 (match_operand:SI 2 "u_short_cint_operand" "")))
3565 (set (match_operand:SI 0 "gpc_reg_operand" "")
3566 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3568 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
3569 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3572 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3573 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
3574 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3577 [(set_attr "type" "fpcompare")])
3580 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3581 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
3582 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3585 [(set_attr "type" "fpcompare")])
3587 ;; Now we have the scc insns. We can do some combinations because of the
3588 ;; way the machine works.
3590 ;; Note that this is probably faster if we can put an insn between the
3591 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
3592 ;; cases the insns below which don't use an intermediate CR field will
3595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3596 (match_operator:SI 1 "scc_comparison_operator"
3597 [(match_operand 2 "cc_reg_operand" "y")
3600 "%D1mfcr %0\;rlinm %0,%0,%J1,0x00000001"
3601 [(set_attr "length" "12")])
3604 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3605 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
3606 [(match_operand 2 "cc_reg_operand" "y")
3609 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
3610 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
3612 "%D1mfcr %3\;rlinm. %3,%3,%J1,0x00000001"
3613 [(set_attr "type" "delayed_compare")
3614 (set_attr "length" "12")])
3617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3618 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3619 [(match_operand 2 "cc_reg_operand" "y")
3621 (match_operand:SI 3 "const_int_operand" "n")))]
3625 int is_bit = ccr_bit (operands[1], 1);
3626 int put_bit = 31 - (INTVAL (operands[3]) & 31);
3629 if (is_bit >= put_bit)
3630 count = is_bit - put_bit;
3632 count = 32 - (put_bit - is_bit);
3634 operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
3635 operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3637 return \"%D1mfcr %0\;rlinm %0,%0,%4,%5,%5\";
3639 [(set_attr "length" "12")])
3642 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3644 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3645 [(match_operand 2 "cc_reg_operand" "y")
3647 (match_operand:SI 3 "const_int_operand" "n"))
3649 (set (match_operand:SI 4 "gpc_reg_operand" "=r")
3650 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
3655 int is_bit = ccr_bit (operands[1], 1);
3656 int put_bit = 31 - (INTVAL (operands[3]) & 31);
3659 if (is_bit >= put_bit)
3660 count = is_bit - put_bit;
3662 count = 32 - (put_bit - is_bit);
3664 operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
3665 operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3667 return \"%D1mfcr %4\;rlinm. %4,%4,%5,%6,%6\";
3669 [(set_attr "type" "delayed_compare")
3670 (set_attr "length" "12")])
3672 ;; If we are comparing the result of two comparisons, this can be done
3673 ;; using creqv or crxor.
3676 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
3677 (compare:CCEQ (match_operator 1 "scc_comparison_operator"
3678 [(match_operand 2 "cc_reg_operand" "y")
3680 (match_operator 3 "scc_comparison_operator"
3681 [(match_operand 4 "cc_reg_operand" "y")
3683 "REGNO (operands[2]) != REGNO (operands[4])"
3686 enum rtx_code code1, code2;
3688 code1 = GET_CODE (operands[1]);
3689 code2 = GET_CODE (operands[3]);
3691 if ((code1 == EQ || code1 == LT || code1 == GT
3692 || code1 == LTU || code1 == GTU
3693 || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
3695 (code2 == EQ || code2 == LT || code2 == GT
3696 || code2 == LTU || code2 == GTU
3697 || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
3698 return \"%C1%C3crxor %E0,%j1,%j3\";
3700 return \"%C1%C3creqv %E0,%j1,%j3\";
3702 [(set_attr "length" "12")])
3704 ;; There is a 3 cycle delay between consecutive mfcr instructions
3705 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
3708 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3709 (match_operator:SI 1 "scc_comparison_operator"
3710 [(match_operand 2 "cc_reg_operand" "y")
3712 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
3713 (match_operator:SI 4 "scc_comparison_operator"
3714 [(match_operand 5 "cc_reg_operand" "y")
3716 "REGNO (operands[2]) != REGNO (operands[5])"
3717 "%D1%D4mfcr %3\;rlinm %0,%3,%J1,0x00000001\;rlinm %3,%3,%J4,0x00000001"
3718 [(set_attr "length" "20")])
3720 ;; There are some scc insns that can be done directly, without a compare.
3721 ;; These are faster because they don't involve the communications between
3722 ;; the FXU and branch units. In fact, we will be replacing all of the
3723 ;; integer scc insns here or in the portable methods in emit_store_flag.
3725 ;; Also support (neg (scc ..)) since that construct is used to replace
3726 ;; branches, (plus (scc ..) ..) since that construct is common and
3727 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
3728 ;; cases where it is no more expensive than (neg (scc ..)).
3730 ;; Have reload force a constant into a register for the simple insns that
3731 ;; otherwise won't accept constants. We do this because it is faster than
3732 ;; the cmp/mfcr sequence we would otherwise generate.
3735 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
3736 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
3737 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
3738 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3741 xor %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0
3742 sfi %3,%1,0\;ae %0,%3,%1
3743 xoril %0,%1,%b2\;sfi %3,%0,0\;ae %0,%3,%0
3744 xoriu %0,%1,%u2\;sfi %3,%0,0\;ae %0,%3,%0
3745 sfi %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0"
3746 [(set_attr "length" "12,8,12,12,12")])
3749 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
3751 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
3752 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3754 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
3755 (eq:SI (match_dup 1) (match_dup 2)))
3756 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3759 xor %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0
3760 sfi %3,%1,0\;ae. %0,%3,%1
3761 xoril %0,%1,%b2\;sfi %3,%0,0\;ae. %0,%3,%0
3762 xoriu %0,%1,%u2\;sfi %3,%0,0\;ae. %0,%3,%0
3763 sfi %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0"
3764 [(set_attr "type" "compare")
3765 (set_attr "length" "12,8,12,12,12")])
3767 ;; We have insns of the form shown by the first define_insn below. If
3768 ;; there is something inside the comparison operation, we must split it.
3770 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3771 (plus:SI (match_operator 1 "comparison_operator"
3772 [(match_operand:SI 2 "" "")
3774 "reg_or_cint_operand" "")])
3775 (match_operand:SI 4 "gpc_reg_operand" "")))
3776 (clobber (match_operand:SI 5 "register_operand" ""))]
3777 "! gpc_reg_operand (operands[2], SImode)"
3778 [(set (match_dup 5) (match_dup 2))
3779 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
3783 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
3784 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
3785 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3786 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
3787 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3790 xor %4,%1,%2\;sfi %4,%4,0\;aze %0,%3
3791 sfi %4,%1,0\;aze %0,%3
3792 xoril %4,%1,%b2\;sfi %4,%4,0\;aze %0,%3
3793 xoriu %4,%1,%u2\;sfi %4,%4,0\;aze %0,%3
3794 sfi %4,%1,%2\;sfi %4,%4,0\;aze %0,%3"
3795 [(set_attr "length" "12,8,12,12,12")])
3798 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
3801 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
3802 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3803 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
3805 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3808 xor %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3
3809 sfi %4,%1,0\;aze. %0,%3
3810 xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %4,%3
3811 xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %4,%3
3812 sfi %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
3813 [(set_attr "type" "compare")
3814 (set_attr "length" "12,8,12,12,12")])
3817 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
3820 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
3821 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3822 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
3824 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
3825 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3826 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3829 xor %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3
3830 sfi %4,%1,0\;aze. %4,%3
3831 xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %0,%3
3832 xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %0,%3
3833 sfi %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
3834 [(set_attr "type" "compare")
3835 (set_attr "length" "12,8,12,12,12")])
3838 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
3839 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r")
3840 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
3843 xor %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0
3844 ai %0,%1,-1\;sfe %0,%0,%0
3845 xoril %0,%1,%b2\;ai %0,%0,-1\;sfe %0,%0,%0
3846 xoriu %0,%1,%u2\;ai %0,%0,-1\;sfe %0,%0,%0
3847 sfi %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0"
3848 [(set_attr "length" "12,8,12,12,12")])
3850 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
3852 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3853 (plus:SI (lshiftrt:SI
3854 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
3856 (match_operand:SI 2 "gpc_reg_operand" "r")))
3857 (clobber (match_scratch:SI 3 "=&r"))]
3859 "ai %3,%1,-1\;aze %0,%2"
3860 [(set_attr "length" "8")])
3863 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3865 (plus:SI (lshiftrt:SI
3866 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
3868 (match_operand:SI 2 "gpc_reg_operand" "r"))
3870 (clobber (match_scratch:SI 3 "=&r"))]
3872 "ai %3,%1,-1\;aze. %3,%2"
3873 [(set_attr "type" "compare")
3874 (set_attr "length" "8")])
3877 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3879 (plus:SI (lshiftrt:SI
3880 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
3882 (match_operand:SI 2 "gpc_reg_operand" "r"))
3884 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3885 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
3887 (clobber (match_scratch:SI 3 "=&r"))]
3889 "ai %3,%1,-1\;aze. %0,%2"
3890 [(set_attr "type" "compare")
3891 (set_attr "length" "8")])
3894 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3895 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3896 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
3897 (clobber (match_scratch:SI 3 "=r,X"))]
3900 doz %3,%2,%1\;sfi %0,%3,0\;ae %0,%0,%3
3901 ai %0,%1,-1\;aze %0,%0\;sri %0,%0,31"
3902 [(set_attr "length" "12")])
3905 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
3907 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3908 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3910 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3911 (le:SI (match_dup 1) (match_dup 2)))
3912 (clobber (match_scratch:SI 3 "=r,X"))]
3915 doz %3,%2,%1\;sfi %0,%3,0\;ae. %0,%0,%3
3916 ai %0,%1,-1\;aze %0,%0\;sri. %0,%0,31"
3917 [(set_attr "type" "delayed_compare,compare")
3918 (set_attr "length" "12")])
3921 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3922 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3923 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3924 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3925 (clobber (match_scratch:SI 4 "=&r,&r"))]
3928 doz %4,%2,%1\;sfi %4,%4,0\;aze %0,%3
3929 srai %4,%1,31\;sf %4,%1,%4\;aze %0,%3"
3930 [(set_attr "length" "12")])
3933 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3935 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3936 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3937 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3939 (clobber (match_scratch:SI 4 "=&r,&r"))]
3942 doz %4,%2,%1\;sfi %4,%4,0\;aze. %4,%3
3943 srai %4,%1,31\;sf %4,%1,%4\;aze. %4,%3"
3944 [(set_attr "type" "compare")
3945 (set_attr "length" "12")])
3948 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
3950 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3951 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3952 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3954 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3955 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3956 (clobber (match_scratch:SI 4 "=&r,&r"))]
3959 doz %4,%2,%1\;sfi %4,%4,0\;aze. %0,%3
3960 srai %4,%1,31\;sf %4,%1,%4\;aze. %0,%3"
3961 [(set_attr "type" "compare")
3962 (set_attr "length" "12")])
3965 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3966 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3967 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
3970 doz %0,%2,%1\;ai %0,%0,-1\;sfe %0,%0,%0
3971 ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31"
3972 [(set_attr "length" "12")])
3975 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3976 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3977 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3979 "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0"
3980 [(set_attr "length" "12")])
3983 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3985 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3986 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3988 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3989 (leu:SI (match_dup 1) (match_dup 2)))]
3991 "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0"
3992 [(set_attr "type" "compare")
3993 (set_attr "length" "12")])
3996 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3997 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3998 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3999 (match_operand:SI 3 "gpc_reg_operand" "r")))
4000 (clobber (match_scratch:SI 4 "=&r"))]
4002 "sf%I2 %4,%1,%2\;aze %0,%3"
4003 [(set_attr "length" "8")])
4006 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4008 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4009 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4010 (match_operand:SI 3 "gpc_reg_operand" "r"))
4012 (clobber (match_scratch:SI 4 "=&r"))]
4014 "sf%I2 %4,%1,%2\;aze. %4,%3"
4015 [(set_attr "type" "compare")
4016 (set_attr "length" "8")])
4019 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4021 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4022 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4023 (match_operand:SI 3 "gpc_reg_operand" "r"))
4025 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
4026 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4027 (clobber (match_scratch:SI 4 "=&r"))]
4029 "sf%I2 %4,%1,%2\;aze. %0,%3"
4030 [(set_attr "type" "compare")
4031 (set_attr "length" "8")])
4034 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4035 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4036 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4038 "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0"
4039 [(set_attr "length" "12")])
4042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4044 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4045 (match_operand:SI 2 "reg_or_short_operand" "rI")))
4046 (match_operand:SI 3 "gpc_reg_operand" "r")))
4047 (clobber (match_scratch:SI 4 "=&r"))]
4049 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4"
4050 [(set_attr "length" "12")])
4053 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4056 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4057 (match_operand:SI 2 "reg_or_short_operand" "rI")))
4058 (match_operand:SI 3 "gpc_reg_operand" "r"))
4060 (clobber (match_scratch:SI 4 "=&r"))]
4062 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %4,%3,%4"
4063 [(set_attr "type" "compare")
4064 (set_attr "length" "12")])
4067 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4070 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4071 (match_operand:SI 2 "reg_or_short_operand" "rI")))
4072 (match_operand:SI 3 "gpc_reg_operand" "r"))
4074 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
4075 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
4076 (clobber (match_scratch:SI 4 "=&r"))]
4078 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %0,%3,%4"
4079 [(set_attr "type" "compare")
4080 (set_attr "length" "12")])
4083 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4084 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4085 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
4087 "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31"
4088 [(set_attr "length" "12")])
4091 [(set (match_operand:SI 3 "cc_reg_operand" "=x")
4093 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4094 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4096 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
4097 (lt:SI (match_dup 1) (match_dup 2)))]
4099 "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31"
4100 [(set_attr "type" "delayed_compare")
4101 (set_attr "length" "12")])
4104 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4105 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4106 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4107 (match_operand:SI 3 "gpc_reg_operand" "r")))
4108 (clobber (match_scratch:SI 4 "=&r"))]
4110 "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3"
4111 [(set_attr "length" "12")])
4114 [(set (match_operand:SI 0 "cc_reg_operand" "=x")
4116 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4117 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4118 (match_operand:SI 3 "gpc_reg_operand" "r"))
4120 (clobber (match_scratch:SI 4 "=&r"))]
4122 "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %4,%3"
4123 [(set_attr "type" "compare")
4124 (set_attr "length" "12")])
4127 [(set (match_operand:SI 5 "cc_reg_operand" "=x")
4129 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4130 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4131 (match_operand:SI 3 "gpc_reg_operand" "r"))
4133 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
4134 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4135 (clobber (match_scratch:SI 4 "=&r"))]
4137 "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %0,%3"
4138 [(set_attr "type" "compare")
4139 (set_attr "length" "12")])
4142 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4143 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4144 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4146 "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31"
4147 [(set_attr "length" "12")])
4150 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4151 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4152 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
4155 sf %0,%2,%1\;sfe %0,%0,%0\;neg %0,%0
4156 ai %0,%1,%n2\;sfe %0,%0,%0\;neg %0,%0"
4157 [(set_attr "length" "12")])
4160 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
4162 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4163 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4165 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4166 (ltu:SI (match_dup 1) (match_dup 2)))]
4169 sf %0,%2,%1\;sfe %0,%0,%0\;neg. %0,%0
4170 ai %0,%1,%n2\;sfe %0,%0,%0\;neg. %0,%0"
4171 [(set_attr "type" "compare")
4172 (set_attr "length" "12")])
4175 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4176 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4177 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
4178 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
4179 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
4182 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
4183 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
4184 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
4185 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3"
4186 [(set_attr "length" "12")])
4189 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4191 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4192 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4193 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
4195 (clobber (match_scratch:SI 4 "=&r,&r"))]
4198 sf %4,%2,%1\;sfe %4,%4,%4\;sf. %4,%4,%3
4199 ai %4,%1,%n2\;sfe %4,%4,%4\;sf. %4,%4,%3"
4200 [(set_attr "type" "compare")
4201 (set_attr "length" "12")])
4204 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4206 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4207 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4208 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
4210 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4211 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4212 (clobber (match_scratch:SI 4 "=&r,&r"))]
4215 sf %4,%2,%1\;sfe %4,%4,%4\;sf. %0,%4,%3
4216 ai %4,%1,%n2\;sfe %4,%4,%4\;sf. %0,%4,%3"
4217 [(set_attr "type" "compare")
4218 (set_attr "length" "12")])
4221 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4222 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4223 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
4226 sf %0,%2,%1\;sfe %0,%0,%0
4227 ai %0,%1,%n2\;sfe %0,%0,%0"
4228 [(set_attr "length" "8")])
4231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4232 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4233 (match_operand:SI 2 "reg_or_short_operand" "rI")))
4234 (clobber (match_scratch:SI 3 "=r"))]
4236 "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae %0,%0,%3"
4237 [(set_attr "length" "12")])
4240 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4242 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4243 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4245 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
4246 (ge:SI (match_dup 1) (match_dup 2)))
4247 (clobber (match_scratch:SI 3 "=r"))]
4249 "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae. %0,%0,%3"
4250 [(set_attr "type" "compare")
4251 (set_attr "length" "12")])
4254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4255 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4256 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4257 (match_operand:SI 3 "gpc_reg_operand" "r")))
4258 (clobber (match_scratch:SI 4 "=&r"))]
4260 "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3"
4261 [(set_attr "length" "12")])
4264 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4266 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4267 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4268 (match_operand:SI 3 "gpc_reg_operand" "r"))
4270 (clobber (match_scratch:SI 4 "=&r"))]
4272 "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
4273 [(set_attr "type" "compare")
4274 (set_attr "length" "12")])
4277 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4279 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4280 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4281 (match_operand:SI 3 "gpc_reg_operand" "r"))
4283 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
4284 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4285 (clobber (match_scratch:SI 4 "=&r"))]
4287 "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
4288 [(set_attr "type" "compare")
4289 (set_attr "length" "12")])
4292 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4293 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4294 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4296 "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0"
4297 [(set_attr "length" "12")])
4299 ;; This is (and (neg (ge X (const_int 0))) Y).
4301 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4304 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
4306 (match_operand:SI 2 "gpc_reg_operand" "r")))
4307 (clobber (match_scratch:SI 3 "=&r"))]
4309 "srai %3,%1,31\;andc %0,%2,%3"
4310 [(set_attr "length" "8")])
4313 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4317 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
4319 (match_operand:SI 2 "gpc_reg_operand" "r"))
4321 (clobber (match_scratch:SI 3 "=&r"))]
4323 "srai %3,%1,31\;andc. %3,%2,%3"
4324 [(set_attr "type" "compare")
4325 (set_attr "length" "8")])
4328 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4332 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
4334 (match_operand:SI 2 "gpc_reg_operand" "r"))
4336 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
4337 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
4340 (clobber (match_scratch:SI 3 "=&r"))]
4342 "srai %3,%1,31\;andc. %0,%2,%3"
4343 [(set_attr "type" "compare")
4344 (set_attr "length" "8")])
4347 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4348 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4349 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
4352 sf %0,%2,%1\;cal %0,0(0)\;ae %0,%0,%0
4353 ai %0,%1,%n2\;cal %0,0(0)\;ae %0,%0,%0"
4354 [(set_attr "length" "12")])
4357 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
4359 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4360 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4362 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4363 (geu:SI (match_dup 1) (match_dup 2)))]
4366 sf %0,%2,%1\;cal %0,0(0)\;ae. %0,%0,%0
4367 ai %0,%1,%n2\;cal %0,0(0)\;ae. %0,%0,%0"
4368 [(set_attr "type" "compare")
4369 (set_attr "length" "12")])
4372 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4373 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4374 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4375 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
4376 (clobber (match_scratch:SI 4 "=&r,&r"))]
4379 sf %4,%2,%1\;aze %0,%3
4380 ai %4,%1,%n2\;aze %0,%3"
4381 [(set_attr "length" "8")])
4384 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4386 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4387 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4388 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
4390 (clobber (match_scratch:SI 4 "=&r,&r"))]
4393 sf %4,%2,%1\;aze. %4,%3
4394 ai %4,%1,%n2\;aze. %4,%3"
4395 [(set_attr "type" "compare")
4396 (set_attr "length" "8")])
4399 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4401 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4402 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4403 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
4405 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4406 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4407 (clobber (match_scratch:SI 4 "=&r,&r"))]
4410 sf %4,%2,%1\;aze. %0,%3
4411 ai %4,%1,%n2\;aze. %4,%3"
4412 [(set_attr "type" "compare")
4413 (set_attr "length" "8")])
4416 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4417 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4418 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
4421 sf %0,%2,%1\;sfe %0,%0,%0\;nand %0,%0,%0
4422 sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0"
4423 [(set_attr "length" "12")])
4426 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4428 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4429 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4430 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
4431 (clobber (match_scratch:SI 4 "=&r,&r"))]
4434 sf %4,%2,%1\;sfe %4,%4,%4\;andc %0,%3,%4
4435 ai %4,%1,%n2\;sfe %4,%4,%4\;andc %0,%3,%4"
4436 [(set_attr "length" "12")])
4439 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4442 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4443 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4444 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
4446 (clobber (match_scratch:SI 4 "=&r,&r"))]
4449 sf %4,%2,%1\;sfe %4,%4,%4\;andc. %4,%3,%4
4450 ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %4,%3,%4"
4451 [(set_attr "type" "compare")
4452 (set_attr "length" "12")])
4455 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4458 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4459 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4460 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
4462 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4463 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
4464 (clobber (match_scratch:SI 4 "=&r,&r"))]
4467 sf %4,%2,%1\;sfe %4,%4,%4\;andc. %0,%3,%4
4468 ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %0,%3,%4"
4469 [(set_attr "type" "compare")
4470 (set_attr "length" "12")])
4473 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4474 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4477 "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31"
4478 [(set_attr "length" "12")])
4481 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4483 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4486 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
4487 (gt:SI (match_dup 1) (const_int 0)))]
4489 "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31"
4490 [(set_attr "type" "delayed_compare")
4491 (set_attr "length" "12")])
4494 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4495 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4496 (match_operand:SI 2 "reg_or_short_operand" "r")))]
4498 "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31"
4499 [(set_attr "length" "12")])
4502 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4504 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4505 (match_operand:SI 2 "reg_or_short_operand" "r"))
4507 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
4508 (gt:SI (match_dup 1) (match_dup 2)))]
4510 "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31"
4511 [(set_attr "type" "delayed_compare")
4512 (set_attr "length" "12")])
4515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4516 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4518 (match_operand:SI 2 "gpc_reg_operand" "r")))
4519 (clobber (match_scratch:SI 3 "=&r"))]
4521 "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2"
4522 [(set_attr "length" "12")])
4525 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4527 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4529 (match_operand:SI 2 "gpc_reg_operand" "r"))
4531 (clobber (match_scratch:SI 3 "=&r"))]
4533 "a %3,%1,%1\;sfe %3,%1,%3\;aze. %0,%2"
4534 [(set_attr "type" "compare")
4535 (set_attr "length" "12")])
4538 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4540 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4542 (match_operand:SI 2 "gpc_reg_operand" "r"))
4544 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
4545 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
4546 (clobber (match_scratch:SI 3 "=&r"))]
4548 "a %3,%1,%1\;sfe %3,%1,%3\;aze. %3,%2"
4549 [(set_attr "type" "compare")
4550 (set_attr "length" "12")])
4553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4554 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4555 (match_operand:SI 2 "reg_or_short_operand" "r"))
4556 (match_operand:SI 3 "gpc_reg_operand" "r")))
4557 (clobber (match_scratch:SI 4 "=&r"))]
4559 "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3"
4560 [(set_attr "length" "12")])
4563 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4565 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4566 (match_operand:SI 2 "reg_or_short_operand" "r"))
4567 (match_operand:SI 3 "gpc_reg_operand" "r"))
4569 (clobber (match_scratch:SI 4 "=&r"))]
4571 "doz %4,%2,%1\;ai %4,%4,-1\;aze. %4,%3"
4572 [(set_attr "type" "compare")
4573 (set_attr "length" "12")])
4576 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4578 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4579 (match_operand:SI 2 "reg_or_short_operand" "r"))
4580 (match_operand:SI 3 "gpc_reg_operand" "r"))
4582 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
4583 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4584 (clobber (match_scratch:SI 4 "=&r"))]
4586 "doz %4,%2,%1\;ai %4,%4,-1\;aze. %0,%3"
4587 [(set_attr "type" "compare")
4588 (set_attr "length" "12")])
4591 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4592 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4595 "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31"
4596 [(set_attr "length" "12")])
4599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4600 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4601 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
4603 "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31"
4604 [(set_attr "length" "12")])
4607 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4608 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4609 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
4611 "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0"
4612 [(set_attr "length" "12")])
4615 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4617 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4618 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4620 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
4621 (gtu:SI (match_dup 1) (match_dup 2)))]
4623 "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0"
4624 [(set_attr "type" "compare")
4625 (set_attr "length" "12")])
4628 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4629 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4630 (match_operand:SI 2 "reg_or_short_operand" "I,r,rI"))
4631 (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))
4632 (clobber (match_scratch:SI 4 "=&r,&r,&r"))]
4635 ai %4,%1,%k2\;aze %0,%3
4636 sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
4637 sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3"
4638 [(set_attr "length" "8,12,12")])
4641 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4643 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4644 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
4645 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
4647 (clobber (match_scratch:SI 4 "=&r,&r"))]
4650 ai %4,%1,%k2\;aze. %0,%3
4651 sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf. %0,%4,%3"
4652 [(set_attr "type" "compare")
4653 (set_attr "length" "8,12")])
4656 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4658 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4659 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
4660 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
4662 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4663 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4664 (clobber (match_scratch:SI 4 "=&r,&r"))]
4667 ai %4,%1,%k2\;aze. %0,%3
4668 sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf. %0,%4,%3"
4669 [(set_attr "type" "compare")
4670 (set_attr "length" "8,12")])
4673 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4674 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4675 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4677 "sf%I2 %0,%1,%2\;sfe %0,%0,%0"
4678 [(set_attr "length" "8")])
4680 ;; Define both directions of branch and return. If we need a reload
4681 ;; register, we'd rather use CR0 since it is much easier to copy a
4682 ;; register CC value to there.
4686 (if_then_else (match_operator 1 "branch_comparison_operator"
4688 "cc_reg_operand" "x,?y")
4690 (label_ref (match_operand 0 "" ""))
4695 if (get_attr_length (insn) == 8)
4696 return \"%C1bc %t1,%j1,%l0\";
4698 return \"%C1bc %T1,%j1,$+8\;b %l0\";
4700 [(set_attr "type" "branch")])
4705 (if_then_else (match_operator 0 "branch_comparison_operator"
4707 "cc_reg_operand" "x,?y")
4713 [(set_attr "length" "8")])
4717 (if_then_else (match_operator 1 "branch_comparison_operator"
4719 "cc_reg_operand" "x,?y")
4722 (label_ref (match_operand 0 "" ""))))]
4726 if (get_attr_length (insn) == 8)
4727 return \"%C1bc %T1,%j1,%l0\";
4729 return \"%C1bc %t1,%j1,$+8\;b %l0\";
4731 [(set_attr "type" "branch")])
4735 (if_then_else (match_operator 0 "branch_comparison_operator"
4737 "cc_reg_operand" "x,?y")
4743 [(set_attr "length" "8")])
4745 ;; Unconditional branch and return.
4749 (label_ref (match_operand 0 "" "")))]
4753 (define_insn "return"
4758 (define_insn "indirect_jump"
4759 [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
4765 ;; Table jump for switch statements:
4766 (define_expand "tablejump"
4768 (plus:SI (match_operand:SI 0 "" "")
4770 (parallel [(set (pc) (match_dup 3))
4771 (use (label_ref (match_operand 1 "" "")))])]
4774 { operands[0] = force_reg (SImode, operands[0]);
4775 operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
4776 operands[3] = gen_reg_rtx (SImode);
4781 (match_operand:SI 0 "register_operand" "c,l"))
4782 (use (label_ref (match_operand 1 "" "")))]
4793 ;; Define the subtract-one-and-jump insns, starting with the template
4794 ;; so loop.c knows what to generate.
4796 (define_expand "decrement_and_branchsi"
4797 [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "c")
4799 (label_ref (match_operand 1 "" ""))
4801 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])]
4805 ;; We need to be able to do this for any operand, including MEM, or we
4806 ;; will cause reload to blow up since we don't allow output reloads on
4810 (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r")
4812 (label_ref (match_operand 2 "" ""))
4814 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4815 (plus:SI (match_dup 1) (const_int -1)))
4816 (clobber (match_scratch:CC 3 "=X,&x,&x"))
4817 (clobber (match_scratch:SI 4 "=X,X,r"))]
4821 if (which_alternative == 1)
4823 else if (get_attr_length (insn) == 8)
4826 return \"bdz $+8\;b %l2\";
4828 [(set_attr "type" "branch")])
4830 ;; Similar, but we can use GE since we have a REG_NONNEG.
4833 (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r")
4835 (label_ref (match_operand 2 "" ""))
4837 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4838 (plus:SI (match_dup 1) (const_int -1)))
4839 (clobber (match_scratch:CC 3 "=X,&x,&X"))
4840 (clobber (match_scratch:SI 4 "=X,X,r"))]
4841 "find_reg_note (insn, REG_NONNEG, 0)"
4844 if (which_alternative == 1)
4846 else if (get_attr_length (insn) == 8)
4849 return \"bdz $+8\;b %l2\";
4851 [(set_attr "type" "branch")])
4855 (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r")
4857 (label_ref (match_operand 2 "" ""))
4859 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4860 (plus:SI (match_dup 1) (const_int -1)))
4861 (clobber (match_scratch:CC 3 "=X,&x,&x"))
4862 (clobber (match_scratch:SI 4 "=X,X,r"))]
4866 if (which_alternative == 1)
4868 else if (get_attr_length (insn) == 8)
4871 return \"bdn $+8\;b %l2\";
4873 [(set_attr "type" "branch")])
4877 (if_then_else (match_operator 2 "comparison_operator"
4878 [(match_operand:SI 1 "gpc_reg_operand" "")
4880 (match_operand 5 "" "")
4881 (match_operand 6 "" "")))
4882 (set (match_operand:SI 0 "gpc_reg_operand" "")
4883 (plus:SI (match_dup 1) (const_int -1)))
4884 (clobber (match_scratch:CC 3 ""))
4885 (clobber (match_scratch:SI 4 ""))]
4887 [(parallel [(set (match_dup 3)
4888 (compare:CC (plus:SI (match_dup 1) (const_int -1))
4890 (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
4891 (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4893 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4898 (if_then_else (match_operator 2 "comparison_operator"
4899 [(match_operand:SI 1 "gpc_reg_operand" "")
4901 (match_operand 5 "" "")
4902 (match_operand 6 "" "")))
4903 (set (match_operand:SI 0 "general_operand" "")
4904 (plus:SI (match_dup 1) (const_int -1)))
4905 (clobber (match_scratch:CC 3 ""))
4906 (clobber (match_scratch:SI 4 ""))]
4907 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
4908 [(parallel [(set (match_dup 3)
4909 (compare:CC (plus:SI (match_dup 1) (const_int -1))
4911 (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))])
4912 (set (match_dup 0) (match_dup 4))
4913 (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4915 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],