1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_EQ 31) ; move_from_CR_eq_bit
57 ;; UNSPEC_VOLATILE usage
62 (UNSPECV_EH_RR 9) ; eh_reg_restore
65 ;; Define an insn type attribute. This is used in function unit delay
67 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
68 (const_string "integer"))
71 ; '(pc)' in the following doesn't include the instruction itself; it is
72 ; calculated as if the instruction had zero size.
73 (define_attr "length" ""
74 (if_then_else (eq_attr "type" "branch")
75 (if_then_else (and (ge (minus (match_dup 0) (pc))
77 (lt (minus (match_dup 0) (pc))
83 ;; Processor type -- this attribute must exactly match the processor_type
84 ;; enumeration in rs6000.h.
86 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
87 (const (symbol_ref "rs6000_cpu_attr")))
89 (automata_option "ndfa")
102 (include "power4.md")
103 (include "power5.md")
104 (include "darwin.md")
107 ;; This mode macro allows :P to be used for patterns that operate on
108 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
109 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
111 ;; Start with fixed-point load and store insns. Here we put only the more
112 ;; complex forms. Basic data transfer is done later.
114 (define_expand "zero_extendqidi2"
115 [(set (match_operand:DI 0 "gpc_reg_operand" "")
116 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
121 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
122 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
127 [(set_attr "type" "load,*")])
130 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
131 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
133 (clobber (match_scratch:DI 2 "=r,r"))]
138 [(set_attr "type" "compare")
139 (set_attr "length" "4,8")])
142 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
143 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
145 (clobber (match_scratch:DI 2 ""))]
146 "TARGET_POWERPC64 && reload_completed"
148 (zero_extend:DI (match_dup 1)))
150 (compare:CC (match_dup 2)
155 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
156 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
158 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
159 (zero_extend:DI (match_dup 1)))]
164 [(set_attr "type" "compare")
165 (set_attr "length" "4,8")])
168 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
169 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
171 (set (match_operand:DI 0 "gpc_reg_operand" "")
172 (zero_extend:DI (match_dup 1)))]
173 "TARGET_POWERPC64 && reload_completed"
175 (zero_extend:DI (match_dup 1)))
177 (compare:CC (match_dup 0)
181 (define_insn "extendqidi2"
182 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
183 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
189 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
191 (clobber (match_scratch:DI 2 "=r,r"))]
196 [(set_attr "type" "compare")
197 (set_attr "length" "4,8")])
200 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
201 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
203 (clobber (match_scratch:DI 2 ""))]
204 "TARGET_POWERPC64 && reload_completed"
206 (sign_extend:DI (match_dup 1)))
208 (compare:CC (match_dup 2)
213 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
214 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
216 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
217 (sign_extend:DI (match_dup 1)))]
222 [(set_attr "type" "compare")
223 (set_attr "length" "4,8")])
226 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
227 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
229 (set (match_operand:DI 0 "gpc_reg_operand" "")
230 (sign_extend:DI (match_dup 1)))]
231 "TARGET_POWERPC64 && reload_completed"
233 (sign_extend:DI (match_dup 1)))
235 (compare:CC (match_dup 0)
239 (define_expand "zero_extendhidi2"
240 [(set (match_operand:DI 0 "gpc_reg_operand" "")
241 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
246 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
247 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
252 [(set_attr "type" "load,*")])
255 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
256 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
258 (clobber (match_scratch:DI 2 "=r,r"))]
263 [(set_attr "type" "compare")
264 (set_attr "length" "4,8")])
267 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
268 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
270 (clobber (match_scratch:DI 2 ""))]
271 "TARGET_POWERPC64 && reload_completed"
273 (zero_extend:DI (match_dup 1)))
275 (compare:CC (match_dup 2)
280 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
281 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
283 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
284 (zero_extend:DI (match_dup 1)))]
289 [(set_attr "type" "compare")
290 (set_attr "length" "4,8")])
293 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
294 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
296 (set (match_operand:DI 0 "gpc_reg_operand" "")
297 (zero_extend:DI (match_dup 1)))]
298 "TARGET_POWERPC64 && reload_completed"
300 (zero_extend:DI (match_dup 1)))
302 (compare:CC (match_dup 0)
306 (define_expand "extendhidi2"
307 [(set (match_operand:DI 0 "gpc_reg_operand" "")
308 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
313 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
314 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
319 [(set_attr "type" "load_ext,*")])
322 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
323 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
325 (clobber (match_scratch:DI 2 "=r,r"))]
330 [(set_attr "type" "compare")
331 (set_attr "length" "4,8")])
334 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
335 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
337 (clobber (match_scratch:DI 2 ""))]
338 "TARGET_POWERPC64 && reload_completed"
340 (sign_extend:DI (match_dup 1)))
342 (compare:CC (match_dup 2)
347 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
348 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
350 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
351 (sign_extend:DI (match_dup 1)))]
356 [(set_attr "type" "compare")
357 (set_attr "length" "4,8")])
360 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
361 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
363 (set (match_operand:DI 0 "gpc_reg_operand" "")
364 (sign_extend:DI (match_dup 1)))]
365 "TARGET_POWERPC64 && reload_completed"
367 (sign_extend:DI (match_dup 1)))
369 (compare:CC (match_dup 0)
373 (define_expand "zero_extendsidi2"
374 [(set (match_operand:DI 0 "gpc_reg_operand" "")
375 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
380 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
381 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
386 [(set_attr "type" "load,*")])
389 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
390 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
392 (clobber (match_scratch:DI 2 "=r,r"))]
397 [(set_attr "type" "compare")
398 (set_attr "length" "4,8")])
401 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
402 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
404 (clobber (match_scratch:DI 2 ""))]
405 "TARGET_POWERPC64 && reload_completed"
407 (zero_extend:DI (match_dup 1)))
409 (compare:CC (match_dup 2)
414 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
415 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
417 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
418 (zero_extend:DI (match_dup 1)))]
423 [(set_attr "type" "compare")
424 (set_attr "length" "4,8")])
427 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
428 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
430 (set (match_operand:DI 0 "gpc_reg_operand" "")
431 (zero_extend:DI (match_dup 1)))]
432 "TARGET_POWERPC64 && reload_completed"
434 (zero_extend:DI (match_dup 1)))
436 (compare:CC (match_dup 0)
440 (define_expand "extendsidi2"
441 [(set (match_operand:DI 0 "gpc_reg_operand" "")
442 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
447 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
448 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
453 [(set_attr "type" "load_ext,*")])
456 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
457 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
459 (clobber (match_scratch:DI 2 "=r,r"))]
464 [(set_attr "type" "compare")
465 (set_attr "length" "4,8")])
468 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
469 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
471 (clobber (match_scratch:DI 2 ""))]
472 "TARGET_POWERPC64 && reload_completed"
474 (sign_extend:DI (match_dup 1)))
476 (compare:CC (match_dup 2)
481 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
482 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
484 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
485 (sign_extend:DI (match_dup 1)))]
490 [(set_attr "type" "compare")
491 (set_attr "length" "4,8")])
494 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
495 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
497 (set (match_operand:DI 0 "gpc_reg_operand" "")
498 (sign_extend:DI (match_dup 1)))]
499 "TARGET_POWERPC64 && reload_completed"
501 (sign_extend:DI (match_dup 1)))
503 (compare:CC (match_dup 0)
507 (define_expand "zero_extendqisi2"
508 [(set (match_operand:SI 0 "gpc_reg_operand" "")
509 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
515 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
519 {rlinm|rlwinm} %0,%1,0,0xff"
520 [(set_attr "type" "load,*")])
523 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
524 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
526 (clobber (match_scratch:SI 2 "=r,r"))]
529 {andil.|andi.} %2,%1,0xff
531 [(set_attr "type" "compare")
532 (set_attr "length" "4,8")])
535 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
536 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
538 (clobber (match_scratch:SI 2 ""))]
541 (zero_extend:SI (match_dup 1)))
543 (compare:CC (match_dup 2)
548 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
549 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
551 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
552 (zero_extend:SI (match_dup 1)))]
555 {andil.|andi.} %0,%1,0xff
557 [(set_attr "type" "compare")
558 (set_attr "length" "4,8")])
561 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
562 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
564 (set (match_operand:SI 0 "gpc_reg_operand" "")
565 (zero_extend:SI (match_dup 1)))]
568 (zero_extend:SI (match_dup 1)))
570 (compare:CC (match_dup 0)
574 (define_expand "extendqisi2"
575 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
576 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
581 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
582 else if (TARGET_POWER)
583 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
585 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
589 (define_insn "extendqisi2_ppc"
590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
591 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
596 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
597 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
599 (clobber (match_scratch:SI 2 "=r,r"))]
604 [(set_attr "type" "compare")
605 (set_attr "length" "4,8")])
608 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
609 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
611 (clobber (match_scratch:SI 2 ""))]
612 "TARGET_POWERPC && reload_completed"
614 (sign_extend:SI (match_dup 1)))
616 (compare:CC (match_dup 2)
621 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
622 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
624 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
625 (sign_extend:SI (match_dup 1)))]
630 [(set_attr "type" "compare")
631 (set_attr "length" "4,8")])
634 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
635 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
637 (set (match_operand:SI 0 "gpc_reg_operand" "")
638 (sign_extend:SI (match_dup 1)))]
639 "TARGET_POWERPC && reload_completed"
641 (sign_extend:SI (match_dup 1)))
643 (compare:CC (match_dup 0)
647 (define_expand "extendqisi2_power"
648 [(parallel [(set (match_dup 2)
649 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
651 (clobber (scratch:SI))])
652 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
653 (ashiftrt:SI (match_dup 2)
655 (clobber (scratch:SI))])]
658 { operands[1] = gen_lowpart (SImode, operands[1]);
659 operands[2] = gen_reg_rtx (SImode); }")
661 (define_expand "extendqisi2_no_power"
663 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
665 (set (match_operand:SI 0 "gpc_reg_operand" "")
666 (ashiftrt:SI (match_dup 2)
668 "! TARGET_POWER && ! TARGET_POWERPC"
670 { operands[1] = gen_lowpart (SImode, operands[1]);
671 operands[2] = gen_reg_rtx (SImode); }")
673 (define_expand "zero_extendqihi2"
674 [(set (match_operand:HI 0 "gpc_reg_operand" "")
675 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
680 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
681 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
685 {rlinm|rlwinm} %0,%1,0,0xff"
686 [(set_attr "type" "load,*")])
689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
690 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
692 (clobber (match_scratch:HI 2 "=r,r"))]
695 {andil.|andi.} %2,%1,0xff
697 [(set_attr "type" "compare")
698 (set_attr "length" "4,8")])
701 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
702 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
704 (clobber (match_scratch:HI 2 ""))]
707 (zero_extend:HI (match_dup 1)))
709 (compare:CC (match_dup 2)
714 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
715 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
717 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
718 (zero_extend:HI (match_dup 1)))]
721 {andil.|andi.} %0,%1,0xff
723 [(set_attr "type" "compare")
724 (set_attr "length" "4,8")])
727 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
728 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
730 (set (match_operand:HI 0 "gpc_reg_operand" "")
731 (zero_extend:HI (match_dup 1)))]
734 (zero_extend:HI (match_dup 1)))
736 (compare:CC (match_dup 0)
740 (define_expand "extendqihi2"
741 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
742 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
747 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
748 else if (TARGET_POWER)
749 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
751 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
755 (define_insn "extendqihi2_ppc"
756 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
757 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
762 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
763 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
765 (clobber (match_scratch:HI 2 "=r,r"))]
770 [(set_attr "type" "compare")
771 (set_attr "length" "4,8")])
774 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
775 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
777 (clobber (match_scratch:HI 2 ""))]
778 "TARGET_POWERPC && reload_completed"
780 (sign_extend:HI (match_dup 1)))
782 (compare:CC (match_dup 2)
787 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
788 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
790 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
791 (sign_extend:HI (match_dup 1)))]
796 [(set_attr "type" "compare")
797 (set_attr "length" "4,8")])
800 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
801 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
803 (set (match_operand:HI 0 "gpc_reg_operand" "")
804 (sign_extend:HI (match_dup 1)))]
805 "TARGET_POWERPC && reload_completed"
807 (sign_extend:HI (match_dup 1)))
809 (compare:CC (match_dup 0)
813 (define_expand "extendqihi2_power"
814 [(parallel [(set (match_dup 2)
815 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
817 (clobber (scratch:SI))])
818 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
819 (ashiftrt:SI (match_dup 2)
821 (clobber (scratch:SI))])]
824 { operands[0] = gen_lowpart (SImode, operands[0]);
825 operands[1] = gen_lowpart (SImode, operands[1]);
826 operands[2] = gen_reg_rtx (SImode); }")
828 (define_expand "extendqihi2_no_power"
830 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
832 (set (match_operand:HI 0 "gpc_reg_operand" "")
833 (ashiftrt:SI (match_dup 2)
835 "! TARGET_POWER && ! TARGET_POWERPC"
837 { operands[0] = gen_lowpart (SImode, operands[0]);
838 operands[1] = gen_lowpart (SImode, operands[1]);
839 operands[2] = gen_reg_rtx (SImode); }")
841 (define_expand "zero_extendhisi2"
842 [(set (match_operand:SI 0 "gpc_reg_operand" "")
843 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
848 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
849 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
853 {rlinm|rlwinm} %0,%1,0,0xffff"
854 [(set_attr "type" "load,*")])
857 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
858 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
860 (clobber (match_scratch:SI 2 "=r,r"))]
863 {andil.|andi.} %2,%1,0xffff
865 [(set_attr "type" "compare")
866 (set_attr "length" "4,8")])
869 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
870 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
872 (clobber (match_scratch:SI 2 ""))]
875 (zero_extend:SI (match_dup 1)))
877 (compare:CC (match_dup 2)
882 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
883 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
885 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
886 (zero_extend:SI (match_dup 1)))]
889 {andil.|andi.} %0,%1,0xffff
891 [(set_attr "type" "compare")
892 (set_attr "length" "4,8")])
895 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
896 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
898 (set (match_operand:SI 0 "gpc_reg_operand" "")
899 (zero_extend:SI (match_dup 1)))]
902 (zero_extend:SI (match_dup 1)))
904 (compare:CC (match_dup 0)
908 (define_expand "extendhisi2"
909 [(set (match_operand:SI 0 "gpc_reg_operand" "")
910 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
915 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
916 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
921 [(set_attr "type" "load_ext,*")])
924 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
925 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
927 (clobber (match_scratch:SI 2 "=r,r"))]
932 [(set_attr "type" "compare")
933 (set_attr "length" "4,8")])
936 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
937 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
939 (clobber (match_scratch:SI 2 ""))]
942 (sign_extend:SI (match_dup 1)))
944 (compare:CC (match_dup 2)
949 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
950 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
952 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
953 (sign_extend:SI (match_dup 1)))]
958 [(set_attr "type" "compare")
959 (set_attr "length" "4,8")])
962 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
963 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
965 (set (match_operand:SI 0 "gpc_reg_operand" "")
966 (sign_extend:SI (match_dup 1)))]
969 (sign_extend:SI (match_dup 1)))
971 (compare:CC (match_dup 0)
975 ;; Fixed-point arithmetic insns.
977 ;; Discourage ai/addic because of carry but provide it in an alternative
978 ;; allowing register zero as source.
979 (define_expand "addsi3"
980 [(set (match_operand:SI 0 "gpc_reg_operand" "")
981 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
982 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
986 if (GET_CODE (operands[2]) == CONST_INT
987 && ! add_operand (operands[2], SImode))
989 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
990 ? operands[0] : gen_reg_rtx (SImode));
992 HOST_WIDE_INT val = INTVAL (operands[2]);
993 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
994 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
996 /* The ordering here is important for the prolog expander.
997 When space is allocated from the stack, adding 'low' first may
998 produce a temporary deallocation (which would be bad). */
999 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
1000 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1005 (define_insn "*addsi3_internal1"
1006 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1007 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1008 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1012 {cal %0,%2(%1)|addi %0,%1,%2}
1014 {cau|addis} %0,%1,%v2"
1015 [(set_attr "length" "4,4,4,4")])
1017 (define_insn "addsi3_high"
1018 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1019 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1020 (high:SI (match_operand 2 "" ""))))]
1021 "TARGET_MACHO && !TARGET_64BIT"
1022 "{cau|addis} %0,%1,ha16(%2)"
1023 [(set_attr "length" "4")])
1025 (define_insn "*addsi3_internal2"
1026 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1027 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1028 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1030 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1033 {cax.|add.} %3,%1,%2
1034 {ai.|addic.} %3,%1,%2
1037 [(set_attr "type" "fast_compare,compare,compare,compare")
1038 (set_attr "length" "4,4,8,8")])
1041 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1042 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1043 (match_operand:SI 2 "reg_or_short_operand" ""))
1045 (clobber (match_scratch:SI 3 ""))]
1046 "TARGET_32BIT && reload_completed"
1048 (plus:SI (match_dup 1)
1051 (compare:CC (match_dup 3)
1055 (define_insn "*addsi3_internal3"
1056 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1057 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1058 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1060 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1061 (plus:SI (match_dup 1)
1065 {cax.|add.} %0,%1,%2
1066 {ai.|addic.} %0,%1,%2
1069 [(set_attr "type" "fast_compare,compare,compare,compare")
1070 (set_attr "length" "4,4,8,8")])
1073 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1074 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1075 (match_operand:SI 2 "reg_or_short_operand" ""))
1077 (set (match_operand:SI 0 "gpc_reg_operand" "")
1078 (plus:SI (match_dup 1) (match_dup 2)))]
1079 "TARGET_32BIT && reload_completed"
1081 (plus:SI (match_dup 1)
1084 (compare:CC (match_dup 0)
1088 ;; Split an add that we can't do in one insn into two insns, each of which
1089 ;; does one 16-bit part. This is used by combine. Note that the low-order
1090 ;; add should be last in case the result gets used in an address.
1093 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1094 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1095 (match_operand:SI 2 "non_add_cint_operand" "")))]
1097 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1098 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1101 HOST_WIDE_INT val = INTVAL (operands[2]);
1102 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1103 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1105 operands[3] = GEN_INT (rest);
1106 operands[4] = GEN_INT (low);
1109 (define_insn "one_cmplsi2"
1110 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1111 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1116 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1117 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1119 (clobber (match_scratch:SI 2 "=r,r"))]
1124 [(set_attr "type" "compare")
1125 (set_attr "length" "4,8")])
1128 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1129 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1131 (clobber (match_scratch:SI 2 ""))]
1132 "TARGET_32BIT && reload_completed"
1134 (not:SI (match_dup 1)))
1136 (compare:CC (match_dup 2)
1141 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1142 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1144 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1145 (not:SI (match_dup 1)))]
1150 [(set_attr "type" "compare")
1151 (set_attr "length" "4,8")])
1154 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1155 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1157 (set (match_operand:SI 0 "gpc_reg_operand" "")
1158 (not:SI (match_dup 1)))]
1159 "TARGET_32BIT && reload_completed"
1161 (not:SI (match_dup 1)))
1163 (compare:CC (match_dup 0)
1168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1169 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1170 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1172 "{sf%I1|subf%I1c} %0,%2,%1")
1175 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1176 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1177 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1184 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1185 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1186 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1188 (clobber (match_scratch:SI 3 "=r,r"))]
1191 {sf.|subfc.} %3,%2,%1
1193 [(set_attr "type" "compare")
1194 (set_attr "length" "4,8")])
1197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1198 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1199 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1201 (clobber (match_scratch:SI 3 "=r,r"))]
1202 "TARGET_POWERPC && TARGET_32BIT"
1206 [(set_attr "type" "fast_compare")
1207 (set_attr "length" "4,8")])
1210 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1211 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1212 (match_operand:SI 2 "gpc_reg_operand" ""))
1214 (clobber (match_scratch:SI 3 ""))]
1215 "TARGET_32BIT && reload_completed"
1217 (minus:SI (match_dup 1)
1220 (compare:CC (match_dup 3)
1225 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1226 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1227 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1229 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1230 (minus:SI (match_dup 1) (match_dup 2)))]
1233 {sf.|subfc.} %0,%2,%1
1235 [(set_attr "type" "compare")
1236 (set_attr "length" "4,8")])
1239 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1240 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1241 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1243 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1244 (minus:SI (match_dup 1)
1246 "TARGET_POWERPC && TARGET_32BIT"
1250 [(set_attr "type" "fast_compare")
1251 (set_attr "length" "4,8")])
1254 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1255 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1256 (match_operand:SI 2 "gpc_reg_operand" ""))
1258 (set (match_operand:SI 0 "gpc_reg_operand" "")
1259 (minus:SI (match_dup 1)
1261 "TARGET_32BIT && reload_completed"
1263 (minus:SI (match_dup 1)
1266 (compare:CC (match_dup 0)
1270 (define_expand "subsi3"
1271 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1272 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1273 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1277 if (GET_CODE (operands[2]) == CONST_INT)
1279 emit_insn (gen_addsi3 (operands[0], operands[1],
1280 negate_rtx (SImode, operands[2])));
1285 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1286 ;; instruction and some auxiliary computations. Then we just have a single
1287 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1290 (define_expand "sminsi3"
1292 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1293 (match_operand:SI 2 "reg_or_short_operand" ""))
1295 (minus:SI (match_dup 2) (match_dup 1))))
1296 (set (match_operand:SI 0 "gpc_reg_operand" "")
1297 (minus:SI (match_dup 2) (match_dup 3)))]
1298 "TARGET_POWER || TARGET_ISEL"
1303 operands[2] = force_reg (SImode, operands[2]);
1304 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1308 operands[3] = gen_reg_rtx (SImode);
1312 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1313 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1314 (match_operand:SI 2 "reg_or_short_operand" "")))
1315 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1318 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1320 (minus:SI (match_dup 2) (match_dup 1))))
1321 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1324 (define_expand "smaxsi3"
1326 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1327 (match_operand:SI 2 "reg_or_short_operand" ""))
1329 (minus:SI (match_dup 2) (match_dup 1))))
1330 (set (match_operand:SI 0 "gpc_reg_operand" "")
1331 (plus:SI (match_dup 3) (match_dup 1)))]
1332 "TARGET_POWER || TARGET_ISEL"
1337 operands[2] = force_reg (SImode, operands[2]);
1338 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1341 operands[3] = gen_reg_rtx (SImode);
1345 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1346 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1347 (match_operand:SI 2 "reg_or_short_operand" "")))
1348 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1351 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1353 (minus:SI (match_dup 2) (match_dup 1))))
1354 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1357 (define_expand "uminsi3"
1358 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1360 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1362 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1364 (minus:SI (match_dup 4) (match_dup 3))))
1365 (set (match_operand:SI 0 "gpc_reg_operand" "")
1366 (minus:SI (match_dup 2) (match_dup 3)))]
1367 "TARGET_POWER || TARGET_ISEL"
1372 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1375 operands[3] = gen_reg_rtx (SImode);
1376 operands[4] = gen_reg_rtx (SImode);
1377 operands[5] = GEN_INT (-2147483647 - 1);
1380 (define_expand "umaxsi3"
1381 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1383 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1385 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1387 (minus:SI (match_dup 4) (match_dup 3))))
1388 (set (match_operand:SI 0 "gpc_reg_operand" "")
1389 (plus:SI (match_dup 3) (match_dup 1)))]
1390 "TARGET_POWER || TARGET_ISEL"
1395 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1398 operands[3] = gen_reg_rtx (SImode);
1399 operands[4] = gen_reg_rtx (SImode);
1400 operands[5] = GEN_INT (-2147483647 - 1);
1404 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1405 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1406 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1408 (minus:SI (match_dup 2) (match_dup 1))))]
1413 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1415 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1416 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1418 (minus:SI (match_dup 2) (match_dup 1)))
1420 (clobber (match_scratch:SI 3 "=r,r"))]
1425 [(set_attr "type" "delayed_compare")
1426 (set_attr "length" "4,8")])
1429 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1431 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1432 (match_operand:SI 2 "reg_or_short_operand" ""))
1434 (minus:SI (match_dup 2) (match_dup 1)))
1436 (clobber (match_scratch:SI 3 ""))]
1437 "TARGET_POWER && reload_completed"
1439 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1441 (minus:SI (match_dup 2) (match_dup 1))))
1443 (compare:CC (match_dup 3)
1448 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1450 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1451 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1453 (minus:SI (match_dup 2) (match_dup 1)))
1455 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1456 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1458 (minus:SI (match_dup 2) (match_dup 1))))]
1463 [(set_attr "type" "delayed_compare")
1464 (set_attr "length" "4,8")])
1467 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1469 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1470 (match_operand:SI 2 "reg_or_short_operand" ""))
1472 (minus:SI (match_dup 2) (match_dup 1)))
1474 (set (match_operand:SI 0 "gpc_reg_operand" "")
1475 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1477 (minus:SI (match_dup 2) (match_dup 1))))]
1478 "TARGET_POWER && reload_completed"
1480 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1482 (minus:SI (match_dup 2) (match_dup 1))))
1484 (compare:CC (match_dup 0)
1488 ;; We don't need abs with condition code because such comparisons should
1490 (define_expand "abssi2"
1491 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1492 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1498 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1501 else if (! TARGET_POWER)
1503 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1508 (define_insn "*abssi2_power"
1509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1510 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1514 (define_insn_and_split "abssi2_isel"
1515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1516 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1517 (clobber (match_scratch:SI 2 "=&b"))
1518 (clobber (match_scratch:CC 3 "=y"))]
1521 "&& reload_completed"
1522 [(set (match_dup 2) (neg:SI (match_dup 1)))
1524 (compare:CC (match_dup 1)
1527 (if_then_else:SI (ge (match_dup 3)
1533 (define_insn_and_split "abssi2_nopower"
1534 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1535 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1536 (clobber (match_scratch:SI 2 "=&r,&r"))]
1537 "! TARGET_POWER && ! TARGET_ISEL"
1539 "&& reload_completed"
1540 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1541 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1542 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1545 (define_insn "*nabs_power"
1546 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1547 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1551 (define_insn_and_split "*nabs_nopower"
1552 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1553 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1554 (clobber (match_scratch:SI 2 "=&r,&r"))]
1557 "&& reload_completed"
1558 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1559 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1560 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1563 (define_insn "negsi2"
1564 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1565 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1570 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1571 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1573 (clobber (match_scratch:SI 2 "=r,r"))]
1578 [(set_attr "type" "fast_compare")
1579 (set_attr "length" "4,8")])
1582 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1583 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1585 (clobber (match_scratch:SI 2 ""))]
1586 "TARGET_32BIT && reload_completed"
1588 (neg:SI (match_dup 1)))
1590 (compare:CC (match_dup 2)
1595 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1596 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1598 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1599 (neg:SI (match_dup 1)))]
1604 [(set_attr "type" "fast_compare")
1605 (set_attr "length" "4,8")])
1608 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1609 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1611 (set (match_operand:SI 0 "gpc_reg_operand" "")
1612 (neg:SI (match_dup 1)))]
1613 "TARGET_32BIT && reload_completed"
1615 (neg:SI (match_dup 1)))
1617 (compare:CC (match_dup 0)
1621 (define_insn "clzsi2"
1622 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1623 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1625 "{cntlz|cntlzw} %0,%1")
1627 (define_expand "ctzsi2"
1629 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1630 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1632 (clobber (scratch:CC))])
1633 (set (match_dup 4) (clz:SI (match_dup 3)))
1634 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1635 (minus:SI (const_int 31) (match_dup 4)))]
1638 operands[2] = gen_reg_rtx (SImode);
1639 operands[3] = gen_reg_rtx (SImode);
1640 operands[4] = gen_reg_rtx (SImode);
1643 (define_expand "ffssi2"
1645 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1646 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1648 (clobber (scratch:CC))])
1649 (set (match_dup 4) (clz:SI (match_dup 3)))
1650 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1651 (minus:SI (const_int 32) (match_dup 4)))]
1654 operands[2] = gen_reg_rtx (SImode);
1655 operands[3] = gen_reg_rtx (SImode);
1656 operands[4] = gen_reg_rtx (SImode);
1659 (define_expand "mulsi3"
1660 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1661 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1662 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1667 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1669 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1673 (define_insn "mulsi3_mq"
1674 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1675 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1676 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1677 (clobber (match_scratch:SI 3 "=q,q"))]
1680 {muls|mullw} %0,%1,%2
1681 {muli|mulli} %0,%1,%2"
1683 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1684 (const_string "imul3")
1685 (match_operand:SI 2 "short_cint_operand" "")
1686 (const_string "imul2")]
1687 (const_string "imul")))])
1689 (define_insn "mulsi3_no_mq"
1690 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1691 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1692 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1695 {muls|mullw} %0,%1,%2
1696 {muli|mulli} %0,%1,%2"
1698 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1699 (const_string "imul3")
1700 (match_operand:SI 2 "short_cint_operand" "")
1701 (const_string "imul2")]
1702 (const_string "imul")))])
1704 (define_insn "*mulsi3_mq_internal1"
1705 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1706 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1707 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1709 (clobber (match_scratch:SI 3 "=r,r"))
1710 (clobber (match_scratch:SI 4 "=q,q"))]
1713 {muls.|mullw.} %3,%1,%2
1715 [(set_attr "type" "imul_compare")
1716 (set_attr "length" "4,8")])
1719 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1720 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1721 (match_operand:SI 2 "gpc_reg_operand" ""))
1723 (clobber (match_scratch:SI 3 ""))
1724 (clobber (match_scratch:SI 4 ""))]
1725 "TARGET_POWER && reload_completed"
1726 [(parallel [(set (match_dup 3)
1727 (mult:SI (match_dup 1) (match_dup 2)))
1728 (clobber (match_dup 4))])
1730 (compare:CC (match_dup 3)
1734 (define_insn "*mulsi3_no_mq_internal1"
1735 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1736 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1737 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1739 (clobber (match_scratch:SI 3 "=r,r"))]
1742 {muls.|mullw.} %3,%1,%2
1744 [(set_attr "type" "imul_compare")
1745 (set_attr "length" "4,8")])
1748 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1749 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1750 (match_operand:SI 2 "gpc_reg_operand" ""))
1752 (clobber (match_scratch:SI 3 ""))]
1753 "! TARGET_POWER && reload_completed"
1755 (mult:SI (match_dup 1) (match_dup 2)))
1757 (compare:CC (match_dup 3)
1761 (define_insn "*mulsi3_mq_internal2"
1762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1763 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1764 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1766 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1767 (mult:SI (match_dup 1) (match_dup 2)))
1768 (clobber (match_scratch:SI 4 "=q,q"))]
1771 {muls.|mullw.} %0,%1,%2
1773 [(set_attr "type" "imul_compare")
1774 (set_attr "length" "4,8")])
1777 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1778 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1779 (match_operand:SI 2 "gpc_reg_operand" ""))
1781 (set (match_operand:SI 0 "gpc_reg_operand" "")
1782 (mult:SI (match_dup 1) (match_dup 2)))
1783 (clobber (match_scratch:SI 4 ""))]
1784 "TARGET_POWER && reload_completed"
1785 [(parallel [(set (match_dup 0)
1786 (mult:SI (match_dup 1) (match_dup 2)))
1787 (clobber (match_dup 4))])
1789 (compare:CC (match_dup 0)
1793 (define_insn "*mulsi3_no_mq_internal2"
1794 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1795 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1796 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1798 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1799 (mult:SI (match_dup 1) (match_dup 2)))]
1802 {muls.|mullw.} %0,%1,%2
1804 [(set_attr "type" "imul_compare")
1805 (set_attr "length" "4,8")])
1808 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1809 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1810 (match_operand:SI 2 "gpc_reg_operand" ""))
1812 (set (match_operand:SI 0 "gpc_reg_operand" "")
1813 (mult:SI (match_dup 1) (match_dup 2)))]
1814 "! TARGET_POWER && reload_completed"
1816 (mult:SI (match_dup 1) (match_dup 2)))
1818 (compare:CC (match_dup 0)
1822 ;; Operand 1 is divided by operand 2; quotient goes to operand
1823 ;; 0 and remainder to operand 3.
1824 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1826 (define_expand "divmodsi4"
1827 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1828 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1829 (match_operand:SI 2 "gpc_reg_operand" "")))
1830 (set (match_operand:SI 3 "register_operand" "")
1831 (mod:SI (match_dup 1) (match_dup 2)))])]
1832 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1835 if (! TARGET_POWER && ! TARGET_POWERPC)
1837 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1838 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1839 emit_insn (gen_divss_call ());
1840 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1841 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1846 (define_insn "*divmodsi4_internal"
1847 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1848 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1849 (match_operand:SI 2 "gpc_reg_operand" "r")))
1850 (set (match_operand:SI 3 "register_operand" "=q")
1851 (mod:SI (match_dup 1) (match_dup 2)))]
1854 [(set_attr "type" "idiv")])
1856 (define_expand "udivsi3"
1857 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1858 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1859 (match_operand:SI 2 "gpc_reg_operand" "")))]
1860 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1863 if (! TARGET_POWER && ! TARGET_POWERPC)
1865 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1866 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1867 emit_insn (gen_quous_call ());
1868 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1871 else if (TARGET_POWER)
1873 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1878 (define_insn "udivsi3_mq"
1879 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1880 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1881 (match_operand:SI 2 "gpc_reg_operand" "r")))
1882 (clobber (match_scratch:SI 3 "=q"))]
1883 "TARGET_POWERPC && TARGET_POWER"
1885 [(set_attr "type" "idiv")])
1887 (define_insn "*udivsi3_no_mq"
1888 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1889 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1890 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1891 "TARGET_POWERPC && ! TARGET_POWER"
1893 [(set_attr "type" "idiv")])
1895 ;; For powers of two we can do srai/aze for divide and then adjust for
1896 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1897 ;; used; for PowerPC, force operands into register and do a normal divide;
1898 ;; for AIX common-mode, use quoss call on register operands.
1899 (define_expand "divsi3"
1900 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1901 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1902 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1906 if (GET_CODE (operands[2]) == CONST_INT
1907 && INTVAL (operands[2]) > 0
1908 && exact_log2 (INTVAL (operands[2])) >= 0)
1910 else if (TARGET_POWERPC)
1912 operands[2] = force_reg (SImode, operands[2]);
1915 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1919 else if (TARGET_POWER)
1923 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1924 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1925 emit_insn (gen_quoss_call ());
1926 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1931 (define_insn "divsi3_mq"
1932 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1933 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1934 (match_operand:SI 2 "gpc_reg_operand" "r")))
1935 (clobber (match_scratch:SI 3 "=q"))]
1936 "TARGET_POWERPC && TARGET_POWER"
1938 [(set_attr "type" "idiv")])
1940 (define_insn "*divsi3_no_mq"
1941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1942 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1943 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1944 "TARGET_POWERPC && ! TARGET_POWER"
1946 [(set_attr "type" "idiv")])
1948 (define_expand "modsi3"
1949 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1950 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1951 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1959 if (GET_CODE (operands[2]) != CONST_INT
1960 || INTVAL (operands[2]) <= 0
1961 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1964 temp1 = gen_reg_rtx (SImode);
1965 temp2 = gen_reg_rtx (SImode);
1967 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1968 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1969 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1975 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1976 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1978 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1979 [(set_attr "type" "two")
1980 (set_attr "length" "8")])
1983 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1984 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1985 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1987 (clobber (match_scratch:SI 3 "=r,r"))]
1990 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1992 [(set_attr "type" "compare")
1993 (set_attr "length" "8,12")])
1996 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1997 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1998 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2000 (clobber (match_scratch:SI 3 ""))]
2003 (div:SI (match_dup 1) (match_dup 2)))
2005 (compare:CC (match_dup 3)
2010 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2011 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2012 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2014 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2015 (div:SI (match_dup 1) (match_dup 2)))]
2018 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2020 [(set_attr "type" "compare")
2021 (set_attr "length" "8,12")])
2024 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2025 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2026 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2028 (set (match_operand:SI 0 "gpc_reg_operand" "")
2029 (div:SI (match_dup 1) (match_dup 2)))]
2032 (div:SI (match_dup 1) (match_dup 2)))
2034 (compare:CC (match_dup 0)
2039 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2042 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2044 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2045 (match_operand:SI 3 "gpc_reg_operand" "r")))
2046 (set (match_operand:SI 2 "register_operand" "=*q")
2049 (zero_extend:DI (match_dup 1)) (const_int 32))
2050 (zero_extend:DI (match_dup 4)))
2054 [(set_attr "type" "idiv")])
2056 ;; To do unsigned divide we handle the cases of the divisor looking like a
2057 ;; negative number. If it is a constant that is less than 2**31, we don't
2058 ;; have to worry about the branches. So make a few subroutines here.
2060 ;; First comes the normal case.
2061 (define_expand "udivmodsi4_normal"
2062 [(set (match_dup 4) (const_int 0))
2063 (parallel [(set (match_operand:SI 0 "" "")
2064 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2066 (zero_extend:DI (match_operand:SI 1 "" "")))
2067 (match_operand:SI 2 "" "")))
2068 (set (match_operand:SI 3 "" "")
2069 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2071 (zero_extend:DI (match_dup 1)))
2075 { operands[4] = gen_reg_rtx (SImode); }")
2077 ;; This handles the branches.
2078 (define_expand "udivmodsi4_tests"
2079 [(set (match_operand:SI 0 "" "") (const_int 0))
2080 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2081 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2082 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2083 (label_ref (match_operand:SI 4 "" "")) (pc)))
2084 (set (match_dup 0) (const_int 1))
2085 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2086 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2087 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2088 (label_ref (match_dup 4)) (pc)))]
2091 { operands[5] = gen_reg_rtx (CCUNSmode);
2092 operands[6] = gen_reg_rtx (CCmode);
2095 (define_expand "udivmodsi4"
2096 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2097 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2098 (match_operand:SI 2 "reg_or_cint_operand" "")))
2099 (set (match_operand:SI 3 "gpc_reg_operand" "")
2100 (umod:SI (match_dup 1) (match_dup 2)))])]
2108 if (! TARGET_POWERPC)
2110 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2111 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2112 emit_insn (gen_divus_call ());
2113 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2114 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2121 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2123 operands[2] = force_reg (SImode, operands[2]);
2124 label = gen_label_rtx ();
2125 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2126 operands[3], label));
2129 operands[2] = force_reg (SImode, operands[2]);
2131 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2139 ;; AIX architecture-independent common-mode multiply (DImode),
2140 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2141 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2142 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2143 ;; assumed unused if generating common-mode, so ignore.
2144 (define_insn "mulh_call"
2147 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2148 (sign_extend:DI (reg:SI 4)))
2150 (clobber (match_scratch:SI 0 "=l"))]
2151 "! TARGET_POWER && ! TARGET_POWERPC"
2153 [(set_attr "type" "imul")])
2155 (define_insn "mull_call"
2157 (mult:DI (sign_extend:DI (reg:SI 3))
2158 (sign_extend:DI (reg:SI 4))))
2159 (clobber (match_scratch:SI 0 "=l"))
2160 (clobber (reg:SI 0))]
2161 "! TARGET_POWER && ! TARGET_POWERPC"
2163 [(set_attr "type" "imul")])
2165 (define_insn "divss_call"
2167 (div:SI (reg:SI 3) (reg:SI 4)))
2169 (mod:SI (reg:SI 3) (reg:SI 4)))
2170 (clobber (match_scratch:SI 0 "=l"))
2171 (clobber (reg:SI 0))]
2172 "! TARGET_POWER && ! TARGET_POWERPC"
2174 [(set_attr "type" "idiv")])
2176 (define_insn "divus_call"
2178 (udiv:SI (reg:SI 3) (reg:SI 4)))
2180 (umod:SI (reg:SI 3) (reg:SI 4)))
2181 (clobber (match_scratch:SI 0 "=l"))
2182 (clobber (reg:SI 0))
2183 (clobber (match_scratch:CC 1 "=x"))
2184 (clobber (reg:CC 69))]
2185 "! TARGET_POWER && ! TARGET_POWERPC"
2187 [(set_attr "type" "idiv")])
2189 (define_insn "quoss_call"
2191 (div:SI (reg:SI 3) (reg:SI 4)))
2192 (clobber (match_scratch:SI 0 "=l"))]
2193 "! TARGET_POWER && ! TARGET_POWERPC"
2195 [(set_attr "type" "idiv")])
2197 (define_insn "quous_call"
2199 (udiv:SI (reg:SI 3) (reg:SI 4)))
2200 (clobber (match_scratch:SI 0 "=l"))
2201 (clobber (reg:SI 0))
2202 (clobber (match_scratch:CC 1 "=x"))
2203 (clobber (reg:CC 69))]
2204 "! TARGET_POWER && ! TARGET_POWERPC"
2206 [(set_attr "type" "idiv")])
2208 ;; Logical instructions
2209 ;; The logical instructions are mostly combined by using match_operator,
2210 ;; but the plain AND insns are somewhat different because there is no
2211 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2212 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2214 (define_insn "andsi3"
2215 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2216 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2217 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2218 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2222 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2223 {andil.|andi.} %0,%1,%b2
2224 {andiu.|andis.} %0,%1,%u2"
2225 [(set_attr "type" "*,*,compare,compare")])
2227 ;; Note to set cr's other than cr0 we do the and immediate and then
2228 ;; the test again -- this avoids a mfcr which on the higher end
2229 ;; machines causes an execution serialization
2231 (define_insn "*andsi3_internal2"
2232 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2233 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2234 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2236 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2237 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2241 {andil.|andi.} %3,%1,%b2
2242 {andiu.|andis.} %3,%1,%u2
2243 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2248 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2249 (set_attr "length" "4,4,4,4,8,8,8,8")])
2251 (define_insn "*andsi3_internal3"
2252 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2253 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2254 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2256 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2257 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2261 {andil.|andi.} %3,%1,%b2
2262 {andiu.|andis.} %3,%1,%u2
2263 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2268 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2269 (set_attr "length" "8,4,4,4,8,8,8,8")])
2272 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2273 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2274 (match_operand:SI 2 "and_operand" ""))
2276 (clobber (match_scratch:SI 3 ""))
2277 (clobber (match_scratch:CC 4 ""))]
2279 [(parallel [(set (match_dup 3)
2280 (and:SI (match_dup 1)
2282 (clobber (match_dup 4))])
2284 (compare:CC (match_dup 3)
2288 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2289 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2292 [(set (match_operand:CC 0 "cc_reg_operand" "")
2293 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2294 (match_operand:SI 2 "gpc_reg_operand" ""))
2296 (clobber (match_scratch:SI 3 ""))
2297 (clobber (match_scratch:CC 4 ""))]
2298 "TARGET_POWERPC64 && reload_completed"
2299 [(parallel [(set (match_dup 3)
2300 (and:SI (match_dup 1)
2302 (clobber (match_dup 4))])
2304 (compare:CC (match_dup 3)
2308 (define_insn "*andsi3_internal4"
2309 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2310 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2311 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2313 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2314 (and:SI (match_dup 1)
2316 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2320 {andil.|andi.} %0,%1,%b2
2321 {andiu.|andis.} %0,%1,%u2
2322 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2327 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2328 (set_attr "length" "4,4,4,4,8,8,8,8")])
2330 (define_insn "*andsi3_internal5"
2331 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2332 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2333 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2335 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2336 (and:SI (match_dup 1)
2338 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2342 {andil.|andi.} %0,%1,%b2
2343 {andiu.|andis.} %0,%1,%u2
2344 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2349 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2350 (set_attr "length" "8,4,4,4,8,8,8,8")])
2353 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2354 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2355 (match_operand:SI 2 "and_operand" ""))
2357 (set (match_operand:SI 0 "gpc_reg_operand" "")
2358 (and:SI (match_dup 1)
2360 (clobber (match_scratch:CC 4 ""))]
2362 [(parallel [(set (match_dup 0)
2363 (and:SI (match_dup 1)
2365 (clobber (match_dup 4))])
2367 (compare:CC (match_dup 0)
2372 [(set (match_operand:CC 3 "cc_reg_operand" "")
2373 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2374 (match_operand:SI 2 "gpc_reg_operand" ""))
2376 (set (match_operand:SI 0 "gpc_reg_operand" "")
2377 (and:SI (match_dup 1)
2379 (clobber (match_scratch:CC 4 ""))]
2380 "TARGET_POWERPC64 && reload_completed"
2381 [(parallel [(set (match_dup 0)
2382 (and:SI (match_dup 1)
2384 (clobber (match_dup 4))])
2386 (compare:CC (match_dup 0)
2390 ;; Handle the PowerPC64 rlwinm corner case
2392 (define_insn_and_split "*andsi3_internal6"
2393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2394 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2395 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2400 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2403 (rotate:SI (match_dup 0) (match_dup 5)))]
2406 int mb = extract_MB (operands[2]);
2407 int me = extract_ME (operands[2]);
2408 operands[3] = GEN_INT (me + 1);
2409 operands[5] = GEN_INT (32 - (me + 1));
2410 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2412 [(set_attr "length" "8")])
2414 (define_expand "iorsi3"
2415 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2416 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2417 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2421 if (GET_CODE (operands[2]) == CONST_INT
2422 && ! logical_operand (operands[2], SImode))
2424 HOST_WIDE_INT value = INTVAL (operands[2]);
2425 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2426 ? operands[0] : gen_reg_rtx (SImode));
2428 emit_insn (gen_iorsi3 (tmp, operands[1],
2429 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2430 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2435 (define_expand "xorsi3"
2436 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2437 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2438 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2442 if (GET_CODE (operands[2]) == CONST_INT
2443 && ! logical_operand (operands[2], SImode))
2445 HOST_WIDE_INT value = INTVAL (operands[2]);
2446 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2447 ? operands[0] : gen_reg_rtx (SImode));
2449 emit_insn (gen_xorsi3 (tmp, operands[1],
2450 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2451 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2456 (define_insn "*boolsi3_internal1"
2457 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2458 (match_operator:SI 3 "boolean_or_operator"
2459 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2460 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2464 {%q3il|%q3i} %0,%1,%b2
2465 {%q3iu|%q3is} %0,%1,%u2")
2467 (define_insn "*boolsi3_internal2"
2468 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2469 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2470 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2471 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2473 (clobber (match_scratch:SI 3 "=r,r"))]
2478 [(set_attr "type" "compare")
2479 (set_attr "length" "4,8")])
2482 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2483 (compare:CC (match_operator:SI 4 "boolean_operator"
2484 [(match_operand:SI 1 "gpc_reg_operand" "")
2485 (match_operand:SI 2 "gpc_reg_operand" "")])
2487 (clobber (match_scratch:SI 3 ""))]
2488 "TARGET_32BIT && reload_completed"
2489 [(set (match_dup 3) (match_dup 4))
2491 (compare:CC (match_dup 3)
2495 (define_insn "*boolsi3_internal3"
2496 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2497 (compare:CC (match_operator:SI 4 "boolean_operator"
2498 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2499 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2501 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2507 [(set_attr "type" "compare")
2508 (set_attr "length" "4,8")])
2511 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2512 (compare:CC (match_operator:SI 4 "boolean_operator"
2513 [(match_operand:SI 1 "gpc_reg_operand" "")
2514 (match_operand:SI 2 "gpc_reg_operand" "")])
2516 (set (match_operand:SI 0 "gpc_reg_operand" "")
2518 "TARGET_32BIT && reload_completed"
2519 [(set (match_dup 0) (match_dup 4))
2521 (compare:CC (match_dup 0)
2525 ;; Split a logical operation that we can't do in one insn into two insns,
2526 ;; each of which does one 16-bit part. This is used by combine.
2529 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2530 (match_operator:SI 3 "boolean_or_operator"
2531 [(match_operand:SI 1 "gpc_reg_operand" "")
2532 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2534 [(set (match_dup 0) (match_dup 4))
2535 (set (match_dup 0) (match_dup 5))]
2539 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2540 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2542 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2543 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2547 (define_insn "*boolcsi3_internal1"
2548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2549 (match_operator:SI 3 "boolean_operator"
2550 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2551 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2555 (define_insn "*boolcsi3_internal2"
2556 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2557 (compare:CC (match_operator:SI 4 "boolean_operator"
2558 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2559 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2561 (clobber (match_scratch:SI 3 "=r,r"))]
2566 [(set_attr "type" "compare")
2567 (set_attr "length" "4,8")])
2570 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2571 (compare:CC (match_operator:SI 4 "boolean_operator"
2572 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2573 (match_operand:SI 2 "gpc_reg_operand" "")])
2575 (clobber (match_scratch:SI 3 ""))]
2576 "TARGET_32BIT && reload_completed"
2577 [(set (match_dup 3) (match_dup 4))
2579 (compare:CC (match_dup 3)
2583 (define_insn "*boolcsi3_internal3"
2584 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2585 (compare:CC (match_operator:SI 4 "boolean_operator"
2586 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2587 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2589 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2595 [(set_attr "type" "compare")
2596 (set_attr "length" "4,8")])
2599 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2600 (compare:CC (match_operator:SI 4 "boolean_operator"
2601 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2602 (match_operand:SI 2 "gpc_reg_operand" "")])
2604 (set (match_operand:SI 0 "gpc_reg_operand" "")
2606 "TARGET_32BIT && reload_completed"
2607 [(set (match_dup 0) (match_dup 4))
2609 (compare:CC (match_dup 0)
2613 (define_insn "*boolccsi3_internal1"
2614 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2615 (match_operator:SI 3 "boolean_operator"
2616 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2617 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2621 (define_insn "*boolccsi3_internal2"
2622 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2623 (compare:CC (match_operator:SI 4 "boolean_operator"
2624 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2625 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2627 (clobber (match_scratch:SI 3 "=r,r"))]
2632 [(set_attr "type" "compare")
2633 (set_attr "length" "4,8")])
2636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2637 (compare:CC (match_operator:SI 4 "boolean_operator"
2638 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2639 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2641 (clobber (match_scratch:SI 3 ""))]
2642 "TARGET_32BIT && reload_completed"
2643 [(set (match_dup 3) (match_dup 4))
2645 (compare:CC (match_dup 3)
2649 (define_insn "*boolccsi3_internal3"
2650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2651 (compare:CC (match_operator:SI 4 "boolean_operator"
2652 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2653 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2655 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2661 [(set_attr "type" "compare")
2662 (set_attr "length" "4,8")])
2665 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2666 (compare:CC (match_operator:SI 4 "boolean_operator"
2667 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2668 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2670 (set (match_operand:SI 0 "gpc_reg_operand" "")
2672 "TARGET_32BIT && reload_completed"
2673 [(set (match_dup 0) (match_dup 4))
2675 (compare:CC (match_dup 0)
2679 ;; maskir insn. We need four forms because things might be in arbitrary
2680 ;; orders. Don't define forms that only set CR fields because these
2681 ;; would modify an input register.
2683 (define_insn "*maskir_internal1"
2684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2685 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2686 (match_operand:SI 1 "gpc_reg_operand" "0"))
2687 (and:SI (match_dup 2)
2688 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2692 (define_insn "*maskir_internal2"
2693 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2694 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2695 (match_operand:SI 1 "gpc_reg_operand" "0"))
2696 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2701 (define_insn "*maskir_internal3"
2702 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2703 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2704 (match_operand:SI 3 "gpc_reg_operand" "r"))
2705 (and:SI (not:SI (match_dup 2))
2706 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2710 (define_insn "*maskir_internal4"
2711 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2712 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2713 (match_operand:SI 2 "gpc_reg_operand" "r"))
2714 (and:SI (not:SI (match_dup 2))
2715 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2719 (define_insn "*maskir_internal5"
2720 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2722 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2723 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2724 (and:SI (match_dup 2)
2725 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2727 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2728 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2729 (and:SI (match_dup 2) (match_dup 3))))]
2734 [(set_attr "type" "compare")
2735 (set_attr "length" "4,8")])
2738 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2740 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2741 (match_operand:SI 1 "gpc_reg_operand" ""))
2742 (and:SI (match_dup 2)
2743 (match_operand:SI 3 "gpc_reg_operand" "")))
2745 (set (match_operand:SI 0 "gpc_reg_operand" "")
2746 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2747 (and:SI (match_dup 2) (match_dup 3))))]
2748 "TARGET_POWER && reload_completed"
2750 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2751 (and:SI (match_dup 2) (match_dup 3))))
2753 (compare:CC (match_dup 0)
2757 (define_insn "*maskir_internal6"
2758 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2760 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2761 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2762 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2765 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2766 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2767 (and:SI (match_dup 3) (match_dup 2))))]
2772 [(set_attr "type" "compare")
2773 (set_attr "length" "4,8")])
2776 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2778 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2779 (match_operand:SI 1 "gpc_reg_operand" ""))
2780 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2783 (set (match_operand:SI 0 "gpc_reg_operand" "")
2784 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2785 (and:SI (match_dup 3) (match_dup 2))))]
2786 "TARGET_POWER && reload_completed"
2788 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2789 (and:SI (match_dup 3) (match_dup 2))))
2791 (compare:CC (match_dup 0)
2795 (define_insn "*maskir_internal7"
2796 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2798 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2799 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2800 (and:SI (not:SI (match_dup 2))
2801 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2803 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2804 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2805 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2810 [(set_attr "type" "compare")
2811 (set_attr "length" "4,8")])
2814 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2816 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2817 (match_operand:SI 3 "gpc_reg_operand" ""))
2818 (and:SI (not:SI (match_dup 2))
2819 (match_operand:SI 1 "gpc_reg_operand" "")))
2821 (set (match_operand:SI 0 "gpc_reg_operand" "")
2822 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2823 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2824 "TARGET_POWER && reload_completed"
2826 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2827 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2829 (compare:CC (match_dup 0)
2833 (define_insn "*maskir_internal8"
2834 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2836 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2837 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2838 (and:SI (not:SI (match_dup 2))
2839 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2841 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2842 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2843 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2848 [(set_attr "type" "compare")
2849 (set_attr "length" "4,8")])
2852 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2854 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2855 (match_operand:SI 2 "gpc_reg_operand" ""))
2856 (and:SI (not:SI (match_dup 2))
2857 (match_operand:SI 1 "gpc_reg_operand" "")))
2859 (set (match_operand:SI 0 "gpc_reg_operand" "")
2860 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2861 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2862 "TARGET_POWER && reload_completed"
2864 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2865 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2867 (compare:CC (match_dup 0)
2871 ;; Rotate and shift insns, in all their variants. These support shifts,
2872 ;; field inserts and extracts, and various combinations thereof.
2873 (define_expand "insv"
2874 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2875 (match_operand:SI 1 "const_int_operand" "")
2876 (match_operand:SI 2 "const_int_operand" ""))
2877 (match_operand 3 "gpc_reg_operand" ""))]
2881 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2882 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2883 compiler if the address of the structure is taken later. */
2884 if (GET_CODE (operands[0]) == SUBREG
2885 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2888 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2889 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2891 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2895 (define_insn "insvsi"
2896 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2897 (match_operand:SI 1 "const_int_operand" "i")
2898 (match_operand:SI 2 "const_int_operand" "i"))
2899 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2903 int start = INTVAL (operands[2]) & 31;
2904 int size = INTVAL (operands[1]) & 31;
2906 operands[4] = GEN_INT (32 - start - size);
2907 operands[1] = GEN_INT (start + size - 1);
2908 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2910 [(set_attr "type" "insert_word")])
2912 (define_insn "*insvsi_internal1"
2913 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2914 (match_operand:SI 1 "const_int_operand" "i")
2915 (match_operand:SI 2 "const_int_operand" "i"))
2916 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2917 (match_operand:SI 4 "const_int_operand" "i")))]
2918 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2921 int shift = INTVAL (operands[4]) & 31;
2922 int start = INTVAL (operands[2]) & 31;
2923 int size = INTVAL (operands[1]) & 31;
2925 operands[4] = GEN_INT (shift - start - size);
2926 operands[1] = GEN_INT (start + size - 1);
2927 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2929 [(set_attr "type" "insert_word")])
2931 (define_insn "*insvsi_internal2"
2932 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2933 (match_operand:SI 1 "const_int_operand" "i")
2934 (match_operand:SI 2 "const_int_operand" "i"))
2935 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2936 (match_operand:SI 4 "const_int_operand" "i")))]
2937 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2940 int shift = INTVAL (operands[4]) & 31;
2941 int start = INTVAL (operands[2]) & 31;
2942 int size = INTVAL (operands[1]) & 31;
2944 operands[4] = GEN_INT (32 - shift - start - size);
2945 operands[1] = GEN_INT (start + size - 1);
2946 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2948 [(set_attr "type" "insert_word")])
2950 (define_insn "*insvsi_internal3"
2951 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2952 (match_operand:SI 1 "const_int_operand" "i")
2953 (match_operand:SI 2 "const_int_operand" "i"))
2954 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2955 (match_operand:SI 4 "const_int_operand" "i")))]
2956 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2959 int shift = INTVAL (operands[4]) & 31;
2960 int start = INTVAL (operands[2]) & 31;
2961 int size = INTVAL (operands[1]) & 31;
2963 operands[4] = GEN_INT (32 - shift - start - size);
2964 operands[1] = GEN_INT (start + size - 1);
2965 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2967 [(set_attr "type" "insert_word")])
2969 (define_insn "*insvsi_internal4"
2970 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2971 (match_operand:SI 1 "const_int_operand" "i")
2972 (match_operand:SI 2 "const_int_operand" "i"))
2973 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2974 (match_operand:SI 4 "const_int_operand" "i")
2975 (match_operand:SI 5 "const_int_operand" "i")))]
2976 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2979 int extract_start = INTVAL (operands[5]) & 31;
2980 int extract_size = INTVAL (operands[4]) & 31;
2981 int insert_start = INTVAL (operands[2]) & 31;
2982 int insert_size = INTVAL (operands[1]) & 31;
2984 /* Align extract field with insert field */
2985 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
2986 operands[1] = GEN_INT (insert_start + insert_size - 1);
2987 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2989 [(set_attr "type" "insert_word")])
2991 ;; combine patterns for rlwimi
2992 (define_insn "*insvsi_internal5"
2993 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2994 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2995 (match_operand:SI 1 "mask_operand" "i"))
2996 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2997 (match_operand:SI 2 "const_int_operand" "i"))
2998 (match_operand:SI 5 "mask_operand" "i"))))]
2999 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3002 int me = extract_ME(operands[5]);
3003 int mb = extract_MB(operands[5]);
3004 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3005 operands[2] = GEN_INT(mb);
3006 operands[1] = GEN_INT(me);
3007 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3009 [(set_attr "type" "insert_word")])
3011 (define_insn "*insvsi_internal6"
3012 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3013 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3014 (match_operand:SI 2 "const_int_operand" "i"))
3015 (match_operand:SI 5 "mask_operand" "i"))
3016 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3017 (match_operand:SI 1 "mask_operand" "i"))))]
3018 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3021 int me = extract_ME(operands[5]);
3022 int mb = extract_MB(operands[5]);
3023 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3024 operands[2] = GEN_INT(mb);
3025 operands[1] = GEN_INT(me);
3026 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3028 [(set_attr "type" "insert_word")])
3030 (define_insn "insvdi"
3031 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3032 (match_operand:SI 1 "const_int_operand" "i")
3033 (match_operand:SI 2 "const_int_operand" "i"))
3034 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3038 int start = INTVAL (operands[2]) & 63;
3039 int size = INTVAL (operands[1]) & 63;
3041 operands[1] = GEN_INT (64 - start - size);
3042 return \"rldimi %0,%3,%H1,%H2\";
3045 (define_insn "*insvdi_internal2"
3046 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3047 (match_operand:SI 1 "const_int_operand" "i")
3048 (match_operand:SI 2 "const_int_operand" "i"))
3049 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3050 (match_operand:SI 4 "const_int_operand" "i")))]
3052 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3055 int shift = INTVAL (operands[4]) & 63;
3056 int start = (INTVAL (operands[2]) & 63) - 32;
3057 int size = INTVAL (operands[1]) & 63;
3059 operands[4] = GEN_INT (64 - shift - start - size);
3060 operands[2] = GEN_INT (start);
3061 operands[1] = GEN_INT (start + size - 1);
3062 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3065 (define_insn "*insvdi_internal3"
3066 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3067 (match_operand:SI 1 "const_int_operand" "i")
3068 (match_operand:SI 2 "const_int_operand" "i"))
3069 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3070 (match_operand:SI 4 "const_int_operand" "i")))]
3072 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3075 int shift = INTVAL (operands[4]) & 63;
3076 int start = (INTVAL (operands[2]) & 63) - 32;
3077 int size = INTVAL (operands[1]) & 63;
3079 operands[4] = GEN_INT (64 - shift - start - size);
3080 operands[2] = GEN_INT (start);
3081 operands[1] = GEN_INT (start + size - 1);
3082 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3085 (define_expand "extzv"
3086 [(set (match_operand 0 "gpc_reg_operand" "")
3087 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3088 (match_operand:SI 2 "const_int_operand" "")
3089 (match_operand:SI 3 "const_int_operand" "")))]
3093 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3094 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3095 compiler if the address of the structure is taken later. */
3096 if (GET_CODE (operands[0]) == SUBREG
3097 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3100 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3101 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3103 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3107 (define_insn "extzvsi"
3108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3109 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3110 (match_operand:SI 2 "const_int_operand" "i")
3111 (match_operand:SI 3 "const_int_operand" "i")))]
3115 int start = INTVAL (operands[3]) & 31;
3116 int size = INTVAL (operands[2]) & 31;
3118 if (start + size >= 32)
3119 operands[3] = const0_rtx;
3121 operands[3] = GEN_INT (start + size);
3122 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3125 (define_insn "*extzvsi_internal1"
3126 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3127 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3128 (match_operand:SI 2 "const_int_operand" "i,i")
3129 (match_operand:SI 3 "const_int_operand" "i,i"))
3131 (clobber (match_scratch:SI 4 "=r,r"))]
3135 int start = INTVAL (operands[3]) & 31;
3136 int size = INTVAL (operands[2]) & 31;
3138 /* Force split for non-cc0 compare. */
3139 if (which_alternative == 1)
3142 /* If the bit-field being tested fits in the upper or lower half of a
3143 word, it is possible to use andiu. or andil. to test it. This is
3144 useful because the condition register set-use delay is smaller for
3145 andi[ul]. than for rlinm. This doesn't work when the starting bit
3146 position is 0 because the LT and GT bits may be set wrong. */
3148 if ((start > 0 && start + size <= 16) || start >= 16)
3150 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3151 - (1 << (16 - (start & 15) - size))));
3153 return \"{andiu.|andis.} %4,%1,%3\";
3155 return \"{andil.|andi.} %4,%1,%3\";
3158 if (start + size >= 32)
3159 operands[3] = const0_rtx;
3161 operands[3] = GEN_INT (start + size);
3162 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3164 [(set_attr "type" "compare")
3165 (set_attr "length" "4,8")])
3168 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3169 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3170 (match_operand:SI 2 "const_int_operand" "")
3171 (match_operand:SI 3 "const_int_operand" ""))
3173 (clobber (match_scratch:SI 4 ""))]
3176 (zero_extract:SI (match_dup 1) (match_dup 2)
3179 (compare:CC (match_dup 4)
3183 (define_insn "*extzvsi_internal2"
3184 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3185 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3186 (match_operand:SI 2 "const_int_operand" "i,i")
3187 (match_operand:SI 3 "const_int_operand" "i,i"))
3189 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3190 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3194 int start = INTVAL (operands[3]) & 31;
3195 int size = INTVAL (operands[2]) & 31;
3197 /* Force split for non-cc0 compare. */
3198 if (which_alternative == 1)
3201 /* Since we are using the output value, we can't ignore any need for
3202 a shift. The bit-field must end at the LSB. */
3203 if (start >= 16 && start + size == 32)
3205 operands[3] = GEN_INT ((1 << size) - 1);
3206 return \"{andil.|andi.} %0,%1,%3\";
3209 if (start + size >= 32)
3210 operands[3] = const0_rtx;
3212 operands[3] = GEN_INT (start + size);
3213 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3215 [(set_attr "type" "compare")
3216 (set_attr "length" "4,8")])
3219 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3220 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3221 (match_operand:SI 2 "const_int_operand" "")
3222 (match_operand:SI 3 "const_int_operand" ""))
3224 (set (match_operand:SI 0 "gpc_reg_operand" "")
3225 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3228 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3230 (compare:CC (match_dup 0)
3234 (define_insn "extzvdi"
3235 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3236 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3237 (match_operand:SI 2 "const_int_operand" "i")
3238 (match_operand:SI 3 "const_int_operand" "i")))]
3242 int start = INTVAL (operands[3]) & 63;
3243 int size = INTVAL (operands[2]) & 63;
3245 if (start + size >= 64)
3246 operands[3] = const0_rtx;
3248 operands[3] = GEN_INT (start + size);
3249 operands[2] = GEN_INT (64 - size);
3250 return \"rldicl %0,%1,%3,%2\";
3253 (define_insn "*extzvdi_internal1"
3254 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3255 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3256 (match_operand:SI 2 "const_int_operand" "i")
3257 (match_operand:SI 3 "const_int_operand" "i"))
3259 (clobber (match_scratch:DI 4 "=r"))]
3263 int start = INTVAL (operands[3]) & 63;
3264 int size = INTVAL (operands[2]) & 63;
3266 if (start + size >= 64)
3267 operands[3] = const0_rtx;
3269 operands[3] = GEN_INT (start + size);
3270 operands[2] = GEN_INT (64 - size);
3271 return \"rldicl. %4,%1,%3,%2\";
3273 [(set_attr "type" "compare")])
3275 (define_insn "*extzvdi_internal2"
3276 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3277 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3278 (match_operand:SI 2 "const_int_operand" "i")
3279 (match_operand:SI 3 "const_int_operand" "i"))
3281 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3282 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3286 int start = INTVAL (operands[3]) & 63;
3287 int size = INTVAL (operands[2]) & 63;
3289 if (start + size >= 64)
3290 operands[3] = const0_rtx;
3292 operands[3] = GEN_INT (start + size);
3293 operands[2] = GEN_INT (64 - size);
3294 return \"rldicl. %0,%1,%3,%2\";
3296 [(set_attr "type" "compare")])
3298 (define_insn "rotlsi3"
3299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3300 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3301 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3303 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3305 (define_insn "*rotlsi3_internal2"
3306 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3307 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3308 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3310 (clobber (match_scratch:SI 3 "=r,r"))]
3313 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3315 [(set_attr "type" "delayed_compare")
3316 (set_attr "length" "4,8")])
3319 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3320 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3321 (match_operand:SI 2 "reg_or_cint_operand" ""))
3323 (clobber (match_scratch:SI 3 ""))]
3326 (rotate:SI (match_dup 1) (match_dup 2)))
3328 (compare:CC (match_dup 3)
3332 (define_insn "*rotlsi3_internal3"
3333 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3334 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3335 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3337 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3338 (rotate:SI (match_dup 1) (match_dup 2)))]
3341 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3343 [(set_attr "type" "delayed_compare")
3344 (set_attr "length" "4,8")])
3347 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3348 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3349 (match_operand:SI 2 "reg_or_cint_operand" ""))
3351 (set (match_operand:SI 0 "gpc_reg_operand" "")
3352 (rotate:SI (match_dup 1) (match_dup 2)))]
3355 (rotate:SI (match_dup 1) (match_dup 2)))
3357 (compare:CC (match_dup 0)
3361 (define_insn "*rotlsi3_internal4"
3362 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3363 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3364 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3365 (match_operand:SI 3 "mask_operand" "n")))]
3367 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3369 (define_insn "*rotlsi3_internal5"
3370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3372 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3373 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3374 (match_operand:SI 3 "mask_operand" "n,n"))
3376 (clobber (match_scratch:SI 4 "=r,r"))]
3379 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3381 [(set_attr "type" "delayed_compare")
3382 (set_attr "length" "4,8")])
3385 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3387 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3388 (match_operand:SI 2 "reg_or_cint_operand" ""))
3389 (match_operand:SI 3 "mask_operand" ""))
3391 (clobber (match_scratch:SI 4 ""))]
3394 (and:SI (rotate:SI (match_dup 1)
3398 (compare:CC (match_dup 4)
3402 (define_insn "*rotlsi3_internal6"
3403 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3405 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3406 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3407 (match_operand:SI 3 "mask_operand" "n,n"))
3409 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3410 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3413 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3415 [(set_attr "type" "delayed_compare")
3416 (set_attr "length" "4,8")])
3419 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3421 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3422 (match_operand:SI 2 "reg_or_cint_operand" ""))
3423 (match_operand:SI 3 "mask_operand" ""))
3425 (set (match_operand:SI 0 "gpc_reg_operand" "")
3426 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3429 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3431 (compare:CC (match_dup 0)
3435 (define_insn "*rotlsi3_internal7"
3436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3439 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3440 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3442 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3444 (define_insn "*rotlsi3_internal8"
3445 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3446 (compare:CC (zero_extend:SI
3448 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3449 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3451 (clobber (match_scratch:SI 3 "=r,r"))]
3454 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3456 [(set_attr "type" "delayed_compare")
3457 (set_attr "length" "4,8")])
3460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3461 (compare:CC (zero_extend:SI
3463 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3464 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3466 (clobber (match_scratch:SI 3 ""))]
3469 (zero_extend:SI (subreg:QI
3470 (rotate:SI (match_dup 1)
3473 (compare:CC (match_dup 3)
3477 (define_insn "*rotlsi3_internal9"
3478 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3479 (compare:CC (zero_extend:SI
3481 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3482 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3484 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3485 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3488 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3490 [(set_attr "type" "delayed_compare")
3491 (set_attr "length" "4,8")])
3494 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3495 (compare:CC (zero_extend:SI
3497 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3498 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3500 (set (match_operand:SI 0 "gpc_reg_operand" "")
3501 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3504 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3506 (compare:CC (match_dup 0)
3510 (define_insn "*rotlsi3_internal10"
3511 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3514 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3515 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3517 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3519 (define_insn "*rotlsi3_internal11"
3520 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3521 (compare:CC (zero_extend:SI
3523 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3524 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3526 (clobber (match_scratch:SI 3 "=r,r"))]
3529 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3531 [(set_attr "type" "delayed_compare")
3532 (set_attr "length" "4,8")])
3535 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3536 (compare:CC (zero_extend:SI
3538 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3539 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3541 (clobber (match_scratch:SI 3 ""))]
3544 (zero_extend:SI (subreg:HI
3545 (rotate:SI (match_dup 1)
3548 (compare:CC (match_dup 3)
3552 (define_insn "*rotlsi3_internal12"
3553 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3554 (compare:CC (zero_extend:SI
3556 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3557 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3559 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3560 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3563 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3565 [(set_attr "type" "delayed_compare")
3566 (set_attr "length" "4,8")])
3569 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3570 (compare:CC (zero_extend:SI
3572 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3573 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3575 (set (match_operand:SI 0 "gpc_reg_operand" "")
3576 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3579 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3581 (compare:CC (match_dup 0)
3585 ;; Note that we use "sle." instead of "sl." so that we can set
3586 ;; SHIFT_COUNT_TRUNCATED.
3588 (define_expand "ashlsi3"
3589 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3590 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3591 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3596 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3598 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3602 (define_insn "ashlsi3_power"
3603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3604 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3605 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3606 (clobber (match_scratch:SI 3 "=q,X"))]
3610 {sli|slwi} %0,%1,%h2")
3612 (define_insn "ashlsi3_no_power"
3613 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3614 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3615 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3617 "{sl|slw}%I2 %0,%1,%h2")
3620 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3621 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3622 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3624 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3625 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3629 {sli.|slwi.} %3,%1,%h2
3632 [(set_attr "type" "delayed_compare")
3633 (set_attr "length" "4,4,8,8")])
3636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3637 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3638 (match_operand:SI 2 "reg_or_cint_operand" ""))
3640 (clobber (match_scratch:SI 3 ""))
3641 (clobber (match_scratch:SI 4 ""))]
3642 "TARGET_POWER && reload_completed"
3643 [(parallel [(set (match_dup 3)
3644 (ashift:SI (match_dup 1) (match_dup 2)))
3645 (clobber (match_dup 4))])
3647 (compare:CC (match_dup 3)
3652 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3653 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3654 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3656 (clobber (match_scratch:SI 3 "=r,r"))]
3657 "! TARGET_POWER && TARGET_32BIT"
3659 {sl|slw}%I2. %3,%1,%h2
3661 [(set_attr "type" "delayed_compare")
3662 (set_attr "length" "4,8")])
3665 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3666 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3667 (match_operand:SI 2 "reg_or_cint_operand" ""))
3669 (clobber (match_scratch:SI 3 ""))]
3670 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3672 (ashift:SI (match_dup 1) (match_dup 2)))
3674 (compare:CC (match_dup 3)
3679 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3680 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3681 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3683 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3684 (ashift:SI (match_dup 1) (match_dup 2)))
3685 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3689 {sli.|slwi.} %0,%1,%h2
3692 [(set_attr "type" "delayed_compare")
3693 (set_attr "length" "4,4,8,8")])
3696 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3697 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3698 (match_operand:SI 2 "reg_or_cint_operand" ""))
3700 (set (match_operand:SI 0 "gpc_reg_operand" "")
3701 (ashift:SI (match_dup 1) (match_dup 2)))
3702 (clobber (match_scratch:SI 4 ""))]
3703 "TARGET_POWER && reload_completed"
3704 [(parallel [(set (match_dup 0)
3705 (ashift:SI (match_dup 1) (match_dup 2)))
3706 (clobber (match_dup 4))])
3708 (compare:CC (match_dup 0)
3713 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3714 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3715 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3717 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3718 (ashift:SI (match_dup 1) (match_dup 2)))]
3719 "! TARGET_POWER && TARGET_32BIT"
3721 {sl|slw}%I2. %0,%1,%h2
3723 [(set_attr "type" "delayed_compare")
3724 (set_attr "length" "4,8")])
3727 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3728 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3729 (match_operand:SI 2 "reg_or_cint_operand" ""))
3731 (set (match_operand:SI 0 "gpc_reg_operand" "")
3732 (ashift:SI (match_dup 1) (match_dup 2)))]
3733 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3735 (ashift:SI (match_dup 1) (match_dup 2)))
3737 (compare:CC (match_dup 0)
3742 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3743 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3744 (match_operand:SI 2 "const_int_operand" "i"))
3745 (match_operand:SI 3 "mask_operand" "n")))]
3746 "includes_lshift_p (operands[2], operands[3])"
3747 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3750 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3752 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3753 (match_operand:SI 2 "const_int_operand" "i,i"))
3754 (match_operand:SI 3 "mask_operand" "n,n"))
3756 (clobber (match_scratch:SI 4 "=r,r"))]
3757 "includes_lshift_p (operands[2], operands[3])"
3759 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3761 [(set_attr "type" "delayed_compare")
3762 (set_attr "length" "4,8")])
3765 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3767 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3768 (match_operand:SI 2 "const_int_operand" ""))
3769 (match_operand:SI 3 "mask_operand" ""))
3771 (clobber (match_scratch:SI 4 ""))]
3772 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3774 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3777 (compare:CC (match_dup 4)
3782 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3784 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3785 (match_operand:SI 2 "const_int_operand" "i,i"))
3786 (match_operand:SI 3 "mask_operand" "n,n"))
3788 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3789 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3790 "includes_lshift_p (operands[2], operands[3])"
3792 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3794 [(set_attr "type" "delayed_compare")
3795 (set_attr "length" "4,8")])
3798 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3800 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3801 (match_operand:SI 2 "const_int_operand" ""))
3802 (match_operand:SI 3 "mask_operand" ""))
3804 (set (match_operand:SI 0 "gpc_reg_operand" "")
3805 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3806 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3808 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3810 (compare:CC (match_dup 0)
3814 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3816 (define_expand "lshrsi3"
3817 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3818 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3819 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3824 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3826 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3830 (define_insn "lshrsi3_power"
3831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3832 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3833 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3834 (clobber (match_scratch:SI 3 "=q,X,X"))]
3839 {s%A2i|s%A2wi} %0,%1,%h2")
3841 (define_insn "lshrsi3_no_power"
3842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3843 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3844 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3848 {sr|srw}%I2 %0,%1,%h2")
3851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3852 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3853 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3855 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3856 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3861 {s%A2i.|s%A2wi.} %3,%1,%h2
3865 [(set_attr "type" "delayed_compare")
3866 (set_attr "length" "4,4,4,8,8,8")])
3869 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3870 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3871 (match_operand:SI 2 "reg_or_cint_operand" ""))
3873 (clobber (match_scratch:SI 3 ""))
3874 (clobber (match_scratch:SI 4 ""))]
3875 "TARGET_POWER && reload_completed"
3876 [(parallel [(set (match_dup 3)
3877 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3878 (clobber (match_dup 4))])
3880 (compare:CC (match_dup 3)
3885 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3886 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3887 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3889 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3890 "! TARGET_POWER && TARGET_32BIT"
3893 {sr|srw}%I2. %3,%1,%h2
3896 [(set_attr "type" "delayed_compare")
3897 (set_attr "length" "4,4,8,8")])
3900 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3901 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3902 (match_operand:SI 2 "reg_or_cint_operand" ""))
3904 (clobber (match_scratch:SI 3 ""))]
3905 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3907 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3909 (compare:CC (match_dup 3)
3914 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3915 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3916 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3918 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3919 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3920 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3925 {s%A2i.|s%A2wi.} %0,%1,%h2
3929 [(set_attr "type" "delayed_compare")
3930 (set_attr "length" "4,4,4,8,8,8")])
3933 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3934 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3935 (match_operand:SI 2 "reg_or_cint_operand" ""))
3937 (set (match_operand:SI 0 "gpc_reg_operand" "")
3938 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3939 (clobber (match_scratch:SI 4 ""))]
3940 "TARGET_POWER && reload_completed"
3941 [(parallel [(set (match_dup 0)
3942 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3943 (clobber (match_dup 4))])
3945 (compare:CC (match_dup 0)
3950 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3951 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3952 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3954 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3955 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3956 "! TARGET_POWER && TARGET_32BIT"
3959 {sr|srw}%I2. %0,%1,%h2
3962 [(set_attr "type" "delayed_compare")
3963 (set_attr "length" "4,4,8,8")])
3966 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3967 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3968 (match_operand:SI 2 "reg_or_cint_operand" ""))
3970 (set (match_operand:SI 0 "gpc_reg_operand" "")
3971 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3972 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3974 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3976 (compare:CC (match_dup 0)
3981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3982 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3983 (match_operand:SI 2 "const_int_operand" "i"))
3984 (match_operand:SI 3 "mask_operand" "n")))]
3985 "includes_rshift_p (operands[2], operands[3])"
3986 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3989 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3991 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3992 (match_operand:SI 2 "const_int_operand" "i,i"))
3993 (match_operand:SI 3 "mask_operand" "n,n"))
3995 (clobber (match_scratch:SI 4 "=r,r"))]
3996 "includes_rshift_p (operands[2], operands[3])"
3998 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4000 [(set_attr "type" "delayed_compare")
4001 (set_attr "length" "4,8")])
4004 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4006 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4007 (match_operand:SI 2 "const_int_operand" ""))
4008 (match_operand:SI 3 "mask_operand" ""))
4010 (clobber (match_scratch:SI 4 ""))]
4011 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4013 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4016 (compare:CC (match_dup 4)
4021 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4023 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4024 (match_operand:SI 2 "const_int_operand" "i,i"))
4025 (match_operand:SI 3 "mask_operand" "n,n"))
4027 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4028 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4029 "includes_rshift_p (operands[2], operands[3])"
4031 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4033 [(set_attr "type" "delayed_compare")
4034 (set_attr "length" "4,8")])
4037 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4039 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4040 (match_operand:SI 2 "const_int_operand" ""))
4041 (match_operand:SI 3 "mask_operand" ""))
4043 (set (match_operand:SI 0 "gpc_reg_operand" "")
4044 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4045 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4047 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4049 (compare:CC (match_dup 0)
4054 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4057 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4058 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4059 "includes_rshift_p (operands[2], GEN_INT (255))"
4060 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4063 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4067 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4068 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4070 (clobber (match_scratch:SI 3 "=r,r"))]
4071 "includes_rshift_p (operands[2], GEN_INT (255))"
4073 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4075 [(set_attr "type" "delayed_compare")
4076 (set_attr "length" "4,8")])
4079 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4083 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4084 (match_operand:SI 2 "const_int_operand" "")) 0))
4086 (clobber (match_scratch:SI 3 ""))]
4087 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4089 (zero_extend:SI (subreg:QI
4090 (lshiftrt:SI (match_dup 1)
4093 (compare:CC (match_dup 3)
4098 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4102 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4103 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4105 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4106 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4107 "includes_rshift_p (operands[2], GEN_INT (255))"
4109 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4111 [(set_attr "type" "delayed_compare")
4112 (set_attr "length" "4,8")])
4115 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4119 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4120 (match_operand:SI 2 "const_int_operand" "")) 0))
4122 (set (match_operand:SI 0 "gpc_reg_operand" "")
4123 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4124 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4126 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4128 (compare:CC (match_dup 0)
4133 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4136 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4137 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4138 "includes_rshift_p (operands[2], GEN_INT (65535))"
4139 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4142 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4146 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4147 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4149 (clobber (match_scratch:SI 3 "=r,r"))]
4150 "includes_rshift_p (operands[2], GEN_INT (65535))"
4152 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4154 [(set_attr "type" "delayed_compare")
4155 (set_attr "length" "4,8")])
4158 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4162 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4163 (match_operand:SI 2 "const_int_operand" "")) 0))
4165 (clobber (match_scratch:SI 3 ""))]
4166 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4168 (zero_extend:SI (subreg:HI
4169 (lshiftrt:SI (match_dup 1)
4172 (compare:CC (match_dup 3)
4177 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4181 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4182 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4184 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4185 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4186 "includes_rshift_p (operands[2], GEN_INT (65535))"
4188 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4190 [(set_attr "type" "delayed_compare")
4191 (set_attr "length" "4,8")])
4194 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4198 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4199 (match_operand:SI 2 "const_int_operand" "")) 0))
4201 (set (match_operand:SI 0 "gpc_reg_operand" "")
4202 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4203 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4205 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4207 (compare:CC (match_dup 0)
4212 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4214 (match_operand:SI 1 "gpc_reg_operand" "r"))
4215 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4221 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4223 (match_operand:SI 1 "gpc_reg_operand" "r"))
4224 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4230 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4232 (match_operand:SI 1 "gpc_reg_operand" "r"))
4233 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4239 (define_expand "ashrsi3"
4240 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4241 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4242 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4247 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4249 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4253 (define_insn "ashrsi3_power"
4254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4255 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4256 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4257 (clobber (match_scratch:SI 3 "=q,X"))]
4261 {srai|srawi} %0,%1,%h2")
4263 (define_insn "ashrsi3_no_power"
4264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4265 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4266 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4268 "{sra|sraw}%I2 %0,%1,%h2")
4271 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4272 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4273 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4275 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4276 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4280 {srai.|srawi.} %3,%1,%h2
4283 [(set_attr "type" "delayed_compare")
4284 (set_attr "length" "4,4,8,8")])
4287 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4288 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4289 (match_operand:SI 2 "reg_or_cint_operand" ""))
4291 (clobber (match_scratch:SI 3 ""))
4292 (clobber (match_scratch:SI 4 ""))]
4293 "TARGET_POWER && reload_completed"
4294 [(parallel [(set (match_dup 3)
4295 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4296 (clobber (match_dup 4))])
4298 (compare:CC (match_dup 3)
4303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4304 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4305 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4307 (clobber (match_scratch:SI 3 "=r,r"))]
4310 {sra|sraw}%I2. %3,%1,%h2
4312 [(set_attr "type" "delayed_compare")
4313 (set_attr "length" "4,8")])
4316 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4317 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4318 (match_operand:SI 2 "reg_or_cint_operand" ""))
4320 (clobber (match_scratch:SI 3 ""))]
4321 "! TARGET_POWER && reload_completed"
4323 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4325 (compare:CC (match_dup 3)
4330 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4331 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4332 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4334 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4335 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4336 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4340 {srai.|srawi.} %0,%1,%h2
4343 [(set_attr "type" "delayed_compare")
4344 (set_attr "length" "4,4,8,8")])
4347 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4348 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4349 (match_operand:SI 2 "reg_or_cint_operand" ""))
4351 (set (match_operand:SI 0 "gpc_reg_operand" "")
4352 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4353 (clobber (match_scratch:SI 4 ""))]
4354 "TARGET_POWER && reload_completed"
4355 [(parallel [(set (match_dup 0)
4356 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4357 (clobber (match_dup 4))])
4359 (compare:CC (match_dup 0)
4364 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4365 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4366 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4368 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4369 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4372 {sra|sraw}%I2. %0,%1,%h2
4374 [(set_attr "type" "delayed_compare")
4375 (set_attr "length" "4,8")])
4378 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4379 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4380 (match_operand:SI 2 "reg_or_cint_operand" ""))
4382 (set (match_operand:SI 0 "gpc_reg_operand" "")
4383 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4384 "! TARGET_POWER && reload_completed"
4386 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4388 (compare:CC (match_dup 0)
4392 ;; Floating-point insns, excluding normal data motion.
4394 ;; PowerPC has a full set of single-precision floating point instructions.
4396 ;; For the POWER architecture, we pretend that we have both SFmode and
4397 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4398 ;; The only conversions we will do will be when storing to memory. In that
4399 ;; case, we will use the "frsp" instruction before storing.
4401 ;; Note that when we store into a single-precision memory location, we need to
4402 ;; use the frsp insn first. If the register being stored isn't dead, we
4403 ;; need a scratch register for the frsp. But this is difficult when the store
4404 ;; is done by reload. It is not incorrect to do the frsp on the register in
4405 ;; this case, we just lose precision that we would have otherwise gotten but
4406 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4408 (define_expand "extendsfdf2"
4409 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4410 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "")))]
4411 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4414 (define_insn_and_split "*extendsfdf2_fpr"
4415 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
4416 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))]
4417 "TARGET_HARD_FLOAT && TARGET_FPRS"
4421 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
4424 emit_note (NOTE_INSN_DELETED);
4427 [(set_attr "type" "fp")])
4429 (define_expand "truncdfsf2"
4430 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4431 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4432 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4435 (define_insn "*truncdfsf2_fpr"
4436 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4437 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4438 "TARGET_HARD_FLOAT && TARGET_FPRS"
4440 [(set_attr "type" "fp")])
4442 (define_insn "aux_truncdfsf2"
4443 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4444 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4445 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4447 [(set_attr "type" "fp")])
4449 (define_expand "negsf2"
4450 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4451 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4455 (define_insn "*negsf2"
4456 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4457 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4458 "TARGET_HARD_FLOAT && TARGET_FPRS"
4460 [(set_attr "type" "fp")])
4462 (define_expand "abssf2"
4463 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4464 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4468 (define_insn "*abssf2"
4469 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4470 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4471 "TARGET_HARD_FLOAT && TARGET_FPRS"
4473 [(set_attr "type" "fp")])
4476 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4477 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4478 "TARGET_HARD_FLOAT && TARGET_FPRS"
4480 [(set_attr "type" "fp")])
4482 (define_expand "addsf3"
4483 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4484 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4485 (match_operand:SF 2 "gpc_reg_operand" "")))]
4490 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4491 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4492 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4493 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4495 [(set_attr "type" "fp")])
4498 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4499 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4500 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4501 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4502 "{fa|fadd} %0,%1,%2"
4503 [(set_attr "type" "fp")])
4505 (define_expand "subsf3"
4506 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4507 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4508 (match_operand:SF 2 "gpc_reg_operand" "")))]
4513 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4514 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4515 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4516 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4518 [(set_attr "type" "fp")])
4521 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4522 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4523 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4524 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4525 "{fs|fsub} %0,%1,%2"
4526 [(set_attr "type" "fp")])
4528 (define_expand "mulsf3"
4529 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4530 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4531 (match_operand:SF 2 "gpc_reg_operand" "")))]
4536 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4537 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4538 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4539 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4541 [(set_attr "type" "fp")])
4544 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4545 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4546 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4547 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4548 "{fm|fmul} %0,%1,%2"
4549 [(set_attr "type" "dmul")])
4551 (define_expand "divsf3"
4552 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4553 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4554 (match_operand:SF 2 "gpc_reg_operand" "")))]
4559 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4560 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4561 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4562 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4564 [(set_attr "type" "sdiv")])
4567 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4568 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4569 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4570 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4571 "{fd|fdiv} %0,%1,%2"
4572 [(set_attr "type" "ddiv")])
4575 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4576 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4577 (match_operand:SF 2 "gpc_reg_operand" "f"))
4578 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4579 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4580 "fmadds %0,%1,%2,%3"
4581 [(set_attr "type" "fp")])
4584 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4585 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4586 (match_operand:SF 2 "gpc_reg_operand" "f"))
4587 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4588 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4589 "{fma|fmadd} %0,%1,%2,%3"
4590 [(set_attr "type" "dmul")])
4593 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4594 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4595 (match_operand:SF 2 "gpc_reg_operand" "f"))
4596 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4597 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4598 "fmsubs %0,%1,%2,%3"
4599 [(set_attr "type" "fp")])
4602 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4603 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4604 (match_operand:SF 2 "gpc_reg_operand" "f"))
4605 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4606 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4607 "{fms|fmsub} %0,%1,%2,%3"
4608 [(set_attr "type" "dmul")])
4611 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4612 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4613 (match_operand:SF 2 "gpc_reg_operand" "f"))
4614 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4615 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4616 && HONOR_SIGNED_ZEROS (SFmode)"
4617 "fnmadds %0,%1,%2,%3"
4618 [(set_attr "type" "fp")])
4621 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4622 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4623 (match_operand:SF 2 "gpc_reg_operand" "f"))
4624 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4625 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4626 && ! HONOR_SIGNED_ZEROS (SFmode)"
4627 "fnmadds %0,%1,%2,%3"
4628 [(set_attr "type" "fp")])
4631 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4632 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4633 (match_operand:SF 2 "gpc_reg_operand" "f"))
4634 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4635 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4636 "{fnma|fnmadd} %0,%1,%2,%3"
4637 [(set_attr "type" "dmul")])
4640 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4641 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4642 (match_operand:SF 2 "gpc_reg_operand" "f"))
4643 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4644 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4645 && ! HONOR_SIGNED_ZEROS (SFmode)"
4646 "{fnma|fnmadd} %0,%1,%2,%3"
4647 [(set_attr "type" "dmul")])
4650 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4651 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4652 (match_operand:SF 2 "gpc_reg_operand" "f"))
4653 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4654 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4655 && HONOR_SIGNED_ZEROS (SFmode)"
4656 "fnmsubs %0,%1,%2,%3"
4657 [(set_attr "type" "fp")])
4660 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4661 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4662 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4663 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4664 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4665 && ! HONOR_SIGNED_ZEROS (SFmode)"
4666 "fnmsubs %0,%1,%2,%3"
4667 [(set_attr "type" "fp")])
4670 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4671 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4672 (match_operand:SF 2 "gpc_reg_operand" "f"))
4673 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4674 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4675 "{fnms|fnmsub} %0,%1,%2,%3"
4676 [(set_attr "type" "dmul")])
4679 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4680 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4681 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4682 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4683 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4684 && ! HONOR_SIGNED_ZEROS (SFmode)"
4685 "{fnms|fnmsub} %0,%1,%2,%3"
4686 [(set_attr "type" "fp")])
4688 (define_expand "sqrtsf2"
4689 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4690 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4691 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4695 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4696 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4697 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4699 [(set_attr "type" "ssqrt")])
4702 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4703 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4704 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4706 [(set_attr "type" "dsqrt")])
4708 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4709 ;; fsel instruction and some auxiliary computations. Then we just have a
4710 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4712 (define_expand "maxsf3"
4713 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4714 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4715 (match_operand:SF 2 "gpc_reg_operand" ""))
4718 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4719 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4721 (define_expand "minsf3"
4722 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4723 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4724 (match_operand:SF 2 "gpc_reg_operand" ""))
4727 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4728 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4731 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4732 (match_operator:SF 3 "min_max_operator"
4733 [(match_operand:SF 1 "gpc_reg_operand" "")
4734 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4735 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4738 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4739 operands[1], operands[2]);
4743 (define_expand "movsicc"
4744 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4745 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4746 (match_operand:SI 2 "gpc_reg_operand" "")
4747 (match_operand:SI 3 "gpc_reg_operand" "")))]
4751 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4757 ;; We use the BASE_REGS for the isel input operands because, if rA is
4758 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4759 ;; because we may switch the operands and rB may end up being rA.
4761 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4762 ;; leave out the mode in operand 4 and use one pattern, but reload can
4763 ;; change the mode underneath our feet and then gets confused trying
4764 ;; to reload the value.
4765 (define_insn "isel_signed"
4766 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4768 (match_operator 1 "comparison_operator"
4769 [(match_operand:CC 4 "cc_reg_operand" "y")
4771 (match_operand:SI 2 "gpc_reg_operand" "b")
4772 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4775 { return output_isel (operands); }"
4776 [(set_attr "length" "4")])
4778 (define_insn "isel_unsigned"
4779 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4781 (match_operator 1 "comparison_operator"
4782 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4784 (match_operand:SI 2 "gpc_reg_operand" "b")
4785 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4788 { return output_isel (operands); }"
4789 [(set_attr "length" "4")])
4791 (define_expand "movsfcc"
4792 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4793 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4794 (match_operand:SF 2 "gpc_reg_operand" "")
4795 (match_operand:SF 3 "gpc_reg_operand" "")))]
4796 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4799 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4805 (define_insn "*fselsfsf4"
4806 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4807 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4808 (match_operand:SF 4 "zero_fp_constant" "F"))
4809 (match_operand:SF 2 "gpc_reg_operand" "f")
4810 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4811 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4813 [(set_attr "type" "fp")])
4815 (define_insn "*fseldfsf4"
4816 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4817 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4818 (match_operand:DF 4 "zero_fp_constant" "F"))
4819 (match_operand:SF 2 "gpc_reg_operand" "f")
4820 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4821 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4823 [(set_attr "type" "fp")])
4825 (define_expand "negdf2"
4826 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4827 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4828 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4831 (define_insn "*negdf2_fpr"
4832 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4833 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4834 "TARGET_HARD_FLOAT && TARGET_FPRS"
4836 [(set_attr "type" "fp")])
4838 (define_expand "absdf2"
4839 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4840 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4841 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4844 (define_insn "*absdf2_fpr"
4845 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4846 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4847 "TARGET_HARD_FLOAT && TARGET_FPRS"
4849 [(set_attr "type" "fp")])
4851 (define_insn "*nabsdf2_fpr"
4852 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4853 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4854 "TARGET_HARD_FLOAT && TARGET_FPRS"
4856 [(set_attr "type" "fp")])
4858 (define_expand "adddf3"
4859 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4860 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4861 (match_operand:DF 2 "gpc_reg_operand" "")))]
4862 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4865 (define_insn "*adddf3_fpr"
4866 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4867 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4868 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4869 "TARGET_HARD_FLOAT && TARGET_FPRS"
4870 "{fa|fadd} %0,%1,%2"
4871 [(set_attr "type" "fp")])
4873 (define_expand "subdf3"
4874 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4875 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4876 (match_operand:DF 2 "gpc_reg_operand" "")))]
4877 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4880 (define_insn "*subdf3_fpr"
4881 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4882 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4883 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4884 "TARGET_HARD_FLOAT && TARGET_FPRS"
4885 "{fs|fsub} %0,%1,%2"
4886 [(set_attr "type" "fp")])
4888 (define_expand "muldf3"
4889 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4890 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4891 (match_operand:DF 2 "gpc_reg_operand" "")))]
4892 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4895 (define_insn "*muldf3_fpr"
4896 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4897 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4898 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4899 "TARGET_HARD_FLOAT && TARGET_FPRS"
4900 "{fm|fmul} %0,%1,%2"
4901 [(set_attr "type" "dmul")])
4903 (define_expand "divdf3"
4904 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4905 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4906 (match_operand:DF 2 "gpc_reg_operand" "")))]
4907 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4910 (define_insn "*divdf3_fpr"
4911 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4912 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4913 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4914 "TARGET_HARD_FLOAT && TARGET_FPRS"
4915 "{fd|fdiv} %0,%1,%2"
4916 [(set_attr "type" "ddiv")])
4919 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4920 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4921 (match_operand:DF 2 "gpc_reg_operand" "f"))
4922 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4923 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4924 "{fma|fmadd} %0,%1,%2,%3"
4925 [(set_attr "type" "dmul")])
4928 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4929 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4930 (match_operand:DF 2 "gpc_reg_operand" "f"))
4931 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4932 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4933 "{fms|fmsub} %0,%1,%2,%3"
4934 [(set_attr "type" "dmul")])
4937 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4938 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4939 (match_operand:DF 2 "gpc_reg_operand" "f"))
4940 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4941 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4942 && HONOR_SIGNED_ZEROS (DFmode)"
4943 "{fnma|fnmadd} %0,%1,%2,%3"
4944 [(set_attr "type" "dmul")])
4947 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4948 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4949 (match_operand:DF 2 "gpc_reg_operand" "f"))
4950 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4951 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4952 && ! HONOR_SIGNED_ZEROS (DFmode)"
4953 "{fnma|fnmadd} %0,%1,%2,%3"
4954 [(set_attr "type" "dmul")])
4957 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4958 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4959 (match_operand:DF 2 "gpc_reg_operand" "f"))
4960 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4961 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4962 && HONOR_SIGNED_ZEROS (DFmode)"
4963 "{fnms|fnmsub} %0,%1,%2,%3"
4964 [(set_attr "type" "dmul")])
4967 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4968 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4969 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4970 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4971 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4972 && ! HONOR_SIGNED_ZEROS (DFmode)"
4973 "{fnms|fnmsub} %0,%1,%2,%3"
4974 [(set_attr "type" "dmul")])
4976 (define_insn "sqrtdf2"
4977 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4978 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4979 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4981 [(set_attr "type" "dsqrt")])
4983 ;; The conditional move instructions allow us to perform max and min
4984 ;; operations even when
4986 (define_expand "maxdf3"
4987 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4988 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4989 (match_operand:DF 2 "gpc_reg_operand" ""))
4992 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4993 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4995 (define_expand "mindf3"
4996 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4997 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4998 (match_operand:DF 2 "gpc_reg_operand" ""))
5001 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5002 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5005 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5006 (match_operator:DF 3 "min_max_operator"
5007 [(match_operand:DF 1 "gpc_reg_operand" "")
5008 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5009 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5012 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5013 operands[1], operands[2]);
5017 (define_expand "movdfcc"
5018 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5019 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5020 (match_operand:DF 2 "gpc_reg_operand" "")
5021 (match_operand:DF 3 "gpc_reg_operand" "")))]
5022 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5025 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5031 (define_insn "*fseldfdf4"
5032 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5033 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5034 (match_operand:DF 4 "zero_fp_constant" "F"))
5035 (match_operand:DF 2 "gpc_reg_operand" "f")
5036 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5037 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5039 [(set_attr "type" "fp")])
5041 (define_insn "*fselsfdf4"
5042 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5043 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5044 (match_operand:SF 4 "zero_fp_constant" "F"))
5045 (match_operand:DF 2 "gpc_reg_operand" "f")
5046 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5049 [(set_attr "type" "fp")])
5051 ;; Conversions to and from floating-point.
5053 (define_expand "fixuns_truncsfsi2"
5054 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5055 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5056 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5059 (define_expand "fix_truncsfsi2"
5060 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5061 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5062 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5065 ; For each of these conversions, there is a define_expand, a define_insn
5066 ; with a '#' template, and a define_split (with C code). The idea is
5067 ; to allow constant folding with the template of the define_insn,
5068 ; then to have the insns split later (between sched1 and final).
5070 (define_expand "floatsidf2"
5071 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5072 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5075 (clobber (match_dup 4))
5076 (clobber (match_dup 5))
5077 (clobber (match_dup 6))])]
5078 "TARGET_HARD_FLOAT && TARGET_FPRS"
5081 if (TARGET_E500_DOUBLE)
5083 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5086 if (TARGET_POWERPC64)
5088 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5089 rtx t1 = gen_reg_rtx (DImode);
5090 rtx t2 = gen_reg_rtx (DImode);
5091 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5095 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5096 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5097 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5098 operands[5] = gen_reg_rtx (DFmode);
5099 operands[6] = gen_reg_rtx (SImode);
5102 (define_insn "*floatsidf2_internal"
5103 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5104 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5105 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5106 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5107 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5108 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5109 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5110 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5112 [(set_attr "length" "24")])
5115 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5116 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5117 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5118 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5119 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5120 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5121 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5122 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5123 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5124 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5125 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5126 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5127 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5128 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5129 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5132 rtx lowword, highword;
5133 if (GET_CODE (operands[4]) != MEM)
5135 highword = XEXP (operands[4], 0);
5136 lowword = plus_constant (highword, 4);
5137 if (! WORDS_BIG_ENDIAN)
5140 tmp = highword; highword = lowword; lowword = tmp;
5143 emit_insn (gen_xorsi3 (operands[6], operands[1],
5144 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5145 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5146 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5147 emit_move_insn (operands[5], operands[4]);
5148 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5152 (define_expand "floatunssisf2"
5153 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5154 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5155 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5158 (define_expand "floatunssidf2"
5159 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5160 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5163 (clobber (match_dup 4))
5164 (clobber (match_dup 5))])]
5165 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5168 if (TARGET_E500_DOUBLE)
5170 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5173 if (TARGET_POWERPC64)
5175 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5176 rtx t1 = gen_reg_rtx (DImode);
5177 rtx t2 = gen_reg_rtx (DImode);
5178 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5183 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5184 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5185 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5186 operands[5] = gen_reg_rtx (DFmode);
5189 (define_insn "*floatunssidf2_internal"
5190 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5191 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5192 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5193 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5194 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5195 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5196 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5198 [(set_attr "length" "20")])
5201 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5202 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5203 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5204 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5205 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5206 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5207 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5208 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5209 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5210 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5211 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5212 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5213 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5216 rtx lowword, highword;
5217 if (GET_CODE (operands[4]) != MEM)
5219 highword = XEXP (operands[4], 0);
5220 lowword = plus_constant (highword, 4);
5221 if (! WORDS_BIG_ENDIAN)
5224 tmp = highword; highword = lowword; lowword = tmp;
5227 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5228 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5229 emit_move_insn (operands[5], operands[4]);
5230 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5234 (define_expand "fix_truncdfsi2"
5235 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5236 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5237 (clobber (match_dup 2))
5238 (clobber (match_dup 3))])]
5239 "(TARGET_POWER2 || TARGET_POWERPC)
5240 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5243 if (TARGET_E500_DOUBLE)
5245 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5248 operands[2] = gen_reg_rtx (DImode);
5249 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5252 (define_insn "*fix_truncdfsi2_internal"
5253 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5254 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5255 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5256 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5257 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5259 [(set_attr "length" "16")])
5262 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5263 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5264 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5265 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5266 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5267 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5268 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5269 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5270 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5274 if (GET_CODE (operands[3]) != MEM)
5276 lowword = XEXP (operands[3], 0);
5277 if (WORDS_BIG_ENDIAN)
5278 lowword = plus_constant (lowword, 4);
5280 emit_insn (gen_fctiwz (operands[2], operands[1]));
5281 emit_move_insn (operands[3], operands[2]);
5282 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5286 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5287 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5288 ; because the first makes it clear that operand 0 is not live
5289 ; before the instruction.
5290 (define_insn "fctiwz"
5291 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5292 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5294 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5295 "{fcirz|fctiwz} %0,%1"
5296 [(set_attr "type" "fp")])
5298 (define_expand "floatsisf2"
5299 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5300 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5301 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5304 (define_insn "floatdidf2"
5305 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5306 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5307 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5309 [(set_attr "type" "fp")])
5311 (define_insn_and_split "floatsidf_ppc64"
5312 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5313 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5314 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5315 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5316 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5317 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5320 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5321 (set (match_dup 2) (match_dup 3))
5322 (set (match_dup 4) (match_dup 2))
5323 (set (match_dup 0) (float:DF (match_dup 4)))]
5326 (define_insn_and_split "floatunssidf_ppc64"
5327 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5328 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5329 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5330 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5331 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5332 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5335 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5336 (set (match_dup 2) (match_dup 3))
5337 (set (match_dup 4) (match_dup 2))
5338 (set (match_dup 0) (float:DF (match_dup 4)))]
5341 (define_insn "fix_truncdfdi2"
5342 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5343 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5344 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5346 [(set_attr "type" "fp")])
5348 (define_expand "floatdisf2"
5349 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5350 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5351 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5354 rtx val = operands[1];
5355 if (!flag_unsafe_math_optimizations)
5357 rtx label = gen_label_rtx ();
5358 val = gen_reg_rtx (DImode);
5359 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5362 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5366 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5367 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5368 ;; from double rounding.
5369 (define_insn_and_split "floatdisf2_internal1"
5370 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5371 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5372 (clobber (match_scratch:DF 2 "=f"))]
5373 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5375 "&& reload_completed"
5377 (float:DF (match_dup 1)))
5379 (float_truncate:SF (match_dup 2)))]
5382 ;; Twiddles bits to avoid double rounding.
5383 ;; Bits that might be truncated when converting to DFmode are replaced
5384 ;; by a bit that won't be lost at that stage, but is below the SFmode
5385 ;; rounding position.
5386 (define_expand "floatdisf2_internal2"
5387 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5389 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5391 (clobber (scratch:CC))])
5392 (set (match_dup 3) (plus:DI (match_dup 3)
5394 (set (match_dup 0) (plus:DI (match_dup 0)
5396 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5398 (set (match_dup 0) (ior:DI (match_dup 0)
5400 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5402 (clobber (scratch:CC))])
5403 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5404 (label_ref (match_operand:DI 2 "" ""))
5406 (set (match_dup 0) (match_dup 1))]
5407 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5410 operands[3] = gen_reg_rtx (DImode);
5411 operands[4] = gen_reg_rtx (CCUNSmode);
5414 ;; Define the DImode operations that can be done in a small number
5415 ;; of instructions. The & constraints are to prevent the register
5416 ;; allocator from allocating registers that overlap with the inputs
5417 ;; (for example, having an input in 7,8 and an output in 6,7). We
5418 ;; also allow for the output being the same as one of the inputs.
5420 (define_insn "*adddi3_noppc64"
5421 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5422 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5423 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5424 "! TARGET_POWERPC64"
5427 if (WORDS_BIG_ENDIAN)
5428 return (GET_CODE (operands[2])) != CONST_INT
5429 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5430 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5432 return (GET_CODE (operands[2])) != CONST_INT
5433 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5434 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5436 [(set_attr "type" "two")
5437 (set_attr "length" "8")])
5439 (define_insn "*subdi3_noppc64"
5440 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5441 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5442 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5443 "! TARGET_POWERPC64"
5446 if (WORDS_BIG_ENDIAN)
5447 return (GET_CODE (operands[1]) != CONST_INT)
5448 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5449 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5451 return (GET_CODE (operands[1]) != CONST_INT)
5452 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5453 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5455 [(set_attr "type" "two")
5456 (set_attr "length" "8")])
5458 (define_insn "*negdi2_noppc64"
5459 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5460 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5461 "! TARGET_POWERPC64"
5464 return (WORDS_BIG_ENDIAN)
5465 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5466 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5468 [(set_attr "type" "two")
5469 (set_attr "length" "8")])
5471 (define_expand "mulsidi3"
5472 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5473 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5474 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5475 "! TARGET_POWERPC64"
5478 if (! TARGET_POWER && ! TARGET_POWERPC)
5480 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5481 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5482 emit_insn (gen_mull_call ());
5483 if (WORDS_BIG_ENDIAN)
5484 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5487 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5488 gen_rtx_REG (SImode, 3));
5489 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5490 gen_rtx_REG (SImode, 4));
5494 else if (TARGET_POWER)
5496 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5501 (define_insn "mulsidi3_mq"
5502 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5503 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5504 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5505 (clobber (match_scratch:SI 3 "=q"))]
5507 "mul %0,%1,%2\;mfmq %L0"
5508 [(set_attr "type" "imul")
5509 (set_attr "length" "8")])
5511 (define_insn "*mulsidi3_no_mq"
5512 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5513 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5514 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5515 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5518 return (WORDS_BIG_ENDIAN)
5519 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5520 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5522 [(set_attr "type" "imul")
5523 (set_attr "length" "8")])
5526 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5527 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5528 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5529 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5532 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5533 (sign_extend:DI (match_dup 2)))
5536 (mult:SI (match_dup 1)
5540 int endian = (WORDS_BIG_ENDIAN == 0);
5541 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5542 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5545 (define_expand "umulsidi3"
5546 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5547 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5548 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5549 "TARGET_POWERPC && ! TARGET_POWERPC64"
5554 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5559 (define_insn "umulsidi3_mq"
5560 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5561 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5562 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5563 (clobber (match_scratch:SI 3 "=q"))]
5564 "TARGET_POWERPC && TARGET_POWER"
5567 return (WORDS_BIG_ENDIAN)
5568 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5569 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5571 [(set_attr "type" "imul")
5572 (set_attr "length" "8")])
5574 (define_insn "*umulsidi3_no_mq"
5575 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5576 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5577 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5578 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5581 return (WORDS_BIG_ENDIAN)
5582 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5583 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5585 [(set_attr "type" "imul")
5586 (set_attr "length" "8")])
5589 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5590 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5591 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5592 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5595 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5596 (zero_extend:DI (match_dup 2)))
5599 (mult:SI (match_dup 1)
5603 int endian = (WORDS_BIG_ENDIAN == 0);
5604 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5605 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5608 (define_expand "smulsi3_highpart"
5609 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5611 (lshiftrt:DI (mult:DI (sign_extend:DI
5612 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5614 (match_operand:SI 2 "gpc_reg_operand" "r")))
5619 if (! TARGET_POWER && ! TARGET_POWERPC)
5621 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5622 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5623 emit_insn (gen_mulh_call ());
5624 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5627 else if (TARGET_POWER)
5629 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5634 (define_insn "smulsi3_highpart_mq"
5635 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5637 (lshiftrt:DI (mult:DI (sign_extend:DI
5638 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5640 (match_operand:SI 2 "gpc_reg_operand" "r")))
5642 (clobber (match_scratch:SI 3 "=q"))]
5645 [(set_attr "type" "imul")])
5647 (define_insn "*smulsi3_highpart_no_mq"
5648 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5650 (lshiftrt:DI (mult:DI (sign_extend:DI
5651 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5653 (match_operand:SI 2 "gpc_reg_operand" "r")))
5655 "TARGET_POWERPC && ! TARGET_POWER"
5657 [(set_attr "type" "imul")])
5659 (define_expand "umulsi3_highpart"
5660 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5662 (lshiftrt:DI (mult:DI (zero_extend:DI
5663 (match_operand:SI 1 "gpc_reg_operand" ""))
5665 (match_operand:SI 2 "gpc_reg_operand" "")))
5672 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5677 (define_insn "umulsi3_highpart_mq"
5678 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5680 (lshiftrt:DI (mult:DI (zero_extend:DI
5681 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5683 (match_operand:SI 2 "gpc_reg_operand" "r")))
5685 (clobber (match_scratch:SI 3 "=q"))]
5686 "TARGET_POWERPC && TARGET_POWER"
5688 [(set_attr "type" "imul")])
5690 (define_insn "*umulsi3_highpart_no_mq"
5691 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5693 (lshiftrt:DI (mult:DI (zero_extend:DI
5694 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5696 (match_operand:SI 2 "gpc_reg_operand" "r")))
5698 "TARGET_POWERPC && ! TARGET_POWER"
5700 [(set_attr "type" "imul")])
5702 ;; If operands 0 and 2 are in the same register, we have a problem. But
5703 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5704 ;; why we have the strange constraints below.
5705 (define_insn "ashldi3_power"
5706 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5707 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5708 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5709 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5712 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5713 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5714 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5715 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5716 [(set_attr "length" "8")])
5718 (define_insn "lshrdi3_power"
5719 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5720 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5721 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5722 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5725 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5726 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5727 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5728 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5729 [(set_attr "length" "8")])
5731 ;; Shift by a variable amount is too complex to be worth open-coding. We
5732 ;; just handle shifts by constants.
5733 (define_insn "ashrdi3_power"
5734 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5735 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5736 (match_operand:SI 2 "const_int_operand" "M,i")))
5737 (clobber (match_scratch:SI 3 "=X,q"))]
5740 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5741 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5742 [(set_attr "length" "8")])
5744 (define_insn "ashrdi3_no_power"
5745 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5746 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5747 (match_operand:SI 2 "const_int_operand" "M,i")))]
5748 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5750 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5751 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5752 [(set_attr "type" "two,three")
5753 (set_attr "length" "8,12")])
5755 (define_insn "*ashrdisi3_noppc64"
5756 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5757 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5758 (const_int 32)) 4))]
5759 "TARGET_32BIT && !TARGET_POWERPC64"
5762 if (REGNO (operands[0]) == REGNO (operands[1]))
5765 return \"mr %0,%1\";
5767 [(set_attr "length" "4")])
5770 ;; PowerPC64 DImode operations.
5772 (define_expand "adddi3"
5773 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5774 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5775 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5779 if (! TARGET_POWERPC64)
5781 if (non_short_cint_operand (operands[2], DImode))
5785 if (GET_CODE (operands[2]) == CONST_INT
5786 && ! add_operand (operands[2], DImode))
5788 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5789 ? operands[0] : gen_reg_rtx (DImode));
5791 HOST_WIDE_INT val = INTVAL (operands[2]);
5792 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5793 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5795 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5798 /* The ordering here is important for the prolog expander.
5799 When space is allocated from the stack, adding 'low' first may
5800 produce a temporary deallocation (which would be bad). */
5801 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5802 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5807 ;; Discourage ai/addic because of carry but provide it in an alternative
5808 ;; allowing register zero as source.
5810 (define_insn "*adddi3_internal1"
5811 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5812 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5813 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5821 (define_insn "*adddi3_internal2"
5822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5823 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5824 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5826 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5833 [(set_attr "type" "fast_compare,compare,compare,compare")
5834 (set_attr "length" "4,4,8,8")])
5837 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5838 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5839 (match_operand:DI 2 "reg_or_short_operand" ""))
5841 (clobber (match_scratch:DI 3 ""))]
5842 "TARGET_POWERPC64 && reload_completed"
5844 (plus:DI (match_dup 1) (match_dup 2)))
5846 (compare:CC (match_dup 3)
5850 (define_insn "*adddi3_internal3"
5851 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5852 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5853 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5855 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5856 (plus:DI (match_dup 1) (match_dup 2)))]
5863 [(set_attr "type" "fast_compare,compare,compare,compare")
5864 (set_attr "length" "4,4,8,8")])
5867 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5868 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5869 (match_operand:DI 2 "reg_or_short_operand" ""))
5871 (set (match_operand:DI 0 "gpc_reg_operand" "")
5872 (plus:DI (match_dup 1) (match_dup 2)))]
5873 "TARGET_POWERPC64 && reload_completed"
5875 (plus:DI (match_dup 1) (match_dup 2)))
5877 (compare:CC (match_dup 0)
5881 ;; Split an add that we can't do in one insn into two insns, each of which
5882 ;; does one 16-bit part. This is used by combine. Note that the low-order
5883 ;; add should be last in case the result gets used in an address.
5886 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5887 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5888 (match_operand:DI 2 "non_add_cint_operand" "")))]
5890 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5891 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5894 HOST_WIDE_INT val = INTVAL (operands[2]);
5895 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5896 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5898 operands[4] = GEN_INT (low);
5899 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5900 operands[3] = GEN_INT (rest);
5901 else if (! no_new_pseudos)
5903 operands[3] = gen_reg_rtx (DImode);
5904 emit_move_insn (operands[3], operands[2]);
5905 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5912 (define_insn "one_cmpldi2"
5913 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5914 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5919 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5920 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5922 (clobber (match_scratch:DI 2 "=r,r"))]
5927 [(set_attr "type" "compare")
5928 (set_attr "length" "4,8")])
5931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5932 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5934 (clobber (match_scratch:DI 2 ""))]
5935 "TARGET_POWERPC64 && reload_completed"
5937 (not:DI (match_dup 1)))
5939 (compare:CC (match_dup 2)
5944 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5945 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5947 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5948 (not:DI (match_dup 1)))]
5953 [(set_attr "type" "compare")
5954 (set_attr "length" "4,8")])
5957 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5958 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5960 (set (match_operand:DI 0 "gpc_reg_operand" "")
5961 (not:DI (match_dup 1)))]
5962 "TARGET_POWERPC64 && reload_completed"
5964 (not:DI (match_dup 1)))
5966 (compare:CC (match_dup 0)
5971 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5972 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5973 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5980 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5981 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5982 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5984 (clobber (match_scratch:DI 3 "=r,r"))]
5989 [(set_attr "type" "fast_compare")
5990 (set_attr "length" "4,8")])
5993 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5994 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5995 (match_operand:DI 2 "gpc_reg_operand" ""))
5997 (clobber (match_scratch:DI 3 ""))]
5998 "TARGET_POWERPC64 && reload_completed"
6000 (minus:DI (match_dup 1) (match_dup 2)))
6002 (compare:CC (match_dup 3)
6007 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6008 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6009 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6011 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6012 (minus:DI (match_dup 1) (match_dup 2)))]
6017 [(set_attr "type" "fast_compare")
6018 (set_attr "length" "4,8")])
6021 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6022 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6023 (match_operand:DI 2 "gpc_reg_operand" ""))
6025 (set (match_operand:DI 0 "gpc_reg_operand" "")
6026 (minus:DI (match_dup 1) (match_dup 2)))]
6027 "TARGET_POWERPC64 && reload_completed"
6029 (minus:DI (match_dup 1) (match_dup 2)))
6031 (compare:CC (match_dup 0)
6035 (define_expand "subdi3"
6036 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6037 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
6038 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
6042 if (GET_CODE (operands[2]) == CONST_INT)
6044 emit_insn (gen_adddi3 (operands[0], operands[1],
6045 negate_rtx (DImode, operands[2])));
6050 (define_insn_and_split "absdi2"
6051 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6052 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6053 (clobber (match_scratch:DI 2 "=&r,&r"))]
6056 "&& reload_completed"
6057 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6058 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6059 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6062 (define_insn_and_split "*nabsdi2"
6063 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6064 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6065 (clobber (match_scratch:DI 2 "=&r,&r"))]
6068 "&& reload_completed"
6069 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6070 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6071 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6074 (define_expand "negdi2"
6075 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6076 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
6081 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6082 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6087 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6088 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6090 (clobber (match_scratch:DI 2 "=r,r"))]
6095 [(set_attr "type" "fast_compare")
6096 (set_attr "length" "4,8")])
6099 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6100 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6102 (clobber (match_scratch:DI 2 ""))]
6103 "TARGET_POWERPC64 && reload_completed"
6105 (neg:DI (match_dup 1)))
6107 (compare:CC (match_dup 2)
6112 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6113 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6115 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6116 (neg:DI (match_dup 1)))]
6121 [(set_attr "type" "fast_compare")
6122 (set_attr "length" "4,8")])
6125 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6126 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6128 (set (match_operand:DI 0 "gpc_reg_operand" "")
6129 (neg:DI (match_dup 1)))]
6130 "TARGET_POWERPC64 && reload_completed"
6132 (neg:DI (match_dup 1)))
6134 (compare:CC (match_dup 0)
6138 (define_insn "clzdi2"
6139 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6140 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6144 (define_expand "ctzdi2"
6146 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6147 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6149 (clobber (scratch:CC))])
6150 (set (match_dup 4) (clz:DI (match_dup 3)))
6151 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6152 (minus:DI (const_int 63) (match_dup 4)))]
6155 operands[2] = gen_reg_rtx (DImode);
6156 operands[3] = gen_reg_rtx (DImode);
6157 operands[4] = gen_reg_rtx (DImode);
6160 (define_expand "ffsdi2"
6162 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6163 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6165 (clobber (scratch:CC))])
6166 (set (match_dup 4) (clz:DI (match_dup 3)))
6167 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6168 (minus:DI (const_int 64) (match_dup 4)))]
6171 operands[2] = gen_reg_rtx (DImode);
6172 operands[3] = gen_reg_rtx (DImode);
6173 operands[4] = gen_reg_rtx (DImode);
6176 (define_insn "muldi3"
6177 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6178 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6179 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6182 [(set_attr "type" "lmul")])
6184 (define_insn "*muldi3_internal1"
6185 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6186 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6187 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6189 (clobber (match_scratch:DI 3 "=r,r"))]
6194 [(set_attr "type" "lmul_compare")
6195 (set_attr "length" "4,8")])
6198 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6199 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6200 (match_operand:DI 2 "gpc_reg_operand" ""))
6202 (clobber (match_scratch:DI 3 ""))]
6203 "TARGET_POWERPC64 && reload_completed"
6205 (mult:DI (match_dup 1) (match_dup 2)))
6207 (compare:CC (match_dup 3)
6211 (define_insn "*muldi3_internal2"
6212 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6213 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6214 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6216 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6217 (mult:DI (match_dup 1) (match_dup 2)))]
6222 [(set_attr "type" "lmul_compare")
6223 (set_attr "length" "4,8")])
6226 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6227 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6228 (match_operand:DI 2 "gpc_reg_operand" ""))
6230 (set (match_operand:DI 0 "gpc_reg_operand" "")
6231 (mult:DI (match_dup 1) (match_dup 2)))]
6232 "TARGET_POWERPC64 && reload_completed"
6234 (mult:DI (match_dup 1) (match_dup 2)))
6236 (compare:CC (match_dup 0)
6240 (define_insn "smuldi3_highpart"
6241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6243 (lshiftrt:TI (mult:TI (sign_extend:TI
6244 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6246 (match_operand:DI 2 "gpc_reg_operand" "r")))
6250 [(set_attr "type" "lmul")])
6252 (define_insn "umuldi3_highpart"
6253 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6255 (lshiftrt:TI (mult:TI (zero_extend:TI
6256 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6258 (match_operand:DI 2 "gpc_reg_operand" "r")))
6262 [(set_attr "type" "lmul")])
6264 (define_expand "divdi3"
6265 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6266 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6267 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6271 if (GET_CODE (operands[2]) == CONST_INT
6272 && INTVAL (operands[2]) > 0
6273 && exact_log2 (INTVAL (operands[2])) >= 0)
6276 operands[2] = force_reg (DImode, operands[2]);
6279 (define_expand "moddi3"
6280 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6281 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6282 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6290 if (GET_CODE (operands[2]) != CONST_INT
6291 || INTVAL (operands[2]) <= 0
6292 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6295 temp1 = gen_reg_rtx (DImode);
6296 temp2 = gen_reg_rtx (DImode);
6298 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6299 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6300 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6306 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6307 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6309 "sradi %0,%1,%p2\;addze %0,%0"
6310 [(set_attr "type" "two")
6311 (set_attr "length" "8")])
6314 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6315 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6316 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6318 (clobber (match_scratch:DI 3 "=r,r"))]
6321 sradi %3,%1,%p2\;addze. %3,%3
6323 [(set_attr "type" "compare")
6324 (set_attr "length" "8,12")])
6327 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6328 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6329 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6331 (clobber (match_scratch:DI 3 ""))]
6332 "TARGET_POWERPC64 && reload_completed"
6334 (div:DI (match_dup 1) (match_dup 2)))
6336 (compare:CC (match_dup 3)
6341 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6342 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6343 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6345 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6346 (div:DI (match_dup 1) (match_dup 2)))]
6349 sradi %0,%1,%p2\;addze. %0,%0
6351 [(set_attr "type" "compare")
6352 (set_attr "length" "8,12")])
6355 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6356 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6357 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6359 (set (match_operand:DI 0 "gpc_reg_operand" "")
6360 (div:DI (match_dup 1) (match_dup 2)))]
6361 "TARGET_POWERPC64 && reload_completed"
6363 (div:DI (match_dup 1) (match_dup 2)))
6365 (compare:CC (match_dup 0)
6370 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6371 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6372 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6375 [(set_attr "type" "ldiv")])
6377 (define_insn "udivdi3"
6378 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6379 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6380 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6383 [(set_attr "type" "ldiv")])
6385 (define_insn "rotldi3"
6386 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6387 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6388 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6390 "rld%I2cl %0,%1,%H2,0")
6392 (define_insn "*rotldi3_internal2"
6393 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6394 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6395 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6397 (clobber (match_scratch:DI 3 "=r,r"))]
6400 rld%I2cl. %3,%1,%H2,0
6402 [(set_attr "type" "delayed_compare")
6403 (set_attr "length" "4,8")])
6406 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6407 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6408 (match_operand:DI 2 "reg_or_cint_operand" ""))
6410 (clobber (match_scratch:DI 3 ""))]
6411 "TARGET_POWERPC64 && reload_completed"
6413 (rotate:DI (match_dup 1) (match_dup 2)))
6415 (compare:CC (match_dup 3)
6419 (define_insn "*rotldi3_internal3"
6420 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6421 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6422 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6424 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6425 (rotate:DI (match_dup 1) (match_dup 2)))]
6428 rld%I2cl. %0,%1,%H2,0
6430 [(set_attr "type" "delayed_compare")
6431 (set_attr "length" "4,8")])
6434 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6435 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6436 (match_operand:DI 2 "reg_or_cint_operand" ""))
6438 (set (match_operand:DI 0 "gpc_reg_operand" "")
6439 (rotate:DI (match_dup 1) (match_dup 2)))]
6440 "TARGET_POWERPC64 && reload_completed"
6442 (rotate:DI (match_dup 1) (match_dup 2)))
6444 (compare:CC (match_dup 0)
6448 (define_insn "*rotldi3_internal4"
6449 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6450 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6451 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6452 (match_operand:DI 3 "mask64_operand" "n")))]
6454 "rld%I2c%B3 %0,%1,%H2,%S3")
6456 (define_insn "*rotldi3_internal5"
6457 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6459 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6460 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6461 (match_operand:DI 3 "mask64_operand" "n,n"))
6463 (clobber (match_scratch:DI 4 "=r,r"))]
6466 rld%I2c%B3. %4,%1,%H2,%S3
6468 [(set_attr "type" "delayed_compare")
6469 (set_attr "length" "4,8")])
6472 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6474 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6475 (match_operand:DI 2 "reg_or_cint_operand" ""))
6476 (match_operand:DI 3 "mask64_operand" ""))
6478 (clobber (match_scratch:DI 4 ""))]
6479 "TARGET_POWERPC64 && reload_completed"
6481 (and:DI (rotate:DI (match_dup 1)
6485 (compare:CC (match_dup 4)
6489 (define_insn "*rotldi3_internal6"
6490 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6492 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6493 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6494 (match_operand:DI 3 "mask64_operand" "n,n"))
6496 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6497 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6500 rld%I2c%B3. %0,%1,%H2,%S3
6502 [(set_attr "type" "delayed_compare")
6503 (set_attr "length" "4,8")])
6506 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6508 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6509 (match_operand:DI 2 "reg_or_cint_operand" ""))
6510 (match_operand:DI 3 "mask64_operand" ""))
6512 (set (match_operand:DI 0 "gpc_reg_operand" "")
6513 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6514 "TARGET_POWERPC64 && reload_completed"
6516 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6518 (compare:CC (match_dup 0)
6522 (define_insn "*rotldi3_internal7"
6523 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6526 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6527 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6529 "rld%I2cl %0,%1,%H2,56")
6531 (define_insn "*rotldi3_internal8"
6532 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6533 (compare:CC (zero_extend:DI
6535 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6536 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6538 (clobber (match_scratch:DI 3 "=r,r"))]
6541 rld%I2cl. %3,%1,%H2,56
6543 [(set_attr "type" "delayed_compare")
6544 (set_attr "length" "4,8")])
6547 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6548 (compare:CC (zero_extend:DI
6550 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6551 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6553 (clobber (match_scratch:DI 3 ""))]
6554 "TARGET_POWERPC64 && reload_completed"
6556 (zero_extend:DI (subreg:QI
6557 (rotate:DI (match_dup 1)
6560 (compare:CC (match_dup 3)
6564 (define_insn "*rotldi3_internal9"
6565 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6566 (compare:CC (zero_extend:DI
6568 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6569 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6571 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6572 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6575 rld%I2cl. %0,%1,%H2,56
6577 [(set_attr "type" "delayed_compare")
6578 (set_attr "length" "4,8")])
6581 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6582 (compare:CC (zero_extend:DI
6584 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6585 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6587 (set (match_operand:DI 0 "gpc_reg_operand" "")
6588 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6589 "TARGET_POWERPC64 && reload_completed"
6591 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6593 (compare:CC (match_dup 0)
6597 (define_insn "*rotldi3_internal10"
6598 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6601 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6602 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6604 "rld%I2cl %0,%1,%H2,48")
6606 (define_insn "*rotldi3_internal11"
6607 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6608 (compare:CC (zero_extend:DI
6610 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6611 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6613 (clobber (match_scratch:DI 3 "=r,r"))]
6616 rld%I2cl. %3,%1,%H2,48
6618 [(set_attr "type" "delayed_compare")
6619 (set_attr "length" "4,8")])
6622 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6623 (compare:CC (zero_extend:DI
6625 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6626 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6628 (clobber (match_scratch:DI 3 ""))]
6629 "TARGET_POWERPC64 && reload_completed"
6631 (zero_extend:DI (subreg:HI
6632 (rotate:DI (match_dup 1)
6635 (compare:CC (match_dup 3)
6639 (define_insn "*rotldi3_internal12"
6640 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6641 (compare:CC (zero_extend:DI
6643 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6644 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6646 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6647 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6650 rld%I2cl. %0,%1,%H2,48
6652 [(set_attr "type" "delayed_compare")
6653 (set_attr "length" "4,8")])
6656 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6657 (compare:CC (zero_extend:DI
6659 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6660 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6662 (set (match_operand:DI 0 "gpc_reg_operand" "")
6663 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6664 "TARGET_POWERPC64 && reload_completed"
6666 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6668 (compare:CC (match_dup 0)
6672 (define_insn "*rotldi3_internal13"
6673 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6676 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6677 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6679 "rld%I2cl %0,%1,%H2,32")
6681 (define_insn "*rotldi3_internal14"
6682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6683 (compare:CC (zero_extend:DI
6685 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6686 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6688 (clobber (match_scratch:DI 3 "=r,r"))]
6691 rld%I2cl. %3,%1,%H2,32
6693 [(set_attr "type" "delayed_compare")
6694 (set_attr "length" "4,8")])
6697 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6698 (compare:CC (zero_extend:DI
6700 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6701 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6703 (clobber (match_scratch:DI 3 ""))]
6704 "TARGET_POWERPC64 && reload_completed"
6706 (zero_extend:DI (subreg:SI
6707 (rotate:DI (match_dup 1)
6710 (compare:CC (match_dup 3)
6714 (define_insn "*rotldi3_internal15"
6715 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6716 (compare:CC (zero_extend:DI
6718 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6719 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6721 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6722 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6725 rld%I2cl. %0,%1,%H2,32
6727 [(set_attr "type" "delayed_compare")
6728 (set_attr "length" "4,8")])
6731 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6732 (compare:CC (zero_extend:DI
6734 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6735 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6737 (set (match_operand:DI 0 "gpc_reg_operand" "")
6738 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6739 "TARGET_POWERPC64 && reload_completed"
6741 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6743 (compare:CC (match_dup 0)
6747 (define_expand "ashldi3"
6748 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6749 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6750 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6751 "TARGET_POWERPC64 || TARGET_POWER"
6754 if (TARGET_POWERPC64)
6756 else if (TARGET_POWER)
6758 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6765 (define_insn "*ashldi3_internal1"
6766 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6767 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6768 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6772 (define_insn "*ashldi3_internal2"
6773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6774 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6775 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6777 (clobber (match_scratch:DI 3 "=r,r"))]
6782 [(set_attr "type" "delayed_compare")
6783 (set_attr "length" "4,8")])
6786 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6787 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6788 (match_operand:SI 2 "reg_or_cint_operand" ""))
6790 (clobber (match_scratch:DI 3 ""))]
6791 "TARGET_POWERPC64 && reload_completed"
6793 (ashift:DI (match_dup 1) (match_dup 2)))
6795 (compare:CC (match_dup 3)
6799 (define_insn "*ashldi3_internal3"
6800 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6801 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6802 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6804 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6805 (ashift:DI (match_dup 1) (match_dup 2)))]
6810 [(set_attr "type" "delayed_compare")
6811 (set_attr "length" "4,8")])
6814 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6815 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6816 (match_operand:SI 2 "reg_or_cint_operand" ""))
6818 (set (match_operand:DI 0 "gpc_reg_operand" "")
6819 (ashift:DI (match_dup 1) (match_dup 2)))]
6820 "TARGET_POWERPC64 && reload_completed"
6822 (ashift:DI (match_dup 1) (match_dup 2)))
6824 (compare:CC (match_dup 0)
6828 (define_insn "*ashldi3_internal4"
6829 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6830 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6831 (match_operand:SI 2 "const_int_operand" "i"))
6832 (match_operand:DI 3 "const_int_operand" "n")))]
6833 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6834 "rldic %0,%1,%H2,%W3")
6836 (define_insn "ashldi3_internal5"
6837 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6839 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6840 (match_operand:SI 2 "const_int_operand" "i,i"))
6841 (match_operand:DI 3 "const_int_operand" "n,n"))
6843 (clobber (match_scratch:DI 4 "=r,r"))]
6844 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6846 rldic. %4,%1,%H2,%W3
6848 [(set_attr "type" "delayed_compare")
6849 (set_attr "length" "4,8")])
6852 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6854 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6855 (match_operand:SI 2 "const_int_operand" ""))
6856 (match_operand:DI 3 "const_int_operand" ""))
6858 (clobber (match_scratch:DI 4 ""))]
6859 "TARGET_POWERPC64 && reload_completed
6860 && includes_rldic_lshift_p (operands[2], operands[3])"
6862 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6865 (compare:CC (match_dup 4)
6869 (define_insn "*ashldi3_internal6"
6870 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6872 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6873 (match_operand:SI 2 "const_int_operand" "i,i"))
6874 (match_operand:DI 3 "const_int_operand" "n,n"))
6876 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6877 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6878 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6880 rldic. %0,%1,%H2,%W3
6882 [(set_attr "type" "delayed_compare")
6883 (set_attr "length" "4,8")])
6886 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6888 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6889 (match_operand:SI 2 "const_int_operand" ""))
6890 (match_operand:DI 3 "const_int_operand" ""))
6892 (set (match_operand:DI 0 "gpc_reg_operand" "")
6893 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6894 "TARGET_POWERPC64 && reload_completed
6895 && includes_rldic_lshift_p (operands[2], operands[3])"
6897 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6900 (compare:CC (match_dup 0)
6904 (define_insn "*ashldi3_internal7"
6905 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6906 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6907 (match_operand:SI 2 "const_int_operand" "i"))
6908 (match_operand:DI 3 "mask64_operand" "n")))]
6909 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6910 "rldicr %0,%1,%H2,%S3")
6912 (define_insn "ashldi3_internal8"
6913 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6915 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6916 (match_operand:SI 2 "const_int_operand" "i,i"))
6917 (match_operand:DI 3 "mask64_operand" "n,n"))
6919 (clobber (match_scratch:DI 4 "=r,r"))]
6920 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6922 rldicr. %4,%1,%H2,%S3
6924 [(set_attr "type" "delayed_compare")
6925 (set_attr "length" "4,8")])
6928 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6930 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6931 (match_operand:SI 2 "const_int_operand" ""))
6932 (match_operand:DI 3 "mask64_operand" ""))
6934 (clobber (match_scratch:DI 4 ""))]
6935 "TARGET_POWERPC64 && reload_completed
6936 && includes_rldicr_lshift_p (operands[2], operands[3])"
6938 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6941 (compare:CC (match_dup 4)
6945 (define_insn "*ashldi3_internal9"
6946 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6948 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6949 (match_operand:SI 2 "const_int_operand" "i,i"))
6950 (match_operand:DI 3 "mask64_operand" "n,n"))
6952 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6953 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6954 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6956 rldicr. %0,%1,%H2,%S3
6958 [(set_attr "type" "delayed_compare")
6959 (set_attr "length" "4,8")])
6962 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6964 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6965 (match_operand:SI 2 "const_int_operand" ""))
6966 (match_operand:DI 3 "mask64_operand" ""))
6968 (set (match_operand:DI 0 "gpc_reg_operand" "")
6969 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6970 "TARGET_POWERPC64 && reload_completed
6971 && includes_rldicr_lshift_p (operands[2], operands[3])"
6973 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6976 (compare:CC (match_dup 0)
6980 (define_expand "lshrdi3"
6981 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6982 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6983 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6984 "TARGET_POWERPC64 || TARGET_POWER"
6987 if (TARGET_POWERPC64)
6989 else if (TARGET_POWER)
6991 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6998 (define_insn "*lshrdi3_internal1"
6999 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7000 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7001 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7005 (define_insn "*lshrdi3_internal2"
7006 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7007 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7008 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7010 (clobber (match_scratch:DI 3 "=r,r"))]
7015 [(set_attr "type" "delayed_compare")
7016 (set_attr "length" "4,8")])
7019 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7020 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7021 (match_operand:SI 2 "reg_or_cint_operand" ""))
7023 (clobber (match_scratch:DI 3 ""))]
7024 "TARGET_POWERPC64 && reload_completed"
7026 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7028 (compare:CC (match_dup 3)
7032 (define_insn "*lshrdi3_internal3"
7033 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7034 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7035 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7037 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7038 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7043 [(set_attr "type" "delayed_compare")
7044 (set_attr "length" "4,8")])
7047 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7048 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7049 (match_operand:SI 2 "reg_or_cint_operand" ""))
7051 (set (match_operand:DI 0 "gpc_reg_operand" "")
7052 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7053 "TARGET_POWERPC64 && reload_completed"
7055 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7057 (compare:CC (match_dup 0)
7061 (define_expand "ashrdi3"
7062 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7063 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7064 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7068 if (TARGET_POWERPC64)
7070 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7072 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7075 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7076 && WORDS_BIG_ENDIAN)
7078 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7085 (define_insn "*ashrdi3_internal1"
7086 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7087 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7088 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7090 "srad%I2 %0,%1,%H2")
7092 (define_insn "*ashrdi3_internal2"
7093 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7094 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7095 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7097 (clobber (match_scratch:DI 3 "=r,r"))]
7102 [(set_attr "type" "delayed_compare")
7103 (set_attr "length" "4,8")])
7106 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7107 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7108 (match_operand:SI 2 "reg_or_cint_operand" ""))
7110 (clobber (match_scratch:DI 3 ""))]
7111 "TARGET_POWERPC64 && reload_completed"
7113 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7115 (compare:CC (match_dup 3)
7119 (define_insn "*ashrdi3_internal3"
7120 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7121 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7122 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7124 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7125 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7130 [(set_attr "type" "delayed_compare")
7131 (set_attr "length" "4,8")])
7134 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7135 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7136 (match_operand:SI 2 "reg_or_cint_operand" ""))
7138 (set (match_operand:DI 0 "gpc_reg_operand" "")
7139 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7140 "TARGET_POWERPC64 && reload_completed"
7142 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7144 (compare:CC (match_dup 0)
7148 (define_insn "anddi3"
7149 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7150 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7151 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7152 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7156 rldic%B2 %0,%1,0,%S2
7157 rlwinm %0,%1,0,%m2,%M2
7161 [(set_attr "type" "*,*,*,compare,compare,*")
7162 (set_attr "length" "4,4,4,4,4,8")])
7165 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7166 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7167 (match_operand:DI 2 "mask64_2_operand" "")))
7168 (clobber (match_scratch:CC 3 ""))]
7170 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7171 && !mask64_operand (operands[2], DImode)"
7173 (and:DI (rotate:DI (match_dup 1)
7177 (and:DI (rotate:DI (match_dup 0)
7181 build_mask64_2_operands (operands[2], &operands[4]);
7184 (define_insn "*anddi3_internal2"
7185 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7186 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7187 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7189 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7190 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7194 rldic%B2. %3,%1,0,%S2
7203 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7204 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7207 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7208 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7209 (match_operand:DI 2 "and64_operand" ""))
7211 (clobber (match_scratch:DI 3 ""))
7212 (clobber (match_scratch:CC 4 ""))]
7213 "TARGET_POWERPC64 && reload_completed"
7214 [(parallel [(set (match_dup 3)
7215 (and:DI (match_dup 1)
7217 (clobber (match_dup 4))])
7219 (compare:CC (match_dup 3)
7224 [(set (match_operand:CC 0 "cc_reg_operand" "")
7225 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7226 (match_operand:DI 2 "mask64_2_operand" ""))
7228 (clobber (match_scratch:DI 3 ""))
7229 (clobber (match_scratch:CC 4 ""))]
7230 "TARGET_POWERPC64 && reload_completed
7231 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7232 && !mask64_operand (operands[2], DImode)"
7234 (and:DI (rotate:DI (match_dup 1)
7237 (parallel [(set (match_dup 0)
7238 (compare:CC (and:DI (rotate:DI (match_dup 3)
7242 (clobber (match_dup 3))])]
7245 build_mask64_2_operands (operands[2], &operands[5]);
7248 (define_insn "*anddi3_internal3"
7249 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7250 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7251 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7253 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7254 (and:DI (match_dup 1) (match_dup 2)))
7255 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7259 rldic%B2. %0,%1,0,%S2
7268 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7269 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7272 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7273 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7274 (match_operand:DI 2 "and64_operand" ""))
7276 (set (match_operand:DI 0 "gpc_reg_operand" "")
7277 (and:DI (match_dup 1) (match_dup 2)))
7278 (clobber (match_scratch:CC 4 ""))]
7279 "TARGET_POWERPC64 && reload_completed"
7280 [(parallel [(set (match_dup 0)
7281 (and:DI (match_dup 1) (match_dup 2)))
7282 (clobber (match_dup 4))])
7284 (compare:CC (match_dup 0)
7289 [(set (match_operand:CC 3 "cc_reg_operand" "")
7290 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7291 (match_operand:DI 2 "mask64_2_operand" ""))
7293 (set (match_operand:DI 0 "gpc_reg_operand" "")
7294 (and:DI (match_dup 1) (match_dup 2)))
7295 (clobber (match_scratch:CC 4 ""))]
7296 "TARGET_POWERPC64 && reload_completed
7297 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7298 && !mask64_operand (operands[2], DImode)"
7300 (and:DI (rotate:DI (match_dup 1)
7303 (parallel [(set (match_dup 3)
7304 (compare:CC (and:DI (rotate:DI (match_dup 0)
7309 (and:DI (rotate:DI (match_dup 0)
7314 build_mask64_2_operands (operands[2], &operands[5]);
7317 (define_expand "iordi3"
7318 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7319 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7320 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7324 if (non_logical_cint_operand (operands[2], DImode))
7326 HOST_WIDE_INT value;
7327 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7328 ? operands[0] : gen_reg_rtx (DImode));
7330 if (GET_CODE (operands[2]) == CONST_INT)
7332 value = INTVAL (operands[2]);
7333 emit_insn (gen_iordi3 (tmp, operands[1],
7334 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7338 value = CONST_DOUBLE_LOW (operands[2]);
7339 emit_insn (gen_iordi3 (tmp, operands[1],
7340 immed_double_const (value
7341 & (~ (HOST_WIDE_INT) 0xffff),
7345 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7350 (define_expand "xordi3"
7351 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7352 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7353 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7357 if (non_logical_cint_operand (operands[2], DImode))
7359 HOST_WIDE_INT value;
7360 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7361 ? operands[0] : gen_reg_rtx (DImode));
7363 if (GET_CODE (operands[2]) == CONST_INT)
7365 value = INTVAL (operands[2]);
7366 emit_insn (gen_xordi3 (tmp, operands[1],
7367 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7371 value = CONST_DOUBLE_LOW (operands[2]);
7372 emit_insn (gen_xordi3 (tmp, operands[1],
7373 immed_double_const (value
7374 & (~ (HOST_WIDE_INT) 0xffff),
7378 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7383 (define_insn "*booldi3_internal1"
7384 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7385 (match_operator:DI 3 "boolean_or_operator"
7386 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7387 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7394 (define_insn "*booldi3_internal2"
7395 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7396 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7397 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7398 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7400 (clobber (match_scratch:DI 3 "=r,r"))]
7405 [(set_attr "type" "compare")
7406 (set_attr "length" "4,8")])
7409 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7410 (compare:CC (match_operator:DI 4 "boolean_operator"
7411 [(match_operand:DI 1 "gpc_reg_operand" "")
7412 (match_operand:DI 2 "gpc_reg_operand" "")])
7414 (clobber (match_scratch:DI 3 ""))]
7415 "TARGET_POWERPC64 && reload_completed"
7416 [(set (match_dup 3) (match_dup 4))
7418 (compare:CC (match_dup 3)
7422 (define_insn "*booldi3_internal3"
7423 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7424 (compare:CC (match_operator:DI 4 "boolean_operator"
7425 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7426 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7428 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7434 [(set_attr "type" "compare")
7435 (set_attr "length" "4,8")])
7438 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7439 (compare:CC (match_operator:DI 4 "boolean_operator"
7440 [(match_operand:DI 1 "gpc_reg_operand" "")
7441 (match_operand:DI 2 "gpc_reg_operand" "")])
7443 (set (match_operand:DI 0 "gpc_reg_operand" "")
7445 "TARGET_POWERPC64 && reload_completed"
7446 [(set (match_dup 0) (match_dup 4))
7448 (compare:CC (match_dup 0)
7452 ;; Split a logical operation that we can't do in one insn into two insns,
7453 ;; each of which does one 16-bit part. This is used by combine.
7456 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7457 (match_operator:DI 3 "boolean_or_operator"
7458 [(match_operand:DI 1 "gpc_reg_operand" "")
7459 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7461 [(set (match_dup 0) (match_dup 4))
7462 (set (match_dup 0) (match_dup 5))]
7467 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7469 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7470 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7472 i4 = GEN_INT (value & 0xffff);
7476 i3 = GEN_INT (INTVAL (operands[2])
7477 & (~ (HOST_WIDE_INT) 0xffff));
7478 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7480 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7482 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7486 (define_insn "*boolcdi3_internal1"
7487 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7488 (match_operator:DI 3 "boolean_operator"
7489 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7490 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7494 (define_insn "*boolcdi3_internal2"
7495 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7496 (compare:CC (match_operator:DI 4 "boolean_operator"
7497 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7498 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7500 (clobber (match_scratch:DI 3 "=r,r"))]
7505 [(set_attr "type" "compare")
7506 (set_attr "length" "4,8")])
7509 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7510 (compare:CC (match_operator:DI 4 "boolean_operator"
7511 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7512 (match_operand:DI 2 "gpc_reg_operand" "")])
7514 (clobber (match_scratch:DI 3 ""))]
7515 "TARGET_POWERPC64 && reload_completed"
7516 [(set (match_dup 3) (match_dup 4))
7518 (compare:CC (match_dup 3)
7522 (define_insn "*boolcdi3_internal3"
7523 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7524 (compare:CC (match_operator:DI 4 "boolean_operator"
7525 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7526 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7528 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7534 [(set_attr "type" "compare")
7535 (set_attr "length" "4,8")])
7538 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7539 (compare:CC (match_operator:DI 4 "boolean_operator"
7540 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7541 (match_operand:DI 2 "gpc_reg_operand" "")])
7543 (set (match_operand:DI 0 "gpc_reg_operand" "")
7545 "TARGET_POWERPC64 && reload_completed"
7546 [(set (match_dup 0) (match_dup 4))
7548 (compare:CC (match_dup 0)
7552 (define_insn "*boolccdi3_internal1"
7553 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7554 (match_operator:DI 3 "boolean_operator"
7555 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7556 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7560 (define_insn "*boolccdi3_internal2"
7561 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7562 (compare:CC (match_operator:DI 4 "boolean_operator"
7563 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7564 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7566 (clobber (match_scratch:DI 3 "=r,r"))]
7571 [(set_attr "type" "compare")
7572 (set_attr "length" "4,8")])
7575 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7576 (compare:CC (match_operator:DI 4 "boolean_operator"
7577 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7578 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7580 (clobber (match_scratch:DI 3 ""))]
7581 "TARGET_POWERPC64 && reload_completed"
7582 [(set (match_dup 3) (match_dup 4))
7584 (compare:CC (match_dup 3)
7588 (define_insn "*boolccdi3_internal3"
7589 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7590 (compare:CC (match_operator:DI 4 "boolean_operator"
7591 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7592 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7594 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7600 [(set_attr "type" "compare")
7601 (set_attr "length" "4,8")])
7604 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7605 (compare:CC (match_operator:DI 4 "boolean_operator"
7606 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7607 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7609 (set (match_operand:DI 0 "gpc_reg_operand" "")
7611 "TARGET_POWERPC64 && reload_completed"
7612 [(set (match_dup 0) (match_dup 4))
7614 (compare:CC (match_dup 0)
7618 ;; Now define ways of moving data around.
7620 ;; Elf specific ways of loading addresses for non-PIC code.
7621 ;; The output of this could be r0, but we make a very strong
7622 ;; preference for a base register because it will usually
7624 (define_insn "elf_high"
7625 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7626 (high:SI (match_operand 1 "" "")))]
7627 "TARGET_ELF && ! TARGET_64BIT"
7628 "{liu|lis} %0,%1@ha")
7630 (define_insn "elf_low"
7631 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7632 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7633 (match_operand 2 "" "")))]
7634 "TARGET_ELF && ! TARGET_64BIT"
7636 {cal|la} %0,%2@l(%1)
7637 {ai|addic} %0,%1,%K2")
7640 ;; Set up a register with a value from the GOT table
7642 (define_expand "movsi_got"
7643 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7644 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7645 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7646 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7649 if (GET_CODE (operands[1]) == CONST)
7651 rtx offset = const0_rtx;
7652 HOST_WIDE_INT value;
7654 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7655 value = INTVAL (offset);
7658 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7659 emit_insn (gen_movsi_got (tmp, operands[1]));
7660 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7665 operands[2] = rs6000_got_register (operands[1]);
7668 (define_insn "*movsi_got_internal"
7669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7670 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7671 (match_operand:SI 2 "gpc_reg_operand" "b")]
7673 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7674 "{l|lwz} %0,%a1@got(%2)"
7675 [(set_attr "type" "load")])
7677 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7678 ;; didn't get allocated to a hard register.
7680 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7681 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7682 (match_operand:SI 2 "memory_operand" "")]
7684 "DEFAULT_ABI == ABI_V4
7686 && (reload_in_progress || reload_completed)"
7687 [(set (match_dup 0) (match_dup 2))
7688 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7692 ;; For SI, we special-case integers that can't be loaded in one insn. We
7693 ;; do the load 16-bits at a time. We could do this by loading from memory,
7694 ;; and this is even supposed to be faster, but it is simpler not to get
7695 ;; integers in the TOC.
7696 (define_expand "movsi"
7697 [(set (match_operand:SI 0 "general_operand" "")
7698 (match_operand:SI 1 "any_operand" ""))]
7700 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7702 (define_insn "movsi_low"
7703 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7704 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7705 (match_operand 2 "" ""))))]
7706 "TARGET_MACHO && ! TARGET_64BIT"
7707 "{l|lwz} %0,lo16(%2)(%1)"
7708 [(set_attr "type" "load")
7709 (set_attr "length" "4")])
7711 (define_insn "*movsi_internal1"
7712 [(set (match_operand:SI 0 "rs6k_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7713 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7714 "gpc_reg_operand (operands[0], SImode)
7715 || gpc_reg_operand (operands[1], SImode)"
7719 {l%U1%X1|lwz%U1%X1} %0,%1
7720 {st%U0%X0|stw%U0%X0} %1,%0
7730 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7731 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7733 ;; Split a load of a large constant into the appropriate two-insn
7737 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7738 (match_operand:SI 1 "const_int_operand" ""))]
7739 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7740 && (INTVAL (operands[1]) & 0xffff) != 0"
7744 (ior:SI (match_dup 0)
7747 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7749 if (tem == operands[0])
7755 (define_insn "*movsi_internal2"
7756 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7757 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7759 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7762 {cmpi|cmpwi} %2,%0,0
7765 [(set_attr "type" "cmp,compare,cmp")
7766 (set_attr "length" "4,4,8")])
7769 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7770 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7772 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7773 "TARGET_32BIT && reload_completed"
7774 [(set (match_dup 0) (match_dup 1))
7776 (compare:CC (match_dup 0)
7780 (define_expand "movhi"
7781 [(set (match_operand:HI 0 "general_operand" "")
7782 (match_operand:HI 1 "any_operand" ""))]
7784 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7786 (define_insn "*movhi_internal"
7787 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7788 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7789 "gpc_reg_operand (operands[0], HImode)
7790 || gpc_reg_operand (operands[1], HImode)"
7800 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7802 (define_expand "movqi"
7803 [(set (match_operand:QI 0 "general_operand" "")
7804 (match_operand:QI 1 "any_operand" ""))]
7806 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7808 (define_insn "*movqi_internal"
7809 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7810 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7811 "gpc_reg_operand (operands[0], QImode)
7812 || gpc_reg_operand (operands[1], QImode)"
7822 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7824 ;; Here is how to move condition codes around. When we store CC data in
7825 ;; an integer register or memory, we store just the high-order 4 bits.
7826 ;; This lets us not shift in the most common case of CR0.
7827 (define_expand "movcc"
7828 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7829 (match_operand:CC 1 "nonimmediate_operand" ""))]
7833 (define_insn "*movcc_internal1"
7834 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7835 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7836 "register_operand (operands[0], CCmode)
7837 || register_operand (operands[1], CCmode)"
7841 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7843 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7848 {l%U1%X1|lwz%U1%X1} %0,%1
7849 {st%U0%U1|stw%U0%U1} %1,%0"
7851 (cond [(eq_attr "alternative" "0")
7852 (const_string "cr_logical")
7853 (eq_attr "alternative" "1,2")
7854 (const_string "mtcr")
7855 (eq_attr "alternative" "5,7")
7856 (const_string "integer")
7857 (eq_attr "alternative" "6")
7858 (const_string "mfjmpr")
7859 (eq_attr "alternative" "8")
7860 (const_string "mtjmpr")
7861 (eq_attr "alternative" "9")
7862 (const_string "load")
7863 (eq_attr "alternative" "10")
7864 (const_string "store")
7865 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7866 (const_string "mfcrf")
7868 (const_string "mfcr")))
7869 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7871 ;; For floating-point, we normally deal with the floating-point registers
7872 ;; unless -msoft-float is used. The sole exception is that parameter passing
7873 ;; can produce floating-point values in fixed-point registers. Unless the
7874 ;; value is a simple constant or already in memory, we deal with this by
7875 ;; allocating memory and copying the value explicitly via that memory location.
7876 (define_expand "movsf"
7877 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7878 (match_operand:SF 1 "any_operand" ""))]
7880 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7883 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7884 (match_operand:SF 1 "const_double_operand" ""))]
7886 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7887 || (GET_CODE (operands[0]) == SUBREG
7888 && GET_CODE (SUBREG_REG (operands[0])) == REG
7889 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7890 [(set (match_dup 2) (match_dup 3))]
7896 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7897 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7899 if (! TARGET_POWERPC64)
7900 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7902 operands[2] = gen_lowpart (SImode, operands[0]);
7904 operands[3] = gen_int_mode (l, SImode);
7907 (define_insn "*movsf_hardfloat"
7908 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7909 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7910 "(gpc_reg_operand (operands[0], SFmode)
7911 || gpc_reg_operand (operands[1], SFmode))
7912 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7915 {l%U1%X1|lwz%U1%X1} %0,%1
7916 {st%U0%X0|stw%U0%X0} %1,%0
7926 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7927 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7929 (define_insn "*movsf_softfloat"
7930 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7931 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7932 "(gpc_reg_operand (operands[0], SFmode)
7933 || gpc_reg_operand (operands[1], SFmode))
7934 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7940 {l%U1%X1|lwz%U1%X1} %0,%1
7941 {st%U0%X0|stw%U0%X0} %1,%0
7948 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7949 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7952 (define_expand "movdf"
7953 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7954 (match_operand:DF 1 "any_operand" ""))]
7956 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7959 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7960 (match_operand:DF 1 "const_int_operand" ""))]
7961 "! TARGET_POWERPC64 && reload_completed
7962 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7963 || (GET_CODE (operands[0]) == SUBREG
7964 && GET_CODE (SUBREG_REG (operands[0])) == REG
7965 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7966 [(set (match_dup 2) (match_dup 4))
7967 (set (match_dup 3) (match_dup 1))]
7970 int endian = (WORDS_BIG_ENDIAN == 0);
7971 HOST_WIDE_INT value = INTVAL (operands[1]);
7973 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7974 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7975 #if HOST_BITS_PER_WIDE_INT == 32
7976 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7978 operands[4] = GEN_INT (value >> 32);
7979 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7984 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7985 (match_operand:DF 1 "const_double_operand" ""))]
7986 "! TARGET_POWERPC64 && reload_completed
7987 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7988 || (GET_CODE (operands[0]) == SUBREG
7989 && GET_CODE (SUBREG_REG (operands[0])) == REG
7990 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7991 [(set (match_dup 2) (match_dup 4))
7992 (set (match_dup 3) (match_dup 5))]
7995 int endian = (WORDS_BIG_ENDIAN == 0);
7999 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8000 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8002 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8003 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8004 operands[4] = gen_int_mode (l[endian], SImode);
8005 operands[5] = gen_int_mode (l[1 - endian], SImode);
8009 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8010 (match_operand:DF 1 "easy_fp_constant" ""))]
8011 "TARGET_POWERPC64 && reload_completed
8012 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8013 || (GET_CODE (operands[0]) == SUBREG
8014 && GET_CODE (SUBREG_REG (operands[0])) == REG
8015 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8016 [(set (match_dup 2) (match_dup 3))]
8019 int endian = (WORDS_BIG_ENDIAN == 0);
8022 #if HOST_BITS_PER_WIDE_INT >= 64
8026 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8027 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8029 operands[2] = gen_lowpart (DImode, operands[0]);
8030 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8031 #if HOST_BITS_PER_WIDE_INT >= 64
8032 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8033 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8035 operands[3] = gen_int_mode (val, DImode);
8037 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8041 ;; Don't have reload use general registers to load a constant. First,
8042 ;; it might not work if the output operand is the equivalent of
8043 ;; a non-offsettable memref, but also it is less efficient than loading
8044 ;; the constant into an FP register, since it will probably be used there.
8045 ;; The "??" is a kludge until we can figure out a more reasonable way
8046 ;; of handling these non-offsettable values.
8047 (define_insn "*movdf_hardfloat32"
8048 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8049 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8050 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8051 && (gpc_reg_operand (operands[0], DFmode)
8052 || gpc_reg_operand (operands[1], DFmode))"
8055 switch (which_alternative)
8060 /* We normally copy the low-numbered register first. However, if
8061 the first register operand 0 is the same as the second register
8062 of operand 1, we must copy in the opposite order. */
8063 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8064 return \"mr %L0,%L1\;mr %0,%1\";
8066 return \"mr %0,%1\;mr %L0,%L1\";
8068 if (GET_CODE (operands[1]) == MEM
8069 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
8070 reload_completed || reload_in_progress)
8071 || GET_CODE (XEXP (operands[1], 0)) == REG
8072 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8073 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8074 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
8076 /* If the low-address word is used in the address, we must load
8077 it last. Otherwise, load it first. Note that we cannot have
8078 auto-increment in that case since the address register is
8079 known to be dead. */
8080 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8082 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8084 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8090 addreg = find_addr_reg (XEXP (operands[1], 0));
8091 if (refers_to_regno_p (REGNO (operands[0]),
8092 REGNO (operands[0]) + 1,
8095 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8096 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8097 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8098 return \"{lx|lwzx} %0,%1\";
8102 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8103 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8104 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8105 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8110 if (GET_CODE (operands[0]) == MEM
8111 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
8112 reload_completed || reload_in_progress)
8113 || GET_CODE (XEXP (operands[0], 0)) == REG
8114 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8115 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8116 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
8117 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8122 addreg = find_addr_reg (XEXP (operands[0], 0));
8123 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8124 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8125 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8126 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8130 return \"fmr %0,%1\";
8132 return \"lfd%U1%X1 %0,%1\";
8134 return \"stfd%U0%X0 %1,%0\";
8141 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8142 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8144 (define_insn "*movdf_softfloat32"
8145 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8146 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8147 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8148 && (gpc_reg_operand (operands[0], DFmode)
8149 || gpc_reg_operand (operands[1], DFmode))"
8152 switch (which_alternative)
8157 /* We normally copy the low-numbered register first. However, if
8158 the first register operand 0 is the same as the second register of
8159 operand 1, we must copy in the opposite order. */
8160 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8161 return \"mr %L0,%L1\;mr %0,%1\";
8163 return \"mr %0,%1\;mr %L0,%L1\";
8165 /* If the low-address word is used in the address, we must load
8166 it last. Otherwise, load it first. Note that we cannot have
8167 auto-increment in that case since the address register is
8168 known to be dead. */
8169 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8171 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8173 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8175 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8182 [(set_attr "type" "two,load,store,*,*,*")
8183 (set_attr "length" "8,8,8,8,12,16")])
8185 ; ld/std require word-aligned displacements -> 'Y' constraint.
8186 ; List Y->r and r->Y before r->r for reload.
8187 (define_insn "*movdf_hardfloat64"
8188 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
8189 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8190 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8191 && (gpc_reg_operand (operands[0], DFmode)
8192 || gpc_reg_operand (operands[1], DFmode))"
8206 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
8207 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8209 (define_insn "*movdf_softfloat64"
8210 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8211 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8212 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8213 && (gpc_reg_operand (operands[0], DFmode)
8214 || gpc_reg_operand (operands[1], DFmode))"
8225 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
8226 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8228 (define_expand "movtf"
8229 [(set (match_operand:TF 0 "general_operand" "")
8230 (match_operand:TF 1 "any_operand" ""))]
8231 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8232 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8233 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8235 ; It's important to list the o->f and f->o moves before f->f because
8236 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8237 ; which doesn't make progress. Likewise r->Y must be before r->r.
8238 (define_insn_and_split "*movtf_internal"
8239 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8240 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8241 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8242 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8243 && (gpc_reg_operand (operands[0], TFmode)
8244 || gpc_reg_operand (operands[1], TFmode))"
8246 "&& reload_completed"
8248 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8249 [(set_attr "length" "8,8,8,20,20,16")])
8251 (define_expand "extenddftf2"
8252 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8253 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8254 (use (match_dup 2))])]
8255 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8256 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8258 operands[2] = CONST0_RTX (DFmode);
8261 (define_insn_and_split "*extenddftf2_internal"
8262 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8263 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8264 (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))]
8265 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8266 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8268 "&& reload_completed"
8271 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8272 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8273 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8275 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8280 (define_expand "extendsftf2"
8281 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8282 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8283 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8284 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8286 rtx tmp = gen_reg_rtx (DFmode);
8287 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8288 emit_insn (gen_extenddftf2 (operands[0], tmp));
8292 (define_insn "trunctfdf2"
8293 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8294 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8295 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8296 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8298 [(set_attr "type" "fp")
8299 (set_attr "length" "4")])
8301 (define_insn_and_split "trunctfsf2"
8302 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8303 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8304 (clobber (match_scratch:DF 2 "=f"))]
8305 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8306 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8308 "&& reload_completed"
8310 (float_truncate:DF (match_dup 1)))
8312 (float_truncate:SF (match_dup 2)))]
8315 (define_expand "floatsitf2"
8316 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8317 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8318 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8319 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8321 rtx tmp = gen_reg_rtx (DFmode);
8322 expand_float (tmp, operands[1], false);
8323 emit_insn (gen_extenddftf2 (operands[0], tmp));
8327 ; fadd, but rounding towards zero.
8328 ; This is probably not the optimal code sequence.
8329 (define_insn "fix_trunc_helper"
8330 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8331 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8332 UNSPEC_FIX_TRUNC_TF))
8333 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8334 "TARGET_HARD_FLOAT && TARGET_FPRS"
8335 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8336 [(set_attr "type" "fp")
8337 (set_attr "length" "20")])
8339 (define_expand "fix_trunctfsi2"
8340 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8341 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8342 (clobber (match_dup 2))
8343 (clobber (match_dup 3))
8344 (clobber (match_dup 4))
8345 (clobber (match_dup 5))])]
8346 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8347 && (TARGET_POWER2 || TARGET_POWERPC)
8348 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8350 operands[2] = gen_reg_rtx (DFmode);
8351 operands[3] = gen_reg_rtx (DFmode);
8352 operands[4] = gen_reg_rtx (DImode);
8353 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8356 (define_insn_and_split "*fix_trunctfsi2_internal"
8357 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8358 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8359 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8360 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8361 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8362 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8363 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8364 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8366 "&& reload_completed"
8370 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8372 if (GET_CODE (operands[5]) != MEM)
8374 lowword = XEXP (operands[5], 0);
8375 if (WORDS_BIG_ENDIAN)
8376 lowword = plus_constant (lowword, 4);
8378 emit_insn (gen_fctiwz (operands[4], operands[2]));
8379 emit_move_insn (operands[5], operands[4]);
8380 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
8384 (define_insn "negtf2"
8385 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8386 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8387 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8388 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8391 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8392 return \"fneg %L0,%L1\;fneg %0,%1\";
8394 return \"fneg %0,%1\;fneg %L0,%L1\";
8396 [(set_attr "type" "fp")
8397 (set_attr "length" "8")])
8399 (define_expand "abstf2"
8400 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8401 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8402 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8403 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8406 rtx label = gen_label_rtx ();
8407 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8412 (define_expand "abstf2_internal"
8413 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8414 (match_operand:TF 1 "gpc_reg_operand" "f"))
8415 (set (match_dup 3) (match_dup 5))
8416 (set (match_dup 5) (abs:DF (match_dup 5)))
8417 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8418 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8419 (label_ref (match_operand 2 "" ""))
8421 (set (match_dup 6) (neg:DF (match_dup 6)))]
8422 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8423 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8426 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8427 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8428 operands[3] = gen_reg_rtx (DFmode);
8429 operands[4] = gen_reg_rtx (CCFPmode);
8430 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8431 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8434 ;; Next come the multi-word integer load and store and the load and store
8436 (define_expand "movdi"
8437 [(set (match_operand:DI 0 "general_operand" "")
8438 (match_operand:DI 1 "any_operand" ""))]
8440 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8442 ; List r->r after r->"o<>", otherwise reload will try to reload a
8443 ; non-offsettable address by using r->r which won't make progress.
8444 (define_insn "*movdi_internal32"
8445 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8446 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8448 && (gpc_reg_operand (operands[0], DImode)
8449 || gpc_reg_operand (operands[1], DImode))"
8458 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8461 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8462 (match_operand:DI 1 "const_int_operand" ""))]
8463 "! TARGET_POWERPC64 && reload_completed"
8464 [(set (match_dup 2) (match_dup 4))
8465 (set (match_dup 3) (match_dup 1))]
8468 HOST_WIDE_INT value = INTVAL (operands[1]);
8469 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8471 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8473 #if HOST_BITS_PER_WIDE_INT == 32
8474 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8476 operands[4] = GEN_INT (value >> 32);
8477 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8482 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8483 (match_operand:DI 1 "input_operand" ""))]
8484 "reload_completed && !TARGET_POWERPC64
8485 && gpr_or_gpr_p (operands[0], operands[1])"
8487 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8489 (define_insn "*movdi_internal64"
8490 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8491 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8493 && (gpc_reg_operand (operands[0], DImode)
8494 || gpc_reg_operand (operands[1], DImode))"
8509 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8510 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8512 ;; immediate value valid for a single instruction hiding in a const_double
8514 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8515 (match_operand:DI 1 "const_double_operand" "F"))]
8516 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8517 && GET_CODE (operands[1]) == CONST_DOUBLE
8518 && num_insns_constant (operands[1], DImode) == 1"
8521 return ((unsigned HOST_WIDE_INT)
8522 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8523 ? \"li %0,%1\" : \"lis %0,%v1\";
8526 ;; Generate all one-bits and clear left or right.
8527 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8529 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8530 (match_operand:DI 1 "mask64_operand" ""))]
8531 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8532 [(set (match_dup 0) (const_int -1))
8534 (and:DI (rotate:DI (match_dup 0)
8539 ;; Split a load of a large constant into the appropriate five-instruction
8540 ;; sequence. Handle anything in a constant number of insns.
8541 ;; When non-easy constants can go in the TOC, this should use
8542 ;; easy_fp_constant predicate.
8544 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8545 (match_operand:DI 1 "const_int_operand" ""))]
8546 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8547 [(set (match_dup 0) (match_dup 2))
8548 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8550 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8552 if (tem == operands[0])
8559 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8560 (match_operand:DI 1 "const_double_operand" ""))]
8561 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8562 [(set (match_dup 0) (match_dup 2))
8563 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8565 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8567 if (tem == operands[0])
8573 (define_insn "*movdi_internal2"
8574 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8575 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8577 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8583 [(set_attr "type" "cmp,compare,cmp")
8584 (set_attr "length" "4,4,8")])
8587 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8588 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8590 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8591 "TARGET_POWERPC64 && reload_completed"
8592 [(set (match_dup 0) (match_dup 1))
8594 (compare:CC (match_dup 0)
8598 ;; TImode is similar, except that we usually want to compute the address into
8599 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8600 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8601 (define_expand "movti"
8602 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8603 (match_operand:TI 1 "general_operand" ""))
8604 (clobber (scratch:SI))])]
8606 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8608 ;; We say that MQ is clobbered in the last alternative because the first
8609 ;; alternative would never get used otherwise since it would need a reload
8610 ;; while the 2nd alternative would not. We put memory cases first so they
8611 ;; are preferred. Otherwise, we'd try to reload the output instead of
8612 ;; giving the SCRATCH mq.
8614 (define_insn "*movti_power"
8615 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8616 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8617 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8618 "TARGET_POWER && ! TARGET_POWERPC64
8619 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8622 switch (which_alternative)
8629 return \"{stsi|stswi} %1,%P0,16\";
8634 /* If the address is not used in the output, we can use lsi. Otherwise,
8635 fall through to generating four loads. */
8637 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8638 return \"{lsi|lswi} %0,%P1,16\";
8639 /* ... fall through ... */
8645 [(set_attr "type" "store,store,*,load,load,*")])
8647 (define_insn "*movti_string"
8648 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8649 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8650 "! TARGET_POWER && ! TARGET_POWERPC64
8651 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8654 switch (which_alternative)
8660 return \"{stsi|stswi} %1,%P0,16\";
8665 /* If the address is not used in the output, we can use lsi. Otherwise,
8666 fall through to generating four loads. */
8668 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8669 return \"{lsi|lswi} %0,%P1,16\";
8670 /* ... fall through ... */
8676 [(set_attr "type" "store,store,*,load,load,*")])
8678 (define_insn "*movti_ppc64"
8679 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8680 (match_operand:TI 1 "input_operand" "r,r,m"))]
8681 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8682 || gpc_reg_operand (operands[1], TImode))"
8684 [(set_attr "type" "*,load,store")])
8687 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8688 (match_operand:TI 1 "const_double_operand" ""))]
8690 [(set (match_dup 2) (match_dup 4))
8691 (set (match_dup 3) (match_dup 5))]
8694 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8696 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8698 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8700 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8701 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8703 else if (GET_CODE (operands[1]) == CONST_INT)
8705 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8706 operands[5] = operands[1];
8713 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8714 (match_operand:TI 1 "input_operand" ""))]
8716 && gpr_or_gpr_p (operands[0], operands[1])"
8718 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8720 (define_expand "load_multiple"
8721 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8722 (match_operand:SI 1 "" ""))
8723 (use (match_operand:SI 2 "" ""))])]
8724 "TARGET_STRING && !TARGET_POWERPC64"
8732 /* Support only loading a constant number of fixed-point registers from
8733 memory and only bother with this if more than two; the machine
8734 doesn't support more than eight. */
8735 if (GET_CODE (operands[2]) != CONST_INT
8736 || INTVAL (operands[2]) <= 2
8737 || INTVAL (operands[2]) > 8
8738 || GET_CODE (operands[1]) != MEM
8739 || GET_CODE (operands[0]) != REG
8740 || REGNO (operands[0]) >= 32)
8743 count = INTVAL (operands[2]);
8744 regno = REGNO (operands[0]);
8746 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8747 op1 = replace_equiv_address (operands[1],
8748 force_reg (SImode, XEXP (operands[1], 0)));
8750 for (i = 0; i < count; i++)
8751 XVECEXP (operands[3], 0, i)
8752 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8753 adjust_address_nv (op1, SImode, i * 4));
8756 (define_insn "*ldmsi8"
8757 [(match_parallel 0 "load_multiple_operation"
8758 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8759 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8760 (set (match_operand:SI 3 "gpc_reg_operand" "")
8761 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8762 (set (match_operand:SI 4 "gpc_reg_operand" "")
8763 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8764 (set (match_operand:SI 5 "gpc_reg_operand" "")
8765 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8766 (set (match_operand:SI 6 "gpc_reg_operand" "")
8767 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8768 (set (match_operand:SI 7 "gpc_reg_operand" "")
8769 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8770 (set (match_operand:SI 8 "gpc_reg_operand" "")
8771 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8772 (set (match_operand:SI 9 "gpc_reg_operand" "")
8773 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8774 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8776 { return rs6000_output_load_multiple (operands); }"
8777 [(set_attr "type" "load")
8778 (set_attr "length" "32")])
8780 (define_insn "*ldmsi7"
8781 [(match_parallel 0 "load_multiple_operation"
8782 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8783 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8784 (set (match_operand:SI 3 "gpc_reg_operand" "")
8785 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8786 (set (match_operand:SI 4 "gpc_reg_operand" "")
8787 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8788 (set (match_operand:SI 5 "gpc_reg_operand" "")
8789 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8790 (set (match_operand:SI 6 "gpc_reg_operand" "")
8791 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8792 (set (match_operand:SI 7 "gpc_reg_operand" "")
8793 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8794 (set (match_operand:SI 8 "gpc_reg_operand" "")
8795 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8796 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8798 { return rs6000_output_load_multiple (operands); }"
8799 [(set_attr "type" "load")
8800 (set_attr "length" "32")])
8802 (define_insn "*ldmsi6"
8803 [(match_parallel 0 "load_multiple_operation"
8804 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8805 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8806 (set (match_operand:SI 3 "gpc_reg_operand" "")
8807 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8808 (set (match_operand:SI 4 "gpc_reg_operand" "")
8809 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8810 (set (match_operand:SI 5 "gpc_reg_operand" "")
8811 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8812 (set (match_operand:SI 6 "gpc_reg_operand" "")
8813 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8814 (set (match_operand:SI 7 "gpc_reg_operand" "")
8815 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8816 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8818 { return rs6000_output_load_multiple (operands); }"
8819 [(set_attr "type" "load")
8820 (set_attr "length" "32")])
8822 (define_insn "*ldmsi5"
8823 [(match_parallel 0 "load_multiple_operation"
8824 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8825 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8826 (set (match_operand:SI 3 "gpc_reg_operand" "")
8827 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8828 (set (match_operand:SI 4 "gpc_reg_operand" "")
8829 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8830 (set (match_operand:SI 5 "gpc_reg_operand" "")
8831 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8832 (set (match_operand:SI 6 "gpc_reg_operand" "")
8833 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8834 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8836 { return rs6000_output_load_multiple (operands); }"
8837 [(set_attr "type" "load")
8838 (set_attr "length" "32")])
8840 (define_insn "*ldmsi4"
8841 [(match_parallel 0 "load_multiple_operation"
8842 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8843 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8844 (set (match_operand:SI 3 "gpc_reg_operand" "")
8845 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8846 (set (match_operand:SI 4 "gpc_reg_operand" "")
8847 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8848 (set (match_operand:SI 5 "gpc_reg_operand" "")
8849 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8850 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8852 { return rs6000_output_load_multiple (operands); }"
8853 [(set_attr "type" "load")
8854 (set_attr "length" "32")])
8856 (define_insn "*ldmsi3"
8857 [(match_parallel 0 "load_multiple_operation"
8858 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8859 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8860 (set (match_operand:SI 3 "gpc_reg_operand" "")
8861 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8862 (set (match_operand:SI 4 "gpc_reg_operand" "")
8863 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8864 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8866 { return rs6000_output_load_multiple (operands); }"
8867 [(set_attr "type" "load")
8868 (set_attr "length" "32")])
8870 (define_expand "store_multiple"
8871 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8872 (match_operand:SI 1 "" ""))
8873 (clobber (scratch:SI))
8874 (use (match_operand:SI 2 "" ""))])]
8875 "TARGET_STRING && !TARGET_POWERPC64"
8884 /* Support only storing a constant number of fixed-point registers to
8885 memory and only bother with this if more than two; the machine
8886 doesn't support more than eight. */
8887 if (GET_CODE (operands[2]) != CONST_INT
8888 || INTVAL (operands[2]) <= 2
8889 || INTVAL (operands[2]) > 8
8890 || GET_CODE (operands[0]) != MEM
8891 || GET_CODE (operands[1]) != REG
8892 || REGNO (operands[1]) >= 32)
8895 count = INTVAL (operands[2]);
8896 regno = REGNO (operands[1]);
8898 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8899 to = force_reg (SImode, XEXP (operands[0], 0));
8900 op0 = replace_equiv_address (operands[0], to);
8902 XVECEXP (operands[3], 0, 0)
8903 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8904 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8905 gen_rtx_SCRATCH (SImode));
8907 for (i = 1; i < count; i++)
8908 XVECEXP (operands[3], 0, i + 1)
8909 = gen_rtx_SET (VOIDmode,
8910 adjust_address_nv (op0, SImode, i * 4),
8911 gen_rtx_REG (SImode, regno + i));
8914 (define_insn "*store_multiple_power"
8915 [(match_parallel 0 "store_multiple_operation"
8916 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8917 (match_operand:SI 2 "gpc_reg_operand" "r"))
8918 (clobber (match_scratch:SI 3 "=q"))])]
8919 "TARGET_STRING && TARGET_POWER"
8920 "{stsi|stswi} %2,%P1,%O0"
8921 [(set_attr "type" "store")])
8923 (define_insn "*stmsi8"
8924 [(match_parallel 0 "store_multiple_operation"
8925 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8926 (match_operand:SI 2 "gpc_reg_operand" "r"))
8927 (clobber (match_scratch:SI 3 "X"))
8928 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8929 (match_operand:SI 4 "gpc_reg_operand" "r"))
8930 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8931 (match_operand:SI 5 "gpc_reg_operand" "r"))
8932 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8933 (match_operand:SI 6 "gpc_reg_operand" "r"))
8934 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8935 (match_operand:SI 7 "gpc_reg_operand" "r"))
8936 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8937 (match_operand:SI 8 "gpc_reg_operand" "r"))
8938 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8939 (match_operand:SI 9 "gpc_reg_operand" "r"))
8940 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8941 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8942 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8943 "{stsi|stswi} %2,%1,%O0"
8944 [(set_attr "type" "store")])
8946 (define_insn "*stmsi7"
8947 [(match_parallel 0 "store_multiple_operation"
8948 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8949 (match_operand:SI 2 "gpc_reg_operand" "r"))
8950 (clobber (match_scratch:SI 3 "X"))
8951 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8952 (match_operand:SI 4 "gpc_reg_operand" "r"))
8953 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8954 (match_operand:SI 5 "gpc_reg_operand" "r"))
8955 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8956 (match_operand:SI 6 "gpc_reg_operand" "r"))
8957 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8958 (match_operand:SI 7 "gpc_reg_operand" "r"))
8959 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8960 (match_operand:SI 8 "gpc_reg_operand" "r"))
8961 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8962 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8963 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8964 "{stsi|stswi} %2,%1,%O0"
8965 [(set_attr "type" "store")])
8967 (define_insn "*stmsi6"
8968 [(match_parallel 0 "store_multiple_operation"
8969 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8970 (match_operand:SI 2 "gpc_reg_operand" "r"))
8971 (clobber (match_scratch:SI 3 "X"))
8972 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8973 (match_operand:SI 4 "gpc_reg_operand" "r"))
8974 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8975 (match_operand:SI 5 "gpc_reg_operand" "r"))
8976 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8977 (match_operand:SI 6 "gpc_reg_operand" "r"))
8978 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8979 (match_operand:SI 7 "gpc_reg_operand" "r"))
8980 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8981 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8982 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8983 "{stsi|stswi} %2,%1,%O0"
8984 [(set_attr "type" "store")])
8986 (define_insn "*stmsi5"
8987 [(match_parallel 0 "store_multiple_operation"
8988 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8989 (match_operand:SI 2 "gpc_reg_operand" "r"))
8990 (clobber (match_scratch:SI 3 "X"))
8991 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8992 (match_operand:SI 4 "gpc_reg_operand" "r"))
8993 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8994 (match_operand:SI 5 "gpc_reg_operand" "r"))
8995 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8996 (match_operand:SI 6 "gpc_reg_operand" "r"))
8997 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8998 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8999 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9000 "{stsi|stswi} %2,%1,%O0"
9001 [(set_attr "type" "store")])
9003 (define_insn "*stmsi4"
9004 [(match_parallel 0 "store_multiple_operation"
9005 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9006 (match_operand:SI 2 "gpc_reg_operand" "r"))
9007 (clobber (match_scratch:SI 3 "X"))
9008 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9009 (match_operand:SI 4 "gpc_reg_operand" "r"))
9010 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9011 (match_operand:SI 5 "gpc_reg_operand" "r"))
9012 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9013 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9014 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9015 "{stsi|stswi} %2,%1,%O0"
9016 [(set_attr "type" "store")])
9018 (define_insn "*stmsi3"
9019 [(match_parallel 0 "store_multiple_operation"
9020 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9021 (match_operand:SI 2 "gpc_reg_operand" "r"))
9022 (clobber (match_scratch:SI 3 "X"))
9023 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9024 (match_operand:SI 4 "gpc_reg_operand" "r"))
9025 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9026 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9027 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9028 "{stsi|stswi} %2,%1,%O0"
9029 [(set_attr "type" "store")])
9031 (define_expand "clrmemsi"
9032 [(parallel [(set (match_operand:BLK 0 "" "")
9034 (use (match_operand:SI 1 "" ""))
9035 (use (match_operand:SI 2 "" ""))])]
9039 if (expand_block_clear (operands))
9045 ;; String/block move insn.
9046 ;; Argument 0 is the destination
9047 ;; Argument 1 is the source
9048 ;; Argument 2 is the length
9049 ;; Argument 3 is the alignment
9051 (define_expand "movmemsi"
9052 [(parallel [(set (match_operand:BLK 0 "" "")
9053 (match_operand:BLK 1 "" ""))
9054 (use (match_operand:SI 2 "" ""))
9055 (use (match_operand:SI 3 "" ""))])]
9059 if (expand_block_move (operands))
9065 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9066 ;; register allocator doesn't have a clue about allocating 8 word registers.
9067 ;; rD/rS = r5 is preferred, efficient form.
9068 (define_expand "movmemsi_8reg"
9069 [(parallel [(set (match_operand 0 "" "")
9070 (match_operand 1 "" ""))
9071 (use (match_operand 2 "" ""))
9072 (use (match_operand 3 "" ""))
9073 (clobber (reg:SI 5))
9074 (clobber (reg:SI 6))
9075 (clobber (reg:SI 7))
9076 (clobber (reg:SI 8))
9077 (clobber (reg:SI 9))
9078 (clobber (reg:SI 10))
9079 (clobber (reg:SI 11))
9080 (clobber (reg:SI 12))
9081 (clobber (match_scratch:SI 4 ""))])]
9086 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9087 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9088 (use (match_operand:SI 2 "immediate_operand" "i"))
9089 (use (match_operand:SI 3 "immediate_operand" "i"))
9090 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9091 (clobber (reg:SI 6))
9092 (clobber (reg:SI 7))
9093 (clobber (reg:SI 8))
9094 (clobber (reg:SI 9))
9095 (clobber (reg:SI 10))
9096 (clobber (reg:SI 11))
9097 (clobber (reg:SI 12))
9098 (clobber (match_scratch:SI 5 "=q"))]
9099 "TARGET_STRING && TARGET_POWER
9100 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9101 || INTVAL (operands[2]) == 0)
9102 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9103 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9104 && REGNO (operands[4]) == 5"
9105 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9106 [(set_attr "type" "load")
9107 (set_attr "length" "8")])
9110 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9111 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9112 (use (match_operand:SI 2 "immediate_operand" "i"))
9113 (use (match_operand:SI 3 "immediate_operand" "i"))
9114 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9115 (clobber (reg:SI 6))
9116 (clobber (reg:SI 7))
9117 (clobber (reg:SI 8))
9118 (clobber (reg:SI 9))
9119 (clobber (reg:SI 10))
9120 (clobber (reg:SI 11))
9121 (clobber (reg:SI 12))
9122 (clobber (match_scratch:SI 5 "X"))]
9123 "TARGET_STRING && ! TARGET_POWER
9124 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9125 || INTVAL (operands[2]) == 0)
9126 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9127 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9128 && REGNO (operands[4]) == 5"
9129 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9130 [(set_attr "type" "load")
9131 (set_attr "length" "8")])
9134 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9135 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9136 (use (match_operand:SI 2 "immediate_operand" "i"))
9137 (use (match_operand:SI 3 "immediate_operand" "i"))
9138 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9139 (clobber (reg:SI 6))
9140 (clobber (reg:SI 7))
9141 (clobber (reg:SI 8))
9142 (clobber (reg:SI 9))
9143 (clobber (reg:SI 10))
9144 (clobber (reg:SI 11))
9145 (clobber (reg:SI 12))
9146 (clobber (match_scratch:SI 5 "X"))]
9147 "TARGET_STRING && TARGET_POWERPC64
9148 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9149 || INTVAL (operands[2]) == 0)
9150 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9151 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9152 && REGNO (operands[4]) == 5"
9153 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9154 [(set_attr "type" "load")
9155 (set_attr "length" "8")])
9157 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9158 ;; register allocator doesn't have a clue about allocating 6 word registers.
9159 ;; rD/rS = r5 is preferred, efficient form.
9160 (define_expand "movmemsi_6reg"
9161 [(parallel [(set (match_operand 0 "" "")
9162 (match_operand 1 "" ""))
9163 (use (match_operand 2 "" ""))
9164 (use (match_operand 3 "" ""))
9165 (clobber (reg:SI 5))
9166 (clobber (reg:SI 6))
9167 (clobber (reg:SI 7))
9168 (clobber (reg:SI 8))
9169 (clobber (reg:SI 9))
9170 (clobber (reg:SI 10))
9171 (clobber (match_scratch:SI 4 ""))])]
9176 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9177 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9178 (use (match_operand:SI 2 "immediate_operand" "i"))
9179 (use (match_operand:SI 3 "immediate_operand" "i"))
9180 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9181 (clobber (reg:SI 6))
9182 (clobber (reg:SI 7))
9183 (clobber (reg:SI 8))
9184 (clobber (reg:SI 9))
9185 (clobber (reg:SI 10))
9186 (clobber (match_scratch:SI 5 "=q"))]
9187 "TARGET_STRING && TARGET_POWER
9188 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9189 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9190 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9191 && REGNO (operands[4]) == 5"
9192 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9193 [(set_attr "type" "load")
9194 (set_attr "length" "8")])
9197 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9198 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9199 (use (match_operand:SI 2 "immediate_operand" "i"))
9200 (use (match_operand:SI 3 "immediate_operand" "i"))
9201 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9202 (clobber (reg:SI 6))
9203 (clobber (reg:SI 7))
9204 (clobber (reg:SI 8))
9205 (clobber (reg:SI 9))
9206 (clobber (reg:SI 10))
9207 (clobber (match_scratch:SI 5 "X"))]
9208 "TARGET_STRING && ! TARGET_POWER
9209 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9210 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9211 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9212 && REGNO (operands[4]) == 5"
9213 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9214 [(set_attr "type" "load")
9215 (set_attr "length" "8")])
9218 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9219 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9220 (use (match_operand:SI 2 "immediate_operand" "i"))
9221 (use (match_operand:SI 3 "immediate_operand" "i"))
9222 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9223 (clobber (reg:SI 6))
9224 (clobber (reg:SI 7))
9225 (clobber (reg:SI 8))
9226 (clobber (reg:SI 9))
9227 (clobber (reg:SI 10))
9228 (clobber (match_scratch:SI 5 "X"))]
9229 "TARGET_STRING && TARGET_POWERPC64
9230 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9231 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9232 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9233 && REGNO (operands[4]) == 5"
9234 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9235 [(set_attr "type" "load")
9236 (set_attr "length" "8")])
9238 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9239 ;; problems with TImode.
9240 ;; rD/rS = r5 is preferred, efficient form.
9241 (define_expand "movmemsi_4reg"
9242 [(parallel [(set (match_operand 0 "" "")
9243 (match_operand 1 "" ""))
9244 (use (match_operand 2 "" ""))
9245 (use (match_operand 3 "" ""))
9246 (clobber (reg:SI 5))
9247 (clobber (reg:SI 6))
9248 (clobber (reg:SI 7))
9249 (clobber (reg:SI 8))
9250 (clobber (match_scratch:SI 4 ""))])]
9255 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9256 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9257 (use (match_operand:SI 2 "immediate_operand" "i"))
9258 (use (match_operand:SI 3 "immediate_operand" "i"))
9259 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9260 (clobber (reg:SI 6))
9261 (clobber (reg:SI 7))
9262 (clobber (reg:SI 8))
9263 (clobber (match_scratch:SI 5 "=q"))]
9264 "TARGET_STRING && TARGET_POWER
9265 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9266 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9267 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9268 && REGNO (operands[4]) == 5"
9269 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9270 [(set_attr "type" "load")
9271 (set_attr "length" "8")])
9274 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9275 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9276 (use (match_operand:SI 2 "immediate_operand" "i"))
9277 (use (match_operand:SI 3 "immediate_operand" "i"))
9278 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9279 (clobber (reg:SI 6))
9280 (clobber (reg:SI 7))
9281 (clobber (reg:SI 8))
9282 (clobber (match_scratch:SI 5 "X"))]
9283 "TARGET_STRING && ! TARGET_POWER
9284 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9285 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9286 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9287 && REGNO (operands[4]) == 5"
9288 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9289 [(set_attr "type" "load")
9290 (set_attr "length" "8")])
9293 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9294 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9295 (use (match_operand:SI 2 "immediate_operand" "i"))
9296 (use (match_operand:SI 3 "immediate_operand" "i"))
9297 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9298 (clobber (reg:SI 6))
9299 (clobber (reg:SI 7))
9300 (clobber (reg:SI 8))
9301 (clobber (match_scratch:SI 5 "X"))]
9302 "TARGET_STRING && TARGET_POWERPC64
9303 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9304 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9305 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9306 && REGNO (operands[4]) == 5"
9307 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9308 [(set_attr "type" "load")
9309 (set_attr "length" "8")])
9311 ;; Move up to 8 bytes at a time.
9312 (define_expand "movmemsi_2reg"
9313 [(parallel [(set (match_operand 0 "" "")
9314 (match_operand 1 "" ""))
9315 (use (match_operand 2 "" ""))
9316 (use (match_operand 3 "" ""))
9317 (clobber (match_scratch:DI 4 ""))
9318 (clobber (match_scratch:SI 5 ""))])]
9319 "TARGET_STRING && ! TARGET_POWERPC64"
9323 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9324 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9325 (use (match_operand:SI 2 "immediate_operand" "i"))
9326 (use (match_operand:SI 3 "immediate_operand" "i"))
9327 (clobber (match_scratch:DI 4 "=&r"))
9328 (clobber (match_scratch:SI 5 "=q"))]
9329 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9330 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9331 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9332 [(set_attr "type" "load")
9333 (set_attr "length" "8")])
9336 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9337 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9338 (use (match_operand:SI 2 "immediate_operand" "i"))
9339 (use (match_operand:SI 3 "immediate_operand" "i"))
9340 (clobber (match_scratch:DI 4 "=&r"))
9341 (clobber (match_scratch:SI 5 "X"))]
9342 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9343 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9344 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9345 [(set_attr "type" "load")
9346 (set_attr "length" "8")])
9348 ;; Move up to 4 bytes at a time.
9349 (define_expand "movmemsi_1reg"
9350 [(parallel [(set (match_operand 0 "" "")
9351 (match_operand 1 "" ""))
9352 (use (match_operand 2 "" ""))
9353 (use (match_operand 3 "" ""))
9354 (clobber (match_scratch:SI 4 ""))
9355 (clobber (match_scratch:SI 5 ""))])]
9360 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9361 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9362 (use (match_operand:SI 2 "immediate_operand" "i"))
9363 (use (match_operand:SI 3 "immediate_operand" "i"))
9364 (clobber (match_scratch:SI 4 "=&r"))
9365 (clobber (match_scratch:SI 5 "=q"))]
9366 "TARGET_STRING && TARGET_POWER
9367 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9368 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9369 [(set_attr "type" "load")
9370 (set_attr "length" "8")])
9373 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9374 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9375 (use (match_operand:SI 2 "immediate_operand" "i"))
9376 (use (match_operand:SI 3 "immediate_operand" "i"))
9377 (clobber (match_scratch:SI 4 "=&r"))
9378 (clobber (match_scratch:SI 5 "X"))]
9379 "TARGET_STRING && ! TARGET_POWER
9380 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9381 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9382 [(set_attr "type" "load")
9383 (set_attr "length" "8")])
9386 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9387 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9388 (use (match_operand:SI 2 "immediate_operand" "i"))
9389 (use (match_operand:SI 3 "immediate_operand" "i"))
9390 (clobber (match_scratch:SI 4 "=&r"))
9391 (clobber (match_scratch:SI 5 "X"))]
9392 "TARGET_STRING && TARGET_POWERPC64
9393 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9394 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9395 [(set_attr "type" "load")
9396 (set_attr "length" "8")])
9399 ;; Define insns that do load or store with update. Some of these we can
9400 ;; get by using pre-decrement or pre-increment, but the hardware can also
9401 ;; do cases where the increment is not the size of the object.
9403 ;; In all these cases, we use operands 0 and 1 for the register being
9404 ;; incremented because those are the operands that local-alloc will
9405 ;; tie and these are the pair most likely to be tieable (and the ones
9406 ;; that will benefit the most).
9408 (define_insn "*movdi_update1"
9409 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9410 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9411 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9412 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9413 (plus:DI (match_dup 1) (match_dup 2)))]
9414 "TARGET_POWERPC64 && TARGET_UPDATE"
9418 [(set_attr "type" "load_ux,load_u")])
9420 (define_insn "movdi_<mode>_update"
9421 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9422 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9423 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9424 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9425 (plus:P (match_dup 1) (match_dup 2)))]
9426 "TARGET_POWERPC64 && TARGET_UPDATE"
9430 [(set_attr "type" "store_ux,store_u")])
9432 (define_insn "*movsi_update1"
9433 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9434 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9435 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9436 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9437 (plus:SI (match_dup 1) (match_dup 2)))]
9440 {lux|lwzux} %3,%0,%2
9441 {lu|lwzu} %3,%2(%0)"
9442 [(set_attr "type" "load_ux,load_u")])
9444 (define_insn "*movsi_update2"
9445 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9447 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9448 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9449 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9450 (plus:DI (match_dup 1) (match_dup 2)))]
9453 [(set_attr "type" "load_ext_ux")])
9455 (define_insn "movsi_update"
9456 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9457 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9458 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9459 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9460 (plus:SI (match_dup 1) (match_dup 2)))]
9463 {stux|stwux} %3,%0,%2
9464 {stu|stwu} %3,%2(%0)"
9465 [(set_attr "type" "store_ux,store_u")])
9467 (define_insn "*movhi_update1"
9468 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9469 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9470 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9471 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9472 (plus:SI (match_dup 1) (match_dup 2)))]
9477 [(set_attr "type" "load_ux,load_u")])
9479 (define_insn "*movhi_update2"
9480 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9482 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9483 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9484 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9485 (plus:SI (match_dup 1) (match_dup 2)))]
9490 [(set_attr "type" "load_ux,load_u")])
9492 (define_insn "*movhi_update3"
9493 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9495 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9496 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9497 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9498 (plus:SI (match_dup 1) (match_dup 2)))]
9503 [(set_attr "type" "load_ext_ux,load_ext_u")])
9505 (define_insn "*movhi_update4"
9506 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9507 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9508 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9509 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9510 (plus:SI (match_dup 1) (match_dup 2)))]
9515 [(set_attr "type" "store_ux,store_u")])
9517 (define_insn "*movqi_update1"
9518 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9519 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9520 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9521 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9522 (plus:SI (match_dup 1) (match_dup 2)))]
9527 [(set_attr "type" "load_ux,load_u")])
9529 (define_insn "*movqi_update2"
9530 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9532 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9533 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9534 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9535 (plus:SI (match_dup 1) (match_dup 2)))]
9540 [(set_attr "type" "load_ux,load_u")])
9542 (define_insn "*movqi_update3"
9543 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9544 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9545 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9546 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9547 (plus:SI (match_dup 1) (match_dup 2)))]
9552 [(set_attr "type" "store_ux,store_u")])
9554 (define_insn "*movsf_update1"
9555 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9556 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9557 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9558 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9559 (plus:SI (match_dup 1) (match_dup 2)))]
9560 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9564 [(set_attr "type" "fpload_ux,fpload_u")])
9566 (define_insn "*movsf_update2"
9567 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9568 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9569 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9570 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9571 (plus:SI (match_dup 1) (match_dup 2)))]
9572 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9576 [(set_attr "type" "fpstore_ux,fpstore_u")])
9578 (define_insn "*movsf_update3"
9579 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9580 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9581 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9582 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9583 (plus:SI (match_dup 1) (match_dup 2)))]
9584 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9586 {lux|lwzux} %3,%0,%2
9587 {lu|lwzu} %3,%2(%0)"
9588 [(set_attr "type" "load_ux,load_u")])
9590 (define_insn "*movsf_update4"
9591 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9592 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9593 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9594 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9595 (plus:SI (match_dup 1) (match_dup 2)))]
9596 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9598 {stux|stwux} %3,%0,%2
9599 {stu|stwu} %3,%2(%0)"
9600 [(set_attr "type" "store_ux,store_u")])
9602 (define_insn "*movdf_update1"
9603 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9604 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9605 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9606 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9607 (plus:SI (match_dup 1) (match_dup 2)))]
9608 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9612 [(set_attr "type" "fpload_ux,fpload_u")])
9614 (define_insn "*movdf_update2"
9615 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9616 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9617 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9618 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9619 (plus:SI (match_dup 1) (match_dup 2)))]
9620 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9624 [(set_attr "type" "fpstore_ux,fpstore_u")])
9626 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9628 (define_insn "*lfq_power2"
9629 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9630 (match_operand:TF 1 "memory_operand" ""))]
9632 && TARGET_HARD_FLOAT && TARGET_FPRS"
9636 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9637 (match_operand:DF 1 "memory_operand" ""))
9638 (set (match_operand:DF 2 "gpc_reg_operand" "")
9639 (match_operand:DF 3 "memory_operand" ""))]
9641 && TARGET_HARD_FLOAT && TARGET_FPRS
9642 && registers_ok_for_quad_peep (operands[0], operands[2])
9643 && mems_ok_for_quad_peep (operands[1], operands[3])"
9646 "operands[1] = widen_memory_access (operands[1], TFmode, 0);
9647 operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
9649 (define_insn "*stfq_power2"
9650 [(set (match_operand:TF 0 "memory_operand" "")
9651 (match_operand:TF 1 "gpc_reg_operand" "f"))]
9653 && TARGET_HARD_FLOAT && TARGET_FPRS"
9658 [(set (match_operand:DF 0 "memory_operand" "")
9659 (match_operand:DF 1 "gpc_reg_operand" ""))
9660 (set (match_operand:DF 2 "memory_operand" "")
9661 (match_operand:DF 3 "gpc_reg_operand" ""))]
9663 && TARGET_HARD_FLOAT && TARGET_FPRS
9664 && registers_ok_for_quad_peep (operands[1], operands[3])
9665 && mems_ok_for_quad_peep (operands[0], operands[2])"
9668 "operands[0] = widen_memory_access (operands[0], TFmode, 0);
9669 operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
9671 ;; after inserting conditional returns we can sometimes have
9672 ;; unnecessary register moves. Unfortunately we cannot have a
9673 ;; modeless peephole here, because some single SImode sets have early
9674 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9675 ;; sequences, using get_attr_length here will smash the operands
9676 ;; array. Neither is there an early_cobbler_p predicate.
9678 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9679 (match_operand:DF 1 "any_operand" ""))
9680 (set (match_operand:DF 2 "gpc_reg_operand" "")
9682 "peep2_reg_dead_p (2, operands[0])"
9683 [(set (match_dup 2) (match_dup 1))])
9686 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9687 (match_operand:SF 1 "any_operand" ""))
9688 (set (match_operand:SF 2 "gpc_reg_operand" "")
9690 "peep2_reg_dead_p (2, operands[0])"
9691 [(set (match_dup 2) (match_dup 1))])
9696 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9697 (define_insn "tls_gd_32"
9698 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9699 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9700 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9702 "HAVE_AS_TLS && !TARGET_64BIT"
9703 "addi %0,%1,%2@got@tlsgd")
9705 (define_insn "tls_gd_64"
9706 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9707 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9708 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9710 "HAVE_AS_TLS && TARGET_64BIT"
9711 "addi %0,%1,%2@got@tlsgd")
9713 (define_insn "tls_ld_32"
9714 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9715 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9717 "HAVE_AS_TLS && !TARGET_64BIT"
9718 "addi %0,%1,%&@got@tlsld")
9720 (define_insn "tls_ld_64"
9721 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9722 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9724 "HAVE_AS_TLS && TARGET_64BIT"
9725 "addi %0,%1,%&@got@tlsld")
9727 (define_insn "tls_dtprel_32"
9728 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9729 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9730 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9732 "HAVE_AS_TLS && !TARGET_64BIT"
9733 "addi %0,%1,%2@dtprel")
9735 (define_insn "tls_dtprel_64"
9736 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9737 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9738 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9740 "HAVE_AS_TLS && TARGET_64BIT"
9741 "addi %0,%1,%2@dtprel")
9743 (define_insn "tls_dtprel_ha_32"
9744 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9745 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9746 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9747 UNSPEC_TLSDTPRELHA))]
9748 "HAVE_AS_TLS && !TARGET_64BIT"
9749 "addis %0,%1,%2@dtprel@ha")
9751 (define_insn "tls_dtprel_ha_64"
9752 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9753 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9754 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9755 UNSPEC_TLSDTPRELHA))]
9756 "HAVE_AS_TLS && TARGET_64BIT"
9757 "addis %0,%1,%2@dtprel@ha")
9759 (define_insn "tls_dtprel_lo_32"
9760 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9761 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9762 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9763 UNSPEC_TLSDTPRELLO))]
9764 "HAVE_AS_TLS && !TARGET_64BIT"
9765 "addi %0,%1,%2@dtprel@l")
9767 (define_insn "tls_dtprel_lo_64"
9768 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9769 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9770 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9771 UNSPEC_TLSDTPRELLO))]
9772 "HAVE_AS_TLS && TARGET_64BIT"
9773 "addi %0,%1,%2@dtprel@l")
9775 (define_insn "tls_got_dtprel_32"
9776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9777 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9778 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9779 UNSPEC_TLSGOTDTPREL))]
9780 "HAVE_AS_TLS && !TARGET_64BIT"
9781 "lwz %0,%2@got@dtprel(%1)")
9783 (define_insn "tls_got_dtprel_64"
9784 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9785 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9786 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9787 UNSPEC_TLSGOTDTPREL))]
9788 "HAVE_AS_TLS && TARGET_64BIT"
9789 "ld %0,%2@got@dtprel(%1)")
9791 (define_insn "tls_tprel_32"
9792 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9793 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9794 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9796 "HAVE_AS_TLS && !TARGET_64BIT"
9797 "addi %0,%1,%2@tprel")
9799 (define_insn "tls_tprel_64"
9800 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9801 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9802 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9804 "HAVE_AS_TLS && TARGET_64BIT"
9805 "addi %0,%1,%2@tprel")
9807 (define_insn "tls_tprel_ha_32"
9808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9809 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9810 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9811 UNSPEC_TLSTPRELHA))]
9812 "HAVE_AS_TLS && !TARGET_64BIT"
9813 "addis %0,%1,%2@tprel@ha")
9815 (define_insn "tls_tprel_ha_64"
9816 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9817 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9818 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9819 UNSPEC_TLSTPRELHA))]
9820 "HAVE_AS_TLS && TARGET_64BIT"
9821 "addis %0,%1,%2@tprel@ha")
9823 (define_insn "tls_tprel_lo_32"
9824 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9825 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9826 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9827 UNSPEC_TLSTPRELLO))]
9828 "HAVE_AS_TLS && !TARGET_64BIT"
9829 "addi %0,%1,%2@tprel@l")
9831 (define_insn "tls_tprel_lo_64"
9832 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9833 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9834 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9835 UNSPEC_TLSTPRELLO))]
9836 "HAVE_AS_TLS && TARGET_64BIT"
9837 "addi %0,%1,%2@tprel@l")
9839 ;; "b" output constraint here and on tls_tls input to support linker tls
9840 ;; optimization. The linker may edit the instructions emitted by a
9841 ;; tls_got_tprel/tls_tls pair to addis,addi.
9842 (define_insn "tls_got_tprel_32"
9843 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9844 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9845 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9846 UNSPEC_TLSGOTTPREL))]
9847 "HAVE_AS_TLS && !TARGET_64BIT"
9848 "lwz %0,%2@got@tprel(%1)")
9850 (define_insn "tls_got_tprel_64"
9851 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9852 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9853 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9854 UNSPEC_TLSGOTTPREL))]
9855 "HAVE_AS_TLS && TARGET_64BIT"
9856 "ld %0,%2@got@tprel(%1)")
9858 (define_insn "tls_tls_32"
9859 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9860 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9861 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9863 "HAVE_AS_TLS && !TARGET_64BIT"
9866 (define_insn "tls_tls_64"
9867 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9868 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9869 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9871 "HAVE_AS_TLS && TARGET_64BIT"
9874 ;; Next come insns related to the calling sequence.
9876 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9877 ;; We move the back-chain and decrement the stack pointer.
9879 (define_expand "allocate_stack"
9880 [(set (match_operand 0 "gpc_reg_operand" "=r")
9881 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9883 (minus (reg 1) (match_dup 1)))]
9886 { rtx chain = gen_reg_rtx (Pmode);
9887 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9890 emit_move_insn (chain, stack_bot);
9892 /* Check stack bounds if necessary. */
9893 if (current_function_limit_stack)
9896 available = expand_binop (Pmode, sub_optab,
9897 stack_pointer_rtx, stack_limit_rtx,
9898 NULL_RTX, 1, OPTAB_WIDEN);
9899 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9902 if (GET_CODE (operands[1]) != CONST_INT
9903 || INTVAL (operands[1]) < -32767
9904 || INTVAL (operands[1]) > 32768)
9906 neg_op0 = gen_reg_rtx (Pmode);
9908 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9910 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9913 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9916 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9917 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9921 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9922 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9923 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9926 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9930 ;; These patterns say how to save and restore the stack pointer. We need not
9931 ;; save the stack pointer at function level since we are careful to
9932 ;; preserve the backchain. At block level, we have to restore the backchain
9933 ;; when we restore the stack pointer.
9935 ;; For nonlocal gotos, we must save both the stack pointer and its
9936 ;; backchain and restore both. Note that in the nonlocal case, the
9937 ;; save area is a memory location.
9939 (define_expand "save_stack_function"
9940 [(match_operand 0 "any_operand" "")
9941 (match_operand 1 "any_operand" "")]
9945 (define_expand "restore_stack_function"
9946 [(match_operand 0 "any_operand" "")
9947 (match_operand 1 "any_operand" "")]
9951 (define_expand "restore_stack_block"
9952 [(use (match_operand 0 "register_operand" ""))
9953 (set (match_dup 2) (match_dup 3))
9954 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9955 (set (match_dup 3) (match_dup 2))]
9959 operands[2] = gen_reg_rtx (Pmode);
9960 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9963 (define_expand "save_stack_nonlocal"
9964 [(match_operand 0 "memory_operand" "")
9965 (match_operand 1 "register_operand" "")]
9969 rtx temp = gen_reg_rtx (Pmode);
9970 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9972 /* Copy the backchain to the first word, sp to the second. */
9973 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9974 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9975 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
9980 (define_expand "restore_stack_nonlocal"
9981 [(match_operand 0 "register_operand" "")
9982 (match_operand 1 "memory_operand" "")]
9986 rtx temp = gen_reg_rtx (Pmode);
9987 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9989 /* Restore the backchain from the first word, sp from the second. */
9990 emit_move_insn (temp,
9991 adjust_address_nv (operands[1], Pmode, 0));
9992 emit_move_insn (operands[0],
9993 adjust_address_nv (operands[1], Pmode, units_per_word));
9994 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9998 ;; TOC register handling.
10000 ;; Code to initialize the TOC register...
10002 (define_insn "load_toc_aix_si"
10003 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10004 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10005 (use (reg:SI 2))])]
10006 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10010 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10011 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10012 operands[2] = gen_rtx_REG (Pmode, 2);
10013 return \"{l|lwz} %0,%1(%2)\";
10015 [(set_attr "type" "load")])
10017 (define_insn "load_toc_aix_di"
10018 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10019 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10020 (use (reg:DI 2))])]
10021 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10025 #ifdef TARGET_RELOCATABLE
10026 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10027 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10029 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10032 strcat (buf, \"@toc\");
10033 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10034 operands[2] = gen_rtx_REG (Pmode, 2);
10035 return \"ld %0,%1(%2)\";
10037 [(set_attr "type" "load")])
10039 (define_insn "load_toc_v4_pic_si"
10040 [(set (match_operand:SI 0 "register_operand" "=l")
10041 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10042 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10043 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10044 [(set_attr "type" "branch")
10045 (set_attr "length" "4")])
10047 (define_insn "load_toc_v4_PIC_1"
10048 [(set (match_operand:SI 0 "register_operand" "=l")
10049 (match_operand:SI 1 "immediate_operand" "s"))
10050 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10051 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10052 "bcl 20,31,%1\\n%1:"
10053 [(set_attr "type" "branch")
10054 (set_attr "length" "4")])
10056 (define_insn "load_toc_v4_PIC_1b"
10057 [(set (match_operand:SI 0 "register_operand" "=l")
10058 (match_operand:SI 1 "immediate_operand" "s"))
10059 (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")]
10061 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10062 "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1"
10063 [(set_attr "type" "branch")
10064 (set_attr "length" "8")])
10066 (define_insn "load_toc_v4_PIC_2"
10067 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10068 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10069 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10070 (match_operand:SI 3 "immediate_operand" "s")))))]
10071 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10072 "{l|lwz} %0,%2-%3(%1)"
10073 [(set_attr "type" "load")])
10076 ;; If the TOC is shared over a translation unit, as happens with all
10077 ;; the kinds of PIC that we support, we need to restore the TOC
10078 ;; pointer only when jumping over units of translation.
10079 ;; On Darwin, we need to reload the picbase.
10081 (define_expand "builtin_setjmp_receiver"
10082 [(use (label_ref (match_operand 0 "" "")))]
10083 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10084 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10085 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10089 if (DEFAULT_ABI == ABI_DARWIN)
10091 const char *picbase = machopic_function_base_name ();
10092 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10093 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10097 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10098 CODE_LABEL_NUMBER (operands[0]));
10099 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10101 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10102 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10106 rs6000_emit_load_toc_table (FALSE);
10110 ;; A function pointer under AIX is a pointer to a data area whose first word
10111 ;; contains the actual address of the function, whose second word contains a
10112 ;; pointer to its TOC, and whose third word contains a value to place in the
10113 ;; static chain register (r11). Note that if we load the static chain, our
10114 ;; "trampoline" need not have any executable code.
10116 (define_expand "call_indirect_aix32"
10117 [(set (match_dup 2)
10118 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10119 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10122 (mem:SI (plus:SI (match_dup 0)
10125 (mem:SI (plus:SI (match_dup 0)
10127 (parallel [(call (mem:SI (match_dup 2))
10128 (match_operand 1 "" ""))
10132 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10133 (clobber (scratch:SI))])]
10136 { operands[2] = gen_reg_rtx (SImode); }")
10138 (define_expand "call_indirect_aix64"
10139 [(set (match_dup 2)
10140 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10141 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10144 (mem:DI (plus:DI (match_dup 0)
10147 (mem:DI (plus:DI (match_dup 0)
10149 (parallel [(call (mem:SI (match_dup 2))
10150 (match_operand 1 "" ""))
10154 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10155 (clobber (scratch:SI))])]
10158 { operands[2] = gen_reg_rtx (DImode); }")
10160 (define_expand "call_value_indirect_aix32"
10161 [(set (match_dup 3)
10162 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10163 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10166 (mem:SI (plus:SI (match_dup 1)
10169 (mem:SI (plus:SI (match_dup 1)
10171 (parallel [(set (match_operand 0 "" "")
10172 (call (mem:SI (match_dup 3))
10173 (match_operand 2 "" "")))
10177 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10178 (clobber (scratch:SI))])]
10181 { operands[3] = gen_reg_rtx (SImode); }")
10183 (define_expand "call_value_indirect_aix64"
10184 [(set (match_dup 3)
10185 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10186 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10189 (mem:DI (plus:DI (match_dup 1)
10192 (mem:DI (plus:DI (match_dup 1)
10194 (parallel [(set (match_operand 0 "" "")
10195 (call (mem:SI (match_dup 3))
10196 (match_operand 2 "" "")))
10200 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10201 (clobber (scratch:SI))])]
10204 { operands[3] = gen_reg_rtx (DImode); }")
10206 ;; Now the definitions for the call and call_value insns
10207 (define_expand "call"
10208 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10209 (match_operand 1 "" ""))
10210 (use (match_operand 2 "" ""))
10211 (clobber (scratch:SI))])]
10216 if (MACHOPIC_INDIRECT)
10217 operands[0] = machopic_indirect_call_target (operands[0]);
10220 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10223 operands[0] = XEXP (operands[0], 0);
10225 if (GET_CODE (operands[0]) != SYMBOL_REF
10226 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10227 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10229 if (INTVAL (operands[2]) & CALL_LONG)
10230 operands[0] = rs6000_longcall_ref (operands[0]);
10232 if (DEFAULT_ABI == ABI_V4
10233 || DEFAULT_ABI == ABI_DARWIN)
10234 operands[0] = force_reg (Pmode, operands[0]);
10236 else if (DEFAULT_ABI == ABI_AIX)
10238 /* AIX function pointers are really pointers to a three word
10240 emit_call_insn (TARGET_32BIT
10241 ? gen_call_indirect_aix32 (force_reg (SImode,
10244 : gen_call_indirect_aix64 (force_reg (DImode,
10254 (define_expand "call_value"
10255 [(parallel [(set (match_operand 0 "" "")
10256 (call (mem:SI (match_operand 1 "address_operand" ""))
10257 (match_operand 2 "" "")))
10258 (use (match_operand 3 "" ""))
10259 (clobber (scratch:SI))])]
10264 if (MACHOPIC_INDIRECT)
10265 operands[1] = machopic_indirect_call_target (operands[1]);
10268 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10271 operands[1] = XEXP (operands[1], 0);
10273 if (GET_CODE (operands[1]) != SYMBOL_REF
10274 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10275 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10277 if (INTVAL (operands[3]) & CALL_LONG)
10278 operands[1] = rs6000_longcall_ref (operands[1]);
10280 if (DEFAULT_ABI == ABI_V4
10281 || DEFAULT_ABI == ABI_DARWIN)
10282 operands[1] = force_reg (Pmode, operands[1]);
10284 else if (DEFAULT_ABI == ABI_AIX)
10286 /* AIX function pointers are really pointers to a three word
10288 emit_call_insn (TARGET_32BIT
10289 ? gen_call_value_indirect_aix32 (operands[0],
10293 : gen_call_value_indirect_aix64 (operands[0],
10304 ;; Call to function in current module. No TOC pointer reload needed.
10305 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10306 ;; either the function was not prototyped, or it was prototyped as a
10307 ;; variable argument function. It is > 0 if FP registers were passed
10308 ;; and < 0 if they were not.
10310 (define_insn "*call_local32"
10311 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10312 (match_operand 1 "" "g,g"))
10313 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10314 (clobber (match_scratch:SI 3 "=l,l"))]
10315 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10318 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10319 output_asm_insn (\"crxor 6,6,6\", operands);
10321 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10322 output_asm_insn (\"creqv 6,6,6\", operands);
10324 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10326 [(set_attr "type" "branch")
10327 (set_attr "length" "4,8")])
10329 (define_insn "*call_local64"
10330 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10331 (match_operand 1 "" "g,g"))
10332 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10333 (clobber (match_scratch:SI 3 "=l,l"))]
10334 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10337 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10338 output_asm_insn (\"crxor 6,6,6\", operands);
10340 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10341 output_asm_insn (\"creqv 6,6,6\", operands);
10343 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10345 [(set_attr "type" "branch")
10346 (set_attr "length" "4,8")])
10348 (define_insn "*call_value_local32"
10349 [(set (match_operand 0 "" "")
10350 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10351 (match_operand 2 "" "g,g")))
10352 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10353 (clobber (match_scratch:SI 4 "=l,l"))]
10354 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10357 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10358 output_asm_insn (\"crxor 6,6,6\", operands);
10360 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10361 output_asm_insn (\"creqv 6,6,6\", operands);
10363 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10365 [(set_attr "type" "branch")
10366 (set_attr "length" "4,8")])
10369 (define_insn "*call_value_local64"
10370 [(set (match_operand 0 "" "")
10371 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10372 (match_operand 2 "" "g,g")))
10373 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10374 (clobber (match_scratch:SI 4 "=l,l"))]
10375 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10378 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10379 output_asm_insn (\"crxor 6,6,6\", operands);
10381 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10382 output_asm_insn (\"creqv 6,6,6\", operands);
10384 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10386 [(set_attr "type" "branch")
10387 (set_attr "length" "4,8")])
10389 ;; Call to function which may be in another module. Restore the TOC
10390 ;; pointer (r2) after the call unless this is System V.
10391 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10392 ;; either the function was not prototyped, or it was prototyped as a
10393 ;; variable argument function. It is > 0 if FP registers were passed
10394 ;; and < 0 if they were not.
10396 (define_insn "*call_indirect_nonlocal_aix32"
10397 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10398 (match_operand 1 "" "g"))
10402 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10403 (clobber (match_scratch:SI 2 "=l"))]
10404 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10405 "b%T0l\;{l|lwz} 2,20(1)"
10406 [(set_attr "type" "jmpreg")
10407 (set_attr "length" "8")])
10409 (define_insn "*call_nonlocal_aix32"
10410 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10411 (match_operand 1 "" "g"))
10412 (use (match_operand:SI 2 "immediate_operand" "O"))
10413 (clobber (match_scratch:SI 3 "=l"))]
10415 && DEFAULT_ABI == ABI_AIX
10416 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10418 [(set_attr "type" "branch")
10419 (set_attr "length" "8")])
10421 (define_insn "*call_indirect_nonlocal_aix64"
10422 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10423 (match_operand 1 "" "g"))
10427 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10428 (clobber (match_scratch:SI 2 "=l"))]
10429 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10430 "b%T0l\;ld 2,40(1)"
10431 [(set_attr "type" "jmpreg")
10432 (set_attr "length" "8")])
10434 (define_insn "*call_nonlocal_aix64"
10435 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10436 (match_operand 1 "" "g"))
10437 (use (match_operand:SI 2 "immediate_operand" "O"))
10438 (clobber (match_scratch:SI 3 "=l"))]
10440 && DEFAULT_ABI == ABI_AIX
10441 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10443 [(set_attr "type" "branch")
10444 (set_attr "length" "8")])
10446 (define_insn "*call_value_indirect_nonlocal_aix32"
10447 [(set (match_operand 0 "" "")
10448 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10449 (match_operand 2 "" "g")))
10453 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10454 (clobber (match_scratch:SI 3 "=l"))]
10455 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10456 "b%T1l\;{l|lwz} 2,20(1)"
10457 [(set_attr "type" "jmpreg")
10458 (set_attr "length" "8")])
10460 (define_insn "*call_value_nonlocal_aix32"
10461 [(set (match_operand 0 "" "")
10462 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10463 (match_operand 2 "" "g")))
10464 (use (match_operand:SI 3 "immediate_operand" "O"))
10465 (clobber (match_scratch:SI 4 "=l"))]
10467 && DEFAULT_ABI == ABI_AIX
10468 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10470 [(set_attr "type" "branch")
10471 (set_attr "length" "8")])
10473 (define_insn "*call_value_indirect_nonlocal_aix64"
10474 [(set (match_operand 0 "" "")
10475 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10476 (match_operand 2 "" "g")))
10480 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10481 (clobber (match_scratch:SI 3 "=l"))]
10482 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10483 "b%T1l\;ld 2,40(1)"
10484 [(set_attr "type" "jmpreg")
10485 (set_attr "length" "8")])
10487 (define_insn "*call_value_nonlocal_aix64"
10488 [(set (match_operand 0 "" "")
10489 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10490 (match_operand 2 "" "g")))
10491 (use (match_operand:SI 3 "immediate_operand" "O"))
10492 (clobber (match_scratch:SI 4 "=l"))]
10494 && DEFAULT_ABI == ABI_AIX
10495 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10497 [(set_attr "type" "branch")
10498 (set_attr "length" "8")])
10500 ;; A function pointer under System V is just a normal pointer
10501 ;; operands[0] is the function pointer
10502 ;; operands[1] is the stack size to clean up
10503 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10504 ;; which indicates how to set cr1
10506 (define_insn "*call_indirect_nonlocal_sysv"
10507 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10508 (match_operand 1 "" "g,g"))
10509 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10510 (clobber (match_scratch:SI 3 "=l,l"))]
10511 "DEFAULT_ABI == ABI_V4
10512 || DEFAULT_ABI == ABI_DARWIN"
10514 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10515 output_asm_insn ("crxor 6,6,6", operands);
10517 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10518 output_asm_insn ("creqv 6,6,6", operands);
10522 [(set_attr "type" "jmpreg,jmpreg")
10523 (set_attr "length" "4,8")])
10525 (define_insn "*call_nonlocal_sysv"
10526 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10527 (match_operand 1 "" "g,g"))
10528 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10529 (clobber (match_scratch:SI 3 "=l,l"))]
10530 "(DEFAULT_ABI == ABI_DARWIN
10531 || (DEFAULT_ABI == ABI_V4
10532 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10534 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10535 output_asm_insn ("crxor 6,6,6", operands);
10537 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10538 output_asm_insn ("creqv 6,6,6", operands);
10541 return output_call(insn, operands, 0, 2);
10543 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10546 [(set_attr "type" "branch,branch")
10547 (set_attr "length" "4,8")])
10549 (define_insn "*call_value_indirect_nonlocal_sysv"
10550 [(set (match_operand 0 "" "")
10551 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10552 (match_operand 2 "" "g,g")))
10553 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10554 (clobber (match_scratch:SI 4 "=l,l"))]
10555 "DEFAULT_ABI == ABI_V4
10556 || DEFAULT_ABI == ABI_DARWIN"
10558 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10559 output_asm_insn ("crxor 6,6,6", operands);
10561 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10562 output_asm_insn ("creqv 6,6,6", operands);
10566 [(set_attr "type" "jmpreg,jmpreg")
10567 (set_attr "length" "4,8")])
10569 (define_insn "*call_value_nonlocal_sysv"
10570 [(set (match_operand 0 "" "")
10571 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10572 (match_operand 2 "" "g,g")))
10573 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10574 (clobber (match_scratch:SI 4 "=l,l"))]
10575 "(DEFAULT_ABI == ABI_DARWIN
10576 || (DEFAULT_ABI == ABI_V4
10577 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10579 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10580 output_asm_insn ("crxor 6,6,6", operands);
10582 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10583 output_asm_insn ("creqv 6,6,6", operands);
10586 return output_call(insn, operands, 1, 3);
10588 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10591 [(set_attr "type" "branch,branch")
10592 (set_attr "length" "4,8")])
10594 ;; Call subroutine returning any type.
10595 (define_expand "untyped_call"
10596 [(parallel [(call (match_operand 0 "" "")
10598 (match_operand 1 "" "")
10599 (match_operand 2 "" "")])]
10605 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10607 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10609 rtx set = XVECEXP (operands[2], 0, i);
10610 emit_move_insn (SET_DEST (set), SET_SRC (set));
10613 /* The optimizer does not know that the call sets the function value
10614 registers we stored in the result block. We avoid problems by
10615 claiming that all hard registers are used and clobbered at this
10617 emit_insn (gen_blockage ());
10622 ;; sibling call patterns
10623 (define_expand "sibcall"
10624 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10625 (match_operand 1 "" ""))
10626 (use (match_operand 2 "" ""))
10627 (use (match_operand 3 "" ""))
10633 if (MACHOPIC_INDIRECT)
10634 operands[0] = machopic_indirect_call_target (operands[0]);
10637 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10640 operands[0] = XEXP (operands[0], 0);
10641 operands[3] = gen_reg_rtx (SImode);
10645 ;; this and similar patterns must be marked as using LR, otherwise
10646 ;; dataflow will try to delete the store into it. This is true
10647 ;; even when the actual reg to jump to is in CTR, when LR was
10648 ;; saved and restored around the PIC-setting BCL.
10649 (define_insn "*sibcall_local32"
10650 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10651 (match_operand 1 "" "g,g"))
10652 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10653 (use (match_operand:SI 3 "register_operand" "l,l"))
10655 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10658 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10659 output_asm_insn (\"crxor 6,6,6\", operands);
10661 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10662 output_asm_insn (\"creqv 6,6,6\", operands);
10664 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10666 [(set_attr "type" "branch")
10667 (set_attr "length" "4,8")])
10669 (define_insn "*sibcall_local64"
10670 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10671 (match_operand 1 "" "g,g"))
10672 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10673 (use (match_operand:SI 3 "register_operand" "l,l"))
10675 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10678 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10679 output_asm_insn (\"crxor 6,6,6\", operands);
10681 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10682 output_asm_insn (\"creqv 6,6,6\", operands);
10684 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10686 [(set_attr "type" "branch")
10687 (set_attr "length" "4,8")])
10689 (define_insn "*sibcall_value_local32"
10690 [(set (match_operand 0 "" "")
10691 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10692 (match_operand 2 "" "g,g")))
10693 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10694 (use (match_operand:SI 4 "register_operand" "l,l"))
10696 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10699 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10700 output_asm_insn (\"crxor 6,6,6\", operands);
10702 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10703 output_asm_insn (\"creqv 6,6,6\", operands);
10705 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10707 [(set_attr "type" "branch")
10708 (set_attr "length" "4,8")])
10711 (define_insn "*sibcall_value_local64"
10712 [(set (match_operand 0 "" "")
10713 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10714 (match_operand 2 "" "g,g")))
10715 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10716 (use (match_operand:SI 4 "register_operand" "l,l"))
10718 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10721 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10722 output_asm_insn (\"crxor 6,6,6\", operands);
10724 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10725 output_asm_insn (\"creqv 6,6,6\", operands);
10727 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10729 [(set_attr "type" "branch")
10730 (set_attr "length" "4,8")])
10732 (define_insn "*sibcall_nonlocal_aix32"
10733 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10734 (match_operand 1 "" "g"))
10735 (use (match_operand:SI 2 "immediate_operand" "O"))
10736 (use (match_operand:SI 3 "register_operand" "l"))
10739 && DEFAULT_ABI == ABI_AIX
10740 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10742 [(set_attr "type" "branch")
10743 (set_attr "length" "4")])
10745 (define_insn "*sibcall_nonlocal_aix64"
10746 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10747 (match_operand 1 "" "g"))
10748 (use (match_operand:SI 2 "immediate_operand" "O"))
10749 (use (match_operand:SI 3 "register_operand" "l"))
10752 && DEFAULT_ABI == ABI_AIX
10753 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10755 [(set_attr "type" "branch")
10756 (set_attr "length" "4")])
10758 (define_insn "*sibcall_value_nonlocal_aix32"
10759 [(set (match_operand 0 "" "")
10760 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10761 (match_operand 2 "" "g")))
10762 (use (match_operand:SI 3 "immediate_operand" "O"))
10763 (use (match_operand:SI 4 "register_operand" "l"))
10766 && DEFAULT_ABI == ABI_AIX
10767 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10769 [(set_attr "type" "branch")
10770 (set_attr "length" "4")])
10772 (define_insn "*sibcall_value_nonlocal_aix64"
10773 [(set (match_operand 0 "" "")
10774 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10775 (match_operand 2 "" "g")))
10776 (use (match_operand:SI 3 "immediate_operand" "O"))
10777 (use (match_operand:SI 4 "register_operand" "l"))
10780 && DEFAULT_ABI == ABI_AIX
10781 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10783 [(set_attr "type" "branch")
10784 (set_attr "length" "4")])
10786 (define_insn "*sibcall_nonlocal_sysv"
10787 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10788 (match_operand 1 "" ""))
10789 (use (match_operand 2 "immediate_operand" "O,n"))
10790 (use (match_operand:SI 3 "register_operand" "l,l"))
10792 "(DEFAULT_ABI == ABI_DARWIN
10793 || DEFAULT_ABI == ABI_V4)
10794 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10797 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10798 output_asm_insn (\"crxor 6,6,6\", operands);
10800 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10801 output_asm_insn (\"creqv 6,6,6\", operands);
10803 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10805 [(set_attr "type" "branch,branch")
10806 (set_attr "length" "4,8")])
10808 (define_expand "sibcall_value"
10809 [(parallel [(set (match_operand 0 "register_operand" "")
10810 (call (mem:SI (match_operand 1 "address_operand" ""))
10811 (match_operand 2 "" "")))
10812 (use (match_operand 3 "" ""))
10813 (use (match_operand 4 "" ""))
10819 if (MACHOPIC_INDIRECT)
10820 operands[1] = machopic_indirect_call_target (operands[1]);
10823 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10826 operands[1] = XEXP (operands[1], 0);
10827 operands[4] = gen_reg_rtx (SImode);
10831 (define_insn "*sibcall_value_nonlocal_sysv"
10832 [(set (match_operand 0 "" "")
10833 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10834 (match_operand 2 "" "")))
10835 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10836 (use (match_operand:SI 4 "register_operand" "l,l"))
10838 "(DEFAULT_ABI == ABI_DARWIN
10839 || DEFAULT_ABI == ABI_V4)
10840 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10843 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10844 output_asm_insn (\"crxor 6,6,6\", operands);
10846 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10847 output_asm_insn (\"creqv 6,6,6\", operands);
10849 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10851 [(set_attr "type" "branch,branch")
10852 (set_attr "length" "4,8")])
10854 (define_expand "sibcall_epilogue"
10855 [(use (const_int 0))]
10856 "TARGET_SCHED_PROLOG"
10859 rs6000_emit_epilogue (TRUE);
10863 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10864 ;; all of memory. This blocks insns from being moved across this point.
10866 (define_insn "blockage"
10867 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10871 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10872 ;; signed & unsigned, and one type of branch.
10874 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10875 ;; insns, and branches. We store the operands of compares until we see
10877 (define_expand "cmpsi"
10879 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10880 (match_operand:SI 1 "reg_or_short_operand" "")))]
10884 /* Take care of the possibility that operands[1] might be negative but
10885 this might be a logical operation. That insn doesn't exist. */
10886 if (GET_CODE (operands[1]) == CONST_INT
10887 && INTVAL (operands[1]) < 0)
10888 operands[1] = force_reg (SImode, operands[1]);
10890 rs6000_compare_op0 = operands[0];
10891 rs6000_compare_op1 = operands[1];
10892 rs6000_compare_fp_p = 0;
10896 (define_expand "cmpdi"
10898 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10899 (match_operand:DI 1 "reg_or_short_operand" "")))]
10903 /* Take care of the possibility that operands[1] might be negative but
10904 this might be a logical operation. That insn doesn't exist. */
10905 if (GET_CODE (operands[1]) == CONST_INT
10906 && INTVAL (operands[1]) < 0)
10907 operands[1] = force_reg (DImode, operands[1]);
10909 rs6000_compare_op0 = operands[0];
10910 rs6000_compare_op1 = operands[1];
10911 rs6000_compare_fp_p = 0;
10915 (define_expand "cmpsf"
10916 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10917 (match_operand:SF 1 "gpc_reg_operand" "")))]
10918 "TARGET_HARD_FLOAT"
10921 rs6000_compare_op0 = operands[0];
10922 rs6000_compare_op1 = operands[1];
10923 rs6000_compare_fp_p = 1;
10927 (define_expand "cmpdf"
10928 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10929 (match_operand:DF 1 "gpc_reg_operand" "")))]
10930 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
10933 rs6000_compare_op0 = operands[0];
10934 rs6000_compare_op1 = operands[1];
10935 rs6000_compare_fp_p = 1;
10939 (define_expand "cmptf"
10940 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10941 (match_operand:TF 1 "gpc_reg_operand" "")))]
10942 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10943 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10946 rs6000_compare_op0 = operands[0];
10947 rs6000_compare_op1 = operands[1];
10948 rs6000_compare_fp_p = 1;
10952 (define_expand "beq"
10953 [(use (match_operand 0 "" ""))]
10955 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10957 (define_expand "bne"
10958 [(use (match_operand 0 "" ""))]
10960 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10962 (define_expand "bge"
10963 [(use (match_operand 0 "" ""))]
10965 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10967 (define_expand "bgt"
10968 [(use (match_operand 0 "" ""))]
10970 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10972 (define_expand "ble"
10973 [(use (match_operand 0 "" ""))]
10975 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10977 (define_expand "blt"
10978 [(use (match_operand 0 "" ""))]
10980 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10982 (define_expand "bgeu"
10983 [(use (match_operand 0 "" ""))]
10985 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10987 (define_expand "bgtu"
10988 [(use (match_operand 0 "" ""))]
10990 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10992 (define_expand "bleu"
10993 [(use (match_operand 0 "" ""))]
10995 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10997 (define_expand "bltu"
10998 [(use (match_operand 0 "" ""))]
11000 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11002 (define_expand "bunordered"
11003 [(use (match_operand 0 "" ""))]
11004 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11005 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11007 (define_expand "bordered"
11008 [(use (match_operand 0 "" ""))]
11009 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11010 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11012 (define_expand "buneq"
11013 [(use (match_operand 0 "" ""))]
11015 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11017 (define_expand "bunge"
11018 [(use (match_operand 0 "" ""))]
11020 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11022 (define_expand "bungt"
11023 [(use (match_operand 0 "" ""))]
11025 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11027 (define_expand "bunle"
11028 [(use (match_operand 0 "" ""))]
11030 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11032 (define_expand "bunlt"
11033 [(use (match_operand 0 "" ""))]
11035 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11037 (define_expand "bltgt"
11038 [(use (match_operand 0 "" ""))]
11040 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11042 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11043 ;; For SEQ, likewise, except that comparisons with zero should be done
11044 ;; with an scc insns. However, due to the order that combine see the
11045 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11046 ;; the cases we don't want to handle.
11047 (define_expand "seq"
11048 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11050 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11052 (define_expand "sne"
11053 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11057 if (! rs6000_compare_fp_p)
11060 rs6000_emit_sCOND (NE, operands[0]);
11064 ;; A >= 0 is best done the portable way for A an integer.
11065 (define_expand "sge"
11066 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11070 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11073 rs6000_emit_sCOND (GE, operands[0]);
11077 ;; A > 0 is best done using the portable sequence, so fail in that case.
11078 (define_expand "sgt"
11079 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11083 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11086 rs6000_emit_sCOND (GT, operands[0]);
11090 ;; A <= 0 is best done the portable way for A an integer.
11091 (define_expand "sle"
11092 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11096 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11099 rs6000_emit_sCOND (LE, operands[0]);
11103 ;; A < 0 is best done in the portable way for A an integer.
11104 (define_expand "slt"
11105 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11109 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11112 rs6000_emit_sCOND (LT, operands[0]);
11116 (define_expand "sgeu"
11117 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11119 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11121 (define_expand "sgtu"
11122 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11124 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11126 (define_expand "sleu"
11127 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11129 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11131 (define_expand "sltu"
11132 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11134 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11136 (define_expand "sunordered"
11137 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11139 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11141 (define_expand "sordered"
11142 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11144 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11146 (define_expand "suneq"
11147 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11149 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11151 (define_expand "sunge"
11152 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11154 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11156 (define_expand "sungt"
11157 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11159 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11161 (define_expand "sunle"
11162 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11164 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11166 (define_expand "sunlt"
11167 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11169 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11171 (define_expand "sltgt"
11172 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11174 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11177 ;; Here are the actual compare insns.
11178 (define_insn "*cmpsi_internal1"
11179 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11180 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11181 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11183 "{cmp%I2|cmpw%I2} %0,%1,%2"
11184 [(set_attr "type" "cmp")])
11186 (define_insn "*cmpdi_internal1"
11187 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11188 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11189 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11192 [(set_attr "type" "cmp")])
11194 ;; If we are comparing a register for equality with a large constant,
11195 ;; we can do this with an XOR followed by a compare. But we need a scratch
11196 ;; register for the result of the XOR.
11199 [(set (match_operand:CC 0 "cc_reg_operand" "")
11200 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11201 (match_operand:SI 2 "non_short_cint_operand" "")))
11202 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11203 "find_single_use (operands[0], insn, 0)
11204 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11205 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11206 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11207 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11210 /* Get the constant we are comparing against, C, and see what it looks like
11211 sign-extended to 16 bits. Then see what constant could be XOR'ed
11212 with C to get the sign-extended value. */
11214 HOST_WIDE_INT c = INTVAL (operands[2]);
11215 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11216 HOST_WIDE_INT xorv = c ^ sextc;
11218 operands[4] = GEN_INT (xorv);
11219 operands[5] = GEN_INT (sextc);
11222 (define_insn "*cmpsi_internal2"
11223 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11224 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11225 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11227 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11228 [(set_attr "type" "cmp")])
11230 (define_insn "*cmpdi_internal2"
11231 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11232 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11233 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11235 "cmpld%I2 %0,%1,%b2"
11236 [(set_attr "type" "cmp")])
11238 ;; The following two insns don't exist as single insns, but if we provide
11239 ;; them, we can swap an add and compare, which will enable us to overlap more
11240 ;; of the required delay between a compare and branch. We generate code for
11241 ;; them by splitting.
11244 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11245 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11246 (match_operand:SI 2 "short_cint_operand" "i")))
11247 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11248 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11251 [(set_attr "length" "8")])
11254 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11255 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11256 (match_operand:SI 2 "u_short_cint_operand" "i")))
11257 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11258 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11261 [(set_attr "length" "8")])
11264 [(set (match_operand:CC 3 "cc_reg_operand" "")
11265 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11266 (match_operand:SI 2 "short_cint_operand" "")))
11267 (set (match_operand:SI 0 "gpc_reg_operand" "")
11268 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11270 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11271 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11274 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11275 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11276 (match_operand:SI 2 "u_short_cint_operand" "")))
11277 (set (match_operand:SI 0 "gpc_reg_operand" "")
11278 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11280 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11281 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11283 (define_insn "*cmpsf_internal1"
11284 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11285 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11286 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11287 "TARGET_HARD_FLOAT && TARGET_FPRS"
11289 [(set_attr "type" "fpcompare")])
11291 (define_insn "*cmpdf_internal1"
11292 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11293 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11294 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11295 "TARGET_HARD_FLOAT && TARGET_FPRS"
11297 [(set_attr "type" "fpcompare")])
11299 ;; Only need to compare second words if first words equal
11300 (define_insn "*cmptf_internal1"
11301 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11302 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11303 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11304 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11305 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11306 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11307 [(set_attr "type" "fpcompare")
11308 (set_attr "length" "12")])
11310 ;; Now we have the scc insns. We can do some combinations because of the
11311 ;; way the machine works.
11313 ;; Note that this is probably faster if we can put an insn between the
11314 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11315 ;; cases the insns below which don't use an intermediate CR field will
11316 ;; be used instead.
11318 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11319 (match_operator:SI 1 "scc_comparison_operator"
11320 [(match_operand 2 "cc_reg_operand" "y")
11323 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11324 [(set (attr "type")
11325 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11326 (const_string "mfcrf")
11328 (const_string "mfcr")))
11329 (set_attr "length" "8")])
11331 ;; Same as above, but get the GT bit.
11332 (define_insn "move_from_CR_eq_bit"
11333 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11334 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))]
11336 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
11337 [(set_attr "type" "mfcr")
11338 (set_attr "length" "8")])
11340 ;; Same as above, but get the OV/ORDERED bit.
11341 (define_insn "move_from_CR_ov_bit"
11342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11343 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11345 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11346 [(set_attr "type" "mfcr")
11347 (set_attr "length" "8")])
11350 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11351 (match_operator:DI 1 "scc_comparison_operator"
11352 [(match_operand 2 "cc_reg_operand" "y")
11355 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11356 [(set (attr "type")
11357 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11358 (const_string "mfcrf")
11360 (const_string "mfcr")))
11361 (set_attr "length" "8")])
11364 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11365 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11366 [(match_operand 2 "cc_reg_operand" "y,y")
11369 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11370 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11373 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11375 [(set_attr "type" "delayed_compare")
11376 (set_attr "length" "8,16")])
11379 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11380 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11381 [(match_operand 2 "cc_reg_operand" "")
11384 (set (match_operand:SI 3 "gpc_reg_operand" "")
11385 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11386 "TARGET_32BIT && reload_completed"
11387 [(set (match_dup 3)
11388 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11390 (compare:CC (match_dup 3)
11395 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11396 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11397 [(match_operand 2 "cc_reg_operand" "y")
11399 (match_operand:SI 3 "const_int_operand" "n")))]
11403 int is_bit = ccr_bit (operands[1], 1);
11404 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11407 if (is_bit >= put_bit)
11408 count = is_bit - put_bit;
11410 count = 32 - (put_bit - is_bit);
11412 operands[4] = GEN_INT (count);
11413 operands[5] = GEN_INT (put_bit);
11415 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11417 [(set (attr "type")
11418 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11419 (const_string "mfcrf")
11421 (const_string "mfcr")))
11422 (set_attr "length" "8")])
11425 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11427 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11428 [(match_operand 2 "cc_reg_operand" "y,y")
11430 (match_operand:SI 3 "const_int_operand" "n,n"))
11432 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11433 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11438 int is_bit = ccr_bit (operands[1], 1);
11439 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11442 /* Force split for non-cc0 compare. */
11443 if (which_alternative == 1)
11446 if (is_bit >= put_bit)
11447 count = is_bit - put_bit;
11449 count = 32 - (put_bit - is_bit);
11451 operands[5] = GEN_INT (count);
11452 operands[6] = GEN_INT (put_bit);
11454 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11456 [(set_attr "type" "delayed_compare")
11457 (set_attr "length" "8,16")])
11460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11462 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11463 [(match_operand 2 "cc_reg_operand" "")
11465 (match_operand:SI 3 "const_int_operand" ""))
11467 (set (match_operand:SI 4 "gpc_reg_operand" "")
11468 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11471 [(set (match_dup 4)
11472 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11475 (compare:CC (match_dup 4)
11479 ;; There is a 3 cycle delay between consecutive mfcr instructions
11480 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11483 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11484 (match_operator:SI 1 "scc_comparison_operator"
11485 [(match_operand 2 "cc_reg_operand" "y")
11487 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11488 (match_operator:SI 4 "scc_comparison_operator"
11489 [(match_operand 5 "cc_reg_operand" "y")
11491 "REGNO (operands[2]) != REGNO (operands[5])"
11492 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11493 [(set_attr "type" "mfcr")
11494 (set_attr "length" "12")])
11497 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11498 (match_operator:DI 1 "scc_comparison_operator"
11499 [(match_operand 2 "cc_reg_operand" "y")
11501 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11502 (match_operator:DI 4 "scc_comparison_operator"
11503 [(match_operand 5 "cc_reg_operand" "y")
11505 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11506 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11507 [(set_attr "type" "mfcr")
11508 (set_attr "length" "12")])
11510 ;; There are some scc insns that can be done directly, without a compare.
11511 ;; These are faster because they don't involve the communications between
11512 ;; the FXU and branch units. In fact, we will be replacing all of the
11513 ;; integer scc insns here or in the portable methods in emit_store_flag.
11515 ;; Also support (neg (scc ..)) since that construct is used to replace
11516 ;; branches, (plus (scc ..) ..) since that construct is common and
11517 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11518 ;; cases where it is no more expensive than (neg (scc ..)).
11520 ;; Have reload force a constant into a register for the simple insns that
11521 ;; otherwise won't accept constants. We do this because it is faster than
11522 ;; the cmp/mfcr sequence we would otherwise generate.
11525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11526 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11527 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11528 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11531 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11532 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11533 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11534 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11535 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11536 [(set_attr "type" "three,two,three,three,three")
11537 (set_attr "length" "12,8,12,12,12")])
11540 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11541 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11542 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11543 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11546 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11547 subfic %3,%1,0\;adde %0,%3,%1
11548 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11549 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11550 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11551 [(set_attr "type" "three,two,three,three,three")
11552 (set_attr "length" "12,8,12,12,12")])
11555 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11557 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11558 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11560 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11561 (eq:SI (match_dup 1) (match_dup 2)))
11562 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11565 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11566 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11567 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11568 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11569 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11575 [(set_attr "type" "compare")
11576 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11579 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11581 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11582 (match_operand:SI 2 "reg_or_cint_operand" ""))
11584 (set (match_operand:SI 0 "gpc_reg_operand" "")
11585 (eq:SI (match_dup 1) (match_dup 2)))
11586 (clobber (match_scratch:SI 3 ""))]
11587 "TARGET_32BIT && reload_completed"
11588 [(parallel [(set (match_dup 0)
11589 (eq:SI (match_dup 1) (match_dup 2)))
11590 (clobber (match_dup 3))])
11592 (compare:CC (match_dup 0)
11597 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11599 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11600 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11602 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11603 (eq:DI (match_dup 1) (match_dup 2)))
11604 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11607 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11608 subfic %3,%1,0\;adde. %0,%3,%1
11609 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11610 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11611 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11617 [(set_attr "type" "compare")
11618 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11621 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11623 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11624 (match_operand:DI 2 "reg_or_cint_operand" ""))
11626 (set (match_operand:DI 0 "gpc_reg_operand" "")
11627 (eq:DI (match_dup 1) (match_dup 2)))
11628 (clobber (match_scratch:DI 3 ""))]
11629 "TARGET_64BIT && reload_completed"
11630 [(parallel [(set (match_dup 0)
11631 (eq:DI (match_dup 1) (match_dup 2)))
11632 (clobber (match_dup 3))])
11634 (compare:CC (match_dup 0)
11638 ;; We have insns of the form shown by the first define_insn below. If
11639 ;; there is something inside the comparison operation, we must split it.
11641 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11642 (plus:SI (match_operator 1 "comparison_operator"
11643 [(match_operand:SI 2 "" "")
11644 (match_operand:SI 3
11645 "reg_or_cint_operand" "")])
11646 (match_operand:SI 4 "gpc_reg_operand" "")))
11647 (clobber (match_operand:SI 5 "register_operand" ""))]
11648 "! gpc_reg_operand (operands[2], SImode)"
11649 [(set (match_dup 5) (match_dup 2))
11650 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11654 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11655 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11656 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11657 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11660 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11661 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11662 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11663 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11664 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11665 [(set_attr "type" "three,two,three,three,three")
11666 (set_attr "length" "12,8,12,12,12")])
11669 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11672 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11673 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11674 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11676 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11679 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11680 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11681 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11682 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11683 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11689 [(set_attr "type" "compare")
11690 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11693 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11696 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11697 (match_operand:SI 2 "reg_or_cint_operand" ""))
11698 (match_operand:SI 3 "gpc_reg_operand" ""))
11700 (clobber (match_scratch:SI 4 ""))]
11701 "TARGET_32BIT && reload_completed"
11702 [(set (match_dup 4)
11703 (plus:SI (eq:SI (match_dup 1)
11707 (compare:CC (match_dup 4)
11712 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11715 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11716 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11717 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11719 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11720 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11723 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11724 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11725 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11726 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11727 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11733 [(set_attr "type" "compare")
11734 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11737 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11740 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11741 (match_operand:SI 2 "reg_or_cint_operand" ""))
11742 (match_operand:SI 3 "gpc_reg_operand" ""))
11744 (set (match_operand:SI 0 "gpc_reg_operand" "")
11745 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11746 "TARGET_32BIT && reload_completed"
11747 [(set (match_dup 0)
11748 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11750 (compare:CC (match_dup 0)
11755 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11756 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11757 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11760 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11761 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11762 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11763 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11764 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11765 [(set_attr "type" "three,two,three,three,three")
11766 (set_attr "length" "12,8,12,12,12")])
11768 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11769 ;; since it nabs/sr is just as fast.
11770 (define_insn "*ne0"
11771 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11772 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11774 (clobber (match_scratch:SI 2 "=&r"))]
11775 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11776 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11777 [(set_attr "type" "two")
11778 (set_attr "length" "8")])
11781 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11782 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11784 (clobber (match_scratch:DI 2 "=&r"))]
11786 "addic %2,%1,-1\;subfe %0,%2,%1"
11787 [(set_attr "type" "two")
11788 (set_attr "length" "8")])
11790 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11792 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11793 (plus:SI (lshiftrt:SI
11794 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11796 (match_operand:SI 2 "gpc_reg_operand" "r")))
11797 (clobber (match_scratch:SI 3 "=&r"))]
11799 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11800 [(set_attr "type" "two")
11801 (set_attr "length" "8")])
11804 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11805 (plus:DI (lshiftrt:DI
11806 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11808 (match_operand:DI 2 "gpc_reg_operand" "r")))
11809 (clobber (match_scratch:DI 3 "=&r"))]
11811 "addic %3,%1,-1\;addze %0,%2"
11812 [(set_attr "type" "two")
11813 (set_attr "length" "8")])
11816 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11818 (plus:SI (lshiftrt:SI
11819 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11821 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11823 (clobber (match_scratch:SI 3 "=&r,&r"))
11824 (clobber (match_scratch:SI 4 "=X,&r"))]
11827 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11829 [(set_attr "type" "compare")
11830 (set_attr "length" "8,12")])
11833 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11835 (plus:SI (lshiftrt:SI
11836 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11838 (match_operand:SI 2 "gpc_reg_operand" ""))
11840 (clobber (match_scratch:SI 3 ""))
11841 (clobber (match_scratch:SI 4 ""))]
11842 "TARGET_32BIT && reload_completed"
11843 [(parallel [(set (match_dup 3)
11844 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11847 (clobber (match_dup 4))])
11849 (compare:CC (match_dup 3)
11854 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11856 (plus:DI (lshiftrt:DI
11857 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11859 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11861 (clobber (match_scratch:DI 3 "=&r,&r"))]
11864 addic %3,%1,-1\;addze. %3,%2
11866 [(set_attr "type" "compare")
11867 (set_attr "length" "8,12")])
11870 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11872 (plus:DI (lshiftrt:DI
11873 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11875 (match_operand:DI 2 "gpc_reg_operand" ""))
11877 (clobber (match_scratch:DI 3 ""))]
11878 "TARGET_64BIT && reload_completed"
11879 [(set (match_dup 3)
11880 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11884 (compare:CC (match_dup 3)
11889 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11891 (plus:SI (lshiftrt:SI
11892 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11894 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11896 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11897 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11899 (clobber (match_scratch:SI 3 "=&r,&r"))]
11902 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11904 [(set_attr "type" "compare")
11905 (set_attr "length" "8,12")])
11908 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11910 (plus:SI (lshiftrt:SI
11911 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11913 (match_operand:SI 2 "gpc_reg_operand" ""))
11915 (set (match_operand:SI 0 "gpc_reg_operand" "")
11916 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11918 (clobber (match_scratch:SI 3 ""))]
11919 "TARGET_32BIT && reload_completed"
11920 [(parallel [(set (match_dup 0)
11921 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11923 (clobber (match_dup 3))])
11925 (compare:CC (match_dup 0)
11930 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11932 (plus:DI (lshiftrt:DI
11933 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11935 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11937 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11938 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11940 (clobber (match_scratch:DI 3 "=&r,&r"))]
11943 addic %3,%1,-1\;addze. %0,%2
11945 [(set_attr "type" "compare")
11946 (set_attr "length" "8,12")])
11949 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11951 (plus:DI (lshiftrt:DI
11952 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11954 (match_operand:DI 2 "gpc_reg_operand" ""))
11956 (set (match_operand:DI 0 "gpc_reg_operand" "")
11957 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11959 (clobber (match_scratch:DI 3 ""))]
11960 "TARGET_64BIT && reload_completed"
11961 [(parallel [(set (match_dup 0)
11962 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11964 (clobber (match_dup 3))])
11966 (compare:CC (match_dup 0)
11971 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11972 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11973 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11974 (clobber (match_scratch:SI 3 "=r,X"))]
11977 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11978 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11979 [(set_attr "length" "12")])
11982 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11984 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11985 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11987 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11988 (le:SI (match_dup 1) (match_dup 2)))
11989 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11992 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11993 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11996 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11997 (set_attr "length" "12,12,16,16")])
12000 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12002 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12003 (match_operand:SI 2 "reg_or_short_operand" ""))
12005 (set (match_operand:SI 0 "gpc_reg_operand" "")
12006 (le:SI (match_dup 1) (match_dup 2)))
12007 (clobber (match_scratch:SI 3 ""))]
12008 "TARGET_POWER && reload_completed"
12009 [(parallel [(set (match_dup 0)
12010 (le:SI (match_dup 1) (match_dup 2)))
12011 (clobber (match_dup 3))])
12013 (compare:CC (match_dup 0)
12018 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12019 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12020 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12021 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12024 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12025 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12026 [(set_attr "length" "12")])
12029 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12031 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12032 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12033 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12035 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12038 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12039 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12042 [(set_attr "type" "compare")
12043 (set_attr "length" "12,12,16,16")])
12046 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12048 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12049 (match_operand:SI 2 "reg_or_short_operand" ""))
12050 (match_operand:SI 3 "gpc_reg_operand" ""))
12052 (clobber (match_scratch:SI 4 ""))]
12053 "TARGET_POWER && reload_completed"
12054 [(set (match_dup 4)
12055 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12058 (compare:CC (match_dup 4)
12063 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12065 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12066 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12067 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12069 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12070 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12073 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12074 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12077 [(set_attr "type" "compare")
12078 (set_attr "length" "12,12,16,16")])
12081 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12083 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12084 (match_operand:SI 2 "reg_or_short_operand" ""))
12085 (match_operand:SI 3 "gpc_reg_operand" ""))
12087 (set (match_operand:SI 0 "gpc_reg_operand" "")
12088 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12089 "TARGET_POWER && reload_completed"
12090 [(set (match_dup 0)
12091 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12093 (compare:CC (match_dup 0)
12098 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12099 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12100 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12103 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12104 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12105 [(set_attr "length" "12")])
12108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12109 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12110 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12112 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12113 [(set_attr "type" "three")
12114 (set_attr "length" "12")])
12117 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12118 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12119 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12121 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12122 [(set_attr "type" "three")
12123 (set_attr "length" "12")])
12126 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12128 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12129 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12131 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12132 (leu:DI (match_dup 1) (match_dup 2)))]
12135 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12137 [(set_attr "type" "compare")
12138 (set_attr "length" "12,16")])
12141 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12143 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12144 (match_operand:DI 2 "reg_or_short_operand" ""))
12146 (set (match_operand:DI 0 "gpc_reg_operand" "")
12147 (leu:DI (match_dup 1) (match_dup 2)))]
12148 "TARGET_64BIT && reload_completed"
12149 [(set (match_dup 0)
12150 (leu:DI (match_dup 1) (match_dup 2)))
12152 (compare:CC (match_dup 0)
12157 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12159 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12160 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12162 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12163 (leu:SI (match_dup 1) (match_dup 2)))]
12166 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12168 [(set_attr "type" "compare")
12169 (set_attr "length" "12,16")])
12172 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12174 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12175 (match_operand:SI 2 "reg_or_short_operand" ""))
12177 (set (match_operand:SI 0 "gpc_reg_operand" "")
12178 (leu:SI (match_dup 1) (match_dup 2)))]
12179 "TARGET_32BIT && reload_completed"
12180 [(set (match_dup 0)
12181 (leu:SI (match_dup 1) (match_dup 2)))
12183 (compare:CC (match_dup 0)
12188 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12189 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12190 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12191 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12193 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12194 [(set_attr "type" "two")
12195 (set_attr "length" "8")])
12198 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12200 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12201 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12202 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12204 (clobber (match_scratch:SI 4 "=&r,&r"))]
12207 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12209 [(set_attr "type" "compare")
12210 (set_attr "length" "8,12")])
12213 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12215 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12216 (match_operand:SI 2 "reg_or_short_operand" ""))
12217 (match_operand:SI 3 "gpc_reg_operand" ""))
12219 (clobber (match_scratch:SI 4 ""))]
12220 "TARGET_32BIT && reload_completed"
12221 [(set (match_dup 4)
12222 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12225 (compare:CC (match_dup 4)
12230 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12232 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12233 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12234 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12236 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12237 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12240 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12242 [(set_attr "type" "compare")
12243 (set_attr "length" "8,12")])
12246 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12248 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12249 (match_operand:SI 2 "reg_or_short_operand" ""))
12250 (match_operand:SI 3 "gpc_reg_operand" ""))
12252 (set (match_operand:SI 0 "gpc_reg_operand" "")
12253 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12254 "TARGET_32BIT && reload_completed"
12255 [(set (match_dup 0)
12256 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12258 (compare:CC (match_dup 0)
12263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12264 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12265 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12267 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12268 [(set_attr "type" "three")
12269 (set_attr "length" "12")])
12272 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12274 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12275 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12276 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12278 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12279 [(set_attr "type" "three")
12280 (set_attr "length" "12")])
12283 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12286 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12287 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12288 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12290 (clobber (match_scratch:SI 4 "=&r,&r"))]
12293 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12295 [(set_attr "type" "compare")
12296 (set_attr "length" "12,16")])
12299 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12302 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12303 (match_operand:SI 2 "reg_or_short_operand" "")))
12304 (match_operand:SI 3 "gpc_reg_operand" ""))
12306 (clobber (match_scratch:SI 4 ""))]
12307 "TARGET_32BIT && reload_completed"
12308 [(set (match_dup 4)
12309 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12312 (compare:CC (match_dup 4)
12317 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12320 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12321 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12322 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12324 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12325 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12328 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12330 [(set_attr "type" "compare")
12331 (set_attr "length" "12,16")])
12334 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12337 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12338 (match_operand:SI 2 "reg_or_short_operand" "")))
12339 (match_operand:SI 3 "gpc_reg_operand" ""))
12341 (set (match_operand:SI 0 "gpc_reg_operand" "")
12342 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12343 "TARGET_32BIT && reload_completed"
12344 [(set (match_dup 0)
12345 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12348 (compare:CC (match_dup 0)
12353 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12354 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12355 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12357 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12358 [(set_attr "length" "12")])
12361 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12363 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12364 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12366 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12367 (lt:SI (match_dup 1) (match_dup 2)))]
12370 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12372 [(set_attr "type" "delayed_compare")
12373 (set_attr "length" "12,16")])
12376 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12378 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12379 (match_operand:SI 2 "reg_or_short_operand" ""))
12381 (set (match_operand:SI 0 "gpc_reg_operand" "")
12382 (lt:SI (match_dup 1) (match_dup 2)))]
12383 "TARGET_POWER && reload_completed"
12384 [(set (match_dup 0)
12385 (lt:SI (match_dup 1) (match_dup 2)))
12387 (compare:CC (match_dup 0)
12392 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12393 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12394 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12395 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12397 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12398 [(set_attr "length" "12")])
12401 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12403 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12404 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12405 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12407 (clobber (match_scratch:SI 4 "=&r,&r"))]
12410 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12412 [(set_attr "type" "compare")
12413 (set_attr "length" "12,16")])
12416 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12418 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12419 (match_operand:SI 2 "reg_or_short_operand" ""))
12420 (match_operand:SI 3 "gpc_reg_operand" ""))
12422 (clobber (match_scratch:SI 4 ""))]
12423 "TARGET_POWER && reload_completed"
12424 [(set (match_dup 4)
12425 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12428 (compare:CC (match_dup 4)
12433 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12435 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12436 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12437 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12439 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12440 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12443 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12445 [(set_attr "type" "compare")
12446 (set_attr "length" "12,16")])
12449 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12451 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12452 (match_operand:SI 2 "reg_or_short_operand" ""))
12453 (match_operand:SI 3 "gpc_reg_operand" ""))
12455 (set (match_operand:SI 0 "gpc_reg_operand" "")
12456 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12457 "TARGET_POWER && reload_completed"
12458 [(set (match_dup 0)
12459 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12461 (compare:CC (match_dup 0)
12466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12467 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12468 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12470 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12471 [(set_attr "length" "12")])
12473 (define_insn_and_split ""
12474 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12475 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12476 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12480 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12481 (set (match_dup 0) (neg:SI (match_dup 0)))]
12484 (define_insn_and_split ""
12485 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12486 (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12487 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12491 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12492 (set (match_dup 0) (neg:DI (match_dup 0)))]
12496 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12498 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12499 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12501 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12502 (ltu:SI (match_dup 1) (match_dup 2)))]
12505 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12506 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12509 [(set_attr "type" "compare")
12510 (set_attr "length" "12,12,16,16")])
12513 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12515 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12516 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12518 (set (match_operand:SI 0 "gpc_reg_operand" "")
12519 (ltu:SI (match_dup 1) (match_dup 2)))]
12520 "TARGET_32BIT && reload_completed"
12521 [(set (match_dup 0)
12522 (ltu:SI (match_dup 1) (match_dup 2)))
12524 (compare:CC (match_dup 0)
12528 (define_insn_and_split ""
12529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12530 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12531 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12532 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12536 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12537 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
12540 (define_insn_and_split ""
12541 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12542 (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12543 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
12544 (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
12548 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12549 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
12553 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12555 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12556 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12557 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12559 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12562 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12563 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12566 [(set_attr "type" "compare")
12567 (set_attr "length" "12,12,16,16")])
12570 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12572 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12573 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12574 (match_operand:SI 3 "gpc_reg_operand" ""))
12576 (clobber (match_scratch:SI 4 ""))]
12577 "TARGET_32BIT && reload_completed"
12578 [(set (match_dup 4)
12579 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12582 (compare:CC (match_dup 4)
12587 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12589 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12590 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12591 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12593 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12594 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12597 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12598 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12601 [(set_attr "type" "compare")
12602 (set_attr "length" "12,12,16,16")])
12605 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12607 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12608 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12609 (match_operand:SI 3 "gpc_reg_operand" ""))
12611 (set (match_operand:SI 0 "gpc_reg_operand" "")
12612 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12613 "TARGET_32BIT && reload_completed"
12614 [(set (match_dup 0)
12615 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12617 (compare:CC (match_dup 0)
12622 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12623 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12624 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12627 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12628 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12629 [(set_attr "type" "two")
12630 (set_attr "length" "8")])
12633 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12634 (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12635 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
12638 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12639 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12640 [(set_attr "type" "two")
12641 (set_attr "length" "8")])
12644 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12645 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12646 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12647 (clobber (match_scratch:SI 3 "=r"))]
12649 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12650 [(set_attr "length" "12")])
12653 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12655 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12656 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12658 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12659 (ge:SI (match_dup 1) (match_dup 2)))
12660 (clobber (match_scratch:SI 3 "=r,r"))]
12663 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12665 [(set_attr "type" "compare")
12666 (set_attr "length" "12,16")])
12669 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12671 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12672 (match_operand:SI 2 "reg_or_short_operand" ""))
12674 (set (match_operand:SI 0 "gpc_reg_operand" "")
12675 (ge:SI (match_dup 1) (match_dup 2)))
12676 (clobber (match_scratch:SI 3 ""))]
12677 "TARGET_POWER && reload_completed"
12678 [(parallel [(set (match_dup 0)
12679 (ge:SI (match_dup 1) (match_dup 2)))
12680 (clobber (match_dup 3))])
12682 (compare:CC (match_dup 0)
12687 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12688 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12689 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12690 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12692 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12693 [(set_attr "length" "12")])
12696 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12698 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12699 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12700 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12702 (clobber (match_scratch:SI 4 "=&r,&r"))]
12705 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12707 [(set_attr "type" "compare")
12708 (set_attr "length" "12,16")])
12711 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12713 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12714 (match_operand:SI 2 "reg_or_short_operand" ""))
12715 (match_operand:SI 3 "gpc_reg_operand" ""))
12717 (clobber (match_scratch:SI 4 ""))]
12718 "TARGET_POWER && reload_completed"
12719 [(set (match_dup 4)
12720 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12723 (compare:CC (match_dup 4)
12728 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12730 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12731 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12732 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12734 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12735 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12738 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12740 [(set_attr "type" "compare")
12741 (set_attr "length" "12,16")])
12744 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12746 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12747 (match_operand:SI 2 "reg_or_short_operand" ""))
12748 (match_operand:SI 3 "gpc_reg_operand" ""))
12750 (set (match_operand:SI 0 "gpc_reg_operand" "")
12751 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12752 "TARGET_POWER && reload_completed"
12753 [(set (match_dup 0)
12754 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12756 (compare:CC (match_dup 0)
12761 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12762 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12763 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12765 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12766 [(set_attr "length" "12")])
12769 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12770 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12771 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12774 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12775 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12776 [(set_attr "type" "three")
12777 (set_attr "length" "12")])
12780 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12781 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12782 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12785 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12786 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12787 [(set_attr "type" "three")
12788 (set_attr "length" "12")])
12791 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12793 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12794 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12796 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12797 (geu:SI (match_dup 1) (match_dup 2)))]
12800 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12801 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12804 [(set_attr "type" "compare")
12805 (set_attr "length" "12,12,16,16")])
12808 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12810 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12811 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12813 (set (match_operand:SI 0 "gpc_reg_operand" "")
12814 (geu:SI (match_dup 1) (match_dup 2)))]
12815 "TARGET_32BIT && reload_completed"
12816 [(set (match_dup 0)
12817 (geu:SI (match_dup 1) (match_dup 2)))
12819 (compare:CC (match_dup 0)
12824 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12826 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12827 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12829 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12830 (geu:DI (match_dup 1) (match_dup 2)))]
12833 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12834 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12837 [(set_attr "type" "compare")
12838 (set_attr "length" "12,12,16,16")])
12841 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12843 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12844 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12846 (set (match_operand:DI 0 "gpc_reg_operand" "")
12847 (geu:DI (match_dup 1) (match_dup 2)))]
12848 "TARGET_64BIT && reload_completed"
12849 [(set (match_dup 0)
12850 (geu:DI (match_dup 1) (match_dup 2)))
12852 (compare:CC (match_dup 0)
12857 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12858 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12859 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12860 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12863 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12864 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12865 [(set_attr "type" "two")
12866 (set_attr "length" "8")])
12869 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12871 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12872 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12873 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12875 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12878 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12879 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12882 [(set_attr "type" "compare")
12883 (set_attr "length" "8,8,12,12")])
12886 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12888 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12889 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12890 (match_operand:SI 3 "gpc_reg_operand" ""))
12892 (clobber (match_scratch:SI 4 ""))]
12893 "TARGET_32BIT && reload_completed"
12894 [(set (match_dup 4)
12895 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12898 (compare:CC (match_dup 4)
12903 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12905 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12906 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12907 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12909 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12910 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12913 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12914 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12917 [(set_attr "type" "compare")
12918 (set_attr "length" "8,8,12,12")])
12921 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12923 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12924 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12925 (match_operand:SI 3 "gpc_reg_operand" ""))
12927 (set (match_operand:SI 0 "gpc_reg_operand" "")
12928 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12929 "TARGET_32BIT && reload_completed"
12930 [(set (match_dup 0)
12931 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12933 (compare:CC (match_dup 0)
12938 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12939 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12940 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12943 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12944 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12945 [(set_attr "type" "three")
12946 (set_attr "length" "12")])
12949 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12951 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12952 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12953 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12956 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12957 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12958 [(set_attr "type" "three")
12959 (set_attr "length" "12")])
12962 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12965 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12966 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12967 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12969 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12972 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12973 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12976 [(set_attr "type" "compare")
12977 (set_attr "length" "12,12,16,16")])
12980 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12983 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12984 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12985 (match_operand:SI 3 "gpc_reg_operand" ""))
12987 (clobber (match_scratch:SI 4 ""))]
12988 "TARGET_32BIT && reload_completed"
12989 [(set (match_dup 4)
12990 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12993 (compare:CC (match_dup 4)
12998 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13001 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13002 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13003 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13005 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13006 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13009 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13010 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13013 [(set_attr "type" "compare")
13014 (set_attr "length" "12,12,16,16")])
13017 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13020 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13021 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13022 (match_operand:SI 3 "gpc_reg_operand" ""))
13024 (set (match_operand:SI 0 "gpc_reg_operand" "")
13025 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13026 "TARGET_32BIT && reload_completed"
13027 [(set (match_dup 0)
13028 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13030 (compare:CC (match_dup 0)
13035 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13036 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13039 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
13040 [(set_attr "type" "three")
13041 (set_attr "length" "12")])
13044 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13045 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13048 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
13049 [(set_attr "type" "three")
13050 (set_attr "length" "12")])
13053 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13055 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13058 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13059 (gt:SI (match_dup 1) (const_int 0)))]
13062 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
13064 [(set_attr "type" "delayed_compare")
13065 (set_attr "length" "12,16")])
13068 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13070 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13073 (set (match_operand:SI 0 "gpc_reg_operand" "")
13074 (gt:SI (match_dup 1) (const_int 0)))]
13075 "TARGET_32BIT && reload_completed"
13076 [(set (match_dup 0)
13077 (gt:SI (match_dup 1) (const_int 0)))
13079 (compare:CC (match_dup 0)
13084 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13086 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13089 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13090 (gt:DI (match_dup 1) (const_int 0)))]
13093 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13095 [(set_attr "type" "delayed_compare")
13096 (set_attr "length" "12,16")])
13099 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13101 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13104 (set (match_operand:DI 0 "gpc_reg_operand" "")
13105 (gt:DI (match_dup 1) (const_int 0)))]
13106 "TARGET_64BIT && reload_completed"
13107 [(set (match_dup 0)
13108 (gt:DI (match_dup 1) (const_int 0)))
13110 (compare:CC (match_dup 0)
13115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13116 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13117 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13119 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13120 [(set_attr "length" "12")])
13123 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13125 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13126 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13128 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13129 (gt:SI (match_dup 1) (match_dup 2)))]
13132 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13134 [(set_attr "type" "delayed_compare")
13135 (set_attr "length" "12,16")])
13138 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13140 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13141 (match_operand:SI 2 "reg_or_short_operand" ""))
13143 (set (match_operand:SI 0 "gpc_reg_operand" "")
13144 (gt:SI (match_dup 1) (match_dup 2)))]
13145 "TARGET_POWER && reload_completed"
13146 [(set (match_dup 0)
13147 (gt:SI (match_dup 1) (match_dup 2)))
13149 (compare:CC (match_dup 0)
13154 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13155 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13157 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13159 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13160 [(set_attr "type" "three")
13161 (set_attr "length" "12")])
13164 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13165 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13167 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13169 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13170 [(set_attr "type" "three")
13171 (set_attr "length" "12")])
13174 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13176 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13178 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13180 (clobber (match_scratch:SI 3 "=&r,&r"))]
13183 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13185 [(set_attr "type" "compare")
13186 (set_attr "length" "12,16")])
13189 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13191 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13193 (match_operand:SI 2 "gpc_reg_operand" ""))
13195 (clobber (match_scratch:SI 3 ""))]
13196 "TARGET_32BIT && reload_completed"
13197 [(set (match_dup 3)
13198 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13201 (compare:CC (match_dup 3)
13206 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13208 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13210 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13212 (clobber (match_scratch:DI 3 "=&r,&r"))]
13215 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13217 [(set_attr "type" "compare")
13218 (set_attr "length" "12,16")])
13221 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13223 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13225 (match_operand:DI 2 "gpc_reg_operand" ""))
13227 (clobber (match_scratch:DI 3 ""))]
13228 "TARGET_64BIT && reload_completed"
13229 [(set (match_dup 3)
13230 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13233 (compare:CC (match_dup 3)
13238 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13240 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13242 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13244 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13245 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13248 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13250 [(set_attr "type" "compare")
13251 (set_attr "length" "12,16")])
13254 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13256 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13258 (match_operand:SI 2 "gpc_reg_operand" ""))
13260 (set (match_operand:SI 0 "gpc_reg_operand" "")
13261 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13262 "TARGET_32BIT && reload_completed"
13263 [(set (match_dup 0)
13264 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13266 (compare:CC (match_dup 0)
13271 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13273 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13275 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13277 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13278 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13281 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13283 [(set_attr "type" "compare")
13284 (set_attr "length" "12,16")])
13287 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13289 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13291 (match_operand:DI 2 "gpc_reg_operand" ""))
13293 (set (match_operand:DI 0 "gpc_reg_operand" "")
13294 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13295 "TARGET_64BIT && reload_completed"
13296 [(set (match_dup 0)
13297 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13299 (compare:CC (match_dup 0)
13304 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13305 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13306 (match_operand:SI 2 "reg_or_short_operand" "r"))
13307 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13309 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13310 [(set_attr "length" "12")])
13313 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13315 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13316 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13317 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13319 (clobber (match_scratch:SI 4 "=&r,&r"))]
13322 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13324 [(set_attr "type" "compare")
13325 (set_attr "length" "12,16")])
13328 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13330 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13331 (match_operand:SI 2 "reg_or_short_operand" ""))
13332 (match_operand:SI 3 "gpc_reg_operand" ""))
13334 (clobber (match_scratch:SI 4 ""))]
13335 "TARGET_POWER && reload_completed"
13336 [(set (match_dup 4)
13337 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13339 (compare:CC (match_dup 4)
13344 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13346 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13347 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13348 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13350 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13351 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13354 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13356 [(set_attr "type" "compare")
13357 (set_attr "length" "12,16")])
13360 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13362 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13363 (match_operand:SI 2 "reg_or_short_operand" ""))
13364 (match_operand:SI 3 "gpc_reg_operand" ""))
13366 (set (match_operand:SI 0 "gpc_reg_operand" "")
13367 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13368 "TARGET_POWER && reload_completed"
13369 [(set (match_dup 0)
13370 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13372 (compare:CC (match_dup 0)
13377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13378 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13381 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13382 [(set_attr "type" "three")
13383 (set_attr "length" "12")])
13386 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13387 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13390 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13391 [(set_attr "type" "three")
13392 (set_attr "length" "12")])
13395 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13396 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13397 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13399 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13400 [(set_attr "length" "12")])
13402 (define_insn_and_split ""
13403 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13404 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13405 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13409 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13410 (set (match_dup 0) (neg:SI (match_dup 0)))]
13413 (define_insn_and_split ""
13414 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13415 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13416 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13420 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13421 (set (match_dup 0) (neg:DI (match_dup 0)))]
13425 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13427 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13428 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13430 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13431 (gtu:SI (match_dup 1) (match_dup 2)))]
13434 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13436 [(set_attr "type" "compare")
13437 (set_attr "length" "12,16")])
13440 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13442 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13443 (match_operand:SI 2 "reg_or_short_operand" ""))
13445 (set (match_operand:SI 0 "gpc_reg_operand" "")
13446 (gtu:SI (match_dup 1) (match_dup 2)))]
13447 "TARGET_32BIT && reload_completed"
13448 [(set (match_dup 0)
13449 (gtu:SI (match_dup 1) (match_dup 2)))
13451 (compare:CC (match_dup 0)
13456 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13458 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13459 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13461 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13462 (gtu:DI (match_dup 1) (match_dup 2)))]
13465 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13467 [(set_attr "type" "compare")
13468 (set_attr "length" "12,16")])
13471 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13473 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13474 (match_operand:DI 2 "reg_or_short_operand" ""))
13476 (set (match_operand:DI 0 "gpc_reg_operand" "")
13477 (gtu:DI (match_dup 1) (match_dup 2)))]
13478 "TARGET_64BIT && reload_completed"
13479 [(set (match_dup 0)
13480 (gtu:DI (match_dup 1) (match_dup 2)))
13482 (compare:CC (match_dup 0)
13486 (define_insn_and_split ""
13487 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13488 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13489 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13490 (match_operand:SI 3 "reg_or_short_operand" "rI")))]
13494 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13495 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
13498 (define_insn_and_split ""
13499 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13500 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13501 (match_operand:DI 2 "reg_or_short_operand" "rI"))
13502 (match_operand:DI 3 "reg_or_short_operand" "rI")))]
13506 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13507 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
13511 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13513 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13514 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13515 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13517 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13520 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13521 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
13524 [(set_attr "type" "compare")
13525 (set_attr "length" "8,12,12,16")])
13528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13530 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13531 (match_operand:SI 2 "reg_or_short_operand" ""))
13532 (match_operand:SI 3 "gpc_reg_operand" ""))
13534 (clobber (match_scratch:SI 4 ""))]
13535 "TARGET_32BIT && reload_completed"
13536 [(set (match_dup 4)
13537 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13540 (compare:CC (match_dup 4)
13545 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13547 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13548 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13549 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13551 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13554 addic %4,%1,%k2\;addze. %4,%3
13555 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
13558 [(set_attr "type" "compare")
13559 (set_attr "length" "8,12,12,16")])
13562 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13564 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13565 (match_operand:DI 2 "reg_or_short_operand" ""))
13566 (match_operand:DI 3 "gpc_reg_operand" ""))
13568 (clobber (match_scratch:DI 4 ""))]
13569 "TARGET_64BIT && reload_completed"
13570 [(set (match_dup 4)
13571 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13574 (compare:CC (match_dup 4)
13579 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13581 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13582 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13583 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13585 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13586 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13589 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13590 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
13593 [(set_attr "type" "compare")
13594 (set_attr "length" "8,12,12,16")])
13597 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13599 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13600 (match_operand:SI 2 "reg_or_short_operand" ""))
13601 (match_operand:SI 3 "gpc_reg_operand" ""))
13603 (set (match_operand:SI 0 "gpc_reg_operand" "")
13604 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13605 "TARGET_32BIT && reload_completed"
13606 [(set (match_dup 0)
13607 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13609 (compare:CC (match_dup 0)
13614 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13616 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13617 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13618 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13620 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13621 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13624 addic %0,%1,%k2\;addze. %0,%3
13625 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
13628 [(set_attr "type" "compare")
13629 (set_attr "length" "8,12,12,16")])
13632 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13634 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13635 (match_operand:DI 2 "reg_or_short_operand" ""))
13636 (match_operand:DI 3 "gpc_reg_operand" ""))
13638 (set (match_operand:DI 0 "gpc_reg_operand" "")
13639 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13640 "TARGET_64BIT && reload_completed"
13641 [(set (match_dup 0)
13642 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13644 (compare:CC (match_dup 0)
13649 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13650 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13651 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13653 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13654 [(set_attr "type" "two")
13655 (set_attr "length" "8")])
13658 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13659 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13660 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13662 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13663 [(set_attr "type" "two")
13664 (set_attr "length" "8")])
13666 ;; Define both directions of branch and return. If we need a reload
13667 ;; register, we'd rather use CR0 since it is much easier to copy a
13668 ;; register CC value to there.
13672 (if_then_else (match_operator 1 "branch_comparison_operator"
13674 "cc_reg_operand" "y")
13676 (label_ref (match_operand 0 "" ""))
13681 return output_cbranch (operands[1], \"%l0\", 0, insn);
13683 [(set_attr "type" "branch")])
13687 (if_then_else (match_operator 0 "branch_comparison_operator"
13689 "cc_reg_operand" "y")
13696 return output_cbranch (operands[0], NULL, 0, insn);
13698 [(set_attr "type" "branch")
13699 (set_attr "length" "4")])
13703 (if_then_else (match_operator 1 "branch_comparison_operator"
13705 "cc_reg_operand" "y")
13708 (label_ref (match_operand 0 "" ""))))]
13712 return output_cbranch (operands[1], \"%l0\", 1, insn);
13714 [(set_attr "type" "branch")])
13718 (if_then_else (match_operator 0 "branch_comparison_operator"
13720 "cc_reg_operand" "y")
13727 return output_cbranch (operands[0], NULL, 1, insn);
13729 [(set_attr "type" "branch")
13730 (set_attr "length" "4")])
13732 ;; Logic on condition register values.
13734 ; This pattern matches things like
13735 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13736 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13738 ; which are generated by the branch logic.
13739 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13741 (define_insn "*cceq_ior_compare"
13742 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13743 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13744 [(match_operator:SI 2
13745 "branch_positive_comparison_operator"
13747 "cc_reg_operand" "y,y")
13749 (match_operator:SI 4
13750 "branch_positive_comparison_operator"
13752 "cc_reg_operand" "0,y")
13756 "cr%q1 %E0,%j2,%j4"
13757 [(set_attr "type" "cr_logical,delayed_cr")])
13759 ; Why is the constant -1 here, but 1 in the previous pattern?
13760 ; Because ~1 has all but the low bit set.
13762 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13763 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13764 [(not:SI (match_operator:SI 2
13765 "branch_positive_comparison_operator"
13767 "cc_reg_operand" "y,y")
13769 (match_operator:SI 4
13770 "branch_positive_comparison_operator"
13772 "cc_reg_operand" "0,y")
13776 "cr%q1 %E0,%j2,%j4"
13777 [(set_attr "type" "cr_logical,delayed_cr")])
13779 (define_insn "*cceq_rev_compare"
13780 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13781 (compare:CCEQ (match_operator:SI 1
13782 "branch_positive_comparison_operator"
13784 "cc_reg_operand" "0,y")
13788 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13789 [(set_attr "type" "cr_logical,delayed_cr")])
13791 ;; If we are comparing the result of two comparisons, this can be done
13792 ;; using creqv or crxor.
13794 (define_insn_and_split ""
13795 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13796 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13797 [(match_operand 2 "cc_reg_operand" "y")
13799 (match_operator 3 "branch_comparison_operator"
13800 [(match_operand 4 "cc_reg_operand" "y")
13805 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13809 int positive_1, positive_2;
13811 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13812 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13815 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13816 GET_CODE (operands[1])),
13818 operands[2], const0_rtx);
13819 else if (GET_MODE (operands[1]) != SImode)
13820 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13821 operands[2], const0_rtx);
13824 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13825 GET_CODE (operands[3])),
13827 operands[4], const0_rtx);
13828 else if (GET_MODE (operands[3]) != SImode)
13829 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13830 operands[4], const0_rtx);
13832 if (positive_1 == positive_2)
13834 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13835 operands[5] = constm1_rtx;
13839 operands[5] = const1_rtx;
13843 ;; Unconditional branch and return.
13845 (define_insn "jump"
13847 (label_ref (match_operand 0 "" "")))]
13850 [(set_attr "type" "branch")])
13852 (define_insn "return"
13856 [(set_attr "type" "jmpreg")])
13858 (define_expand "indirect_jump"
13859 [(set (pc) (match_operand 0 "register_operand" ""))]
13864 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13866 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13870 (define_insn "indirect_jumpsi"
13871 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13876 [(set_attr "type" "jmpreg")])
13878 (define_insn "indirect_jumpdi"
13879 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13884 [(set_attr "type" "jmpreg")])
13886 ;; Table jump for switch statements:
13887 (define_expand "tablejump"
13888 [(use (match_operand 0 "" ""))
13889 (use (label_ref (match_operand 1 "" "")))]
13894 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13896 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13900 (define_expand "tablejumpsi"
13901 [(set (match_dup 3)
13902 (plus:SI (match_operand:SI 0 "" "")
13904 (parallel [(set (pc) (match_dup 3))
13905 (use (label_ref (match_operand 1 "" "")))])]
13908 { operands[0] = force_reg (SImode, operands[0]);
13909 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13910 operands[3] = gen_reg_rtx (SImode);
13913 (define_expand "tablejumpdi"
13914 [(set (match_dup 4)
13915 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13917 (plus:DI (match_dup 4)
13919 (parallel [(set (pc) (match_dup 3))
13920 (use (label_ref (match_operand 1 "" "")))])]
13923 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13924 operands[3] = gen_reg_rtx (DImode);
13925 operands[4] = gen_reg_rtx (DImode);
13930 (match_operand:SI 0 "register_operand" "c,*l"))
13931 (use (label_ref (match_operand 1 "" "")))]
13936 [(set_attr "type" "jmpreg")])
13940 (match_operand:DI 0 "register_operand" "c,*l"))
13941 (use (label_ref (match_operand 1 "" "")))]
13946 [(set_attr "type" "jmpreg")])
13951 "{cror 0,0,0|nop}")
13953 ;; Define the subtract-one-and-jump insns, starting with the template
13954 ;; so loop.c knows what to generate.
13956 (define_expand "doloop_end"
13957 [(use (match_operand 0 "" "")) ; loop pseudo
13958 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13959 (use (match_operand 2 "" "")) ; max iterations
13960 (use (match_operand 3 "" "")) ; loop level
13961 (use (match_operand 4 "" ""))] ; label
13965 /* Only use this on innermost loops. */
13966 if (INTVAL (operands[3]) > 1)
13970 if (GET_MODE (operands[0]) != DImode)
13972 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13976 if (GET_MODE (operands[0]) != SImode)
13978 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13983 (define_expand "ctrsi"
13984 [(parallel [(set (pc)
13985 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13987 (label_ref (match_operand 1 "" ""))
13990 (plus:SI (match_dup 0)
13992 (clobber (match_scratch:CC 2 ""))
13993 (clobber (match_scratch:SI 3 ""))])]
13997 (define_expand "ctrdi"
13998 [(parallel [(set (pc)
13999 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
14001 (label_ref (match_operand 1 "" ""))
14004 (plus:DI (match_dup 0)
14006 (clobber (match_scratch:CC 2 ""))
14007 (clobber (match_scratch:DI 3 ""))])]
14011 ;; We need to be able to do this for any operand, including MEM, or we
14012 ;; will cause reload to blow up since we don't allow output reloads on
14014 ;; For the length attribute to be calculated correctly, the
14015 ;; label MUST be operand 0.
14017 (define_insn "*ctrsi_internal1"
14019 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14021 (label_ref (match_operand 0 "" ""))
14023 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14024 (plus:SI (match_dup 1)
14026 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14027 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14031 if (which_alternative != 0)
14033 else if (get_attr_length (insn) == 4)
14034 return \"{bdn|bdnz} %l0\";
14036 return \"bdz $+8\;b %l0\";
14038 [(set_attr "type" "branch")
14039 (set_attr "length" "*,12,16,16")])
14041 (define_insn "*ctrsi_internal2"
14043 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14046 (label_ref (match_operand 0 "" ""))))
14047 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14048 (plus:SI (match_dup 1)
14050 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14051 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14055 if (which_alternative != 0)
14057 else if (get_attr_length (insn) == 4)
14058 return \"bdz %l0\";
14060 return \"{bdn|bdnz} $+8\;b %l0\";
14062 [(set_attr "type" "branch")
14063 (set_attr "length" "*,12,16,16")])
14065 (define_insn "*ctrdi_internal1"
14067 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14069 (label_ref (match_operand 0 "" ""))
14071 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14072 (plus:DI (match_dup 1)
14074 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14075 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14079 if (which_alternative != 0)
14081 else if (get_attr_length (insn) == 4)
14082 return \"{bdn|bdnz} %l0\";
14084 return \"bdz $+8\;b %l0\";
14086 [(set_attr "type" "branch")
14087 (set_attr "length" "*,12,16,16")])
14089 (define_insn "*ctrdi_internal2"
14091 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14094 (label_ref (match_operand 0 "" ""))))
14095 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14096 (plus:DI (match_dup 1)
14098 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14099 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14103 if (which_alternative != 0)
14105 else if (get_attr_length (insn) == 4)
14106 return \"bdz %l0\";
14108 return \"{bdn|bdnz} $+8\;b %l0\";
14110 [(set_attr "type" "branch")
14111 (set_attr "length" "*,12,16,16")])
14113 ;; Similar but use EQ
14115 (define_insn "*ctrsi_internal5"
14117 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14119 (label_ref (match_operand 0 "" ""))
14121 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14122 (plus:SI (match_dup 1)
14124 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14125 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14129 if (which_alternative != 0)
14131 else if (get_attr_length (insn) == 4)
14132 return \"bdz %l0\";
14134 return \"{bdn|bdnz} $+8\;b %l0\";
14136 [(set_attr "type" "branch")
14137 (set_attr "length" "*,12,16,16")])
14139 (define_insn "*ctrsi_internal6"
14141 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14144 (label_ref (match_operand 0 "" ""))))
14145 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14146 (plus:SI (match_dup 1)
14148 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14149 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14153 if (which_alternative != 0)
14155 else if (get_attr_length (insn) == 4)
14156 return \"{bdn|bdnz} %l0\";
14158 return \"bdz $+8\;b %l0\";
14160 [(set_attr "type" "branch")
14161 (set_attr "length" "*,12,16,16")])
14163 (define_insn "*ctrdi_internal5"
14165 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14167 (label_ref (match_operand 0 "" ""))
14169 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14170 (plus:DI (match_dup 1)
14172 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14173 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14177 if (which_alternative != 0)
14179 else if (get_attr_length (insn) == 4)
14180 return \"bdz %l0\";
14182 return \"{bdn|bdnz} $+8\;b %l0\";
14184 [(set_attr "type" "branch")
14185 (set_attr "length" "*,12,16,16")])
14187 (define_insn "*ctrdi_internal6"
14189 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14192 (label_ref (match_operand 0 "" ""))))
14193 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14194 (plus:DI (match_dup 1)
14196 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14197 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14201 if (which_alternative != 0)
14203 else if (get_attr_length (insn) == 4)
14204 return \"{bdn|bdnz} %l0\";
14206 return \"bdz $+8\;b %l0\";
14208 [(set_attr "type" "branch")
14209 (set_attr "length" "*,12,16,16")])
14211 ;; Now the splitters if we could not allocate the CTR register
14215 (if_then_else (match_operator 2 "comparison_operator"
14216 [(match_operand:SI 1 "gpc_reg_operand" "")
14218 (match_operand 5 "" "")
14219 (match_operand 6 "" "")))
14220 (set (match_operand:SI 0 "gpc_reg_operand" "")
14221 (plus:SI (match_dup 1)
14223 (clobber (match_scratch:CC 3 ""))
14224 (clobber (match_scratch:SI 4 ""))]
14225 "TARGET_32BIT && reload_completed"
14226 [(parallel [(set (match_dup 3)
14227 (compare:CC (plus:SI (match_dup 1)
14231 (plus:SI (match_dup 1)
14233 (set (pc) (if_then_else (match_dup 7)
14237 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14238 operands[3], const0_rtx); }")
14242 (if_then_else (match_operator 2 "comparison_operator"
14243 [(match_operand:SI 1 "gpc_reg_operand" "")
14245 (match_operand 5 "" "")
14246 (match_operand 6 "" "")))
14247 (set (match_operand:SI 0 "nonimmediate_operand" "")
14248 (plus:SI (match_dup 1) (const_int -1)))
14249 (clobber (match_scratch:CC 3 ""))
14250 (clobber (match_scratch:SI 4 ""))]
14251 "TARGET_32BIT && reload_completed
14252 && ! gpc_reg_operand (operands[0], SImode)"
14253 [(parallel [(set (match_dup 3)
14254 (compare:CC (plus:SI (match_dup 1)
14258 (plus:SI (match_dup 1)
14262 (set (pc) (if_then_else (match_dup 7)
14266 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14267 operands[3], const0_rtx); }")
14270 (if_then_else (match_operator 2 "comparison_operator"
14271 [(match_operand:DI 1 "gpc_reg_operand" "")
14273 (match_operand 5 "" "")
14274 (match_operand 6 "" "")))
14275 (set (match_operand:DI 0 "gpc_reg_operand" "")
14276 (plus:DI (match_dup 1)
14278 (clobber (match_scratch:CC 3 ""))
14279 (clobber (match_scratch:DI 4 ""))]
14280 "TARGET_64BIT && reload_completed"
14281 [(parallel [(set (match_dup 3)
14282 (compare:CC (plus:DI (match_dup 1)
14286 (plus:DI (match_dup 1)
14288 (set (pc) (if_then_else (match_dup 7)
14292 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14293 operands[3], const0_rtx); }")
14297 (if_then_else (match_operator 2 "comparison_operator"
14298 [(match_operand:DI 1 "gpc_reg_operand" "")
14300 (match_operand 5 "" "")
14301 (match_operand 6 "" "")))
14302 (set (match_operand:DI 0 "nonimmediate_operand" "")
14303 (plus:DI (match_dup 1) (const_int -1)))
14304 (clobber (match_scratch:CC 3 ""))
14305 (clobber (match_scratch:DI 4 ""))]
14306 "TARGET_64BIT && reload_completed
14307 && ! gpc_reg_operand (operands[0], DImode)"
14308 [(parallel [(set (match_dup 3)
14309 (compare:CC (plus:DI (match_dup 1)
14313 (plus:DI (match_dup 1)
14317 (set (pc) (if_then_else (match_dup 7)
14321 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14322 operands[3], const0_rtx); }")
14324 (define_insn "trap"
14325 [(trap_if (const_int 1) (const_int 0))]
14329 (define_expand "conditional_trap"
14330 [(trap_if (match_operator 0 "trap_comparison_operator"
14331 [(match_dup 2) (match_dup 3)])
14332 (match_operand 1 "const_int_operand" ""))]
14334 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14335 operands[2] = rs6000_compare_op0;
14336 operands[3] = rs6000_compare_op1;")
14339 [(trap_if (match_operator 0 "trap_comparison_operator"
14340 [(match_operand:SI 1 "register_operand" "r")
14341 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14344 "{t|tw}%V0%I2 %1,%2")
14347 [(trap_if (match_operator 0 "trap_comparison_operator"
14348 [(match_operand:DI 1 "register_operand" "r")
14349 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14354 ;; Insns related to generating the function prologue and epilogue.
14356 (define_expand "prologue"
14357 [(use (const_int 0))]
14358 "TARGET_SCHED_PROLOG"
14361 rs6000_emit_prologue ();
14365 (define_insn "*movesi_from_cr_one"
14366 [(match_parallel 0 "mfcr_operation"
14367 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14368 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14369 (match_operand 3 "immediate_operand" "n")]
14370 UNSPEC_MOVESI_FROM_CR))])]
14376 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14378 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14379 operands[4] = GEN_INT (mask);
14380 output_asm_insn (\"mfcr %1,%4\", operands);
14384 [(set_attr "type" "mfcrf")])
14386 (define_insn "movesi_from_cr"
14387 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14388 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14389 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14390 UNSPEC_MOVESI_FROM_CR))]
14393 [(set_attr "type" "mfcr")])
14395 (define_insn "*stmw"
14396 [(match_parallel 0 "stmw_operation"
14397 [(set (match_operand:SI 1 "memory_operand" "=m")
14398 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14400 "{stm|stmw} %2,%1")
14402 (define_insn "*save_fpregs_si"
14403 [(match_parallel 0 "any_parallel_operand"
14404 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14405 (use (match_operand:SI 2 "call_operand" "s"))
14406 (set (match_operand:DF 3 "memory_operand" "=m")
14407 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14410 [(set_attr "type" "branch")
14411 (set_attr "length" "4")])
14413 (define_insn "*save_fpregs_di"
14414 [(match_parallel 0 "any_parallel_operand"
14415 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14416 (use (match_operand:DI 2 "call_operand" "s"))
14417 (set (match_operand:DF 3 "memory_operand" "=m")
14418 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14421 [(set_attr "type" "branch")
14422 (set_attr "length" "4")])
14424 ; These are to explain that changes to the stack pointer should
14425 ; not be moved over stores to stack memory.
14426 (define_insn "stack_tie"
14427 [(set (match_operand:BLK 0 "memory_operand" "+m")
14428 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14431 [(set_attr "length" "0")])
14434 (define_expand "epilogue"
14435 [(use (const_int 0))]
14436 "TARGET_SCHED_PROLOG"
14439 rs6000_emit_epilogue (FALSE);
14443 ; On some processors, doing the mtcrf one CC register at a time is
14444 ; faster (like on the 604e). On others, doing them all at once is
14445 ; faster; for instance, on the 601 and 750.
14447 (define_expand "movsi_to_cr_one"
14448 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14449 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14450 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14452 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14454 (define_insn "*movsi_to_cr"
14455 [(match_parallel 0 "mtcrf_operation"
14456 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14457 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14458 (match_operand 3 "immediate_operand" "n")]
14459 UNSPEC_MOVESI_TO_CR))])]
14465 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14466 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14467 operands[4] = GEN_INT (mask);
14468 return \"mtcrf %4,%2\";
14470 [(set_attr "type" "mtcr")])
14472 (define_insn "*mtcrfsi"
14473 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14474 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14475 (match_operand 2 "immediate_operand" "n")]
14476 UNSPEC_MOVESI_TO_CR))]
14477 "GET_CODE (operands[0]) == REG
14478 && CR_REGNO_P (REGNO (operands[0]))
14479 && GET_CODE (operands[2]) == CONST_INT
14480 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14482 [(set_attr "type" "mtcr")])
14484 ; The load-multiple instructions have similar properties.
14485 ; Note that "load_multiple" is a name known to the machine-independent
14486 ; code that actually corresponds to the powerpc load-string.
14488 (define_insn "*lmw"
14489 [(match_parallel 0 "lmw_operation"
14490 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14491 (match_operand:SI 2 "memory_operand" "m"))])]
14495 (define_insn "*return_internal_si"
14497 (use (match_operand:SI 0 "register_operand" "lc"))]
14500 [(set_attr "type" "jmpreg")])
14502 (define_insn "*return_internal_di"
14504 (use (match_operand:DI 0 "register_operand" "lc"))]
14507 [(set_attr "type" "jmpreg")])
14509 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14510 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14512 (define_insn "*return_and_restore_fpregs_si"
14513 [(match_parallel 0 "any_parallel_operand"
14515 (use (match_operand:SI 1 "register_operand" "l"))
14516 (use (match_operand:SI 2 "call_operand" "s"))
14517 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14518 (match_operand:DF 4 "memory_operand" "m"))])]
14522 (define_insn "*return_and_restore_fpregs_di"
14523 [(match_parallel 0 "any_parallel_operand"
14525 (use (match_operand:DI 1 "register_operand" "l"))
14526 (use (match_operand:DI 2 "call_operand" "s"))
14527 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14528 (match_operand:DF 4 "memory_operand" "m"))])]
14532 ; This is used in compiling the unwind routines.
14533 (define_expand "eh_return"
14534 [(use (match_operand 0 "general_operand" ""))]
14539 emit_insn (gen_eh_set_lr_si (operands[0]));
14541 emit_insn (gen_eh_set_lr_di (operands[0]));
14545 ; We can't expand this before we know where the link register is stored.
14546 (define_insn "eh_set_lr_si"
14547 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14549 (clobber (match_scratch:SI 1 "=&b"))]
14553 (define_insn "eh_set_lr_di"
14554 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14556 (clobber (match_scratch:DI 1 "=&b"))]
14561 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14562 (clobber (match_scratch 1 ""))]
14567 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14571 (define_insn "prefetch"
14572 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14573 (match_operand:SI 1 "const_int_operand" "n")
14574 (match_operand:SI 2 "const_int_operand" "n"))]
14578 if (GET_CODE (operands[0]) == REG)
14579 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14580 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14582 [(set_attr "type" "load")])
14584 (include "altivec.md")