1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions. */
27 /* Definitions for the object file format. These are set at
30 #define OBJECT_XCOFF 1
33 #define OBJECT_MACHO 4
35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
44 /* Print subsidiary information on the compiler version in use. */
45 #define TARGET_VERSION ;
47 /* Default string to use for cpu if not specified. */
48 #ifndef TARGET_CPU_DEFAULT
49 #define TARGET_CPU_DEFAULT ((char *)0)
52 /* Common CPP definitions used by CPP_SPEC among the various targets
53 for handling -mcpu=xxx switches. */
54 #define CPP_CPU_SPEC \
56 %{mpower: %{!mpower2: -D_ARCH_PWR}} \
57 %{mpower2: -D_ARCH_PWR2} \
58 %{mpowerpc*: -D_ARCH_PPC} \
59 %{mno-power: %{!mpowerpc*: -D_ARCH_COM}} \
60 %{!mno-power: %{!mpower2: %(cpp_default)}}} \
61 %{mcpu=common: -D_ARCH_COM} \
62 %{mcpu=power: -D_ARCH_PWR} \
63 %{mcpu=power2: -D_ARCH_PWR2} \
64 %{mcpu=powerpc: -D_ARCH_PPC} \
65 %{mcpu=rios: -D_ARCH_PWR} \
66 %{mcpu=rios1: -D_ARCH_PWR} \
67 %{mcpu=rios2: -D_ARCH_PWR2} \
68 %{mcpu=rsc: -D_ARCH_PWR} \
69 %{mcpu=rsc1: -D_ARCH_PWR} \
70 %{mcpu=401: -D_ARCH_PPC} \
71 %{mcpu=403: -D_ARCH_PPC} \
72 %{mcpu=505: -D_ARCH_PPC} \
73 %{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
74 %{mcpu=602: -D_ARCH_PPC} \
75 %{mcpu=603: -D_ARCH_PPC} \
76 %{mcpu=603e: -D_ARCH_PPC} \
77 %{mcpu=ec603e: -D_ARCH_PPC} \
78 %{mcpu=604: -D_ARCH_PPC} \
79 %{mcpu=604e: -D_ARCH_PPC} \
80 %{mcpu=620: -D_ARCH_PPC} \
81 %{mcpu=740: -D_ARCH_PPC} \
82 %{mcpu=750: -D_ARCH_PPC} \
83 %{mcpu=801: -D_ARCH_PPC} \
84 %{mcpu=821: -D_ARCH_PPC} \
85 %{mcpu=823: -D_ARCH_PPC} \
86 %{mcpu=860: -D_ARCH_PPC}"
88 /* Common ASM definitions used by ASM_SPEC among the various targets
89 for handling -mcpu=xxx switches. */
90 #define ASM_CPU_SPEC \
92 %{mpower: %{!mpower2: -mpwr}} \
95 %{mno-power: %{!mpowerpc*: -mcom}} \
96 %{!mno-power: %{!mpower2: %(asm_default)}}} \
97 %{mcpu=common: -mcom} \
98 %{mcpu=power: -mpwr} \
99 %{mcpu=power2: -mpwrx} \
100 %{mcpu=powerpc: -mppc} \
101 %{mcpu=rios: -mpwr} \
102 %{mcpu=rios1: -mpwr} \
103 %{mcpu=rios2: -mpwrx} \
105 %{mcpu=rsc1: -mpwr} \
112 %{mcpu=603e: -mppc} \
113 %{mcpu=ec603e: -mppc} \
115 %{mcpu=604e: -mppc} \
124 #define CPP_DEFAULT_SPEC ""
126 #define ASM_DEFAULT_SPEC ""
128 /* This macro defines names of additional specifications to put in the specs
129 that can be used in various specifications like CC1_SPEC. Its definition
130 is an initializer with a subgrouping for each command option.
132 Each subgrouping contains a string constant, that defines the
133 specification name, and a string constant that used by the GNU CC driver
136 Do not define this macro if it does not need to do anything. */
138 #define SUBTARGET_EXTRA_SPECS
140 #define EXTRA_SPECS \
141 { "cpp_cpu", CPP_CPU_SPEC }, \
142 { "cpp_default", CPP_DEFAULT_SPEC }, \
143 { "asm_cpu", ASM_CPU_SPEC }, \
144 { "asm_default", ASM_DEFAULT_SPEC }, \
145 SUBTARGET_EXTRA_SPECS
147 /* Architecture type. */
149 extern int target_flags;
151 /* Use POWER architecture instructions and MQ register. */
152 #define MASK_POWER 0x00000001
154 /* Use POWER2 extensions to POWER architecture. */
155 #define MASK_POWER2 0x00000002
157 /* Use PowerPC architecture instructions. */
158 #define MASK_POWERPC 0x00000004
160 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
161 #define MASK_PPC_GPOPT 0x00000008
163 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
164 #define MASK_PPC_GFXOPT 0x00000010
166 /* Use PowerPC-64 architecture instructions. */
167 #define MASK_POWERPC64 0x00000020
169 /* Use revised mnemonic names defined for PowerPC architecture. */
170 #define MASK_NEW_MNEMONICS 0x00000040
172 /* Disable placing fp constants in the TOC; can be turned on when the
174 #define MASK_NO_FP_IN_TOC 0x00000080
176 /* Disable placing symbol+offset constants in the TOC; can be turned on when
177 the TOC overflows. */
178 #define MASK_NO_SUM_IN_TOC 0x00000100
180 /* Output only one TOC entry per module. Normally linking fails if
181 there are more than 16K unique variables/constants in an executable. With
182 this option, linking fails only if there are more than 16K modules, or
183 if there are more than 16K unique variables/constant in a single module.
185 This is at the cost of having 2 extra loads and one extra store per
186 function, and one less allocable register. */
187 #define MASK_MINIMAL_TOC 0x00000200
189 /* Nonzero for the 64bit model: ints, longs, and pointers are 64 bits. */
190 #define MASK_64BIT 0x00000400
192 /* Disable use of FPRs. */
193 #define MASK_SOFT_FLOAT 0x00000800
195 /* Enable load/store multiple, even on powerpc */
196 #define MASK_MULTIPLE 0x00001000
197 #define MASK_MULTIPLE_SET 0x00002000
199 /* Use string instructions for block moves */
200 #define MASK_STRING 0x00004000
201 #define MASK_STRING_SET 0x00008000
203 /* Disable update form of load/store */
204 #define MASK_NO_UPDATE 0x00010000
206 /* Disable fused multiply/add operations */
207 #define MASK_NO_FUSED_MADD 0x00020000
209 /* Nonzero if we need to schedule the prolog and epilog. */
210 #define MASK_SCHED_PROLOG 0x00040000
212 #define TARGET_POWER (target_flags & MASK_POWER)
213 #define TARGET_POWER2 (target_flags & MASK_POWER2)
214 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
215 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
216 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
217 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
218 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
219 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
220 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
221 #define TARGET_64BIT (target_flags & MASK_64BIT)
222 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
223 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
224 #define TARGET_MULTIPLE_SET (target_flags & MASK_MULTIPLE_SET)
225 #define TARGET_STRING (target_flags & MASK_STRING)
226 #define TARGET_STRING_SET (target_flags & MASK_STRING_SET)
227 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
228 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
229 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
231 #define TARGET_32BIT (! TARGET_64BIT)
232 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
233 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
234 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
237 /* For libgcc2 we make sure this is a compile time constant */
239 #define TARGET_POWERPC64 1
241 #define TARGET_POWERPC64 0
244 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
247 #define TARGET_XL_CALL 0
249 /* Run-time compilation parameters selecting different hardware subsets.
251 Macro to define tables used to set the flags.
252 This is a list in braces of pairs in braces,
253 each pair being { "NAME", VALUE }
254 where VALUE is the bits to set or minus the bits to clear.
255 An empty string NAME is used to identify the default VALUE. */
257 #define TARGET_SWITCHES \
258 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
259 N_("Use POWER instruction set")}, \
260 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
262 N_("Use POWER2 instruction set")}, \
263 {"no-power2", - MASK_POWER2, \
264 N_("Do not use POWER2 instruction set")}, \
265 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
267 N_("Do not use POWER instruction set")}, \
268 {"powerpc", MASK_POWERPC, \
269 N_("Use PowerPC instruction set")}, \
270 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
271 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
272 N_("Do not use PowerPC instruction set")}, \
273 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
274 N_("Use PowerPC General Purpose group optional instructions")},\
275 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
276 N_("Don't use PowerPC General Purpose group optional instructions")},\
277 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
278 N_("Use PowerPC Graphics group optional instructions")},\
279 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
280 N_("Don't use PowerPC Graphics group optional instructions")},\
281 {"powerpc64", MASK_POWERPC64, \
282 N_("Use PowerPC-64 instruction set")}, \
283 {"no-powerpc64", - MASK_POWERPC64, \
284 N_("Don't use PowerPC-64 instruction set")}, \
285 {"new-mnemonics", MASK_NEW_MNEMONICS, \
286 N_("Use new mnemonics for PowerPC architecture")},\
287 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
288 N_("Use old mnemonics for PowerPC architecture")},\
289 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
290 | MASK_MINIMAL_TOC), \
291 N_("Put everything in the regular TOC")}, \
292 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
293 N_("Place floating point constants in TOC")}, \
294 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
295 N_("Don't place floating point constants in TOC")},\
296 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
297 N_("Place symbol+offset constants in TOC")}, \
298 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
299 N_("Don't place symbol+offset constants in TOC")},\
300 {"minimal-toc", MASK_MINIMAL_TOC, \
301 "Use only one TOC entry per procedure"}, \
302 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
304 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
305 N_("Place variable addresses in the regular TOC")},\
306 {"hard-float", - MASK_SOFT_FLOAT, \
307 N_("Use hardware fp")}, \
308 {"soft-float", MASK_SOFT_FLOAT, \
309 N_("Do not use hardware fp")}, \
310 {"multiple", MASK_MULTIPLE | MASK_MULTIPLE_SET, \
311 N_("Generate load/store multiple instructions")}, \
312 {"no-multiple", - MASK_MULTIPLE, \
313 N_("Do not generate load/store multiple instructions")},\
314 {"no-multiple", MASK_MULTIPLE_SET, \
316 {"string", MASK_STRING | MASK_STRING_SET, \
317 N_("Generate string instructions for block moves")},\
318 {"no-string", - MASK_STRING, \
319 N_("Do not generate string instructions for block moves")},\
320 {"no-string", MASK_STRING_SET, \
322 {"update", - MASK_NO_UPDATE, \
323 N_("Generate load/store with update instructions")},\
324 {"no-update", MASK_NO_UPDATE, \
325 N_("Do not generate load/store with update instructions")},\
326 {"fused-madd", - MASK_NO_FUSED_MADD, \
327 N_("Generate fused multiply/add instructions")},\
328 {"no-fused-madd", MASK_NO_FUSED_MADD, \
329 N_("Don't generate fused multiply/add instructions")},\
330 {"sched-prolog", MASK_SCHED_PROLOG, \
332 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
333 N_("Don't schedule the start and end of the procedure")},\
334 {"sched-epilog", MASK_SCHED_PROLOG, \
336 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
339 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
342 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
344 /* This is meant to be redefined in the host dependent files */
345 #define SUBTARGET_SWITCHES
347 /* Processor type. Order must match cpu attribute in MD file. */
364 extern enum processor_type rs6000_cpu;
366 /* Recast the processor type to the cpu attribute. */
367 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
369 /* Define generic processor types based upon current deployment. */
370 #define PROCESSOR_COMMON PROCESSOR_PPC601
371 #define PROCESSOR_POWER PROCESSOR_RIOS1
372 #define PROCESSOR_POWERPC PROCESSOR_PPC604
373 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
375 /* Define the default processor. This is overridden by other tm.h files. */
376 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
377 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
379 /* Specify the dialect of assembler to use. New mnemonics is dialect one
380 and the old mnemonics are dialect zero. */
381 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
383 /* This macro is similar to `TARGET_SWITCHES' but defines names of
384 command options that have values. Its definition is an
385 initializer with a subgrouping for each command option.
387 Each subgrouping contains a string constant, that defines the
388 fixed part of the option name, and the address of a variable.
389 The variable, type `char *', is set to the variable part of the
390 given option if the fixed part matches. The actual option name
391 is made by appending `-m' to the specified name.
393 Here is an example which defines `-mshort-data-NUMBER'. If the
394 given option is `-mshort-data-512', the variable `m88k_short_data'
395 will be set to the string `"512"'.
397 extern char *m88k_short_data;
398 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
400 /* This is meant to be overridden in target specific files. */
401 #define SUBTARGET_OPTIONS
403 #define TARGET_OPTIONS \
405 {"cpu=", &rs6000_select[1].string, \
406 N_("Use features of and schedule code for given CPU") }, \
407 {"tune=", &rs6000_select[2].string, \
408 N_("Schedule code for given CPU") }, \
409 {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \
413 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
414 struct rs6000_cpu_select
422 extern struct rs6000_cpu_select rs6000_select[];
425 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
426 extern int rs6000_debug_stack; /* debug stack applications */
427 extern int rs6000_debug_arg; /* debug argument handling */
429 #define TARGET_DEBUG_STACK rs6000_debug_stack
430 #define TARGET_DEBUG_ARG rs6000_debug_arg
432 /* Sometimes certain combinations of command options do not make sense
433 on a particular target machine. You can define a macro
434 `OVERRIDE_OPTIONS' to take account of this. This macro, if
435 defined, is executed once just after all the command options have
438 Don't use this macro to turn on various extra optimizations for
439 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
441 On the RS/6000 this is used to define the target cpu type. */
443 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
445 /* Define this to change the optimizations performed by default. */
446 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
448 /* Show we can debug even without a frame pointer. */
449 #define CAN_DEBUG_WITHOUT_FP
451 /* target machine storage layout */
453 /* Define to support cross compilation to an RS6000 target. */
454 #define REAL_ARITHMETIC
456 /* Define this macro if it is advisable to hold scalars in registers
457 in a wider mode than that declared by the program. In such cases,
458 the value is constrained to be within the bounds of the declared
459 type, but kept valid in the wider mode. The signedness of the
460 extension may differ from that of the type. */
462 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
463 if (GET_MODE_CLASS (MODE) == MODE_INT \
464 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
467 /* Define this if function arguments should also be promoted using the above
470 #define PROMOTE_FUNCTION_ARGS
472 /* Likewise, if the function return value is promoted. */
474 #define PROMOTE_FUNCTION_RETURN
476 /* Define this if most significant bit is lowest numbered
477 in instructions that operate on numbered bit-fields. */
478 /* That is true on RS/6000. */
479 #define BITS_BIG_ENDIAN 1
481 /* Define this if most significant byte of a word is the lowest numbered. */
482 /* That is true on RS/6000. */
483 #define BYTES_BIG_ENDIAN 1
485 /* Define this if most significant word of a multiword number is lowest
488 For RS/6000 we can decide arbitrarily since there are no machine
489 instructions for them. Might as well be consistent with bits and bytes. */
490 #define WORDS_BIG_ENDIAN 1
492 /* number of bits in an addressable storage unit */
493 #define BITS_PER_UNIT 8
495 /* Width in bits of a "word", which is the contents of a machine register.
496 Note that this is not necessarily the width of data type `int';
497 if using 16-bit ints on a 68000, this would still be 32.
498 But on a machine with 16-bit registers, this would be 16. */
499 #define BITS_PER_WORD (! TARGET_POWERPC64 ? 32 : 64)
500 #define MAX_BITS_PER_WORD 64
502 /* Width of a word, in units (bytes). */
503 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
504 #define MIN_UNITS_PER_WORD 4
505 #define UNITS_PER_FP_WORD 8
507 /* Type used for ptrdiff_t, as a string used in a declaration. */
508 #define PTRDIFF_TYPE "int"
510 /* Type used for size_t, as a string used in a declaration. */
511 #define SIZE_TYPE "long unsigned int"
513 /* Type used for wchar_t, as a string used in a declaration. */
514 #define WCHAR_TYPE "short unsigned int"
516 /* Width of wchar_t in bits. */
517 #define WCHAR_TYPE_SIZE 16
519 /* A C expression for the size in bits of the type `short' on the
520 target machine. If you don't define this, the default is half a
521 word. (If this would be less than one storage unit, it is
522 rounded up to one unit.) */
523 #define SHORT_TYPE_SIZE 16
525 /* A C expression for the size in bits of the type `int' on the
526 target machine. If you don't define this, the default is one
528 #define INT_TYPE_SIZE 32
530 /* A C expression for the size in bits of the type `long' on the
531 target machine. If you don't define this, the default is one
533 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
534 #define MAX_LONG_TYPE_SIZE 64
536 /* A C expression for the size in bits of the type `long long' on the
537 target machine. If you don't define this, the default is two
539 #define LONG_LONG_TYPE_SIZE 64
541 /* A C expression for the size in bits of the type `char' on the
542 target machine. If you don't define this, the default is one
543 quarter of a word. (If this would be less than one storage unit,
544 it is rounded up to one unit.) */
545 #define CHAR_TYPE_SIZE BITS_PER_UNIT
547 /* A C expression for the size in bits of the type `float' on the
548 target machine. If you don't define this, the default is one
550 #define FLOAT_TYPE_SIZE 32
552 /* A C expression for the size in bits of the type `double' on the
553 target machine. If you don't define this, the default is two
555 #define DOUBLE_TYPE_SIZE 64
557 /* A C expression for the size in bits of the type `long double' on
558 the target machine. If you don't define this, the default is two
560 #define LONG_DOUBLE_TYPE_SIZE 64
562 /* Width in bits of a pointer.
563 See also the macro `Pmode' defined below. */
564 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
566 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
567 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
569 /* Boundary (in *bits*) on which stack pointer should be aligned. */
570 #define STACK_BOUNDARY (TARGET_32BIT ? 64 : 128)
572 /* Allocation boundary (in *bits*) for the code of a function. */
573 #define FUNCTION_BOUNDARY 32
575 /* No data type wants to be aligned rounder than this. */
576 #define BIGGEST_ALIGNMENT 64
578 /* Handle #pragma pack. */
579 #define HANDLE_PRAGMA_PACK 1
581 /* Alignment of field after `int : 0' in a structure. */
582 #define EMPTY_FIELD_BOUNDARY 32
584 /* Every structure's size must be a multiple of this. */
585 #define STRUCTURE_SIZE_BOUNDARY 8
587 /* A bitfield declared as `int' forces `int' alignment for the struct. */
588 #define PCC_BITFIELD_TYPE_MATTERS 1
590 /* Make strings word-aligned so strcpy from constants will be faster. */
591 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
592 (TREE_CODE (EXP) == STRING_CST \
593 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
595 /* Make arrays of chars word-aligned for the same reasons. */
596 #define DATA_ALIGNMENT(TYPE, ALIGN) \
597 (TREE_CODE (TYPE) == ARRAY_TYPE \
598 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
599 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
601 /* Non-zero if move instructions will actually fail to work
602 when given unaligned data. */
603 #define STRICT_ALIGNMENT 0
605 /* Define this macro to be the value 1 if unaligned accesses have a cost
606 many times greater than aligned accesses, for example if they are
607 emulated in a trap handler. */
608 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
610 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode) \
611 && (ALIGN) < 32)) ? 1 : 0)
613 /* Standard register usage. */
615 /* Number of actual hardware registers.
616 The hardware registers are assigned numbers for the compiler
617 from 0 to just below FIRST_PSEUDO_REGISTER.
618 All registers that the compiler knows about must be given numbers,
619 even those that are not normally considered general registers.
621 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
622 an MQ register, a count register, a link register, and 8 condition
623 register fields, which we view here as separate registers.
625 In addition, the difference between the frame and argument pointers is
626 a function of the number of registers saved, so we need to have a
627 register for AP that will later be eliminated in favor of SP or FP.
628 This is a normal register, but it is fixed.
630 We also create a pseudo register for float/int conversions, that will
631 really represent the memory location used. It is represented here as
632 a register, in order to work around problems in allocating stack storage
633 in inline functions. */
635 #define FIRST_PSEUDO_REGISTER 77
637 /* This must not decrease, for backwards compatibility. If
638 FIRST_PSEUDO_REGISTER increases, this should as well. */
639 #define DWARF_FRAME_REGISTERS 77
641 /* 1 for registers that have pervasive standard uses
642 and are not available for the register allocator.
644 On RS/6000, r1 is used for the stack and r2 is used as the TOC pointer.
646 cr5 is not supposed to be used.
648 On System V implementations, r13 is fixed and not available for use. */
650 #define FIXED_REGISTERS \
651 {0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
652 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
653 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
654 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
655 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1}
657 /* 1 for registers not available across function calls.
658 These must include the FIXED_REGISTERS and also any
659 registers that can be used without being saved.
660 The latter must include the registers where values are returned
661 and the register where structure-value addresses are passed.
662 Aside from that, you can include as many other registers as you like. */
664 #define CALL_USED_REGISTERS \
665 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
666 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
667 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
668 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
669 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1}
677 #define MAX_CR_REGNO 75
680 /* List the order in which to allocate registers. Each register must be
681 listed once, even those in FIXED_REGISTERS.
683 We allocate in the following order:
684 fp0 (not saved or used for anything)
685 fp13 - fp2 (not saved; incoming fp arg registers)
686 fp1 (not saved; return value)
687 fp31 - fp14 (saved; order given to save least number)
688 cr7, cr6 (not saved or special)
689 cr1 (not saved, but used for FP operations)
690 cr0 (not saved, but used for arithmetic operations)
691 cr4, cr3, cr2 (saved)
692 r0 (not saved; cannot be base reg)
693 r9 (not saved; best for TImode)
694 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
695 r3 (not saved; return value register)
696 r31 - r13 (saved; order given to save least number)
697 r12 (not saved; if used for DImode or DFmode would use r13)
698 mq (not saved; best to use it if we can)
699 ctr (not saved; when we have the choice ctr is better)
701 cr5, r1, r2, ap, xer (fixed) */
703 #define REG_ALLOC_ORDER \
705 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
707 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
708 50, 49, 48, 47, 46, \
709 75, 74, 69, 68, 72, 71, 70, \
711 9, 11, 10, 8, 7, 6, 5, 4, \
713 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
714 18, 17, 16, 15, 14, 13, 12, \
718 /* True if register is floating-point. */
719 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
721 /* True if register is a condition register. */
722 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
724 /* True if register is a condition register, but not cr0. */
725 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
727 /* True if register is an integer register. */
728 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
730 /* True if register is the XER register. */
731 #define XER_REGNO_P(N) ((N) == XER_REGNO)
733 /* Return number of consecutive hard regs needed starting at reg REGNO
734 to hold something of mode MODE.
735 This is ordinarily the length in words of a value of mode MODE
736 but can be less for certain modes in special long registers.
738 POWER and PowerPC GPRs hold 32 bits worth;
739 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
741 #define HARD_REGNO_NREGS(REGNO, MODE) \
742 (FP_REGNO_P (REGNO) \
743 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
744 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
746 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
747 For POWER and PowerPC, the GPRs can hold any mode, but the float
748 registers only can hold floating modes and DImode, and CR register only
749 can hold CC modes. We cannot put TImode anywhere except general
750 register and it must be able to fit within the register set. */
752 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
753 (FP_REGNO_P (REGNO) ? \
754 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
755 || (GET_MODE_CLASS (MODE) == MODE_INT \
756 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
757 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
758 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
759 : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \
760 && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
763 /* Value is 1 if it is a good idea to tie two pseudo registers
764 when one has mode MODE1 and one has mode MODE2.
765 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
766 for any hard reg, then this must be 0 for correct output. */
767 #define MODES_TIEABLE_P(MODE1, MODE2) \
768 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
769 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
770 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
771 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
772 : GET_MODE_CLASS (MODE1) == MODE_CC \
773 ? GET_MODE_CLASS (MODE2) == MODE_CC \
774 : GET_MODE_CLASS (MODE2) == MODE_CC \
775 ? GET_MODE_CLASS (MODE1) == MODE_CC \
778 /* A C expression returning the cost of moving data from a register of class
779 CLASS1 to one of CLASS2.
781 On the RS/6000, copying between floating-point and fixed-point
782 registers is expensive. */
784 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
785 ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \
786 : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10 \
787 : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10 \
788 : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS \
789 || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS \
790 || (CLASS1) == LINK_OR_CTR_REGS) \
791 && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \
792 || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS \
793 || (CLASS2) == LINK_OR_CTR_REGS)) ? 10 \
796 /* A C expressions returning the cost of moving data of MODE from a register to
799 On the RS/6000, bump this up a bit. */
801 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
802 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
803 && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \
807 /* Specify the cost of a branch insn; roughly the number of extra insns that
808 should be added to avoid a branch.
810 Set this to 3 on the RS/6000 since that is roughly the average cost of an
811 unscheduled conditional branch. */
813 #define BRANCH_COST 3
815 /* Define this macro to change register usage conditional on target flags.
816 Set MQ register fixed (already call_used) if not POWER architecture
817 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
818 64-bit AIX reserves GPR13 for thread-private data.
819 Conditionally disable FPRs. */
821 #define CONDITIONAL_REGISTER_USAGE \
823 if (! TARGET_POWER) \
824 fixed_regs[64] = 1; \
826 fixed_regs[13] = call_used_regs[13] = 1; \
827 if (TARGET_SOFT_FLOAT) \
828 for (i = 32; i < 64; i++) \
829 fixed_regs[i] = call_used_regs[i] = 1; \
830 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
832 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
833 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
834 if (DEFAULT_ABI == ABI_DARWIN && flag_pic) \
835 global_regs[PIC_OFFSET_TABLE_REGNUM] \
836 = fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
837 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
840 /* Specify the registers used for certain standard purposes.
841 The values of these macros are register numbers. */
843 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
844 /* #define PC_REGNUM */
846 /* Register to use for pushing function arguments. */
847 #define STACK_POINTER_REGNUM 1
849 /* Base register for access to local variables of the function. */
850 #define FRAME_POINTER_REGNUM 31
852 /* Value should be nonzero if functions must have frame pointers.
853 Zero means the frame pointer need not be set up (and parms
854 may be accessed via the stack pointer) in functions that seem suitable.
855 This is computed in `reload', in reload1.c. */
856 #define FRAME_POINTER_REQUIRED 0
858 /* Base register for access to arguments of the function. */
859 #define ARG_POINTER_REGNUM 67
861 /* Place to put static chain when calling a function that requires it. */
862 #define STATIC_CHAIN_REGNUM 11
864 /* Link register number. */
865 #define LINK_REGISTER_REGNUM 65
867 /* Count register number. */
868 #define COUNT_REGISTER_REGNUM 66
870 /* Place that structure value return address is placed.
872 On the RS/6000, it is passed as an extra parameter. */
873 #define STRUCT_VALUE 0
875 /* Define the classes of registers for register constraints in the
876 machine description. Also define ranges of constants.
878 One of the classes must always be named ALL_REGS and include all hard regs.
879 If there is more than one class, another class must be named NO_REGS
880 and contain no registers.
882 The name GENERAL_REGS must be the name of a class (or an alias for
883 another name such as ALL_REGS). This is the class of registers
884 that is allowed by "g" or "r" in a register constraint.
885 Also, registers outside this class are allocated only when
886 instructions express preferences for them.
888 The classes must be numbered in nondecreasing order; that is,
889 a larger-numbered class must never be contained completely
890 in a smaller-numbered class.
892 For any two classes, it is very desirable that there be another
893 class that represents their union. */
895 /* The RS/6000 has three types of registers, fixed-point, floating-point,
896 and condition registers, plus three special registers, MQ, CTR, and the
899 However, r0 is special in that it cannot be used as a base register.
900 So make a class for registers valid as base registers.
902 Also, cr0 is the only condition code register that can be used in
903 arithmetic insns, so make a separate class for it. */
926 #define N_REG_CLASSES (int) LIM_REG_CLASSES
928 /* Give names of register classes as strings for dump file. */
930 #define REG_CLASS_NAMES \
936 "NON_SPECIAL_REGS", \
940 "LINK_OR_CTR_REGS", \
942 "SPEC_OR_GEN_REGS", \
950 /* Define which registers fit in which classes.
951 This is an initializer for a vector of HARD_REG_SET
952 of length N_REG_CLASSES. */
954 #define REG_CLASS_CONTENTS \
956 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
957 { 0xfffffffe, 0x00000000, 0x00000008 }, /* BASE_REGS */ \
958 { 0xffffffff, 0x00000000, 0x00000008 }, /* GENERAL_REGS */ \
959 { 0x00000000, 0xffffffff, 0x00000000 }, /* FLOAT_REGS */ \
960 { 0xffffffff, 0xffffffff, 0x00000008 }, /* NON_SPECIAL_REGS */ \
961 { 0x00000000, 0x00000000, 0x00000001 }, /* MQ_REGS */ \
962 { 0x00000000, 0x00000000, 0x00000002 }, /* LINK_REGS */ \
963 { 0x00000000, 0x00000000, 0x00000004 }, /* CTR_REGS */ \
964 { 0x00000000, 0x00000000, 0x00000006 }, /* LINK_OR_CTR_REGS */ \
965 { 0x00000000, 0x00000000, 0x00000007 }, /* SPECIAL_REGS */ \
966 { 0xffffffff, 0x00000000, 0x0000000f }, /* SPEC_OR_GEN_REGS */ \
967 { 0x00000000, 0x00000000, 0x00000010 }, /* CR0_REGS */ \
968 { 0x00000000, 0x00000000, 0x00000ff0 }, /* CR_REGS */ \
969 { 0xffffffff, 0x00000000, 0x0000ffff }, /* NON_FLOAT_REGS */ \
970 { 0x00000000, 0x00000000, 0x00010000 }, /* XER_REGS */ \
971 { 0xffffffff, 0xffffffff, 0x0001ffff } /* ALL_REGS */ \
974 /* The same information, inverted:
975 Return the class number of the smallest class containing
976 reg number REGNO. This could be a conditional expression
977 or could index an array. */
979 #define REGNO_REG_CLASS(REGNO) \
980 ((REGNO) == 0 ? GENERAL_REGS \
981 : (REGNO) < 32 ? BASE_REGS \
982 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
983 : (REGNO) == CR0_REGNO ? CR0_REGS \
984 : CR_REGNO_P (REGNO) ? CR_REGS \
985 : (REGNO) == MQ_REGNO ? MQ_REGS \
986 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
987 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
988 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
989 : (REGNO) == XER_REGNO ? XER_REGS \
992 /* The class value for index registers, and the one for base regs. */
993 #define INDEX_REG_CLASS GENERAL_REGS
994 #define BASE_REG_CLASS BASE_REGS
996 /* Get reg_class from a letter such as appears in the machine description. */
998 #define REG_CLASS_FROM_LETTER(C) \
999 ((C) == 'f' ? FLOAT_REGS \
1000 : (C) == 'b' ? BASE_REGS \
1001 : (C) == 'h' ? SPECIAL_REGS \
1002 : (C) == 'q' ? MQ_REGS \
1003 : (C) == 'c' ? CTR_REGS \
1004 : (C) == 'l' ? LINK_REGS \
1005 : (C) == 'x' ? CR0_REGS \
1006 : (C) == 'y' ? CR_REGS \
1007 : (C) == 'z' ? XER_REGS \
1010 /* The letters I, J, K, L, M, N, and P in a register constraint string
1011 can be used to stand for particular ranges of immediate operands.
1012 This macro defines what the ranges are.
1013 C is the letter, and VALUE is a constant value.
1014 Return 1 if VALUE is in the range specified by C.
1016 `I' is a signed 16-bit constant
1017 `J' is a constant with only the high-order 16 bits non-zero
1018 `K' is a constant with only the low-order 16 bits non-zero
1019 `L' is a signed 16-bit constant shifted left 16 bits
1020 `M' is a constant that is greater than 31
1021 `N' is a positive constant that is an exact power of two
1022 `O' is the constant zero
1023 `P' is a constant whose negation is a signed 16-bit constant */
1025 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1026 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1027 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1028 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1029 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1030 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1031 : (C) == 'M' ? (VALUE) > 31 \
1032 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1033 : (C) == 'O' ? (VALUE) == 0 \
1034 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1037 /* Similar, but for floating constants, and defining letters G and H.
1038 Here VALUE is the CONST_DOUBLE rtx itself.
1040 We flag for special constants when we can copy the constant into
1041 a general register in two insns for DF/DI and one insn for SF.
1043 'H' is used for DI/DF constants that take 3 insns. */
1045 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1046 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1047 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1048 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1051 /* Optional extra constraints for this machine.
1053 'Q' means that is a memory operand that is just an offset from a reg.
1054 'R' is for AIX TOC entries.
1055 'S' is a constant that can be placed into a 64-bit mask operand
1056 'T' is a consatnt that can be placed into a 32-bit mask operand
1057 'U' is for V.4 small data references. */
1059 #define EXTRA_CONSTRAINT(OP, C) \
1060 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1061 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
1062 : (C) == 'S' ? mask64_operand (OP, VOIDmode) \
1063 : (C) == 'T' ? mask_operand (OP, VOIDmode) \
1064 : (C) == 'U' ? ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
1065 && small_data_operand (OP, GET_MODE (OP))) \
1068 /* Given an rtx X being reloaded into a reg required to be
1069 in class CLASS, return the class of reg to actually use.
1070 In general this is just CLASS; but on some machines
1071 in some cases it is preferable to use a more restrictive class.
1073 On the RS/6000, we have to return NO_REGS when we want to reload a
1074 floating-point CONST_DOUBLE to force it to be copied to memory.
1076 We also don't want to reload integer values into floating-point
1077 registers if we can at all help it. In fact, this can
1078 cause reload to abort, if it tries to generate a reload of CTR
1079 into a FP register and discovers it doesn't have the memory location
1082 ??? Would it be a good idea to have reload do the converse, that is
1083 try to reload floating modes into FP registers if possible?
1086 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1087 (((GET_CODE (X) == CONST_DOUBLE \
1088 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1090 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1091 && (CLASS) == NON_SPECIAL_REGS) \
1095 /* Return the register class of a scratch register needed to copy IN into
1096 or out of a register in CLASS in MODE. If it can be done directly,
1097 NO_REGS is returned. */
1099 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1100 secondary_reload_class (CLASS, MODE, IN)
1102 /* If we are copying between FP registers and anything else, we need a memory
1105 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1106 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS || (CLASS2) == FLOAT_REGS))
1108 /* Return the maximum number of consecutive registers
1109 needed to represent mode MODE in a register of class CLASS.
1111 On RS/6000, this is the size of MODE in words,
1112 except in the FP regs, where a single reg is enough for two words. */
1113 #define CLASS_MAX_NREGS(CLASS, MODE) \
1114 (((CLASS) == FLOAT_REGS) \
1115 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1116 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1118 /* If defined, gives a class of registers that cannot be used as the
1119 operand of a SUBREG that changes the mode of the object illegally. */
1121 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
1123 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1125 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1126 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1128 /* Stack layout; function entry, exit and calling. */
1130 /* Enumeration to give which calling sequence to use. */
1133 ABI_AIX, /* IBM's AIX */
1134 ABI_AIX_NODESC, /* AIX calling sequence minus function descriptors */
1135 ABI_V4, /* System V.4/eabi */
1136 ABI_SOLARIS, /* Solaris */
1137 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1140 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1142 /* Structure used to define the rs6000 stack */
1143 typedef struct rs6000_stack {
1144 int first_gp_reg_save; /* first callee saved GP register used */
1145 int first_fp_reg_save; /* first callee saved FP register used */
1146 int lr_save_p; /* true if the link reg needs to be saved */
1147 int cr_save_p; /* true if the CR reg needs to be saved */
1148 int toc_save_p; /* true if the TOC needs to be saved */
1149 int push_p; /* true if we need to allocate stack space */
1150 int calls_p; /* true if the function makes any calls */
1151 enum rs6000_abi abi; /* which ABI to use */
1152 int gp_save_offset; /* offset to save GP regs from initial SP */
1153 int fp_save_offset; /* offset to save FP regs from initial SP */
1154 int lr_save_offset; /* offset to save LR from initial SP */
1155 int cr_save_offset; /* offset to save CR from initial SP */
1156 int toc_save_offset; /* offset to save the TOC pointer */
1157 int varargs_save_offset; /* offset to save the varargs registers */
1158 int ehrd_offset; /* offset to EH return data */
1159 int reg_size; /* register size (4 or 8) */
1160 int varargs_size; /* size to hold V.4 args passed in regs */
1161 int vars_size; /* variable save area size */
1162 int parm_size; /* outgoing parameter size */
1163 int save_size; /* save area size */
1164 int fixed_size; /* fixed size of stack frame */
1165 int gp_size; /* size of saved GP registers */
1166 int fp_size; /* size of saved FP registers */
1167 int cr_size; /* size to hold CR if not in save_size */
1168 int lr_size; /* size to hold LR if not in save_size */
1169 int toc_size; /* size to hold TOC if not in save_size */
1170 int total_size; /* total bytes allocated for stack */
1173 /* Define this if pushing a word on the stack
1174 makes the stack pointer a smaller address. */
1175 #define STACK_GROWS_DOWNWARD
1177 /* Define this if the nominal address of the stack frame
1178 is at the high-address end of the local variables;
1179 that is, each additional local variable allocated
1180 goes at a more negative offset in the frame.
1182 On the RS/6000, we grow upwards, from the area after the outgoing
1184 /* #define FRAME_GROWS_DOWNWARD */
1186 /* Size of the outgoing register save area */
1187 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1188 || DEFAULT_ABI == ABI_AIX_NODESC \
1189 || DEFAULT_ABI == ABI_DARWIN) \
1190 ? (TARGET_64BIT ? 64 : 32) \
1193 /* Size of the fixed area on the stack */
1194 #define RS6000_SAVE_AREA \
1195 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1196 << (TARGET_64BIT ? 1 : 0))
1198 /* MEM representing address to save the TOC register */
1199 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1200 plus_constant (stack_pointer_rtx, \
1201 (TARGET_32BIT ? 20 : 40)))
1203 /* Size of the V.4 varargs area if needed */
1204 #define RS6000_VARARGS_AREA 0
1206 /* Align an address */
1207 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1209 /* Size of V.4 varargs area in bytes */
1210 #define RS6000_VARARGS_SIZE \
1211 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1213 /* Offset within stack frame to start allocating local variables at.
1214 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1215 first local allocated. Otherwise, it is the offset to the BEGINNING
1216 of the first local allocated.
1218 On the RS/6000, the frame pointer is the same as the stack pointer,
1219 except for dynamic allocations. So we start after the fixed area and
1220 outgoing parameter area. */
1222 #define STARTING_FRAME_OFFSET \
1223 (RS6000_ALIGN (current_function_outgoing_args_size, 8) \
1224 + RS6000_VARARGS_AREA \
1227 /* Offset from the stack pointer register to an item dynamically
1228 allocated on the stack, e.g., by `alloca'.
1230 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1231 length of the outgoing arguments. The default is correct for most
1232 machines. See `function.c' for details. */
1233 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1234 (RS6000_ALIGN (current_function_outgoing_args_size, 8) \
1235 + (STACK_POINTER_OFFSET))
1237 /* If we generate an insn to push BYTES bytes,
1238 this says how many the stack pointer really advances by.
1239 On RS/6000, don't define this because there are no push insns. */
1240 /* #define PUSH_ROUNDING(BYTES) */
1242 /* Offset of first parameter from the argument pointer register value.
1243 On the RS/6000, we define the argument pointer to the start of the fixed
1245 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1247 /* Offset from the argument pointer register value to the top of
1248 stack. This is different from FIRST_PARM_OFFSET because of the
1249 register save area. */
1250 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1252 /* Define this if stack space is still allocated for a parameter passed
1253 in a register. The value is the number of bytes allocated to this
1255 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1257 /* Define this if the above stack space is to be considered part of the
1258 space allocated by the caller. */
1259 #define OUTGOING_REG_PARM_STACK_SPACE
1261 /* This is the difference between the logical top of stack and the actual sp.
1263 For the RS/6000, sp points past the fixed area. */
1264 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1266 /* Define this if the maximum size of all the outgoing args is to be
1267 accumulated and pushed during the prologue. The amount can be
1268 found in the variable current_function_outgoing_args_size. */
1269 #define ACCUMULATE_OUTGOING_ARGS 1
1271 /* Value is the number of bytes of arguments automatically
1272 popped when returning from a subroutine call.
1273 FUNDECL is the declaration node of the function (as a tree),
1274 FUNTYPE is the data type of the function (as a tree),
1275 or for a library call it is an identifier node for the subroutine name.
1276 SIZE is the number of bytes of arguments passed on the stack. */
1278 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1280 /* Define how to find the value returned by a function.
1281 VALTYPE is the data type of the value (as a tree).
1282 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1283 otherwise, FUNC is 0.
1285 On RS/6000 an integer value is in r3 and a floating-point value is in
1286 fp1, unless -msoft-float. */
1288 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1289 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
1290 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1291 || POINTER_TYPE_P (VALTYPE) \
1292 ? word_mode : TYPE_MODE (VALTYPE), \
1293 TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT ? 33 : 3)
1295 /* Define how to find the value returned by a library function
1296 assuming the value has mode MODE. */
1298 #define LIBCALL_VALUE(MODE) \
1299 gen_rtx_REG (MODE, (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1300 && TARGET_HARD_FLOAT ? 33 : 3))
1302 /* The definition of this macro implies that there are cases where
1303 a scalar value cannot be returned in registers.
1305 For the RS/6000, any structure or union type is returned in memory, except for
1306 Solaris, which returns structures <= 8 bytes in registers. */
1308 #define RETURN_IN_MEMORY(TYPE) \
1309 (TYPE_MODE (TYPE) == BLKmode \
1310 && (DEFAULT_ABI != ABI_SOLARIS || int_size_in_bytes (TYPE) > 8))
1312 /* Mode of stack savearea.
1313 FUNCTION is VOIDmode because calling convention maintains SP.
1314 BLOCK needs Pmode for SP.
1315 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1316 #define STACK_SAVEAREA_MODE(LEVEL) \
1317 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1318 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1320 /* Minimum and maximum general purpose registers used to hold arguments. */
1321 #define GP_ARG_MIN_REG 3
1322 #define GP_ARG_MAX_REG 10
1323 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1325 /* Minimum and maximum floating point registers used to hold arguments. */
1326 #define FP_ARG_MIN_REG 33
1327 #define FP_ARG_AIX_MAX_REG 45
1328 #define FP_ARG_V4_MAX_REG 40
1329 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1330 || DEFAULT_ABI == ABI_AIX_NODESC \
1331 || DEFAULT_ABI == ABI_DARWIN) \
1332 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1333 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1335 /* Return registers */
1336 #define GP_ARG_RETURN GP_ARG_MIN_REG
1337 #define FP_ARG_RETURN FP_ARG_MIN_REG
1339 /* Flags for the call/call_value rtl operations set up by function_arg */
1340 #define CALL_NORMAL 0x00000000 /* no special processing */
1341 /* Bits in 0x00000001 are unused. */
1342 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1343 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1344 #define CALL_LONG 0x00000008 /* always call indirect */
1346 /* 1 if N is a possible register number for a function value
1347 as seen by the caller.
1349 On RS/6000, this is r3 and fp1. */
1350 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN || ((N) == FP_ARG_RETURN))
1352 /* 1 if N is a possible register number for function argument passing.
1353 On RS/6000, these are r3-r10 and fp1-fp13. */
1354 #define FUNCTION_ARG_REGNO_P(N) \
1355 ((unsigned)(((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \
1356 || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))
1359 /* A C structure for machine-specific, per-function data.
1360 This is added to the cfun structure. */
1361 typedef struct machine_function
1363 /* Whether a System V.4 varargs area was created. */
1365 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1366 int ra_needs_full_frame;
1369 /* Define a data type for recording info about an argument list
1370 during the scan of that argument list. This data type should
1371 hold all necessary information about the function itself
1372 and about the args processed so far, enough to enable macros
1373 such as FUNCTION_ARG to determine where the next arg should go.
1375 On the RS/6000, this is a structure. The first element is the number of
1376 total argument words, the second is used to store the next
1377 floating-point register number, and the third says how many more args we
1378 have prototype types for.
1380 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1381 the next availible GP register, `fregno' is the next available FP
1382 register, and `words' is the number of words used on the stack.
1384 The varargs/stdarg support requires that this structure's size
1385 be a multiple of sizeof(int). */
1387 typedef struct rs6000_args
1389 int words; /* # words used for passing GP registers */
1390 int fregno; /* next available FP register */
1391 int nargs_prototype; /* # args left in the current prototype */
1392 int orig_nargs; /* Original value of nargs_prototype */
1393 int prototype; /* Whether a prototype was defined */
1394 int call_cookie; /* Do special things for this call */
1395 int sysv_gregno; /* next available GP register */
1398 /* Define intermediate macro to compute the size (in registers) of an argument
1401 #define RS6000_ARG_SIZE(MODE, TYPE) \
1402 ((MODE) != BLKmode \
1403 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1404 : ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1405 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1407 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1408 for a call to a function whose data type is FNTYPE.
1409 For a library call, FNTYPE is 0. */
1411 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1412 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
1414 /* Similar, but when scanning the definition of a procedure. We always
1415 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1417 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1418 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
1420 /* Update the data in CUM to advance over an argument
1421 of mode MODE and data type TYPE.
1422 (TYPE is null for libcalls where that information may not be available.) */
1424 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1425 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1427 /* Non-zero if we can use a floating-point register to pass this arg. */
1428 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1429 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1430 && (CUM).fregno <= FP_ARG_MAX_REG \
1431 && TARGET_HARD_FLOAT)
1433 /* Determine where to put an argument to a function.
1434 Value is zero to push the argument on the stack,
1435 or a hard register in which to store the argument.
1437 MODE is the argument's machine mode.
1438 TYPE is the data type of the argument (as a tree).
1439 This is null for libcalls where that information may
1441 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1442 the preceding args and about the function being called.
1443 NAMED is nonzero if this argument is a named parameter
1444 (otherwise it is an extra parameter matching an ellipsis).
1446 On RS/6000 the first eight words of non-FP are normally in registers
1447 and the rest are pushed. The first 13 FP args are in registers.
1449 If this is floating-point and no prototype is specified, we use
1450 both an FP and integer register (or possibly FP reg and stack). Library
1451 functions (when TYPE is zero) always have the proper types for args,
1452 so we can pass the FP value just in one register. emit_library_function
1453 doesn't support EXPR_LIST anyway. */
1455 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1456 function_arg (&CUM, MODE, TYPE, NAMED)
1458 /* For an arg passed partly in registers and partly in memory,
1459 this is the number of registers used.
1460 For args passed entirely in registers or entirely in memory, zero. */
1462 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1463 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1465 /* A C expression that indicates when an argument must be passed by
1466 reference. If nonzero for an argument, a copy of that argument is
1467 made in memory and a pointer to the argument is passed instead of
1468 the argument itself. The pointer is passed in whatever way is
1469 appropriate for passing a pointer to that type. */
1471 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1472 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1474 /* If defined, a C expression which determines whether, and in which
1475 direction, to pad out an argument with extra space. The value
1476 should be of type `enum direction': either `upward' to pad above
1477 the argument, `downward' to pad below, or `none' to inhibit
1480 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1482 /* If defined, a C expression that gives the alignment boundary, in bits,
1483 of an argument with the specified mode and type. If it is not defined,
1484 PARM_BOUNDARY is used for all arguments. */
1486 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1487 function_arg_boundary (MODE, TYPE)
1489 /* Perform any needed actions needed for a function that is receiving a
1490 variable number of arguments.
1494 MODE and TYPE are the mode and type of the current parameter.
1496 PRETEND_SIZE is a variable that should be set to the amount of stack
1497 that must be pushed by the prolog to pretend that our caller pushed
1500 Normally, this macro will push all remaining incoming registers on the
1501 stack and set PRETEND_SIZE to the length of the registers pushed. */
1503 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1504 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1506 /* Define the `__builtin_va_list' type for the ABI. */
1507 #define BUILD_VA_LIST_TYPE(VALIST) \
1508 (VALIST) = rs6000_build_va_list ()
1510 /* Implement `va_start' for varargs and stdarg. */
1511 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1512 rs6000_va_start (stdarg, valist, nextarg)
1514 /* Implement `va_arg'. */
1515 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1516 rs6000_va_arg (valist, type)
1518 /* Define this macro to be a nonzero value if the location where a function
1519 argument is passed depends on whether or not it is a named argument. */
1520 #define STRICT_ARGUMENT_NAMING 1
1522 /* Output assembler code to FILE to increment profiler label # LABELNO
1523 for profiling a function entry. */
1525 #define FUNCTION_PROFILER(FILE, LABELNO) \
1526 output_function_profiler ((FILE), (LABELNO));
1528 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1529 the stack pointer does not matter. No definition is equivalent to
1532 On the RS/6000, this is non-zero because we can restore the stack from
1533 its backpointer, which we maintain. */
1534 #define EXIT_IGNORE_STACK 1
1536 /* Define this macro as a C expression that is nonzero for registers
1537 that are used by the epilogue or the return' pattern. The stack
1538 and frame pointer registers are already be assumed to be used as
1541 #define EPILOGUE_USES(REGNO) \
1542 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1543 || (current_function_calls_eh_return \
1545 && (REGNO) == TOC_REGISTER))
1548 /* TRAMPOLINE_TEMPLATE deleted */
1550 /* Length in units of the trampoline for entering a nested function. */
1552 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1554 /* Emit RTL insns to initialize the variable parts of a trampoline.
1555 FNADDR is an RTX for the address of the function's pure code.
1556 CXT is an RTX for the static chain value for the function. */
1558 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1559 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1561 /* Definitions for __builtin_return_address and __builtin_frame_address.
1562 __builtin_return_address (0) should give link register (65), enable
1564 /* This should be uncommented, so that the link register is used, but
1565 currently this would result in unmatched insns and spilling fixed
1566 registers so we'll leave it for another day. When these problems are
1567 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1569 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1571 /* Number of bytes into the frame return addresses can be found. See
1572 rs6000_stack_info in rs6000.c for more information on how the different
1573 abi's store the return address. */
1574 #define RETURN_ADDRESS_OFFSET \
1575 ((DEFAULT_ABI == ABI_AIX \
1576 || DEFAULT_ABI == ABI_DARWIN \
1577 || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \
1578 (DEFAULT_ABI == ABI_V4 \
1579 || DEFAULT_ABI == ABI_SOLARIS) ? (TARGET_32BIT ? 4 : 8) : \
1580 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1582 /* The current return address is in link register (65). The return address
1583 of anything farther back is accessed normally at an offset of 8 from the
1585 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1586 (rs6000_return_addr (COUNT, FRAME))
1589 /* Definitions for register eliminations.
1591 We have two registers that can be eliminated on the RS/6000. First, the
1592 frame pointer register can often be eliminated in favor of the stack
1593 pointer register. Secondly, the argument pointer register can always be
1594 eliminated; it is replaced with either the stack or frame pointer.
1596 In addition, we use the elimination mechanism to see if r30 is needed
1597 Initially we assume that it isn't. If it is, we spill it. This is done
1598 by making it an eliminable register. We replace it with itself so that
1599 if it isn't needed, then existing uses won't be modified. */
1601 /* This is an array of structures. Each structure initializes one pair
1602 of eliminable registers. The "from" register number is given first,
1603 followed by "to". Eliminations of the same "from" register are listed
1604 in order of preference. */
1605 #define ELIMINABLE_REGS \
1606 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1607 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1608 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1611 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1612 Frame pointer elimination is automatically handled.
1614 For the RS/6000, if frame pointer elimination is being done, we would like
1615 to convert ap into fp, not sp.
1617 We need r30 if -mminimal-toc was specified, and there are constant pool
1620 #define CAN_ELIMINATE(FROM, TO) \
1621 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1622 ? ! frame_pointer_needed \
1623 : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1626 /* Define the offset between two registers, one to be eliminated, and the other
1627 its replacement, at the start of a routine. */
1628 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1630 rs6000_stack_t *info = rs6000_stack_info (); \
1632 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1633 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
1634 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1635 (OFFSET) = info->total_size; \
1636 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1637 (OFFSET) = (info->push_p) ? info->total_size : 0; \
1638 else if ((FROM) == 30) \
1644 /* Addressing modes, and classification of registers for them. */
1646 /* #define HAVE_POST_INCREMENT 0 */
1647 /* #define HAVE_POST_DECREMENT 0 */
1649 #define HAVE_PRE_DECREMENT 1
1650 #define HAVE_PRE_INCREMENT 1
1652 /* Macros to check register numbers against specific register classes. */
1654 /* These assume that REGNO is a hard or pseudo reg number.
1655 They give nonzero only if REGNO is a hard reg of the suitable class
1656 or a pseudo reg currently allocated to a suitable hard reg.
1657 Since they use reg_renumber, they are safe only once reg_renumber
1658 has been allocated, which happens in local-alloc.c. */
1660 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1661 ((REGNO) < FIRST_PSEUDO_REGISTER \
1662 ? (REGNO) <= 31 || (REGNO) == 67 \
1663 : (reg_renumber[REGNO] >= 0 \
1664 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1666 #define REGNO_OK_FOR_BASE_P(REGNO) \
1667 ((REGNO) < FIRST_PSEUDO_REGISTER \
1668 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1669 : (reg_renumber[REGNO] > 0 \
1670 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1672 /* Maximum number of registers that can appear in a valid memory address. */
1674 #define MAX_REGS_PER_ADDRESS 2
1676 /* Recognize any constant value that is a valid address. */
1678 #define CONSTANT_ADDRESS_P(X) \
1679 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1680 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1681 || GET_CODE (X) == HIGH)
1683 /* Nonzero if the constant value X is a legitimate general operand.
1684 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1686 On the RS/6000, all integer constants are acceptable, most won't be valid
1687 for particular insns, though. Only easy FP constants are
1690 #define LEGITIMATE_CONSTANT_P(X) \
1691 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1692 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1693 || easy_fp_constant (X, GET_MODE (X)))
1695 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1696 and check its validity for a certain class.
1697 We have two alternate definitions for each of them.
1698 The usual definition accepts all pseudo regs; the other rejects
1699 them unless they have been allocated suitable hard regs.
1700 The symbol REG_OK_STRICT causes the latter definition to be used.
1702 Most source files want to accept pseudo regs in the hope that
1703 they will get allocated to the class that the insn wants them to be in.
1704 Source files for reload pass need to be strict.
1705 After reload, it makes no difference, since pseudo regs have
1706 been eliminated by then. */
1708 #ifdef REG_OK_STRICT
1709 # define REG_OK_STRICT_FLAG 1
1711 # define REG_OK_STRICT_FLAG 0
1714 /* Nonzero if X is a hard reg that can be used as an index
1715 or if it is a pseudo reg in the non-strict case. */
1716 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1718 && (REGNO (X) <= 31 \
1719 || REGNO (X) == ARG_POINTER_REGNUM \
1720 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1721 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1723 /* Nonzero if X is a hard reg that can be used as a base reg
1724 or if it is a pseudo reg in the non-strict case. */
1725 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1726 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1728 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1729 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1731 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1732 that is a valid memory address for an instruction.
1733 The MODE argument is the machine mode for the MEM expression
1734 that wants to use this address.
1736 On the RS/6000, there are four valid address: a SYMBOL_REF that
1737 refers to a constant pool entry of an address (or the sum of it
1738 plus a constant), a short (16-bit signed) constant plus a register,
1739 the sum of two registers, or a register indirect, possibly with an
1740 auto-increment. For DFmode and DImode with an constant plus register,
1741 we must ensure that both words are addressable or PowerPC64 with offset
1744 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1745 32-bit DImode, TImode), indexed addressing cannot be used because
1746 adjacent memory cells are accessed by adding word-sized offsets
1747 during assembly output. */
1749 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X))
1751 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X))
1753 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \
1755 && GET_CODE (X) == PLUS \
1756 && GET_CODE (XEXP (X, 0)) == REG \
1757 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \
1758 && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))
1760 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \
1761 ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
1762 && !flag_pic && !TARGET_TOC \
1763 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \
1764 && small_data_operand (X, MODE))
1766 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \
1767 (GET_CODE (X) == CONST_INT \
1768 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
1770 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \
1771 (GET_CODE (X) == PLUS \
1772 && GET_CODE (XEXP (X, 0)) == REG \
1773 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1774 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \
1775 && (((MODE) != DFmode && (MODE) != DImode) \
1777 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
1778 : ! (INTVAL (XEXP (X, 1)) & 3))) \
1779 && ((MODE) != TImode \
1781 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
1782 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
1783 && ! (INTVAL (XEXP (X, 1)) & 3)))))
1785 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \
1786 (GET_CODE (X) == PLUS \
1787 && GET_CODE (XEXP (X, 0)) == REG \
1788 && GET_CODE (XEXP (X, 1)) == REG \
1789 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1790 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
1791 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \
1792 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))
1794 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \
1795 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
1797 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \
1799 && ! flag_pic && ! TARGET_TOC \
1800 && (MODE) != DImode \
1801 && (MODE) != TImode \
1802 && (TARGET_HARD_FLOAT || (MODE) != DFmode) \
1803 && GET_CODE (X) == LO_SUM \
1804 && GET_CODE (XEXP (X, 0)) == REG \
1805 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1806 && CONSTANT_P (XEXP (X, 1)))
1808 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1809 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1813 /* Try machine-dependent ways of modifying an illegitimate address
1814 to be legitimate. If we find one, return the new, valid address.
1815 This macro is used in only one place: `memory_address' in explow.c.
1817 OLDX is the address as it was before break_out_memory_refs was called.
1818 In some cases it is useful to look at this to decide what needs to be done.
1820 MODE and WIN are passed so that this macro can use
1821 GO_IF_LEGITIMATE_ADDRESS.
1823 It is always safe for this macro to do nothing. It exists to recognize
1824 opportunities to optimize the output.
1826 On RS/6000, first check for the sum of a register with a constant
1827 integer that is out of range. If so, generate code to add the
1828 constant with the low-order 16 bits masked to the register and force
1829 this result into another register (this can be done with `cau').
1830 Then generate an address of REG+(CONST&0xffff), allowing for the
1831 possibility of bit 16 being a one.
1833 Then check for the sum of a register and something not constant, try to
1834 load the other things into a register and return the sum. */
1836 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1837 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
1838 if (result != NULL_RTX) \
1845 /* Try a machine-dependent way of reloading an illegitimate address
1846 operand. If we find one, push the reload and jump to WIN. This
1847 macro is used in only one place: `find_reloads_address' in reload.c.
1849 For RS/6000, we wish to handle large displacements off a base
1850 register by splitting the addend across an addiu/addis and the mem insn.
1851 This cuts number of extra insns needed from 3 to 1. */
1853 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1855 /* We must recognize output that we have already generated ourselves. */ \
1856 if (GET_CODE (X) == PLUS \
1857 && GET_CODE (XEXP (X, 0)) == PLUS \
1858 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1859 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1860 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1862 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1863 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1867 if (GET_CODE (X) == PLUS \
1868 && GET_CODE (XEXP (X, 0)) == REG \
1869 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1870 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1871 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1873 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1874 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
1875 HOST_WIDE_INT high \
1876 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
1878 /* Check for 32-bit overflow. */ \
1879 if (high + low != val) \
1882 /* Reload the high part into a base reg; leave the low part \
1883 in the mem directly. */ \
1885 X = gen_rtx_PLUS (GET_MODE (X), \
1886 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1890 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1891 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1895 else if (TARGET_TOC \
1896 && CONSTANT_POOL_EXPR_P (X) \
1897 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (X), MODE)) \
1899 (X) = create_TOC_reference (X); \
1904 /* Go to LABEL if ADDR (a legitimate address expression)
1905 has an effect that depends on the machine mode it is used for.
1907 On the RS/6000 this is true if the address is valid with a zero offset
1908 but not with an offset of four (this means it cannot be used as an
1909 address for DImode or DFmode) or is a pre-increment or decrement. Since
1910 we know it is valid, we just check for an address that is not valid with
1911 an offset of four. */
1913 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1914 { if (GET_CODE (ADDR) == PLUS \
1915 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
1916 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \
1917 (TARGET_32BIT ? 4 : 8))) \
1919 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \
1921 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \
1923 if (GET_CODE (ADDR) == LO_SUM) \
1927 /* The register number of the register used to address a table of
1928 static data addresses in memory. In some cases this register is
1929 defined by a processor's "application binary interface" (ABI).
1930 When this macro is defined, RTL is generated for this register
1931 once, as with the stack pointer and frame pointer registers. If
1932 this macro is not defined, it is up to the machine-dependent files
1933 to allocate such a register (if necessary). */
1935 #define PIC_OFFSET_TABLE_REGNUM 30
1937 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? 30 : 2)
1939 /* Define this macro if the register defined by
1940 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1941 this macro if `PPIC_OFFSET_TABLE_REGNUM' is not defined. */
1943 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1945 /* By generating position-independent code, when two different
1946 programs (A and B) share a common library (libC.a), the text of
1947 the library can be shared whether or not the library is linked at
1948 the same address for both programs. In some of these
1949 environments, position-independent code requires not only the use
1950 of different addressing modes, but also special code to enable the
1951 use of these addressing modes.
1953 The `FINALIZE_PIC' macro serves as a hook to emit these special
1954 codes once the function is being compiled into assembly code, but
1955 not before. (It is not done before, because in the case of
1956 compiling an inline function, it would lead to multiple PIC
1957 prologues being included in functions which used inline functions
1958 and were compiled to assembly language.) */
1960 /* #define FINALIZE_PIC */
1962 /* A C expression that is nonzero if X is a legitimate immediate
1963 operand on the target machine when generating position independent
1964 code. You can assume that X satisfies `CONSTANT_P', so you need
1965 not check this. You can also assume FLAG_PIC is true, so you need
1966 not check it either. You need not define this macro if all
1967 constants (including `SYMBOL_REF') can be immediate operands when
1968 generating position independent code. */
1970 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1972 /* In rare cases, correct code generation requires extra machine
1973 dependent processing between the second jump optimization pass and
1974 delayed branch scheduling. On those machines, define this macro
1975 as a C statement to act on the code starting at INSN. */
1977 /* #define MACHINE_DEPENDENT_REORG(INSN) */
1980 /* Define this if some processing needs to be done immediately before
1981 emitting code for an insn. */
1983 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
1985 /* Specify the machine mode that this machine uses
1986 for the index in the tablejump instruction. */
1987 #define CASE_VECTOR_MODE SImode
1989 /* Define as C expression which evaluates to nonzero if the tablejump
1990 instruction expects the table to contain offsets from the address of the
1992 Do not define this if the table should contain absolute addresses. */
1993 #define CASE_VECTOR_PC_RELATIVE 1
1995 /* Specify the tree operation to be used to convert reals to integers. */
1996 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1998 /* This is the kind of divide that is easiest to do in the general case. */
1999 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2001 /* Define this as 1 if `char' should by default be signed; else as 0. */
2002 #define DEFAULT_SIGNED_CHAR 0
2004 /* This flag, if defined, says the same insns that convert to a signed fixnum
2005 also convert validly to an unsigned one. */
2007 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2009 /* Max number of bytes we can move from memory to memory
2010 in one reasonably fast instruction. */
2011 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2012 #define MAX_MOVE_MAX 8
2014 /* Nonzero if access to memory by bytes is no faster than for words.
2015 Also non-zero if doing byte operations (specifically shifts) in registers
2017 #define SLOW_BYTE_ACCESS 1
2019 /* Define if operations between registers always perform the operation
2020 on the full register even if a narrower mode is specified. */
2021 #define WORD_REGISTER_OPERATIONS
2023 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2024 will either zero-extend or sign-extend. The value of this macro should
2025 be the code that says which one of the two operations is implicitly
2026 done, NIL if none. */
2027 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2029 /* Define if loading short immediate values into registers sign extends. */
2030 #define SHORT_IMMEDIATES_SIGN_EXTEND
2032 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2033 is done just by pretending it is already truncated. */
2034 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2036 /* Specify the machine mode that pointers have.
2037 After generation of rtl, the compiler makes no further distinction
2038 between pointers and any other objects of this machine mode. */
2039 #define Pmode (TARGET_32BIT ? SImode : DImode)
2041 /* Mode of a function address in a call instruction (for indexing purposes).
2042 Doesn't matter on RS/6000. */
2043 #define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode)
2045 /* Define this if addresses of constant functions
2046 shouldn't be put through pseudo regs where they can be cse'd.
2047 Desirable on machines where ordinary constants are expensive
2048 but a CALL with constant address is cheap. */
2049 #define NO_FUNCTION_CSE
2051 /* Define this to be nonzero if shift instructions ignore all but the low-order
2054 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2055 have been dropped from the PowerPC architecture. */
2057 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2059 /* Compute the cost of computing a constant rtl expression RTX
2060 whose rtx-code is CODE. The body of this macro is a portion
2061 of a switch statement. If the code is computed here,
2062 return it with a return statement. Otherwise, break from the switch.
2064 On the RS/6000, if it is valid in the insn, it is free. So this
2065 always returns 0. */
2067 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2072 case CONST_DOUBLE: \
2076 /* Provide the costs of a rtl expression. This is in the body of a
2079 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2081 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2082 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) \
2083 + 0x8000) >= 0x10000) \
2084 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2085 ? COSTS_N_INSNS (2) \
2086 : COSTS_N_INSNS (1)); \
2090 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2091 && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \
2092 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2093 ? COSTS_N_INSNS (2) \
2094 : COSTS_N_INSNS (1)); \
2096 switch (rs6000_cpu) \
2098 case PROCESSOR_RIOS1: \
2099 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2100 ? COSTS_N_INSNS (5) \
2101 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2102 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2103 case PROCESSOR_RS64A: \
2104 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2105 ? GET_MODE (XEXP (X, 1)) != DImode \
2106 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \
2107 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2108 ? COSTS_N_INSNS (12) : COSTS_N_INSNS (14)); \
2109 case PROCESSOR_RIOS2: \
2110 case PROCESSOR_MPCCORE: \
2111 case PROCESSOR_PPC604e: \
2112 return COSTS_N_INSNS (2); \
2113 case PROCESSOR_PPC601: \
2114 return COSTS_N_INSNS (5); \
2115 case PROCESSOR_PPC603: \
2116 case PROCESSOR_PPC750: \
2117 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2118 ? COSTS_N_INSNS (5) \
2119 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2120 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
2121 case PROCESSOR_PPC403: \
2122 case PROCESSOR_PPC604: \
2123 return COSTS_N_INSNS (4); \
2124 case PROCESSOR_PPC620: \
2125 case PROCESSOR_PPC630: \
2126 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2127 ? GET_MODE (XEXP (X, 1)) != DImode \
2128 ? COSTS_N_INSNS (4) : COSTS_N_INSNS (7) \
2129 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2130 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2134 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2135 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
2136 return COSTS_N_INSNS (2); \
2137 /* otherwise fall through to normal divide. */ \
2140 switch (rs6000_cpu) \
2142 case PROCESSOR_RIOS1: \
2143 return COSTS_N_INSNS (19); \
2144 case PROCESSOR_RIOS2: \
2145 return COSTS_N_INSNS (13); \
2146 case PROCESSOR_RS64A: \
2147 return (GET_MODE (XEXP (X, 1)) != DImode \
2148 ? COSTS_N_INSNS (65) \
2149 : COSTS_N_INSNS (67)); \
2150 case PROCESSOR_MPCCORE: \
2151 return COSTS_N_INSNS (6); \
2152 case PROCESSOR_PPC403: \
2153 return COSTS_N_INSNS (33); \
2154 case PROCESSOR_PPC601: \
2155 return COSTS_N_INSNS (36); \
2156 case PROCESSOR_PPC603: \
2157 return COSTS_N_INSNS (37); \
2158 case PROCESSOR_PPC604: \
2159 case PROCESSOR_PPC604e: \
2160 return COSTS_N_INSNS (20); \
2161 case PROCESSOR_PPC620: \
2162 case PROCESSOR_PPC630: \
2163 return (GET_MODE (XEXP (X, 1)) != DImode \
2164 ? COSTS_N_INSNS (21) \
2165 : COSTS_N_INSNS (37)); \
2166 case PROCESSOR_PPC750: \
2167 return COSTS_N_INSNS (19); \
2170 return COSTS_N_INSNS (4); \
2172 /* MEM should be slightly more expensive than (plus (reg) (const)) */ \
2175 /* Compute the cost of an address. This is meant to approximate the size
2176 and/or execution delay of an insn using that address. If the cost is
2177 approximated by the RTL complexity, including CONST_COSTS above, as
2178 is usually the case for CISC machines, this macro should not be defined.
2179 For aggressively RISCy machines, only one insn format is allowed, so
2180 this macro should be a constant. The value of this macro only matters
2181 for valid addresses.
2183 For the RS/6000, everything is cost 0. */
2185 #define ADDRESS_COST(RTX) 0
2187 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2188 should be adjusted to reflect any required changes. This macro is used when
2189 there is some systematic length adjustment required that would be difficult
2190 to express in the length attribute. */
2192 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2194 /* Add any extra modes needed to represent the condition code.
2196 For the RS/6000, we need separate modes when unsigned (logical) comparisons
2197 are being done and we need a separate mode for floating-point. We also
2198 use a mode for the case when we are comparing the results of two
2199 comparisons, as then only the EQ bit is valid in the register. */
2201 #define EXTRA_CC_MODES \
2202 CC(CCUNSmode, "CCUNS") \
2203 CC(CCFPmode, "CCFP") \
2204 CC(CCEQmode, "CCEQ")
2206 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2207 COMPARE, return the mode to be used for the comparison. For
2208 floating-point, CCFPmode should be used. CCUNSmode should be used
2209 for unsigned comparisons. CCEQmode should be used when we are
2210 doing an inequality comparison on the result of a
2211 comparison. CCmode should be used in all other cases. */
2213 #define SELECT_CC_MODE(OP,X,Y) \
2214 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2215 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2216 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2217 ? CCEQmode : CCmode))
2219 /* Define the information needed to generate branch and scc insns. This is
2220 stored from the compare operation. Note that we can't use "rtx" here
2221 since it hasn't been defined! */
2223 extern struct rtx_def *rs6000_compare_op0, *rs6000_compare_op1;
2224 extern int rs6000_compare_fp_p;
2226 /* Control the assembler format that we output. */
2228 /* A C string constant describing how to begin a comment in the target
2229 assembler language. The compiler assumes that the comment will end at
2230 the end of the line. */
2231 #define ASM_COMMENT_START " #"
2233 /* Implicit library calls should use memcpy, not bcopy, etc. */
2235 #define TARGET_MEM_FUNCTIONS
2237 /* Flag to say the TOC is initialized */
2238 extern int toc_initialized;
2240 /* Macro to output a special constant pool entry. Go to WIN if we output
2241 it. Otherwise, it is written the usual way.
2243 On the RS/6000, toc entries are handled this way. */
2245 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2246 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2248 output_toc (FILE, X, LABELNO, MODE); \
2253 /* This implementes the `alias' attribute. */
2255 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE,decl,target) \
2257 const char * alias = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2258 char * name = IDENTIFIER_POINTER (target); \
2259 if (TREE_CODE (decl) == FUNCTION_DECL \
2260 && DEFAULT_ABI == ABI_AIX) \
2262 if (TREE_PUBLIC (decl)) \
2264 fputs ("\t.globl .", FILE); \
2265 assemble_name (FILE, alias); \
2266 putc ('\n', FILE); \
2270 fputs ("\t.lglobl .", FILE); \
2271 assemble_name (FILE, alias); \
2272 putc ('\n', FILE); \
2274 fputs ("\t.set .", FILE); \
2275 assemble_name (FILE, alias); \
2276 fputs (",.", FILE); \
2277 assemble_name (FILE, name); \
2278 fputc ('\n', FILE); \
2280 ASM_OUTPUT_DEF (FILE, alias, name); \
2283 /* Output to assembler file text saying following lines
2284 may contain character constants, extra white space, comments, etc. */
2286 #define ASM_APP_ON ""
2288 /* Output to assembler file text saying following lines
2289 no longer contain unusual constructs. */
2291 #define ASM_APP_OFF ""
2293 /* How to refer to registers in assembler output.
2294 This sequence is indexed by compiler's hard-register-number (see above). */
2296 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2298 #define REGISTER_NAMES \
2300 &rs6000_reg_names[ 0][0], /* r0 */ \
2301 &rs6000_reg_names[ 1][0], /* r1 */ \
2302 &rs6000_reg_names[ 2][0], /* r2 */ \
2303 &rs6000_reg_names[ 3][0], /* r3 */ \
2304 &rs6000_reg_names[ 4][0], /* r4 */ \
2305 &rs6000_reg_names[ 5][0], /* r5 */ \
2306 &rs6000_reg_names[ 6][0], /* r6 */ \
2307 &rs6000_reg_names[ 7][0], /* r7 */ \
2308 &rs6000_reg_names[ 8][0], /* r8 */ \
2309 &rs6000_reg_names[ 9][0], /* r9 */ \
2310 &rs6000_reg_names[10][0], /* r10 */ \
2311 &rs6000_reg_names[11][0], /* r11 */ \
2312 &rs6000_reg_names[12][0], /* r12 */ \
2313 &rs6000_reg_names[13][0], /* r13 */ \
2314 &rs6000_reg_names[14][0], /* r14 */ \
2315 &rs6000_reg_names[15][0], /* r15 */ \
2316 &rs6000_reg_names[16][0], /* r16 */ \
2317 &rs6000_reg_names[17][0], /* r17 */ \
2318 &rs6000_reg_names[18][0], /* r18 */ \
2319 &rs6000_reg_names[19][0], /* r19 */ \
2320 &rs6000_reg_names[20][0], /* r20 */ \
2321 &rs6000_reg_names[21][0], /* r21 */ \
2322 &rs6000_reg_names[22][0], /* r22 */ \
2323 &rs6000_reg_names[23][0], /* r23 */ \
2324 &rs6000_reg_names[24][0], /* r24 */ \
2325 &rs6000_reg_names[25][0], /* r25 */ \
2326 &rs6000_reg_names[26][0], /* r26 */ \
2327 &rs6000_reg_names[27][0], /* r27 */ \
2328 &rs6000_reg_names[28][0], /* r28 */ \
2329 &rs6000_reg_names[29][0], /* r29 */ \
2330 &rs6000_reg_names[30][0], /* r30 */ \
2331 &rs6000_reg_names[31][0], /* r31 */ \
2333 &rs6000_reg_names[32][0], /* fr0 */ \
2334 &rs6000_reg_names[33][0], /* fr1 */ \
2335 &rs6000_reg_names[34][0], /* fr2 */ \
2336 &rs6000_reg_names[35][0], /* fr3 */ \
2337 &rs6000_reg_names[36][0], /* fr4 */ \
2338 &rs6000_reg_names[37][0], /* fr5 */ \
2339 &rs6000_reg_names[38][0], /* fr6 */ \
2340 &rs6000_reg_names[39][0], /* fr7 */ \
2341 &rs6000_reg_names[40][0], /* fr8 */ \
2342 &rs6000_reg_names[41][0], /* fr9 */ \
2343 &rs6000_reg_names[42][0], /* fr10 */ \
2344 &rs6000_reg_names[43][0], /* fr11 */ \
2345 &rs6000_reg_names[44][0], /* fr12 */ \
2346 &rs6000_reg_names[45][0], /* fr13 */ \
2347 &rs6000_reg_names[46][0], /* fr14 */ \
2348 &rs6000_reg_names[47][0], /* fr15 */ \
2349 &rs6000_reg_names[48][0], /* fr16 */ \
2350 &rs6000_reg_names[49][0], /* fr17 */ \
2351 &rs6000_reg_names[50][0], /* fr18 */ \
2352 &rs6000_reg_names[51][0], /* fr19 */ \
2353 &rs6000_reg_names[52][0], /* fr20 */ \
2354 &rs6000_reg_names[53][0], /* fr21 */ \
2355 &rs6000_reg_names[54][0], /* fr22 */ \
2356 &rs6000_reg_names[55][0], /* fr23 */ \
2357 &rs6000_reg_names[56][0], /* fr24 */ \
2358 &rs6000_reg_names[57][0], /* fr25 */ \
2359 &rs6000_reg_names[58][0], /* fr26 */ \
2360 &rs6000_reg_names[59][0], /* fr27 */ \
2361 &rs6000_reg_names[60][0], /* fr28 */ \
2362 &rs6000_reg_names[61][0], /* fr29 */ \
2363 &rs6000_reg_names[62][0], /* fr30 */ \
2364 &rs6000_reg_names[63][0], /* fr31 */ \
2366 &rs6000_reg_names[64][0], /* mq */ \
2367 &rs6000_reg_names[65][0], /* lr */ \
2368 &rs6000_reg_names[66][0], /* ctr */ \
2369 &rs6000_reg_names[67][0], /* ap */ \
2371 &rs6000_reg_names[68][0], /* cr0 */ \
2372 &rs6000_reg_names[69][0], /* cr1 */ \
2373 &rs6000_reg_names[70][0], /* cr2 */ \
2374 &rs6000_reg_names[71][0], /* cr3 */ \
2375 &rs6000_reg_names[72][0], /* cr4 */ \
2376 &rs6000_reg_names[73][0], /* cr5 */ \
2377 &rs6000_reg_names[74][0], /* cr6 */ \
2378 &rs6000_reg_names[75][0], /* cr7 */ \
2380 &rs6000_reg_names[76][0], /* xer */ \
2383 /* print-rtl can't handle the above REGISTER_NAMES, so define the
2384 following for it. Switch to use the alternate names since
2385 they are more mnemonic. */
2387 #define DEBUG_REGISTER_NAMES \
2389 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2390 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2391 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2392 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
2393 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2394 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
2395 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
2396 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
2397 "mq", "lr", "ctr", "ap", \
2398 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
2402 /* Table of additional register names to use in user input. */
2404 #define ADDITIONAL_REGISTER_NAMES \
2405 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2406 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2407 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2408 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2409 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2410 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2411 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2412 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2413 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2414 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2415 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2416 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2417 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2418 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2419 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2420 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2421 /* no additional names for: mq, lr, ctr, ap */ \
2422 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2423 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2424 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2426 /* How to renumber registers for dbx and gdb. */
2428 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2430 /* Text to write out after a CALL that may be replaced by glue code by
2431 the loader. This depends on the AIX version. */
2432 #define RS6000_CALL_GLUE "cror 31,31,31"
2434 /* This is how to output an assembler line defining a `double' constant. */
2436 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
2439 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2440 fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", \
2441 t[0] & 0xffffffff, t[1] & 0xffffffff); \
2444 /* This is how to output an assembler line defining a `float' constant. */
2446 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \
2449 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2450 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
2453 /* This is how to output an assembler line defining an `int' constant. */
2455 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2459 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
2460 UNITS_PER_WORD, BITS_PER_WORD, 1); \
2461 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
2462 UNITS_PER_WORD, BITS_PER_WORD, 1); \
2466 fprintf (FILE, "%s", DOUBLE_INT_ASM_OP); \
2467 output_addr_const (FILE, (VALUE)); \
2468 putc ('\n', FILE); \
2472 #define ASM_OUTPUT_INT(FILE,VALUE) \
2473 ( fputs ("\t.long ", FILE), \
2474 output_addr_const (FILE, (VALUE)), \
2477 /* Likewise for `char' and `short' constants. */
2479 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2480 ( fputs ("\t.short ", FILE), \
2481 output_addr_const (FILE, (VALUE)), \
2484 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2485 ( fputs ("\t.byte ", FILE), \
2486 output_addr_const (FILE, (VALUE)), \
2489 /* This is how to output an assembler line for a numeric constant byte. */
2491 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2492 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
2494 /* This is used by the definition of ASM_OUTPUT_ADDR_ELT in defaults.h. */
2495 #define ASM_LONG (TARGET_32BIT ? ".long" : DOUBLE_INT_ASM_OP)
2497 /* This is how to output an element of a case-vector that is relative. */
2499 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2500 do { char buf[100]; \
2501 fputs ("\t.long ", FILE); \
2502 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2503 assemble_name (FILE, buf); \
2505 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2506 assemble_name (FILE, buf); \
2507 putc ('\n', FILE); \
2510 /* This is how to output an assembler line
2511 that says to advance the location counter
2512 to a multiple of 2**LOG bytes. */
2514 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2516 fprintf (FILE, "\t.align %d\n", (LOG))
2518 /* Store in OUTPUT a string (made with alloca) containing
2519 an assembler-name for a local static variable named NAME.
2520 LABELNO is an integer which is different for each call. */
2522 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2523 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2524 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2526 /* Pick up the return address upon entry to a procedure. Used for
2527 dwarf2 unwind information. This also enables the table driven
2530 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2531 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2533 /* Describe how we implement __builtin_eh_return. */
2534 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2535 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2537 /* Print operand X (an rtx) in assembler syntax to file FILE.
2538 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2539 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2541 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2543 /* Define which CODE values are valid. */
2545 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2546 ((CODE) == '.' || (CODE) == '*' || (CODE) == '$')
2548 /* Print a memory address as an operand to reference that memory location. */
2550 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2552 /* Define the codes that are matched by predicates in rs6000.c. */
2554 #define PREDICATE_CODES \
2555 {"short_cint_operand", {CONST_INT}}, \
2556 {"u_short_cint_operand", {CONST_INT}}, \
2557 {"non_short_cint_operand", {CONST_INT}}, \
2558 {"exact_log2_cint_operand", {CONST_INT}}, \
2559 {"gpc_reg_operand", {SUBREG, REG}}, \
2560 {"cc_reg_operand", {SUBREG, REG}}, \
2561 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2562 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2563 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2564 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2565 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2566 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2567 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2568 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2569 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2570 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2571 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2572 {"easy_fp_constant", {CONST_DOUBLE}}, \
2573 {"zero_fp_constant", {CONST_DOUBLE}}, \
2574 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2575 {"lwa_operand", {SUBREG, MEM, REG}}, \
2576 {"volatile_mem_operand", {MEM}}, \
2577 {"offsettable_mem_operand", {MEM}}, \
2578 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2579 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2580 {"non_add_cint_operand", {CONST_INT}}, \
2581 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2582 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2583 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2584 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2585 {"mask_operand", {CONST_INT}}, \
2586 {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \
2587 {"rldic_operand", {CONST_INT, CONST_DOUBLE}}, \
2588 {"count_register_operand", {REG}}, \
2589 {"xer_operand", {REG}}, \
2590 {"call_operand", {SYMBOL_REF, REG}}, \
2591 {"current_file_function_operand", {SYMBOL_REF}}, \
2592 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2593 CONST_DOUBLE, SYMBOL_REF}}, \
2594 {"load_multiple_operation", {PARALLEL}}, \
2595 {"store_multiple_operation", {PARALLEL}}, \
2596 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2597 GT, LEU, LTU, GEU, GTU, \
2598 UNORDERED, ORDERED, \
2600 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2602 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2603 GT, LEU, LTU, GEU, GTU, \
2604 UNORDERED, ORDERED, \
2606 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2607 GT, LEU, LTU, GEU, GTU}}, \
2608 {"boolean_operator", {AND, IOR, XOR}}, \
2609 {"boolean_or_operator", {IOR, XOR}}, \
2610 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2612 /* uncomment for disabling the corresponding default options */
2613 /* #define MACHINE_no_sched_interblock */
2614 /* #define MACHINE_no_sched_speculative */
2615 /* #define MACHINE_no_sched_speculative_load */
2617 /* General flags. */
2618 extern int flag_pic;
2619 extern int optimize;
2620 extern int flag_expensive_optimizations;
2621 extern int frame_pointer_needed;
OSDN Git Service
