1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Default string to use for cpu if not specified. */
44 #ifndef TARGET_CPU_DEFAULT
45 #define TARGET_CPU_DEFAULT ((char *)0)
48 /* Common ASM definitions used by ASM_SPEC among the various targets
49 for handling -mcpu=xxx switches. */
50 #define ASM_CPU_SPEC \
52 %{mpower: %{!mpower2: -mpwr}} \
54 %{mpowerpc64*: -mppc64} \
55 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
56 %{mno-power: %{!mpowerpc*: -mcom}} \
57 %{!mno-power: %{!mpower*: %(asm_default)}}} \
58 %{mcpu=common: -mcom} \
59 %{mcpu=power: -mpwr} \
60 %{mcpu=power2: -mpwrx} \
61 %{mcpu=power3: -mppc64} \
62 %{mcpu=power4: -mpower4} \
63 %{mcpu=power5: -mpower4} \
64 %{mcpu=powerpc: -mppc} \
66 %{mcpu=rios1: -mpwr} \
67 %{mcpu=rios2: -mpwrx} \
70 %{mcpu=rs64a: -mppc64} \
74 %{mcpu=405fp: -m405} \
76 %{mcpu=440fp: -m440} \
82 %{mcpu=ec603e: -mppc} \
85 %{mcpu=620: -mppc64} \
86 %{mcpu=630: -mppc64} \
90 %{mcpu=7400: -mppc -maltivec} \
91 %{mcpu=7450: -mppc -maltivec} \
92 %{mcpu=G4: -mppc -maltivec} \
97 %{mcpu=970: -mpower4 -maltivec} \
98 %{mcpu=G5: -mpower4 -maltivec} \
99 %{mcpu=8540: -me500} \
100 %{maltivec: -maltivec} \
103 #define CPP_DEFAULT_SPEC ""
105 #define ASM_DEFAULT_SPEC ""
107 /* This macro defines names of additional specifications to put in the specs
108 that can be used in various specifications like CC1_SPEC. Its definition
109 is an initializer with a subgrouping for each command option.
111 Each subgrouping contains a string constant, that defines the
112 specification name, and a string constant that used by the GCC driver
115 Do not define this macro if it does not need to do anything. */
117 #define SUBTARGET_EXTRA_SPECS
119 #define EXTRA_SPECS \
120 { "cpp_default", CPP_DEFAULT_SPEC }, \
121 { "asm_cpu", ASM_CPU_SPEC }, \
122 { "asm_default", ASM_DEFAULT_SPEC }, \
123 SUBTARGET_EXTRA_SPECS
125 /* Architecture type. */
127 extern int target_flags;
129 /* Use POWER architecture instructions and MQ register. */
130 #define MASK_POWER 0x00000001
132 /* Use POWER2 extensions to POWER architecture. */
133 #define MASK_POWER2 0x00000002
135 /* Use PowerPC architecture instructions. */
136 #define MASK_POWERPC 0x00000004
138 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
139 #define MASK_PPC_GPOPT 0x00000008
141 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
142 #define MASK_PPC_GFXOPT 0x00000010
144 /* Use PowerPC-64 architecture instructions. */
145 #define MASK_POWERPC64 0x00000020
147 /* Use revised mnemonic names defined for PowerPC architecture. */
148 #define MASK_NEW_MNEMONICS 0x00000040
150 /* Disable placing fp constants in the TOC; can be turned on when the
152 #define MASK_NO_FP_IN_TOC 0x00000080
154 /* Disable placing symbol+offset constants in the TOC; can be turned on when
155 the TOC overflows. */
156 #define MASK_NO_SUM_IN_TOC 0x00000100
158 /* Output only one TOC entry per module. Normally linking fails if
159 there are more than 16K unique variables/constants in an executable. With
160 this option, linking fails only if there are more than 16K modules, or
161 if there are more than 16K unique variables/constant in a single module.
163 This is at the cost of having 2 extra loads and one extra store per
164 function, and one less allocable register. */
165 #define MASK_MINIMAL_TOC 0x00000200
167 /* Nonzero for the 64 bit ABIs: longs and pointers are 64 bits. The
168 chip is running in "64-bit mode", in which CR0 is set in dot
169 operations based on all 64 bits of the register, bdnz works on 64-bit
170 ctr, lr is 64 bits, and so on. Requires MASK_POWERPC64. */
171 #define MASK_64BIT 0x00000400
173 /* Disable use of FPRs. */
174 #define MASK_SOFT_FLOAT 0x00000800
176 /* Enable load/store multiple, even on PowerPC */
177 #define MASK_MULTIPLE 0x00001000
179 /* Use string instructions for block moves */
180 #define MASK_STRING 0x00002000
182 /* Disable update form of load/store */
183 #define MASK_NO_UPDATE 0x00004000
185 /* Disable fused multiply/add operations */
186 #define MASK_NO_FUSED_MADD 0x00008000
188 /* Nonzero if we need to schedule the prolog and epilog. */
189 #define MASK_SCHED_PROLOG 0x00010000
191 /* Use AltiVec instructions. */
192 #define MASK_ALTIVEC 0x00020000
194 /* Return small structures in memory (as the AIX ABI requires). */
195 #define MASK_AIX_STRUCT_RET 0x00040000
197 /* Use single field mfcr instruction. */
198 #define MASK_MFCRF 0x00080000
200 /* The only remaining free bits are 0x00600000. linux64.h uses
201 0x00100000, and sysv4.h uses 0x00800000 -> 0x40000000.
202 0x80000000 is not available because target_flags is signed. */
204 #define TARGET_POWER (target_flags & MASK_POWER)
205 #define TARGET_POWER2 (target_flags & MASK_POWER2)
206 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
207 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
208 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
209 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
210 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
211 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
212 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
213 #define TARGET_64BIT (target_flags & MASK_64BIT)
214 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
215 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
216 #define TARGET_STRING (target_flags & MASK_STRING)
217 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
218 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
219 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
220 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
221 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
223 /* Define TARGET_MFCRF if the target assembler supports the optional
224 field operand for mfcr and the target processor supports the
228 #define TARGET_MFCRF (target_flags & MASK_MFCRF)
230 #define TARGET_MFCRF 0
234 #define TARGET_32BIT (! TARGET_64BIT)
235 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
236 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
237 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
239 /* Emit a dtp-relative reference to a TLS variable. */
242 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
243 rs6000_output_dwarf_dtprel (FILE, SIZE, X)
247 #define HAVE_AS_TLS 0
251 /* For libgcc2 we make sure this is a compile time constant */
252 #if defined (__64BIT__) || defined (__powerpc64__)
253 #define TARGET_POWERPC64 1
255 #define TARGET_POWERPC64 0
258 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
261 #define TARGET_XL_CALL 0
263 /* Run-time compilation parameters selecting different hardware subsets.
265 Macro to define tables used to set the flags.
266 This is a list in braces of pairs in braces,
267 each pair being { "NAME", VALUE }
268 where VALUE is the bits to set or minus the bits to clear.
269 An empty string NAME is used to identify the default VALUE. */
271 #define TARGET_SWITCHES \
272 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
273 N_("Use POWER instruction set")}, \
274 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
276 N_("Use POWER2 instruction set")}, \
277 {"no-power2", - MASK_POWER2, \
278 N_("Do not use POWER2 instruction set")}, \
279 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
281 N_("Do not use POWER instruction set")}, \
282 {"powerpc", MASK_POWERPC, \
283 N_("Use PowerPC instruction set")}, \
284 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
285 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
286 N_("Do not use PowerPC instruction set")}, \
287 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
288 N_("Use PowerPC General Purpose group optional instructions")},\
289 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
290 N_("Do not use PowerPC General Purpose group optional instructions")},\
291 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
292 N_("Use PowerPC Graphics group optional instructions")},\
293 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
294 N_("Do not use PowerPC Graphics group optional instructions")},\
295 {"powerpc64", MASK_POWERPC64, \
296 N_("Use PowerPC-64 instruction set")}, \
297 {"no-powerpc64", - MASK_POWERPC64, \
298 N_("Do not use PowerPC-64 instruction set")}, \
299 {"altivec", MASK_ALTIVEC , \
300 N_("Use AltiVec instructions")}, \
301 {"no-altivec", - MASK_ALTIVEC , \
302 N_("Do not use AltiVec instructions")}, \
303 {"new-mnemonics", MASK_NEW_MNEMONICS, \
304 N_("Use new mnemonics for PowerPC architecture")},\
305 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
306 N_("Use old mnemonics for PowerPC architecture")},\
307 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
308 | MASK_MINIMAL_TOC), \
309 N_("Put everything in the regular TOC")}, \
310 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
311 N_("Place floating point constants in TOC")}, \
312 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
313 N_("Do not place floating point constants in TOC")},\
314 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
315 N_("Place symbol+offset constants in TOC")}, \
316 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
317 N_("Do not place symbol+offset constants in TOC")},\
318 {"minimal-toc", MASK_MINIMAL_TOC, \
319 "Use only one TOC entry per procedure"}, \
320 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
322 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
323 N_("Place variable addresses in the regular TOC")},\
324 {"hard-float", - MASK_SOFT_FLOAT, \
325 N_("Use hardware floating point")}, \
326 {"soft-float", MASK_SOFT_FLOAT, \
327 N_("Do not use hardware floating point")}, \
328 {"multiple", MASK_MULTIPLE, \
329 N_("Generate load/store multiple instructions")}, \
330 {"no-multiple", - MASK_MULTIPLE, \
331 N_("Do not generate load/store multiple instructions")},\
332 {"string", MASK_STRING, \
333 N_("Generate string instructions for block moves")},\
334 {"no-string", - MASK_STRING, \
335 N_("Do not generate string instructions for block moves")},\
336 {"update", - MASK_NO_UPDATE, \
337 N_("Generate load/store with update instructions")},\
338 {"no-update", MASK_NO_UPDATE, \
339 N_("Do not generate load/store with update instructions")},\
340 {"fused-madd", - MASK_NO_FUSED_MADD, \
341 N_("Generate fused multiply/add instructions")},\
342 {"no-fused-madd", MASK_NO_FUSED_MADD, \
343 N_("Do not generate fused multiply/add instructions")},\
344 {"sched-prolog", MASK_SCHED_PROLOG, \
346 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
347 N_("Do not schedule the start and end of the procedure")},\
348 {"sched-epilog", MASK_SCHED_PROLOG, \
350 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
352 {"aix-struct-return", MASK_AIX_STRUCT_RET, \
353 N_("Return all structures in memory (AIX default)")},\
354 {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \
355 N_("Return small structures in registers (SVR4 default)")},\
356 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \
358 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \
360 {"mfcrf", MASK_MFCRF, \
361 N_("Generate single field mfcr instruction")}, \
362 {"no-mfcrf", - MASK_MFCRF, \
363 N_("Do not generate single field mfcr instruction")},\
365 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
368 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
370 /* This is meant to be redefined in the host dependent files */
371 #define SUBTARGET_SWITCHES
373 /* Processor type. Order must match cpu attribute in MD file. */
397 extern enum processor_type rs6000_cpu;
399 /* Recast the processor type to the cpu attribute. */
400 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
402 /* Define generic processor types based upon current deployment. */
403 #define PROCESSOR_COMMON PROCESSOR_PPC601
404 #define PROCESSOR_POWER PROCESSOR_RIOS1
405 #define PROCESSOR_POWERPC PROCESSOR_PPC604
406 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
408 /* Define the default processor. This is overridden by other tm.h files. */
409 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
410 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
412 /* Specify the dialect of assembler to use. New mnemonics is dialect one
413 and the old mnemonics are dialect zero. */
414 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
416 /* Types of costly dependences. */
417 enum rs6000_dependence_cost
419 max_dep_latency = 1000,
422 true_store_to_load_dep_costly,
423 store_to_load_dep_costly
426 /* Types of nop insertion schemes in sched target hook sched_finish. */
427 enum rs6000_nop_insertion
429 sched_finish_regroup_exact = 1000,
430 sched_finish_pad_groups,
434 /* Dispatch group termination caused by an insn. */
435 enum group_termination
441 /* This is meant to be overridden in target specific files. */
442 #define SUBTARGET_OPTIONS
444 #define TARGET_OPTIONS \
446 {"cpu=", &rs6000_select[1].string, \
447 N_("Use features of and schedule code for given CPU"), 0}, \
448 {"tune=", &rs6000_select[2].string, \
449 N_("Schedule code for given CPU"), 0}, \
450 {"debug=", &rs6000_debug_name, N_("Enable debug output"), 0}, \
451 {"traceback=", &rs6000_traceback_name, \
452 N_("Select full, part, or no traceback table"), 0}, \
453 {"abi=", &rs6000_abi_string, N_("Specify ABI to use"), 0}, \
454 {"long-double-", &rs6000_long_double_size_string, \
455 N_("Specify size of long double (64 or 128 bits)"), 0}, \
456 {"isel=", &rs6000_isel_string, \
457 N_("Specify yes/no if isel instructions should be generated"), 0}, \
458 {"spe=", &rs6000_spe_string, \
459 N_("Specify yes/no if SPE SIMD instructions should be generated"), 0},\
460 {"float-gprs=", &rs6000_float_gprs_string, \
461 N_("Specify yes/no if using floating point in the GPRs"), 0}, \
462 {"vrsave=", &rs6000_altivec_vrsave_string, \
463 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec"), 0}, \
464 {"longcall", &rs6000_longcall_switch, \
465 N_("Avoid all range limits on call instructions"), 0}, \
466 {"no-longcall", &rs6000_longcall_switch, "", 0}, \
467 {"warn-altivec-long", &rs6000_warn_altivec_long_switch, \
468 N_("Warn about deprecated 'vector long ...' AltiVec type usage"), 0}, \
469 {"no-warn-altivec-long", &rs6000_warn_altivec_long_switch, "", 0}, \
470 {"sched-costly-dep=", &rs6000_sched_costly_dep_str, \
471 N_("Determine which dependences between insns are considered costly"), 0}, \
472 {"insert-sched-nops=", &rs6000_sched_insert_nops_str, \
473 N_("Specify which post scheduling nop insertion scheme to apply"), 0}, \
474 {"align-", &rs6000_alignment_string, \
475 N_("Specify alignment of structure fields default/natural"), 0}, \
476 {"prioritize-restricted-insns=", &rs6000_sched_restricted_insns_priority_str, \
477 N_("Specify scheduling priority for dispatch slot restricted insns"), 0}, \
481 /* Support for a compile-time default CPU, et cetera. The rules are:
482 --with-cpu is ignored if -mcpu is specified.
483 --with-tune is ignored if -mtune is specified.
484 --with-float is ignored if -mhard-float or -msoft-float are
486 #define OPTION_DEFAULT_SPECS \
487 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
488 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
489 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
491 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
492 struct rs6000_cpu_select
500 extern struct rs6000_cpu_select rs6000_select[];
503 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
504 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
505 extern int rs6000_debug_stack; /* debug stack applications */
506 extern int rs6000_debug_arg; /* debug argument handling */
508 #define TARGET_DEBUG_STACK rs6000_debug_stack
509 #define TARGET_DEBUG_ARG rs6000_debug_arg
511 extern const char *rs6000_traceback_name; /* Type of traceback table. */
513 /* These are separate from target_flags because we've run out of bits
515 extern const char *rs6000_long_double_size_string;
516 extern int rs6000_long_double_type_size;
517 extern int rs6000_altivec_abi;
518 extern int rs6000_spe_abi;
519 extern int rs6000_isel;
520 extern int rs6000_spe;
521 extern int rs6000_float_gprs;
522 extern const char *rs6000_float_gprs_string;
523 extern const char *rs6000_isel_string;
524 extern const char *rs6000_spe_string;
525 extern const char *rs6000_altivec_vrsave_string;
526 extern int rs6000_altivec_vrsave;
527 extern const char *rs6000_longcall_switch;
528 extern int rs6000_default_long_calls;
529 extern const char* rs6000_alignment_string;
530 extern int rs6000_alignment_flags;
531 extern const char *rs6000_sched_restricted_insns_priority_str;
532 extern int rs6000_sched_restricted_insns_priority;
533 extern const char *rs6000_sched_costly_dep_str;
534 extern enum rs6000_dependence_cost rs6000_sched_costly_dep;
535 extern const char *rs6000_sched_insert_nops_str;
536 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
538 extern int rs6000_warn_altivec_long;
539 extern const char *rs6000_warn_altivec_long_switch;
541 /* Alignment options for fields in structures for sub-targets following
543 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
544 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
546 Override the macro definitions when compiling libobjc to avoid undefined
547 reference to rs6000_alignment_flags due to library's use of GCC alignment
548 macros which use the macros below. */
550 #ifndef IN_TARGET_LIBS
551 #define MASK_ALIGN_POWER 0x00000000
552 #define MASK_ALIGN_NATURAL 0x00000001
553 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
555 #define TARGET_ALIGN_NATURAL 0
558 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
559 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
560 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
562 #define TARGET_SPE_ABI 0
564 #define TARGET_E500 0
565 #define TARGET_ISEL 0
566 #define TARGET_FPRS 1
568 /* Sometimes certain combinations of command options do not make sense
569 on a particular target machine. You can define a macro
570 `OVERRIDE_OPTIONS' to take account of this. This macro, if
571 defined, is executed once just after all the command options have
574 Do not use this macro to turn on various extra optimizations for
575 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
577 On the RS/6000 this is used to define the target cpu type. */
579 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
581 /* Define this to change the optimizations performed by default. */
582 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
584 /* Show we can debug even without a frame pointer. */
585 #define CAN_DEBUG_WITHOUT_FP
588 #define REGISTER_TARGET_PRAGMAS() do { \
589 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
592 /* Target #defines. */
593 #define TARGET_CPU_CPP_BUILTINS() \
594 rs6000_cpu_cpp_builtins (pfile)
596 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
597 we're compiling for. Some configurations may need to override it. */
598 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
601 if (BYTES_BIG_ENDIAN) \
603 builtin_define ("__BIG_ENDIAN__"); \
604 builtin_define ("_BIG_ENDIAN"); \
605 builtin_assert ("machine=bigendian"); \
609 builtin_define ("__LITTLE_ENDIAN__"); \
610 builtin_define ("_LITTLE_ENDIAN"); \
611 builtin_assert ("machine=littleendian"); \
616 /* Target machine storage layout. */
618 /* Define this macro if it is advisable to hold scalars in registers
619 in a wider mode than that declared by the program. In such cases,
620 the value is constrained to be within the bounds of the declared
621 type, but kept valid in the wider mode. The signedness of the
622 extension may differ from that of the type. */
624 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
625 if (GET_MODE_CLASS (MODE) == MODE_INT \
626 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
627 (MODE) = TARGET_32BIT ? SImode : DImode;
629 /* Define this if most significant bit is lowest numbered
630 in instructions that operate on numbered bit-fields. */
631 /* That is true on RS/6000. */
632 #define BITS_BIG_ENDIAN 1
634 /* Define this if most significant byte of a word is the lowest numbered. */
635 /* That is true on RS/6000. */
636 #define BYTES_BIG_ENDIAN 1
638 /* Define this if most significant word of a multiword number is lowest
641 For RS/6000 we can decide arbitrarily since there are no machine
642 instructions for them. Might as well be consistent with bits and bytes. */
643 #define WORDS_BIG_ENDIAN 1
645 #define MAX_BITS_PER_WORD 64
647 /* Width of a word, in units (bytes). */
648 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
650 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
652 #define MIN_UNITS_PER_WORD 4
654 #define UNITS_PER_FP_WORD 8
655 #define UNITS_PER_ALTIVEC_WORD 16
656 #define UNITS_PER_SPE_WORD 8
658 /* Type used for ptrdiff_t, as a string used in a declaration. */
659 #define PTRDIFF_TYPE "int"
661 /* Type used for size_t, as a string used in a declaration. */
662 #define SIZE_TYPE "long unsigned int"
664 /* Type used for wchar_t, as a string used in a declaration. */
665 #define WCHAR_TYPE "short unsigned int"
667 /* Width of wchar_t in bits. */
668 #define WCHAR_TYPE_SIZE 16
670 /* A C expression for the size in bits of the type `short' on the
671 target machine. If you don't define this, the default is half a
672 word. (If this would be less than one storage unit, it is
673 rounded up to one unit.) */
674 #define SHORT_TYPE_SIZE 16
676 /* A C expression for the size in bits of the type `int' on the
677 target machine. If you don't define this, the default is one
679 #define INT_TYPE_SIZE 32
681 /* A C expression for the size in bits of the type `long' on the
682 target machine. If you don't define this, the default is one
684 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
686 /* A C expression for the size in bits of the type `long long' on the
687 target machine. If you don't define this, the default is two
689 #define LONG_LONG_TYPE_SIZE 64
691 /* A C expression for the size in bits of the type `float' on the
692 target machine. If you don't define this, the default is one
694 #define FLOAT_TYPE_SIZE 32
696 /* A C expression for the size in bits of the type `double' on the
697 target machine. If you don't define this, the default is two
699 #define DOUBLE_TYPE_SIZE 64
701 /* A C expression for the size in bits of the type `long double' on
702 the target machine. If you don't define this, the default is two
704 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
706 /* Define this to set long double type size to use in libgcc2.c, which can
707 not depend on target_flags. */
708 #ifdef __LONG_DOUBLE_128__
709 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
711 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
714 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
715 #define WIDEST_HARDWARE_FP_SIZE 64
717 /* Width in bits of a pointer.
718 See also the macro `Pmode' defined below. */
719 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
721 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
722 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
724 /* Boundary (in *bits*) on which stack pointer should be aligned. */
725 #define STACK_BOUNDARY \
726 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
728 /* Allocation boundary (in *bits*) for the code of a function. */
729 #define FUNCTION_BOUNDARY 32
731 /* No data type wants to be aligned rounder than this. */
732 #define BIGGEST_ALIGNMENT 128
734 /* A C expression to compute the alignment for a variables in the
735 local store. TYPE is the data type, and ALIGN is the alignment
736 that the object would ordinarily have. */
737 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
738 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
739 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
741 /* Alignment of field after `int : 0' in a structure. */
742 #define EMPTY_FIELD_BOUNDARY 32
744 /* Every structure's size must be a multiple of this. */
745 #define STRUCTURE_SIZE_BOUNDARY 8
747 /* Return 1 if a structure or array containing FIELD should be
748 accessed using `BLKMODE'.
750 For the SPE, simd types are V2SI, and gcc can be tempted to put the
751 entire thing in a DI and use subregs to access the internals.
752 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
753 back-end. Because a single GPR can hold a V2SI, but not a DI, the
754 best thing to do is set structs to BLKmode and avoid Severe Tire
756 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
757 (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE)
759 /* A bit-field declared as `int' forces `int' alignment for the struct. */
760 #define PCC_BITFIELD_TYPE_MATTERS 1
762 /* Make strings word-aligned so strcpy from constants will be faster.
763 Make vector constants quadword aligned. */
764 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
765 (TREE_CODE (EXP) == STRING_CST \
766 && (ALIGN) < BITS_PER_WORD \
770 /* Make arrays of chars word-aligned for the same reasons.
771 Align vectors to 128 bits. */
772 #define DATA_ALIGNMENT(TYPE, ALIGN) \
773 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
774 : TREE_CODE (TYPE) == ARRAY_TYPE \
775 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
776 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
778 /* Nonzero if move instructions will actually fail to work
779 when given unaligned data. */
780 #define STRICT_ALIGNMENT 0
782 /* Define this macro to be the value 1 if unaligned accesses have a cost
783 many times greater than aligned accesses, for example if they are
784 emulated in a trap handler. */
785 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
787 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
788 || (MODE) == DImode) \
791 /* Standard register usage. */
793 /* Number of actual hardware registers.
794 The hardware registers are assigned numbers for the compiler
795 from 0 to just below FIRST_PSEUDO_REGISTER.
796 All registers that the compiler knows about must be given numbers,
797 even those that are not normally considered general registers.
799 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
800 an MQ register, a count register, a link register, and 8 condition
801 register fields, which we view here as separate registers. AltiVec
802 adds 32 vector registers and a VRsave register.
804 In addition, the difference between the frame and argument pointers is
805 a function of the number of registers saved, so we need to have a
806 register for AP that will later be eliminated in favor of SP or FP.
807 This is a normal register, but it is fixed.
809 We also create a pseudo register for float/int conversions, that will
810 really represent the memory location used. It is represented here as
811 a register, in order to work around problems in allocating stack storage
812 in inline functions. */
814 #define FIRST_PSEUDO_REGISTER 113
816 /* This must be included for pre gcc 3.0 glibc compatibility. */
817 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
819 /* Add 32 dwarf columns for synthetic SPE registers. */
820 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32)
822 /* The SPE has an additional 32 synthetic registers, with DWARF debug
823 info numbering for these registers starting at 1200. While eh_frame
824 register numbering need not be the same as the debug info numbering,
825 we choose to number these regs for eh_frame at 1200 too. This allows
826 future versions of the rs6000 backend to add hard registers and
827 continue to use the gcc hard register numbering for eh_frame. If the
828 extra SPE registers in eh_frame were numbered starting from the
829 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
830 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
831 avoid invalidating older SPE eh_frame info.
833 We must map them here to avoid huge unwinder tables mostly consisting
835 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
836 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER) : (r))
838 /* Use gcc hard register numbering for eh_frame. */
839 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
841 /* 1 for registers that have pervasive standard uses
842 and are not available for the register allocator.
844 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
845 as a local register; for all other OS's r2 is the TOC pointer.
847 cr5 is not supposed to be used.
849 On System V implementations, r13 is fixed and not available for use. */
851 #define FIXED_REGISTERS \
852 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
853 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
854 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
855 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
856 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
857 /* AltiVec registers. */ \
858 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
859 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
864 /* 1 for registers not available across function calls.
865 These must include the FIXED_REGISTERS and also any
866 registers that can be used without being saved.
867 The latter must include the registers where values are returned
868 and the register where structure-value addresses are passed.
869 Aside from that, you can include as many other registers as you like. */
871 #define CALL_USED_REGISTERS \
872 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
873 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
874 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
875 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
876 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
877 /* AltiVec registers. */ \
878 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
879 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
884 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
885 the entire set of `FIXED_REGISTERS' be included.
886 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
887 This macro is optional. If not specified, it defaults to the value
888 of `CALL_USED_REGISTERS'. */
890 #define CALL_REALLY_USED_REGISTERS \
891 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
892 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
893 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
894 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
895 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
896 /* AltiVec registers. */ \
897 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
898 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
909 #define MAX_CR_REGNO 75
911 #define FIRST_ALTIVEC_REGNO 77
912 #define LAST_ALTIVEC_REGNO 108
913 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
914 #define VRSAVE_REGNO 109
915 #define VSCR_REGNO 110
916 #define SPE_ACC_REGNO 111
917 #define SPEFSCR_REGNO 112
919 /* List the order in which to allocate registers. Each register must be
920 listed once, even those in FIXED_REGISTERS.
922 We allocate in the following order:
923 fp0 (not saved or used for anything)
924 fp13 - fp2 (not saved; incoming fp arg registers)
925 fp1 (not saved; return value)
926 fp31 - fp14 (saved; order given to save least number)
927 cr7, cr6 (not saved or special)
928 cr1 (not saved, but used for FP operations)
929 cr0 (not saved, but used for arithmetic operations)
930 cr4, cr3, cr2 (saved)
931 r0 (not saved; cannot be base reg)
932 r9 (not saved; best for TImode)
933 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
934 r3 (not saved; return value register)
935 r31 - r13 (saved; order given to save least number)
936 r12 (not saved; if used for DImode or DFmode would use r13)
937 mq (not saved; best to use it if we can)
938 ctr (not saved; when we have the choice ctr is better)
940 cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
941 spe_acc, spefscr (fixed)
944 v0 - v1 (not saved or used for anything)
945 v13 - v3 (not saved; incoming vector arg registers)
946 v2 (not saved; incoming vector arg reg; return value)
947 v19 - v14 (not saved or used for anything)
948 v31 - v20 (saved; order given to save least number)
952 #define MAYBE_R2_AVAILABLE
953 #define MAYBE_R2_FIXED 2,
955 #define MAYBE_R2_AVAILABLE 2,
956 #define MAYBE_R2_FIXED
959 #define REG_ALLOC_ORDER \
961 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
963 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
964 50, 49, 48, 47, 46, \
965 75, 74, 69, 68, 72, 71, 70, \
966 0, MAYBE_R2_AVAILABLE \
967 9, 11, 10, 8, 7, 6, 5, 4, \
969 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
970 18, 17, 16, 15, 14, 13, 12, \
972 73, 1, MAYBE_R2_FIXED 67, 76, \
973 /* AltiVec registers. */ \
975 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
977 96, 95, 94, 93, 92, 91, \
978 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
983 /* True if register is floating-point. */
984 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
986 /* True if register is a condition register. */
987 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
989 /* True if register is a condition register, but not cr0. */
990 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
992 /* True if register is an integer register. */
993 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
995 /* SPE SIMD registers are just the GPRs. */
996 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
998 /* True if register is the XER register. */
999 #define XER_REGNO_P(N) ((N) == XER_REGNO)
1001 /* True if register is an AltiVec register. */
1002 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1004 /* Return number of consecutive hard regs needed starting at reg REGNO
1005 to hold something of mode MODE. */
1007 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE))
1009 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1010 ((TARGET_32BIT && TARGET_POWERPC64 \
1011 && (MODE == DImode || MODE == DFmode) \
1012 && INT_REGNO_P (REGNO)) ? 1 : 0)
1014 #define ALTIVEC_VECTOR_MODE(MODE) \
1015 ((MODE) == V16QImode \
1016 || (MODE) == V8HImode \
1017 || (MODE) == V4SFmode \
1018 || (MODE) == V4SImode)
1020 #define SPE_VECTOR_MODE(MODE) \
1021 ((MODE) == V4HImode \
1022 || (MODE) == V2SFmode \
1023 || (MODE) == V1DImode \
1024 || (MODE) == V2SImode)
1026 /* Define this macro to be nonzero if the port is prepared to handle
1027 insns involving vector mode MODE. At the very least, it must have
1028 move patterns for this mode. */
1030 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1031 ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
1032 || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE)))
1034 /* Value is TRUE if hard register REGNO can hold a value of
1035 machine-mode MODE. */
1036 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1037 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
1039 /* Value is 1 if it is a good idea to tie two pseudo registers
1040 when one has mode MODE1 and one has mode MODE2.
1041 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1042 for any hard reg, then this must be 0 for correct output. */
1043 #define MODES_TIEABLE_P(MODE1, MODE2) \
1044 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
1045 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
1046 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
1047 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
1048 : GET_MODE_CLASS (MODE1) == MODE_CC \
1049 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1050 : GET_MODE_CLASS (MODE2) == MODE_CC \
1051 ? GET_MODE_CLASS (MODE1) == MODE_CC \
1052 : SPE_VECTOR_MODE (MODE1) \
1053 ? SPE_VECTOR_MODE (MODE2) \
1054 : SPE_VECTOR_MODE (MODE2) \
1055 ? SPE_VECTOR_MODE (MODE1) \
1056 : ALTIVEC_VECTOR_MODE (MODE1) \
1057 ? ALTIVEC_VECTOR_MODE (MODE2) \
1058 : ALTIVEC_VECTOR_MODE (MODE2) \
1059 ? ALTIVEC_VECTOR_MODE (MODE1) \
1062 /* Post-reload, we can't use any new AltiVec registers, as we already
1063 emitted the vrsave mask. */
1065 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1066 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
1068 /* A C expression returning the cost of moving data from a register of class
1069 CLASS1 to one of CLASS2. */
1071 #define REGISTER_MOVE_COST rs6000_register_move_cost
1073 /* A C expressions returning the cost of moving data of MODE from a register to
1076 #define MEMORY_MOVE_COST rs6000_memory_move_cost
1078 /* Specify the cost of a branch insn; roughly the number of extra insns that
1079 should be added to avoid a branch.
1081 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1082 unscheduled conditional branch. */
1084 #define BRANCH_COST 3
1086 /* Override BRANCH_COST heuristic which empirically produces worse
1087 performance for fold_range_test(). */
1089 #define RANGE_TEST_NON_SHORT_CIRCUIT 0
1091 /* A fixed register used at prologue and epilogue generation to fix
1092 addressing modes. The SPE needs heavy addressing fixes at the last
1093 minute, and it's best to save a register for it.
1095 AltiVec also needs fixes, but we've gotten around using r11, which
1096 is actually wrong because when use_backchain_to_restore_sp is true,
1097 we end up clobbering r11.
1099 The AltiVec case needs to be fixed. Dunno if we should break ABI
1100 compatibility and reserve a register for it as well.. */
1102 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
1104 /* Define this macro to change register usage conditional on target
1107 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
1109 /* Specify the registers used for certain standard purposes.
1110 The values of these macros are register numbers. */
1112 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1113 /* #define PC_REGNUM */
1115 /* Register to use for pushing function arguments. */
1116 #define STACK_POINTER_REGNUM 1
1118 /* Base register for access to local variables of the function. */
1119 #define FRAME_POINTER_REGNUM 31
1121 /* Value should be nonzero if functions must have frame pointers.
1122 Zero means the frame pointer need not be set up (and parms
1123 may be accessed via the stack pointer) in functions that seem suitable.
1124 This is computed in `reload', in reload1.c. */
1125 #define FRAME_POINTER_REQUIRED 0
1127 /* Base register for access to arguments of the function. */
1128 #define ARG_POINTER_REGNUM 67
1130 /* Place to put static chain when calling a function that requires it. */
1131 #define STATIC_CHAIN_REGNUM 11
1133 /* Link register number. */
1134 #define LINK_REGISTER_REGNUM 65
1136 /* Count register number. */
1137 #define COUNT_REGISTER_REGNUM 66
1139 /* Define the classes of registers for register constraints in the
1140 machine description. Also define ranges of constants.
1142 One of the classes must always be named ALL_REGS and include all hard regs.
1143 If there is more than one class, another class must be named NO_REGS
1144 and contain no registers.
1146 The name GENERAL_REGS must be the name of a class (or an alias for
1147 another name such as ALL_REGS). This is the class of registers
1148 that is allowed by "g" or "r" in a register constraint.
1149 Also, registers outside this class are allocated only when
1150 instructions express preferences for them.
1152 The classes must be numbered in nondecreasing order; that is,
1153 a larger-numbered class must never be contained completely
1154 in a smaller-numbered class.
1156 For any two classes, it is very desirable that there be another
1157 class that represents their union. */
1159 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1160 and condition registers, plus three special registers, MQ, CTR, and the
1161 link register. AltiVec adds a vector register class.
1163 However, r0 is special in that it cannot be used as a base register.
1164 So make a class for registers valid as base registers.
1166 Also, cr0 is the only condition code register that can be used in
1167 arithmetic insns, so make a separate class for it. */
1195 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1197 /* Give names of register classes as strings for dump file. */
1199 #define REG_CLASS_NAMES \
1210 "NON_SPECIAL_REGS", \
1214 "LINK_OR_CTR_REGS", \
1216 "SPEC_OR_GEN_REGS", \
1224 /* Define which registers fit in which classes.
1225 This is an initializer for a vector of HARD_REG_SET
1226 of length N_REG_CLASSES. */
1228 #define REG_CLASS_CONTENTS \
1230 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1231 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1232 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1233 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1234 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1235 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1236 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1237 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1238 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1239 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1240 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1241 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1242 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1243 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1244 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1245 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1246 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1247 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1248 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1249 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1250 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1253 /* The same information, inverted:
1254 Return the class number of the smallest class containing
1255 reg number REGNO. This could be a conditional expression
1256 or could index an array. */
1258 #define REGNO_REG_CLASS(REGNO) \
1259 ((REGNO) == 0 ? GENERAL_REGS \
1260 : (REGNO) < 32 ? BASE_REGS \
1261 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1262 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1263 : (REGNO) == CR0_REGNO ? CR0_REGS \
1264 : CR_REGNO_P (REGNO) ? CR_REGS \
1265 : (REGNO) == MQ_REGNO ? MQ_REGS \
1266 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1267 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1268 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1269 : (REGNO) == XER_REGNO ? XER_REGS \
1270 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1271 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1272 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1273 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1276 /* The class value for index registers, and the one for base regs. */
1277 #define INDEX_REG_CLASS GENERAL_REGS
1278 #define BASE_REG_CLASS BASE_REGS
1280 /* Get reg_class from a letter such as appears in the machine description. */
1282 #define REG_CLASS_FROM_LETTER(C) \
1283 ((C) == 'f' ? FLOAT_REGS \
1284 : (C) == 'b' ? BASE_REGS \
1285 : (C) == 'h' ? SPECIAL_REGS \
1286 : (C) == 'q' ? MQ_REGS \
1287 : (C) == 'c' ? CTR_REGS \
1288 : (C) == 'l' ? LINK_REGS \
1289 : (C) == 'v' ? ALTIVEC_REGS \
1290 : (C) == 'x' ? CR0_REGS \
1291 : (C) == 'y' ? CR_REGS \
1292 : (C) == 'z' ? XER_REGS \
1295 /* The letters I, J, K, L, M, N, and P in a register constraint string
1296 can be used to stand for particular ranges of immediate operands.
1297 This macro defines what the ranges are.
1298 C is the letter, and VALUE is a constant value.
1299 Return 1 if VALUE is in the range specified by C.
1301 `I' is a signed 16-bit constant
1302 `J' is a constant with only the high-order 16 bits nonzero
1303 `K' is a constant with only the low-order 16 bits nonzero
1304 `L' is a signed 16-bit constant shifted left 16 bits
1305 `M' is a constant that is greater than 31
1306 `N' is a positive constant that is an exact power of two
1307 `O' is the constant zero
1308 `P' is a constant whose negation is a signed 16-bit constant */
1310 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1311 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1312 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1313 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1314 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1315 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1316 : (C) == 'M' ? (VALUE) > 31 \
1317 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1318 : (C) == 'O' ? (VALUE) == 0 \
1319 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1322 /* Similar, but for floating constants, and defining letters G and H.
1323 Here VALUE is the CONST_DOUBLE rtx itself.
1325 We flag for special constants when we can copy the constant into
1326 a general register in two insns for DF/DI and one insn for SF.
1328 'H' is used for DI/DF constants that take 3 insns. */
1330 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1331 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1332 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1333 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1336 /* Optional extra constraints for this machine.
1338 'Q' means that is a memory operand that is just an offset from a reg.
1339 'R' is for AIX TOC entries.
1340 'S' is a constant that can be placed into a 64-bit mask operand
1341 'T' is a constant that can be placed into a 32-bit mask operand
1342 'U' is for V.4 small data references.
1343 'W' is a vector constant that can be easily generated (no mem refs).
1344 'Y' is a indexed or word-aligned displacement memory operand.
1345 't' is for AND masks that can be performed by two rldic{l,r} insns. */
1347 #define EXTRA_CONSTRAINT(OP, C) \
1348 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1349 : (C) == 'R' ? legitimate_constant_pool_address_p (OP) \
1350 : (C) == 'S' ? mask64_operand (OP, DImode) \
1351 : (C) == 'T' ? mask_operand (OP, SImode) \
1352 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1353 && small_data_operand (OP, GET_MODE (OP))) \
1354 : (C) == 't' ? (mask64_2_operand (OP, DImode) \
1355 && (fixed_regs[CR0_REGNO] \
1356 || !logical_operand (OP, DImode)) \
1357 && !mask64_operand (OP, DImode)) \
1358 : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
1359 : (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \
1362 /* Define which constraints are memory constraints. Tell reload
1363 that any memory address can be reloaded by copying the
1364 memory address into a base register if required. */
1366 #define EXTRA_MEMORY_CONSTRAINT(C, STR) \
1367 ((C) == 'Q' || (C) == 'Y')
1369 /* Given an rtx X being reloaded into a reg required to be
1370 in class CLASS, return the class of reg to actually use.
1371 In general this is just CLASS; but on some machines
1372 in some cases it is preferable to use a more restrictive class.
1374 On the RS/6000, we have to return NO_REGS when we want to reload a
1375 floating-point CONST_DOUBLE to force it to be copied to memory.
1377 We also don't want to reload integer values into floating-point
1378 registers if we can at all help it. In fact, this can
1379 cause reload to abort, if it tries to generate a reload of CTR
1380 into a FP register and discovers it doesn't have the memory location
1383 ??? Would it be a good idea to have reload do the converse, that is
1384 try to reload floating modes into FP registers if possible?
1387 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1388 (((GET_CODE (X) == CONST_DOUBLE \
1389 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1391 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1392 && (CLASS) == NON_SPECIAL_REGS) \
1396 /* Return the register class of a scratch register needed to copy IN into
1397 or out of a register in CLASS in MODE. If it can be done directly,
1398 NO_REGS is returned. */
1400 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1401 secondary_reload_class (CLASS, MODE, IN)
1403 /* If we are copying between FP or AltiVec registers and anything
1404 else, we need a memory location. */
1406 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1407 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1408 || (CLASS2) == FLOAT_REGS \
1409 || (CLASS1) == ALTIVEC_REGS \
1410 || (CLASS2) == ALTIVEC_REGS))
1412 /* Return the maximum number of consecutive registers
1413 needed to represent mode MODE in a register of class CLASS.
1415 On RS/6000, this is the size of MODE in words,
1416 except in the FP regs, where a single reg is enough for two words. */
1417 #define CLASS_MAX_NREGS(CLASS, MODE) \
1418 (((CLASS) == FLOAT_REGS) \
1419 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1420 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1423 /* Return a class of registers that cannot change FROM mode to TO mode. */
1425 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1426 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) \
1427 && GET_MODE_SIZE (FROM) >= 8 && GET_MODE_SIZE (TO) >= 8) \
1429 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1430 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
1431 : (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \
1432 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1435 /* Stack layout; function entry, exit and calling. */
1437 /* Enumeration to give which calling sequence to use. */
1440 ABI_AIX, /* IBM's AIX */
1441 ABI_V4, /* System V.4/eabi */
1442 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1445 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1447 /* Define this if pushing a word on the stack
1448 makes the stack pointer a smaller address. */
1449 #define STACK_GROWS_DOWNWARD
1451 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1452 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1454 /* Define this if the nominal address of the stack frame
1455 is at the high-address end of the local variables;
1456 that is, each additional local variable allocated
1457 goes at a more negative offset in the frame.
1459 On the RS/6000, we grow upwards, from the area after the outgoing
1461 /* #define FRAME_GROWS_DOWNWARD */
1463 /* Size of the outgoing register save area */
1464 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1465 || DEFAULT_ABI == ABI_DARWIN) \
1466 ? (TARGET_64BIT ? 64 : 32) \
1469 /* Size of the fixed area on the stack */
1470 #define RS6000_SAVE_AREA \
1471 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1472 << (TARGET_64BIT ? 1 : 0))
1474 /* MEM representing address to save the TOC register */
1475 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1476 plus_constant (stack_pointer_rtx, \
1477 (TARGET_32BIT ? 20 : 40)))
1479 /* Size of the V.4 varargs area if needed */
1480 #define RS6000_VARARGS_AREA 0
1482 /* Align an address */
1483 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1485 /* Size of V.4 varargs area in bytes */
1486 #define RS6000_VARARGS_SIZE \
1487 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1489 /* Offset within stack frame to start allocating local variables at.
1490 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1491 first local allocated. Otherwise, it is the offset to the BEGINNING
1492 of the first local allocated.
1494 On the RS/6000, the frame pointer is the same as the stack pointer,
1495 except for dynamic allocations. So we start after the fixed area and
1496 outgoing parameter area. */
1498 #define STARTING_FRAME_OFFSET \
1499 (RS6000_ALIGN (current_function_outgoing_args_size, \
1500 TARGET_ALTIVEC ? 16 : 8) \
1501 + RS6000_VARARGS_AREA \
1504 /* Offset from the stack pointer register to an item dynamically
1505 allocated on the stack, e.g., by `alloca'.
1507 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1508 length of the outgoing arguments. The default is correct for most
1509 machines. See `function.c' for details. */
1510 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1511 (RS6000_ALIGN (current_function_outgoing_args_size, \
1512 TARGET_ALTIVEC ? 16 : 8) \
1513 + (STACK_POINTER_OFFSET))
1515 /* If we generate an insn to push BYTES bytes,
1516 this says how many the stack pointer really advances by.
1517 On RS/6000, don't define this because there are no push insns. */
1518 /* #define PUSH_ROUNDING(BYTES) */
1520 /* Offset of first parameter from the argument pointer register value.
1521 On the RS/6000, we define the argument pointer to the start of the fixed
1523 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1525 /* Offset from the argument pointer register value to the top of
1526 stack. This is different from FIRST_PARM_OFFSET because of the
1527 register save area. */
1528 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1530 /* Define this if stack space is still allocated for a parameter passed
1531 in a register. The value is the number of bytes allocated to this
1533 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1535 /* Define this if the above stack space is to be considered part of the
1536 space allocated by the caller. */
1537 #define OUTGOING_REG_PARM_STACK_SPACE
1539 /* This is the difference between the logical top of stack and the actual sp.
1541 For the RS/6000, sp points past the fixed area. */
1542 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1544 /* Define this if the maximum size of all the outgoing args is to be
1545 accumulated and pushed during the prologue. The amount can be
1546 found in the variable current_function_outgoing_args_size. */
1547 #define ACCUMULATE_OUTGOING_ARGS 1
1549 /* Value is the number of bytes of arguments automatically
1550 popped when returning from a subroutine call.
1551 FUNDECL is the declaration node of the function (as a tree),
1552 FUNTYPE is the data type of the function (as a tree),
1553 or for a library call it is an identifier node for the subroutine name.
1554 SIZE is the number of bytes of arguments passed on the stack. */
1556 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1558 /* Define how to find the value returned by a function.
1559 VALTYPE is the data type of the value (as a tree).
1560 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1561 otherwise, FUNC is 0. */
1563 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1565 /* Define how to find the value returned by a library function
1566 assuming the value has mode MODE. */
1568 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1570 /* DRAFT_V4_STRUCT_RET defaults off. */
1571 #define DRAFT_V4_STRUCT_RET 0
1573 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1574 #define DEFAULT_PCC_STRUCT_RETURN 0
1576 /* Mode of stack savearea.
1577 FUNCTION is VOIDmode because calling convention maintains SP.
1578 BLOCK needs Pmode for SP.
1579 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1580 #define STACK_SAVEAREA_MODE(LEVEL) \
1581 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1582 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1584 /* Minimum and maximum general purpose registers used to hold arguments. */
1585 #define GP_ARG_MIN_REG 3
1586 #define GP_ARG_MAX_REG 10
1587 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1589 /* Minimum and maximum floating point registers used to hold arguments. */
1590 #define FP_ARG_MIN_REG 33
1591 #define FP_ARG_AIX_MAX_REG 45
1592 #define FP_ARG_V4_MAX_REG 40
1593 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1594 || DEFAULT_ABI == ABI_DARWIN) \
1595 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1596 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1598 /* Minimum and maximum AltiVec registers used to hold arguments. */
1599 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1600 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1601 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1603 /* Return registers */
1604 #define GP_ARG_RETURN GP_ARG_MIN_REG
1605 #define FP_ARG_RETURN FP_ARG_MIN_REG
1606 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1608 /* Flags for the call/call_value rtl operations set up by function_arg */
1609 #define CALL_NORMAL 0x00000000 /* no special processing */
1610 /* Bits in 0x00000001 are unused. */
1611 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1612 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1613 #define CALL_LONG 0x00000008 /* always call indirect */
1614 #define CALL_LIBCALL 0x00000010 /* libcall */
1616 /* 1 if N is a possible register number for a function value
1617 as seen by the caller.
1619 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1620 #define FUNCTION_VALUE_REGNO_P(N) \
1621 ((N) == GP_ARG_RETURN \
1622 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \
1623 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1625 /* 1 if N is a possible register number for function argument passing.
1626 On RS/6000, these are r3-r10 and fp1-fp13.
1627 On AltiVec, v2 - v13 are used for passing vectors. */
1628 #define FUNCTION_ARG_REGNO_P(N) \
1629 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1630 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1631 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1632 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1633 && TARGET_HARD_FLOAT))
1635 /* A C structure for machine-specific, per-function data.
1636 This is added to the cfun structure. */
1637 typedef struct machine_function GTY(())
1639 /* Whether a System V.4 varargs area was created. */
1641 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1642 int ra_needs_full_frame;
1643 /* Some local-dynamic symbol. */
1644 const char *some_ld_name;
1645 /* Whether the instruction chain has been scanned already. */
1646 int insn_chain_scanned_p;
1647 /* Flags if __builtin_return_address (0) was used. */
1651 /* Define a data type for recording info about an argument list
1652 during the scan of that argument list. This data type should
1653 hold all necessary information about the function itself
1654 and about the args processed so far, enough to enable macros
1655 such as FUNCTION_ARG to determine where the next arg should go.
1657 On the RS/6000, this is a structure. The first element is the number of
1658 total argument words, the second is used to store the next
1659 floating-point register number, and the third says how many more args we
1660 have prototype types for.
1662 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1663 the next available GP register, `fregno' is the next available FP
1664 register, and `words' is the number of words used on the stack.
1666 The varargs/stdarg support requires that this structure's size
1667 be a multiple of sizeof(int). */
1669 typedef struct rs6000_args
1671 int words; /* # words used for passing GP registers */
1672 int fregno; /* next available FP register */
1673 int vregno; /* next available AltiVec register */
1674 int nargs_prototype; /* # args left in the current prototype */
1675 int prototype; /* Whether a prototype was defined */
1676 int stdarg; /* Whether function is a stdarg function. */
1677 int call_cookie; /* Do special things for this call */
1678 int sysv_gregno; /* next available GP register */
1681 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1682 for a call to a function whose data type is FNTYPE.
1683 For a library call, FNTYPE is 0. */
1685 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1686 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1688 /* Similar, but when scanning the definition of a procedure. We always
1689 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1691 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1692 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1694 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1696 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1697 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1699 /* Update the data in CUM to advance over an argument
1700 of mode MODE and data type TYPE.
1701 (TYPE is null for libcalls where that information may not be available.) */
1703 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1704 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1706 /* Determine where to put an argument to a function.
1707 Value is zero to push the argument on the stack,
1708 or a hard register in which to store the argument.
1710 MODE is the argument's machine mode.
1711 TYPE is the data type of the argument (as a tree).
1712 This is null for libcalls where that information may
1714 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1715 the preceding args and about the function being called.
1716 NAMED is nonzero if this argument is a named parameter
1717 (otherwise it is an extra parameter matching an ellipsis).
1719 On RS/6000 the first eight words of non-FP are normally in registers
1720 and the rest are pushed. The first 13 FP args are in registers.
1722 If this is floating-point and no prototype is specified, we use
1723 both an FP and integer register (or possibly FP reg and stack). Library
1724 functions (when TYPE is zero) always have the proper types for args,
1725 so we can pass the FP value just in one register. emit_library_function
1726 doesn't support EXPR_LIST anyway. */
1728 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1729 function_arg (&CUM, MODE, TYPE, NAMED)
1731 /* For an arg passed partly in registers and partly in memory,
1732 this is the number of registers used.
1733 For args passed entirely in registers or entirely in memory, zero. */
1735 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1736 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1738 /* If defined, a C expression which determines whether, and in which
1739 direction, to pad out an argument with extra space. The value
1740 should be of type `enum direction': either `upward' to pad above
1741 the argument, `downward' to pad below, or `none' to inhibit
1744 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1746 /* If defined, a C expression that gives the alignment boundary, in bits,
1747 of an argument with the specified mode and type. If it is not defined,
1748 PARM_BOUNDARY is used for all arguments. */
1750 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1751 function_arg_boundary (MODE, TYPE)
1753 /* Implement `va_start' for varargs and stdarg. */
1754 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1755 rs6000_va_start (valist, nextarg)
1757 /* Implement `va_arg'. */
1758 #define EXPAND_BUILTIN_VA_ARG(valist, type) (abort (), NULL_RTX)
1760 #define PAD_VARARGS_DOWN \
1761 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1763 /* Output assembler code to FILE to increment profiler label # LABELNO
1764 for profiling a function entry. */
1766 #define FUNCTION_PROFILER(FILE, LABELNO) \
1767 output_function_profiler ((FILE), (LABELNO));
1769 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1770 the stack pointer does not matter. No definition is equivalent to
1773 On the RS/6000, this is nonzero because we can restore the stack from
1774 its backpointer, which we maintain. */
1775 #define EXIT_IGNORE_STACK 1
1777 /* Define this macro as a C expression that is nonzero for registers
1778 that are used by the epilogue or the return' pattern. The stack
1779 and frame pointer registers are already be assumed to be used as
1782 #define EPILOGUE_USES(REGNO) \
1783 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1784 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1785 || (current_function_calls_eh_return \
1790 /* TRAMPOLINE_TEMPLATE deleted */
1792 /* Length in units of the trampoline for entering a nested function. */
1794 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1796 /* Emit RTL insns to initialize the variable parts of a trampoline.
1797 FNADDR is an RTX for the address of the function's pure code.
1798 CXT is an RTX for the static chain value for the function. */
1800 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1801 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1803 /* Definitions for __builtin_return_address and __builtin_frame_address.
1804 __builtin_return_address (0) should give link register (65), enable
1806 /* This should be uncommented, so that the link register is used, but
1807 currently this would result in unmatched insns and spilling fixed
1808 registers so we'll leave it for another day. When these problems are
1809 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1811 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1813 /* Number of bytes into the frame return addresses can be found. See
1814 rs6000_stack_info in rs6000.c for more information on how the different
1815 abi's store the return address. */
1816 #define RETURN_ADDRESS_OFFSET \
1817 ((DEFAULT_ABI == ABI_AIX \
1818 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1819 (DEFAULT_ABI == ABI_V4) ? 4 : \
1820 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1822 /* The current return address is in link register (65). The return address
1823 of anything farther back is accessed normally at an offset of 8 from the
1825 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1826 (rs6000_return_addr (COUNT, FRAME))
1829 /* Definitions for register eliminations.
1831 We have two registers that can be eliminated on the RS/6000. First, the
1832 frame pointer register can often be eliminated in favor of the stack
1833 pointer register. Secondly, the argument pointer register can always be
1834 eliminated; it is replaced with either the stack or frame pointer.
1836 In addition, we use the elimination mechanism to see if r30 is needed
1837 Initially we assume that it isn't. If it is, we spill it. This is done
1838 by making it an eliminable register. We replace it with itself so that
1839 if it isn't needed, then existing uses won't be modified. */
1841 /* This is an array of structures. Each structure initializes one pair
1842 of eliminable registers. The "from" register number is given first,
1843 followed by "to". Eliminations of the same "from" register are listed
1844 in order of preference. */
1845 #define ELIMINABLE_REGS \
1846 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1847 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1848 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1849 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1851 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1852 Frame pointer elimination is automatically handled.
1854 For the RS/6000, if frame pointer elimination is being done, we would like
1855 to convert ap into fp, not sp.
1857 We need r30 if -mminimal-toc was specified, and there are constant pool
1860 #define CAN_ELIMINATE(FROM, TO) \
1861 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1862 ? ! frame_pointer_needed \
1863 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1864 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1867 /* Define the offset between two registers, one to be eliminated, and the other
1868 its replacement, at the start of a routine. */
1869 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1870 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1872 /* Addressing modes, and classification of registers for them. */
1874 #define HAVE_PRE_DECREMENT 1
1875 #define HAVE_PRE_INCREMENT 1
1877 /* Macros to check register numbers against specific register classes. */
1879 /* These assume that REGNO is a hard or pseudo reg number.
1880 They give nonzero only if REGNO is a hard reg of the suitable class
1881 or a pseudo reg currently allocated to a suitable hard reg.
1882 Since they use reg_renumber, they are safe only once reg_renumber
1883 has been allocated, which happens in local-alloc.c. */
1885 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1886 ((REGNO) < FIRST_PSEUDO_REGISTER \
1887 ? (REGNO) <= 31 || (REGNO) == 67 \
1888 : (reg_renumber[REGNO] >= 0 \
1889 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1891 #define REGNO_OK_FOR_BASE_P(REGNO) \
1892 ((REGNO) < FIRST_PSEUDO_REGISTER \
1893 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1894 : (reg_renumber[REGNO] > 0 \
1895 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1897 /* Maximum number of registers that can appear in a valid memory address. */
1899 #define MAX_REGS_PER_ADDRESS 2
1901 /* Recognize any constant value that is a valid address. */
1903 #define CONSTANT_ADDRESS_P(X) \
1904 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1905 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1906 || GET_CODE (X) == HIGH)
1908 /* Nonzero if the constant value X is a legitimate general operand.
1909 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1911 On the RS/6000, all integer constants are acceptable, most won't be valid
1912 for particular insns, though. Only easy FP constants are
1915 #define LEGITIMATE_CONSTANT_P(X) \
1916 (((GET_CODE (X) != CONST_DOUBLE \
1917 && GET_CODE (X) != CONST_VECTOR) \
1918 || GET_MODE (X) == VOIDmode \
1919 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1920 || easy_fp_constant (X, GET_MODE (X)) \
1921 || easy_vector_constant (X, GET_MODE (X))) \
1922 && !rs6000_tls_referenced_p (X))
1924 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1925 and check its validity for a certain class.
1926 We have two alternate definitions for each of them.
1927 The usual definition accepts all pseudo regs; the other rejects
1928 them unless they have been allocated suitable hard regs.
1929 The symbol REG_OK_STRICT causes the latter definition to be used.
1931 Most source files want to accept pseudo regs in the hope that
1932 they will get allocated to the class that the insn wants them to be in.
1933 Source files for reload pass need to be strict.
1934 After reload, it makes no difference, since pseudo regs have
1935 been eliminated by then. */
1937 #ifdef REG_OK_STRICT
1938 # define REG_OK_STRICT_FLAG 1
1940 # define REG_OK_STRICT_FLAG 0
1943 /* Nonzero if X is a hard reg that can be used as an index
1944 or if it is a pseudo reg in the non-strict case. */
1945 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1947 && (REGNO (X) <= 31 \
1948 || REGNO (X) == ARG_POINTER_REGNUM \
1949 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1950 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1952 /* Nonzero if X is a hard reg that can be used as a base reg
1953 or if it is a pseudo reg in the non-strict case. */
1954 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1955 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1957 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1958 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1960 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1961 that is a valid memory address for an instruction.
1962 The MODE argument is the machine mode for the MEM expression
1963 that wants to use this address.
1965 On the RS/6000, there are four valid address: a SYMBOL_REF that
1966 refers to a constant pool entry of an address (or the sum of it
1967 plus a constant), a short (16-bit signed) constant plus a register,
1968 the sum of two registers, or a register indirect, possibly with an
1969 auto-increment. For DFmode and DImode with a constant plus register,
1970 we must ensure that both words are addressable or PowerPC64 with offset
1973 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1974 32-bit DImode, TImode), indexed addressing cannot be used because
1975 adjacent memory cells are accessed by adding word-sized offsets
1976 during assembly output. */
1978 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1979 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1983 /* Try machine-dependent ways of modifying an illegitimate address
1984 to be legitimate. If we find one, return the new, valid address.
1985 This macro is used in only one place: `memory_address' in explow.c.
1987 OLDX is the address as it was before break_out_memory_refs was called.
1988 In some cases it is useful to look at this to decide what needs to be done.
1990 MODE and WIN are passed so that this macro can use
1991 GO_IF_LEGITIMATE_ADDRESS.
1993 It is always safe for this macro to do nothing. It exists to recognize
1994 opportunities to optimize the output.
1996 On RS/6000, first check for the sum of a register with a constant
1997 integer that is out of range. If so, generate code to add the
1998 constant with the low-order 16 bits masked to the register and force
1999 this result into another register (this can be done with `cau').
2000 Then generate an address of REG+(CONST&0xffff), allowing for the
2001 possibility of bit 16 being a one.
2003 Then check for the sum of a register and something not constant, try to
2004 load the other things into a register and return the sum. */
2006 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2007 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2008 if (result != NULL_RTX) \
2015 /* Try a machine-dependent way of reloading an illegitimate address
2016 operand. If we find one, push the reload and jump to WIN. This
2017 macro is used in only one place: `find_reloads_address' in reload.c.
2019 Implemented on rs6000 by rs6000_legitimize_reload_address.
2020 Note that (X) is evaluated twice; this is safe in current usage. */
2022 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2025 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2026 (int)(TYPE), (IND_LEVELS), &win); \
2031 /* Go to LABEL if ADDR (a legitimate address expression)
2032 has an effect that depends on the machine mode it is used for. */
2034 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2036 if (rs6000_mode_dependent_address (ADDR)) \
2040 /* The register number of the register used to address a table of
2041 static data addresses in memory. In some cases this register is
2042 defined by a processor's "application binary interface" (ABI).
2043 When this macro is defined, RTL is generated for this register
2044 once, as with the stack pointer and frame pointer registers. If
2045 this macro is not defined, it is up to the machine-dependent files
2046 to allocate such a register (if necessary). */
2048 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2049 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
2051 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
2053 /* Define this macro if the register defined by
2054 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2055 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2057 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2059 /* By generating position-independent code, when two different
2060 programs (A and B) share a common library (libC.a), the text of
2061 the library can be shared whether or not the library is linked at
2062 the same address for both programs. In some of these
2063 environments, position-independent code requires not only the use
2064 of different addressing modes, but also special code to enable the
2065 use of these addressing modes.
2067 The `FINALIZE_PIC' macro serves as a hook to emit these special
2068 codes once the function is being compiled into assembly code, but
2069 not before. (It is not done before, because in the case of
2070 compiling an inline function, it would lead to multiple PIC
2071 prologues being included in functions which used inline functions
2072 and were compiled to assembly language.) */
2074 /* #define FINALIZE_PIC */
2076 /* A C expression that is nonzero if X is a legitimate immediate
2077 operand on the target machine when generating position independent
2078 code. You can assume that X satisfies `CONSTANT_P', so you need
2079 not check this. You can also assume FLAG_PIC is true, so you need
2080 not check it either. You need not define this macro if all
2081 constants (including `SYMBOL_REF') can be immediate operands when
2082 generating position independent code. */
2084 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2086 /* Define this if some processing needs to be done immediately before
2087 emitting code for an insn. */
2089 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2091 /* Specify the machine mode that this machine uses
2092 for the index in the tablejump instruction. */
2093 #define CASE_VECTOR_MODE SImode
2095 /* Define as C expression which evaluates to nonzero if the tablejump
2096 instruction expects the table to contain offsets from the address of the
2098 Do not define this if the table should contain absolute addresses. */
2099 #define CASE_VECTOR_PC_RELATIVE 1
2101 /* Define this as 1 if `char' should by default be signed; else as 0. */
2102 #define DEFAULT_SIGNED_CHAR 0
2104 /* This flag, if defined, says the same insns that convert to a signed fixnum
2105 also convert validly to an unsigned one. */
2107 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2109 /* Max number of bytes we can move from memory to memory
2110 in one reasonably fast instruction. */
2111 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2112 #define MAX_MOVE_MAX 8
2114 /* Nonzero if access to memory by bytes is no faster than for words.
2115 Also nonzero if doing byte operations (specifically shifts) in registers
2117 #define SLOW_BYTE_ACCESS 1
2119 /* Define if operations between registers always perform the operation
2120 on the full register even if a narrower mode is specified. */
2121 #define WORD_REGISTER_OPERATIONS
2123 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2124 will either zero-extend or sign-extend. The value of this macro should
2125 be the code that says which one of the two operations is implicitly
2126 done, NIL if none. */
2127 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2129 /* Define if loading short immediate values into registers sign extends. */
2130 #define SHORT_IMMEDIATES_SIGN_EXTEND
2132 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2133 is done just by pretending it is already truncated. */
2134 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2136 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2137 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2138 ((VALUE) = ((MODE) == SImode ? 32 : 64))
2140 /* The CTZ patterns return -1 for input of zero. */
2141 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
2143 /* Specify the machine mode that pointers have.
2144 After generation of rtl, the compiler makes no further distinction
2145 between pointers and any other objects of this machine mode. */
2146 #define Pmode (TARGET_32BIT ? SImode : DImode)
2148 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
2149 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2151 /* Mode of a function address in a call instruction (for indexing purposes).
2152 Doesn't matter on RS/6000. */
2153 #define FUNCTION_MODE SImode
2155 /* Define this if addresses of constant functions
2156 shouldn't be put through pseudo regs where they can be cse'd.
2157 Desirable on machines where ordinary constants are expensive
2158 but a CALL with constant address is cheap. */
2159 #define NO_FUNCTION_CSE
2161 /* Define this to be nonzero if shift instructions ignore all but the low-order
2164 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2165 have been dropped from the PowerPC architecture. */
2167 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2169 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2170 should be adjusted to reflect any required changes. This macro is used when
2171 there is some systematic length adjustment required that would be difficult
2172 to express in the length attribute. */
2174 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2176 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2177 COMPARE, return the mode to be used for the comparison. For
2178 floating-point, CCFPmode should be used. CCUNSmode should be used
2179 for unsigned comparisons. CCEQmode should be used when we are
2180 doing an inequality comparison on the result of a
2181 comparison. CCmode should be used in all other cases. */
2183 #define SELECT_CC_MODE(OP,X,Y) \
2184 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2185 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2186 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2187 ? CCEQmode : CCmode))
2189 /* Can the condition code MODE be safely reversed? This is safe in
2190 all cases on this port, because at present it doesn't use the
2191 trapping FP comparisons (fcmpo). */
2192 #define REVERSIBLE_CC_MODE(MODE) 1
2194 /* Given a condition code and a mode, return the inverse condition. */
2195 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2197 /* Define the information needed to generate branch and scc insns. This is
2198 stored from the compare operation. */
2200 extern GTY(()) rtx rs6000_compare_op0;
2201 extern GTY(()) rtx rs6000_compare_op1;
2202 extern int rs6000_compare_fp_p;
2204 /* Control the assembler format that we output. */
2206 /* A C string constant describing how to begin a comment in the target
2207 assembler language. The compiler assumes that the comment will end at
2208 the end of the line. */
2209 #define ASM_COMMENT_START " #"
2211 /* Flag to say the TOC is initialized */
2212 extern int toc_initialized;
2214 /* Macro to output a special constant pool entry. Go to WIN if we output
2215 it. Otherwise, it is written the usual way.
2217 On the RS/6000, toc entries are handled this way. */
2219 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2220 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2222 output_toc (FILE, X, LABELNO, MODE); \
2227 #ifdef HAVE_GAS_WEAK
2228 #define RS6000_WEAK 1
2230 #define RS6000_WEAK 0
2234 /* Used in lieu of ASM_WEAKEN_LABEL. */
2235 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2238 fputs ("\t.weak\t", (FILE)); \
2239 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2240 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2241 && DEFAULT_ABI == ABI_AIX) \
2244 fputs ("[DS]", (FILE)); \
2245 fputs ("\n\t.weak\t.", (FILE)); \
2246 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2248 fputc ('\n', (FILE)); \
2251 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2252 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2253 && DEFAULT_ABI == ABI_AIX) \
2255 fputs ("\t.set\t.", (FILE)); \
2256 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2257 fputs (",.", (FILE)); \
2258 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2259 fputc ('\n', (FILE)); \
2266 /* This implements the `alias' attribute. */
2267 #undef ASM_OUTPUT_DEF_FROM_DECLS
2268 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2271 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2272 const char *name = IDENTIFIER_POINTER (TARGET); \
2273 if (TREE_CODE (DECL) == FUNCTION_DECL \
2274 && DEFAULT_ABI == ABI_AIX) \
2276 if (TREE_PUBLIC (DECL)) \
2278 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2280 fputs ("\t.globl\t.", FILE); \
2281 RS6000_OUTPUT_BASENAME (FILE, alias); \
2282 putc ('\n', FILE); \
2285 else if (TARGET_XCOFF) \
2287 fputs ("\t.lglobl\t.", FILE); \
2288 RS6000_OUTPUT_BASENAME (FILE, alias); \
2289 putc ('\n', FILE); \
2291 fputs ("\t.set\t.", FILE); \
2292 RS6000_OUTPUT_BASENAME (FILE, alias); \
2293 fputs (",.", FILE); \
2294 RS6000_OUTPUT_BASENAME (FILE, name); \
2295 fputc ('\n', FILE); \
2297 ASM_OUTPUT_DEF (FILE, alias, name); \
2301 #define TARGET_ASM_FILE_START rs6000_file_start
2303 /* Output to assembler file text saying following lines
2304 may contain character constants, extra white space, comments, etc. */
2306 #define ASM_APP_ON ""
2308 /* Output to assembler file text saying following lines
2309 no longer contain unusual constructs. */
2311 #define ASM_APP_OFF ""
2313 /* How to refer to registers in assembler output.
2314 This sequence is indexed by compiler's hard-register-number (see above). */
2316 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2318 #define REGISTER_NAMES \
2320 &rs6000_reg_names[ 0][0], /* r0 */ \
2321 &rs6000_reg_names[ 1][0], /* r1 */ \
2322 &rs6000_reg_names[ 2][0], /* r2 */ \
2323 &rs6000_reg_names[ 3][0], /* r3 */ \
2324 &rs6000_reg_names[ 4][0], /* r4 */ \
2325 &rs6000_reg_names[ 5][0], /* r5 */ \
2326 &rs6000_reg_names[ 6][0], /* r6 */ \
2327 &rs6000_reg_names[ 7][0], /* r7 */ \
2328 &rs6000_reg_names[ 8][0], /* r8 */ \
2329 &rs6000_reg_names[ 9][0], /* r9 */ \
2330 &rs6000_reg_names[10][0], /* r10 */ \
2331 &rs6000_reg_names[11][0], /* r11 */ \
2332 &rs6000_reg_names[12][0], /* r12 */ \
2333 &rs6000_reg_names[13][0], /* r13 */ \
2334 &rs6000_reg_names[14][0], /* r14 */ \
2335 &rs6000_reg_names[15][0], /* r15 */ \
2336 &rs6000_reg_names[16][0], /* r16 */ \
2337 &rs6000_reg_names[17][0], /* r17 */ \
2338 &rs6000_reg_names[18][0], /* r18 */ \
2339 &rs6000_reg_names[19][0], /* r19 */ \
2340 &rs6000_reg_names[20][0], /* r20 */ \
2341 &rs6000_reg_names[21][0], /* r21 */ \
2342 &rs6000_reg_names[22][0], /* r22 */ \
2343 &rs6000_reg_names[23][0], /* r23 */ \
2344 &rs6000_reg_names[24][0], /* r24 */ \
2345 &rs6000_reg_names[25][0], /* r25 */ \
2346 &rs6000_reg_names[26][0], /* r26 */ \
2347 &rs6000_reg_names[27][0], /* r27 */ \
2348 &rs6000_reg_names[28][0], /* r28 */ \
2349 &rs6000_reg_names[29][0], /* r29 */ \
2350 &rs6000_reg_names[30][0], /* r30 */ \
2351 &rs6000_reg_names[31][0], /* r31 */ \
2353 &rs6000_reg_names[32][0], /* fr0 */ \
2354 &rs6000_reg_names[33][0], /* fr1 */ \
2355 &rs6000_reg_names[34][0], /* fr2 */ \
2356 &rs6000_reg_names[35][0], /* fr3 */ \
2357 &rs6000_reg_names[36][0], /* fr4 */ \
2358 &rs6000_reg_names[37][0], /* fr5 */ \
2359 &rs6000_reg_names[38][0], /* fr6 */ \
2360 &rs6000_reg_names[39][0], /* fr7 */ \
2361 &rs6000_reg_names[40][0], /* fr8 */ \
2362 &rs6000_reg_names[41][0], /* fr9 */ \
2363 &rs6000_reg_names[42][0], /* fr10 */ \
2364 &rs6000_reg_names[43][0], /* fr11 */ \
2365 &rs6000_reg_names[44][0], /* fr12 */ \
2366 &rs6000_reg_names[45][0], /* fr13 */ \
2367 &rs6000_reg_names[46][0], /* fr14 */ \
2368 &rs6000_reg_names[47][0], /* fr15 */ \
2369 &rs6000_reg_names[48][0], /* fr16 */ \
2370 &rs6000_reg_names[49][0], /* fr17 */ \
2371 &rs6000_reg_names[50][0], /* fr18 */ \
2372 &rs6000_reg_names[51][0], /* fr19 */ \
2373 &rs6000_reg_names[52][0], /* fr20 */ \
2374 &rs6000_reg_names[53][0], /* fr21 */ \
2375 &rs6000_reg_names[54][0], /* fr22 */ \
2376 &rs6000_reg_names[55][0], /* fr23 */ \
2377 &rs6000_reg_names[56][0], /* fr24 */ \
2378 &rs6000_reg_names[57][0], /* fr25 */ \
2379 &rs6000_reg_names[58][0], /* fr26 */ \
2380 &rs6000_reg_names[59][0], /* fr27 */ \
2381 &rs6000_reg_names[60][0], /* fr28 */ \
2382 &rs6000_reg_names[61][0], /* fr29 */ \
2383 &rs6000_reg_names[62][0], /* fr30 */ \
2384 &rs6000_reg_names[63][0], /* fr31 */ \
2386 &rs6000_reg_names[64][0], /* mq */ \
2387 &rs6000_reg_names[65][0], /* lr */ \
2388 &rs6000_reg_names[66][0], /* ctr */ \
2389 &rs6000_reg_names[67][0], /* ap */ \
2391 &rs6000_reg_names[68][0], /* cr0 */ \
2392 &rs6000_reg_names[69][0], /* cr1 */ \
2393 &rs6000_reg_names[70][0], /* cr2 */ \
2394 &rs6000_reg_names[71][0], /* cr3 */ \
2395 &rs6000_reg_names[72][0], /* cr4 */ \
2396 &rs6000_reg_names[73][0], /* cr5 */ \
2397 &rs6000_reg_names[74][0], /* cr6 */ \
2398 &rs6000_reg_names[75][0], /* cr7 */ \
2400 &rs6000_reg_names[76][0], /* xer */ \
2402 &rs6000_reg_names[77][0], /* v0 */ \
2403 &rs6000_reg_names[78][0], /* v1 */ \
2404 &rs6000_reg_names[79][0], /* v2 */ \
2405 &rs6000_reg_names[80][0], /* v3 */ \
2406 &rs6000_reg_names[81][0], /* v4 */ \
2407 &rs6000_reg_names[82][0], /* v5 */ \
2408 &rs6000_reg_names[83][0], /* v6 */ \
2409 &rs6000_reg_names[84][0], /* v7 */ \
2410 &rs6000_reg_names[85][0], /* v8 */ \
2411 &rs6000_reg_names[86][0], /* v9 */ \
2412 &rs6000_reg_names[87][0], /* v10 */ \
2413 &rs6000_reg_names[88][0], /* v11 */ \
2414 &rs6000_reg_names[89][0], /* v12 */ \
2415 &rs6000_reg_names[90][0], /* v13 */ \
2416 &rs6000_reg_names[91][0], /* v14 */ \
2417 &rs6000_reg_names[92][0], /* v15 */ \
2418 &rs6000_reg_names[93][0], /* v16 */ \
2419 &rs6000_reg_names[94][0], /* v17 */ \
2420 &rs6000_reg_names[95][0], /* v18 */ \
2421 &rs6000_reg_names[96][0], /* v19 */ \
2422 &rs6000_reg_names[97][0], /* v20 */ \
2423 &rs6000_reg_names[98][0], /* v21 */ \
2424 &rs6000_reg_names[99][0], /* v22 */ \
2425 &rs6000_reg_names[100][0], /* v23 */ \
2426 &rs6000_reg_names[101][0], /* v24 */ \
2427 &rs6000_reg_names[102][0], /* v25 */ \
2428 &rs6000_reg_names[103][0], /* v26 */ \
2429 &rs6000_reg_names[104][0], /* v27 */ \
2430 &rs6000_reg_names[105][0], /* v28 */ \
2431 &rs6000_reg_names[106][0], /* v29 */ \
2432 &rs6000_reg_names[107][0], /* v30 */ \
2433 &rs6000_reg_names[108][0], /* v31 */ \
2434 &rs6000_reg_names[109][0], /* vrsave */ \
2435 &rs6000_reg_names[110][0], /* vscr */ \
2436 &rs6000_reg_names[111][0], /* spe_acc */ \
2437 &rs6000_reg_names[112][0], /* spefscr */ \
2440 /* Table of additional register names to use in user input. */
2442 #define ADDITIONAL_REGISTER_NAMES \
2443 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2444 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2445 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2446 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2447 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2448 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2449 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2450 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2451 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2452 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2453 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2454 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2455 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2456 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2457 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2458 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2459 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2460 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2461 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2462 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2463 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2464 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2465 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2466 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2467 {"vrsave", 109}, {"vscr", 110}, \
2468 {"spe_acc", 111}, {"spefscr", 112}, \
2469 /* no additional names for: mq, lr, ctr, ap */ \
2470 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2471 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2472 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2474 /* Text to write out after a CALL that may be replaced by glue code by
2475 the loader. This depends on the AIX version. */
2476 #define RS6000_CALL_GLUE "cror 31,31,31"
2478 /* This is how to output an element of a case-vector that is relative. */
2480 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2481 do { char buf[100]; \
2482 fputs ("\t.long ", FILE); \
2483 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2484 assemble_name (FILE, buf); \
2486 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2487 assemble_name (FILE, buf); \
2488 putc ('\n', FILE); \
2491 /* This is how to output an assembler line
2492 that says to advance the location counter
2493 to a multiple of 2**LOG bytes. */
2495 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2497 fprintf (FILE, "\t.align %d\n", (LOG))
2499 /* Pick up the return address upon entry to a procedure. Used for
2500 dwarf2 unwind information. This also enables the table driven
2503 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2504 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2506 /* Describe how we implement __builtin_eh_return. */
2507 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2508 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2510 /* Print operand X (an rtx) in assembler syntax to file FILE.
2511 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2512 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2514 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2516 /* Define which CODE values are valid. */
2518 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2519 ((CODE) == '.' || (CODE) == '&')
2521 /* Print a memory address as an operand to reference that memory location. */
2523 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2525 /* Define the codes that are matched by predicates in rs6000.c. */
2527 #define PREDICATE_CODES \
2528 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2529 LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \
2530 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2531 LABEL_REF, SUBREG, REG, MEM}}, \
2532 {"short_cint_operand", {CONST_INT}}, \
2533 {"u_short_cint_operand", {CONST_INT}}, \
2534 {"non_short_cint_operand", {CONST_INT}}, \
2535 {"exact_log2_cint_operand", {CONST_INT}}, \
2536 {"gpc_reg_operand", {SUBREG, REG}}, \
2537 {"cc_reg_operand", {SUBREG, REG}}, \
2538 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2539 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2540 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2541 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
2542 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2543 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2544 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2545 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2546 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2547 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2548 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2549 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2550 {"easy_fp_constant", {CONST_DOUBLE}}, \
2551 {"easy_vector_constant", {CONST_VECTOR}}, \
2552 {"easy_vector_constant_add_self", {CONST_VECTOR}}, \
2553 {"zero_fp_constant", {CONST_DOUBLE}}, \
2554 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2555 {"lwa_operand", {SUBREG, MEM, REG}}, \
2556 {"volatile_mem_operand", {MEM}}, \
2557 {"offsettable_mem_operand", {MEM}}, \
2558 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2559 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2560 {"non_add_cint_operand", {CONST_INT}}, \
2561 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2562 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2563 {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \
2564 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2565 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2566 {"mask_operand", {CONST_INT}}, \
2567 {"mask_operand_wrap", {CONST_INT}}, \
2568 {"mask64_operand", {CONST_INT}}, \
2569 {"mask64_2_operand", {CONST_INT}}, \
2570 {"count_register_operand", {REG}}, \
2571 {"xer_operand", {REG}}, \
2572 {"symbol_ref_operand", {SYMBOL_REF}}, \
2573 {"rs6000_tls_symbol_ref", {SYMBOL_REF}}, \
2574 {"call_operand", {SYMBOL_REF, REG}}, \
2575 {"current_file_function_operand", {SYMBOL_REF}}, \
2576 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2577 CONST_DOUBLE, SYMBOL_REF}}, \
2578 {"load_multiple_operation", {PARALLEL}}, \
2579 {"store_multiple_operation", {PARALLEL}}, \
2580 {"vrsave_operation", {PARALLEL}}, \
2581 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2582 GT, LEU, LTU, GEU, GTU, \
2583 UNORDERED, ORDERED, \
2585 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2587 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2588 GT, LEU, LTU, GEU, GTU, \
2589 UNORDERED, ORDERED, \
2591 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2592 GT, LEU, LTU, GEU, GTU}}, \
2593 {"boolean_operator", {AND, IOR, XOR}}, \
2594 {"boolean_or_operator", {IOR, XOR}}, \
2595 {"altivec_register_operand", {REG}}, \
2596 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2598 /* uncomment for disabling the corresponding default options */
2599 /* #define MACHINE_no_sched_interblock */
2600 /* #define MACHINE_no_sched_speculative */
2601 /* #define MACHINE_no_sched_speculative_load */
2603 /* General flags. */
2604 extern int flag_pic;
2605 extern int optimize;
2606 extern int flag_expensive_optimizations;
2607 extern int frame_pointer_needed;
2609 enum rs6000_builtins
2611 /* AltiVec builtins. */
2612 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2613 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2614 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2615 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2616 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2617 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2618 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2619 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2620 ALTIVEC_BUILTIN_VADDUBM,
2621 ALTIVEC_BUILTIN_VADDUHM,
2622 ALTIVEC_BUILTIN_VADDUWM,
2623 ALTIVEC_BUILTIN_VADDFP,
2624 ALTIVEC_BUILTIN_VADDCUW,
2625 ALTIVEC_BUILTIN_VADDUBS,
2626 ALTIVEC_BUILTIN_VADDSBS,
2627 ALTIVEC_BUILTIN_VADDUHS,
2628 ALTIVEC_BUILTIN_VADDSHS,
2629 ALTIVEC_BUILTIN_VADDUWS,
2630 ALTIVEC_BUILTIN_VADDSWS,
2631 ALTIVEC_BUILTIN_VAND,
2632 ALTIVEC_BUILTIN_VANDC,
2633 ALTIVEC_BUILTIN_VAVGUB,
2634 ALTIVEC_BUILTIN_VAVGSB,
2635 ALTIVEC_BUILTIN_VAVGUH,
2636 ALTIVEC_BUILTIN_VAVGSH,
2637 ALTIVEC_BUILTIN_VAVGUW,
2638 ALTIVEC_BUILTIN_VAVGSW,
2639 ALTIVEC_BUILTIN_VCFUX,
2640 ALTIVEC_BUILTIN_VCFSX,
2641 ALTIVEC_BUILTIN_VCTSXS,
2642 ALTIVEC_BUILTIN_VCTUXS,
2643 ALTIVEC_BUILTIN_VCMPBFP,
2644 ALTIVEC_BUILTIN_VCMPEQUB,
2645 ALTIVEC_BUILTIN_VCMPEQUH,
2646 ALTIVEC_BUILTIN_VCMPEQUW,
2647 ALTIVEC_BUILTIN_VCMPEQFP,
2648 ALTIVEC_BUILTIN_VCMPGEFP,
2649 ALTIVEC_BUILTIN_VCMPGTUB,
2650 ALTIVEC_BUILTIN_VCMPGTSB,
2651 ALTIVEC_BUILTIN_VCMPGTUH,
2652 ALTIVEC_BUILTIN_VCMPGTSH,
2653 ALTIVEC_BUILTIN_VCMPGTUW,
2654 ALTIVEC_BUILTIN_VCMPGTSW,
2655 ALTIVEC_BUILTIN_VCMPGTFP,
2656 ALTIVEC_BUILTIN_VEXPTEFP,
2657 ALTIVEC_BUILTIN_VLOGEFP,
2658 ALTIVEC_BUILTIN_VMADDFP,
2659 ALTIVEC_BUILTIN_VMAXUB,
2660 ALTIVEC_BUILTIN_VMAXSB,
2661 ALTIVEC_BUILTIN_VMAXUH,
2662 ALTIVEC_BUILTIN_VMAXSH,
2663 ALTIVEC_BUILTIN_VMAXUW,
2664 ALTIVEC_BUILTIN_VMAXSW,
2665 ALTIVEC_BUILTIN_VMAXFP,
2666 ALTIVEC_BUILTIN_VMHADDSHS,
2667 ALTIVEC_BUILTIN_VMHRADDSHS,
2668 ALTIVEC_BUILTIN_VMLADDUHM,
2669 ALTIVEC_BUILTIN_VMRGHB,
2670 ALTIVEC_BUILTIN_VMRGHH,
2671 ALTIVEC_BUILTIN_VMRGHW,
2672 ALTIVEC_BUILTIN_VMRGLB,
2673 ALTIVEC_BUILTIN_VMRGLH,
2674 ALTIVEC_BUILTIN_VMRGLW,
2675 ALTIVEC_BUILTIN_VMSUMUBM,
2676 ALTIVEC_BUILTIN_VMSUMMBM,
2677 ALTIVEC_BUILTIN_VMSUMUHM,
2678 ALTIVEC_BUILTIN_VMSUMSHM,
2679 ALTIVEC_BUILTIN_VMSUMUHS,
2680 ALTIVEC_BUILTIN_VMSUMSHS,
2681 ALTIVEC_BUILTIN_VMINUB,
2682 ALTIVEC_BUILTIN_VMINSB,
2683 ALTIVEC_BUILTIN_VMINUH,
2684 ALTIVEC_BUILTIN_VMINSH,
2685 ALTIVEC_BUILTIN_VMINUW,
2686 ALTIVEC_BUILTIN_VMINSW,
2687 ALTIVEC_BUILTIN_VMINFP,
2688 ALTIVEC_BUILTIN_VMULEUB,
2689 ALTIVEC_BUILTIN_VMULESB,
2690 ALTIVEC_BUILTIN_VMULEUH,
2691 ALTIVEC_BUILTIN_VMULESH,
2692 ALTIVEC_BUILTIN_VMULOUB,
2693 ALTIVEC_BUILTIN_VMULOSB,
2694 ALTIVEC_BUILTIN_VMULOUH,
2695 ALTIVEC_BUILTIN_VMULOSH,
2696 ALTIVEC_BUILTIN_VNMSUBFP,
2697 ALTIVEC_BUILTIN_VNOR,
2698 ALTIVEC_BUILTIN_VOR,
2699 ALTIVEC_BUILTIN_VSEL_4SI,
2700 ALTIVEC_BUILTIN_VSEL_4SF,
2701 ALTIVEC_BUILTIN_VSEL_8HI,
2702 ALTIVEC_BUILTIN_VSEL_16QI,
2703 ALTIVEC_BUILTIN_VPERM_4SI,
2704 ALTIVEC_BUILTIN_VPERM_4SF,
2705 ALTIVEC_BUILTIN_VPERM_8HI,
2706 ALTIVEC_BUILTIN_VPERM_16QI,
2707 ALTIVEC_BUILTIN_VPKUHUM,
2708 ALTIVEC_BUILTIN_VPKUWUM,
2709 ALTIVEC_BUILTIN_VPKPX,
2710 ALTIVEC_BUILTIN_VPKUHSS,
2711 ALTIVEC_BUILTIN_VPKSHSS,
2712 ALTIVEC_BUILTIN_VPKUWSS,
2713 ALTIVEC_BUILTIN_VPKSWSS,
2714 ALTIVEC_BUILTIN_VPKUHUS,
2715 ALTIVEC_BUILTIN_VPKSHUS,
2716 ALTIVEC_BUILTIN_VPKUWUS,
2717 ALTIVEC_BUILTIN_VPKSWUS,
2718 ALTIVEC_BUILTIN_VREFP,
2719 ALTIVEC_BUILTIN_VRFIM,
2720 ALTIVEC_BUILTIN_VRFIN,
2721 ALTIVEC_BUILTIN_VRFIP,
2722 ALTIVEC_BUILTIN_VRFIZ,
2723 ALTIVEC_BUILTIN_VRLB,
2724 ALTIVEC_BUILTIN_VRLH,
2725 ALTIVEC_BUILTIN_VRLW,
2726 ALTIVEC_BUILTIN_VRSQRTEFP,
2727 ALTIVEC_BUILTIN_VSLB,
2728 ALTIVEC_BUILTIN_VSLH,
2729 ALTIVEC_BUILTIN_VSLW,
2730 ALTIVEC_BUILTIN_VSL,
2731 ALTIVEC_BUILTIN_VSLO,
2732 ALTIVEC_BUILTIN_VSPLTB,
2733 ALTIVEC_BUILTIN_VSPLTH,
2734 ALTIVEC_BUILTIN_VSPLTW,
2735 ALTIVEC_BUILTIN_VSPLTISB,
2736 ALTIVEC_BUILTIN_VSPLTISH,
2737 ALTIVEC_BUILTIN_VSPLTISW,
2738 ALTIVEC_BUILTIN_VSRB,
2739 ALTIVEC_BUILTIN_VSRH,
2740 ALTIVEC_BUILTIN_VSRW,
2741 ALTIVEC_BUILTIN_VSRAB,
2742 ALTIVEC_BUILTIN_VSRAH,
2743 ALTIVEC_BUILTIN_VSRAW,
2744 ALTIVEC_BUILTIN_VSR,
2745 ALTIVEC_BUILTIN_VSRO,
2746 ALTIVEC_BUILTIN_VSUBUBM,
2747 ALTIVEC_BUILTIN_VSUBUHM,
2748 ALTIVEC_BUILTIN_VSUBUWM,
2749 ALTIVEC_BUILTIN_VSUBFP,
2750 ALTIVEC_BUILTIN_VSUBCUW,
2751 ALTIVEC_BUILTIN_VSUBUBS,
2752 ALTIVEC_BUILTIN_VSUBSBS,
2753 ALTIVEC_BUILTIN_VSUBUHS,
2754 ALTIVEC_BUILTIN_VSUBSHS,
2755 ALTIVEC_BUILTIN_VSUBUWS,
2756 ALTIVEC_BUILTIN_VSUBSWS,
2757 ALTIVEC_BUILTIN_VSUM4UBS,
2758 ALTIVEC_BUILTIN_VSUM4SBS,
2759 ALTIVEC_BUILTIN_VSUM4SHS,
2760 ALTIVEC_BUILTIN_VSUM2SWS,
2761 ALTIVEC_BUILTIN_VSUMSWS,
2762 ALTIVEC_BUILTIN_VXOR,
2763 ALTIVEC_BUILTIN_VSLDOI_16QI,
2764 ALTIVEC_BUILTIN_VSLDOI_8HI,
2765 ALTIVEC_BUILTIN_VSLDOI_4SI,
2766 ALTIVEC_BUILTIN_VSLDOI_4SF,
2767 ALTIVEC_BUILTIN_VUPKHSB,
2768 ALTIVEC_BUILTIN_VUPKHPX,
2769 ALTIVEC_BUILTIN_VUPKHSH,
2770 ALTIVEC_BUILTIN_VUPKLSB,
2771 ALTIVEC_BUILTIN_VUPKLPX,
2772 ALTIVEC_BUILTIN_VUPKLSH,
2773 ALTIVEC_BUILTIN_MTVSCR,
2774 ALTIVEC_BUILTIN_MFVSCR,
2775 ALTIVEC_BUILTIN_DSSALL,
2776 ALTIVEC_BUILTIN_DSS,
2777 ALTIVEC_BUILTIN_LVSL,
2778 ALTIVEC_BUILTIN_LVSR,
2779 ALTIVEC_BUILTIN_DSTT,
2780 ALTIVEC_BUILTIN_DSTST,
2781 ALTIVEC_BUILTIN_DSTSTT,
2782 ALTIVEC_BUILTIN_DST,
2783 ALTIVEC_BUILTIN_LVEBX,
2784 ALTIVEC_BUILTIN_LVEHX,
2785 ALTIVEC_BUILTIN_LVEWX,
2786 ALTIVEC_BUILTIN_LVXL,
2787 ALTIVEC_BUILTIN_LVX,
2788 ALTIVEC_BUILTIN_STVX,
2789 ALTIVEC_BUILTIN_STVEBX,
2790 ALTIVEC_BUILTIN_STVEHX,
2791 ALTIVEC_BUILTIN_STVEWX,
2792 ALTIVEC_BUILTIN_STVXL,
2793 ALTIVEC_BUILTIN_VCMPBFP_P,
2794 ALTIVEC_BUILTIN_VCMPEQFP_P,
2795 ALTIVEC_BUILTIN_VCMPEQUB_P,
2796 ALTIVEC_BUILTIN_VCMPEQUH_P,
2797 ALTIVEC_BUILTIN_VCMPEQUW_P,
2798 ALTIVEC_BUILTIN_VCMPGEFP_P,
2799 ALTIVEC_BUILTIN_VCMPGTFP_P,
2800 ALTIVEC_BUILTIN_VCMPGTSB_P,
2801 ALTIVEC_BUILTIN_VCMPGTSH_P,
2802 ALTIVEC_BUILTIN_VCMPGTSW_P,
2803 ALTIVEC_BUILTIN_VCMPGTUB_P,
2804 ALTIVEC_BUILTIN_VCMPGTUH_P,
2805 ALTIVEC_BUILTIN_VCMPGTUW_P,
2806 ALTIVEC_BUILTIN_ABSS_V4SI,
2807 ALTIVEC_BUILTIN_ABSS_V8HI,
2808 ALTIVEC_BUILTIN_ABSS_V16QI,
2809 ALTIVEC_BUILTIN_ABS_V4SI,
2810 ALTIVEC_BUILTIN_ABS_V4SF,
2811 ALTIVEC_BUILTIN_ABS_V8HI,
2812 ALTIVEC_BUILTIN_ABS_V16QI,
2813 ALTIVEC_BUILTIN_COMPILETIME_ERROR,
2819 SPE_BUILTIN_EVDIVWS,
2820 SPE_BUILTIN_EVDIVWU,
2822 SPE_BUILTIN_EVFSADD,
2823 SPE_BUILTIN_EVFSDIV,
2824 SPE_BUILTIN_EVFSMUL,
2825 SPE_BUILTIN_EVFSSUB,
2829 SPE_BUILTIN_EVLHHESPLATX,
2830 SPE_BUILTIN_EVLHHOSSPLATX,
2831 SPE_BUILTIN_EVLHHOUSPLATX,
2832 SPE_BUILTIN_EVLWHEX,
2833 SPE_BUILTIN_EVLWHOSX,
2834 SPE_BUILTIN_EVLWHOUX,
2835 SPE_BUILTIN_EVLWHSPLATX,
2836 SPE_BUILTIN_EVLWWSPLATX,
2837 SPE_BUILTIN_EVMERGEHI,
2838 SPE_BUILTIN_EVMERGEHILO,
2839 SPE_BUILTIN_EVMERGELO,
2840 SPE_BUILTIN_EVMERGELOHI,
2841 SPE_BUILTIN_EVMHEGSMFAA,
2842 SPE_BUILTIN_EVMHEGSMFAN,
2843 SPE_BUILTIN_EVMHEGSMIAA,
2844 SPE_BUILTIN_EVMHEGSMIAN,
2845 SPE_BUILTIN_EVMHEGUMIAA,
2846 SPE_BUILTIN_EVMHEGUMIAN,
2847 SPE_BUILTIN_EVMHESMF,
2848 SPE_BUILTIN_EVMHESMFA,
2849 SPE_BUILTIN_EVMHESMFAAW,
2850 SPE_BUILTIN_EVMHESMFANW,
2851 SPE_BUILTIN_EVMHESMI,
2852 SPE_BUILTIN_EVMHESMIA,
2853 SPE_BUILTIN_EVMHESMIAAW,
2854 SPE_BUILTIN_EVMHESMIANW,
2855 SPE_BUILTIN_EVMHESSF,
2856 SPE_BUILTIN_EVMHESSFA,
2857 SPE_BUILTIN_EVMHESSFAAW,
2858 SPE_BUILTIN_EVMHESSFANW,
2859 SPE_BUILTIN_EVMHESSIAAW,
2860 SPE_BUILTIN_EVMHESSIANW,
2861 SPE_BUILTIN_EVMHEUMI,
2862 SPE_BUILTIN_EVMHEUMIA,
2863 SPE_BUILTIN_EVMHEUMIAAW,
2864 SPE_BUILTIN_EVMHEUMIANW,
2865 SPE_BUILTIN_EVMHEUSIAAW,
2866 SPE_BUILTIN_EVMHEUSIANW,
2867 SPE_BUILTIN_EVMHOGSMFAA,
2868 SPE_BUILTIN_EVMHOGSMFAN,
2869 SPE_BUILTIN_EVMHOGSMIAA,
2870 SPE_BUILTIN_EVMHOGSMIAN,
2871 SPE_BUILTIN_EVMHOGUMIAA,
2872 SPE_BUILTIN_EVMHOGUMIAN,
2873 SPE_BUILTIN_EVMHOSMF,
2874 SPE_BUILTIN_EVMHOSMFA,
2875 SPE_BUILTIN_EVMHOSMFAAW,
2876 SPE_BUILTIN_EVMHOSMFANW,
2877 SPE_BUILTIN_EVMHOSMI,
2878 SPE_BUILTIN_EVMHOSMIA,
2879 SPE_BUILTIN_EVMHOSMIAAW,
2880 SPE_BUILTIN_EVMHOSMIANW,
2881 SPE_BUILTIN_EVMHOSSF,
2882 SPE_BUILTIN_EVMHOSSFA,
2883 SPE_BUILTIN_EVMHOSSFAAW,
2884 SPE_BUILTIN_EVMHOSSFANW,
2885 SPE_BUILTIN_EVMHOSSIAAW,
2886 SPE_BUILTIN_EVMHOSSIANW,
2887 SPE_BUILTIN_EVMHOUMI,
2888 SPE_BUILTIN_EVMHOUMIA,
2889 SPE_BUILTIN_EVMHOUMIAAW,
2890 SPE_BUILTIN_EVMHOUMIANW,
2891 SPE_BUILTIN_EVMHOUSIAAW,
2892 SPE_BUILTIN_EVMHOUSIANW,
2893 SPE_BUILTIN_EVMWHSMF,
2894 SPE_BUILTIN_EVMWHSMFA,
2895 SPE_BUILTIN_EVMWHSMI,
2896 SPE_BUILTIN_EVMWHSMIA,
2897 SPE_BUILTIN_EVMWHSSF,
2898 SPE_BUILTIN_EVMWHSSFA,
2899 SPE_BUILTIN_EVMWHUMI,
2900 SPE_BUILTIN_EVMWHUMIA,
2901 SPE_BUILTIN_EVMWLSMIAAW,
2902 SPE_BUILTIN_EVMWLSMIANW,
2903 SPE_BUILTIN_EVMWLSSIAAW,
2904 SPE_BUILTIN_EVMWLSSIANW,
2905 SPE_BUILTIN_EVMWLUMI,
2906 SPE_BUILTIN_EVMWLUMIA,
2907 SPE_BUILTIN_EVMWLUMIAAW,
2908 SPE_BUILTIN_EVMWLUMIANW,
2909 SPE_BUILTIN_EVMWLUSIAAW,
2910 SPE_BUILTIN_EVMWLUSIANW,
2911 SPE_BUILTIN_EVMWSMF,
2912 SPE_BUILTIN_EVMWSMFA,
2913 SPE_BUILTIN_EVMWSMFAA,
2914 SPE_BUILTIN_EVMWSMFAN,
2915 SPE_BUILTIN_EVMWSMI,
2916 SPE_BUILTIN_EVMWSMIA,
2917 SPE_BUILTIN_EVMWSMIAA,
2918 SPE_BUILTIN_EVMWSMIAN,
2919 SPE_BUILTIN_EVMWHSSFAA,
2920 SPE_BUILTIN_EVMWSSF,
2921 SPE_BUILTIN_EVMWSSFA,
2922 SPE_BUILTIN_EVMWSSFAA,
2923 SPE_BUILTIN_EVMWSSFAN,
2924 SPE_BUILTIN_EVMWUMI,
2925 SPE_BUILTIN_EVMWUMIA,
2926 SPE_BUILTIN_EVMWUMIAA,
2927 SPE_BUILTIN_EVMWUMIAN,
2936 SPE_BUILTIN_EVSTDDX,
2937 SPE_BUILTIN_EVSTDHX,
2938 SPE_BUILTIN_EVSTDWX,
2939 SPE_BUILTIN_EVSTWHEX,
2940 SPE_BUILTIN_EVSTWHOX,
2941 SPE_BUILTIN_EVSTWWEX,
2942 SPE_BUILTIN_EVSTWWOX,
2943 SPE_BUILTIN_EVSUBFW,
2946 SPE_BUILTIN_EVADDSMIAAW,
2947 SPE_BUILTIN_EVADDSSIAAW,
2948 SPE_BUILTIN_EVADDUMIAAW,
2949 SPE_BUILTIN_EVADDUSIAAW,
2950 SPE_BUILTIN_EVCNTLSW,
2951 SPE_BUILTIN_EVCNTLZW,
2952 SPE_BUILTIN_EVEXTSB,
2953 SPE_BUILTIN_EVEXTSH,
2954 SPE_BUILTIN_EVFSABS,
2955 SPE_BUILTIN_EVFSCFSF,
2956 SPE_BUILTIN_EVFSCFSI,
2957 SPE_BUILTIN_EVFSCFUF,
2958 SPE_BUILTIN_EVFSCFUI,
2959 SPE_BUILTIN_EVFSCTSF,
2960 SPE_BUILTIN_EVFSCTSI,
2961 SPE_BUILTIN_EVFSCTSIZ,
2962 SPE_BUILTIN_EVFSCTUF,
2963 SPE_BUILTIN_EVFSCTUI,
2964 SPE_BUILTIN_EVFSCTUIZ,
2965 SPE_BUILTIN_EVFSNABS,
2966 SPE_BUILTIN_EVFSNEG,
2970 SPE_BUILTIN_EVSUBFSMIAAW,
2971 SPE_BUILTIN_EVSUBFSSIAAW,
2972 SPE_BUILTIN_EVSUBFUMIAAW,
2973 SPE_BUILTIN_EVSUBFUSIAAW,
2974 SPE_BUILTIN_EVADDIW,
2978 SPE_BUILTIN_EVLHHESPLAT,
2979 SPE_BUILTIN_EVLHHOSSPLAT,
2980 SPE_BUILTIN_EVLHHOUSPLAT,
2982 SPE_BUILTIN_EVLWHOS,
2983 SPE_BUILTIN_EVLWHOU,
2984 SPE_BUILTIN_EVLWHSPLAT,
2985 SPE_BUILTIN_EVLWWSPLAT,
2988 SPE_BUILTIN_EVSRWIS,
2989 SPE_BUILTIN_EVSRWIU,
2993 SPE_BUILTIN_EVSTWHE,
2994 SPE_BUILTIN_EVSTWHO,
2995 SPE_BUILTIN_EVSTWWE,
2996 SPE_BUILTIN_EVSTWWO,
2997 SPE_BUILTIN_EVSUBIFW,
3000 SPE_BUILTIN_EVCMPEQ,
3001 SPE_BUILTIN_EVCMPGTS,
3002 SPE_BUILTIN_EVCMPGTU,
3003 SPE_BUILTIN_EVCMPLTS,
3004 SPE_BUILTIN_EVCMPLTU,
3005 SPE_BUILTIN_EVFSCMPEQ,
3006 SPE_BUILTIN_EVFSCMPGT,
3007 SPE_BUILTIN_EVFSCMPLT,
3008 SPE_BUILTIN_EVFSTSTEQ,
3009 SPE_BUILTIN_EVFSTSTGT,
3010 SPE_BUILTIN_EVFSTSTLT,
3012 /* EVSEL compares. */
3013 SPE_BUILTIN_EVSEL_CMPEQ,
3014 SPE_BUILTIN_EVSEL_CMPGTS,
3015 SPE_BUILTIN_EVSEL_CMPGTU,
3016 SPE_BUILTIN_EVSEL_CMPLTS,
3017 SPE_BUILTIN_EVSEL_CMPLTU,
3018 SPE_BUILTIN_EVSEL_FSCMPEQ,
3019 SPE_BUILTIN_EVSEL_FSCMPGT,
3020 SPE_BUILTIN_EVSEL_FSCMPLT,
3021 SPE_BUILTIN_EVSEL_FSTSTEQ,
3022 SPE_BUILTIN_EVSEL_FSTSTGT,
3023 SPE_BUILTIN_EVSEL_FSTSTLT,
3025 SPE_BUILTIN_EVSPLATFI,
3026 SPE_BUILTIN_EVSPLATI,
3027 SPE_BUILTIN_EVMWHSSMAA,
3028 SPE_BUILTIN_EVMWHSMFAA,
3029 SPE_BUILTIN_EVMWHSMIAA,
3030 SPE_BUILTIN_EVMWHUSIAA,
3031 SPE_BUILTIN_EVMWHUMIAA,
3032 SPE_BUILTIN_EVMWHSSFAN,
3033 SPE_BUILTIN_EVMWHSSIAN,
3034 SPE_BUILTIN_EVMWHSMFAN,
3035 SPE_BUILTIN_EVMWHSMIAN,
3036 SPE_BUILTIN_EVMWHUSIAN,
3037 SPE_BUILTIN_EVMWHUMIAN,
3038 SPE_BUILTIN_EVMWHGSSFAA,
3039 SPE_BUILTIN_EVMWHGSMFAA,
3040 SPE_BUILTIN_EVMWHGSMIAA,
3041 SPE_BUILTIN_EVMWHGUMIAA,
3042 SPE_BUILTIN_EVMWHGSSFAN,
3043 SPE_BUILTIN_EVMWHGSMFAN,
3044 SPE_BUILTIN_EVMWHGSMIAN,
3045 SPE_BUILTIN_EVMWHGUMIAN,
3046 SPE_BUILTIN_MTSPEFSCR,
3047 SPE_BUILTIN_MFSPEFSCR,
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