1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions. */
27 /* Definitions for the object file format. These are set at
30 #define OBJECT_XCOFF 1
33 #define OBJECT_MACHO 4
35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
44 /* Default string to use for cpu if not specified. */
45 #ifndef TARGET_CPU_DEFAULT
46 #define TARGET_CPU_DEFAULT ((char *)0)
49 /* Common CPP definitions used by CPP_SPEC among the various targets
50 for handling -mcpu=xxx switches. */
51 #define CPP_CPU_SPEC \
53 %{mpower: %{!mpower2: -D_ARCH_PWR}} \
54 %{mpower2: -D_ARCH_PWR2} \
55 %{mpowerpc*: -D_ARCH_PPC} \
56 %{mno-power: %{!mpowerpc*: -D_ARCH_COM}} \
57 %{!mno-power: %{!mpower2: %(cpp_default)}}} \
58 %{mcpu=common: -D_ARCH_COM} \
59 %{mcpu=power: -D_ARCH_PWR} \
60 %{mcpu=power2: -D_ARCH_PWR2} \
61 %{mcpu=powerpc: -D_ARCH_PPC} \
62 %{mcpu=rios: -D_ARCH_PWR} \
63 %{mcpu=rios1: -D_ARCH_PWR} \
64 %{mcpu=rios2: -D_ARCH_PWR2} \
65 %{mcpu=rsc: -D_ARCH_PWR} \
66 %{mcpu=rsc1: -D_ARCH_PWR} \
67 %{mcpu=401: -D_ARCH_PPC} \
68 %{mcpu=403: -D_ARCH_PPC} \
69 %{mcpu=505: -D_ARCH_PPC} \
70 %{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
71 %{mcpu=602: -D_ARCH_PPC} \
72 %{mcpu=603: -D_ARCH_PPC} \
73 %{mcpu=603e: -D_ARCH_PPC} \
74 %{mcpu=ec603e: -D_ARCH_PPC} \
75 %{mcpu=604: -D_ARCH_PPC} \
76 %{mcpu=604e: -D_ARCH_PPC} \
77 %{mcpu=620: -D_ARCH_PPC} \
78 %{mcpu=740: -D_ARCH_PPC} \
79 %{mcpu=7450: -D_ARCH_PPC} \
80 %{mcpu=750: -D_ARCH_PPC} \
81 %{mcpu=801: -D_ARCH_PPC} \
82 %{mcpu=821: -D_ARCH_PPC} \
83 %{mcpu=823: -D_ARCH_PPC} \
84 %{mcpu=860: -D_ARCH_PPC} \
85 %{maltivec: -D__ALTIVEC__}"
87 /* Common ASM definitions used by ASM_SPEC among the various targets
88 for handling -mcpu=xxx switches. */
89 #define ASM_CPU_SPEC \
91 %{mpower: %{!mpower2: -mpwr}} \
94 %{mno-power: %{!mpowerpc*: -mcom}} \
95 %{!mno-power: %{!mpower2: %(asm_default)}}} \
96 %{mcpu=common: -mcom} \
97 %{mcpu=power: -mpwr} \
98 %{mcpu=power2: -mpwrx} \
99 %{mcpu=powerpc: -mppc} \
100 %{mcpu=rios: -mpwr} \
101 %{mcpu=rios1: -mpwr} \
102 %{mcpu=rios2: -mpwrx} \
104 %{mcpu=rsc1: -mpwr} \
111 %{mcpu=603e: -mppc} \
112 %{mcpu=ec603e: -mppc} \
114 %{mcpu=604e: -mppc} \
117 %{mcpu=7450: -mppc} \
123 %{maltivec: -maltivec}"
125 #define CPP_DEFAULT_SPEC ""
127 #define ASM_DEFAULT_SPEC ""
129 /* This macro defines names of additional specifications to put in the specs
130 that can be used in various specifications like CC1_SPEC. Its definition
131 is an initializer with a subgrouping for each command option.
133 Each subgrouping contains a string constant, that defines the
134 specification name, and a string constant that used by the GNU CC driver
137 Do not define this macro if it does not need to do anything. */
139 #define SUBTARGET_EXTRA_SPECS
141 #define EXTRA_SPECS \
142 { "cpp_cpu", CPP_CPU_SPEC }, \
143 { "cpp_default", CPP_DEFAULT_SPEC }, \
144 { "asm_cpu", ASM_CPU_SPEC }, \
145 { "asm_default", ASM_DEFAULT_SPEC }, \
146 SUBTARGET_EXTRA_SPECS
148 /* Architecture type. */
150 extern int target_flags;
152 /* Use POWER architecture instructions and MQ register. */
153 #define MASK_POWER 0x00000001
155 /* Use POWER2 extensions to POWER architecture. */
156 #define MASK_POWER2 0x00000002
158 /* Use PowerPC architecture instructions. */
159 #define MASK_POWERPC 0x00000004
161 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
162 #define MASK_PPC_GPOPT 0x00000008
164 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
165 #define MASK_PPC_GFXOPT 0x00000010
167 /* Use PowerPC-64 architecture instructions. */
168 #define MASK_POWERPC64 0x00000020
170 /* Use revised mnemonic names defined for PowerPC architecture. */
171 #define MASK_NEW_MNEMONICS 0x00000040
173 /* Disable placing fp constants in the TOC; can be turned on when the
175 #define MASK_NO_FP_IN_TOC 0x00000080
177 /* Disable placing symbol+offset constants in the TOC; can be turned on when
178 the TOC overflows. */
179 #define MASK_NO_SUM_IN_TOC 0x00000100
181 /* Output only one TOC entry per module. Normally linking fails if
182 there are more than 16K unique variables/constants in an executable. With
183 this option, linking fails only if there are more than 16K modules, or
184 if there are more than 16K unique variables/constant in a single module.
186 This is at the cost of having 2 extra loads and one extra store per
187 function, and one less allocable register. */
188 #define MASK_MINIMAL_TOC 0x00000200
190 /* Nonzero for the 64bit model: ints, longs, and pointers are 64 bits. */
191 #define MASK_64BIT 0x00000400
193 /* Disable use of FPRs. */
194 #define MASK_SOFT_FLOAT 0x00000800
196 /* Enable load/store multiple, even on powerpc */
197 #define MASK_MULTIPLE 0x00001000
198 #define MASK_MULTIPLE_SET 0x00002000
200 /* Use string instructions for block moves */
201 #define MASK_STRING 0x00004000
202 #define MASK_STRING_SET 0x00008000
204 /* Disable update form of load/store */
205 #define MASK_NO_UPDATE 0x00010000
207 /* Disable fused multiply/add operations */
208 #define MASK_NO_FUSED_MADD 0x00020000
210 /* Nonzero if we need to schedule the prolog and epilog. */
211 #define MASK_SCHED_PROLOG 0x00040000
213 /* Use AltiVec instructions. */
214 #define MASK_ALTIVEC 0x00080000
216 /* Return small structures in memory (as the AIX ABI requires). */
217 #define MASK_AIX_STRUCT_RET 0x00100000
218 #define MASK_AIX_STRUCT_RET_SET 0x00200000
220 /* The only remaining free bit is 0x00400000. sysv4.h uses
221 0x00800000 -> 0x40000000, and 0x80000000 is not available
222 because target_flags is signed. */
224 #define TARGET_POWER (target_flags & MASK_POWER)
225 #define TARGET_POWER2 (target_flags & MASK_POWER2)
226 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
227 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
228 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
229 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
230 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
231 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
232 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
233 #define TARGET_64BIT (target_flags & MASK_64BIT)
234 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
235 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
236 #define TARGET_MULTIPLE_SET (target_flags & MASK_MULTIPLE_SET)
237 #define TARGET_STRING (target_flags & MASK_STRING)
238 #define TARGET_STRING_SET (target_flags & MASK_STRING_SET)
239 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
240 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
241 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
242 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
243 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
245 #define TARGET_32BIT (! TARGET_64BIT)
246 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
247 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
248 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
251 /* For libgcc2 we make sure this is a compile time constant */
253 #define TARGET_POWERPC64 1
255 #define TARGET_POWERPC64 0
258 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
261 #define TARGET_XL_CALL 0
263 /* Run-time compilation parameters selecting different hardware subsets.
265 Macro to define tables used to set the flags.
266 This is a list in braces of pairs in braces,
267 each pair being { "NAME", VALUE }
268 where VALUE is the bits to set or minus the bits to clear.
269 An empty string NAME is used to identify the default VALUE. */
271 #define TARGET_SWITCHES \
272 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
273 N_("Use POWER instruction set")}, \
274 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
276 N_("Use POWER2 instruction set")}, \
277 {"no-power2", - MASK_POWER2, \
278 N_("Do not use POWER2 instruction set")}, \
279 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
281 N_("Do not use POWER instruction set")}, \
282 {"powerpc", MASK_POWERPC, \
283 N_("Use PowerPC instruction set")}, \
284 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
285 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
286 N_("Do not use PowerPC instruction set")}, \
287 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
288 N_("Use PowerPC General Purpose group optional instructions")},\
289 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
290 N_("Don't use PowerPC General Purpose group optional instructions")},\
291 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
292 N_("Use PowerPC Graphics group optional instructions")},\
293 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
294 N_("Don't use PowerPC Graphics group optional instructions")},\
295 {"powerpc64", MASK_POWERPC64, \
296 N_("Use PowerPC-64 instruction set")}, \
297 {"no-powerpc64", - MASK_POWERPC64, \
298 N_("Don't use PowerPC-64 instruction set")}, \
299 {"altivec", MASK_ALTIVEC , \
300 N_("Use AltiVec instructions")}, \
301 {"no-altivec", - MASK_ALTIVEC , \
302 N_("Don't use AltiVec instructions")}, \
303 {"new-mnemonics", MASK_NEW_MNEMONICS, \
304 N_("Use new mnemonics for PowerPC architecture")},\
305 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
306 N_("Use old mnemonics for PowerPC architecture")},\
307 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
308 | MASK_MINIMAL_TOC), \
309 N_("Put everything in the regular TOC")}, \
310 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
311 N_("Place floating point constants in TOC")}, \
312 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
313 N_("Don't place floating point constants in TOC")},\
314 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
315 N_("Place symbol+offset constants in TOC")}, \
316 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
317 N_("Don't place symbol+offset constants in TOC")},\
318 {"minimal-toc", MASK_MINIMAL_TOC, \
319 "Use only one TOC entry per procedure"}, \
320 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
322 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
323 N_("Place variable addresses in the regular TOC")},\
324 {"hard-float", - MASK_SOFT_FLOAT, \
325 N_("Use hardware fp")}, \
326 {"soft-float", MASK_SOFT_FLOAT, \
327 N_("Do not use hardware fp")}, \
328 {"multiple", MASK_MULTIPLE | MASK_MULTIPLE_SET, \
329 N_("Generate load/store multiple instructions")}, \
330 {"no-multiple", - MASK_MULTIPLE, \
331 N_("Do not generate load/store multiple instructions")},\
332 {"no-multiple", MASK_MULTIPLE_SET, \
334 {"string", MASK_STRING | MASK_STRING_SET, \
335 N_("Generate string instructions for block moves")},\
336 {"no-string", - MASK_STRING, \
337 N_("Do not generate string instructions for block moves")},\
338 {"no-string", MASK_STRING_SET, \
340 {"update", - MASK_NO_UPDATE, \
341 N_("Generate load/store with update instructions")},\
342 {"no-update", MASK_NO_UPDATE, \
343 N_("Do not generate load/store with update instructions")},\
344 {"fused-madd", - MASK_NO_FUSED_MADD, \
345 N_("Generate fused multiply/add instructions")},\
346 {"no-fused-madd", MASK_NO_FUSED_MADD, \
347 N_("Don't generate fused multiply/add instructions")},\
348 {"sched-prolog", MASK_SCHED_PROLOG, \
350 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
351 N_("Don't schedule the start and end of the procedure")},\
352 {"sched-epilog", MASK_SCHED_PROLOG, \
354 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
356 {"aix-struct-return", MASK_AIX_STRUCT_RET | MASK_AIX_STRUCT_RET_SET, \
357 N_("Return all structures in memory (AIX default)")},\
358 {"svr4-struct-return", - MASK_AIX_STRUCT_RET,\
359 N_("Return small structures in registers (SVR4 default)")},\
360 {"svr4-struct-return",MASK_AIX_STRUCT_RET_SET,\
362 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET,\
364 {"no-aix-struct-return", MASK_AIX_STRUCT_RET_SET,\
366 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET | MASK_AIX_STRUCT_RET_SET,\
369 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
372 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
374 /* This is meant to be redefined in the host dependent files */
375 #define SUBTARGET_SWITCHES
377 /* Processor type. Order must match cpu attribute in MD file. */
397 extern enum processor_type rs6000_cpu;
399 /* Recast the processor type to the cpu attribute. */
400 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
402 /* Define generic processor types based upon current deployment. */
403 #define PROCESSOR_COMMON PROCESSOR_PPC601
404 #define PROCESSOR_POWER PROCESSOR_RIOS1
405 #define PROCESSOR_POWERPC PROCESSOR_PPC604
406 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
408 /* Define the default processor. This is overridden by other tm.h files. */
409 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
410 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
412 /* Specify the dialect of assembler to use. New mnemonics is dialect one
413 and the old mnemonics are dialect zero. */
414 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
416 /* This macro is similar to `TARGET_SWITCHES' but defines names of
417 command options that have values. Its definition is an
418 initializer with a subgrouping for each command option.
420 Each subgrouping contains a string constant, that defines the
421 fixed part of the option name, and the address of a variable.
422 The variable, type `char *', is set to the variable part of the
423 given option if the fixed part matches. The actual option name
424 is made by appending `-m' to the specified name.
426 Here is an example which defines `-mshort-data-NUMBER'. If the
427 given option is `-mshort-data-512', the variable `m88k_short_data'
428 will be set to the string `"512"'.
430 extern char *m88k_short_data;
431 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
433 /* This is meant to be overridden in target specific files. */
434 #define SUBTARGET_OPTIONS
436 #define TARGET_OPTIONS \
438 {"cpu=", &rs6000_select[1].string, \
439 N_("Use features of and schedule code for given CPU") }, \
440 {"tune=", &rs6000_select[2].string, \
441 N_("Schedule code for given CPU") }, \
442 {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \
443 {"abi=", &rs6000_abi_string, N_("Specify ABI to use") }, \
444 {"long-double-", &rs6000_long_double_size_string, \
445 N_("Specify size of long double (64 or 128 bits)") }, \
449 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
450 struct rs6000_cpu_select
458 extern struct rs6000_cpu_select rs6000_select[];
461 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
462 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
463 extern int rs6000_debug_stack; /* debug stack applications */
464 extern int rs6000_debug_arg; /* debug argument handling */
466 #define TARGET_DEBUG_STACK rs6000_debug_stack
467 #define TARGET_DEBUG_ARG rs6000_debug_arg
469 /* These are separate from target_flags because we've run out of bits
471 extern const char *rs6000_long_double_size_string;
472 extern int rs6000_long_double_type_size;
473 extern int rs6000_altivec_abi;
475 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
476 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
478 /* Sometimes certain combinations of command options do not make sense
479 on a particular target machine. You can define a macro
480 `OVERRIDE_OPTIONS' to take account of this. This macro, if
481 defined, is executed once just after all the command options have
484 Don't use this macro to turn on various extra optimizations for
485 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
487 On the RS/6000 this is used to define the target cpu type. */
489 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
491 /* Define this to change the optimizations performed by default. */
492 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
494 /* Show we can debug even without a frame pointer. */
495 #define CAN_DEBUG_WITHOUT_FP
497 /* target machine storage layout */
499 /* Define to support cross compilation to an RS6000 target. */
500 #define REAL_ARITHMETIC
502 /* Define this macro if it is advisable to hold scalars in registers
503 in a wider mode than that declared by the program. In such cases,
504 the value is constrained to be within the bounds of the declared
505 type, but kept valid in the wider mode. The signedness of the
506 extension may differ from that of the type. */
508 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
509 if (GET_MODE_CLASS (MODE) == MODE_INT \
510 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
513 /* Define this if function arguments should also be promoted using the above
516 #define PROMOTE_FUNCTION_ARGS
518 /* Likewise, if the function return value is promoted. */
520 #define PROMOTE_FUNCTION_RETURN
522 /* Define this if most significant bit is lowest numbered
523 in instructions that operate on numbered bit-fields. */
524 /* That is true on RS/6000. */
525 #define BITS_BIG_ENDIAN 1
527 /* Define this if most significant byte of a word is the lowest numbered. */
528 /* That is true on RS/6000. */
529 #define BYTES_BIG_ENDIAN 1
531 /* Define this if most significant word of a multiword number is lowest
534 For RS/6000 we can decide arbitrarily since there are no machine
535 instructions for them. Might as well be consistent with bits and bytes. */
536 #define WORDS_BIG_ENDIAN 1
538 /* number of bits in an addressable storage unit */
539 #define BITS_PER_UNIT 8
541 /* Width in bits of a "word", which is the contents of a machine register.
542 Note that this is not necessarily the width of data type `int';
543 if using 16-bit ints on a 68000, this would still be 32.
544 But on a machine with 16-bit registers, this would be 16. */
545 #define BITS_PER_WORD (! TARGET_POWERPC64 ? 32 : 64)
546 #define MAX_BITS_PER_WORD 64
548 /* Width of a word, in units (bytes). */
549 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
550 #define MIN_UNITS_PER_WORD 4
551 #define UNITS_PER_FP_WORD 8
552 #define UNITS_PER_ALTIVEC_WORD 16
554 /* Type used for ptrdiff_t, as a string used in a declaration. */
555 #define PTRDIFF_TYPE "int"
557 /* Type used for size_t, as a string used in a declaration. */
558 #define SIZE_TYPE "long unsigned int"
560 /* Type used for wchar_t, as a string used in a declaration. */
561 #define WCHAR_TYPE "short unsigned int"
563 /* Width of wchar_t in bits. */
564 #define WCHAR_TYPE_SIZE 16
566 /* A C expression for the size in bits of the type `short' on the
567 target machine. If you don't define this, the default is half a
568 word. (If this would be less than one storage unit, it is
569 rounded up to one unit.) */
570 #define SHORT_TYPE_SIZE 16
572 /* A C expression for the size in bits of the type `int' on the
573 target machine. If you don't define this, the default is one
575 #define INT_TYPE_SIZE 32
577 /* A C expression for the size in bits of the type `long' on the
578 target machine. If you don't define this, the default is one
580 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
581 #define MAX_LONG_TYPE_SIZE 64
583 /* A C expression for the size in bits of the type `long long' on the
584 target machine. If you don't define this, the default is two
586 #define LONG_LONG_TYPE_SIZE 64
588 /* A C expression for the size in bits of the type `char' on the
589 target machine. If you don't define this, the default is one
590 quarter of a word. (If this would be less than one storage unit,
591 it is rounded up to one unit.) */
592 #define CHAR_TYPE_SIZE BITS_PER_UNIT
594 /* A C expression for the size in bits of the type `float' on the
595 target machine. If you don't define this, the default is one
597 #define FLOAT_TYPE_SIZE 32
599 /* A C expression for the size in bits of the type `double' on the
600 target machine. If you don't define this, the default is two
602 #define DOUBLE_TYPE_SIZE 64
604 /* A C expression for the size in bits of the type `long double' on
605 the target machine. If you don't define this, the default is two
607 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
609 /* Constant which presents upper bound of the above value. */
610 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
612 /* Define this to set long double type size to use in libgcc2.c, which can
613 not depend on target_flags. */
614 #ifdef __LONG_DOUBLE_128__
615 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
617 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
620 /* Width in bits of a pointer.
621 See also the macro `Pmode' defined below. */
622 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
624 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
625 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
627 /* Boundary (in *bits*) on which stack pointer should be aligned. */
628 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
630 /* Allocation boundary (in *bits*) for the code of a function. */
631 #define FUNCTION_BOUNDARY 32
633 /* No data type wants to be aligned rounder than this. */
634 #define BIGGEST_ALIGNMENT 128
636 /* A C expression to compute the alignment for a variables in the
637 local store. TYPE is the data type, and ALIGN is the alignment
638 that the object would ordinarily have. */
639 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
641 && TREE_CODE (TYPE)) == VECTOR_TYPE ? 128 : ALIGN)
643 /* Handle #pragma pack. */
644 #define HANDLE_PRAGMA_PACK 1
646 /* Alignment of field after `int : 0' in a structure. */
647 #define EMPTY_FIELD_BOUNDARY 32
649 /* Every structure's size must be a multiple of this. */
650 #define STRUCTURE_SIZE_BOUNDARY 8
652 /* A bitfield declared as `int' forces `int' alignment for the struct. */
653 #define PCC_BITFIELD_TYPE_MATTERS 1
655 /* Make strings word-aligned so strcpy from constants will be faster. */
656 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
657 (TREE_CODE (EXP) == STRING_CST \
658 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
660 /* Make arrays of chars word-aligned for the same reasons.
661 Align vectors to 128 bits. */
662 #define DATA_ALIGNMENT(TYPE, ALIGN) \
663 (TREE_CODE (TYPE) == VECTOR_TYPE ? 128 \
664 : TREE_CODE (TYPE) == ARRAY_TYPE \
665 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
666 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
668 /* Non-zero if move instructions will actually fail to work
669 when given unaligned data. */
670 #define STRICT_ALIGNMENT 0
672 /* Define this macro to be the value 1 if unaligned accesses have a cost
673 many times greater than aligned accesses, for example if they are
674 emulated in a trap handler. */
675 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
677 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode) \
680 /* Standard register usage. */
682 /* Number of actual hardware registers.
683 The hardware registers are assigned numbers for the compiler
684 from 0 to just below FIRST_PSEUDO_REGISTER.
685 All registers that the compiler knows about must be given numbers,
686 even those that are not normally considered general registers.
688 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
689 an MQ register, a count register, a link register, and 8 condition
690 register fields, which we view here as separate registers.
692 In addition, the difference between the frame and argument pointers is
693 a function of the number of registers saved, so we need to have a
694 register for AP that will later be eliminated in favor of SP or FP.
695 This is a normal register, but it is fixed.
697 We also create a pseudo register for float/int conversions, that will
698 really represent the memory location used. It is represented here as
699 a register, in order to work around problems in allocating stack storage
700 in inline functions. */
702 #define FIRST_PSEUDO_REGISTER 110
704 /* This must be included for pre gcc 3.0 glibc compatibility. */
705 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
707 /* 1 for registers that have pervasive standard uses
708 and are not available for the register allocator.
710 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
711 as a local register; for all other OS's r2 is the TOC pointer.
713 cr5 is not supposed to be used.
715 On System V implementations, r13 is fixed and not available for use. */
717 #define FIXED_REGISTERS \
718 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
719 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
720 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
721 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
722 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
723 /* AltiVec registers. */ \
724 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
725 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
729 /* 1 for registers not available across function calls.
730 These must include the FIXED_REGISTERS and also any
731 registers that can be used without being saved.
732 The latter must include the registers where values are returned
733 and the register where structure-value addresses are passed.
734 Aside from that, you can include as many other registers as you like. */
736 #define CALL_USED_REGISTERS \
737 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
738 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
739 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
740 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
741 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
742 /* AltiVec registers. */ \
743 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
744 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
748 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
749 the entire set of `FIXED_REGISTERS' be included.
750 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
751 This macro is optional. If not specified, it defaults to the value
752 of `CALL_USED_REGISTERS'. */
754 #define CALL_REALLY_USED_REGISTERS \
755 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
756 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
757 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
758 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
759 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
760 /* AltiVec registers. */ \
761 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
762 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
772 #define MAX_CR_REGNO 75
774 #define FIRST_ALTIVEC_REGNO 77
775 #define LAST_ALTIVEC_REGNO 108
776 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO)
777 #define VRSAVE_REGNO 109
779 /* List the order in which to allocate registers. Each register must be
780 listed once, even those in FIXED_REGISTERS.
782 We allocate in the following order:
783 fp0 (not saved or used for anything)
784 fp13 - fp2 (not saved; incoming fp arg registers)
785 fp1 (not saved; return value)
786 fp31 - fp14 (saved; order given to save least number)
787 cr7, cr6 (not saved or special)
788 cr1 (not saved, but used for FP operations)
789 cr0 (not saved, but used for arithmetic operations)
790 cr4, cr3, cr2 (saved)
791 r0 (not saved; cannot be base reg)
792 r9 (not saved; best for TImode)
793 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
794 r3 (not saved; return value register)
795 r31 - r13 (saved; order given to save least number)
796 r12 (not saved; if used for DImode or DFmode would use r13)
797 mq (not saved; best to use it if we can)
798 ctr (not saved; when we have the choice ctr is better)
800 cr5, r1, r2, ap, xer, vrsave (fixed)
803 v0 - v1 (not saved or used for anything)
804 v13 - v3 (not saved; incoming vector arg registers)
805 v2 (not saved; incoming vector arg reg; return value)
806 v19 - v14 (not saved or used for anything)
807 v31 - v20 (saved; order given to save least number)
811 #define REG_ALLOC_ORDER \
813 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
815 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
816 50, 49, 48, 47, 46, \
817 75, 74, 69, 68, 72, 71, 70, \
819 9, 11, 10, 8, 7, 6, 5, 4, \
821 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
822 18, 17, 16, 15, 14, 13, 12, \
825 /* AltiVec registers. */ \
827 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
829 96, 95, 94, 93, 92, 91, \
830 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
834 /* True if register is floating-point. */
835 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
837 /* True if register is a condition register. */
838 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
840 /* True if register is a condition register, but not cr0. */
841 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
843 /* True if register is an integer register. */
844 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
846 /* True if register is the XER register. */
847 #define XER_REGNO_P(N) ((N) == XER_REGNO)
849 /* True if register is an AltiVec register. */
850 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
852 /* Return number of consecutive hard regs needed starting at reg REGNO
853 to hold something of mode MODE.
854 This is ordinarily the length in words of a value of mode MODE
855 but can be less for certain modes in special long registers.
857 POWER and PowerPC GPRs hold 32 bits worth;
858 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
860 #define HARD_REGNO_NREGS(REGNO, MODE) \
861 (FP_REGNO_P (REGNO) \
862 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
863 : ALTIVEC_REGNO_P (REGNO) \
864 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
865 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
867 #define ALTIVEC_VECTOR_MODE(MODE) \
868 ((MODE) == V16QImode \
869 || (MODE) == V8HImode \
870 || (MODE) == V4SFmode \
871 || (MODE) == V4SImode)
873 /* Define this macro to be nonzero if the port is prepared to handle
874 insns involving vector mode MODE. At the very least, it must have
875 move patterns for this mode. */
877 #define VECTOR_MODE_SUPPORTED_P(MODE) \
878 (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))
880 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
881 For POWER and PowerPC, the GPRs can hold any mode, but the float
882 registers only can hold floating modes and DImode, and CR register only
883 can hold CC modes. We cannot put TImode anywhere except general
884 register and it must be able to fit within the register set. */
886 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
887 (FP_REGNO_P (REGNO) ? \
888 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
889 || (GET_MODE_CLASS (MODE) == MODE_INT \
890 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
891 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
892 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
893 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
894 : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \
895 && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
898 /* Value is 1 if it is a good idea to tie two pseudo registers
899 when one has mode MODE1 and one has mode MODE2.
900 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
901 for any hard reg, then this must be 0 for correct output. */
902 #define MODES_TIEABLE_P(MODE1, MODE2) \
903 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
904 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
905 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
906 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
907 : GET_MODE_CLASS (MODE1) == MODE_CC \
908 ? GET_MODE_CLASS (MODE2) == MODE_CC \
909 : GET_MODE_CLASS (MODE2) == MODE_CC \
910 ? GET_MODE_CLASS (MODE1) == MODE_CC \
911 : ALTIVEC_VECTOR_MODE (MODE1) \
912 ? ALTIVEC_VECTOR_MODE (MODE2) \
913 : ALTIVEC_VECTOR_MODE (MODE2) \
914 ? ALTIVEC_VECTOR_MODE (MODE1) \
917 /* A C expression returning the cost of moving data from a register of class
918 CLASS1 to one of CLASS2.
920 On the RS/6000, copying between floating-point and fixed-point
921 registers is expensive. */
923 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
924 ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \
925 : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10 \
926 : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10 \
927 : (CLASS1) == ALTIVEC_REGS && (CLASS2) != ALTIVEC_REGS ? 20 \
928 : (CLASS1) != ALTIVEC_REGS && (CLASS2) == ALTIVEC_REGS ? 20 \
929 : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS \
930 || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS \
931 || (CLASS1) == LINK_OR_CTR_REGS) \
932 && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \
933 || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS \
934 || (CLASS2) == LINK_OR_CTR_REGS)) ? 10 \
937 /* A C expressions returning the cost of moving data of MODE from a register to
940 On the RS/6000, bump this up a bit. */
942 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
943 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
944 && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \
948 /* Specify the cost of a branch insn; roughly the number of extra insns that
949 should be added to avoid a branch.
951 Set this to 3 on the RS/6000 since that is roughly the average cost of an
952 unscheduled conditional branch. */
954 #define BRANCH_COST 3
956 /* Define this macro to change register usage conditional on target flags.
957 Set MQ register fixed (already call_used) if not POWER architecture
958 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
959 64-bit AIX reserves GPR13 for thread-private data.
960 Conditionally disable FPRs. */
962 #define CONDITIONAL_REGISTER_USAGE \
965 if (! TARGET_POWER) \
966 fixed_regs[64] = 1; \
968 fixed_regs[13] = call_used_regs[13] \
969 = call_really_used_regs[13] = 1; \
970 if (TARGET_SOFT_FLOAT) \
971 for (i = 32; i < 64; i++) \
972 fixed_regs[i] = call_used_regs[i] \
973 = call_really_used_regs[i] = 1; \
974 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1) \
975 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
976 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] \
977 = call_really_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
978 if (DEFAULT_ABI == ABI_DARWIN && flag_pic) \
979 global_regs[PIC_OFFSET_TABLE_REGNUM] \
980 = fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
981 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] \
982 = call_really_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
983 if (! TARGET_ALTIVEC) \
984 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
985 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \
986 if (TARGET_ALTIVEC_ABI) \
987 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
988 call_used_regs[i] = call_really_used_regs[i] = 1; \
991 /* Specify the registers used for certain standard purposes.
992 The values of these macros are register numbers. */
994 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
995 /* #define PC_REGNUM */
997 /* Register to use for pushing function arguments. */
998 #define STACK_POINTER_REGNUM 1
1000 /* Base register for access to local variables of the function. */
1001 #define FRAME_POINTER_REGNUM 31
1003 /* Value should be nonzero if functions must have frame pointers.
1004 Zero means the frame pointer need not be set up (and parms
1005 may be accessed via the stack pointer) in functions that seem suitable.
1006 This is computed in `reload', in reload1.c. */
1007 #define FRAME_POINTER_REQUIRED 0
1009 /* Base register for access to arguments of the function. */
1010 #define ARG_POINTER_REGNUM 67
1012 /* Place to put static chain when calling a function that requires it. */
1013 #define STATIC_CHAIN_REGNUM 11
1015 /* Link register number. */
1016 #define LINK_REGISTER_REGNUM 65
1018 /* Count register number. */
1019 #define COUNT_REGISTER_REGNUM 66
1021 /* Place that structure value return address is placed.
1023 On the RS/6000, it is passed as an extra parameter. */
1024 #define STRUCT_VALUE 0
1026 /* Define the classes of registers for register constraints in the
1027 machine description. Also define ranges of constants.
1029 One of the classes must always be named ALL_REGS and include all hard regs.
1030 If there is more than one class, another class must be named NO_REGS
1031 and contain no registers.
1033 The name GENERAL_REGS must be the name of a class (or an alias for
1034 another name such as ALL_REGS). This is the class of registers
1035 that is allowed by "g" or "r" in a register constraint.
1036 Also, registers outside this class are allocated only when
1037 instructions express preferences for them.
1039 The classes must be numbered in nondecreasing order; that is,
1040 a larger-numbered class must never be contained completely
1041 in a smaller-numbered class.
1043 For any two classes, it is very desirable that there be another
1044 class that represents their union. */
1046 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1047 and condition registers, plus three special registers, MQ, CTR, and the
1050 However, r0 is special in that it cannot be used as a base register.
1051 So make a class for registers valid as base registers.
1053 Also, cr0 is the only condition code register that can be used in
1054 arithmetic insns, so make a separate class for it. */
1079 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1081 /* Give names of register classes as strings for dump file. */
1083 #define REG_CLASS_NAMES \
1091 "NON_SPECIAL_REGS", \
1095 "LINK_OR_CTR_REGS", \
1097 "SPEC_OR_GEN_REGS", \
1105 /* Define which registers fit in which classes.
1106 This is an initializer for a vector of HARD_REG_SET
1107 of length N_REG_CLASSES. */
1109 #define REG_CLASS_CONTENTS \
1111 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1112 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1113 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1114 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1115 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1116 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1117 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1118 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1119 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1120 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1121 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1122 { 0x00000000, 0x00000000, 0x00000007, 0x00000000 }, /* SPECIAL_REGS */ \
1123 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1124 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1125 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1126 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1127 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1128 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1131 /* The same information, inverted:
1132 Return the class number of the smallest class containing
1133 reg number REGNO. This could be a conditional expression
1134 or could index an array. */
1136 #define REGNO_REG_CLASS(REGNO) \
1137 ((REGNO) == 0 ? GENERAL_REGS \
1138 : (REGNO) < 32 ? BASE_REGS \
1139 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1140 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1141 : (REGNO) == CR0_REGNO ? CR0_REGS \
1142 : CR_REGNO_P (REGNO) ? CR_REGS \
1143 : (REGNO) == MQ_REGNO ? MQ_REGS \
1144 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1145 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1146 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1147 : (REGNO) == XER_REGNO ? XER_REGS \
1148 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1151 /* The class value for index registers, and the one for base regs. */
1152 #define INDEX_REG_CLASS GENERAL_REGS
1153 #define BASE_REG_CLASS BASE_REGS
1155 /* Get reg_class from a letter such as appears in the machine description. */
1157 #define REG_CLASS_FROM_LETTER(C) \
1158 ((C) == 'f' ? FLOAT_REGS \
1159 : (C) == 'b' ? BASE_REGS \
1160 : (C) == 'h' ? SPECIAL_REGS \
1161 : (C) == 'q' ? MQ_REGS \
1162 : (C) == 'c' ? CTR_REGS \
1163 : (C) == 'l' ? LINK_REGS \
1164 : (C) == 'v' ? ALTIVEC_REGS \
1165 : (C) == 'x' ? CR0_REGS \
1166 : (C) == 'y' ? CR_REGS \
1167 : (C) == 'z' ? XER_REGS \
1170 /* The letters I, J, K, L, M, N, and P in a register constraint string
1171 can be used to stand for particular ranges of immediate operands.
1172 This macro defines what the ranges are.
1173 C is the letter, and VALUE is a constant value.
1174 Return 1 if VALUE is in the range specified by C.
1176 `I' is a signed 16-bit constant
1177 `J' is a constant with only the high-order 16 bits non-zero
1178 `K' is a constant with only the low-order 16 bits non-zero
1179 `L' is a signed 16-bit constant shifted left 16 bits
1180 `M' is a constant that is greater than 31
1181 `N' is a positive constant that is an exact power of two
1182 `O' is the constant zero
1183 `P' is a constant whose negation is a signed 16-bit constant */
1185 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1186 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1187 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1188 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1189 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1190 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1191 : (C) == 'M' ? (VALUE) > 31 \
1192 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1193 : (C) == 'O' ? (VALUE) == 0 \
1194 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1197 /* Similar, but for floating constants, and defining letters G and H.
1198 Here VALUE is the CONST_DOUBLE rtx itself.
1200 We flag for special constants when we can copy the constant into
1201 a general register in two insns for DF/DI and one insn for SF.
1203 'H' is used for DI/DF constants that take 3 insns. */
1205 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1206 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1207 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1208 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1211 /* Optional extra constraints for this machine.
1213 'Q' means that is a memory operand that is just an offset from a reg.
1214 'R' is for AIX TOC entries.
1215 'S' is a constant that can be placed into a 64-bit mask operand
1216 'T' is a consatnt that can be placed into a 32-bit mask operand
1217 'U' is for V.4 small data references. */
1219 #define EXTRA_CONSTRAINT(OP, C) \
1220 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1221 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
1222 : (C) == 'S' ? mask64_operand (OP, VOIDmode) \
1223 : (C) == 'T' ? mask_operand (OP, VOIDmode) \
1224 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1225 && small_data_operand (OP, GET_MODE (OP))) \
1228 /* Given an rtx X being reloaded into a reg required to be
1229 in class CLASS, return the class of reg to actually use.
1230 In general this is just CLASS; but on some machines
1231 in some cases it is preferable to use a more restrictive class.
1233 On the RS/6000, we have to return NO_REGS when we want to reload a
1234 floating-point CONST_DOUBLE to force it to be copied to memory.
1236 We also don't want to reload integer values into floating-point
1237 registers if we can at all help it. In fact, this can
1238 cause reload to abort, if it tries to generate a reload of CTR
1239 into a FP register and discovers it doesn't have the memory location
1242 ??? Would it be a good idea to have reload do the converse, that is
1243 try to reload floating modes into FP registers if possible?
1246 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1247 (((GET_CODE (X) == CONST_DOUBLE \
1248 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1250 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1251 && (CLASS) == NON_SPECIAL_REGS) \
1255 /* Return the register class of a scratch register needed to copy IN into
1256 or out of a register in CLASS in MODE. If it can be done directly,
1257 NO_REGS is returned. */
1259 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1260 secondary_reload_class (CLASS, MODE, IN)
1262 /* If we are copying between FP or AltiVec registers and anything
1263 else, we need a memory location. */
1265 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1266 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1267 || (CLASS2) == FLOAT_REGS \
1268 || (CLASS1) == ALTIVEC_REGS \
1269 || (CLASS2) == ALTIVEC_REGS))
1271 /* Return the maximum number of consecutive registers
1272 needed to represent mode MODE in a register of class CLASS.
1274 On RS/6000, this is the size of MODE in words,
1275 except in the FP regs, where a single reg is enough for two words. */
1276 #define CLASS_MAX_NREGS(CLASS, MODE) \
1277 (((CLASS) == FLOAT_REGS) \
1278 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1279 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1281 /* If defined, gives a class of registers that cannot be used as the
1282 operand of a SUBREG that changes the mode of the object illegally. */
1284 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
1286 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1288 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1289 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1291 /* Stack layout; function entry, exit and calling. */
1293 /* Enumeration to give which calling sequence to use. */
1296 ABI_AIX, /* IBM's AIX */
1297 ABI_AIX_NODESC, /* AIX calling sequence minus
1298 function descriptors */
1299 ABI_V4, /* System V.4/eabi */
1300 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1303 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1305 /* Structure used to define the rs6000 stack */
1306 typedef struct rs6000_stack {
1307 int first_gp_reg_save; /* first callee saved GP register used */
1308 int first_fp_reg_save; /* first callee saved FP register used */
1309 int first_altivec_reg_save; /* first callee saved AltiVec register used */
1310 int lr_save_p; /* true if the link reg needs to be saved */
1311 int cr_save_p; /* true if the CR reg needs to be saved */
1312 unsigned int vrsave_mask; /* mask of vec registers to save */
1313 int toc_save_p; /* true if the TOC needs to be saved */
1314 int push_p; /* true if we need to allocate stack space */
1315 int calls_p; /* true if the function makes any calls */
1316 enum rs6000_abi abi; /* which ABI to use */
1317 int gp_save_offset; /* offset to save GP regs from initial SP */
1318 int fp_save_offset; /* offset to save FP regs from initial SP */
1319 int altivec_save_offset; /* offset to save AltiVec regs from inital SP */
1320 int lr_save_offset; /* offset to save LR from initial SP */
1321 int cr_save_offset; /* offset to save CR from initial SP */
1322 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
1323 int toc_save_offset; /* offset to save the TOC pointer */
1324 int varargs_save_offset; /* offset to save the varargs registers */
1325 int ehrd_offset; /* offset to EH return data */
1326 int reg_size; /* register size (4 or 8) */
1327 int varargs_size; /* size to hold V.4 args passed in regs */
1328 int vars_size; /* variable save area size */
1329 int parm_size; /* outgoing parameter size */
1330 int save_size; /* save area size */
1331 int fixed_size; /* fixed size of stack frame */
1332 int gp_size; /* size of saved GP registers */
1333 int fp_size; /* size of saved FP registers */
1334 int altivec_size; /* size of saved AltiVec registers */
1335 int cr_size; /* size to hold CR if not in save_size */
1336 int lr_size; /* size to hold LR if not in save_size */
1337 int vrsave_size; /* size to hold VRSAVE if not in save_size */
1338 int altivec_padding_size; /* size of altivec alignment padding if
1340 int toc_size; /* size to hold TOC if not in save_size */
1341 int total_size; /* total bytes allocated for stack */
1344 /* Define this if pushing a word on the stack
1345 makes the stack pointer a smaller address. */
1346 #define STACK_GROWS_DOWNWARD
1348 /* Define this if the nominal address of the stack frame
1349 is at the high-address end of the local variables;
1350 that is, each additional local variable allocated
1351 goes at a more negative offset in the frame.
1353 On the RS/6000, we grow upwards, from the area after the outgoing
1355 /* #define FRAME_GROWS_DOWNWARD */
1357 /* Size of the outgoing register save area */
1358 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1359 || DEFAULT_ABI == ABI_AIX_NODESC \
1360 || DEFAULT_ABI == ABI_DARWIN) \
1361 ? (TARGET_64BIT ? 64 : 32) \
1364 /* Size of the fixed area on the stack */
1365 #define RS6000_SAVE_AREA \
1366 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1367 << (TARGET_64BIT ? 1 : 0))
1369 /* MEM representing address to save the TOC register */
1370 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1371 plus_constant (stack_pointer_rtx, \
1372 (TARGET_32BIT ? 20 : 40)))
1374 /* Size of the V.4 varargs area if needed */
1375 #define RS6000_VARARGS_AREA 0
1377 /* Align an address */
1378 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1380 /* Size of V.4 varargs area in bytes */
1381 #define RS6000_VARARGS_SIZE \
1382 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1384 /* Offset within stack frame to start allocating local variables at.
1385 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1386 first local allocated. Otherwise, it is the offset to the BEGINNING
1387 of the first local allocated.
1389 On the RS/6000, the frame pointer is the same as the stack pointer,
1390 except for dynamic allocations. So we start after the fixed area and
1391 outgoing parameter area. */
1393 #define STARTING_FRAME_OFFSET \
1394 (RS6000_ALIGN (current_function_outgoing_args_size, \
1395 TARGET_ALTIVEC ? 16 : 8) \
1396 + RS6000_VARARGS_AREA \
1399 /* Offset from the stack pointer register to an item dynamically
1400 allocated on the stack, e.g., by `alloca'.
1402 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1403 length of the outgoing arguments. The default is correct for most
1404 machines. See `function.c' for details. */
1405 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1406 (RS6000_ALIGN (current_function_outgoing_args_size, \
1407 TARGET_ALTIVEC ? 16 : 8) \
1408 + (STACK_POINTER_OFFSET))
1410 /* If we generate an insn to push BYTES bytes,
1411 this says how many the stack pointer really advances by.
1412 On RS/6000, don't define this because there are no push insns. */
1413 /* #define PUSH_ROUNDING(BYTES) */
1415 /* Offset of first parameter from the argument pointer register value.
1416 On the RS/6000, we define the argument pointer to the start of the fixed
1418 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1420 /* Offset from the argument pointer register value to the top of
1421 stack. This is different from FIRST_PARM_OFFSET because of the
1422 register save area. */
1423 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1425 /* Define this if stack space is still allocated for a parameter passed
1426 in a register. The value is the number of bytes allocated to this
1428 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1430 /* Define this if the above stack space is to be considered part of the
1431 space allocated by the caller. */
1432 #define OUTGOING_REG_PARM_STACK_SPACE
1434 /* This is the difference between the logical top of stack and the actual sp.
1436 For the RS/6000, sp points past the fixed area. */
1437 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1439 /* Define this if the maximum size of all the outgoing args is to be
1440 accumulated and pushed during the prologue. The amount can be
1441 found in the variable current_function_outgoing_args_size. */
1442 #define ACCUMULATE_OUTGOING_ARGS 1
1444 /* Value is the number of bytes of arguments automatically
1445 popped when returning from a subroutine call.
1446 FUNDECL is the declaration node of the function (as a tree),
1447 FUNTYPE is the data type of the function (as a tree),
1448 or for a library call it is an identifier node for the subroutine name.
1449 SIZE is the number of bytes of arguments passed on the stack. */
1451 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1453 /* Define how to find the value returned by a function.
1454 VALTYPE is the data type of the value (as a tree).
1455 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1456 otherwise, FUNC is 0.
1458 On RS/6000 an integer value is in r3 and a floating-point value is in
1459 fp1, unless -msoft-float. */
1461 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1462 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
1463 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1464 || POINTER_TYPE_P (VALTYPE) \
1465 ? word_mode : TYPE_MODE (VALTYPE), \
1466 TREE_CODE (VALTYPE) == VECTOR_TYPE ? ALTIVEC_ARG_RETURN \
1467 : TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT \
1468 ? FP_ARG_RETURN : GP_ARG_RETURN)
1470 /* Define how to find the value returned by a library function
1471 assuming the value has mode MODE. */
1473 #define LIBCALL_VALUE(MODE) \
1474 gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \
1475 : GET_MODE_CLASS (MODE) == MODE_FLOAT \
1476 && TARGET_HARD_FLOAT \
1477 ? FP_ARG_RETURN : GP_ARG_RETURN)
1479 /* The AIX ABI for the RS/6000 specifies that all structures are
1480 returned in memory. The Darwin ABI does the same. The SVR4 ABI
1481 specifies that structures <= 8 bytes are returned in r3/r4, but a
1482 draft put them in memory, and GCC used to implement the draft
1483 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
1484 controls this instead of DEFAULT_ABI; V.4 targets needing backward
1485 compatibility can change DRAFT_V4_STRUCT_RET to override the
1486 default, and -m switches get the final word. See
1487 rs6000_override_options for more details.
1489 int_size_in_bytes returns -1 for variable size objects, which go in
1490 memory always. The cast to unsigned makes -1 > 8. */
1492 #define RETURN_IN_MEMORY(TYPE) \
1493 (AGGREGATE_TYPE_P (TYPE) && \
1494 (TARGET_AIX_STRUCT_RET || \
1495 (unsigned HOST_WIDEST_INT) int_size_in_bytes (TYPE) > 8))
1497 /* DRAFT_V4_STRUCT_RET defaults off. */
1498 #define DRAFT_V4_STRUCT_RET 0
1500 /* Let RETURN_IN_MEMORY control what happens. */
1501 #define DEFAULT_PCC_STRUCT_RETURN 0
1503 /* Mode of stack savearea.
1504 FUNCTION is VOIDmode because calling convention maintains SP.
1505 BLOCK needs Pmode for SP.
1506 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1507 #define STACK_SAVEAREA_MODE(LEVEL) \
1508 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1509 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1511 /* Minimum and maximum general purpose registers used to hold arguments. */
1512 #define GP_ARG_MIN_REG 3
1513 #define GP_ARG_MAX_REG 10
1514 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1516 /* Minimum and maximum floating point registers used to hold arguments. */
1517 #define FP_ARG_MIN_REG 33
1518 #define FP_ARG_AIX_MAX_REG 45
1519 #define FP_ARG_V4_MAX_REG 40
1520 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1521 || DEFAULT_ABI == ABI_AIX_NODESC \
1522 || DEFAULT_ABI == ABI_DARWIN) \
1523 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1524 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1526 /* Minimum and maximum AltiVec registers used to hold arguments. */
1527 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1528 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1529 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1531 /* Return registers */
1532 #define GP_ARG_RETURN GP_ARG_MIN_REG
1533 #define FP_ARG_RETURN FP_ARG_MIN_REG
1534 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1536 /* Flags for the call/call_value rtl operations set up by function_arg */
1537 #define CALL_NORMAL 0x00000000 /* no special processing */
1538 /* Bits in 0x00000001 are unused. */
1539 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1540 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1541 #define CALL_LONG 0x00000008 /* always call indirect */
1543 /* 1 if N is a possible register number for a function value
1544 as seen by the caller.
1546 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1547 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN \
1548 || ((N) == FP_ARG_RETURN) \
1549 || (TARGET_ALTIVEC && \
1550 (N) == ALTIVEC_ARG_RETURN))
1552 /* 1 if N is a possible register number for function argument passing.
1553 On RS/6000, these are r3-r10 and fp1-fp13.
1554 On AltiVec, v2 - v13 are used for passing vectors. */
1555 #define FUNCTION_ARG_REGNO_P(N) \
1556 ((unsigned)(((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \
1557 || (TARGET_ALTIVEC && \
1558 (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_NUM_REG)) \
1559 || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))
1562 /* A C structure for machine-specific, per-function data.
1563 This is added to the cfun structure. */
1564 typedef struct machine_function
1566 /* Whether a System V.4 varargs area was created. */
1568 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1569 int ra_needs_full_frame;
1572 /* Define a data type for recording info about an argument list
1573 during the scan of that argument list. This data type should
1574 hold all necessary information about the function itself
1575 and about the args processed so far, enough to enable macros
1576 such as FUNCTION_ARG to determine where the next arg should go.
1578 On the RS/6000, this is a structure. The first element is the number of
1579 total argument words, the second is used to store the next
1580 floating-point register number, and the third says how many more args we
1581 have prototype types for.
1583 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1584 the next availible GP register, `fregno' is the next available FP
1585 register, and `words' is the number of words used on the stack.
1587 The varargs/stdarg support requires that this structure's size
1588 be a multiple of sizeof(int). */
1590 typedef struct rs6000_args
1592 int words; /* # words used for passing GP registers */
1593 int fregno; /* next available FP register */
1594 int vregno; /* next available AltiVec register */
1595 int nargs_prototype; /* # args left in the current prototype */
1596 int orig_nargs; /* Original value of nargs_prototype */
1597 int prototype; /* Whether a prototype was defined */
1598 int call_cookie; /* Do special things for this call */
1599 int sysv_gregno; /* next available GP register */
1602 /* Define intermediate macro to compute the size (in registers) of an argument
1605 #define RS6000_ARG_SIZE(MODE, TYPE) \
1606 ((MODE) != BLKmode \
1607 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1608 : ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1609 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1611 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1612 for a call to a function whose data type is FNTYPE.
1613 For a library call, FNTYPE is 0. */
1615 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1616 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
1618 /* Similar, but when scanning the definition of a procedure. We always
1619 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1621 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1622 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
1624 /* Update the data in CUM to advance over an argument
1625 of mode MODE and data type TYPE.
1626 (TYPE is null for libcalls where that information may not be available.) */
1628 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1629 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1631 /* Non-zero if we can use a floating-point register to pass this arg. */
1632 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1633 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1634 && (CUM).fregno <= FP_ARG_MAX_REG \
1635 && TARGET_HARD_FLOAT)
1637 /* Non-zero if we can use an AltiVec register to pass this arg. */
1638 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \
1639 (ALTIVEC_VECTOR_MODE (MODE) \
1640 && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \
1641 && TARGET_ALTIVEC_ABI)
1643 /* Determine where to put an argument to a function.
1644 Value is zero to push the argument on the stack,
1645 or a hard register in which to store the argument.
1647 MODE is the argument's machine mode.
1648 TYPE is the data type of the argument (as a tree).
1649 This is null for libcalls where that information may
1651 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1652 the preceding args and about the function being called.
1653 NAMED is nonzero if this argument is a named parameter
1654 (otherwise it is an extra parameter matching an ellipsis).
1656 On RS/6000 the first eight words of non-FP are normally in registers
1657 and the rest are pushed. The first 13 FP args are in registers.
1659 If this is floating-point and no prototype is specified, we use
1660 both an FP and integer register (or possibly FP reg and stack). Library
1661 functions (when TYPE is zero) always have the proper types for args,
1662 so we can pass the FP value just in one register. emit_library_function
1663 doesn't support EXPR_LIST anyway. */
1665 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1666 function_arg (&CUM, MODE, TYPE, NAMED)
1668 /* For an arg passed partly in registers and partly in memory,
1669 this is the number of registers used.
1670 For args passed entirely in registers or entirely in memory, zero. */
1672 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1673 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1675 /* A C expression that indicates when an argument must be passed by
1676 reference. If nonzero for an argument, a copy of that argument is
1677 made in memory and a pointer to the argument is passed instead of
1678 the argument itself. The pointer is passed in whatever way is
1679 appropriate for passing a pointer to that type. */
1681 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1682 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1684 /* If defined, a C expression which determines whether, and in which
1685 direction, to pad out an argument with extra space. The value
1686 should be of type `enum direction': either `upward' to pad above
1687 the argument, `downward' to pad below, or `none' to inhibit
1690 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1692 /* If defined, a C expression that gives the alignment boundary, in bits,
1693 of an argument with the specified mode and type. If it is not defined,
1694 PARM_BOUNDARY is used for all arguments. */
1696 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1697 function_arg_boundary (MODE, TYPE)
1699 /* Perform any needed actions needed for a function that is receiving a
1700 variable number of arguments.
1704 MODE and TYPE are the mode and type of the current parameter.
1706 PRETEND_SIZE is a variable that should be set to the amount of stack
1707 that must be pushed by the prolog to pretend that our caller pushed
1710 Normally, this macro will push all remaining incoming registers on the
1711 stack and set PRETEND_SIZE to the length of the registers pushed. */
1713 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1714 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1716 /* Define the `__builtin_va_list' type for the ABI. */
1717 #define BUILD_VA_LIST_TYPE(VALIST) \
1718 (VALIST) = rs6000_build_va_list ()
1720 /* Implement `va_start' for varargs and stdarg. */
1721 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1722 rs6000_va_start (stdarg, valist, nextarg)
1724 /* Implement `va_arg'. */
1725 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1726 rs6000_va_arg (valist, type)
1728 /* Define this macro to be a nonzero value if the location where a function
1729 argument is passed depends on whether or not it is a named argument. */
1730 #define STRICT_ARGUMENT_NAMING 1
1732 /* Output assembler code to FILE to increment profiler label # LABELNO
1733 for profiling a function entry. */
1735 #define FUNCTION_PROFILER(FILE, LABELNO) \
1736 output_function_profiler ((FILE), (LABELNO));
1738 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1739 the stack pointer does not matter. No definition is equivalent to
1742 On the RS/6000, this is non-zero because we can restore the stack from
1743 its backpointer, which we maintain. */
1744 #define EXIT_IGNORE_STACK 1
1746 /* Define this macro as a C expression that is nonzero for registers
1747 that are used by the epilogue or the return' pattern. The stack
1748 and frame pointer registers are already be assumed to be used as
1751 #define EPILOGUE_USES(REGNO) \
1752 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1753 || (REGNO) == VRSAVE_REGNO \
1754 || (current_function_calls_eh_return \
1756 && (REGNO) == TOC_REGISTER))
1759 /* TRAMPOLINE_TEMPLATE deleted */
1761 /* Length in units of the trampoline for entering a nested function. */
1763 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1765 /* Emit RTL insns to initialize the variable parts of a trampoline.
1766 FNADDR is an RTX for the address of the function's pure code.
1767 CXT is an RTX for the static chain value for the function. */
1769 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1770 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1772 /* Definitions for __builtin_return_address and __builtin_frame_address.
1773 __builtin_return_address (0) should give link register (65), enable
1775 /* This should be uncommented, so that the link register is used, but
1776 currently this would result in unmatched insns and spilling fixed
1777 registers so we'll leave it for another day. When these problems are
1778 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1780 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1782 /* Number of bytes into the frame return addresses can be found. See
1783 rs6000_stack_info in rs6000.c for more information on how the different
1784 abi's store the return address. */
1785 #define RETURN_ADDRESS_OFFSET \
1786 ((DEFAULT_ABI == ABI_AIX \
1787 || DEFAULT_ABI == ABI_DARWIN \
1788 || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \
1789 (DEFAULT_ABI == ABI_V4) ? (TARGET_32BIT ? 4 : 8) : \
1790 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1792 /* The current return address is in link register (65). The return address
1793 of anything farther back is accessed normally at an offset of 8 from the
1795 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1796 (rs6000_return_addr (COUNT, FRAME))
1799 /* Definitions for register eliminations.
1801 We have two registers that can be eliminated on the RS/6000. First, the
1802 frame pointer register can often be eliminated in favor of the stack
1803 pointer register. Secondly, the argument pointer register can always be
1804 eliminated; it is replaced with either the stack or frame pointer.
1806 In addition, we use the elimination mechanism to see if r30 is needed
1807 Initially we assume that it isn't. If it is, we spill it. This is done
1808 by making it an eliminable register. We replace it with itself so that
1809 if it isn't needed, then existing uses won't be modified. */
1811 /* This is an array of structures. Each structure initializes one pair
1812 of eliminable registers. The "from" register number is given first,
1813 followed by "to". Eliminations of the same "from" register are listed
1814 in order of preference. */
1815 #define ELIMINABLE_REGS \
1816 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1817 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1818 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1821 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1822 Frame pointer elimination is automatically handled.
1824 For the RS/6000, if frame pointer elimination is being done, we would like
1825 to convert ap into fp, not sp.
1827 We need r30 if -mminimal-toc was specified, and there are constant pool
1830 #define CAN_ELIMINATE(FROM, TO) \
1831 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1832 ? ! frame_pointer_needed \
1833 : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1836 /* Define the offset between two registers, one to be eliminated, and the other
1837 its replacement, at the start of a routine. */
1838 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1840 rs6000_stack_t *info = rs6000_stack_info (); \
1842 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1843 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
1844 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1845 (OFFSET) = info->total_size; \
1846 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1847 (OFFSET) = (info->push_p) ? info->total_size : 0; \
1848 else if ((FROM) == 30) \
1854 /* Addressing modes, and classification of registers for them. */
1856 /* #define HAVE_POST_INCREMENT 0 */
1857 /* #define HAVE_POST_DECREMENT 0 */
1859 #define HAVE_PRE_DECREMENT 1
1860 #define HAVE_PRE_INCREMENT 1
1862 /* Macros to check register numbers against specific register classes. */
1864 /* These assume that REGNO is a hard or pseudo reg number.
1865 They give nonzero only if REGNO is a hard reg of the suitable class
1866 or a pseudo reg currently allocated to a suitable hard reg.
1867 Since they use reg_renumber, they are safe only once reg_renumber
1868 has been allocated, which happens in local-alloc.c. */
1870 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1871 ((REGNO) < FIRST_PSEUDO_REGISTER \
1872 ? (REGNO) <= 31 || (REGNO) == 67 \
1873 : (reg_renumber[REGNO] >= 0 \
1874 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1876 #define REGNO_OK_FOR_BASE_P(REGNO) \
1877 ((REGNO) < FIRST_PSEUDO_REGISTER \
1878 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1879 : (reg_renumber[REGNO] > 0 \
1880 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1882 /* Maximum number of registers that can appear in a valid memory address. */
1884 #define MAX_REGS_PER_ADDRESS 2
1886 /* Recognize any constant value that is a valid address. */
1888 #define CONSTANT_ADDRESS_P(X) \
1889 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1890 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1891 || GET_CODE (X) == HIGH)
1893 /* Nonzero if the constant value X is a legitimate general operand.
1894 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1896 On the RS/6000, all integer constants are acceptable, most won't be valid
1897 for particular insns, though. Only easy FP constants are
1900 #define LEGITIMATE_CONSTANT_P(X) \
1901 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1902 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1903 || easy_fp_constant (X, GET_MODE (X)))
1905 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1906 and check its validity for a certain class.
1907 We have two alternate definitions for each of them.
1908 The usual definition accepts all pseudo regs; the other rejects
1909 them unless they have been allocated suitable hard regs.
1910 The symbol REG_OK_STRICT causes the latter definition to be used.
1912 Most source files want to accept pseudo regs in the hope that
1913 they will get allocated to the class that the insn wants them to be in.
1914 Source files for reload pass need to be strict.
1915 After reload, it makes no difference, since pseudo regs have
1916 been eliminated by then. */
1918 #ifdef REG_OK_STRICT
1919 # define REG_OK_STRICT_FLAG 1
1921 # define REG_OK_STRICT_FLAG 0
1924 /* Nonzero if X is a hard reg that can be used as an index
1925 or if it is a pseudo reg in the non-strict case. */
1926 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1928 && (REGNO (X) <= 31 \
1929 || REGNO (X) == ARG_POINTER_REGNUM \
1930 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1931 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1933 /* Nonzero if X is a hard reg that can be used as a base reg
1934 or if it is a pseudo reg in the non-strict case. */
1935 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1936 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1938 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1939 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1941 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1942 that is a valid memory address for an instruction.
1943 The MODE argument is the machine mode for the MEM expression
1944 that wants to use this address.
1946 On the RS/6000, there are four valid address: a SYMBOL_REF that
1947 refers to a constant pool entry of an address (or the sum of it
1948 plus a constant), a short (16-bit signed) constant plus a register,
1949 the sum of two registers, or a register indirect, possibly with an
1950 auto-increment. For DFmode and DImode with an constant plus register,
1951 we must ensure that both words are addressable or PowerPC64 with offset
1954 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1955 32-bit DImode, TImode), indexed addressing cannot be used because
1956 adjacent memory cells are accessed by adding word-sized offsets
1957 during assembly output. */
1959 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X))
1961 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X))
1963 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \
1965 && GET_CODE (X) == PLUS \
1966 && GET_CODE (XEXP (X, 0)) == REG \
1967 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \
1968 && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))
1970 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \
1971 (DEFAULT_ABI == ABI_V4 \
1972 && !flag_pic && !TARGET_TOC \
1973 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \
1974 && small_data_operand (X, MODE))
1976 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \
1977 (GET_CODE (X) == CONST_INT \
1978 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
1980 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \
1981 (GET_CODE (X) == PLUS \
1982 && GET_CODE (XEXP (X, 0)) == REG \
1983 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1984 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \
1985 && (! ALTIVEC_VECTOR_MODE (MODE) || INTVAL (X) == 0) \
1986 && (((MODE) != DFmode && (MODE) != DImode) \
1988 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
1989 : ! (INTVAL (XEXP (X, 1)) & 3))) \
1990 && ((MODE) != TImode \
1992 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
1993 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
1994 && ! (INTVAL (XEXP (X, 1)) & 3)))))
1996 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \
1997 (GET_CODE (X) == PLUS \
1998 && GET_CODE (XEXP (X, 0)) == REG \
1999 && GET_CODE (XEXP (X, 1)) == REG \
2000 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2001 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
2002 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \
2003 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))
2005 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \
2006 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
2008 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \
2010 && ! flag_pic && ! TARGET_TOC \
2011 && GET_MODE_NUNITS (MODE) == 1 \
2012 && (GET_MODE_BITSIZE (MODE) <= 32 \
2013 || (TARGET_HARD_FLOAT && (MODE) == DFmode)) \
2014 && GET_CODE (X) == LO_SUM \
2015 && GET_CODE (XEXP (X, 0)) == REG \
2016 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2017 && CONSTANT_P (XEXP (X, 1)))
2019 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2020 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
2024 /* Try machine-dependent ways of modifying an illegitimate address
2025 to be legitimate. If we find one, return the new, valid address.
2026 This macro is used in only one place: `memory_address' in explow.c.
2028 OLDX is the address as it was before break_out_memory_refs was called.
2029 In some cases it is useful to look at this to decide what needs to be done.
2031 MODE and WIN are passed so that this macro can use
2032 GO_IF_LEGITIMATE_ADDRESS.
2034 It is always safe for this macro to do nothing. It exists to recognize
2035 opportunities to optimize the output.
2037 On RS/6000, first check for the sum of a register with a constant
2038 integer that is out of range. If so, generate code to add the
2039 constant with the low-order 16 bits masked to the register and force
2040 this result into another register (this can be done with `cau').
2041 Then generate an address of REG+(CONST&0xffff), allowing for the
2042 possibility of bit 16 being a one.
2044 Then check for the sum of a register and something not constant, try to
2045 load the other things into a register and return the sum. */
2047 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2048 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2049 if (result != NULL_RTX) \
2056 /* Try a machine-dependent way of reloading an illegitimate address
2057 operand. If we find one, push the reload and jump to WIN. This
2058 macro is used in only one place: `find_reloads_address' in reload.c.
2060 For RS/6000, we wish to handle large displacements off a base
2061 register by splitting the addend across an addiu/addis and the mem insn.
2062 This cuts number of extra insns needed from 3 to 1. */
2064 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2066 /* We must recognize output that we have already generated ourselves. */ \
2067 if (GET_CODE (X) == PLUS \
2068 && GET_CODE (XEXP (X, 0)) == PLUS \
2069 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
2070 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2071 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2073 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2074 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2078 if (GET_CODE (X) == PLUS \
2079 && GET_CODE (XEXP (X, 0)) == REG \
2080 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
2081 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
2082 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2084 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2085 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
2086 HOST_WIDE_INT high \
2087 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
2089 /* Check for 32-bit overflow. */ \
2090 if (high + low != val) \
2093 /* Reload the high part into a base reg; leave the low part \
2094 in the mem directly. */ \
2096 X = gen_rtx_PLUS (GET_MODE (X), \
2097 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
2101 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2102 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2106 else if (TARGET_TOC \
2107 && CONSTANT_POOL_EXPR_P (X) \
2108 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (X), MODE)) \
2110 (X) = create_TOC_reference (X); \
2115 /* Go to LABEL if ADDR (a legitimate address expression)
2116 has an effect that depends on the machine mode it is used for.
2118 On the RS/6000 this is true if the address is valid with a zero offset
2119 but not with an offset of four (this means it cannot be used as an
2120 address for DImode or DFmode) or is a pre-increment or decrement. Since
2121 we know it is valid, we just check for an address that is not valid with
2122 an offset of four. */
2124 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2125 { if (GET_CODE (ADDR) == PLUS \
2126 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
2127 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \
2128 (TARGET_32BIT ? 4 : 8))) \
2130 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \
2132 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \
2134 if (GET_CODE (ADDR) == LO_SUM) \
2138 /* The register number of the register used to address a table of
2139 static data addresses in memory. In some cases this register is
2140 defined by a processor's "application binary interface" (ABI).
2141 When this macro is defined, RTL is generated for this register
2142 once, as with the stack pointer and frame pointer registers. If
2143 this macro is not defined, it is up to the machine-dependent files
2144 to allocate such a register (if necessary). */
2146 #define PIC_OFFSET_TABLE_REGNUM 30
2148 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? 30 : 2)
2150 /* Define this macro if the register defined by
2151 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2152 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2154 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2156 /* By generating position-independent code, when two different
2157 programs (A and B) share a common library (libC.a), the text of
2158 the library can be shared whether or not the library is linked at
2159 the same address for both programs. In some of these
2160 environments, position-independent code requires not only the use
2161 of different addressing modes, but also special code to enable the
2162 use of these addressing modes.
2164 The `FINALIZE_PIC' macro serves as a hook to emit these special
2165 codes once the function is being compiled into assembly code, but
2166 not before. (It is not done before, because in the case of
2167 compiling an inline function, it would lead to multiple PIC
2168 prologues being included in functions which used inline functions
2169 and were compiled to assembly language.) */
2171 /* #define FINALIZE_PIC */
2173 /* A C expression that is nonzero if X is a legitimate immediate
2174 operand on the target machine when generating position independent
2175 code. You can assume that X satisfies `CONSTANT_P', so you need
2176 not check this. You can also assume FLAG_PIC is true, so you need
2177 not check it either. You need not define this macro if all
2178 constants (including `SYMBOL_REF') can be immediate operands when
2179 generating position independent code. */
2181 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2183 /* In rare cases, correct code generation requires extra machine
2184 dependent processing between the second jump optimization pass and
2185 delayed branch scheduling. On those machines, define this macro
2186 as a C statement to act on the code starting at INSN. */
2188 /* #define MACHINE_DEPENDENT_REORG(INSN) */
2191 /* Define this if some processing needs to be done immediately before
2192 emitting code for an insn. */
2194 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2196 /* Specify the machine mode that this machine uses
2197 for the index in the tablejump instruction. */
2198 #define CASE_VECTOR_MODE SImode
2200 /* Define as C expression which evaluates to nonzero if the tablejump
2201 instruction expects the table to contain offsets from the address of the
2203 Do not define this if the table should contain absolute addresses. */
2204 #define CASE_VECTOR_PC_RELATIVE 1
2206 /* Specify the tree operation to be used to convert reals to integers. */
2207 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2209 /* This is the kind of divide that is easiest to do in the general case. */
2210 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2212 /* Define this as 1 if `char' should by default be signed; else as 0. */
2213 #define DEFAULT_SIGNED_CHAR 0
2215 /* This flag, if defined, says the same insns that convert to a signed fixnum
2216 also convert validly to an unsigned one. */
2218 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2220 /* Max number of bytes we can move from memory to memory
2221 in one reasonably fast instruction. */
2222 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2223 #define MAX_MOVE_MAX 8
2225 /* Nonzero if access to memory by bytes is no faster than for words.
2226 Also non-zero if doing byte operations (specifically shifts) in registers
2228 #define SLOW_BYTE_ACCESS 1
2230 /* Define if operations between registers always perform the operation
2231 on the full register even if a narrower mode is specified. */
2232 #define WORD_REGISTER_OPERATIONS
2234 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2235 will either zero-extend or sign-extend. The value of this macro should
2236 be the code that says which one of the two operations is implicitly
2237 done, NIL if none. */
2238 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2240 /* Define if loading short immediate values into registers sign extends. */
2241 #define SHORT_IMMEDIATES_SIGN_EXTEND
2243 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2244 is done just by pretending it is already truncated. */
2245 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2247 /* Specify the machine mode that pointers have.
2248 After generation of rtl, the compiler makes no further distinction
2249 between pointers and any other objects of this machine mode. */
2250 #define Pmode (TARGET_32BIT ? SImode : DImode)
2252 /* Mode of a function address in a call instruction (for indexing purposes).
2253 Doesn't matter on RS/6000. */
2254 #define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode)
2256 /* Define this if addresses of constant functions
2257 shouldn't be put through pseudo regs where they can be cse'd.
2258 Desirable on machines where ordinary constants are expensive
2259 but a CALL with constant address is cheap. */
2260 #define NO_FUNCTION_CSE
2262 /* Define this to be nonzero if shift instructions ignore all but the low-order
2265 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2266 have been dropped from the PowerPC architecture. */
2268 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2270 /* Compute the cost of computing a constant rtl expression RTX
2271 whose rtx-code is CODE. The body of this macro is a portion
2272 of a switch statement. If the code is computed here,
2273 return it with a return statement. Otherwise, break from the switch.
2275 On the RS/6000, if it is valid in the insn, it is free. So this
2276 always returns 0. */
2278 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2283 case CONST_DOUBLE: \
2287 /* Provide the costs of a rtl expression. This is in the body of a
2290 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2292 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2293 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) \
2294 + 0x8000) >= 0x10000) \
2295 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2296 ? COSTS_N_INSNS (2) \
2297 : COSTS_N_INSNS (1)); \
2301 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2302 && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \
2303 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2304 ? COSTS_N_INSNS (2) \
2305 : COSTS_N_INSNS (1)); \
2307 switch (rs6000_cpu) \
2309 case PROCESSOR_RIOS1: \
2310 case PROCESSOR_PPC405: \
2311 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2312 ? COSTS_N_INSNS (5) \
2313 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2314 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2315 case PROCESSOR_RS64A: \
2316 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2317 ? GET_MODE (XEXP (X, 1)) != DImode \
2318 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \
2319 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2320 ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12)); \
2321 case PROCESSOR_RIOS2: \
2322 case PROCESSOR_MPCCORE: \
2323 case PROCESSOR_PPC604e: \
2324 return COSTS_N_INSNS (2); \
2325 case PROCESSOR_PPC601: \
2326 return COSTS_N_INSNS (5); \
2327 case PROCESSOR_PPC603: \
2328 case PROCESSOR_PPC7400: \
2329 case PROCESSOR_PPC7450: \
2330 case PROCESSOR_PPC750: \
2331 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2332 ? COSTS_N_INSNS (5) \
2333 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2334 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
2335 case PROCESSOR_PPC403: \
2336 case PROCESSOR_PPC604: \
2337 return COSTS_N_INSNS (4); \
2338 case PROCESSOR_PPC620: \
2339 case PROCESSOR_PPC630: \
2340 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2341 ? GET_MODE (XEXP (X, 1)) != DImode \
2342 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) \
2343 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2344 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2348 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2349 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
2350 return COSTS_N_INSNS (2); \
2351 /* otherwise fall through to normal divide. */ \
2354 switch (rs6000_cpu) \
2356 case PROCESSOR_RIOS1: \
2357 return COSTS_N_INSNS (19); \
2358 case PROCESSOR_RIOS2: \
2359 return COSTS_N_INSNS (13); \
2360 case PROCESSOR_RS64A: \
2361 return (GET_MODE (XEXP (X, 1)) != DImode \
2362 ? COSTS_N_INSNS (65) \
2363 : COSTS_N_INSNS (67)); \
2364 case PROCESSOR_MPCCORE: \
2365 return COSTS_N_INSNS (6); \
2366 case PROCESSOR_PPC403: \
2367 return COSTS_N_INSNS (33); \
2368 case PROCESSOR_PPC405: \
2369 return COSTS_N_INSNS (35); \
2370 case PROCESSOR_PPC601: \
2371 return COSTS_N_INSNS (36); \
2372 case PROCESSOR_PPC603: \
2373 return COSTS_N_INSNS (37); \
2374 case PROCESSOR_PPC604: \
2375 case PROCESSOR_PPC604e: \
2376 return COSTS_N_INSNS (20); \
2377 case PROCESSOR_PPC620: \
2378 case PROCESSOR_PPC630: \
2379 return (GET_MODE (XEXP (X, 1)) != DImode \
2380 ? COSTS_N_INSNS (21) \
2381 : COSTS_N_INSNS (37)); \
2382 case PROCESSOR_PPC750: \
2383 case PROCESSOR_PPC7400: \
2384 return COSTS_N_INSNS (19); \
2385 case PROCESSOR_PPC7450: \
2386 return COSTS_N_INSNS (23); \
2389 return COSTS_N_INSNS (4); \
2391 /* MEM should be slightly more expensive than (plus (reg) (const)) */ \
2394 /* Compute the cost of an address. This is meant to approximate the size
2395 and/or execution delay of an insn using that address. If the cost is
2396 approximated by the RTL complexity, including CONST_COSTS above, as
2397 is usually the case for CISC machines, this macro should not be defined.
2398 For aggressively RISCy machines, only one insn format is allowed, so
2399 this macro should be a constant. The value of this macro only matters
2400 for valid addresses.
2402 For the RS/6000, everything is cost 0. */
2404 #define ADDRESS_COST(RTX) 0
2406 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2407 should be adjusted to reflect any required changes. This macro is used when
2408 there is some systematic length adjustment required that would be difficult
2409 to express in the length attribute. */
2411 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2413 /* Add any extra modes needed to represent the condition code.
2415 For the RS/6000, we need separate modes when unsigned (logical) comparisons
2416 are being done and we need a separate mode for floating-point. We also
2417 use a mode for the case when we are comparing the results of two
2418 comparisons, as then only the EQ bit is valid in the register. */
2420 #define EXTRA_CC_MODES \
2421 CC(CCUNSmode, "CCUNS") \
2422 CC(CCFPmode, "CCFP") \
2423 CC(CCEQmode, "CCEQ")
2425 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2426 COMPARE, return the mode to be used for the comparison. For
2427 floating-point, CCFPmode should be used. CCUNSmode should be used
2428 for unsigned comparisons. CCEQmode should be used when we are
2429 doing an inequality comparison on the result of a
2430 comparison. CCmode should be used in all other cases. */
2432 #define SELECT_CC_MODE(OP,X,Y) \
2433 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2434 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2435 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2436 ? CCEQmode : CCmode))
2438 /* Define the information needed to generate branch and scc insns. This is
2439 stored from the compare operation. Note that we can't use "rtx" here
2440 since it hasn't been defined! */
2442 extern struct rtx_def *rs6000_compare_op0, *rs6000_compare_op1;
2443 extern int rs6000_compare_fp_p;
2445 /* Control the assembler format that we output. */
2447 /* A C string constant describing how to begin a comment in the target
2448 assembler language. The compiler assumes that the comment will end at
2449 the end of the line. */
2450 #define ASM_COMMENT_START " #"
2452 /* Implicit library calls should use memcpy, not bcopy, etc. */
2454 #define TARGET_MEM_FUNCTIONS
2456 /* Flag to say the TOC is initialized */
2457 extern int toc_initialized;
2459 /* Macro to output a special constant pool entry. Go to WIN if we output
2460 it. Otherwise, it is written the usual way.
2462 On the RS/6000, toc entries are handled this way. */
2464 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2465 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2467 output_toc (FILE, X, LABELNO, MODE); \
2472 #ifdef HAVE_GAS_WEAK
2473 #define RS6000_WEAK 1
2475 #define RS6000_WEAK 0
2478 /* This implementes the `alias' attribute. */
2479 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE,decl,target) \
2481 const char * alias = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2482 char * name = IDENTIFIER_POINTER (target); \
2483 if (TREE_CODE (decl) == FUNCTION_DECL \
2484 && DEFAULT_ABI == ABI_AIX) \
2486 if (TREE_PUBLIC (decl)) \
2488 if (RS6000_WEAK && DECL_WEAK (decl)) \
2490 fputs ("\t.weak .", FILE); \
2491 assemble_name (FILE, alias); \
2492 putc ('\n', FILE); \
2496 fputs ("\t.globl .", FILE); \
2497 assemble_name (FILE, alias); \
2498 putc ('\n', FILE); \
2503 fputs ("\t.lglobl .", FILE); \
2504 assemble_name (FILE, alias); \
2505 putc ('\n', FILE); \
2507 fputs ("\t.set .", FILE); \
2508 assemble_name (FILE, alias); \
2509 fputs (",.", FILE); \
2510 assemble_name (FILE, name); \
2511 fputc ('\n', FILE); \
2513 ASM_OUTPUT_DEF (FILE, alias, name); \
2516 /* Output to assembler file text saying following lines
2517 may contain character constants, extra white space, comments, etc. */
2519 #define ASM_APP_ON ""
2521 /* Output to assembler file text saying following lines
2522 no longer contain unusual constructs. */
2524 #define ASM_APP_OFF ""
2526 /* How to refer to registers in assembler output.
2527 This sequence is indexed by compiler's hard-register-number (see above). */
2529 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2531 #define REGISTER_NAMES \
2533 &rs6000_reg_names[ 0][0], /* r0 */ \
2534 &rs6000_reg_names[ 1][0], /* r1 */ \
2535 &rs6000_reg_names[ 2][0], /* r2 */ \
2536 &rs6000_reg_names[ 3][0], /* r3 */ \
2537 &rs6000_reg_names[ 4][0], /* r4 */ \
2538 &rs6000_reg_names[ 5][0], /* r5 */ \
2539 &rs6000_reg_names[ 6][0], /* r6 */ \
2540 &rs6000_reg_names[ 7][0], /* r7 */ \
2541 &rs6000_reg_names[ 8][0], /* r8 */ \
2542 &rs6000_reg_names[ 9][0], /* r9 */ \
2543 &rs6000_reg_names[10][0], /* r10 */ \
2544 &rs6000_reg_names[11][0], /* r11 */ \
2545 &rs6000_reg_names[12][0], /* r12 */ \
2546 &rs6000_reg_names[13][0], /* r13 */ \
2547 &rs6000_reg_names[14][0], /* r14 */ \
2548 &rs6000_reg_names[15][0], /* r15 */ \
2549 &rs6000_reg_names[16][0], /* r16 */ \
2550 &rs6000_reg_names[17][0], /* r17 */ \
2551 &rs6000_reg_names[18][0], /* r18 */ \
2552 &rs6000_reg_names[19][0], /* r19 */ \
2553 &rs6000_reg_names[20][0], /* r20 */ \
2554 &rs6000_reg_names[21][0], /* r21 */ \
2555 &rs6000_reg_names[22][0], /* r22 */ \
2556 &rs6000_reg_names[23][0], /* r23 */ \
2557 &rs6000_reg_names[24][0], /* r24 */ \
2558 &rs6000_reg_names[25][0], /* r25 */ \
2559 &rs6000_reg_names[26][0], /* r26 */ \
2560 &rs6000_reg_names[27][0], /* r27 */ \
2561 &rs6000_reg_names[28][0], /* r28 */ \
2562 &rs6000_reg_names[29][0], /* r29 */ \
2563 &rs6000_reg_names[30][0], /* r30 */ \
2564 &rs6000_reg_names[31][0], /* r31 */ \
2566 &rs6000_reg_names[32][0], /* fr0 */ \
2567 &rs6000_reg_names[33][0], /* fr1 */ \
2568 &rs6000_reg_names[34][0], /* fr2 */ \
2569 &rs6000_reg_names[35][0], /* fr3 */ \
2570 &rs6000_reg_names[36][0], /* fr4 */ \
2571 &rs6000_reg_names[37][0], /* fr5 */ \
2572 &rs6000_reg_names[38][0], /* fr6 */ \
2573 &rs6000_reg_names[39][0], /* fr7 */ \
2574 &rs6000_reg_names[40][0], /* fr8 */ \
2575 &rs6000_reg_names[41][0], /* fr9 */ \
2576 &rs6000_reg_names[42][0], /* fr10 */ \
2577 &rs6000_reg_names[43][0], /* fr11 */ \
2578 &rs6000_reg_names[44][0], /* fr12 */ \
2579 &rs6000_reg_names[45][0], /* fr13 */ \
2580 &rs6000_reg_names[46][0], /* fr14 */ \
2581 &rs6000_reg_names[47][0], /* fr15 */ \
2582 &rs6000_reg_names[48][0], /* fr16 */ \
2583 &rs6000_reg_names[49][0], /* fr17 */ \
2584 &rs6000_reg_names[50][0], /* fr18 */ \
2585 &rs6000_reg_names[51][0], /* fr19 */ \
2586 &rs6000_reg_names[52][0], /* fr20 */ \
2587 &rs6000_reg_names[53][0], /* fr21 */ \
2588 &rs6000_reg_names[54][0], /* fr22 */ \
2589 &rs6000_reg_names[55][0], /* fr23 */ \
2590 &rs6000_reg_names[56][0], /* fr24 */ \
2591 &rs6000_reg_names[57][0], /* fr25 */ \
2592 &rs6000_reg_names[58][0], /* fr26 */ \
2593 &rs6000_reg_names[59][0], /* fr27 */ \
2594 &rs6000_reg_names[60][0], /* fr28 */ \
2595 &rs6000_reg_names[61][0], /* fr29 */ \
2596 &rs6000_reg_names[62][0], /* fr30 */ \
2597 &rs6000_reg_names[63][0], /* fr31 */ \
2599 &rs6000_reg_names[64][0], /* mq */ \
2600 &rs6000_reg_names[65][0], /* lr */ \
2601 &rs6000_reg_names[66][0], /* ctr */ \
2602 &rs6000_reg_names[67][0], /* ap */ \
2604 &rs6000_reg_names[68][0], /* cr0 */ \
2605 &rs6000_reg_names[69][0], /* cr1 */ \
2606 &rs6000_reg_names[70][0], /* cr2 */ \
2607 &rs6000_reg_names[71][0], /* cr3 */ \
2608 &rs6000_reg_names[72][0], /* cr4 */ \
2609 &rs6000_reg_names[73][0], /* cr5 */ \
2610 &rs6000_reg_names[74][0], /* cr6 */ \
2611 &rs6000_reg_names[75][0], /* cr7 */ \
2613 &rs6000_reg_names[76][0], /* xer */ \
2615 &rs6000_reg_names[77][0], /* v0 */ \
2616 &rs6000_reg_names[78][0], /* v1 */ \
2617 &rs6000_reg_names[79][0], /* v2 */ \
2618 &rs6000_reg_names[80][0], /* v3 */ \
2619 &rs6000_reg_names[81][0], /* v4 */ \
2620 &rs6000_reg_names[82][0], /* v5 */ \
2621 &rs6000_reg_names[83][0], /* v6 */ \
2622 &rs6000_reg_names[84][0], /* v7 */ \
2623 &rs6000_reg_names[85][0], /* v8 */ \
2624 &rs6000_reg_names[86][0], /* v9 */ \
2625 &rs6000_reg_names[87][0], /* v10 */ \
2626 &rs6000_reg_names[88][0], /* v11 */ \
2627 &rs6000_reg_names[89][0], /* v12 */ \
2628 &rs6000_reg_names[90][0], /* v13 */ \
2629 &rs6000_reg_names[91][0], /* v14 */ \
2630 &rs6000_reg_names[92][0], /* v15 */ \
2631 &rs6000_reg_names[93][0], /* v16 */ \
2632 &rs6000_reg_names[94][0], /* v17 */ \
2633 &rs6000_reg_names[95][0], /* v18 */ \
2634 &rs6000_reg_names[96][0], /* v19 */ \
2635 &rs6000_reg_names[97][0], /* v20 */ \
2636 &rs6000_reg_names[98][0], /* v21 */ \
2637 &rs6000_reg_names[99][0], /* v22 */ \
2638 &rs6000_reg_names[100][0], /* v23 */ \
2639 &rs6000_reg_names[101][0], /* v24 */ \
2640 &rs6000_reg_names[102][0], /* v25 */ \
2641 &rs6000_reg_names[103][0], /* v26 */ \
2642 &rs6000_reg_names[104][0], /* v27 */ \
2643 &rs6000_reg_names[105][0], /* v28 */ \
2644 &rs6000_reg_names[106][0], /* v29 */ \
2645 &rs6000_reg_names[107][0], /* v30 */ \
2646 &rs6000_reg_names[108][0], /* v31 */ \
2647 &rs6000_reg_names[109][0], /* vrsave */ \
2650 /* print-rtl can't handle the above REGISTER_NAMES, so define the
2651 following for it. Switch to use the alternate names since
2652 they are more mnemonic. */
2654 #define DEBUG_REGISTER_NAMES \
2656 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2657 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2658 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2659 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
2660 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2661 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
2662 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
2663 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
2664 "mq", "lr", "ctr", "ap", \
2665 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
2667 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
2668 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
2669 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
2670 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
2674 /* Table of additional register names to use in user input. */
2676 #define ADDITIONAL_REGISTER_NAMES \
2677 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2678 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2679 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2680 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2681 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2682 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2683 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2684 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2685 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2686 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2687 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2688 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2689 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2690 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2691 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2692 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2693 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2694 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2695 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2696 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2697 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2698 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2699 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2700 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2702 /* no additional names for: mq, lr, ctr, ap */ \
2703 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2704 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2705 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2707 /* Text to write out after a CALL that may be replaced by glue code by
2708 the loader. This depends on the AIX version. */
2709 #define RS6000_CALL_GLUE "cror 31,31,31"
2711 /* This is how to output an assembler line defining a `double' constant. */
2713 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
2716 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2717 fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", \
2718 t[0] & 0xffffffff, t[1] & 0xffffffff); \
2721 /* This is how to output an assembler line defining a `float' constant. */
2723 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \
2726 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2727 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
2730 /* This is how to output an element of a case-vector that is relative. */
2732 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2733 do { char buf[100]; \
2734 fputs ("\t.long ", FILE); \
2735 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2736 assemble_name (FILE, buf); \
2738 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2739 assemble_name (FILE, buf); \
2740 putc ('\n', FILE); \
2743 /* This is how to output an assembler line
2744 that says to advance the location counter
2745 to a multiple of 2**LOG bytes. */
2747 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2749 fprintf (FILE, "\t.align %d\n", (LOG))
2751 /* Store in OUTPUT a string (made with alloca) containing
2752 an assembler-name for a local static variable named NAME.
2753 LABELNO is an integer which is different for each call. */
2755 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2756 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2757 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2759 /* Pick up the return address upon entry to a procedure. Used for
2760 dwarf2 unwind information. This also enables the table driven
2763 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2764 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2766 /* Describe how we implement __builtin_eh_return. */
2767 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2768 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2770 /* Print operand X (an rtx) in assembler syntax to file FILE.
2771 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2772 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2774 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2776 /* Define which CODE values are valid. */
2778 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2781 /* Print a memory address as an operand to reference that memory location. */
2783 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2785 /* Define the codes that are matched by predicates in rs6000.c. */
2787 #define PREDICATE_CODES \
2788 {"short_cint_operand", {CONST_INT}}, \
2789 {"u_short_cint_operand", {CONST_INT}}, \
2790 {"non_short_cint_operand", {CONST_INT}}, \
2791 {"exact_log2_cint_operand", {CONST_INT}}, \
2792 {"gpc_reg_operand", {SUBREG, REG}}, \
2793 {"cc_reg_operand", {SUBREG, REG}}, \
2794 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2795 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2796 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2797 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2798 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2799 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2800 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2801 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2802 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2803 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2804 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2805 {"easy_fp_constant", {CONST_DOUBLE}}, \
2806 {"zero_fp_constant", {CONST_DOUBLE}}, \
2807 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2808 {"lwa_operand", {SUBREG, MEM, REG}}, \
2809 {"volatile_mem_operand", {MEM}}, \
2810 {"offsettable_mem_operand", {MEM}}, \
2811 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2812 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2813 {"non_add_cint_operand", {CONST_INT}}, \
2814 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2815 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2816 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2817 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2818 {"mask_operand", {CONST_INT}}, \
2819 {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \
2820 {"count_register_operand", {REG}}, \
2821 {"xer_operand", {REG}}, \
2822 {"call_operand", {SYMBOL_REF, REG}}, \
2823 {"current_file_function_operand", {SYMBOL_REF}}, \
2824 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2825 CONST_DOUBLE, SYMBOL_REF}}, \
2826 {"load_multiple_operation", {PARALLEL}}, \
2827 {"store_multiple_operation", {PARALLEL}}, \
2828 {"vrsave_operation", {PARALLEL}}, \
2829 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2830 GT, LEU, LTU, GEU, GTU, \
2831 UNORDERED, ORDERED, \
2833 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2835 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2836 GT, LEU, LTU, GEU, GTU, \
2837 UNORDERED, ORDERED, \
2839 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2840 GT, LEU, LTU, GEU, GTU}}, \
2841 {"boolean_operator", {AND, IOR, XOR}}, \
2842 {"boolean_or_operator", {IOR, XOR}}, \
2843 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2845 /* uncomment for disabling the corresponding default options */
2846 /* #define MACHINE_no_sched_interblock */
2847 /* #define MACHINE_no_sched_speculative */
2848 /* #define MACHINE_no_sched_speculative_load */
2850 /* General flags. */
2851 extern int flag_pic;
2852 extern int optimize;
2853 extern int flag_expensive_optimizations;
2854 extern int frame_pointer_needed;
2856 enum rs6000_builtins
2858 /* AltiVec builtins. */
2859 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2860 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2861 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2862 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2863 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2864 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2865 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2866 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2867 ALTIVEC_BUILTIN_VADDUBM,
2868 ALTIVEC_BUILTIN_VADDUHM,
2869 ALTIVEC_BUILTIN_VADDUWM,
2870 ALTIVEC_BUILTIN_VADDFP,
2871 ALTIVEC_BUILTIN_VADDCUW,
2872 ALTIVEC_BUILTIN_VADDUBS,
2873 ALTIVEC_BUILTIN_VADDSBS,
2874 ALTIVEC_BUILTIN_VADDUHS,
2875 ALTIVEC_BUILTIN_VADDSHS,
2876 ALTIVEC_BUILTIN_VADDUWS,
2877 ALTIVEC_BUILTIN_VADDSWS,
2878 ALTIVEC_BUILTIN_VAND,
2879 ALTIVEC_BUILTIN_VANDC,
2880 ALTIVEC_BUILTIN_VAVGUB,
2881 ALTIVEC_BUILTIN_VAVGSB,
2882 ALTIVEC_BUILTIN_VAVGUH,
2883 ALTIVEC_BUILTIN_VAVGSH,
2884 ALTIVEC_BUILTIN_VAVGUW,
2885 ALTIVEC_BUILTIN_VAVGSW,
2886 ALTIVEC_BUILTIN_VCFUX,
2887 ALTIVEC_BUILTIN_VCFSX,
2888 ALTIVEC_BUILTIN_VCTSXS,
2889 ALTIVEC_BUILTIN_VCTUXS,
2890 ALTIVEC_BUILTIN_VCMPBFP,
2891 ALTIVEC_BUILTIN_VCMPEQUB,
2892 ALTIVEC_BUILTIN_VCMPEQUH,
2893 ALTIVEC_BUILTIN_VCMPEQUW,
2894 ALTIVEC_BUILTIN_VCMPEQFP,
2895 ALTIVEC_BUILTIN_VCMPGEFP,
2896 ALTIVEC_BUILTIN_VCMPGTUB,
2897 ALTIVEC_BUILTIN_VCMPGTSB,
2898 ALTIVEC_BUILTIN_VCMPGTUH,
2899 ALTIVEC_BUILTIN_VCMPGTSH,
2900 ALTIVEC_BUILTIN_VCMPGTUW,
2901 ALTIVEC_BUILTIN_VCMPGTSW,
2902 ALTIVEC_BUILTIN_VCMPGTFP,
2903 ALTIVEC_BUILTIN_VEXPTEFP,
2904 ALTIVEC_BUILTIN_VLOGEFP,
2905 ALTIVEC_BUILTIN_VMADDFP,
2906 ALTIVEC_BUILTIN_VMAXUB,
2907 ALTIVEC_BUILTIN_VMAXSB,
2908 ALTIVEC_BUILTIN_VMAXUH,
2909 ALTIVEC_BUILTIN_VMAXSH,
2910 ALTIVEC_BUILTIN_VMAXUW,
2911 ALTIVEC_BUILTIN_VMAXSW,
2912 ALTIVEC_BUILTIN_VMAXFP,
2913 ALTIVEC_BUILTIN_VMHADDSHS,
2914 ALTIVEC_BUILTIN_VMHRADDSHS,
2915 ALTIVEC_BUILTIN_VMLADDUHM,
2916 ALTIVEC_BUILTIN_VMRGHB,
2917 ALTIVEC_BUILTIN_VMRGHH,
2918 ALTIVEC_BUILTIN_VMRGHW,
2919 ALTIVEC_BUILTIN_VMRGLB,
2920 ALTIVEC_BUILTIN_VMRGLH,
2921 ALTIVEC_BUILTIN_VMRGLW,
2922 ALTIVEC_BUILTIN_VMSUMUBM,
2923 ALTIVEC_BUILTIN_VMSUMMBM,
2924 ALTIVEC_BUILTIN_VMSUMUHM,
2925 ALTIVEC_BUILTIN_VMSUMSHM,
2926 ALTIVEC_BUILTIN_VMSUMUHS,
2927 ALTIVEC_BUILTIN_VMSUMSHS,
2928 ALTIVEC_BUILTIN_VMINUB,
2929 ALTIVEC_BUILTIN_VMINSB,
2930 ALTIVEC_BUILTIN_VMINUH,
2931 ALTIVEC_BUILTIN_VMINSH,
2932 ALTIVEC_BUILTIN_VMINUW,
2933 ALTIVEC_BUILTIN_VMINSW,
2934 ALTIVEC_BUILTIN_VMINFP,
2935 ALTIVEC_BUILTIN_VMULEUB,
2936 ALTIVEC_BUILTIN_VMULESB,
2937 ALTIVEC_BUILTIN_VMULEUH,
2938 ALTIVEC_BUILTIN_VMULESH,
2939 ALTIVEC_BUILTIN_VMULOUB,
2940 ALTIVEC_BUILTIN_VMULOSB,
2941 ALTIVEC_BUILTIN_VMULOUH,
2942 ALTIVEC_BUILTIN_VMULOSH,
2943 ALTIVEC_BUILTIN_VNMSUBFP,
2944 ALTIVEC_BUILTIN_VNOR,
2945 ALTIVEC_BUILTIN_VOR,
2946 ALTIVEC_BUILTIN_VSEL_4SI,
2947 ALTIVEC_BUILTIN_VSEL_4SF,
2948 ALTIVEC_BUILTIN_VSEL_8HI,
2949 ALTIVEC_BUILTIN_VSEL_16QI,
2950 ALTIVEC_BUILTIN_VPERM_4SI,
2951 ALTIVEC_BUILTIN_VPERM_4SF,
2952 ALTIVEC_BUILTIN_VPERM_8HI,
2953 ALTIVEC_BUILTIN_VPERM_16QI,
2954 ALTIVEC_BUILTIN_VPKUHUM,
2955 ALTIVEC_BUILTIN_VPKUWUM,
2956 ALTIVEC_BUILTIN_VPKPX,
2957 ALTIVEC_BUILTIN_VPKUHSS,
2958 ALTIVEC_BUILTIN_VPKSHSS,
2959 ALTIVEC_BUILTIN_VPKUWSS,
2960 ALTIVEC_BUILTIN_VPKSWSS,
2961 ALTIVEC_BUILTIN_VPKUHUS,
2962 ALTIVEC_BUILTIN_VPKSHUS,
2963 ALTIVEC_BUILTIN_VPKUWUS,
2964 ALTIVEC_BUILTIN_VPKSWUS,
2965 ALTIVEC_BUILTIN_VREFP,
2966 ALTIVEC_BUILTIN_VRFIM,
2967 ALTIVEC_BUILTIN_VRFIN,
2968 ALTIVEC_BUILTIN_VRFIP,
2969 ALTIVEC_BUILTIN_VRFIZ,
2970 ALTIVEC_BUILTIN_VRLB,
2971 ALTIVEC_BUILTIN_VRLH,
2972 ALTIVEC_BUILTIN_VRLW,
2973 ALTIVEC_BUILTIN_VRSQRTEFP,
2974 ALTIVEC_BUILTIN_VSLB,
2975 ALTIVEC_BUILTIN_VSLH,
2976 ALTIVEC_BUILTIN_VSLW,
2977 ALTIVEC_BUILTIN_VSL,
2978 ALTIVEC_BUILTIN_VSLO,
2979 ALTIVEC_BUILTIN_VSPLTB,
2980 ALTIVEC_BUILTIN_VSPLTH,
2981 ALTIVEC_BUILTIN_VSPLTW,
2982 ALTIVEC_BUILTIN_VSPLTISB,
2983 ALTIVEC_BUILTIN_VSPLTISH,
2984 ALTIVEC_BUILTIN_VSPLTISW,
2985 ALTIVEC_BUILTIN_VSRB,
2986 ALTIVEC_BUILTIN_VSRH,
2987 ALTIVEC_BUILTIN_VSRW,
2988 ALTIVEC_BUILTIN_VSRAB,
2989 ALTIVEC_BUILTIN_VSRAH,
2990 ALTIVEC_BUILTIN_VSRAW,
2991 ALTIVEC_BUILTIN_VSR,
2992 ALTIVEC_BUILTIN_VSRO,
2993 ALTIVEC_BUILTIN_VSUBUBM,
2994 ALTIVEC_BUILTIN_VSUBUHM,
2995 ALTIVEC_BUILTIN_VSUBUWM,
2996 ALTIVEC_BUILTIN_VSUBFP,
2997 ALTIVEC_BUILTIN_VSUBCUW,
2998 ALTIVEC_BUILTIN_VSUBUBS,
2999 ALTIVEC_BUILTIN_VSUBSBS,
3000 ALTIVEC_BUILTIN_VSUBUHS,
3001 ALTIVEC_BUILTIN_VSUBSHS,
3002 ALTIVEC_BUILTIN_VSUBUWS,
3003 ALTIVEC_BUILTIN_VSUBSWS,
3004 ALTIVEC_BUILTIN_VSUM4UBS,
3005 ALTIVEC_BUILTIN_VSUM4SBS,
3006 ALTIVEC_BUILTIN_VSUM4SHS,
3007 ALTIVEC_BUILTIN_VSUM2SWS,
3008 ALTIVEC_BUILTIN_VSUMSWS,
3009 ALTIVEC_BUILTIN_VXOR
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