1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
131 /* Target cpu type */
133 enum processor_type rs6000_cpu;
134 struct rs6000_cpu_select rs6000_select[3] =
136 /* switch name, tune arch */
137 { (const char *)0, "--with-cpu=", 1, 1 },
138 { (const char *)0, "-mcpu=", 1, 1 },
139 { (const char *)0, "-mtune=", 1, 0 },
142 static GTY(()) bool rs6000_cell_dont_microcode;
144 /* Always emit branch hint bits. */
145 static GTY(()) bool rs6000_always_hint;
147 /* Schedule instructions for group formation. */
148 static GTY(()) bool rs6000_sched_groups;
150 /* Align branch targets. */
151 static GTY(()) bool rs6000_align_branch_targets;
153 /* Support for -msched-costly-dep option. */
154 const char *rs6000_sched_costly_dep_str;
155 enum rs6000_dependence_cost rs6000_sched_costly_dep;
157 /* Support for -minsert-sched-nops option. */
158 const char *rs6000_sched_insert_nops_str;
159 enum rs6000_nop_insertion rs6000_sched_insert_nops;
161 /* Support targetm.vectorize.builtin_mask_for_load. */
162 static GTY(()) tree altivec_builtin_mask_for_load;
164 /* Size of long double. */
165 int rs6000_long_double_type_size;
167 /* IEEE quad extended precision long double. */
170 /* Whether -mabi=altivec has appeared. */
171 int rs6000_altivec_abi;
173 /* Nonzero if we want SPE ABI extensions. */
176 /* Nonzero if floating point operations are done in the GPRs. */
177 int rs6000_float_gprs = 0;
179 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
180 int rs6000_darwin64_abi;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Save information from a "cmpxx" operation until the branch or scc is
187 rtx rs6000_compare_op0, rs6000_compare_op1;
188 int rs6000_compare_fp_p;
190 /* Label number of label created for -mrelocatable, to call to so we can
191 get the address of the GOT section */
192 int rs6000_pic_labelno;
195 /* Which abi to adhere to */
196 const char *rs6000_abi_name;
198 /* Semantics of the small data area */
199 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
201 /* Which small data model to use */
202 const char *rs6000_sdata_name = (char *)0;
204 /* Counter for labels which are to be placed in .fixup. */
205 int fixuplabelno = 0;
208 /* Bit size of immediate TLS offsets and string from which it is decoded. */
209 int rs6000_tls_size = 32;
210 const char *rs6000_tls_size_string;
212 /* ABI enumeration available for subtarget to use. */
213 enum rs6000_abi rs6000_current_abi;
215 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
219 const char *rs6000_debug_name;
220 int rs6000_debug_stack; /* debug stack applications */
221 int rs6000_debug_arg; /* debug argument handling */
223 /* Value is TRUE if register/mode pair is acceptable. */
224 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
226 /* Built in types. */
228 tree rs6000_builtin_types[RS6000_BTI_MAX];
229 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
231 const char *rs6000_traceback_name;
233 traceback_default = 0,
239 /* Flag to say the TOC is initialized */
241 char toc_label_name[10];
243 /* Cached value of rs6000_variable_issue. This is cached in
244 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
245 static short cached_can_issue_more;
247 static GTY(()) section *read_only_data_section;
248 static GTY(()) section *private_data_section;
249 static GTY(()) section *read_only_private_data_section;
250 static GTY(()) section *sdata2_section;
251 static GTY(()) section *toc_section;
253 /* Control alignment for fields within structures. */
254 /* String from -malign-XXXXX. */
255 int rs6000_alignment_flags;
257 /* True for any options that were explicitly set. */
259 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
260 bool alignment; /* True if -malign- was used. */
261 bool abi; /* True if -mabi=spe/nospe was used. */
262 bool spe; /* True if -mspe= was used. */
263 bool float_gprs; /* True if -mfloat-gprs= was used. */
264 bool isel; /* True if -misel was used. */
265 bool long_double; /* True if -mlong-double- was used. */
266 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
267 } rs6000_explicit_options;
269 struct builtin_description
271 /* mask is not const because we're going to alter it below. This
272 nonsense will go away when we rewrite the -march infrastructure
273 to give us more target flag bits. */
275 const enum insn_code icode;
276 const char *const name;
277 const enum rs6000_builtins code;
280 /* Target cpu costs. */
282 struct processor_costs {
283 const int mulsi; /* cost of SImode multiplication. */
284 const int mulsi_const; /* cost of SImode multiplication by constant. */
285 const int mulsi_const9; /* cost of SImode mult by short constant. */
286 const int muldi; /* cost of DImode multiplication. */
287 const int divsi; /* cost of SImode division. */
288 const int divdi; /* cost of DImode division. */
289 const int fp; /* cost of simple SFmode and DFmode insns. */
290 const int dmul; /* cost of DFmode multiplication (and fmadd). */
291 const int sdiv; /* cost of SFmode division (fdivs). */
292 const int ddiv; /* cost of DFmode division (fdiv). */
295 const struct processor_costs *rs6000_cost;
297 /* Processor costs (relative to an add) */
299 /* Instruction size costs on 32bit processors. */
301 struct processor_costs size32_cost = {
302 COSTS_N_INSNS (1), /* mulsi */
303 COSTS_N_INSNS (1), /* mulsi_const */
304 COSTS_N_INSNS (1), /* mulsi_const9 */
305 COSTS_N_INSNS (1), /* muldi */
306 COSTS_N_INSNS (1), /* divsi */
307 COSTS_N_INSNS (1), /* divdi */
308 COSTS_N_INSNS (1), /* fp */
309 COSTS_N_INSNS (1), /* dmul */
310 COSTS_N_INSNS (1), /* sdiv */
311 COSTS_N_INSNS (1), /* ddiv */
314 /* Instruction size costs on 64bit processors. */
316 struct processor_costs size64_cost = {
317 COSTS_N_INSNS (1), /* mulsi */
318 COSTS_N_INSNS (1), /* mulsi_const */
319 COSTS_N_INSNS (1), /* mulsi_const9 */
320 COSTS_N_INSNS (1), /* muldi */
321 COSTS_N_INSNS (1), /* divsi */
322 COSTS_N_INSNS (1), /* divdi */
323 COSTS_N_INSNS (1), /* fp */
324 COSTS_N_INSNS (1), /* dmul */
325 COSTS_N_INSNS (1), /* sdiv */
326 COSTS_N_INSNS (1), /* ddiv */
329 /* Instruction costs on RIOS1 processors. */
331 struct processor_costs rios1_cost = {
332 COSTS_N_INSNS (5), /* mulsi */
333 COSTS_N_INSNS (4), /* mulsi_const */
334 COSTS_N_INSNS (3), /* mulsi_const9 */
335 COSTS_N_INSNS (5), /* muldi */
336 COSTS_N_INSNS (19), /* divsi */
337 COSTS_N_INSNS (19), /* divdi */
338 COSTS_N_INSNS (2), /* fp */
339 COSTS_N_INSNS (2), /* dmul */
340 COSTS_N_INSNS (19), /* sdiv */
341 COSTS_N_INSNS (19), /* ddiv */
344 /* Instruction costs on RIOS2 processors. */
346 struct processor_costs rios2_cost = {
347 COSTS_N_INSNS (2), /* mulsi */
348 COSTS_N_INSNS (2), /* mulsi_const */
349 COSTS_N_INSNS (2), /* mulsi_const9 */
350 COSTS_N_INSNS (2), /* muldi */
351 COSTS_N_INSNS (13), /* divsi */
352 COSTS_N_INSNS (13), /* divdi */
353 COSTS_N_INSNS (2), /* fp */
354 COSTS_N_INSNS (2), /* dmul */
355 COSTS_N_INSNS (17), /* sdiv */
356 COSTS_N_INSNS (17), /* ddiv */
359 /* Instruction costs on RS64A processors. */
361 struct processor_costs rs64a_cost = {
362 COSTS_N_INSNS (20), /* mulsi */
363 COSTS_N_INSNS (12), /* mulsi_const */
364 COSTS_N_INSNS (8), /* mulsi_const9 */
365 COSTS_N_INSNS (34), /* muldi */
366 COSTS_N_INSNS (65), /* divsi */
367 COSTS_N_INSNS (67), /* divdi */
368 COSTS_N_INSNS (4), /* fp */
369 COSTS_N_INSNS (4), /* dmul */
370 COSTS_N_INSNS (31), /* sdiv */
371 COSTS_N_INSNS (31), /* ddiv */
374 /* Instruction costs on MPCCORE processors. */
376 struct processor_costs mpccore_cost = {
377 COSTS_N_INSNS (2), /* mulsi */
378 COSTS_N_INSNS (2), /* mulsi_const */
379 COSTS_N_INSNS (2), /* mulsi_const9 */
380 COSTS_N_INSNS (2), /* muldi */
381 COSTS_N_INSNS (6), /* divsi */
382 COSTS_N_INSNS (6), /* divdi */
383 COSTS_N_INSNS (4), /* fp */
384 COSTS_N_INSNS (5), /* dmul */
385 COSTS_N_INSNS (10), /* sdiv */
386 COSTS_N_INSNS (17), /* ddiv */
389 /* Instruction costs on PPC403 processors. */
391 struct processor_costs ppc403_cost = {
392 COSTS_N_INSNS (4), /* mulsi */
393 COSTS_N_INSNS (4), /* mulsi_const */
394 COSTS_N_INSNS (4), /* mulsi_const9 */
395 COSTS_N_INSNS (4), /* muldi */
396 COSTS_N_INSNS (33), /* divsi */
397 COSTS_N_INSNS (33), /* divdi */
398 COSTS_N_INSNS (11), /* fp */
399 COSTS_N_INSNS (11), /* dmul */
400 COSTS_N_INSNS (11), /* sdiv */
401 COSTS_N_INSNS (11), /* ddiv */
404 /* Instruction costs on PPC405 processors. */
406 struct processor_costs ppc405_cost = {
407 COSTS_N_INSNS (5), /* mulsi */
408 COSTS_N_INSNS (4), /* mulsi_const */
409 COSTS_N_INSNS (3), /* mulsi_const9 */
410 COSTS_N_INSNS (5), /* muldi */
411 COSTS_N_INSNS (35), /* divsi */
412 COSTS_N_INSNS (35), /* divdi */
413 COSTS_N_INSNS (11), /* fp */
414 COSTS_N_INSNS (11), /* dmul */
415 COSTS_N_INSNS (11), /* sdiv */
416 COSTS_N_INSNS (11), /* ddiv */
419 /* Instruction costs on PPC440 processors. */
421 struct processor_costs ppc440_cost = {
422 COSTS_N_INSNS (3), /* mulsi */
423 COSTS_N_INSNS (2), /* mulsi_const */
424 COSTS_N_INSNS (2), /* mulsi_const9 */
425 COSTS_N_INSNS (3), /* muldi */
426 COSTS_N_INSNS (34), /* divsi */
427 COSTS_N_INSNS (34), /* divdi */
428 COSTS_N_INSNS (5), /* fp */
429 COSTS_N_INSNS (5), /* dmul */
430 COSTS_N_INSNS (19), /* sdiv */
431 COSTS_N_INSNS (33), /* ddiv */
434 /* Instruction costs on PPC601 processors. */
436 struct processor_costs ppc601_cost = {
437 COSTS_N_INSNS (5), /* mulsi */
438 COSTS_N_INSNS (5), /* mulsi_const */
439 COSTS_N_INSNS (5), /* mulsi_const9 */
440 COSTS_N_INSNS (5), /* muldi */
441 COSTS_N_INSNS (36), /* divsi */
442 COSTS_N_INSNS (36), /* divdi */
443 COSTS_N_INSNS (4), /* fp */
444 COSTS_N_INSNS (5), /* dmul */
445 COSTS_N_INSNS (17), /* sdiv */
446 COSTS_N_INSNS (31), /* ddiv */
449 /* Instruction costs on PPC603 processors. */
451 struct processor_costs ppc603_cost = {
452 COSTS_N_INSNS (5), /* mulsi */
453 COSTS_N_INSNS (3), /* mulsi_const */
454 COSTS_N_INSNS (2), /* mulsi_const9 */
455 COSTS_N_INSNS (5), /* muldi */
456 COSTS_N_INSNS (37), /* divsi */
457 COSTS_N_INSNS (37), /* divdi */
458 COSTS_N_INSNS (3), /* fp */
459 COSTS_N_INSNS (4), /* dmul */
460 COSTS_N_INSNS (18), /* sdiv */
461 COSTS_N_INSNS (33), /* ddiv */
464 /* Instruction costs on PPC604 processors. */
466 struct processor_costs ppc604_cost = {
467 COSTS_N_INSNS (4), /* mulsi */
468 COSTS_N_INSNS (4), /* mulsi_const */
469 COSTS_N_INSNS (4), /* mulsi_const9 */
470 COSTS_N_INSNS (4), /* muldi */
471 COSTS_N_INSNS (20), /* divsi */
472 COSTS_N_INSNS (20), /* divdi */
473 COSTS_N_INSNS (3), /* fp */
474 COSTS_N_INSNS (3), /* dmul */
475 COSTS_N_INSNS (18), /* sdiv */
476 COSTS_N_INSNS (32), /* ddiv */
479 /* Instruction costs on PPC604e processors. */
481 struct processor_costs ppc604e_cost = {
482 COSTS_N_INSNS (2), /* mulsi */
483 COSTS_N_INSNS (2), /* mulsi_const */
484 COSTS_N_INSNS (2), /* mulsi_const9 */
485 COSTS_N_INSNS (2), /* muldi */
486 COSTS_N_INSNS (20), /* divsi */
487 COSTS_N_INSNS (20), /* divdi */
488 COSTS_N_INSNS (3), /* fp */
489 COSTS_N_INSNS (3), /* dmul */
490 COSTS_N_INSNS (18), /* sdiv */
491 COSTS_N_INSNS (32), /* ddiv */
494 /* Instruction costs on PPC620 processors. */
496 struct processor_costs ppc620_cost = {
497 COSTS_N_INSNS (5), /* mulsi */
498 COSTS_N_INSNS (4), /* mulsi_const */
499 COSTS_N_INSNS (3), /* mulsi_const9 */
500 COSTS_N_INSNS (7), /* muldi */
501 COSTS_N_INSNS (21), /* divsi */
502 COSTS_N_INSNS (37), /* divdi */
503 COSTS_N_INSNS (3), /* fp */
504 COSTS_N_INSNS (3), /* dmul */
505 COSTS_N_INSNS (18), /* sdiv */
506 COSTS_N_INSNS (32), /* ddiv */
509 /* Instruction costs on PPC630 processors. */
511 struct processor_costs ppc630_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (4), /* mulsi_const */
514 COSTS_N_INSNS (3), /* mulsi_const9 */
515 COSTS_N_INSNS (7), /* muldi */
516 COSTS_N_INSNS (21), /* divsi */
517 COSTS_N_INSNS (37), /* divdi */
518 COSTS_N_INSNS (3), /* fp */
519 COSTS_N_INSNS (3), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (21), /* ddiv */
524 /* Instruction costs on Cell processor. */
525 /* COSTS_N_INSNS (1) ~ one add. */
527 struct processor_costs ppccell_cost = {
528 COSTS_N_INSNS (9/2)+2, /* mulsi */
529 COSTS_N_INSNS (6/2), /* mulsi_const */
530 COSTS_N_INSNS (6/2), /* mulsi_const9 */
531 COSTS_N_INSNS (15/2)+2, /* muldi */
532 COSTS_N_INSNS (38/2), /* divsi */
533 COSTS_N_INSNS (70/2), /* divdi */
534 COSTS_N_INSNS (10/2), /* fp */
535 COSTS_N_INSNS (10/2), /* dmul */
536 COSTS_N_INSNS (74/2), /* sdiv */
537 COSTS_N_INSNS (74/2), /* ddiv */
540 /* Instruction costs on PPC750 and PPC7400 processors. */
542 struct processor_costs ppc750_cost = {
543 COSTS_N_INSNS (5), /* mulsi */
544 COSTS_N_INSNS (3), /* mulsi_const */
545 COSTS_N_INSNS (2), /* mulsi_const9 */
546 COSTS_N_INSNS (5), /* muldi */
547 COSTS_N_INSNS (17), /* divsi */
548 COSTS_N_INSNS (17), /* divdi */
549 COSTS_N_INSNS (3), /* fp */
550 COSTS_N_INSNS (3), /* dmul */
551 COSTS_N_INSNS (17), /* sdiv */
552 COSTS_N_INSNS (31), /* ddiv */
555 /* Instruction costs on PPC7450 processors. */
557 struct processor_costs ppc7450_cost = {
558 COSTS_N_INSNS (4), /* mulsi */
559 COSTS_N_INSNS (3), /* mulsi_const */
560 COSTS_N_INSNS (3), /* mulsi_const9 */
561 COSTS_N_INSNS (4), /* muldi */
562 COSTS_N_INSNS (23), /* divsi */
563 COSTS_N_INSNS (23), /* divdi */
564 COSTS_N_INSNS (5), /* fp */
565 COSTS_N_INSNS (5), /* dmul */
566 COSTS_N_INSNS (21), /* sdiv */
567 COSTS_N_INSNS (35), /* ddiv */
570 /* Instruction costs on PPC8540 processors. */
572 struct processor_costs ppc8540_cost = {
573 COSTS_N_INSNS (4), /* mulsi */
574 COSTS_N_INSNS (4), /* mulsi_const */
575 COSTS_N_INSNS (4), /* mulsi_const9 */
576 COSTS_N_INSNS (4), /* muldi */
577 COSTS_N_INSNS (19), /* divsi */
578 COSTS_N_INSNS (19), /* divdi */
579 COSTS_N_INSNS (4), /* fp */
580 COSTS_N_INSNS (4), /* dmul */
581 COSTS_N_INSNS (29), /* sdiv */
582 COSTS_N_INSNS (29), /* ddiv */
585 /* Instruction costs on POWER4 and POWER5 processors. */
587 struct processor_costs power4_cost = {
588 COSTS_N_INSNS (3), /* mulsi */
589 COSTS_N_INSNS (2), /* mulsi_const */
590 COSTS_N_INSNS (2), /* mulsi_const9 */
591 COSTS_N_INSNS (4), /* muldi */
592 COSTS_N_INSNS (18), /* divsi */
593 COSTS_N_INSNS (34), /* divdi */
594 COSTS_N_INSNS (3), /* fp */
595 COSTS_N_INSNS (3), /* dmul */
596 COSTS_N_INSNS (17), /* sdiv */
597 COSTS_N_INSNS (17), /* ddiv */
600 /* Instruction costs on POWER6 processors. */
602 struct processor_costs power6_cost = {
603 COSTS_N_INSNS (8), /* mulsi */
604 COSTS_N_INSNS (8), /* mulsi_const */
605 COSTS_N_INSNS (8), /* mulsi_const9 */
606 COSTS_N_INSNS (8), /* muldi */
607 COSTS_N_INSNS (22), /* divsi */
608 COSTS_N_INSNS (28), /* divdi */
609 COSTS_N_INSNS (3), /* fp */
610 COSTS_N_INSNS (3), /* dmul */
611 COSTS_N_INSNS (13), /* sdiv */
612 COSTS_N_INSNS (16), /* ddiv */
616 static bool rs6000_function_ok_for_sibcall (tree, tree);
617 static const char *rs6000_invalid_within_doloop (rtx);
618 static rtx rs6000_generate_compare (enum rtx_code);
619 static void rs6000_emit_stack_tie (void);
620 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
621 static rtx spe_synthesize_frame_save (rtx);
622 static bool spe_func_has_64bit_regs_p (void);
623 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
625 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
626 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
627 static unsigned rs6000_hash_constant (rtx);
628 static unsigned toc_hash_function (const void *);
629 static int toc_hash_eq (const void *, const void *);
630 static int constant_pool_expr_1 (rtx, int *, int *);
631 static bool constant_pool_expr_p (rtx);
632 static bool legitimate_small_data_p (enum machine_mode, rtx);
633 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
634 static struct machine_function * rs6000_init_machine_status (void);
635 static bool rs6000_assemble_integer (rtx, unsigned int, int);
636 static bool no_global_regs_above (int);
637 #ifdef HAVE_GAS_HIDDEN
638 static void rs6000_assemble_visibility (tree, int);
640 static int rs6000_ra_ever_killed (void);
641 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
642 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
643 static bool rs6000_ms_bitfield_layout_p (tree);
644 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
645 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
646 static const char *rs6000_mangle_fundamental_type (tree);
647 extern const struct attribute_spec rs6000_attribute_table[];
648 static void rs6000_set_default_type_attributes (tree);
649 static bool rs6000_reg_live_or_pic_offset_p (int);
650 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
651 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
652 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
654 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
655 static bool rs6000_return_in_memory (tree, tree);
656 static void rs6000_file_start (void);
658 static int rs6000_elf_reloc_rw_mask (void);
659 static void rs6000_elf_asm_out_constructor (rtx, int);
660 static void rs6000_elf_asm_out_destructor (rtx, int);
661 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
662 static void rs6000_elf_asm_init_sections (void);
663 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
664 unsigned HOST_WIDE_INT);
665 static void rs6000_elf_encode_section_info (tree, rtx, int)
668 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
670 static void rs6000_xcoff_asm_output_anchor (rtx);
671 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
672 static void rs6000_xcoff_asm_init_sections (void);
673 static int rs6000_xcoff_reloc_rw_mask (void);
674 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
675 static section *rs6000_xcoff_select_section (tree, int,
676 unsigned HOST_WIDE_INT);
677 static void rs6000_xcoff_unique_section (tree, int);
678 static section *rs6000_xcoff_select_rtx_section
679 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
680 static const char * rs6000_xcoff_strip_name_encoding (const char *);
681 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
682 static void rs6000_xcoff_file_start (void);
683 static void rs6000_xcoff_file_end (void);
685 static int rs6000_variable_issue (FILE *, int, rtx, int);
686 static bool rs6000_rtx_costs (rtx, int, int, int *);
687 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
688 static void rs6000_sched_init (FILE *, int, int);
689 static bool is_microcoded_insn (rtx);
690 static bool is_nonpipeline_insn (rtx);
691 static bool is_cracked_insn (rtx);
692 static bool is_branch_slot_insn (rtx);
693 static bool is_load_insn (rtx);
694 static rtx get_store_dest (rtx pat);
695 static bool is_store_insn (rtx);
696 static bool set_to_load_agen (rtx,rtx);
697 static bool adjacent_mem_locations (rtx,rtx);
698 static int rs6000_adjust_priority (rtx, int);
699 static int rs6000_issue_rate (void);
700 static bool rs6000_is_costly_dependence (dep_t, int, int);
701 static rtx get_next_active_insn (rtx, rtx);
702 static bool insn_terminates_group_p (rtx , enum group_termination);
703 static bool insn_must_be_first_in_group (rtx);
704 static bool insn_must_be_last_in_group (rtx);
705 static bool is_costly_group (rtx *, rtx);
706 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
707 static int redefine_groups (FILE *, int, rtx, rtx);
708 static int pad_groups (FILE *, int, rtx, rtx);
709 static void rs6000_sched_finish (FILE *, int);
710 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
711 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
712 static int rs6000_use_sched_lookahead (void);
713 static int rs6000_use_sched_lookahead_guard (rtx);
714 static tree rs6000_builtin_mask_for_load (void);
715 static tree rs6000_builtin_mul_widen_even (tree);
716 static tree rs6000_builtin_mul_widen_odd (tree);
717 static tree rs6000_builtin_conversion (enum tree_code, tree);
719 static void def_builtin (int, const char *, tree, int);
720 static void rs6000_init_builtins (void);
721 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
722 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
723 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
724 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
725 static void altivec_init_builtins (void);
726 static void rs6000_common_init_builtins (void);
727 static void rs6000_init_libfuncs (void);
729 static void enable_mask_for_builtins (struct builtin_description *, int,
730 enum rs6000_builtins,
731 enum rs6000_builtins);
732 static tree build_opaque_vector_type (tree, int);
733 static void spe_init_builtins (void);
734 static rtx spe_expand_builtin (tree, rtx, bool *);
735 static rtx spe_expand_stv_builtin (enum insn_code, tree);
736 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
737 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
738 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
739 static rs6000_stack_t *rs6000_stack_info (void);
740 static void debug_stack_info (rs6000_stack_t *);
742 static rtx altivec_expand_builtin (tree, rtx, bool *);
743 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
744 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
745 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
746 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
747 static rtx altivec_expand_predicate_builtin (enum insn_code,
748 const char *, tree, rtx);
749 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
750 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
751 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
752 static rtx altivec_expand_vec_set_builtin (tree);
753 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
754 static int get_element_number (tree, tree);
755 static bool rs6000_handle_option (size_t, const char *, int);
756 static void rs6000_parse_tls_size_option (void);
757 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
758 static int first_altivec_reg_to_save (void);
759 static unsigned int compute_vrsave_mask (void);
760 static void compute_save_world_info (rs6000_stack_t *info_ptr);
761 static void is_altivec_return_reg (rtx, void *);
762 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
763 int easy_vector_constant (rtx, enum machine_mode);
764 static bool rs6000_is_opaque_type (tree);
765 static rtx rs6000_dwarf_register_span (rtx);
766 static void rs6000_init_dwarf_reg_sizes_extra (tree);
767 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
768 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
769 static rtx rs6000_tls_get_addr (void);
770 static rtx rs6000_got_sym (void);
771 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
772 static const char *rs6000_get_some_local_dynamic_name (void);
773 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
774 static rtx rs6000_complex_function_value (enum machine_mode);
775 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
776 enum machine_mode, tree);
777 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
779 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
780 tree, HOST_WIDE_INT);
781 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
784 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
787 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
788 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
789 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
790 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
791 enum machine_mode, tree,
793 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
795 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
797 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
799 static void macho_branch_islands (void);
800 static int no_previous_def (tree function_name);
801 static tree get_prev_label (tree function_name);
802 static void rs6000_darwin_file_start (void);
805 static tree rs6000_build_builtin_va_list (void);
806 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
807 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
808 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
809 static bool rs6000_vector_mode_supported_p (enum machine_mode);
810 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
812 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
814 static int get_vsel_insn (enum machine_mode);
815 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
816 static tree rs6000_stack_protect_fail (void);
818 const int INSN_NOT_AVAILABLE = -1;
819 static enum machine_mode rs6000_eh_return_filter_mode (void);
821 /* Hash table stuff for keeping track of TOC entries. */
823 struct toc_hash_struct GTY(())
825 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
826 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
828 enum machine_mode key_mode;
832 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
834 /* Default register names. */
835 char rs6000_reg_names[][8] =
837 "0", "1", "2", "3", "4", "5", "6", "7",
838 "8", "9", "10", "11", "12", "13", "14", "15",
839 "16", "17", "18", "19", "20", "21", "22", "23",
840 "24", "25", "26", "27", "28", "29", "30", "31",
841 "0", "1", "2", "3", "4", "5", "6", "7",
842 "8", "9", "10", "11", "12", "13", "14", "15",
843 "16", "17", "18", "19", "20", "21", "22", "23",
844 "24", "25", "26", "27", "28", "29", "30", "31",
845 "mq", "lr", "ctr","ap",
846 "0", "1", "2", "3", "4", "5", "6", "7",
848 /* AltiVec registers. */
849 "0", "1", "2", "3", "4", "5", "6", "7",
850 "8", "9", "10", "11", "12", "13", "14", "15",
851 "16", "17", "18", "19", "20", "21", "22", "23",
852 "24", "25", "26", "27", "28", "29", "30", "31",
855 "spe_acc", "spefscr",
856 /* Soft frame pointer. */
860 #ifdef TARGET_REGNAMES
861 static const char alt_reg_names[][8] =
863 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
864 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
865 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
866 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
867 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
868 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
869 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
870 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
871 "mq", "lr", "ctr", "ap",
872 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
874 /* AltiVec registers. */
875 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
876 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
877 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
878 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
881 "spe_acc", "spefscr",
882 /* Soft frame pointer. */
887 #ifndef MASK_STRICT_ALIGN
888 #define MASK_STRICT_ALIGN 0
890 #ifndef TARGET_PROFILE_KERNEL
891 #define TARGET_PROFILE_KERNEL 0
894 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
895 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
897 /* Initialize the GCC target structure. */
898 #undef TARGET_ATTRIBUTE_TABLE
899 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
900 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
901 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
903 #undef TARGET_ASM_ALIGNED_DI_OP
904 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
906 /* Default unaligned ops are only provided for ELF. Find the ops needed
907 for non-ELF systems. */
908 #ifndef OBJECT_FORMAT_ELF
910 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
912 #undef TARGET_ASM_UNALIGNED_HI_OP
913 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
914 #undef TARGET_ASM_UNALIGNED_SI_OP
915 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
916 #undef TARGET_ASM_UNALIGNED_DI_OP
917 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
920 #undef TARGET_ASM_UNALIGNED_HI_OP
921 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
922 #undef TARGET_ASM_UNALIGNED_SI_OP
923 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
924 #undef TARGET_ASM_UNALIGNED_DI_OP
925 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
926 #undef TARGET_ASM_ALIGNED_DI_OP
927 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
931 /* This hook deals with fixups for relocatable code and DI-mode objects
933 #undef TARGET_ASM_INTEGER
934 #define TARGET_ASM_INTEGER rs6000_assemble_integer
936 #ifdef HAVE_GAS_HIDDEN
937 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
938 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
941 #undef TARGET_HAVE_TLS
942 #define TARGET_HAVE_TLS HAVE_AS_TLS
944 #undef TARGET_CANNOT_FORCE_CONST_MEM
945 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
947 #undef TARGET_ASM_FUNCTION_PROLOGUE
948 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
949 #undef TARGET_ASM_FUNCTION_EPILOGUE
950 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
952 #undef TARGET_SCHED_VARIABLE_ISSUE
953 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
955 #undef TARGET_SCHED_ISSUE_RATE
956 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
957 #undef TARGET_SCHED_ADJUST_COST
958 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
959 #undef TARGET_SCHED_ADJUST_PRIORITY
960 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
961 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
962 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
963 #undef TARGET_SCHED_INIT
964 #define TARGET_SCHED_INIT rs6000_sched_init
965 #undef TARGET_SCHED_FINISH
966 #define TARGET_SCHED_FINISH rs6000_sched_finish
967 #undef TARGET_SCHED_REORDER
968 #define TARGET_SCHED_REORDER rs6000_sched_reorder
969 #undef TARGET_SCHED_REORDER2
970 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
972 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
973 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
975 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
976 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
978 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
979 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
980 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
981 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
982 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
983 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
984 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
985 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
987 #undef TARGET_INIT_BUILTINS
988 #define TARGET_INIT_BUILTINS rs6000_init_builtins
990 #undef TARGET_EXPAND_BUILTIN
991 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
993 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
994 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
996 #undef TARGET_INIT_LIBFUNCS
997 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1000 #undef TARGET_BINDS_LOCAL_P
1001 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1004 #undef TARGET_MS_BITFIELD_LAYOUT_P
1005 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1007 #undef TARGET_ASM_OUTPUT_MI_THUNK
1008 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1010 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1011 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1013 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1014 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1016 #undef TARGET_INVALID_WITHIN_DOLOOP
1017 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1019 #undef TARGET_RTX_COSTS
1020 #define TARGET_RTX_COSTS rs6000_rtx_costs
1021 #undef TARGET_ADDRESS_COST
1022 #define TARGET_ADDRESS_COST hook_int_rtx_0
1024 #undef TARGET_VECTOR_OPAQUE_P
1025 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1027 #undef TARGET_DWARF_REGISTER_SPAN
1028 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1030 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1031 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1033 /* On rs6000, function arguments are promoted, as are function return
1035 #undef TARGET_PROMOTE_FUNCTION_ARGS
1036 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1037 #undef TARGET_PROMOTE_FUNCTION_RETURN
1038 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1040 #undef TARGET_RETURN_IN_MEMORY
1041 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1043 #undef TARGET_SETUP_INCOMING_VARARGS
1044 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1046 /* Always strict argument naming on rs6000. */
1047 #undef TARGET_STRICT_ARGUMENT_NAMING
1048 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1049 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1050 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1051 #undef TARGET_SPLIT_COMPLEX_ARG
1052 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
1053 #undef TARGET_MUST_PASS_IN_STACK
1054 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1055 #undef TARGET_PASS_BY_REFERENCE
1056 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1057 #undef TARGET_ARG_PARTIAL_BYTES
1058 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1060 #undef TARGET_BUILD_BUILTIN_VA_LIST
1061 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1063 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1064 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1066 #undef TARGET_EH_RETURN_FILTER_MODE
1067 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1069 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1070 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1072 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1073 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1075 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1076 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1078 #undef TARGET_HANDLE_OPTION
1079 #define TARGET_HANDLE_OPTION rs6000_handle_option
1081 #undef TARGET_DEFAULT_TARGET_FLAGS
1082 #define TARGET_DEFAULT_TARGET_FLAGS \
1085 #undef TARGET_STACK_PROTECT_FAIL
1086 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1088 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1089 The PowerPC architecture requires only weak consistency among
1090 processors--that is, memory accesses between processors need not be
1091 sequentially consistent and memory accesses among processors can occur
1092 in any order. The ability to order memory accesses weakly provides
1093 opportunities for more efficient use of the system bus. Unless a
1094 dependency exists, the 604e allows read operations to precede store
1096 #undef TARGET_RELAXED_ORDERING
1097 #define TARGET_RELAXED_ORDERING true
1100 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1101 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1104 /* Use a 32-bit anchor range. This leads to sequences like:
1106 addis tmp,anchor,high
1109 where tmp itself acts as an anchor, and can be shared between
1110 accesses to the same 64k page. */
1111 #undef TARGET_MIN_ANCHOR_OFFSET
1112 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1113 #undef TARGET_MAX_ANCHOR_OFFSET
1114 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1115 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1116 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1118 struct gcc_target targetm = TARGET_INITIALIZER;
1121 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1124 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1126 /* The GPRs can hold any mode, but values bigger than one register
1127 cannot go past R31. */
1128 if (INT_REGNO_P (regno))
1129 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1131 /* The float registers can only hold floating modes and DImode.
1132 This excludes the 32-bit decimal float mode for now. */
1133 if (FP_REGNO_P (regno))
1135 (SCALAR_FLOAT_MODE_P (mode)
1136 && (mode != TDmode || (regno % 2) == 0)
1138 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1139 || (GET_MODE_CLASS (mode) == MODE_INT
1140 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1142 /* The CR register can only hold CC modes. */
1143 if (CR_REGNO_P (regno))
1144 return GET_MODE_CLASS (mode) == MODE_CC;
1146 if (XER_REGNO_P (regno))
1147 return mode == PSImode;
1149 /* AltiVec only in AldyVec registers. */
1150 if (ALTIVEC_REGNO_P (regno))
1151 return ALTIVEC_VECTOR_MODE (mode);
1153 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1154 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1157 /* We cannot put TImode anywhere except general register and it must be
1158 able to fit within the register set. */
1160 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1163 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1165 rs6000_init_hard_regno_mode_ok (void)
1169 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1170 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1171 if (rs6000_hard_regno_mode_ok (r, m))
1172 rs6000_hard_regno_mode_ok_p[m][r] = true;
1176 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1179 darwin_rs6000_override_options (void)
1181 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1183 rs6000_altivec_abi = 1;
1184 TARGET_ALTIVEC_VRSAVE = 1;
1185 if (DEFAULT_ABI == ABI_DARWIN)
1187 if (MACHO_DYNAMIC_NO_PIC_P)
1190 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1193 else if (flag_pic == 1)
1198 if (TARGET_64BIT && ! TARGET_POWERPC64)
1200 target_flags |= MASK_POWERPC64;
1201 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1205 rs6000_default_long_calls = 1;
1206 target_flags |= MASK_SOFT_FLOAT;
1209 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1211 if (!flag_mkernel && !flag_apple_kext
1213 && ! (target_flags_explicit & MASK_ALTIVEC))
1214 target_flags |= MASK_ALTIVEC;
1216 /* Unless the user (not the configurer) has explicitly overridden
1217 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1218 G4 unless targetting the kernel. */
1221 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1222 && ! (target_flags_explicit & MASK_ALTIVEC)
1223 && ! rs6000_select[1].string)
1225 target_flags |= MASK_ALTIVEC;
1230 /* If not otherwise specified by a target, make 'long double' equivalent to
1233 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1234 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1237 /* Override command line options. Mostly we process the processor
1238 type and sometimes adjust other TARGET_ options. */
1241 rs6000_override_options (const char *default_cpu)
1244 struct rs6000_cpu_select *ptr;
1247 /* Simplifications for entries below. */
1250 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1251 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1254 /* This table occasionally claims that a processor does not support
1255 a particular feature even though it does, but the feature is slower
1256 than the alternative. Thus, it shouldn't be relied on as a
1257 complete description of the processor's support.
1259 Please keep this list in order, and don't forget to update the
1260 documentation in invoke.texi when adding a new processor or
1264 const char *const name; /* Canonical processor name. */
1265 const enum processor_type processor; /* Processor type enum value. */
1266 const int target_enable; /* Target flags to enable. */
1267 } const processor_target_table[]
1268 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1269 {"403", PROCESSOR_PPC403,
1270 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1271 {"405", PROCESSOR_PPC405,
1272 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1273 {"405fp", PROCESSOR_PPC405,
1274 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1275 {"440", PROCESSOR_PPC440,
1276 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1277 {"440fp", PROCESSOR_PPC440,
1278 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1279 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1280 {"601", PROCESSOR_PPC601,
1281 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1282 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1283 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1284 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1285 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1286 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1287 {"620", PROCESSOR_PPC620,
1288 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1289 {"630", PROCESSOR_PPC630,
1290 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1291 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1292 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1293 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1294 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1295 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1296 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1297 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1298 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1299 /* 8548 has a dummy entry for now. */
1300 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1301 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1302 {"970", PROCESSOR_POWER4,
1303 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1304 {"cell", PROCESSOR_CELL,
1305 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1306 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1307 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1308 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1309 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1310 {"G5", PROCESSOR_POWER4,
1311 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1312 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1313 {"power2", PROCESSOR_POWER,
1314 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1315 {"power3", PROCESSOR_PPC630,
1316 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1317 {"power4", PROCESSOR_POWER4,
1318 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1319 {"power5", PROCESSOR_POWER5,
1320 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1321 | MASK_MFCRF | MASK_POPCNTB},
1322 {"power5+", PROCESSOR_POWER5,
1323 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1324 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1325 {"power6", PROCESSOR_POWER6,
1326 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1327 | MASK_FPRND | MASK_CMPB | MASK_DFP },
1328 {"power6x", PROCESSOR_POWER6,
1329 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1330 | MASK_FPRND | MASK_CMPB | MASK_MFPGPR | MASK_DFP },
1331 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1332 {"powerpc64", PROCESSOR_POWERPC64,
1333 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1334 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1335 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1336 {"rios2", PROCESSOR_RIOS2,
1337 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1338 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1339 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1340 {"rs64", PROCESSOR_RS64A,
1341 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1344 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1346 /* Some OSs don't support saving the high part of 64-bit registers on
1347 context switch. Other OSs don't support saving Altivec registers.
1348 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1349 settings; if the user wants either, the user must explicitly specify
1350 them and we won't interfere with the user's specification. */
1353 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1354 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1355 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1356 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1357 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1360 rs6000_init_hard_regno_mode_ok ();
1362 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1363 #ifdef OS_MISSING_POWERPC64
1364 if (OS_MISSING_POWERPC64)
1365 set_masks &= ~MASK_POWERPC64;
1367 #ifdef OS_MISSING_ALTIVEC
1368 if (OS_MISSING_ALTIVEC)
1369 set_masks &= ~MASK_ALTIVEC;
1372 /* Don't override by the processor default if given explicitly. */
1373 set_masks &= ~target_flags_explicit;
1375 /* Identify the processor type. */
1376 rs6000_select[0].string = default_cpu;
1377 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1379 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1381 ptr = &rs6000_select[i];
1382 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1384 for (j = 0; j < ptt_size; j++)
1385 if (! strcmp (ptr->string, processor_target_table[j].name))
1387 if (ptr->set_tune_p)
1388 rs6000_cpu = processor_target_table[j].processor;
1390 if (ptr->set_arch_p)
1392 target_flags &= ~set_masks;
1393 target_flags |= (processor_target_table[j].target_enable
1400 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1407 /* If we are optimizing big endian systems for space, use the load/store
1408 multiple and string instructions. */
1409 if (BYTES_BIG_ENDIAN && optimize_size)
1410 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1412 /* Don't allow -mmultiple or -mstring on little endian systems
1413 unless the cpu is a 750, because the hardware doesn't support the
1414 instructions used in little endian mode, and causes an alignment
1415 trap. The 750 does not cause an alignment trap (except when the
1416 target is unaligned). */
1418 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1420 if (TARGET_MULTIPLE)
1422 target_flags &= ~MASK_MULTIPLE;
1423 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1424 warning (0, "-mmultiple is not supported on little endian systems");
1429 target_flags &= ~MASK_STRING;
1430 if ((target_flags_explicit & MASK_STRING) != 0)
1431 warning (0, "-mstring is not supported on little endian systems");
1435 /* Set debug flags */
1436 if (rs6000_debug_name)
1438 if (! strcmp (rs6000_debug_name, "all"))
1439 rs6000_debug_stack = rs6000_debug_arg = 1;
1440 else if (! strcmp (rs6000_debug_name, "stack"))
1441 rs6000_debug_stack = 1;
1442 else if (! strcmp (rs6000_debug_name, "arg"))
1443 rs6000_debug_arg = 1;
1445 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1448 if (rs6000_traceback_name)
1450 if (! strncmp (rs6000_traceback_name, "full", 4))
1451 rs6000_traceback = traceback_full;
1452 else if (! strncmp (rs6000_traceback_name, "part", 4))
1453 rs6000_traceback = traceback_part;
1454 else if (! strncmp (rs6000_traceback_name, "no", 2))
1455 rs6000_traceback = traceback_none;
1457 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1458 rs6000_traceback_name);
1461 if (!rs6000_explicit_options.long_double)
1462 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1464 #ifndef POWERPC_LINUX
1465 if (!rs6000_explicit_options.ieee)
1466 rs6000_ieeequad = 1;
1469 /* Set Altivec ABI as default for powerpc64 linux. */
1470 if (TARGET_ELF && TARGET_64BIT)
1472 rs6000_altivec_abi = 1;
1473 TARGET_ALTIVEC_VRSAVE = 1;
1476 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1477 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1479 rs6000_darwin64_abi = 1;
1481 darwin_one_byte_bool = 1;
1483 /* Default to natural alignment, for better performance. */
1484 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1487 /* Place FP constants in the constant pool instead of TOC
1488 if section anchors enabled. */
1489 if (flag_section_anchors)
1490 TARGET_NO_FP_IN_TOC = 1;
1492 /* Handle -mtls-size option. */
1493 rs6000_parse_tls_size_option ();
1495 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1496 SUBTARGET_OVERRIDE_OPTIONS;
1498 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1499 SUBSUBTARGET_OVERRIDE_OPTIONS;
1501 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1502 SUB3TARGET_OVERRIDE_OPTIONS;
1507 /* The e500 does not have string instructions, and we set
1508 MASK_STRING above when optimizing for size. */
1509 if ((target_flags & MASK_STRING) != 0)
1510 target_flags = target_flags & ~MASK_STRING;
1512 else if (rs6000_select[1].string != NULL)
1514 /* For the powerpc-eabispe configuration, we set all these by
1515 default, so let's unset them if we manually set another
1516 CPU that is not the E500. */
1517 if (!rs6000_explicit_options.abi)
1519 if (!rs6000_explicit_options.spe)
1521 if (!rs6000_explicit_options.float_gprs)
1522 rs6000_float_gprs = 0;
1523 if (!rs6000_explicit_options.isel)
1527 /* Detect invalid option combinations with E500. */
1530 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1531 && rs6000_cpu != PROCESSOR_POWER5
1532 && rs6000_cpu != PROCESSOR_POWER6
1533 && rs6000_cpu != PROCESSOR_CELL);
1534 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1535 || rs6000_cpu == PROCESSOR_POWER5);
1536 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1537 || rs6000_cpu == PROCESSOR_POWER5
1538 || rs6000_cpu == PROCESSOR_POWER6);
1540 rs6000_sched_restricted_insns_priority
1541 = (rs6000_sched_groups ? 1 : 0);
1543 /* Handle -msched-costly-dep option. */
1544 rs6000_sched_costly_dep
1545 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1547 if (rs6000_sched_costly_dep_str)
1549 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1550 rs6000_sched_costly_dep = no_dep_costly;
1551 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1552 rs6000_sched_costly_dep = all_deps_costly;
1553 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1554 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1555 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1556 rs6000_sched_costly_dep = store_to_load_dep_costly;
1558 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1561 /* Handle -minsert-sched-nops option. */
1562 rs6000_sched_insert_nops
1563 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1565 if (rs6000_sched_insert_nops_str)
1567 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1568 rs6000_sched_insert_nops = sched_finish_none;
1569 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1570 rs6000_sched_insert_nops = sched_finish_pad_groups;
1571 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1572 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1574 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1577 #ifdef TARGET_REGNAMES
1578 /* If the user desires alternate register names, copy in the
1579 alternate names now. */
1580 if (TARGET_REGNAMES)
1581 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1584 /* Set aix_struct_return last, after the ABI is determined.
1585 If -maix-struct-return or -msvr4-struct-return was explicitly
1586 used, don't override with the ABI default. */
1587 if (!rs6000_explicit_options.aix_struct_ret)
1588 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1590 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1591 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1594 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1596 /* We can only guarantee the availability of DI pseudo-ops when
1597 assembling for 64-bit targets. */
1600 targetm.asm_out.aligned_op.di = NULL;
1601 targetm.asm_out.unaligned_op.di = NULL;
1604 /* Set branch target alignment, if not optimizing for size. */
1607 /* Cell wants to be aligned 8byte for dual issue. */
1608 if (rs6000_cpu == PROCESSOR_CELL)
1610 if (align_functions <= 0)
1611 align_functions = 8;
1612 if (align_jumps <= 0)
1614 if (align_loops <= 0)
1617 if (rs6000_align_branch_targets)
1619 if (align_functions <= 0)
1620 align_functions = 16;
1621 if (align_jumps <= 0)
1623 if (align_loops <= 0)
1626 if (align_jumps_max_skip <= 0)
1627 align_jumps_max_skip = 15;
1628 if (align_loops_max_skip <= 0)
1629 align_loops_max_skip = 15;
1632 /* Arrange to save and restore machine status around nested functions. */
1633 init_machine_status = rs6000_init_machine_status;
1635 /* We should always be splitting complex arguments, but we can't break
1636 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1637 if (DEFAULT_ABI != ABI_AIX)
1638 targetm.calls.split_complex_arg = NULL;
1640 /* Initialize rs6000_cost with the appropriate target costs. */
1642 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1646 case PROCESSOR_RIOS1:
1647 rs6000_cost = &rios1_cost;
1650 case PROCESSOR_RIOS2:
1651 rs6000_cost = &rios2_cost;
1654 case PROCESSOR_RS64A:
1655 rs6000_cost = &rs64a_cost;
1658 case PROCESSOR_MPCCORE:
1659 rs6000_cost = &mpccore_cost;
1662 case PROCESSOR_PPC403:
1663 rs6000_cost = &ppc403_cost;
1666 case PROCESSOR_PPC405:
1667 rs6000_cost = &ppc405_cost;
1670 case PROCESSOR_PPC440:
1671 rs6000_cost = &ppc440_cost;
1674 case PROCESSOR_PPC601:
1675 rs6000_cost = &ppc601_cost;
1678 case PROCESSOR_PPC603:
1679 rs6000_cost = &ppc603_cost;
1682 case PROCESSOR_PPC604:
1683 rs6000_cost = &ppc604_cost;
1686 case PROCESSOR_PPC604e:
1687 rs6000_cost = &ppc604e_cost;
1690 case PROCESSOR_PPC620:
1691 rs6000_cost = &ppc620_cost;
1694 case PROCESSOR_PPC630:
1695 rs6000_cost = &ppc630_cost;
1698 case PROCESSOR_CELL:
1699 rs6000_cost = &ppccell_cost;
1702 case PROCESSOR_PPC750:
1703 case PROCESSOR_PPC7400:
1704 rs6000_cost = &ppc750_cost;
1707 case PROCESSOR_PPC7450:
1708 rs6000_cost = &ppc7450_cost;
1711 case PROCESSOR_PPC8540:
1712 rs6000_cost = &ppc8540_cost;
1715 case PROCESSOR_POWER4:
1716 case PROCESSOR_POWER5:
1717 rs6000_cost = &power4_cost;
1720 case PROCESSOR_POWER6:
1721 rs6000_cost = &power6_cost;
1729 /* Implement targetm.vectorize.builtin_mask_for_load. */
1731 rs6000_builtin_mask_for_load (void)
1734 return altivec_builtin_mask_for_load;
1739 /* Implement targetm.vectorize.builtin_conversion. */
1741 rs6000_builtin_conversion (enum tree_code code, tree type)
1743 if (!TARGET_ALTIVEC)
1749 switch (TYPE_MODE (type))
1752 return TYPE_UNSIGNED (type) ?
1753 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1754 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1763 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1765 rs6000_builtin_mul_widen_even (tree type)
1767 if (!TARGET_ALTIVEC)
1770 switch (TYPE_MODE (type))
1773 return TYPE_UNSIGNED (type) ?
1774 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1775 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1778 return TYPE_UNSIGNED (type) ?
1779 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1780 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1786 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1788 rs6000_builtin_mul_widen_odd (tree type)
1790 if (!TARGET_ALTIVEC)
1793 switch (TYPE_MODE (type))
1796 return TYPE_UNSIGNED (type) ?
1797 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1798 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1801 return TYPE_UNSIGNED (type) ?
1802 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1803 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1809 /* Handle generic options of the form -mfoo=yes/no.
1810 NAME is the option name.
1811 VALUE is the option value.
1812 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1813 whether the option value is 'yes' or 'no' respectively. */
1815 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1819 else if (!strcmp (value, "yes"))
1821 else if (!strcmp (value, "no"))
1824 error ("unknown -m%s= option specified: '%s'", name, value);
1827 /* Validate and record the size specified with the -mtls-size option. */
1830 rs6000_parse_tls_size_option (void)
1832 if (rs6000_tls_size_string == 0)
1834 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1835 rs6000_tls_size = 16;
1836 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1837 rs6000_tls_size = 32;
1838 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1839 rs6000_tls_size = 64;
1841 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1845 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1847 if (DEFAULT_ABI == ABI_DARWIN)
1848 /* The Darwin libraries never set errno, so we might as well
1849 avoid calling them when that's the only reason we would. */
1850 flag_errno_math = 0;
1852 /* Double growth factor to counter reduced min jump length. */
1853 set_param_value ("max-grow-copy-bb-insns", 16);
1855 /* Enable section anchors by default.
1856 Skip section anchors for Objective C and Objective C++
1857 until front-ends fixed. */
1858 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
1859 flag_section_anchors = 1;
1862 /* Implement TARGET_HANDLE_OPTION. */
1865 rs6000_handle_option (size_t code, const char *arg, int value)
1870 target_flags &= ~(MASK_POWER | MASK_POWER2
1871 | MASK_MULTIPLE | MASK_STRING);
1872 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1873 | MASK_MULTIPLE | MASK_STRING);
1875 case OPT_mno_powerpc:
1876 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1877 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1878 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1879 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1882 target_flags &= ~MASK_MINIMAL_TOC;
1883 TARGET_NO_FP_IN_TOC = 0;
1884 TARGET_NO_SUM_IN_TOC = 0;
1885 target_flags_explicit |= MASK_MINIMAL_TOC;
1886 #ifdef TARGET_USES_SYSV4_OPT
1887 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1888 just the same as -mminimal-toc. */
1889 target_flags |= MASK_MINIMAL_TOC;
1890 target_flags_explicit |= MASK_MINIMAL_TOC;
1894 #ifdef TARGET_USES_SYSV4_OPT
1896 /* Make -mtoc behave like -mminimal-toc. */
1897 target_flags |= MASK_MINIMAL_TOC;
1898 target_flags_explicit |= MASK_MINIMAL_TOC;
1902 #ifdef TARGET_USES_AIX64_OPT
1907 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1908 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1909 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1912 #ifdef TARGET_USES_AIX64_OPT
1917 target_flags &= ~MASK_POWERPC64;
1918 target_flags_explicit |= MASK_POWERPC64;
1921 case OPT_minsert_sched_nops_:
1922 rs6000_sched_insert_nops_str = arg;
1925 case OPT_mminimal_toc:
1928 TARGET_NO_FP_IN_TOC = 0;
1929 TARGET_NO_SUM_IN_TOC = 0;
1936 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1937 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1944 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1945 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1949 case OPT_mpowerpc_gpopt:
1950 case OPT_mpowerpc_gfxopt:
1953 target_flags |= MASK_POWERPC;
1954 target_flags_explicit |= MASK_POWERPC;
1958 case OPT_maix_struct_return:
1959 case OPT_msvr4_struct_return:
1960 rs6000_explicit_options.aix_struct_ret = true;
1964 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1968 rs6000_explicit_options.isel = true;
1969 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1973 rs6000_explicit_options.spe = true;
1974 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1978 rs6000_debug_name = arg;
1981 #ifdef TARGET_USES_SYSV4_OPT
1983 rs6000_abi_name = arg;
1987 rs6000_sdata_name = arg;
1990 case OPT_mtls_size_:
1991 rs6000_tls_size_string = arg;
1994 case OPT_mrelocatable:
1997 target_flags |= MASK_MINIMAL_TOC;
1998 target_flags_explicit |= MASK_MINIMAL_TOC;
1999 TARGET_NO_FP_IN_TOC = 1;
2003 case OPT_mrelocatable_lib:
2006 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2007 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2008 TARGET_NO_FP_IN_TOC = 1;
2012 target_flags &= ~MASK_RELOCATABLE;
2013 target_flags_explicit |= MASK_RELOCATABLE;
2019 if (!strcmp (arg, "altivec"))
2021 rs6000_explicit_options.abi = true;
2022 rs6000_altivec_abi = 1;
2025 else if (! strcmp (arg, "no-altivec"))
2027 /* ??? Don't set rs6000_explicit_options.abi here, to allow
2028 the default for rs6000_spe_abi to be chosen later. */
2029 rs6000_altivec_abi = 0;
2031 else if (! strcmp (arg, "spe"))
2033 rs6000_explicit_options.abi = true;
2035 rs6000_altivec_abi = 0;
2036 if (!TARGET_SPE_ABI)
2037 error ("not configured for ABI: '%s'", arg);
2039 else if (! strcmp (arg, "no-spe"))
2041 rs6000_explicit_options.abi = true;
2045 /* These are here for testing during development only, do not
2046 document in the manual please. */
2047 else if (! strcmp (arg, "d64"))
2049 rs6000_darwin64_abi = 1;
2050 warning (0, "Using darwin64 ABI");
2052 else if (! strcmp (arg, "d32"))
2054 rs6000_darwin64_abi = 0;
2055 warning (0, "Using old darwin ABI");
2058 else if (! strcmp (arg, "ibmlongdouble"))
2060 rs6000_explicit_options.ieee = true;
2061 rs6000_ieeequad = 0;
2062 warning (0, "Using IBM extended precision long double");
2064 else if (! strcmp (arg, "ieeelongdouble"))
2066 rs6000_explicit_options.ieee = true;
2067 rs6000_ieeequad = 1;
2068 warning (0, "Using IEEE extended precision long double");
2073 error ("unknown ABI specified: '%s'", arg);
2079 rs6000_select[1].string = arg;
2083 rs6000_select[2].string = arg;
2086 case OPT_mtraceback_:
2087 rs6000_traceback_name = arg;
2090 case OPT_mfloat_gprs_:
2091 rs6000_explicit_options.float_gprs = true;
2092 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2093 rs6000_float_gprs = 1;
2094 else if (! strcmp (arg, "double"))
2095 rs6000_float_gprs = 2;
2096 else if (! strcmp (arg, "no"))
2097 rs6000_float_gprs = 0;
2100 error ("invalid option for -mfloat-gprs: '%s'", arg);
2105 case OPT_mlong_double_:
2106 rs6000_explicit_options.long_double = true;
2107 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2108 if (value != 64 && value != 128)
2110 error ("Unknown switch -mlong-double-%s", arg);
2111 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2115 rs6000_long_double_type_size = value;
2118 case OPT_msched_costly_dep_:
2119 rs6000_sched_costly_dep_str = arg;
2123 rs6000_explicit_options.alignment = true;
2124 if (! strcmp (arg, "power"))
2126 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2127 some C library functions, so warn about it. The flag may be
2128 useful for performance studies from time to time though, so
2129 don't disable it entirely. */
2130 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2131 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2132 " it is incompatible with the installed C and C++ libraries");
2133 rs6000_alignment_flags = MASK_ALIGN_POWER;
2135 else if (! strcmp (arg, "natural"))
2136 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2139 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2147 /* Do anything needed at the start of the asm file. */
2150 rs6000_file_start (void)
2154 const char *start = buffer;
2155 struct rs6000_cpu_select *ptr;
2156 const char *default_cpu = TARGET_CPU_DEFAULT;
2157 FILE *file = asm_out_file;
2159 default_file_start ();
2161 #ifdef TARGET_BI_ARCH
2162 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2166 if (flag_verbose_asm)
2168 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2169 rs6000_select[0].string = default_cpu;
2171 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2173 ptr = &rs6000_select[i];
2174 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2176 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2181 if (PPC405_ERRATUM77)
2183 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2187 #ifdef USING_ELFOS_H
2188 switch (rs6000_sdata)
2190 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2191 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2192 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2193 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2196 if (rs6000_sdata && g_switch_value)
2198 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2208 #ifdef HAVE_AS_GNU_ATTRIBUTE
2209 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
2210 fprintf (file, "\t.gnu_attribute 4, %d\n",
2211 (TARGET_HARD_FLOAT && TARGET_FPRS) ? 1 : 2);
2214 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2216 switch_to_section (toc_section);
2217 switch_to_section (text_section);
2222 /* Return nonzero if this function is known to have a null epilogue. */
2225 direct_return (void)
2227 if (reload_completed)
2229 rs6000_stack_t *info = rs6000_stack_info ();
2231 if (info->first_gp_reg_save == 32
2232 && info->first_fp_reg_save == 64
2233 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2234 && ! info->lr_save_p
2235 && ! info->cr_save_p
2236 && info->vrsave_mask == 0
2244 /* Return the number of instructions it takes to form a constant in an
2245 integer register. */
2248 num_insns_constant_wide (HOST_WIDE_INT value)
2250 /* signed constant loadable with {cal|addi} */
2251 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2254 /* constant loadable with {cau|addis} */
2255 else if ((value & 0xffff) == 0
2256 && (value >> 31 == -1 || value >> 31 == 0))
2259 #if HOST_BITS_PER_WIDE_INT == 64
2260 else if (TARGET_POWERPC64)
2262 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2263 HOST_WIDE_INT high = value >> 31;
2265 if (high == 0 || high == -1)
2271 return num_insns_constant_wide (high) + 1;
2273 return (num_insns_constant_wide (high)
2274 + num_insns_constant_wide (low) + 1);
2283 num_insns_constant (rtx op, enum machine_mode mode)
2285 HOST_WIDE_INT low, high;
2287 switch (GET_CODE (op))
2290 #if HOST_BITS_PER_WIDE_INT == 64
2291 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2292 && mask64_operand (op, mode))
2296 return num_insns_constant_wide (INTVAL (op));
2304 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2305 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2306 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2309 if (mode == VOIDmode || mode == DImode)
2311 high = CONST_DOUBLE_HIGH (op);
2312 low = CONST_DOUBLE_LOW (op);
2319 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2320 if (DECIMAL_FLOAT_MODE_P (mode))
2321 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2323 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2324 high = l[WORDS_BIG_ENDIAN == 0];
2325 low = l[WORDS_BIG_ENDIAN != 0];
2329 return (num_insns_constant_wide (low)
2330 + num_insns_constant_wide (high));
2333 if ((high == 0 && low >= 0)
2334 || (high == -1 && low < 0))
2335 return num_insns_constant_wide (low);
2337 else if (mask64_operand (op, mode))
2341 return num_insns_constant_wide (high) + 1;
2344 return (num_insns_constant_wide (high)
2345 + num_insns_constant_wide (low) + 1);
2353 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2354 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2355 corresponding element of the vector, but for V4SFmode and V2SFmode,
2356 the corresponding "float" is interpreted as an SImode integer. */
2358 static HOST_WIDE_INT
2359 const_vector_elt_as_int (rtx op, unsigned int elt)
2361 rtx tmp = CONST_VECTOR_ELT (op, elt);
2362 if (GET_MODE (op) == V4SFmode
2363 || GET_MODE (op) == V2SFmode)
2364 tmp = gen_lowpart (SImode, tmp);
2365 return INTVAL (tmp);
2368 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2369 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2370 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2371 all items are set to the same value and contain COPIES replicas of the
2372 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2373 operand and the others are set to the value of the operand's msb. */
2376 vspltis_constant (rtx op, unsigned step, unsigned copies)
2378 enum machine_mode mode = GET_MODE (op);
2379 enum machine_mode inner = GET_MODE_INNER (mode);
2382 unsigned nunits = GET_MODE_NUNITS (mode);
2383 unsigned bitsize = GET_MODE_BITSIZE (inner);
2384 unsigned mask = GET_MODE_MASK (inner);
2386 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2387 HOST_WIDE_INT splat_val = val;
2388 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2390 /* Construct the value to be splatted, if possible. If not, return 0. */
2391 for (i = 2; i <= copies; i *= 2)
2393 HOST_WIDE_INT small_val;
2395 small_val = splat_val >> bitsize;
2397 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2399 splat_val = small_val;
2402 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2403 if (EASY_VECTOR_15 (splat_val))
2406 /* Also check if we can splat, and then add the result to itself. Do so if
2407 the value is positive, of if the splat instruction is using OP's mode;
2408 for splat_val < 0, the splat and the add should use the same mode. */
2409 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2410 && (splat_val >= 0 || (step == 1 && copies == 1)))
2416 /* Check if VAL is present in every STEP-th element, and the
2417 other elements are filled with its most significant bit. */
2418 for (i = 0; i < nunits - 1; ++i)
2420 HOST_WIDE_INT desired_val;
2421 if (((i + 1) & (step - 1)) == 0)
2424 desired_val = msb_val;
2426 if (desired_val != const_vector_elt_as_int (op, i))
2434 /* Return true if OP is of the given MODE and can be synthesized
2435 with a vspltisb, vspltish or vspltisw. */
2438 easy_altivec_constant (rtx op, enum machine_mode mode)
2440 unsigned step, copies;
2442 if (mode == VOIDmode)
2443 mode = GET_MODE (op);
2444 else if (mode != GET_MODE (op))
2447 /* Start with a vspltisw. */
2448 step = GET_MODE_NUNITS (mode) / 4;
2451 if (vspltis_constant (op, step, copies))
2454 /* Then try with a vspltish. */
2460 if (vspltis_constant (op, step, copies))
2463 /* And finally a vspltisb. */
2469 if (vspltis_constant (op, step, copies))
2475 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2476 result is OP. Abort if it is not possible. */
2479 gen_easy_altivec_constant (rtx op)
2481 enum machine_mode mode = GET_MODE (op);
2482 int nunits = GET_MODE_NUNITS (mode);
2483 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2484 unsigned step = nunits / 4;
2485 unsigned copies = 1;
2487 /* Start with a vspltisw. */
2488 if (vspltis_constant (op, step, copies))
2489 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2491 /* Then try with a vspltish. */
2497 if (vspltis_constant (op, step, copies))
2498 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2500 /* And finally a vspltisb. */
2506 if (vspltis_constant (op, step, copies))
2507 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2513 output_vec_const_move (rtx *operands)
2516 enum machine_mode mode;
2521 mode = GET_MODE (dest);
2526 if (zero_constant (vec, mode))
2527 return "vxor %0,%0,%0";
2529 splat_vec = gen_easy_altivec_constant (vec);
2530 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2531 operands[1] = XEXP (splat_vec, 0);
2532 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2535 switch (GET_MODE (splat_vec))
2538 return "vspltisw %0,%1";
2541 return "vspltish %0,%1";
2544 return "vspltisb %0,%1";
2551 gcc_assert (TARGET_SPE);
2553 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2554 pattern of V1DI, V4HI, and V2SF.
2556 FIXME: We should probably return # and add post reload
2557 splitters for these, but this way is so easy ;-). */
2558 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2559 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2560 operands[1] = CONST_VECTOR_ELT (vec, 0);
2561 operands[2] = CONST_VECTOR_ELT (vec, 1);
2563 return "li %0,%1\n\tevmergelo %0,%0,%0";
2565 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2568 /* Initialize vector TARGET to VALS. */
2571 rs6000_expand_vector_init (rtx target, rtx vals)
2573 enum machine_mode mode = GET_MODE (target);
2574 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2575 int n_elts = GET_MODE_NUNITS (mode);
2576 int n_var = 0, one_var = -1;
2577 bool all_same = true, all_const_zero = true;
2581 for (i = 0; i < n_elts; ++i)
2583 x = XVECEXP (vals, 0, i);
2584 if (!CONSTANT_P (x))
2585 ++n_var, one_var = i;
2586 else if (x != CONST0_RTX (inner_mode))
2587 all_const_zero = false;
2589 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2595 if (mode != V4SFmode && all_const_zero)
2597 /* Zero register. */
2598 emit_insn (gen_rtx_SET (VOIDmode, target,
2599 gen_rtx_XOR (mode, target, target)));
2602 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2604 /* Splat immediate. */
2605 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2609 ; /* Splat vector element. */
2612 /* Load from constant pool. */
2613 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2618 /* Store value to stack temp. Load vector element. Splat. */
2621 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2622 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2623 XVECEXP (vals, 0, 0));
2624 x = gen_rtx_UNSPEC (VOIDmode,
2625 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2626 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2628 gen_rtx_SET (VOIDmode,
2631 x = gen_rtx_VEC_SELECT (inner_mode, target,
2632 gen_rtx_PARALLEL (VOIDmode,
2633 gen_rtvec (1, const0_rtx)));
2634 emit_insn (gen_rtx_SET (VOIDmode, target,
2635 gen_rtx_VEC_DUPLICATE (mode, x)));
2639 /* One field is non-constant. Load constant then overwrite
2643 rtx copy = copy_rtx (vals);
2645 /* Load constant part of vector, substitute neighboring value for
2647 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2648 rs6000_expand_vector_init (target, copy);
2650 /* Insert variable. */
2651 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2655 /* Construct the vector in memory one field at a time
2656 and load the whole vector. */
2657 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2658 for (i = 0; i < n_elts; i++)
2659 emit_move_insn (adjust_address_nv (mem, inner_mode,
2660 i * GET_MODE_SIZE (inner_mode)),
2661 XVECEXP (vals, 0, i));
2662 emit_move_insn (target, mem);
2665 /* Set field ELT of TARGET to VAL. */
2668 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2670 enum machine_mode mode = GET_MODE (target);
2671 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2672 rtx reg = gen_reg_rtx (mode);
2674 int width = GET_MODE_SIZE (inner_mode);
2677 /* Load single variable value. */
2678 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2679 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2680 x = gen_rtx_UNSPEC (VOIDmode,
2681 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2682 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2684 gen_rtx_SET (VOIDmode,
2688 /* Linear sequence. */
2689 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2690 for (i = 0; i < 16; ++i)
2691 XVECEXP (mask, 0, i) = GEN_INT (i);
2693 /* Set permute mask to insert element into target. */
2694 for (i = 0; i < width; ++i)
2695 XVECEXP (mask, 0, elt*width + i)
2696 = GEN_INT (i + 0x10);
2697 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2698 x = gen_rtx_UNSPEC (mode,
2699 gen_rtvec (3, target, reg,
2700 force_reg (V16QImode, x)),
2702 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2705 /* Extract field ELT from VEC into TARGET. */
2708 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2710 enum machine_mode mode = GET_MODE (vec);
2711 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2714 /* Allocate mode-sized buffer. */
2715 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2717 /* Add offset to field within buffer matching vector element. */
2718 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2720 /* Store single field into mode-sized buffer. */
2721 x = gen_rtx_UNSPEC (VOIDmode,
2722 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2723 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2725 gen_rtx_SET (VOIDmode,
2728 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2731 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2732 implement ANDing by the mask IN. */
2734 build_mask64_2_operands (rtx in, rtx *out)
2736 #if HOST_BITS_PER_WIDE_INT >= 64
2737 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2740 gcc_assert (GET_CODE (in) == CONST_INT);
2745 /* Assume c initially something like 0x00fff000000fffff. The idea
2746 is to rotate the word so that the middle ^^^^^^ group of zeros
2747 is at the MS end and can be cleared with an rldicl mask. We then
2748 rotate back and clear off the MS ^^ group of zeros with a
2750 c = ~c; /* c == 0xff000ffffff00000 */
2751 lsb = c & -c; /* lsb == 0x0000000000100000 */
2752 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2753 c = ~c; /* c == 0x00fff000000fffff */
2754 c &= -lsb; /* c == 0x00fff00000000000 */
2755 lsb = c & -c; /* lsb == 0x0000100000000000 */
2756 c = ~c; /* c == 0xff000fffffffffff */
2757 c &= -lsb; /* c == 0xff00000000000000 */
2759 while ((lsb >>= 1) != 0)
2760 shift++; /* shift == 44 on exit from loop */
2761 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2762 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2763 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2767 /* Assume c initially something like 0xff000f0000000000. The idea
2768 is to rotate the word so that the ^^^ middle group of zeros
2769 is at the LS end and can be cleared with an rldicr mask. We then
2770 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2772 lsb = c & -c; /* lsb == 0x0000010000000000 */
2773 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2774 c = ~c; /* c == 0x00fff0ffffffffff */
2775 c &= -lsb; /* c == 0x00fff00000000000 */
2776 lsb = c & -c; /* lsb == 0x0000100000000000 */
2777 c = ~c; /* c == 0xff000fffffffffff */
2778 c &= -lsb; /* c == 0xff00000000000000 */
2780 while ((lsb >>= 1) != 0)
2781 shift++; /* shift == 44 on exit from loop */
2782 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2783 m1 >>= shift; /* m1 == 0x0000000000000fff */
2784 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2787 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2788 masks will be all 1's. We are guaranteed more than one transition. */
2789 out[0] = GEN_INT (64 - shift);
2790 out[1] = GEN_INT (m1);
2791 out[2] = GEN_INT (shift);
2792 out[3] = GEN_INT (m2);
2800 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2803 invalid_e500_subreg (rtx op, enum machine_mode mode)
2805 if (TARGET_E500_DOUBLE)
2807 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
2808 subreg:TI and reg:TF. */
2809 if (GET_CODE (op) == SUBREG
2810 && (mode == SImode || mode == DImode || mode == TImode)
2811 && REG_P (SUBREG_REG (op))
2812 && (GET_MODE (SUBREG_REG (op)) == DFmode
2813 || GET_MODE (SUBREG_REG (op)) == TFmode))
2816 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
2818 if (GET_CODE (op) == SUBREG
2819 && (mode == DFmode || mode == TFmode)
2820 && REG_P (SUBREG_REG (op))
2821 && (GET_MODE (SUBREG_REG (op)) == DImode
2822 || GET_MODE (SUBREG_REG (op)) == TImode))
2827 && GET_CODE (op) == SUBREG
2829 && REG_P (SUBREG_REG (op))
2830 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
2836 /* AIX increases natural record alignment to doubleword if the first
2837 field is an FP double while the FP fields remain word aligned. */
2840 rs6000_special_round_type_align (tree type, unsigned int computed,
2841 unsigned int specified)
2843 unsigned int align = MAX (computed, specified);
2844 tree field = TYPE_FIELDS (type);
2846 /* Skip all non field decls */
2847 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2848 field = TREE_CHAIN (field);
2850 if (field != NULL && field != type)
2852 type = TREE_TYPE (field);
2853 while (TREE_CODE (type) == ARRAY_TYPE)
2854 type = TREE_TYPE (type);
2856 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2857 align = MAX (align, 64);
2863 /* Darwin increases record alignment to the natural alignment of
2867 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
2868 unsigned int specified)
2870 unsigned int align = MAX (computed, specified);
2872 if (TYPE_PACKED (type))
2875 /* Find the first field, looking down into aggregates. */
2877 tree field = TYPE_FIELDS (type);
2878 /* Skip all non field decls */
2879 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2880 field = TREE_CHAIN (field);
2883 type = TREE_TYPE (field);
2884 while (TREE_CODE (type) == ARRAY_TYPE)
2885 type = TREE_TYPE (type);
2886 } while (AGGREGATE_TYPE_P (type));
2888 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
2889 align = MAX (align, TYPE_ALIGN (type));
2894 /* Return 1 for an operand in small memory on V.4/eabi. */
2897 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2898 enum machine_mode mode ATTRIBUTE_UNUSED)
2903 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2906 if (DEFAULT_ABI != ABI_V4)
2909 if (GET_CODE (op) == SYMBOL_REF)
2912 else if (GET_CODE (op) != CONST
2913 || GET_CODE (XEXP (op, 0)) != PLUS
2914 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2915 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2920 rtx sum = XEXP (op, 0);
2921 HOST_WIDE_INT summand;
2923 /* We have to be careful here, because it is the referenced address
2924 that must be 32k from _SDA_BASE_, not just the symbol. */
2925 summand = INTVAL (XEXP (sum, 1));
2926 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2929 sym_ref = XEXP (sum, 0);
2932 return SYMBOL_REF_SMALL_P (sym_ref);
2938 /* Return true if either operand is a general purpose register. */
2941 gpr_or_gpr_p (rtx op0, rtx op1)
2943 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2944 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2948 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2951 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2953 switch (GET_CODE (op))
2956 if (RS6000_SYMBOL_REF_TLS_P (op))
2958 else if (CONSTANT_POOL_ADDRESS_P (op))
2960 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2968 else if (! strcmp (XSTR (op, 0), toc_label_name))
2977 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2978 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2980 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2989 constant_pool_expr_p (rtx op)
2993 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2997 toc_relative_expr_p (rtx op)
3001 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3005 legitimate_constant_pool_address_p (rtx x)
3008 && GET_CODE (x) == PLUS
3009 && GET_CODE (XEXP (x, 0)) == REG
3010 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3011 && constant_pool_expr_p (XEXP (x, 1)));
3015 legitimate_small_data_p (enum machine_mode mode, rtx x)
3017 return (DEFAULT_ABI == ABI_V4
3018 && !flag_pic && !TARGET_TOC
3019 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3020 && small_data_operand (x, mode));
3023 /* SPE offset addressing is limited to 5-bits worth of double words. */
3024 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3027 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3029 unsigned HOST_WIDE_INT offset, extra;
3031 if (GET_CODE (x) != PLUS)
3033 if (GET_CODE (XEXP (x, 0)) != REG)
3035 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3037 if (legitimate_constant_pool_address_p (x))
3039 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3042 offset = INTVAL (XEXP (x, 1));
3050 /* AltiVec vector modes. Only reg+reg addressing is valid and
3051 constant offset zero should not occur due to canonicalization.
3052 Allow any offset when not strict before reload. */
3059 /* SPE vector modes. */
3060 return SPE_CONST_OFFSET_OK (offset);
3064 if (TARGET_E500_DOUBLE)
3065 return SPE_CONST_OFFSET_OK (offset);
3068 /* On e500v2, we may have:
3070 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3072 Which gets addressed with evldd instructions. */
3073 if (TARGET_E500_DOUBLE)
3074 return SPE_CONST_OFFSET_OK (offset);
3076 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3078 else if (offset & 3)
3083 if (TARGET_E500_DOUBLE)
3084 return (SPE_CONST_OFFSET_OK (offset)
3085 && SPE_CONST_OFFSET_OK (offset + 8));
3089 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3091 else if (offset & 3)
3102 return (offset < 0x10000) && (offset + extra < 0x10000);
3106 legitimate_indexed_address_p (rtx x, int strict)
3110 if (GET_CODE (x) != PLUS)
3116 /* Recognize the rtl generated by reload which we know will later be
3117 replaced with proper base and index regs. */
3119 && reload_in_progress
3120 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3124 return (REG_P (op0) && REG_P (op1)
3125 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3126 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3127 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3128 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3132 legitimate_indirect_address_p (rtx x, int strict)
3134 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3138 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3140 if (!TARGET_MACHO || !flag_pic
3141 || mode != SImode || GET_CODE (x) != MEM)
3145 if (GET_CODE (x) != LO_SUM)
3147 if (GET_CODE (XEXP (x, 0)) != REG)
3149 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3153 return CONSTANT_P (x);
3157 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3159 if (GET_CODE (x) != LO_SUM)
3161 if (GET_CODE (XEXP (x, 0)) != REG)
3163 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3165 /* Restrict addressing for DI because of our SUBREG hackery. */
3166 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3171 if (TARGET_ELF || TARGET_MACHO)
3173 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3177 if (GET_MODE_NUNITS (mode) != 1)
3179 if (GET_MODE_BITSIZE (mode) > 64
3180 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3181 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3184 return CONSTANT_P (x);
3191 /* Try machine-dependent ways of modifying an illegitimate address
3192 to be legitimate. If we find one, return the new, valid address.
3193 This is used from only one place: `memory_address' in explow.c.
3195 OLDX is the address as it was before break_out_memory_refs was
3196 called. In some cases it is useful to look at this to decide what
3199 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3201 It is always safe for this function to do nothing. It exists to
3202 recognize opportunities to optimize the output.
3204 On RS/6000, first check for the sum of a register with a constant
3205 integer that is out of range. If so, generate code to add the
3206 constant with the low-order 16 bits masked to the register and force
3207 this result into another register (this can be done with `cau').
3208 Then generate an address of REG+(CONST&0xffff), allowing for the
3209 possibility of bit 16 being a one.
3211 Then check for the sum of a register and something not constant, try to
3212 load the other things into a register and return the sum. */
3215 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3216 enum machine_mode mode)
3218 if (GET_CODE (x) == SYMBOL_REF)
3220 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3222 return rs6000_legitimize_tls_address (x, model);
3225 if (GET_CODE (x) == PLUS
3226 && GET_CODE (XEXP (x, 0)) == REG
3227 && GET_CODE (XEXP (x, 1)) == CONST_INT
3228 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3230 HOST_WIDE_INT high_int, low_int;
3232 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3233 high_int = INTVAL (XEXP (x, 1)) - low_int;
3234 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3235 GEN_INT (high_int)), 0);
3236 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3238 else if (GET_CODE (x) == PLUS
3239 && GET_CODE (XEXP (x, 0)) == REG
3240 && GET_CODE (XEXP (x, 1)) != CONST_INT
3241 && GET_MODE_NUNITS (mode) == 1
3242 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3244 || (((mode != DImode && mode != DFmode && mode != DDmode)
3245 || TARGET_E500_DOUBLE)
3246 && mode != TFmode && mode != TDmode))
3247 && (TARGET_POWERPC64 || mode != DImode)
3250 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3251 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3253 else if (ALTIVEC_VECTOR_MODE (mode))
3257 /* Make sure both operands are registers. */
3258 if (GET_CODE (x) == PLUS)
3259 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3260 force_reg (Pmode, XEXP (x, 1)));
3262 reg = force_reg (Pmode, x);
3265 else if (SPE_VECTOR_MODE (mode)
3266 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3267 || mode == DDmode || mode == TDmode
3268 || mode == DImode)))
3272 /* We accept [reg + reg] and [reg + OFFSET]. */
3274 if (GET_CODE (x) == PLUS)
3276 rtx op1 = XEXP (x, 0);
3277 rtx op2 = XEXP (x, 1);
3279 op1 = force_reg (Pmode, op1);
3281 if (GET_CODE (op2) != REG
3282 && (GET_CODE (op2) != CONST_INT
3283 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3284 op2 = force_reg (Pmode, op2);
3286 return gen_rtx_PLUS (Pmode, op1, op2);
3289 return force_reg (Pmode, x);
3295 && GET_CODE (x) != CONST_INT
3296 && GET_CODE (x) != CONST_DOUBLE
3298 && GET_MODE_NUNITS (mode) == 1
3299 && (GET_MODE_BITSIZE (mode) <= 32
3300 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3302 rtx reg = gen_reg_rtx (Pmode);
3303 emit_insn (gen_elf_high (reg, x));
3304 return gen_rtx_LO_SUM (Pmode, reg, x);
3306 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3309 && ! MACHO_DYNAMIC_NO_PIC_P
3311 && GET_CODE (x) != CONST_INT
3312 && GET_CODE (x) != CONST_DOUBLE
3314 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3318 rtx reg = gen_reg_rtx (Pmode);
3319 emit_insn (gen_macho_high (reg, x));
3320 return gen_rtx_LO_SUM (Pmode, reg, x);
3323 && constant_pool_expr_p (x)
3324 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3326 return create_TOC_reference (x);
3332 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3333 We need to emit DTP-relative relocations. */
3336 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3341 fputs ("\t.long\t", file);
3344 fputs (DOUBLE_INT_ASM_OP, file);
3349 output_addr_const (file, x);
3350 fputs ("@dtprel+0x8000", file);
3353 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3355 static GTY(()) rtx rs6000_tls_symbol;
3357 rs6000_tls_get_addr (void)
3359 if (!rs6000_tls_symbol)
3360 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3362 return rs6000_tls_symbol;
3365 /* Construct the SYMBOL_REF for TLS GOT references. */
3367 static GTY(()) rtx rs6000_got_symbol;
3369 rs6000_got_sym (void)
3371 if (!rs6000_got_symbol)
3373 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3374 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3375 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3378 return rs6000_got_symbol;
3381 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3382 this (thread-local) address. */
3385 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3389 dest = gen_reg_rtx (Pmode);
3390 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3396 tlsreg = gen_rtx_REG (Pmode, 13);
3397 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3401 tlsreg = gen_rtx_REG (Pmode, 2);
3402 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3406 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3410 tmp = gen_reg_rtx (Pmode);
3413 tlsreg = gen_rtx_REG (Pmode, 13);
3414 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3418 tlsreg = gen_rtx_REG (Pmode, 2);
3419 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3423 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3425 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3430 rtx r3, got, tga, tmp1, tmp2, eqv;
3432 /* We currently use relocations like @got@tlsgd for tls, which
3433 means the linker will handle allocation of tls entries, placing
3434 them in the .got section. So use a pointer to the .got section,
3435 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3436 or to secondary GOT sections used by 32-bit -fPIC. */
3438 got = gen_rtx_REG (Pmode, 2);
3442 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3445 rtx gsym = rs6000_got_sym ();
3446 got = gen_reg_rtx (Pmode);
3448 rs6000_emit_move (got, gsym, Pmode);
3454 tmp1 = gen_reg_rtx (Pmode);
3455 tmp2 = gen_reg_rtx (Pmode);
3456 tmp3 = gen_reg_rtx (Pmode);
3457 mem = gen_const_mem (Pmode, tmp1);
3459 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3460 emit_move_insn (tmp1,
3461 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
3462 emit_move_insn (tmp2, mem);
3463 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3464 last = emit_move_insn (got, tmp3);
3465 set_unique_reg_note (last, REG_EQUAL, gsym);
3466 maybe_encapsulate_block (first, last, gsym);
3471 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3473 r3 = gen_rtx_REG (Pmode, 3);
3475 insn = gen_tls_gd_64 (r3, got, addr);
3477 insn = gen_tls_gd_32 (r3, got, addr);
3480 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3481 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3482 insn = emit_call_insn (insn);
3483 CONST_OR_PURE_CALL_P (insn) = 1;
3484 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3485 insn = get_insns ();
3487 emit_libcall_block (insn, dest, r3, addr);
3489 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3491 r3 = gen_rtx_REG (Pmode, 3);
3493 insn = gen_tls_ld_64 (r3, got);
3495 insn = gen_tls_ld_32 (r3, got);
3498 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3499 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3500 insn = emit_call_insn (insn);
3501 CONST_OR_PURE_CALL_P (insn) = 1;
3502 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3503 insn = get_insns ();
3505 tmp1 = gen_reg_rtx (Pmode);
3506 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3508 emit_libcall_block (insn, tmp1, r3, eqv);
3509 if (rs6000_tls_size == 16)
3512 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3514 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3516 else if (rs6000_tls_size == 32)
3518 tmp2 = gen_reg_rtx (Pmode);
3520 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3522 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3525 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3527 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3531 tmp2 = gen_reg_rtx (Pmode);
3533 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3535 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3537 insn = gen_rtx_SET (Pmode, dest,
3538 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3544 /* IE, or 64-bit offset LE. */
3545 tmp2 = gen_reg_rtx (Pmode);
3547 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3549 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3552 insn = gen_tls_tls_64 (dest, tmp2, addr);
3554 insn = gen_tls_tls_32 (dest, tmp2, addr);
3562 /* Return 1 if X contains a thread-local symbol. */
3565 rs6000_tls_referenced_p (rtx x)
3567 if (! TARGET_HAVE_TLS)
3570 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3573 /* Return 1 if *X is a thread-local symbol. This is the same as
3574 rs6000_tls_symbol_ref except for the type of the unused argument. */
3577 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3579 return RS6000_SYMBOL_REF_TLS_P (*x);
3582 /* The convention appears to be to define this wherever it is used.
3583 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3584 is now used here. */
3585 #ifndef REG_MODE_OK_FOR_BASE_P
3586 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3589 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3590 replace the input X, or the original X if no replacement is called for.
3591 The output parameter *WIN is 1 if the calling macro should goto WIN,
3594 For RS/6000, we wish to handle large displacements off a base
3595 register by splitting the addend across an addiu/addis and the mem insn.
3596 This cuts number of extra insns needed from 3 to 1.
3598 On Darwin, we use this to generate code for floating point constants.
3599 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3600 The Darwin code is inside #if TARGET_MACHO because only then is
3601 machopic_function_base_name() defined. */
3603 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3604 int opnum, int type,
3605 int ind_levels ATTRIBUTE_UNUSED, int *win)
3607 /* We must recognize output that we have already generated ourselves. */
3608 if (GET_CODE (x) == PLUS
3609 && GET_CODE (XEXP (x, 0)) == PLUS
3610 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3611 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3612 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3614 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3615 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3616 opnum, (enum reload_type)type);
3622 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3623 && GET_CODE (x) == LO_SUM
3624 && GET_CODE (XEXP (x, 0)) == PLUS
3625 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3626 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3627 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3628 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3629 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3630 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3631 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3633 /* Result of previous invocation of this function on Darwin
3634 floating point constant. */
3635 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3636 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3637 opnum, (enum reload_type)type);
3643 /* Force ld/std non-word aligned offset into base register by wrapping
3645 if (GET_CODE (x) == PLUS
3646 && GET_CODE (XEXP (x, 0)) == REG
3647 && REGNO (XEXP (x, 0)) < 32
3648 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3649 && GET_CODE (XEXP (x, 1)) == CONST_INT
3650 && (INTVAL (XEXP (x, 1)) & 3) != 0
3651 && !ALTIVEC_VECTOR_MODE (mode)
3652 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3653 && TARGET_POWERPC64)
3655 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3656 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3657 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3658 opnum, (enum reload_type) type);
3663 if (GET_CODE (x) == PLUS
3664 && GET_CODE (XEXP (x, 0)) == REG
3665 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3666 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3667 && GET_CODE (XEXP (x, 1)) == CONST_INT
3668 && !SPE_VECTOR_MODE (mode)
3669 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3671 && !ALTIVEC_VECTOR_MODE (mode))
3673 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3674 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3676 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3678 /* Check for 32-bit overflow. */
3679 if (high + low != val)
3685 /* Reload the high part into a base reg; leave the low part
3686 in the mem directly. */
3688 x = gen_rtx_PLUS (GET_MODE (x),
3689 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3693 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3694 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3695 opnum, (enum reload_type)type);
3700 if (GET_CODE (x) == SYMBOL_REF
3701 && !ALTIVEC_VECTOR_MODE (mode)
3702 && !SPE_VECTOR_MODE (mode)
3704 && DEFAULT_ABI == ABI_DARWIN
3705 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3707 && DEFAULT_ABI == ABI_V4
3710 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
3711 The same goes for DImode without 64-bit gprs and DFmode
3715 && (mode != DImode || TARGET_POWERPC64)
3716 && (mode != DFmode || TARGET_POWERPC64
3717 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3722 rtx offset = gen_rtx_CONST (Pmode,
3723 gen_rtx_MINUS (Pmode, x,
3724 machopic_function_base_sym ()));
3725 x = gen_rtx_LO_SUM (GET_MODE (x),
3726 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3727 gen_rtx_HIGH (Pmode, offset)), offset);
3731 x = gen_rtx_LO_SUM (GET_MODE (x),
3732 gen_rtx_HIGH (Pmode, x), x);
3734 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3735 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3736 opnum, (enum reload_type)type);
3741 /* Reload an offset address wrapped by an AND that represents the
3742 masking of the lower bits. Strip the outer AND and let reload
3743 convert the offset address into an indirect address. */
3745 && ALTIVEC_VECTOR_MODE (mode)
3746 && GET_CODE (x) == AND
3747 && GET_CODE (XEXP (x, 0)) == PLUS
3748 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3749 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3750 && GET_CODE (XEXP (x, 1)) == CONST_INT
3751 && INTVAL (XEXP (x, 1)) == -16)
3759 && constant_pool_expr_p (x)
3760 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3762 x = create_TOC_reference (x);
3770 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3771 that is a valid memory address for an instruction.
3772 The MODE argument is the machine mode for the MEM expression
3773 that wants to use this address.
3775 On the RS/6000, there are four valid address: a SYMBOL_REF that
3776 refers to a constant pool entry of an address (or the sum of it
3777 plus a constant), a short (16-bit signed) constant plus a register,
3778 the sum of two registers, or a register indirect, possibly with an
3779 auto-increment. For DFmode and DImode with a constant plus register,
3780 we must ensure that both words are addressable or PowerPC64 with offset
3783 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3784 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
3785 because adjacent memory cells are accessed by adding word-sized offsets
3786 during assembly output. */
3788 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3790 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3792 && ALTIVEC_VECTOR_MODE (mode)
3793 && GET_CODE (x) == AND
3794 && GET_CODE (XEXP (x, 1)) == CONST_INT
3795 && INTVAL (XEXP (x, 1)) == -16)
3798 if (RS6000_SYMBOL_REF_TLS_P (x))
3800 if (legitimate_indirect_address_p (x, reg_ok_strict))
3802 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3803 && !ALTIVEC_VECTOR_MODE (mode)
3804 && !SPE_VECTOR_MODE (mode)
3807 /* Restrict addressing for DI because of our SUBREG hackery. */
3808 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3811 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3813 if (legitimate_small_data_p (mode, x))
3815 if (legitimate_constant_pool_address_p (x))
3817 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3819 && GET_CODE (x) == PLUS
3820 && GET_CODE (XEXP (x, 0)) == REG
3821 && (XEXP (x, 0) == virtual_stack_vars_rtx
3822 || XEXP (x, 0) == arg_pointer_rtx)
3823 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3825 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3830 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3832 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3833 && (TARGET_POWERPC64 || mode != DImode)
3834 && legitimate_indexed_address_p (x, reg_ok_strict))
3836 if (GET_CODE (x) == PRE_MODIFY
3840 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3842 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3843 && (TARGET_POWERPC64 || mode != DImode)
3844 && !ALTIVEC_VECTOR_MODE (mode)
3845 && !SPE_VECTOR_MODE (mode)
3846 /* Restrict addressing for DI because of our SUBREG hackery. */
3847 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3849 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
3850 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
3851 || legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))
3852 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3854 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3859 /* Go to LABEL if ADDR (a legitimate address expression)
3860 has an effect that depends on the machine mode it is used for.
3862 On the RS/6000 this is true of all integral offsets (since AltiVec
3863 modes don't allow them) or is a pre-increment or decrement.
3865 ??? Except that due to conceptual problems in offsettable_address_p
3866 we can't really report the problems of integral offsets. So leave
3867 this assuming that the adjustable offset must be valid for the
3868 sub-words of a TFmode operand, which is what we had before. */
3871 rs6000_mode_dependent_address (rtx addr)
3873 switch (GET_CODE (addr))
3876 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3878 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3879 return val + 12 + 0x8000 >= 0x10000;
3889 return TARGET_UPDATE;
3898 /* More elaborate version of recog's offsettable_memref_p predicate
3899 that works around the ??? note of rs6000_mode_dependent_address.
3900 In particular it accepts
3902 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
3904 in 32-bit mode, that the recog predicate rejects. */
3907 rs6000_offsettable_memref_p (rtx op)
3912 /* First mimic offsettable_memref_p. */
3913 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
3916 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
3917 the latter predicate knows nothing about the mode of the memory
3918 reference and, therefore, assumes that it is the largest supported
3919 mode (TFmode). As a consequence, legitimate offsettable memory
3920 references are rejected. rs6000_legitimate_offset_address_p contains
3921 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
3922 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
3925 /* Return number of consecutive hard regs needed starting at reg REGNO
3926 to hold something of mode MODE.
3927 This is ordinarily the length in words of a value of mode MODE
3928 but can be less for certain modes in special long registers.
3930 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3931 scalar instructions. The upper 32 bits are only available to the
3934 POWER and PowerPC GPRs hold 32 bits worth;
3935 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3938 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3940 if (FP_REGNO_P (regno))
3941 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3943 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3944 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3946 if (ALTIVEC_REGNO_P (regno))
3948 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3950 /* The value returned for SCmode in the E500 double case is 2 for
3951 ABI compatibility; storing an SCmode value in a single register
3952 would require function_arg and rs6000_spe_function_arg to handle
3953 SCmode so as to pass the value correctly in a pair of
3955 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
3956 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3958 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3961 /* Change register usage conditional on target flags. */
3963 rs6000_conditional_register_usage (void)
3967 /* Set MQ register fixed (already call_used) if not POWER
3968 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3973 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3975 fixed_regs[13] = call_used_regs[13]
3976 = call_really_used_regs[13] = 1;
3978 /* Conditionally disable FPRs. */
3979 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3980 for (i = 32; i < 64; i++)
3981 fixed_regs[i] = call_used_regs[i]
3982 = call_really_used_regs[i] = 1;
3984 /* The TOC register is not killed across calls in a way that is
3985 visible to the compiler. */
3986 if (DEFAULT_ABI == ABI_AIX)
3987 call_really_used_regs[2] = 0;
3989 if (DEFAULT_ABI == ABI_V4
3990 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3992 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3994 if (DEFAULT_ABI == ABI_V4
3995 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3997 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3998 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3999 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4001 if (DEFAULT_ABI == ABI_DARWIN
4002 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4003 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4004 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4005 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4007 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4008 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4009 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4012 global_regs[VSCR_REGNO] = 1;
4016 global_regs[SPEFSCR_REGNO] = 1;
4017 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4018 registers in prologues and epilogues. We no longer use r14
4019 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4020 pool for link-compatibility with older versions of GCC. Once
4021 "old" code has died out, we can return r14 to the allocation
4024 = call_used_regs[14]
4025 = call_really_used_regs[14] = 1;
4028 if (! TARGET_ALTIVEC)
4030 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4031 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4032 call_really_used_regs[VRSAVE_REGNO] = 1;
4035 if (TARGET_ALTIVEC_ABI)
4036 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4037 call_used_regs[i] = call_really_used_regs[i] = 1;
4040 /* Try to output insns to set TARGET equal to the constant C if it can
4041 be done in less than N insns. Do all computations in MODE.
4042 Returns the place where the output has been placed if it can be
4043 done and the insns have been emitted. If it would take more than N
4044 insns, zero is returned and no insns and emitted. */
4047 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4048 rtx source, int n ATTRIBUTE_UNUSED)
4050 rtx result, insn, set;
4051 HOST_WIDE_INT c0, c1;
4058 dest = gen_reg_rtx (mode);
4059 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4063 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
4065 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4066 GEN_INT (INTVAL (source)
4067 & (~ (HOST_WIDE_INT) 0xffff))));
4068 emit_insn (gen_rtx_SET (VOIDmode, dest,
4069 gen_rtx_IOR (SImode, copy_rtx (result),
4070 GEN_INT (INTVAL (source) & 0xffff))));
4075 switch (GET_CODE (source))
4078 c0 = INTVAL (source);
4083 #if HOST_BITS_PER_WIDE_INT >= 64
4084 c0 = CONST_DOUBLE_LOW (source);
4087 c0 = CONST_DOUBLE_LOW (source);
4088 c1 = CONST_DOUBLE_HIGH (source);
4096 result = rs6000_emit_set_long_const (dest, c0, c1);
4103 insn = get_last_insn ();
4104 set = single_set (insn);
4105 if (! CONSTANT_P (SET_SRC (set)))
4106 set_unique_reg_note (insn, REG_EQUAL, source);
4111 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4112 fall back to a straight forward decomposition. We do this to avoid
4113 exponential run times encountered when looking for longer sequences
4114 with rs6000_emit_set_const. */
4116 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4118 if (!TARGET_POWERPC64)
4120 rtx operand1, operand2;
4122 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4124 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4126 emit_move_insn (operand1, GEN_INT (c1));
4127 emit_move_insn (operand2, GEN_INT (c2));
4131 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4134 ud2 = (c1 & 0xffff0000) >> 16;
4135 #if HOST_BITS_PER_WIDE_INT >= 64
4139 ud4 = (c2 & 0xffff0000) >> 16;
4141 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4142 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4145 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4147 emit_move_insn (dest, GEN_INT (ud1));
4150 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4151 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4154 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4157 emit_move_insn (dest, GEN_INT (ud2 << 16));
4159 emit_move_insn (copy_rtx (dest),
4160 gen_rtx_IOR (DImode, copy_rtx (dest),
4163 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4164 || (ud4 == 0 && ! (ud3 & 0x8000)))
4167 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4170 emit_move_insn (dest, GEN_INT (ud3 << 16));
4173 emit_move_insn (copy_rtx (dest),
4174 gen_rtx_IOR (DImode, copy_rtx (dest),
4176 emit_move_insn (copy_rtx (dest),
4177 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4180 emit_move_insn (copy_rtx (dest),
4181 gen_rtx_IOR (DImode, copy_rtx (dest),
4187 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4190 emit_move_insn (dest, GEN_INT (ud4 << 16));
4193 emit_move_insn (copy_rtx (dest),
4194 gen_rtx_IOR (DImode, copy_rtx (dest),
4197 emit_move_insn (copy_rtx (dest),
4198 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4201 emit_move_insn (copy_rtx (dest),
4202 gen_rtx_IOR (DImode, copy_rtx (dest),
4203 GEN_INT (ud2 << 16)));
4205 emit_move_insn (copy_rtx (dest),
4206 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4212 /* Helper for the following. Get rid of [r+r] memory refs
4213 in cases where it won't work (TImode, TFmode, TDmode). */
4216 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4218 if (GET_CODE (operands[0]) == MEM
4219 && GET_CODE (XEXP (operands[0], 0)) != REG
4220 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4221 && ! reload_in_progress)
4223 = replace_equiv_address (operands[0],
4224 copy_addr_to_reg (XEXP (operands[0], 0)));
4226 if (GET_CODE (operands[1]) == MEM
4227 && GET_CODE (XEXP (operands[1], 0)) != REG
4228 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4229 && ! reload_in_progress)
4231 = replace_equiv_address (operands[1],
4232 copy_addr_to_reg (XEXP (operands[1], 0)));
4235 /* Emit a move from SOURCE to DEST in mode MODE. */
4237 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4241 operands[1] = source;
4243 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4244 if (GET_CODE (operands[1]) == CONST_DOUBLE
4245 && ! FLOAT_MODE_P (mode)
4246 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4248 /* FIXME. This should never happen. */
4249 /* Since it seems that it does, do the safe thing and convert
4251 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4253 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4254 || FLOAT_MODE_P (mode)
4255 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4256 || CONST_DOUBLE_LOW (operands[1]) < 0)
4257 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4258 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4260 /* Check if GCC is setting up a block move that will end up using FP
4261 registers as temporaries. We must make sure this is acceptable. */
4262 if (GET_CODE (operands[0]) == MEM
4263 && GET_CODE (operands[1]) == MEM
4265 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4266 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4267 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4268 ? 32 : MEM_ALIGN (operands[0])))
4269 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4271 : MEM_ALIGN (operands[1]))))
4272 && ! MEM_VOLATILE_P (operands [0])
4273 && ! MEM_VOLATILE_P (operands [1]))
4275 emit_move_insn (adjust_address (operands[0], SImode, 0),
4276 adjust_address (operands[1], SImode, 0));
4277 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4278 adjust_address (copy_rtx (operands[1]), SImode, 4));
4282 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
4283 && !gpc_reg_operand (operands[1], mode))
4284 operands[1] = force_reg (mode, operands[1]);
4286 if (mode == SFmode && ! TARGET_POWERPC
4287 && TARGET_HARD_FLOAT && TARGET_FPRS
4288 && GET_CODE (operands[0]) == MEM)
4292 if (reload_in_progress || reload_completed)
4293 regnum = true_regnum (operands[1]);
4294 else if (GET_CODE (operands[1]) == REG)
4295 regnum = REGNO (operands[1]);
4299 /* If operands[1] is a register, on POWER it may have
4300 double-precision data in it, so truncate it to single
4302 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4305 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
4306 : gen_reg_rtx (mode));
4307 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4308 operands[1] = newreg;
4312 /* Recognize the case where operand[1] is a reference to thread-local
4313 data and load its address to a register. */
4314 if (rs6000_tls_referenced_p (operands[1]))
4316 enum tls_model model;
4317 rtx tmp = operands[1];
4320 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4322 addend = XEXP (XEXP (tmp, 0), 1);
4323 tmp = XEXP (XEXP (tmp, 0), 0);
4326 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4327 model = SYMBOL_REF_TLS_MODEL (tmp);
4328 gcc_assert (model != 0);
4330 tmp = rs6000_legitimize_tls_address (tmp, model);
4333 tmp = gen_rtx_PLUS (mode, tmp, addend);
4334 tmp = force_operand (tmp, operands[0]);
4339 /* Handle the case where reload calls us with an invalid address. */
4340 if (reload_in_progress && mode == Pmode
4341 && (! general_operand (operands[1], mode)
4342 || ! nonimmediate_operand (operands[0], mode)))
4345 /* 128-bit constant floating-point values on Darwin should really be
4346 loaded as two parts. */
4347 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4348 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4350 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4351 know how to get a DFmode SUBREG of a TFmode. */
4352 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4353 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4354 simplify_gen_subreg (imode, operands[1], mode, 0),
4356 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4357 GET_MODE_SIZE (imode)),
4358 simplify_gen_subreg (imode, operands[1], mode,
4359 GET_MODE_SIZE (imode)),
4364 /* FIXME: In the long term, this switch statement should go away
4365 and be replaced by a sequence of tests based on things like
4371 if (CONSTANT_P (operands[1])
4372 && GET_CODE (operands[1]) != CONST_INT)
4373 operands[1] = force_const_mem (mode, operands[1]);
4378 rs6000_eliminate_indexed_memrefs (operands);
4384 if (CONSTANT_P (operands[1])
4385 && ! easy_fp_constant (operands[1], mode))
4386 operands[1] = force_const_mem (mode, operands[1]);
4397 if (CONSTANT_P (operands[1])
4398 && !easy_vector_constant (operands[1], mode))
4399 operands[1] = force_const_mem (mode, operands[1]);
4404 /* Use default pattern for address of ELF small data */
4407 && DEFAULT_ABI == ABI_V4
4408 && (GET_CODE (operands[1]) == SYMBOL_REF
4409 || GET_CODE (operands[1]) == CONST)
4410 && small_data_operand (operands[1], mode))
4412 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4416 if (DEFAULT_ABI == ABI_V4
4417 && mode == Pmode && mode == SImode
4418 && flag_pic == 1 && got_operand (operands[1], mode))
4420 emit_insn (gen_movsi_got (operands[0], operands[1]));
4424 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4428 && CONSTANT_P (operands[1])
4429 && GET_CODE (operands[1]) != HIGH
4430 && GET_CODE (operands[1]) != CONST_INT)
4432 rtx target = (!can_create_pseudo_p ()
4434 : gen_reg_rtx (mode));
4436 /* If this is a function address on -mcall-aixdesc,
4437 convert it to the address of the descriptor. */
4438 if (DEFAULT_ABI == ABI_AIX
4439 && GET_CODE (operands[1]) == SYMBOL_REF
4440 && XSTR (operands[1], 0)[0] == '.')
4442 const char *name = XSTR (operands[1], 0);
4444 while (*name == '.')
4446 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4447 CONSTANT_POOL_ADDRESS_P (new_ref)
4448 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4449 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4450 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4451 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4452 operands[1] = new_ref;
4455 if (DEFAULT_ABI == ABI_DARWIN)
4458 if (MACHO_DYNAMIC_NO_PIC_P)
4460 /* Take care of any required data indirection. */
4461 operands[1] = rs6000_machopic_legitimize_pic_address (
4462 operands[1], mode, operands[0]);
4463 if (operands[0] != operands[1])
4464 emit_insn (gen_rtx_SET (VOIDmode,
4465 operands[0], operands[1]));
4469 emit_insn (gen_macho_high (target, operands[1]));
4470 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4474 emit_insn (gen_elf_high (target, operands[1]));
4475 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4479 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4480 and we have put it in the TOC, we just need to make a TOC-relative
4483 && GET_CODE (operands[1]) == SYMBOL_REF
4484 && constant_pool_expr_p (operands[1])
4485 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4486 get_pool_mode (operands[1])))
4488 operands[1] = create_TOC_reference (operands[1]);
4490 else if (mode == Pmode
4491 && CONSTANT_P (operands[1])
4492 && ((GET_CODE (operands[1]) != CONST_INT
4493 && ! easy_fp_constant (operands[1], mode))
4494 || (GET_CODE (operands[1]) == CONST_INT
4495 && num_insns_constant (operands[1], mode) > 2)
4496 || (GET_CODE (operands[0]) == REG
4497 && FP_REGNO_P (REGNO (operands[0]))))
4498 && GET_CODE (operands[1]) != HIGH
4499 && ! legitimate_constant_pool_address_p (operands[1])
4500 && ! toc_relative_expr_p (operands[1]))
4502 /* Emit a USE operation so that the constant isn't deleted if
4503 expensive optimizations are turned on because nobody
4504 references it. This should only be done for operands that
4505 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4506 This should not be done for operands that contain LABEL_REFs.
4507 For now, we just handle the obvious case. */
4508 if (GET_CODE (operands[1]) != LABEL_REF)
4509 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4512 /* Darwin uses a special PIC legitimizer. */
4513 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4516 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4518 if (operands[0] != operands[1])
4519 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4524 /* If we are to limit the number of things we put in the TOC and
4525 this is a symbol plus a constant we can add in one insn,
4526 just put the symbol in the TOC and add the constant. Don't do
4527 this if reload is in progress. */
4528 if (GET_CODE (operands[1]) == CONST
4529 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4530 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4531 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4532 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4533 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4534 && ! side_effects_p (operands[0]))
4537 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4538 rtx other = XEXP (XEXP (operands[1], 0), 1);
4540 sym = force_reg (mode, sym);
4542 emit_insn (gen_addsi3 (operands[0], sym, other));
4544 emit_insn (gen_adddi3 (operands[0], sym, other));
4548 operands[1] = force_const_mem (mode, operands[1]);
4551 && constant_pool_expr_p (XEXP (operands[1], 0))
4552 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4553 get_pool_constant (XEXP (operands[1], 0)),
4554 get_pool_mode (XEXP (operands[1], 0))))
4557 = gen_const_mem (mode,
4558 create_TOC_reference (XEXP (operands[1], 0)));
4559 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4565 rs6000_eliminate_indexed_memrefs (operands);
4569 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4571 gen_rtx_SET (VOIDmode,
4572 operands[0], operands[1]),
4573 gen_rtx_CLOBBER (VOIDmode,
4574 gen_rtx_SCRATCH (SImode)))));
4583 /* Above, we may have called force_const_mem which may have returned
4584 an invalid address. If we can, fix this up; otherwise, reload will
4585 have to deal with it. */
4586 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4587 operands[1] = validize_mem (operands[1]);
4590 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4593 /* Nonzero if we can use a floating-point register to pass this arg. */
4594 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4595 (SCALAR_FLOAT_MODE_P (MODE) \
4596 && (MODE) != SDmode \
4597 && (CUM)->fregno <= FP_ARG_MAX_REG \
4598 && TARGET_HARD_FLOAT && TARGET_FPRS)
4600 /* Nonzero if we can use an AltiVec register to pass this arg. */
4601 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4602 (ALTIVEC_VECTOR_MODE (MODE) \
4603 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4604 && TARGET_ALTIVEC_ABI \
4607 /* Return a nonzero value to say to return the function value in
4608 memory, just as large structures are always returned. TYPE will be
4609 the data type of the value, and FNTYPE will be the type of the
4610 function doing the returning, or @code{NULL} for libcalls.
4612 The AIX ABI for the RS/6000 specifies that all structures are
4613 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4614 specifies that structures <= 8 bytes are returned in r3/r4, but a
4615 draft put them in memory, and GCC used to implement the draft
4616 instead of the final standard. Therefore, aix_struct_return
4617 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4618 compatibility can change DRAFT_V4_STRUCT_RET to override the
4619 default, and -m switches get the final word. See
4620 rs6000_override_options for more details.
4622 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4623 long double support is enabled. These values are returned in memory.
4625 int_size_in_bytes returns -1 for variable size objects, which go in
4626 memory always. The cast to unsigned makes -1 > 8. */
4629 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4631 /* In the darwin64 abi, try to use registers for larger structs
4633 if (rs6000_darwin64_abi
4634 && TREE_CODE (type) == RECORD_TYPE
4635 && int_size_in_bytes (type) > 0)
4637 CUMULATIVE_ARGS valcum;
4641 valcum.fregno = FP_ARG_MIN_REG;
4642 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4643 /* Do a trial code generation as if this were going to be passed
4644 as an argument; if any part goes in memory, we return NULL. */
4645 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4648 /* Otherwise fall through to more conventional ABI rules. */
4651 if (AGGREGATE_TYPE_P (type)
4652 && (aix_struct_return
4653 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4656 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4657 modes only exist for GCC vector types if -maltivec. */
4658 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4659 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4662 /* Return synthetic vectors in memory. */
4663 if (TREE_CODE (type) == VECTOR_TYPE
4664 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4666 static bool warned_for_return_big_vectors = false;
4667 if (!warned_for_return_big_vectors)
4669 warning (0, "GCC vector returned by reference: "
4670 "non-standard ABI extension with no compatibility guarantee");
4671 warned_for_return_big_vectors = true;
4676 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4682 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4683 for a call to a function whose data type is FNTYPE.
4684 For a library call, FNTYPE is 0.
4686 For incoming args we set the number of arguments in the prototype large
4687 so we never return a PARALLEL. */
4690 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4691 rtx libname ATTRIBUTE_UNUSED, int incoming,
4692 int libcall, int n_named_args)
4694 static CUMULATIVE_ARGS zero_cumulative;
4696 *cum = zero_cumulative;
4698 cum->fregno = FP_ARG_MIN_REG;
4699 cum->vregno = ALTIVEC_ARG_MIN_REG;
4700 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4701 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4702 ? CALL_LIBCALL : CALL_NORMAL);
4703 cum->sysv_gregno = GP_ARG_MIN_REG;
4704 cum->stdarg = fntype
4705 && (TYPE_ARG_TYPES (fntype) != 0
4706 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4707 != void_type_node));
4709 cum->nargs_prototype = 0;
4710 if (incoming || cum->prototype)
4711 cum->nargs_prototype = n_named_args;
4713 /* Check for a longcall attribute. */
4714 if ((!fntype && rs6000_default_long_calls)
4716 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4717 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4718 cum->call_cookie |= CALL_LONG;
4720 if (TARGET_DEBUG_ARG)
4722 fprintf (stderr, "\ninit_cumulative_args:");
4725 tree ret_type = TREE_TYPE (fntype);
4726 fprintf (stderr, " ret code = %s,",
4727 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4730 if (cum->call_cookie & CALL_LONG)
4731 fprintf (stderr, " longcall,");
4733 fprintf (stderr, " proto = %d, nargs = %d\n",
4734 cum->prototype, cum->nargs_prototype);
4739 && TARGET_ALTIVEC_ABI
4740 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4742 error ("cannot return value in vector register because"
4743 " altivec instructions are disabled, use -maltivec"
4748 /* Return true if TYPE must be passed on the stack and not in registers. */
4751 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4753 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4754 return must_pass_in_stack_var_size (mode, type);
4756 return must_pass_in_stack_var_size_or_pad (mode, type);
4759 /* If defined, a C expression which determines whether, and in which
4760 direction, to pad out an argument with extra space. The value
4761 should be of type `enum direction': either `upward' to pad above
4762 the argument, `downward' to pad below, or `none' to inhibit
4765 For the AIX ABI structs are always stored left shifted in their
4769 function_arg_padding (enum machine_mode mode, tree type)
4771 #ifndef AGGREGATE_PADDING_FIXED
4772 #define AGGREGATE_PADDING_FIXED 0
4774 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4775 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4778 if (!AGGREGATE_PADDING_FIXED)
4780 /* GCC used to pass structures of the same size as integer types as
4781 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4782 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4783 passed padded downward, except that -mstrict-align further
4784 muddied the water in that multi-component structures of 2 and 4
4785 bytes in size were passed padded upward.
4787 The following arranges for best compatibility with previous
4788 versions of gcc, but removes the -mstrict-align dependency. */
4789 if (BYTES_BIG_ENDIAN)
4791 HOST_WIDE_INT size = 0;
4793 if (mode == BLKmode)
4795 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4796 size = int_size_in_bytes (type);
4799 size = GET_MODE_SIZE (mode);
4801 if (size == 1 || size == 2 || size == 4)
4807 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4809 if (type != 0 && AGGREGATE_TYPE_P (type))
4813 /* Fall back to the default. */
4814 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4817 /* If defined, a C expression that gives the alignment boundary, in bits,
4818 of an argument with the specified mode and type. If it is not defined,
4819 PARM_BOUNDARY is used for all arguments.
4821 V.4 wants long longs and doubles to be double word aligned. Just
4822 testing the mode size is a boneheaded way to do this as it means
4823 that other types such as complex int are also double word aligned.
4824 However, we're stuck with this because changing the ABI might break
4825 existing library interfaces.
4827 Doubleword align SPE vectors.
4828 Quadword align Altivec vectors.
4829 Quadword align large synthetic vector types. */
4832 function_arg_boundary (enum machine_mode mode, tree type)
4834 if (DEFAULT_ABI == ABI_V4
4835 && (GET_MODE_SIZE (mode) == 8
4836 || (TARGET_HARD_FLOAT
4838 && (mode == TFmode || mode == TDmode))))
4840 else if (SPE_VECTOR_MODE (mode)
4841 || (type && TREE_CODE (type) == VECTOR_TYPE
4842 && int_size_in_bytes (type) >= 8
4843 && int_size_in_bytes (type) < 16))
4845 else if (ALTIVEC_VECTOR_MODE (mode)
4846 || (type && TREE_CODE (type) == VECTOR_TYPE
4847 && int_size_in_bytes (type) >= 16))
4849 else if (rs6000_darwin64_abi && mode == BLKmode
4850 && type && TYPE_ALIGN (type) > 64)
4853 return PARM_BOUNDARY;
4856 /* For a function parm of MODE and TYPE, return the starting word in
4857 the parameter area. NWORDS of the parameter area are already used. */
4860 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4863 unsigned int parm_offset;
4865 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4866 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4867 return nwords + (-(parm_offset + nwords) & align);
4870 /* Compute the size (in words) of a function argument. */
4872 static unsigned long
4873 rs6000_arg_size (enum machine_mode mode, tree type)
4877 if (mode != BLKmode)
4878 size = GET_MODE_SIZE (mode);
4880 size = int_size_in_bytes (type);
4883 return (size + 3) >> 2;
4885 return (size + 7) >> 3;
4888 /* Use this to flush pending int fields. */
4891 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4892 HOST_WIDE_INT bitpos)
4894 unsigned int startbit, endbit;
4895 int intregs, intoffset;
4896 enum machine_mode mode;
4898 if (cum->intoffset == -1)
4901 intoffset = cum->intoffset;
4902 cum->intoffset = -1;
4904 if (intoffset % BITS_PER_WORD != 0)
4906 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4908 if (mode == BLKmode)
4910 /* We couldn't find an appropriate mode, which happens,
4911 e.g., in packed structs when there are 3 bytes to load.
4912 Back intoffset back to the beginning of the word in this
4914 intoffset = intoffset & -BITS_PER_WORD;
4918 startbit = intoffset & -BITS_PER_WORD;
4919 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4920 intregs = (endbit - startbit) / BITS_PER_WORD;
4921 cum->words += intregs;
4924 /* The darwin64 ABI calls for us to recurse down through structs,
4925 looking for elements passed in registers. Unfortunately, we have
4926 to track int register count here also because of misalignments
4927 in powerpc alignment mode. */
4930 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4932 HOST_WIDE_INT startbitpos)
4936 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4937 if (TREE_CODE (f) == FIELD_DECL)
4939 HOST_WIDE_INT bitpos = startbitpos;
4940 tree ftype = TREE_TYPE (f);
4941 enum machine_mode mode;
4942 if (ftype == error_mark_node)
4944 mode = TYPE_MODE (ftype);
4946 if (DECL_SIZE (f) != 0
4947 && host_integerp (bit_position (f), 1))
4948 bitpos += int_bit_position (f);
4950 /* ??? FIXME: else assume zero offset. */
4952 if (TREE_CODE (ftype) == RECORD_TYPE)
4953 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4954 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4956 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4957 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4958 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4960 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4962 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4966 else if (cum->intoffset == -1)
4967 cum->intoffset = bitpos;
4971 /* Update the data in CUM to advance over an argument
4972 of mode MODE and data type TYPE.
4973 (TYPE is null for libcalls where that information may not be available.)
4975 Note that for args passed by reference, function_arg will be called
4976 with MODE and TYPE set to that of the pointer to the arg, not the arg
4980 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4981 tree type, int named, int depth)
4985 /* Only tick off an argument if we're not recursing. */
4987 cum->nargs_prototype--;
4989 if (TARGET_ALTIVEC_ABI
4990 && (ALTIVEC_VECTOR_MODE (mode)
4991 || (type && TREE_CODE (type) == VECTOR_TYPE
4992 && int_size_in_bytes (type) == 16)))
4996 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4999 if (!TARGET_ALTIVEC)
5000 error ("cannot pass argument in vector register because"
5001 " altivec instructions are disabled, use -maltivec"
5004 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5005 even if it is going to be passed in a vector register.
5006 Darwin does the same for variable-argument functions. */
5007 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5008 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5018 /* Vector parameters must be 16-byte aligned. This places
5019 them at 2 mod 4 in terms of words in 32-bit mode, since
5020 the parameter save area starts at offset 24 from the
5021 stack. In 64-bit mode, they just have to start on an
5022 even word, since the parameter save area is 16-byte
5023 aligned. Space for GPRs is reserved even if the argument
5024 will be passed in memory. */
5026 align = (2 - cum->words) & 3;
5028 align = cum->words & 1;
5029 cum->words += align + rs6000_arg_size (mode, type);
5031 if (TARGET_DEBUG_ARG)
5033 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5035 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5036 cum->nargs_prototype, cum->prototype,
5037 GET_MODE_NAME (mode));
5041 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5043 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5046 else if (rs6000_darwin64_abi
5048 && TREE_CODE (type) == RECORD_TYPE
5049 && (size = int_size_in_bytes (type)) > 0)
5051 /* Variable sized types have size == -1 and are
5052 treated as if consisting entirely of ints.
5053 Pad to 16 byte boundary if needed. */
5054 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5055 && (cum->words % 2) != 0)
5057 /* For varargs, we can just go up by the size of the struct. */
5059 cum->words += (size + 7) / 8;
5062 /* It is tempting to say int register count just goes up by
5063 sizeof(type)/8, but this is wrong in a case such as
5064 { int; double; int; } [powerpc alignment]. We have to
5065 grovel through the fields for these too. */
5067 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5068 rs6000_darwin64_record_arg_advance_flush (cum,
5069 size * BITS_PER_UNIT);
5072 else if (DEFAULT_ABI == ABI_V4)
5074 if (TARGET_HARD_FLOAT && TARGET_FPRS
5075 && (mode == SFmode || mode == DFmode
5076 || mode == DDmode || mode == TDmode
5077 || (mode == TFmode && !TARGET_IEEEQUAD)))
5079 /* _Decimal128 must use an even/odd register pair. This assumes
5080 that the register number is odd when fregno is odd. */
5081 if (mode == TDmode && (cum->fregno % 2) == 1)
5084 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5085 <= FP_ARG_V4_MAX_REG)
5086 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5089 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5090 if (mode == DFmode || mode == TFmode || mode == DDmode || mode == TDmode)
5091 cum->words += cum->words & 1;
5092 cum->words += rs6000_arg_size (mode, type);
5097 int n_words = rs6000_arg_size (mode, type);
5098 int gregno = cum->sysv_gregno;
5100 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5101 (r7,r8) or (r9,r10). As does any other 2 word item such
5102 as complex int due to a historical mistake. */
5104 gregno += (1 - gregno) & 1;
5106 /* Multi-reg args are not split between registers and stack. */
5107 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5109 /* Long long and SPE vectors are aligned on the stack.
5110 So are other 2 word items such as complex int due to
5111 a historical mistake. */
5113 cum->words += cum->words & 1;
5114 cum->words += n_words;
5117 /* Note: continuing to accumulate gregno past when we've started
5118 spilling to the stack indicates the fact that we've started
5119 spilling to the stack to expand_builtin_saveregs. */
5120 cum->sysv_gregno = gregno + n_words;
5123 if (TARGET_DEBUG_ARG)
5125 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5126 cum->words, cum->fregno);
5127 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5128 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5129 fprintf (stderr, "mode = %4s, named = %d\n",
5130 GET_MODE_NAME (mode), named);
5135 int n_words = rs6000_arg_size (mode, type);
5136 int start_words = cum->words;
5137 int align_words = rs6000_parm_start (mode, type, start_words);
5139 cum->words = align_words + n_words;
5141 if (SCALAR_FLOAT_MODE_P (mode)
5143 && TARGET_HARD_FLOAT && TARGET_FPRS)
5145 /* _Decimal128 must be passed in an even/odd float register pair.
5146 This assumes that the register number is odd when fregno is
5148 if (mode == TDmode && (cum->fregno % 2) == 1)
5150 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5153 if (TARGET_DEBUG_ARG)
5155 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5156 cum->words, cum->fregno);
5157 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5158 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5159 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5160 named, align_words - start_words, depth);
5166 spe_build_register_parallel (enum machine_mode mode, int gregno)
5173 r1 = gen_rtx_REG (DImode, gregno);
5174 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5175 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5179 r1 = gen_rtx_REG (DImode, gregno);
5180 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5181 r3 = gen_rtx_REG (DImode, gregno + 2);
5182 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5183 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5186 r1 = gen_rtx_REG (DImode, gregno);
5187 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5188 r3 = gen_rtx_REG (DImode, gregno + 2);
5189 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5190 r5 = gen_rtx_REG (DImode, gregno + 4);
5191 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5192 r7 = gen_rtx_REG (DImode, gregno + 6);
5193 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5194 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5201 /* Determine where to put a SIMD argument on the SPE. */
5203 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5206 int gregno = cum->sysv_gregno;
5208 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5209 are passed and returned in a pair of GPRs for ABI compatibility. */
5210 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode
5211 || mode == TFmode || mode == TCmode))
5213 int n_words = rs6000_arg_size (mode, type);
5215 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5217 gregno += (1 - gregno) & 1;
5219 /* Multi-reg args are not split between registers and stack. */
5220 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5223 return spe_build_register_parallel (mode, gregno);
5227 int n_words = rs6000_arg_size (mode, type);
5229 /* SPE vectors are put in odd registers. */
5230 if (n_words == 2 && (gregno & 1) == 0)
5233 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5236 enum machine_mode m = SImode;
5238 r1 = gen_rtx_REG (m, gregno);
5239 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5240 r2 = gen_rtx_REG (m, gregno + 1);
5241 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5242 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5249 if (gregno <= GP_ARG_MAX_REG)
5250 return gen_rtx_REG (mode, gregno);
5256 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5257 structure between cum->intoffset and bitpos to integer registers. */
5260 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5261 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5263 enum machine_mode mode;
5265 unsigned int startbit, endbit;
5266 int this_regno, intregs, intoffset;
5269 if (cum->intoffset == -1)
5272 intoffset = cum->intoffset;
5273 cum->intoffset = -1;
5275 /* If this is the trailing part of a word, try to only load that
5276 much into the register. Otherwise load the whole register. Note
5277 that in the latter case we may pick up unwanted bits. It's not a
5278 problem at the moment but may wish to revisit. */
5280 if (intoffset % BITS_PER_WORD != 0)
5282 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5284 if (mode == BLKmode)
5286 /* We couldn't find an appropriate mode, which happens,
5287 e.g., in packed structs when there are 3 bytes to load.
5288 Back intoffset back to the beginning of the word in this
5290 intoffset = intoffset & -BITS_PER_WORD;
5297 startbit = intoffset & -BITS_PER_WORD;
5298 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5299 intregs = (endbit - startbit) / BITS_PER_WORD;
5300 this_regno = cum->words + intoffset / BITS_PER_WORD;
5302 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5305 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5309 intoffset /= BITS_PER_UNIT;
5312 regno = GP_ARG_MIN_REG + this_regno;
5313 reg = gen_rtx_REG (mode, regno);
5315 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5318 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5322 while (intregs > 0);
5325 /* Recursive workhorse for the following. */
5328 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
5329 HOST_WIDE_INT startbitpos, rtx rvec[],
5334 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5335 if (TREE_CODE (f) == FIELD_DECL)
5337 HOST_WIDE_INT bitpos = startbitpos;
5338 tree ftype = TREE_TYPE (f);
5339 enum machine_mode mode;
5340 if (ftype == error_mark_node)
5342 mode = TYPE_MODE (ftype);
5344 if (DECL_SIZE (f) != 0
5345 && host_integerp (bit_position (f), 1))
5346 bitpos += int_bit_position (f);
5348 /* ??? FIXME: else assume zero offset. */
5350 if (TREE_CODE (ftype) == RECORD_TYPE)
5351 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5352 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5357 case SCmode: mode = SFmode; break;
5358 case DCmode: mode = DFmode; break;
5359 case TCmode: mode = TFmode; break;
5363 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5365 = gen_rtx_EXPR_LIST (VOIDmode,
5366 gen_rtx_REG (mode, cum->fregno++),
5367 GEN_INT (bitpos / BITS_PER_UNIT));
5368 if (mode == TFmode || mode == TDmode)
5371 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5373 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5375 = gen_rtx_EXPR_LIST (VOIDmode,
5376 gen_rtx_REG (mode, cum->vregno++),
5377 GEN_INT (bitpos / BITS_PER_UNIT));
5379 else if (cum->intoffset == -1)
5380 cum->intoffset = bitpos;
5384 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5385 the register(s) to be used for each field and subfield of a struct
5386 being passed by value, along with the offset of where the
5387 register's value may be found in the block. FP fields go in FP
5388 register, vector fields go in vector registers, and everything
5389 else goes in int registers, packed as in memory.
5391 This code is also used for function return values. RETVAL indicates
5392 whether this is the case.
5394 Much of this is taken from the SPARC V9 port, which has a similar
5395 calling convention. */
5398 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
5399 int named, bool retval)
5401 rtx rvec[FIRST_PSEUDO_REGISTER];
5402 int k = 1, kbase = 1;
5403 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5404 /* This is a copy; modifications are not visible to our caller. */
5405 CUMULATIVE_ARGS copy_cum = *orig_cum;
5406 CUMULATIVE_ARGS *cum = ©_cum;
5408 /* Pad to 16 byte boundary if needed. */
5409 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5410 && (cum->words % 2) != 0)
5417 /* Put entries into rvec[] for individual FP and vector fields, and
5418 for the chunks of memory that go in int regs. Note we start at
5419 element 1; 0 is reserved for an indication of using memory, and
5420 may or may not be filled in below. */
5421 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5422 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5424 /* If any part of the struct went on the stack put all of it there.
5425 This hack is because the generic code for
5426 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5427 parts of the struct are not at the beginning. */
5431 return NULL_RTX; /* doesn't go in registers at all */
5433 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5435 if (k > 1 || cum->use_stack)
5436 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5441 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5444 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5448 rtx rvec[GP_ARG_NUM_REG + 1];
5450 if (align_words >= GP_ARG_NUM_REG)
5453 n_units = rs6000_arg_size (mode, type);
5455 /* Optimize the simple case where the arg fits in one gpr, except in
5456 the case of BLKmode due to assign_parms assuming that registers are
5457 BITS_PER_WORD wide. */
5459 || (n_units == 1 && mode != BLKmode))
5460 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5463 if (align_words + n_units > GP_ARG_NUM_REG)
5464 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5465 using a magic NULL_RTX component.
5466 This is not strictly correct. Only some of the arg belongs in
5467 memory, not all of it. However, the normal scheme using
5468 function_arg_partial_nregs can result in unusual subregs, eg.
5469 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5470 store the whole arg to memory is often more efficient than code
5471 to store pieces, and we know that space is available in the right
5472 place for the whole arg. */
5473 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5478 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5479 rtx off = GEN_INT (i++ * 4);
5480 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5482 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5484 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5487 /* Determine where to put an argument to a function.
5488 Value is zero to push the argument on the stack,
5489 or a hard register in which to store the argument.
5491 MODE is the argument's machine mode.
5492 TYPE is the data type of the argument (as a tree).
5493 This is null for libcalls where that information may
5495 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5496 the preceding args and about the function being called. It is
5497 not modified in this routine.
5498 NAMED is nonzero if this argument is a named parameter
5499 (otherwise it is an extra parameter matching an ellipsis).
5501 On RS/6000 the first eight words of non-FP are normally in registers
5502 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5503 Under V.4, the first 8 FP args are in registers.
5505 If this is floating-point and no prototype is specified, we use
5506 both an FP and integer register (or possibly FP reg and stack). Library
5507 functions (when CALL_LIBCALL is set) always have the proper types for args,
5508 so we can pass the FP value just in one register. emit_library_function
5509 doesn't support PARALLEL anyway.
5511 Note that for args passed by reference, function_arg will be called
5512 with MODE and TYPE set to that of the pointer to the arg, not the arg
5516 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5517 tree type, int named)
5519 enum rs6000_abi abi = DEFAULT_ABI;
5521 /* Return a marker to indicate whether CR1 needs to set or clear the
5522 bit that V.4 uses to say fp args were passed in registers.
5523 Assume that we don't need the marker for software floating point,
5524 or compiler generated library calls. */
5525 if (mode == VOIDmode)
5528 && (cum->call_cookie & CALL_LIBCALL) == 0
5530 || (cum->nargs_prototype < 0
5531 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5533 /* For the SPE, we need to crxor CR6 always. */
5535 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5536 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5537 return GEN_INT (cum->call_cookie
5538 | ((cum->fregno == FP_ARG_MIN_REG)
5539 ? CALL_V4_SET_FP_ARGS
5540 : CALL_V4_CLEAR_FP_ARGS));
5543 return GEN_INT (cum->call_cookie);
5546 if (rs6000_darwin64_abi && mode == BLKmode
5547 && TREE_CODE (type) == RECORD_TYPE)
5549 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5550 if (rslt != NULL_RTX)
5552 /* Else fall through to usual handling. */
5555 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5556 if (TARGET_64BIT && ! cum->prototype)
5558 /* Vector parameters get passed in vector register
5559 and also in GPRs or memory, in absence of prototype. */
5562 align_words = (cum->words + 1) & ~1;
5564 if (align_words >= GP_ARG_NUM_REG)
5570 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5572 return gen_rtx_PARALLEL (mode,
5574 gen_rtx_EXPR_LIST (VOIDmode,
5576 gen_rtx_EXPR_LIST (VOIDmode,
5577 gen_rtx_REG (mode, cum->vregno),
5581 return gen_rtx_REG (mode, cum->vregno);
5582 else if (TARGET_ALTIVEC_ABI
5583 && (ALTIVEC_VECTOR_MODE (mode)
5584 || (type && TREE_CODE (type) == VECTOR_TYPE
5585 && int_size_in_bytes (type) == 16)))
5587 if (named || abi == ABI_V4)
5591 /* Vector parameters to varargs functions under AIX or Darwin
5592 get passed in memory and possibly also in GPRs. */
5593 int align, align_words, n_words;
5594 enum machine_mode part_mode;
5596 /* Vector parameters must be 16-byte aligned. This places them at
5597 2 mod 4 in terms of words in 32-bit mode, since the parameter
5598 save area starts at offset 24 from the stack. In 64-bit mode,
5599 they just have to start on an even word, since the parameter
5600 save area is 16-byte aligned. */
5602 align = (2 - cum->words) & 3;
5604 align = cum->words & 1;
5605 align_words = cum->words + align;
5607 /* Out of registers? Memory, then. */
5608 if (align_words >= GP_ARG_NUM_REG)
5611 if (TARGET_32BIT && TARGET_POWERPC64)
5612 return rs6000_mixed_function_arg (mode, type, align_words);
5614 /* The vector value goes in GPRs. Only the part of the
5615 value in GPRs is reported here. */
5617 n_words = rs6000_arg_size (mode, type);
5618 if (align_words + n_words > GP_ARG_NUM_REG)
5619 /* Fortunately, there are only two possibilities, the value
5620 is either wholly in GPRs or half in GPRs and half not. */
5623 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5626 else if (TARGET_SPE_ABI && TARGET_SPE
5627 && (SPE_VECTOR_MODE (mode)
5628 || (TARGET_E500_DOUBLE && (mode == DFmode
5633 || mode == TCmode))))
5634 return rs6000_spe_function_arg (cum, mode, type);
5636 else if (abi == ABI_V4)
5638 if (TARGET_HARD_FLOAT && TARGET_FPRS
5639 && (mode == SFmode || mode == DFmode
5640 || (mode == TFmode && !TARGET_IEEEQUAD)
5641 || mode == DDmode || mode == TDmode))
5643 /* _Decimal128 must use an even/odd register pair. This assumes
5644 that the register number is odd when fregno is odd. */
5645 if (mode == TDmode && (cum->fregno % 2) == 1)
5648 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5649 <= FP_ARG_V4_MAX_REG)
5650 return gen_rtx_REG (mode, cum->fregno);
5656 int n_words = rs6000_arg_size (mode, type);
5657 int gregno = cum->sysv_gregno;
5659 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5660 (r7,r8) or (r9,r10). As does any other 2 word item such
5661 as complex int due to a historical mistake. */
5663 gregno += (1 - gregno) & 1;
5665 /* Multi-reg args are not split between registers and stack. */
5666 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5669 if (TARGET_32BIT && TARGET_POWERPC64)
5670 return rs6000_mixed_function_arg (mode, type,
5671 gregno - GP_ARG_MIN_REG);
5672 return gen_rtx_REG (mode, gregno);
5677 int align_words = rs6000_parm_start (mode, type, cum->words);
5679 /* _Decimal128 must be passed in an even/odd float register pair.
5680 This assumes that the register number is odd when fregno is odd. */
5681 if (mode == TDmode && (cum->fregno % 2) == 1)
5684 if (USE_FP_FOR_ARG_P (cum, mode, type))
5686 rtx rvec[GP_ARG_NUM_REG + 1];
5690 enum machine_mode fmode = mode;
5691 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5693 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5695 /* Currently, we only ever need one reg here because complex
5696 doubles are split. */
5697 gcc_assert (cum->fregno == FP_ARG_MAX_REG
5698 && (fmode == TFmode || fmode == TDmode));
5700 /* Long double or _Decimal128 split over regs and memory. */
5701 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
5704 /* Do we also need to pass this arg in the parameter save
5707 && (cum->nargs_prototype <= 0
5708 || (DEFAULT_ABI == ABI_AIX
5710 && align_words >= GP_ARG_NUM_REG)));
5712 if (!needs_psave && mode == fmode)
5713 return gen_rtx_REG (fmode, cum->fregno);
5718 /* Describe the part that goes in gprs or the stack.
5719 This piece must come first, before the fprs. */
5720 if (align_words < GP_ARG_NUM_REG)
5722 unsigned long n_words = rs6000_arg_size (mode, type);
5724 if (align_words + n_words > GP_ARG_NUM_REG
5725 || (TARGET_32BIT && TARGET_POWERPC64))
5727 /* If this is partially on the stack, then we only
5728 include the portion actually in registers here. */
5729 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5732 if (align_words + n_words > GP_ARG_NUM_REG)
5733 /* Not all of the arg fits in gprs. Say that it
5734 goes in memory too, using a magic NULL_RTX
5735 component. Also see comment in
5736 rs6000_mixed_function_arg for why the normal
5737 function_arg_partial_nregs scheme doesn't work
5739 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5743 r = gen_rtx_REG (rmode,
5744 GP_ARG_MIN_REG + align_words);
5745 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5746 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5748 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5752 /* The whole arg fits in gprs. */
5753 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5754 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5758 /* It's entirely in memory. */
5759 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5762 /* Describe where this piece goes in the fprs. */
5763 r = gen_rtx_REG (fmode, cum->fregno);
5764 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5766 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5768 else if (align_words < GP_ARG_NUM_REG)
5770 if (TARGET_32BIT && TARGET_POWERPC64)
5771 return rs6000_mixed_function_arg (mode, type, align_words);
5773 if (mode == BLKmode)
5776 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5783 /* For an arg passed partly in registers and partly in memory, this is
5784 the number of bytes passed in registers. For args passed entirely in
5785 registers or entirely in memory, zero. When an arg is described by a
5786 PARALLEL, perhaps using more than one register type, this function
5787 returns the number of bytes used by the first element of the PARALLEL. */
5790 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5791 tree type, bool named)
5796 if (DEFAULT_ABI == ABI_V4)
5799 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5800 && cum->nargs_prototype >= 0)
5803 /* In this complicated case we just disable the partial_nregs code. */
5804 if (rs6000_darwin64_abi && mode == BLKmode
5805 && TREE_CODE (type) == RECORD_TYPE
5806 && int_size_in_bytes (type) > 0)
5809 align_words = rs6000_parm_start (mode, type, cum->words);
5811 if (USE_FP_FOR_ARG_P (cum, mode, type))
5813 /* If we are passing this arg in the fixed parameter save area
5814 (gprs or memory) as well as fprs, then this function should
5815 return the number of partial bytes passed in the parameter
5816 save area rather than partial bytes passed in fprs. */
5818 && (cum->nargs_prototype <= 0
5819 || (DEFAULT_ABI == ABI_AIX
5821 && align_words >= GP_ARG_NUM_REG)))
5823 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5824 > FP_ARG_MAX_REG + 1)
5825 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5826 else if (cum->nargs_prototype >= 0)
5830 if (align_words < GP_ARG_NUM_REG
5831 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5832 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5834 if (ret != 0 && TARGET_DEBUG_ARG)
5835 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5840 /* A C expression that indicates when an argument must be passed by
5841 reference. If nonzero for an argument, a copy of that argument is
5842 made in memory and a pointer to the argument is passed instead of
5843 the argument itself. The pointer is passed in whatever way is
5844 appropriate for passing a pointer to that type.
5846 Under V.4, aggregates and long double are passed by reference.
5848 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5849 reference unless the AltiVec vector extension ABI is in force.
5851 As an extension to all ABIs, variable sized types are passed by
5855 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5856 enum machine_mode mode, tree type,
5857 bool named ATTRIBUTE_UNUSED)
5859 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5861 if (TARGET_DEBUG_ARG)
5862 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5869 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5871 if (TARGET_DEBUG_ARG)
5872 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5876 if (int_size_in_bytes (type) < 0)
5878 if (TARGET_DEBUG_ARG)
5879 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5883 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5884 modes only exist for GCC vector types if -maltivec. */
5885 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5887 if (TARGET_DEBUG_ARG)
5888 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5892 /* Pass synthetic vectors in memory. */
5893 if (TREE_CODE (type) == VECTOR_TYPE
5894 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5896 static bool warned_for_pass_big_vectors = false;
5897 if (TARGET_DEBUG_ARG)
5898 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5899 if (!warned_for_pass_big_vectors)
5901 warning (0, "GCC vector passed by reference: "
5902 "non-standard ABI extension with no compatibility guarantee");
5903 warned_for_pass_big_vectors = true;
5912 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5915 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5920 for (i = 0; i < nregs; i++)
5922 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5923 if (reload_completed)
5925 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5928 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5929 i * GET_MODE_SIZE (reg_mode));
5932 tem = replace_equiv_address (tem, XEXP (tem, 0));
5936 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5940 /* Perform any needed actions needed for a function that is receiving a
5941 variable number of arguments.
5945 MODE and TYPE are the mode and type of the current parameter.
5947 PRETEND_SIZE is a variable that should be set to the amount of stack
5948 that must be pushed by the prolog to pretend that our caller pushed
5951 Normally, this macro will push all remaining incoming registers on the
5952 stack and set PRETEND_SIZE to the length of the registers pushed. */
5955 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5956 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5959 CUMULATIVE_ARGS next_cum;
5960 int reg_size = TARGET_32BIT ? 4 : 8;
5961 rtx save_area = NULL_RTX, mem;
5962 int first_reg_offset, set;
5964 /* Skip the last named argument. */
5966 function_arg_advance (&next_cum, mode, type, 1, 0);
5968 if (DEFAULT_ABI == ABI_V4)
5970 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5974 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5975 HOST_WIDE_INT offset = 0;
5977 /* Try to optimize the size of the varargs save area.
5978 The ABI requires that ap.reg_save_area is doubleword
5979 aligned, but we don't need to allocate space for all
5980 the bytes, only those to which we actually will save
5982 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5983 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5984 if (TARGET_HARD_FLOAT && TARGET_FPRS
5985 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5986 && cfun->va_list_fpr_size)
5989 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5990 * UNITS_PER_FP_WORD;
5991 if (cfun->va_list_fpr_size
5992 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5993 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5995 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5996 * UNITS_PER_FP_WORD;
6000 offset = -((first_reg_offset * reg_size) & ~7);
6001 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
6003 gpr_reg_num = cfun->va_list_gpr_size;
6004 if (reg_size == 4 && (first_reg_offset & 1))
6007 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
6010 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
6012 - (int) (GP_ARG_NUM_REG * reg_size);
6014 if (gpr_size + fpr_size)
6017 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
6018 gcc_assert (GET_CODE (reg_save_area) == MEM);
6019 reg_save_area = XEXP (reg_save_area, 0);
6020 if (GET_CODE (reg_save_area) == PLUS)
6022 gcc_assert (XEXP (reg_save_area, 0)
6023 == virtual_stack_vars_rtx);
6024 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6025 offset += INTVAL (XEXP (reg_save_area, 1));
6028 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6031 cfun->machine->varargs_save_offset = offset;
6032 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6037 first_reg_offset = next_cum.words;
6038 save_area = virtual_incoming_args_rtx;
6040 if (targetm.calls.must_pass_in_stack (mode, type))
6041 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6044 set = get_varargs_alias_set ();
6045 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6046 && cfun->va_list_gpr_size)
6048 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6050 if (va_list_gpr_counter_field)
6052 /* V4 va_list_gpr_size counts number of registers needed. */
6053 if (nregs > cfun->va_list_gpr_size)
6054 nregs = cfun->va_list_gpr_size;
6058 /* char * va_list instead counts number of bytes needed. */
6059 if (nregs > cfun->va_list_gpr_size / reg_size)
6060 nregs = cfun->va_list_gpr_size / reg_size;
6063 mem = gen_rtx_MEM (BLKmode,
6064 plus_constant (save_area,
6065 first_reg_offset * reg_size));
6066 MEM_NOTRAP_P (mem) = 1;
6067 set_mem_alias_set (mem, set);
6068 set_mem_align (mem, BITS_PER_WORD);
6070 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6074 /* Save FP registers if needed. */
6075 if (DEFAULT_ABI == ABI_V4
6076 && TARGET_HARD_FLOAT && TARGET_FPRS
6078 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6079 && cfun->va_list_fpr_size)
6081 int fregno = next_cum.fregno, nregs;
6082 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6083 rtx lab = gen_label_rtx ();
6084 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6085 * UNITS_PER_FP_WORD);
6088 (gen_rtx_SET (VOIDmode,
6090 gen_rtx_IF_THEN_ELSE (VOIDmode,
6091 gen_rtx_NE (VOIDmode, cr1,
6093 gen_rtx_LABEL_REF (VOIDmode, lab),
6097 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6098 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6100 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6101 MEM_NOTRAP_P (mem) = 1;
6102 set_mem_alias_set (mem, set);
6103 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6104 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6111 /* Create the va_list data type. */
6114 rs6000_build_builtin_va_list (void)
6116 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6118 /* For AIX, prefer 'char *' because that's what the system
6119 header files like. */
6120 if (DEFAULT_ABI != ABI_V4)
6121 return build_pointer_type (char_type_node);
6123 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6124 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6126 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6127 unsigned_char_type_node);
6128 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6129 unsigned_char_type_node);
6130 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6132 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6133 short_unsigned_type_node);
6134 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6136 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6139 va_list_gpr_counter_field = f_gpr;
6140 va_list_fpr_counter_field = f_fpr;
6142 DECL_FIELD_CONTEXT (f_gpr) = record;
6143 DECL_FIELD_CONTEXT (f_fpr) = record;
6144 DECL_FIELD_CONTEXT (f_res) = record;
6145 DECL_FIELD_CONTEXT (f_ovf) = record;
6146 DECL_FIELD_CONTEXT (f_sav) = record;
6148 TREE_CHAIN (record) = type_decl;
6149 TYPE_NAME (record) = type_decl;
6150 TYPE_FIELDS (record) = f_gpr;
6151 TREE_CHAIN (f_gpr) = f_fpr;
6152 TREE_CHAIN (f_fpr) = f_res;
6153 TREE_CHAIN (f_res) = f_ovf;
6154 TREE_CHAIN (f_ovf) = f_sav;
6156 layout_type (record);
6158 /* The correct type is an array type of one element. */
6159 return build_array_type (record, build_index_type (size_zero_node));
6162 /* Implement va_start. */
6165 rs6000_va_start (tree valist, rtx nextarg)
6167 HOST_WIDE_INT words, n_gpr, n_fpr;
6168 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6169 tree gpr, fpr, ovf, sav, t;
6171 /* Only SVR4 needs something special. */
6172 if (DEFAULT_ABI != ABI_V4)
6174 std_expand_builtin_va_start (valist, nextarg);
6178 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6179 f_fpr = TREE_CHAIN (f_gpr);
6180 f_res = TREE_CHAIN (f_fpr);
6181 f_ovf = TREE_CHAIN (f_res);
6182 f_sav = TREE_CHAIN (f_ovf);
6184 valist = build_va_arg_indirect_ref (valist);
6185 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6186 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6187 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6188 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6190 /* Count number of gp and fp argument registers used. */
6191 words = current_function_args_info.words;
6192 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6194 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6197 if (TARGET_DEBUG_ARG)
6198 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6199 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6200 words, n_gpr, n_fpr);
6202 if (cfun->va_list_gpr_size)
6204 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6205 build_int_cst (NULL_TREE, n_gpr));
6206 TREE_SIDE_EFFECTS (t) = 1;
6207 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6210 if (cfun->va_list_fpr_size)
6212 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6213 build_int_cst (NULL_TREE, n_fpr));
6214 TREE_SIDE_EFFECTS (t) = 1;
6215 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6218 /* Find the overflow area. */
6219 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6221 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t,
6222 size_int (words * UNITS_PER_WORD));
6223 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6224 TREE_SIDE_EFFECTS (t) = 1;
6225 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6227 /* If there were no va_arg invocations, don't set up the register
6229 if (!cfun->va_list_gpr_size
6230 && !cfun->va_list_fpr_size
6231 && n_gpr < GP_ARG_NUM_REG
6232 && n_fpr < FP_ARG_V4_MAX_REG)
6235 /* Find the register save area. */
6236 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6237 if (cfun->machine->varargs_save_offset)
6238 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
6239 size_int (cfun->machine->varargs_save_offset));
6240 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6241 TREE_SIDE_EFFECTS (t) = 1;
6242 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6245 /* Implement va_arg. */
6248 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6250 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6251 tree gpr, fpr, ovf, sav, reg, t, u;
6252 int size, rsize, n_reg, sav_ofs, sav_scale;
6253 tree lab_false, lab_over, addr;
6255 tree ptrtype = build_pointer_type (type);
6258 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6260 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6261 return build_va_arg_indirect_ref (t);
6264 if (DEFAULT_ABI != ABI_V4)
6266 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6268 tree elem_type = TREE_TYPE (type);
6269 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6270 int elem_size = GET_MODE_SIZE (elem_mode);
6272 if (elem_size < UNITS_PER_WORD)
6274 tree real_part, imag_part;
6275 tree post = NULL_TREE;
6277 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6279 /* Copy the value into a temporary, lest the formal temporary
6280 be reused out from under us. */
6281 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6282 append_to_statement_list (post, pre_p);
6284 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6287 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6291 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6294 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6295 f_fpr = TREE_CHAIN (f_gpr);
6296 f_res = TREE_CHAIN (f_fpr);
6297 f_ovf = TREE_CHAIN (f_res);
6298 f_sav = TREE_CHAIN (f_ovf);
6300 valist = build_va_arg_indirect_ref (valist);
6301 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6302 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6303 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6304 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6306 size = int_size_in_bytes (type);
6307 rsize = (size + 3) / 4;
6310 if (TARGET_HARD_FLOAT && TARGET_FPRS
6311 && (TYPE_MODE (type) == SFmode
6312 || TYPE_MODE (type) == DFmode
6313 || TYPE_MODE (type) == TFmode
6314 || TYPE_MODE (type) == DDmode
6315 || TYPE_MODE (type) == TDmode))
6317 /* FP args go in FP registers, if present. */
6319 n_reg = (size + 7) / 8;
6322 if (TYPE_MODE (type) != SFmode)
6327 /* Otherwise into GP registers. */
6336 /* Pull the value out of the saved registers.... */
6339 addr = create_tmp_var (ptr_type_node, "addr");
6340 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6342 /* AltiVec vectors never go in registers when -mabi=altivec. */
6343 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6347 lab_false = create_artificial_label ();
6348 lab_over = create_artificial_label ();
6350 /* Long long and SPE vectors are aligned in the registers.
6351 As are any other 2 gpr item such as complex int due to a
6352 historical mistake. */
6354 if (n_reg == 2 && reg == gpr)
6357 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6358 size_int (n_reg - 1));
6359 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6361 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6362 reg number is 0 for f1, so we want to make it odd. */
6363 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6366 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), reg, size_int (1));
6367 u = build2 (MODIFY_EXPR, void_type_node, reg, t);
6370 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6371 t = build2 (GE_EXPR, boolean_type_node, u, t);
6372 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6373 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6374 gimplify_and_add (t, pre_p);
6378 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6380 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
6381 u = fold_convert (sizetype, u);
6382 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
6383 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u);
6385 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6386 gimplify_and_add (t, pre_p);
6388 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6389 gimplify_and_add (t, pre_p);
6391 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6392 append_to_statement_list (t, pre_p);
6394 if ((n_reg == 2 && !regalign) || n_reg > 2)
6396 /* Ensure that we don't find any more args in regs.
6397 Alignment has taken care of for special cases. */
6398 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (reg), reg, size_int (8));
6399 gimplify_and_add (t, pre_p);
6403 /* ... otherwise out of the overflow area. */
6405 /* Care for on-stack alignment if needed. */
6409 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6410 t = fold_convert (sizetype, t);
6411 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6413 t = fold_convert (TREE_TYPE (ovf), t);
6415 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6417 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6418 gimplify_and_add (u, pre_p);
6420 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6421 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6422 gimplify_and_add (t, pre_p);
6426 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6427 append_to_statement_list (t, pre_p);
6430 if (STRICT_ALIGNMENT
6431 && (TYPE_ALIGN (type)
6432 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6434 /* The value (of type complex double, for example) may not be
6435 aligned in memory in the saved registers, so copy via a
6436 temporary. (This is the same code as used for SPARC.) */
6437 tree tmp = create_tmp_var (type, "va_arg_tmp");
6438 tree dest_addr = build_fold_addr_expr (tmp);
6440 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6441 3, dest_addr, addr, size_int (rsize * 4));
6443 gimplify_and_add (copy, pre_p);
6447 addr = fold_convert (ptrtype, addr);
6448 return build_va_arg_indirect_ref (addr);
6454 def_builtin (int mask, const char *name, tree type, int code)
6456 if (mask & target_flags)
6458 if (rs6000_builtin_decls[code])
6461 rs6000_builtin_decls[code] =
6462 add_builtin_function (name, type, code, BUILT_IN_MD,
6467 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6469 static const struct builtin_description bdesc_3arg[] =
6471 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6472 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6473 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6474 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6475 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6476 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6477 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6478 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6479 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6480 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6481 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6482 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6483 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6484 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6485 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6486 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6487 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6488 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6489 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6490 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6491 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6492 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6493 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6495 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6496 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6497 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6498 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6499 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6500 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6501 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6502 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6503 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6504 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6505 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6506 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6507 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6508 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6509 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6512 /* DST operations: void foo (void *, const int, const char). */
6514 static const struct builtin_description bdesc_dst[] =
6516 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6517 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6518 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6519 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6521 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6522 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6523 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6524 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6527 /* Simple binary operations: VECc = foo (VECa, VECb). */
6529 static struct builtin_description bdesc_2arg[] =
6531 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6532 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6533 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6534 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6535 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6536 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6537 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6538 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6539 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6540 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6541 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6542 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6543 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6544 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6545 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6546 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6547 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6548 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6549 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6550 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6551 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6552 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6553 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6554 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6555 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6556 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6557 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6558 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6559 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6560 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6561 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6562 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6563 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6564 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6565 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6566 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6567 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6568 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6569 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6570 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6571 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6572 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6573 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6574 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6575 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6576 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6577 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6578 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6579 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6580 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6581 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6582 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6583 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6584 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6585 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6586 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6587 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6588 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6589 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6590 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6591 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6592 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6593 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6594 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6595 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6596 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6597 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6598 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6599 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6600 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6601 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6602 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6603 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6604 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6605 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6606 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6607 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6608 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6609 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6610 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6611 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6612 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6613 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6614 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6615 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6616 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6617 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6618 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6619 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6620 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6621 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6622 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6623 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6624 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6625 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6626 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6627 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6628 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6629 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6630 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6631 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6632 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6633 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6634 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6635 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6636 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6637 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6638 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6639 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6640 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6641 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6643 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6644 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6645 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6646 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6647 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6648 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6649 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6650 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6651 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6652 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6653 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6654 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6655 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6656 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6657 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6658 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6659 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6660 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6661 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6662 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6663 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6664 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6665 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6666 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6667 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6668 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6669 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6670 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6671 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6672 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6673 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6674 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6675 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6676 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6677 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6678 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6679 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6680 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6681 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6682 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6683 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6684 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6685 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6686 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6687 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6688 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6689 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6690 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6691 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6692 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6693 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6694 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6695 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6696 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6697 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6698 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6699 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6700 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6701 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6702 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6703 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6704 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6705 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6706 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6707 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6708 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6709 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6710 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6711 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6712 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6713 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6714 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6715 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6716 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6717 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6718 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6719 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6720 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6721 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6722 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6723 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6724 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6725 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6726 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6727 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6728 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6729 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6730 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6731 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6732 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6733 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6734 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6735 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6736 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6737 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6738 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6739 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6740 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6741 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6742 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6743 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6744 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6745 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6746 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6747 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6748 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6749 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6750 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6751 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6752 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6753 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6754 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6755 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6756 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6757 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6758 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6759 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6760 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6761 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6762 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6763 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6764 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6765 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6766 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6767 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6768 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6769 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6771 /* Place holder, leave as first spe builtin. */
6772 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6773 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6774 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6775 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6776 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6777 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6778 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6779 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6780 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6781 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6782 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6783 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6784 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6785 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6786 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6787 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6788 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6789 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6790 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6791 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6792 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6793 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6794 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6795 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6796 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6797 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6798 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6799 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6800 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6801 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6802 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6803 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6804 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6805 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6806 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6807 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6808 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6809 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6810 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6811 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6812 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6813 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6814 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6815 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6816 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6817 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6818 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6819 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6820 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6821 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6822 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6823 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6824 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6825 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6826 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6827 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6828 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6829 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6830 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6831 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6832 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6833 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6834 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6835 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6836 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6837 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6838 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6839 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6840 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6841 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6842 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6843 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6844 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6845 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6846 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6847 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6848 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6849 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6850 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6851 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6852 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6853 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6854 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6855 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6856 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6857 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6858 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6859 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6860 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6861 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6862 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6863 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6864 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6865 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6866 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6867 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6868 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6869 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6870 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6871 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6872 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6873 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6874 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6875 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6876 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6877 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6878 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6879 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6880 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6882 /* SPE binary operations expecting a 5-bit unsigned literal. */
6883 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6885 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6886 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6887 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6888 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6889 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6890 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6891 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6892 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6893 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6894 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6895 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6896 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6897 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6898 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6899 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6900 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6901 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6902 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6903 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6904 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6905 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6906 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6907 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6908 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6909 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6910 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6912 /* Place-holder. Leave as last binary SPE builtin. */
6913 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6916 /* AltiVec predicates. */
6918 struct builtin_description_predicates
6920 const unsigned int mask;
6921 const enum insn_code icode;
6923 const char *const name;
6924 const enum rs6000_builtins code;
6927 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6929 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6930 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6931 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6932 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6933 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6934 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6935 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6936 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6937 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6938 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6939 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6940 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6941 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6943 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6944 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6945 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6948 /* SPE predicates. */
6949 static struct builtin_description bdesc_spe_predicates[] =
6951 /* Place-holder. Leave as first. */
6952 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6953 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6954 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6955 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6956 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6957 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6958 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6959 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6960 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6961 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6962 /* Place-holder. Leave as last. */
6963 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6966 /* SPE evsel predicates. */
6967 static struct builtin_description bdesc_spe_evsel[] =
6969 /* Place-holder. Leave as first. */
6970 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6971 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6972 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6973 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6974 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6975 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6976 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6977 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6978 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6979 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6980 /* Place-holder. Leave as last. */
6981 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6984 /* ABS* operations. */
6986 static const struct builtin_description bdesc_abs[] =
6988 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6989 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6990 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6991 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6992 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6993 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6994 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6997 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7000 static struct builtin_description bdesc_1arg[] =
7002 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
7003 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
7004 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
7005 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
7006 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
7007 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
7008 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
7009 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
7010 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
7011 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
7012 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
7013 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
7014 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
7015 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
7016 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
7017 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
7018 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
7020 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
7021 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
7022 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
7023 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
7024 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
7025 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7026 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7027 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7028 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7029 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7030 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7031 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7032 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7033 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7034 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7035 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7036 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7037 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7038 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7040 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7041 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7042 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7043 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7044 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7045 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7046 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7047 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7048 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7049 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7050 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7051 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7052 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7053 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7054 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7055 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7056 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7057 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7058 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7059 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7060 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7061 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7062 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7063 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7064 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7065 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7066 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7067 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7068 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7069 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7071 /* Place-holder. Leave as last unary SPE builtin. */
7072 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
7076 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7079 tree arg0 = CALL_EXPR_ARG (exp, 0);
7080 rtx op0 = expand_normal (arg0);
7081 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7082 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7084 if (icode == CODE_FOR_nothing)
7085 /* Builtin not supported on this processor. */
7088 /* If we got invalid arguments bail out before generating bad rtl. */
7089 if (arg0 == error_mark_node)
7092 if (icode == CODE_FOR_altivec_vspltisb
7093 || icode == CODE_FOR_altivec_vspltish
7094 || icode == CODE_FOR_altivec_vspltisw
7095 || icode == CODE_FOR_spe_evsplatfi
7096 || icode == CODE_FOR_spe_evsplati)
7098 /* Only allow 5-bit *signed* literals. */
7099 if (GET_CODE (op0) != CONST_INT
7100 || INTVAL (op0) > 15
7101 || INTVAL (op0) < -16)
7103 error ("argument 1 must be a 5-bit signed literal");
7109 || GET_MODE (target) != tmode
7110 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7111 target = gen_reg_rtx (tmode);
7113 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7114 op0 = copy_to_mode_reg (mode0, op0);
7116 pat = GEN_FCN (icode) (target, op0);
7125 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7127 rtx pat, scratch1, scratch2;
7128 tree arg0 = CALL_EXPR_ARG (exp, 0);
7129 rtx op0 = expand_normal (arg0);
7130 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7131 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7133 /* If we have invalid arguments, bail out before generating bad rtl. */
7134 if (arg0 == error_mark_node)
7138 || GET_MODE (target) != tmode
7139 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7140 target = gen_reg_rtx (tmode);
7142 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7143 op0 = copy_to_mode_reg (mode0, op0);
7145 scratch1 = gen_reg_rtx (mode0);
7146 scratch2 = gen_reg_rtx (mode0);
7148 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7157 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7160 tree arg0 = CALL_EXPR_ARG (exp, 0);
7161 tree arg1 = CALL_EXPR_ARG (exp, 1);
7162 rtx op0 = expand_normal (arg0);
7163 rtx op1 = expand_normal (arg1);
7164 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7165 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7166 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7168 if (icode == CODE_FOR_nothing)
7169 /* Builtin not supported on this processor. */
7172 /* If we got invalid arguments bail out before generating bad rtl. */
7173 if (arg0 == error_mark_node || arg1 == error_mark_node)
7176 if (icode == CODE_FOR_altivec_vcfux
7177 || icode == CODE_FOR_altivec_vcfsx
7178 || icode == CODE_FOR_altivec_vctsxs
7179 || icode == CODE_FOR_altivec_vctuxs
7180 || icode == CODE_FOR_altivec_vspltb
7181 || icode == CODE_FOR_altivec_vsplth
7182 || icode == CODE_FOR_altivec_vspltw
7183 || icode == CODE_FOR_spe_evaddiw
7184 || icode == CODE_FOR_spe_evldd
7185 || icode == CODE_FOR_spe_evldh
7186 || icode == CODE_FOR_spe_evldw
7187 || icode == CODE_FOR_spe_evlhhesplat
7188 || icode == CODE_FOR_spe_evlhhossplat
7189 || icode == CODE_FOR_spe_evlhhousplat
7190 || icode == CODE_FOR_spe_evlwhe
7191 || icode == CODE_FOR_spe_evlwhos
7192 || icode == CODE_FOR_spe_evlwhou
7193 || icode == CODE_FOR_spe_evlwhsplat
7194 || icode == CODE_FOR_spe_evlwwsplat
7195 || icode == CODE_FOR_spe_evrlwi
7196 || icode == CODE_FOR_spe_evslwi
7197 || icode == CODE_FOR_spe_evsrwis
7198 || icode == CODE_FOR_spe_evsubifw
7199 || icode == CODE_FOR_spe_evsrwiu)
7201 /* Only allow 5-bit unsigned literals. */
7203 if (TREE_CODE (arg1) != INTEGER_CST
7204 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7206 error ("argument 2 must be a 5-bit unsigned literal");
7212 || GET_MODE (target) != tmode
7213 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7214 target = gen_reg_rtx (tmode);
7216 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7217 op0 = copy_to_mode_reg (mode0, op0);
7218 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7219 op1 = copy_to_mode_reg (mode1, op1);
7221 pat = GEN_FCN (icode) (target, op0, op1);
7230 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7231 tree exp, rtx target)
7234 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7235 tree arg0 = CALL_EXPR_ARG (exp, 1);
7236 tree arg1 = CALL_EXPR_ARG (exp, 2);
7237 rtx op0 = expand_normal (arg0);
7238 rtx op1 = expand_normal (arg1);
7239 enum machine_mode tmode = SImode;
7240 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7241 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7244 if (TREE_CODE (cr6_form) != INTEGER_CST)
7246 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7250 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7252 gcc_assert (mode0 == mode1);
7254 /* If we have invalid arguments, bail out before generating bad rtl. */
7255 if (arg0 == error_mark_node || arg1 == error_mark_node)
7259 || GET_MODE (target) != tmode
7260 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7261 target = gen_reg_rtx (tmode);
7263 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7264 op0 = copy_to_mode_reg (mode0, op0);
7265 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7266 op1 = copy_to_mode_reg (mode1, op1);
7268 scratch = gen_reg_rtx (mode0);
7270 pat = GEN_FCN (icode) (scratch, op0, op1,
7271 gen_rtx_SYMBOL_REF (Pmode, opcode));
7276 /* The vec_any* and vec_all* predicates use the same opcodes for two
7277 different operations, but the bits in CR6 will be different
7278 depending on what information we want. So we have to play tricks
7279 with CR6 to get the right bits out.
7281 If you think this is disgusting, look at the specs for the
7282 AltiVec predicates. */
7284 switch (cr6_form_int)
7287 emit_insn (gen_cr6_test_for_zero (target));
7290 emit_insn (gen_cr6_test_for_zero_reverse (target));
7293 emit_insn (gen_cr6_test_for_lt (target));
7296 emit_insn (gen_cr6_test_for_lt_reverse (target));
7299 error ("argument 1 of __builtin_altivec_predicate is out of range");
7307 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7310 tree arg0 = CALL_EXPR_ARG (exp, 0);
7311 tree arg1 = CALL_EXPR_ARG (exp, 1);
7312 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7313 enum machine_mode mode0 = Pmode;
7314 enum machine_mode mode1 = Pmode;
7315 rtx op0 = expand_normal (arg0);
7316 rtx op1 = expand_normal (arg1);
7318 if (icode == CODE_FOR_nothing)
7319 /* Builtin not supported on this processor. */
7322 /* If we got invalid arguments bail out before generating bad rtl. */
7323 if (arg0 == error_mark_node || arg1 == error_mark_node)
7327 || GET_MODE (target) != tmode
7328 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7329 target = gen_reg_rtx (tmode);
7331 op1 = copy_to_mode_reg (mode1, op1);
7333 if (op0 == const0_rtx)
7335 addr = gen_rtx_MEM (tmode, op1);
7339 op0 = copy_to_mode_reg (mode0, op0);
7340 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7343 pat = GEN_FCN (icode) (target, addr);
7353 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7355 tree arg0 = CALL_EXPR_ARG (exp, 0);
7356 tree arg1 = CALL_EXPR_ARG (exp, 1);
7357 tree arg2 = CALL_EXPR_ARG (exp, 2);
7358 rtx op0 = expand_normal (arg0);
7359 rtx op1 = expand_normal (arg1);
7360 rtx op2 = expand_normal (arg2);
7362 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7363 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7364 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7366 /* Invalid arguments. Bail before doing anything stoopid! */
7367 if (arg0 == error_mark_node
7368 || arg1 == error_mark_node
7369 || arg2 == error_mark_node)
7372 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7373 op0 = copy_to_mode_reg (mode2, op0);
7374 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7375 op1 = copy_to_mode_reg (mode0, op1);
7376 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7377 op2 = copy_to_mode_reg (mode1, op2);
7379 pat = GEN_FCN (icode) (op1, op2, op0);
7386 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
7388 tree arg0 = CALL_EXPR_ARG (exp, 0);
7389 tree arg1 = CALL_EXPR_ARG (exp, 1);
7390 tree arg2 = CALL_EXPR_ARG (exp, 2);
7391 rtx op0 = expand_normal (arg0);
7392 rtx op1 = expand_normal (arg1);
7393 rtx op2 = expand_normal (arg2);
7395 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7396 enum machine_mode mode1 = Pmode;
7397 enum machine_mode mode2 = Pmode;
7399 /* Invalid arguments. Bail before doing anything stoopid! */
7400 if (arg0 == error_mark_node
7401 || arg1 == error_mark_node
7402 || arg2 == error_mark_node)
7405 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7406 op0 = copy_to_mode_reg (tmode, op0);
7408 op2 = copy_to_mode_reg (mode2, op2);
7410 if (op1 == const0_rtx)
7412 addr = gen_rtx_MEM (tmode, op2);
7416 op1 = copy_to_mode_reg (mode1, op1);
7417 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7420 pat = GEN_FCN (icode) (addr, op0);
7427 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
7430 tree arg0 = CALL_EXPR_ARG (exp, 0);
7431 tree arg1 = CALL_EXPR_ARG (exp, 1);
7432 tree arg2 = CALL_EXPR_ARG (exp, 2);
7433 rtx op0 = expand_normal (arg0);
7434 rtx op1 = expand_normal (arg1);
7435 rtx op2 = expand_normal (arg2);
7436 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7437 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7438 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7439 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7441 if (icode == CODE_FOR_nothing)
7442 /* Builtin not supported on this processor. */
7445 /* If we got invalid arguments bail out before generating bad rtl. */
7446 if (arg0 == error_mark_node
7447 || arg1 == error_mark_node
7448 || arg2 == error_mark_node)
7451 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7452 || icode == CODE_FOR_altivec_vsldoi_v4si
7453 || icode == CODE_FOR_altivec_vsldoi_v8hi
7454 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7456 /* Only allow 4-bit unsigned literals. */
7458 if (TREE_CODE (arg2) != INTEGER_CST
7459 || TREE_INT_CST_LOW (arg2) & ~0xf)
7461 error ("argument 3 must be a 4-bit unsigned literal");
7467 || GET_MODE (target) != tmode
7468 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7469 target = gen_reg_rtx (tmode);
7471 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7472 op0 = copy_to_mode_reg (mode0, op0);
7473 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7474 op1 = copy_to_mode_reg (mode1, op1);
7475 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7476 op2 = copy_to_mode_reg (mode2, op2);
7478 pat = GEN_FCN (icode) (target, op0, op1, op2);
7486 /* Expand the lvx builtins. */
7488 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7490 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7491 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7493 enum machine_mode tmode, mode0;
7495 enum insn_code icode;
7499 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7500 icode = CODE_FOR_altivec_lvx_v16qi;
7502 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7503 icode = CODE_FOR_altivec_lvx_v8hi;
7505 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7506 icode = CODE_FOR_altivec_lvx_v4si;
7508 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7509 icode = CODE_FOR_altivec_lvx_v4sf;
7518 arg0 = CALL_EXPR_ARG (exp, 0);
7519 op0 = expand_normal (arg0);
7520 tmode = insn_data[icode].operand[0].mode;
7521 mode0 = insn_data[icode].operand[1].mode;
7524 || GET_MODE (target) != tmode
7525 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7526 target = gen_reg_rtx (tmode);
7528 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7529 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7531 pat = GEN_FCN (icode) (target, op0);
7538 /* Expand the stvx builtins. */
7540 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7543 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7544 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7546 enum machine_mode mode0, mode1;
7548 enum insn_code icode;
7552 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7553 icode = CODE_FOR_altivec_stvx_v16qi;
7555 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7556 icode = CODE_FOR_altivec_stvx_v8hi;
7558 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7559 icode = CODE_FOR_altivec_stvx_v4si;
7561 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7562 icode = CODE_FOR_altivec_stvx_v4sf;
7569 arg0 = CALL_EXPR_ARG (exp, 0);
7570 arg1 = CALL_EXPR_ARG (exp, 1);
7571 op0 = expand_normal (arg0);
7572 op1 = expand_normal (arg1);
7573 mode0 = insn_data[icode].operand[0].mode;
7574 mode1 = insn_data[icode].operand[1].mode;
7576 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7577 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7578 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7579 op1 = copy_to_mode_reg (mode1, op1);
7581 pat = GEN_FCN (icode) (op0, op1);
7589 /* Expand the dst builtins. */
7591 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7594 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7595 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7596 tree arg0, arg1, arg2;
7597 enum machine_mode mode0, mode1, mode2;
7598 rtx pat, op0, op1, op2;
7599 struct builtin_description *d;
7604 /* Handle DST variants. */
7605 d = (struct builtin_description *) bdesc_dst;
7606 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7607 if (d->code == fcode)
7609 arg0 = CALL_EXPR_ARG (exp, 0);
7610 arg1 = CALL_EXPR_ARG (exp, 1);
7611 arg2 = CALL_EXPR_ARG (exp, 2);
7612 op0 = expand_normal (arg0);
7613 op1 = expand_normal (arg1);
7614 op2 = expand_normal (arg2);
7615 mode0 = insn_data[d->icode].operand[0].mode;
7616 mode1 = insn_data[d->icode].operand[1].mode;
7617 mode2 = insn_data[d->icode].operand[2].mode;
7619 /* Invalid arguments, bail out before generating bad rtl. */
7620 if (arg0 == error_mark_node
7621 || arg1 == error_mark_node
7622 || arg2 == error_mark_node)
7627 if (TREE_CODE (arg2) != INTEGER_CST
7628 || TREE_INT_CST_LOW (arg2) & ~0x3)
7630 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7634 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7635 op0 = copy_to_mode_reg (Pmode, op0);
7636 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7637 op1 = copy_to_mode_reg (mode1, op1);
7639 pat = GEN_FCN (d->icode) (op0, op1, op2);
7649 /* Expand vec_init builtin. */
7651 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
7653 enum machine_mode tmode = TYPE_MODE (type);
7654 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7655 int i, n_elt = GET_MODE_NUNITS (tmode);
7656 rtvec v = rtvec_alloc (n_elt);
7658 gcc_assert (VECTOR_MODE_P (tmode));
7659 gcc_assert (n_elt == call_expr_nargs (exp));
7661 for (i = 0; i < n_elt; ++i)
7663 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
7664 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7667 if (!target || !register_operand (target, tmode))
7668 target = gen_reg_rtx (tmode);
7670 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7674 /* Return the integer constant in ARG. Constrain it to be in the range
7675 of the subparts of VEC_TYPE; issue an error if not. */
7678 get_element_number (tree vec_type, tree arg)
7680 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7682 if (!host_integerp (arg, 1)
7683 || (elt = tree_low_cst (arg, 1), elt > max))
7685 error ("selector must be an integer constant in the range 0..%wi", max);
7692 /* Expand vec_set builtin. */
7694 altivec_expand_vec_set_builtin (tree exp)
7696 enum machine_mode tmode, mode1;
7697 tree arg0, arg1, arg2;
7701 arg0 = CALL_EXPR_ARG (exp, 0);
7702 arg1 = CALL_EXPR_ARG (exp, 1);
7703 arg2 = CALL_EXPR_ARG (exp, 2);
7705 tmode = TYPE_MODE (TREE_TYPE (arg0));
7706 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7707 gcc_assert (VECTOR_MODE_P (tmode));
7709 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7710 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7711 elt = get_element_number (TREE_TYPE (arg0), arg2);
7713 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7714 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7716 op0 = force_reg (tmode, op0);
7717 op1 = force_reg (mode1, op1);
7719 rs6000_expand_vector_set (op0, op1, elt);
7724 /* Expand vec_ext builtin. */
7726 altivec_expand_vec_ext_builtin (tree exp, rtx target)
7728 enum machine_mode tmode, mode0;
7733 arg0 = CALL_EXPR_ARG (exp, 0);
7734 arg1 = CALL_EXPR_ARG (exp, 1);
7736 op0 = expand_normal (arg0);
7737 elt = get_element_number (TREE_TYPE (arg0), arg1);
7739 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7740 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7741 gcc_assert (VECTOR_MODE_P (mode0));
7743 op0 = force_reg (mode0, op0);
7745 if (optimize || !target || !register_operand (target, tmode))
7746 target = gen_reg_rtx (tmode);
7748 rs6000_expand_vector_extract (target, op0, elt);
7753 /* Expand the builtin in EXP and store the result in TARGET. Store
7754 true in *EXPANDEDP if we found a builtin to expand. */
7756 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7758 struct builtin_description *d;
7759 struct builtin_description_predicates *dp;
7761 enum insn_code icode;
7762 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7765 enum machine_mode tmode, mode0;
7766 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7768 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7769 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7772 error ("unresolved overload for Altivec builtin %qF", fndecl);
7776 target = altivec_expand_ld_builtin (exp, target, expandedp);
7780 target = altivec_expand_st_builtin (exp, target, expandedp);
7784 target = altivec_expand_dst_builtin (exp, target, expandedp);
7792 case ALTIVEC_BUILTIN_STVX:
7793 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
7794 case ALTIVEC_BUILTIN_STVEBX:
7795 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
7796 case ALTIVEC_BUILTIN_STVEHX:
7797 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
7798 case ALTIVEC_BUILTIN_STVEWX:
7799 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
7800 case ALTIVEC_BUILTIN_STVXL:
7801 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
7803 case ALTIVEC_BUILTIN_MFVSCR:
7804 icode = CODE_FOR_altivec_mfvscr;
7805 tmode = insn_data[icode].operand[0].mode;
7808 || GET_MODE (target) != tmode
7809 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7810 target = gen_reg_rtx (tmode);
7812 pat = GEN_FCN (icode) (target);
7818 case ALTIVEC_BUILTIN_MTVSCR:
7819 icode = CODE_FOR_altivec_mtvscr;
7820 arg0 = CALL_EXPR_ARG (exp, 0);
7821 op0 = expand_normal (arg0);
7822 mode0 = insn_data[icode].operand[0].mode;
7824 /* If we got invalid arguments bail out before generating bad rtl. */
7825 if (arg0 == error_mark_node)
7828 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7829 op0 = copy_to_mode_reg (mode0, op0);
7831 pat = GEN_FCN (icode) (op0);
7836 case ALTIVEC_BUILTIN_DSSALL:
7837 emit_insn (gen_altivec_dssall ());
7840 case ALTIVEC_BUILTIN_DSS:
7841 icode = CODE_FOR_altivec_dss;
7842 arg0 = CALL_EXPR_ARG (exp, 0);
7844 op0 = expand_normal (arg0);
7845 mode0 = insn_data[icode].operand[0].mode;
7847 /* If we got invalid arguments bail out before generating bad rtl. */
7848 if (arg0 == error_mark_node)
7851 if (TREE_CODE (arg0) != INTEGER_CST
7852 || TREE_INT_CST_LOW (arg0) & ~0x3)
7854 error ("argument to dss must be a 2-bit unsigned literal");
7858 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7859 op0 = copy_to_mode_reg (mode0, op0);
7861 emit_insn (gen_altivec_dss (op0));
7864 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7865 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7866 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7867 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7868 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
7870 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7871 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7872 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7873 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7874 return altivec_expand_vec_set_builtin (exp);
7876 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7877 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7878 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7879 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7880 return altivec_expand_vec_ext_builtin (exp, target);
7887 /* Expand abs* operations. */
7888 d = (struct builtin_description *) bdesc_abs;
7889 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7890 if (d->code == fcode)
7891 return altivec_expand_abs_builtin (d->icode, exp, target);
7893 /* Expand the AltiVec predicates. */
7894 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7895 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7896 if (dp->code == fcode)
7897 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7900 /* LV* are funky. We initialized them differently. */
7903 case ALTIVEC_BUILTIN_LVSL:
7904 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7906 case ALTIVEC_BUILTIN_LVSR:
7907 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7909 case ALTIVEC_BUILTIN_LVEBX:
7910 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7912 case ALTIVEC_BUILTIN_LVEHX:
7913 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7915 case ALTIVEC_BUILTIN_LVEWX:
7916 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7918 case ALTIVEC_BUILTIN_LVXL:
7919 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7921 case ALTIVEC_BUILTIN_LVX:
7922 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7933 /* Binops that need to be initialized manually, but can be expanded
7934 automagically by rs6000_expand_binop_builtin. */
7935 static struct builtin_description bdesc_2arg_spe[] =
7937 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7938 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7939 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7940 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7941 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7942 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7943 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7944 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7945 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7946 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7947 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7948 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7949 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7950 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7951 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7952 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7953 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7954 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7955 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7956 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7957 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7958 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7961 /* Expand the builtin in EXP and store the result in TARGET. Store
7962 true in *EXPANDEDP if we found a builtin to expand.
7964 This expands the SPE builtins that are not simple unary and binary
7967 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7969 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7971 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7972 enum insn_code icode;
7973 enum machine_mode tmode, mode0;
7975 struct builtin_description *d;
7980 /* Syntax check for a 5-bit unsigned immediate. */
7983 case SPE_BUILTIN_EVSTDD:
7984 case SPE_BUILTIN_EVSTDH:
7985 case SPE_BUILTIN_EVSTDW:
7986 case SPE_BUILTIN_EVSTWHE:
7987 case SPE_BUILTIN_EVSTWHO:
7988 case SPE_BUILTIN_EVSTWWE:
7989 case SPE_BUILTIN_EVSTWWO:
7990 arg1 = CALL_EXPR_ARG (exp, 2);
7991 if (TREE_CODE (arg1) != INTEGER_CST
7992 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7994 error ("argument 2 must be a 5-bit unsigned literal");
8002 /* The evsplat*i instructions are not quite generic. */
8005 case SPE_BUILTIN_EVSPLATFI:
8006 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
8008 case SPE_BUILTIN_EVSPLATI:
8009 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
8015 d = (struct builtin_description *) bdesc_2arg_spe;
8016 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
8017 if (d->code == fcode)
8018 return rs6000_expand_binop_builtin (d->icode, exp, target);
8020 d = (struct builtin_description *) bdesc_spe_predicates;
8021 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
8022 if (d->code == fcode)
8023 return spe_expand_predicate_builtin (d->icode, exp, target);
8025 d = (struct builtin_description *) bdesc_spe_evsel;
8026 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8027 if (d->code == fcode)
8028 return spe_expand_evsel_builtin (d->icode, exp, target);
8032 case SPE_BUILTIN_EVSTDDX:
8033 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8034 case SPE_BUILTIN_EVSTDHX:
8035 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8036 case SPE_BUILTIN_EVSTDWX:
8037 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8038 case SPE_BUILTIN_EVSTWHEX:
8039 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8040 case SPE_BUILTIN_EVSTWHOX:
8041 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8042 case SPE_BUILTIN_EVSTWWEX:
8043 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8044 case SPE_BUILTIN_EVSTWWOX:
8045 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8046 case SPE_BUILTIN_EVSTDD:
8047 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8048 case SPE_BUILTIN_EVSTDH:
8049 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8050 case SPE_BUILTIN_EVSTDW:
8051 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8052 case SPE_BUILTIN_EVSTWHE:
8053 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8054 case SPE_BUILTIN_EVSTWHO:
8055 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8056 case SPE_BUILTIN_EVSTWWE:
8057 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8058 case SPE_BUILTIN_EVSTWWO:
8059 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8060 case SPE_BUILTIN_MFSPEFSCR:
8061 icode = CODE_FOR_spe_mfspefscr;
8062 tmode = insn_data[icode].operand[0].mode;
8065 || GET_MODE (target) != tmode
8066 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8067 target = gen_reg_rtx (tmode);
8069 pat = GEN_FCN (icode) (target);
8074 case SPE_BUILTIN_MTSPEFSCR:
8075 icode = CODE_FOR_spe_mtspefscr;
8076 arg0 = CALL_EXPR_ARG (exp, 0);
8077 op0 = expand_normal (arg0);
8078 mode0 = insn_data[icode].operand[0].mode;
8080 if (arg0 == error_mark_node)
8083 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8084 op0 = copy_to_mode_reg (mode0, op0);
8086 pat = GEN_FCN (icode) (op0);
8099 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8101 rtx pat, scratch, tmp;
8102 tree form = CALL_EXPR_ARG (exp, 0);
8103 tree arg0 = CALL_EXPR_ARG (exp, 1);
8104 tree arg1 = CALL_EXPR_ARG (exp, 2);
8105 rtx op0 = expand_normal (arg0);
8106 rtx op1 = expand_normal (arg1);
8107 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8108 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8112 if (TREE_CODE (form) != INTEGER_CST)
8114 error ("argument 1 of __builtin_spe_predicate must be a constant");
8118 form_int = TREE_INT_CST_LOW (form);
8120 gcc_assert (mode0 == mode1);
8122 if (arg0 == error_mark_node || arg1 == error_mark_node)
8126 || GET_MODE (target) != SImode
8127 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8128 target = gen_reg_rtx (SImode);
8130 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8131 op0 = copy_to_mode_reg (mode0, op0);
8132 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8133 op1 = copy_to_mode_reg (mode1, op1);
8135 scratch = gen_reg_rtx (CCmode);
8137 pat = GEN_FCN (icode) (scratch, op0, op1);
8142 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8143 _lower_. We use one compare, but look in different bits of the
8144 CR for each variant.
8146 There are 2 elements in each SPE simd type (upper/lower). The CR
8147 bits are set as follows:
8149 BIT0 | BIT 1 | BIT 2 | BIT 3
8150 U | L | (U | L) | (U & L)
8152 So, for an "all" relationship, BIT 3 would be set.
8153 For an "any" relationship, BIT 2 would be set. Etc.
8155 Following traditional nomenclature, these bits map to:
8157 BIT0 | BIT 1 | BIT 2 | BIT 3
8160 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8165 /* All variant. OV bit. */
8167 /* We need to get to the OV bit, which is the ORDERED bit. We
8168 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8169 that's ugly and will make validate_condition_mode die.
8170 So let's just use another pattern. */
8171 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8173 /* Any variant. EQ bit. */
8177 /* Upper variant. LT bit. */
8181 /* Lower variant. GT bit. */
8186 error ("argument 1 of __builtin_spe_predicate is out of range");
8190 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8191 emit_move_insn (target, tmp);
8196 /* The evsel builtins look like this:
8198 e = __builtin_spe_evsel_OP (a, b, c, d);
8202 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8203 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8207 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8210 tree arg0 = CALL_EXPR_ARG (exp, 0);
8211 tree arg1 = CALL_EXPR_ARG (exp, 1);
8212 tree arg2 = CALL_EXPR_ARG (exp, 2);
8213 tree arg3 = CALL_EXPR_ARG (exp, 3);
8214 rtx op0 = expand_normal (arg0);
8215 rtx op1 = expand_normal (arg1);
8216 rtx op2 = expand_normal (arg2);
8217 rtx op3 = expand_normal (arg3);
8218 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8219 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8221 gcc_assert (mode0 == mode1);
8223 if (arg0 == error_mark_node || arg1 == error_mark_node
8224 || arg2 == error_mark_node || arg3 == error_mark_node)
8228 || GET_MODE (target) != mode0
8229 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8230 target = gen_reg_rtx (mode0);
8232 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8233 op0 = copy_to_mode_reg (mode0, op0);
8234 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8235 op1 = copy_to_mode_reg (mode0, op1);
8236 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8237 op2 = copy_to_mode_reg (mode0, op2);
8238 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8239 op3 = copy_to_mode_reg (mode0, op3);
8241 /* Generate the compare. */
8242 scratch = gen_reg_rtx (CCmode);
8243 pat = GEN_FCN (icode) (scratch, op0, op1);
8248 if (mode0 == V2SImode)
8249 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8251 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8256 /* Expand an expression EXP that calls a built-in function,
8257 with result going to TARGET if that's convenient
8258 (and in mode MODE if that's convenient).
8259 SUBTARGET may be used as the target for computing one of EXP's operands.
8260 IGNORE is nonzero if the value is to be ignored. */
8263 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8264 enum machine_mode mode ATTRIBUTE_UNUSED,
8265 int ignore ATTRIBUTE_UNUSED)
8267 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8268 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8269 struct builtin_description *d;
8274 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8275 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8277 int icode = (int) CODE_FOR_altivec_lvsr;
8278 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8279 enum machine_mode mode = insn_data[icode].operand[1].mode;
8283 gcc_assert (TARGET_ALTIVEC);
8285 arg = CALL_EXPR_ARG (exp, 0);
8286 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
8287 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
8288 addr = memory_address (mode, op);
8289 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8293 /* For the load case need to negate the address. */
8294 op = gen_reg_rtx (GET_MODE (addr));
8295 emit_insn (gen_rtx_SET (VOIDmode, op,
8296 gen_rtx_NEG (GET_MODE (addr), addr)));
8298 op = gen_rtx_MEM (mode, op);
8301 || GET_MODE (target) != tmode
8302 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8303 target = gen_reg_rtx (tmode);
8305 /*pat = gen_altivec_lvsr (target, op);*/
8306 pat = GEN_FCN (icode) (target, op);
8314 /* FIXME: There's got to be a nicer way to handle this case than
8315 constructing a new CALL_EXPR. */
8316 if (fcode == ALTIVEC_BUILTIN_VCFUX
8317 || fcode == ALTIVEC_BUILTIN_VCFSX)
8319 if (call_expr_nargs (exp) == 1)
8320 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
8321 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
8326 ret = altivec_expand_builtin (exp, target, &success);
8333 ret = spe_expand_builtin (exp, target, &success);
8339 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
8341 /* Handle simple unary operations. */
8342 d = (struct builtin_description *) bdesc_1arg;
8343 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8344 if (d->code == fcode)
8345 return rs6000_expand_unop_builtin (d->icode, exp, target);
8347 /* Handle simple binary operations. */
8348 d = (struct builtin_description *) bdesc_2arg;
8349 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8350 if (d->code == fcode)
8351 return rs6000_expand_binop_builtin (d->icode, exp, target);
8353 /* Handle simple ternary operations. */
8354 d = (struct builtin_description *) bdesc_3arg;
8355 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8356 if (d->code == fcode)
8357 return rs6000_expand_ternop_builtin (d->icode, exp, target);
8363 build_opaque_vector_type (tree node, int nunits)
8365 node = copy_node (node);
8366 TYPE_MAIN_VARIANT (node) = node;
8367 return build_vector_type (node, nunits);
8371 rs6000_init_builtins (void)
8373 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8374 V2SF_type_node = build_vector_type (float_type_node, 2);
8375 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8376 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8377 V4SF_type_node = build_vector_type (float_type_node, 4);
8378 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8379 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8381 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8382 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8383 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8385 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8386 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8387 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8388 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8390 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8391 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8392 'vector unsigned short'. */
8394 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8395 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8396 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8397 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8399 long_integer_type_internal_node = long_integer_type_node;
8400 long_unsigned_type_internal_node = long_unsigned_type_node;
8401 intQI_type_internal_node = intQI_type_node;
8402 uintQI_type_internal_node = unsigned_intQI_type_node;
8403 intHI_type_internal_node = intHI_type_node;
8404 uintHI_type_internal_node = unsigned_intHI_type_node;
8405 intSI_type_internal_node = intSI_type_node;
8406 uintSI_type_internal_node = unsigned_intSI_type_node;
8407 float_type_internal_node = float_type_node;
8408 void_type_internal_node = void_type_node;
8410 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8411 get_identifier ("__bool char"),
8412 bool_char_type_node));
8413 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8414 get_identifier ("__bool short"),
8415 bool_short_type_node));
8416 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8417 get_identifier ("__bool int"),
8418 bool_int_type_node));
8419 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8420 get_identifier ("__pixel"),
8423 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8424 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8425 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8426 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8428 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8429 get_identifier ("__vector unsigned char"),
8430 unsigned_V16QI_type_node));
8431 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8432 get_identifier ("__vector signed char"),
8434 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8435 get_identifier ("__vector __bool char"),
8436 bool_V16QI_type_node));
8438 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8439 get_identifier ("__vector unsigned short"),
8440 unsigned_V8HI_type_node));
8441 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8442 get_identifier ("__vector signed short"),
8444 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8445 get_identifier ("__vector __bool short"),
8446 bool_V8HI_type_node));
8448 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8449 get_identifier ("__vector unsigned int"),
8450 unsigned_V4SI_type_node));
8451 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8452 get_identifier ("__vector signed int"),
8454 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8455 get_identifier ("__vector __bool int"),
8456 bool_V4SI_type_node));
8458 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8459 get_identifier ("__vector float"),
8461 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8462 get_identifier ("__vector __pixel"),
8463 pixel_V8HI_type_node));
8466 spe_init_builtins ();
8468 altivec_init_builtins ();
8469 if (TARGET_ALTIVEC || TARGET_SPE)
8470 rs6000_common_init_builtins ();
8473 /* AIX libm provides clog as __clog. */
8474 if (built_in_decls [BUILT_IN_CLOG])
8475 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8479 /* Search through a set of builtins and enable the mask bits.
8480 DESC is an array of builtins.
8481 SIZE is the total number of builtins.
8482 START is the builtin enum at which to start.
8483 END is the builtin enum at which to end. */
8485 enable_mask_for_builtins (struct builtin_description *desc, int size,
8486 enum rs6000_builtins start,
8487 enum rs6000_builtins end)
8491 for (i = 0; i < size; ++i)
8492 if (desc[i].code == start)
8498 for (; i < size; ++i)
8500 /* Flip all the bits on. */
8501 desc[i].mask = target_flags;
8502 if (desc[i].code == end)
8508 spe_init_builtins (void)
8510 tree endlink = void_list_node;
8511 tree puint_type_node = build_pointer_type (unsigned_type_node);
8512 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8513 struct builtin_description *d;
8516 tree v2si_ftype_4_v2si
8517 = build_function_type
8518 (opaque_V2SI_type_node,
8519 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8520 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8521 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8522 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8525 tree v2sf_ftype_4_v2sf
8526 = build_function_type
8527 (opaque_V2SF_type_node,
8528 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8529 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8530 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8531 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8534 tree int_ftype_int_v2si_v2si
8535 = build_function_type
8537 tree_cons (NULL_TREE, integer_type_node,
8538 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8539 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8542 tree int_ftype_int_v2sf_v2sf
8543 = build_function_type
8545 tree_cons (NULL_TREE, integer_type_node,
8546 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8547 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8550 tree void_ftype_v2si_puint_int
8551 = build_function_type (void_type_node,
8552 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8553 tree_cons (NULL_TREE, puint_type_node,
8554 tree_cons (NULL_TREE,
8558 tree void_ftype_v2si_puint_char
8559 = build_function_type (void_type_node,
8560 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8561 tree_cons (NULL_TREE, puint_type_node,
8562 tree_cons (NULL_TREE,
8566 tree void_ftype_v2si_pv2si_int
8567 = build_function_type (void_type_node,
8568 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8569 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8570 tree_cons (NULL_TREE,
8574 tree void_ftype_v2si_pv2si_char
8575 = build_function_type (void_type_node,
8576 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8577 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8578 tree_cons (NULL_TREE,
8583 = build_function_type (void_type_node,
8584 tree_cons (NULL_TREE, integer_type_node, endlink));
8587 = build_function_type (integer_type_node, endlink);
8589 tree v2si_ftype_pv2si_int
8590 = build_function_type (opaque_V2SI_type_node,
8591 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8592 tree_cons (NULL_TREE, integer_type_node,
8595 tree v2si_ftype_puint_int
8596 = build_function_type (opaque_V2SI_type_node,
8597 tree_cons (NULL_TREE, puint_type_node,
8598 tree_cons (NULL_TREE, integer_type_node,
8601 tree v2si_ftype_pushort_int
8602 = build_function_type (opaque_V2SI_type_node,
8603 tree_cons (NULL_TREE, pushort_type_node,
8604 tree_cons (NULL_TREE, integer_type_node,
8607 tree v2si_ftype_signed_char
8608 = build_function_type (opaque_V2SI_type_node,
8609 tree_cons (NULL_TREE, signed_char_type_node,
8612 /* The initialization of the simple binary and unary builtins is
8613 done in rs6000_common_init_builtins, but we have to enable the
8614 mask bits here manually because we have run out of `target_flags'
8615 bits. We really need to redesign this mask business. */
8617 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8618 ARRAY_SIZE (bdesc_2arg),
8621 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8622 ARRAY_SIZE (bdesc_1arg),
8624 SPE_BUILTIN_EVSUBFUSIAAW);
8625 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8626 ARRAY_SIZE (bdesc_spe_predicates),
8627 SPE_BUILTIN_EVCMPEQ,
8628 SPE_BUILTIN_EVFSTSTLT);
8629 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8630 ARRAY_SIZE (bdesc_spe_evsel),
8631 SPE_BUILTIN_EVSEL_CMPGTS,
8632 SPE_BUILTIN_EVSEL_FSTSTEQ);
8634 (*lang_hooks.decls.pushdecl)
8635 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8636 opaque_V2SI_type_node));
8638 /* Initialize irregular SPE builtins. */
8640 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8641 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8642 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8643 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8644 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8645 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8646 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8647 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8648 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8649 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8650 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8651 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8652 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8653 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8654 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8655 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8656 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8657 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8660 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8661 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8662 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8663 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8664 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8665 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8666 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8667 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8668 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8669 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8670 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8671 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8672 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8673 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8674 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8675 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8676 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8677 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8678 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8679 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8680 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8681 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8684 d = (struct builtin_description *) bdesc_spe_predicates;
8685 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8689 switch (insn_data[d->icode].operand[1].mode)
8692 type = int_ftype_int_v2si_v2si;
8695 type = int_ftype_int_v2sf_v2sf;
8701 def_builtin (d->mask, d->name, type, d->code);
8704 /* Evsel predicates. */
8705 d = (struct builtin_description *) bdesc_spe_evsel;
8706 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8710 switch (insn_data[d->icode].operand[1].mode)
8713 type = v2si_ftype_4_v2si;
8716 type = v2sf_ftype_4_v2sf;
8722 def_builtin (d->mask, d->name, type, d->code);
8727 altivec_init_builtins (void)
8729 struct builtin_description *d;
8730 struct builtin_description_predicates *dp;
8734 tree pfloat_type_node = build_pointer_type (float_type_node);
8735 tree pint_type_node = build_pointer_type (integer_type_node);
8736 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8737 tree pchar_type_node = build_pointer_type (char_type_node);
8739 tree pvoid_type_node = build_pointer_type (void_type_node);
8741 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8742 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8743 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8744 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8746 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8748 tree int_ftype_opaque
8749 = build_function_type_list (integer_type_node,
8750 opaque_V4SI_type_node, NULL_TREE);
8752 tree opaque_ftype_opaque_int
8753 = build_function_type_list (opaque_V4SI_type_node,
8754 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8755 tree opaque_ftype_opaque_opaque_int
8756 = build_function_type_list (opaque_V4SI_type_node,
8757 opaque_V4SI_type_node, opaque_V4SI_type_node,
8758 integer_type_node, NULL_TREE);
8759 tree int_ftype_int_opaque_opaque
8760 = build_function_type_list (integer_type_node,
8761 integer_type_node, opaque_V4SI_type_node,
8762 opaque_V4SI_type_node, NULL_TREE);
8763 tree int_ftype_int_v4si_v4si
8764 = build_function_type_list (integer_type_node,
8765 integer_type_node, V4SI_type_node,
8766 V4SI_type_node, NULL_TREE);
8767 tree v4sf_ftype_pcfloat
8768 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8769 tree void_ftype_pfloat_v4sf
8770 = build_function_type_list (void_type_node,
8771 pfloat_type_node, V4SF_type_node, NULL_TREE);
8772 tree v4si_ftype_pcint
8773 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8774 tree void_ftype_pint_v4si
8775 = build_function_type_list (void_type_node,
8776 pint_type_node, V4SI_type_node, NULL_TREE);
8777 tree v8hi_ftype_pcshort
8778 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8779 tree void_ftype_pshort_v8hi
8780 = build_function_type_list (void_type_node,
8781 pshort_type_node, V8HI_type_node, NULL_TREE);
8782 tree v16qi_ftype_pcchar
8783 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8784 tree void_ftype_pchar_v16qi
8785 = build_function_type_list (void_type_node,
8786 pchar_type_node, V16QI_type_node, NULL_TREE);
8787 tree void_ftype_v4si
8788 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8789 tree v8hi_ftype_void
8790 = build_function_type (V8HI_type_node, void_list_node);
8791 tree void_ftype_void
8792 = build_function_type (void_type_node, void_list_node);
8794 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8796 tree opaque_ftype_long_pcvoid
8797 = build_function_type_list (opaque_V4SI_type_node,
8798 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8799 tree v16qi_ftype_long_pcvoid
8800 = build_function_type_list (V16QI_type_node,
8801 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8802 tree v8hi_ftype_long_pcvoid
8803 = build_function_type_list (V8HI_type_node,
8804 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8805 tree v4si_ftype_long_pcvoid
8806 = build_function_type_list (V4SI_type_node,
8807 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8809 tree void_ftype_opaque_long_pvoid
8810 = build_function_type_list (void_type_node,
8811 opaque_V4SI_type_node, long_integer_type_node,
8812 pvoid_type_node, NULL_TREE);
8813 tree void_ftype_v4si_long_pvoid
8814 = build_function_type_list (void_type_node,
8815 V4SI_type_node, long_integer_type_node,
8816 pvoid_type_node, NULL_TREE);
8817 tree void_ftype_v16qi_long_pvoid
8818 = build_function_type_list (void_type_node,
8819 V16QI_type_node, long_integer_type_node,
8820 pvoid_type_node, NULL_TREE);
8821 tree void_ftype_v8hi_long_pvoid
8822 = build_function_type_list (void_type_node,
8823 V8HI_type_node, long_integer_type_node,
8824 pvoid_type_node, NULL_TREE);
8825 tree int_ftype_int_v8hi_v8hi
8826 = build_function_type_list (integer_type_node,
8827 integer_type_node, V8HI_type_node,
8828 V8HI_type_node, NULL_TREE);
8829 tree int_ftype_int_v16qi_v16qi
8830 = build_function_type_list (integer_type_node,
8831 integer_type_node, V16QI_type_node,
8832 V16QI_type_node, NULL_TREE);
8833 tree int_ftype_int_v4sf_v4sf
8834 = build_function_type_list (integer_type_node,
8835 integer_type_node, V4SF_type_node,
8836 V4SF_type_node, NULL_TREE);
8837 tree v4si_ftype_v4si
8838 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8839 tree v8hi_ftype_v8hi
8840 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8841 tree v16qi_ftype_v16qi
8842 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8843 tree v4sf_ftype_v4sf
8844 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8845 tree void_ftype_pcvoid_int_int
8846 = build_function_type_list (void_type_node,
8847 pcvoid_type_node, integer_type_node,
8848 integer_type_node, NULL_TREE);
8850 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8851 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8852 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8853 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8854 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8855 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8856 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8857 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8858 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8859 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8860 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8861 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8862 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8863 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8864 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8865 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8866 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8867 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8868 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8869 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8870 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8871 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8872 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8873 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8874 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8875 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8876 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8877 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8878 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8879 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8880 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8881 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8882 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8883 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8884 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8885 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8886 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8887 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8888 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8889 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8890 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8891 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8892 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8893 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8894 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8895 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8897 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8899 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8900 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8901 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8902 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8903 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8904 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8905 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8906 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8907 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8908 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8910 /* Add the DST variants. */
8911 d = (struct builtin_description *) bdesc_dst;
8912 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8913 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8915 /* Initialize the predicates. */
8916 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8917 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8919 enum machine_mode mode1;
8921 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8922 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8927 mode1 = insn_data[dp->icode].operand[1].mode;
8932 type = int_ftype_int_opaque_opaque;
8935 type = int_ftype_int_v4si_v4si;
8938 type = int_ftype_int_v8hi_v8hi;
8941 type = int_ftype_int_v16qi_v16qi;
8944 type = int_ftype_int_v4sf_v4sf;
8950 def_builtin (dp->mask, dp->name, type, dp->code);
8953 /* Initialize the abs* operators. */
8954 d = (struct builtin_description *) bdesc_abs;
8955 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8957 enum machine_mode mode0;
8960 mode0 = insn_data[d->icode].operand[0].mode;
8965 type = v4si_ftype_v4si;
8968 type = v8hi_ftype_v8hi;
8971 type = v16qi_ftype_v16qi;
8974 type = v4sf_ftype_v4sf;
8980 def_builtin (d->mask, d->name, type, d->code);
8987 /* Initialize target builtin that implements
8988 targetm.vectorize.builtin_mask_for_load. */
8990 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
8991 v16qi_ftype_long_pcvoid,
8992 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8993 BUILT_IN_MD, NULL, NULL_TREE);
8994 TREE_READONLY (decl) = 1;
8995 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8996 altivec_builtin_mask_for_load = decl;
8999 /* Access to the vec_init patterns. */
9000 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
9001 integer_type_node, integer_type_node,
9002 integer_type_node, NULL_TREE);
9003 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
9004 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
9006 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
9007 short_integer_type_node,
9008 short_integer_type_node,
9009 short_integer_type_node,
9010 short_integer_type_node,
9011 short_integer_type_node,
9012 short_integer_type_node,
9013 short_integer_type_node, NULL_TREE);
9014 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
9015 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
9017 ftype = build_function_type_list (V16QI_type_node, char_type_node,
9018 char_type_node, char_type_node,
9019 char_type_node, char_type_node,
9020 char_type_node, char_type_node,
9021 char_type_node, char_type_node,
9022 char_type_node, char_type_node,
9023 char_type_node, char_type_node,
9024 char_type_node, char_type_node,
9025 char_type_node, NULL_TREE);
9026 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
9027 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
9029 ftype = build_function_type_list (V4SF_type_node, float_type_node,
9030 float_type_node, float_type_node,
9031 float_type_node, NULL_TREE);
9032 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9033 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9035 /* Access to the vec_set patterns. */
9036 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9038 integer_type_node, NULL_TREE);
9039 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9040 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9042 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9044 integer_type_node, NULL_TREE);
9045 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9046 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9048 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9050 integer_type_node, NULL_TREE);
9051 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9052 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9054 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9056 integer_type_node, NULL_TREE);
9057 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9058 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9060 /* Access to the vec_extract patterns. */
9061 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9062 integer_type_node, NULL_TREE);
9063 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9064 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9066 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9067 integer_type_node, NULL_TREE);
9068 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9069 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9071 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9072 integer_type_node, NULL_TREE);
9073 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9074 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9076 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9077 integer_type_node, NULL_TREE);
9078 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9079 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9083 rs6000_common_init_builtins (void)
9085 struct builtin_description *d;
9088 tree v4sf_ftype_v4sf_v4sf_v16qi
9089 = build_function_type_list (V4SF_type_node,
9090 V4SF_type_node, V4SF_type_node,
9091 V16QI_type_node, NULL_TREE);
9092 tree v4si_ftype_v4si_v4si_v16qi
9093 = build_function_type_list (V4SI_type_node,
9094 V4SI_type_node, V4SI_type_node,
9095 V16QI_type_node, NULL_TREE);
9096 tree v8hi_ftype_v8hi_v8hi_v16qi
9097 = build_function_type_list (V8HI_type_node,
9098 V8HI_type_node, V8HI_type_node,
9099 V16QI_type_node, NULL_TREE);
9100 tree v16qi_ftype_v16qi_v16qi_v16qi
9101 = build_function_type_list (V16QI_type_node,
9102 V16QI_type_node, V16QI_type_node,
9103 V16QI_type_node, NULL_TREE);
9105 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9107 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9108 tree v16qi_ftype_int
9109 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9110 tree v8hi_ftype_v16qi
9111 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9112 tree v4sf_ftype_v4sf
9113 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9115 tree v2si_ftype_v2si_v2si
9116 = build_function_type_list (opaque_V2SI_type_node,
9117 opaque_V2SI_type_node,
9118 opaque_V2SI_type_node, NULL_TREE);
9120 tree v2sf_ftype_v2sf_v2sf
9121 = build_function_type_list (opaque_V2SF_type_node,
9122 opaque_V2SF_type_node,
9123 opaque_V2SF_type_node, NULL_TREE);
9125 tree v2si_ftype_int_int
9126 = build_function_type_list (opaque_V2SI_type_node,
9127 integer_type_node, integer_type_node,
9130 tree opaque_ftype_opaque
9131 = build_function_type_list (opaque_V4SI_type_node,
9132 opaque_V4SI_type_node, NULL_TREE);
9134 tree v2si_ftype_v2si
9135 = build_function_type_list (opaque_V2SI_type_node,
9136 opaque_V2SI_type_node, NULL_TREE);
9138 tree v2sf_ftype_v2sf
9139 = build_function_type_list (opaque_V2SF_type_node,
9140 opaque_V2SF_type_node, NULL_TREE);
9142 tree v2sf_ftype_v2si
9143 = build_function_type_list (opaque_V2SF_type_node,
9144 opaque_V2SI_type_node, NULL_TREE);
9146 tree v2si_ftype_v2sf
9147 = build_function_type_list (opaque_V2SI_type_node,
9148 opaque_V2SF_type_node, NULL_TREE);
9150 tree v2si_ftype_v2si_char
9151 = build_function_type_list (opaque_V2SI_type_node,
9152 opaque_V2SI_type_node,
9153 char_type_node, NULL_TREE);
9155 tree v2si_ftype_int_char
9156 = build_function_type_list (opaque_V2SI_type_node,
9157 integer_type_node, char_type_node, NULL_TREE);
9159 tree v2si_ftype_char
9160 = build_function_type_list (opaque_V2SI_type_node,
9161 char_type_node, NULL_TREE);
9163 tree int_ftype_int_int
9164 = build_function_type_list (integer_type_node,
9165 integer_type_node, integer_type_node,
9168 tree opaque_ftype_opaque_opaque
9169 = build_function_type_list (opaque_V4SI_type_node,
9170 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
9171 tree v4si_ftype_v4si_v4si
9172 = build_function_type_list (V4SI_type_node,
9173 V4SI_type_node, V4SI_type_node, NULL_TREE);
9174 tree v4sf_ftype_v4si_int
9175 = build_function_type_list (V4SF_type_node,
9176 V4SI_type_node, integer_type_node, NULL_TREE);
9177 tree v4si_ftype_v4sf_int
9178 = build_function_type_list (V4SI_type_node,
9179 V4SF_type_node, integer_type_node, NULL_TREE);
9180 tree v4si_ftype_v4si_int
9181 = build_function_type_list (V4SI_type_node,
9182 V4SI_type_node, integer_type_node, NULL_TREE);
9183 tree v8hi_ftype_v8hi_int
9184 = build_function_type_list (V8HI_type_node,
9185 V8HI_type_node, integer_type_node, NULL_TREE);
9186 tree v16qi_ftype_v16qi_int
9187 = build_function_type_list (V16QI_type_node,
9188 V16QI_type_node, integer_type_node, NULL_TREE);
9189 tree v16qi_ftype_v16qi_v16qi_int
9190 = build_function_type_list (V16QI_type_node,
9191 V16QI_type_node, V16QI_type_node,
9192 integer_type_node, NULL_TREE);
9193 tree v8hi_ftype_v8hi_v8hi_int
9194 = build_function_type_list (V8HI_type_node,
9195 V8HI_type_node, V8HI_type_node,
9196 integer_type_node, NULL_TREE);
9197 tree v4si_ftype_v4si_v4si_int
9198 = build_function_type_list (V4SI_type_node,
9199 V4SI_type_node, V4SI_type_node,
9200 integer_type_node, NULL_TREE);
9201 tree v4sf_ftype_v4sf_v4sf_int
9202 = build_function_type_list (V4SF_type_node,
9203 V4SF_type_node, V4SF_type_node,
9204 integer_type_node, NULL_TREE);
9205 tree v4sf_ftype_v4sf_v4sf
9206 = build_function_type_list (V4SF_type_node,
9207 V4SF_type_node, V4SF_type_node, NULL_TREE);
9208 tree opaque_ftype_opaque_opaque_opaque
9209 = build_function_type_list (opaque_V4SI_type_node,
9210 opaque_V4SI_type_node, opaque_V4SI_type_node,
9211 opaque_V4SI_type_node, NULL_TREE);
9212 tree v4sf_ftype_v4sf_v4sf_v4si
9213 = build_function_type_list (V4SF_type_node,
9214 V4SF_type_node, V4SF_type_node,
9215 V4SI_type_node, NULL_TREE);
9216 tree v4sf_ftype_v4sf_v4sf_v4sf
9217 = build_function_type_list (V4SF_type_node,
9218 V4SF_type_node, V4SF_type_node,
9219 V4SF_type_node, NULL_TREE);
9220 tree v4si_ftype_v4si_v4si_v4si
9221 = build_function_type_list (V4SI_type_node,
9222 V4SI_type_node, V4SI_type_node,
9223 V4SI_type_node, NULL_TREE);
9224 tree v8hi_ftype_v8hi_v8hi
9225 = build_function_type_list (V8HI_type_node,
9226 V8HI_type_node, V8HI_type_node, NULL_TREE);
9227 tree v8hi_ftype_v8hi_v8hi_v8hi
9228 = build_function_type_list (V8HI_type_node,
9229 V8HI_type_node, V8HI_type_node,
9230 V8HI_type_node, NULL_TREE);
9231 tree v4si_ftype_v8hi_v8hi_v4si
9232 = build_function_type_list (V4SI_type_node,
9233 V8HI_type_node, V8HI_type_node,
9234 V4SI_type_node, NULL_TREE);
9235 tree v4si_ftype_v16qi_v16qi_v4si
9236 = build_function_type_list (V4SI_type_node,
9237 V16QI_type_node, V16QI_type_node,
9238 V4SI_type_node, NULL_TREE);
9239 tree v16qi_ftype_v16qi_v16qi
9240 = build_function_type_list (V16QI_type_node,
9241 V16QI_type_node, V16QI_type_node, NULL_TREE);
9242 tree v4si_ftype_v4sf_v4sf
9243 = build_function_type_list (V4SI_type_node,
9244 V4SF_type_node, V4SF_type_node, NULL_TREE);
9245 tree v8hi_ftype_v16qi_v16qi
9246 = build_function_type_list (V8HI_type_node,
9247 V16QI_type_node, V16QI_type_node, NULL_TREE);
9248 tree v4si_ftype_v8hi_v8hi
9249 = build_function_type_list (V4SI_type_node,
9250 V8HI_type_node, V8HI_type_node, NULL_TREE);
9251 tree v8hi_ftype_v4si_v4si
9252 = build_function_type_list (V8HI_type_node,
9253 V4SI_type_node, V4SI_type_node, NULL_TREE);
9254 tree v16qi_ftype_v8hi_v8hi
9255 = build_function_type_list (V16QI_type_node,
9256 V8HI_type_node, V8HI_type_node, NULL_TREE);
9257 tree v4si_ftype_v16qi_v4si
9258 = build_function_type_list (V4SI_type_node,
9259 V16QI_type_node, V4SI_type_node, NULL_TREE);
9260 tree v4si_ftype_v16qi_v16qi
9261 = build_function_type_list (V4SI_type_node,
9262 V16QI_type_node, V16QI_type_node, NULL_TREE);
9263 tree v4si_ftype_v8hi_v4si
9264 = build_function_type_list (V4SI_type_node,
9265 V8HI_type_node, V4SI_type_node, NULL_TREE);
9266 tree v4si_ftype_v8hi
9267 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
9268 tree int_ftype_v4si_v4si
9269 = build_function_type_list (integer_type_node,
9270 V4SI_type_node, V4SI_type_node, NULL_TREE);
9271 tree int_ftype_v4sf_v4sf
9272 = build_function_type_list (integer_type_node,
9273 V4SF_type_node, V4SF_type_node, NULL_TREE);
9274 tree int_ftype_v16qi_v16qi
9275 = build_function_type_list (integer_type_node,
9276 V16QI_type_node, V16QI_type_node, NULL_TREE);
9277 tree int_ftype_v8hi_v8hi
9278 = build_function_type_list (integer_type_node,
9279 V8HI_type_node, V8HI_type_node, NULL_TREE);
9281 /* Add the simple ternary operators. */
9282 d = (struct builtin_description *) bdesc_3arg;
9283 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9285 enum machine_mode mode0, mode1, mode2, mode3;
9287 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9288 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9299 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9302 mode0 = insn_data[d->icode].operand[0].mode;
9303 mode1 = insn_data[d->icode].operand[1].mode;
9304 mode2 = insn_data[d->icode].operand[2].mode;
9305 mode3 = insn_data[d->icode].operand[3].mode;
9308 /* When all four are of the same mode. */
9309 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
9314 type = opaque_ftype_opaque_opaque_opaque;
9317 type = v4si_ftype_v4si_v4si_v4si;
9320 type = v4sf_ftype_v4sf_v4sf_v4sf;
9323 type = v8hi_ftype_v8hi_v8hi_v8hi;
9326 type = v16qi_ftype_v16qi_v16qi_v16qi;
9332 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
9337 type = v4si_ftype_v4si_v4si_v16qi;
9340 type = v4sf_ftype_v4sf_v4sf_v16qi;
9343 type = v8hi_ftype_v8hi_v8hi_v16qi;
9346 type = v16qi_ftype_v16qi_v16qi_v16qi;
9352 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
9353 && mode3 == V4SImode)
9354 type = v4si_ftype_v16qi_v16qi_v4si;
9355 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
9356 && mode3 == V4SImode)
9357 type = v4si_ftype_v8hi_v8hi_v4si;
9358 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
9359 && mode3 == V4SImode)
9360 type = v4sf_ftype_v4sf_v4sf_v4si;
9362 /* vchar, vchar, vchar, 4-bit literal. */
9363 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
9365 type = v16qi_ftype_v16qi_v16qi_int;
9367 /* vshort, vshort, vshort, 4-bit literal. */
9368 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
9370 type = v8hi_ftype_v8hi_v8hi_int;
9372 /* vint, vint, vint, 4-bit literal. */
9373 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9375 type = v4si_ftype_v4si_v4si_int;
9377 /* vfloat, vfloat, vfloat, 4-bit literal. */
9378 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9380 type = v4sf_ftype_v4sf_v4sf_int;
9385 def_builtin (d->mask, d->name, type, d->code);
9388 /* Add the simple binary operators. */
9389 d = (struct builtin_description *) bdesc_2arg;
9390 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9392 enum machine_mode mode0, mode1, mode2;
9394 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9395 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9405 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9408 mode0 = insn_data[d->icode].operand[0].mode;
9409 mode1 = insn_data[d->icode].operand[1].mode;
9410 mode2 = insn_data[d->icode].operand[2].mode;
9413 /* When all three operands are of the same mode. */
9414 if (mode0 == mode1 && mode1 == mode2)
9419 type = opaque_ftype_opaque_opaque;
9422 type = v4sf_ftype_v4sf_v4sf;
9425 type = v4si_ftype_v4si_v4si;
9428 type = v16qi_ftype_v16qi_v16qi;
9431 type = v8hi_ftype_v8hi_v8hi;
9434 type = v2si_ftype_v2si_v2si;
9437 type = v2sf_ftype_v2sf_v2sf;
9440 type = int_ftype_int_int;
9447 /* A few other combos we really don't want to do manually. */
9449 /* vint, vfloat, vfloat. */
9450 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9451 type = v4si_ftype_v4sf_v4sf;
9453 /* vshort, vchar, vchar. */
9454 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9455 type = v8hi_ftype_v16qi_v16qi;
9457 /* vint, vshort, vshort. */
9458 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9459 type = v4si_ftype_v8hi_v8hi;
9461 /* vshort, vint, vint. */
9462 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9463 type = v8hi_ftype_v4si_v4si;
9465 /* vchar, vshort, vshort. */
9466 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9467 type = v16qi_ftype_v8hi_v8hi;
9469 /* vint, vchar, vint. */
9470 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9471 type = v4si_ftype_v16qi_v4si;
9473 /* vint, vchar, vchar. */
9474 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9475 type = v4si_ftype_v16qi_v16qi;
9477 /* vint, vshort, vint. */
9478 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9479 type = v4si_ftype_v8hi_v4si;
9481 /* vint, vint, 5-bit literal. */
9482 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9483 type = v4si_ftype_v4si_int;
9485 /* vshort, vshort, 5-bit literal. */
9486 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9487 type = v8hi_ftype_v8hi_int;
9489 /* vchar, vchar, 5-bit literal. */
9490 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9491 type = v16qi_ftype_v16qi_int;
9493 /* vfloat, vint, 5-bit literal. */
9494 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9495 type = v4sf_ftype_v4si_int;
9497 /* vint, vfloat, 5-bit literal. */
9498 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9499 type = v4si_ftype_v4sf_int;
9501 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9502 type = v2si_ftype_int_int;
9504 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9505 type = v2si_ftype_v2si_char;
9507 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9508 type = v2si_ftype_int_char;
9513 gcc_assert (mode0 == SImode);
9517 type = int_ftype_v4si_v4si;
9520 type = int_ftype_v4sf_v4sf;
9523 type = int_ftype_v16qi_v16qi;
9526 type = int_ftype_v8hi_v8hi;
9533 def_builtin (d->mask, d->name, type, d->code);
9536 /* Add the simple unary operators. */
9537 d = (struct builtin_description *) bdesc_1arg;
9538 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9540 enum machine_mode mode0, mode1;
9542 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9543 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9552 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9555 mode0 = insn_data[d->icode].operand[0].mode;
9556 mode1 = insn_data[d->icode].operand[1].mode;
9559 if (mode0 == V4SImode && mode1 == QImode)
9560 type = v4si_ftype_int;
9561 else if (mode0 == V8HImode && mode1 == QImode)
9562 type = v8hi_ftype_int;
9563 else if (mode0 == V16QImode && mode1 == QImode)
9564 type = v16qi_ftype_int;
9565 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9566 type = opaque_ftype_opaque;
9567 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9568 type = v4sf_ftype_v4sf;
9569 else if (mode0 == V8HImode && mode1 == V16QImode)
9570 type = v8hi_ftype_v16qi;
9571 else if (mode0 == V4SImode && mode1 == V8HImode)
9572 type = v4si_ftype_v8hi;
9573 else if (mode0 == V2SImode && mode1 == V2SImode)
9574 type = v2si_ftype_v2si;
9575 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9576 type = v2sf_ftype_v2sf;
9577 else if (mode0 == V2SFmode && mode1 == V2SImode)
9578 type = v2sf_ftype_v2si;
9579 else if (mode0 == V2SImode && mode1 == V2SFmode)
9580 type = v2si_ftype_v2sf;
9581 else if (mode0 == V2SImode && mode1 == QImode)
9582 type = v2si_ftype_char;
9586 def_builtin (d->mask, d->name, type, d->code);
9591 rs6000_init_libfuncs (void)
9593 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9594 && !TARGET_POWER2 && !TARGET_POWERPC)
9596 /* AIX library routines for float->int conversion. */
9597 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9598 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9599 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9600 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9603 if (!TARGET_IEEEQUAD)
9604 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9605 if (!TARGET_XL_COMPAT)
9607 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9608 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9609 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9610 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9612 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
9614 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
9615 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
9616 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
9617 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
9618 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
9619 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
9620 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
9622 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
9623 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
9624 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
9625 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
9626 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
9627 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
9628 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
9629 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
9632 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
9633 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
9637 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9638 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9639 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9640 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9644 /* 32-bit SVR4 quad floating point routines. */
9646 set_optab_libfunc (add_optab, TFmode, "_q_add");
9647 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9648 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9649 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9650 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9651 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9652 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9654 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9655 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9656 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9657 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9658 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9659 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9661 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9662 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9663 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9664 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9665 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9666 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9667 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9668 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9673 /* Expand a block clear operation, and return 1 if successful. Return 0
9674 if we should let the compiler generate normal code.
9676 operands[0] is the destination
9677 operands[1] is the length
9678 operands[3] is the alignment */
9681 expand_block_clear (rtx operands[])
9683 rtx orig_dest = operands[0];
9684 rtx bytes_rtx = operands[1];
9685 rtx align_rtx = operands[3];
9686 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9687 HOST_WIDE_INT align;
9688 HOST_WIDE_INT bytes;
9693 /* If this is not a fixed size move, just call memcpy */
9697 /* This must be a fixed size alignment */
9698 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9699 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9701 /* Anything to clear? */
9702 bytes = INTVAL (bytes_rtx);
9706 /* Use the builtin memset after a point, to avoid huge code bloat.
9707 When optimize_size, avoid any significant code bloat; calling
9708 memset is about 4 instructions, so allow for one instruction to
9709 load zero and three to do clearing. */
9710 if (TARGET_ALTIVEC && align >= 128)
9712 else if (TARGET_POWERPC64 && align >= 32)
9717 if (optimize_size && bytes > 3 * clear_step)
9719 if (! optimize_size && bytes > 8 * clear_step)
9722 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9724 enum machine_mode mode = BLKmode;
9727 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9732 else if (bytes >= 8 && TARGET_POWERPC64
9733 /* 64-bit loads and stores require word-aligned
9735 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9740 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9741 { /* move 4 bytes */
9745 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9746 { /* move 2 bytes */
9750 else /* move 1 byte at a time */
9756 dest = adjust_address (orig_dest, mode, offset);
9758 emit_move_insn (dest, CONST0_RTX (mode));
9765 /* Expand a block move operation, and return 1 if successful. Return 0
9766 if we should let the compiler generate normal code.
9768 operands[0] is the destination
9769 operands[1] is the source
9770 operands[2] is the length
9771 operands[3] is the alignment */
9773 #define MAX_MOVE_REG 4
9776 expand_block_move (rtx operands[])
9778 rtx orig_dest = operands[0];
9779 rtx orig_src = operands[1];
9780 rtx bytes_rtx = operands[2];
9781 rtx align_rtx = operands[3];
9782 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9787 rtx stores[MAX_MOVE_REG];
9790 /* If this is not a fixed size move, just call memcpy */
9794 /* This must be a fixed size alignment */
9795 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9796 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9798 /* Anything to move? */
9799 bytes = INTVAL (bytes_rtx);
9803 /* store_one_arg depends on expand_block_move to handle at least the size of
9804 reg_parm_stack_space. */
9805 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9808 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9811 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9812 rtx (*mov) (rtx, rtx);
9814 enum machine_mode mode = BLKmode;
9817 /* Altivec first, since it will be faster than a string move
9818 when it applies, and usually not significantly larger. */
9819 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9823 gen_func.mov = gen_movv4si;
9825 else if (TARGET_STRING
9826 && bytes > 24 /* move up to 32 bytes at a time */
9834 && ! fixed_regs[12])
9836 move_bytes = (bytes > 32) ? 32 : bytes;
9837 gen_func.movmemsi = gen_movmemsi_8reg;
9839 else if (TARGET_STRING
9840 && bytes > 16 /* move up to 24 bytes at a time */
9846 && ! fixed_regs[10])
9848 move_bytes = (bytes > 24) ? 24 : bytes;
9849 gen_func.movmemsi = gen_movmemsi_6reg;
9851 else if (TARGET_STRING
9852 && bytes > 8 /* move up to 16 bytes at a time */
9858 move_bytes = (bytes > 16) ? 16 : bytes;
9859 gen_func.movmemsi = gen_movmemsi_4reg;
9861 else if (bytes >= 8 && TARGET_POWERPC64
9862 /* 64-bit loads and stores require word-aligned
9864 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9868 gen_func.mov = gen_movdi;
9870 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9871 { /* move up to 8 bytes at a time */
9872 move_bytes = (bytes > 8) ? 8 : bytes;
9873 gen_func.movmemsi = gen_movmemsi_2reg;
9875 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9876 { /* move 4 bytes */
9879 gen_func.mov = gen_movsi;
9881 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9882 { /* move 2 bytes */
9885 gen_func.mov = gen_movhi;
9887 else if (TARGET_STRING && bytes > 1)
9888 { /* move up to 4 bytes at a time */
9889 move_bytes = (bytes > 4) ? 4 : bytes;
9890 gen_func.movmemsi = gen_movmemsi_1reg;
9892 else /* move 1 byte at a time */
9896 gen_func.mov = gen_movqi;
9899 src = adjust_address (orig_src, mode, offset);
9900 dest = adjust_address (orig_dest, mode, offset);
9902 if (mode != BLKmode)
9904 rtx tmp_reg = gen_reg_rtx (mode);
9906 emit_insn ((*gen_func.mov) (tmp_reg, src));
9907 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9910 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9913 for (i = 0; i < num_reg; i++)
9914 emit_insn (stores[i]);
9918 if (mode == BLKmode)
9920 /* Move the address into scratch registers. The movmemsi
9921 patterns require zero offset. */
9922 if (!REG_P (XEXP (src, 0)))
9924 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9925 src = replace_equiv_address (src, src_reg);
9927 set_mem_size (src, GEN_INT (move_bytes));
9929 if (!REG_P (XEXP (dest, 0)))
9931 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9932 dest = replace_equiv_address (dest, dest_reg);
9934 set_mem_size (dest, GEN_INT (move_bytes));
9936 emit_insn ((*gen_func.movmemsi) (dest, src,
9937 GEN_INT (move_bytes & 31),
9946 /* Return a string to perform a load_multiple operation.
9947 operands[0] is the vector.
9948 operands[1] is the source address.
9949 operands[2] is the first destination register. */
9952 rs6000_output_load_multiple (rtx operands[3])
9954 /* We have to handle the case where the pseudo used to contain the address
9955 is assigned to one of the output registers. */
9957 int words = XVECLEN (operands[0], 0);
9960 if (XVECLEN (operands[0], 0) == 1)
9961 return "{l|lwz} %2,0(%1)";
9963 for (i = 0; i < words; i++)
9964 if (refers_to_regno_p (REGNO (operands[2]) + i,
9965 REGNO (operands[2]) + i + 1, operands[1], 0))
9969 xop[0] = GEN_INT (4 * (words-1));
9970 xop[1] = operands[1];
9971 xop[2] = operands[2];
9972 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9977 xop[0] = GEN_INT (4 * (words-1));
9978 xop[1] = operands[1];
9979 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9980 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9985 for (j = 0; j < words; j++)
9988 xop[0] = GEN_INT (j * 4);
9989 xop[1] = operands[1];
9990 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9991 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9993 xop[0] = GEN_INT (i * 4);
9994 xop[1] = operands[1];
9995 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
10000 return "{lsi|lswi} %2,%1,%N0";
10004 /* A validation routine: say whether CODE, a condition code, and MODE
10005 match. The other alternatives either don't make sense or should
10006 never be generated. */
10009 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
10011 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
10012 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
10013 && GET_MODE_CLASS (mode) == MODE_CC);
10015 /* These don't make sense. */
10016 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
10017 || mode != CCUNSmode);
10019 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
10020 || mode == CCUNSmode);
10022 gcc_assert (mode == CCFPmode
10023 || (code != ORDERED && code != UNORDERED
10024 && code != UNEQ && code != LTGT
10025 && code != UNGT && code != UNLT
10026 && code != UNGE && code != UNLE));
10028 /* These should never be generated except for
10029 flag_finite_math_only. */
10030 gcc_assert (mode != CCFPmode
10031 || flag_finite_math_only
10032 || (code != LE && code != GE
10033 && code != UNEQ && code != LTGT
10034 && code != UNGT && code != UNLT));
10036 /* These are invalid; the information is not there. */
10037 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10041 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10042 mask required to convert the result of a rotate insn into a shift
10043 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10046 includes_lshift_p (rtx shiftop, rtx andop)
10048 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10050 shift_mask <<= INTVAL (shiftop);
10052 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10055 /* Similar, but for right shift. */
10058 includes_rshift_p (rtx shiftop, rtx andop)
10060 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10062 shift_mask >>= INTVAL (shiftop);
10064 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10067 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10068 to perform a left shift. It must have exactly SHIFTOP least
10069 significant 0's, then one or more 1's, then zero or more 0's. */
10072 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10074 if (GET_CODE (andop) == CONST_INT)
10076 HOST_WIDE_INT c, lsb, shift_mask;
10078 c = INTVAL (andop);
10079 if (c == 0 || c == ~0)
10083 shift_mask <<= INTVAL (shiftop);
10085 /* Find the least significant one bit. */
10088 /* It must coincide with the LSB of the shift mask. */
10089 if (-lsb != shift_mask)
10092 /* Invert to look for the next transition (if any). */
10095 /* Remove the low group of ones (originally low group of zeros). */
10098 /* Again find the lsb, and check we have all 1's above. */
10102 else if (GET_CODE (andop) == CONST_DOUBLE
10103 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10105 HOST_WIDE_INT low, high, lsb;
10106 HOST_WIDE_INT shift_mask_low, shift_mask_high;
10108 low = CONST_DOUBLE_LOW (andop);
10109 if (HOST_BITS_PER_WIDE_INT < 64)
10110 high = CONST_DOUBLE_HIGH (andop);
10112 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
10113 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
10116 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10118 shift_mask_high = ~0;
10119 if (INTVAL (shiftop) > 32)
10120 shift_mask_high <<= INTVAL (shiftop) - 32;
10122 lsb = high & -high;
10124 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
10130 lsb = high & -high;
10131 return high == -lsb;
10134 shift_mask_low = ~0;
10135 shift_mask_low <<= INTVAL (shiftop);
10139 if (-lsb != shift_mask_low)
10142 if (HOST_BITS_PER_WIDE_INT < 64)
10147 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10149 lsb = high & -high;
10150 return high == -lsb;
10154 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
10160 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10161 to perform a left shift. It must have SHIFTOP or more least
10162 significant 0's, with the remainder of the word 1's. */
10165 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
10167 if (GET_CODE (andop) == CONST_INT)
10169 HOST_WIDE_INT c, lsb, shift_mask;
10172 shift_mask <<= INTVAL (shiftop);
10173 c = INTVAL (andop);
10175 /* Find the least significant one bit. */
10178 /* It must be covered by the shift mask.
10179 This test also rejects c == 0. */
10180 if ((lsb & shift_mask) == 0)
10183 /* Check we have all 1's above the transition, and reject all 1's. */
10184 return c == -lsb && lsb != 1;
10186 else if (GET_CODE (andop) == CONST_DOUBLE
10187 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10189 HOST_WIDE_INT low, lsb, shift_mask_low;
10191 low = CONST_DOUBLE_LOW (andop);
10193 if (HOST_BITS_PER_WIDE_INT < 64)
10195 HOST_WIDE_INT high, shift_mask_high;
10197 high = CONST_DOUBLE_HIGH (andop);
10201 shift_mask_high = ~0;
10202 if (INTVAL (shiftop) > 32)
10203 shift_mask_high <<= INTVAL (shiftop) - 32;
10205 lsb = high & -high;
10207 if ((lsb & shift_mask_high) == 0)
10210 return high == -lsb;
10216 shift_mask_low = ~0;
10217 shift_mask_low <<= INTVAL (shiftop);
10221 if ((lsb & shift_mask_low) == 0)
10224 return low == -lsb && lsb != 1;
10230 /* Return 1 if operands will generate a valid arguments to rlwimi
10231 instruction for insert with right shift in 64-bit mode. The mask may
10232 not start on the first bit or stop on the last bit because wrap-around
10233 effects of instruction do not correspond to semantics of RTL insn. */
10236 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10238 if (INTVAL (startop) > 32
10239 && INTVAL (startop) < 64
10240 && INTVAL (sizeop) > 1
10241 && INTVAL (sizeop) + INTVAL (startop) < 64
10242 && INTVAL (shiftop) > 0
10243 && INTVAL (sizeop) + INTVAL (shiftop) < 32
10244 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10250 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10251 for lfq and stfq insns iff the registers are hard registers. */
10254 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10256 /* We might have been passed a SUBREG. */
10257 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10260 /* We might have been passed non floating point registers. */
10261 if (!FP_REGNO_P (REGNO (reg1))
10262 || !FP_REGNO_P (REGNO (reg2)))
10265 return (REGNO (reg1) == REGNO (reg2) - 1);
10268 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10269 addr1 and addr2 must be in consecutive memory locations
10270 (addr2 == addr1 + 8). */
10273 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10276 unsigned int reg1, reg2;
10277 int offset1, offset2;
10279 /* The mems cannot be volatile. */
10280 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10283 addr1 = XEXP (mem1, 0);
10284 addr2 = XEXP (mem2, 0);
10286 /* Extract an offset (if used) from the first addr. */
10287 if (GET_CODE (addr1) == PLUS)
10289 /* If not a REG, return zero. */
10290 if (GET_CODE (XEXP (addr1, 0)) != REG)
10294 reg1 = REGNO (XEXP (addr1, 0));
10295 /* The offset must be constant! */
10296 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10298 offset1 = INTVAL (XEXP (addr1, 1));
10301 else if (GET_CODE (addr1) != REG)
10305 reg1 = REGNO (addr1);
10306 /* This was a simple (mem (reg)) expression. Offset is 0. */
10310 /* And now for the second addr. */
10311 if (GET_CODE (addr2) == PLUS)
10313 /* If not a REG, return zero. */
10314 if (GET_CODE (XEXP (addr2, 0)) != REG)
10318 reg2 = REGNO (XEXP (addr2, 0));
10319 /* The offset must be constant. */
10320 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10322 offset2 = INTVAL (XEXP (addr2, 1));
10325 else if (GET_CODE (addr2) != REG)
10329 reg2 = REGNO (addr2);
10330 /* This was a simple (mem (reg)) expression. Offset is 0. */
10334 /* Both of these must have the same base register. */
10338 /* The offset for the second addr must be 8 more than the first addr. */
10339 if (offset2 != offset1 + 8)
10342 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10347 /* Return the register class of a scratch register needed to copy IN into
10348 or out of a register in CLASS in MODE. If it can be done directly,
10349 NO_REGS is returned. */
10352 rs6000_secondary_reload_class (enum reg_class class,
10353 enum machine_mode mode ATTRIBUTE_UNUSED,
10358 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10360 && MACHOPIC_INDIRECT
10364 /* We cannot copy a symbolic operand directly into anything
10365 other than BASE_REGS for TARGET_ELF. So indicate that a
10366 register from BASE_REGS is needed as an intermediate
10369 On Darwin, pic addresses require a load from memory, which
10370 needs a base register. */
10371 if (class != BASE_REGS
10372 && (GET_CODE (in) == SYMBOL_REF
10373 || GET_CODE (in) == HIGH
10374 || GET_CODE (in) == LABEL_REF
10375 || GET_CODE (in) == CONST))
10379 if (GET_CODE (in) == REG)
10381 regno = REGNO (in);
10382 if (regno >= FIRST_PSEUDO_REGISTER)
10384 regno = true_regnum (in);
10385 if (regno >= FIRST_PSEUDO_REGISTER)
10389 else if (GET_CODE (in) == SUBREG)
10391 regno = true_regnum (in);
10392 if (regno >= FIRST_PSEUDO_REGISTER)
10398 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10400 if (class == GENERAL_REGS || class == BASE_REGS
10401 || (regno >= 0 && INT_REGNO_P (regno)))
10404 /* Constants, memory, and FP registers can go into FP registers. */
10405 if ((regno == -1 || FP_REGNO_P (regno))
10406 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10409 /* Memory, and AltiVec registers can go into AltiVec registers. */
10410 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10411 && class == ALTIVEC_REGS)
10414 /* We can copy among the CR registers. */
10415 if ((class == CR_REGS || class == CR0_REGS)
10416 && regno >= 0 && CR_REGNO_P (regno))
10419 /* Otherwise, we need GENERAL_REGS. */
10420 return GENERAL_REGS;
10423 /* Given a comparison operation, return the bit number in CCR to test. We
10424 know this is a valid comparison.
10426 SCC_P is 1 if this is for an scc. That means that %D will have been
10427 used instead of %C, so the bits will be in different places.
10429 Return -1 if OP isn't a valid comparison for some reason. */
10432 ccr_bit (rtx op, int scc_p)
10434 enum rtx_code code = GET_CODE (op);
10435 enum machine_mode cc_mode;
10440 if (!COMPARISON_P (op))
10443 reg = XEXP (op, 0);
10445 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10447 cc_mode = GET_MODE (reg);
10448 cc_regnum = REGNO (reg);
10449 base_bit = 4 * (cc_regnum - CR0_REGNO);
10451 validate_condition_mode (code, cc_mode);
10453 /* When generating a sCOND operation, only positive conditions are
10456 || code == EQ || code == GT || code == LT || code == UNORDERED
10457 || code == GTU || code == LTU);
10462 return scc_p ? base_bit + 3 : base_bit + 2;
10464 return base_bit + 2;
10465 case GT: case GTU: case UNLE:
10466 return base_bit + 1;
10467 case LT: case LTU: case UNGE:
10469 case ORDERED: case UNORDERED:
10470 return base_bit + 3;
10473 /* If scc, we will have done a cror to put the bit in the
10474 unordered position. So test that bit. For integer, this is ! LT
10475 unless this is an scc insn. */
10476 return scc_p ? base_bit + 3 : base_bit;
10479 return scc_p ? base_bit + 3 : base_bit + 1;
10482 gcc_unreachable ();
10486 /* Return the GOT register. */
10489 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10491 /* The second flow pass currently (June 1999) can't update
10492 regs_ever_live without disturbing other parts of the compiler, so
10493 update it here to make the prolog/epilogue code happy. */
10494 if (!can_create_pseudo_p ()
10495 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
10496 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
10498 current_function_uses_pic_offset_table = 1;
10500 return pic_offset_table_rtx;
10503 /* Function to init struct machine_function.
10504 This will be called, via a pointer variable,
10505 from push_function_context. */
10507 static struct machine_function *
10508 rs6000_init_machine_status (void)
10510 return ggc_alloc_cleared (sizeof (machine_function));
10513 /* These macros test for integers and extract the low-order bits. */
10515 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10516 && GET_MODE (X) == VOIDmode)
10518 #define INT_LOWPART(X) \
10519 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10522 extract_MB (rtx op)
10525 unsigned long val = INT_LOWPART (op);
10527 /* If the high bit is zero, the value is the first 1 bit we find
10529 if ((val & 0x80000000) == 0)
10531 gcc_assert (val & 0xffffffff);
10534 while (((val <<= 1) & 0x80000000) == 0)
10539 /* If the high bit is set and the low bit is not, or the mask is all
10540 1's, the value is zero. */
10541 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10544 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10547 while (((val >>= 1) & 1) != 0)
10554 extract_ME (rtx op)
10557 unsigned long val = INT_LOWPART (op);
10559 /* If the low bit is zero, the value is the first 1 bit we find from
10561 if ((val & 1) == 0)
10563 gcc_assert (val & 0xffffffff);
10566 while (((val >>= 1) & 1) == 0)
10572 /* If the low bit is set and the high bit is not, or the mask is all
10573 1's, the value is 31. */
10574 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10577 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10580 while (((val <<= 1) & 0x80000000) != 0)
10586 /* Locate some local-dynamic symbol still in use by this function
10587 so that we can print its name in some tls_ld pattern. */
10589 static const char *
10590 rs6000_get_some_local_dynamic_name (void)
10594 if (cfun->machine->some_ld_name)
10595 return cfun->machine->some_ld_name;
10597 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10599 && for_each_rtx (&PATTERN (insn),
10600 rs6000_get_some_local_dynamic_name_1, 0))
10601 return cfun->machine->some_ld_name;
10603 gcc_unreachable ();
10606 /* Helper function for rs6000_get_some_local_dynamic_name. */
10609 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10613 if (GET_CODE (x) == SYMBOL_REF)
10615 const char *str = XSTR (x, 0);
10616 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10618 cfun->machine->some_ld_name = str;
10626 /* Write out a function code label. */
10629 rs6000_output_function_entry (FILE *file, const char *fname)
10631 if (fname[0] != '.')
10633 switch (DEFAULT_ABI)
10636 gcc_unreachable ();
10642 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10651 RS6000_OUTPUT_BASENAME (file, fname);
10653 assemble_name (file, fname);
10656 /* Print an operand. Recognize special options, documented below. */
10659 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10660 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10662 #define SMALL_DATA_RELOC "sda21"
10663 #define SMALL_DATA_REG 0
10667 print_operand (FILE *file, rtx x, int code)
10671 unsigned HOST_WIDE_INT uval;
10676 /* Write out an instruction after the call which may be replaced
10677 with glue code by the loader. This depends on the AIX version. */
10678 asm_fprintf (file, RS6000_CALL_GLUE);
10681 /* %a is output_address. */
10684 /* If X is a constant integer whose low-order 5 bits are zero,
10685 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10686 in the AIX assembler where "sri" with a zero shift count
10687 writes a trash instruction. */
10688 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10695 /* If constant, low-order 16 bits of constant, unsigned.
10696 Otherwise, write normally. */
10698 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10700 print_operand (file, x, 0);
10704 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10705 for 64-bit mask direction. */
10706 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10709 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10713 /* X is a CR register. Print the number of the GT bit of the CR. */
10714 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10715 output_operand_lossage ("invalid %%E value");
10717 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10721 /* Like 'J' but get to the GT bit only. */
10722 gcc_assert (GET_CODE (x) == REG);
10724 /* Bit 1 is GT bit. */
10725 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
10727 /* Add one for shift count in rlinm for scc. */
10728 fprintf (file, "%d", i + 1);
10732 /* X is a CR register. Print the number of the EQ bit of the CR */
10733 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10734 output_operand_lossage ("invalid %%E value");
10736 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10740 /* X is a CR register. Print the shift count needed to move it
10741 to the high-order four bits. */
10742 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10743 output_operand_lossage ("invalid %%f value");
10745 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10749 /* Similar, but print the count for the rotate in the opposite
10751 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10752 output_operand_lossage ("invalid %%F value");
10754 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10758 /* X is a constant integer. If it is negative, print "m",
10759 otherwise print "z". This is to make an aze or ame insn. */
10760 if (GET_CODE (x) != CONST_INT)
10761 output_operand_lossage ("invalid %%G value");
10762 else if (INTVAL (x) >= 0)
10769 /* If constant, output low-order five bits. Otherwise, write
10772 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10774 print_operand (file, x, 0);
10778 /* If constant, output low-order six bits. Otherwise, write
10781 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10783 print_operand (file, x, 0);
10787 /* Print `i' if this is a constant, else nothing. */
10793 /* Write the bit number in CCR for jump. */
10794 i = ccr_bit (x, 0);
10796 output_operand_lossage ("invalid %%j code");
10798 fprintf (file, "%d", i);
10802 /* Similar, but add one for shift count in rlinm for scc and pass
10803 scc flag to `ccr_bit'. */
10804 i = ccr_bit (x, 1);
10806 output_operand_lossage ("invalid %%J code");
10808 /* If we want bit 31, write a shift count of zero, not 32. */
10809 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10813 /* X must be a constant. Write the 1's complement of the
10816 output_operand_lossage ("invalid %%k value");
10818 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10822 /* X must be a symbolic constant on ELF. Write an
10823 expression suitable for an 'addi' that adds in the low 16
10824 bits of the MEM. */
10825 if (GET_CODE (x) != CONST)
10827 print_operand_address (file, x);
10828 fputs ("@l", file);
10832 if (GET_CODE (XEXP (x, 0)) != PLUS
10833 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10834 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10835 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10836 output_operand_lossage ("invalid %%K value");
10837 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10838 fputs ("@l", file);
10839 /* For GNU as, there must be a non-alphanumeric character
10840 between 'l' and the number. The '-' is added by
10841 print_operand() already. */
10842 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10844 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10848 /* %l is output_asm_label. */
10851 /* Write second word of DImode or DFmode reference. Works on register
10852 or non-indexed memory only. */
10853 if (GET_CODE (x) == REG)
10854 fputs (reg_names[REGNO (x) + 1], file);
10855 else if (GET_CODE (x) == MEM)
10857 /* Handle possible auto-increment. Since it is pre-increment and
10858 we have already done it, we can just use an offset of word. */
10859 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10860 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10861 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10863 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
10864 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10867 output_address (XEXP (adjust_address_nv (x, SImode,
10871 if (small_data_operand (x, GET_MODE (x)))
10872 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10873 reg_names[SMALL_DATA_REG]);
10878 /* MB value for a mask operand. */
10879 if (! mask_operand (x, SImode))
10880 output_operand_lossage ("invalid %%m value");
10882 fprintf (file, "%d", extract_MB (x));
10886 /* ME value for a mask operand. */
10887 if (! mask_operand (x, SImode))
10888 output_operand_lossage ("invalid %%M value");
10890 fprintf (file, "%d", extract_ME (x));
10893 /* %n outputs the negative of its operand. */
10896 /* Write the number of elements in the vector times 4. */
10897 if (GET_CODE (x) != PARALLEL)
10898 output_operand_lossage ("invalid %%N value");
10900 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10904 /* Similar, but subtract 1 first. */
10905 if (GET_CODE (x) != PARALLEL)
10906 output_operand_lossage ("invalid %%O value");
10908 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10912 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10914 || INT_LOWPART (x) < 0
10915 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10916 output_operand_lossage ("invalid %%p value");
10918 fprintf (file, "%d", i);
10922 /* The operand must be an indirect memory reference. The result
10923 is the register name. */
10924 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10925 || REGNO (XEXP (x, 0)) >= 32)
10926 output_operand_lossage ("invalid %%P value");
10928 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10932 /* This outputs the logical code corresponding to a boolean
10933 expression. The expression may have one or both operands
10934 negated (if one, only the first one). For condition register
10935 logical operations, it will also treat the negated
10936 CR codes as NOTs, but not handle NOTs of them. */
10938 const char *const *t = 0;
10940 enum rtx_code code = GET_CODE (x);
10941 static const char * const tbl[3][3] = {
10942 { "and", "andc", "nor" },
10943 { "or", "orc", "nand" },
10944 { "xor", "eqv", "xor" } };
10948 else if (code == IOR)
10950 else if (code == XOR)
10953 output_operand_lossage ("invalid %%q value");
10955 if (GET_CODE (XEXP (x, 0)) != NOT)
10959 if (GET_CODE (XEXP (x, 1)) == NOT)
10977 /* X is a CR register. Print the mask for `mtcrf'. */
10978 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10979 output_operand_lossage ("invalid %%R value");
10981 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10985 /* Low 5 bits of 32 - value */
10987 output_operand_lossage ("invalid %%s value");
10989 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10993 /* PowerPC64 mask position. All 0's is excluded.
10994 CONST_INT 32-bit mask is considered sign-extended so any
10995 transition must occur within the CONST_INT, not on the boundary. */
10996 if (! mask64_operand (x, DImode))
10997 output_operand_lossage ("invalid %%S value");
10999 uval = INT_LOWPART (x);
11001 if (uval & 1) /* Clear Left */
11003 #if HOST_BITS_PER_WIDE_INT > 64
11004 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11008 else /* Clear Right */
11011 #if HOST_BITS_PER_WIDE_INT > 64
11012 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11018 gcc_assert (i >= 0);
11019 fprintf (file, "%d", i);
11023 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
11024 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
11026 /* Bit 3 is OV bit. */
11027 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
11029 /* If we want bit 31, write a shift count of zero, not 32. */
11030 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11034 /* Print the symbolic name of a branch target register. */
11035 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
11036 && REGNO (x) != COUNT_REGISTER_REGNUM))
11037 output_operand_lossage ("invalid %%T value");
11038 else if (REGNO (x) == LINK_REGISTER_REGNUM)
11039 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
11041 fputs ("ctr", file);
11045 /* High-order 16 bits of constant for use in unsigned operand. */
11047 output_operand_lossage ("invalid %%u value");
11049 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11050 (INT_LOWPART (x) >> 16) & 0xffff);
11054 /* High-order 16 bits of constant for use in signed operand. */
11056 output_operand_lossage ("invalid %%v value");
11058 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11059 (INT_LOWPART (x) >> 16) & 0xffff);
11063 /* Print `u' if this has an auto-increment or auto-decrement. */
11064 if (GET_CODE (x) == MEM
11065 && (GET_CODE (XEXP (x, 0)) == PRE_INC
11066 || GET_CODE (XEXP (x, 0)) == PRE_DEC
11067 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
11072 /* Print the trap code for this operand. */
11073 switch (GET_CODE (x))
11076 fputs ("eq", file); /* 4 */
11079 fputs ("ne", file); /* 24 */
11082 fputs ("lt", file); /* 16 */
11085 fputs ("le", file); /* 20 */
11088 fputs ("gt", file); /* 8 */
11091 fputs ("ge", file); /* 12 */
11094 fputs ("llt", file); /* 2 */
11097 fputs ("lle", file); /* 6 */
11100 fputs ("lgt", file); /* 1 */
11103 fputs ("lge", file); /* 5 */
11106 gcc_unreachable ();
11111 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
11114 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
11115 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
11117 print_operand (file, x, 0);
11121 /* MB value for a PowerPC64 rldic operand. */
11122 val = (GET_CODE (x) == CONST_INT
11123 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
11128 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
11129 if ((val <<= 1) < 0)
11132 #if HOST_BITS_PER_WIDE_INT == 32
11133 if (GET_CODE (x) == CONST_INT && i >= 0)
11134 i += 32; /* zero-extend high-part was all 0's */
11135 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
11137 val = CONST_DOUBLE_LOW (x);
11143 for ( ; i < 64; i++)
11144 if ((val <<= 1) < 0)
11149 fprintf (file, "%d", i + 1);
11153 if (GET_CODE (x) == MEM
11154 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
11155 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
11156 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
11161 /* Like 'L', for third word of TImode */
11162 if (GET_CODE (x) == REG)
11163 fputs (reg_names[REGNO (x) + 2], file);
11164 else if (GET_CODE (x) == MEM)
11166 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11167 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11168 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11169 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11170 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11172 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
11173 if (small_data_operand (x, GET_MODE (x)))
11174 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11175 reg_names[SMALL_DATA_REG]);
11180 /* X is a SYMBOL_REF. Write out the name preceded by a
11181 period and without any trailing data in brackets. Used for function
11182 names. If we are configured for System V (or the embedded ABI) on
11183 the PowerPC, do not emit the period, since those systems do not use
11184 TOCs and the like. */
11185 gcc_assert (GET_CODE (x) == SYMBOL_REF);
11187 /* Mark the decl as referenced so that cgraph will output the
11189 if (SYMBOL_REF_DECL (x))
11190 mark_decl_referenced (SYMBOL_REF_DECL (x));
11192 /* For macho, check to see if we need a stub. */
11195 const char *name = XSTR (x, 0);
11197 if (MACHOPIC_INDIRECT
11198 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
11199 name = machopic_indirection_name (x, /*stub_p=*/true);
11201 assemble_name (file, name);
11203 else if (!DOT_SYMBOLS)
11204 assemble_name (file, XSTR (x, 0));
11206 rs6000_output_function_entry (file, XSTR (x, 0));
11210 /* Like 'L', for last word of TImode. */
11211 if (GET_CODE (x) == REG)
11212 fputs (reg_names[REGNO (x) + 3], file);
11213 else if (GET_CODE (x) == MEM)
11215 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11216 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11217 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11218 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11219 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11221 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
11222 if (small_data_operand (x, GET_MODE (x)))
11223 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11224 reg_names[SMALL_DATA_REG]);
11228 /* Print AltiVec or SPE memory operand. */
11233 gcc_assert (GET_CODE (x) == MEM);
11237 /* Ugly hack because %y is overloaded. */
11238 if ((TARGET_SPE || TARGET_E500_DOUBLE)
11239 && (GET_MODE_SIZE (GET_MODE (x)) == 8
11240 || GET_MODE (x) == TFmode
11241 || GET_MODE (x) == TImode))
11243 /* Handle [reg]. */
11244 if (GET_CODE (tmp) == REG)
11246 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11249 /* Handle [reg+UIMM]. */
11250 else if (GET_CODE (tmp) == PLUS &&
11251 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11255 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
11257 x = INTVAL (XEXP (tmp, 1));
11258 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11262 /* Fall through. Must be [reg+reg]. */
11265 && GET_CODE (tmp) == AND
11266 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11267 && INTVAL (XEXP (tmp, 1)) == -16)
11268 tmp = XEXP (tmp, 0);
11269 if (GET_CODE (tmp) == REG)
11270 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11273 gcc_assert (GET_CODE (tmp) == PLUS
11274 && REG_P (XEXP (tmp, 0))
11275 && REG_P (XEXP (tmp, 1)));
11277 if (REGNO (XEXP (tmp, 0)) == 0)
11278 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11279 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11281 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11282 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11288 if (GET_CODE (x) == REG)
11289 fprintf (file, "%s", reg_names[REGNO (x)]);
11290 else if (GET_CODE (x) == MEM)
11292 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11293 know the width from the mode. */
11294 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11295 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11296 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11297 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11298 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11299 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11300 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11301 output_address (XEXP (XEXP (x, 0), 1));
11303 output_address (XEXP (x, 0));
11306 output_addr_const (file, x);
11310 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11314 output_operand_lossage ("invalid %%xn code");
11318 /* Print the address of an operand. */
11321 print_operand_address (FILE *file, rtx x)
11323 if (GET_CODE (x) == REG)
11324 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11325 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11326 || GET_CODE (x) == LABEL_REF)
11328 output_addr_const (file, x);
11329 if (small_data_operand (x, GET_MODE (x)))
11330 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11331 reg_names[SMALL_DATA_REG]);
11333 gcc_assert (!TARGET_TOC);
11335 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11337 gcc_assert (REG_P (XEXP (x, 0)));
11338 if (REGNO (XEXP (x, 0)) == 0)
11339 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11340 reg_names[ REGNO (XEXP (x, 0)) ]);
11342 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11343 reg_names[ REGNO (XEXP (x, 1)) ]);
11345 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11346 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11347 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11349 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11350 && CONSTANT_P (XEXP (x, 1)))
11352 output_addr_const (file, XEXP (x, 1));
11353 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11357 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11358 && CONSTANT_P (XEXP (x, 1)))
11360 fprintf (file, "lo16(");
11361 output_addr_const (file, XEXP (x, 1));
11362 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11365 else if (legitimate_constant_pool_address_p (x))
11367 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11369 rtx contains_minus = XEXP (x, 1);
11373 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11374 turn it into (sym) for output_addr_const. */
11375 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11376 contains_minus = XEXP (contains_minus, 0);
11378 minus = XEXP (contains_minus, 0);
11379 symref = XEXP (minus, 0);
11380 XEXP (contains_minus, 0) = symref;
11385 name = XSTR (symref, 0);
11386 newname = alloca (strlen (name) + sizeof ("@toc"));
11387 strcpy (newname, name);
11388 strcat (newname, "@toc");
11389 XSTR (symref, 0) = newname;
11391 output_addr_const (file, XEXP (x, 1));
11393 XSTR (symref, 0) = name;
11394 XEXP (contains_minus, 0) = minus;
11397 output_addr_const (file, XEXP (x, 1));
11399 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11402 gcc_unreachable ();
11405 /* Target hook for assembling integer objects. The PowerPC version has
11406 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11407 is defined. It also needs to handle DI-mode objects on 64-bit
11411 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11413 #ifdef RELOCATABLE_NEEDS_FIXUP
11414 /* Special handling for SI values. */
11415 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11417 static int recurse = 0;
11419 /* For -mrelocatable, we mark all addresses that need to be fixed up
11420 in the .fixup section. */
11421 if (TARGET_RELOCATABLE
11422 && in_section != toc_section
11423 && in_section != text_section
11424 && !unlikely_text_section_p (in_section)
11426 && GET_CODE (x) != CONST_INT
11427 && GET_CODE (x) != CONST_DOUBLE
11433 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11435 ASM_OUTPUT_LABEL (asm_out_file, buf);
11436 fprintf (asm_out_file, "\t.long\t(");
11437 output_addr_const (asm_out_file, x);
11438 fprintf (asm_out_file, ")@fixup\n");
11439 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11440 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11441 fprintf (asm_out_file, "\t.long\t");
11442 assemble_name (asm_out_file, buf);
11443 fprintf (asm_out_file, "\n\t.previous\n");
11447 /* Remove initial .'s to turn a -mcall-aixdesc function
11448 address into the address of the descriptor, not the function
11450 else if (GET_CODE (x) == SYMBOL_REF
11451 && XSTR (x, 0)[0] == '.'
11452 && DEFAULT_ABI == ABI_AIX)
11454 const char *name = XSTR (x, 0);
11455 while (*name == '.')
11458 fprintf (asm_out_file, "\t.long\t%s\n", name);
11462 #endif /* RELOCATABLE_NEEDS_FIXUP */
11463 return default_assemble_integer (x, size, aligned_p);
11466 #ifdef HAVE_GAS_HIDDEN
11467 /* Emit an assembler directive to set symbol visibility for DECL to
11468 VISIBILITY_TYPE. */
11471 rs6000_assemble_visibility (tree decl, int vis)
11473 /* Functions need to have their entry point symbol visibility set as
11474 well as their descriptor symbol visibility. */
11475 if (DEFAULT_ABI == ABI_AIX
11477 && TREE_CODE (decl) == FUNCTION_DECL)
11479 static const char * const visibility_types[] = {
11480 NULL, "internal", "hidden", "protected"
11483 const char *name, *type;
11485 name = ((* targetm.strip_name_encoding)
11486 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11487 type = visibility_types[vis];
11489 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11490 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11493 default_assemble_visibility (decl, vis);
11498 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11500 /* Reversal of FP compares takes care -- an ordered compare
11501 becomes an unordered compare and vice versa. */
11502 if (mode == CCFPmode
11503 && (!flag_finite_math_only
11504 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11505 || code == UNEQ || code == LTGT))
11506 return reverse_condition_maybe_unordered (code);
11508 return reverse_condition (code);
11511 /* Generate a compare for CODE. Return a brand-new rtx that
11512 represents the result of the compare. */
11515 rs6000_generate_compare (enum rtx_code code)
11517 enum machine_mode comp_mode;
11518 rtx compare_result;
11520 if (rs6000_compare_fp_p)
11521 comp_mode = CCFPmode;
11522 else if (code == GTU || code == LTU
11523 || code == GEU || code == LEU)
11524 comp_mode = CCUNSmode;
11525 else if ((code == EQ || code == NE)
11526 && GET_CODE (rs6000_compare_op0) == SUBREG
11527 && GET_CODE (rs6000_compare_op1) == SUBREG
11528 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11529 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11530 /* These are unsigned values, perhaps there will be a later
11531 ordering compare that can be shared with this one.
11532 Unfortunately we cannot detect the signedness of the operands
11533 for non-subregs. */
11534 comp_mode = CCUNSmode;
11536 comp_mode = CCmode;
11538 /* First, the compare. */
11539 compare_result = gen_reg_rtx (comp_mode);
11541 /* E500 FP compare instructions on the GPRs. Yuck! */
11542 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
11543 && rs6000_compare_fp_p)
11545 rtx cmp, or_result, compare_result2;
11546 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11548 if (op_mode == VOIDmode)
11549 op_mode = GET_MODE (rs6000_compare_op1);
11551 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
11552 This explains the following mess. */
11556 case EQ: case UNEQ: case NE: case LTGT:
11560 cmp = flag_unsafe_math_optimizations
11561 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11562 rs6000_compare_op1)
11563 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11564 rs6000_compare_op1);
11568 cmp = flag_unsafe_math_optimizations
11569 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11570 rs6000_compare_op1)
11571 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11572 rs6000_compare_op1);
11576 cmp = flag_unsafe_math_optimizations
11577 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
11578 rs6000_compare_op1)
11579 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
11580 rs6000_compare_op1);
11584 gcc_unreachable ();
11588 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11592 cmp = flag_unsafe_math_optimizations
11593 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11594 rs6000_compare_op1)
11595 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11596 rs6000_compare_op1);
11600 cmp = flag_unsafe_math_optimizations
11601 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11602 rs6000_compare_op1)
11603 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11604 rs6000_compare_op1);
11608 cmp = flag_unsafe_math_optimizations
11609 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
11610 rs6000_compare_op1)
11611 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
11612 rs6000_compare_op1);
11616 gcc_unreachable ();
11620 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11624 cmp = flag_unsafe_math_optimizations
11625 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11626 rs6000_compare_op1)
11627 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11628 rs6000_compare_op1);
11632 cmp = flag_unsafe_math_optimizations
11633 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11634 rs6000_compare_op1)
11635 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11636 rs6000_compare_op1);
11640 cmp = flag_unsafe_math_optimizations
11641 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
11642 rs6000_compare_op1)
11643 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
11644 rs6000_compare_op1);
11648 gcc_unreachable ();
11652 gcc_unreachable ();
11655 /* Synthesize LE and GE from LT/GT || EQ. */
11656 if (code == LE || code == GE || code == LEU || code == GEU)
11662 case LE: code = LT; break;
11663 case GE: code = GT; break;
11664 case LEU: code = LT; break;
11665 case GEU: code = GT; break;
11666 default: gcc_unreachable ();
11669 compare_result2 = gen_reg_rtx (CCFPmode);
11675 cmp = flag_unsafe_math_optimizations
11676 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11677 rs6000_compare_op1)
11678 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11679 rs6000_compare_op1);
11683 cmp = flag_unsafe_math_optimizations
11684 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11685 rs6000_compare_op1)
11686 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11687 rs6000_compare_op1);
11691 cmp = flag_unsafe_math_optimizations
11692 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
11693 rs6000_compare_op1)
11694 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
11695 rs6000_compare_op1);
11699 gcc_unreachable ();
11703 /* OR them together. */
11704 or_result = gen_reg_rtx (CCFPmode);
11705 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11707 compare_result = or_result;
11712 if (code == NE || code == LTGT)
11722 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11723 CLOBBERs to match cmptf_internal2 pattern. */
11724 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11725 && GET_MODE (rs6000_compare_op0) == TFmode
11726 && !TARGET_IEEEQUAD
11727 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11728 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11730 gen_rtx_SET (VOIDmode,
11732 gen_rtx_COMPARE (comp_mode,
11733 rs6000_compare_op0,
11734 rs6000_compare_op1)),
11735 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11736 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11737 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11738 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11739 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11740 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11741 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11742 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11743 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11744 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11746 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11747 comp_mode = CCEQmode;
11748 compare_result = gen_reg_rtx (CCEQmode);
11750 emit_insn (gen_stack_protect_testdi (compare_result,
11751 rs6000_compare_op0, op1));
11753 emit_insn (gen_stack_protect_testsi (compare_result,
11754 rs6000_compare_op0, op1));
11757 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11758 gen_rtx_COMPARE (comp_mode,
11759 rs6000_compare_op0,
11760 rs6000_compare_op1)));
11763 /* Some kinds of FP comparisons need an OR operation;
11764 under flag_finite_math_only we don't bother. */
11765 if (rs6000_compare_fp_p
11766 && !flag_finite_math_only
11767 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
11768 && (code == LE || code == GE
11769 || code == UNEQ || code == LTGT
11770 || code == UNGT || code == UNLT))
11772 enum rtx_code or1, or2;
11773 rtx or1_rtx, or2_rtx, compare2_rtx;
11774 rtx or_result = gen_reg_rtx (CCEQmode);
11778 case LE: or1 = LT; or2 = EQ; break;
11779 case GE: or1 = GT; or2 = EQ; break;
11780 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11781 case LTGT: or1 = LT; or2 = GT; break;
11782 case UNGT: or1 = UNORDERED; or2 = GT; break;
11783 case UNLT: or1 = UNORDERED; or2 = LT; break;
11784 default: gcc_unreachable ();
11786 validate_condition_mode (or1, comp_mode);
11787 validate_condition_mode (or2, comp_mode);
11788 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11789 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11790 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11791 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11793 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11795 compare_result = or_result;
11799 validate_condition_mode (code, GET_MODE (compare_result));
11801 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11805 /* Emit the RTL for an sCOND pattern. */
11808 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11811 enum machine_mode op_mode;
11812 enum rtx_code cond_code;
11814 condition_rtx = rs6000_generate_compare (code);
11815 cond_code = GET_CODE (condition_rtx);
11817 if (rs6000_compare_fp_p
11818 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11822 PUT_MODE (condition_rtx, SImode);
11823 t = XEXP (condition_rtx, 0);
11825 gcc_assert (cond_code == NE || cond_code == EQ);
11827 if (cond_code == NE)
11828 emit_insn (gen_e500_flip_gt_bit (t, t));
11830 emit_insn (gen_move_from_CR_gt_bit (result, t));
11834 if (cond_code == NE
11835 || cond_code == GE || cond_code == LE
11836 || cond_code == GEU || cond_code == LEU
11837 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11839 rtx not_result = gen_reg_rtx (CCEQmode);
11840 rtx not_op, rev_cond_rtx;
11841 enum machine_mode cc_mode;
11843 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11845 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11846 SImode, XEXP (condition_rtx, 0), const0_rtx);
11847 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11848 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11849 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11852 op_mode = GET_MODE (rs6000_compare_op0);
11853 if (op_mode == VOIDmode)
11854 op_mode = GET_MODE (rs6000_compare_op1);
11856 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11858 PUT_MODE (condition_rtx, DImode);
11859 convert_move (result, condition_rtx, 0);
11863 PUT_MODE (condition_rtx, SImode);
11864 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11868 /* Emit a branch of kind CODE to location LOC. */
11871 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11873 rtx condition_rtx, loc_ref;
11875 condition_rtx = rs6000_generate_compare (code);
11876 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11877 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11878 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11879 loc_ref, pc_rtx)));
11882 /* Return the string to output a conditional branch to LABEL, which is
11883 the operand number of the label, or -1 if the branch is really a
11884 conditional return.
11886 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11887 condition code register and its mode specifies what kind of
11888 comparison we made.
11890 REVERSED is nonzero if we should reverse the sense of the comparison.
11892 INSN is the insn. */
11895 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11897 static char string[64];
11898 enum rtx_code code = GET_CODE (op);
11899 rtx cc_reg = XEXP (op, 0);
11900 enum machine_mode mode = GET_MODE (cc_reg);
11901 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11902 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11903 int really_reversed = reversed ^ need_longbranch;
11909 validate_condition_mode (code, mode);
11911 /* Work out which way this really branches. We could use
11912 reverse_condition_maybe_unordered here always but this
11913 makes the resulting assembler clearer. */
11914 if (really_reversed)
11916 /* Reversal of FP compares takes care -- an ordered compare
11917 becomes an unordered compare and vice versa. */
11918 if (mode == CCFPmode)
11919 code = reverse_condition_maybe_unordered (code);
11921 code = reverse_condition (code);
11924 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11926 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11931 /* Opposite of GT. */
11940 gcc_unreachable ();
11946 /* Not all of these are actually distinct opcodes, but
11947 we distinguish them for clarity of the resulting assembler. */
11948 case NE: case LTGT:
11949 ccode = "ne"; break;
11950 case EQ: case UNEQ:
11951 ccode = "eq"; break;
11953 ccode = "ge"; break;
11954 case GT: case GTU: case UNGT:
11955 ccode = "gt"; break;
11957 ccode = "le"; break;
11958 case LT: case LTU: case UNLT:
11959 ccode = "lt"; break;
11960 case UNORDERED: ccode = "un"; break;
11961 case ORDERED: ccode = "nu"; break;
11962 case UNGE: ccode = "nl"; break;
11963 case UNLE: ccode = "ng"; break;
11965 gcc_unreachable ();
11968 /* Maybe we have a guess as to how likely the branch is.
11969 The old mnemonics don't have a way to specify this information. */
11971 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11972 if (note != NULL_RTX)
11974 /* PROB is the difference from 50%. */
11975 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11977 /* Only hint for highly probable/improbable branches on newer
11978 cpus as static prediction overrides processor dynamic
11979 prediction. For older cpus we may as well always hint, but
11980 assume not taken for branches that are very close to 50% as a
11981 mispredicted taken branch is more expensive than a
11982 mispredicted not-taken branch. */
11983 if (rs6000_always_hint
11984 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
11985 && br_prob_note_reliable_p (note)))
11987 if (abs (prob) > REG_BR_PROB_BASE / 20
11988 && ((prob > 0) ^ need_longbranch))
11996 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11998 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12000 /* We need to escape any '%' characters in the reg_names string.
12001 Assume they'd only be the first character.... */
12002 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
12004 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12008 /* If the branch distance was too far, we may have to use an
12009 unconditional branch to go the distance. */
12010 if (need_longbranch)
12011 s += sprintf (s, ",$+8\n\tb %s", label);
12013 s += sprintf (s, ",%s", label);
12019 /* Return the string to flip the GT bit on a CR. */
12021 output_e500_flip_gt_bit (rtx dst, rtx src)
12023 static char string[64];
12026 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
12027 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
12030 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
12031 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
12033 sprintf (string, "crnot %d,%d", a, b);
12037 /* Return insn index for the vector compare instruction for given CODE,
12038 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
12042 get_vec_cmp_insn (enum rtx_code code,
12043 enum machine_mode dest_mode,
12044 enum machine_mode op_mode)
12046 if (!TARGET_ALTIVEC)
12047 return INSN_NOT_AVAILABLE;
12052 if (dest_mode == V16QImode && op_mode == V16QImode)
12053 return UNSPEC_VCMPEQUB;
12054 if (dest_mode == V8HImode && op_mode == V8HImode)
12055 return UNSPEC_VCMPEQUH;
12056 if (dest_mode == V4SImode && op_mode == V4SImode)
12057 return UNSPEC_VCMPEQUW;
12058 if (dest_mode == V4SImode && op_mode == V4SFmode)
12059 return UNSPEC_VCMPEQFP;
12062 if (dest_mode == V4SImode && op_mode == V4SFmode)
12063 return UNSPEC_VCMPGEFP;
12065 if (dest_mode == V16QImode && op_mode == V16QImode)
12066 return UNSPEC_VCMPGTSB;
12067 if (dest_mode == V8HImode && op_mode == V8HImode)
12068 return UNSPEC_VCMPGTSH;
12069 if (dest_mode == V4SImode && op_mode == V4SImode)
12070 return UNSPEC_VCMPGTSW;
12071 if (dest_mode == V4SImode && op_mode == V4SFmode)
12072 return UNSPEC_VCMPGTFP;
12075 if (dest_mode == V16QImode && op_mode == V16QImode)
12076 return UNSPEC_VCMPGTUB;
12077 if (dest_mode == V8HImode && op_mode == V8HImode)
12078 return UNSPEC_VCMPGTUH;
12079 if (dest_mode == V4SImode && op_mode == V4SImode)
12080 return UNSPEC_VCMPGTUW;
12085 return INSN_NOT_AVAILABLE;
12088 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
12089 DMODE is expected destination mode. This is a recursive function. */
12092 rs6000_emit_vector_compare (enum rtx_code rcode,
12094 enum machine_mode dmode)
12098 enum machine_mode dest_mode;
12099 enum machine_mode op_mode = GET_MODE (op1);
12101 gcc_assert (TARGET_ALTIVEC);
12102 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
12104 /* Floating point vector compare instructions uses destination V4SImode.
12105 Move destination to appropriate mode later. */
12106 if (dmode == V4SFmode)
12107 dest_mode = V4SImode;
12111 mask = gen_reg_rtx (dest_mode);
12112 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12114 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
12116 bool swap_operands = false;
12117 bool try_again = false;
12122 swap_operands = true;
12127 swap_operands = true;
12135 /* Invert condition and try again.
12136 e.g., A != B becomes ~(A==B). */
12138 enum rtx_code rev_code;
12139 enum insn_code nor_code;
12142 rev_code = reverse_condition_maybe_unordered (rcode);
12143 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
12146 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
12147 gcc_assert (nor_code != CODE_FOR_nothing);
12148 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
12150 if (dmode != dest_mode)
12152 rtx temp = gen_reg_rtx (dest_mode);
12153 convert_move (temp, mask, 0);
12163 /* Try GT/GTU/LT/LTU OR EQ */
12166 enum insn_code ior_code;
12167 enum rtx_code new_code;
12188 gcc_unreachable ();
12191 c_rtx = rs6000_emit_vector_compare (new_code,
12192 op0, op1, dest_mode);
12193 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
12196 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
12197 gcc_assert (ior_code != CODE_FOR_nothing);
12198 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
12199 if (dmode != dest_mode)
12201 rtx temp = gen_reg_rtx (dest_mode);
12202 convert_move (temp, mask, 0);
12209 gcc_unreachable ();
12214 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12215 /* You only get two chances. */
12216 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
12228 emit_insn (gen_rtx_SET (VOIDmode, mask,
12229 gen_rtx_UNSPEC (dest_mode,
12230 gen_rtvec (2, op0, op1),
12232 if (dmode != dest_mode)
12234 rtx temp = gen_reg_rtx (dest_mode);
12235 convert_move (temp, mask, 0);
12241 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
12242 valid insn doesn exist for given mode. */
12245 get_vsel_insn (enum machine_mode mode)
12250 return UNSPEC_VSEL4SI;
12253 return UNSPEC_VSEL4SF;
12256 return UNSPEC_VSEL8HI;
12259 return UNSPEC_VSEL16QI;
12262 return INSN_NOT_AVAILABLE;
12265 return INSN_NOT_AVAILABLE;
12268 /* Emit vector select insn where DEST is destination using
12269 operands OP1, OP2 and MASK. */
12272 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
12275 enum machine_mode dest_mode = GET_MODE (dest);
12276 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
12278 temp = gen_reg_rtx (dest_mode);
12280 /* For each vector element, select op1 when mask is 1 otherwise
12282 t = gen_rtx_SET (VOIDmode, temp,
12283 gen_rtx_UNSPEC (dest_mode,
12284 gen_rtvec (3, op2, op1, mask),
12287 emit_move_insn (dest, temp);
12291 /* Emit vector conditional expression.
12292 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12293 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12296 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
12297 rtx cond, rtx cc_op0, rtx cc_op1)
12299 enum machine_mode dest_mode = GET_MODE (dest);
12300 enum rtx_code rcode = GET_CODE (cond);
12303 if (!TARGET_ALTIVEC)
12306 /* Get the vector mask for the given relational operations. */
12307 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
12309 rs6000_emit_vector_select (dest, op1, op2, mask);
12314 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12315 operands of the last comparison is nonzero/true, FALSE_COND if it
12316 is zero/false. Return 0 if the hardware has no such operation. */
12319 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12321 enum rtx_code code = GET_CODE (op);
12322 rtx op0 = rs6000_compare_op0;
12323 rtx op1 = rs6000_compare_op1;
12324 REAL_VALUE_TYPE c1;
12325 enum machine_mode compare_mode = GET_MODE (op0);
12326 enum machine_mode result_mode = GET_MODE (dest);
12328 bool is_against_zero;
12330 /* These modes should always match. */
12331 if (GET_MODE (op1) != compare_mode
12332 /* In the isel case however, we can use a compare immediate, so
12333 op1 may be a small constant. */
12334 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12336 if (GET_MODE (true_cond) != result_mode)
12338 if (GET_MODE (false_cond) != result_mode)
12341 /* First, work out if the hardware can do this at all, or
12342 if it's too slow.... */
12343 if (! rs6000_compare_fp_p)
12346 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12349 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
12350 && SCALAR_FLOAT_MODE_P (compare_mode))
12353 is_against_zero = op1 == CONST0_RTX (compare_mode);
12355 /* A floating-point subtract might overflow, underflow, or produce
12356 an inexact result, thus changing the floating-point flags, so it
12357 can't be generated if we care about that. It's safe if one side
12358 of the construct is zero, since then no subtract will be
12360 if (SCALAR_FLOAT_MODE_P (compare_mode)
12361 && flag_trapping_math && ! is_against_zero)
12364 /* Eliminate half of the comparisons by switching operands, this
12365 makes the remaining code simpler. */
12366 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12367 || code == LTGT || code == LT || code == UNLE)
12369 code = reverse_condition_maybe_unordered (code);
12371 true_cond = false_cond;
12375 /* UNEQ and LTGT take four instructions for a comparison with zero,
12376 it'll probably be faster to use a branch here too. */
12377 if (code == UNEQ && HONOR_NANS (compare_mode))
12380 if (GET_CODE (op1) == CONST_DOUBLE)
12381 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12383 /* We're going to try to implement comparisons by performing
12384 a subtract, then comparing against zero. Unfortunately,
12385 Inf - Inf is NaN which is not zero, and so if we don't
12386 know that the operand is finite and the comparison
12387 would treat EQ different to UNORDERED, we can't do it. */
12388 if (HONOR_INFINITIES (compare_mode)
12389 && code != GT && code != UNGE
12390 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12391 /* Constructs of the form (a OP b ? a : b) are safe. */
12392 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12393 || (! rtx_equal_p (op0, true_cond)
12394 && ! rtx_equal_p (op1, true_cond))))
12397 /* At this point we know we can use fsel. */
12399 /* Reduce the comparison to a comparison against zero. */
12400 if (! is_against_zero)
12402 temp = gen_reg_rtx (compare_mode);
12403 emit_insn (gen_rtx_SET (VOIDmode, temp,
12404 gen_rtx_MINUS (compare_mode, op0, op1)));
12406 op1 = CONST0_RTX (compare_mode);
12409 /* If we don't care about NaNs we can reduce some of the comparisons
12410 down to faster ones. */
12411 if (! HONOR_NANS (compare_mode))
12417 true_cond = false_cond;
12430 /* Now, reduce everything down to a GE. */
12437 temp = gen_reg_rtx (compare_mode);
12438 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12443 temp = gen_reg_rtx (compare_mode);
12444 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12449 temp = gen_reg_rtx (compare_mode);
12450 emit_insn (gen_rtx_SET (VOIDmode, temp,
12451 gen_rtx_NEG (compare_mode,
12452 gen_rtx_ABS (compare_mode, op0))));
12457 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12458 temp = gen_reg_rtx (result_mode);
12459 emit_insn (gen_rtx_SET (VOIDmode, temp,
12460 gen_rtx_IF_THEN_ELSE (result_mode,
12461 gen_rtx_GE (VOIDmode,
12463 true_cond, false_cond)));
12464 false_cond = true_cond;
12467 temp = gen_reg_rtx (compare_mode);
12468 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12473 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12474 temp = gen_reg_rtx (result_mode);
12475 emit_insn (gen_rtx_SET (VOIDmode, temp,
12476 gen_rtx_IF_THEN_ELSE (result_mode,
12477 gen_rtx_GE (VOIDmode,
12479 true_cond, false_cond)));
12480 true_cond = false_cond;
12483 temp = gen_reg_rtx (compare_mode);
12484 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12489 gcc_unreachable ();
12492 emit_insn (gen_rtx_SET (VOIDmode, dest,
12493 gen_rtx_IF_THEN_ELSE (result_mode,
12494 gen_rtx_GE (VOIDmode,
12496 true_cond, false_cond)));
12500 /* Same as above, but for ints (isel). */
12503 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12505 rtx condition_rtx, cr;
12507 /* All isel implementations thus far are 32-bits. */
12508 if (GET_MODE (rs6000_compare_op0) != SImode)
12511 /* We still have to do the compare, because isel doesn't do a
12512 compare, it just looks at the CRx bits set by a previous compare
12514 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12515 cr = XEXP (condition_rtx, 0);
12517 if (GET_MODE (cr) == CCmode)
12518 emit_insn (gen_isel_signed (dest, condition_rtx,
12519 true_cond, false_cond, cr));
12521 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12522 true_cond, false_cond, cr));
12528 output_isel (rtx *operands)
12530 enum rtx_code code;
12532 code = GET_CODE (operands[1]);
12533 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12535 PUT_CODE (operands[1], reverse_condition (code));
12536 return "isel %0,%3,%2,%j1";
12539 return "isel %0,%2,%3,%j1";
12543 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12545 enum machine_mode mode = GET_MODE (op0);
12549 if (code == SMAX || code == SMIN)
12554 if (code == SMAX || code == UMAX)
12555 target = emit_conditional_move (dest, c, op0, op1, mode,
12556 op0, op1, mode, 0);
12558 target = emit_conditional_move (dest, c, op0, op1, mode,
12559 op1, op0, mode, 0);
12560 gcc_assert (target);
12561 if (target != dest)
12562 emit_move_insn (dest, target);
12565 /* Emit instructions to perform a load-reserved/store-conditional operation.
12566 The operation performed is an atomic
12567 (set M (CODE:MODE M OP))
12568 If not NULL, BEFORE is atomically set to M before the operation, and
12569 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12570 If SYNC_P then a memory barrier is emitted before the operation.
12571 Either OP or M may be wrapped in a NOT operation. */
12574 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12575 rtx m, rtx op, rtx before_param, rtx after_param,
12578 enum machine_mode used_mode;
12579 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12582 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12583 rtx shift = NULL_RTX;
12586 emit_insn (gen_memory_barrier ());
12588 if (GET_CODE (m) == NOT)
12589 used_m = XEXP (m, 0);
12593 /* If this is smaller than SImode, we'll have to use SImode with
12595 if (mode == QImode || mode == HImode)
12599 if (MEM_ALIGN (used_m) >= 32)
12602 if (BYTES_BIG_ENDIAN)
12603 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12605 shift = GEN_INT (ishift);
12609 rtx addrSI, aligned_addr;
12610 int shift_mask = mode == QImode ? 0x18 : 0x10;
12612 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12613 XEXP (used_m, 0)));
12614 shift = gen_reg_rtx (SImode);
12616 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12617 GEN_INT (shift_mask)));
12618 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12620 aligned_addr = expand_binop (Pmode, and_optab,
12622 GEN_INT (-4), NULL_RTX,
12623 1, OPTAB_LIB_WIDEN);
12624 used_m = change_address (used_m, SImode, aligned_addr);
12625 set_mem_align (used_m, 32);
12626 /* It's safe to keep the old alias set of USED_M, because
12627 the operation is atomic and only affects the original
12629 if (GET_CODE (m) == NOT)
12630 m = gen_rtx_NOT (SImode, used_m);
12635 if (GET_CODE (op) == NOT)
12637 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12638 oldop = gen_rtx_NOT (SImode, oldop);
12641 oldop = lowpart_subreg (SImode, op, mode);
12647 newop = expand_binop (SImode, and_optab,
12648 oldop, GEN_INT (imask), NULL_RTX,
12649 1, OPTAB_LIB_WIDEN);
12650 emit_insn (gen_ashlsi3 (newop, newop, shift));
12654 newop = expand_binop (SImode, ior_optab,
12655 oldop, GEN_INT (~imask), NULL_RTX,
12656 1, OPTAB_LIB_WIDEN);
12657 emit_insn (gen_rotlsi3 (newop, newop, shift));
12665 newop = expand_binop (SImode, and_optab,
12666 oldop, GEN_INT (imask), NULL_RTX,
12667 1, OPTAB_LIB_WIDEN);
12668 emit_insn (gen_ashlsi3 (newop, newop, shift));
12670 mask = gen_reg_rtx (SImode);
12671 emit_move_insn (mask, GEN_INT (imask));
12672 emit_insn (gen_ashlsi3 (mask, mask, shift));
12675 newop = gen_rtx_PLUS (SImode, m, newop);
12677 newop = gen_rtx_MINUS (SImode, m, newop);
12678 newop = gen_rtx_AND (SImode, newop, mask);
12679 newop = gen_rtx_IOR (SImode, newop,
12680 gen_rtx_AND (SImode,
12681 gen_rtx_NOT (SImode, mask),
12687 gcc_unreachable ();
12690 if (GET_CODE (m) == NOT)
12694 mask = gen_reg_rtx (SImode);
12695 emit_move_insn (mask, GEN_INT (imask));
12696 emit_insn (gen_ashlsi3 (mask, mask, shift));
12698 xorm = gen_rtx_XOR (SImode, used_m, mask);
12699 /* Depending on the value of 'op', the XOR or the operation might
12700 be able to be simplified away. */
12701 newop = simplify_gen_binary (code, SImode, xorm, newop);
12704 used_mode = SImode;
12705 before = gen_reg_rtx (used_mode);
12706 after = gen_reg_rtx (used_mode);
12711 before = before_param;
12712 after = after_param;
12714 if (before == NULL_RTX)
12715 before = gen_reg_rtx (used_mode);
12716 if (after == NULL_RTX)
12717 after = gen_reg_rtx (used_mode);
12720 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12721 && used_mode != mode)
12722 the_op = op; /* Computed above. */
12723 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12724 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12726 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12728 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12729 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12730 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12731 gen_rtx_UNSPEC (used_mode,
12732 gen_rtvec (1, the_op),
12734 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12736 if ((code == PLUS || code == MINUS) && used_mode != mode)
12737 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12738 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12740 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12741 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12743 /* Shift and mask the return values properly. */
12744 if (used_mode != mode && before_param)
12746 emit_insn (gen_lshrsi3 (before, before, shift));
12747 convert_move (before_param, before, 1);
12750 if (used_mode != mode && after_param)
12752 emit_insn (gen_lshrsi3 (after, after, shift));
12753 convert_move (after_param, after, 1);
12756 /* The previous sequence will end with a branch that's dependent on
12757 the conditional store, so placing an isync will ensure that no
12758 other instructions (especially, no load or store instructions)
12759 can start before the atomic operation completes. */
12761 emit_insn (gen_isync ());
12764 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12765 COND is true. Mark the jump as unlikely to be taken. */
12768 emit_unlikely_jump (rtx cond, rtx label)
12770 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12773 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12774 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12775 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12778 /* A subroutine of the atomic operation splitters. Emit a load-locked
12779 instruction in MODE. */
12782 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12784 rtx (*fn) (rtx, rtx) = NULL;
12785 if (mode == SImode)
12786 fn = gen_load_locked_si;
12787 else if (mode == DImode)
12788 fn = gen_load_locked_di;
12789 emit_insn (fn (reg, mem));
12792 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12793 instruction in MODE. */
12796 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12798 rtx (*fn) (rtx, rtx, rtx) = NULL;
12799 if (mode == SImode)
12800 fn = gen_store_conditional_si;
12801 else if (mode == DImode)
12802 fn = gen_store_conditional_di;
12804 /* Emit sync before stwcx. to address PPC405 Erratum. */
12805 if (PPC405_ERRATUM77)
12806 emit_insn (gen_memory_barrier ());
12808 emit_insn (fn (res, mem, val));
12811 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
12812 to perform. MEM is the memory on which to operate. VAL is the second
12813 operand of the binary operator. BEFORE and AFTER are optional locations to
12814 return the value of MEM either before of after the operation. SCRATCH is
12815 a scratch register. */
12818 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12819 rtx before, rtx after, rtx scratch)
12821 enum machine_mode mode = GET_MODE (mem);
12822 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12824 emit_insn (gen_memory_barrier ());
12826 label = gen_label_rtx ();
12827 emit_label (label);
12828 label = gen_rtx_LABEL_REF (VOIDmode, label);
12830 if (before == NULL_RTX)
12832 emit_load_locked (mode, before, mem);
12835 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12836 else if (code == AND)
12837 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12839 x = gen_rtx_fmt_ee (code, mode, before, val);
12841 if (after != NULL_RTX)
12842 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12843 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12845 emit_store_conditional (mode, cond, mem, scratch);
12847 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12848 emit_unlikely_jump (x, label);
12850 emit_insn (gen_isync ());
12853 /* Expand an atomic compare and swap operation. MEM is the memory on which
12854 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12855 value to be stored. SCRATCH is a scratch GPR. */
12858 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12861 enum machine_mode mode = GET_MODE (mem);
12862 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12864 emit_insn (gen_memory_barrier ());
12866 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12867 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12868 emit_label (XEXP (label1, 0));
12870 emit_load_locked (mode, retval, mem);
12872 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12873 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12875 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12876 emit_unlikely_jump (x, label2);
12878 emit_move_insn (scratch, newval);
12879 emit_store_conditional (mode, cond, mem, scratch);
12881 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12882 emit_unlikely_jump (x, label1);
12884 emit_insn (gen_isync ());
12885 emit_label (XEXP (label2, 0));
12888 /* Expand an atomic test and set operation. MEM is the memory on which
12889 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12892 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12894 enum machine_mode mode = GET_MODE (mem);
12895 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12897 emit_insn (gen_memory_barrier ());
12899 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12900 emit_label (XEXP (label, 0));
12902 emit_load_locked (mode, retval, mem);
12903 emit_move_insn (scratch, val);
12904 emit_store_conditional (mode, cond, mem, scratch);
12906 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12907 emit_unlikely_jump (x, label);
12909 emit_insn (gen_isync ());
12913 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12915 enum machine_mode mode = GET_MODE (mem);
12916 rtx addrSI, align, wdst, shift, mask;
12917 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12918 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12920 /* Shift amount for subword relative to aligned word. */
12921 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12922 shift = gen_reg_rtx (SImode);
12923 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12924 GEN_INT (shift_mask)));
12925 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12927 /* Shift and mask old value into position within word. */
12928 oldval = convert_modes (SImode, mode, oldval, 1);
12929 oldval = expand_binop (SImode, and_optab,
12930 oldval, GEN_INT (imask), NULL_RTX,
12931 1, OPTAB_LIB_WIDEN);
12932 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12934 /* Shift and mask new value into position within word. */
12935 newval = convert_modes (SImode, mode, newval, 1);
12936 newval = expand_binop (SImode, and_optab,
12937 newval, GEN_INT (imask), NULL_RTX,
12938 1, OPTAB_LIB_WIDEN);
12939 emit_insn (gen_ashlsi3 (newval, newval, shift));
12941 /* Mask for insertion. */
12942 mask = gen_reg_rtx (SImode);
12943 emit_move_insn (mask, GEN_INT (imask));
12944 emit_insn (gen_ashlsi3 (mask, mask, shift));
12946 /* Address of aligned word containing subword. */
12947 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12948 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12949 mem = change_address (mem, SImode, align);
12950 set_mem_align (mem, 32);
12951 MEM_VOLATILE_P (mem) = 1;
12953 wdst = gen_reg_rtx (SImode);
12954 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12955 oldval, newval, mem));
12957 emit_move_insn (dst, gen_lowpart (mode, wdst));
12961 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12962 rtx oldval, rtx newval, rtx mem,
12965 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12967 emit_insn (gen_memory_barrier ());
12968 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12969 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12970 emit_label (XEXP (label1, 0));
12972 emit_load_locked (SImode, scratch, mem);
12974 /* Mask subword within loaded value for comparison with oldval.
12975 Use UNSPEC_AND to avoid clobber.*/
12976 emit_insn (gen_rtx_SET (SImode, dest,
12977 gen_rtx_UNSPEC (SImode,
12978 gen_rtvec (2, scratch, mask),
12981 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12982 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12984 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12985 emit_unlikely_jump (x, label2);
12987 /* Clear subword within loaded value for insertion of new value. */
12988 emit_insn (gen_rtx_SET (SImode, scratch,
12989 gen_rtx_AND (SImode,
12990 gen_rtx_NOT (SImode, mask), scratch)));
12991 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12992 emit_store_conditional (SImode, cond, mem, scratch);
12994 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12995 emit_unlikely_jump (x, label1);
12997 emit_insn (gen_isync ());
12998 emit_label (XEXP (label2, 0));
13002 /* Emit instructions to move SRC to DST. Called by splitters for
13003 multi-register moves. It will emit at most one instruction for
13004 each register that is accessed; that is, it won't emit li/lis pairs
13005 (or equivalent for 64-bit code). One of SRC or DST must be a hard
13009 rs6000_split_multireg_move (rtx dst, rtx src)
13011 /* The register number of the first register being moved. */
13013 /* The mode that is to be moved. */
13014 enum machine_mode mode;
13015 /* The mode that the move is being done in, and its size. */
13016 enum machine_mode reg_mode;
13018 /* The number of registers that will be moved. */
13021 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
13022 mode = GET_MODE (dst);
13023 nregs = hard_regno_nregs[reg][mode];
13024 if (FP_REGNO_P (reg))
13025 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
13026 else if (ALTIVEC_REGNO_P (reg))
13027 reg_mode = V16QImode;
13028 else if (TARGET_E500_DOUBLE && mode == TFmode)
13031 reg_mode = word_mode;
13032 reg_mode_size = GET_MODE_SIZE (reg_mode);
13034 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
13036 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
13038 /* Move register range backwards, if we might have destructive
13041 for (i = nregs - 1; i >= 0; i--)
13042 emit_insn (gen_rtx_SET (VOIDmode,
13043 simplify_gen_subreg (reg_mode, dst, mode,
13044 i * reg_mode_size),
13045 simplify_gen_subreg (reg_mode, src, mode,
13046 i * reg_mode_size)));
13052 bool used_update = false;
13054 if (MEM_P (src) && INT_REGNO_P (reg))
13058 if (GET_CODE (XEXP (src, 0)) == PRE_INC
13059 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
13062 breg = XEXP (XEXP (src, 0), 0);
13063 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
13064 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
13065 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
13066 emit_insn (TARGET_32BIT
13067 ? gen_addsi3 (breg, breg, delta_rtx)
13068 : gen_adddi3 (breg, breg, delta_rtx));
13069 src = replace_equiv_address (src, breg);
13071 else if (! rs6000_offsettable_memref_p (src))
13074 basereg = gen_rtx_REG (Pmode, reg);
13075 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
13076 src = replace_equiv_address (src, basereg);
13079 breg = XEXP (src, 0);
13080 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
13081 breg = XEXP (breg, 0);
13083 /* If the base register we are using to address memory is
13084 also a destination reg, then change that register last. */
13086 && REGNO (breg) >= REGNO (dst)
13087 && REGNO (breg) < REGNO (dst) + nregs)
13088 j = REGNO (breg) - REGNO (dst);
13091 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
13095 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
13096 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
13099 breg = XEXP (XEXP (dst, 0), 0);
13100 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
13101 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
13102 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
13104 /* We have to update the breg before doing the store.
13105 Use store with update, if available. */
13109 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
13110 emit_insn (TARGET_32BIT
13111 ? (TARGET_POWERPC64
13112 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
13113 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
13114 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
13115 used_update = true;
13118 emit_insn (TARGET_32BIT
13119 ? gen_addsi3 (breg, breg, delta_rtx)
13120 : gen_adddi3 (breg, breg, delta_rtx));
13121 dst = replace_equiv_address (dst, breg);
13124 gcc_assert (rs6000_offsettable_memref_p (dst));
13127 for (i = 0; i < nregs; i++)
13129 /* Calculate index to next subword. */
13134 /* If compiler already emitted move of first word by
13135 store with update, no need to do anything. */
13136 if (j == 0 && used_update)
13139 emit_insn (gen_rtx_SET (VOIDmode,
13140 simplify_gen_subreg (reg_mode, dst, mode,
13141 j * reg_mode_size),
13142 simplify_gen_subreg (reg_mode, src, mode,
13143 j * reg_mode_size)));
13149 /* This page contains routines that are used to determine what the
13150 function prologue and epilogue code will do and write them out. */
13152 /* Return the first fixed-point register that is required to be
13153 saved. 32 if none. */
13156 first_reg_to_save (void)
13160 /* Find lowest numbered live register. */
13161 for (first_reg = 13; first_reg <= 31; first_reg++)
13162 if (df_regs_ever_live_p (first_reg)
13163 && (! call_used_regs[first_reg]
13164 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
13165 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13166 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
13167 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
13172 && current_function_uses_pic_offset_table
13173 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
13174 return RS6000_PIC_OFFSET_TABLE_REGNUM;
13180 /* Similar, for FP regs. */
13183 first_fp_reg_to_save (void)
13187 /* Find lowest numbered live register. */
13188 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
13189 if (df_regs_ever_live_p (first_reg))
13195 /* Similar, for AltiVec regs. */
13198 first_altivec_reg_to_save (void)
13202 /* Stack frame remains as is unless we are in AltiVec ABI. */
13203 if (! TARGET_ALTIVEC_ABI)
13204 return LAST_ALTIVEC_REGNO + 1;
13206 /* On Darwin, the unwind routines are compiled without
13207 TARGET_ALTIVEC, and use save_world to save/restore the
13208 altivec registers when necessary. */
13209 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13210 && ! TARGET_ALTIVEC)
13211 return FIRST_ALTIVEC_REGNO + 20;
13213 /* Find lowest numbered live register. */
13214 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
13215 if (df_regs_ever_live_p (i))
13221 /* Return a 32-bit mask of the AltiVec registers we need to set in
13222 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
13223 the 32-bit word is 0. */
13225 static unsigned int
13226 compute_vrsave_mask (void)
13228 unsigned int i, mask = 0;
13230 /* On Darwin, the unwind routines are compiled without
13231 TARGET_ALTIVEC, and use save_world to save/restore the
13232 call-saved altivec registers when necessary. */
13233 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13234 && ! TARGET_ALTIVEC)
13237 /* First, find out if we use _any_ altivec registers. */
13238 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13239 if (df_regs_ever_live_p (i))
13240 mask |= ALTIVEC_REG_BIT (i);
13245 /* Next, remove the argument registers from the set. These must
13246 be in the VRSAVE mask set by the caller, so we don't need to add
13247 them in again. More importantly, the mask we compute here is
13248 used to generate CLOBBERs in the set_vrsave insn, and we do not
13249 wish the argument registers to die. */
13250 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
13251 mask &= ~ALTIVEC_REG_BIT (i);
13253 /* Similarly, remove the return value from the set. */
13256 diddle_return_value (is_altivec_return_reg, &yes);
13258 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
13264 /* For a very restricted set of circumstances, we can cut down the
13265 size of prologues/epilogues by calling our own save/restore-the-world
13269 compute_save_world_info (rs6000_stack_t *info_ptr)
13271 info_ptr->world_save_p = 1;
13272 info_ptr->world_save_p
13273 = (WORLD_SAVE_P (info_ptr)
13274 && DEFAULT_ABI == ABI_DARWIN
13275 && ! (current_function_calls_setjmp && flag_exceptions)
13276 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
13277 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
13278 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
13279 && info_ptr->cr_save_p);
13281 /* This will not work in conjunction with sibcalls. Make sure there
13282 are none. (This check is expensive, but seldom executed.) */
13283 if (WORLD_SAVE_P (info_ptr))
13286 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
13287 if ( GET_CODE (insn) == CALL_INSN
13288 && SIBLING_CALL_P (insn))
13290 info_ptr->world_save_p = 0;
13295 if (WORLD_SAVE_P (info_ptr))
13297 /* Even if we're not touching VRsave, make sure there's room on the
13298 stack for it, if it looks like we're calling SAVE_WORLD, which
13299 will attempt to save it. */
13300 info_ptr->vrsave_size = 4;
13302 /* "Save" the VRsave register too if we're saving the world. */
13303 if (info_ptr->vrsave_mask == 0)
13304 info_ptr->vrsave_mask = compute_vrsave_mask ();
13306 /* Because the Darwin register save/restore routines only handle
13307 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13309 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
13310 && (info_ptr->first_altivec_reg_save
13311 >= FIRST_SAVED_ALTIVEC_REGNO));
13318 is_altivec_return_reg (rtx reg, void *xyes)
13320 bool *yes = (bool *) xyes;
13321 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
13326 /* Calculate the stack information for the current function. This is
13327 complicated by having two separate calling sequences, the AIX calling
13328 sequence and the V.4 calling sequence.
13330 AIX (and Darwin/Mac OS X) stack frames look like:
13332 SP----> +---------------------------------------+
13333 | back chain to caller | 0 0
13334 +---------------------------------------+
13335 | saved CR | 4 8 (8-11)
13336 +---------------------------------------+
13338 +---------------------------------------+
13339 | reserved for compilers | 12 24
13340 +---------------------------------------+
13341 | reserved for binders | 16 32
13342 +---------------------------------------+
13343 | saved TOC pointer | 20 40
13344 +---------------------------------------+
13345 | Parameter save area (P) | 24 48
13346 +---------------------------------------+
13347 | Alloca space (A) | 24+P etc.
13348 +---------------------------------------+
13349 | Local variable space (L) | 24+P+A
13350 +---------------------------------------+
13351 | Float/int conversion temporary (X) | 24+P+A+L
13352 +---------------------------------------+
13353 | Save area for AltiVec registers (W) | 24+P+A+L+X
13354 +---------------------------------------+
13355 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13356 +---------------------------------------+
13357 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13358 +---------------------------------------+
13359 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13360 +---------------------------------------+
13361 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13362 +---------------------------------------+
13363 old SP->| back chain to caller's caller |
13364 +---------------------------------------+
13366 The required alignment for AIX configurations is two words (i.e., 8
13370 V.4 stack frames look like:
13372 SP----> +---------------------------------------+
13373 | back chain to caller | 0
13374 +---------------------------------------+
13375 | caller's saved LR | 4
13376 +---------------------------------------+
13377 | Parameter save area (P) | 8
13378 +---------------------------------------+
13379 | Alloca space (A) | 8+P
13380 +---------------------------------------+
13381 | Varargs save area (V) | 8+P+A
13382 +---------------------------------------+
13383 | Local variable space (L) | 8+P+A+V
13384 +---------------------------------------+
13385 | Float/int conversion temporary (X) | 8+P+A+V+L
13386 +---------------------------------------+
13387 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13388 +---------------------------------------+
13389 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13390 +---------------------------------------+
13391 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13392 +---------------------------------------+
13393 | SPE: area for 64-bit GP registers |
13394 +---------------------------------------+
13395 | SPE alignment padding |
13396 +---------------------------------------+
13397 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13398 +---------------------------------------+
13399 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13400 +---------------------------------------+
13401 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13402 +---------------------------------------+
13403 old SP->| back chain to caller's caller |
13404 +---------------------------------------+
13406 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13407 given. (But note below and in sysv4.h that we require only 8 and
13408 may round up the size of our stack frame anyways. The historical
13409 reason is early versions of powerpc-linux which didn't properly
13410 align the stack at program startup. A happy side-effect is that
13411 -mno-eabi libraries can be used with -meabi programs.)
13413 The EABI configuration defaults to the V.4 layout. However,
13414 the stack alignment requirements may differ. If -mno-eabi is not
13415 given, the required stack alignment is 8 bytes; if -mno-eabi is
13416 given, the required alignment is 16 bytes. (But see V.4 comment
13419 #ifndef ABI_STACK_BOUNDARY
13420 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
13423 static rs6000_stack_t *
13424 rs6000_stack_info (void)
13426 static rs6000_stack_t info;
13427 rs6000_stack_t *info_ptr = &info;
13428 int reg_size = TARGET_32BIT ? 4 : 8;
13431 HOST_WIDE_INT non_fixed_size;
13433 memset (&info, 0, sizeof (info));
13437 /* Cache value so we don't rescan instruction chain over and over. */
13438 if (cfun->machine->insn_chain_scanned_p == 0)
13439 cfun->machine->insn_chain_scanned_p
13440 = spe_func_has_64bit_regs_p () + 1;
13441 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
13444 /* Select which calling sequence. */
13445 info_ptr->abi = DEFAULT_ABI;
13447 /* Calculate which registers need to be saved & save area size. */
13448 info_ptr->first_gp_reg_save = first_reg_to_save ();
13449 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13450 even if it currently looks like we won't. */
13451 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
13452 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
13453 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
13454 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
13455 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
13457 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
13459 /* For the SPE, we have an additional upper 32-bits on each GPR.
13460 Ideally we should save the entire 64-bits only when the upper
13461 half is used in SIMD instructions. Since we only record
13462 registers live (not the size they are used in), this proves
13463 difficult because we'd have to traverse the instruction chain at
13464 the right time, taking reload into account. This is a real pain,
13465 so we opt to save the GPRs in 64-bits always if but one register
13466 gets used in 64-bits. Otherwise, all the registers in the frame
13467 get saved in 32-bits.
13469 So... since when we save all GPRs (except the SP) in 64-bits, the
13470 traditional GP save area will be empty. */
13471 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13472 info_ptr->gp_size = 0;
13474 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
13475 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
13477 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
13478 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
13479 - info_ptr->first_altivec_reg_save);
13481 /* Does this function call anything? */
13482 info_ptr->calls_p = (! current_function_is_leaf
13483 || cfun->machine->ra_needs_full_frame);
13485 /* Determine if we need to save the link register. */
13486 if ((DEFAULT_ABI == ABI_AIX
13487 && current_function_profile
13488 && !TARGET_PROFILE_KERNEL)
13489 #ifdef TARGET_RELOCATABLE
13490 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
13492 || (info_ptr->first_fp_reg_save != 64
13493 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
13494 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
13495 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
13496 || info_ptr->calls_p
13497 || rs6000_ra_ever_killed ())
13499 info_ptr->lr_save_p = 1;
13500 df_set_regs_ever_live (LINK_REGISTER_REGNUM, true);
13503 /* Determine if we need to save the condition code registers. */
13504 if (df_regs_ever_live_p (CR2_REGNO)
13505 || df_regs_ever_live_p (CR3_REGNO)
13506 || df_regs_ever_live_p (CR4_REGNO))
13508 info_ptr->cr_save_p = 1;
13509 if (DEFAULT_ABI == ABI_V4)
13510 info_ptr->cr_size = reg_size;
13513 /* If the current function calls __builtin_eh_return, then we need
13514 to allocate stack space for registers that will hold data for
13515 the exception handler. */
13516 if (current_function_calls_eh_return)
13519 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
13522 /* SPE saves EH registers in 64-bits. */
13523 ehrd_size = i * (TARGET_SPE_ABI
13524 && info_ptr->spe_64bit_regs_used != 0
13525 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
13530 /* Determine various sizes. */
13531 info_ptr->reg_size = reg_size;
13532 info_ptr->fixed_size = RS6000_SAVE_AREA;
13533 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
13534 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
13535 TARGET_ALTIVEC ? 16 : 8);
13536 if (FRAME_GROWS_DOWNWARD)
13537 info_ptr->vars_size
13538 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
13539 + info_ptr->parm_size,
13540 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
13541 - (info_ptr->fixed_size + info_ptr->vars_size
13542 + info_ptr->parm_size);
13544 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13545 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
13547 info_ptr->spe_gp_size = 0;
13549 if (TARGET_ALTIVEC_ABI)
13550 info_ptr->vrsave_mask = compute_vrsave_mask ();
13552 info_ptr->vrsave_mask = 0;
13554 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13555 info_ptr->vrsave_size = 4;
13557 info_ptr->vrsave_size = 0;
13559 compute_save_world_info (info_ptr);
13561 /* Calculate the offsets. */
13562 switch (DEFAULT_ABI)
13566 gcc_unreachable ();
13570 info_ptr->fp_save_offset = - info_ptr->fp_size;
13571 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13573 if (TARGET_ALTIVEC_ABI)
13575 info_ptr->vrsave_save_offset
13576 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13578 /* Align stack so vector save area is on a quadword boundary.
13579 The padding goes above the vectors. */
13580 if (info_ptr->altivec_size != 0)
13581 info_ptr->altivec_padding_size
13582 = info_ptr->vrsave_save_offset & 0xF;
13584 info_ptr->altivec_padding_size = 0;
13586 info_ptr->altivec_save_offset
13587 = info_ptr->vrsave_save_offset
13588 - info_ptr->altivec_padding_size
13589 - info_ptr->altivec_size;
13590 gcc_assert (info_ptr->altivec_size == 0
13591 || info_ptr->altivec_save_offset % 16 == 0);
13593 /* Adjust for AltiVec case. */
13594 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13597 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13598 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13599 info_ptr->lr_save_offset = 2*reg_size;
13603 info_ptr->fp_save_offset = - info_ptr->fp_size;
13604 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13605 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13607 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13609 /* Align stack so SPE GPR save area is aligned on a
13610 double-word boundary. */
13611 if (info_ptr->spe_gp_size != 0)
13612 info_ptr->spe_padding_size
13613 = 8 - (-info_ptr->cr_save_offset % 8);
13615 info_ptr->spe_padding_size = 0;
13617 info_ptr->spe_gp_save_offset
13618 = info_ptr->cr_save_offset
13619 - info_ptr->spe_padding_size
13620 - info_ptr->spe_gp_size;
13622 /* Adjust for SPE case. */
13623 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13625 else if (TARGET_ALTIVEC_ABI)
13627 info_ptr->vrsave_save_offset
13628 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13630 /* Align stack so vector save area is on a quadword boundary. */
13631 if (info_ptr->altivec_size != 0)
13632 info_ptr->altivec_padding_size
13633 = 16 - (-info_ptr->vrsave_save_offset % 16);
13635 info_ptr->altivec_padding_size = 0;
13637 info_ptr->altivec_save_offset
13638 = info_ptr->vrsave_save_offset
13639 - info_ptr->altivec_padding_size
13640 - info_ptr->altivec_size;
13642 /* Adjust for AltiVec case. */
13643 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13646 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13647 info_ptr->ehrd_offset -= ehrd_size;
13648 info_ptr->lr_save_offset = reg_size;
13652 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13653 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13654 + info_ptr->gp_size
13655 + info_ptr->altivec_size
13656 + info_ptr->altivec_padding_size
13657 + info_ptr->spe_gp_size
13658 + info_ptr->spe_padding_size
13660 + info_ptr->cr_size
13661 + info_ptr->vrsave_size,
13664 non_fixed_size = (info_ptr->vars_size
13665 + info_ptr->parm_size
13666 + info_ptr->save_size);
13668 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13669 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13671 /* Determine if we need to allocate any stack frame:
13673 For AIX we need to push the stack if a frame pointer is needed
13674 (because the stack might be dynamically adjusted), if we are
13675 debugging, if we make calls, or if the sum of fp_save, gp_save,
13676 and local variables are more than the space needed to save all
13677 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13678 + 18*8 = 288 (GPR13 reserved).
13680 For V.4 we don't have the stack cushion that AIX uses, but assume
13681 that the debugger can handle stackless frames. */
13683 if (info_ptr->calls_p)
13684 info_ptr->push_p = 1;
13686 else if (DEFAULT_ABI == ABI_V4)
13687 info_ptr->push_p = non_fixed_size != 0;
13689 else if (frame_pointer_needed)
13690 info_ptr->push_p = 1;
13692 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13693 info_ptr->push_p = 1;
13696 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13698 /* Zero offsets if we're not saving those registers. */
13699 if (info_ptr->fp_size == 0)
13700 info_ptr->fp_save_offset = 0;
13702 if (info_ptr->gp_size == 0)
13703 info_ptr->gp_save_offset = 0;
13705 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13706 info_ptr->altivec_save_offset = 0;
13708 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13709 info_ptr->vrsave_save_offset = 0;
13711 if (! TARGET_SPE_ABI
13712 || info_ptr->spe_64bit_regs_used == 0
13713 || info_ptr->spe_gp_size == 0)
13714 info_ptr->spe_gp_save_offset = 0;
13716 if (! info_ptr->lr_save_p)
13717 info_ptr->lr_save_offset = 0;
13719 if (! info_ptr->cr_save_p)
13720 info_ptr->cr_save_offset = 0;
13725 /* Return true if the current function uses any GPRs in 64-bit SIMD
13729 spe_func_has_64bit_regs_p (void)
13733 /* Functions that save and restore all the call-saved registers will
13734 need to save/restore the registers in 64-bits. */
13735 if (current_function_calls_eh_return
13736 || current_function_calls_setjmp
13737 || current_function_has_nonlocal_goto)
13740 insns = get_insns ();
13742 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13748 /* FIXME: This should be implemented with attributes...
13750 (set_attr "spe64" "true")....then,
13751 if (get_spe64(insn)) return true;
13753 It's the only reliable way to do the stuff below. */
13755 i = PATTERN (insn);
13756 if (GET_CODE (i) == SET)
13758 enum machine_mode mode = GET_MODE (SET_SRC (i));
13760 if (SPE_VECTOR_MODE (mode))
13762 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
13772 debug_stack_info (rs6000_stack_t *info)
13774 const char *abi_string;
13777 info = rs6000_stack_info ();
13779 fprintf (stderr, "\nStack information for function %s:\n",
13780 ((current_function_decl && DECL_NAME (current_function_decl))
13781 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13786 default: abi_string = "Unknown"; break;
13787 case ABI_NONE: abi_string = "NONE"; break;
13788 case ABI_AIX: abi_string = "AIX"; break;
13789 case ABI_DARWIN: abi_string = "Darwin"; break;
13790 case ABI_V4: abi_string = "V.4"; break;
13793 fprintf (stderr, "\tABI = %5s\n", abi_string);
13795 if (TARGET_ALTIVEC_ABI)
13796 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13798 if (TARGET_SPE_ABI)
13799 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13801 if (info->first_gp_reg_save != 32)
13802 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13804 if (info->first_fp_reg_save != 64)
13805 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13807 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13808 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13809 info->first_altivec_reg_save);
13811 if (info->lr_save_p)
13812 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13814 if (info->cr_save_p)
13815 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13817 if (info->vrsave_mask)
13818 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13821 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13824 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13826 if (info->gp_save_offset)
13827 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13829 if (info->fp_save_offset)
13830 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13832 if (info->altivec_save_offset)
13833 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13834 info->altivec_save_offset);
13836 if (info->spe_gp_save_offset)
13837 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13838 info->spe_gp_save_offset);
13840 if (info->vrsave_save_offset)
13841 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13842 info->vrsave_save_offset);
13844 if (info->lr_save_offset)
13845 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13847 if (info->cr_save_offset)
13848 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13850 if (info->varargs_save_offset)
13851 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13853 if (info->total_size)
13854 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13857 if (info->vars_size)
13858 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13861 if (info->parm_size)
13862 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13864 if (info->fixed_size)
13865 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13868 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13870 if (info->spe_gp_size)
13871 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13874 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13876 if (info->altivec_size)
13877 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13879 if (info->vrsave_size)
13880 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13882 if (info->altivec_padding_size)
13883 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13884 info->altivec_padding_size);
13886 if (info->spe_padding_size)
13887 fprintf (stderr, "\tspe_padding_size = %5d\n",
13888 info->spe_padding_size);
13891 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13893 if (info->save_size)
13894 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13896 if (info->reg_size != 4)
13897 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13899 fprintf (stderr, "\n");
13903 rs6000_return_addr (int count, rtx frame)
13905 /* Currently we don't optimize very well between prolog and body
13906 code and for PIC code the code can be actually quite bad, so
13907 don't try to be too clever here. */
13908 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13910 cfun->machine->ra_needs_full_frame = 1;
13917 plus_constant (copy_to_reg
13918 (gen_rtx_MEM (Pmode,
13919 memory_address (Pmode, frame))),
13920 RETURN_ADDRESS_OFFSET)));
13923 cfun->machine->ra_need_lr = 1;
13924 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13927 /* Say whether a function is a candidate for sibcall handling or not.
13928 We do not allow indirect calls to be optimized into sibling calls.
13929 Also, we can't do it if there are any vector parameters; there's
13930 nowhere to put the VRsave code so it works; note that functions with
13931 vector parameters are required to have a prototype, so the argument
13932 type info must be available here. (The tail recursion case can work
13933 with vector parameters, but there's no way to distinguish here.) */
13935 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13940 if (TARGET_ALTIVEC_VRSAVE)
13942 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13943 type; type = TREE_CHAIN (type))
13945 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13949 if (DEFAULT_ABI == ABI_DARWIN
13950 || ((*targetm.binds_local_p) (decl)
13951 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
13953 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13955 if (!lookup_attribute ("longcall", attr_list)
13956 || lookup_attribute ("shortcall", attr_list))
13963 /* NULL if INSN insn is valid within a low-overhead loop.
13964 Otherwise return why doloop cannot be applied.
13965 PowerPC uses the COUNT register for branch on table instructions. */
13967 static const char *
13968 rs6000_invalid_within_doloop (rtx insn)
13971 return "Function call in the loop.";
13974 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13975 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13976 return "Computed branch in the loop.";
13982 rs6000_ra_ever_killed (void)
13988 if (current_function_is_thunk)
13991 /* regs_ever_live has LR marked as used if any sibcalls are present,
13992 but this should not force saving and restoring in the
13993 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13994 clobbers LR, so that is inappropriate. */
13996 /* Also, the prologue can generate a store into LR that
13997 doesn't really count, like this:
14000 bcl to set PIC register
14004 When we're called from the epilogue, we need to avoid counting
14005 this as a store. */
14007 push_topmost_sequence ();
14008 top = get_insns ();
14009 pop_topmost_sequence ();
14010 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14012 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
14018 if (!SIBLING_CALL_P (insn))
14021 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
14023 else if (set_of (reg, insn) != NULL_RTX
14024 && !prologue_epilogue_contains (insn))
14031 /* Emit instructions needed to load the TOC register.
14032 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
14033 a constant pool; or for SVR4 -fpic. */
14036 rs6000_emit_load_toc_table (int fromprolog)
14039 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
14041 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
14044 rtx lab, tmp1, tmp2, got;
14046 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14047 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14049 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14051 got = rs6000_got_sym ();
14052 tmp1 = tmp2 = dest;
14055 tmp1 = gen_reg_rtx (Pmode);
14056 tmp2 = gen_reg_rtx (Pmode);
14058 emit_insn (gen_load_toc_v4_PIC_1 (lab));
14059 emit_move_insn (tmp1,
14060 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14061 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
14062 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
14064 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
14066 emit_insn (gen_load_toc_v4_pic_si ());
14067 emit_move_insn (dest, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14069 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
14072 rtx temp0 = (fromprolog
14073 ? gen_rtx_REG (Pmode, 0)
14074 : gen_reg_rtx (Pmode));
14080 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14081 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14083 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
14084 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14086 emit_insn (gen_load_toc_v4_PIC_1 (symF));
14087 emit_move_insn (dest,
14088 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14089 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
14095 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14096 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
14097 emit_move_insn (dest,
14098 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14099 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
14101 emit_insn (gen_addsi3 (dest, temp0, dest));
14103 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
14105 /* This is for AIX code running in non-PIC ELF32. */
14108 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
14109 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14111 emit_insn (gen_elf_high (dest, realsym));
14112 emit_insn (gen_elf_low (dest, dest, realsym));
14116 gcc_assert (DEFAULT_ABI == ABI_AIX);
14119 emit_insn (gen_load_toc_aix_si (dest));
14121 emit_insn (gen_load_toc_aix_di (dest));
14125 /* Emit instructions to restore the link register after determining where
14126 its value has been stored. */
14129 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
14131 rs6000_stack_t *info = rs6000_stack_info ();
14134 operands[0] = source;
14135 operands[1] = scratch;
14137 if (info->lr_save_p)
14139 rtx frame_rtx = stack_pointer_rtx;
14140 HOST_WIDE_INT sp_offset = 0;
14143 if (frame_pointer_needed
14144 || current_function_calls_alloca
14145 || info->total_size > 32767)
14147 tmp = gen_frame_mem (Pmode, frame_rtx);
14148 emit_move_insn (operands[1], tmp);
14149 frame_rtx = operands[1];
14151 else if (info->push_p)
14152 sp_offset = info->total_size;
14154 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14155 tmp = gen_frame_mem (Pmode, tmp);
14156 emit_move_insn (tmp, operands[0]);
14159 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
14162 static GTY(()) int set = -1;
14165 get_TOC_alias_set (void)
14168 set = new_alias_set ();
14172 /* This returns nonzero if the current function uses the TOC. This is
14173 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
14174 is generated by the ABI_V4 load_toc_* patterns. */
14181 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14184 rtx pat = PATTERN (insn);
14187 if (GET_CODE (pat) == PARALLEL)
14188 for (i = 0; i < XVECLEN (pat, 0); i++)
14190 rtx sub = XVECEXP (pat, 0, i);
14191 if (GET_CODE (sub) == USE)
14193 sub = XEXP (sub, 0);
14194 if (GET_CODE (sub) == UNSPEC
14195 && XINT (sub, 1) == UNSPEC_TOC)
14205 create_TOC_reference (rtx symbol)
14207 if (!can_create_pseudo_p ())
14208 df_set_regs_ever_live (TOC_REGISTER, true);
14209 return gen_rtx_PLUS (Pmode,
14210 gen_rtx_REG (Pmode, TOC_REGISTER),
14211 gen_rtx_CONST (Pmode,
14212 gen_rtx_MINUS (Pmode, symbol,
14213 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
14216 /* If _Unwind_* has been called from within the same module,
14217 toc register is not guaranteed to be saved to 40(1) on function
14218 entry. Save it there in that case. */
14221 rs6000_aix_emit_builtin_unwind_init (void)
14224 rtx stack_top = gen_reg_rtx (Pmode);
14225 rtx opcode_addr = gen_reg_rtx (Pmode);
14226 rtx opcode = gen_reg_rtx (SImode);
14227 rtx tocompare = gen_reg_rtx (SImode);
14228 rtx no_toc_save_needed = gen_label_rtx ();
14230 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
14231 emit_move_insn (stack_top, mem);
14233 mem = gen_frame_mem (Pmode,
14234 gen_rtx_PLUS (Pmode, stack_top,
14235 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
14236 emit_move_insn (opcode_addr, mem);
14237 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
14238 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
14239 : 0xE8410028, SImode));
14241 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
14242 SImode, NULL_RTX, NULL_RTX,
14243 no_toc_save_needed);
14245 mem = gen_frame_mem (Pmode,
14246 gen_rtx_PLUS (Pmode, stack_top,
14247 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
14248 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
14249 emit_label (no_toc_save_needed);
14252 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
14253 and the change to the stack pointer. */
14256 rs6000_emit_stack_tie (void)
14258 rtx mem = gen_frame_mem (BLKmode,
14259 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
14261 emit_insn (gen_stack_tie (mem));
14264 /* Emit the correct code for allocating stack space, as insns.
14265 If COPY_R12, make sure a copy of the old frame is left in r12.
14266 The generated code may use hard register 0 as a temporary. */
14269 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
14272 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14273 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
14274 rtx todec = gen_int_mode (-size, Pmode);
14276 if (INTVAL (todec) != -size)
14278 warning (0, "stack frame too large");
14279 emit_insn (gen_trap ());
14283 if (current_function_limit_stack)
14285 if (REG_P (stack_limit_rtx)
14286 && REGNO (stack_limit_rtx) > 1
14287 && REGNO (stack_limit_rtx) <= 31)
14289 emit_insn (TARGET_32BIT
14290 ? gen_addsi3 (tmp_reg,
14293 : gen_adddi3 (tmp_reg,
14297 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14300 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
14302 && DEFAULT_ABI == ABI_V4)
14304 rtx toload = gen_rtx_CONST (VOIDmode,
14305 gen_rtx_PLUS (Pmode,
14309 emit_insn (gen_elf_high (tmp_reg, toload));
14310 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
14311 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14315 warning (0, "stack limit expression is not supported");
14318 if (copy_r12 || ! TARGET_UPDATE)
14319 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
14325 /* Need a note here so that try_split doesn't get confused. */
14326 if (get_last_insn () == NULL_RTX)
14327 emit_note (NOTE_INSN_DELETED);
14328 insn = emit_move_insn (tmp_reg, todec);
14329 try_split (PATTERN (insn), insn, 0);
14333 insn = emit_insn (TARGET_32BIT
14334 ? gen_movsi_update (stack_reg, stack_reg,
14336 : gen_movdi_di_update (stack_reg, stack_reg,
14337 todec, stack_reg));
14341 insn = emit_insn (TARGET_32BIT
14342 ? gen_addsi3 (stack_reg, stack_reg, todec)
14343 : gen_adddi3 (stack_reg, stack_reg, todec));
14344 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
14345 gen_rtx_REG (Pmode, 12));
14348 RTX_FRAME_RELATED_P (insn) = 1;
14350 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14351 gen_rtx_SET (VOIDmode, stack_reg,
14352 gen_rtx_PLUS (Pmode, stack_reg,
14357 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14358 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14359 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14360 deduce these equivalences by itself so it wasn't necessary to hold
14361 its hand so much. */
14364 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
14365 rtx reg2, rtx rreg)
14369 /* copy_rtx will not make unique copies of registers, so we need to
14370 ensure we don't have unwanted sharing here. */
14372 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14375 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14377 real = copy_rtx (PATTERN (insn));
14379 if (reg2 != NULL_RTX)
14380 real = replace_rtx (real, reg2, rreg);
14382 real = replace_rtx (real, reg,
14383 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
14384 STACK_POINTER_REGNUM),
14387 /* We expect that 'real' is either a SET or a PARALLEL containing
14388 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14389 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14391 if (GET_CODE (real) == SET)
14395 temp = simplify_rtx (SET_SRC (set));
14397 SET_SRC (set) = temp;
14398 temp = simplify_rtx (SET_DEST (set));
14400 SET_DEST (set) = temp;
14401 if (GET_CODE (SET_DEST (set)) == MEM)
14403 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14405 XEXP (SET_DEST (set), 0) = temp;
14412 gcc_assert (GET_CODE (real) == PARALLEL);
14413 for (i = 0; i < XVECLEN (real, 0); i++)
14414 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
14416 rtx set = XVECEXP (real, 0, i);
14418 temp = simplify_rtx (SET_SRC (set));
14420 SET_SRC (set) = temp;
14421 temp = simplify_rtx (SET_DEST (set));
14423 SET_DEST (set) = temp;
14424 if (GET_CODE (SET_DEST (set)) == MEM)
14426 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14428 XEXP (SET_DEST (set), 0) = temp;
14430 RTX_FRAME_RELATED_P (set) = 1;
14435 real = spe_synthesize_frame_save (real);
14437 RTX_FRAME_RELATED_P (insn) = 1;
14438 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14443 /* Given an SPE frame note, return a PARALLEL of SETs with the
14444 original note, plus a synthetic register save. */
14447 spe_synthesize_frame_save (rtx real)
14449 rtx synth, offset, reg, real2;
14451 if (GET_CODE (real) != SET
14452 || GET_MODE (SET_SRC (real)) != V2SImode)
14455 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14456 frame related note. The parallel contains a set of the register
14457 being saved, and another set to a synthetic register (n+1200).
14458 This is so we can differentiate between 64-bit and 32-bit saves.
14459 Words cannot describe this nastiness. */
14461 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
14462 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
14463 && GET_CODE (SET_SRC (real)) == REG);
14466 (set (mem (plus (reg x) (const y)))
14469 (set (mem (plus (reg x) (const y+4)))
14473 real2 = copy_rtx (real);
14474 PUT_MODE (SET_DEST (real2), SImode);
14475 reg = SET_SRC (real2);
14476 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14477 synth = copy_rtx (real2);
14479 if (BYTES_BIG_ENDIAN)
14481 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14482 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14485 reg = SET_SRC (synth);
14487 synth = replace_rtx (synth, reg,
14488 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14490 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14491 synth = replace_rtx (synth, offset,
14492 GEN_INT (INTVAL (offset)
14493 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14495 RTX_FRAME_RELATED_P (synth) = 1;
14496 RTX_FRAME_RELATED_P (real2) = 1;
14497 if (BYTES_BIG_ENDIAN)
14498 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14500 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14505 /* Returns an insn that has a vrsave set operation with the
14506 appropriate CLOBBERs. */
14509 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
14512 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14513 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14516 = gen_rtx_SET (VOIDmode,
14518 gen_rtx_UNSPEC_VOLATILE (SImode,
14519 gen_rtvec (2, reg, vrsave),
14520 UNSPECV_SET_VRSAVE));
14524 /* We need to clobber the registers in the mask so the scheduler
14525 does not move sets to VRSAVE before sets of AltiVec registers.
14527 However, if the function receives nonlocal gotos, reload will set
14528 all call saved registers live. We will end up with:
14530 (set (reg 999) (mem))
14531 (parallel [ (set (reg vrsave) (unspec blah))
14532 (clobber (reg 999))])
14534 The clobber will cause the store into reg 999 to be dead, and
14535 flow will attempt to delete an epilogue insn. In this case, we
14536 need an unspec use/set of the register. */
14538 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14539 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14541 if (!epiloguep || call_used_regs [i])
14542 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14543 gen_rtx_REG (V4SImode, i));
14546 rtx reg = gen_rtx_REG (V4SImode, i);
14549 = gen_rtx_SET (VOIDmode,
14551 gen_rtx_UNSPEC (V4SImode,
14552 gen_rtvec (1, reg), 27));
14556 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14558 for (i = 0; i < nclobs; ++i)
14559 XVECEXP (insn, 0, i) = clobs[i];
14564 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14565 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14568 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14569 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14571 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14572 rtx replacea, replaceb;
14574 int_rtx = GEN_INT (offset);
14576 /* Some cases that need register indexed addressing. */
14577 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14578 || (TARGET_E500_DOUBLE && mode == DFmode)
14580 && SPE_VECTOR_MODE (mode)
14581 && !SPE_CONST_OFFSET_OK (offset)))
14583 /* Whomever calls us must make sure r11 is available in the
14584 flow path of instructions in the prologue. */
14585 offset_rtx = gen_rtx_REG (Pmode, 11);
14586 emit_move_insn (offset_rtx, int_rtx);
14588 replacea = offset_rtx;
14589 replaceb = int_rtx;
14593 offset_rtx = int_rtx;
14594 replacea = NULL_RTX;
14595 replaceb = NULL_RTX;
14598 reg = gen_rtx_REG (mode, regno);
14599 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14600 mem = gen_frame_mem (mode, addr);
14602 insn = emit_move_insn (mem, reg);
14604 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14607 /* Emit an offset memory reference suitable for a frame store, while
14608 converting to a valid addressing mode. */
14611 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14613 rtx int_rtx, offset_rtx;
14615 int_rtx = GEN_INT (offset);
14617 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14618 || (TARGET_E500_DOUBLE && mode == DFmode))
14620 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14621 emit_move_insn (offset_rtx, int_rtx);
14624 offset_rtx = int_rtx;
14626 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14629 /* Look for user-defined global regs. We should not save and restore these,
14630 and cannot use stmw/lmw if there are any in its range. */
14633 no_global_regs_above (int first_greg)
14636 for (i = 0; i < 32 - first_greg; i++)
14637 if (global_regs[first_greg + i])
14642 #ifndef TARGET_FIX_AND_CONTINUE
14643 #define TARGET_FIX_AND_CONTINUE 0
14646 /* Determine whether the gp REG is really used. */
14649 rs6000_reg_live_or_pic_offset_p (int reg)
14651 return ((df_regs_ever_live_p (reg)
14652 && (!call_used_regs[reg]
14653 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14654 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14655 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14656 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14657 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
14660 /* Emit function prologue as insns. */
14663 rs6000_emit_prologue (void)
14665 rs6000_stack_t *info = rs6000_stack_info ();
14666 enum machine_mode reg_mode = Pmode;
14667 int reg_size = TARGET_32BIT ? 4 : 8;
14668 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14669 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14670 rtx frame_reg_rtx = sp_reg_rtx;
14671 rtx cr_save_rtx = NULL_RTX;
14673 int saving_FPRs_inline;
14674 int using_store_multiple;
14675 HOST_WIDE_INT sp_offset = 0;
14677 if (TARGET_FIX_AND_CONTINUE)
14679 /* gdb on darwin arranges to forward a function from the old
14680 address by modifying the first 5 instructions of the function
14681 to branch to the overriding function. This is necessary to
14682 permit function pointers that point to the old function to
14683 actually forward to the new function. */
14684 emit_insn (gen_nop ());
14685 emit_insn (gen_nop ());
14686 emit_insn (gen_nop ());
14687 emit_insn (gen_nop ());
14688 emit_insn (gen_nop ());
14691 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14693 reg_mode = V2SImode;
14697 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14698 && (!TARGET_SPE_ABI
14699 || info->spe_64bit_regs_used == 0)
14700 && info->first_gp_reg_save < 31
14701 && no_global_regs_above (info->first_gp_reg_save));
14702 saving_FPRs_inline = (info->first_fp_reg_save == 64
14703 || FP_SAVE_INLINE (info->first_fp_reg_save)
14704 || current_function_calls_eh_return
14705 || cfun->machine->ra_need_lr);
14707 /* For V.4, update stack before we do any saving and set back pointer. */
14708 if (! WORLD_SAVE_P (info)
14710 && (DEFAULT_ABI == ABI_V4
14711 || current_function_calls_eh_return))
14713 if (info->total_size < 32767)
14714 sp_offset = info->total_size;
14716 frame_reg_rtx = frame_ptr_rtx;
14717 rs6000_emit_allocate_stack (info->total_size,
14718 (frame_reg_rtx != sp_reg_rtx
14719 && (info->cr_save_p
14721 || info->first_fp_reg_save < 64
14722 || info->first_gp_reg_save < 32
14724 if (frame_reg_rtx != sp_reg_rtx)
14725 rs6000_emit_stack_tie ();
14728 /* Handle world saves specially here. */
14729 if (WORLD_SAVE_P (info))
14736 /* save_world expects lr in r0. */
14737 reg0 = gen_rtx_REG (Pmode, 0);
14738 if (info->lr_save_p)
14740 insn = emit_move_insn (reg0,
14741 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14742 RTX_FRAME_RELATED_P (insn) = 1;
14745 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14746 assumptions about the offsets of various bits of the stack
14748 gcc_assert (info->gp_save_offset == -220
14749 && info->fp_save_offset == -144
14750 && info->lr_save_offset == 8
14751 && info->cr_save_offset == 4
14754 && (!current_function_calls_eh_return
14755 || info->ehrd_offset == -432)
14756 && info->vrsave_save_offset == -224
14757 && info->altivec_save_offset == -416);
14759 treg = gen_rtx_REG (SImode, 11);
14760 emit_move_insn (treg, GEN_INT (-info->total_size));
14762 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14763 in R11. It also clobbers R12, so beware! */
14765 /* Preserve CR2 for save_world prologues */
14767 sz += 32 - info->first_gp_reg_save;
14768 sz += 64 - info->first_fp_reg_save;
14769 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14770 p = rtvec_alloc (sz);
14772 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14773 gen_rtx_REG (SImode,
14774 LINK_REGISTER_REGNUM));
14775 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14776 gen_rtx_SYMBOL_REF (Pmode,
14778 /* We do floats first so that the instruction pattern matches
14780 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14782 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14783 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14784 GEN_INT (info->fp_save_offset
14785 + sp_offset + 8 * i));
14786 rtx mem = gen_frame_mem (DFmode, addr);
14788 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14790 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14792 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14793 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14794 GEN_INT (info->altivec_save_offset
14795 + sp_offset + 16 * i));
14796 rtx mem = gen_frame_mem (V4SImode, addr);
14798 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14800 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14802 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14803 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14804 GEN_INT (info->gp_save_offset
14805 + sp_offset + reg_size * i));
14806 rtx mem = gen_frame_mem (reg_mode, addr);
14808 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14812 /* CR register traditionally saved as CR2. */
14813 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14814 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14815 GEN_INT (info->cr_save_offset
14817 rtx mem = gen_frame_mem (reg_mode, addr);
14819 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14821 /* Explain about use of R0. */
14822 if (info->lr_save_p)
14824 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14825 GEN_INT (info->lr_save_offset
14827 rtx mem = gen_frame_mem (reg_mode, addr);
14829 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
14831 /* Explain what happens to the stack pointer. */
14833 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
14834 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
14837 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14838 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14839 treg, GEN_INT (-info->total_size));
14840 sp_offset = info->total_size;
14843 /* If we use the link register, get it into r0. */
14844 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14846 rtx addr, reg, mem;
14848 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14849 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14850 RTX_FRAME_RELATED_P (insn) = 1;
14852 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14853 GEN_INT (info->lr_save_offset + sp_offset));
14854 reg = gen_rtx_REG (Pmode, 0);
14855 mem = gen_rtx_MEM (Pmode, addr);
14856 /* This should not be of rs6000_sr_alias_set, because of
14857 __builtin_return_address. */
14859 insn = emit_move_insn (mem, reg);
14860 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14861 NULL_RTX, NULL_RTX);
14864 /* If we need to save CR, put it into r12. */
14865 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14869 cr_save_rtx = gen_rtx_REG (SImode, 12);
14870 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14871 RTX_FRAME_RELATED_P (insn) = 1;
14872 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14873 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14874 But that's OK. All we have to do is specify that _one_ condition
14875 code register is saved in this stack slot. The thrower's epilogue
14876 will then restore all the call-saved registers.
14877 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14878 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14879 gen_rtx_REG (SImode, CR2_REGNO));
14880 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14885 /* Do any required saving of fpr's. If only one or two to save, do
14886 it ourselves. Otherwise, call function. */
14887 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14890 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14891 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
14892 && ! call_used_regs[info->first_fp_reg_save+i]))
14893 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14894 info->first_fp_reg_save + i,
14895 info->fp_save_offset + sp_offset + 8 * i,
14898 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14902 const char *alloc_rname;
14904 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14906 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14907 gen_rtx_REG (Pmode,
14908 LINK_REGISTER_REGNUM));
14909 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14910 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14911 alloc_rname = ggc_strdup (rname);
14912 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14913 gen_rtx_SYMBOL_REF (Pmode,
14915 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14917 rtx addr, reg, mem;
14918 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14919 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14920 GEN_INT (info->fp_save_offset
14921 + sp_offset + 8*i));
14922 mem = gen_frame_mem (DFmode, addr);
14924 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14926 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14927 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14928 NULL_RTX, NULL_RTX);
14931 /* Save GPRs. This is done as a PARALLEL if we are using
14932 the store-multiple instructions. */
14933 if (!WORLD_SAVE_P (info) && using_store_multiple)
14937 p = rtvec_alloc (32 - info->first_gp_reg_save);
14938 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14940 rtx addr, reg, mem;
14941 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14942 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14943 GEN_INT (info->gp_save_offset
14946 mem = gen_frame_mem (reg_mode, addr);
14948 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14950 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14951 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14952 NULL_RTX, NULL_RTX);
14954 else if (!WORLD_SAVE_P (info)
14956 && info->spe_64bit_regs_used != 0
14957 && info->first_gp_reg_save != 32)
14960 rtx spe_save_area_ptr;
14961 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
14962 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
14963 && !call_used_regs[STATIC_CHAIN_REGNUM]);
14965 /* Determine whether we can address all of the registers that need
14966 to be saved with an offset from the stack pointer that fits in
14967 the small const field for SPE memory instructions. */
14968 int spe_regs_addressable_via_sp
14969 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
14970 + (32 - info->first_gp_reg_save - 1) * reg_size);
14973 if (spe_regs_addressable_via_sp)
14975 spe_save_area_ptr = sp_reg_rtx;
14976 spe_offset = info->spe_gp_save_offset + sp_offset;
14980 /* Make r11 point to the start of the SPE save area. We need
14981 to be careful here if r11 is holding the static chain. If
14982 it is, then temporarily save it in r0. We would use r0 as
14983 our base register here, but using r0 as a base register in
14984 loads and stores means something different from what we
14986 if (using_static_chain_p)
14988 rtx r0 = gen_rtx_REG (Pmode, 0);
14990 gcc_assert (info->first_gp_reg_save > 11);
14992 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
14995 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
14996 emit_insn (gen_addsi3 (spe_save_area_ptr, sp_reg_rtx,
14997 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15002 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15003 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15005 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15006 rtx offset, addr, mem;
15008 /* We're doing all this to ensure that the offset fits into
15009 the immediate offset of 'evstdd'. */
15010 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
15012 offset = GEN_INT (reg_size * i + spe_offset);
15013 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15014 mem = gen_rtx_MEM (V2SImode, addr);
15016 insn = emit_move_insn (mem, reg);
15018 rs6000_frame_related (insn, spe_save_area_ptr,
15019 info->spe_gp_save_offset
15020 + sp_offset + reg_size * i,
15021 offset, const0_rtx);
15024 /* Move the static chain pointer back. */
15025 if (using_static_chain_p && !spe_regs_addressable_via_sp)
15026 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
15028 else if (!WORLD_SAVE_P (info))
15031 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15032 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15034 rtx addr, reg, mem;
15035 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15037 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15038 GEN_INT (info->gp_save_offset
15041 mem = gen_frame_mem (reg_mode, addr);
15043 insn = emit_move_insn (mem, reg);
15044 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15045 NULL_RTX, NULL_RTX);
15049 /* ??? There's no need to emit actual instructions here, but it's the
15050 easiest way to get the frame unwind information emitted. */
15051 if (current_function_calls_eh_return)
15053 unsigned int i, regno;
15055 /* In AIX ABI we need to pretend we save r2 here. */
15058 rtx addr, reg, mem;
15060 reg = gen_rtx_REG (reg_mode, 2);
15061 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15062 GEN_INT (sp_offset + 5 * reg_size));
15063 mem = gen_frame_mem (reg_mode, addr);
15065 insn = emit_move_insn (mem, reg);
15066 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15067 NULL_RTX, NULL_RTX);
15068 PATTERN (insn) = gen_blockage ();
15073 regno = EH_RETURN_DATA_REGNO (i);
15074 if (regno == INVALID_REGNUM)
15077 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
15078 info->ehrd_offset + sp_offset
15079 + reg_size * (int) i,
15084 /* Save CR if we use any that must be preserved. */
15085 if (!WORLD_SAVE_P (info) && info->cr_save_p)
15087 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15088 GEN_INT (info->cr_save_offset + sp_offset));
15089 rtx mem = gen_frame_mem (SImode, addr);
15090 /* See the large comment above about why CR2_REGNO is used. */
15091 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
15093 /* If r12 was used to hold the original sp, copy cr into r0 now
15095 if (REGNO (frame_reg_rtx) == 12)
15099 cr_save_rtx = gen_rtx_REG (SImode, 0);
15100 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15101 RTX_FRAME_RELATED_P (insn) = 1;
15102 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
15103 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15108 insn = emit_move_insn (mem, cr_save_rtx);
15110 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15111 NULL_RTX, NULL_RTX);
15114 /* Update stack and set back pointer unless this is V.4,
15115 for which it was done previously. */
15116 if (!WORLD_SAVE_P (info) && info->push_p
15117 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
15119 if (info->total_size < 32767)
15120 sp_offset = info->total_size;
15122 frame_reg_rtx = frame_ptr_rtx;
15123 rs6000_emit_allocate_stack (info->total_size,
15124 (frame_reg_rtx != sp_reg_rtx
15125 && ((info->altivec_size != 0)
15126 || (info->vrsave_mask != 0)
15128 if (frame_reg_rtx != sp_reg_rtx)
15129 rs6000_emit_stack_tie ();
15132 /* Set frame pointer, if needed. */
15133 if (frame_pointer_needed)
15135 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
15137 RTX_FRAME_RELATED_P (insn) = 1;
15140 /* Save AltiVec registers if needed. Save here because the red zone does
15141 not include AltiVec registers. */
15142 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15146 /* There should be a non inline version of this, for when we
15147 are saving lots of vector registers. */
15148 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15149 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15151 rtx areg, savereg, mem;
15154 offset = info->altivec_save_offset + sp_offset
15155 + 16 * (i - info->first_altivec_reg_save);
15157 savereg = gen_rtx_REG (V4SImode, i);
15159 areg = gen_rtx_REG (Pmode, 0);
15160 emit_move_insn (areg, GEN_INT (offset));
15162 /* AltiVec addressing mode is [reg+reg]. */
15163 mem = gen_frame_mem (V4SImode,
15164 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
15166 insn = emit_move_insn (mem, savereg);
15168 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15169 areg, GEN_INT (offset));
15173 /* VRSAVE is a bit vector representing which AltiVec registers
15174 are used. The OS uses this to determine which vector
15175 registers to save on a context switch. We need to save
15176 VRSAVE on the stack frame, add whatever AltiVec registers we
15177 used in this function, and do the corresponding magic in the
15180 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15181 && info->vrsave_mask != 0)
15183 rtx reg, mem, vrsave;
15186 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
15187 as frame_reg_rtx and r11 as the static chain pointer for
15188 nested functions. */
15189 reg = gen_rtx_REG (SImode, 0);
15190 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15192 emit_insn (gen_get_vrsave_internal (reg));
15194 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
15196 if (!WORLD_SAVE_P (info))
15199 offset = info->vrsave_save_offset + sp_offset;
15200 mem = gen_frame_mem (SImode,
15201 gen_rtx_PLUS (Pmode, frame_reg_rtx,
15202 GEN_INT (offset)));
15203 insn = emit_move_insn (mem, reg);
15206 /* Include the registers in the mask. */
15207 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
15209 insn = emit_insn (generate_set_vrsave (reg, info, 0));
15212 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
15213 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
15214 || (DEFAULT_ABI == ABI_V4
15215 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
15216 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))
15218 /* If emit_load_toc_table will use the link register, we need to save
15219 it. We use R12 for this purpose because emit_load_toc_table
15220 can use register 0. This allows us to use a plain 'blr' to return
15221 from the procedure more often. */
15222 int save_LR_around_toc_setup = (TARGET_ELF
15223 && DEFAULT_ABI != ABI_AIX
15225 && ! info->lr_save_p
15226 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
15227 if (save_LR_around_toc_setup)
15229 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
15231 insn = emit_move_insn (frame_ptr_rtx, lr);
15232 RTX_FRAME_RELATED_P (insn) = 1;
15234 rs6000_emit_load_toc_table (TRUE);
15236 insn = emit_move_insn (lr, frame_ptr_rtx);
15237 RTX_FRAME_RELATED_P (insn) = 1;
15240 rs6000_emit_load_toc_table (TRUE);
15244 if (DEFAULT_ABI == ABI_DARWIN
15245 && flag_pic && current_function_uses_pic_offset_table)
15247 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
15248 rtx src = machopic_function_base_sym ();
15250 /* Save and restore LR locally around this call (in R0). */
15251 if (!info->lr_save_p)
15252 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
15254 emit_insn (gen_load_macho_picbase (src));
15256 emit_move_insn (gen_rtx_REG (Pmode,
15257 RS6000_PIC_OFFSET_TABLE_REGNUM),
15260 if (!info->lr_save_p)
15261 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
15266 /* Write function prologue. */
15269 rs6000_output_function_prologue (FILE *file,
15270 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15272 rs6000_stack_t *info = rs6000_stack_info ();
15274 if (TARGET_DEBUG_STACK)
15275 debug_stack_info (info);
15277 /* Write .extern for any function we will call to save and restore
15279 if (info->first_fp_reg_save < 64
15280 && !FP_SAVE_INLINE (info->first_fp_reg_save))
15281 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
15282 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
15283 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
15284 RESTORE_FP_SUFFIX);
15286 /* Write .extern for AIX common mode routines, if needed. */
15287 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
15289 fputs ("\t.extern __mulh\n", file);
15290 fputs ("\t.extern __mull\n", file);
15291 fputs ("\t.extern __divss\n", file);
15292 fputs ("\t.extern __divus\n", file);
15293 fputs ("\t.extern __quoss\n", file);
15294 fputs ("\t.extern __quous\n", file);
15295 common_mode_defined = 1;
15298 if (! HAVE_prologue)
15302 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
15303 the "toplevel" insn chain. */
15304 emit_note (NOTE_INSN_DELETED);
15305 rs6000_emit_prologue ();
15306 emit_note (NOTE_INSN_DELETED);
15308 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15312 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15314 INSN_ADDRESSES_NEW (insn, addr);
15319 if (TARGET_DEBUG_STACK)
15320 debug_rtx_list (get_insns (), 100);
15321 final (get_insns (), file, FALSE);
15325 rs6000_pic_labelno++;
15328 /* Emit function epilogue as insns.
15330 At present, dwarf2out_frame_debug_expr doesn't understand
15331 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15332 anywhere in the epilogue. Most of the insns below would in any case
15333 need special notes to explain where r11 is in relation to the stack. */
15336 rs6000_emit_epilogue (int sibcall)
15338 rs6000_stack_t *info;
15339 int restoring_FPRs_inline;
15340 int using_load_multiple;
15341 int using_mtcr_multiple;
15342 int use_backchain_to_restore_sp;
15344 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
15345 rtx frame_reg_rtx = sp_reg_rtx;
15346 enum machine_mode reg_mode = Pmode;
15347 int reg_size = TARGET_32BIT ? 4 : 8;
15350 info = rs6000_stack_info ();
15352 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15354 reg_mode = V2SImode;
15358 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15359 && (!TARGET_SPE_ABI
15360 || info->spe_64bit_regs_used == 0)
15361 && info->first_gp_reg_save < 31
15362 && no_global_regs_above (info->first_gp_reg_save));
15363 restoring_FPRs_inline = (sibcall
15364 || current_function_calls_eh_return
15365 || info->first_fp_reg_save == 64
15366 || FP_SAVE_INLINE (info->first_fp_reg_save));
15367 use_backchain_to_restore_sp = (frame_pointer_needed
15368 || current_function_calls_alloca
15369 || info->total_size > 32767);
15370 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
15371 || rs6000_cpu == PROCESSOR_PPC603
15372 || rs6000_cpu == PROCESSOR_PPC750
15375 if (WORLD_SAVE_P (info))
15379 const char *alloc_rname;
15382 /* eh_rest_world_r10 will return to the location saved in the LR
15383 stack slot (which is not likely to be our caller.)
15384 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15385 rest_world is similar, except any R10 parameter is ignored.
15386 The exception-handling stuff that was here in 2.95 is no
15387 longer necessary. */
15391 + 32 - info->first_gp_reg_save
15392 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
15393 + 63 + 1 - info->first_fp_reg_save);
15395 strcpy (rname, ((current_function_calls_eh_return) ?
15396 "*eh_rest_world_r10" : "*rest_world"));
15397 alloc_rname = ggc_strdup (rname);
15400 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
15401 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15402 gen_rtx_REG (Pmode,
15403 LINK_REGISTER_REGNUM));
15405 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
15406 /* The instruction pattern requires a clobber here;
15407 it is shared with the restVEC helper. */
15409 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
15412 /* CR register traditionally saved as CR2. */
15413 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15414 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15415 GEN_INT (info->cr_save_offset));
15416 rtx mem = gen_frame_mem (reg_mode, addr);
15418 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15421 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15423 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15424 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15425 GEN_INT (info->gp_save_offset
15427 rtx mem = gen_frame_mem (reg_mode, addr);
15429 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15431 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15433 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15434 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15435 GEN_INT (info->altivec_save_offset
15437 rtx mem = gen_frame_mem (V4SImode, addr);
15439 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15441 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
15443 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15444 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15445 GEN_INT (info->fp_save_offset
15447 rtx mem = gen_frame_mem (DFmode, addr);
15449 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15452 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
15454 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
15456 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
15458 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
15460 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
15461 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15466 /* Set sp_offset based on the stack push from the prologue. */
15467 if (info->total_size < 32767)
15468 sp_offset = info->total_size;
15470 /* Restore AltiVec registers if needed. */
15471 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15475 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15476 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15478 rtx addr, areg, mem;
15480 areg = gen_rtx_REG (Pmode, 0);
15482 (areg, GEN_INT (info->altivec_save_offset
15484 + 16 * (i - info->first_altivec_reg_save)));
15486 /* AltiVec addressing mode is [reg+reg]. */
15487 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
15488 mem = gen_frame_mem (V4SImode, addr);
15490 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
15494 /* Restore VRSAVE if needed. */
15495 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15496 && info->vrsave_mask != 0)
15498 rtx addr, mem, reg;
15500 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15501 GEN_INT (info->vrsave_save_offset + sp_offset));
15502 mem = gen_frame_mem (SImode, addr);
15503 reg = gen_rtx_REG (SImode, 12);
15504 emit_move_insn (reg, mem);
15506 emit_insn (generate_set_vrsave (reg, info, 1));
15511 /* If we have a frame pointer, a call to alloca, or a large stack
15512 frame, restore the old stack pointer using the backchain. Otherwise,
15513 we know what size to update it with. */
15514 if (use_backchain_to_restore_sp)
15516 /* Under V.4, don't reset the stack pointer until after we're done
15517 loading the saved registers. */
15518 if (DEFAULT_ABI == ABI_V4)
15519 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
15521 emit_move_insn (frame_reg_rtx,
15522 gen_rtx_MEM (Pmode, sp_reg_rtx));
15524 else if (info->push_p)
15526 if (DEFAULT_ABI == ABI_V4
15527 || current_function_calls_eh_return)
15528 sp_offset = info->total_size;
15531 emit_insn (TARGET_32BIT
15532 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15533 GEN_INT (info->total_size))
15534 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15535 GEN_INT (info->total_size)));
15539 /* Get the old lr if we saved it. */
15540 if (info->lr_save_p)
15542 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
15543 info->lr_save_offset + sp_offset);
15545 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
15548 /* Get the old cr if we saved it. */
15549 if (info->cr_save_p)
15551 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15552 GEN_INT (info->cr_save_offset + sp_offset));
15553 rtx mem = gen_frame_mem (SImode, addr);
15555 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
15558 /* Set LR here to try to overlap restores below. */
15559 if (info->lr_save_p)
15560 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
15561 gen_rtx_REG (Pmode, 0));
15563 /* Load exception handler data registers, if needed. */
15564 if (current_function_calls_eh_return)
15566 unsigned int i, regno;
15570 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15571 GEN_INT (sp_offset + 5 * reg_size));
15572 rtx mem = gen_frame_mem (reg_mode, addr);
15574 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15581 regno = EH_RETURN_DATA_REGNO (i);
15582 if (regno == INVALID_REGNUM)
15585 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15586 info->ehrd_offset + sp_offset
15587 + reg_size * (int) i);
15589 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15593 /* Restore GPRs. This is done as a PARALLEL if we are using
15594 the load-multiple instructions. */
15595 if (using_load_multiple)
15598 p = rtvec_alloc (32 - info->first_gp_reg_save);
15599 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15601 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15602 GEN_INT (info->gp_save_offset
15605 rtx mem = gen_frame_mem (reg_mode, addr);
15608 gen_rtx_SET (VOIDmode,
15609 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15612 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15614 else if (TARGET_SPE_ABI
15615 && info->spe_64bit_regs_used != 0
15616 && info->first_gp_reg_save != 32)
15618 rtx spe_save_area_ptr;
15619 /* Determine whether we can address all of the registers that need
15620 to be saved with an offset from the stack pointer that fits in
15621 the small const field for SPE memory instructions. */
15622 int spe_regs_addressable_via_sp
15623 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15624 + (32 - info->first_gp_reg_save - 1) * reg_size);
15627 if (spe_regs_addressable_via_sp)
15629 spe_save_area_ptr = frame_reg_rtx;
15630 spe_offset = info->spe_gp_save_offset + sp_offset;
15634 /* Make r11 point to the start of the SPE save area. We worried about
15635 not clobbering it when we were saving registers in the prologue.
15636 There's no need to worry here because the static chain is passed
15637 anew to every function. */
15638 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15640 emit_insn (gen_addsi3 (spe_save_area_ptr, frame_reg_rtx,
15641 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15646 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15647 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15649 rtx offset, addr, mem;
15651 /* We're doing all this to ensure that the immediate offset
15652 fits into the immediate field of 'evldd'. */
15653 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
15655 offset = GEN_INT (spe_offset + reg_size * i);
15656 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15657 mem = gen_rtx_MEM (V2SImode, addr);
15659 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15664 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15665 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15667 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15668 GEN_INT (info->gp_save_offset
15671 rtx mem = gen_frame_mem (reg_mode, addr);
15673 emit_move_insn (gen_rtx_REG (reg_mode,
15674 info->first_gp_reg_save + i), mem);
15677 /* Restore fpr's if we need to do it without calling a function. */
15678 if (restoring_FPRs_inline)
15679 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15680 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15681 && ! call_used_regs[info->first_fp_reg_save+i]))
15684 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15685 GEN_INT (info->fp_save_offset
15688 mem = gen_frame_mem (DFmode, addr);
15690 emit_move_insn (gen_rtx_REG (DFmode,
15691 info->first_fp_reg_save + i),
15695 /* If we saved cr, restore it here. Just those that were used. */
15696 if (info->cr_save_p)
15698 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15701 if (using_mtcr_multiple)
15703 for (i = 0; i < 8; i++)
15704 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15706 gcc_assert (count);
15709 if (using_mtcr_multiple && count > 1)
15714 p = rtvec_alloc (count);
15717 for (i = 0; i < 8; i++)
15718 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15720 rtvec r = rtvec_alloc (2);
15721 RTVEC_ELT (r, 0) = r12_rtx;
15722 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15723 RTVEC_ELT (p, ndx) =
15724 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15725 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15728 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15729 gcc_assert (ndx == count);
15732 for (i = 0; i < 8; i++)
15733 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15735 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15741 /* If this is V.4, unwind the stack pointer after all of the loads
15743 if (frame_reg_rtx != sp_reg_rtx)
15745 /* This blockage is needed so that sched doesn't decide to move
15746 the sp change before the register restores. */
15747 rs6000_emit_stack_tie ();
15749 && info->spe_64bit_regs_used != 0
15750 && info->first_gp_reg_save != 32)
15751 emit_insn (gen_addsi3 (sp_reg_rtx, gen_rtx_REG (Pmode, 11),
15752 GEN_INT (-(info->spe_gp_save_offset + sp_offset))));
15754 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15756 else if (sp_offset != 0)
15757 emit_insn (TARGET_32BIT
15758 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15759 GEN_INT (sp_offset))
15760 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15761 GEN_INT (sp_offset)));
15763 if (current_function_calls_eh_return)
15765 rtx sa = EH_RETURN_STACKADJ_RTX;
15766 emit_insn (TARGET_32BIT
15767 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15768 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15774 if (! restoring_FPRs_inline)
15775 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15777 p = rtvec_alloc (2);
15779 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15780 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15781 gen_rtx_REG (Pmode,
15782 LINK_REGISTER_REGNUM));
15784 /* If we have to restore more than two FP registers, branch to the
15785 restore function. It will return to our caller. */
15786 if (! restoring_FPRs_inline)
15790 const char *alloc_rname;
15792 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15793 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15794 alloc_rname = ggc_strdup (rname);
15795 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15796 gen_rtx_SYMBOL_REF (Pmode,
15799 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15802 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15803 GEN_INT (info->fp_save_offset + 8*i));
15804 mem = gen_frame_mem (DFmode, addr);
15806 RTVEC_ELT (p, i+3) =
15807 gen_rtx_SET (VOIDmode,
15808 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15813 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15817 /* Write function epilogue. */
15820 rs6000_output_function_epilogue (FILE *file,
15821 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15823 if (! HAVE_epilogue)
15825 rtx insn = get_last_insn ();
15826 /* If the last insn was a BARRIER, we don't have to write anything except
15827 the trace table. */
15828 if (GET_CODE (insn) == NOTE)
15829 insn = prev_nonnote_insn (insn);
15830 if (insn == 0 || GET_CODE (insn) != BARRIER)
15832 /* This is slightly ugly, but at least we don't have two
15833 copies of the epilogue-emitting code. */
15836 /* A NOTE_INSN_DELETED is supposed to be at the start
15837 and end of the "toplevel" insn chain. */
15838 emit_note (NOTE_INSN_DELETED);
15839 rs6000_emit_epilogue (FALSE);
15840 emit_note (NOTE_INSN_DELETED);
15842 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15846 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15848 INSN_ADDRESSES_NEW (insn, addr);
15853 if (TARGET_DEBUG_STACK)
15854 debug_rtx_list (get_insns (), 100);
15855 final (get_insns (), file, FALSE);
15861 macho_branch_islands ();
15862 /* Mach-O doesn't support labels at the end of objects, so if
15863 it looks like we might want one, insert a NOP. */
15865 rtx insn = get_last_insn ();
15868 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
15869 insn = PREV_INSN (insn);
15873 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
15874 fputs ("\tnop\n", file);
15878 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15881 We don't output a traceback table if -finhibit-size-directive was
15882 used. The documentation for -finhibit-size-directive reads
15883 ``don't output a @code{.size} assembler directive, or anything
15884 else that would cause trouble if the function is split in the
15885 middle, and the two halves are placed at locations far apart in
15886 memory.'' The traceback table has this property, since it
15887 includes the offset from the start of the function to the
15888 traceback table itself.
15890 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15891 different traceback table. */
15892 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15893 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15895 const char *fname = NULL;
15896 const char *language_string = lang_hooks.name;
15897 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15899 int optional_tbtab;
15900 rs6000_stack_t *info = rs6000_stack_info ();
15902 if (rs6000_traceback == traceback_full)
15903 optional_tbtab = 1;
15904 else if (rs6000_traceback == traceback_part)
15905 optional_tbtab = 0;
15907 optional_tbtab = !optimize_size && !TARGET_ELF;
15909 if (optional_tbtab)
15911 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15912 while (*fname == '.') /* V.4 encodes . in the name */
15915 /* Need label immediately before tbtab, so we can compute
15916 its offset from the function start. */
15917 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15918 ASM_OUTPUT_LABEL (file, fname);
15921 /* The .tbtab pseudo-op can only be used for the first eight
15922 expressions, since it can't handle the possibly variable
15923 length fields that follow. However, if you omit the optional
15924 fields, the assembler outputs zeros for all optional fields
15925 anyways, giving each variable length field is minimum length
15926 (as defined in sys/debug.h). Thus we can not use the .tbtab
15927 pseudo-op at all. */
15929 /* An all-zero word flags the start of the tbtab, for debuggers
15930 that have to find it by searching forward from the entry
15931 point or from the current pc. */
15932 fputs ("\t.long 0\n", file);
15934 /* Tbtab format type. Use format type 0. */
15935 fputs ("\t.byte 0,", file);
15937 /* Language type. Unfortunately, there does not seem to be any
15938 official way to discover the language being compiled, so we
15939 use language_string.
15940 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15941 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
15942 a number, so for now use 9. */
15943 if (! strcmp (language_string, "GNU C"))
15945 else if (! strcmp (language_string, "GNU F77")
15946 || ! strcmp (language_string, "GNU F95"))
15948 else if (! strcmp (language_string, "GNU Pascal"))
15950 else if (! strcmp (language_string, "GNU Ada"))
15952 else if (! strcmp (language_string, "GNU C++")
15953 || ! strcmp (language_string, "GNU Objective-C++"))
15955 else if (! strcmp (language_string, "GNU Java"))
15957 else if (! strcmp (language_string, "GNU Objective-C"))
15960 gcc_unreachable ();
15961 fprintf (file, "%d,", i);
15963 /* 8 single bit fields: global linkage (not set for C extern linkage,
15964 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15965 from start of procedure stored in tbtab, internal function, function
15966 has controlled storage, function has no toc, function uses fp,
15967 function logs/aborts fp operations. */
15968 /* Assume that fp operations are used if any fp reg must be saved. */
15969 fprintf (file, "%d,",
15970 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15972 /* 6 bitfields: function is interrupt handler, name present in
15973 proc table, function calls alloca, on condition directives
15974 (controls stack walks, 3 bits), saves condition reg, saves
15976 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15977 set up as a frame pointer, even when there is no alloca call. */
15978 fprintf (file, "%d,",
15979 ((optional_tbtab << 6)
15980 | ((optional_tbtab & frame_pointer_needed) << 5)
15981 | (info->cr_save_p << 1)
15982 | (info->lr_save_p)));
15984 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15986 fprintf (file, "%d,",
15987 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15989 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15990 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15992 if (optional_tbtab)
15994 /* Compute the parameter info from the function decl argument
15997 int next_parm_info_bit = 31;
15999 for (decl = DECL_ARGUMENTS (current_function_decl);
16000 decl; decl = TREE_CHAIN (decl))
16002 rtx parameter = DECL_INCOMING_RTL (decl);
16003 enum machine_mode mode = GET_MODE (parameter);
16005 if (GET_CODE (parameter) == REG)
16007 if (SCALAR_FLOAT_MODE_P (mode))
16027 gcc_unreachable ();
16030 /* If only one bit will fit, don't or in this entry. */
16031 if (next_parm_info_bit > 0)
16032 parm_info |= (bits << (next_parm_info_bit - 1));
16033 next_parm_info_bit -= 2;
16037 fixed_parms += ((GET_MODE_SIZE (mode)
16038 + (UNITS_PER_WORD - 1))
16040 next_parm_info_bit -= 1;
16046 /* Number of fixed point parameters. */
16047 /* This is actually the number of words of fixed point parameters; thus
16048 an 8 byte struct counts as 2; and thus the maximum value is 8. */
16049 fprintf (file, "%d,", fixed_parms);
16051 /* 2 bitfields: number of floating point parameters (7 bits), parameters
16053 /* This is actually the number of fp registers that hold parameters;
16054 and thus the maximum value is 13. */
16055 /* Set parameters on stack bit if parameters are not in their original
16056 registers, regardless of whether they are on the stack? Xlc
16057 seems to set the bit when not optimizing. */
16058 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
16060 if (! optional_tbtab)
16063 /* Optional fields follow. Some are variable length. */
16065 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
16066 11 double float. */
16067 /* There is an entry for each parameter in a register, in the order that
16068 they occur in the parameter list. Any intervening arguments on the
16069 stack are ignored. If the list overflows a long (max possible length
16070 34 bits) then completely leave off all elements that don't fit. */
16071 /* Only emit this long if there was at least one parameter. */
16072 if (fixed_parms || float_parms)
16073 fprintf (file, "\t.long %d\n", parm_info);
16075 /* Offset from start of code to tb table. */
16076 fputs ("\t.long ", file);
16077 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16079 RS6000_OUTPUT_BASENAME (file, fname);
16081 assemble_name (file, fname);
16083 rs6000_output_function_entry (file, fname);
16086 /* Interrupt handler mask. */
16087 /* Omit this long, since we never set the interrupt handler bit
16090 /* Number of CTL (controlled storage) anchors. */
16091 /* Omit this long, since the has_ctl bit is never set above. */
16093 /* Displacement into stack of each CTL anchor. */
16094 /* Omit this list of longs, because there are no CTL anchors. */
16096 /* Length of function name. */
16099 fprintf (file, "\t.short %d\n", (int) strlen (fname));
16101 /* Function name. */
16102 assemble_string (fname, strlen (fname));
16104 /* Register for alloca automatic storage; this is always reg 31.
16105 Only emit this if the alloca bit was set above. */
16106 if (frame_pointer_needed)
16107 fputs ("\t.byte 31\n", file);
16109 fputs ("\t.align 2\n", file);
16113 /* A C compound statement that outputs the assembler code for a thunk
16114 function, used to implement C++ virtual function calls with
16115 multiple inheritance. The thunk acts as a wrapper around a virtual
16116 function, adjusting the implicit object parameter before handing
16117 control off to the real function.
16119 First, emit code to add the integer DELTA to the location that
16120 contains the incoming first argument. Assume that this argument
16121 contains a pointer, and is the one used to pass the `this' pointer
16122 in C++. This is the incoming argument *before* the function
16123 prologue, e.g. `%o0' on a sparc. The addition must preserve the
16124 values of all other incoming arguments.
16126 After the addition, emit code to jump to FUNCTION, which is a
16127 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
16128 not touch the return address. Hence returning from FUNCTION will
16129 return to whoever called the current `thunk'.
16131 The effect must be as if FUNCTION had been called directly with the
16132 adjusted first argument. This macro is responsible for emitting
16133 all of the code for a thunk function; output_function_prologue()
16134 and output_function_epilogue() are not invoked.
16136 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
16137 been extracted from it.) It might possibly be useful on some
16138 targets, but probably not.
16140 If you do not define this macro, the target-independent code in the
16141 C++ frontend will generate a less efficient heavyweight thunk that
16142 calls FUNCTION instead of jumping to it. The generic approach does
16143 not support varargs. */
16146 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16147 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16150 rtx this, insn, funexp;
16152 reload_completed = 1;
16153 epilogue_completed = 1;
16155 /* Mark the end of the (empty) prologue. */
16156 emit_note (NOTE_INSN_PROLOGUE_END);
16158 /* Find the "this" pointer. If the function returns a structure,
16159 the structure return pointer is in r3. */
16160 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16161 this = gen_rtx_REG (Pmode, 4);
16163 this = gen_rtx_REG (Pmode, 3);
16165 /* Apply the constant offset, if required. */
16168 rtx delta_rtx = GEN_INT (delta);
16169 emit_insn (TARGET_32BIT
16170 ? gen_addsi3 (this, this, delta_rtx)
16171 : gen_adddi3 (this, this, delta_rtx));
16174 /* Apply the offset from the vtable, if required. */
16177 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
16178 rtx tmp = gen_rtx_REG (Pmode, 12);
16180 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
16181 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
16183 emit_insn (TARGET_32BIT
16184 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
16185 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
16186 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
16190 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
16192 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
16194 emit_insn (TARGET_32BIT
16195 ? gen_addsi3 (this, this, tmp)
16196 : gen_adddi3 (this, this, tmp));
16199 /* Generate a tail call to the target function. */
16200 if (!TREE_USED (function))
16202 assemble_external (function);
16203 TREE_USED (function) = 1;
16205 funexp = XEXP (DECL_RTL (function), 0);
16206 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
16209 if (MACHOPIC_INDIRECT)
16210 funexp = machopic_indirect_call_target (funexp);
16213 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
16214 generate sibcall RTL explicitly. */
16215 insn = emit_call_insn (
16216 gen_rtx_PARALLEL (VOIDmode,
16218 gen_rtx_CALL (VOIDmode,
16219 funexp, const0_rtx),
16220 gen_rtx_USE (VOIDmode, const0_rtx),
16221 gen_rtx_USE (VOIDmode,
16222 gen_rtx_REG (SImode,
16223 LINK_REGISTER_REGNUM)),
16224 gen_rtx_RETURN (VOIDmode))));
16225 SIBLING_CALL_P (insn) = 1;
16228 /* Run just enough of rest_of_compilation to get the insns emitted.
16229 There's not really enough bulk here to make other passes such as
16230 instruction scheduling worth while. Note that use_thunk calls
16231 assemble_start_function and assemble_end_function. */
16232 insn = get_insns ();
16233 insn_locators_alloc ();
16234 shorten_branches (insn);
16235 final_start_function (insn, file, 1);
16236 final (insn, file, 1);
16237 final_end_function ();
16239 reload_completed = 0;
16240 epilogue_completed = 0;
16243 /* A quick summary of the various types of 'constant-pool tables'
16246 Target Flags Name One table per
16247 AIX (none) AIX TOC object file
16248 AIX -mfull-toc AIX TOC object file
16249 AIX -mminimal-toc AIX minimal TOC translation unit
16250 SVR4/EABI (none) SVR4 SDATA object file
16251 SVR4/EABI -fpic SVR4 pic object file
16252 SVR4/EABI -fPIC SVR4 PIC translation unit
16253 SVR4/EABI -mrelocatable EABI TOC function
16254 SVR4/EABI -maix AIX TOC object file
16255 SVR4/EABI -maix -mminimal-toc
16256 AIX minimal TOC translation unit
16258 Name Reg. Set by entries contains:
16259 made by addrs? fp? sum?
16261 AIX TOC 2 crt0 as Y option option
16262 AIX minimal TOC 30 prolog gcc Y Y option
16263 SVR4 SDATA 13 crt0 gcc N Y N
16264 SVR4 pic 30 prolog ld Y not yet N
16265 SVR4 PIC 30 prolog gcc Y option option
16266 EABI TOC 30 prolog gcc Y option option
16270 /* Hash functions for the hash table. */
16273 rs6000_hash_constant (rtx k)
16275 enum rtx_code code = GET_CODE (k);
16276 enum machine_mode mode = GET_MODE (k);
16277 unsigned result = (code << 3) ^ mode;
16278 const char *format;
16281 format = GET_RTX_FORMAT (code);
16282 flen = strlen (format);
16288 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
16291 if (mode != VOIDmode)
16292 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
16304 for (; fidx < flen; fidx++)
16305 switch (format[fidx])
16310 const char *str = XSTR (k, fidx);
16311 len = strlen (str);
16312 result = result * 613 + len;
16313 for (i = 0; i < len; i++)
16314 result = result * 613 + (unsigned) str[i];
16319 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
16323 result = result * 613 + (unsigned) XINT (k, fidx);
16326 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
16327 result = result * 613 + (unsigned) XWINT (k, fidx);
16331 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
16332 result = result * 613 + (unsigned) (XWINT (k, fidx)
16339 gcc_unreachable ();
16346 toc_hash_function (const void *hash_entry)
16348 const struct toc_hash_struct *thc =
16349 (const struct toc_hash_struct *) hash_entry;
16350 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
16353 /* Compare H1 and H2 for equivalence. */
16356 toc_hash_eq (const void *h1, const void *h2)
16358 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
16359 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
16361 if (((const struct toc_hash_struct *) h1)->key_mode
16362 != ((const struct toc_hash_struct *) h2)->key_mode)
16365 return rtx_equal_p (r1, r2);
16368 /* These are the names given by the C++ front-end to vtables, and
16369 vtable-like objects. Ideally, this logic should not be here;
16370 instead, there should be some programmatic way of inquiring as
16371 to whether or not an object is a vtable. */
16373 #define VTABLE_NAME_P(NAME) \
16374 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16375 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16376 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16377 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16378 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16381 rs6000_output_symbol_ref (FILE *file, rtx x)
16383 /* Currently C++ toc references to vtables can be emitted before it
16384 is decided whether the vtable is public or private. If this is
16385 the case, then the linker will eventually complain that there is
16386 a reference to an unknown section. Thus, for vtables only,
16387 we emit the TOC reference to reference the symbol and not the
16389 const char *name = XSTR (x, 0);
16391 if (VTABLE_NAME_P (name))
16393 RS6000_OUTPUT_BASENAME (file, name);
16396 assemble_name (file, name);
16399 /* Output a TOC entry. We derive the entry name from what is being
16403 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
16406 const char *name = buf;
16407 const char *real_name;
16409 HOST_WIDE_INT offset = 0;
16411 gcc_assert (!TARGET_NO_TOC);
16413 /* When the linker won't eliminate them, don't output duplicate
16414 TOC entries (this happens on AIX if there is any kind of TOC,
16415 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
16417 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
16419 struct toc_hash_struct *h;
16422 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
16423 time because GGC is not initialized at that point. */
16424 if (toc_hash_table == NULL)
16425 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
16426 toc_hash_eq, NULL);
16428 h = ggc_alloc (sizeof (*h));
16430 h->key_mode = mode;
16431 h->labelno = labelno;
16433 found = htab_find_slot (toc_hash_table, h, 1);
16434 if (*found == NULL)
16436 else /* This is indeed a duplicate.
16437 Set this label equal to that label. */
16439 fputs ("\t.set ", file);
16440 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16441 fprintf (file, "%d,", labelno);
16442 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16443 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
16449 /* If we're going to put a double constant in the TOC, make sure it's
16450 aligned properly when strict alignment is on. */
16451 if (GET_CODE (x) == CONST_DOUBLE
16452 && STRICT_ALIGNMENT
16453 && GET_MODE_BITSIZE (mode) >= 64
16454 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
16455 ASM_OUTPUT_ALIGN (file, 3);
16458 (*targetm.asm_out.internal_label) (file, "LC", labelno);
16460 /* Handle FP constants specially. Note that if we have a minimal
16461 TOC, things we put here aren't actually in the TOC, so we can allow
16463 if (GET_CODE (x) == CONST_DOUBLE &&
16464 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
16466 REAL_VALUE_TYPE rv;
16469 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16470 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16471 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
16473 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
16477 if (TARGET_MINIMAL_TOC)
16478 fputs (DOUBLE_INT_ASM_OP, file);
16480 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16481 k[0] & 0xffffffff, k[1] & 0xffffffff,
16482 k[2] & 0xffffffff, k[3] & 0xffffffff);
16483 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
16484 k[0] & 0xffffffff, k[1] & 0xffffffff,
16485 k[2] & 0xffffffff, k[3] & 0xffffffff);
16490 if (TARGET_MINIMAL_TOC)
16491 fputs ("\t.long ", file);
16493 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16494 k[0] & 0xffffffff, k[1] & 0xffffffff,
16495 k[2] & 0xffffffff, k[3] & 0xffffffff);
16496 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
16497 k[0] & 0xffffffff, k[1] & 0xffffffff,
16498 k[2] & 0xffffffff, k[3] & 0xffffffff);
16502 else if (GET_CODE (x) == CONST_DOUBLE &&
16503 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
16505 REAL_VALUE_TYPE rv;
16508 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16510 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16511 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
16513 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
16517 if (TARGET_MINIMAL_TOC)
16518 fputs (DOUBLE_INT_ASM_OP, file);
16520 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16521 k[0] & 0xffffffff, k[1] & 0xffffffff);
16522 fprintf (file, "0x%lx%08lx\n",
16523 k[0] & 0xffffffff, k[1] & 0xffffffff);
16528 if (TARGET_MINIMAL_TOC)
16529 fputs ("\t.long ", file);
16531 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16532 k[0] & 0xffffffff, k[1] & 0xffffffff);
16533 fprintf (file, "0x%lx,0x%lx\n",
16534 k[0] & 0xffffffff, k[1] & 0xffffffff);
16538 else if (GET_CODE (x) == CONST_DOUBLE &&
16539 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
16541 REAL_VALUE_TYPE rv;
16544 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16545 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16546 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
16548 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
16552 if (TARGET_MINIMAL_TOC)
16553 fputs (DOUBLE_INT_ASM_OP, file);
16555 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16556 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
16561 if (TARGET_MINIMAL_TOC)
16562 fputs ("\t.long ", file);
16564 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16565 fprintf (file, "0x%lx\n", l & 0xffffffff);
16569 else if (GET_MODE (x) == VOIDmode
16570 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
16572 unsigned HOST_WIDE_INT low;
16573 HOST_WIDE_INT high;
16575 if (GET_CODE (x) == CONST_DOUBLE)
16577 low = CONST_DOUBLE_LOW (x);
16578 high = CONST_DOUBLE_HIGH (x);
16581 #if HOST_BITS_PER_WIDE_INT == 32
16584 high = (low & 0x80000000) ? ~0 : 0;
16588 low = INTVAL (x) & 0xffffffff;
16589 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
16593 /* TOC entries are always Pmode-sized, but since this
16594 is a bigendian machine then if we're putting smaller
16595 integer constants in the TOC we have to pad them.
16596 (This is still a win over putting the constants in
16597 a separate constant pool, because then we'd have
16598 to have both a TOC entry _and_ the actual constant.)
16600 For a 32-bit target, CONST_INT values are loaded and shifted
16601 entirely within `low' and can be stored in one TOC entry. */
16603 /* It would be easy to make this work, but it doesn't now. */
16604 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
16606 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
16608 #if HOST_BITS_PER_WIDE_INT == 32
16609 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
16610 POINTER_SIZE, &low, &high, 0);
16613 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16614 high = (HOST_WIDE_INT) low >> 32;
16621 if (TARGET_MINIMAL_TOC)
16622 fputs (DOUBLE_INT_ASM_OP, file);
16624 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16625 (long) high & 0xffffffff, (long) low & 0xffffffff);
16626 fprintf (file, "0x%lx%08lx\n",
16627 (long) high & 0xffffffff, (long) low & 0xffffffff);
16632 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16634 if (TARGET_MINIMAL_TOC)
16635 fputs ("\t.long ", file);
16637 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16638 (long) high & 0xffffffff, (long) low & 0xffffffff);
16639 fprintf (file, "0x%lx,0x%lx\n",
16640 (long) high & 0xffffffff, (long) low & 0xffffffff);
16644 if (TARGET_MINIMAL_TOC)
16645 fputs ("\t.long ", file);
16647 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16648 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16654 if (GET_CODE (x) == CONST)
16656 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16658 base = XEXP (XEXP (x, 0), 0);
16659 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16662 switch (GET_CODE (base))
16665 name = XSTR (base, 0);
16669 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16670 CODE_LABEL_NUMBER (XEXP (base, 0)));
16674 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16678 gcc_unreachable ();
16681 real_name = (*targetm.strip_name_encoding) (name);
16682 if (TARGET_MINIMAL_TOC)
16683 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16686 fprintf (file, "\t.tc %s", real_name);
16689 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16691 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16693 fputs ("[TC],", file);
16696 /* Currently C++ toc references to vtables can be emitted before it
16697 is decided whether the vtable is public or private. If this is
16698 the case, then the linker will eventually complain that there is
16699 a TOC reference to an unknown section. Thus, for vtables only,
16700 we emit the TOC reference to reference the symbol and not the
16702 if (VTABLE_NAME_P (name))
16704 RS6000_OUTPUT_BASENAME (file, name);
16706 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16707 else if (offset > 0)
16708 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16711 output_addr_const (file, x);
16715 /* Output an assembler pseudo-op to write an ASCII string of N characters
16716 starting at P to FILE.
16718 On the RS/6000, we have to do this using the .byte operation and
16719 write out special characters outside the quoted string.
16720 Also, the assembler is broken; very long strings are truncated,
16721 so we must artificially break them up early. */
16724 output_ascii (FILE *file, const char *p, int n)
16727 int i, count_string;
16728 const char *for_string = "\t.byte \"";
16729 const char *for_decimal = "\t.byte ";
16730 const char *to_close = NULL;
16733 for (i = 0; i < n; i++)
16736 if (c >= ' ' && c < 0177)
16739 fputs (for_string, file);
16742 /* Write two quotes to get one. */
16750 for_decimal = "\"\n\t.byte ";
16754 if (count_string >= 512)
16756 fputs (to_close, file);
16758 for_string = "\t.byte \"";
16759 for_decimal = "\t.byte ";
16767 fputs (for_decimal, file);
16768 fprintf (file, "%d", c);
16770 for_string = "\n\t.byte \"";
16771 for_decimal = ", ";
16777 /* Now close the string if we have written one. Then end the line. */
16779 fputs (to_close, file);
16782 /* Generate a unique section name for FILENAME for a section type
16783 represented by SECTION_DESC. Output goes into BUF.
16785 SECTION_DESC can be any string, as long as it is different for each
16786 possible section type.
16788 We name the section in the same manner as xlc. The name begins with an
16789 underscore followed by the filename (after stripping any leading directory
16790 names) with the last period replaced by the string SECTION_DESC. If
16791 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16795 rs6000_gen_section_name (char **buf, const char *filename,
16796 const char *section_desc)
16798 const char *q, *after_last_slash, *last_period = 0;
16802 after_last_slash = filename;
16803 for (q = filename; *q; q++)
16806 after_last_slash = q + 1;
16807 else if (*q == '.')
16811 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16812 *buf = (char *) xmalloc (len);
16817 for (q = after_last_slash; *q; q++)
16819 if (q == last_period)
16821 strcpy (p, section_desc);
16822 p += strlen (section_desc);
16826 else if (ISALNUM (*q))
16830 if (last_period == 0)
16831 strcpy (p, section_desc);
16836 /* Emit profile function. */
16839 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16841 /* Non-standard profiling for kernels, which just saves LR then calls
16842 _mcount without worrying about arg saves. The idea is to change
16843 the function prologue as little as possible as it isn't easy to
16844 account for arg save/restore code added just for _mcount. */
16845 if (TARGET_PROFILE_KERNEL)
16848 if (DEFAULT_ABI == ABI_AIX)
16850 #ifndef NO_PROFILE_COUNTERS
16851 # define NO_PROFILE_COUNTERS 0
16853 if (NO_PROFILE_COUNTERS)
16854 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16858 const char *label_name;
16861 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16862 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16863 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16865 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16869 else if (DEFAULT_ABI == ABI_DARWIN)
16871 const char *mcount_name = RS6000_MCOUNT;
16872 int caller_addr_regno = LINK_REGISTER_REGNUM;
16874 /* Be conservative and always set this, at least for now. */
16875 current_function_uses_pic_offset_table = 1;
16878 /* For PIC code, set up a stub and collect the caller's address
16879 from r0, which is where the prologue puts it. */
16880 if (MACHOPIC_INDIRECT
16881 && current_function_uses_pic_offset_table)
16882 caller_addr_regno = 0;
16884 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16886 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16890 /* Write function profiler code. */
16893 output_function_profiler (FILE *file, int labelno)
16897 switch (DEFAULT_ABI)
16900 gcc_unreachable ();
16905 warning (0, "no profiling of 64-bit code for this ABI");
16908 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16909 fprintf (file, "\tmflr %s\n", reg_names[0]);
16910 if (NO_PROFILE_COUNTERS)
16912 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16913 reg_names[0], reg_names[1]);
16915 else if (TARGET_SECURE_PLT && flag_pic)
16917 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16918 reg_names[0], reg_names[1]);
16919 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16920 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16921 reg_names[12], reg_names[12]);
16922 assemble_name (file, buf);
16923 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16924 assemble_name (file, buf);
16925 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16927 else if (flag_pic == 1)
16929 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16930 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16931 reg_names[0], reg_names[1]);
16932 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16933 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16934 assemble_name (file, buf);
16935 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16937 else if (flag_pic > 1)
16939 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16940 reg_names[0], reg_names[1]);
16941 /* Now, we need to get the address of the label. */
16942 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16943 assemble_name (file, buf);
16944 fputs ("-.\n1:", file);
16945 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16946 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16947 reg_names[0], reg_names[11]);
16948 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16949 reg_names[0], reg_names[0], reg_names[11]);
16953 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16954 assemble_name (file, buf);
16955 fputs ("@ha\n", file);
16956 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16957 reg_names[0], reg_names[1]);
16958 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16959 assemble_name (file, buf);
16960 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16963 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16964 fprintf (file, "\tbl %s%s\n",
16965 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16970 if (!TARGET_PROFILE_KERNEL)
16972 /* Don't do anything, done in output_profile_hook (). */
16976 gcc_assert (!TARGET_32BIT);
16978 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16979 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16981 if (cfun->static_chain_decl != NULL)
16983 asm_fprintf (file, "\tstd %s,24(%s)\n",
16984 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16985 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16986 asm_fprintf (file, "\tld %s,24(%s)\n",
16987 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16990 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16998 /* The following variable value is the last issued insn. */
17000 static rtx last_scheduled_insn;
17002 /* The following variable helps to balance issuing of load and
17003 store instructions */
17005 static int load_store_pendulum;
17007 /* Power4 load update and store update instructions are cracked into a
17008 load or store and an integer insn which are executed in the same cycle.
17009 Branches have their own dispatch slot which does not count against the
17010 GCC issue rate, but it changes the program flow so there are no other
17011 instructions to issue in this cycle. */
17014 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
17015 int verbose ATTRIBUTE_UNUSED,
17016 rtx insn, int more)
17018 last_scheduled_insn = insn;
17019 if (GET_CODE (PATTERN (insn)) == USE
17020 || GET_CODE (PATTERN (insn)) == CLOBBER)
17022 cached_can_issue_more = more;
17023 return cached_can_issue_more;
17026 if (insn_terminates_group_p (insn, current_group))
17028 cached_can_issue_more = 0;
17029 return cached_can_issue_more;
17032 /* If no reservation, but reach here */
17033 if (recog_memoized (insn) < 0)
17036 if (rs6000_sched_groups)
17038 if (is_microcoded_insn (insn))
17039 cached_can_issue_more = 0;
17040 else if (is_cracked_insn (insn))
17041 cached_can_issue_more = more > 2 ? more - 2 : 0;
17043 cached_can_issue_more = more - 1;
17045 return cached_can_issue_more;
17048 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
17051 cached_can_issue_more = more - 1;
17052 return cached_can_issue_more;
17055 /* Adjust the cost of a scheduling dependency. Return the new cost of
17056 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
17059 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
17061 enum attr_type attr_type;
17063 if (! recog_memoized (insn))
17066 switch (REG_NOTE_KIND (link))
17070 /* Data dependency; DEP_INSN writes a register that INSN reads
17071 some cycles later. */
17073 /* Separate a load from a narrower, dependent store. */
17074 if (rs6000_sched_groups
17075 && GET_CODE (PATTERN (insn)) == SET
17076 && GET_CODE (PATTERN (dep_insn)) == SET
17077 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
17078 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
17079 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
17080 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
17083 attr_type = get_attr_type (insn);
17088 /* Tell the first scheduling pass about the latency between
17089 a mtctr and bctr (and mtlr and br/blr). The first
17090 scheduling pass will not know about this latency since
17091 the mtctr instruction, which has the latency associated
17092 to it, will be generated by reload. */
17093 return TARGET_POWER ? 5 : 4;
17095 /* Leave some extra cycles between a compare and its
17096 dependent branch, to inhibit expensive mispredicts. */
17097 if ((rs6000_cpu_attr == CPU_PPC603
17098 || rs6000_cpu_attr == CPU_PPC604
17099 || rs6000_cpu_attr == CPU_PPC604E
17100 || rs6000_cpu_attr == CPU_PPC620
17101 || rs6000_cpu_attr == CPU_PPC630
17102 || rs6000_cpu_attr == CPU_PPC750
17103 || rs6000_cpu_attr == CPU_PPC7400
17104 || rs6000_cpu_attr == CPU_PPC7450
17105 || rs6000_cpu_attr == CPU_POWER4
17106 || rs6000_cpu_attr == CPU_POWER5
17107 || rs6000_cpu_attr == CPU_CELL)
17108 && recog_memoized (dep_insn)
17109 && (INSN_CODE (dep_insn) >= 0))
17111 switch (get_attr_type (dep_insn))
17115 case TYPE_DELAYED_COMPARE:
17116 case TYPE_IMUL_COMPARE:
17117 case TYPE_LMUL_COMPARE:
17118 case TYPE_FPCOMPARE:
17119 case TYPE_CR_LOGICAL:
17120 case TYPE_DELAYED_CR:
17129 case TYPE_STORE_UX:
17131 case TYPE_FPSTORE_U:
17132 case TYPE_FPSTORE_UX:
17133 if ((rs6000_cpu == PROCESSOR_POWER6)
17134 && recog_memoized (dep_insn)
17135 && (INSN_CODE (dep_insn) >= 0))
17138 if (GET_CODE (PATTERN (insn)) != SET)
17139 /* If this happens, we have to extend this to schedule
17140 optimally. Return default for now. */
17143 /* Adjust the cost for the case where the value written
17144 by a fixed point operation is used as the address
17145 gen value on a store. */
17146 switch (get_attr_type (dep_insn))
17153 if (! store_data_bypass_p (dep_insn, insn))
17157 case TYPE_LOAD_EXT:
17158 case TYPE_LOAD_EXT_U:
17159 case TYPE_LOAD_EXT_UX:
17160 case TYPE_VAR_SHIFT_ROTATE:
17161 case TYPE_VAR_DELAYED_COMPARE:
17163 if (! store_data_bypass_p (dep_insn, insn))
17169 case TYPE_FAST_COMPARE:
17172 case TYPE_INSERT_WORD:
17173 case TYPE_INSERT_DWORD:
17174 case TYPE_FPLOAD_U:
17175 case TYPE_FPLOAD_UX:
17177 case TYPE_STORE_UX:
17178 case TYPE_FPSTORE_U:
17179 case TYPE_FPSTORE_UX:
17181 if (! store_data_bypass_p (dep_insn, insn))
17189 case TYPE_IMUL_COMPARE:
17190 case TYPE_LMUL_COMPARE:
17192 if (! store_data_bypass_p (dep_insn, insn))
17198 if (! store_data_bypass_p (dep_insn, insn))
17204 if (! store_data_bypass_p (dep_insn, insn))
17217 case TYPE_LOAD_EXT:
17218 case TYPE_LOAD_EXT_U:
17219 case TYPE_LOAD_EXT_UX:
17220 if ((rs6000_cpu == PROCESSOR_POWER6)
17221 && recog_memoized (dep_insn)
17222 && (INSN_CODE (dep_insn) >= 0))
17225 /* Adjust the cost for the case where the value written
17226 by a fixed point instruction is used within the address
17227 gen portion of a subsequent load(u)(x) */
17228 switch (get_attr_type (dep_insn))
17235 if (set_to_load_agen (dep_insn, insn))
17239 case TYPE_LOAD_EXT:
17240 case TYPE_LOAD_EXT_U:
17241 case TYPE_LOAD_EXT_UX:
17242 case TYPE_VAR_SHIFT_ROTATE:
17243 case TYPE_VAR_DELAYED_COMPARE:
17245 if (set_to_load_agen (dep_insn, insn))
17251 case TYPE_FAST_COMPARE:
17254 case TYPE_INSERT_WORD:
17255 case TYPE_INSERT_DWORD:
17256 case TYPE_FPLOAD_U:
17257 case TYPE_FPLOAD_UX:
17259 case TYPE_STORE_UX:
17260 case TYPE_FPSTORE_U:
17261 case TYPE_FPSTORE_UX:
17263 if (set_to_load_agen (dep_insn, insn))
17271 case TYPE_IMUL_COMPARE:
17272 case TYPE_LMUL_COMPARE:
17274 if (set_to_load_agen (dep_insn, insn))
17280 if (set_to_load_agen (dep_insn, insn))
17286 if (set_to_load_agen (dep_insn, insn))
17297 if ((rs6000_cpu == PROCESSOR_POWER6)
17298 && recog_memoized (dep_insn)
17299 && (INSN_CODE (dep_insn) >= 0)
17300 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
17307 /* Fall out to return default cost. */
17311 case REG_DEP_OUTPUT:
17312 /* Output dependency; DEP_INSN writes a register that INSN writes some
17314 if ((rs6000_cpu == PROCESSOR_POWER6)
17315 && recog_memoized (dep_insn)
17316 && (INSN_CODE (dep_insn) >= 0))
17318 attr_type = get_attr_type (insn);
17323 if (get_attr_type (dep_insn) == TYPE_FP)
17327 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
17335 /* Anti dependency; DEP_INSN reads a register that INSN writes some
17340 gcc_unreachable ();
17346 /* The function returns a true if INSN is microcoded.
17347 Return false otherwise. */
17350 is_microcoded_insn (rtx insn)
17352 if (!insn || !INSN_P (insn)
17353 || GET_CODE (PATTERN (insn)) == USE
17354 || GET_CODE (PATTERN (insn)) == CLOBBER)
17357 if (rs6000_cpu_attr == CPU_CELL)
17358 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
17360 if (rs6000_sched_groups)
17362 enum attr_type type = get_attr_type (insn);
17363 if (type == TYPE_LOAD_EXT_U
17364 || type == TYPE_LOAD_EXT_UX
17365 || type == TYPE_LOAD_UX
17366 || type == TYPE_STORE_UX
17367 || type == TYPE_MFCR)
17374 /* The function returns true if INSN is cracked into 2 instructions
17375 by the processor (and therefore occupies 2 issue slots). */
17378 is_cracked_insn (rtx insn)
17380 if (!insn || !INSN_P (insn)
17381 || GET_CODE (PATTERN (insn)) == USE
17382 || GET_CODE (PATTERN (insn)) == CLOBBER)
17385 if (rs6000_sched_groups)
17387 enum attr_type type = get_attr_type (insn);
17388 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
17389 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
17390 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
17391 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
17392 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
17393 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
17394 || type == TYPE_IDIV || type == TYPE_LDIV
17395 || type == TYPE_INSERT_WORD)
17402 /* The function returns true if INSN can be issued only from
17403 the branch slot. */
17406 is_branch_slot_insn (rtx insn)
17408 if (!insn || !INSN_P (insn)
17409 || GET_CODE (PATTERN (insn)) == USE
17410 || GET_CODE (PATTERN (insn)) == CLOBBER)
17413 if (rs6000_sched_groups)
17415 enum attr_type type = get_attr_type (insn);
17416 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
17424 /* The function returns true if out_inst sets a value that is
17425 used in the address generation computation of in_insn */
17427 set_to_load_agen (rtx out_insn, rtx in_insn)
17429 rtx out_set, in_set;
17431 /* For performance reasons, only handle the simple case where
17432 both loads are a single_set. */
17433 out_set = single_set (out_insn);
17436 in_set = single_set (in_insn);
17438 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
17444 /* The function returns true if the target storage location of
17445 out_insn is adjacent to the target storage location of in_insn */
17446 /* Return 1 if memory locations are adjacent. */
17449 adjacent_mem_locations (rtx insn1, rtx insn2)
17452 rtx a = get_store_dest (PATTERN (insn1));
17453 rtx b = get_store_dest (PATTERN (insn2));
17455 if ((GET_CODE (XEXP (a, 0)) == REG
17456 || (GET_CODE (XEXP (a, 0)) == PLUS
17457 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
17458 && (GET_CODE (XEXP (b, 0)) == REG
17459 || (GET_CODE (XEXP (b, 0)) == PLUS
17460 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
17462 HOST_WIDE_INT val0 = 0, val1 = 0;
17466 if (GET_CODE (XEXP (a, 0)) == PLUS)
17468 reg0 = XEXP (XEXP (a, 0), 0);
17469 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
17472 reg0 = XEXP (a, 0);
17474 if (GET_CODE (XEXP (b, 0)) == PLUS)
17476 reg1 = XEXP (XEXP (b, 0), 0);
17477 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
17480 reg1 = XEXP (b, 0);
17482 val_diff = val1 - val0;
17484 return ((REGNO (reg0) == REGNO (reg1))
17485 && (val_diff == INTVAL (MEM_SIZE (a))
17486 || val_diff == -INTVAL (MEM_SIZE (b))));
17492 /* A C statement (sans semicolon) to update the integer scheduling
17493 priority INSN_PRIORITY (INSN). Increase the priority to execute the
17494 INSN earlier, reduce the priority to execute INSN later. Do not
17495 define this macro if you do not need to adjust the scheduling
17496 priorities of insns. */
17499 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
17501 /* On machines (like the 750) which have asymmetric integer units,
17502 where one integer unit can do multiply and divides and the other
17503 can't, reduce the priority of multiply/divide so it is scheduled
17504 before other integer operations. */
17507 if (! INSN_P (insn))
17510 if (GET_CODE (PATTERN (insn)) == USE)
17513 switch (rs6000_cpu_attr) {
17515 switch (get_attr_type (insn))
17522 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
17523 priority, priority);
17524 if (priority >= 0 && priority < 0x01000000)
17531 if (insn_must_be_first_in_group (insn)
17532 && reload_completed
17533 && current_sched_info->sched_max_insns_priority
17534 && rs6000_sched_restricted_insns_priority)
17537 /* Prioritize insns that can be dispatched only in the first
17539 if (rs6000_sched_restricted_insns_priority == 1)
17540 /* Attach highest priority to insn. This means that in
17541 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
17542 precede 'priority' (critical path) considerations. */
17543 return current_sched_info->sched_max_insns_priority;
17544 else if (rs6000_sched_restricted_insns_priority == 2)
17545 /* Increase priority of insn by a minimal amount. This means that in
17546 haifa-sched.c:ready_sort(), only 'priority' (critical path)
17547 considerations precede dispatch-slot restriction considerations. */
17548 return (priority + 1);
17551 if (rs6000_cpu == PROCESSOR_POWER6
17552 && ((load_store_pendulum == -2 && is_load_insn (insn))
17553 || (load_store_pendulum == 2 && is_store_insn (insn))))
17554 /* Attach highest priority to insn if the scheduler has just issued two
17555 stores and this instruction is a load, or two loads and this instruction
17556 is a store. Power6 wants loads and stores scheduled alternately
17558 return current_sched_info->sched_max_insns_priority;
17563 /* Return true if the instruction is nonpipelined on the Cell. */
17565 is_nonpipeline_insn (rtx insn)
17567 enum attr_type type;
17568 if (!insn || !INSN_P (insn)
17569 || GET_CODE (PATTERN (insn)) == USE
17570 || GET_CODE (PATTERN (insn)) == CLOBBER)
17573 type = get_attr_type (insn);
17574 if (type == TYPE_IMUL
17575 || type == TYPE_IMUL2
17576 || type == TYPE_IMUL3
17577 || type == TYPE_LMUL
17578 || type == TYPE_IDIV
17579 || type == TYPE_LDIV
17580 || type == TYPE_SDIV
17581 || type == TYPE_DDIV
17582 || type == TYPE_SSQRT
17583 || type == TYPE_DSQRT
17584 || type == TYPE_MFCR
17585 || type == TYPE_MFCRF
17586 || type == TYPE_MFJMPR)
17594 /* Return how many instructions the machine can issue per cycle. */
17597 rs6000_issue_rate (void)
17599 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
17600 if (!reload_completed)
17603 switch (rs6000_cpu_attr) {
17604 case CPU_RIOS1: /* ? */
17606 case CPU_PPC601: /* ? */
17631 /* Return how many instructions to look ahead for better insn
17635 rs6000_use_sched_lookahead (void)
17637 if (rs6000_cpu_attr == CPU_PPC8540)
17639 if (rs6000_cpu_attr == CPU_CELL)
17640 return (reload_completed ? 8 : 0);
17644 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
17646 rs6000_use_sched_lookahead_guard (rtx insn)
17648 if (rs6000_cpu_attr != CPU_CELL)
17651 if (insn == NULL_RTX || !INSN_P (insn))
17654 if (!reload_completed
17655 || is_nonpipeline_insn (insn)
17656 || is_microcoded_insn (insn))
17662 /* Determine is PAT refers to memory. */
17665 is_mem_ref (rtx pat)
17671 if (GET_CODE (pat) == MEM)
17674 /* Recursively process the pattern. */
17675 fmt = GET_RTX_FORMAT (GET_CODE (pat));
17677 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
17680 ret |= is_mem_ref (XEXP (pat, i));
17681 else if (fmt[i] == 'E')
17682 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
17683 ret |= is_mem_ref (XVECEXP (pat, i, j));
17689 /* Determine if PAT is a PATTERN of a load insn. */
17692 is_load_insn1 (rtx pat)
17694 if (!pat || pat == NULL_RTX)
17697 if (GET_CODE (pat) == SET)
17698 return is_mem_ref (SET_SRC (pat));
17700 if (GET_CODE (pat) == PARALLEL)
17704 for (i = 0; i < XVECLEN (pat, 0); i++)
17705 if (is_load_insn1 (XVECEXP (pat, 0, i)))
17712 /* Determine if INSN loads from memory. */
17715 is_load_insn (rtx insn)
17717 if (!insn || !INSN_P (insn))
17720 if (GET_CODE (insn) == CALL_INSN)
17723 return is_load_insn1 (PATTERN (insn));
17726 /* Determine if PAT is a PATTERN of a store insn. */
17729 is_store_insn1 (rtx pat)
17731 if (!pat || pat == NULL_RTX)
17734 if (GET_CODE (pat) == SET)
17735 return is_mem_ref (SET_DEST (pat));
17737 if (GET_CODE (pat) == PARALLEL)
17741 for (i = 0; i < XVECLEN (pat, 0); i++)
17742 if (is_store_insn1 (XVECEXP (pat, 0, i)))
17749 /* Determine if INSN stores to memory. */
17752 is_store_insn (rtx insn)
17754 if (!insn || !INSN_P (insn))
17757 return is_store_insn1 (PATTERN (insn));
17760 /* Return the dest of a store insn. */
17763 get_store_dest (rtx pat)
17765 gcc_assert (is_store_insn1 (pat));
17767 if (GET_CODE (pat) == SET)
17768 return SET_DEST (pat);
17769 else if (GET_CODE (pat) == PARALLEL)
17773 for (i = 0; i < XVECLEN (pat, 0); i++)
17775 rtx inner_pat = XVECEXP (pat, 0, i);
17776 if (GET_CODE (inner_pat) == SET
17777 && is_mem_ref (SET_DEST (inner_pat)))
17781 /* We shouldn't get here, because we should have either a simple
17782 store insn or a store with update which are covered above. */
17786 /* Returns whether the dependence between INSN and NEXT is considered
17787 costly by the given target. */
17790 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
17795 /* If the flag is not enabled - no dependence is considered costly;
17796 allow all dependent insns in the same group.
17797 This is the most aggressive option. */
17798 if (rs6000_sched_costly_dep == no_dep_costly)
17801 /* If the flag is set to 1 - a dependence is always considered costly;
17802 do not allow dependent instructions in the same group.
17803 This is the most conservative option. */
17804 if (rs6000_sched_costly_dep == all_deps_costly)
17807 insn = DEP_PRO (dep);
17808 next = DEP_CON (dep);
17810 if (rs6000_sched_costly_dep == store_to_load_dep_costly
17811 && is_load_insn (next)
17812 && is_store_insn (insn))
17813 /* Prevent load after store in the same group. */
17816 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
17817 && is_load_insn (next)
17818 && is_store_insn (insn)
17819 && DEP_KIND (dep) == REG_DEP_TRUE)
17820 /* Prevent load after store in the same group if it is a true
17824 /* The flag is set to X; dependences with latency >= X are considered costly,
17825 and will not be scheduled in the same group. */
17826 if (rs6000_sched_costly_dep <= max_dep_latency
17827 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
17833 /* Return the next insn after INSN that is found before TAIL is reached,
17834 skipping any "non-active" insns - insns that will not actually occupy
17835 an issue slot. Return NULL_RTX if such an insn is not found. */
17838 get_next_active_insn (rtx insn, rtx tail)
17840 if (insn == NULL_RTX || insn == tail)
17845 insn = NEXT_INSN (insn);
17846 if (insn == NULL_RTX || insn == tail)
17851 || (NONJUMP_INSN_P (insn)
17852 && GET_CODE (PATTERN (insn)) != USE
17853 && GET_CODE (PATTERN (insn)) != CLOBBER
17854 && INSN_CODE (insn) != CODE_FOR_stack_tie))
17860 /* We are about to begin issuing insns for this clock cycle. */
17863 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
17864 rtx *ready ATTRIBUTE_UNUSED,
17865 int *pn_ready ATTRIBUTE_UNUSED,
17866 int clock_var ATTRIBUTE_UNUSED)
17868 int n_ready = *pn_ready;
17871 fprintf (dump, "// rs6000_sched_reorder :\n");
17873 /* Reorder the ready list, if the second to last ready insn
17874 is a nonepipeline insn. */
17875 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
17877 if (is_nonpipeline_insn (ready[n_ready - 1])
17878 && (recog_memoized (ready[n_ready - 2]) > 0))
17879 /* Simply swap first two insns. */
17881 rtx tmp = ready[n_ready - 1];
17882 ready[n_ready - 1] = ready[n_ready - 2];
17883 ready[n_ready - 2] = tmp;
17887 if (rs6000_cpu == PROCESSOR_POWER6)
17888 load_store_pendulum = 0;
17890 return rs6000_issue_rate ();
17893 /* Like rs6000_sched_reorder, but called after issuing each insn. */
17896 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
17897 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
17900 fprintf (dump, "// rs6000_sched_reorder2 :\n");
17902 /* For Power6, we need to handle some special cases to try and keep the
17903 store queue from overflowing and triggering expensive flushes.
17905 This code monitors how load and store instructions are being issued
17906 and skews the ready list one way or the other to increase the likelihood
17907 that a desired instruction is issued at the proper time.
17909 A couple of things are done. First, we maintain a "load_store_pendulum"
17910 to track the current state of load/store issue.
17912 - If the pendulum is at zero, then no loads or stores have been
17913 issued in the current cycle so we do nothing.
17915 - If the pendulum is 1, then a single load has been issued in this
17916 cycle and we attempt to locate another load in the ready list to
17919 - If the pendulum is -2, then two stores have already been
17920 issued in this cycle, so we increase the priority of the first load
17921 in the ready list to increase it's likelihood of being chosen first
17924 - If the pendulum is -1, then a single store has been issued in this
17925 cycle and we attempt to locate another store in the ready list to
17926 issue with it, preferring a store to an adjacent memory location to
17927 facilitate store pairing in the store queue.
17929 - If the pendulum is 2, then two loads have already been
17930 issued in this cycle, so we increase the priority of the first store
17931 in the ready list to increase it's likelihood of being chosen first
17934 - If the pendulum < -2 or > 2, then do nothing.
17936 Note: This code covers the most common scenarios. There exist non
17937 load/store instructions which make use of the LSU and which
17938 would need to be accounted for to strictly model the behavior
17939 of the machine. Those instructions are currently unaccounted
17940 for to help minimize compile time overhead of this code.
17942 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
17948 if (is_store_insn (last_scheduled_insn))
17949 /* Issuing a store, swing the load_store_pendulum to the left */
17950 load_store_pendulum--;
17951 else if (is_load_insn (last_scheduled_insn))
17952 /* Issuing a load, swing the load_store_pendulum to the right */
17953 load_store_pendulum++;
17955 return cached_can_issue_more;
17957 /* If the pendulum is balanced, or there is only one instruction on
17958 the ready list, then all is well, so return. */
17959 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
17960 return cached_can_issue_more;
17962 if (load_store_pendulum == 1)
17964 /* A load has been issued in this cycle. Scan the ready list
17965 for another load to issue with it */
17970 if (is_load_insn (ready[pos]))
17972 /* Found a load. Move it to the head of the ready list,
17973 and adjust it's priority so that it is more likely to
17976 for (i=pos; i<*pn_ready-1; i++)
17977 ready[i] = ready[i + 1];
17978 ready[*pn_ready-1] = tmp;
17979 if INSN_PRIORITY_KNOWN (tmp)
17980 INSN_PRIORITY (tmp)++;
17986 else if (load_store_pendulum == -2)
17988 /* Two stores have been issued in this cycle. Increase the
17989 priority of the first load in the ready list to favor it for
17990 issuing in the next cycle. */
17995 if (is_load_insn (ready[pos])
17996 && INSN_PRIORITY_KNOWN (ready[pos]))
17998 INSN_PRIORITY (ready[pos])++;
18000 /* Adjust the pendulum to account for the fact that a load
18001 was found and increased in priority. This is to prevent
18002 increasing the priority of multiple loads */
18003 load_store_pendulum--;
18010 else if (load_store_pendulum == -1)
18012 /* A store has been issued in this cycle. Scan the ready list for
18013 another store to issue with it, preferring a store to an adjacent
18015 int first_store_pos = -1;
18021 if (is_store_insn (ready[pos]))
18023 /* Maintain the index of the first store found on the
18025 if (first_store_pos == -1)
18026 first_store_pos = pos;
18028 if (is_store_insn (last_scheduled_insn)
18029 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
18031 /* Found an adjacent store. Move it to the head of the
18032 ready list, and adjust it's priority so that it is
18033 more likely to stay there */
18035 for (i=pos; i<*pn_ready-1; i++)
18036 ready[i] = ready[i + 1];
18037 ready[*pn_ready-1] = tmp;
18038 if INSN_PRIORITY_KNOWN (tmp)
18039 INSN_PRIORITY (tmp)++;
18040 first_store_pos = -1;
18048 if (first_store_pos >= 0)
18050 /* An adjacent store wasn't found, but a non-adjacent store was,
18051 so move the non-adjacent store to the front of the ready
18052 list, and adjust its priority so that it is more likely to
18054 tmp = ready[first_store_pos];
18055 for (i=first_store_pos; i<*pn_ready-1; i++)
18056 ready[i] = ready[i + 1];
18057 ready[*pn_ready-1] = tmp;
18058 if INSN_PRIORITY_KNOWN (tmp)
18059 INSN_PRIORITY (tmp)++;
18062 else if (load_store_pendulum == 2)
18064 /* Two loads have been issued in this cycle. Increase the priority
18065 of the first store in the ready list to favor it for issuing in
18071 if (is_store_insn (ready[pos])
18072 && INSN_PRIORITY_KNOWN (ready[pos]))
18074 INSN_PRIORITY (ready[pos])++;
18076 /* Adjust the pendulum to account for the fact that a store
18077 was found and increased in priority. This is to prevent
18078 increasing the priority of multiple stores */
18079 load_store_pendulum++;
18088 return cached_can_issue_more;
18091 /* Return whether the presence of INSN causes a dispatch group termination
18092 of group WHICH_GROUP.
18094 If WHICH_GROUP == current_group, this function will return true if INSN
18095 causes the termination of the current group (i.e, the dispatch group to
18096 which INSN belongs). This means that INSN will be the last insn in the
18097 group it belongs to.
18099 If WHICH_GROUP == previous_group, this function will return true if INSN
18100 causes the termination of the previous group (i.e, the dispatch group that
18101 precedes the group to which INSN belongs). This means that INSN will be
18102 the first insn in the group it belongs to). */
18105 insn_terminates_group_p (rtx insn, enum group_termination which_group)
18112 first = insn_must_be_first_in_group (insn);
18113 last = insn_must_be_last_in_group (insn);
18118 if (which_group == current_group)
18120 else if (which_group == previous_group)
18128 insn_must_be_first_in_group (rtx insn)
18130 enum attr_type type;
18133 || insn == NULL_RTX
18134 || GET_CODE (insn) == NOTE
18135 || GET_CODE (PATTERN (insn)) == USE
18136 || GET_CODE (PATTERN (insn)) == CLOBBER)
18139 switch (rs6000_cpu)
18141 case PROCESSOR_POWER5:
18142 if (is_cracked_insn (insn))
18144 case PROCESSOR_POWER4:
18145 if (is_microcoded_insn (insn))
18148 if (!rs6000_sched_groups)
18151 type = get_attr_type (insn);
18158 case TYPE_DELAYED_CR:
18159 case TYPE_CR_LOGICAL:
18173 case PROCESSOR_POWER6:
18174 type = get_attr_type (insn);
18178 case TYPE_INSERT_DWORD:
18182 case TYPE_VAR_SHIFT_ROTATE:
18189 case TYPE_INSERT_WORD:
18190 case TYPE_DELAYED_COMPARE:
18191 case TYPE_IMUL_COMPARE:
18192 case TYPE_LMUL_COMPARE:
18193 case TYPE_FPCOMPARE:
18204 case TYPE_LOAD_EXT_UX:
18206 case TYPE_STORE_UX:
18207 case TYPE_FPLOAD_U:
18208 case TYPE_FPLOAD_UX:
18209 case TYPE_FPSTORE_U:
18210 case TYPE_FPSTORE_UX:
18224 insn_must_be_last_in_group (rtx insn)
18226 enum attr_type type;
18229 || insn == NULL_RTX
18230 || GET_CODE (insn) == NOTE
18231 || GET_CODE (PATTERN (insn)) == USE
18232 || GET_CODE (PATTERN (insn)) == CLOBBER)
18235 switch (rs6000_cpu) {
18236 case PROCESSOR_POWER4:
18237 case PROCESSOR_POWER5:
18238 if (is_microcoded_insn (insn))
18241 if (is_branch_slot_insn (insn))
18245 case PROCESSOR_POWER6:
18246 type = get_attr_type (insn);
18253 case TYPE_VAR_SHIFT_ROTATE:
18260 case TYPE_DELAYED_COMPARE:
18261 case TYPE_IMUL_COMPARE:
18262 case TYPE_LMUL_COMPARE:
18263 case TYPE_FPCOMPARE:
18284 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
18285 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
18288 is_costly_group (rtx *group_insns, rtx next_insn)
18291 int issue_rate = rs6000_issue_rate ();
18293 for (i = 0; i < issue_rate; i++)
18296 rtx insn = group_insns[i];
18301 FOR_EACH_DEP_LINK (link, INSN_FORW_DEPS (insn))
18303 dep_t dep = DEP_LINK_DEP (link);
18304 rtx next = DEP_CON (dep);
18306 if (next == next_insn
18307 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
18315 /* Utility of the function redefine_groups.
18316 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
18317 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
18318 to keep it "far" (in a separate group) from GROUP_INSNS, following
18319 one of the following schemes, depending on the value of the flag
18320 -minsert_sched_nops = X:
18321 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
18322 in order to force NEXT_INSN into a separate group.
18323 (2) X < sched_finish_regroup_exact: insert exactly X nops.
18324 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
18325 insertion (has a group just ended, how many vacant issue slots remain in the
18326 last group, and how many dispatch groups were encountered so far). */
18329 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
18330 rtx next_insn, bool *group_end, int can_issue_more,
18335 int issue_rate = rs6000_issue_rate ();
18336 bool end = *group_end;
18339 if (next_insn == NULL_RTX)
18340 return can_issue_more;
18342 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
18343 return can_issue_more;
18345 force = is_costly_group (group_insns, next_insn);
18347 return can_issue_more;
18349 if (sched_verbose > 6)
18350 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
18351 *group_count ,can_issue_more);
18353 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
18356 can_issue_more = 0;
18358 /* Since only a branch can be issued in the last issue_slot, it is
18359 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18360 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18361 in this case the last nop will start a new group and the branch
18362 will be forced to the new group. */
18363 if (can_issue_more && !is_branch_slot_insn (next_insn))
18366 while (can_issue_more > 0)
18369 emit_insn_before (nop, next_insn);
18377 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
18379 int n_nops = rs6000_sched_insert_nops;
18381 /* Nops can't be issued from the branch slot, so the effective
18382 issue_rate for nops is 'issue_rate - 1'. */
18383 if (can_issue_more == 0)
18384 can_issue_more = issue_rate;
18386 if (can_issue_more == 0)
18388 can_issue_more = issue_rate - 1;
18391 for (i = 0; i < issue_rate; i++)
18393 group_insns[i] = 0;
18400 emit_insn_before (nop, next_insn);
18401 if (can_issue_more == issue_rate - 1) /* new group begins */
18404 if (can_issue_more == 0)
18406 can_issue_more = issue_rate - 1;
18409 for (i = 0; i < issue_rate; i++)
18411 group_insns[i] = 0;
18417 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
18420 /* Is next_insn going to start a new group? */
18423 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18424 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18425 || (can_issue_more < issue_rate &&
18426 insn_terminates_group_p (next_insn, previous_group)));
18427 if (*group_end && end)
18430 if (sched_verbose > 6)
18431 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
18432 *group_count, can_issue_more);
18433 return can_issue_more;
18436 return can_issue_more;
18439 /* This function tries to synch the dispatch groups that the compiler "sees"
18440 with the dispatch groups that the processor dispatcher is expected to
18441 form in practice. It tries to achieve this synchronization by forcing the
18442 estimated processor grouping on the compiler (as opposed to the function
18443 'pad_goups' which tries to force the scheduler's grouping on the processor).
18445 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
18446 examines the (estimated) dispatch groups that will be formed by the processor
18447 dispatcher. It marks these group boundaries to reflect the estimated
18448 processor grouping, overriding the grouping that the scheduler had marked.
18449 Depending on the value of the flag '-minsert-sched-nops' this function can
18450 force certain insns into separate groups or force a certain distance between
18451 them by inserting nops, for example, if there exists a "costly dependence"
18454 The function estimates the group boundaries that the processor will form as
18455 follows: It keeps track of how many vacant issue slots are available after
18456 each insn. A subsequent insn will start a new group if one of the following
18458 - no more vacant issue slots remain in the current dispatch group.
18459 - only the last issue slot, which is the branch slot, is vacant, but the next
18460 insn is not a branch.
18461 - only the last 2 or less issue slots, including the branch slot, are vacant,
18462 which means that a cracked insn (which occupies two issue slots) can't be
18463 issued in this group.
18464 - less than 'issue_rate' slots are vacant, and the next insn always needs to
18465 start a new group. */
18468 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18470 rtx insn, next_insn;
18472 int can_issue_more;
18475 int group_count = 0;
18479 issue_rate = rs6000_issue_rate ();
18480 group_insns = alloca (issue_rate * sizeof (rtx));
18481 for (i = 0; i < issue_rate; i++)
18483 group_insns[i] = 0;
18485 can_issue_more = issue_rate;
18487 insn = get_next_active_insn (prev_head_insn, tail);
18490 while (insn != NULL_RTX)
18492 slot = (issue_rate - can_issue_more);
18493 group_insns[slot] = insn;
18495 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18496 if (insn_terminates_group_p (insn, current_group))
18497 can_issue_more = 0;
18499 next_insn = get_next_active_insn (insn, tail);
18500 if (next_insn == NULL_RTX)
18501 return group_count + 1;
18503 /* Is next_insn going to start a new group? */
18505 = (can_issue_more == 0
18506 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18507 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18508 || (can_issue_more < issue_rate &&
18509 insn_terminates_group_p (next_insn, previous_group)));
18511 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
18512 next_insn, &group_end, can_issue_more,
18518 can_issue_more = 0;
18519 for (i = 0; i < issue_rate; i++)
18521 group_insns[i] = 0;
18525 if (GET_MODE (next_insn) == TImode && can_issue_more)
18526 PUT_MODE (next_insn, VOIDmode);
18527 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
18528 PUT_MODE (next_insn, TImode);
18531 if (can_issue_more == 0)
18532 can_issue_more = issue_rate;
18535 return group_count;
18538 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
18539 dispatch group boundaries that the scheduler had marked. Pad with nops
18540 any dispatch groups which have vacant issue slots, in order to force the
18541 scheduler's grouping on the processor dispatcher. The function
18542 returns the number of dispatch groups found. */
18545 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18547 rtx insn, next_insn;
18550 int can_issue_more;
18552 int group_count = 0;
18554 /* Initialize issue_rate. */
18555 issue_rate = rs6000_issue_rate ();
18556 can_issue_more = issue_rate;
18558 insn = get_next_active_insn (prev_head_insn, tail);
18559 next_insn = get_next_active_insn (insn, tail);
18561 while (insn != NULL_RTX)
18564 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18566 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
18568 if (next_insn == NULL_RTX)
18573 /* If the scheduler had marked group termination at this location
18574 (between insn and next_indn), and neither insn nor next_insn will
18575 force group termination, pad the group with nops to force group
18578 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
18579 && !insn_terminates_group_p (insn, current_group)
18580 && !insn_terminates_group_p (next_insn, previous_group))
18582 if (!is_branch_slot_insn (next_insn))
18585 while (can_issue_more)
18588 emit_insn_before (nop, next_insn);
18593 can_issue_more = issue_rate;
18598 next_insn = get_next_active_insn (insn, tail);
18601 return group_count;
18604 /* We're beginning a new block. Initialize data structures as necessary. */
18607 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
18608 int sched_verbose ATTRIBUTE_UNUSED,
18609 int max_ready ATTRIBUTE_UNUSED)
18611 last_scheduled_insn = NULL_RTX;
18612 load_store_pendulum = 0;
18615 /* The following function is called at the end of scheduling BB.
18616 After reload, it inserts nops at insn group bundling. */
18619 rs6000_sched_finish (FILE *dump, int sched_verbose)
18624 fprintf (dump, "=== Finishing schedule.\n");
18626 if (reload_completed && rs6000_sched_groups)
18628 if (rs6000_sched_insert_nops == sched_finish_none)
18631 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
18632 n_groups = pad_groups (dump, sched_verbose,
18633 current_sched_info->prev_head,
18634 current_sched_info->next_tail);
18636 n_groups = redefine_groups (dump, sched_verbose,
18637 current_sched_info->prev_head,
18638 current_sched_info->next_tail);
18640 if (sched_verbose >= 6)
18642 fprintf (dump, "ngroups = %d\n", n_groups);
18643 print_rtl (dump, current_sched_info->prev_head);
18644 fprintf (dump, "Done finish_sched\n");
18649 /* Length in units of the trampoline for entering a nested function. */
18652 rs6000_trampoline_size (void)
18656 switch (DEFAULT_ABI)
18659 gcc_unreachable ();
18662 ret = (TARGET_32BIT) ? 12 : 24;
18667 ret = (TARGET_32BIT) ? 40 : 48;
18674 /* Emit RTL insns to initialize the variable parts of a trampoline.
18675 FNADDR is an RTX for the address of the function's pure code.
18676 CXT is an RTX for the static chain value for the function. */
18679 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
18681 int regsize = (TARGET_32BIT) ? 4 : 8;
18682 rtx ctx_reg = force_reg (Pmode, cxt);
18684 switch (DEFAULT_ABI)
18687 gcc_unreachable ();
18689 /* Macros to shorten the code expansions below. */
18690 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
18691 #define MEM_PLUS(addr,offset) \
18692 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
18694 /* Under AIX, just build the 3 word function descriptor */
18697 rtx fn_reg = gen_reg_rtx (Pmode);
18698 rtx toc_reg = gen_reg_rtx (Pmode);
18699 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
18700 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
18701 emit_move_insn (MEM_DEREF (addr), fn_reg);
18702 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
18703 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
18707 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
18710 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
18711 FALSE, VOIDmode, 4,
18713 GEN_INT (rs6000_trampoline_size ()), SImode,
18723 /* Table of valid machine attributes. */
18725 const struct attribute_spec rs6000_attribute_table[] =
18727 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
18728 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
18729 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18730 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18731 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18732 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18733 #ifdef SUBTARGET_ATTRIBUTE_TABLE
18734 SUBTARGET_ATTRIBUTE_TABLE,
18736 { NULL, 0, 0, false, false, false, NULL }
18739 /* Handle the "altivec" attribute. The attribute may have
18740 arguments as follows:
18742 __attribute__((altivec(vector__)))
18743 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
18744 __attribute__((altivec(bool__))) (always followed by 'unsigned')
18746 and may appear more than once (e.g., 'vector bool char') in a
18747 given declaration. */
18750 rs6000_handle_altivec_attribute (tree *node,
18751 tree name ATTRIBUTE_UNUSED,
18753 int flags ATTRIBUTE_UNUSED,
18754 bool *no_add_attrs)
18756 tree type = *node, result = NULL_TREE;
18757 enum machine_mode mode;
18760 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
18761 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
18762 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
18765 while (POINTER_TYPE_P (type)
18766 || TREE_CODE (type) == FUNCTION_TYPE
18767 || TREE_CODE (type) == METHOD_TYPE
18768 || TREE_CODE (type) == ARRAY_TYPE)
18769 type = TREE_TYPE (type);
18771 mode = TYPE_MODE (type);
18773 /* Check for invalid AltiVec type qualifiers. */
18774 if (type == long_unsigned_type_node || type == long_integer_type_node)
18777 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
18778 else if (rs6000_warn_altivec_long)
18779 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
18781 else if (type == long_long_unsigned_type_node
18782 || type == long_long_integer_type_node)
18783 error ("use of %<long long%> in AltiVec types is invalid");
18784 else if (type == double_type_node)
18785 error ("use of %<double%> in AltiVec types is invalid");
18786 else if (type == long_double_type_node)
18787 error ("use of %<long double%> in AltiVec types is invalid");
18788 else if (type == boolean_type_node)
18789 error ("use of boolean types in AltiVec types is invalid");
18790 else if (TREE_CODE (type) == COMPLEX_TYPE)
18791 error ("use of %<complex%> in AltiVec types is invalid");
18792 else if (DECIMAL_FLOAT_MODE_P (mode))
18793 error ("use of decimal floating point types in AltiVec types is invalid");
18795 switch (altivec_type)
18798 unsigned_p = TYPE_UNSIGNED (type);
18802 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
18805 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
18808 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
18810 case SFmode: result = V4SF_type_node; break;
18811 /* If the user says 'vector int bool', we may be handed the 'bool'
18812 attribute _before_ the 'vector' attribute, and so select the
18813 proper type in the 'b' case below. */
18814 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
18822 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
18823 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
18824 case QImode: case V16QImode: result = bool_V16QI_type_node;
18831 case V8HImode: result = pixel_V8HI_type_node;
18837 if (result && result != type && TYPE_READONLY (type))
18838 result = build_qualified_type (result, TYPE_QUAL_CONST);
18840 *no_add_attrs = true; /* No need to hang on to the attribute. */
18843 *node = reconstruct_complex_type (*node, result);
18848 /* AltiVec defines four built-in scalar types that serve as vector
18849 elements; we must teach the compiler how to mangle them. */
18851 static const char *
18852 rs6000_mangle_fundamental_type (tree type)
18854 if (type == bool_char_type_node) return "U6__boolc";
18855 if (type == bool_short_type_node) return "U6__bools";
18856 if (type == pixel_type_node) return "u7__pixel";
18857 if (type == bool_int_type_node) return "U6__booli";
18859 /* Mangle IBM extended float long double as `g' (__float128) on
18860 powerpc*-linux where long-double-64 previously was the default. */
18861 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
18863 && TARGET_LONG_DOUBLE_128
18864 && !TARGET_IEEEQUAD)
18867 /* For all other types, use normal C++ mangling. */
18871 /* Handle a "longcall" or "shortcall" attribute; arguments as in
18872 struct attribute_spec.handler. */
18875 rs6000_handle_longcall_attribute (tree *node, tree name,
18876 tree args ATTRIBUTE_UNUSED,
18877 int flags ATTRIBUTE_UNUSED,
18878 bool *no_add_attrs)
18880 if (TREE_CODE (*node) != FUNCTION_TYPE
18881 && TREE_CODE (*node) != FIELD_DECL
18882 && TREE_CODE (*node) != TYPE_DECL)
18884 warning (OPT_Wattributes, "%qs attribute only applies to functions",
18885 IDENTIFIER_POINTER (name));
18886 *no_add_attrs = true;
18892 /* Set longcall attributes on all functions declared when
18893 rs6000_default_long_calls is true. */
18895 rs6000_set_default_type_attributes (tree type)
18897 if (rs6000_default_long_calls
18898 && (TREE_CODE (type) == FUNCTION_TYPE
18899 || TREE_CODE (type) == METHOD_TYPE))
18900 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
18902 TYPE_ATTRIBUTES (type));
18905 darwin_set_default_type_attributes (type);
18909 /* Return a reference suitable for calling a function with the
18910 longcall attribute. */
18913 rs6000_longcall_ref (rtx call_ref)
18915 const char *call_name;
18918 if (GET_CODE (call_ref) != SYMBOL_REF)
18921 /* System V adds '.' to the internal name, so skip them. */
18922 call_name = XSTR (call_ref, 0);
18923 if (*call_name == '.')
18925 while (*call_name == '.')
18928 node = get_identifier (call_name);
18929 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
18932 return force_reg (Pmode, call_ref);
18935 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
18936 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
18939 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
18940 struct attribute_spec.handler. */
18942 rs6000_handle_struct_attribute (tree *node, tree name,
18943 tree args ATTRIBUTE_UNUSED,
18944 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
18947 if (DECL_P (*node))
18949 if (TREE_CODE (*node) == TYPE_DECL)
18950 type = &TREE_TYPE (*node);
18955 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
18956 || TREE_CODE (*type) == UNION_TYPE)))
18958 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
18959 *no_add_attrs = true;
18962 else if ((is_attribute_p ("ms_struct", name)
18963 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
18964 || ((is_attribute_p ("gcc_struct", name)
18965 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
18967 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
18968 IDENTIFIER_POINTER (name));
18969 *no_add_attrs = true;
18976 rs6000_ms_bitfield_layout_p (tree record_type)
18978 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
18979 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
18980 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
18983 #ifdef USING_ELFOS_H
18985 /* A get_unnamed_section callback, used for switching to toc_section. */
18988 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18990 if (DEFAULT_ABI == ABI_AIX
18991 && TARGET_MINIMAL_TOC
18992 && !TARGET_RELOCATABLE)
18994 if (!toc_initialized)
18996 toc_initialized = 1;
18997 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
18998 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
18999 fprintf (asm_out_file, "\t.tc ");
19000 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
19001 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19002 fprintf (asm_out_file, "\n");
19004 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19005 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19006 fprintf (asm_out_file, " = .+32768\n");
19009 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19011 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
19012 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19015 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19016 if (!toc_initialized)
19018 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19019 fprintf (asm_out_file, " = .+32768\n");
19020 toc_initialized = 1;
19025 /* Implement TARGET_ASM_INIT_SECTIONS. */
19028 rs6000_elf_asm_init_sections (void)
19031 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
19034 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
19035 SDATA2_SECTION_ASM_OP);
19038 /* Implement TARGET_SELECT_RTX_SECTION. */
19041 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
19042 unsigned HOST_WIDE_INT align)
19044 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19045 return toc_section;
19047 return default_elf_select_rtx_section (mode, x, align);
19050 /* For a SYMBOL_REF, set generic flags and then perform some
19051 target-specific processing.
19053 When the AIX ABI is requested on a non-AIX system, replace the
19054 function name with the real name (with a leading .) rather than the
19055 function descriptor name. This saves a lot of overriding code to
19056 read the prefixes. */
19059 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
19061 default_encode_section_info (decl, rtl, first);
19064 && TREE_CODE (decl) == FUNCTION_DECL
19066 && DEFAULT_ABI == ABI_AIX)
19068 rtx sym_ref = XEXP (rtl, 0);
19069 size_t len = strlen (XSTR (sym_ref, 0));
19070 char *str = alloca (len + 2);
19072 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
19073 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
19078 rs6000_elf_in_small_data_p (tree decl)
19080 if (rs6000_sdata == SDATA_NONE)
19083 /* We want to merge strings, so we never consider them small data. */
19084 if (TREE_CODE (decl) == STRING_CST)
19087 /* Functions are never in the small data area. */
19088 if (TREE_CODE (decl) == FUNCTION_DECL)
19091 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
19093 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
19094 if (strcmp (section, ".sdata") == 0
19095 || strcmp (section, ".sdata2") == 0
19096 || strcmp (section, ".sbss") == 0
19097 || strcmp (section, ".sbss2") == 0
19098 || strcmp (section, ".PPC.EMB.sdata0") == 0
19099 || strcmp (section, ".PPC.EMB.sbss0") == 0)
19104 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
19107 && (unsigned HOST_WIDE_INT) size <= g_switch_value
19108 /* If it's not public, and we're not going to reference it there,
19109 there's no need to put it in the small data section. */
19110 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
19117 #endif /* USING_ELFOS_H */
19119 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
19122 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
19124 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
19127 /* Return a REG that occurs in ADDR with coefficient 1.
19128 ADDR can be effectively incremented by incrementing REG.
19130 r0 is special and we must not select it as an address
19131 register by this routine since our caller will try to
19132 increment the returned register via an "la" instruction. */
19135 find_addr_reg (rtx addr)
19137 while (GET_CODE (addr) == PLUS)
19139 if (GET_CODE (XEXP (addr, 0)) == REG
19140 && REGNO (XEXP (addr, 0)) != 0)
19141 addr = XEXP (addr, 0);
19142 else if (GET_CODE (XEXP (addr, 1)) == REG
19143 && REGNO (XEXP (addr, 1)) != 0)
19144 addr = XEXP (addr, 1);
19145 else if (CONSTANT_P (XEXP (addr, 0)))
19146 addr = XEXP (addr, 1);
19147 else if (CONSTANT_P (XEXP (addr, 1)))
19148 addr = XEXP (addr, 0);
19150 gcc_unreachable ();
19152 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
19157 rs6000_fatal_bad_address (rtx op)
19159 fatal_insn ("bad address", op);
19164 static tree branch_island_list = 0;
19166 /* Remember to generate a branch island for far calls to the given
19170 add_compiler_branch_island (tree label_name, tree function_name,
19173 tree branch_island = build_tree_list (function_name, label_name);
19174 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
19175 TREE_CHAIN (branch_island) = branch_island_list;
19176 branch_island_list = branch_island;
19179 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
19180 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
19181 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
19182 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
19184 /* Generate far-jump branch islands for everything on the
19185 branch_island_list. Invoked immediately after the last instruction
19186 of the epilogue has been emitted; the branch-islands must be
19187 appended to, and contiguous with, the function body. Mach-O stubs
19188 are generated in machopic_output_stub(). */
19191 macho_branch_islands (void)
19194 tree branch_island;
19196 for (branch_island = branch_island_list;
19198 branch_island = TREE_CHAIN (branch_island))
19200 const char *label =
19201 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
19203 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
19204 char name_buf[512];
19205 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
19206 if (name[0] == '*' || name[0] == '&')
19207 strcpy (name_buf, name+1);
19211 strcpy (name_buf+1, name);
19213 strcpy (tmp_buf, "\n");
19214 strcat (tmp_buf, label);
19215 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19216 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19217 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19218 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19221 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
19222 strcat (tmp_buf, label);
19223 strcat (tmp_buf, "_pic\n");
19224 strcat (tmp_buf, label);
19225 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
19227 strcat (tmp_buf, "\taddis r11,r11,ha16(");
19228 strcat (tmp_buf, name_buf);
19229 strcat (tmp_buf, " - ");
19230 strcat (tmp_buf, label);
19231 strcat (tmp_buf, "_pic)\n");
19233 strcat (tmp_buf, "\tmtlr r0\n");
19235 strcat (tmp_buf, "\taddi r12,r11,lo16(");
19236 strcat (tmp_buf, name_buf);
19237 strcat (tmp_buf, " - ");
19238 strcat (tmp_buf, label);
19239 strcat (tmp_buf, "_pic)\n");
19241 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
19245 strcat (tmp_buf, ":\nlis r12,hi16(");
19246 strcat (tmp_buf, name_buf);
19247 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
19248 strcat (tmp_buf, name_buf);
19249 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
19251 output_asm_insn (tmp_buf, 0);
19252 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19253 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19254 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19255 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19258 branch_island_list = 0;
19261 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
19262 already there or not. */
19265 no_previous_def (tree function_name)
19267 tree branch_island;
19268 for (branch_island = branch_island_list;
19270 branch_island = TREE_CHAIN (branch_island))
19271 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19276 /* GET_PREV_LABEL gets the label name from the previous definition of
19280 get_prev_label (tree function_name)
19282 tree branch_island;
19283 for (branch_island = branch_island_list;
19285 branch_island = TREE_CHAIN (branch_island))
19286 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19287 return BRANCH_ISLAND_LABEL_NAME (branch_island);
19291 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
19292 #define DARWIN_LINKER_GENERATES_ISLANDS 0
19295 /* KEXTs still need branch islands. */
19296 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
19297 || flag_mkernel || flag_apple_kext)
19299 /* INSN is either a function call or a millicode call. It may have an
19300 unconditional jump in its delay slot.
19302 CALL_DEST is the routine we are calling. */
19305 output_call (rtx insn, rtx *operands, int dest_operand_number,
19306 int cookie_operand_number)
19308 static char buf[256];
19309 if (DARWIN_GENERATE_ISLANDS
19310 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
19311 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
19314 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
19316 if (no_previous_def (funname))
19318 rtx label_rtx = gen_label_rtx ();
19319 char *label_buf, temp_buf[256];
19320 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
19321 CODE_LABEL_NUMBER (label_rtx));
19322 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
19323 labelname = get_identifier (label_buf);
19324 add_compiler_branch_island (labelname, funname, insn_line (insn));
19327 labelname = get_prev_label (funname);
19329 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
19330 instruction will reach 'foo', otherwise link as 'bl L42'".
19331 "L42" should be a 'branch island', that will do a far jump to
19332 'foo'. Branch islands are generated in
19333 macho_branch_islands(). */
19334 sprintf (buf, "jbsr %%z%d,%.246s",
19335 dest_operand_number, IDENTIFIER_POINTER (labelname));
19338 sprintf (buf, "bl %%z%d", dest_operand_number);
19342 /* Generate PIC and indirect symbol stubs. */
19345 machopic_output_stub (FILE *file, const char *symb, const char *stub)
19347 unsigned int length;
19348 char *symbol_name, *lazy_ptr_name;
19349 char *local_label_0;
19350 static int label = 0;
19352 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19353 symb = (*targetm.strip_name_encoding) (symb);
19356 length = strlen (symb);
19357 symbol_name = alloca (length + 32);
19358 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
19360 lazy_ptr_name = alloca (length + 32);
19361 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
19364 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
19366 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
19370 fprintf (file, "\t.align 5\n");
19372 fprintf (file, "%s:\n", stub);
19373 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19376 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
19377 sprintf (local_label_0, "\"L%011d$spb\"", label);
19379 fprintf (file, "\tmflr r0\n");
19380 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
19381 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
19382 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
19383 lazy_ptr_name, local_label_0);
19384 fprintf (file, "\tmtlr r0\n");
19385 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
19386 (TARGET_64BIT ? "ldu" : "lwzu"),
19387 lazy_ptr_name, local_label_0);
19388 fprintf (file, "\tmtctr r12\n");
19389 fprintf (file, "\tbctr\n");
19393 fprintf (file, "\t.align 4\n");
19395 fprintf (file, "%s:\n", stub);
19396 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19398 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
19399 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
19400 (TARGET_64BIT ? "ldu" : "lwzu"),
19402 fprintf (file, "\tmtctr r12\n");
19403 fprintf (file, "\tbctr\n");
19406 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
19407 fprintf (file, "%s:\n", lazy_ptr_name);
19408 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19409 fprintf (file, "%sdyld_stub_binding_helper\n",
19410 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
19413 /* Legitimize PIC addresses. If the address is already
19414 position-independent, we return ORIG. Newly generated
19415 position-independent addresses go into a reg. This is REG if non
19416 zero, otherwise we allocate register(s) as necessary. */
19418 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
19421 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
19426 if (reg == NULL && ! reload_in_progress && ! reload_completed)
19427 reg = gen_reg_rtx (Pmode);
19429 if (GET_CODE (orig) == CONST)
19433 if (GET_CODE (XEXP (orig, 0)) == PLUS
19434 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
19437 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
19439 /* Use a different reg for the intermediate value, as
19440 it will be marked UNCHANGING. */
19441 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
19442 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
19445 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
19448 if (GET_CODE (offset) == CONST_INT)
19450 if (SMALL_INT (offset))
19451 return plus_constant (base, INTVAL (offset));
19452 else if (! reload_in_progress && ! reload_completed)
19453 offset = force_reg (Pmode, offset);
19456 rtx mem = force_const_mem (Pmode, orig);
19457 return machopic_legitimize_pic_address (mem, Pmode, reg);
19460 return gen_rtx_PLUS (Pmode, base, offset);
19463 /* Fall back on generic machopic code. */
19464 return machopic_legitimize_pic_address (orig, mode, reg);
19467 /* Output a .machine directive for the Darwin assembler, and call
19468 the generic start_file routine. */
19471 rs6000_darwin_file_start (void)
19473 static const struct
19479 { "ppc64", "ppc64", MASK_64BIT },
19480 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
19481 { "power4", "ppc970", 0 },
19482 { "G5", "ppc970", 0 },
19483 { "7450", "ppc7450", 0 },
19484 { "7400", "ppc7400", MASK_ALTIVEC },
19485 { "G4", "ppc7400", 0 },
19486 { "750", "ppc750", 0 },
19487 { "740", "ppc750", 0 },
19488 { "G3", "ppc750", 0 },
19489 { "604e", "ppc604e", 0 },
19490 { "604", "ppc604", 0 },
19491 { "603e", "ppc603", 0 },
19492 { "603", "ppc603", 0 },
19493 { "601", "ppc601", 0 },
19494 { NULL, "ppc", 0 } };
19495 const char *cpu_id = "";
19498 rs6000_file_start ();
19499 darwin_file_start ();
19501 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
19502 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
19503 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
19504 && rs6000_select[i].string[0] != '\0')
19505 cpu_id = rs6000_select[i].string;
19507 /* Look through the mapping array. Pick the first name that either
19508 matches the argument, has a bit set in IF_SET that is also set
19509 in the target flags, or has a NULL name. */
19512 while (mapping[i].arg != NULL
19513 && strcmp (mapping[i].arg, cpu_id) != 0
19514 && (mapping[i].if_set & target_flags) == 0)
19517 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
19520 #endif /* TARGET_MACHO */
19524 rs6000_elf_reloc_rw_mask (void)
19528 else if (DEFAULT_ABI == ABI_AIX)
19534 /* Record an element in the table of global constructors. SYMBOL is
19535 a SYMBOL_REF of the function to be called; PRIORITY is a number
19536 between 0 and MAX_INIT_PRIORITY.
19538 This differs from default_named_section_asm_out_constructor in
19539 that we have special handling for -mrelocatable. */
19542 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
19544 const char *section = ".ctors";
19547 if (priority != DEFAULT_INIT_PRIORITY)
19549 sprintf (buf, ".ctors.%.5u",
19550 /* Invert the numbering so the linker puts us in the proper
19551 order; constructors are run from right to left, and the
19552 linker sorts in increasing order. */
19553 MAX_INIT_PRIORITY - priority);
19557 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19558 assemble_align (POINTER_SIZE);
19560 if (TARGET_RELOCATABLE)
19562 fputs ("\t.long (", asm_out_file);
19563 output_addr_const (asm_out_file, symbol);
19564 fputs (")@fixup\n", asm_out_file);
19567 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19571 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
19573 const char *section = ".dtors";
19576 if (priority != DEFAULT_INIT_PRIORITY)
19578 sprintf (buf, ".dtors.%.5u",
19579 /* Invert the numbering so the linker puts us in the proper
19580 order; constructors are run from right to left, and the
19581 linker sorts in increasing order. */
19582 MAX_INIT_PRIORITY - priority);
19586 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19587 assemble_align (POINTER_SIZE);
19589 if (TARGET_RELOCATABLE)
19591 fputs ("\t.long (", asm_out_file);
19592 output_addr_const (asm_out_file, symbol);
19593 fputs (")@fixup\n", asm_out_file);
19596 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19600 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
19604 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
19605 ASM_OUTPUT_LABEL (file, name);
19606 fputs (DOUBLE_INT_ASM_OP, file);
19607 rs6000_output_function_entry (file, name);
19608 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
19611 fputs ("\t.size\t", file);
19612 assemble_name (file, name);
19613 fputs (",24\n\t.type\t.", file);
19614 assemble_name (file, name);
19615 fputs (",@function\n", file);
19616 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
19618 fputs ("\t.globl\t.", file);
19619 assemble_name (file, name);
19624 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19625 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19626 rs6000_output_function_entry (file, name);
19627 fputs (":\n", file);
19631 if (TARGET_RELOCATABLE
19632 && !TARGET_SECURE_PLT
19633 && (get_pool_size () != 0 || current_function_profile)
19638 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
19640 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
19641 fprintf (file, "\t.long ");
19642 assemble_name (file, buf);
19644 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
19645 assemble_name (file, buf);
19649 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19650 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19652 if (DEFAULT_ABI == ABI_AIX)
19654 const char *desc_name, *orig_name;
19656 orig_name = (*targetm.strip_name_encoding) (name);
19657 desc_name = orig_name;
19658 while (*desc_name == '.')
19661 if (TREE_PUBLIC (decl))
19662 fprintf (file, "\t.globl %s\n", desc_name);
19664 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19665 fprintf (file, "%s:\n", desc_name);
19666 fprintf (file, "\t.long %s\n", orig_name);
19667 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
19668 if (DEFAULT_ABI == ABI_AIX)
19669 fputs ("\t.long 0\n", file);
19670 fprintf (file, "\t.previous\n");
19672 ASM_OUTPUT_LABEL (file, name);
19676 rs6000_elf_end_indicate_exec_stack (void)
19679 file_end_indicate_exec_stack ();
19685 rs6000_xcoff_asm_output_anchor (rtx symbol)
19689 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
19690 SYMBOL_REF_BLOCK_OFFSET (symbol));
19691 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
19695 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
19697 fputs (GLOBAL_ASM_OP, stream);
19698 RS6000_OUTPUT_BASENAME (stream, name);
19699 putc ('\n', stream);
19702 /* A get_unnamed_decl callback, used for read-only sections. PTR
19703 points to the section string variable. */
19706 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
19708 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
19709 *(const char *const *) directive);
19712 /* Likewise for read-write sections. */
19715 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
19717 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
19718 *(const char *const *) directive);
19721 /* A get_unnamed_section callback, used for switching to toc_section. */
19724 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19726 if (TARGET_MINIMAL_TOC)
19728 /* toc_section is always selected at least once from
19729 rs6000_xcoff_file_start, so this is guaranteed to
19730 always be defined once and only once in each file. */
19731 if (!toc_initialized)
19733 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
19734 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
19735 toc_initialized = 1;
19737 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
19738 (TARGET_32BIT ? "" : ",3"));
19741 fputs ("\t.toc\n", asm_out_file);
19744 /* Implement TARGET_ASM_INIT_SECTIONS. */
19747 rs6000_xcoff_asm_init_sections (void)
19749 read_only_data_section
19750 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19751 &xcoff_read_only_section_name);
19753 private_data_section
19754 = get_unnamed_section (SECTION_WRITE,
19755 rs6000_xcoff_output_readwrite_section_asm_op,
19756 &xcoff_private_data_section_name);
19758 read_only_private_data_section
19759 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19760 &xcoff_private_data_section_name);
19763 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
19765 readonly_data_section = read_only_data_section;
19766 exception_section = data_section;
19770 rs6000_xcoff_reloc_rw_mask (void)
19776 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
19777 tree decl ATTRIBUTE_UNUSED)
19780 static const char * const suffix[3] = { "PR", "RO", "RW" };
19782 if (flags & SECTION_CODE)
19784 else if (flags & SECTION_WRITE)
19789 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
19790 (flags & SECTION_CODE) ? "." : "",
19791 name, suffix[smclass], flags & SECTION_ENTSIZE);
19795 rs6000_xcoff_select_section (tree decl, int reloc,
19796 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19798 if (decl_readonly_section (decl, reloc))
19800 if (TREE_PUBLIC (decl))
19801 return read_only_data_section;
19803 return read_only_private_data_section;
19807 if (TREE_PUBLIC (decl))
19808 return data_section;
19810 return private_data_section;
19815 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
19819 /* Use select_section for private and uninitialized data. */
19820 if (!TREE_PUBLIC (decl)
19821 || DECL_COMMON (decl)
19822 || DECL_INITIAL (decl) == NULL_TREE
19823 || DECL_INITIAL (decl) == error_mark_node
19824 || (flag_zero_initialized_in_bss
19825 && initializer_zerop (DECL_INITIAL (decl))))
19828 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
19829 name = (*targetm.strip_name_encoding) (name);
19830 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
19833 /* Select section for constant in constant pool.
19835 On RS/6000, all constants are in the private read-only data area.
19836 However, if this is being placed in the TOC it must be output as a
19840 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
19841 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19843 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19844 return toc_section;
19846 return read_only_private_data_section;
19849 /* Remove any trailing [DS] or the like from the symbol name. */
19851 static const char *
19852 rs6000_xcoff_strip_name_encoding (const char *name)
19857 len = strlen (name);
19858 if (name[len - 1] == ']')
19859 return ggc_alloc_string (name, len - 4);
19864 /* Section attributes. AIX is always PIC. */
19866 static unsigned int
19867 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
19869 unsigned int align;
19870 unsigned int flags = default_section_type_flags (decl, name, reloc);
19872 /* Align to at least UNIT size. */
19873 if (flags & SECTION_CODE)
19874 align = MIN_UNITS_PER_WORD;
19876 /* Increase alignment of large objects if not already stricter. */
19877 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
19878 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
19879 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
19881 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
19884 /* Output at beginning of assembler file.
19886 Initialize the section names for the RS/6000 at this point.
19888 Specify filename, including full path, to assembler.
19890 We want to go into the TOC section so at least one .toc will be emitted.
19891 Also, in order to output proper .bs/.es pairs, we need at least one static
19892 [RW] section emitted.
19894 Finally, declare mcount when profiling to make the assembler happy. */
19897 rs6000_xcoff_file_start (void)
19899 rs6000_gen_section_name (&xcoff_bss_section_name,
19900 main_input_filename, ".bss_");
19901 rs6000_gen_section_name (&xcoff_private_data_section_name,
19902 main_input_filename, ".rw_");
19903 rs6000_gen_section_name (&xcoff_read_only_section_name,
19904 main_input_filename, ".ro_");
19906 fputs ("\t.file\t", asm_out_file);
19907 output_quoted_string (asm_out_file, main_input_filename);
19908 fputc ('\n', asm_out_file);
19909 if (write_symbols != NO_DEBUG)
19910 switch_to_section (private_data_section);
19911 switch_to_section (text_section);
19913 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
19914 rs6000_file_start ();
19917 /* Output at end of assembler file.
19918 On the RS/6000, referencing data should automatically pull in text. */
19921 rs6000_xcoff_file_end (void)
19923 switch_to_section (text_section);
19924 fputs ("_section_.text:\n", asm_out_file);
19925 switch_to_section (data_section);
19926 fputs (TARGET_32BIT
19927 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
19930 #endif /* TARGET_XCOFF */
19932 /* Compute a (partial) cost for rtx X. Return true if the complete
19933 cost has been computed, and false if subexpressions should be
19934 scanned. In either case, *TOTAL contains the cost result. */
19937 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
19939 enum machine_mode mode = GET_MODE (x);
19943 /* On the RS/6000, if it is valid in the insn, it is free. */
19945 if (((outer_code == SET
19946 || outer_code == PLUS
19947 || outer_code == MINUS)
19948 && (satisfies_constraint_I (x)
19949 || satisfies_constraint_L (x)))
19950 || (outer_code == AND
19951 && (satisfies_constraint_K (x)
19953 ? satisfies_constraint_L (x)
19954 : satisfies_constraint_J (x))
19955 || mask_operand (x, mode)
19957 && mask64_operand (x, DImode))))
19958 || ((outer_code == IOR || outer_code == XOR)
19959 && (satisfies_constraint_K (x)
19961 ? satisfies_constraint_L (x)
19962 : satisfies_constraint_J (x))))
19963 || outer_code == ASHIFT
19964 || outer_code == ASHIFTRT
19965 || outer_code == LSHIFTRT
19966 || outer_code == ROTATE
19967 || outer_code == ROTATERT
19968 || outer_code == ZERO_EXTRACT
19969 || (outer_code == MULT
19970 && satisfies_constraint_I (x))
19971 || ((outer_code == DIV || outer_code == UDIV
19972 || outer_code == MOD || outer_code == UMOD)
19973 && exact_log2 (INTVAL (x)) >= 0)
19974 || (outer_code == COMPARE
19975 && (satisfies_constraint_I (x)
19976 || satisfies_constraint_K (x)))
19977 || (outer_code == EQ
19978 && (satisfies_constraint_I (x)
19979 || satisfies_constraint_K (x)
19981 ? satisfies_constraint_L (x)
19982 : satisfies_constraint_J (x))))
19983 || (outer_code == GTU
19984 && satisfies_constraint_I (x))
19985 || (outer_code == LTU
19986 && satisfies_constraint_P (x)))
19991 else if ((outer_code == PLUS
19992 && reg_or_add_cint_operand (x, VOIDmode))
19993 || (outer_code == MINUS
19994 && reg_or_sub_cint_operand (x, VOIDmode))
19995 || ((outer_code == SET
19996 || outer_code == IOR
19997 || outer_code == XOR)
19999 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
20001 *total = COSTS_N_INSNS (1);
20007 if (mode == DImode && code == CONST_DOUBLE)
20009 if ((outer_code == IOR || outer_code == XOR)
20010 && CONST_DOUBLE_HIGH (x) == 0
20011 && (CONST_DOUBLE_LOW (x)
20012 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
20017 else if ((outer_code == AND && and64_2_operand (x, DImode))
20018 || ((outer_code == SET
20019 || outer_code == IOR
20020 || outer_code == XOR)
20021 && CONST_DOUBLE_HIGH (x) == 0))
20023 *total = COSTS_N_INSNS (1);
20033 /* When optimizing for size, MEM should be slightly more expensive
20034 than generating address, e.g., (plus (reg) (const)).
20035 L1 cache latency is about two instructions. */
20036 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
20044 if (mode == DFmode)
20046 if (GET_CODE (XEXP (x, 0)) == MULT)
20048 /* FNMA accounted in outer NEG. */
20049 if (outer_code == NEG)
20050 *total = rs6000_cost->dmul - rs6000_cost->fp;
20052 *total = rs6000_cost->dmul;
20055 *total = rs6000_cost->fp;
20057 else if (mode == SFmode)
20059 /* FNMA accounted in outer NEG. */
20060 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20063 *total = rs6000_cost->fp;
20066 *total = COSTS_N_INSNS (1);
20070 if (mode == DFmode)
20072 if (GET_CODE (XEXP (x, 0)) == MULT
20073 || GET_CODE (XEXP (x, 1)) == MULT)
20075 /* FNMA accounted in outer NEG. */
20076 if (outer_code == NEG)
20077 *total = rs6000_cost->dmul - rs6000_cost->fp;
20079 *total = rs6000_cost->dmul;
20082 *total = rs6000_cost->fp;
20084 else if (mode == SFmode)
20086 /* FNMA accounted in outer NEG. */
20087 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20090 *total = rs6000_cost->fp;
20093 *total = COSTS_N_INSNS (1);
20097 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20098 && satisfies_constraint_I (XEXP (x, 1)))
20100 if (INTVAL (XEXP (x, 1)) >= -256
20101 && INTVAL (XEXP (x, 1)) <= 255)
20102 *total = rs6000_cost->mulsi_const9;
20104 *total = rs6000_cost->mulsi_const;
20106 /* FMA accounted in outer PLUS/MINUS. */
20107 else if ((mode == DFmode || mode == SFmode)
20108 && (outer_code == PLUS || outer_code == MINUS))
20110 else if (mode == DFmode)
20111 *total = rs6000_cost->dmul;
20112 else if (mode == SFmode)
20113 *total = rs6000_cost->fp;
20114 else if (mode == DImode)
20115 *total = rs6000_cost->muldi;
20117 *total = rs6000_cost->mulsi;
20122 if (FLOAT_MODE_P (mode))
20124 *total = mode == DFmode ? rs6000_cost->ddiv
20125 : rs6000_cost->sdiv;
20132 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20133 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
20135 if (code == DIV || code == MOD)
20137 *total = COSTS_N_INSNS (2);
20140 *total = COSTS_N_INSNS (1);
20144 if (GET_MODE (XEXP (x, 1)) == DImode)
20145 *total = rs6000_cost->divdi;
20147 *total = rs6000_cost->divsi;
20149 /* Add in shift and subtract for MOD. */
20150 if (code == MOD || code == UMOD)
20151 *total += COSTS_N_INSNS (2);
20155 *total = COSTS_N_INSNS (4);
20159 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
20170 *total = COSTS_N_INSNS (1);
20178 /* Handle mul_highpart. */
20179 if (outer_code == TRUNCATE
20180 && GET_CODE (XEXP (x, 0)) == MULT)
20182 if (mode == DImode)
20183 *total = rs6000_cost->muldi;
20185 *total = rs6000_cost->mulsi;
20188 else if (outer_code == AND)
20191 *total = COSTS_N_INSNS (1);
20196 if (GET_CODE (XEXP (x, 0)) == MEM)
20199 *total = COSTS_N_INSNS (1);
20205 if (!FLOAT_MODE_P (mode))
20207 *total = COSTS_N_INSNS (1);
20213 case UNSIGNED_FLOAT:
20216 case FLOAT_TRUNCATE:
20217 *total = rs6000_cost->fp;
20221 if (mode == DFmode)
20224 *total = rs6000_cost->fp;
20228 switch (XINT (x, 1))
20231 *total = rs6000_cost->fp;
20243 *total = COSTS_N_INSNS (1);
20246 else if (FLOAT_MODE_P (mode)
20247 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
20249 *total = rs6000_cost->fp;
20257 /* Carry bit requires mode == Pmode.
20258 NEG or PLUS already counted so only add one. */
20260 && (outer_code == NEG || outer_code == PLUS))
20262 *total = COSTS_N_INSNS (1);
20265 if (outer_code == SET)
20267 if (XEXP (x, 1) == const0_rtx)
20269 *total = COSTS_N_INSNS (2);
20272 else if (mode == Pmode)
20274 *total = COSTS_N_INSNS (3);
20283 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
20285 *total = COSTS_N_INSNS (2);
20289 if (outer_code == COMPARE)
20303 /* A C expression returning the cost of moving data from a register of class
20304 CLASS1 to one of CLASS2. */
20307 rs6000_register_move_cost (enum machine_mode mode,
20308 enum reg_class from, enum reg_class to)
20310 /* Moves from/to GENERAL_REGS. */
20311 if (reg_classes_intersect_p (to, GENERAL_REGS)
20312 || reg_classes_intersect_p (from, GENERAL_REGS))
20314 if (! reg_classes_intersect_p (to, GENERAL_REGS))
20317 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
20318 return (rs6000_memory_move_cost (mode, from, 0)
20319 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
20321 /* It's more expensive to move CR_REGS than CR0_REGS because of the
20323 else if (from == CR_REGS)
20327 /* A move will cost one instruction per GPR moved. */
20328 return 2 * hard_regno_nregs[0][mode];
20331 /* Moving between two similar registers is just one instruction. */
20332 else if (reg_classes_intersect_p (to, from))
20333 return (mode == TFmode || mode == TDmode) ? 4 : 2;
20335 /* Everything else has to go through GENERAL_REGS. */
20337 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
20338 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
20341 /* A C expressions returning the cost of moving data of MODE from a register to
20345 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
20346 int in ATTRIBUTE_UNUSED)
20348 if (reg_classes_intersect_p (class, GENERAL_REGS))
20349 return 4 * hard_regno_nregs[0][mode];
20350 else if (reg_classes_intersect_p (class, FLOAT_REGS))
20351 return 4 * hard_regno_nregs[32][mode];
20352 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
20353 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
20355 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
20358 /* Newton-Raphson approximation of single-precision floating point divide n/d.
20359 Assumes no trapping math and finite arguments. */
20362 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
20364 rtx x0, e0, e1, y1, u0, v0, one;
20366 x0 = gen_reg_rtx (SFmode);
20367 e0 = gen_reg_rtx (SFmode);
20368 e1 = gen_reg_rtx (SFmode);
20369 y1 = gen_reg_rtx (SFmode);
20370 u0 = gen_reg_rtx (SFmode);
20371 v0 = gen_reg_rtx (SFmode);
20372 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
20374 /* x0 = 1./d estimate */
20375 emit_insn (gen_rtx_SET (VOIDmode, x0,
20376 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
20378 /* e0 = 1. - d * x0 */
20379 emit_insn (gen_rtx_SET (VOIDmode, e0,
20380 gen_rtx_MINUS (SFmode, one,
20381 gen_rtx_MULT (SFmode, d, x0))));
20382 /* e1 = e0 + e0 * e0 */
20383 emit_insn (gen_rtx_SET (VOIDmode, e1,
20384 gen_rtx_PLUS (SFmode,
20385 gen_rtx_MULT (SFmode, e0, e0), e0)));
20386 /* y1 = x0 + e1 * x0 */
20387 emit_insn (gen_rtx_SET (VOIDmode, y1,
20388 gen_rtx_PLUS (SFmode,
20389 gen_rtx_MULT (SFmode, e1, x0), x0)));
20391 emit_insn (gen_rtx_SET (VOIDmode, u0,
20392 gen_rtx_MULT (SFmode, n, y1)));
20393 /* v0 = n - d * u0 */
20394 emit_insn (gen_rtx_SET (VOIDmode, v0,
20395 gen_rtx_MINUS (SFmode, n,
20396 gen_rtx_MULT (SFmode, d, u0))));
20397 /* res = u0 + v0 * y1 */
20398 emit_insn (gen_rtx_SET (VOIDmode, res,
20399 gen_rtx_PLUS (SFmode,
20400 gen_rtx_MULT (SFmode, v0, y1), u0)));
20403 /* Newton-Raphson approximation of double-precision floating point divide n/d.
20404 Assumes no trapping math and finite arguments. */
20407 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
20409 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
20411 x0 = gen_reg_rtx (DFmode);
20412 e0 = gen_reg_rtx (DFmode);
20413 e1 = gen_reg_rtx (DFmode);
20414 e2 = gen_reg_rtx (DFmode);
20415 y1 = gen_reg_rtx (DFmode);
20416 y2 = gen_reg_rtx (DFmode);
20417 y3 = gen_reg_rtx (DFmode);
20418 u0 = gen_reg_rtx (DFmode);
20419 v0 = gen_reg_rtx (DFmode);
20420 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
20422 /* x0 = 1./d estimate */
20423 emit_insn (gen_rtx_SET (VOIDmode, x0,
20424 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
20426 /* e0 = 1. - d * x0 */
20427 emit_insn (gen_rtx_SET (VOIDmode, e0,
20428 gen_rtx_MINUS (DFmode, one,
20429 gen_rtx_MULT (SFmode, d, x0))));
20430 /* y1 = x0 + e0 * x0 */
20431 emit_insn (gen_rtx_SET (VOIDmode, y1,
20432 gen_rtx_PLUS (DFmode,
20433 gen_rtx_MULT (DFmode, e0, x0), x0)));
20435 emit_insn (gen_rtx_SET (VOIDmode, e1,
20436 gen_rtx_MULT (DFmode, e0, e0)));
20437 /* y2 = y1 + e1 * y1 */
20438 emit_insn (gen_rtx_SET (VOIDmode, y2,
20439 gen_rtx_PLUS (DFmode,
20440 gen_rtx_MULT (DFmode, e1, y1), y1)));
20442 emit_insn (gen_rtx_SET (VOIDmode, e2,
20443 gen_rtx_MULT (DFmode, e1, e1)));
20444 /* y3 = y2 + e2 * y2 */
20445 emit_insn (gen_rtx_SET (VOIDmode, y3,
20446 gen_rtx_PLUS (DFmode,
20447 gen_rtx_MULT (DFmode, e2, y2), y2)));
20449 emit_insn (gen_rtx_SET (VOIDmode, u0,
20450 gen_rtx_MULT (DFmode, n, y3)));
20451 /* v0 = n - d * u0 */
20452 emit_insn (gen_rtx_SET (VOIDmode, v0,
20453 gen_rtx_MINUS (DFmode, n,
20454 gen_rtx_MULT (DFmode, d, u0))));
20455 /* res = u0 + v0 * y3 */
20456 emit_insn (gen_rtx_SET (VOIDmode, res,
20457 gen_rtx_PLUS (DFmode,
20458 gen_rtx_MULT (DFmode, v0, y3), u0)));
20462 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
20463 target, and SRC is the argument operand. */
20466 rs6000_emit_popcount (rtx dst, rtx src)
20468 enum machine_mode mode = GET_MODE (dst);
20471 tmp1 = gen_reg_rtx (mode);
20473 if (mode == SImode)
20475 emit_insn (gen_popcntbsi2 (tmp1, src));
20476 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
20478 tmp2 = force_reg (SImode, tmp2);
20479 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
20483 emit_insn (gen_popcntbdi2 (tmp1, src));
20484 tmp2 = expand_mult (DImode, tmp1,
20485 GEN_INT ((HOST_WIDE_INT)
20486 0x01010101 << 32 | 0x01010101),
20488 tmp2 = force_reg (DImode, tmp2);
20489 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
20494 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
20495 target, and SRC is the argument operand. */
20498 rs6000_emit_parity (rtx dst, rtx src)
20500 enum machine_mode mode = GET_MODE (dst);
20503 tmp = gen_reg_rtx (mode);
20504 if (mode == SImode)
20506 /* Is mult+shift >= shift+xor+shift+xor? */
20507 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
20509 rtx tmp1, tmp2, tmp3, tmp4;
20511 tmp1 = gen_reg_rtx (SImode);
20512 emit_insn (gen_popcntbsi2 (tmp1, src));
20514 tmp2 = gen_reg_rtx (SImode);
20515 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
20516 tmp3 = gen_reg_rtx (SImode);
20517 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
20519 tmp4 = gen_reg_rtx (SImode);
20520 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
20521 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
20524 rs6000_emit_popcount (tmp, src);
20525 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
20529 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
20530 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
20532 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
20534 tmp1 = gen_reg_rtx (DImode);
20535 emit_insn (gen_popcntbdi2 (tmp1, src));
20537 tmp2 = gen_reg_rtx (DImode);
20538 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
20539 tmp3 = gen_reg_rtx (DImode);
20540 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
20542 tmp4 = gen_reg_rtx (DImode);
20543 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
20544 tmp5 = gen_reg_rtx (DImode);
20545 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
20547 tmp6 = gen_reg_rtx (DImode);
20548 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
20549 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
20552 rs6000_emit_popcount (tmp, src);
20553 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
20557 /* Return an RTX representing where to find the function value of a
20558 function returning MODE. */
20560 rs6000_complex_function_value (enum machine_mode mode)
20562 unsigned int regno;
20564 enum machine_mode inner = GET_MODE_INNER (mode);
20565 unsigned int inner_bytes = GET_MODE_SIZE (inner);
20567 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
20568 regno = FP_ARG_RETURN;
20571 regno = GP_ARG_RETURN;
20573 /* 32-bit is OK since it'll go in r3/r4. */
20574 if (TARGET_32BIT && inner_bytes >= 4)
20575 return gen_rtx_REG (mode, regno);
20578 if (inner_bytes >= 8)
20579 return gen_rtx_REG (mode, regno);
20581 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
20583 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
20584 GEN_INT (inner_bytes));
20585 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
20588 /* Define how to find the value returned by a function.
20589 VALTYPE is the data type of the value (as a tree).
20590 If the precise function being called is known, FUNC is its FUNCTION_DECL;
20591 otherwise, FUNC is 0.
20593 On the SPE, both FPs and vectors are returned in r3.
20595 On RS/6000 an integer value is in r3 and a floating-point value is in
20596 fp1, unless -msoft-float. */
20599 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
20601 enum machine_mode mode;
20602 unsigned int regno;
20604 /* Special handling for structs in darwin64. */
20605 if (rs6000_darwin64_abi
20606 && TYPE_MODE (valtype) == BLKmode
20607 && TREE_CODE (valtype) == RECORD_TYPE
20608 && int_size_in_bytes (valtype) > 0)
20610 CUMULATIVE_ARGS valcum;
20614 valcum.fregno = FP_ARG_MIN_REG;
20615 valcum.vregno = ALTIVEC_ARG_MIN_REG;
20616 /* Do a trial code generation as if this were going to be passed as
20617 an argument; if any part goes in memory, we return NULL. */
20618 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
20621 /* Otherwise fall through to standard ABI rules. */
20624 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
20626 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20627 return gen_rtx_PARALLEL (DImode,
20629 gen_rtx_EXPR_LIST (VOIDmode,
20630 gen_rtx_REG (SImode, GP_ARG_RETURN),
20632 gen_rtx_EXPR_LIST (VOIDmode,
20633 gen_rtx_REG (SImode,
20634 GP_ARG_RETURN + 1),
20637 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
20639 return gen_rtx_PARALLEL (DCmode,
20641 gen_rtx_EXPR_LIST (VOIDmode,
20642 gen_rtx_REG (SImode, GP_ARG_RETURN),
20644 gen_rtx_EXPR_LIST (VOIDmode,
20645 gen_rtx_REG (SImode,
20646 GP_ARG_RETURN + 1),
20648 gen_rtx_EXPR_LIST (VOIDmode,
20649 gen_rtx_REG (SImode,
20650 GP_ARG_RETURN + 2),
20652 gen_rtx_EXPR_LIST (VOIDmode,
20653 gen_rtx_REG (SImode,
20654 GP_ARG_RETURN + 3),
20658 mode = TYPE_MODE (valtype);
20659 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
20660 || POINTER_TYPE_P (valtype))
20661 mode = TARGET_32BIT ? SImode : DImode;
20663 if (DECIMAL_FLOAT_MODE_P (mode))
20665 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20670 gcc_unreachable ();
20672 regno = GP_ARG_RETURN;
20675 regno = FP_ARG_RETURN;
20678 /* Use f2:f3 specified by the ABI. */
20679 regno = FP_ARG_RETURN + 1;
20684 regno = GP_ARG_RETURN;
20686 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
20687 regno = FP_ARG_RETURN;
20688 else if (TREE_CODE (valtype) == COMPLEX_TYPE
20689 && targetm.calls.split_complex_arg)
20690 return rs6000_complex_function_value (mode);
20691 else if (TREE_CODE (valtype) == VECTOR_TYPE
20692 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
20693 && ALTIVEC_VECTOR_MODE (mode))
20694 regno = ALTIVEC_ARG_RETURN;
20695 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20696 && (mode == DFmode || mode == DCmode
20697 || mode == TFmode || mode == TCmode))
20698 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20700 regno = GP_ARG_RETURN;
20702 return gen_rtx_REG (mode, regno);
20705 /* Define how to find the value returned by a library function
20706 assuming the value has mode MODE. */
20708 rs6000_libcall_value (enum machine_mode mode)
20710 unsigned int regno;
20712 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
20714 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20715 return gen_rtx_PARALLEL (DImode,
20717 gen_rtx_EXPR_LIST (VOIDmode,
20718 gen_rtx_REG (SImode, GP_ARG_RETURN),
20720 gen_rtx_EXPR_LIST (VOIDmode,
20721 gen_rtx_REG (SImode,
20722 GP_ARG_RETURN + 1),
20726 if (DECIMAL_FLOAT_MODE_P (mode))
20728 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20733 gcc_unreachable ();
20735 regno = GP_ARG_RETURN;
20738 regno = FP_ARG_RETURN;
20741 /* Use f2:f3 specified by the ABI. */
20742 regno = FP_ARG_RETURN + 1;
20747 regno = GP_ARG_RETURN;
20749 else if (SCALAR_FLOAT_MODE_P (mode)
20750 && TARGET_HARD_FLOAT && TARGET_FPRS)
20751 regno = FP_ARG_RETURN;
20752 else if (ALTIVEC_VECTOR_MODE (mode)
20753 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
20754 regno = ALTIVEC_ARG_RETURN;
20755 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
20756 return rs6000_complex_function_value (mode);
20757 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20758 && (mode == DFmode || mode == DCmode
20759 || mode == TFmode || mode == TCmode))
20760 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20762 regno = GP_ARG_RETURN;
20764 return gen_rtx_REG (mode, regno);
20767 /* Define the offset between two registers, FROM to be eliminated and its
20768 replacement TO, at the start of a routine. */
20770 rs6000_initial_elimination_offset (int from, int to)
20772 rs6000_stack_t *info = rs6000_stack_info ();
20773 HOST_WIDE_INT offset;
20775 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20776 offset = info->push_p ? 0 : -info->total_size;
20777 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20779 offset = info->push_p ? 0 : -info->total_size;
20780 if (FRAME_GROWS_DOWNWARD)
20781 offset += info->fixed_size + info->vars_size + info->parm_size;
20783 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20784 offset = FRAME_GROWS_DOWNWARD
20785 ? info->fixed_size + info->vars_size + info->parm_size
20787 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20788 offset = info->total_size;
20789 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20790 offset = info->push_p ? info->total_size : 0;
20791 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
20794 gcc_unreachable ();
20799 /* Return true if TYPE is a SPE or AltiVec opaque type. */
20802 rs6000_is_opaque_type (tree type)
20804 return (type == opaque_V2SI_type_node
20805 || type == opaque_V2SF_type_node
20806 || type == opaque_p_V2SI_type_node
20807 || type == opaque_V4SI_type_node);
20811 rs6000_dwarf_register_span (rtx reg)
20816 && (SPE_VECTOR_MODE (GET_MODE (reg))
20817 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
20822 regno = REGNO (reg);
20824 /* The duality of the SPE register size wreaks all kinds of havoc.
20825 This is a way of distinguishing r0 in 32-bits from r0 in
20828 gen_rtx_PARALLEL (VOIDmode,
20831 gen_rtx_REG (SImode, regno + 1200),
20832 gen_rtx_REG (SImode, regno))
20834 gen_rtx_REG (SImode, regno),
20835 gen_rtx_REG (SImode, regno + 1200)));
20838 /* Fill in sizes for SPE register high parts in table used by unwinder. */
20841 rs6000_init_dwarf_reg_sizes_extra (tree address)
20846 enum machine_mode mode = TYPE_MODE (char_type_node);
20847 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
20848 rtx mem = gen_rtx_MEM (BLKmode, addr);
20849 rtx value = gen_int_mode (4, mode);
20851 for (i = 1201; i < 1232; i++)
20853 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
20854 HOST_WIDE_INT offset
20855 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
20857 emit_move_insn (adjust_address (mem, mode, offset), value);
20862 /* Map internal gcc register numbers to DWARF2 register numbers. */
20865 rs6000_dbx_register_number (unsigned int regno)
20867 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
20869 if (regno == MQ_REGNO)
20871 if (regno == LINK_REGISTER_REGNUM)
20873 if (regno == COUNT_REGISTER_REGNUM)
20875 if (CR_REGNO_P (regno))
20876 return regno - CR0_REGNO + 86;
20877 if (regno == XER_REGNO)
20879 if (ALTIVEC_REGNO_P (regno))
20880 return regno - FIRST_ALTIVEC_REGNO + 1124;
20881 if (regno == VRSAVE_REGNO)
20883 if (regno == VSCR_REGNO)
20885 if (regno == SPE_ACC_REGNO)
20887 if (regno == SPEFSCR_REGNO)
20889 /* SPE high reg number. We get these values of regno from
20890 rs6000_dwarf_register_span. */
20891 gcc_assert (regno >= 1200 && regno < 1232);
20895 /* target hook eh_return_filter_mode */
20896 static enum machine_mode
20897 rs6000_eh_return_filter_mode (void)
20899 return TARGET_32BIT ? SImode : word_mode;
20902 /* Target hook for scalar_mode_supported_p. */
20904 rs6000_scalar_mode_supported_p (enum machine_mode mode)
20906 if (DECIMAL_FLOAT_MODE_P (mode))
20909 return default_scalar_mode_supported_p (mode);
20912 /* Target hook for vector_mode_supported_p. */
20914 rs6000_vector_mode_supported_p (enum machine_mode mode)
20917 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
20920 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
20927 /* Target hook for invalid_arg_for_unprototyped_fn. */
20928 static const char *
20929 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
20931 return (!rs6000_darwin64_abi
20933 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
20934 && (funcdecl == NULL_TREE
20935 || (TREE_CODE (funcdecl) == FUNCTION_DECL
20936 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
20937 ? N_("AltiVec argument passed to unprototyped function")
20941 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
20942 setup by using __stack_chk_fail_local hidden function instead of
20943 calling __stack_chk_fail directly. Otherwise it is better to call
20944 __stack_chk_fail directly. */
20947 rs6000_stack_protect_fail (void)
20949 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
20950 ? default_hidden_stack_protect_fail ()
20951 : default_external_stack_protect_fail ();
20954 #include "gt-rs6000.h"