1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
56 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
59 #ifndef TARGET_NO_PROTOTYPE
60 #define TARGET_NO_PROTOTYPE 0
63 #define EASY_VECTOR_15(n, x, y) ((n) >= -16 && (n) <= 15 \
64 && easy_vector_same (x, y))
66 #define EASY_VECTOR_15_ADD_SELF(n, x, y) ((n) >= 0x10 && (n) <= 0x1e \
68 && easy_vector_same (x, y))
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int toc_save_p; /* true if the TOC needs to be saved */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
116 /* Target cpu type */
118 enum processor_type rs6000_cpu;
119 struct rs6000_cpu_select rs6000_select[3] =
121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
127 /* Support adjust_priority scheduler hook
128 and -mprioritize-restricted-insns= option. */
129 const char *rs6000_sched_restricted_insns_priority_str;
130 int rs6000_sched_restricted_insns_priority;
132 /* Support for -msched-costly-dep option. */
133 const char *rs6000_sched_costly_dep_str;
134 enum rs6000_dependence_cost rs6000_sched_costly_dep;
136 /* Support for -minsert-sched-nops option. */
137 const char *rs6000_sched_insert_nops_str;
138 enum rs6000_nop_insertion rs6000_sched_insert_nops;
140 /* Size of long double */
141 const char *rs6000_long_double_size_string;
142 int rs6000_long_double_type_size;
144 /* Whether -mabi=altivec has appeared */
145 int rs6000_altivec_abi;
147 /* Whether VRSAVE instructions should be generated. */
148 int rs6000_altivec_vrsave;
150 /* String from -mvrsave= option. */
151 const char *rs6000_altivec_vrsave_string;
153 /* Nonzero if we want SPE ABI extensions. */
156 /* Whether isel instructions should be generated. */
159 /* Whether SPE simd instructions should be generated. */
162 /* Nonzero if floating point operations are done in the GPRs. */
163 int rs6000_float_gprs = 0;
165 /* String from -mfloat-gprs=. */
166 const char *rs6000_float_gprs_string;
168 /* String from -misel=. */
169 const char *rs6000_isel_string;
171 /* String from -mspe=. */
172 const char *rs6000_spe_string;
174 /* Set to nonzero once AIX common-mode calls have been defined. */
175 static GTY(()) int common_mode_defined;
177 /* Save information from a "cmpxx" operation until the branch or scc is
179 rtx rs6000_compare_op0, rs6000_compare_op1;
180 int rs6000_compare_fp_p;
182 /* Label number of label created for -mrelocatable, to call to so we can
183 get the address of the GOT section */
184 int rs6000_pic_labelno;
187 /* Which abi to adhere to */
188 const char *rs6000_abi_name;
190 /* Semantics of the small data area */
191 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
193 /* Which small data model to use */
194 const char *rs6000_sdata_name = (char *)0;
196 /* Counter for labels which are to be placed in .fixup. */
197 int fixuplabelno = 0;
200 /* Bit size of immediate TLS offsets and string from which it is decoded. */
201 int rs6000_tls_size = 32;
202 const char *rs6000_tls_size_string;
204 /* ABI enumeration available for subtarget to use. */
205 enum rs6000_abi rs6000_current_abi;
207 /* ABI string from -mabi= option. */
208 const char *rs6000_abi_string;
211 const char *rs6000_debug_name;
212 int rs6000_debug_stack; /* debug stack applications */
213 int rs6000_debug_arg; /* debug argument handling */
216 static GTY(()) tree opaque_V2SI_type_node;
217 static GTY(()) tree opaque_V2SF_type_node;
218 static GTY(()) tree opaque_p_V2SI_type_node;
220 const char *rs6000_traceback_name;
222 traceback_default = 0,
228 /* Flag to say the TOC is initialized */
230 char toc_label_name[10];
232 /* Alias set for saves and restores from the rs6000 stack. */
233 static int rs6000_sr_alias_set;
235 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
236 The only place that looks at this is rs6000_set_default_type_attributes;
237 everywhere else should rely on the presence or absence of a longcall
238 attribute on the function declaration. */
239 int rs6000_default_long_calls;
240 const char *rs6000_longcall_switch;
242 /* Control alignment for fields within structures. */
243 /* String from -malign-XXXXX. */
244 const char *rs6000_alignment_string;
245 int rs6000_alignment_flags;
247 struct builtin_description
249 /* mask is not const because we're going to alter it below. This
250 nonsense will go away when we rewrite the -march infrastructure
251 to give us more target flag bits. */
253 const enum insn_code icode;
254 const char *const name;
255 const enum rs6000_builtins code;
258 static bool rs6000_function_ok_for_sibcall (tree, tree);
259 static int num_insns_constant_wide (HOST_WIDE_INT);
260 static void validate_condition_mode (enum rtx_code, enum machine_mode);
261 static rtx rs6000_generate_compare (enum rtx_code);
262 static void rs6000_maybe_dead (rtx);
263 static void rs6000_emit_stack_tie (void);
264 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
265 static rtx spe_synthesize_frame_save (rtx);
266 static bool spe_func_has_64bit_regs_p (void);
267 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
269 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
270 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
271 static unsigned rs6000_hash_constant (rtx);
272 static unsigned toc_hash_function (const void *);
273 static int toc_hash_eq (const void *, const void *);
274 static int constant_pool_expr_1 (rtx, int *, int *);
275 static bool constant_pool_expr_p (rtx);
276 static bool toc_relative_expr_p (rtx);
277 static bool legitimate_small_data_p (enum machine_mode, rtx);
278 static bool legitimate_offset_address_p (enum machine_mode, rtx, int);
279 static bool legitimate_indexed_address_p (rtx, int);
280 static bool legitimate_indirect_address_p (rtx, int);
281 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
282 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
283 static struct machine_function * rs6000_init_machine_status (void);
284 static bool rs6000_assemble_integer (rtx, unsigned int, int);
285 #ifdef HAVE_GAS_HIDDEN
286 static void rs6000_assemble_visibility (tree, int);
288 static int rs6000_ra_ever_killed (void);
289 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
290 extern const struct attribute_spec rs6000_attribute_table[];
291 static void rs6000_set_default_type_attributes (tree);
292 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
293 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
294 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
296 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
297 static bool rs6000_return_in_memory (tree, tree);
298 static void rs6000_file_start (void);
300 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
301 static void rs6000_elf_asm_out_constructor (rtx, int);
302 static void rs6000_elf_asm_out_destructor (rtx, int);
303 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
304 static void rs6000_elf_unique_section (tree, int);
305 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
306 unsigned HOST_WIDE_INT);
307 static void rs6000_elf_encode_section_info (tree, rtx, int)
309 static bool rs6000_elf_in_small_data_p (tree);
312 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
313 static void rs6000_xcoff_asm_named_section (const char *, unsigned int);
314 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
315 static void rs6000_xcoff_unique_section (tree, int);
316 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
317 unsigned HOST_WIDE_INT);
318 static const char * rs6000_xcoff_strip_name_encoding (const char *);
319 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
320 static void rs6000_xcoff_file_start (void);
321 static void rs6000_xcoff_file_end (void);
324 static bool rs6000_binds_local_p (tree);
326 static int rs6000_use_dfa_pipeline_interface (void);
327 static int rs6000_variable_issue (FILE *, int, rtx, int);
328 static bool rs6000_rtx_costs (rtx, int, int, int *);
329 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
330 static bool is_microcoded_insn (rtx);
331 static int is_dispatch_slot_restricted (rtx);
332 static bool is_cracked_insn (rtx);
333 static bool is_branch_slot_insn (rtx);
334 static int rs6000_adjust_priority (rtx, int);
335 static int rs6000_issue_rate (void);
336 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
337 static rtx get_next_active_insn (rtx, rtx);
338 static bool insn_terminates_group_p (rtx , enum group_termination);
339 static bool is_costly_group (rtx *, rtx);
340 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
341 static int redefine_groups (FILE *, int, rtx, rtx);
342 static int pad_groups (FILE *, int, rtx, rtx);
343 static void rs6000_sched_finish (FILE *, int);
344 static int rs6000_use_sched_lookahead (void);
346 static void rs6000_init_builtins (void);
347 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
348 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
349 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
350 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
351 static void altivec_init_builtins (void);
352 static void rs6000_common_init_builtins (void);
353 static void rs6000_init_libfuncs (void);
355 static void enable_mask_for_builtins (struct builtin_description *, int,
356 enum rs6000_builtins,
357 enum rs6000_builtins);
358 static void spe_init_builtins (void);
359 static rtx spe_expand_builtin (tree, rtx, bool *);
360 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
361 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
362 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
363 static rs6000_stack_t *rs6000_stack_info (void);
364 static void debug_stack_info (rs6000_stack_t *);
366 static rtx altivec_expand_builtin (tree, rtx, bool *);
367 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
368 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
369 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
370 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
371 static rtx altivec_expand_predicate_builtin (enum insn_code,
372 const char *, tree, rtx);
373 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
374 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
375 static void rs6000_parse_abi_options (void);
376 static void rs6000_parse_alignment_option (void);
377 static void rs6000_parse_tls_size_option (void);
378 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
379 static int first_altivec_reg_to_save (void);
380 static unsigned int compute_vrsave_mask (void);
381 static void is_altivec_return_reg (rtx, void *);
382 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
383 int easy_vector_constant (rtx, enum machine_mode);
384 static int easy_vector_same (rtx, enum machine_mode);
385 static bool is_ev64_opaque_type (tree);
386 static rtx rs6000_dwarf_register_span (rtx);
387 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
388 static rtx rs6000_tls_get_addr (void);
389 static rtx rs6000_got_sym (void);
390 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
391 static const char *rs6000_get_some_local_dynamic_name (void);
392 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
393 static rtx rs6000_complex_function_value (enum machine_mode);
394 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
395 enum machine_mode, tree);
396 static rtx rs6000_mixed_function_arg (CUMULATIVE_ARGS *,
397 enum machine_mode, tree, int);
398 static void rs6000_move_block_from_reg(int regno, rtx x, int nregs);
399 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
400 enum machine_mode, tree,
403 static void macho_branch_islands (void);
404 static void add_compiler_branch_island (tree, tree, int);
405 static int no_previous_def (tree function_name);
406 static tree get_prev_label (tree function_name);
409 static tree rs6000_build_builtin_va_list (void);
411 /* Hash table stuff for keeping track of TOC entries. */
413 struct toc_hash_struct GTY(())
415 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
416 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
418 enum machine_mode key_mode;
422 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
424 /* Default register names. */
425 char rs6000_reg_names[][8] =
427 "0", "1", "2", "3", "4", "5", "6", "7",
428 "8", "9", "10", "11", "12", "13", "14", "15",
429 "16", "17", "18", "19", "20", "21", "22", "23",
430 "24", "25", "26", "27", "28", "29", "30", "31",
431 "0", "1", "2", "3", "4", "5", "6", "7",
432 "8", "9", "10", "11", "12", "13", "14", "15",
433 "16", "17", "18", "19", "20", "21", "22", "23",
434 "24", "25", "26", "27", "28", "29", "30", "31",
435 "mq", "lr", "ctr","ap",
436 "0", "1", "2", "3", "4", "5", "6", "7",
438 /* AltiVec registers. */
439 "0", "1", "2", "3", "4", "5", "6", "7",
440 "8", "9", "10", "11", "12", "13", "14", "15",
441 "16", "17", "18", "19", "20", "21", "22", "23",
442 "24", "25", "26", "27", "28", "29", "30", "31",
448 #ifdef TARGET_REGNAMES
449 static const char alt_reg_names[][8] =
451 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
452 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
453 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
454 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
455 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
456 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
457 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
458 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
459 "mq", "lr", "ctr", "ap",
460 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
462 /* AltiVec registers. */
463 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
464 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
465 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
466 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
473 #ifndef MASK_STRICT_ALIGN
474 #define MASK_STRICT_ALIGN 0
476 #ifndef TARGET_PROFILE_KERNEL
477 #define TARGET_PROFILE_KERNEL 0
480 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
481 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
483 /* Return 1 for a symbol ref for a thread-local storage symbol. */
484 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
485 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
487 /* Initialize the GCC target structure. */
488 #undef TARGET_ATTRIBUTE_TABLE
489 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
490 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
491 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
493 #undef TARGET_ASM_ALIGNED_DI_OP
494 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
496 /* Default unaligned ops are only provided for ELF. Find the ops needed
497 for non-ELF systems. */
498 #ifndef OBJECT_FORMAT_ELF
500 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
502 #undef TARGET_ASM_UNALIGNED_HI_OP
503 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
504 #undef TARGET_ASM_UNALIGNED_SI_OP
505 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
506 #undef TARGET_ASM_UNALIGNED_DI_OP
507 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
510 #undef TARGET_ASM_UNALIGNED_HI_OP
511 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
512 #undef TARGET_ASM_UNALIGNED_SI_OP
513 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
517 /* This hook deals with fixups for relocatable code and DI-mode objects
519 #undef TARGET_ASM_INTEGER
520 #define TARGET_ASM_INTEGER rs6000_assemble_integer
522 #ifdef HAVE_GAS_HIDDEN
523 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
524 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
527 #undef TARGET_HAVE_TLS
528 #define TARGET_HAVE_TLS HAVE_AS_TLS
530 #undef TARGET_CANNOT_FORCE_CONST_MEM
531 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
533 #undef TARGET_ASM_FUNCTION_PROLOGUE
534 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
535 #undef TARGET_ASM_FUNCTION_EPILOGUE
536 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
538 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
539 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE rs6000_use_dfa_pipeline_interface
540 #undef TARGET_SCHED_VARIABLE_ISSUE
541 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
543 #undef TARGET_SCHED_ISSUE_RATE
544 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
545 #undef TARGET_SCHED_ADJUST_COST
546 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
547 #undef TARGET_SCHED_ADJUST_PRIORITY
548 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
549 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
550 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
551 #undef TARGET_SCHED_FINISH
552 #define TARGET_SCHED_FINISH rs6000_sched_finish
554 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
555 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
557 #undef TARGET_INIT_BUILTINS
558 #define TARGET_INIT_BUILTINS rs6000_init_builtins
560 #undef TARGET_EXPAND_BUILTIN
561 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
563 #undef TARGET_INIT_LIBFUNCS
564 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
567 #undef TARGET_BINDS_LOCAL_P
568 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
571 #undef TARGET_ASM_OUTPUT_MI_THUNK
572 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
574 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
575 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
577 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
578 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
580 #undef TARGET_RTX_COSTS
581 #define TARGET_RTX_COSTS rs6000_rtx_costs
582 #undef TARGET_ADDRESS_COST
583 #define TARGET_ADDRESS_COST hook_int_rtx_0
585 #undef TARGET_VECTOR_OPAQUE_P
586 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
588 #undef TARGET_DWARF_REGISTER_SPAN
589 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
591 /* On rs6000, function arguments are promoted, as are function return
593 #undef TARGET_PROMOTE_FUNCTION_ARGS
594 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
595 #undef TARGET_PROMOTE_FUNCTION_RETURN
596 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
598 /* Structure return values are passed as an extra parameter. */
599 #undef TARGET_STRUCT_VALUE_RTX
600 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
602 #undef TARGET_RETURN_IN_MEMORY
603 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
605 #undef TARGET_SETUP_INCOMING_VARARGS
606 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
608 /* Always strict argument naming on rs6000. */
609 #undef TARGET_STRICT_ARGUMENT_NAMING
610 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
611 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
612 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
614 #undef TARGET_BUILD_BUILTIN_VA_LIST
615 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
617 struct gcc_target targetm = TARGET_INITIALIZER;
619 /* Override command line options. Mostly we process the processor
620 type and sometimes adjust other TARGET_ options. */
623 rs6000_override_options (const char *default_cpu)
626 struct rs6000_cpu_select *ptr;
629 /* Simplifications for entries below. */
632 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
633 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
636 /* This table occasionally claims that a processor does not support
637 a particular feature even though it does, but the feature is slower
638 than the alternative. Thus, it shouldn't be relied on as a
639 complete description of the processor's support.
641 Please keep this list in order, and don't forget to update the
642 documentation in invoke.texi when adding a new processor or
646 const char *const name; /* Canonical processor name. */
647 const enum processor_type processor; /* Processor type enum value. */
648 const int target_enable; /* Target flags to enable. */
649 } const processor_target_table[]
650 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
651 {"403", PROCESSOR_PPC403,
652 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
653 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
654 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
655 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
656 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
657 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
658 {"601", PROCESSOR_PPC601,
659 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
660 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
661 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
662 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
663 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
664 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
665 {"620", PROCESSOR_PPC620, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
666 {"630", PROCESSOR_PPC630, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
667 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
668 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
669 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
670 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
671 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
672 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
673 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
674 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
675 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
676 {"970", PROCESSOR_POWER4,
677 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
678 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
679 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
680 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
681 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
682 {"G5", PROCESSOR_POWER4,
683 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
684 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
685 {"power2", PROCESSOR_POWER,
686 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
687 {"power3", PROCESSOR_PPC630, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
688 {"power4", PROCESSOR_POWER4, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
689 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
690 {"powerpc64", PROCESSOR_POWERPC64,
691 POWERPC_BASE_MASK | MASK_POWERPC64},
692 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
693 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
694 {"rios2", PROCESSOR_RIOS2,
695 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
696 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
697 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
698 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK},
701 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
703 /* Save current -mmultiple/-mno-multiple status. */
704 int multiple = TARGET_MULTIPLE;
705 /* Save current -mstring/-mno-string status. */
706 int string = TARGET_STRING;
708 /* Some OSs don't support saving the high part of 64-bit registers on
709 context switch. Other OSs don't support saving Altivec registers.
710 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
711 settings; if the user wants either, the user must explicitly specify
712 them and we won't interfere with the user's specification. */
715 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
716 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
717 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
720 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
721 #ifdef OS_MISSING_POWERPC64
722 if (OS_MISSING_POWERPC64)
723 set_masks &= ~MASK_POWERPC64;
725 #ifdef OS_MISSING_ALTIVEC
726 if (OS_MISSING_ALTIVEC)
727 set_masks &= ~MASK_ALTIVEC;
730 /* Identify the processor type. */
731 rs6000_select[0].string = default_cpu;
732 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
734 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
736 ptr = &rs6000_select[i];
737 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
739 for (j = 0; j < ptt_size; j++)
740 if (! strcmp (ptr->string, processor_target_table[j].name))
743 rs6000_cpu = processor_target_table[j].processor;
747 target_flags &= ~set_masks;
748 target_flags |= (processor_target_table[j].target_enable
755 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
762 /* If we are optimizing big endian systems for space, use the load/store
763 multiple and string instructions. */
764 if (BYTES_BIG_ENDIAN && optimize_size)
765 target_flags |= MASK_MULTIPLE | MASK_STRING;
767 /* If -mmultiple or -mno-multiple was explicitly used, don't
768 override with the processor default */
769 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
770 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
772 /* If -mstring or -mno-string was explicitly used, don't override
773 with the processor default. */
774 if ((target_flags_explicit & MASK_STRING) != 0)
775 target_flags = (target_flags & ~MASK_STRING) | string;
777 /* Don't allow -mmultiple or -mstring on little endian systems
778 unless the cpu is a 750, because the hardware doesn't support the
779 instructions used in little endian mode, and causes an alignment
780 trap. The 750 does not cause an alignment trap (except when the
781 target is unaligned). */
783 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
787 target_flags &= ~MASK_MULTIPLE;
788 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
789 warning ("-mmultiple is not supported on little endian systems");
794 target_flags &= ~MASK_STRING;
795 if ((target_flags_explicit & MASK_STRING) != 0)
796 warning ("-mstring is not supported on little endian systems");
800 /* Set debug flags */
801 if (rs6000_debug_name)
803 if (! strcmp (rs6000_debug_name, "all"))
804 rs6000_debug_stack = rs6000_debug_arg = 1;
805 else if (! strcmp (rs6000_debug_name, "stack"))
806 rs6000_debug_stack = 1;
807 else if (! strcmp (rs6000_debug_name, "arg"))
808 rs6000_debug_arg = 1;
810 error ("unknown -mdebug-%s switch", rs6000_debug_name);
813 if (rs6000_traceback_name)
815 if (! strncmp (rs6000_traceback_name, "full", 4))
816 rs6000_traceback = traceback_full;
817 else if (! strncmp (rs6000_traceback_name, "part", 4))
818 rs6000_traceback = traceback_part;
819 else if (! strncmp (rs6000_traceback_name, "no", 2))
820 rs6000_traceback = traceback_none;
822 error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'",
823 rs6000_traceback_name);
826 /* Set size of long double */
827 rs6000_long_double_type_size = 64;
828 if (rs6000_long_double_size_string)
831 int size = strtol (rs6000_long_double_size_string, &tail, 10);
832 if (*tail != '\0' || (size != 64 && size != 128))
833 error ("Unknown switch -mlong-double-%s",
834 rs6000_long_double_size_string);
836 rs6000_long_double_type_size = size;
839 /* Handle -mabi= options. */
840 rs6000_parse_abi_options ();
842 /* Handle -malign-XXXXX option. */
843 rs6000_parse_alignment_option ();
845 /* Handle generic -mFOO=YES/NO options. */
846 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
847 &rs6000_altivec_vrsave);
848 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
850 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
851 rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string,
854 /* Handle -mtls-size option. */
855 rs6000_parse_tls_size_option ();
857 #ifdef SUBTARGET_OVERRIDE_OPTIONS
858 SUBTARGET_OVERRIDE_OPTIONS;
860 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
861 SUBSUBTARGET_OVERRIDE_OPTIONS;
866 /* The e500 does not have string instructions, and we set
867 MASK_STRING above when optimizing for size. */
868 if ((target_flags & MASK_STRING) != 0)
869 target_flags = target_flags & ~MASK_STRING;
871 /* No SPE means 64-bit long doubles, even if an E500. */
872 if (rs6000_spe_string != 0
873 && !strcmp (rs6000_spe_string, "no"))
874 rs6000_long_double_type_size = 64;
876 else if (rs6000_select[1].string != NULL)
878 /* For the powerpc-eabispe configuration, we set all these by
879 default, so let's unset them if we manually set another
880 CPU that is not the E500. */
881 if (rs6000_abi_string == 0)
883 if (rs6000_spe_string == 0)
885 if (rs6000_float_gprs_string == 0)
886 rs6000_float_gprs = 0;
887 if (rs6000_isel_string == 0)
889 if (rs6000_long_double_size_string == 0)
890 rs6000_long_double_type_size = 64;
893 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
894 using TARGET_OPTIONS to handle a toggle switch, but we're out of
895 bits in target_flags so TARGET_SWITCHES cannot be used.
896 Assumption here is that rs6000_longcall_switch points into the
897 text of the complete option, rather than being a copy, so we can
898 scan back for the presence or absence of the no- modifier. */
899 if (rs6000_longcall_switch)
901 const char *base = rs6000_longcall_switch;
902 while (base[-1] != 'm') base--;
904 if (*rs6000_longcall_switch != '\0')
905 error ("invalid option `%s'", base);
906 rs6000_default_long_calls = (base[0] != 'n');
909 /* Handle -mprioritize-restricted-insns option. */
910 rs6000_sched_restricted_insns_priority = DEFAULT_RESTRICTED_INSNS_PRIORITY;
911 if (rs6000_sched_restricted_insns_priority_str)
912 rs6000_sched_restricted_insns_priority =
913 atoi (rs6000_sched_restricted_insns_priority_str);
915 /* Handle -msched-costly-dep option. */
916 rs6000_sched_costly_dep = DEFAULT_SCHED_COSTLY_DEP;
917 if (rs6000_sched_costly_dep_str)
919 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
920 rs6000_sched_costly_dep = no_dep_costly;
921 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
922 rs6000_sched_costly_dep = all_deps_costly;
923 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
924 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
925 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
926 rs6000_sched_costly_dep = store_to_load_dep_costly;
928 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
931 /* Handle -minsert-sched-nops option. */
932 rs6000_sched_insert_nops = DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME;
933 if (rs6000_sched_insert_nops_str)
935 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
936 rs6000_sched_insert_nops = sched_finish_none;
937 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
938 rs6000_sched_insert_nops = sched_finish_pad_groups;
939 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
940 rs6000_sched_insert_nops = sched_finish_regroup_exact;
942 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
945 #ifdef TARGET_REGNAMES
946 /* If the user desires alternate register names, copy in the
947 alternate names now. */
949 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
952 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
953 If -maix-struct-return or -msvr4-struct-return was explicitly
954 used, don't override with the ABI default. */
955 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
957 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
958 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
960 target_flags |= MASK_AIX_STRUCT_RET;
963 if (TARGET_LONG_DOUBLE_128
964 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
965 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
967 /* Allocate an alias set for register saves & restores from stack. */
968 rs6000_sr_alias_set = new_alias_set ();
971 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
973 /* We can only guarantee the availability of DI pseudo-ops when
974 assembling for 64-bit targets. */
977 targetm.asm_out.aligned_op.di = NULL;
978 targetm.asm_out.unaligned_op.di = NULL;
981 /* Set maximum branch target alignment at two instructions, eight bytes. */
982 align_jumps_max_skip = 8;
983 align_loops_max_skip = 8;
985 /* Arrange to save and restore machine status around nested functions. */
986 init_machine_status = rs6000_init_machine_status;
989 /* Handle generic options of the form -mfoo=yes/no.
990 NAME is the option name.
991 VALUE is the option value.
992 FLAG is the pointer to the flag where to store a 1 or 0, depending on
993 whether the option value is 'yes' or 'no' respectively. */
995 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
999 else if (!strcmp (value, "yes"))
1001 else if (!strcmp (value, "no"))
1004 error ("unknown -m%s= option specified: '%s'", name, value);
1007 /* Handle -mabi= options. */
1009 rs6000_parse_abi_options (void)
1011 if (rs6000_abi_string == 0)
1013 else if (! strcmp (rs6000_abi_string, "altivec"))
1014 rs6000_altivec_abi = 1;
1015 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1016 rs6000_altivec_abi = 0;
1017 else if (! strcmp (rs6000_abi_string, "spe"))
1020 if (!TARGET_SPE_ABI)
1021 error ("not configured for ABI: '%s'", rs6000_abi_string);
1024 else if (! strcmp (rs6000_abi_string, "no-spe"))
1027 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1030 /* Handle -malign-XXXXXX options. */
1032 rs6000_parse_alignment_option (void)
1034 if (rs6000_alignment_string == 0)
1036 else if (! strcmp (rs6000_alignment_string, "power"))
1037 rs6000_alignment_flags = MASK_ALIGN_POWER;
1038 else if (! strcmp (rs6000_alignment_string, "natural"))
1039 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1041 error ("unknown -malign-XXXXX option specified: '%s'",
1042 rs6000_alignment_string);
1045 /* Validate and record the size specified with the -mtls-size option. */
1048 rs6000_parse_tls_size_option (void)
1050 if (rs6000_tls_size_string == 0)
1052 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1053 rs6000_tls_size = 16;
1054 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1055 rs6000_tls_size = 32;
1056 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1057 rs6000_tls_size = 64;
1059 error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string);
1063 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1067 /* Do anything needed at the start of the asm file. */
1070 rs6000_file_start (void)
1074 const char *start = buffer;
1075 struct rs6000_cpu_select *ptr;
1076 const char *default_cpu = TARGET_CPU_DEFAULT;
1077 FILE *file = asm_out_file;
1079 default_file_start ();
1081 #ifdef TARGET_BI_ARCH
1082 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1086 if (flag_verbose_asm)
1088 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1089 rs6000_select[0].string = default_cpu;
1091 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1093 ptr = &rs6000_select[i];
1094 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1096 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1101 #ifdef USING_ELFOS_H
1102 switch (rs6000_sdata)
1104 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1105 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1106 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1107 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1110 if (rs6000_sdata && g_switch_value)
1112 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1123 /* Return nonzero if this function is known to have a null epilogue. */
1126 direct_return (void)
1128 if (reload_completed)
1130 rs6000_stack_t *info = rs6000_stack_info ();
1132 if (info->first_gp_reg_save == 32
1133 && info->first_fp_reg_save == 64
1134 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1135 && ! info->lr_save_p
1136 && ! info->cr_save_p
1137 && info->vrsave_mask == 0
1145 /* Returns 1 always. */
1148 any_operand (rtx op ATTRIBUTE_UNUSED,
1149 enum machine_mode mode ATTRIBUTE_UNUSED)
1154 /* Returns 1 if op is the count register. */
1156 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1158 if (GET_CODE (op) != REG)
1161 if (REGNO (op) == COUNT_REGISTER_REGNUM)
1164 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1170 /* Returns 1 if op is an altivec register. */
1172 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1175 return (register_operand (op, mode)
1176 && (GET_CODE (op) != REG
1177 || REGNO (op) > FIRST_PSEUDO_REGISTER
1178 || ALTIVEC_REGNO_P (REGNO (op))));
1182 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1184 if (GET_CODE (op) != REG)
1187 if (XER_REGNO_P (REGNO (op)))
1193 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1194 by such constants completes more quickly. */
1197 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1199 return ( GET_CODE (op) == CONST_INT
1200 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1203 /* Return 1 if OP is a constant that can fit in a D field. */
1206 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1208 return (GET_CODE (op) == CONST_INT
1209 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1212 /* Similar for an unsigned D field. */
1215 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1217 return (GET_CODE (op) == CONST_INT
1218 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1221 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1224 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1226 return (GET_CODE (op) == CONST_INT
1227 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1230 /* Returns 1 if OP is a CONST_INT that is a positive value
1231 and an exact power of 2. */
1234 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1236 return (GET_CODE (op) == CONST_INT
1238 && exact_log2 (INTVAL (op)) >= 0);
1241 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1245 gpc_reg_operand (rtx op, enum machine_mode mode)
1247 return (register_operand (op, mode)
1248 && (GET_CODE (op) != REG
1249 || (REGNO (op) >= ARG_POINTER_REGNUM
1250 && !XER_REGNO_P (REGNO (op)))
1251 || REGNO (op) < MQ_REGNO));
1254 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1258 cc_reg_operand (rtx op, enum machine_mode mode)
1260 return (register_operand (op, mode)
1261 && (GET_CODE (op) != REG
1262 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1263 || CR_REGNO_P (REGNO (op))));
1266 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1267 CR field that isn't CR0. */
1270 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1272 return (register_operand (op, mode)
1273 && (GET_CODE (op) != REG
1274 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1275 || CR_REGNO_NOT_CR0_P (REGNO (op))));
1278 /* Returns 1 if OP is either a constant integer valid for a D-field or
1279 a non-special register. If a register, it must be in the proper
1280 mode unless MODE is VOIDmode. */
1283 reg_or_short_operand (rtx op, enum machine_mode mode)
1285 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1288 /* Similar, except check if the negation of the constant would be
1289 valid for a D-field. */
1292 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1294 if (GET_CODE (op) == CONST_INT)
1295 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
1297 return gpc_reg_operand (op, mode);
1300 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1301 a non-special register. If a register, it must be in the proper
1302 mode unless MODE is VOIDmode. */
1305 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1307 if (gpc_reg_operand (op, mode))
1309 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1316 /* Return 1 if the operand is either a register or an integer whose
1317 high-order 16 bits are zero. */
1320 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1322 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1325 /* Return 1 is the operand is either a non-special register or ANY
1326 constant integer. */
1329 reg_or_cint_operand (rtx op, enum machine_mode mode)
1331 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1334 /* Return 1 is the operand is either a non-special register or ANY
1335 32-bit signed constant integer. */
1338 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
1340 return (gpc_reg_operand (op, mode)
1341 || (GET_CODE (op) == CONST_INT
1342 #if HOST_BITS_PER_WIDE_INT != 32
1343 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
1344 < (unsigned HOST_WIDE_INT) 0x100000000ll)
1349 /* Return 1 is the operand is either a non-special register or a 32-bit
1350 signed constant integer valid for 64-bit addition. */
1353 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
1355 return (gpc_reg_operand (op, mode)
1356 || (GET_CODE (op) == CONST_INT
1357 #if HOST_BITS_PER_WIDE_INT == 32
1358 && INTVAL (op) < 0x7fff8000
1360 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
1366 /* Return 1 is the operand is either a non-special register or a 32-bit
1367 signed constant integer valid for 64-bit subtraction. */
1370 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
1372 return (gpc_reg_operand (op, mode)
1373 || (GET_CODE (op) == CONST_INT
1374 #if HOST_BITS_PER_WIDE_INT == 32
1375 && (- INTVAL (op)) < 0x7fff8000
1377 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
1383 /* Return 1 is the operand is either a non-special register or ANY
1384 32-bit unsigned constant integer. */
1387 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
1389 if (GET_CODE (op) == CONST_INT)
1391 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
1393 if (GET_MODE_BITSIZE (mode) <= 32)
1396 if (INTVAL (op) < 0)
1400 return ((INTVAL (op) & GET_MODE_MASK (mode)
1401 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
1403 else if (GET_CODE (op) == CONST_DOUBLE)
1405 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1409 return CONST_DOUBLE_HIGH (op) == 0;
1412 return gpc_reg_operand (op, mode);
1415 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
1418 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1420 return (GET_CODE (op) == SYMBOL_REF
1421 || GET_CODE (op) == CONST
1422 || GET_CODE (op) == LABEL_REF);
1425 /* Return 1 if the operand is a simple references that can be loaded via
1426 the GOT (labels involving addition aren't allowed). */
1429 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1431 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
1434 /* Return the number of instructions it takes to form a constant in an
1435 integer register. */
1438 num_insns_constant_wide (HOST_WIDE_INT value)
1440 /* signed constant loadable with {cal|addi} */
1441 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1444 /* constant loadable with {cau|addis} */
1445 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1448 #if HOST_BITS_PER_WIDE_INT == 64
1449 else if (TARGET_POWERPC64)
1451 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1452 HOST_WIDE_INT high = value >> 31;
1454 if (high == 0 || high == -1)
1460 return num_insns_constant_wide (high) + 1;
1462 return (num_insns_constant_wide (high)
1463 + num_insns_constant_wide (low) + 1);
1472 num_insns_constant (rtx op, enum machine_mode mode)
1474 if (GET_CODE (op) == CONST_INT)
1476 #if HOST_BITS_PER_WIDE_INT == 64
1477 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1478 && mask64_operand (op, mode))
1482 return num_insns_constant_wide (INTVAL (op));
1485 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1490 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1491 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1492 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1495 else if (GET_CODE (op) == CONST_DOUBLE)
1501 int endian = (WORDS_BIG_ENDIAN == 0);
1503 if (mode == VOIDmode || mode == DImode)
1505 high = CONST_DOUBLE_HIGH (op);
1506 low = CONST_DOUBLE_LOW (op);
1510 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1511 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1513 low = l[1 - endian];
1517 return (num_insns_constant_wide (low)
1518 + num_insns_constant_wide (high));
1522 if (high == 0 && low >= 0)
1523 return num_insns_constant_wide (low);
1525 else if (high == -1 && low < 0)
1526 return num_insns_constant_wide (low);
1528 else if (mask64_operand (op, mode))
1532 return num_insns_constant_wide (high) + 1;
1535 return (num_insns_constant_wide (high)
1536 + num_insns_constant_wide (low) + 1);
1544 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
1545 register with one instruction per word. We only do this if we can
1546 safely read CONST_DOUBLE_{LOW,HIGH}. */
1549 easy_fp_constant (rtx op, enum machine_mode mode)
1551 if (GET_CODE (op) != CONST_DOUBLE
1552 || GET_MODE (op) != mode
1553 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
1556 /* Consider all constants with -msoft-float to be easy. */
1557 if ((TARGET_SOFT_FLOAT || !TARGET_FPRS)
1561 /* If we are using V.4 style PIC, consider all constants to be hard. */
1562 if (flag_pic && DEFAULT_ABI == ABI_V4)
1565 #ifdef TARGET_RELOCATABLE
1566 /* Similarly if we are using -mrelocatable, consider all constants
1568 if (TARGET_RELOCATABLE)
1577 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1578 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
1580 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1581 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
1582 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
1583 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
1586 else if (mode == DFmode)
1591 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1592 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
1594 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1595 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
1598 else if (mode == SFmode)
1603 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1604 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1606 return num_insns_constant_wide (l) == 1;
1609 else if (mode == DImode)
1610 return ((TARGET_POWERPC64
1611 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
1612 || (num_insns_constant (op, DImode) <= 2));
1614 else if (mode == SImode)
1620 /* Return nonzero if all elements of a vector have the same value. */
1623 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1627 units = CONST_VECTOR_NUNITS (op);
1629 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1630 for (i = 1; i < units; ++i)
1631 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1638 /* Return 1 if the operand is a CONST_INT and can be put into a
1639 register without using memory. */
1642 easy_vector_constant (rtx op, enum machine_mode mode)
1646 if (GET_CODE (op) != CONST_VECTOR
1651 if (zero_constant (op, mode)
1652 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
1653 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
1656 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
1659 if (TARGET_SPE && mode == V1DImode)
1662 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1663 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
1665 /* Limit SPE vectors to 15 bits signed. These we can generate with:
1667 evmergelo r0, r0, r0
1670 I don't know how efficient it would be to allow bigger constants,
1671 considering we'll have an extra 'ori' for every 'li'. I doubt 5
1672 instructions is better than a 64-bit memory load, but I don't
1673 have the e500 timing specs. */
1674 if (TARGET_SPE && mode == V2SImode
1675 && cst >= -0x7fff && cst <= 0x7fff
1676 && cst2 >= -0x7fff && cst2 <= 0x7fff)
1679 if (TARGET_ALTIVEC && EASY_VECTOR_15 (cst, op, mode))
1682 if (TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode))
1688 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
1691 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
1695 if (!easy_vector_constant (op, mode))
1698 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1700 return TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode);
1704 output_vec_const_move (rtx *operands)
1707 enum machine_mode mode;
1713 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
1714 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
1715 mode = GET_MODE (dest);
1719 if (zero_constant (vec, mode))
1720 return "vxor %0,%0,%0";
1721 else if (EASY_VECTOR_15 (cst, vec, mode))
1723 operands[1] = GEN_INT (cst);
1727 return "vspltisw %0,%1";
1729 return "vspltish %0,%1";
1731 return "vspltisb %0,%1";
1736 else if (EASY_VECTOR_15_ADD_SELF (cst, vec, mode))
1744 /* Vector constant 0 is handled as a splitter of V2SI, and in the
1745 pattern of V1DI, V4HI, and V2SF.
1747 FIXME: We should probably return # and add post reload
1748 splitters for these, but this way is so easy ;-).
1750 operands[1] = GEN_INT (cst);
1751 operands[2] = GEN_INT (cst2);
1753 return "li %0,%1\n\tevmergelo %0,%0,%0";
1755 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
1761 /* Return 1 if the operand is the constant 0. This works for scalars
1762 as well as vectors. */
1764 zero_constant (rtx op, enum machine_mode mode)
1766 return op == CONST0_RTX (mode);
1769 /* Return 1 if the operand is 0.0. */
1771 zero_fp_constant (rtx op, enum machine_mode mode)
1773 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
1776 /* Return 1 if the operand is in volatile memory. Note that during
1777 the RTL generation phase, memory_operand does not return TRUE for
1778 volatile memory references. So this function allows us to
1779 recognize volatile references where its safe. */
1782 volatile_mem_operand (rtx op, enum machine_mode mode)
1784 if (GET_CODE (op) != MEM)
1787 if (!MEM_VOLATILE_P (op))
1790 if (mode != GET_MODE (op))
1793 if (reload_completed)
1794 return memory_operand (op, mode);
1796 if (reload_in_progress)
1797 return strict_memory_address_p (mode, XEXP (op, 0));
1799 return memory_address_p (mode, XEXP (op, 0));
1802 /* Return 1 if the operand is an offsettable memory operand. */
1805 offsettable_mem_operand (rtx op, enum machine_mode mode)
1807 return ((GET_CODE (op) == MEM)
1808 && offsettable_address_p (reload_completed || reload_in_progress,
1809 mode, XEXP (op, 0)));
1812 /* Return 1 if the operand is either an easy FP constant (see above) or
1816 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
1818 return memory_operand (op, mode) || easy_fp_constant (op, mode);
1821 /* Return 1 if the operand is either a non-special register or an item
1822 that can be used as the operand of a `mode' add insn. */
1825 add_operand (rtx op, enum machine_mode mode)
1827 if (GET_CODE (op) == CONST_INT)
1828 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1829 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1831 return gpc_reg_operand (op, mode);
1834 /* Return 1 if OP is a constant but not a valid add_operand. */
1837 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1839 return (GET_CODE (op) == CONST_INT
1840 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1841 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1844 /* Return 1 if the operand is a non-special register or a constant that
1845 can be used as the operand of an OR or XOR insn on the RS/6000. */
1848 logical_operand (rtx op, enum machine_mode mode)
1850 HOST_WIDE_INT opl, oph;
1852 if (gpc_reg_operand (op, mode))
1855 if (GET_CODE (op) == CONST_INT)
1857 opl = INTVAL (op) & GET_MODE_MASK (mode);
1859 #if HOST_BITS_PER_WIDE_INT <= 32
1860 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
1864 else if (GET_CODE (op) == CONST_DOUBLE)
1866 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1869 opl = CONST_DOUBLE_LOW (op);
1870 oph = CONST_DOUBLE_HIGH (op);
1877 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
1878 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
1881 /* Return 1 if C is a constant that is not a logical operand (as
1882 above), but could be split into one. */
1885 non_logical_cint_operand (rtx op, enum machine_mode mode)
1887 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
1888 && ! logical_operand (op, mode)
1889 && reg_or_logical_cint_operand (op, mode));
1892 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
1893 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
1894 Reject all ones and all zeros, since these should have been optimized
1895 away and confuse the making of MB and ME. */
1898 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1900 HOST_WIDE_INT c, lsb;
1902 if (GET_CODE (op) != CONST_INT)
1907 /* Fail in 64-bit mode if the mask wraps around because the upper
1908 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
1909 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
1912 /* We don't change the number of transitions by inverting,
1913 so make sure we start with the LS bit zero. */
1917 /* Reject all zeros or all ones. */
1921 /* Find the first transition. */
1924 /* Invert to look for a second transition. */
1927 /* Erase first transition. */
1930 /* Find the second transition (if any). */
1933 /* Match if all the bits above are 1's (or c is zero). */
1937 /* Return 1 for the PowerPC64 rlwinm corner case. */
1940 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1942 HOST_WIDE_INT c, lsb;
1944 if (GET_CODE (op) != CONST_INT)
1949 if ((c & 0x80000001) != 0x80000001)
1963 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
1964 It is if there are no more than one 1->0 or 0->1 transitions.
1965 Reject all zeros, since zero should have been optimized away and
1966 confuses the making of MB and ME. */
1969 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1971 if (GET_CODE (op) == CONST_INT)
1973 HOST_WIDE_INT c, lsb;
1977 /* Reject all zeros. */
1981 /* We don't change the number of transitions by inverting,
1982 so make sure we start with the LS bit zero. */
1986 /* Find the transition, and check that all bits above are 1's. */
1989 /* Match if all the bits above are 1's (or c is zero). */
1995 /* Like mask64_operand, but allow up to three transitions. This
1996 predicate is used by insn patterns that generate two rldicl or
1997 rldicr machine insns. */
2000 mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2002 if (GET_CODE (op) == CONST_INT)
2004 HOST_WIDE_INT c, lsb;
2008 /* Disallow all zeros. */
2012 /* We don't change the number of transitions by inverting,
2013 so make sure we start with the LS bit zero. */
2017 /* Find the first transition. */
2020 /* Invert to look for a second transition. */
2023 /* Erase first transition. */
2026 /* Find the second transition. */
2029 /* Invert to look for a third transition. */
2032 /* Erase second transition. */
2035 /* Find the third transition (if any). */
2038 /* Match if all the bits above are 1's (or c is zero). */
2044 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2045 implement ANDing by the mask IN. */
2047 build_mask64_2_operands (rtx in, rtx *out)
2049 #if HOST_BITS_PER_WIDE_INT >= 64
2050 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2053 if (GET_CODE (in) != CONST_INT)
2059 /* Assume c initially something like 0x00fff000000fffff. The idea
2060 is to rotate the word so that the middle ^^^^^^ group of zeros
2061 is at the MS end and can be cleared with an rldicl mask. We then
2062 rotate back and clear off the MS ^^ group of zeros with a
2064 c = ~c; /* c == 0xff000ffffff00000 */
2065 lsb = c & -c; /* lsb == 0x0000000000100000 */
2066 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2067 c = ~c; /* c == 0x00fff000000fffff */
2068 c &= -lsb; /* c == 0x00fff00000000000 */
2069 lsb = c & -c; /* lsb == 0x0000100000000000 */
2070 c = ~c; /* c == 0xff000fffffffffff */
2071 c &= -lsb; /* c == 0xff00000000000000 */
2073 while ((lsb >>= 1) != 0)
2074 shift++; /* shift == 44 on exit from loop */
2075 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2076 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2077 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2081 /* Assume c initially something like 0xff000f0000000000. The idea
2082 is to rotate the word so that the ^^^ middle group of zeros
2083 is at the LS end and can be cleared with an rldicr mask. We then
2084 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2086 lsb = c & -c; /* lsb == 0x0000010000000000 */
2087 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2088 c = ~c; /* c == 0x00fff0ffffffffff */
2089 c &= -lsb; /* c == 0x00fff00000000000 */
2090 lsb = c & -c; /* lsb == 0x0000100000000000 */
2091 c = ~c; /* c == 0xff000fffffffffff */
2092 c &= -lsb; /* c == 0xff00000000000000 */
2094 while ((lsb >>= 1) != 0)
2095 shift++; /* shift == 44 on exit from loop */
2096 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2097 m1 >>= shift; /* m1 == 0x0000000000000fff */
2098 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2101 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2102 masks will be all 1's. We are guaranteed more than one transition. */
2103 out[0] = GEN_INT (64 - shift);
2104 out[1] = GEN_INT (m1);
2105 out[2] = GEN_INT (shift);
2106 out[3] = GEN_INT (m2);
2114 /* Return 1 if the operand is either a non-special register or a constant
2115 that can be used as the operand of a PowerPC64 logical AND insn. */
2118 and64_operand (rtx op, enum machine_mode mode)
2120 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2121 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2123 return (logical_operand (op, mode) || mask64_operand (op, mode));
2126 /* Like the above, but also match constants that can be implemented
2127 with two rldicl or rldicr insns. */
2130 and64_2_operand (rtx op, enum machine_mode mode)
2132 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2133 return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
2135 return logical_operand (op, mode) || mask64_2_operand (op, mode);
2138 /* Return 1 if the operand is either a non-special register or a
2139 constant that can be used as the operand of an RS/6000 logical AND insn. */
2142 and_operand (rtx op, enum machine_mode mode)
2144 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2145 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2147 return (logical_operand (op, mode) || mask_operand (op, mode));
2150 /* Return 1 if the operand is a general register or memory operand. */
2153 reg_or_mem_operand (rtx op, enum machine_mode mode)
2155 return (gpc_reg_operand (op, mode)
2156 || memory_operand (op, mode)
2157 || macho_lo_sum_memory_operand (op, mode)
2158 || volatile_mem_operand (op, mode));
2161 /* Return 1 if the operand is a general register or memory operand without
2162 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2166 lwa_operand (rtx op, enum machine_mode mode)
2170 if (reload_completed && GET_CODE (inner) == SUBREG)
2171 inner = SUBREG_REG (inner);
2173 return gpc_reg_operand (inner, mode)
2174 || (memory_operand (inner, mode)
2175 && GET_CODE (XEXP (inner, 0)) != PRE_INC
2176 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2177 && (GET_CODE (XEXP (inner, 0)) != PLUS
2178 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2179 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2182 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2185 symbol_ref_operand (rtx op, enum machine_mode mode)
2187 if (mode != VOIDmode && GET_MODE (op) != mode)
2190 return (GET_CODE (op) == SYMBOL_REF
2191 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2194 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2195 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2198 call_operand (rtx op, enum machine_mode mode)
2200 if (mode != VOIDmode && GET_MODE (op) != mode)
2203 return (GET_CODE (op) == SYMBOL_REF
2204 || (GET_CODE (op) == REG
2205 && (REGNO (op) == LINK_REGISTER_REGNUM
2206 || REGNO (op) == COUNT_REGISTER_REGNUM
2207 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2210 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2214 current_file_function_operand (rtx op,
2215 enum machine_mode mode ATTRIBUTE_UNUSED)
2217 return (GET_CODE (op) == SYMBOL_REF
2218 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2219 && (SYMBOL_REF_LOCAL_P (op)
2220 || (op == XEXP (DECL_RTL (current_function_decl), 0))));
2223 /* Return 1 if this operand is a valid input for a move insn. */
2226 input_operand (rtx op, enum machine_mode mode)
2228 /* Memory is always valid. */
2229 if (memory_operand (op, mode))
2232 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
2233 if (GET_CODE (op) == CONSTANT_P_RTX)
2236 /* For floating-point, easy constants are valid. */
2237 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2239 && easy_fp_constant (op, mode))
2242 /* Allow any integer constant. */
2243 if (GET_MODE_CLASS (mode) == MODE_INT
2244 && (GET_CODE (op) == CONST_INT
2245 || GET_CODE (op) == CONST_DOUBLE))
2248 /* Allow easy vector constants. */
2249 if (GET_CODE (op) == CONST_VECTOR
2250 && easy_vector_constant (op, mode))
2253 /* For floating-point or multi-word mode, the only remaining valid type
2255 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2256 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
2257 return register_operand (op, mode);
2259 /* The only cases left are integral modes one word or smaller (we
2260 do not get called for MODE_CC values). These can be in any
2262 if (register_operand (op, mode))
2265 /* A SYMBOL_REF referring to the TOC is valid. */
2266 if (legitimate_constant_pool_address_p (op))
2269 /* A constant pool expression (relative to the TOC) is valid */
2270 if (toc_relative_expr_p (op))
2273 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
2275 if (DEFAULT_ABI == ABI_V4
2276 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
2277 && small_data_operand (op, Pmode))
2283 /* Return 1 for an operand in small memory on V.4/eabi. */
2286 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2287 enum machine_mode mode ATTRIBUTE_UNUSED)
2292 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2295 if (DEFAULT_ABI != ABI_V4)
2298 if (GET_CODE (op) == SYMBOL_REF)
2301 else if (GET_CODE (op) != CONST
2302 || GET_CODE (XEXP (op, 0)) != PLUS
2303 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2304 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2309 rtx sum = XEXP (op, 0);
2310 HOST_WIDE_INT summand;
2312 /* We have to be careful here, because it is the referenced address
2313 that must be 32k from _SDA_BASE_, not just the symbol. */
2314 summand = INTVAL (XEXP (sum, 1));
2315 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2318 sym_ref = XEXP (sum, 0);
2321 return SYMBOL_REF_SMALL_P (sym_ref);
2327 /* Return true if either operand is a general purpose register. */
2330 gpr_or_gpr_p (rtx op0, rtx op1)
2332 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2333 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2337 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2340 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2342 switch (GET_CODE(op))
2345 if (RS6000_SYMBOL_REF_TLS_P (op))
2347 else if (CONSTANT_POOL_ADDRESS_P (op))
2349 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2357 else if (! strcmp (XSTR (op, 0), toc_label_name))
2366 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2367 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2369 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2378 constant_pool_expr_p (rtx op)
2382 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2386 toc_relative_expr_p (rtx op)
2390 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2393 /* SPE offset addressing is limited to 5-bits worth of double words. */
2394 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2397 legitimate_constant_pool_address_p (rtx x)
2400 && GET_CODE (x) == PLUS
2401 && GET_CODE (XEXP (x, 0)) == REG
2402 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2403 && constant_pool_expr_p (XEXP (x, 1)));
2407 legitimate_small_data_p (enum machine_mode mode, rtx x)
2409 return (DEFAULT_ABI == ABI_V4
2410 && !flag_pic && !TARGET_TOC
2411 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2412 && small_data_operand (x, mode));
2416 legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2418 unsigned HOST_WIDE_INT offset, extra;
2420 if (GET_CODE (x) != PLUS)
2422 if (GET_CODE (XEXP (x, 0)) != REG)
2424 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2426 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2429 offset = INTVAL (XEXP (x, 1));
2437 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2438 which leaves the only valid constant offset of zero, which by
2439 canonicalization rules is also invalid. */
2446 /* SPE vector modes. */
2447 return SPE_CONST_OFFSET_OK (offset);
2451 if (!TARGET_POWERPC64)
2453 else if (offset & 3)
2459 if (!TARGET_POWERPC64)
2461 else if (offset & 3)
2471 return (offset + extra >= offset) && (offset + extra + 0x8000 < 0x10000);
2475 legitimate_indexed_address_p (rtx x, int strict)
2479 if (GET_CODE (x) != PLUS)
2484 if (!REG_P (op0) || !REG_P (op1))
2487 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2488 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2489 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2490 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2494 legitimate_indirect_address_p (rtx x, int strict)
2496 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2500 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2502 if (!TARGET_MACHO || !flag_pic
2503 || mode != SImode || GET_CODE(x) != MEM)
2507 if (GET_CODE (x) != LO_SUM)
2509 if (GET_CODE (XEXP (x, 0)) != REG)
2511 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2515 return CONSTANT_P (x);
2519 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2521 if (GET_CODE (x) != LO_SUM)
2523 if (GET_CODE (XEXP (x, 0)) != REG)
2525 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2529 if (TARGET_ELF || TARGET_MACHO)
2531 if (DEFAULT_ABI != ABI_AIX && flag_pic)
2535 if (GET_MODE_NUNITS (mode) != 1)
2537 if (GET_MODE_BITSIZE (mode) > 32
2538 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode))
2541 return CONSTANT_P (x);
2548 /* Try machine-dependent ways of modifying an illegitimate address
2549 to be legitimate. If we find one, return the new, valid address.
2550 This is used from only one place: `memory_address' in explow.c.
2552 OLDX is the address as it was before break_out_memory_refs was
2553 called. In some cases it is useful to look at this to decide what
2556 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2558 It is always safe for this function to do nothing. It exists to
2559 recognize opportunities to optimize the output.
2561 On RS/6000, first check for the sum of a register with a constant
2562 integer that is out of range. If so, generate code to add the
2563 constant with the low-order 16 bits masked to the register and force
2564 this result into another register (this can be done with `cau').
2565 Then generate an address of REG+(CONST&0xffff), allowing for the
2566 possibility of bit 16 being a one.
2568 Then check for the sum of a register and something not constant, try to
2569 load the other things into a register and return the sum. */
2572 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2573 enum machine_mode mode)
2575 if (GET_CODE (x) == SYMBOL_REF)
2577 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2579 return rs6000_legitimize_tls_address (x, model);
2582 if (GET_CODE (x) == PLUS
2583 && GET_CODE (XEXP (x, 0)) == REG
2584 && GET_CODE (XEXP (x, 1)) == CONST_INT
2585 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2587 HOST_WIDE_INT high_int, low_int;
2589 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2590 high_int = INTVAL (XEXP (x, 1)) - low_int;
2591 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2592 GEN_INT (high_int)), 0);
2593 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2595 else if (GET_CODE (x) == PLUS
2596 && GET_CODE (XEXP (x, 0)) == REG
2597 && GET_CODE (XEXP (x, 1)) != CONST_INT
2598 && GET_MODE_NUNITS (mode) == 1
2599 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2601 || (mode != DFmode && mode != TFmode))
2602 && (TARGET_POWERPC64 || mode != DImode)
2605 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2606 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2608 else if (ALTIVEC_VECTOR_MODE (mode))
2612 /* Make sure both operands are registers. */
2613 if (GET_CODE (x) == PLUS)
2614 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2615 force_reg (Pmode, XEXP (x, 1)));
2617 reg = force_reg (Pmode, x);
2620 else if (SPE_VECTOR_MODE (mode))
2622 /* We accept [reg + reg] and [reg + OFFSET]. */
2624 if (GET_CODE (x) == PLUS)
2626 rtx op1 = XEXP (x, 0);
2627 rtx op2 = XEXP (x, 1);
2629 op1 = force_reg (Pmode, op1);
2631 if (GET_CODE (op2) != REG
2632 && (GET_CODE (op2) != CONST_INT
2633 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2634 op2 = force_reg (Pmode, op2);
2636 return gen_rtx_PLUS (Pmode, op1, op2);
2639 return force_reg (Pmode, x);
2645 && GET_CODE (x) != CONST_INT
2646 && GET_CODE (x) != CONST_DOUBLE
2648 && GET_MODE_NUNITS (mode) == 1
2649 && (GET_MODE_BITSIZE (mode) <= 32
2650 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2652 rtx reg = gen_reg_rtx (Pmode);
2653 emit_insn (gen_elf_high (reg, x));
2654 return gen_rtx_LO_SUM (Pmode, reg, x);
2656 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2659 && ! MACHO_DYNAMIC_NO_PIC_P
2661 && GET_CODE (x) != CONST_INT
2662 && GET_CODE (x) != CONST_DOUBLE
2664 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2668 rtx reg = gen_reg_rtx (Pmode);
2669 emit_insn (gen_macho_high (reg, x));
2670 return gen_rtx_LO_SUM (Pmode, reg, x);
2673 && constant_pool_expr_p (x)
2674 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2676 return create_TOC_reference (x);
2682 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2684 static GTY(()) rtx rs6000_tls_symbol;
2686 rs6000_tls_get_addr (void)
2688 if (!rs6000_tls_symbol)
2689 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2691 return rs6000_tls_symbol;
2694 /* Construct the SYMBOL_REF for TLS GOT references. */
2696 static GTY(()) rtx rs6000_got_symbol;
2698 rs6000_got_sym (void)
2700 if (!rs6000_got_symbol)
2702 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2703 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2704 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2707 return rs6000_got_symbol;
2710 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2711 this (thread-local) address. */
2714 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2718 dest = gen_reg_rtx (Pmode);
2719 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2725 tlsreg = gen_rtx_REG (Pmode, 13);
2726 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2730 tlsreg = gen_rtx_REG (Pmode, 2);
2731 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2735 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2739 tmp = gen_reg_rtx (Pmode);
2742 tlsreg = gen_rtx_REG (Pmode, 13);
2743 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2747 tlsreg = gen_rtx_REG (Pmode, 2);
2748 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2752 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2754 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2759 rtx r3, got, tga, tmp1, tmp2, eqv;
2762 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2766 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2769 rtx gsym = rs6000_got_sym ();
2770 got = gen_reg_rtx (Pmode);
2772 rs6000_emit_move (got, gsym, Pmode);
2776 static int tls_got_labelno = 0;
2777 rtx tempLR, lab, tmp3, mem;
2780 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
2781 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
2782 tempLR = gen_reg_rtx (Pmode);
2783 tmp1 = gen_reg_rtx (Pmode);
2784 tmp2 = gen_reg_rtx (Pmode);
2785 tmp3 = gen_reg_rtx (Pmode);
2786 mem = gen_rtx_MEM (Pmode, tmp1);
2787 RTX_UNCHANGING_P (mem) = 1;
2789 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
2791 emit_move_insn (tmp1, tempLR);
2792 emit_move_insn (tmp2, mem);
2793 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2794 last = emit_move_insn (got, tmp3);
2795 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2797 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2799 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2805 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2807 r3 = gen_rtx_REG (Pmode, 3);
2809 insn = gen_tls_gd_64 (r3, got, addr);
2811 insn = gen_tls_gd_32 (r3, got, addr);
2814 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2815 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2816 insn = emit_call_insn (insn);
2817 CONST_OR_PURE_CALL_P (insn) = 1;
2818 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2819 insn = get_insns ();
2821 emit_libcall_block (insn, dest, r3, addr);
2823 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2825 r3 = gen_rtx_REG (Pmode, 3);
2827 insn = gen_tls_ld_64 (r3, got);
2829 insn = gen_tls_ld_32 (r3, got);
2832 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2833 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2834 insn = emit_call_insn (insn);
2835 CONST_OR_PURE_CALL_P (insn) = 1;
2836 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2837 insn = get_insns ();
2839 tmp1 = gen_reg_rtx (Pmode);
2840 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2842 emit_libcall_block (insn, tmp1, r3, eqv);
2843 if (rs6000_tls_size == 16)
2846 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2848 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2850 else if (rs6000_tls_size == 32)
2852 tmp2 = gen_reg_rtx (Pmode);
2854 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2856 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2859 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2861 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2865 tmp2 = gen_reg_rtx (Pmode);
2867 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2869 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2871 insn = gen_rtx_SET (Pmode, dest,
2872 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2878 /* IE, or 64 bit offset LE. */
2879 tmp2 = gen_reg_rtx (Pmode);
2881 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2883 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2886 insn = gen_tls_tls_64 (dest, tmp2, addr);
2888 insn = gen_tls_tls_32 (dest, tmp2, addr);
2896 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
2897 instruction definitions. */
2900 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2902 return RS6000_SYMBOL_REF_TLS_P (x);
2905 /* Return 1 if X contains a thread-local symbol. */
2908 rs6000_tls_referenced_p (rtx x)
2910 if (! TARGET_HAVE_TLS)
2913 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2916 /* Return 1 if *X is a thread-local symbol. This is the same as
2917 rs6000_tls_symbol_ref except for the type of the unused argument. */
2920 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2922 return RS6000_SYMBOL_REF_TLS_P (*x);
2925 /* The convention appears to be to define this wherever it is used.
2926 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2927 is now used here. */
2928 #ifndef REG_MODE_OK_FOR_BASE_P
2929 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2932 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2933 replace the input X, or the original X if no replacement is called for.
2934 The output parameter *WIN is 1 if the calling macro should goto WIN,
2937 For RS/6000, we wish to handle large displacements off a base
2938 register by splitting the addend across an addiu/addis and the mem insn.
2939 This cuts number of extra insns needed from 3 to 1.
2941 On Darwin, we use this to generate code for floating point constants.
2942 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2943 The Darwin code is inside #if TARGET_MACHO because only then is
2944 machopic_function_base_name() defined. */
2946 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
2947 int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win)
2949 /* We must recognize output that we have already generated ourselves. */
2950 if (GET_CODE (x) == PLUS
2951 && GET_CODE (XEXP (x, 0)) == PLUS
2952 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2953 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2954 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2956 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2957 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2958 opnum, (enum reload_type)type);
2964 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
2965 && GET_CODE (x) == LO_SUM
2966 && GET_CODE (XEXP (x, 0)) == PLUS
2967 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
2968 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
2969 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
2970 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
2971 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
2972 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
2973 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
2975 /* Result of previous invocation of this function on Darwin
2976 floating point constant. */
2977 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2978 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
2979 opnum, (enum reload_type)type);
2984 if (GET_CODE (x) == PLUS
2985 && GET_CODE (XEXP (x, 0)) == REG
2986 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2987 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
2988 && GET_CODE (XEXP (x, 1)) == CONST_INT
2989 && !SPE_VECTOR_MODE (mode)
2990 && !ALTIVEC_VECTOR_MODE (mode))
2992 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2993 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2995 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2997 /* Check for 32-bit overflow. */
2998 if (high + low != val)
3004 /* Reload the high part into a base reg; leave the low part
3005 in the mem directly. */
3007 x = gen_rtx_PLUS (GET_MODE (x),
3008 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3012 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3013 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3014 opnum, (enum reload_type)type);
3019 if (GET_CODE (x) == SYMBOL_REF
3020 && DEFAULT_ABI == ABI_DARWIN
3021 && !ALTIVEC_VECTOR_MODE (mode)
3024 /* Darwin load of floating point constant. */
3025 rtx offset = gen_rtx (CONST, Pmode,
3026 gen_rtx (MINUS, Pmode, x,
3027 gen_rtx (SYMBOL_REF, Pmode,
3028 machopic_function_base_name ())));
3029 x = gen_rtx (LO_SUM, GET_MODE (x),
3030 gen_rtx (PLUS, Pmode, pic_offset_table_rtx,
3031 gen_rtx (HIGH, Pmode, offset)), offset);
3032 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3033 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3034 opnum, (enum reload_type)type);
3038 if (GET_CODE (x) == SYMBOL_REF
3039 && DEFAULT_ABI == ABI_DARWIN
3040 && !ALTIVEC_VECTOR_MODE (mode)
3041 && MACHO_DYNAMIC_NO_PIC_P)
3043 /* Darwin load of floating point constant. */
3044 x = gen_rtx (LO_SUM, GET_MODE (x),
3045 gen_rtx (HIGH, Pmode, x), x);
3046 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3047 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3048 opnum, (enum reload_type)type);
3054 && constant_pool_expr_p (x)
3055 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3057 (x) = create_TOC_reference (x);
3065 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3066 that is a valid memory address for an instruction.
3067 The MODE argument is the machine mode for the MEM expression
3068 that wants to use this address.
3070 On the RS/6000, there are four valid address: a SYMBOL_REF that
3071 refers to a constant pool entry of an address (or the sum of it
3072 plus a constant), a short (16-bit signed) constant plus a register,
3073 the sum of two registers, or a register indirect, possibly with an
3074 auto-increment. For DFmode and DImode with a constant plus register,
3075 we must ensure that both words are addressable or PowerPC64 with offset
3078 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3079 32-bit DImode, TImode), indexed addressing cannot be used because
3080 adjacent memory cells are accessed by adding word-sized offsets
3081 during assembly output. */
3083 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3085 if (RS6000_SYMBOL_REF_TLS_P (x))
3087 if (legitimate_indirect_address_p (x, reg_ok_strict))
3089 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3090 && !ALTIVEC_VECTOR_MODE (mode)
3091 && !SPE_VECTOR_MODE (mode)
3093 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3095 if (legitimate_small_data_p (mode, x))
3097 if (legitimate_constant_pool_address_p (x))
3099 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3101 && GET_CODE (x) == PLUS
3102 && GET_CODE (XEXP (x, 0)) == REG
3103 && XEXP (x, 0) == virtual_stack_vars_rtx
3104 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3106 if (legitimate_offset_address_p (mode, x, reg_ok_strict))
3109 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3111 || (mode != DFmode && mode != TFmode))
3112 && (TARGET_POWERPC64 || mode != DImode)
3113 && legitimate_indexed_address_p (x, reg_ok_strict))
3115 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3120 /* Go to LABEL if ADDR (a legitimate address expression)
3121 has an effect that depends on the machine mode it is used for.
3123 On the RS/6000 this is true of all integral offsets (since AltiVec
3124 modes don't allow them) or is a pre-increment or decrement.
3126 ??? Except that due to conceptual problems in offsettable_address_p
3127 we can't really report the problems of integral offsets. So leave
3128 this assuming that the adjustable offset must be valid for the
3129 sub-words of a TFmode operand, which is what we had before. */
3132 rs6000_mode_dependent_address (rtx addr)
3134 switch (GET_CODE (addr))
3137 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3139 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3140 return val + 12 + 0x8000 >= 0x10000;
3149 return TARGET_UPDATE;
3158 /* Try to output insns to set TARGET equal to the constant C if it can
3159 be done in less than N insns. Do all computations in MODE.
3160 Returns the place where the output has been placed if it can be
3161 done and the insns have been emitted. If it would take more than N
3162 insns, zero is returned and no insns and emitted. */
3165 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3166 rtx source, int n ATTRIBUTE_UNUSED)
3168 rtx result, insn, set;
3169 HOST_WIDE_INT c0, c1;
3171 if (mode == QImode || mode == HImode)
3174 dest = gen_reg_rtx (mode);
3175 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3178 else if (mode == SImode)
3180 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3182 emit_insn (gen_rtx_SET (VOIDmode, result,
3183 GEN_INT (INTVAL (source)
3184 & (~ (HOST_WIDE_INT) 0xffff))));
3185 emit_insn (gen_rtx_SET (VOIDmode, dest,
3186 gen_rtx_IOR (SImode, result,
3187 GEN_INT (INTVAL (source) & 0xffff))));
3190 else if (mode == DImode)
3192 if (GET_CODE (source) == CONST_INT)
3194 c0 = INTVAL (source);
3197 else if (GET_CODE (source) == CONST_DOUBLE)
3199 #if HOST_BITS_PER_WIDE_INT >= 64
3200 c0 = CONST_DOUBLE_LOW (source);
3203 c0 = CONST_DOUBLE_LOW (source);
3204 c1 = CONST_DOUBLE_HIGH (source);
3210 result = rs6000_emit_set_long_const (dest, c0, c1);
3215 insn = get_last_insn ();
3216 set = single_set (insn);
3217 if (! CONSTANT_P (SET_SRC (set)))
3218 set_unique_reg_note (insn, REG_EQUAL, source);
3223 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3224 fall back to a straight forward decomposition. We do this to avoid
3225 exponential run times encountered when looking for longer sequences
3226 with rs6000_emit_set_const. */
3228 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3230 if (!TARGET_POWERPC64)
3232 rtx operand1, operand2;
3234 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3236 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3238 emit_move_insn (operand1, GEN_INT (c1));
3239 emit_move_insn (operand2, GEN_INT (c2));
3243 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3246 ud2 = (c1 & 0xffff0000) >> 16;
3247 #if HOST_BITS_PER_WIDE_INT >= 64
3251 ud4 = (c2 & 0xffff0000) >> 16;
3253 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3254 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3257 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3259 emit_move_insn (dest, GEN_INT (ud1));
3262 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3263 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3266 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3269 emit_move_insn (dest, GEN_INT (ud2 << 16));
3271 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3273 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3274 || (ud4 == 0 && ! (ud3 & 0x8000)))
3277 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3280 emit_move_insn (dest, GEN_INT (ud3 << 16));
3283 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3284 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3286 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3291 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3294 emit_move_insn (dest, GEN_INT (ud4 << 16));
3297 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3299 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3301 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3302 GEN_INT (ud2 << 16)));
3304 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3310 /* Emit a move from SOURCE to DEST in mode MODE. */
3312 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3316 operands[1] = source;
3318 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3319 if (GET_CODE (operands[1]) == CONST_DOUBLE
3320 && ! FLOAT_MODE_P (mode)
3321 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3323 /* FIXME. This should never happen. */
3324 /* Since it seems that it does, do the safe thing and convert
3326 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3328 if (GET_CODE (operands[1]) == CONST_DOUBLE
3329 && ! FLOAT_MODE_P (mode)
3330 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3331 && CONST_DOUBLE_LOW (operands[1]) >= 0)
3332 || (CONST_DOUBLE_HIGH (operands[1]) == -1
3333 && CONST_DOUBLE_LOW (operands[1]) < 0)))
3336 /* Check if GCC is setting up a block move that will end up using FP
3337 registers as temporaries. We must make sure this is acceptable. */
3338 if (GET_CODE (operands[0]) == MEM
3339 && GET_CODE (operands[1]) == MEM
3341 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3342 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3343 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3344 ? 32 : MEM_ALIGN (operands[0])))
3345 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3347 : MEM_ALIGN (operands[1]))))
3348 && ! MEM_VOLATILE_P (operands [0])
3349 && ! MEM_VOLATILE_P (operands [1]))
3351 emit_move_insn (adjust_address (operands[0], SImode, 0),
3352 adjust_address (operands[1], SImode, 0));
3353 emit_move_insn (adjust_address (operands[0], SImode, 4),
3354 adjust_address (operands[1], SImode, 4));
3358 if (!no_new_pseudos)
3360 if (GET_CODE (operands[1]) == MEM && optimize > 0
3361 && (mode == QImode || mode == HImode || mode == SImode)
3362 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode))
3364 rtx reg = gen_reg_rtx (word_mode);
3366 emit_insn (gen_rtx_SET (word_mode, reg,
3367 gen_rtx_ZERO_EXTEND (word_mode,
3369 operands[1] = gen_lowpart (mode, reg);
3371 if (GET_CODE (operands[0]) != REG)
3372 operands[1] = force_reg (mode, operands[1]);
3375 if (mode == SFmode && ! TARGET_POWERPC
3376 && TARGET_HARD_FLOAT && TARGET_FPRS
3377 && GET_CODE (operands[0]) == MEM)
3381 if (reload_in_progress || reload_completed)
3382 regnum = true_regnum (operands[1]);
3383 else if (GET_CODE (operands[1]) == REG)
3384 regnum = REGNO (operands[1]);
3388 /* If operands[1] is a register, on POWER it may have
3389 double-precision data in it, so truncate it to single
3391 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3394 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3395 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3396 operands[1] = newreg;
3400 /* Recognize the case where operand[1] is a reference to thread-local
3401 data and load its address to a register. */
3402 if (GET_CODE (operands[1]) == SYMBOL_REF)
3404 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3406 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3409 /* Handle the case where reload calls us with an invalid address. */
3410 if (reload_in_progress && mode == Pmode
3411 && (! general_operand (operands[1], mode)
3412 || ! nonimmediate_operand (operands[0], mode)))
3415 /* Handle the case of CONSTANT_P_RTX. */
3416 if (GET_CODE (operands[1]) == CONSTANT_P_RTX)
3419 /* 128-bit constant floating-point values on Darwin should really be
3420 loaded as two parts. */
3421 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3422 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3423 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3425 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3426 know how to get a DFmode SUBREG of a TFmode. */
3427 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3428 simplify_gen_subreg (DImode, operands[1], mode, 0),
3430 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3431 GET_MODE_SIZE (DImode)),
3432 simplify_gen_subreg (DImode, operands[1], mode,
3433 GET_MODE_SIZE (DImode)),
3438 /* FIXME: In the long term, this switch statement should go away
3439 and be replaced by a sequence of tests based on things like
3445 if (CONSTANT_P (operands[1])
3446 && GET_CODE (operands[1]) != CONST_INT)
3447 operands[1] = force_const_mem (mode, operands[1]);
3453 if (CONSTANT_P (operands[1])
3454 && ! easy_fp_constant (operands[1], mode))
3455 operands[1] = force_const_mem (mode, operands[1]);
3466 if (CONSTANT_P (operands[1])
3467 && !easy_vector_constant (operands[1], mode))
3468 operands[1] = force_const_mem (mode, operands[1]);
3473 /* Use default pattern for address of ELF small data */
3476 && DEFAULT_ABI == ABI_V4
3477 && (GET_CODE (operands[1]) == SYMBOL_REF
3478 || GET_CODE (operands[1]) == CONST)
3479 && small_data_operand (operands[1], mode))
3481 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3485 if (DEFAULT_ABI == ABI_V4
3486 && mode == Pmode && mode == SImode
3487 && flag_pic == 1 && got_operand (operands[1], mode))
3489 emit_insn (gen_movsi_got (operands[0], operands[1]));
3493 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3497 && CONSTANT_P (operands[1])
3498 && GET_CODE (operands[1]) != HIGH
3499 && GET_CODE (operands[1]) != CONST_INT)
3501 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3503 /* If this is a function address on -mcall-aixdesc,
3504 convert it to the address of the descriptor. */
3505 if (DEFAULT_ABI == ABI_AIX
3506 && GET_CODE (operands[1]) == SYMBOL_REF
3507 && XSTR (operands[1], 0)[0] == '.')
3509 const char *name = XSTR (operands[1], 0);
3511 while (*name == '.')
3513 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3514 CONSTANT_POOL_ADDRESS_P (new_ref)
3515 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3516 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3517 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3518 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3519 operands[1] = new_ref;
3522 if (DEFAULT_ABI == ABI_DARWIN)
3525 if (MACHO_DYNAMIC_NO_PIC_P)
3527 /* Take care of any required data indirection. */
3528 operands[1] = rs6000_machopic_legitimize_pic_address (
3529 operands[1], mode, operands[0]);
3530 if (operands[0] != operands[1])
3531 emit_insn (gen_rtx_SET (VOIDmode,
3532 operands[0], operands[1]));
3536 emit_insn (gen_macho_high (target, operands[1]));
3537 emit_insn (gen_macho_low (operands[0], target, operands[1]));
3541 emit_insn (gen_elf_high (target, operands[1]));
3542 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3546 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3547 and we have put it in the TOC, we just need to make a TOC-relative
3550 && GET_CODE (operands[1]) == SYMBOL_REF
3551 && constant_pool_expr_p (operands[1])
3552 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3553 get_pool_mode (operands[1])))
3555 operands[1] = create_TOC_reference (operands[1]);
3557 else if (mode == Pmode
3558 && CONSTANT_P (operands[1])
3559 && ((GET_CODE (operands[1]) != CONST_INT
3560 && ! easy_fp_constant (operands[1], mode))
3561 || (GET_CODE (operands[1]) == CONST_INT
3562 && num_insns_constant (operands[1], mode) > 2)
3563 || (GET_CODE (operands[0]) == REG
3564 && FP_REGNO_P (REGNO (operands[0]))))
3565 && GET_CODE (operands[1]) != HIGH
3566 && ! legitimate_constant_pool_address_p (operands[1])
3567 && ! toc_relative_expr_p (operands[1]))
3569 /* Emit a USE operation so that the constant isn't deleted if
3570 expensive optimizations are turned on because nobody
3571 references it. This should only be done for operands that
3572 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3573 This should not be done for operands that contain LABEL_REFs.
3574 For now, we just handle the obvious case. */
3575 if (GET_CODE (operands[1]) != LABEL_REF)
3576 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3579 /* Darwin uses a special PIC legitimizer. */
3580 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3583 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3585 if (operands[0] != operands[1])
3586 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3591 /* If we are to limit the number of things we put in the TOC and
3592 this is a symbol plus a constant we can add in one insn,
3593 just put the symbol in the TOC and add the constant. Don't do
3594 this if reload is in progress. */
3595 if (GET_CODE (operands[1]) == CONST
3596 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3597 && GET_CODE (XEXP (operands[1], 0)) == PLUS
3598 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
3599 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3600 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3601 && ! side_effects_p (operands[0]))
3604 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
3605 rtx other = XEXP (XEXP (operands[1], 0), 1);
3607 sym = force_reg (mode, sym);
3609 emit_insn (gen_addsi3 (operands[0], sym, other));
3611 emit_insn (gen_adddi3 (operands[0], sym, other));
3615 operands[1] = force_const_mem (mode, operands[1]);
3618 && constant_pool_expr_p (XEXP (operands[1], 0))
3619 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3620 get_pool_constant (XEXP (operands[1], 0)),
3621 get_pool_mode (XEXP (operands[1], 0))))
3624 = gen_rtx_MEM (mode,
3625 create_TOC_reference (XEXP (operands[1], 0)));
3626 set_mem_alias_set (operands[1], get_TOC_alias_set ());
3627 RTX_UNCHANGING_P (operands[1]) = 1;
3633 if (GET_CODE (operands[0]) == MEM
3634 && GET_CODE (XEXP (operands[0], 0)) != REG
3635 && ! reload_in_progress)
3637 = replace_equiv_address (operands[0],
3638 copy_addr_to_reg (XEXP (operands[0], 0)));
3640 if (GET_CODE (operands[1]) == MEM
3641 && GET_CODE (XEXP (operands[1], 0)) != REG
3642 && ! reload_in_progress)
3644 = replace_equiv_address (operands[1],
3645 copy_addr_to_reg (XEXP (operands[1], 0)));
3648 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3650 gen_rtx_SET (VOIDmode,
3651 operands[0], operands[1]),
3652 gen_rtx_CLOBBER (VOIDmode,
3653 gen_rtx_SCRATCH (SImode)))));
3662 /* Above, we may have called force_const_mem which may have returned
3663 an invalid address. If we can, fix this up; otherwise, reload will
3664 have to deal with it. */
3665 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3666 operands[1] = validize_mem (operands[1]);
3669 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3672 /* Nonzero if we can use a floating-point register to pass this arg. */
3673 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3674 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3675 && (CUM)->fregno <= FP_ARG_MAX_REG \
3676 && TARGET_HARD_FLOAT && TARGET_FPRS)
3678 /* Nonzero if we can use an AltiVec register to pass this arg. */
3679 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3680 (ALTIVEC_VECTOR_MODE (MODE) \
3681 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3682 && TARGET_ALTIVEC_ABI \
3685 /* Return a nonzero value to say to return the function value in
3686 memory, just as large structures are always returned. TYPE will be
3687 the data type of the value, and FNTYPE will be the type of the
3688 function doing the returning, or @code{NULL} for libcalls.
3690 The AIX ABI for the RS/6000 specifies that all structures are
3691 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3692 specifies that structures <= 8 bytes are returned in r3/r4, but a
3693 draft put them in memory, and GCC used to implement the draft
3694 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3695 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3696 compatibility can change DRAFT_V4_STRUCT_RET to override the
3697 default, and -m switches get the final word. See
3698 rs6000_override_options for more details.
3700 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3701 long double support is enabled. These values are returned in memory.
3703 int_size_in_bytes returns -1 for variable size objects, which go in
3704 memory always. The cast to unsigned makes -1 > 8. */
3707 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3709 if (AGGREGATE_TYPE_P (type)
3710 && (TARGET_AIX_STRUCT_RET
3711 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3713 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3718 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3719 for a call to a function whose data type is FNTYPE.
3720 For a library call, FNTYPE is 0.
3722 For incoming args we set the number of arguments in the prototype large
3723 so we never return a PARALLEL. */
3726 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3727 rtx libname ATTRIBUTE_UNUSED, int incoming, int libcall)
3729 static CUMULATIVE_ARGS zero_cumulative;
3731 *cum = zero_cumulative;
3733 cum->fregno = FP_ARG_MIN_REG;
3734 cum->vregno = ALTIVEC_ARG_MIN_REG;
3735 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3736 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3737 ? CALL_LIBCALL : CALL_NORMAL);
3738 cum->sysv_gregno = GP_ARG_MIN_REG;
3739 cum->stdarg = fntype
3740 && (TYPE_ARG_TYPES (fntype) != 0
3741 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3742 != void_type_node));
3745 cum->nargs_prototype = 1000; /* don't return a PARALLEL */
3747 else if (cum->prototype)
3748 cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
3749 + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
3750 || rs6000_return_in_memory (TREE_TYPE (fntype),
3754 cum->nargs_prototype = 0;
3756 /* Check for a longcall attribute. */
3758 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3759 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
3760 cum->call_cookie = CALL_LONG;
3762 if (TARGET_DEBUG_ARG)
3764 fprintf (stderr, "\ninit_cumulative_args:");
3767 tree ret_type = TREE_TYPE (fntype);
3768 fprintf (stderr, " ret code = %s,",
3769 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3772 if (cum->call_cookie & CALL_LONG)
3773 fprintf (stderr, " longcall,");
3775 fprintf (stderr, " proto = %d, nargs = %d\n",
3776 cum->prototype, cum->nargs_prototype);
3780 /* If defined, a C expression which determines whether, and in which
3781 direction, to pad out an argument with extra space. The value
3782 should be of type `enum direction': either `upward' to pad above
3783 the argument, `downward' to pad below, or `none' to inhibit
3786 For the AIX ABI structs are always stored left shifted in their
3790 function_arg_padding (enum machine_mode mode, tree type)
3792 #ifndef AGGREGATE_PADDING_FIXED
3793 #define AGGREGATE_PADDING_FIXED 0
3795 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
3796 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
3799 if (!AGGREGATE_PADDING_FIXED)
3801 /* GCC used to pass structures of the same size as integer types as
3802 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
3803 ie. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
3804 passed padded downward, except that -mstrict-align further
3805 muddied the water in that multi-component structures of 2 and 4
3806 bytes in size were passed padded upward.
3808 The following arranges for best compatibility with previous
3809 versions of gcc, but removes the -mstrict-align dependency. */
3810 if (BYTES_BIG_ENDIAN)
3812 HOST_WIDE_INT size = 0;
3814 if (mode == BLKmode)
3816 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
3817 size = int_size_in_bytes (type);
3820 size = GET_MODE_SIZE (mode);
3822 if (size == 1 || size == 2 || size == 4)
3828 if (AGGREGATES_PAD_UPWARD_ALWAYS)
3830 if (type != 0 && AGGREGATE_TYPE_P (type))
3834 /* Fall back to the default. */
3835 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
3838 /* If defined, a C expression that gives the alignment boundary, in bits,
3839 of an argument with the specified mode and type. If it is not defined,
3840 PARM_BOUNDARY is used for all arguments.
3842 V.4 wants long longs to be double word aligned. */
3845 function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED)
3847 if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode))
3849 else if (SPE_VECTOR_MODE (mode))
3851 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
3854 return PARM_BOUNDARY;
3857 /* Update the data in CUM to advance over an argument
3858 of mode MODE and data type TYPE.
3859 (TYPE is null for libcalls where that information may not be available.) */
3862 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3863 tree type, int named)
3865 cum->nargs_prototype--;
3867 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
3869 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
3872 /* In variable-argument functions, vector arguments get GPRs allocated
3873 even if they are going to be passed in a vector register. */
3874 if (cum->stdarg && DEFAULT_ABI != ABI_V4)
3878 /* Vector parameters must be 16-byte aligned. This places
3879 them at 2 mod 4 in terms of words in 32-bit mode, since
3880 the parameter save area starts at offset 24 from the
3881 stack. In 64-bit mode, they just have to start on an
3882 even word, since the parameter save area is 16-byte
3883 aligned. Space for GPRs is reserved even if the argument
3884 will be passed in memory. */
3886 align = ((6 - (cum->words & 3)) & 3);
3888 align = cum->words & 1;
3889 cum->words += align + RS6000_ARG_SIZE (mode, type);
3891 if (TARGET_DEBUG_ARG)
3893 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
3895 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
3896 cum->nargs_prototype, cum->prototype,
3897 GET_MODE_NAME (mode));
3901 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
3903 && cum->sysv_gregno <= GP_ARG_MAX_REG)
3905 else if (DEFAULT_ABI == ABI_V4)
3907 if (TARGET_HARD_FLOAT && TARGET_FPRS
3908 && (mode == SFmode || mode == DFmode))
3910 if (cum->fregno <= FP_ARG_V4_MAX_REG)
3915 cum->words += cum->words & 1;
3916 cum->words += RS6000_ARG_SIZE (mode, type);
3922 int gregno = cum->sysv_gregno;
3924 /* Aggregates and IEEE quad get passed by reference. */
3925 if ((type && AGGREGATE_TYPE_P (type))
3929 n_words = RS6000_ARG_SIZE (mode, type);
3931 /* Long long and SPE vectors are put in odd registers. */
3932 if (n_words == 2 && (gregno & 1) == 0)
3935 /* Long long and SPE vectors are not split between registers
3937 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
3939 /* Long long is aligned on the stack. */
3941 cum->words += cum->words & 1;
3942 cum->words += n_words;
3945 /* Note: continuing to accumulate gregno past when we've started
3946 spilling to the stack indicates the fact that we've started
3947 spilling to the stack to expand_builtin_saveregs. */
3948 cum->sysv_gregno = gregno + n_words;
3951 if (TARGET_DEBUG_ARG)
3953 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
3954 cum->words, cum->fregno);
3955 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
3956 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
3957 fprintf (stderr, "mode = %4s, named = %d\n",
3958 GET_MODE_NAME (mode), named);
3963 int align = (TARGET_32BIT && (cum->words & 1) != 0
3964 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
3966 cum->words += align + RS6000_ARG_SIZE (mode, type);
3968 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3969 && TARGET_HARD_FLOAT && TARGET_FPRS)
3970 cum->fregno += (mode == TFmode ? 2 : 1);
3972 if (TARGET_DEBUG_ARG)
3974 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
3975 cum->words, cum->fregno);
3976 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
3977 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
3978 fprintf (stderr, "named = %d, align = %d\n", named, align);
3983 /* Determine where to put a SIMD argument on the SPE. */
3986 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3991 int gregno = cum->sysv_gregno;
3992 int n_words = RS6000_ARG_SIZE (mode, type);
3994 /* SPE vectors are put in odd registers. */
3995 if (n_words == 2 && (gregno & 1) == 0)
3998 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4001 enum machine_mode m = SImode;
4003 r1 = gen_rtx_REG (m, gregno);
4004 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4005 r2 = gen_rtx_REG (m, gregno + 1);
4006 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4007 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4014 if (cum->sysv_gregno <= GP_ARG_MAX_REG)
4015 return gen_rtx_REG (mode, cum->sysv_gregno);
4021 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4024 rs6000_mixed_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4025 tree type, int align_words)
4029 /* -mpowerpc64 with 32bit ABI splits up a DFmode argument
4030 in vararg list into zero, one or two GPRs */
4031 if (align_words >= GP_ARG_NUM_REG)
4032 return gen_rtx_PARALLEL (DFmode,
4034 gen_rtx_EXPR_LIST (VOIDmode,
4035 NULL_RTX, const0_rtx),
4036 gen_rtx_EXPR_LIST (VOIDmode,
4040 else if (align_words + RS6000_ARG_SIZE (mode, type)
4042 /* If this is partially on the stack, then we only
4043 include the portion actually in registers here. */
4044 return gen_rtx_PARALLEL (DFmode,
4046 gen_rtx_EXPR_LIST (VOIDmode,
4047 gen_rtx_REG (SImode,
4051 gen_rtx_EXPR_LIST (VOIDmode,
4056 /* split a DFmode arg into two GPRs */
4057 return gen_rtx_PARALLEL (DFmode,
4059 gen_rtx_EXPR_LIST (VOIDmode,
4060 gen_rtx_REG (SImode,
4064 gen_rtx_EXPR_LIST (VOIDmode,
4065 gen_rtx_REG (SImode,
4069 gen_rtx_EXPR_LIST (VOIDmode,
4070 gen_rtx_REG (mode, cum->fregno),
4073 /* -mpowerpc64 with 32bit ABI splits up a DImode argument into one
4075 else if (mode == DImode)
4077 if (align_words < GP_ARG_NUM_REG - 1)
4078 return gen_rtx_PARALLEL (DImode,
4080 gen_rtx_EXPR_LIST (VOIDmode,
4081 gen_rtx_REG (SImode,
4085 gen_rtx_EXPR_LIST (VOIDmode,
4086 gen_rtx_REG (SImode,
4090 else if (align_words == GP_ARG_NUM_REG - 1)
4091 return gen_rtx_PARALLEL (DImode,
4093 gen_rtx_EXPR_LIST (VOIDmode,
4094 NULL_RTX, const0_rtx),
4095 gen_rtx_EXPR_LIST (VOIDmode,
4096 gen_rtx_REG (SImode,
4101 else if (mode == BLKmode && align_words <= (GP_ARG_NUM_REG - 1))
4104 int size = int_size_in_bytes (type);
4105 int no_units = ((size - 1) / 4) + 1;
4106 int max_no_words = GP_ARG_NUM_REG - align_words;
4107 int rtlvec_len = no_units < max_no_words ? no_units : max_no_words;
4108 rtx *rtlvec = (rtx *) alloca (rtlvec_len * sizeof (rtx));
4110 memset ((char *) rtlvec, 0, rtlvec_len * sizeof (rtx));
4112 for (k=0; k < rtlvec_len; k++)
4113 rtlvec[k] = gen_rtx_EXPR_LIST (VOIDmode,
4114 gen_rtx_REG (SImode,
4117 k == 0 ? const0_rtx : GEN_INT (k*4));
4119 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k, rtlvec));
4125 /* Determine where to put an argument to a function.
4126 Value is zero to push the argument on the stack,
4127 or a hard register in which to store the argument.
4129 MODE is the argument's machine mode.
4130 TYPE is the data type of the argument (as a tree).
4131 This is null for libcalls where that information may
4133 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4134 the preceding args and about the function being called.
4135 NAMED is nonzero if this argument is a named parameter
4136 (otherwise it is an extra parameter matching an ellipsis).
4138 On RS/6000 the first eight words of non-FP are normally in registers
4139 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4140 Under V.4, the first 8 FP args are in registers.
4142 If this is floating-point and no prototype is specified, we use
4143 both an FP and integer register (or possibly FP reg and stack). Library
4144 functions (when CALL_LIBCALL is set) always have the proper types for args,
4145 so we can pass the FP value just in one register. emit_library_function
4146 doesn't support PARALLEL anyway. */
4149 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4150 tree type, int named)
4152 enum rs6000_abi abi = DEFAULT_ABI;
4154 /* Return a marker to indicate whether CR1 needs to set or clear the
4155 bit that V.4 uses to say fp args were passed in registers.
4156 Assume that we don't need the marker for software floating point,
4157 or compiler generated library calls. */
4158 if (mode == VOIDmode)
4161 && cum->nargs_prototype < 0
4162 && (cum->call_cookie & CALL_LIBCALL) == 0
4163 && (cum->prototype || TARGET_NO_PROTOTYPE))
4165 /* For the SPE, we need to crxor CR6 always. */
4167 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4168 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4169 return GEN_INT (cum->call_cookie
4170 | ((cum->fregno == FP_ARG_MIN_REG)
4171 ? CALL_V4_SET_FP_ARGS
4172 : CALL_V4_CLEAR_FP_ARGS));
4175 return GEN_INT (cum->call_cookie);
4178 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4179 return gen_rtx_REG (mode, cum->vregno);
4180 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4182 if (named || abi == ABI_V4)
4186 /* Vector parameters to varargs functions under AIX or Darwin
4187 get passed in memory and possibly also in GPRs. */
4188 int align, align_words;
4189 enum machine_mode part_mode = mode;
4191 /* Vector parameters must be 16-byte aligned. This places them at
4192 2 mod 4 in terms of words in 32-bit mode, since the parameter
4193 save area starts at offset 24 from the stack. In 64-bit mode,
4194 they just have to start on an even word, since the parameter
4195 save area is 16-byte aligned. */
4197 align = ((6 - (cum->words & 3)) & 3);
4199 align = cum->words & 1;
4200 align_words = cum->words + align;
4202 /* Out of registers? Memory, then. */
4203 if (align_words >= GP_ARG_NUM_REG)
4206 /* The vector value goes in GPRs. Only the part of the
4207 value in GPRs is reported here. */
4208 if (align_words + CLASS_MAX_NREGS (mode, GENERAL_REGS)
4210 /* Fortunately, there are only two possibilities, the value
4211 is either wholly in GPRs or half in GPRs and half not. */
4214 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
4217 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
4218 return rs6000_spe_function_arg (cum, mode, type);
4219 else if (abi == ABI_V4)
4221 if (TARGET_HARD_FLOAT && TARGET_FPRS
4222 && (mode == SFmode || mode == DFmode))
4224 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4225 return gen_rtx_REG (mode, cum->fregno);
4232 int gregno = cum->sysv_gregno;
4234 /* Aggregates and IEEE quad get passed by reference. */
4235 if ((type && AGGREGATE_TYPE_P (type))
4239 n_words = RS6000_ARG_SIZE (mode, type);
4241 /* Long long and SPE vectors are put in odd registers. */
4242 if (n_words == 2 && (gregno & 1) == 0)
4245 /* Long long do not split between registers and stack. */
4246 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4247 return gen_rtx_REG (mode, gregno);
4254 int align = (TARGET_32BIT && (cum->words & 1) != 0
4255 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
4256 int align_words = cum->words + align;
4258 if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
4261 if (TARGET_32BIT && TARGET_POWERPC64
4262 && (mode == DFmode || mode == DImode || mode == BLKmode))
4263 return rs6000_mixed_function_arg (cum, mode, type, align_words);
4265 if (USE_FP_FOR_ARG_P (cum, mode, type))
4268 || ((cum->nargs_prototype > 0)
4269 /* IBM AIX extended its linkage convention definition always
4270 to require FP args after register save area hole on the
4272 && (DEFAULT_ABI != ABI_AIX
4274 || (align_words < GP_ARG_NUM_REG))))
4275 return gen_rtx_REG (mode, cum->fregno);
4277 return gen_rtx_PARALLEL (mode,
4279 gen_rtx_EXPR_LIST (VOIDmode,
4280 ((align_words >= GP_ARG_NUM_REG)
4283 + RS6000_ARG_SIZE (mode, type)
4285 /* If this is partially on the stack, then
4286 we only include the portion actually
4287 in registers here. */
4288 ? gen_rtx_REG (SImode,
4289 GP_ARG_MIN_REG + align_words)
4290 : gen_rtx_REG (mode,
4291 GP_ARG_MIN_REG + align_words))),
4293 gen_rtx_EXPR_LIST (VOIDmode,
4294 gen_rtx_REG (mode, cum->fregno),
4297 else if (align_words < GP_ARG_NUM_REG)
4298 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4304 /* For an arg passed partly in registers and partly in memory,
4305 this is the number of registers used.
4306 For args passed entirely in registers or entirely in memory, zero. */
4309 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4310 tree type, int named)
4312 if (DEFAULT_ABI == ABI_V4)
4315 if (USE_FP_FOR_ARG_P (cum, mode, type)
4316 || USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4318 if (cum->nargs_prototype >= 0)
4322 if (cum->words < GP_ARG_NUM_REG
4323 && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type)))
4325 int ret = GP_ARG_NUM_REG - cum->words;
4326 if (ret && TARGET_DEBUG_ARG)
4327 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
4335 /* A C expression that indicates when an argument must be passed by
4336 reference. If nonzero for an argument, a copy of that argument is
4337 made in memory and a pointer to the argument is passed instead of
4338 the argument itself. The pointer is passed in whatever way is
4339 appropriate for passing a pointer to that type.
4341 Under V.4, structures and unions are passed by reference.
4343 As an extension to all ABIs, variable sized types are passed by
4347 function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4348 enum machine_mode mode ATTRIBUTE_UNUSED,
4349 tree type, int named ATTRIBUTE_UNUSED)
4351 if (DEFAULT_ABI == ABI_V4
4352 && ((type && AGGREGATE_TYPE_P (type))
4355 if (TARGET_DEBUG_ARG)
4356 fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
4360 return type && int_size_in_bytes (type) < 0;
4364 rs6000_move_block_from_reg(int regno, rtx x, int nregs)
4367 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
4372 for (i = 0; i < nregs; i++)
4374 rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
4375 if (reload_completed)
4377 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
4380 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
4381 i * GET_MODE_SIZE(reg_mode));
4384 tem = replace_equiv_address (tem, XEXP (tem, 0));
4386 if (tem == NULL_RTX)
4389 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
4394 /* Perform any needed actions needed for a function that is receiving a
4395 variable number of arguments.
4399 MODE and TYPE are the mode and type of the current parameter.
4401 PRETEND_SIZE is a variable that should be set to the amount of stack
4402 that must be pushed by the prolog to pretend that our caller pushed
4405 Normally, this macro will push all remaining incoming registers on the
4406 stack and set PRETEND_SIZE to the length of the registers pushed. */
4409 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4410 tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
4412 CUMULATIVE_ARGS next_cum;
4413 int reg_size = TARGET_32BIT ? 4 : 8;
4414 rtx save_area = NULL_RTX, mem;
4415 int first_reg_offset, set;
4417 /* Skip the last named argument. */
4419 function_arg_advance (&next_cum, mode, type, 1);
4421 if (DEFAULT_ABI == ABI_V4)
4423 /* Indicate to allocate space on the stack for varargs save area. */
4424 cfun->machine->sysv_varargs_p = 1;
4426 save_area = plus_constant (virtual_stack_vars_rtx,
4427 - RS6000_VARARGS_SIZE);
4429 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4433 first_reg_offset = next_cum.words;
4434 save_area = virtual_incoming_args_rtx;
4435 cfun->machine->sysv_varargs_p = 0;
4437 if (MUST_PASS_IN_STACK (mode, type))
4438 first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type);
4441 set = get_varargs_alias_set ();
4442 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
4444 mem = gen_rtx_MEM (BLKmode,
4445 plus_constant (save_area,
4446 first_reg_offset * reg_size)),
4447 set_mem_alias_set (mem, set);
4448 set_mem_align (mem, BITS_PER_WORD);
4450 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
4451 GP_ARG_NUM_REG - first_reg_offset);
4454 /* Save FP registers if needed. */
4455 if (DEFAULT_ABI == ABI_V4
4456 && TARGET_HARD_FLOAT && TARGET_FPRS
4458 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
4460 int fregno = next_cum.fregno;
4461 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4462 rtx lab = gen_label_rtx ();
4463 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4465 emit_jump_insn (gen_rtx_SET (VOIDmode,
4467 gen_rtx_IF_THEN_ELSE (VOIDmode,
4468 gen_rtx_NE (VOIDmode, cr1,
4470 gen_rtx_LABEL_REF (VOIDmode, lab),
4473 while (fregno <= FP_ARG_V4_MAX_REG)
4475 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
4476 set_mem_alias_set (mem, set);
4477 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
4486 /* Create the va_list data type. */
4489 rs6000_build_builtin_va_list (void)
4491 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
4493 /* For AIX, prefer 'char *' because that's what the system
4494 header files like. */
4495 if (DEFAULT_ABI != ABI_V4)
4496 return build_pointer_type (char_type_node);
4498 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4499 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4501 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
4502 unsigned_char_type_node);
4503 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
4504 unsigned_char_type_node);
4505 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
4507 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
4508 short_unsigned_type_node);
4509 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4511 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4514 DECL_FIELD_CONTEXT (f_gpr) = record;
4515 DECL_FIELD_CONTEXT (f_fpr) = record;
4516 DECL_FIELD_CONTEXT (f_res) = record;
4517 DECL_FIELD_CONTEXT (f_ovf) = record;
4518 DECL_FIELD_CONTEXT (f_sav) = record;
4520 TREE_CHAIN (record) = type_decl;
4521 TYPE_NAME (record) = type_decl;
4522 TYPE_FIELDS (record) = f_gpr;
4523 TREE_CHAIN (f_gpr) = f_fpr;
4524 TREE_CHAIN (f_fpr) = f_res;
4525 TREE_CHAIN (f_res) = f_ovf;
4526 TREE_CHAIN (f_ovf) = f_sav;
4528 layout_type (record);
4530 /* The correct type is an array type of one element. */
4531 return build_array_type (record, build_index_type (size_zero_node));
4534 /* Implement va_start. */
4537 rs6000_va_start (tree valist, rtx nextarg)
4539 HOST_WIDE_INT words, n_gpr, n_fpr;
4540 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4541 tree gpr, fpr, ovf, sav, t;
4543 /* Only SVR4 needs something special. */
4544 if (DEFAULT_ABI != ABI_V4)
4546 std_expand_builtin_va_start (valist, nextarg);
4550 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4551 f_fpr = TREE_CHAIN (f_gpr);
4552 f_res = TREE_CHAIN (f_fpr);
4553 f_ovf = TREE_CHAIN (f_res);
4554 f_sav = TREE_CHAIN (f_ovf);
4556 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4557 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4558 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4559 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4560 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4562 /* Count number of gp and fp argument registers used. */
4563 words = current_function_args_info.words;
4564 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
4565 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
4567 if (TARGET_DEBUG_ARG)
4568 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
4569 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
4570 words, n_gpr, n_fpr);
4572 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0));
4573 TREE_SIDE_EFFECTS (t) = 1;
4574 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4576 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0));
4577 TREE_SIDE_EFFECTS (t) = 1;
4578 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4580 /* Find the overflow area. */
4581 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
4583 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
4584 build_int_2 (words * UNITS_PER_WORD, 0));
4585 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4586 TREE_SIDE_EFFECTS (t) = 1;
4587 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4589 /* Find the register save area. */
4590 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
4591 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
4592 build_int_2 (-RS6000_VARARGS_SIZE, -1));
4593 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
4594 TREE_SIDE_EFFECTS (t) = 1;
4595 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4598 /* Implement va_arg. */
4601 rs6000_va_arg (tree valist, tree type)
4603 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4604 tree gpr, fpr, ovf, sav, reg, t, u;
4605 int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale;
4606 rtx lab_false, lab_over, addr_rtx, r;
4608 if (DEFAULT_ABI != ABI_V4)
4610 /* Variable sized types are passed by reference. */
4611 if (int_size_in_bytes (type) < 0)
4613 u = build_pointer_type (type);
4615 /* Args grow upward. */
4616 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
4617 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4618 TREE_SIDE_EFFECTS (t) = 1;
4620 t = build1 (NOP_EXPR, build_pointer_type (u), t);
4621 TREE_SIDE_EFFECTS (t) = 1;
4623 t = build1 (INDIRECT_REF, u, t);
4624 TREE_SIDE_EFFECTS (t) = 1;
4626 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4630 /* Altivec arguments must be aligned to a 128-bit boundary. */
4631 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4633 tree vtype = TREE_TYPE (valist);
4634 tree new_valist, modify;
4636 /* Round address up to multiple of 16. Computes
4638 new_valist = fold (build (BIT_AND_EXPR, vtype,
4639 fold (build (PLUS_EXPR, vtype, valist,
4640 build_int_2 (15, 0))),
4641 build_int_2 (~15, -1)));
4643 /* Update valist. */
4644 modify = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
4646 TREE_SIDE_EFFECTS (modify) = 1;
4647 expand_expr (modify, const0_rtx, VOIDmode, EXPAND_NORMAL);
4650 return std_expand_builtin_va_arg (valist, type);
4654 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4655 f_fpr = TREE_CHAIN (f_gpr);
4656 f_res = TREE_CHAIN (f_fpr);
4657 f_ovf = TREE_CHAIN (f_res);
4658 f_sav = TREE_CHAIN (f_ovf);
4660 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4661 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4662 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4663 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4664 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4666 size = int_size_in_bytes (type);
4667 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4669 if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode)
4671 /* Aggregates and long doubles are passed by reference. */
4677 size = UNITS_PER_WORD;
4680 else if (FLOAT_TYPE_P (type) && TARGET_HARD_FLOAT && TARGET_FPRS)
4682 /* FP args go in FP registers, if present. */
4691 /* Otherwise into GP registers. */
4699 /* Pull the value out of the saved registers ... */
4701 lab_false = gen_label_rtx ();
4702 lab_over = gen_label_rtx ();
4703 addr_rtx = gen_reg_rtx (Pmode);
4705 /* AltiVec vectors never go in registers. */
4706 if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE)
4708 TREE_THIS_VOLATILE (reg) = 1;
4709 emit_cmp_and_jump_insns
4710 (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
4711 GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1,
4714 /* Long long is aligned in the registers. */
4717 u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
4718 build_int_2 (n_reg - 1, 0));
4719 u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
4720 u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
4721 TREE_SIDE_EFFECTS (u) = 1;
4722 expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
4726 t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
4730 u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
4731 build_int_2 (n_reg, 0));
4732 TREE_SIDE_EFFECTS (u) = 1;
4734 u = build1 (CONVERT_EXPR, integer_type_node, u);
4735 TREE_SIDE_EFFECTS (u) = 1;
4737 u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
4738 TREE_SIDE_EFFECTS (u) = 1;
4740 t = build (PLUS_EXPR, ptr_type_node, t, u);
4741 TREE_SIDE_EFFECTS (t) = 1;
4743 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4745 emit_move_insn (addr_rtx, r);
4747 emit_jump_insn (gen_jump (lab_over));
4751 emit_label (lab_false);
4753 /* ... otherwise out of the overflow area. */
4755 /* Make sure we don't find reg 7 for the next int arg.
4757 All AltiVec vectors go in the overflow area. So in the AltiVec
4758 case we need to get the vectors from the overflow area, but
4759 remember where the GPRs and FPRs are. */
4760 if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE
4761 || !TARGET_ALTIVEC))
4763 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
4764 TREE_SIDE_EFFECTS (t) = 1;
4765 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4768 /* Care for on-stack alignment if needed. */
4775 /* AltiVec vectors are 16 byte aligned. */
4776 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
4781 t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0));
4782 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1));
4786 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4788 emit_move_insn (addr_rtx, r);
4790 t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0));
4791 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4792 TREE_SIDE_EFFECTS (t) = 1;
4793 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4795 emit_label (lab_over);
4799 r = gen_rtx_MEM (Pmode, addr_rtx);
4800 set_mem_alias_set (r, get_varargs_alias_set ());
4801 emit_move_insn (addr_rtx, r);
4809 #define def_builtin(MASK, NAME, TYPE, CODE) \
4811 if ((MASK) & target_flags) \
4812 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
4816 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
4818 static const struct builtin_description bdesc_3arg[] =
4820 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
4821 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
4822 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
4823 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
4824 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
4825 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
4826 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
4827 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
4828 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
4829 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
4830 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
4831 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
4832 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
4833 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
4834 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
4835 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
4836 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
4837 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
4838 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
4839 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
4840 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
4841 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
4842 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
4845 /* DST operations: void foo (void *, const int, const char). */
4847 static const struct builtin_description bdesc_dst[] =
4849 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
4850 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
4851 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
4852 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
4855 /* Simple binary operations: VECc = foo (VECa, VECb). */
4857 static struct builtin_description bdesc_2arg[] =
4859 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
4860 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
4861 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
4862 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
4863 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
4864 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
4865 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
4866 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
4867 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
4868 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
4869 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
4870 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
4871 { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
4872 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
4873 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
4874 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
4875 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
4876 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
4877 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
4878 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
4879 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
4880 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
4881 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
4882 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
4883 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
4884 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
4885 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
4886 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
4887 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
4888 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
4889 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
4890 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
4891 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
4892 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
4893 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
4894 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
4895 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
4896 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
4897 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
4898 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
4899 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
4900 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
4901 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
4902 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
4903 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
4904 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
4905 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
4906 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
4907 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
4908 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
4909 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
4910 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
4911 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
4912 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
4913 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
4914 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
4915 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
4916 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
4917 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
4918 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
4919 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
4920 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
4921 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
4922 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
4923 { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
4924 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
4925 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
4926 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
4927 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
4928 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
4929 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
4930 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
4931 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
4932 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
4933 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
4934 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
4935 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
4936 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
4937 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
4938 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
4939 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
4940 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
4941 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
4942 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
4943 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
4944 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
4945 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
4946 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
4947 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
4948 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
4949 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
4950 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
4951 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
4952 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
4953 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
4954 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
4955 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
4956 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
4957 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
4958 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
4959 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
4960 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
4961 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
4962 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
4963 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
4964 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
4965 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
4966 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
4967 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
4968 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
4969 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
4970 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
4971 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
4973 /* Place holder, leave as first spe builtin. */
4974 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
4975 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
4976 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
4977 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
4978 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
4979 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
4980 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
4981 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
4982 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
4983 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
4984 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
4985 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
4986 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
4987 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
4988 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
4989 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
4990 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
4991 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
4992 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
4993 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
4994 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
4995 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
4996 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
4997 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
4998 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
4999 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5000 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5001 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5002 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5003 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5004 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5005 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5006 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5007 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5008 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5009 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5010 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5011 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5012 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5013 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5014 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5015 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5016 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5017 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5018 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5019 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5020 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5021 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5022 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5023 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5024 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5025 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5026 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5027 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5028 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5029 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5030 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5031 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5032 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5033 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5034 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5035 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5036 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5037 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5038 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5039 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5040 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5041 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5042 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5043 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5044 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5045 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5046 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5047 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
5048 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5049 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
5050 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5051 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5052 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5053 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5054 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5055 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5056 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5057 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5058 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5059 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5060 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5061 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5062 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5063 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5064 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5065 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5066 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5067 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5068 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5069 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5070 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5071 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5072 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5073 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5074 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5075 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5076 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5077 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5078 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5079 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5080 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5081 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5082 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5084 /* SPE binary operations expecting a 5-bit unsigned literal. */
5085 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5087 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5088 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5089 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5090 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5091 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5092 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5093 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5094 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5095 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5096 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5097 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5098 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5099 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5100 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5101 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5102 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5103 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5104 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5105 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5106 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5107 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5108 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5109 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5110 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5111 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5112 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5114 /* Place-holder. Leave as last binary SPE builtin. */
5115 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
5118 /* AltiVec predicates. */
5120 struct builtin_description_predicates
5122 const unsigned int mask;
5123 const enum insn_code icode;
5125 const char *const name;
5126 const enum rs6000_builtins code;
5129 static const struct builtin_description_predicates bdesc_altivec_preds[] =
5131 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5132 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5133 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5134 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5135 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5136 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5137 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5138 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5139 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5140 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5141 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5142 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5143 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
5146 /* SPE predicates. */
5147 static struct builtin_description bdesc_spe_predicates[] =
5149 /* Place-holder. Leave as first. */
5150 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5151 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5152 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5153 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5154 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5155 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5156 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5157 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5158 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5159 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5160 /* Place-holder. Leave as last. */
5161 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5164 /* SPE evsel predicates. */
5165 static struct builtin_description bdesc_spe_evsel[] =
5167 /* Place-holder. Leave as first. */
5168 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5169 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5170 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5171 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5172 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5173 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5174 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5175 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5176 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5177 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5178 /* Place-holder. Leave as last. */
5179 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5182 /* ABS* operations. */
5184 static const struct builtin_description bdesc_abs[] =
5186 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5187 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5188 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5189 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5190 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5191 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5192 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5195 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5198 static struct builtin_description bdesc_1arg[] =
5200 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5201 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5202 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5203 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5204 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5205 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5206 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5207 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
5208 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5209 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5210 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
5211 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5212 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5213 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5214 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5215 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5216 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
5218 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5219 end with SPE_BUILTIN_EVSUBFUSIAAW. */
5220 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5221 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5222 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5223 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5224 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5225 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5226 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5227 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5228 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5229 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5230 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5231 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5232 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5233 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5234 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5235 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5236 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5237 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5238 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5239 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5240 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5241 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5242 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
5243 { 0, CODE_FOR_spe_evneg, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
5244 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5245 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5246 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5247 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
5249 /* Place-holder. Leave as last unary SPE builtin. */
5250 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
5254 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
5257 tree arg0 = TREE_VALUE (arglist);
5258 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5259 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5260 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5262 if (icode == CODE_FOR_nothing)
5263 /* Builtin not supported on this processor. */
5266 /* If we got invalid arguments bail out before generating bad rtl. */
5267 if (arg0 == error_mark_node)
5270 if (icode == CODE_FOR_altivec_vspltisb
5271 || icode == CODE_FOR_altivec_vspltish
5272 || icode == CODE_FOR_altivec_vspltisw
5273 || icode == CODE_FOR_spe_evsplatfi
5274 || icode == CODE_FOR_spe_evsplati)
5276 /* Only allow 5-bit *signed* literals. */
5277 if (GET_CODE (op0) != CONST_INT
5278 || INTVAL (op0) > 0x1f
5279 || INTVAL (op0) < -0x1f)
5281 error ("argument 1 must be a 5-bit signed literal");
5287 || GET_MODE (target) != tmode
5288 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5289 target = gen_reg_rtx (tmode);
5291 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5292 op0 = copy_to_mode_reg (mode0, op0);
5294 pat = GEN_FCN (icode) (target, op0);
5303 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
5305 rtx pat, scratch1, scratch2;
5306 tree arg0 = TREE_VALUE (arglist);
5307 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5308 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5309 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5311 /* If we have invalid arguments, bail out before generating bad rtl. */
5312 if (arg0 == error_mark_node)
5316 || GET_MODE (target) != tmode
5317 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5318 target = gen_reg_rtx (tmode);
5320 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5321 op0 = copy_to_mode_reg (mode0, op0);
5323 scratch1 = gen_reg_rtx (mode0);
5324 scratch2 = gen_reg_rtx (mode0);
5326 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
5335 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
5338 tree arg0 = TREE_VALUE (arglist);
5339 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5340 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5341 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5342 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5343 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5344 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5346 if (icode == CODE_FOR_nothing)
5347 /* Builtin not supported on this processor. */
5350 /* If we got invalid arguments bail out before generating bad rtl. */
5351 if (arg0 == error_mark_node || arg1 == error_mark_node)
5354 if (icode == CODE_FOR_altivec_vcfux
5355 || icode == CODE_FOR_altivec_vcfsx
5356 || icode == CODE_FOR_altivec_vctsxs
5357 || icode == CODE_FOR_altivec_vctuxs
5358 || icode == CODE_FOR_altivec_vspltb
5359 || icode == CODE_FOR_altivec_vsplth
5360 || icode == CODE_FOR_altivec_vspltw
5361 || icode == CODE_FOR_spe_evaddiw
5362 || icode == CODE_FOR_spe_evldd
5363 || icode == CODE_FOR_spe_evldh
5364 || icode == CODE_FOR_spe_evldw
5365 || icode == CODE_FOR_spe_evlhhesplat
5366 || icode == CODE_FOR_spe_evlhhossplat
5367 || icode == CODE_FOR_spe_evlhhousplat
5368 || icode == CODE_FOR_spe_evlwhe
5369 || icode == CODE_FOR_spe_evlwhos
5370 || icode == CODE_FOR_spe_evlwhou
5371 || icode == CODE_FOR_spe_evlwhsplat
5372 || icode == CODE_FOR_spe_evlwwsplat
5373 || icode == CODE_FOR_spe_evrlwi
5374 || icode == CODE_FOR_spe_evslwi
5375 || icode == CODE_FOR_spe_evsrwis
5376 || icode == CODE_FOR_spe_evsubifw
5377 || icode == CODE_FOR_spe_evsrwiu)
5379 /* Only allow 5-bit unsigned literals. */
5380 if (TREE_CODE (arg1) != INTEGER_CST
5381 || TREE_INT_CST_LOW (arg1) & ~0x1f)
5383 error ("argument 2 must be a 5-bit unsigned literal");
5389 || GET_MODE (target) != tmode
5390 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5391 target = gen_reg_rtx (tmode);
5393 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5394 op0 = copy_to_mode_reg (mode0, op0);
5395 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5396 op1 = copy_to_mode_reg (mode1, op1);
5398 pat = GEN_FCN (icode) (target, op0, op1);
5407 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
5408 tree arglist, rtx target)
5411 tree cr6_form = TREE_VALUE (arglist);
5412 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
5413 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5414 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5415 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5416 enum machine_mode tmode = SImode;
5417 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5418 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5421 if (TREE_CODE (cr6_form) != INTEGER_CST)
5423 error ("argument 1 of __builtin_altivec_predicate must be a constant");
5427 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
5432 /* If we have invalid arguments, bail out before generating bad rtl. */
5433 if (arg0 == error_mark_node || arg1 == error_mark_node)
5437 || GET_MODE (target) != tmode
5438 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5439 target = gen_reg_rtx (tmode);
5441 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5442 op0 = copy_to_mode_reg (mode0, op0);
5443 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5444 op1 = copy_to_mode_reg (mode1, op1);
5446 scratch = gen_reg_rtx (mode0);
5448 pat = GEN_FCN (icode) (scratch, op0, op1,
5449 gen_rtx (SYMBOL_REF, Pmode, opcode));
5454 /* The vec_any* and vec_all* predicates use the same opcodes for two
5455 different operations, but the bits in CR6 will be different
5456 depending on what information we want. So we have to play tricks
5457 with CR6 to get the right bits out.
5459 If you think this is disgusting, look at the specs for the
5460 AltiVec predicates. */
5462 switch (cr6_form_int)
5465 emit_insn (gen_cr6_test_for_zero (target));
5468 emit_insn (gen_cr6_test_for_zero_reverse (target));
5471 emit_insn (gen_cr6_test_for_lt (target));
5474 emit_insn (gen_cr6_test_for_lt_reverse (target));
5477 error ("argument 1 of __builtin_altivec_predicate is out of range");
5485 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
5488 tree arg0 = TREE_VALUE (arglist);
5489 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5490 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5491 enum machine_mode mode0 = Pmode;
5492 enum machine_mode mode1 = Pmode;
5493 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5494 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5496 if (icode == CODE_FOR_nothing)
5497 /* Builtin not supported on this processor. */
5500 /* If we got invalid arguments bail out before generating bad rtl. */
5501 if (arg0 == error_mark_node || arg1 == error_mark_node)
5505 || GET_MODE (target) != tmode
5506 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5507 target = gen_reg_rtx (tmode);
5509 op1 = copy_to_mode_reg (mode1, op1);
5511 if (op0 == const0_rtx)
5513 addr = gen_rtx_MEM (tmode, op1);
5517 op0 = copy_to_mode_reg (mode0, op0);
5518 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
5521 pat = GEN_FCN (icode) (target, addr);
5531 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
5533 tree arg0 = TREE_VALUE (arglist);
5534 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5535 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5536 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5537 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5538 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5540 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5541 enum machine_mode mode1 = Pmode;
5542 enum machine_mode mode2 = Pmode;
5544 /* Invalid arguments. Bail before doing anything stoopid! */
5545 if (arg0 == error_mark_node
5546 || arg1 == error_mark_node
5547 || arg2 == error_mark_node)
5550 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
5551 op0 = copy_to_mode_reg (tmode, op0);
5553 op2 = copy_to_mode_reg (mode2, op2);
5555 if (op1 == const0_rtx)
5557 addr = gen_rtx_MEM (tmode, op2);
5561 op1 = copy_to_mode_reg (mode1, op1);
5562 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
5565 pat = GEN_FCN (icode) (addr, op0);
5572 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
5575 tree arg0 = TREE_VALUE (arglist);
5576 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5577 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5578 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5579 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5580 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5581 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5582 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5583 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5584 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
5586 if (icode == CODE_FOR_nothing)
5587 /* Builtin not supported on this processor. */
5590 /* If we got invalid arguments bail out before generating bad rtl. */
5591 if (arg0 == error_mark_node
5592 || arg1 == error_mark_node
5593 || arg2 == error_mark_node)
5596 if (icode == CODE_FOR_altivec_vsldoi_4sf
5597 || icode == CODE_FOR_altivec_vsldoi_4si
5598 || icode == CODE_FOR_altivec_vsldoi_8hi
5599 || icode == CODE_FOR_altivec_vsldoi_16qi)
5601 /* Only allow 4-bit unsigned literals. */
5602 if (TREE_CODE (arg2) != INTEGER_CST
5603 || TREE_INT_CST_LOW (arg2) & ~0xf)
5605 error ("argument 3 must be a 4-bit unsigned literal");
5611 || GET_MODE (target) != tmode
5612 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5613 target = gen_reg_rtx (tmode);
5615 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5616 op0 = copy_to_mode_reg (mode0, op0);
5617 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5618 op1 = copy_to_mode_reg (mode1, op1);
5619 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
5620 op2 = copy_to_mode_reg (mode2, op2);
5622 pat = GEN_FCN (icode) (target, op0, op1, op2);
5630 /* Expand the lvx builtins. */
5632 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
5634 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5635 tree arglist = TREE_OPERAND (exp, 1);
5636 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5638 enum machine_mode tmode, mode0;
5640 enum insn_code icode;
5644 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
5645 icode = CODE_FOR_altivec_lvx_16qi;
5647 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
5648 icode = CODE_FOR_altivec_lvx_8hi;
5650 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
5651 icode = CODE_FOR_altivec_lvx_4si;
5653 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
5654 icode = CODE_FOR_altivec_lvx_4sf;
5663 arg0 = TREE_VALUE (arglist);
5664 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5665 tmode = insn_data[icode].operand[0].mode;
5666 mode0 = insn_data[icode].operand[1].mode;
5669 || GET_MODE (target) != tmode
5670 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5671 target = gen_reg_rtx (tmode);
5673 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5674 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5676 pat = GEN_FCN (icode) (target, op0);
5683 /* Expand the stvx builtins. */
5685 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
5688 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5689 tree arglist = TREE_OPERAND (exp, 1);
5690 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5692 enum machine_mode mode0, mode1;
5694 enum insn_code icode;
5698 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
5699 icode = CODE_FOR_altivec_stvx_16qi;
5701 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
5702 icode = CODE_FOR_altivec_stvx_8hi;
5704 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
5705 icode = CODE_FOR_altivec_stvx_4si;
5707 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
5708 icode = CODE_FOR_altivec_stvx_4sf;
5715 arg0 = TREE_VALUE (arglist);
5716 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5717 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5718 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5719 mode0 = insn_data[icode].operand[0].mode;
5720 mode1 = insn_data[icode].operand[1].mode;
5722 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
5723 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5724 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
5725 op1 = copy_to_mode_reg (mode1, op1);
5727 pat = GEN_FCN (icode) (op0, op1);
5735 /* Expand the dst builtins. */
5737 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
5740 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5741 tree arglist = TREE_OPERAND (exp, 1);
5742 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5743 tree arg0, arg1, arg2;
5744 enum machine_mode mode0, mode1, mode2;
5745 rtx pat, op0, op1, op2;
5746 struct builtin_description *d;
5751 /* Handle DST variants. */
5752 d = (struct builtin_description *) bdesc_dst;
5753 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
5754 if (d->code == fcode)
5756 arg0 = TREE_VALUE (arglist);
5757 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5758 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5759 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5760 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5761 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5762 mode0 = insn_data[d->icode].operand[0].mode;
5763 mode1 = insn_data[d->icode].operand[1].mode;
5764 mode2 = insn_data[d->icode].operand[2].mode;
5766 /* Invalid arguments, bail out before generating bad rtl. */
5767 if (arg0 == error_mark_node
5768 || arg1 == error_mark_node
5769 || arg2 == error_mark_node)
5772 if (TREE_CODE (arg2) != INTEGER_CST
5773 || TREE_INT_CST_LOW (arg2) & ~0x3)
5775 error ("argument to `%s' must be a 2-bit unsigned literal", d->name);
5779 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
5780 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5781 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
5782 op1 = copy_to_mode_reg (mode1, op1);
5784 pat = GEN_FCN (d->icode) (op0, op1, op2);
5795 /* Expand the builtin in EXP and store the result in TARGET. Store
5796 true in *EXPANDEDP if we found a builtin to expand. */
5798 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
5800 struct builtin_description *d;
5801 struct builtin_description_predicates *dp;
5803 enum insn_code icode;
5804 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5805 tree arglist = TREE_OPERAND (exp, 1);
5808 enum machine_mode tmode, mode0;
5809 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5811 target = altivec_expand_ld_builtin (exp, target, expandedp);
5815 target = altivec_expand_st_builtin (exp, target, expandedp);
5819 target = altivec_expand_dst_builtin (exp, target, expandedp);
5827 case ALTIVEC_BUILTIN_STVX:
5828 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
5829 case ALTIVEC_BUILTIN_STVEBX:
5830 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
5831 case ALTIVEC_BUILTIN_STVEHX:
5832 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
5833 case ALTIVEC_BUILTIN_STVEWX:
5834 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
5835 case ALTIVEC_BUILTIN_STVXL:
5836 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
5838 case ALTIVEC_BUILTIN_MFVSCR:
5839 icode = CODE_FOR_altivec_mfvscr;
5840 tmode = insn_data[icode].operand[0].mode;
5843 || GET_MODE (target) != tmode
5844 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5845 target = gen_reg_rtx (tmode);
5847 pat = GEN_FCN (icode) (target);
5853 case ALTIVEC_BUILTIN_MTVSCR:
5854 icode = CODE_FOR_altivec_mtvscr;
5855 arg0 = TREE_VALUE (arglist);
5856 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5857 mode0 = insn_data[icode].operand[0].mode;
5859 /* If we got invalid arguments bail out before generating bad rtl. */
5860 if (arg0 == error_mark_node)
5863 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
5864 op0 = copy_to_mode_reg (mode0, op0);
5866 pat = GEN_FCN (icode) (op0);
5871 case ALTIVEC_BUILTIN_DSSALL:
5872 emit_insn (gen_altivec_dssall ());
5875 case ALTIVEC_BUILTIN_DSS:
5876 icode = CODE_FOR_altivec_dss;
5877 arg0 = TREE_VALUE (arglist);
5878 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5879 mode0 = insn_data[icode].operand[0].mode;
5881 /* If we got invalid arguments bail out before generating bad rtl. */
5882 if (arg0 == error_mark_node)
5885 if (TREE_CODE (arg0) != INTEGER_CST
5886 || TREE_INT_CST_LOW (arg0) & ~0x3)
5888 error ("argument to dss must be a 2-bit unsigned literal");
5892 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
5893 op0 = copy_to_mode_reg (mode0, op0);
5895 emit_insn (gen_altivec_dss (op0));
5899 /* Expand abs* operations. */
5900 d = (struct builtin_description *) bdesc_abs;
5901 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
5902 if (d->code == fcode)
5903 return altivec_expand_abs_builtin (d->icode, arglist, target);
5905 /* Expand the AltiVec predicates. */
5906 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
5907 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
5908 if (dp->code == fcode)
5909 return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target);
5911 /* LV* are funky. We initialized them differently. */
5914 case ALTIVEC_BUILTIN_LVSL:
5915 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
5917 case ALTIVEC_BUILTIN_LVSR:
5918 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
5920 case ALTIVEC_BUILTIN_LVEBX:
5921 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
5923 case ALTIVEC_BUILTIN_LVEHX:
5924 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
5926 case ALTIVEC_BUILTIN_LVEWX:
5927 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
5929 case ALTIVEC_BUILTIN_LVXL:
5930 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
5932 case ALTIVEC_BUILTIN_LVX:
5933 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
5944 /* Binops that need to be initialized manually, but can be expanded
5945 automagically by rs6000_expand_binop_builtin. */
5946 static struct builtin_description bdesc_2arg_spe[] =
5948 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
5949 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
5950 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
5951 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
5952 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
5953 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
5954 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
5955 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
5956 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
5957 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
5958 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
5959 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
5960 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
5961 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
5962 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
5963 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
5964 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
5965 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
5966 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
5967 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
5968 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
5969 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
5972 /* Expand the builtin in EXP and store the result in TARGET. Store
5973 true in *EXPANDEDP if we found a builtin to expand.
5975 This expands the SPE builtins that are not simple unary and binary
5978 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
5980 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5981 tree arglist = TREE_OPERAND (exp, 1);
5983 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5984 enum insn_code icode;
5985 enum machine_mode tmode, mode0;
5987 struct builtin_description *d;
5992 /* Syntax check for a 5-bit unsigned immediate. */
5995 case SPE_BUILTIN_EVSTDD:
5996 case SPE_BUILTIN_EVSTDH:
5997 case SPE_BUILTIN_EVSTDW:
5998 case SPE_BUILTIN_EVSTWHE:
5999 case SPE_BUILTIN_EVSTWHO:
6000 case SPE_BUILTIN_EVSTWWE:
6001 case SPE_BUILTIN_EVSTWWO:
6002 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6003 if (TREE_CODE (arg1) != INTEGER_CST
6004 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6006 error ("argument 2 must be a 5-bit unsigned literal");
6014 /* The evsplat*i instructions are not quite generic. */
6017 case SPE_BUILTIN_EVSPLATFI:
6018 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6020 case SPE_BUILTIN_EVSPLATI:
6021 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6027 d = (struct builtin_description *) bdesc_2arg_spe;
6028 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6029 if (d->code == fcode)
6030 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6032 d = (struct builtin_description *) bdesc_spe_predicates;
6033 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6034 if (d->code == fcode)
6035 return spe_expand_predicate_builtin (d->icode, arglist, target);
6037 d = (struct builtin_description *) bdesc_spe_evsel;
6038 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6039 if (d->code == fcode)
6040 return spe_expand_evsel_builtin (d->icode, arglist, target);
6044 case SPE_BUILTIN_EVSTDDX:
6045 return altivec_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
6046 case SPE_BUILTIN_EVSTDHX:
6047 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
6048 case SPE_BUILTIN_EVSTDWX:
6049 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
6050 case SPE_BUILTIN_EVSTWHEX:
6051 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
6052 case SPE_BUILTIN_EVSTWHOX:
6053 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
6054 case SPE_BUILTIN_EVSTWWEX:
6055 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
6056 case SPE_BUILTIN_EVSTWWOX:
6057 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
6058 case SPE_BUILTIN_EVSTDD:
6059 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
6060 case SPE_BUILTIN_EVSTDH:
6061 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
6062 case SPE_BUILTIN_EVSTDW:
6063 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
6064 case SPE_BUILTIN_EVSTWHE:
6065 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
6066 case SPE_BUILTIN_EVSTWHO:
6067 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
6068 case SPE_BUILTIN_EVSTWWE:
6069 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
6070 case SPE_BUILTIN_EVSTWWO:
6071 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
6072 case SPE_BUILTIN_MFSPEFSCR:
6073 icode = CODE_FOR_spe_mfspefscr;
6074 tmode = insn_data[icode].operand[0].mode;
6077 || GET_MODE (target) != tmode
6078 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6079 target = gen_reg_rtx (tmode);
6081 pat = GEN_FCN (icode) (target);
6086 case SPE_BUILTIN_MTSPEFSCR:
6087 icode = CODE_FOR_spe_mtspefscr;
6088 arg0 = TREE_VALUE (arglist);
6089 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6090 mode0 = insn_data[icode].operand[0].mode;
6092 if (arg0 == error_mark_node)
6095 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6096 op0 = copy_to_mode_reg (mode0, op0);
6098 pat = GEN_FCN (icode) (op0);
6111 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
6113 rtx pat, scratch, tmp;
6114 tree form = TREE_VALUE (arglist);
6115 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6116 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6117 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6118 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6119 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6120 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6124 if (TREE_CODE (form) != INTEGER_CST)
6126 error ("argument 1 of __builtin_spe_predicate must be a constant");
6130 form_int = TREE_INT_CST_LOW (form);
6135 if (arg0 == error_mark_node || arg1 == error_mark_node)
6139 || GET_MODE (target) != SImode
6140 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6141 target = gen_reg_rtx (SImode);
6143 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6144 op0 = copy_to_mode_reg (mode0, op0);
6145 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6146 op1 = copy_to_mode_reg (mode1, op1);
6148 scratch = gen_reg_rtx (CCmode);
6150 pat = GEN_FCN (icode) (scratch, op0, op1);
6155 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6156 _lower_. We use one compare, but look in different bits of the
6157 CR for each variant.
6159 There are 2 elements in each SPE simd type (upper/lower). The CR
6160 bits are set as follows:
6162 BIT0 | BIT 1 | BIT 2 | BIT 3
6163 U | L | (U | L) | (U & L)
6165 So, for an "all" relationship, BIT 3 would be set.
6166 For an "any" relationship, BIT 2 would be set. Etc.
6168 Following traditional nomenclature, these bits map to:
6170 BIT0 | BIT 1 | BIT 2 | BIT 3
6173 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6178 /* All variant. OV bit. */
6180 /* We need to get to the OV bit, which is the ORDERED bit. We
6181 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6182 that's ugly and will trigger a validate_condition_mode abort.
6183 So let's just use another pattern. */
6184 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6186 /* Any variant. EQ bit. */
6190 /* Upper variant. LT bit. */
6194 /* Lower variant. GT bit. */
6199 error ("argument 1 of __builtin_spe_predicate is out of range");
6203 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6204 emit_move_insn (target, tmp);
6209 /* The evsel builtins look like this:
6211 e = __builtin_spe_evsel_OP (a, b, c, d);
6215 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6216 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6220 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
6223 tree arg0 = TREE_VALUE (arglist);
6224 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6225 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6226 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6227 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6228 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6229 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6230 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6231 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6232 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6237 if (arg0 == error_mark_node || arg1 == error_mark_node
6238 || arg2 == error_mark_node || arg3 == error_mark_node)
6242 || GET_MODE (target) != mode0
6243 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6244 target = gen_reg_rtx (mode0);
6246 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6247 op0 = copy_to_mode_reg (mode0, op0);
6248 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6249 op1 = copy_to_mode_reg (mode0, op1);
6250 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6251 op2 = copy_to_mode_reg (mode0, op2);
6252 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6253 op3 = copy_to_mode_reg (mode0, op3);
6255 /* Generate the compare. */
6256 scratch = gen_reg_rtx (CCmode);
6257 pat = GEN_FCN (icode) (scratch, op0, op1);
6262 if (mode0 == V2SImode)
6263 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
6265 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
6270 /* Expand an expression EXP that calls a built-in function,
6271 with result going to TARGET if that's convenient
6272 (and in mode MODE if that's convenient).
6273 SUBTARGET may be used as the target for computing one of EXP's operands.
6274 IGNORE is nonzero if the value is to be ignored. */
6277 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
6278 enum machine_mode mode ATTRIBUTE_UNUSED,
6279 int ignore ATTRIBUTE_UNUSED)
6281 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6282 tree arglist = TREE_OPERAND (exp, 1);
6283 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6284 struct builtin_description *d;
6291 ret = altivec_expand_builtin (exp, target, &success);
6298 ret = spe_expand_builtin (exp, target, &success);
6304 if (TARGET_ALTIVEC || TARGET_SPE)
6306 /* Handle simple unary operations. */
6307 d = (struct builtin_description *) bdesc_1arg;
6308 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
6309 if (d->code == fcode)
6310 return rs6000_expand_unop_builtin (d->icode, arglist, target);
6312 /* Handle simple binary operations. */
6313 d = (struct builtin_description *) bdesc_2arg;
6314 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
6315 if (d->code == fcode)
6316 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6318 /* Handle simple ternary operations. */
6319 d = (struct builtin_description *) bdesc_3arg;
6320 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
6321 if (d->code == fcode)
6322 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
6330 rs6000_init_builtins (void)
6332 opaque_V2SI_type_node = copy_node (V2SI_type_node);
6333 opaque_V2SF_type_node = copy_node (V2SF_type_node);
6334 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
6337 spe_init_builtins ();
6339 altivec_init_builtins ();
6340 if (TARGET_ALTIVEC || TARGET_SPE)
6341 rs6000_common_init_builtins ();
6344 /* Search through a set of builtins and enable the mask bits.
6345 DESC is an array of builtins.
6346 SIZE is the total number of builtins.
6347 START is the builtin enum at which to start.
6348 END is the builtin enum at which to end. */
6350 enable_mask_for_builtins (struct builtin_description *desc, int size,
6351 enum rs6000_builtins start,
6352 enum rs6000_builtins end)
6356 for (i = 0; i < size; ++i)
6357 if (desc[i].code == start)
6363 for (; i < size; ++i)
6365 /* Flip all the bits on. */
6366 desc[i].mask = target_flags;
6367 if (desc[i].code == end)
6373 spe_init_builtins (void)
6375 tree endlink = void_list_node;
6376 tree puint_type_node = build_pointer_type (unsigned_type_node);
6377 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
6378 struct builtin_description *d;
6381 tree v2si_ftype_4_v2si
6382 = build_function_type
6383 (opaque_V2SI_type_node,
6384 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6385 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6386 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6387 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6390 tree v2sf_ftype_4_v2sf
6391 = build_function_type
6392 (opaque_V2SF_type_node,
6393 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6394 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6395 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6396 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6399 tree int_ftype_int_v2si_v2si
6400 = build_function_type
6402 tree_cons (NULL_TREE, integer_type_node,
6403 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6404 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6407 tree int_ftype_int_v2sf_v2sf
6408 = build_function_type
6410 tree_cons (NULL_TREE, integer_type_node,
6411 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6412 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6415 tree void_ftype_v2si_puint_int
6416 = build_function_type (void_type_node,
6417 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6418 tree_cons (NULL_TREE, puint_type_node,
6419 tree_cons (NULL_TREE,
6423 tree void_ftype_v2si_puint_char
6424 = build_function_type (void_type_node,
6425 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6426 tree_cons (NULL_TREE, puint_type_node,
6427 tree_cons (NULL_TREE,
6431 tree void_ftype_v2si_pv2si_int
6432 = build_function_type (void_type_node,
6433 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6434 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6435 tree_cons (NULL_TREE,
6439 tree void_ftype_v2si_pv2si_char
6440 = build_function_type (void_type_node,
6441 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6442 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6443 tree_cons (NULL_TREE,
6448 = build_function_type (void_type_node,
6449 tree_cons (NULL_TREE, integer_type_node, endlink));
6452 = build_function_type (integer_type_node, endlink);
6454 tree v2si_ftype_pv2si_int
6455 = build_function_type (opaque_V2SI_type_node,
6456 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6457 tree_cons (NULL_TREE, integer_type_node,
6460 tree v2si_ftype_puint_int
6461 = build_function_type (opaque_V2SI_type_node,
6462 tree_cons (NULL_TREE, puint_type_node,
6463 tree_cons (NULL_TREE, integer_type_node,
6466 tree v2si_ftype_pushort_int
6467 = build_function_type (opaque_V2SI_type_node,
6468 tree_cons (NULL_TREE, pushort_type_node,
6469 tree_cons (NULL_TREE, integer_type_node,
6472 tree v2si_ftype_signed_char
6473 = build_function_type (opaque_V2SI_type_node,
6474 tree_cons (NULL_TREE, signed_char_type_node,
6477 /* The initialization of the simple binary and unary builtins is
6478 done in rs6000_common_init_builtins, but we have to enable the
6479 mask bits here manually because we have run out of `target_flags'
6480 bits. We really need to redesign this mask business. */
6482 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
6483 ARRAY_SIZE (bdesc_2arg),
6486 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
6487 ARRAY_SIZE (bdesc_1arg),
6489 SPE_BUILTIN_EVSUBFUSIAAW);
6490 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
6491 ARRAY_SIZE (bdesc_spe_predicates),
6492 SPE_BUILTIN_EVCMPEQ,
6493 SPE_BUILTIN_EVFSTSTLT);
6494 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
6495 ARRAY_SIZE (bdesc_spe_evsel),
6496 SPE_BUILTIN_EVSEL_CMPGTS,
6497 SPE_BUILTIN_EVSEL_FSTSTEQ);
6499 (*lang_hooks.decls.pushdecl)
6500 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
6501 opaque_V2SI_type_node));
6503 /* Initialize irregular SPE builtins. */
6505 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
6506 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
6507 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
6508 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
6509 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
6510 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
6511 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
6512 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
6513 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
6514 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
6515 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
6516 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
6517 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
6518 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
6519 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
6520 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
6521 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
6522 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
6525 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
6526 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
6527 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
6528 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
6529 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
6530 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
6531 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
6532 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
6533 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
6534 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
6535 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
6536 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
6537 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
6538 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
6539 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
6540 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
6541 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
6542 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
6543 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
6544 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
6545 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
6546 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
6549 d = (struct builtin_description *) bdesc_spe_predicates;
6550 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
6554 switch (insn_data[d->icode].operand[1].mode)
6557 type = int_ftype_int_v2si_v2si;
6560 type = int_ftype_int_v2sf_v2sf;
6566 def_builtin (d->mask, d->name, type, d->code);
6569 /* Evsel predicates. */
6570 d = (struct builtin_description *) bdesc_spe_evsel;
6571 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
6575 switch (insn_data[d->icode].operand[1].mode)
6578 type = v2si_ftype_4_v2si;
6581 type = v2sf_ftype_4_v2sf;
6587 def_builtin (d->mask, d->name, type, d->code);
6592 altivec_init_builtins (void)
6594 struct builtin_description *d;
6595 struct builtin_description_predicates *dp;
6597 tree pfloat_type_node = build_pointer_type (float_type_node);
6598 tree pint_type_node = build_pointer_type (integer_type_node);
6599 tree pshort_type_node = build_pointer_type (short_integer_type_node);
6600 tree pchar_type_node = build_pointer_type (char_type_node);
6602 tree pvoid_type_node = build_pointer_type (void_type_node);
6604 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
6605 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
6606 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
6607 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
6609 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
6611 tree int_ftype_int_v4si_v4si
6612 = build_function_type_list (integer_type_node,
6613 integer_type_node, V4SI_type_node,
6614 V4SI_type_node, NULL_TREE);
6615 tree v4sf_ftype_pcfloat
6616 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
6617 tree void_ftype_pfloat_v4sf
6618 = build_function_type_list (void_type_node,
6619 pfloat_type_node, V4SF_type_node, NULL_TREE);
6620 tree v4si_ftype_pcint
6621 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
6622 tree void_ftype_pint_v4si
6623 = build_function_type_list (void_type_node,
6624 pint_type_node, V4SI_type_node, NULL_TREE);
6625 tree v8hi_ftype_pcshort
6626 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
6627 tree void_ftype_pshort_v8hi
6628 = build_function_type_list (void_type_node,
6629 pshort_type_node, V8HI_type_node, NULL_TREE);
6630 tree v16qi_ftype_pcchar
6631 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
6632 tree void_ftype_pchar_v16qi
6633 = build_function_type_list (void_type_node,
6634 pchar_type_node, V16QI_type_node, NULL_TREE);
6635 tree void_ftype_v4si
6636 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
6637 tree v8hi_ftype_void
6638 = build_function_type (V8HI_type_node, void_list_node);
6639 tree void_ftype_void
6640 = build_function_type (void_type_node, void_list_node);
6642 = build_function_type_list (void_type_node, char_type_node, NULL_TREE);
6644 tree v16qi_ftype_long_pcvoid
6645 = build_function_type_list (V16QI_type_node,
6646 long_integer_type_node, pcvoid_type_node, NULL_TREE);
6647 tree v8hi_ftype_long_pcvoid
6648 = build_function_type_list (V8HI_type_node,
6649 long_integer_type_node, pcvoid_type_node, NULL_TREE);
6650 tree v4si_ftype_long_pcvoid
6651 = build_function_type_list (V4SI_type_node,
6652 long_integer_type_node, pcvoid_type_node, NULL_TREE);
6654 tree void_ftype_v4si_long_pvoid
6655 = build_function_type_list (void_type_node,
6656 V4SI_type_node, long_integer_type_node,
6657 pvoid_type_node, NULL_TREE);
6658 tree void_ftype_v16qi_long_pvoid
6659 = build_function_type_list (void_type_node,
6660 V16QI_type_node, long_integer_type_node,
6661 pvoid_type_node, NULL_TREE);
6662 tree void_ftype_v8hi_long_pvoid
6663 = build_function_type_list (void_type_node,
6664 V8HI_type_node, long_integer_type_node,
6665 pvoid_type_node, NULL_TREE);
6666 tree int_ftype_int_v8hi_v8hi
6667 = build_function_type_list (integer_type_node,
6668 integer_type_node, V8HI_type_node,
6669 V8HI_type_node, NULL_TREE);
6670 tree int_ftype_int_v16qi_v16qi
6671 = build_function_type_list (integer_type_node,
6672 integer_type_node, V16QI_type_node,
6673 V16QI_type_node, NULL_TREE);
6674 tree int_ftype_int_v4sf_v4sf
6675 = build_function_type_list (integer_type_node,
6676 integer_type_node, V4SF_type_node,
6677 V4SF_type_node, NULL_TREE);
6678 tree v4si_ftype_v4si
6679 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
6680 tree v8hi_ftype_v8hi
6681 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
6682 tree v16qi_ftype_v16qi
6683 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
6684 tree v4sf_ftype_v4sf
6685 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
6686 tree void_ftype_pcvoid_int_char
6687 = build_function_type_list (void_type_node,
6688 pcvoid_type_node, integer_type_node,
6689 char_type_node, NULL_TREE);
6691 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
6692 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
6693 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
6694 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
6695 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
6696 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
6697 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
6698 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
6699 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
6700 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
6701 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
6702 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
6703 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
6704 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
6705 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
6706 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
6707 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
6708 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
6709 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
6710 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS);
6711 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
6712 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
6713 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
6714 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
6715 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
6716 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
6717 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
6718 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
6719 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
6720 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
6721 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
6722 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
6724 /* Add the DST variants. */
6725 d = (struct builtin_description *) bdesc_dst;
6726 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6727 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_char, d->code);
6729 /* Initialize the predicates. */
6730 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6731 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6733 enum machine_mode mode1;
6736 mode1 = insn_data[dp->icode].operand[1].mode;
6741 type = int_ftype_int_v4si_v4si;
6744 type = int_ftype_int_v8hi_v8hi;
6747 type = int_ftype_int_v16qi_v16qi;
6750 type = int_ftype_int_v4sf_v4sf;
6756 def_builtin (dp->mask, dp->name, type, dp->code);
6759 /* Initialize the abs* operators. */
6760 d = (struct builtin_description *) bdesc_abs;
6761 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6763 enum machine_mode mode0;
6766 mode0 = insn_data[d->icode].operand[0].mode;
6771 type = v4si_ftype_v4si;
6774 type = v8hi_ftype_v8hi;
6777 type = v16qi_ftype_v16qi;
6780 type = v4sf_ftype_v4sf;
6786 def_builtin (d->mask, d->name, type, d->code);
6791 rs6000_common_init_builtins (void)
6793 struct builtin_description *d;
6796 tree v4sf_ftype_v4sf_v4sf_v16qi
6797 = build_function_type_list (V4SF_type_node,
6798 V4SF_type_node, V4SF_type_node,
6799 V16QI_type_node, NULL_TREE);
6800 tree v4si_ftype_v4si_v4si_v16qi
6801 = build_function_type_list (V4SI_type_node,
6802 V4SI_type_node, V4SI_type_node,
6803 V16QI_type_node, NULL_TREE);
6804 tree v8hi_ftype_v8hi_v8hi_v16qi
6805 = build_function_type_list (V8HI_type_node,
6806 V8HI_type_node, V8HI_type_node,
6807 V16QI_type_node, NULL_TREE);
6808 tree v16qi_ftype_v16qi_v16qi_v16qi
6809 = build_function_type_list (V16QI_type_node,
6810 V16QI_type_node, V16QI_type_node,
6811 V16QI_type_node, NULL_TREE);
6812 tree v4si_ftype_char
6813 = build_function_type_list (V4SI_type_node, char_type_node, NULL_TREE);
6814 tree v8hi_ftype_char
6815 = build_function_type_list (V8HI_type_node, char_type_node, NULL_TREE);
6816 tree v16qi_ftype_char
6817 = build_function_type_list (V16QI_type_node, char_type_node, NULL_TREE);
6818 tree v8hi_ftype_v16qi
6819 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
6820 tree v4sf_ftype_v4sf
6821 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
6823 tree v2si_ftype_v2si_v2si
6824 = build_function_type_list (opaque_V2SI_type_node,
6825 opaque_V2SI_type_node,
6826 opaque_V2SI_type_node, NULL_TREE);
6828 tree v2sf_ftype_v2sf_v2sf
6829 = build_function_type_list (opaque_V2SF_type_node,
6830 opaque_V2SF_type_node,
6831 opaque_V2SF_type_node, NULL_TREE);
6833 tree v2si_ftype_int_int
6834 = build_function_type_list (opaque_V2SI_type_node,
6835 integer_type_node, integer_type_node,
6838 tree v2si_ftype_v2si
6839 = build_function_type_list (opaque_V2SI_type_node,
6840 opaque_V2SI_type_node, NULL_TREE);
6842 tree v2sf_ftype_v2sf
6843 = build_function_type_list (opaque_V2SF_type_node,
6844 opaque_V2SF_type_node, NULL_TREE);
6846 tree v2sf_ftype_v2si
6847 = build_function_type_list (opaque_V2SF_type_node,
6848 opaque_V2SI_type_node, NULL_TREE);
6850 tree v2si_ftype_v2sf
6851 = build_function_type_list (opaque_V2SI_type_node,
6852 opaque_V2SF_type_node, NULL_TREE);
6854 tree v2si_ftype_v2si_char
6855 = build_function_type_list (opaque_V2SI_type_node,
6856 opaque_V2SI_type_node,
6857 char_type_node, NULL_TREE);
6859 tree v2si_ftype_int_char
6860 = build_function_type_list (opaque_V2SI_type_node,
6861 integer_type_node, char_type_node, NULL_TREE);
6863 tree v2si_ftype_char
6864 = build_function_type_list (opaque_V2SI_type_node,
6865 char_type_node, NULL_TREE);
6867 tree int_ftype_int_int
6868 = build_function_type_list (integer_type_node,
6869 integer_type_node, integer_type_node,
6872 tree v4si_ftype_v4si_v4si
6873 = build_function_type_list (V4SI_type_node,
6874 V4SI_type_node, V4SI_type_node, NULL_TREE);
6875 tree v4sf_ftype_v4si_char
6876 = build_function_type_list (V4SF_type_node,
6877 V4SI_type_node, char_type_node, NULL_TREE);
6878 tree v4si_ftype_v4sf_char
6879 = build_function_type_list (V4SI_type_node,
6880 V4SF_type_node, char_type_node, NULL_TREE);
6881 tree v4si_ftype_v4si_char
6882 = build_function_type_list (V4SI_type_node,
6883 V4SI_type_node, char_type_node, NULL_TREE);
6884 tree v8hi_ftype_v8hi_char
6885 = build_function_type_list (V8HI_type_node,
6886 V8HI_type_node, char_type_node, NULL_TREE);
6887 tree v16qi_ftype_v16qi_char
6888 = build_function_type_list (V16QI_type_node,
6889 V16QI_type_node, char_type_node, NULL_TREE);
6890 tree v16qi_ftype_v16qi_v16qi_char
6891 = build_function_type_list (V16QI_type_node,
6892 V16QI_type_node, V16QI_type_node,
6893 char_type_node, NULL_TREE);
6894 tree v8hi_ftype_v8hi_v8hi_char
6895 = build_function_type_list (V8HI_type_node,
6896 V8HI_type_node, V8HI_type_node,
6897 char_type_node, NULL_TREE);
6898 tree v4si_ftype_v4si_v4si_char
6899 = build_function_type_list (V4SI_type_node,
6900 V4SI_type_node, V4SI_type_node,
6901 char_type_node, NULL_TREE);
6902 tree v4sf_ftype_v4sf_v4sf_char
6903 = build_function_type_list (V4SF_type_node,
6904 V4SF_type_node, V4SF_type_node,
6905 char_type_node, NULL_TREE);
6906 tree v4sf_ftype_v4sf_v4sf
6907 = build_function_type_list (V4SF_type_node,
6908 V4SF_type_node, V4SF_type_node, NULL_TREE);
6909 tree v4sf_ftype_v4sf_v4sf_v4si
6910 = build_function_type_list (V4SF_type_node,
6911 V4SF_type_node, V4SF_type_node,
6912 V4SI_type_node, NULL_TREE);
6913 tree v4sf_ftype_v4sf_v4sf_v4sf
6914 = build_function_type_list (V4SF_type_node,
6915 V4SF_type_node, V4SF_type_node,
6916 V4SF_type_node, NULL_TREE);
6917 tree v4si_ftype_v4si_v4si_v4si
6918 = build_function_type_list (V4SI_type_node,
6919 V4SI_type_node, V4SI_type_node,
6920 V4SI_type_node, NULL_TREE);
6921 tree v8hi_ftype_v8hi_v8hi
6922 = build_function_type_list (V8HI_type_node,
6923 V8HI_type_node, V8HI_type_node, NULL_TREE);
6924 tree v8hi_ftype_v8hi_v8hi_v8hi
6925 = build_function_type_list (V8HI_type_node,
6926 V8HI_type_node, V8HI_type_node,
6927 V8HI_type_node, NULL_TREE);
6928 tree v4si_ftype_v8hi_v8hi_v4si
6929 = build_function_type_list (V4SI_type_node,
6930 V8HI_type_node, V8HI_type_node,
6931 V4SI_type_node, NULL_TREE);
6932 tree v4si_ftype_v16qi_v16qi_v4si
6933 = build_function_type_list (V4SI_type_node,
6934 V16QI_type_node, V16QI_type_node,
6935 V4SI_type_node, NULL_TREE);
6936 tree v16qi_ftype_v16qi_v16qi
6937 = build_function_type_list (V16QI_type_node,
6938 V16QI_type_node, V16QI_type_node, NULL_TREE);
6939 tree v4si_ftype_v4sf_v4sf
6940 = build_function_type_list (V4SI_type_node,
6941 V4SF_type_node, V4SF_type_node, NULL_TREE);
6942 tree v8hi_ftype_v16qi_v16qi
6943 = build_function_type_list (V8HI_type_node,
6944 V16QI_type_node, V16QI_type_node, NULL_TREE);
6945 tree v4si_ftype_v8hi_v8hi
6946 = build_function_type_list (V4SI_type_node,
6947 V8HI_type_node, V8HI_type_node, NULL_TREE);
6948 tree v8hi_ftype_v4si_v4si
6949 = build_function_type_list (V8HI_type_node,
6950 V4SI_type_node, V4SI_type_node, NULL_TREE);
6951 tree v16qi_ftype_v8hi_v8hi
6952 = build_function_type_list (V16QI_type_node,
6953 V8HI_type_node, V8HI_type_node, NULL_TREE);
6954 tree v4si_ftype_v16qi_v4si
6955 = build_function_type_list (V4SI_type_node,
6956 V16QI_type_node, V4SI_type_node, NULL_TREE);
6957 tree v4si_ftype_v16qi_v16qi
6958 = build_function_type_list (V4SI_type_node,
6959 V16QI_type_node, V16QI_type_node, NULL_TREE);
6960 tree v4si_ftype_v8hi_v4si
6961 = build_function_type_list (V4SI_type_node,
6962 V8HI_type_node, V4SI_type_node, NULL_TREE);
6963 tree v4si_ftype_v8hi
6964 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
6965 tree int_ftype_v4si_v4si
6966 = build_function_type_list (integer_type_node,
6967 V4SI_type_node, V4SI_type_node, NULL_TREE);
6968 tree int_ftype_v4sf_v4sf
6969 = build_function_type_list (integer_type_node,
6970 V4SF_type_node, V4SF_type_node, NULL_TREE);
6971 tree int_ftype_v16qi_v16qi
6972 = build_function_type_list (integer_type_node,
6973 V16QI_type_node, V16QI_type_node, NULL_TREE);
6974 tree int_ftype_v8hi_v8hi
6975 = build_function_type_list (integer_type_node,
6976 V8HI_type_node, V8HI_type_node, NULL_TREE);
6978 /* Add the simple ternary operators. */
6979 d = (struct builtin_description *) bdesc_3arg;
6980 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
6983 enum machine_mode mode0, mode1, mode2, mode3;
6986 if (d->name == 0 || d->icode == CODE_FOR_nothing)
6989 mode0 = insn_data[d->icode].operand[0].mode;
6990 mode1 = insn_data[d->icode].operand[1].mode;
6991 mode2 = insn_data[d->icode].operand[2].mode;
6992 mode3 = insn_data[d->icode].operand[3].mode;
6994 /* When all four are of the same mode. */
6995 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7000 type = v4si_ftype_v4si_v4si_v4si;
7003 type = v4sf_ftype_v4sf_v4sf_v4sf;
7006 type = v8hi_ftype_v8hi_v8hi_v8hi;
7009 type = v16qi_ftype_v16qi_v16qi_v16qi;
7015 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
7020 type = v4si_ftype_v4si_v4si_v16qi;
7023 type = v4sf_ftype_v4sf_v4sf_v16qi;
7026 type = v8hi_ftype_v8hi_v8hi_v16qi;
7029 type = v16qi_ftype_v16qi_v16qi_v16qi;
7035 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
7036 && mode3 == V4SImode)
7037 type = v4si_ftype_v16qi_v16qi_v4si;
7038 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
7039 && mode3 == V4SImode)
7040 type = v4si_ftype_v8hi_v8hi_v4si;
7041 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
7042 && mode3 == V4SImode)
7043 type = v4sf_ftype_v4sf_v4sf_v4si;
7045 /* vchar, vchar, vchar, 4 bit literal. */
7046 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7048 type = v16qi_ftype_v16qi_v16qi_char;
7050 /* vshort, vshort, vshort, 4 bit literal. */
7051 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7053 type = v8hi_ftype_v8hi_v8hi_char;
7055 /* vint, vint, vint, 4 bit literal. */
7056 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7058 type = v4si_ftype_v4si_v4si_char;
7060 /* vfloat, vfloat, vfloat, 4 bit literal. */
7061 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7063 type = v4sf_ftype_v4sf_v4sf_char;
7068 def_builtin (d->mask, d->name, type, d->code);
7071 /* Add the simple binary operators. */
7072 d = (struct builtin_description *) bdesc_2arg;
7073 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7075 enum machine_mode mode0, mode1, mode2;
7078 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7081 mode0 = insn_data[d->icode].operand[0].mode;
7082 mode1 = insn_data[d->icode].operand[1].mode;
7083 mode2 = insn_data[d->icode].operand[2].mode;
7085 /* When all three operands are of the same mode. */
7086 if (mode0 == mode1 && mode1 == mode2)
7091 type = v4sf_ftype_v4sf_v4sf;
7094 type = v4si_ftype_v4si_v4si;
7097 type = v16qi_ftype_v16qi_v16qi;
7100 type = v8hi_ftype_v8hi_v8hi;
7103 type = v2si_ftype_v2si_v2si;
7106 type = v2sf_ftype_v2sf_v2sf;
7109 type = int_ftype_int_int;
7116 /* A few other combos we really don't want to do manually. */
7118 /* vint, vfloat, vfloat. */
7119 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
7120 type = v4si_ftype_v4sf_v4sf;
7122 /* vshort, vchar, vchar. */
7123 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
7124 type = v8hi_ftype_v16qi_v16qi;
7126 /* vint, vshort, vshort. */
7127 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
7128 type = v4si_ftype_v8hi_v8hi;
7130 /* vshort, vint, vint. */
7131 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
7132 type = v8hi_ftype_v4si_v4si;
7134 /* vchar, vshort, vshort. */
7135 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
7136 type = v16qi_ftype_v8hi_v8hi;
7138 /* vint, vchar, vint. */
7139 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
7140 type = v4si_ftype_v16qi_v4si;
7142 /* vint, vchar, vchar. */
7143 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
7144 type = v4si_ftype_v16qi_v16qi;
7146 /* vint, vshort, vint. */
7147 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
7148 type = v4si_ftype_v8hi_v4si;
7150 /* vint, vint, 5 bit literal. */
7151 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
7152 type = v4si_ftype_v4si_char;
7154 /* vshort, vshort, 5 bit literal. */
7155 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
7156 type = v8hi_ftype_v8hi_char;
7158 /* vchar, vchar, 5 bit literal. */
7159 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
7160 type = v16qi_ftype_v16qi_char;
7162 /* vfloat, vint, 5 bit literal. */
7163 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
7164 type = v4sf_ftype_v4si_char;
7166 /* vint, vfloat, 5 bit literal. */
7167 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
7168 type = v4si_ftype_v4sf_char;
7170 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
7171 type = v2si_ftype_int_int;
7173 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
7174 type = v2si_ftype_v2si_char;
7176 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
7177 type = v2si_ftype_int_char;
7180 else if (mode0 == SImode)
7185 type = int_ftype_v4si_v4si;
7188 type = int_ftype_v4sf_v4sf;
7191 type = int_ftype_v16qi_v16qi;
7194 type = int_ftype_v8hi_v8hi;
7204 def_builtin (d->mask, d->name, type, d->code);
7207 /* Add the simple unary operators. */
7208 d = (struct builtin_description *) bdesc_1arg;
7209 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7211 enum machine_mode mode0, mode1;
7214 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7217 mode0 = insn_data[d->icode].operand[0].mode;
7218 mode1 = insn_data[d->icode].operand[1].mode;
7220 if (mode0 == V4SImode && mode1 == QImode)
7221 type = v4si_ftype_char;
7222 else if (mode0 == V8HImode && mode1 == QImode)
7223 type = v8hi_ftype_char;
7224 else if (mode0 == V16QImode && mode1 == QImode)
7225 type = v16qi_ftype_char;
7226 else if (mode0 == V4SFmode && mode1 == V4SFmode)
7227 type = v4sf_ftype_v4sf;
7228 else if (mode0 == V8HImode && mode1 == V16QImode)
7229 type = v8hi_ftype_v16qi;
7230 else if (mode0 == V4SImode && mode1 == V8HImode)
7231 type = v4si_ftype_v8hi;
7232 else if (mode0 == V2SImode && mode1 == V2SImode)
7233 type = v2si_ftype_v2si;
7234 else if (mode0 == V2SFmode && mode1 == V2SFmode)
7235 type = v2sf_ftype_v2sf;
7236 else if (mode0 == V2SFmode && mode1 == V2SImode)
7237 type = v2sf_ftype_v2si;
7238 else if (mode0 == V2SImode && mode1 == V2SFmode)
7239 type = v2si_ftype_v2sf;
7240 else if (mode0 == V2SImode && mode1 == QImode)
7241 type = v2si_ftype_char;
7245 def_builtin (d->mask, d->name, type, d->code);
7250 rs6000_init_libfuncs (void)
7252 if (!TARGET_HARD_FLOAT)
7255 if (DEFAULT_ABI != ABI_V4)
7257 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
7259 /* AIX library routines for float->int conversion. */
7260 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
7261 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
7264 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
7265 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
7266 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
7267 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
7268 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
7272 /* 32-bit SVR4 quad floating point routines. */
7274 set_optab_libfunc (add_optab, TFmode, "_q_add");
7275 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
7276 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
7277 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
7278 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
7279 if (TARGET_PPC_GPOPT || TARGET_POWER2)
7280 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
7282 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
7283 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
7284 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
7285 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
7286 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
7287 set_optab_libfunc (le_optab, TFmode, "_q_fle");
7289 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
7290 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
7291 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
7292 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
7293 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
7294 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
7295 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
7299 /* Expand a block move operation, and return 1 if successful. Return 0
7300 if we should let the compiler generate normal code.
7302 operands[0] is the destination
7303 operands[1] is the source
7304 operands[2] is the length
7305 operands[3] is the alignment */
7307 #define MAX_MOVE_REG 4
7310 expand_block_move (rtx operands[])
7312 rtx orig_dest = operands[0];
7313 rtx orig_src = operands[1];
7314 rtx bytes_rtx = operands[2];
7315 rtx align_rtx = operands[3];
7316 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
7321 rtx stores[MAX_MOVE_REG];
7324 /* If this is not a fixed size move, just call memcpy */
7328 /* If this is not a fixed size alignment, abort */
7329 if (GET_CODE (align_rtx) != CONST_INT)
7331 align = INTVAL (align_rtx);
7333 /* Anything to move? */
7334 bytes = INTVAL (bytes_rtx);
7338 /* store_one_arg depends on expand_block_move to handle at least the size of
7339 reg_parm_stack_space. */
7340 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7343 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7346 rtx (*movstrsi) (rtx, rtx, rtx, rtx);
7347 rtx (*mov) (rtx, rtx);
7349 enum machine_mode mode = BLKmode;
7353 && bytes > 24 /* move up to 32 bytes at a time */
7361 && ! fixed_regs[12])
7363 move_bytes = (bytes > 32) ? 32 : bytes;
7364 gen_func.movstrsi = gen_movstrsi_8reg;
7366 else if (TARGET_STRING
7367 && bytes > 16 /* move up to 24 bytes at a time */
7373 && ! fixed_regs[10])
7375 move_bytes = (bytes > 24) ? 24 : bytes;
7376 gen_func.movstrsi = gen_movstrsi_6reg;
7378 else if (TARGET_STRING
7379 && bytes > 8 /* move up to 16 bytes at a time */
7385 move_bytes = (bytes > 16) ? 16 : bytes;
7386 gen_func.movstrsi = gen_movstrsi_4reg;
7388 else if (bytes >= 8 && TARGET_POWERPC64
7389 /* 64-bit loads and stores require word-aligned
7391 && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
7395 gen_func.mov = gen_movdi;
7397 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
7398 { /* move up to 8 bytes at a time */
7399 move_bytes = (bytes > 8) ? 8 : bytes;
7400 gen_func.movstrsi = gen_movstrsi_2reg;
7402 else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
7403 { /* move 4 bytes */
7406 gen_func.mov = gen_movsi;
7408 else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT))
7409 { /* move 2 bytes */
7412 gen_func.mov = gen_movhi;
7414 else if (TARGET_STRING && bytes > 1)
7415 { /* move up to 4 bytes at a time */
7416 move_bytes = (bytes > 4) ? 4 : bytes;
7417 gen_func.movstrsi = gen_movstrsi_1reg;
7419 else /* move 1 byte at a time */
7423 gen_func.mov = gen_movqi;
7426 src = adjust_address (orig_src, mode, offset);
7427 dest = adjust_address (orig_dest, mode, offset);
7429 if (mode != BLKmode)
7431 rtx tmp_reg = gen_reg_rtx (mode);
7433 emit_insn ((*gen_func.mov) (tmp_reg, src));
7434 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
7437 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
7440 for (i = 0; i < num_reg; i++)
7441 emit_insn (stores[i]);
7445 if (mode == BLKmode)
7447 /* Move the address into scratch registers. The movstrsi
7448 patterns require zero offset. */
7449 if (!REG_P (XEXP (src, 0)))
7451 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
7452 src = replace_equiv_address (src, src_reg);
7454 set_mem_size (src, GEN_INT (move_bytes));
7456 if (!REG_P (XEXP (dest, 0)))
7458 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
7459 dest = replace_equiv_address (dest, dest_reg);
7461 set_mem_size (dest, GEN_INT (move_bytes));
7463 emit_insn ((*gen_func.movstrsi) (dest, src,
7464 GEN_INT (move_bytes & 31),
7473 /* Return 1 if OP is a load multiple operation. It is known to be a
7474 PARALLEL and the first section will be tested. */
7477 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7479 int count = XVECLEN (op, 0);
7480 unsigned int dest_regno;
7484 /* Perform a quick check so we don't blow up below. */
7486 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7487 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7488 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
7491 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7492 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
7494 for (i = 1; i < count; i++)
7496 rtx elt = XVECEXP (op, 0, i);
7498 if (GET_CODE (elt) != SET
7499 || GET_CODE (SET_DEST (elt)) != REG
7500 || GET_MODE (SET_DEST (elt)) != SImode
7501 || REGNO (SET_DEST (elt)) != dest_regno + i
7502 || GET_CODE (SET_SRC (elt)) != MEM
7503 || GET_MODE (SET_SRC (elt)) != SImode
7504 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
7505 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
7506 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
7507 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
7514 /* Similar, but tests for store multiple. Here, the second vector element
7515 is a CLOBBER. It will be tested later. */
7518 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7520 int count = XVECLEN (op, 0) - 1;
7521 unsigned int src_regno;
7525 /* Perform a quick check so we don't blow up below. */
7527 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7528 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
7529 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
7532 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7533 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
7535 for (i = 1; i < count; i++)
7537 rtx elt = XVECEXP (op, 0, i + 1);
7539 if (GET_CODE (elt) != SET
7540 || GET_CODE (SET_SRC (elt)) != REG
7541 || GET_MODE (SET_SRC (elt)) != SImode
7542 || REGNO (SET_SRC (elt)) != src_regno + i
7543 || GET_CODE (SET_DEST (elt)) != MEM
7544 || GET_MODE (SET_DEST (elt)) != SImode
7545 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
7546 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
7547 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
7548 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
7555 /* Return a string to perform a load_multiple operation.
7556 operands[0] is the vector.
7557 operands[1] is the source address.
7558 operands[2] is the first destination register. */
7561 rs6000_output_load_multiple (rtx operands[3])
7563 /* We have to handle the case where the pseudo used to contain the address
7564 is assigned to one of the output registers. */
7566 int words = XVECLEN (operands[0], 0);
7569 if (XVECLEN (operands[0], 0) == 1)
7570 return "{l|lwz} %2,0(%1)";
7572 for (i = 0; i < words; i++)
7573 if (refers_to_regno_p (REGNO (operands[2]) + i,
7574 REGNO (operands[2]) + i + 1, operands[1], 0))
7578 xop[0] = GEN_INT (4 * (words-1));
7579 xop[1] = operands[1];
7580 xop[2] = operands[2];
7581 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
7586 xop[0] = GEN_INT (4 * (words-1));
7587 xop[1] = operands[1];
7588 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7589 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
7594 for (j = 0; j < words; j++)
7597 xop[0] = GEN_INT (j * 4);
7598 xop[1] = operands[1];
7599 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
7600 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
7602 xop[0] = GEN_INT (i * 4);
7603 xop[1] = operands[1];
7604 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
7609 return "{lsi|lswi} %2,%1,%N0";
7612 /* Return 1 for a parallel vrsave operation. */
7615 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7617 int count = XVECLEN (op, 0);
7618 unsigned int dest_regno, src_regno;
7622 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7623 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7624 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
7627 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7628 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7630 if (dest_regno != VRSAVE_REGNO
7631 && src_regno != VRSAVE_REGNO)
7634 for (i = 1; i < count; i++)
7636 rtx elt = XVECEXP (op, 0, i);
7638 if (GET_CODE (elt) != CLOBBER
7639 && GET_CODE (elt) != SET)
7646 /* Return 1 for an PARALLEL suitable for mfcr. */
7649 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7651 int count = XVECLEN (op, 0);
7654 /* Perform a quick check so we don't blow up below. */
7656 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7657 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
7658 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
7661 for (i = 0; i < count; i++)
7663 rtx exp = XVECEXP (op, 0, i);
7668 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
7670 if (GET_CODE (src_reg) != REG
7671 || GET_MODE (src_reg) != CCmode
7672 || ! CR_REGNO_P (REGNO (src_reg)))
7675 if (GET_CODE (exp) != SET
7676 || GET_CODE (SET_DEST (exp)) != REG
7677 || GET_MODE (SET_DEST (exp)) != SImode
7678 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
7680 unspec = SET_SRC (exp);
7681 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
7683 if (GET_CODE (unspec) != UNSPEC
7684 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
7685 || XVECLEN (unspec, 0) != 2
7686 || XVECEXP (unspec, 0, 0) != src_reg
7687 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
7688 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
7694 /* Return 1 for an PARALLEL suitable for mtcrf. */
7697 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7699 int count = XVECLEN (op, 0);
7703 /* Perform a quick check so we don't blow up below. */
7705 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7706 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
7707 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
7709 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
7711 if (GET_CODE (src_reg) != REG
7712 || GET_MODE (src_reg) != SImode
7713 || ! INT_REGNO_P (REGNO (src_reg)))
7716 for (i = 0; i < count; i++)
7718 rtx exp = XVECEXP (op, 0, i);
7722 if (GET_CODE (exp) != SET
7723 || GET_CODE (SET_DEST (exp)) != REG
7724 || GET_MODE (SET_DEST (exp)) != CCmode
7725 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
7727 unspec = SET_SRC (exp);
7728 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
7730 if (GET_CODE (unspec) != UNSPEC
7731 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
7732 || XVECLEN (unspec, 0) != 2
7733 || XVECEXP (unspec, 0, 0) != src_reg
7734 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
7735 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
7741 /* Return 1 for an PARALLEL suitable for lmw. */
7744 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7746 int count = XVECLEN (op, 0);
7747 unsigned int dest_regno;
7749 unsigned int base_regno;
7750 HOST_WIDE_INT offset;
7753 /* Perform a quick check so we don't blow up below. */
7755 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7756 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7757 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
7760 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7761 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
7764 || count != 32 - (int) dest_regno)
7767 if (legitimate_indirect_address_p (src_addr, 0))
7770 base_regno = REGNO (src_addr);
7771 if (base_regno == 0)
7774 else if (legitimate_offset_address_p (SImode, src_addr, 0))
7776 offset = INTVAL (XEXP (src_addr, 1));
7777 base_regno = REGNO (XEXP (src_addr, 0));
7782 for (i = 0; i < count; i++)
7784 rtx elt = XVECEXP (op, 0, i);
7787 HOST_WIDE_INT newoffset;
7789 if (GET_CODE (elt) != SET
7790 || GET_CODE (SET_DEST (elt)) != REG
7791 || GET_MODE (SET_DEST (elt)) != SImode
7792 || REGNO (SET_DEST (elt)) != dest_regno + i
7793 || GET_CODE (SET_SRC (elt)) != MEM
7794 || GET_MODE (SET_SRC (elt)) != SImode)
7796 newaddr = XEXP (SET_SRC (elt), 0);
7797 if (legitimate_indirect_address_p (newaddr, 0))
7802 else if (legitimate_offset_address_p (SImode, newaddr, 0))
7804 addr_reg = XEXP (newaddr, 0);
7805 newoffset = INTVAL (XEXP (newaddr, 1));
7809 if (REGNO (addr_reg) != base_regno
7810 || newoffset != offset + 4 * i)
7817 /* Return 1 for an PARALLEL suitable for stmw. */
7820 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7822 int count = XVECLEN (op, 0);
7823 unsigned int src_regno;
7825 unsigned int base_regno;
7826 HOST_WIDE_INT offset;
7829 /* Perform a quick check so we don't blow up below. */
7831 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7832 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
7833 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
7836 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7837 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
7840 || count != 32 - (int) src_regno)
7843 if (legitimate_indirect_address_p (dest_addr, 0))
7846 base_regno = REGNO (dest_addr);
7847 if (base_regno == 0)
7850 else if (legitimate_offset_address_p (SImode, dest_addr, 0))
7852 offset = INTVAL (XEXP (dest_addr, 1));
7853 base_regno = REGNO (XEXP (dest_addr, 0));
7858 for (i = 0; i < count; i++)
7860 rtx elt = XVECEXP (op, 0, i);
7863 HOST_WIDE_INT newoffset;
7865 if (GET_CODE (elt) != SET
7866 || GET_CODE (SET_SRC (elt)) != REG
7867 || GET_MODE (SET_SRC (elt)) != SImode
7868 || REGNO (SET_SRC (elt)) != src_regno + i
7869 || GET_CODE (SET_DEST (elt)) != MEM
7870 || GET_MODE (SET_DEST (elt)) != SImode)
7872 newaddr = XEXP (SET_DEST (elt), 0);
7873 if (legitimate_indirect_address_p (newaddr, 0))
7878 else if (legitimate_offset_address_p (SImode, newaddr, 0))
7880 addr_reg = XEXP (newaddr, 0);
7881 newoffset = INTVAL (XEXP (newaddr, 1));
7885 if (REGNO (addr_reg) != base_regno
7886 || newoffset != offset + 4 * i)
7893 /* A validation routine: say whether CODE, a condition code, and MODE
7894 match. The other alternatives either don't make sense or should
7895 never be generated. */
7898 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
7900 if (GET_RTX_CLASS (code) != '<'
7901 || GET_MODE_CLASS (mode) != MODE_CC)
7904 /* These don't make sense. */
7905 if ((code == GT || code == LT || code == GE || code == LE)
7906 && mode == CCUNSmode)
7909 if ((code == GTU || code == LTU || code == GEU || code == LEU)
7910 && mode != CCUNSmode)
7913 if (mode != CCFPmode
7914 && (code == ORDERED || code == UNORDERED
7915 || code == UNEQ || code == LTGT
7916 || code == UNGT || code == UNLT
7917 || code == UNGE || code == UNLE))
7920 /* These should never be generated except for
7921 flag_finite_math_only. */
7922 if (mode == CCFPmode
7923 && ! flag_finite_math_only
7924 && (code == LE || code == GE
7925 || code == UNEQ || code == LTGT
7926 || code == UNGT || code == UNLT))
7929 /* These are invalid; the information is not there. */
7930 if (mode == CCEQmode
7931 && code != EQ && code != NE)
7935 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
7936 We only check the opcode against the mode of the CC value here. */
7939 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7941 enum rtx_code code = GET_CODE (op);
7942 enum machine_mode cc_mode;
7944 if (GET_RTX_CLASS (code) != '<')
7947 cc_mode = GET_MODE (XEXP (op, 0));
7948 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
7951 validate_condition_mode (code, cc_mode);
7956 /* Return 1 if OP is a comparison operation that is valid for a branch
7957 insn and which is true if the corresponding bit in the CC register
7961 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
7965 if (! branch_comparison_operator (op, mode))
7968 code = GET_CODE (op);
7969 return (code == EQ || code == LT || code == GT
7970 || (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE)
7971 || code == LTU || code == GTU
7972 || code == UNORDERED);
7975 /* Return 1 if OP is a comparison operation that is valid for an scc
7976 insn: it must be a positive comparison. */
7979 scc_comparison_operator (rtx op, enum machine_mode mode)
7981 return branch_positive_comparison_operator (op, mode);
7985 trap_comparison_operator (rtx op, enum machine_mode mode)
7987 if (mode != VOIDmode && mode != GET_MODE (op))
7989 return GET_RTX_CLASS (GET_CODE (op)) == '<';
7993 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7995 enum rtx_code code = GET_CODE (op);
7996 return (code == AND || code == IOR || code == XOR);
8000 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8002 enum rtx_code code = GET_CODE (op);
8003 return (code == IOR || code == XOR);
8007 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8009 enum rtx_code code = GET_CODE (op);
8010 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
8013 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8014 mask required to convert the result of a rotate insn into a shift
8015 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
8018 includes_lshift_p (rtx shiftop, rtx andop)
8020 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8022 shift_mask <<= INTVAL (shiftop);
8024 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8027 /* Similar, but for right shift. */
8030 includes_rshift_p (rtx shiftop, rtx andop)
8032 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8034 shift_mask >>= INTVAL (shiftop);
8036 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8039 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8040 to perform a left shift. It must have exactly SHIFTOP least
8041 significant 0's, then one or more 1's, then zero or more 0's. */
8044 includes_rldic_lshift_p (rtx shiftop, rtx andop)
8046 if (GET_CODE (andop) == CONST_INT)
8048 HOST_WIDE_INT c, lsb, shift_mask;
8051 if (c == 0 || c == ~0)
8055 shift_mask <<= INTVAL (shiftop);
8057 /* Find the least significant one bit. */
8060 /* It must coincide with the LSB of the shift mask. */
8061 if (-lsb != shift_mask)
8064 /* Invert to look for the next transition (if any). */
8067 /* Remove the low group of ones (originally low group of zeros). */
8070 /* Again find the lsb, and check we have all 1's above. */
8074 else if (GET_CODE (andop) == CONST_DOUBLE
8075 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8077 HOST_WIDE_INT low, high, lsb;
8078 HOST_WIDE_INT shift_mask_low, shift_mask_high;
8080 low = CONST_DOUBLE_LOW (andop);
8081 if (HOST_BITS_PER_WIDE_INT < 64)
8082 high = CONST_DOUBLE_HIGH (andop);
8084 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
8085 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
8088 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8090 shift_mask_high = ~0;
8091 if (INTVAL (shiftop) > 32)
8092 shift_mask_high <<= INTVAL (shiftop) - 32;
8096 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8103 return high == -lsb;
8106 shift_mask_low = ~0;
8107 shift_mask_low <<= INTVAL (shiftop);
8111 if (-lsb != shift_mask_low)
8114 if (HOST_BITS_PER_WIDE_INT < 64)
8119 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8122 return high == -lsb;
8126 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8132 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8133 to perform a left shift. It must have SHIFTOP or more least
8134 significant 0's, with the remainder of the word 1's. */
8137 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
8139 if (GET_CODE (andop) == CONST_INT)
8141 HOST_WIDE_INT c, lsb, shift_mask;
8144 shift_mask <<= INTVAL (shiftop);
8147 /* Find the least significant one bit. */
8150 /* It must be covered by the shift mask.
8151 This test also rejects c == 0. */
8152 if ((lsb & shift_mask) == 0)
8155 /* Check we have all 1's above the transition, and reject all 1's. */
8156 return c == -lsb && lsb != 1;
8158 else if (GET_CODE (andop) == CONST_DOUBLE
8159 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8161 HOST_WIDE_INT low, lsb, shift_mask_low;
8163 low = CONST_DOUBLE_LOW (andop);
8165 if (HOST_BITS_PER_WIDE_INT < 64)
8167 HOST_WIDE_INT high, shift_mask_high;
8169 high = CONST_DOUBLE_HIGH (andop);
8173 shift_mask_high = ~0;
8174 if (INTVAL (shiftop) > 32)
8175 shift_mask_high <<= INTVAL (shiftop) - 32;
8179 if ((lsb & shift_mask_high) == 0)
8182 return high == -lsb;
8188 shift_mask_low = ~0;
8189 shift_mask_low <<= INTVAL (shiftop);
8193 if ((lsb & shift_mask_low) == 0)
8196 return low == -lsb && lsb != 1;
8202 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
8203 for lfq and stfq insns.
8205 Note reg1 and reg2 *must* be hard registers. To be sure we will
8206 abort if we are passed pseudo registers. */
8209 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
8211 /* We might have been passed a SUBREG. */
8212 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8215 return (REGNO (reg1) == REGNO (reg2) - 1);
8218 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8219 addr1 and addr2 must be in consecutive memory locations
8220 (addr2 == addr1 + 8). */
8223 addrs_ok_for_quad_peep (rtx addr1, rtx addr2)
8228 /* Extract an offset (if used) from the first addr. */
8229 if (GET_CODE (addr1) == PLUS)
8231 /* If not a REG, return zero. */
8232 if (GET_CODE (XEXP (addr1, 0)) != REG)
8236 reg1 = REGNO (XEXP (addr1, 0));
8237 /* The offset must be constant! */
8238 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8240 offset1 = INTVAL (XEXP (addr1, 1));
8243 else if (GET_CODE (addr1) != REG)
8247 reg1 = REGNO (addr1);
8248 /* This was a simple (mem (reg)) expression. Offset is 0. */
8252 /* Make sure the second address is a (mem (plus (reg) (const_int)))
8253 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
8254 register as addr1. */
8255 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
8257 if (GET_CODE (addr2) != PLUS)
8260 if (GET_CODE (XEXP (addr2, 0)) != REG
8261 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8264 if (reg1 != REGNO (XEXP (addr2, 0)))
8267 /* The offset for the second addr must be 8 more than the first addr. */
8268 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8271 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
8276 /* Return the register class of a scratch register needed to copy IN into
8277 or out of a register in CLASS in MODE. If it can be done directly,
8278 NO_REGS is returned. */
8281 secondary_reload_class (enum reg_class class,
8282 enum machine_mode mode ATTRIBUTE_UNUSED,
8287 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8289 && MACHOPIC_INDIRECT
8293 /* We cannot copy a symbolic operand directly into anything
8294 other than BASE_REGS for TARGET_ELF. So indicate that a
8295 register from BASE_REGS is needed as an intermediate
8298 On Darwin, pic addresses require a load from memory, which
8299 needs a base register. */
8300 if (class != BASE_REGS
8301 && (GET_CODE (in) == SYMBOL_REF
8302 || GET_CODE (in) == HIGH
8303 || GET_CODE (in) == LABEL_REF
8304 || GET_CODE (in) == CONST))
8308 if (GET_CODE (in) == REG)
8311 if (regno >= FIRST_PSEUDO_REGISTER)
8313 regno = true_regnum (in);
8314 if (regno >= FIRST_PSEUDO_REGISTER)
8318 else if (GET_CODE (in) == SUBREG)
8320 regno = true_regnum (in);
8321 if (regno >= FIRST_PSEUDO_REGISTER)
8327 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8329 if (class == GENERAL_REGS || class == BASE_REGS
8330 || (regno >= 0 && INT_REGNO_P (regno)))
8333 /* Constants, memory, and FP registers can go into FP registers. */
8334 if ((regno == -1 || FP_REGNO_P (regno))
8335 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8338 /* Memory, and AltiVec registers can go into AltiVec registers. */
8339 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8340 && class == ALTIVEC_REGS)
8343 /* We can copy among the CR registers. */
8344 if ((class == CR_REGS || class == CR0_REGS)
8345 && regno >= 0 && CR_REGNO_P (regno))
8348 /* Otherwise, we need GENERAL_REGS. */
8349 return GENERAL_REGS;
8352 /* Given a comparison operation, return the bit number in CCR to test. We
8353 know this is a valid comparison.
8355 SCC_P is 1 if this is for an scc. That means that %D will have been
8356 used instead of %C, so the bits will be in different places.
8358 Return -1 if OP isn't a valid comparison for some reason. */
8361 ccr_bit (rtx op, int scc_p)
8363 enum rtx_code code = GET_CODE (op);
8364 enum machine_mode cc_mode;
8369 if (GET_RTX_CLASS (code) != '<')
8374 if (GET_CODE (reg) != REG
8375 || ! CR_REGNO_P (REGNO (reg)))
8378 cc_mode = GET_MODE (reg);
8379 cc_regnum = REGNO (reg);
8380 base_bit = 4 * (cc_regnum - CR0_REGNO);
8382 validate_condition_mode (code, cc_mode);
8384 /* When generating a sCOND operation, only positive conditions are
8386 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8387 && code != GTU && code != LTU)
8393 if (TARGET_E500 && !TARGET_FPRS
8394 && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
8395 return base_bit + 1;
8396 return scc_p ? base_bit + 3 : base_bit + 2;
8398 if (TARGET_E500 && !TARGET_FPRS
8399 && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
8400 return base_bit + 1;
8401 return base_bit + 2;
8402 case GT: case GTU: case UNLE:
8403 return base_bit + 1;
8404 case LT: case LTU: case UNGE:
8406 case ORDERED: case UNORDERED:
8407 return base_bit + 3;
8410 /* If scc, we will have done a cror to put the bit in the
8411 unordered position. So test that bit. For integer, this is ! LT
8412 unless this is an scc insn. */
8413 return scc_p ? base_bit + 3 : base_bit;
8416 return scc_p ? base_bit + 3 : base_bit + 1;
8423 /* Return the GOT register. */
8426 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
8428 /* The second flow pass currently (June 1999) can't update
8429 regs_ever_live without disturbing other parts of the compiler, so
8430 update it here to make the prolog/epilogue code happy. */
8431 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
8432 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
8434 current_function_uses_pic_offset_table = 1;
8436 return pic_offset_table_rtx;
8439 /* Function to init struct machine_function.
8440 This will be called, via a pointer variable,
8441 from push_function_context. */
8443 static struct machine_function *
8444 rs6000_init_machine_status (void)
8446 return ggc_alloc_cleared (sizeof (machine_function));
8449 /* These macros test for integers and extract the low-order bits. */
8451 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
8452 && GET_MODE (X) == VOIDmode)
8454 #define INT_LOWPART(X) \
8455 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
8461 unsigned long val = INT_LOWPART (op);
8463 /* If the high bit is zero, the value is the first 1 bit we find
8465 if ((val & 0x80000000) == 0)
8467 if ((val & 0xffffffff) == 0)
8471 while (((val <<= 1) & 0x80000000) == 0)
8476 /* If the high bit is set and the low bit is not, or the mask is all
8477 1's, the value is zero. */
8478 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
8481 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
8484 while (((val >>= 1) & 1) != 0)
8494 unsigned long val = INT_LOWPART (op);
8496 /* If the low bit is zero, the value is the first 1 bit we find from
8500 if ((val & 0xffffffff) == 0)
8504 while (((val >>= 1) & 1) == 0)
8510 /* If the low bit is set and the high bit is not, or the mask is all
8511 1's, the value is 31. */
8512 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
8515 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
8518 while (((val <<= 1) & 0x80000000) != 0)
8524 /* Locate some local-dynamic symbol still in use by this function
8525 so that we can print its name in some tls_ld pattern. */
8528 rs6000_get_some_local_dynamic_name (void)
8532 if (cfun->machine->some_ld_name)
8533 return cfun->machine->some_ld_name;
8535 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8537 && for_each_rtx (&PATTERN (insn),
8538 rs6000_get_some_local_dynamic_name_1, 0))
8539 return cfun->machine->some_ld_name;
8544 /* Helper function for rs6000_get_some_local_dynamic_name. */
8547 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8551 if (GET_CODE (x) == SYMBOL_REF)
8553 const char *str = XSTR (x, 0);
8554 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8556 cfun->machine->some_ld_name = str;
8564 /* Print an operand. Recognize special options, documented below. */
8567 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
8568 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
8570 #define SMALL_DATA_RELOC "sda21"
8571 #define SMALL_DATA_REG 0
8575 print_operand (FILE *file, rtx x, int code)
8579 unsigned HOST_WIDE_INT uval;
8584 /* Write out an instruction after the call which may be replaced
8585 with glue code by the loader. This depends on the AIX version. */
8586 asm_fprintf (file, RS6000_CALL_GLUE);
8589 /* %a is output_address. */
8592 /* If X is a constant integer whose low-order 5 bits are zero,
8593 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
8594 in the AIX assembler where "sri" with a zero shift count
8595 writes a trash instruction. */
8596 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
8603 /* If constant, low-order 16 bits of constant, unsigned.
8604 Otherwise, write normally. */
8606 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
8608 print_operand (file, x, 0);
8612 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
8613 for 64-bit mask direction. */
8614 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
8617 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
8621 /* X is a CR register. Print the number of the EQ bit of the CR */
8622 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8623 output_operand_lossage ("invalid %%E value");
8625 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
8629 /* X is a CR register. Print the shift count needed to move it
8630 to the high-order four bits. */
8631 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8632 output_operand_lossage ("invalid %%f value");
8634 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
8638 /* Similar, but print the count for the rotate in the opposite
8640 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8641 output_operand_lossage ("invalid %%F value");
8643 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
8647 /* X is a constant integer. If it is negative, print "m",
8648 otherwise print "z". This is to make an aze or ame insn. */
8649 if (GET_CODE (x) != CONST_INT)
8650 output_operand_lossage ("invalid %%G value");
8651 else if (INTVAL (x) >= 0)
8658 /* If constant, output low-order five bits. Otherwise, write
8661 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
8663 print_operand (file, x, 0);
8667 /* If constant, output low-order six bits. Otherwise, write
8670 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
8672 print_operand (file, x, 0);
8676 /* Print `i' if this is a constant, else nothing. */
8682 /* Write the bit number in CCR for jump. */
8685 output_operand_lossage ("invalid %%j code");
8687 fprintf (file, "%d", i);
8691 /* Similar, but add one for shift count in rlinm for scc and pass
8692 scc flag to `ccr_bit'. */
8695 output_operand_lossage ("invalid %%J code");
8697 /* If we want bit 31, write a shift count of zero, not 32. */
8698 fprintf (file, "%d", i == 31 ? 0 : i + 1);
8702 /* X must be a constant. Write the 1's complement of the
8705 output_operand_lossage ("invalid %%k value");
8707 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
8711 /* X must be a symbolic constant on ELF. Write an
8712 expression suitable for an 'addi' that adds in the low 16
8714 if (GET_CODE (x) != CONST)
8716 print_operand_address (file, x);
8721 if (GET_CODE (XEXP (x, 0)) != PLUS
8722 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
8723 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
8724 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
8725 output_operand_lossage ("invalid %%K value");
8726 print_operand_address (file, XEXP (XEXP (x, 0), 0));
8728 /* For GNU as, there must be a non-alphanumeric character
8729 between 'l' and the number. The '-' is added by
8730 print_operand() already. */
8731 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
8733 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
8737 /* %l is output_asm_label. */
8740 /* Write second word of DImode or DFmode reference. Works on register
8741 or non-indexed memory only. */
8742 if (GET_CODE (x) == REG)
8743 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
8744 else if (GET_CODE (x) == MEM)
8746 /* Handle possible auto-increment. Since it is pre-increment and
8747 we have already done it, we can just use an offset of word. */
8748 if (GET_CODE (XEXP (x, 0)) == PRE_INC
8749 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
8750 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
8753 output_address (XEXP (adjust_address_nv (x, SImode,
8757 if (small_data_operand (x, GET_MODE (x)))
8758 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
8759 reg_names[SMALL_DATA_REG]);
8764 /* MB value for a mask operand. */
8765 if (! mask_operand (x, SImode))
8766 output_operand_lossage ("invalid %%m value");
8768 fprintf (file, "%d", extract_MB (x));
8772 /* ME value for a mask operand. */
8773 if (! mask_operand (x, SImode))
8774 output_operand_lossage ("invalid %%M value");
8776 fprintf (file, "%d", extract_ME (x));
8779 /* %n outputs the negative of its operand. */
8782 /* Write the number of elements in the vector times 4. */
8783 if (GET_CODE (x) != PARALLEL)
8784 output_operand_lossage ("invalid %%N value");
8786 fprintf (file, "%d", XVECLEN (x, 0) * 4);
8790 /* Similar, but subtract 1 first. */
8791 if (GET_CODE (x) != PARALLEL)
8792 output_operand_lossage ("invalid %%O value");
8794 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
8798 /* X is a CONST_INT that is a power of two. Output the logarithm. */
8800 || INT_LOWPART (x) < 0
8801 || (i = exact_log2 (INT_LOWPART (x))) < 0)
8802 output_operand_lossage ("invalid %%p value");
8804 fprintf (file, "%d", i);
8808 /* The operand must be an indirect memory reference. The result
8809 is the register number. */
8810 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
8811 || REGNO (XEXP (x, 0)) >= 32)
8812 output_operand_lossage ("invalid %%P value");
8814 fprintf (file, "%d", REGNO (XEXP (x, 0)));
8818 /* This outputs the logical code corresponding to a boolean
8819 expression. The expression may have one or both operands
8820 negated (if one, only the first one). For condition register
8821 logical operations, it will also treat the negated
8822 CR codes as NOTs, but not handle NOTs of them. */
8824 const char *const *t = 0;
8826 enum rtx_code code = GET_CODE (x);
8827 static const char * const tbl[3][3] = {
8828 { "and", "andc", "nor" },
8829 { "or", "orc", "nand" },
8830 { "xor", "eqv", "xor" } };
8834 else if (code == IOR)
8836 else if (code == XOR)
8839 output_operand_lossage ("invalid %%q value");
8841 if (GET_CODE (XEXP (x, 0)) != NOT)
8845 if (GET_CODE (XEXP (x, 1)) == NOT)
8863 /* X is a CR register. Print the mask for `mtcrf'. */
8864 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8865 output_operand_lossage ("invalid %%R value");
8867 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
8871 /* Low 5 bits of 32 - value */
8873 output_operand_lossage ("invalid %%s value");
8875 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
8879 /* PowerPC64 mask position. All 0's is excluded.
8880 CONST_INT 32-bit mask is considered sign-extended so any
8881 transition must occur within the CONST_INT, not on the boundary. */
8882 if (! mask64_operand (x, DImode))
8883 output_operand_lossage ("invalid %%S value");
8885 uval = INT_LOWPART (x);
8887 if (uval & 1) /* Clear Left */
8889 #if HOST_BITS_PER_WIDE_INT > 64
8890 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
8894 else /* Clear Right */
8897 #if HOST_BITS_PER_WIDE_INT > 64
8898 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
8906 fprintf (file, "%d", i);
8910 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
8911 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
8914 /* Bit 3 is OV bit. */
8915 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
8917 /* If we want bit 31, write a shift count of zero, not 32. */
8918 fprintf (file, "%d", i == 31 ? 0 : i + 1);
8922 /* Print the symbolic name of a branch target register. */
8923 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
8924 && REGNO (x) != COUNT_REGISTER_REGNUM))
8925 output_operand_lossage ("invalid %%T value");
8926 else if (REGNO (x) == LINK_REGISTER_REGNUM)
8927 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
8929 fputs ("ctr", file);
8933 /* High-order 16 bits of constant for use in unsigned operand. */
8935 output_operand_lossage ("invalid %%u value");
8937 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
8938 (INT_LOWPART (x) >> 16) & 0xffff);
8942 /* High-order 16 bits of constant for use in signed operand. */
8944 output_operand_lossage ("invalid %%v value");
8946 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
8947 (INT_LOWPART (x) >> 16) & 0xffff);
8951 /* Print `u' if this has an auto-increment or auto-decrement. */
8952 if (GET_CODE (x) == MEM
8953 && (GET_CODE (XEXP (x, 0)) == PRE_INC
8954 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
8959 /* Print the trap code for this operand. */
8960 switch (GET_CODE (x))
8963 fputs ("eq", file); /* 4 */
8966 fputs ("ne", file); /* 24 */
8969 fputs ("lt", file); /* 16 */
8972 fputs ("le", file); /* 20 */
8975 fputs ("gt", file); /* 8 */
8978 fputs ("ge", file); /* 12 */
8981 fputs ("llt", file); /* 2 */
8984 fputs ("lle", file); /* 6 */
8987 fputs ("lgt", file); /* 1 */
8990 fputs ("lge", file); /* 5 */
8998 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
9001 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
9002 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9004 print_operand (file, x, 0);
9008 /* MB value for a PowerPC64 rldic operand. */
9009 val = (GET_CODE (x) == CONST_INT
9010 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9015 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9016 if ((val <<= 1) < 0)
9019 #if HOST_BITS_PER_WIDE_INT == 32
9020 if (GET_CODE (x) == CONST_INT && i >= 0)
9021 i += 32; /* zero-extend high-part was all 0's */
9022 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9024 val = CONST_DOUBLE_LOW (x);
9031 for ( ; i < 64; i++)
9032 if ((val <<= 1) < 0)
9037 fprintf (file, "%d", i + 1);
9041 if (GET_CODE (x) == MEM
9042 && legitimate_indexed_address_p (XEXP (x, 0), 0))
9047 /* Like 'L', for third word of TImode */
9048 if (GET_CODE (x) == REG)
9049 fprintf (file, "%s", reg_names[REGNO (x) + 2]);
9050 else if (GET_CODE (x) == MEM)
9052 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9053 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9054 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9056 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
9057 if (small_data_operand (x, GET_MODE (x)))
9058 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9059 reg_names[SMALL_DATA_REG]);
9064 /* X is a SYMBOL_REF. Write out the name preceded by a
9065 period and without any trailing data in brackets. Used for function
9066 names. If we are configured for System V (or the embedded ABI) on
9067 the PowerPC, do not emit the period, since those systems do not use
9068 TOCs and the like. */
9069 if (GET_CODE (x) != SYMBOL_REF)
9072 if (XSTR (x, 0)[0] != '.')
9074 switch (DEFAULT_ABI)
9089 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
9091 assemble_name (file, XSTR (x, 0));
9095 /* Like 'L', for last word of TImode. */
9096 if (GET_CODE (x) == REG)
9097 fprintf (file, "%s", reg_names[REGNO (x) + 3]);
9098 else if (GET_CODE (x) == MEM)
9100 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9101 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9102 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9104 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
9105 if (small_data_operand (x, GET_MODE (x)))
9106 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9107 reg_names[SMALL_DATA_REG]);
9111 /* Print AltiVec or SPE memory operand. */
9116 if (GET_CODE (x) != MEM)
9124 if (GET_CODE (tmp) == REG)
9126 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9129 /* Handle [reg+UIMM]. */
9130 else if (GET_CODE (tmp) == PLUS &&
9131 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9135 if (GET_CODE (XEXP (tmp, 0)) != REG)
9138 x = INTVAL (XEXP (tmp, 1));
9139 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9143 /* Fall through. Must be [reg+reg]. */
9145 if (GET_CODE (tmp) == REG)
9146 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
9147 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9149 if (REGNO (XEXP (tmp, 0)) == 0)
9150 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9151 reg_names[ REGNO (XEXP (tmp, 0)) ]);
9153 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9154 reg_names[ REGNO (XEXP (tmp, 1)) ]);
9162 if (GET_CODE (x) == REG)
9163 fprintf (file, "%s", reg_names[REGNO (x)]);
9164 else if (GET_CODE (x) == MEM)
9166 /* We need to handle PRE_INC and PRE_DEC here, since we need to
9167 know the width from the mode. */
9168 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
9169 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9170 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9171 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
9172 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9173 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9175 output_address (XEXP (x, 0));
9178 output_addr_const (file, x);
9182 assemble_name (file, rs6000_get_some_local_dynamic_name ());
9186 output_operand_lossage ("invalid %%xn code");
9190 /* Print the address of an operand. */
9193 print_operand_address (FILE *file, rtx x)
9195 if (GET_CODE (x) == REG)
9196 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9197 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9198 || GET_CODE (x) == LABEL_REF)
9200 output_addr_const (file, x);
9201 if (small_data_operand (x, GET_MODE (x)))
9202 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9203 reg_names[SMALL_DATA_REG]);
9204 else if (TARGET_TOC)
9207 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9209 if (REGNO (XEXP (x, 0)) == 0)
9210 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9211 reg_names[ REGNO (XEXP (x, 0)) ]);
9213 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9214 reg_names[ REGNO (XEXP (x, 1)) ]);
9216 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
9217 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9218 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
9220 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9221 && CONSTANT_P (XEXP (x, 1)))
9223 output_addr_const (file, XEXP (x, 1));
9224 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9228 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9229 && CONSTANT_P (XEXP (x, 1)))
9231 fprintf (file, "lo16(");
9232 output_addr_const (file, XEXP (x, 1));
9233 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9236 else if (legitimate_constant_pool_address_p (x))
9238 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9240 rtx contains_minus = XEXP (x, 1);
9244 /* Find the (minus (sym) (toc)) buried in X, and temporarily
9245 turn it into (sym) for output_addr_const. */
9246 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9247 contains_minus = XEXP (contains_minus, 0);
9249 minus = XEXP (contains_minus, 0);
9250 symref = XEXP (minus, 0);
9251 XEXP (contains_minus, 0) = symref;
9256 name = XSTR (symref, 0);
9257 newname = alloca (strlen (name) + sizeof ("@toc"));
9258 strcpy (newname, name);
9259 strcat (newname, "@toc");
9260 XSTR (symref, 0) = newname;
9262 output_addr_const (file, XEXP (x, 1));
9264 XSTR (symref, 0) = name;
9265 XEXP (contains_minus, 0) = minus;
9268 output_addr_const (file, XEXP (x, 1));
9270 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9276 /* Target hook for assembling integer objects. The PowerPC version has
9277 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9278 is defined. It also needs to handle DI-mode objects on 64-bit
9282 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
9284 #ifdef RELOCATABLE_NEEDS_FIXUP
9285 /* Special handling for SI values. */
9286 if (size == 4 && aligned_p)
9288 extern int in_toc_section (void);
9289 static int recurse = 0;
9291 /* For -mrelocatable, we mark all addresses that need to be fixed up
9292 in the .fixup section. */
9293 if (TARGET_RELOCATABLE
9294 && !in_toc_section ()
9295 && !in_text_section ()
9297 && GET_CODE (x) != CONST_INT
9298 && GET_CODE (x) != CONST_DOUBLE
9304 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9306 ASM_OUTPUT_LABEL (asm_out_file, buf);
9307 fprintf (asm_out_file, "\t.long\t(");
9308 output_addr_const (asm_out_file, x);
9309 fprintf (asm_out_file, ")@fixup\n");
9310 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9311 ASM_OUTPUT_ALIGN (asm_out_file, 2);
9312 fprintf (asm_out_file, "\t.long\t");
9313 assemble_name (asm_out_file, buf);
9314 fprintf (asm_out_file, "\n\t.previous\n");
9318 /* Remove initial .'s to turn a -mcall-aixdesc function
9319 address into the address of the descriptor, not the function
9321 else if (GET_CODE (x) == SYMBOL_REF
9322 && XSTR (x, 0)[0] == '.'
9323 && DEFAULT_ABI == ABI_AIX)
9325 const char *name = XSTR (x, 0);
9326 while (*name == '.')
9329 fprintf (asm_out_file, "\t.long\t%s\n", name);
9333 #endif /* RELOCATABLE_NEEDS_FIXUP */
9334 return default_assemble_integer (x, size, aligned_p);
9337 #ifdef HAVE_GAS_HIDDEN
9338 /* Emit an assembler directive to set symbol visibility for DECL to
9342 rs6000_assemble_visibility (tree decl, int vis)
9344 /* Functions need to have their entry point symbol visibility set as
9345 well as their descriptor symbol visibility. */
9346 if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL)
9348 static const char * const visibility_types[] = {
9349 NULL, "internal", "hidden", "protected"
9352 const char *name, *type;
9354 name = ((* targetm.strip_name_encoding)
9355 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
9356 type = visibility_types[vis];
9358 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9359 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
9362 default_assemble_visibility (decl, vis);
9367 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
9369 /* Reversal of FP compares takes care -- an ordered compare
9370 becomes an unordered compare and vice versa. */
9371 if (mode == CCFPmode
9372 && (!flag_finite_math_only
9373 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
9374 || code == UNEQ || code == LTGT))
9375 return reverse_condition_maybe_unordered (code);
9377 return reverse_condition (code);
9380 /* Generate a compare for CODE. Return a brand-new rtx that
9381 represents the result of the compare. */
9384 rs6000_generate_compare (enum rtx_code code)
9386 enum machine_mode comp_mode;
9389 if (rs6000_compare_fp_p)
9390 comp_mode = CCFPmode;
9391 else if (code == GTU || code == LTU
9392 || code == GEU || code == LEU)
9393 comp_mode = CCUNSmode;
9397 /* First, the compare. */
9398 compare_result = gen_reg_rtx (comp_mode);
9400 /* SPE FP compare instructions on the GPRs. Yuck! */
9401 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
9402 && rs6000_compare_fp_p)
9404 rtx cmp, or1, or2, or_result, compare_result2;
9412 cmp = flag_finite_math_only
9413 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
9415 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
9416 rs6000_compare_op1);
9424 cmp = flag_finite_math_only
9425 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
9427 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
9428 rs6000_compare_op1);
9436 cmp = flag_finite_math_only
9437 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
9439 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
9440 rs6000_compare_op1);
9446 /* Synthesize LE and GE from LT/GT || EQ. */
9447 if (code == LE || code == GE || code == LEU || code == GEU)
9449 /* Synthesize GE/LE frome GT/LT || EQ. */
9455 case LE: code = LT; break;
9456 case GE: code = GT; break;
9457 case LEU: code = LT; break;
9458 case GEU: code = GT; break;
9462 or1 = gen_reg_rtx (SImode);
9463 or2 = gen_reg_rtx (SImode);
9464 or_result = gen_reg_rtx (CCEQmode);
9465 compare_result2 = gen_reg_rtx (CCFPmode);
9468 cmp = flag_finite_math_only
9469 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
9471 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
9472 rs6000_compare_op1);
9475 /* The MC8540 FP compare instructions set the CR bits
9476 differently than other PPC compare instructions. For
9477 that matter, there is no generic test instruction, but a
9478 testgt, testlt, and testeq. For a true condition, bit 2
9479 is set (x1xx) in the CR. Following the traditional CR
9485 ... bit 2 would be a GT CR alias, so later on we
9486 look in the GT bits for the branch instructions.
9487 However, we must be careful to emit correct RTL in
9488 the meantime, so optimizations don't get confused. */
9490 or1 = gen_rtx (NE, SImode, compare_result, const0_rtx);
9491 or2 = gen_rtx (NE, SImode, compare_result2, const0_rtx);
9493 /* OR them together. */
9494 cmp = gen_rtx_SET (VOIDmode, or_result,
9495 gen_rtx_COMPARE (CCEQmode,
9496 gen_rtx_IOR (SImode, or1, or2),
9498 compare_result = or_result;
9503 /* We only care about 1 bit (x1xx), so map everything to NE to
9504 maintain rtl sanity. We'll get to the right bit (x1xx) at
9505 code output time. */
9506 if (code == NE || code == LTGT)
9507 /* Do the inverse here because we have no cmpne
9508 instruction. We use the cmpeq instruction and expect
9509 to get a 0 instead. */
9518 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
9519 gen_rtx_COMPARE (comp_mode,
9521 rs6000_compare_op1)));
9523 /* Some kinds of FP comparisons need an OR operation;
9524 under flag_finite_math_only we don't bother. */
9525 if (rs6000_compare_fp_p
9526 && ! flag_finite_math_only
9527 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
9528 && (code == LE || code == GE
9529 || code == UNEQ || code == LTGT
9530 || code == UNGT || code == UNLT))
9532 enum rtx_code or1, or2;
9533 rtx or1_rtx, or2_rtx, compare2_rtx;
9534 rtx or_result = gen_reg_rtx (CCEQmode);
9538 case LE: or1 = LT; or2 = EQ; break;
9539 case GE: or1 = GT; or2 = EQ; break;
9540 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
9541 case LTGT: or1 = LT; or2 = GT; break;
9542 case UNGT: or1 = UNORDERED; or2 = GT; break;
9543 case UNLT: or1 = UNORDERED; or2 = LT; break;
9546 validate_condition_mode (or1, comp_mode);
9547 validate_condition_mode (or2, comp_mode);
9548 or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx);
9549 or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx);
9550 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
9551 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
9553 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
9555 compare_result = or_result;
9559 validate_condition_mode (code, GET_MODE (compare_result));
9561 return gen_rtx (code, VOIDmode, compare_result, const0_rtx);
9565 /* Emit the RTL for an sCOND pattern. */
9568 rs6000_emit_sCOND (enum rtx_code code, rtx result)
9571 enum machine_mode op_mode;
9572 enum rtx_code cond_code;
9574 condition_rtx = rs6000_generate_compare (code);
9575 cond_code = GET_CODE (condition_rtx);
9578 || cond_code == GE || cond_code == LE
9579 || cond_code == GEU || cond_code == LEU
9580 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
9582 rtx not_result = gen_reg_rtx (CCEQmode);
9583 rtx not_op, rev_cond_rtx;
9584 enum machine_mode cc_mode;
9586 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
9588 rev_cond_rtx = gen_rtx (rs6000_reverse_condition (cc_mode, cond_code),
9589 SImode, XEXP (condition_rtx, 0), const0_rtx);
9590 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
9591 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
9592 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
9595 op_mode = GET_MODE (rs6000_compare_op0);
9596 if (op_mode == VOIDmode)
9597 op_mode = GET_MODE (rs6000_compare_op1);
9599 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
9601 PUT_MODE (condition_rtx, DImode);
9602 convert_move (result, condition_rtx, 0);
9606 PUT_MODE (condition_rtx, SImode);
9607 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
9611 /* Emit a branch of kind CODE to location LOC. */
9614 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
9616 rtx condition_rtx, loc_ref;
9618 condition_rtx = rs6000_generate_compare (code);
9619 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
9620 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
9621 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
9625 /* Return the string to output a conditional branch to LABEL, which is
9626 the operand number of the label, or -1 if the branch is really a
9629 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
9630 condition code register and its mode specifies what kind of
9633 REVERSED is nonzero if we should reverse the sense of the comparison.
9635 INSN is the insn. */
9638 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
9640 static char string[64];
9641 enum rtx_code code = GET_CODE (op);
9642 rtx cc_reg = XEXP (op, 0);
9643 enum machine_mode mode = GET_MODE (cc_reg);
9644 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
9645 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
9646 int really_reversed = reversed ^ need_longbranch;
9652 validate_condition_mode (code, mode);
9654 /* Work out which way this really branches. We could use
9655 reverse_condition_maybe_unordered here always but this
9656 makes the resulting assembler clearer. */
9657 if (really_reversed)
9659 /* Reversal of FP compares takes care -- an ordered compare
9660 becomes an unordered compare and vice versa. */
9661 if (mode == CCFPmode)
9662 code = reverse_condition_maybe_unordered (code);
9664 code = reverse_condition (code);
9667 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
9669 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
9672 /* Opposite of GT. */
9674 else if (code == NE)
9682 /* Not all of these are actually distinct opcodes, but
9683 we distinguish them for clarity of the resulting assembler. */
9685 ccode = "ne"; break;
9687 ccode = "eq"; break;
9689 ccode = "ge"; break;
9690 case GT: case GTU: case UNGT:
9691 ccode = "gt"; break;
9693 ccode = "le"; break;
9694 case LT: case LTU: case UNLT:
9695 ccode = "lt"; break;
9696 case UNORDERED: ccode = "un"; break;
9697 case ORDERED: ccode = "nu"; break;
9698 case UNGE: ccode = "nl"; break;
9699 case UNLE: ccode = "ng"; break;
9704 /* Maybe we have a guess as to how likely the branch is.
9705 The old mnemonics don't have a way to specify this information. */
9707 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
9708 if (note != NULL_RTX)
9710 /* PROB is the difference from 50%. */
9711 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
9712 bool always_hint = rs6000_cpu != PROCESSOR_POWER4;
9714 /* Only hint for highly probable/improbable branches on newer
9715 cpus as static prediction overrides processor dynamic
9716 prediction. For older cpus we may as well always hint, but
9717 assume not taken for branches that are very close to 50% as a
9718 mispredicted taken branch is more expensive than a
9719 mispredicted not-taken branch. */
9721 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
9723 if (abs (prob) > REG_BR_PROB_BASE / 20
9724 && ((prob > 0) ^ need_longbranch))
9732 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
9734 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
9736 /* We need to escape any '%' characters in the reg_names string.
9737 Assume they'd only be the first character... */
9738 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
9740 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
9744 /* If the branch distance was too far, we may have to use an
9745 unconditional branch to go the distance. */
9746 if (need_longbranch)
9747 s += sprintf (s, ",$+8\n\tb %s", label);
9749 s += sprintf (s, ",%s", label);
9755 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
9756 operands of the last comparison is nonzero/true, FALSE_COND if it
9757 is zero/false. Return 0 if the hardware has no such operation. */
9760 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
9762 enum rtx_code code = GET_CODE (op);
9763 rtx op0 = rs6000_compare_op0;
9764 rtx op1 = rs6000_compare_op1;
9766 enum machine_mode compare_mode = GET_MODE (op0);
9767 enum machine_mode result_mode = GET_MODE (dest);
9770 /* These modes should always match. */
9771 if (GET_MODE (op1) != compare_mode
9772 /* In the isel case however, we can use a compare immediate, so
9773 op1 may be a small constant. */
9774 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
9776 if (GET_MODE (true_cond) != result_mode)
9778 if (GET_MODE (false_cond) != result_mode)
9781 /* First, work out if the hardware can do this at all, or
9782 if it's too slow... */
9783 if (! rs6000_compare_fp_p)
9786 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
9790 /* Eliminate half of the comparisons by switching operands, this
9791 makes the remaining code simpler. */
9792 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
9793 || code == LTGT || code == LT || code == UNLE)
9795 code = reverse_condition_maybe_unordered (code);
9797 true_cond = false_cond;
9801 /* UNEQ and LTGT take four instructions for a comparison with zero,
9802 it'll probably be faster to use a branch here too. */
9803 if (code == UNEQ && HONOR_NANS (compare_mode))
9806 if (GET_CODE (op1) == CONST_DOUBLE)
9807 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
9809 /* We're going to try to implement comparisons by performing
9810 a subtract, then comparing against zero. Unfortunately,
9811 Inf - Inf is NaN which is not zero, and so if we don't
9812 know that the operand is finite and the comparison
9813 would treat EQ different to UNORDERED, we can't do it. */
9814 if (HONOR_INFINITIES (compare_mode)
9815 && code != GT && code != UNGE
9816 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
9817 /* Constructs of the form (a OP b ? a : b) are safe. */
9818 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
9819 || (! rtx_equal_p (op0, true_cond)
9820 && ! rtx_equal_p (op1, true_cond))))
9822 /* At this point we know we can use fsel. */
9824 /* Reduce the comparison to a comparison against zero. */
9825 temp = gen_reg_rtx (compare_mode);
9826 emit_insn (gen_rtx_SET (VOIDmode, temp,
9827 gen_rtx_MINUS (compare_mode, op0, op1)));
9829 op1 = CONST0_RTX (compare_mode);
9831 /* If we don't care about NaNs we can reduce some of the comparisons
9832 down to faster ones. */
9833 if (! HONOR_NANS (compare_mode))
9839 true_cond = false_cond;
9852 /* Now, reduce everything down to a GE. */
9859 temp = gen_reg_rtx (compare_mode);
9860 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
9865 temp = gen_reg_rtx (compare_mode);
9866 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
9871 temp = gen_reg_rtx (compare_mode);
9872 emit_insn (gen_rtx_SET (VOIDmode, temp,
9873 gen_rtx_NEG (compare_mode,
9874 gen_rtx_ABS (compare_mode, op0))));
9879 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
9880 temp = gen_reg_rtx (result_mode);
9881 emit_insn (gen_rtx_SET (VOIDmode, temp,
9882 gen_rtx_IF_THEN_ELSE (result_mode,
9883 gen_rtx_GE (VOIDmode,
9885 true_cond, false_cond)));
9886 false_cond = true_cond;
9889 temp = gen_reg_rtx (compare_mode);
9890 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
9895 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
9896 temp = gen_reg_rtx (result_mode);
9897 emit_insn (gen_rtx_SET (VOIDmode, temp,
9898 gen_rtx_IF_THEN_ELSE (result_mode,
9899 gen_rtx_GE (VOIDmode,
9901 true_cond, false_cond)));
9902 true_cond = false_cond;
9905 temp = gen_reg_rtx (compare_mode);
9906 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
9914 emit_insn (gen_rtx_SET (VOIDmode, dest,
9915 gen_rtx_IF_THEN_ELSE (result_mode,
9916 gen_rtx_GE (VOIDmode,
9918 true_cond, false_cond)));
9922 /* Same as above, but for ints (isel). */
9925 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
9927 rtx condition_rtx, cr;
9929 /* All isel implementations thus far are 32-bits. */
9930 if (GET_MODE (rs6000_compare_op0) != SImode)
9933 /* We still have to do the compare, because isel doesn't do a
9934 compare, it just looks at the CRx bits set by a previous compare
9936 condition_rtx = rs6000_generate_compare (GET_CODE (op));
9937 cr = XEXP (condition_rtx, 0);
9939 if (GET_MODE (cr) == CCmode)
9940 emit_insn (gen_isel_signed (dest, condition_rtx,
9941 true_cond, false_cond, cr));
9943 emit_insn (gen_isel_unsigned (dest, condition_rtx,
9944 true_cond, false_cond, cr));
9950 output_isel (rtx *operands)
9954 code = GET_CODE (operands[1]);
9955 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
9957 PUT_CODE (operands[1], reverse_condition (code));
9958 return "isel %0,%3,%2,%j1";
9961 return "isel %0,%2,%3,%j1";
9965 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
9967 enum machine_mode mode = GET_MODE (op0);
9971 if (code == SMAX || code == SMIN)
9976 if (code == SMAX || code == UMAX)
9977 target = emit_conditional_move (dest, c, op0, op1, mode,
9980 target = emit_conditional_move (dest, c, op0, op1, mode,
9982 if (target == NULL_RTX)
9985 emit_move_insn (dest, target);
9988 /* Emit instructions to move SRC to DST. Called by splitters for
9989 multi-register moves. It will emit at most one instruction for
9990 each register that is accessed; that is, it won't emit li/lis pairs
9991 (or equivalent for 64-bit code). One of SRC or DST must be a hard
9995 rs6000_split_multireg_move (rtx dst, rtx src)
9997 /* The register number of the first register being moved. */
9999 /* The mode that is to be moved. */
10000 enum machine_mode mode;
10001 /* The mode that the move is being done in, and its size. */
10002 enum machine_mode reg_mode;
10004 /* The number of registers that will be moved. */
10007 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10008 mode = GET_MODE (dst);
10009 nregs = HARD_REGNO_NREGS (reg, mode);
10010 if (FP_REGNO_P (reg))
10012 else if (ALTIVEC_REGNO_P (reg))
10013 reg_mode = V16QImode;
10015 reg_mode = word_mode;
10016 reg_mode_size = GET_MODE_SIZE (reg_mode);
10018 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
10021 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
10023 /* Move register range backwards, if we might have destructive
10026 for (i = nregs - 1; i >= 0; i--)
10027 emit_insn (gen_rtx_SET (VOIDmode,
10028 simplify_gen_subreg (reg_mode, dst, mode,
10029 i * reg_mode_size),
10030 simplify_gen_subreg (reg_mode, src, mode,
10031 i * reg_mode_size)));
10037 bool used_update = false;
10039 if (GET_CODE (src) == MEM && INT_REGNO_P (reg))
10043 if (GET_CODE (XEXP (src, 0)) == PRE_INC
10044 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
10047 breg = XEXP (XEXP (src, 0), 0);
10048 delta_rtx = GET_CODE (XEXP (src, 0)) == PRE_INC
10049 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
10050 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)));
10051 emit_insn (TARGET_32BIT
10052 ? gen_addsi3 (breg, breg, delta_rtx)
10053 : gen_adddi3 (breg, breg, delta_rtx));
10054 src = gen_rtx_MEM (mode, breg);
10057 /* We have now address involving an base register only.
10058 If we use one of the registers to address memory,
10059 we have change that register last. */
10061 breg = (GET_CODE (XEXP (src, 0)) == PLUS
10062 ? XEXP (XEXP (src, 0), 0)
10068 if (REGNO (breg) >= REGNO (dst)
10069 && REGNO (breg) < REGNO (dst) + nregs)
10070 j = REGNO (breg) - REGNO (dst);
10073 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
10077 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
10078 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
10081 breg = XEXP (XEXP (dst, 0), 0);
10082 delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC
10083 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
10084 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)));
10086 /* We have to update the breg before doing the store.
10087 Use store with update, if available. */
10091 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
10092 emit_insn (TARGET_32BIT
10093 ? gen_movsi_update (breg, breg, delta_rtx, nsrc)
10094 : gen_movdi_update (breg, breg, delta_rtx, nsrc));
10095 used_update = true;
10098 emit_insn (TARGET_32BIT
10099 ? gen_addsi3 (breg, breg, delta_rtx)
10100 : gen_adddi3 (breg, breg, delta_rtx));
10101 dst = gen_rtx_MEM (mode, breg);
10105 for (i = 0; i < nregs; i++)
10107 /* Calculate index to next subword. */
10112 /* If compiler already emited move of first word by
10113 store with update, no need to do anything. */
10114 if (j == 0 && used_update)
10117 emit_insn (gen_rtx_SET (VOIDmode,
10118 simplify_gen_subreg (reg_mode, dst, mode,
10119 j * reg_mode_size),
10120 simplify_gen_subreg (reg_mode, src, mode,
10121 j * reg_mode_size)));
10127 /* This page contains routines that are used to determine what the
10128 function prologue and epilogue code will do and write them out. */
10130 /* Return the first fixed-point register that is required to be
10131 saved. 32 if none. */
10134 first_reg_to_save (void)
10138 /* Find lowest numbered live register. */
10139 for (first_reg = 13; first_reg <= 31; first_reg++)
10140 if (regs_ever_live[first_reg]
10141 && (! call_used_regs[first_reg]
10142 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
10143 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
10144 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))))
10149 && current_function_uses_pic_offset_table
10150 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
10151 return RS6000_PIC_OFFSET_TABLE_REGNUM;
10157 /* Similar, for FP regs. */
10160 first_fp_reg_to_save (void)
10164 /* Find lowest numbered live register. */
10165 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
10166 if (regs_ever_live[first_reg])
10172 /* Similar, for AltiVec regs. */
10175 first_altivec_reg_to_save (void)
10179 /* Stack frame remains as is unless we are in AltiVec ABI. */
10180 if (! TARGET_ALTIVEC_ABI)
10181 return LAST_ALTIVEC_REGNO + 1;
10183 /* Find lowest numbered live register. */
10184 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
10185 if (regs_ever_live[i])
10191 /* Return a 32-bit mask of the AltiVec registers we need to set in
10192 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
10193 the 32-bit word is 0. */
10195 static unsigned int
10196 compute_vrsave_mask (void)
10198 unsigned int i, mask = 0;
10200 /* First, find out if we use _any_ altivec registers. */
10201 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10202 if (regs_ever_live[i])
10203 mask |= ALTIVEC_REG_BIT (i);
10208 /* Next, remove the argument registers from the set. These must
10209 be in the VRSAVE mask set by the caller, so we don't need to add
10210 them in again. More importantly, the mask we compute here is
10211 used to generate CLOBBERs in the set_vrsave insn, and we do not
10212 wish the argument registers to die. */
10213 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
10214 mask &= ~ALTIVEC_REG_BIT (i);
10216 /* Similarly, remove the return value from the set. */
10219 diddle_return_value (is_altivec_return_reg, &yes);
10221 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
10228 is_altivec_return_reg (rtx reg, void *xyes)
10230 bool *yes = (bool *) xyes;
10231 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
10236 /* Calculate the stack information for the current function. This is
10237 complicated by having two separate calling sequences, the AIX calling
10238 sequence and the V.4 calling sequence.
10240 AIX (and Darwin/Mac OS X) stack frames look like:
10242 SP----> +---------------------------------------+
10243 | back chain to caller | 0 0
10244 +---------------------------------------+
10245 | saved CR | 4 8 (8-11)
10246 +---------------------------------------+
10248 +---------------------------------------+
10249 | reserved for compilers | 12 24
10250 +---------------------------------------+
10251 | reserved for binders | 16 32
10252 +---------------------------------------+
10253 | saved TOC pointer | 20 40
10254 +---------------------------------------+
10255 | Parameter save area (P) | 24 48
10256 +---------------------------------------+
10257 | Alloca space (A) | 24+P etc.
10258 +---------------------------------------+
10259 | Local variable space (L) | 24+P+A
10260 +---------------------------------------+
10261 | Float/int conversion temporary (X) | 24+P+A+L
10262 +---------------------------------------+
10263 | Save area for AltiVec registers (W) | 24+P+A+L+X
10264 +---------------------------------------+
10265 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
10266 +---------------------------------------+
10267 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
10268 +---------------------------------------+
10269 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
10270 +---------------------------------------+
10271 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
10272 +---------------------------------------+
10273 old SP->| back chain to caller's caller |
10274 +---------------------------------------+
10276 The required alignment for AIX configurations is two words (i.e., 8
10280 V.4 stack frames look like:
10282 SP----> +---------------------------------------+
10283 | back chain to caller | 0
10284 +---------------------------------------+
10285 | caller's saved LR | 4
10286 +---------------------------------------+
10287 | Parameter save area (P) | 8
10288 +---------------------------------------+
10289 | Alloca space (A) | 8+P
10290 +---------------------------------------+
10291 | Varargs save area (V) | 8+P+A
10292 +---------------------------------------+
10293 | Local variable space (L) | 8+P+A+V
10294 +---------------------------------------+
10295 | Float/int conversion temporary (X) | 8+P+A+V+L
10296 +---------------------------------------+
10297 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
10298 +---------------------------------------+
10299 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
10300 +---------------------------------------+
10301 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
10302 +---------------------------------------+
10303 | SPE: area for 64-bit GP registers |
10304 +---------------------------------------+
10305 | SPE alignment padding |
10306 +---------------------------------------+
10307 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
10308 +---------------------------------------+
10309 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
10310 +---------------------------------------+
10311 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
10312 +---------------------------------------+
10313 old SP->| back chain to caller's caller |
10314 +---------------------------------------+
10316 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
10317 given. (But note below and in sysv4.h that we require only 8 and
10318 may round up the size of our stack frame anyways. The historical
10319 reason is early versions of powerpc-linux which didn't properly
10320 align the stack at program startup. A happy side-effect is that
10321 -mno-eabi libraries can be used with -meabi programs.)
10323 The EABI configuration defaults to the V.4 layout. However,
10324 the stack alignment requirements may differ. If -mno-eabi is not
10325 given, the required stack alignment is 8 bytes; if -mno-eabi is
10326 given, the required alignment is 16 bytes. (But see V.4 comment
10329 #ifndef ABI_STACK_BOUNDARY
10330 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
10333 static rs6000_stack_t *
10334 rs6000_stack_info (void)
10336 static rs6000_stack_t info, zero_info;
10337 rs6000_stack_t *info_ptr = &info;
10338 int reg_size = TARGET_POWERPC64 ? 8 : 4;
10340 HOST_WIDE_INT total_raw_size;
10342 /* Zero all fields portably. */
10347 /* Cache value so we don't rescan instruction chain over and over. */
10348 if (cfun->machine->insn_chain_scanned_p == 0)
10350 cfun->machine->insn_chain_scanned_p = 1;
10351 info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
10355 /* Select which calling sequence. */
10356 info_ptr->abi = DEFAULT_ABI;
10358 /* Calculate which registers need to be saved & save area size. */
10359 info_ptr->first_gp_reg_save = first_reg_to_save ();
10360 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
10361 even if it currently looks like we won't. */
10362 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
10363 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
10364 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
10365 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
10366 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
10368 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
10370 /* For the SPE, we have an additional upper 32-bits on each GPR.
10371 Ideally we should save the entire 64-bits only when the upper
10372 half is used in SIMD instructions. Since we only record
10373 registers live (not the size they are used in), this proves
10374 difficult because we'd have to traverse the instruction chain at
10375 the right time, taking reload into account. This is a real pain,
10376 so we opt to save the GPRs in 64-bits always if but one register
10377 gets used in 64-bits. Otherwise, all the registers in the frame
10378 get saved in 32-bits.
10380 So... since when we save all GPRs (except the SP) in 64-bits, the
10381 traditional GP save area will be empty. */
10382 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10383 info_ptr->gp_size = 0;
10385 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
10386 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
10388 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
10389 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
10390 - info_ptr->first_altivec_reg_save);
10392 /* Does this function call anything? */
10393 info_ptr->calls_p = (! current_function_is_leaf
10394 || cfun->machine->ra_needs_full_frame);
10396 /* Determine if we need to save the link register. */
10397 if (rs6000_ra_ever_killed ()
10398 || (DEFAULT_ABI == ABI_AIX
10399 && current_function_profile
10400 && !TARGET_PROFILE_KERNEL)
10401 #ifdef TARGET_RELOCATABLE
10402 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
10404 || (info_ptr->first_fp_reg_save != 64
10405 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
10406 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
10407 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
10408 || (DEFAULT_ABI == ABI_DARWIN
10410 && current_function_uses_pic_offset_table)
10411 || info_ptr->calls_p)
10413 info_ptr->lr_save_p = 1;
10414 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
10417 /* Determine if we need to save the condition code registers. */
10418 if (regs_ever_live[CR2_REGNO]
10419 || regs_ever_live[CR3_REGNO]
10420 || regs_ever_live[CR4_REGNO])
10422 info_ptr->cr_save_p = 1;
10423 if (DEFAULT_ABI == ABI_V4)
10424 info_ptr->cr_size = reg_size;
10427 /* If the current function calls __builtin_eh_return, then we need
10428 to allocate stack space for registers that will hold data for
10429 the exception handler. */
10430 if (current_function_calls_eh_return)
10433 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
10436 /* SPE saves EH registers in 64-bits. */
10437 ehrd_size = i * (TARGET_SPE_ABI
10438 && info_ptr->spe_64bit_regs_used != 0
10439 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
10444 /* Determine various sizes. */
10445 info_ptr->reg_size = reg_size;
10446 info_ptr->fixed_size = RS6000_SAVE_AREA;
10447 info_ptr->varargs_size = RS6000_VARARGS_AREA;
10448 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
10449 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
10452 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10453 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
10455 info_ptr->spe_gp_size = 0;
10457 if (TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE)
10459 info_ptr->vrsave_mask = compute_vrsave_mask ();
10460 info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0;
10464 info_ptr->vrsave_mask = 0;
10465 info_ptr->vrsave_size = 0;
10468 /* Calculate the offsets. */
10469 switch (DEFAULT_ABI)
10477 info_ptr->fp_save_offset = - info_ptr->fp_size;
10478 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
10480 if (TARGET_ALTIVEC_ABI)
10482 info_ptr->vrsave_save_offset
10483 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
10485 /* Align stack so vector save area is on a quadword boundary. */
10486 if (info_ptr->altivec_size != 0)
10487 info_ptr->altivec_padding_size
10488 = 16 - (-info_ptr->vrsave_save_offset % 16);
10490 info_ptr->altivec_padding_size = 0;
10492 info_ptr->altivec_save_offset
10493 = info_ptr->vrsave_save_offset
10494 - info_ptr->altivec_padding_size
10495 - info_ptr->altivec_size;
10497 /* Adjust for AltiVec case. */
10498 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
10501 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
10502 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
10503 info_ptr->lr_save_offset = 2*reg_size;
10507 info_ptr->fp_save_offset = - info_ptr->fp_size;
10508 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
10509 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
10511 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10513 /* Align stack so SPE GPR save area is aligned on a
10514 double-word boundary. */
10515 if (info_ptr->spe_gp_size != 0)
10516 info_ptr->spe_padding_size
10517 = 8 - (-info_ptr->cr_save_offset % 8);
10519 info_ptr->spe_padding_size = 0;
10521 info_ptr->spe_gp_save_offset
10522 = info_ptr->cr_save_offset
10523 - info_ptr->spe_padding_size
10524 - info_ptr->spe_gp_size;
10526 /* Adjust for SPE case. */
10527 info_ptr->toc_save_offset
10528 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
10530 else if (TARGET_ALTIVEC_ABI)
10532 info_ptr->vrsave_save_offset
10533 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
10535 /* Align stack so vector save area is on a quadword boundary. */
10536 if (info_ptr->altivec_size != 0)
10537 info_ptr->altivec_padding_size
10538 = 16 - (-info_ptr->vrsave_save_offset % 16);
10540 info_ptr->altivec_padding_size = 0;
10542 info_ptr->altivec_save_offset
10543 = info_ptr->vrsave_save_offset
10544 - info_ptr->altivec_padding_size
10545 - info_ptr->altivec_size;
10547 /* Adjust for AltiVec case. */
10548 info_ptr->toc_save_offset
10549 = info_ptr->altivec_save_offset - info_ptr->toc_size;
10552 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
10553 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
10554 info_ptr->lr_save_offset = reg_size;
10558 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
10559 + info_ptr->gp_size
10560 + info_ptr->altivec_size
10561 + info_ptr->altivec_padding_size
10562 + info_ptr->spe_gp_size
10563 + info_ptr->spe_padding_size
10565 + info_ptr->cr_size
10566 + info_ptr->lr_size
10567 + info_ptr->vrsave_size
10568 + info_ptr->toc_size,
10569 (TARGET_ALTIVEC_ABI || ABI_DARWIN)
10572 total_raw_size = (info_ptr->vars_size
10573 + info_ptr->parm_size
10574 + info_ptr->save_size
10575 + info_ptr->varargs_size
10576 + info_ptr->fixed_size);
10578 info_ptr->total_size =
10579 RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT);
10581 /* Determine if we need to allocate any stack frame:
10583 For AIX we need to push the stack if a frame pointer is needed
10584 (because the stack might be dynamically adjusted), if we are
10585 debugging, if we make calls, or if the sum of fp_save, gp_save,
10586 and local variables are more than the space needed to save all
10587 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
10588 + 18*8 = 288 (GPR13 reserved).
10590 For V.4 we don't have the stack cushion that AIX uses, but assume
10591 that the debugger can handle stackless frames. */
10593 if (info_ptr->calls_p)
10594 info_ptr->push_p = 1;
10596 else if (DEFAULT_ABI == ABI_V4)
10597 info_ptr->push_p = total_raw_size > info_ptr->fixed_size;
10599 else if (frame_pointer_needed)
10600 info_ptr->push_p = 1;
10602 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
10603 info_ptr->push_p = 1;
10607 = total_raw_size - info_ptr->fixed_size > (TARGET_32BIT ? 220 : 288);
10609 /* Zero offsets if we're not saving those registers. */
10610 if (info_ptr->fp_size == 0)
10611 info_ptr->fp_save_offset = 0;
10613 if (info_ptr->gp_size == 0)
10614 info_ptr->gp_save_offset = 0;
10616 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
10617 info_ptr->altivec_save_offset = 0;
10619 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
10620 info_ptr->vrsave_save_offset = 0;
10622 if (! TARGET_SPE_ABI
10623 || info_ptr->spe_64bit_regs_used == 0
10624 || info_ptr->spe_gp_size == 0)
10625 info_ptr->spe_gp_save_offset = 0;
10627 if (! info_ptr->lr_save_p)
10628 info_ptr->lr_save_offset = 0;
10630 if (! info_ptr->cr_save_p)
10631 info_ptr->cr_save_offset = 0;
10633 if (! info_ptr->toc_save_p)
10634 info_ptr->toc_save_offset = 0;
10639 /* Return true if the current function uses any GPRs in 64-bit SIMD
10643 spe_func_has_64bit_regs_p (void)
10647 /* Functions that save and restore all the call-saved registers will
10648 need to save/restore the registers in 64-bits. */
10649 if (current_function_calls_eh_return
10650 || current_function_calls_setjmp
10651 || current_function_has_nonlocal_goto)
10654 insns = get_insns ();
10656 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
10662 i = PATTERN (insn);
10663 if (GET_CODE (i) == SET
10664 && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i))))
10673 debug_stack_info (rs6000_stack_t *info)
10675 const char *abi_string;
10678 info = rs6000_stack_info ();
10680 fprintf (stderr, "\nStack information for function %s:\n",
10681 ((current_function_decl && DECL_NAME (current_function_decl))
10682 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
10687 default: abi_string = "Unknown"; break;
10688 case ABI_NONE: abi_string = "NONE"; break;
10689 case ABI_AIX: abi_string = "AIX"; break;
10690 case ABI_DARWIN: abi_string = "Darwin"; break;
10691 case ABI_V4: abi_string = "V.4"; break;
10694 fprintf (stderr, "\tABI = %5s\n", abi_string);
10696 if (TARGET_ALTIVEC_ABI)
10697 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
10699 if (TARGET_SPE_ABI)
10700 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
10702 if (info->first_gp_reg_save != 32)
10703 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
10705 if (info->first_fp_reg_save != 64)
10706 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
10708 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
10709 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
10710 info->first_altivec_reg_save);
10712 if (info->lr_save_p)
10713 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
10715 if (info->cr_save_p)
10716 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
10718 if (info->toc_save_p)
10719 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
10721 if (info->vrsave_mask)
10722 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
10725 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
10728 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
10730 if (info->gp_save_offset)
10731 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
10733 if (info->fp_save_offset)
10734 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
10736 if (info->altivec_save_offset)
10737 fprintf (stderr, "\taltivec_save_offset = %5d\n",
10738 info->altivec_save_offset);
10740 if (info->spe_gp_save_offset)
10741 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
10742 info->spe_gp_save_offset);
10744 if (info->vrsave_save_offset)
10745 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
10746 info->vrsave_save_offset);
10748 if (info->lr_save_offset)
10749 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
10751 if (info->cr_save_offset)
10752 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
10754 if (info->toc_save_offset)
10755 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
10757 if (info->varargs_save_offset)
10758 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
10760 if (info->total_size)
10761 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
10764 if (info->varargs_size)
10765 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
10767 if (info->vars_size)
10768 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
10771 if (info->parm_size)
10772 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
10774 if (info->fixed_size)
10775 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
10778 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
10780 if (info->spe_gp_size)
10781 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
10784 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
10786 if (info->altivec_size)
10787 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
10789 if (info->vrsave_size)
10790 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
10792 if (info->altivec_padding_size)
10793 fprintf (stderr, "\taltivec_padding_size= %5d\n",
10794 info->altivec_padding_size);
10796 if (info->spe_padding_size)
10797 fprintf (stderr, "\tspe_padding_size = %5d\n",
10798 info->spe_padding_size);
10801 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
10804 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
10806 if (info->toc_size)
10807 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
10809 if (info->save_size)
10810 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
10812 if (info->reg_size != 4)
10813 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
10815 fprintf (stderr, "\n");
10819 rs6000_return_addr (int count, rtx frame)
10821 /* Currently we don't optimize very well between prolog and body
10822 code and for PIC code the code can be actually quite bad, so
10823 don't try to be too clever here. */
10824 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
10826 cfun->machine->ra_needs_full_frame = 1;
10833 plus_constant (copy_to_reg
10834 (gen_rtx_MEM (Pmode,
10835 memory_address (Pmode, frame))),
10836 RETURN_ADDRESS_OFFSET)));
10839 cfun->machine->ra_need_lr = 1;
10840 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
10843 /* Say whether a function is a candidate for sibcall handling or not.
10844 We do not allow indirect calls to be optimized into sibling calls.
10845 Also, we can't do it if there are any vector parameters; there's
10846 nowhere to put the VRsave code so it works; note that functions with
10847 vector parameters are required to have a prototype, so the argument
10848 type info must be available here. (The tail recursion case can work
10849 with vector parameters, but there's no way to distinguish here.) */
10851 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10856 if (TARGET_ALTIVEC_VRSAVE)
10858 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
10859 type; type = TREE_CHAIN (type))
10861 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
10865 if (DEFAULT_ABI == ABI_DARWIN
10866 || (*targetm.binds_local_p) (decl))
10868 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
10870 if (!lookup_attribute ("longcall", attr_list)
10871 || lookup_attribute ("shortcall", attr_list))
10879 rs6000_ra_ever_killed (void)
10885 /* Irritatingly, there are two kinds of thunks -- those created with
10886 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
10887 through the regular part of the compiler. This is a very hacky
10888 way to tell them apart. */
10889 if (current_function_is_thunk && !no_new_pseudos)
10892 /* regs_ever_live has LR marked as used if any sibcalls are present,
10893 but this should not force saving and restoring in the
10894 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
10895 clobbers LR, so that is inappropriate. */
10897 /* Also, the prologue can generate a store into LR that
10898 doesn't really count, like this:
10901 bcl to set PIC register
10905 When we're called from the epilogue, we need to avoid counting
10906 this as a store. */
10908 push_topmost_sequence ();
10909 top = get_insns ();
10910 pop_topmost_sequence ();
10911 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
10913 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
10917 if (FIND_REG_INC_NOTE (insn, reg))
10919 else if (GET_CODE (insn) == CALL_INSN
10920 && !SIBLING_CALL_P (insn))
10922 else if (set_of (reg, insn) != NULL_RTX
10923 && !prologue_epilogue_contains (insn))
10930 /* Add a REG_MAYBE_DEAD note to the insn. */
10932 rs6000_maybe_dead (rtx insn)
10934 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
10939 /* Emit instructions needed to load the TOC register.
10940 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
10941 a constant pool; or for SVR4 -fpic. */
10944 rs6000_emit_load_toc_table (int fromprolog)
10947 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10949 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10951 rtx temp = (fromprolog
10952 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
10953 : gen_reg_rtx (Pmode));
10954 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
10956 rs6000_maybe_dead (insn);
10957 insn = emit_move_insn (dest, temp);
10959 rs6000_maybe_dead (insn);
10961 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
10964 rtx tempLR = (fromprolog
10965 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
10966 : gen_reg_rtx (Pmode));
10967 rtx temp0 = (fromprolog
10968 ? gen_rtx_REG (Pmode, 0)
10969 : gen_reg_rtx (Pmode));
10972 /* possibly create the toc section */
10973 if (! toc_initialized)
10976 function_section (current_function_decl);
10983 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
10984 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10986 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
10987 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10989 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
10991 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
10992 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
10999 static int reload_toc_labelno = 0;
11001 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
11003 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
11004 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11006 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
11007 emit_move_insn (dest, tempLR);
11008 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
11010 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
11012 rs6000_maybe_dead (insn);
11014 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
11016 /* This is for AIX code running in non-PIC ELF32. */
11019 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
11020 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11022 insn = emit_insn (gen_elf_high (dest, realsym));
11024 rs6000_maybe_dead (insn);
11025 insn = emit_insn (gen_elf_low (dest, dest, realsym));
11027 rs6000_maybe_dead (insn);
11029 else if (DEFAULT_ABI == ABI_AIX)
11032 insn = emit_insn (gen_load_toc_aix_si (dest));
11034 insn = emit_insn (gen_load_toc_aix_di (dest));
11036 rs6000_maybe_dead (insn);
11042 /* Emit instructions to restore the link register after determining where
11043 its value has been stored. */
11046 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
11048 rs6000_stack_t *info = rs6000_stack_info ();
11051 operands[0] = source;
11052 operands[1] = scratch;
11054 if (info->lr_save_p)
11056 rtx frame_rtx = stack_pointer_rtx;
11057 HOST_WIDE_INT sp_offset = 0;
11060 if (frame_pointer_needed
11061 || current_function_calls_alloca
11062 || info->total_size > 32767)
11064 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
11065 frame_rtx = operands[1];
11067 else if (info->push_p)
11068 sp_offset = info->total_size;
11070 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
11071 tmp = gen_rtx_MEM (Pmode, tmp);
11072 emit_move_insn (tmp, operands[0]);
11075 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
11079 get_TOC_alias_set (void)
11081 static int set = -1;
11083 set = new_alias_set ();
11087 /* This returns nonzero if the current function uses the TOC. This is
11088 determined by the presence of (unspec ... UNSPEC_TOC) or
11089 use (unspec ... UNSPEC_TOC), which are generated by the various
11090 load_toc_* patterns. */
11097 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11100 rtx pat = PATTERN (insn);
11103 if (GET_CODE (pat) == PARALLEL)
11104 for (i = 0; i < XVECLEN (pat, 0); i++)
11106 rtx sub = XVECEXP (pat, 0, i);
11107 if (GET_CODE (sub) == USE)
11109 sub = XEXP (sub, 0);
11110 if (GET_CODE (sub) == UNSPEC
11111 && XINT (sub, 1) == UNSPEC_TOC)
11120 create_TOC_reference (rtx symbol)
11122 return gen_rtx_PLUS (Pmode,
11123 gen_rtx_REG (Pmode, TOC_REGISTER),
11124 gen_rtx_CONST (Pmode,
11125 gen_rtx_MINUS (Pmode, symbol,
11126 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
11129 /* If _Unwind_* has been called from within the same module,
11130 toc register is not guaranteed to be saved to 40(1) on function
11131 entry. Save it there in that case. */
11134 rs6000_aix_emit_builtin_unwind_init (void)
11137 rtx stack_top = gen_reg_rtx (Pmode);
11138 rtx opcode_addr = gen_reg_rtx (Pmode);
11139 rtx opcode = gen_reg_rtx (SImode);
11140 rtx tocompare = gen_reg_rtx (SImode);
11141 rtx no_toc_save_needed = gen_label_rtx ();
11143 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
11144 emit_move_insn (stack_top, mem);
11146 mem = gen_rtx_MEM (Pmode,
11147 gen_rtx_PLUS (Pmode, stack_top,
11148 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
11149 emit_move_insn (opcode_addr, mem);
11150 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
11151 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
11152 : 0xE8410028, SImode));
11154 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
11155 SImode, NULL_RTX, NULL_RTX,
11156 no_toc_save_needed);
11158 mem = gen_rtx_MEM (Pmode,
11159 gen_rtx_PLUS (Pmode, stack_top,
11160 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
11161 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
11162 emit_label (no_toc_save_needed);
11165 /* This ties together stack memory (MEM with an alias set of
11166 rs6000_sr_alias_set) and the change to the stack pointer. */
11169 rs6000_emit_stack_tie (void)
11171 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
11173 set_mem_alias_set (mem, rs6000_sr_alias_set);
11174 emit_insn (gen_stack_tie (mem));
11177 /* Emit the correct code for allocating stack space, as insns.
11178 If COPY_R12, make sure a copy of the old frame is left in r12.
11179 The generated code may use hard register 0 as a temporary. */
11182 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
11185 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11186 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
11187 rtx todec = GEN_INT (-size);
11189 if (current_function_limit_stack)
11191 if (REG_P (stack_limit_rtx)
11192 && REGNO (stack_limit_rtx) > 1
11193 && REGNO (stack_limit_rtx) <= 31)
11195 emit_insn (TARGET_32BIT
11196 ? gen_addsi3 (tmp_reg,
11199 : gen_adddi3 (tmp_reg,
11203 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11206 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
11208 && DEFAULT_ABI == ABI_V4)
11210 rtx toload = gen_rtx_CONST (VOIDmode,
11211 gen_rtx_PLUS (Pmode,
11215 emit_insn (gen_elf_high (tmp_reg, toload));
11216 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
11217 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11221 warning ("stack limit expression is not supported");
11224 if (copy_r12 || ! TARGET_UPDATE)
11225 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
11231 /* Need a note here so that try_split doesn't get confused. */
11232 if (get_last_insn() == NULL_RTX)
11233 emit_note (NOTE_INSN_DELETED);
11234 insn = emit_move_insn (tmp_reg, todec);
11235 try_split (PATTERN (insn), insn, 0);
11239 insn = emit_insn (TARGET_32BIT
11240 ? gen_movsi_update (stack_reg, stack_reg,
11242 : gen_movdi_update (stack_reg, stack_reg,
11243 todec, stack_reg));
11247 insn = emit_insn (TARGET_32BIT
11248 ? gen_addsi3 (stack_reg, stack_reg, todec)
11249 : gen_adddi3 (stack_reg, stack_reg, todec));
11250 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
11251 gen_rtx_REG (Pmode, 12));
11254 RTX_FRAME_RELATED_P (insn) = 1;
11256 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11257 gen_rtx_SET (VOIDmode, stack_reg,
11258 gen_rtx_PLUS (Pmode, stack_reg,
11263 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
11264 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
11265 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
11266 deduce these equivalences by itself so it wasn't necessary to hold
11267 its hand so much. */
11270 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
11271 rtx reg2, rtx rreg)
11275 /* copy_rtx will not make unique copies of registers, so we need to
11276 ensure we don't have unwanted sharing here. */
11278 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11281 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11283 real = copy_rtx (PATTERN (insn));
11285 if (reg2 != NULL_RTX)
11286 real = replace_rtx (real, reg2, rreg);
11288 real = replace_rtx (real, reg,
11289 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
11290 STACK_POINTER_REGNUM),
11293 /* We expect that 'real' is either a SET or a PARALLEL containing
11294 SETs (and possibly other stuff). In a PARALLEL, all the SETs
11295 are important so they all have to be marked RTX_FRAME_RELATED_P. */
11297 if (GET_CODE (real) == SET)
11301 temp = simplify_rtx (SET_SRC (set));
11303 SET_SRC (set) = temp;
11304 temp = simplify_rtx (SET_DEST (set));
11306 SET_DEST (set) = temp;
11307 if (GET_CODE (SET_DEST (set)) == MEM)
11309 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11311 XEXP (SET_DEST (set), 0) = temp;
11314 else if (GET_CODE (real) == PARALLEL)
11317 for (i = 0; i < XVECLEN (real, 0); i++)
11318 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
11320 rtx set = XVECEXP (real, 0, i);
11322 temp = simplify_rtx (SET_SRC (set));
11324 SET_SRC (set) = temp;
11325 temp = simplify_rtx (SET_DEST (set));
11327 SET_DEST (set) = temp;
11328 if (GET_CODE (SET_DEST (set)) == MEM)
11330 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11332 XEXP (SET_DEST (set), 0) = temp;
11334 RTX_FRAME_RELATED_P (set) = 1;
11341 real = spe_synthesize_frame_save (real);
11343 RTX_FRAME_RELATED_P (insn) = 1;
11344 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11349 /* Given an SPE frame note, return a PARALLEL of SETs with the
11350 original note, plus a synthetic register save. */
11353 spe_synthesize_frame_save (rtx real)
11355 rtx synth, offset, reg, real2;
11357 if (GET_CODE (real) != SET
11358 || GET_MODE (SET_SRC (real)) != V2SImode)
11361 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
11362 frame related note. The parallel contains a set of the register
11363 being saved, and another set to a synthetic register (n+1200).
11364 This is so we can differentiate between 64-bit and 32-bit saves.
11365 Words cannot describe this nastiness. */
11367 if (GET_CODE (SET_DEST (real)) != MEM
11368 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
11369 || GET_CODE (SET_SRC (real)) != REG)
11373 (set (mem (plus (reg x) (const y)))
11376 (set (mem (plus (reg x) (const y+4)))
11380 real2 = copy_rtx (real);
11381 PUT_MODE (SET_DEST (real2), SImode);
11382 reg = SET_SRC (real2);
11383 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
11384 synth = copy_rtx (real2);
11386 if (BYTES_BIG_ENDIAN)
11388 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
11389 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
11392 reg = SET_SRC (synth);
11394 synth = replace_rtx (synth, reg,
11395 gen_rtx_REG (SImode, REGNO (reg) + 1200));
11397 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
11398 synth = replace_rtx (synth, offset,
11399 GEN_INT (INTVAL (offset)
11400 + (BYTES_BIG_ENDIAN ? 0 : 4)));
11402 RTX_FRAME_RELATED_P (synth) = 1;
11403 RTX_FRAME_RELATED_P (real2) = 1;
11404 if (BYTES_BIG_ENDIAN)
11405 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
11407 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
11412 /* Returns an insn that has a vrsave set operation with the
11413 appropriate CLOBBERs. */
11416 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
11419 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
11420 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
11423 = gen_rtx_SET (VOIDmode,
11425 gen_rtx_UNSPEC_VOLATILE (SImode,
11426 gen_rtvec (2, reg, vrsave),
11431 /* We need to clobber the registers in the mask so the scheduler
11432 does not move sets to VRSAVE before sets of AltiVec registers.
11434 However, if the function receives nonlocal gotos, reload will set
11435 all call saved registers live. We will end up with:
11437 (set (reg 999) (mem))
11438 (parallel [ (set (reg vrsave) (unspec blah))
11439 (clobber (reg 999))])
11441 The clobber will cause the store into reg 999 to be dead, and
11442 flow will attempt to delete an epilogue insn. In this case, we
11443 need an unspec use/set of the register. */
11445 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11446 if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0)
11448 if (!epiloguep || call_used_regs [i])
11449 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
11450 gen_rtx_REG (V4SImode, i));
11453 rtx reg = gen_rtx_REG (V4SImode, i);
11456 = gen_rtx_SET (VOIDmode,
11458 gen_rtx_UNSPEC (V4SImode,
11459 gen_rtvec (1, reg), 27));
11463 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
11465 for (i = 0; i < nclobs; ++i)
11466 XVECEXP (insn, 0, i) = clobs[i];
11471 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
11472 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
11475 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
11476 unsigned int regno, int offset, HOST_WIDE_INT total_size)
11478 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
11479 rtx replacea, replaceb;
11481 int_rtx = GEN_INT (offset);
11483 /* Some cases that need register indexed addressing. */
11484 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
11486 && SPE_VECTOR_MODE (mode)
11487 && !SPE_CONST_OFFSET_OK (offset)))
11489 /* Whomever calls us must make sure r11 is available in the
11490 flow path of instructions in the prologue. */
11491 offset_rtx = gen_rtx_REG (Pmode, 11);
11492 emit_move_insn (offset_rtx, int_rtx);
11494 replacea = offset_rtx;
11495 replaceb = int_rtx;
11499 offset_rtx = int_rtx;
11500 replacea = NULL_RTX;
11501 replaceb = NULL_RTX;
11504 reg = gen_rtx_REG (mode, regno);
11505 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
11506 mem = gen_rtx_MEM (mode, addr);
11507 set_mem_alias_set (mem, rs6000_sr_alias_set);
11509 insn = emit_move_insn (mem, reg);
11511 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
11514 /* Emit an offset memory reference suitable for a frame store, while
11515 converting to a valid addressing mode. */
11518 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
11520 rtx int_rtx, offset_rtx;
11522 int_rtx = GEN_INT (offset);
11524 if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
11526 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
11527 emit_move_insn (offset_rtx, int_rtx);
11530 offset_rtx = int_rtx;
11532 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
11535 /* Emit function prologue as insns. */
11538 rs6000_emit_prologue (void)
11540 rs6000_stack_t *info = rs6000_stack_info ();
11541 enum machine_mode reg_mode = Pmode;
11542 int reg_size = UNITS_PER_WORD;
11543 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11544 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
11545 rtx frame_reg_rtx = sp_reg_rtx;
11546 rtx cr_save_rtx = NULL_RTX;
11548 int saving_FPRs_inline;
11549 int using_store_multiple;
11550 HOST_WIDE_INT sp_offset = 0;
11552 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
11554 reg_mode = V2SImode;
11558 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
11559 && (!TARGET_SPE_ABI
11560 || info->spe_64bit_regs_used == 0)
11561 && info->first_gp_reg_save < 31);
11562 saving_FPRs_inline = (info->first_fp_reg_save == 64
11563 || FP_SAVE_INLINE (info->first_fp_reg_save)
11564 || current_function_calls_eh_return
11565 || cfun->machine->ra_need_lr);
11567 /* For V.4, update stack before we do any saving and set back pointer. */
11569 && (DEFAULT_ABI == ABI_V4
11570 || current_function_calls_eh_return))
11572 if (info->total_size < 32767)
11573 sp_offset = info->total_size;
11575 frame_reg_rtx = frame_ptr_rtx;
11576 rs6000_emit_allocate_stack (info->total_size,
11577 (frame_reg_rtx != sp_reg_rtx
11578 && (info->cr_save_p
11580 || info->first_fp_reg_save < 64
11581 || info->first_gp_reg_save < 32
11583 if (frame_reg_rtx != sp_reg_rtx)
11584 rs6000_emit_stack_tie ();
11587 /* Save AltiVec registers if needed. */
11588 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
11592 /* There should be a non inline version of this, for when we
11593 are saving lots of vector registers. */
11594 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
11595 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
11597 rtx areg, savereg, mem;
11600 offset = info->altivec_save_offset + sp_offset
11601 + 16 * (i - info->first_altivec_reg_save);
11603 savereg = gen_rtx_REG (V4SImode, i);
11605 areg = gen_rtx_REG (Pmode, 0);
11606 emit_move_insn (areg, GEN_INT (offset));
11608 /* AltiVec addressing mode is [reg+reg]. */
11609 mem = gen_rtx_MEM (V4SImode,
11610 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
11612 set_mem_alias_set (mem, rs6000_sr_alias_set);
11614 insn = emit_move_insn (mem, savereg);
11616 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11617 areg, GEN_INT (offset));
11621 /* VRSAVE is a bit vector representing which AltiVec registers
11622 are used. The OS uses this to determine which vector
11623 registers to save on a context switch. We need to save
11624 VRSAVE on the stack frame, add whatever AltiVec registers we
11625 used in this function, and do the corresponding magic in the
11628 if (TARGET_ALTIVEC && info->vrsave_mask != 0)
11630 rtx reg, mem, vrsave;
11633 /* Get VRSAVE onto a GPR. */
11634 reg = gen_rtx_REG (SImode, 12);
11635 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
11637 emit_insn (gen_get_vrsave_internal (reg));
11639 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
11642 offset = info->vrsave_save_offset + sp_offset;
11644 = gen_rtx_MEM (SImode,
11645 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
11646 set_mem_alias_set (mem, rs6000_sr_alias_set);
11647 insn = emit_move_insn (mem, reg);
11649 /* Include the registers in the mask. */
11650 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
11652 insn = emit_insn (generate_set_vrsave (reg, info, 0));
11655 /* If we use the link register, get it into r0. */
11656 if (info->lr_save_p)
11657 emit_move_insn (gen_rtx_REG (Pmode, 0),
11658 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
11660 /* If we need to save CR, put it into r12. */
11661 if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
11663 cr_save_rtx = gen_rtx_REG (SImode, 12);
11664 emit_insn (gen_movesi_from_cr (cr_save_rtx));
11667 /* Do any required saving of fpr's. If only one or two to save, do
11668 it ourselves. Otherwise, call function. */
11669 if (saving_FPRs_inline)
11672 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
11673 if ((regs_ever_live[info->first_fp_reg_save+i]
11674 && ! call_used_regs[info->first_fp_reg_save+i]))
11675 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
11676 info->first_fp_reg_save + i,
11677 info->fp_save_offset + sp_offset + 8 * i,
11680 else if (info->first_fp_reg_save != 64)
11684 const char *alloc_rname;
11686 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
11688 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
11689 gen_rtx_REG (Pmode,
11690 LINK_REGISTER_REGNUM));
11691 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
11692 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
11693 alloc_rname = ggc_strdup (rname);
11694 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
11695 gen_rtx_SYMBOL_REF (Pmode,
11697 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
11699 rtx addr, reg, mem;
11700 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
11701 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11702 GEN_INT (info->fp_save_offset
11703 + sp_offset + 8*i));
11704 mem = gen_rtx_MEM (DFmode, addr);
11705 set_mem_alias_set (mem, rs6000_sr_alias_set);
11707 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
11709 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
11710 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11711 NULL_RTX, NULL_RTX);
11714 /* Save GPRs. This is done as a PARALLEL if we are using
11715 the store-multiple instructions. */
11716 if (using_store_multiple)
11720 p = rtvec_alloc (32 - info->first_gp_reg_save);
11721 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
11723 rtx addr, reg, mem;
11724 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
11725 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11726 GEN_INT (info->gp_save_offset
11729 mem = gen_rtx_MEM (reg_mode, addr);
11730 set_mem_alias_set (mem, rs6000_sr_alias_set);
11732 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
11734 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
11735 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11736 NULL_RTX, NULL_RTX);
11741 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
11742 if ((regs_ever_live[info->first_gp_reg_save+i]
11743 && ! call_used_regs[info->first_gp_reg_save+i])
11744 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
11745 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
11746 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
11748 rtx addr, reg, mem;
11749 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
11751 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
11753 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
11756 if (!SPE_CONST_OFFSET_OK (offset))
11758 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
11759 emit_move_insn (b, GEN_INT (offset));
11762 b = GEN_INT (offset);
11764 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
11765 mem = gen_rtx_MEM (V2SImode, addr);
11766 set_mem_alias_set (mem, rs6000_sr_alias_set);
11767 insn = emit_move_insn (mem, reg);
11769 if (GET_CODE (b) == CONST_INT)
11770 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11771 NULL_RTX, NULL_RTX);
11773 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11774 b, GEN_INT (offset));
11778 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11779 GEN_INT (info->gp_save_offset
11782 mem = gen_rtx_MEM (reg_mode, addr);
11783 set_mem_alias_set (mem, rs6000_sr_alias_set);
11785 insn = emit_move_insn (mem, reg);
11786 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11787 NULL_RTX, NULL_RTX);
11792 /* ??? There's no need to emit actual instructions here, but it's the
11793 easiest way to get the frame unwind information emitted. */
11794 if (current_function_calls_eh_return)
11796 unsigned int i, regno;
11798 /* In AIX ABI we need to pretend we save r2 here. */
11801 rtx addr, reg, mem;
11803 reg = gen_rtx_REG (reg_mode, 2);
11804 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11805 GEN_INT (sp_offset + 5 * reg_size));
11806 mem = gen_rtx_MEM (reg_mode, addr);
11807 set_mem_alias_set (mem, rs6000_sr_alias_set);
11809 insn = emit_move_insn (mem, reg);
11810 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11811 NULL_RTX, NULL_RTX);
11812 PATTERN (insn) = gen_blockage ();
11817 regno = EH_RETURN_DATA_REGNO (i);
11818 if (regno == INVALID_REGNUM)
11821 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
11822 info->ehrd_offset + sp_offset
11823 + reg_size * (int) i,
11828 /* Save lr if we used it. */
11829 if (info->lr_save_p)
11831 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11832 GEN_INT (info->lr_save_offset + sp_offset));
11833 rtx reg = gen_rtx_REG (Pmode, 0);
11834 rtx mem = gen_rtx_MEM (Pmode, addr);
11835 /* This should not be of rs6000_sr_alias_set, because of
11836 __builtin_return_address. */
11838 insn = emit_move_insn (mem, reg);
11839 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11840 reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
11843 /* Save CR if we use any that must be preserved. */
11844 if (info->cr_save_p)
11846 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11847 GEN_INT (info->cr_save_offset + sp_offset));
11848 rtx mem = gen_rtx_MEM (SImode, addr);
11850 set_mem_alias_set (mem, rs6000_sr_alias_set);
11852 /* If r12 was used to hold the original sp, copy cr into r0 now
11854 if (REGNO (frame_reg_rtx) == 12)
11856 cr_save_rtx = gen_rtx_REG (SImode, 0);
11857 emit_insn (gen_movesi_from_cr (cr_save_rtx));
11859 insn = emit_move_insn (mem, cr_save_rtx);
11861 /* Now, there's no way that dwarf2out_frame_debug_expr is going
11862 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
11863 But that's OK. All we have to do is specify that _one_ condition
11864 code register is saved in this stack slot. The thrower's epilogue
11865 will then restore all the call-saved registers.
11866 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
11867 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11868 cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO));
11871 /* Update stack and set back pointer unless this is V.4,
11872 for which it was done previously. */
11874 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
11875 rs6000_emit_allocate_stack (info->total_size, FALSE);
11877 /* Set frame pointer, if needed. */
11878 if (frame_pointer_needed)
11880 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
11882 RTX_FRAME_RELATED_P (insn) = 1;
11885 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
11886 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
11887 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
11888 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
11890 /* If emit_load_toc_table will use the link register, we need to save
11891 it. We use R12 for this purpose because emit_load_toc_table
11892 can use register 0. This allows us to use a plain 'blr' to return
11893 from the procedure more often. */
11894 int save_LR_around_toc_setup = (TARGET_ELF
11895 && DEFAULT_ABI != ABI_AIX
11897 && ! info->lr_save_p
11898 && EXIT_BLOCK_PTR->pred != NULL);
11899 if (save_LR_around_toc_setup)
11901 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11902 rs6000_maybe_dead (emit_move_insn (frame_ptr_rtx, lr));
11903 rs6000_emit_load_toc_table (TRUE);
11904 rs6000_maybe_dead (emit_move_insn (lr, frame_ptr_rtx));
11907 rs6000_emit_load_toc_table (TRUE);
11911 if (DEFAULT_ABI == ABI_DARWIN
11912 && flag_pic && current_function_uses_pic_offset_table)
11914 rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11915 const char *picbase = machopic_function_base_name ();
11916 rtx src = gen_rtx_SYMBOL_REF (Pmode, picbase);
11918 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest, src)));
11920 rs6000_maybe_dead (
11921 emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM),
11922 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)));
11927 /* Write function prologue. */
11930 rs6000_output_function_prologue (FILE *file,
11931 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11933 rs6000_stack_t *info = rs6000_stack_info ();
11935 if (TARGET_DEBUG_STACK)
11936 debug_stack_info (info);
11938 /* Write .extern for any function we will call to save and restore
11940 if (info->first_fp_reg_save < 64
11941 && !FP_SAVE_INLINE (info->first_fp_reg_save))
11942 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
11943 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
11944 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
11945 RESTORE_FP_SUFFIX);
11947 /* Write .extern for AIX common mode routines, if needed. */
11948 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
11950 fputs ("\t.extern __mulh\n", file);
11951 fputs ("\t.extern __mull\n", file);
11952 fputs ("\t.extern __divss\n", file);
11953 fputs ("\t.extern __divus\n", file);
11954 fputs ("\t.extern __quoss\n", file);
11955 fputs ("\t.extern __quous\n", file);
11956 common_mode_defined = 1;
11959 if (! HAVE_prologue)
11963 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
11964 the "toplevel" insn chain. */
11965 emit_note (NOTE_INSN_DELETED);
11966 rs6000_emit_prologue ();
11967 emit_note (NOTE_INSN_DELETED);
11969 /* Expand INSN_ADDRESSES so final() doesn't crash. */
11973 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
11975 INSN_ADDRESSES_NEW (insn, addr);
11980 if (TARGET_DEBUG_STACK)
11981 debug_rtx_list (get_insns (), 100);
11982 final (get_insns (), file, FALSE, FALSE);
11986 rs6000_pic_labelno++;
11989 /* Emit function epilogue as insns.
11991 At present, dwarf2out_frame_debug_expr doesn't understand
11992 register restores, so we don't bother setting RTX_FRAME_RELATED_P
11993 anywhere in the epilogue. Most of the insns below would in any case
11994 need special notes to explain where r11 is in relation to the stack. */
11997 rs6000_emit_epilogue (int sibcall)
11999 rs6000_stack_t *info;
12000 int restoring_FPRs_inline;
12001 int using_load_multiple;
12002 int using_mfcr_multiple;
12003 int use_backchain_to_restore_sp;
12005 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
12006 rtx frame_reg_rtx = sp_reg_rtx;
12007 enum machine_mode reg_mode = Pmode;
12008 int reg_size = UNITS_PER_WORD;
12011 info = rs6000_stack_info ();
12013 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12015 reg_mode = V2SImode;
12019 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12020 && (!TARGET_SPE_ABI
12021 || info->spe_64bit_regs_used == 0)
12022 && info->first_gp_reg_save < 31);
12023 restoring_FPRs_inline = (sibcall
12024 || current_function_calls_eh_return
12025 || info->first_fp_reg_save == 64
12026 || FP_SAVE_INLINE (info->first_fp_reg_save));
12027 use_backchain_to_restore_sp = (frame_pointer_needed
12028 || current_function_calls_alloca
12029 || info->total_size > 32767);
12030 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
12031 || rs6000_cpu == PROCESSOR_PPC603
12032 || rs6000_cpu == PROCESSOR_PPC750
12035 /* If we have a frame pointer, a call to alloca, or a large stack
12036 frame, restore the old stack pointer using the backchain. Otherwise,
12037 we know what size to update it with. */
12038 if (use_backchain_to_restore_sp)
12040 /* Under V.4, don't reset the stack pointer until after we're done
12041 loading the saved registers. */
12042 if (DEFAULT_ABI == ABI_V4)
12043 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
12045 emit_move_insn (frame_reg_rtx,
12046 gen_rtx_MEM (Pmode, sp_reg_rtx));
12049 else if (info->push_p)
12051 if (DEFAULT_ABI == ABI_V4
12052 || current_function_calls_eh_return)
12053 sp_offset = info->total_size;
12056 emit_insn (TARGET_32BIT
12057 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12058 GEN_INT (info->total_size))
12059 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12060 GEN_INT (info->total_size)));
12064 /* Restore AltiVec registers if needed. */
12065 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
12069 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12070 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12072 rtx addr, areg, mem;
12074 areg = gen_rtx_REG (Pmode, 0);
12076 (areg, GEN_INT (info->altivec_save_offset
12078 + 16 * (i - info->first_altivec_reg_save)));
12080 /* AltiVec addressing mode is [reg+reg]. */
12081 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
12082 mem = gen_rtx_MEM (V4SImode, addr);
12083 set_mem_alias_set (mem, rs6000_sr_alias_set);
12085 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
12089 /* Restore VRSAVE if needed. */
12090 if (TARGET_ALTIVEC_ABI && info->vrsave_mask != 0)
12092 rtx addr, mem, reg;
12094 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12095 GEN_INT (info->vrsave_save_offset + sp_offset));
12096 mem = gen_rtx_MEM (SImode, addr);
12097 set_mem_alias_set (mem, rs6000_sr_alias_set);
12098 reg = gen_rtx_REG (SImode, 12);
12099 emit_move_insn (reg, mem);
12101 emit_insn (generate_set_vrsave (reg, info, 1));
12104 /* Get the old lr if we saved it. */
12105 if (info->lr_save_p)
12107 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
12108 info->lr_save_offset + sp_offset);
12110 set_mem_alias_set (mem, rs6000_sr_alias_set);
12112 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
12115 /* Get the old cr if we saved it. */
12116 if (info->cr_save_p)
12118 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12119 GEN_INT (info->cr_save_offset + sp_offset));
12120 rtx mem = gen_rtx_MEM (SImode, addr);
12122 set_mem_alias_set (mem, rs6000_sr_alias_set);
12124 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
12127 /* Set LR here to try to overlap restores below. */
12128 if (info->lr_save_p)
12129 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
12130 gen_rtx_REG (Pmode, 0));
12132 /* Load exception handler data registers, if needed. */
12133 if (current_function_calls_eh_return)
12135 unsigned int i, regno;
12139 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12140 GEN_INT (sp_offset + 5 * reg_size));
12141 rtx mem = gen_rtx_MEM (reg_mode, addr);
12143 set_mem_alias_set (mem, rs6000_sr_alias_set);
12145 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
12152 regno = EH_RETURN_DATA_REGNO (i);
12153 if (regno == INVALID_REGNUM)
12156 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
12157 info->ehrd_offset + sp_offset
12158 + reg_size * (int) i);
12159 set_mem_alias_set (mem, rs6000_sr_alias_set);
12161 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
12165 /* Restore GPRs. This is done as a PARALLEL if we are using
12166 the load-multiple instructions. */
12167 if (using_load_multiple)
12170 p = rtvec_alloc (32 - info->first_gp_reg_save);
12171 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12173 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12174 GEN_INT (info->gp_save_offset
12177 rtx mem = gen_rtx_MEM (reg_mode, addr);
12179 set_mem_alias_set (mem, rs6000_sr_alias_set);
12182 gen_rtx_SET (VOIDmode,
12183 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
12186 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12189 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12190 if ((regs_ever_live[info->first_gp_reg_save+i]
12191 && ! call_used_regs[info->first_gp_reg_save+i])
12192 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12193 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12194 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12196 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12197 GEN_INT (info->gp_save_offset
12200 rtx mem = gen_rtx_MEM (reg_mode, addr);
12202 /* Restore 64-bit quantities for SPE. */
12203 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12205 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12208 if (!SPE_CONST_OFFSET_OK (offset))
12210 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12211 emit_move_insn (b, GEN_INT (offset));
12214 b = GEN_INT (offset);
12216 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12217 mem = gen_rtx_MEM (V2SImode, addr);
12220 set_mem_alias_set (mem, rs6000_sr_alias_set);
12222 emit_move_insn (gen_rtx_REG (reg_mode,
12223 info->first_gp_reg_save + i), mem);
12226 /* Restore fpr's if we need to do it without calling a function. */
12227 if (restoring_FPRs_inline)
12228 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12229 if ((regs_ever_live[info->first_fp_reg_save+i]
12230 && ! call_used_regs[info->first_fp_reg_save+i]))
12233 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12234 GEN_INT (info->fp_save_offset
12237 mem = gen_rtx_MEM (DFmode, addr);
12238 set_mem_alias_set (mem, rs6000_sr_alias_set);
12240 emit_move_insn (gen_rtx_REG (DFmode,
12241 info->first_fp_reg_save + i),
12245 /* If we saved cr, restore it here. Just those that were used. */
12246 if (info->cr_save_p)
12248 rtx r12_rtx = gen_rtx_REG (SImode, 12);
12251 if (using_mfcr_multiple)
12253 for (i = 0; i < 8; i++)
12254 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12260 if (using_mfcr_multiple && count > 1)
12265 p = rtvec_alloc (count);
12268 for (i = 0; i < 8; i++)
12269 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12271 rtvec r = rtvec_alloc (2);
12272 RTVEC_ELT (r, 0) = r12_rtx;
12273 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
12274 RTVEC_ELT (p, ndx) =
12275 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
12276 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
12279 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12284 for (i = 0; i < 8; i++)
12285 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12287 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
12293 /* If this is V.4, unwind the stack pointer after all of the loads
12294 have been done. We need to emit a block here so that sched
12295 doesn't decide to move the sp change before the register restores
12296 (which may not have any obvious dependency on the stack). This
12297 doesn't hurt performance, because there is no scheduling that can
12298 be done after this point. */
12299 if (DEFAULT_ABI == ABI_V4
12300 || current_function_calls_eh_return)
12302 if (frame_reg_rtx != sp_reg_rtx)
12303 rs6000_emit_stack_tie ();
12305 if (use_backchain_to_restore_sp)
12307 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
12309 else if (sp_offset != 0)
12311 emit_insn (TARGET_32BIT
12312 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12313 GEN_INT (sp_offset))
12314 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12315 GEN_INT (sp_offset)));
12319 if (current_function_calls_eh_return)
12321 rtx sa = EH_RETURN_STACKADJ_RTX;
12322 emit_insn (TARGET_32BIT
12323 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
12324 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
12330 if (! restoring_FPRs_inline)
12331 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
12333 p = rtvec_alloc (2);
12335 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
12336 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12337 gen_rtx_REG (Pmode,
12338 LINK_REGISTER_REGNUM));
12340 /* If we have to restore more than two FP registers, branch to the
12341 restore function. It will return to our caller. */
12342 if (! restoring_FPRs_inline)
12346 const char *alloc_rname;
12348 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
12349 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
12350 alloc_rname = ggc_strdup (rname);
12351 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
12352 gen_rtx_SYMBOL_REF (Pmode,
12355 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12358 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
12359 GEN_INT (info->fp_save_offset + 8*i));
12360 mem = gen_rtx_MEM (DFmode, addr);
12361 set_mem_alias_set (mem, rs6000_sr_alias_set);
12363 RTVEC_ELT (p, i+3) =
12364 gen_rtx_SET (VOIDmode,
12365 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
12370 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
12374 /* Write function epilogue. */
12377 rs6000_output_function_epilogue (FILE *file,
12378 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12380 rs6000_stack_t *info = rs6000_stack_info ();
12382 if (! HAVE_epilogue)
12384 rtx insn = get_last_insn ();
12385 /* If the last insn was a BARRIER, we don't have to write anything except
12386 the trace table. */
12387 if (GET_CODE (insn) == NOTE)
12388 insn = prev_nonnote_insn (insn);
12389 if (insn == 0 || GET_CODE (insn) != BARRIER)
12391 /* This is slightly ugly, but at least we don't have two
12392 copies of the epilogue-emitting code. */
12395 /* A NOTE_INSN_DELETED is supposed to be at the start
12396 and end of the "toplevel" insn chain. */
12397 emit_note (NOTE_INSN_DELETED);
12398 rs6000_emit_epilogue (FALSE);
12399 emit_note (NOTE_INSN_DELETED);
12401 /* Expand INSN_ADDRESSES so final() doesn't crash. */
12405 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12407 INSN_ADDRESSES_NEW (insn, addr);
12412 if (TARGET_DEBUG_STACK)
12413 debug_rtx_list (get_insns (), 100);
12414 final (get_insns (), file, FALSE, FALSE);
12420 macho_branch_islands ();
12421 /* Mach-O doesn't support labels at the end of objects, so if
12422 it looks like we might want one, insert a NOP. */
12424 rtx insn = get_last_insn ();
12427 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
12428 insn = PREV_INSN (insn);
12432 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
12433 fputs ("\tnop\n", file);
12437 /* Output a traceback table here. See /usr/include/sys/debug.h for info
12440 We don't output a traceback table if -finhibit-size-directive was
12441 used. The documentation for -finhibit-size-directive reads
12442 ``don't output a @code{.size} assembler directive, or anything
12443 else that would cause trouble if the function is split in the
12444 middle, and the two halves are placed at locations far apart in
12445 memory.'' The traceback table has this property, since it
12446 includes the offset from the start of the function to the
12447 traceback table itself.
12449 System V.4 Powerpc's (and the embedded ABI derived from it) use a
12450 different traceback table. */
12451 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
12452 && rs6000_traceback != traceback_none)
12454 const char *fname = NULL;
12455 const char *language_string = lang_hooks.name;
12456 int fixed_parms = 0, float_parms = 0, parm_info = 0;
12458 int optional_tbtab;
12460 if (rs6000_traceback == traceback_full)
12461 optional_tbtab = 1;
12462 else if (rs6000_traceback == traceback_part)
12463 optional_tbtab = 0;
12465 optional_tbtab = !optimize_size && !TARGET_ELF;
12467 if (optional_tbtab)
12469 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
12470 while (*fname == '.') /* V.4 encodes . in the name */
12473 /* Need label immediately before tbtab, so we can compute
12474 its offset from the function start. */
12475 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
12476 ASM_OUTPUT_LABEL (file, fname);
12479 /* The .tbtab pseudo-op can only be used for the first eight
12480 expressions, since it can't handle the possibly variable
12481 length fields that follow. However, if you omit the optional
12482 fields, the assembler outputs zeros for all optional fields
12483 anyways, giving each variable length field is minimum length
12484 (as defined in sys/debug.h). Thus we can not use the .tbtab
12485 pseudo-op at all. */
12487 /* An all-zero word flags the start of the tbtab, for debuggers
12488 that have to find it by searching forward from the entry
12489 point or from the current pc. */
12490 fputs ("\t.long 0\n", file);
12492 /* Tbtab format type. Use format type 0. */
12493 fputs ("\t.byte 0,", file);
12495 /* Language type. Unfortunately, there doesn't seem to be any
12496 official way to get this info, so we use language_string. C
12497 is 0. C++ is 9. No number defined for Obj-C, so use the
12498 value for C for now. There is no official value for Java,
12499 although IBM appears to be using 13. */
12500 if (! strcmp (language_string, "GNU C")
12501 || ! strcmp (language_string, "GNU Objective-C"))
12503 else if (! strcmp (language_string, "GNU F77"))
12505 else if (! strcmp (language_string, "GNU Ada"))
12507 else if (! strcmp (language_string, "GNU Pascal"))
12509 else if (! strcmp (language_string, "GNU C++"))
12511 else if (! strcmp (language_string, "GNU Java"))
12515 fprintf (file, "%d,", i);
12517 /* 8 single bit fields: global linkage (not set for C extern linkage,
12518 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
12519 from start of procedure stored in tbtab, internal function, function
12520 has controlled storage, function has no toc, function uses fp,
12521 function logs/aborts fp operations. */
12522 /* Assume that fp operations are used if any fp reg must be saved. */
12523 fprintf (file, "%d,",
12524 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
12526 /* 6 bitfields: function is interrupt handler, name present in
12527 proc table, function calls alloca, on condition directives
12528 (controls stack walks, 3 bits), saves condition reg, saves
12530 /* The `function calls alloca' bit seems to be set whenever reg 31 is
12531 set up as a frame pointer, even when there is no alloca call. */
12532 fprintf (file, "%d,",
12533 ((optional_tbtab << 6)
12534 | ((optional_tbtab & frame_pointer_needed) << 5)
12535 | (info->cr_save_p << 1)
12536 | (info->lr_save_p)));
12538 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
12540 fprintf (file, "%d,",
12541 (info->push_p << 7) | (64 - info->first_fp_reg_save));
12543 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
12544 fprintf (file, "%d,", (32 - first_reg_to_save ()));
12546 if (optional_tbtab)
12548 /* Compute the parameter info from the function decl argument
12551 int next_parm_info_bit = 31;
12553 for (decl = DECL_ARGUMENTS (current_function_decl);
12554 decl; decl = TREE_CHAIN (decl))
12556 rtx parameter = DECL_INCOMING_RTL (decl);
12557 enum machine_mode mode = GET_MODE (parameter);
12559 if (GET_CODE (parameter) == REG)
12561 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
12567 if (mode == SFmode)
12569 else if (mode == DFmode || mode == TFmode)
12574 /* If only one bit will fit, don't or in this entry. */
12575 if (next_parm_info_bit > 0)
12576 parm_info |= (bits << (next_parm_info_bit - 1));
12577 next_parm_info_bit -= 2;
12581 fixed_parms += ((GET_MODE_SIZE (mode)
12582 + (UNITS_PER_WORD - 1))
12584 next_parm_info_bit -= 1;
12590 /* Number of fixed point parameters. */
12591 /* This is actually the number of words of fixed point parameters; thus
12592 an 8 byte struct counts as 2; and thus the maximum value is 8. */
12593 fprintf (file, "%d,", fixed_parms);
12595 /* 2 bitfields: number of floating point parameters (7 bits), parameters
12597 /* This is actually the number of fp registers that hold parameters;
12598 and thus the maximum value is 13. */
12599 /* Set parameters on stack bit if parameters are not in their original
12600 registers, regardless of whether they are on the stack? Xlc
12601 seems to set the bit when not optimizing. */
12602 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
12604 if (! optional_tbtab)
12607 /* Optional fields follow. Some are variable length. */
12609 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
12610 11 double float. */
12611 /* There is an entry for each parameter in a register, in the order that
12612 they occur in the parameter list. Any intervening arguments on the
12613 stack are ignored. If the list overflows a long (max possible length
12614 34 bits) then completely leave off all elements that don't fit. */
12615 /* Only emit this long if there was at least one parameter. */
12616 if (fixed_parms || float_parms)
12617 fprintf (file, "\t.long %d\n", parm_info);
12619 /* Offset from start of code to tb table. */
12620 fputs ("\t.long ", file);
12621 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
12623 RS6000_OUTPUT_BASENAME (file, fname);
12625 assemble_name (file, fname);
12627 fputs ("-.", file);
12629 RS6000_OUTPUT_BASENAME (file, fname);
12631 assemble_name (file, fname);
12635 /* Interrupt handler mask. */
12636 /* Omit this long, since we never set the interrupt handler bit
12639 /* Number of CTL (controlled storage) anchors. */
12640 /* Omit this long, since the has_ctl bit is never set above. */
12642 /* Displacement into stack of each CTL anchor. */
12643 /* Omit this list of longs, because there are no CTL anchors. */
12645 /* Length of function name. */
12648 fprintf (file, "\t.short %d\n", (int) strlen (fname));
12650 /* Function name. */
12651 assemble_string (fname, strlen (fname));
12653 /* Register for alloca automatic storage; this is always reg 31.
12654 Only emit this if the alloca bit was set above. */
12655 if (frame_pointer_needed)
12656 fputs ("\t.byte 31\n", file);
12658 fputs ("\t.align 2\n", file);
12662 /* A C compound statement that outputs the assembler code for a thunk
12663 function, used to implement C++ virtual function calls with
12664 multiple inheritance. The thunk acts as a wrapper around a virtual
12665 function, adjusting the implicit object parameter before handing
12666 control off to the real function.
12668 First, emit code to add the integer DELTA to the location that
12669 contains the incoming first argument. Assume that this argument
12670 contains a pointer, and is the one used to pass the `this' pointer
12671 in C++. This is the incoming argument *before* the function
12672 prologue, e.g. `%o0' on a sparc. The addition must preserve the
12673 values of all other incoming arguments.
12675 After the addition, emit code to jump to FUNCTION, which is a
12676 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
12677 not touch the return address. Hence returning from FUNCTION will
12678 return to whoever called the current `thunk'.
12680 The effect must be as if FUNCTION had been called directly with the
12681 adjusted first argument. This macro is responsible for emitting
12682 all of the code for a thunk function; output_function_prologue()
12683 and output_function_epilogue() are not invoked.
12685 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
12686 been extracted from it.) It might possibly be useful on some
12687 targets, but probably not.
12689 If you do not define this macro, the target-independent code in the
12690 C++ frontend will generate a less efficient heavyweight thunk that
12691 calls FUNCTION instead of jumping to it. The generic approach does
12692 not support varargs. */
12695 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
12696 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
12699 rtx this, insn, funexp;
12701 reload_completed = 1;
12702 epilogue_completed = 1;
12703 no_new_pseudos = 1;
12705 /* Mark the end of the (empty) prologue. */
12706 emit_note (NOTE_INSN_PROLOGUE_END);
12708 /* Find the "this" pointer. If the function returns a structure,
12709 the structure return pointer is in r3. */
12710 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
12711 this = gen_rtx_REG (Pmode, 4);
12713 this = gen_rtx_REG (Pmode, 3);
12715 /* Apply the constant offset, if required. */
12718 rtx delta_rtx = GEN_INT (delta);
12719 emit_insn (TARGET_32BIT
12720 ? gen_addsi3 (this, this, delta_rtx)
12721 : gen_adddi3 (this, this, delta_rtx));
12724 /* Apply the offset from the vtable, if required. */
12727 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
12728 rtx tmp = gen_rtx_REG (Pmode, 12);
12730 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
12731 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
12733 emit_insn (TARGET_32BIT
12734 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
12735 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
12736 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
12740 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
12742 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
12744 emit_insn (TARGET_32BIT
12745 ? gen_addsi3 (this, this, tmp)
12746 : gen_adddi3 (this, this, tmp));
12749 /* Generate a tail call to the target function. */
12750 if (!TREE_USED (function))
12752 assemble_external (function);
12753 TREE_USED (function) = 1;
12755 funexp = XEXP (DECL_RTL (function), 0);
12756 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
12759 if (MACHOPIC_INDIRECT)
12760 funexp = machopic_indirect_call_target (funexp);
12763 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
12764 generate sibcall RTL explicitly to avoid constraint abort. */
12765 insn = emit_call_insn (
12766 gen_rtx_PARALLEL (VOIDmode,
12768 gen_rtx_CALL (VOIDmode,
12769 funexp, const0_rtx),
12770 gen_rtx_USE (VOIDmode, const0_rtx),
12771 gen_rtx_USE (VOIDmode,
12772 gen_rtx_REG (SImode,
12773 LINK_REGISTER_REGNUM)),
12774 gen_rtx_RETURN (VOIDmode))));
12775 SIBLING_CALL_P (insn) = 1;
12778 /* Run just enough of rest_of_compilation to get the insns emitted.
12779 There's not really enough bulk here to make other passes such as
12780 instruction scheduling worth while. Note that use_thunk calls
12781 assemble_start_function and assemble_end_function. */
12782 insn = get_insns ();
12783 insn_locators_initialize ();
12784 shorten_branches (insn);
12785 final_start_function (insn, file, 1);
12786 final (insn, file, 1, 0);
12787 final_end_function ();
12789 reload_completed = 0;
12790 epilogue_completed = 0;
12791 no_new_pseudos = 0;
12794 /* A quick summary of the various types of 'constant-pool tables'
12797 Target Flags Name One table per
12798 AIX (none) AIX TOC object file
12799 AIX -mfull-toc AIX TOC object file
12800 AIX -mminimal-toc AIX minimal TOC translation unit
12801 SVR4/EABI (none) SVR4 SDATA object file
12802 SVR4/EABI -fpic SVR4 pic object file
12803 SVR4/EABI -fPIC SVR4 PIC translation unit
12804 SVR4/EABI -mrelocatable EABI TOC function
12805 SVR4/EABI -maix AIX TOC object file
12806 SVR4/EABI -maix -mminimal-toc
12807 AIX minimal TOC translation unit
12809 Name Reg. Set by entries contains:
12810 made by addrs? fp? sum?
12812 AIX TOC 2 crt0 as Y option option
12813 AIX minimal TOC 30 prolog gcc Y Y option
12814 SVR4 SDATA 13 crt0 gcc N Y N
12815 SVR4 pic 30 prolog ld Y not yet N
12816 SVR4 PIC 30 prolog gcc Y option option
12817 EABI TOC 30 prolog gcc Y option option
12821 /* Hash functions for the hash table. */
12824 rs6000_hash_constant (rtx k)
12826 enum rtx_code code = GET_CODE (k);
12827 enum machine_mode mode = GET_MODE (k);
12828 unsigned result = (code << 3) ^ mode;
12829 const char *format;
12832 format = GET_RTX_FORMAT (code);
12833 flen = strlen (format);
12839 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
12842 if (mode != VOIDmode)
12843 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
12855 for (; fidx < flen; fidx++)
12856 switch (format[fidx])
12861 const char *str = XSTR (k, fidx);
12862 len = strlen (str);
12863 result = result * 613 + len;
12864 for (i = 0; i < len; i++)
12865 result = result * 613 + (unsigned) str[i];
12870 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
12874 result = result * 613 + (unsigned) XINT (k, fidx);
12877 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
12878 result = result * 613 + (unsigned) XWINT (k, fidx);
12882 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
12883 result = result * 613 + (unsigned) (XWINT (k, fidx)
12897 toc_hash_function (const void *hash_entry)
12899 const struct toc_hash_struct *thc =
12900 (const struct toc_hash_struct *) hash_entry;
12901 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
12904 /* Compare H1 and H2 for equivalence. */
12907 toc_hash_eq (const void *h1, const void *h2)
12909 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
12910 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
12912 if (((const struct toc_hash_struct *) h1)->key_mode
12913 != ((const struct toc_hash_struct *) h2)->key_mode)
12916 return rtx_equal_p (r1, r2);
12919 /* These are the names given by the C++ front-end to vtables, and
12920 vtable-like objects. Ideally, this logic should not be here;
12921 instead, there should be some programmatic way of inquiring as
12922 to whether or not an object is a vtable. */
12924 #define VTABLE_NAME_P(NAME) \
12925 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
12926 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
12927 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
12928 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
12931 rs6000_output_symbol_ref (FILE *file, rtx x)
12933 /* Currently C++ toc references to vtables can be emitted before it
12934 is decided whether the vtable is public or private. If this is
12935 the case, then the linker will eventually complain that there is
12936 a reference to an unknown section. Thus, for vtables only,
12937 we emit the TOC reference to reference the symbol and not the
12939 const char *name = XSTR (x, 0);
12941 if (VTABLE_NAME_P (name))
12943 RS6000_OUTPUT_BASENAME (file, name);
12946 assemble_name (file, name);
12949 /* Output a TOC entry. We derive the entry name from what is being
12953 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
12956 const char *name = buf;
12957 const char *real_name;
12964 /* When the linker won't eliminate them, don't output duplicate
12965 TOC entries (this happens on AIX if there is any kind of TOC,
12966 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
12968 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
12970 struct toc_hash_struct *h;
12973 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
12974 time because GGC is not initialized at that point. */
12975 if (toc_hash_table == NULL)
12976 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
12977 toc_hash_eq, NULL);
12979 h = ggc_alloc (sizeof (*h));
12981 h->key_mode = mode;
12982 h->labelno = labelno;
12984 found = htab_find_slot (toc_hash_table, h, 1);
12985 if (*found == NULL)
12987 else /* This is indeed a duplicate.
12988 Set this label equal to that label. */
12990 fputs ("\t.set ", file);
12991 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
12992 fprintf (file, "%d,", labelno);
12993 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
12994 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
13000 /* If we're going to put a double constant in the TOC, make sure it's
13001 aligned properly when strict alignment is on. */
13002 if (GET_CODE (x) == CONST_DOUBLE
13003 && STRICT_ALIGNMENT
13004 && GET_MODE_BITSIZE (mode) >= 64
13005 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
13006 ASM_OUTPUT_ALIGN (file, 3);
13009 (*targetm.asm_out.internal_label) (file, "LC", labelno);
13011 /* Handle FP constants specially. Note that if we have a minimal
13012 TOC, things we put here aren't actually in the TOC, so we can allow
13014 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
13016 REAL_VALUE_TYPE rv;
13019 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13020 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
13024 if (TARGET_MINIMAL_TOC)
13025 fputs (DOUBLE_INT_ASM_OP, file);
13027 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13028 k[0] & 0xffffffff, k[1] & 0xffffffff,
13029 k[2] & 0xffffffff, k[3] & 0xffffffff);
13030 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
13031 k[0] & 0xffffffff, k[1] & 0xffffffff,
13032 k[2] & 0xffffffff, k[3] & 0xffffffff);
13037 if (TARGET_MINIMAL_TOC)
13038 fputs ("\t.long ", file);
13040 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13041 k[0] & 0xffffffff, k[1] & 0xffffffff,
13042 k[2] & 0xffffffff, k[3] & 0xffffffff);
13043 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
13044 k[0] & 0xffffffff, k[1] & 0xffffffff,
13045 k[2] & 0xffffffff, k[3] & 0xffffffff);
13049 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
13051 REAL_VALUE_TYPE rv;
13054 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13055 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
13059 if (TARGET_MINIMAL_TOC)
13060 fputs (DOUBLE_INT_ASM_OP, file);
13062 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13063 k[0] & 0xffffffff, k[1] & 0xffffffff);
13064 fprintf (file, "0x%lx%08lx\n",
13065 k[0] & 0xffffffff, k[1] & 0xffffffff);
13070 if (TARGET_MINIMAL_TOC)
13071 fputs ("\t.long ", file);
13073 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13074 k[0] & 0xffffffff, k[1] & 0xffffffff);
13075 fprintf (file, "0x%lx,0x%lx\n",
13076 k[0] & 0xffffffff, k[1] & 0xffffffff);
13080 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
13082 REAL_VALUE_TYPE rv;
13085 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13086 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
13090 if (TARGET_MINIMAL_TOC)
13091 fputs (DOUBLE_INT_ASM_OP, file);
13093 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13094 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
13099 if (TARGET_MINIMAL_TOC)
13100 fputs ("\t.long ", file);
13102 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13103 fprintf (file, "0x%lx\n", l & 0xffffffff);
13107 else if (GET_MODE (x) == VOIDmode
13108 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
13110 unsigned HOST_WIDE_INT low;
13111 HOST_WIDE_INT high;
13113 if (GET_CODE (x) == CONST_DOUBLE)
13115 low = CONST_DOUBLE_LOW (x);
13116 high = CONST_DOUBLE_HIGH (x);
13119 #if HOST_BITS_PER_WIDE_INT == 32
13122 high = (low & 0x80000000) ? ~0 : 0;
13126 low = INTVAL (x) & 0xffffffff;
13127 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
13131 /* TOC entries are always Pmode-sized, but since this
13132 is a bigendian machine then if we're putting smaller
13133 integer constants in the TOC we have to pad them.
13134 (This is still a win over putting the constants in
13135 a separate constant pool, because then we'd have
13136 to have both a TOC entry _and_ the actual constant.)
13138 For a 32-bit target, CONST_INT values are loaded and shifted
13139 entirely within `low' and can be stored in one TOC entry. */
13141 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
13142 abort ();/* It would be easy to make this work, but it doesn't now. */
13144 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
13146 #if HOST_BITS_PER_WIDE_INT == 32
13147 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
13148 POINTER_SIZE, &low, &high, 0);
13151 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
13152 high = (HOST_WIDE_INT) low >> 32;
13159 if (TARGET_MINIMAL_TOC)
13160 fputs (DOUBLE_INT_ASM_OP, file);
13162 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13163 (long) high & 0xffffffff, (long) low & 0xffffffff);
13164 fprintf (file, "0x%lx%08lx\n",
13165 (long) high & 0xffffffff, (long) low & 0xffffffff);
13170 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
13172 if (TARGET_MINIMAL_TOC)
13173 fputs ("\t.long ", file);
13175 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13176 (long) high & 0xffffffff, (long) low & 0xffffffff);
13177 fprintf (file, "0x%lx,0x%lx\n",
13178 (long) high & 0xffffffff, (long) low & 0xffffffff);
13182 if (TARGET_MINIMAL_TOC)
13183 fputs ("\t.long ", file);
13185 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
13186 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
13192 if (GET_CODE (x) == CONST)
13194 if (GET_CODE (XEXP (x, 0)) != PLUS)
13197 base = XEXP (XEXP (x, 0), 0);
13198 offset = INTVAL (XEXP (XEXP (x, 0), 1));
13201 if (GET_CODE (base) == SYMBOL_REF)
13202 name = XSTR (base, 0);
13203 else if (GET_CODE (base) == LABEL_REF)
13204 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
13205 else if (GET_CODE (base) == CODE_LABEL)
13206 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
13210 real_name = (*targetm.strip_name_encoding) (name);
13211 if (TARGET_MINIMAL_TOC)
13212 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
13215 fprintf (file, "\t.tc %s", real_name);
13218 fprintf (file, ".N%d", - offset);
13220 fprintf (file, ".P%d", offset);
13222 fputs ("[TC],", file);
13225 /* Currently C++ toc references to vtables can be emitted before it
13226 is decided whether the vtable is public or private. If this is
13227 the case, then the linker will eventually complain that there is
13228 a TOC reference to an unknown section. Thus, for vtables only,
13229 we emit the TOC reference to reference the symbol and not the
13231 if (VTABLE_NAME_P (name))
13233 RS6000_OUTPUT_BASENAME (file, name);
13235 fprintf (file, "%d", offset);
13236 else if (offset > 0)
13237 fprintf (file, "+%d", offset);
13240 output_addr_const (file, x);
13244 /* Output an assembler pseudo-op to write an ASCII string of N characters
13245 starting at P to FILE.
13247 On the RS/6000, we have to do this using the .byte operation and
13248 write out special characters outside the quoted string.
13249 Also, the assembler is broken; very long strings are truncated,
13250 so we must artificially break them up early. */
13253 output_ascii (FILE *file, const char *p, int n)
13256 int i, count_string;
13257 const char *for_string = "\t.byte \"";
13258 const char *for_decimal = "\t.byte ";
13259 const char *to_close = NULL;
13262 for (i = 0; i < n; i++)
13265 if (c >= ' ' && c < 0177)
13268 fputs (for_string, file);
13271 /* Write two quotes to get one. */
13279 for_decimal = "\"\n\t.byte ";
13283 if (count_string >= 512)
13285 fputs (to_close, file);
13287 for_string = "\t.byte \"";
13288 for_decimal = "\t.byte ";
13296 fputs (for_decimal, file);
13297 fprintf (file, "%d", c);
13299 for_string = "\n\t.byte \"";
13300 for_decimal = ", ";
13306 /* Now close the string if we have written one. Then end the line. */
13308 fputs (to_close, file);
13311 /* Generate a unique section name for FILENAME for a section type
13312 represented by SECTION_DESC. Output goes into BUF.
13314 SECTION_DESC can be any string, as long as it is different for each
13315 possible section type.
13317 We name the section in the same manner as xlc. The name begins with an
13318 underscore followed by the filename (after stripping any leading directory
13319 names) with the last period replaced by the string SECTION_DESC. If
13320 FILENAME does not contain a period, SECTION_DESC is appended to the end of
13324 rs6000_gen_section_name (char **buf, const char *filename,
13325 const char *section_desc)
13327 const char *q, *after_last_slash, *last_period = 0;
13331 after_last_slash = filename;
13332 for (q = filename; *q; q++)
13335 after_last_slash = q + 1;
13336 else if (*q == '.')
13340 len = strlen (after_last_slash) + strlen (section_desc) + 2;
13341 *buf = (char *) xmalloc (len);
13346 for (q = after_last_slash; *q; q++)
13348 if (q == last_period)
13350 strcpy (p, section_desc);
13351 p += strlen (section_desc);
13355 else if (ISALNUM (*q))
13359 if (last_period == 0)
13360 strcpy (p, section_desc);
13365 /* Emit profile function. */
13368 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
13370 if (TARGET_PROFILE_KERNEL)
13373 if (DEFAULT_ABI == ABI_AIX)
13375 #ifndef NO_PROFILE_COUNTERS
13376 # define NO_PROFILE_COUNTERS 0
13378 if (NO_PROFILE_COUNTERS)
13379 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
13383 const char *label_name;
13386 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13387 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
13388 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
13390 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
13394 else if (DEFAULT_ABI == ABI_DARWIN)
13396 const char *mcount_name = RS6000_MCOUNT;
13397 int caller_addr_regno = LINK_REGISTER_REGNUM;
13399 /* Be conservative and always set this, at least for now. */
13400 current_function_uses_pic_offset_table = 1;
13403 /* For PIC code, set up a stub and collect the caller's address
13404 from r0, which is where the prologue puts it. */
13405 if (MACHOPIC_INDIRECT)
13407 mcount_name = machopic_stub_name (mcount_name);
13408 if (current_function_uses_pic_offset_table)
13409 caller_addr_regno = 0;
13412 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
13414 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
13418 /* Write function profiler code. */
13421 output_function_profiler (FILE *file, int labelno)
13426 switch (DEFAULT_ABI)
13435 warning ("no profiling of 64-bit code for this ABI");
13438 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13439 fprintf (file, "\tmflr %s\n", reg_names[0]);
13442 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
13443 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13444 reg_names[0], save_lr, reg_names[1]);
13445 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
13446 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
13447 assemble_name (file, buf);
13448 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
13450 else if (flag_pic > 1)
13452 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13453 reg_names[0], save_lr, reg_names[1]);
13454 /* Now, we need to get the address of the label. */
13455 fputs ("\tbl 1f\n\t.long ", file);
13456 assemble_name (file, buf);
13457 fputs ("-.\n1:", file);
13458 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
13459 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
13460 reg_names[0], reg_names[11]);
13461 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
13462 reg_names[0], reg_names[0], reg_names[11]);
13466 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
13467 assemble_name (file, buf);
13468 fputs ("@ha\n", file);
13469 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13470 reg_names[0], save_lr, reg_names[1]);
13471 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
13472 assemble_name (file, buf);
13473 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
13476 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
13477 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13482 if (!TARGET_PROFILE_KERNEL)
13484 /* Don't do anything, done in output_profile_hook (). */
13491 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
13492 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
13494 if (current_function_needs_context)
13496 asm_fprintf (file, "\tstd %s,24(%s)\n",
13497 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13498 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13499 asm_fprintf (file, "\tld %s,24(%s)\n",
13500 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13503 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13511 rs6000_use_dfa_pipeline_interface (void)
13516 /* Power4 load update and store update instructions are cracked into a
13517 load or store and an integer insn which are executed in the same cycle.
13518 Branches have their own dispatch slot which does not count against the
13519 GCC issue rate, but it changes the program flow so there are no other
13520 instructions to issue in this cycle. */
13523 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
13524 int verbose ATTRIBUTE_UNUSED,
13525 rtx insn, int more)
13527 if (GET_CODE (PATTERN (insn)) == USE
13528 || GET_CODE (PATTERN (insn)) == CLOBBER)
13531 if (rs6000_cpu == PROCESSOR_POWER4)
13533 if (is_microcoded_insn (insn))
13535 else if (is_cracked_insn (insn))
13536 return more > 2 ? more - 2 : 0;
13542 /* Adjust the cost of a scheduling dependency. Return the new cost of
13543 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
13546 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED,
13549 if (! recog_memoized (insn))
13552 if (REG_NOTE_KIND (link) != 0)
13555 if (REG_NOTE_KIND (link) == 0)
13557 /* Data dependency; DEP_INSN writes a register that INSN reads
13558 some cycles later. */
13559 switch (get_attr_type (insn))
13562 /* Tell the first scheduling pass about the latency between
13563 a mtctr and bctr (and mtlr and br/blr). The first
13564 scheduling pass will not know about this latency since
13565 the mtctr instruction, which has the latency associated
13566 to it, will be generated by reload. */
13567 return TARGET_POWER ? 5 : 4;
13569 /* Leave some extra cycles between a compare and its
13570 dependent branch, to inhibit expensive mispredicts. */
13571 if ((rs6000_cpu_attr == CPU_PPC603
13572 || rs6000_cpu_attr == CPU_PPC604
13573 || rs6000_cpu_attr == CPU_PPC604E
13574 || rs6000_cpu_attr == CPU_PPC620
13575 || rs6000_cpu_attr == CPU_PPC630
13576 || rs6000_cpu_attr == CPU_PPC750
13577 || rs6000_cpu_attr == CPU_PPC7400
13578 || rs6000_cpu_attr == CPU_PPC7450
13579 || rs6000_cpu_attr == CPU_POWER4)
13580 && recog_memoized (dep_insn)
13581 && (INSN_CODE (dep_insn) >= 0)
13582 && (get_attr_type (dep_insn) == TYPE_CMP
13583 || get_attr_type (dep_insn) == TYPE_COMPARE
13584 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
13585 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
13586 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
13587 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
13588 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
13589 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
13594 /* Fall out to return default cost. */
13600 /* The function returns a true if INSN is microcoded.
13601 Return false otherwise. */
13604 is_microcoded_insn (rtx insn)
13606 if (!insn || !INSN_P (insn)
13607 || GET_CODE (PATTERN (insn)) == USE
13608 || GET_CODE (PATTERN (insn)) == CLOBBER)
13611 if (rs6000_cpu == PROCESSOR_POWER4)
13613 enum attr_type type = get_attr_type (insn);
13614 if (type == TYPE_LOAD_EXT_U
13615 || type == TYPE_LOAD_EXT_UX
13616 || type == TYPE_LOAD_UX
13617 || type == TYPE_STORE_UX
13618 || type == TYPE_MFCR)
13625 /* The function returns a nonzero value if INSN can be scheduled only
13626 as the first insn in a dispatch group ("dispatch-slot restricted").
13627 In this case, the returned value indicates how many dispatch slots
13628 the insn occupies (at the beginning of the group).
13629 Return 0 otherwise. */
13632 is_dispatch_slot_restricted (rtx insn)
13634 enum attr_type type;
13636 if (rs6000_cpu != PROCESSOR_POWER4)
13640 || insn == NULL_RTX
13641 || GET_CODE (insn) == NOTE
13642 || GET_CODE (PATTERN (insn)) == USE
13643 || GET_CODE (PATTERN (insn)) == CLOBBER)
13646 type = get_attr_type (insn);
13652 case TYPE_DELAYED_CR:
13653 case TYPE_CR_LOGICAL:
13665 /* The function returns true if INSN is cracked into 2 instructions
13666 by the processor (and therefore occupies 2 issue slots). */
13669 is_cracked_insn (rtx insn)
13671 if (!insn || !INSN_P (insn)
13672 || GET_CODE (PATTERN (insn)) == USE
13673 || GET_CODE (PATTERN (insn)) == CLOBBER)
13676 if (rs6000_cpu == PROCESSOR_POWER4)
13678 enum attr_type type = get_attr_type (insn);
13679 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
13680 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
13681 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
13682 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
13683 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
13684 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
13685 || type == TYPE_IDIV || type == TYPE_LDIV
13686 || type == TYPE_INSERT_WORD)
13693 /* The function returns true if INSN can be issued only from
13694 the branch slot. */
13697 is_branch_slot_insn (rtx insn)
13699 if (!insn || !INSN_P (insn)
13700 || GET_CODE (PATTERN (insn)) == USE
13701 || GET_CODE (PATTERN (insn)) == CLOBBER)
13704 if (rs6000_cpu == PROCESSOR_POWER4)
13706 enum attr_type type = get_attr_type (insn);
13707 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
13715 /* A C statement (sans semicolon) to update the integer scheduling
13716 priority INSN_PRIORITY (INSN). Increase the priority to execute the
13717 INSN earlier, reduce the priority to execute INSN later. Do not
13718 define this macro if you do not need to adjust the scheduling
13719 priorities of insns. */
13722 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
13724 /* On machines (like the 750) which have asymmetric integer units,
13725 where one integer unit can do multiply and divides and the other
13726 can't, reduce the priority of multiply/divide so it is scheduled
13727 before other integer operations. */
13730 if (! INSN_P (insn))
13733 if (GET_CODE (PATTERN (insn)) == USE)
13736 switch (rs6000_cpu_attr) {
13738 switch (get_attr_type (insn))
13745 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
13746 priority, priority);
13747 if (priority >= 0 && priority < 0x01000000)
13754 if (is_dispatch_slot_restricted (insn)
13755 && reload_completed
13756 && current_sched_info->sched_max_insns_priority
13757 && rs6000_sched_restricted_insns_priority)
13760 /* Prioritize insns that can be dispatched only in the first dispatch slot. */
13761 if (rs6000_sched_restricted_insns_priority == 1)
13762 /* Attach highest priority to insn. This means that in
13763 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
13764 precede 'priority' (critical path) considerations. */
13765 return current_sched_info->sched_max_insns_priority;
13766 else if (rs6000_sched_restricted_insns_priority == 2)
13767 /* Increase priority of insn by a minimal amount. This means that in
13768 haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations
13769 precede dispatch-slot restriction considerations. */
13770 return (priority + 1);
13776 /* Return how many instructions the machine can issue per cycle. */
13779 rs6000_issue_rate (void)
13781 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
13782 if (!reload_completed)
13785 switch (rs6000_cpu_attr) {
13786 case CPU_RIOS1: /* ? */
13788 case CPU_PPC601: /* ? */
13810 /* Return how many instructions to look ahead for better insn
13814 rs6000_use_sched_lookahead (void)
13816 if (rs6000_cpu_attr == CPU_PPC8540)
13821 /* Determine is PAT refers to memory. */
13824 is_mem_ref (rtx pat)
13830 if (GET_CODE (pat) == MEM)
13833 /* Recursively process the pattern. */
13834 fmt = GET_RTX_FORMAT (GET_CODE (pat));
13836 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
13839 ret |= is_mem_ref (XEXP (pat, i));
13840 else if (fmt[i] == 'E')
13841 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
13842 ret |= is_mem_ref (XVECEXP (pat, i, j));
13848 /* Determine if PAT is a PATTERN of a load insn. */
13851 is_load_insn1 (rtx pat)
13853 if (!pat || pat == NULL_RTX)
13856 if (GET_CODE (pat) == SET)
13857 return is_mem_ref (SET_SRC (pat));
13859 if (GET_CODE (pat) == PARALLEL)
13863 for (i = 0; i < XVECLEN (pat, 0); i++)
13864 if (is_load_insn1 (XVECEXP (pat, 0, i)))
13871 /* Determine if INSN loads from memory. */
13874 is_load_insn (rtx insn)
13876 if (!insn || !INSN_P (insn))
13879 if (GET_CODE (insn) == CALL_INSN)
13882 return is_load_insn1 (PATTERN (insn));
13885 /* Determine if PAT is a PATTERN of a store insn. */
13888 is_store_insn1 (rtx pat)
13890 if (!pat || pat == NULL_RTX)
13893 if (GET_CODE (pat) == SET)
13894 return is_mem_ref (SET_DEST (pat));
13896 if (GET_CODE (pat) == PARALLEL)
13900 for (i = 0; i < XVECLEN (pat, 0); i++)
13901 if (is_store_insn1 (XVECEXP (pat, 0, i)))
13908 /* Determine if INSN stores to memory. */
13911 is_store_insn (rtx insn)
13913 if (!insn || !INSN_P (insn))
13916 return is_store_insn1 (PATTERN (insn));
13919 /* Returns whether the dependence between INSN and NEXT is considered
13920 costly by the given target. */
13923 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distance)
13925 /* If the flag is not enbled - no dependence is considered costly;
13926 allow all dependent insns in the same group.
13927 This is the most aggressive option. */
13928 if (rs6000_sched_costly_dep == no_dep_costly)
13931 /* If the flag is set to 1 - a dependence is always considered costly;
13932 do not allow dependent instructions in the same group.
13933 This is the most conservative option. */
13934 if (rs6000_sched_costly_dep == all_deps_costly)
13937 if (rs6000_sched_costly_dep == store_to_load_dep_costly
13938 && is_load_insn (next)
13939 && is_store_insn (insn))
13940 /* Prevent load after store in the same group. */
13943 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
13944 && is_load_insn (next)
13945 && is_store_insn (insn)
13946 && (!link || (int) REG_NOTE_KIND (link) == 0))
13947 /* Prevent load after store in the same group if it is a true dependence. */
13950 /* The flag is set to X; dependences with latency >= X are considered costly,
13951 and will not be scheduled in the same group. */
13952 if (rs6000_sched_costly_dep <= max_dep_latency
13953 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
13959 /* Return the next insn after INSN that is found before TAIL is reached,
13960 skipping any "non-active" insns - insns that will not actually occupy
13961 an issue slot. Return NULL_RTX if such an insn is not found. */
13964 get_next_active_insn (rtx insn, rtx tail)
13968 if (!insn || insn == tail)
13971 next_insn = NEXT_INSN (insn);
13974 && next_insn != tail
13975 && (GET_CODE(next_insn) == NOTE
13976 || GET_CODE (PATTERN (next_insn)) == USE
13977 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
13979 next_insn = NEXT_INSN (next_insn);
13982 if (!next_insn || next_insn == tail)
13988 /* Return whether the presence of INSN causes a dispatch group termination
13989 of group WHICH_GROUP.
13991 If WHICH_GROUP == current_group, this function will return true if INSN
13992 causes the termination of the current group (i.e, the dispatch group to
13993 which INSN belongs). This means that INSN will be the last insn in the
13994 group it belongs to.
13996 If WHICH_GROUP == previous_group, this function will return true if INSN
13997 causes the termination of the previous group (i.e, the dispatch group that
13998 precedes the group to which INSN belongs). This means that INSN will be
13999 the first insn in the group it belongs to). */
14002 insn_terminates_group_p (rtx insn, enum group_termination which_group)
14004 enum attr_type type;
14009 type = get_attr_type (insn);
14011 if (is_microcoded_insn (insn))
14014 if (which_group == current_group)
14016 if (is_branch_slot_insn (insn))
14020 else if (which_group == previous_group)
14022 if (is_dispatch_slot_restricted (insn))
14030 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
14031 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
14034 is_costly_group (rtx *group_insns, rtx next_insn)
14039 int issue_rate = rs6000_issue_rate ();
14041 for (i = 0; i < issue_rate; i++)
14043 rtx insn = group_insns[i];
14046 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
14048 rtx next = XEXP (link, 0);
14049 if (next == next_insn)
14051 cost = insn_cost (insn, link, next_insn);
14052 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
14061 /* Utility of the function redefine_groups.
14062 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
14063 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
14064 to keep it "far" (in a separate group) from GROUP_INSNS, following
14065 one of the following schemes, depending on the value of the flag
14066 -minsert_sched_nops = X:
14067 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
14068 in order to force NEXT_INSN into a separate group.
14069 (2) X < sched_finish_regroup_exact: insert exactly X nops.
14070 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
14071 insertion (has a group just ended, how many vacant issue slots remain in the
14072 last group, and how many dispatch groups were encountered so far). */
14075 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn,
14076 bool *group_end, int can_issue_more, int *group_count)
14080 int issue_rate = rs6000_issue_rate ();
14081 bool end = *group_end;
14084 if (next_insn == NULL_RTX)
14085 return can_issue_more;
14087 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
14088 return can_issue_more;
14090 force = is_costly_group (group_insns, next_insn);
14092 return can_issue_more;
14094 if (sched_verbose > 6)
14095 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
14096 *group_count ,can_issue_more);
14098 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
14101 can_issue_more = 0;
14103 /* Since only a branch can be issued in the last issue_slot, it is
14104 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
14105 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
14106 in this case the last nop will start a new group and the branch will be
14107 forced to the new group. */
14108 if (can_issue_more && !is_branch_slot_insn (next_insn))
14111 while (can_issue_more > 0)
14114 emit_insn_before (nop, next_insn);
14122 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
14124 int n_nops = rs6000_sched_insert_nops;
14126 /* Nops can't be issued from the branch slot, so the effective
14127 issue_rate for nops is 'issue_rate - 1'. */
14128 if (can_issue_more == 0)
14129 can_issue_more = issue_rate;
14131 if (can_issue_more == 0)
14133 can_issue_more = issue_rate - 1;
14136 for (i = 0; i < issue_rate; i++)
14138 group_insns[i] = 0;
14145 emit_insn_before (nop, next_insn);
14146 if (can_issue_more == issue_rate - 1) /* new group begins */
14149 if (can_issue_more == 0)
14151 can_issue_more = issue_rate - 1;
14154 for (i = 0; i < issue_rate; i++)
14156 group_insns[i] = 0;
14162 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
14165 *group_end = /* Is next_insn going to start a new group? */
14167 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14168 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14169 || (can_issue_more < issue_rate &&
14170 insn_terminates_group_p (next_insn, previous_group)));
14171 if (*group_end && end)
14174 if (sched_verbose > 6)
14175 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
14176 *group_count, can_issue_more);
14177 return can_issue_more;
14180 return can_issue_more;
14183 /* This function tries to synch the dispatch groups that the compiler "sees"
14184 with the dispatch groups that the processor dispatcher is expected to
14185 form in practice. It tries to achieve this synchronization by forcing the
14186 estimated processor grouping on the compiler (as opposed to the function
14187 'pad_goups' which tries to force the scheduler's grouping on the processor).
14189 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
14190 examines the (estimated) dispatch groups that will be formed by the processor
14191 dispatcher. It marks these group boundaries to reflect the estimated
14192 processor grouping, overriding the grouping that the scheduler had marked.
14193 Depending on the value of the flag '-minsert-sched-nops' this function can
14194 force certain insns into separate groups or force a certain distance between
14195 them by inserting nops, for example, if there exists a "costly dependence"
14198 The function estimates the group boundaries that the processor will form as
14199 folllows: It keeps track of how many vacant issue slots are available after
14200 each insn. A subsequent insn will start a new group if one of the following
14202 - no more vacant issue slots remain in the current dispatch group.
14203 - only the last issue slot, which is the branch slot, is vacant, but the next
14204 insn is not a branch.
14205 - only the last 2 or less issue slots, including the branch slot, are vacant,
14206 which means that a cracked insn (which occupies two issue slots) can't be
14207 issued in this group.
14208 - less than 'issue_rate' slots are vacant, and the next insn always needs to
14209 start a new group. */
14212 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14214 rtx insn, next_insn;
14216 int can_issue_more;
14219 int group_count = 0;
14223 issue_rate = rs6000_issue_rate ();
14224 group_insns = alloca (issue_rate * sizeof (rtx));
14225 for (i = 0; i < issue_rate; i++)
14227 group_insns[i] = 0;
14229 can_issue_more = issue_rate;
14231 insn = get_next_active_insn (prev_head_insn, tail);
14234 while (insn != NULL_RTX)
14236 slot = (issue_rate - can_issue_more);
14237 group_insns[slot] = insn;
14239 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14240 if (insn_terminates_group_p (insn, current_group))
14241 can_issue_more = 0;
14243 next_insn = get_next_active_insn (insn, tail);
14244 if (next_insn == NULL_RTX)
14245 return group_count + 1;
14247 group_end = /* Is next_insn going to start a new group? */
14248 (can_issue_more == 0
14249 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14250 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14251 || (can_issue_more < issue_rate &&
14252 insn_terminates_group_p (next_insn, previous_group)));
14254 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
14255 next_insn, &group_end, can_issue_more, &group_count);
14260 can_issue_more = 0;
14261 for (i = 0; i < issue_rate; i++)
14263 group_insns[i] = 0;
14267 if (GET_MODE (next_insn) == TImode && can_issue_more)
14268 PUT_MODE(next_insn, VOIDmode);
14269 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
14270 PUT_MODE (next_insn, TImode);
14273 if (can_issue_more == 0)
14274 can_issue_more = issue_rate;
14277 return group_count;
14280 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
14281 dispatch group boundaries that the scheduler had marked. Pad with nops
14282 any dispatch groups which have vacant issue slots, in order to force the
14283 scheduler's grouping on the processor dispatcher. The function
14284 returns the number of dispatch groups found. */
14287 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14289 rtx insn, next_insn;
14292 int can_issue_more;
14294 int group_count = 0;
14296 /* Initialize issue_rate. */
14297 issue_rate = rs6000_issue_rate ();
14298 can_issue_more = issue_rate;
14300 insn = get_next_active_insn (prev_head_insn, tail);
14301 next_insn = get_next_active_insn (insn, tail);
14303 while (insn != NULL_RTX)
14306 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14308 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
14310 if (next_insn == NULL_RTX)
14315 /* If the scheduler had marked group termination at this location
14316 (between insn and next_indn), and neither insn nor next_insn will
14317 force group termination, pad the group with nops to force group
14320 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
14321 && !insn_terminates_group_p (insn, current_group)
14322 && !insn_terminates_group_p (next_insn, previous_group))
14324 if (!is_branch_slot_insn(next_insn))
14327 while (can_issue_more)
14330 emit_insn_before (nop, next_insn);
14335 can_issue_more = issue_rate;
14340 next_insn = get_next_active_insn (insn, tail);
14343 return group_count;
14346 /* The following function is called at the end of scheduling BB.
14347 After reload, it inserts nops at insn group bundling. */
14350 rs6000_sched_finish (FILE *dump, int sched_verbose)
14355 fprintf (dump, "=== Finishing schedule.\n");
14357 if (reload_completed && rs6000_cpu == PROCESSOR_POWER4)
14359 if (rs6000_sched_insert_nops == sched_finish_none)
14362 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
14363 n_groups = pad_groups (dump, sched_verbose,
14364 current_sched_info->prev_head,
14365 current_sched_info->next_tail);
14367 n_groups = redefine_groups (dump, sched_verbose,
14368 current_sched_info->prev_head,
14369 current_sched_info->next_tail);
14371 if (sched_verbose >= 6)
14373 fprintf (dump, "ngroups = %d\n", n_groups);
14374 print_rtl (dump, current_sched_info->prev_head);
14375 fprintf (dump, "Done finish_sched\n");
14380 /* Length in units of the trampoline for entering a nested function. */
14383 rs6000_trampoline_size (void)
14387 switch (DEFAULT_ABI)
14393 ret = (TARGET_32BIT) ? 12 : 24;
14398 ret = (TARGET_32BIT) ? 40 : 48;
14405 /* Emit RTL insns to initialize the variable parts of a trampoline.
14406 FNADDR is an RTX for the address of the function's pure code.
14407 CXT is an RTX for the static chain value for the function. */
14410 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
14412 enum machine_mode pmode = Pmode;
14413 int regsize = (TARGET_32BIT) ? 4 : 8;
14414 rtx ctx_reg = force_reg (pmode, cxt);
14416 switch (DEFAULT_ABI)
14421 /* Macros to shorten the code expansions below. */
14422 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
14423 #define MEM_PLUS(addr,offset) \
14424 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
14426 /* Under AIX, just build the 3 word function descriptor */
14429 rtx fn_reg = gen_reg_rtx (pmode);
14430 rtx toc_reg = gen_reg_rtx (pmode);
14431 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
14432 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
14433 emit_move_insn (MEM_DEREF (addr), fn_reg);
14434 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
14435 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
14439 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
14442 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
14443 FALSE, VOIDmode, 4,
14445 GEN_INT (rs6000_trampoline_size ()), SImode,
14455 /* Table of valid machine attributes. */
14457 const struct attribute_spec rs6000_attribute_table[] =
14459 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
14460 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
14461 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
14462 { NULL, 0, 0, false, false, false, NULL }
14465 /* Handle a "longcall" or "shortcall" attribute; arguments as in
14466 struct attribute_spec.handler. */
14469 rs6000_handle_longcall_attribute (tree *node, tree name,
14470 tree args ATTRIBUTE_UNUSED,
14471 int flags ATTRIBUTE_UNUSED,
14472 bool *no_add_attrs)
14474 if (TREE_CODE (*node) != FUNCTION_TYPE
14475 && TREE_CODE (*node) != FIELD_DECL
14476 && TREE_CODE (*node) != TYPE_DECL)
14478 warning ("`%s' attribute only applies to functions",
14479 IDENTIFIER_POINTER (name));
14480 *no_add_attrs = true;
14486 /* Set longcall attributes on all functions declared when
14487 rs6000_default_long_calls is true. */
14489 rs6000_set_default_type_attributes (tree type)
14491 if (rs6000_default_long_calls
14492 && (TREE_CODE (type) == FUNCTION_TYPE
14493 || TREE_CODE (type) == METHOD_TYPE))
14494 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
14496 TYPE_ATTRIBUTES (type));
14499 /* Return a reference suitable for calling a function with the
14500 longcall attribute. */
14503 rs6000_longcall_ref (rtx call_ref)
14505 const char *call_name;
14508 if (GET_CODE (call_ref) != SYMBOL_REF)
14511 /* System V adds '.' to the internal name, so skip them. */
14512 call_name = XSTR (call_ref, 0);
14513 if (*call_name == '.')
14515 while (*call_name == '.')
14518 node = get_identifier (call_name);
14519 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
14522 return force_reg (Pmode, call_ref);
14525 #ifdef USING_ELFOS_H
14527 /* A C statement or statements to switch to the appropriate section
14528 for output of RTX in mode MODE. You can assume that RTX is some
14529 kind of constant in RTL. The argument MODE is redundant except in
14530 the case of a `const_int' rtx. Select the section by calling
14531 `text_section' or one of the alternatives for other sections.
14533 Do not define this macro if you put all constants in the read-only
14537 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
14538 unsigned HOST_WIDE_INT align)
14540 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
14543 default_elf_select_rtx_section (mode, x, align);
14546 /* A C statement or statements to switch to the appropriate
14547 section for output of DECL. DECL is either a `VAR_DECL' node
14548 or a constant of some sort. RELOC indicates whether forming
14549 the initial value of DECL requires link-time relocations. */
14552 rs6000_elf_select_section (tree decl, int reloc,
14553 unsigned HOST_WIDE_INT align)
14555 /* Pretend that we're always building for a shared library when
14556 ABI_AIX, because otherwise we end up with dynamic relocations
14557 in read-only sections. This happens for function pointers,
14558 references to vtables in typeinfo, and probably other cases. */
14559 default_elf_select_section_1 (decl, reloc, align,
14560 flag_pic || DEFAULT_ABI == ABI_AIX);
14563 /* A C statement to build up a unique section name, expressed as a
14564 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
14565 RELOC indicates whether the initial value of EXP requires
14566 link-time relocations. If you do not define this macro, GCC will use
14567 the symbol name prefixed by `.' as the section name. Note - this
14568 macro can now be called for uninitialized data items as well as
14569 initialized data and functions. */
14572 rs6000_elf_unique_section (tree decl, int reloc)
14574 /* As above, pretend that we're always building for a shared library
14575 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
14576 default_unique_section_1 (decl, reloc,
14577 flag_pic || DEFAULT_ABI == ABI_AIX);
14580 /* For a SYMBOL_REF, set generic flags and then perform some
14581 target-specific processing.
14583 When the AIX ABI is requested on a non-AIX system, replace the
14584 function name with the real name (with a leading .) rather than the
14585 function descriptor name. This saves a lot of overriding code to
14586 read the prefixes. */
14589 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
14591 default_encode_section_info (decl, rtl, first);
14594 && TREE_CODE (decl) == FUNCTION_DECL
14596 && DEFAULT_ABI == ABI_AIX)
14598 rtx sym_ref = XEXP (rtl, 0);
14599 size_t len = strlen (XSTR (sym_ref, 0));
14600 char *str = alloca (len + 2);
14602 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
14603 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
14608 rs6000_elf_in_small_data_p (tree decl)
14610 if (rs6000_sdata == SDATA_NONE)
14613 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
14615 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
14616 if (strcmp (section, ".sdata") == 0
14617 || strcmp (section, ".sdata2") == 0
14618 || strcmp (section, ".sbss") == 0
14619 || strcmp (section, ".sbss2") == 0
14620 || strcmp (section, ".PPC.EMB.sdata0") == 0
14621 || strcmp (section, ".PPC.EMB.sbss0") == 0)
14626 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
14629 && (unsigned HOST_WIDE_INT) size <= g_switch_value
14630 /* If it's not public, and we're not going to reference it there,
14631 there's no need to put it in the small data section. */
14632 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
14639 #endif /* USING_ELFOS_H */
14642 /* Return a REG that occurs in ADDR with coefficient 1.
14643 ADDR can be effectively incremented by incrementing REG.
14645 r0 is special and we must not select it as an address
14646 register by this routine since our caller will try to
14647 increment the returned register via an "la" instruction. */
14650 find_addr_reg (rtx addr)
14652 while (GET_CODE (addr) == PLUS)
14654 if (GET_CODE (XEXP (addr, 0)) == REG
14655 && REGNO (XEXP (addr, 0)) != 0)
14656 addr = XEXP (addr, 0);
14657 else if (GET_CODE (XEXP (addr, 1)) == REG
14658 && REGNO (XEXP (addr, 1)) != 0)
14659 addr = XEXP (addr, 1);
14660 else if (CONSTANT_P (XEXP (addr, 0)))
14661 addr = XEXP (addr, 1);
14662 else if (CONSTANT_P (XEXP (addr, 1)))
14663 addr = XEXP (addr, 0);
14667 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
14673 rs6000_fatal_bad_address (rtx op)
14675 fatal_insn ("bad address", op);
14681 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
14682 reference and a constant. */
14685 symbolic_operand (rtx op)
14687 switch (GET_CODE (op))
14694 return (GET_CODE (op) == SYMBOL_REF ||
14695 (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
14696 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
14697 && GET_CODE (XEXP (op, 1)) == CONST_INT);
14706 static tree branch_island_list = 0;
14708 /* Remember to generate a branch island for far calls to the given
14712 add_compiler_branch_island (tree label_name, tree function_name, int line_number)
14714 tree branch_island = build_tree_list (function_name, label_name);
14715 TREE_TYPE (branch_island) = build_int_2 (line_number, 0);
14716 TREE_CHAIN (branch_island) = branch_island_list;
14717 branch_island_list = branch_island;
14720 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
14721 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
14722 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
14723 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
14725 /* Generate far-jump branch islands for everything on the
14726 branch_island_list. Invoked immediately after the last instruction
14727 of the epilogue has been emitted; the branch-islands must be
14728 appended to, and contiguous with, the function body. Mach-O stubs
14729 are generated in machopic_output_stub(). */
14732 macho_branch_islands (void)
14735 tree branch_island;
14737 for (branch_island = branch_island_list;
14739 branch_island = TREE_CHAIN (branch_island))
14741 const char *label =
14742 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
14744 darwin_strip_name_encoding (
14745 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)));
14746 char name_buf[512];
14747 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
14748 if (name[0] == '*' || name[0] == '&')
14749 strcpy (name_buf, name+1);
14753 strcpy (name_buf+1, name);
14755 strcpy (tmp_buf, "\n");
14756 strcat (tmp_buf, label);
14757 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
14758 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
14759 fprintf (asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
14760 BRANCH_ISLAND_LINE_NUMBER(branch_island));
14761 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
14764 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
14765 strcat (tmp_buf, label);
14766 strcat (tmp_buf, "_pic\n");
14767 strcat (tmp_buf, label);
14768 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
14770 strcat (tmp_buf, "\taddis r11,r11,ha16(");
14771 strcat (tmp_buf, name_buf);
14772 strcat (tmp_buf, " - ");
14773 strcat (tmp_buf, label);
14774 strcat (tmp_buf, "_pic)\n");
14776 strcat (tmp_buf, "\tmtlr r0\n");
14778 strcat (tmp_buf, "\taddi r12,r11,lo16(");
14779 strcat (tmp_buf, name_buf);
14780 strcat (tmp_buf, " - ");
14781 strcat (tmp_buf, label);
14782 strcat (tmp_buf, "_pic)\n");
14784 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
14788 strcat (tmp_buf, ":\nlis r12,hi16(");
14789 strcat (tmp_buf, name_buf);
14790 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
14791 strcat (tmp_buf, name_buf);
14792 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
14794 output_asm_insn (tmp_buf, 0);
14795 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
14796 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
14797 fprintf(asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
14798 BRANCH_ISLAND_LINE_NUMBER (branch_island));
14799 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
14802 branch_island_list = 0;
14805 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
14806 already there or not. */
14809 no_previous_def (tree function_name)
14811 tree branch_island;
14812 for (branch_island = branch_island_list;
14814 branch_island = TREE_CHAIN (branch_island))
14815 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
14820 /* GET_PREV_LABEL gets the label name from the previous definition of
14824 get_prev_label (tree function_name)
14826 tree branch_island;
14827 for (branch_island = branch_island_list;
14829 branch_island = TREE_CHAIN (branch_island))
14830 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
14831 return BRANCH_ISLAND_LABEL_NAME (branch_island);
14835 /* INSN is either a function call or a millicode call. It may have an
14836 unconditional jump in its delay slot.
14838 CALL_DEST is the routine we are calling. */
14841 output_call (rtx insn, rtx *operands, int dest_operand_number, int cookie_operand_number)
14843 static char buf[256];
14844 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
14845 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
14848 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
14850 if (no_previous_def (funname))
14852 int line_number = 0;
14853 rtx label_rtx = gen_label_rtx ();
14854 char *label_buf, temp_buf[256];
14855 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
14856 CODE_LABEL_NUMBER (label_rtx));
14857 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
14858 labelname = get_identifier (label_buf);
14859 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
14861 line_number = NOTE_LINE_NUMBER (insn);
14862 add_compiler_branch_island (labelname, funname, line_number);
14865 labelname = get_prev_label (funname);
14867 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
14868 instruction will reach 'foo', otherwise link as 'bl L42'".
14869 "L42" should be a 'branch island', that will do a far jump to
14870 'foo'. Branch islands are generated in
14871 macho_branch_islands(). */
14872 sprintf (buf, "jbsr %%z%d,%.246s",
14873 dest_operand_number, IDENTIFIER_POINTER (labelname));
14876 sprintf (buf, "bl %%z%d", dest_operand_number);
14880 #endif /* TARGET_MACHO */
14882 /* Generate PIC and indirect symbol stubs. */
14885 machopic_output_stub (FILE *file, const char *symb, const char *stub)
14887 unsigned int length;
14888 char *symbol_name, *lazy_ptr_name;
14889 char *local_label_0;
14890 static int label = 0;
14892 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
14893 symb = (*targetm.strip_name_encoding) (symb);
14896 length = strlen (symb);
14897 symbol_name = alloca (length + 32);
14898 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
14900 lazy_ptr_name = alloca (length + 32);
14901 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
14904 machopic_picsymbol_stub1_section ();
14906 machopic_symbol_stub1_section ();
14907 fprintf (file, "\t.align 2\n");
14909 fprintf (file, "%s:\n", stub);
14910 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
14915 local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
14916 sprintf (local_label_0, "\"L%011d$spb\"", label);
14918 fprintf (file, "\tmflr r0\n");
14919 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
14920 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
14921 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
14922 lazy_ptr_name, local_label_0);
14923 fprintf (file, "\tmtlr r0\n");
14924 fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n",
14925 lazy_ptr_name, local_label_0);
14926 fprintf (file, "\tmtctr r12\n");
14927 fprintf (file, "\tbctr\n");
14931 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
14932 fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
14933 fprintf (file, "\tmtctr r12\n");
14934 fprintf (file, "\tbctr\n");
14937 machopic_lazy_symbol_ptr_section ();
14938 fprintf (file, "%s:\n", lazy_ptr_name);
14939 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
14940 fprintf (file, "\t.long dyld_stub_binding_helper\n");
14943 /* Legitimize PIC addresses. If the address is already
14944 position-independent, we return ORIG. Newly generated
14945 position-independent addresses go into a reg. This is REG if non
14946 zero, otherwise we allocate register(s) as necessary. */
14948 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
14951 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
14956 if (reg == NULL && ! reload_in_progress && ! reload_completed)
14957 reg = gen_reg_rtx (Pmode);
14959 if (GET_CODE (orig) == CONST)
14961 if (GET_CODE (XEXP (orig, 0)) == PLUS
14962 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
14965 if (GET_CODE (XEXP (orig, 0)) == PLUS)
14967 /* Use a different reg for the intermediate value, as
14968 it will be marked UNCHANGING. */
14969 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
14972 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
14975 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
14981 if (GET_CODE (offset) == CONST_INT)
14983 if (SMALL_INT (offset))
14984 return plus_constant (base, INTVAL (offset));
14985 else if (! reload_in_progress && ! reload_completed)
14986 offset = force_reg (Pmode, offset);
14989 rtx mem = force_const_mem (Pmode, orig);
14990 return machopic_legitimize_pic_address (mem, Pmode, reg);
14993 return gen_rtx (PLUS, Pmode, base, offset);
14996 /* Fall back on generic machopic code. */
14997 return machopic_legitimize_pic_address (orig, mode, reg);
15000 /* This is just a placeholder to make linking work without having to
15001 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
15002 ever needed for Darwin (not too likely!) this would have to get a
15003 real definition. */
15010 #endif /* TARGET_MACHO */
15013 static unsigned int
15014 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
15016 return default_section_type_flags_1 (decl, name, reloc,
15017 flag_pic || DEFAULT_ABI == ABI_AIX);
15020 /* Record an element in the table of global constructors. SYMBOL is
15021 a SYMBOL_REF of the function to be called; PRIORITY is a number
15022 between 0 and MAX_INIT_PRIORITY.
15024 This differs from default_named_section_asm_out_constructor in
15025 that we have special handling for -mrelocatable. */
15028 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
15030 const char *section = ".ctors";
15033 if (priority != DEFAULT_INIT_PRIORITY)
15035 sprintf (buf, ".ctors.%.5u",
15036 /* Invert the numbering so the linker puts us in the proper
15037 order; constructors are run from right to left, and the
15038 linker sorts in increasing order. */
15039 MAX_INIT_PRIORITY - priority);
15043 named_section_flags (section, SECTION_WRITE);
15044 assemble_align (POINTER_SIZE);
15046 if (TARGET_RELOCATABLE)
15048 fputs ("\t.long (", asm_out_file);
15049 output_addr_const (asm_out_file, symbol);
15050 fputs (")@fixup\n", asm_out_file);
15053 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15057 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
15059 const char *section = ".dtors";
15062 if (priority != DEFAULT_INIT_PRIORITY)
15064 sprintf (buf, ".dtors.%.5u",
15065 /* Invert the numbering so the linker puts us in the proper
15066 order; constructors are run from right to left, and the
15067 linker sorts in increasing order. */
15068 MAX_INIT_PRIORITY - priority);
15072 named_section_flags (section, SECTION_WRITE);
15073 assemble_align (POINTER_SIZE);
15075 if (TARGET_RELOCATABLE)
15077 fputs ("\t.long (", asm_out_file);
15078 output_addr_const (asm_out_file, symbol);
15079 fputs (")@fixup\n", asm_out_file);
15082 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15086 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
15090 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
15091 ASM_OUTPUT_LABEL (file, name);
15092 fputs (DOUBLE_INT_ASM_OP, file);
15094 assemble_name (file, name);
15095 fputs (",.TOC.@tocbase,0\n\t.previous\n\t.size\t", file);
15096 assemble_name (file, name);
15097 fputs (",24\n\t.type\t.", file);
15098 assemble_name (file, name);
15099 fputs (",@function\n", file);
15100 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
15102 fputs ("\t.globl\t.", file);
15103 assemble_name (file, name);
15106 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15108 ASM_OUTPUT_LABEL (file, name);
15112 if (TARGET_RELOCATABLE
15113 && (get_pool_size () != 0 || current_function_profile)
15118 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
15120 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
15121 fprintf (file, "\t.long ");
15122 assemble_name (file, buf);
15124 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15125 assemble_name (file, buf);
15129 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
15130 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15132 if (DEFAULT_ABI == ABI_AIX)
15134 const char *desc_name, *orig_name;
15136 orig_name = (*targetm.strip_name_encoding) (name);
15137 desc_name = orig_name;
15138 while (*desc_name == '.')
15141 if (TREE_PUBLIC (decl))
15142 fprintf (file, "\t.globl %s\n", desc_name);
15144 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
15145 fprintf (file, "%s:\n", desc_name);
15146 fprintf (file, "\t.long %s\n", orig_name);
15147 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
15148 if (DEFAULT_ABI == ABI_AIX)
15149 fputs ("\t.long 0\n", file);
15150 fprintf (file, "\t.previous\n");
15152 ASM_OUTPUT_LABEL (file, name);
15158 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
15160 fputs (GLOBAL_ASM_OP, stream);
15161 RS6000_OUTPUT_BASENAME (stream, name);
15162 putc ('\n', stream);
15166 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags)
15169 static const char * const suffix[3] = { "PR", "RO", "RW" };
15171 if (flags & SECTION_CODE)
15173 else if (flags & SECTION_WRITE)
15178 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
15179 (flags & SECTION_CODE) ? "." : "",
15180 name, suffix[smclass], flags & SECTION_ENTSIZE);
15184 rs6000_xcoff_select_section (tree decl, int reloc,
15185 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15187 if (decl_readonly_section_1 (decl, reloc, 1))
15189 if (TREE_PUBLIC (decl))
15190 read_only_data_section ();
15192 read_only_private_data_section ();
15196 if (TREE_PUBLIC (decl))
15199 private_data_section ();
15204 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
15208 /* Use select_section for private and uninitialized data. */
15209 if (!TREE_PUBLIC (decl)
15210 || DECL_COMMON (decl)
15211 || DECL_INITIAL (decl) == NULL_TREE
15212 || DECL_INITIAL (decl) == error_mark_node
15213 || (flag_zero_initialized_in_bss
15214 && initializer_zerop (DECL_INITIAL (decl))))
15217 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
15218 name = (*targetm.strip_name_encoding) (name);
15219 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
15222 /* Select section for constant in constant pool.
15224 On RS/6000, all constants are in the private read-only data area.
15225 However, if this is being placed in the TOC it must be output as a
15229 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
15230 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15232 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15235 read_only_private_data_section ();
15238 /* Remove any trailing [DS] or the like from the symbol name. */
15240 static const char *
15241 rs6000_xcoff_strip_name_encoding (const char *name)
15246 len = strlen (name);
15247 if (name[len - 1] == ']')
15248 return ggc_alloc_string (name, len - 4);
15253 /* Section attributes. AIX is always PIC. */
15255 static unsigned int
15256 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
15258 unsigned int align;
15259 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
15261 /* Align to at least UNIT size. */
15262 if (flags & SECTION_CODE)
15263 align = MIN_UNITS_PER_WORD;
15265 /* Increase alignment of large objects if not already stricter. */
15266 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
15267 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
15268 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
15270 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
15273 /* Output at beginning of assembler file.
15275 Initialize the section names for the RS/6000 at this point.
15277 Specify filename, including full path, to assembler.
15279 We want to go into the TOC section so at least one .toc will be emitted.
15280 Also, in order to output proper .bs/.es pairs, we need at least one static
15281 [RW] section emitted.
15283 Finally, declare mcount when profiling to make the assembler happy. */
15286 rs6000_xcoff_file_start (void)
15288 rs6000_gen_section_name (&xcoff_bss_section_name,
15289 main_input_filename, ".bss_");
15290 rs6000_gen_section_name (&xcoff_private_data_section_name,
15291 main_input_filename, ".rw_");
15292 rs6000_gen_section_name (&xcoff_read_only_section_name,
15293 main_input_filename, ".ro_");
15295 fputs ("\t.file\t", asm_out_file);
15296 output_quoted_string (asm_out_file, main_input_filename);
15297 fputc ('\n', asm_out_file);
15299 if (write_symbols != NO_DEBUG)
15300 private_data_section ();
15303 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
15304 rs6000_file_start ();
15307 /* Output at end of assembler file.
15308 On the RS/6000, referencing data should automatically pull in text. */
15311 rs6000_xcoff_file_end (void)
15314 fputs ("_section_.text:\n", asm_out_file);
15316 fputs (TARGET_32BIT
15317 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
15320 #endif /* TARGET_XCOFF */
15323 /* Cross-module name binding. Darwin does not support overriding
15324 functions at dynamic-link time. */
15327 rs6000_binds_local_p (tree decl)
15329 return default_binds_local_p_1 (decl, 0);
15333 /* Compute a (partial) cost for rtx X. Return true if the complete
15334 cost has been computed, and false if subexpressions should be
15335 scanned. In either case, *TOTAL contains the cost result. */
15338 rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED,
15343 /* On the RS/6000, if it is valid in the insn, it is free.
15344 So this always returns 0. */
15355 *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15356 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1))
15357 + 0x8000) >= 0x10000)
15358 && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15359 ? COSTS_N_INSNS (2)
15360 : COSTS_N_INSNS (1));
15366 *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15367 && (INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0
15368 && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15369 ? COSTS_N_INSNS (2)
15370 : COSTS_N_INSNS (1));
15376 *total = COSTS_N_INSNS (2);
15379 switch (rs6000_cpu)
15381 case PROCESSOR_RIOS1:
15382 case PROCESSOR_PPC405:
15383 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15384 ? COSTS_N_INSNS (5)
15385 : (INTVAL (XEXP (x, 1)) >= -256
15386 && INTVAL (XEXP (x, 1)) <= 255)
15387 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15390 case PROCESSOR_PPC440:
15391 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15392 ? COSTS_N_INSNS (3)
15393 : COSTS_N_INSNS (2));
15396 case PROCESSOR_RS64A:
15397 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15398 ? GET_MODE (XEXP (x, 1)) != DImode
15399 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34)
15400 : (INTVAL (XEXP (x, 1)) >= -256
15401 && INTVAL (XEXP (x, 1)) <= 255)
15402 ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12));
15405 case PROCESSOR_RIOS2:
15406 case PROCESSOR_MPCCORE:
15407 case PROCESSOR_PPC604e:
15408 *total = COSTS_N_INSNS (2);
15411 case PROCESSOR_PPC601:
15412 *total = COSTS_N_INSNS (5);
15415 case PROCESSOR_PPC603:
15416 case PROCESSOR_PPC7400:
15417 case PROCESSOR_PPC750:
15418 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15419 ? COSTS_N_INSNS (5)
15420 : (INTVAL (XEXP (x, 1)) >= -256
15421 && INTVAL (XEXP (x, 1)) <= 255)
15422 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3));
15425 case PROCESSOR_PPC7450:
15426 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15427 ? COSTS_N_INSNS (4)
15428 : COSTS_N_INSNS (3));
15431 case PROCESSOR_PPC403:
15432 case PROCESSOR_PPC604:
15433 case PROCESSOR_PPC8540:
15434 *total = COSTS_N_INSNS (4);
15437 case PROCESSOR_PPC620:
15438 case PROCESSOR_PPC630:
15439 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15440 ? GET_MODE (XEXP (x, 1)) != DImode
15441 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7)
15442 : (INTVAL (XEXP (x, 1)) >= -256
15443 && INTVAL (XEXP (x, 1)) <= 255)
15444 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15447 case PROCESSOR_POWER4:
15448 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15449 ? GET_MODE (XEXP (x, 1)) != DImode
15450 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)
15451 : COSTS_N_INSNS (2));
15460 if (GET_CODE (XEXP (x, 1)) == CONST_INT
15461 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
15463 *total = COSTS_N_INSNS (2);
15470 switch (rs6000_cpu)
15472 case PROCESSOR_RIOS1:
15473 *total = COSTS_N_INSNS (19);
15476 case PROCESSOR_RIOS2:
15477 *total = COSTS_N_INSNS (13);
15480 case PROCESSOR_RS64A:
15481 *total = (GET_MODE (XEXP (x, 1)) != DImode
15482 ? COSTS_N_INSNS (65)
15483 : COSTS_N_INSNS (67));
15486 case PROCESSOR_MPCCORE:
15487 *total = COSTS_N_INSNS (6);
15490 case PROCESSOR_PPC403:
15491 *total = COSTS_N_INSNS (33);
15494 case PROCESSOR_PPC405:
15495 *total = COSTS_N_INSNS (35);
15498 case PROCESSOR_PPC440:
15499 *total = COSTS_N_INSNS (34);
15502 case PROCESSOR_PPC601:
15503 *total = COSTS_N_INSNS (36);
15506 case PROCESSOR_PPC603:
15507 *total = COSTS_N_INSNS (37);
15510 case PROCESSOR_PPC604:
15511 case PROCESSOR_PPC604e:
15512 *total = COSTS_N_INSNS (20);
15515 case PROCESSOR_PPC620:
15516 case PROCESSOR_PPC630:
15517 *total = (GET_MODE (XEXP (x, 1)) != DImode
15518 ? COSTS_N_INSNS (21)
15519 : COSTS_N_INSNS (37));
15522 case PROCESSOR_PPC750:
15523 case PROCESSOR_PPC8540:
15524 case PROCESSOR_PPC7400:
15525 *total = COSTS_N_INSNS (19);
15528 case PROCESSOR_PPC7450:
15529 *total = COSTS_N_INSNS (23);
15532 case PROCESSOR_POWER4:
15533 *total = (GET_MODE (XEXP (x, 1)) != DImode
15534 ? COSTS_N_INSNS (18)
15535 : COSTS_N_INSNS (34));
15543 *total = COSTS_N_INSNS (4);
15547 /* MEM should be slightly more expensive than (plus (reg) (const)) */
15556 /* A C expression returning the cost of moving data from a register of class
15557 CLASS1 to one of CLASS2. */
15560 rs6000_register_move_cost (enum machine_mode mode,
15561 enum reg_class from, enum reg_class to)
15563 /* Moves from/to GENERAL_REGS. */
15564 if (reg_classes_intersect_p (to, GENERAL_REGS)
15565 || reg_classes_intersect_p (from, GENERAL_REGS))
15567 if (! reg_classes_intersect_p (to, GENERAL_REGS))
15570 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
15571 return (rs6000_memory_move_cost (mode, from, 0)
15572 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
15574 /* It's more expensive to move CR_REGS than CR0_REGS because of the shift...*/
15575 else if (from == CR_REGS)
15579 /* A move will cost one instruction per GPR moved. */
15580 return 2 * HARD_REGNO_NREGS (0, mode);
15583 /* Moving between two similar registers is just one instruction. */
15584 else if (reg_classes_intersect_p (to, from))
15585 return mode == TFmode ? 4 : 2;
15587 /* Everything else has to go through GENERAL_REGS. */
15589 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
15590 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
15593 /* A C expressions returning the cost of moving data of MODE from a register to
15597 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
15598 int in ATTRIBUTE_UNUSED)
15600 if (reg_classes_intersect_p (class, GENERAL_REGS))
15601 return 4 * HARD_REGNO_NREGS (0, mode);
15602 else if (reg_classes_intersect_p (class, FLOAT_REGS))
15603 return 4 * HARD_REGNO_NREGS (32, mode);
15604 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
15605 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
15607 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
15610 /* Return an RTX representing where to find the function value of a
15611 function returning MODE. */
15613 rs6000_complex_function_value (enum machine_mode mode)
15615 unsigned int regno;
15617 enum machine_mode inner = GET_MODE_INNER (mode);
15619 if (FLOAT_MODE_P (mode))
15620 regno = FP_ARG_RETURN;
15623 regno = GP_ARG_RETURN;
15625 /* 32-bit is OK since it'll go in r3/r4. */
15627 && GET_MODE_BITSIZE (inner) >= 32)
15628 return gen_rtx_REG (mode, regno);
15631 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
15633 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
15634 GEN_INT (GET_MODE_UNIT_SIZE (inner)));
15635 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
15638 /* Define how to find the value returned by a function.
15639 VALTYPE is the data type of the value (as a tree).
15640 If the precise function being called is known, FUNC is its FUNCTION_DECL;
15641 otherwise, FUNC is 0.
15643 On the SPE, both FPs and vectors are returned in r3.
15645 On RS/6000 an integer value is in r3 and a floating-point value is in
15646 fp1, unless -msoft-float. */
15649 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
15651 enum machine_mode mode;
15652 unsigned int regno;
15654 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
15656 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
15657 return gen_rtx_PARALLEL (DImode,
15659 gen_rtx_EXPR_LIST (VOIDmode,
15660 gen_rtx_REG (SImode, GP_ARG_RETURN),
15662 gen_rtx_EXPR_LIST (VOIDmode,
15663 gen_rtx_REG (SImode,
15664 GP_ARG_RETURN + 1),
15668 if ((INTEGRAL_TYPE_P (valtype)
15669 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
15670 || POINTER_TYPE_P (valtype))
15671 mode = TARGET_32BIT ? SImode : DImode;
15673 mode = TYPE_MODE (valtype);
15675 if (TREE_CODE (valtype) == REAL_TYPE && TARGET_HARD_FLOAT && TARGET_FPRS)
15676 regno = FP_ARG_RETURN;
15677 else if (TREE_CODE (valtype) == COMPLEX_TYPE
15678 && TARGET_HARD_FLOAT
15679 && SPLIT_COMPLEX_ARGS)
15680 return rs6000_complex_function_value (mode);
15681 else if (TREE_CODE (valtype) == VECTOR_TYPE && TARGET_ALTIVEC)
15682 regno = ALTIVEC_ARG_RETURN;
15684 regno = GP_ARG_RETURN;
15686 return gen_rtx_REG (mode, regno);
15689 /* Define how to find the value returned by a library function
15690 assuming the value has mode MODE. */
15692 rs6000_libcall_value (enum machine_mode mode)
15694 unsigned int regno;
15696 if (GET_MODE_CLASS (mode) == MODE_FLOAT
15697 && TARGET_HARD_FLOAT && TARGET_FPRS)
15698 regno = FP_ARG_RETURN;
15699 else if (ALTIVEC_VECTOR_MODE (mode))
15700 regno = ALTIVEC_ARG_RETURN;
15701 else if (COMPLEX_MODE_P (mode) && SPLIT_COMPLEX_ARGS)
15702 return rs6000_complex_function_value (mode);
15704 regno = GP_ARG_RETURN;
15706 return gen_rtx_REG (mode, regno);
15709 /* Define the offset between two registers, FROM to be eliminated and its
15710 replacement TO, at the start of a routine. */
15712 rs6000_initial_elimination_offset (int from, int to)
15714 rs6000_stack_t *info = rs6000_stack_info ();
15715 HOST_WIDE_INT offset;
15717 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
15718 offset = info->push_p ? 0 : -info->total_size;
15719 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
15720 offset = info->total_size;
15721 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
15722 offset = info->push_p ? info->total_size : 0;
15723 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
15731 /* Return true if TYPE is of type __ev64_opaque__. */
15734 is_ev64_opaque_type (tree type)
15737 && (type == opaque_V2SI_type_node
15738 || type == opaque_V2SF_type_node
15739 || type == opaque_p_V2SI_type_node));
15743 rs6000_dwarf_register_span (rtx reg)
15747 if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg)))
15750 regno = REGNO (reg);
15752 /* The duality of the SPE register size wreaks all kinds of havoc.
15753 This is a way of distinguishing r0 in 32-bits from r0 in
15756 gen_rtx_PARALLEL (VOIDmode,
15759 gen_rtx_REG (SImode, regno + 1200),
15760 gen_rtx_REG (SImode, regno))
15762 gen_rtx_REG (SImode, regno),
15763 gen_rtx_REG (SImode, regno + 1200)));
15766 #include "gt-rs6000.h"