1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
56 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
59 #ifndef TARGET_NO_PROTOTYPE
60 #define TARGET_NO_PROTOTYPE 0
63 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
64 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e \
67 #define min(A,B) ((A) < (B) ? (A) : (B))
68 #define max(A,B) ((A) > (B) ? (A) : (B))
70 /* Structure used to define the rs6000 stack */
71 typedef struct rs6000_stack {
72 int first_gp_reg_save; /* first callee saved GP register used */
73 int first_fp_reg_save; /* first callee saved FP register used */
74 int first_altivec_reg_save; /* first callee saved AltiVec register used */
75 int lr_save_p; /* true if the link reg needs to be saved */
76 int cr_save_p; /* true if the CR reg needs to be saved */
77 unsigned int vrsave_mask; /* mask of vec registers to save */
78 int toc_save_p; /* true if the TOC needs to be saved */
79 int push_p; /* true if we need to allocate stack space */
80 int calls_p; /* true if the function makes any calls */
81 enum rs6000_abi abi; /* which ABI to use */
82 int gp_save_offset; /* offset to save GP regs from initial SP */
83 int fp_save_offset; /* offset to save FP regs from initial SP */
84 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
85 int lr_save_offset; /* offset to save LR from initial SP */
86 int cr_save_offset; /* offset to save CR from initial SP */
87 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
88 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
89 int toc_save_offset; /* offset to save the TOC pointer */
90 int varargs_save_offset; /* offset to save the varargs registers */
91 int ehrd_offset; /* offset to EH return data */
92 int reg_size; /* register size (4 or 8) */
93 int varargs_size; /* size to hold V.4 args passed in regs */
94 HOST_WIDE_INT vars_size; /* variable save area size */
95 int parm_size; /* outgoing parameter size */
96 int save_size; /* save area size */
97 int fixed_size; /* fixed size of stack frame */
98 int gp_size; /* size of saved GP registers */
99 int fp_size; /* size of saved FP registers */
100 int altivec_size; /* size of saved AltiVec registers */
101 int cr_size; /* size to hold CR if not in save_size */
102 int lr_size; /* size to hold LR if not in save_size */
103 int vrsave_size; /* size to hold VRSAVE if not in save_size */
104 int altivec_padding_size; /* size of altivec alignment padding if
106 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
107 int spe_padding_size;
108 int toc_size; /* size to hold TOC if not in save_size */
109 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
110 int spe_64bit_regs_used;
113 /* Target cpu type */
115 enum processor_type rs6000_cpu;
116 struct rs6000_cpu_select rs6000_select[3] =
118 /* switch name, tune arch */
119 { (const char *)0, "--with-cpu=", 1, 1 },
120 { (const char *)0, "-mcpu=", 1, 1 },
121 { (const char *)0, "-mtune=", 1, 0 },
124 /* Always emit branch hint bits. */
125 static GTY(()) bool rs6000_always_hint;
127 /* Schedule instructions for group formation. */
128 static GTY(()) bool rs6000_sched_groups;
130 /* Support adjust_priority scheduler hook
131 and -mprioritize-restricted-insns= option. */
132 const char *rs6000_sched_restricted_insns_priority_str;
133 int rs6000_sched_restricted_insns_priority;
135 /* Support for -msched-costly-dep option. */
136 const char *rs6000_sched_costly_dep_str;
137 enum rs6000_dependence_cost rs6000_sched_costly_dep;
139 /* Support for -minsert-sched-nops option. */
140 const char *rs6000_sched_insert_nops_str;
141 enum rs6000_nop_insertion rs6000_sched_insert_nops;
143 /* Size of long double */
144 const char *rs6000_long_double_size_string;
145 int rs6000_long_double_type_size;
147 /* Whether -mabi=altivec has appeared */
148 int rs6000_altivec_abi;
150 /* Whether VRSAVE instructions should be generated. */
151 int rs6000_altivec_vrsave;
153 /* String from -mvrsave= option. */
154 const char *rs6000_altivec_vrsave_string;
156 /* Nonzero if we want SPE ABI extensions. */
159 /* Whether isel instructions should be generated. */
162 /* Whether SPE simd instructions should be generated. */
165 /* Nonzero if floating point operations are done in the GPRs. */
166 int rs6000_float_gprs = 0;
168 /* String from -mfloat-gprs=. */
169 const char *rs6000_float_gprs_string;
171 /* String from -misel=. */
172 const char *rs6000_isel_string;
174 /* String from -mspe=. */
175 const char *rs6000_spe_string;
177 /* Set to nonzero once AIX common-mode calls have been defined. */
178 static GTY(()) int common_mode_defined;
180 /* Save information from a "cmpxx" operation until the branch or scc is
182 rtx rs6000_compare_op0, rs6000_compare_op1;
183 int rs6000_compare_fp_p;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 int rs6000_pic_labelno;
190 /* Which abi to adhere to */
191 const char *rs6000_abi_name;
193 /* Semantics of the small data area */
194 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
196 /* Which small data model to use */
197 const char *rs6000_sdata_name = (char *)0;
199 /* Counter for labels which are to be placed in .fixup. */
200 int fixuplabelno = 0;
203 /* Bit size of immediate TLS offsets and string from which it is decoded. */
204 int rs6000_tls_size = 32;
205 const char *rs6000_tls_size_string;
207 /* ABI enumeration available for subtarget to use. */
208 enum rs6000_abi rs6000_current_abi;
210 /* ABI string from -mabi= option. */
211 const char *rs6000_abi_string;
214 const char *rs6000_debug_name;
215 int rs6000_debug_stack; /* debug stack applications */
216 int rs6000_debug_arg; /* debug argument handling */
219 static GTY(()) tree opaque_V2SI_type_node;
220 static GTY(()) tree opaque_V2SF_type_node;
221 static GTY(()) tree opaque_p_V2SI_type_node;
222 static GTY(()) tree V16QI_type_node;
223 static GTY(()) tree V2SI_type_node;
224 static GTY(()) tree V2SF_type_node;
225 static GTY(()) tree V4HI_type_node;
226 static GTY(()) tree V4SI_type_node;
227 static GTY(()) tree V4SF_type_node;
228 static GTY(()) tree V8HI_type_node;
229 static GTY(()) tree unsigned_V16QI_type_node;
230 static GTY(()) tree unsigned_V8HI_type_node;
231 static GTY(()) tree unsigned_V4SI_type_node;
232 static GTY(()) tree bool_char_type_node; /* __bool char */
233 static GTY(()) tree bool_short_type_node; /* __bool short */
234 static GTY(()) tree bool_int_type_node; /* __bool int */
235 static GTY(()) tree pixel_type_node; /* __pixel */
236 static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
237 static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
238 static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
239 static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
241 int rs6000_warn_altivec_long = 1; /* On by default. */
242 const char *rs6000_warn_altivec_long_switch;
244 const char *rs6000_traceback_name;
246 traceback_default = 0,
252 /* Flag to say the TOC is initialized */
254 char toc_label_name[10];
256 /* Alias set for saves and restores from the rs6000 stack. */
257 static GTY(()) int rs6000_sr_alias_set;
259 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
260 The only place that looks at this is rs6000_set_default_type_attributes;
261 everywhere else should rely on the presence or absence of a longcall
262 attribute on the function declaration. */
263 int rs6000_default_long_calls;
264 const char *rs6000_longcall_switch;
266 /* Control alignment for fields within structures. */
267 /* String from -malign-XXXXX. */
268 const char *rs6000_alignment_string;
269 int rs6000_alignment_flags;
271 struct builtin_description
273 /* mask is not const because we're going to alter it below. This
274 nonsense will go away when we rewrite the -march infrastructure
275 to give us more target flag bits. */
277 const enum insn_code icode;
278 const char *const name;
279 const enum rs6000_builtins code;
282 static bool rs6000_function_ok_for_sibcall (tree, tree);
283 static int num_insns_constant_wide (HOST_WIDE_INT);
284 static void validate_condition_mode (enum rtx_code, enum machine_mode);
285 static rtx rs6000_generate_compare (enum rtx_code);
286 static void rs6000_maybe_dead (rtx);
287 static void rs6000_emit_stack_tie (void);
288 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
289 static rtx spe_synthesize_frame_save (rtx);
290 static bool spe_func_has_64bit_regs_p (void);
291 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
293 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
294 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
295 static unsigned rs6000_hash_constant (rtx);
296 static unsigned toc_hash_function (const void *);
297 static int toc_hash_eq (const void *, const void *);
298 static int constant_pool_expr_1 (rtx, int *, int *);
299 static bool constant_pool_expr_p (rtx);
300 static bool toc_relative_expr_p (rtx);
301 static bool legitimate_small_data_p (enum machine_mode, rtx);
302 static bool legitimate_offset_address_p (enum machine_mode, rtx, int);
303 static bool legitimate_indexed_address_p (rtx, int);
304 static bool legitimate_indirect_address_p (rtx, int);
305 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
306 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
307 static struct machine_function * rs6000_init_machine_status (void);
308 static bool rs6000_assemble_integer (rtx, unsigned int, int);
309 #ifdef HAVE_GAS_HIDDEN
310 static void rs6000_assemble_visibility (tree, int);
312 static int rs6000_ra_ever_killed (void);
313 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
314 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
315 static const char *rs6000_mangle_fundamental_type (tree);
316 extern const struct attribute_spec rs6000_attribute_table[];
317 static void rs6000_set_default_type_attributes (tree);
318 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
319 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
320 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
322 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
323 static bool rs6000_return_in_memory (tree, tree);
324 static void rs6000_file_start (void);
326 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
327 static void rs6000_elf_asm_out_constructor (rtx, int);
328 static void rs6000_elf_asm_out_destructor (rtx, int);
329 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
330 static void rs6000_elf_unique_section (tree, int);
331 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
332 unsigned HOST_WIDE_INT);
333 static void rs6000_elf_encode_section_info (tree, rtx, int)
335 static bool rs6000_elf_in_small_data_p (tree);
338 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
339 static void rs6000_xcoff_asm_named_section (const char *, unsigned int);
340 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
341 static void rs6000_xcoff_unique_section (tree, int);
342 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
343 unsigned HOST_WIDE_INT);
344 static const char * rs6000_xcoff_strip_name_encoding (const char *);
345 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
346 static void rs6000_xcoff_file_start (void);
347 static void rs6000_xcoff_file_end (void);
350 static bool rs6000_binds_local_p (tree);
352 static int rs6000_use_dfa_pipeline_interface (void);
353 static int rs6000_variable_issue (FILE *, int, rtx, int);
354 static bool rs6000_rtx_costs (rtx, int, int, int *);
355 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
356 static bool is_microcoded_insn (rtx);
357 static int is_dispatch_slot_restricted (rtx);
358 static bool is_cracked_insn (rtx);
359 static bool is_branch_slot_insn (rtx);
360 static int rs6000_adjust_priority (rtx, int);
361 static int rs6000_issue_rate (void);
362 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
363 static rtx get_next_active_insn (rtx, rtx);
364 static bool insn_terminates_group_p (rtx , enum group_termination);
365 static bool is_costly_group (rtx *, rtx);
366 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
367 static int redefine_groups (FILE *, int, rtx, rtx);
368 static int pad_groups (FILE *, int, rtx, rtx);
369 static void rs6000_sched_finish (FILE *, int);
370 static int rs6000_use_sched_lookahead (void);
372 static void rs6000_init_builtins (void);
373 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
374 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
375 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
376 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
377 static void altivec_init_builtins (void);
378 static void rs6000_common_init_builtins (void);
379 static void rs6000_init_libfuncs (void);
381 static void enable_mask_for_builtins (struct builtin_description *, int,
382 enum rs6000_builtins,
383 enum rs6000_builtins);
384 static void spe_init_builtins (void);
385 static rtx spe_expand_builtin (tree, rtx, bool *);
386 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
387 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
388 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
389 static rs6000_stack_t *rs6000_stack_info (void);
390 static void debug_stack_info (rs6000_stack_t *);
392 static rtx altivec_expand_builtin (tree, rtx, bool *);
393 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
394 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
395 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
396 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
397 static rtx altivec_expand_predicate_builtin (enum insn_code,
398 const char *, tree, rtx);
399 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
400 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
401 static void rs6000_parse_abi_options (void);
402 static void rs6000_parse_alignment_option (void);
403 static void rs6000_parse_tls_size_option (void);
404 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
405 static int first_altivec_reg_to_save (void);
406 static unsigned int compute_vrsave_mask (void);
407 static void is_altivec_return_reg (rtx, void *);
408 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
409 int easy_vector_constant (rtx, enum machine_mode);
410 static int easy_vector_same (rtx, enum machine_mode);
411 static int easy_vector_splat_const (int, enum machine_mode);
412 static bool is_ev64_opaque_type (tree);
413 static rtx rs6000_dwarf_register_span (rtx);
414 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
415 static rtx rs6000_tls_get_addr (void);
416 static rtx rs6000_got_sym (void);
417 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
418 static const char *rs6000_get_some_local_dynamic_name (void);
419 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
420 static rtx rs6000_complex_function_value (enum machine_mode);
421 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
422 enum machine_mode, tree);
423 static rtx rs6000_mixed_function_arg (CUMULATIVE_ARGS *,
424 enum machine_mode, tree, int);
425 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
426 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
427 enum machine_mode, tree,
430 static void macho_branch_islands (void);
431 static void add_compiler_branch_island (tree, tree, int);
432 static int no_previous_def (tree function_name);
433 static tree get_prev_label (tree function_name);
436 static tree rs6000_build_builtin_va_list (void);
438 /* Hash table stuff for keeping track of TOC entries. */
440 struct toc_hash_struct GTY(())
442 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
443 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
445 enum machine_mode key_mode;
449 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
451 /* Default register names. */
452 char rs6000_reg_names[][8] =
454 "0", "1", "2", "3", "4", "5", "6", "7",
455 "8", "9", "10", "11", "12", "13", "14", "15",
456 "16", "17", "18", "19", "20", "21", "22", "23",
457 "24", "25", "26", "27", "28", "29", "30", "31",
458 "0", "1", "2", "3", "4", "5", "6", "7",
459 "8", "9", "10", "11", "12", "13", "14", "15",
460 "16", "17", "18", "19", "20", "21", "22", "23",
461 "24", "25", "26", "27", "28", "29", "30", "31",
462 "mq", "lr", "ctr","ap",
463 "0", "1", "2", "3", "4", "5", "6", "7",
465 /* AltiVec registers. */
466 "0", "1", "2", "3", "4", "5", "6", "7",
467 "8", "9", "10", "11", "12", "13", "14", "15",
468 "16", "17", "18", "19", "20", "21", "22", "23",
469 "24", "25", "26", "27", "28", "29", "30", "31",
475 #ifdef TARGET_REGNAMES
476 static const char alt_reg_names[][8] =
478 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
479 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
480 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
481 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
482 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
483 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
484 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
485 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
486 "mq", "lr", "ctr", "ap",
487 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
489 /* AltiVec registers. */
490 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
491 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
492 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
493 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
500 #ifndef MASK_STRICT_ALIGN
501 #define MASK_STRICT_ALIGN 0
503 #ifndef TARGET_PROFILE_KERNEL
504 #define TARGET_PROFILE_KERNEL 0
507 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
508 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
510 /* Return 1 for a symbol ref for a thread-local storage symbol. */
511 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
512 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
514 /* Initialize the GCC target structure. */
515 #undef TARGET_ATTRIBUTE_TABLE
516 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
517 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
518 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
520 #undef TARGET_ASM_ALIGNED_DI_OP
521 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
523 /* Default unaligned ops are only provided for ELF. Find the ops needed
524 for non-ELF systems. */
525 #ifndef OBJECT_FORMAT_ELF
527 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
529 #undef TARGET_ASM_UNALIGNED_HI_OP
530 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
531 #undef TARGET_ASM_UNALIGNED_SI_OP
532 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
533 #undef TARGET_ASM_UNALIGNED_DI_OP
534 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
537 #undef TARGET_ASM_UNALIGNED_HI_OP
538 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
539 #undef TARGET_ASM_UNALIGNED_SI_OP
540 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
544 /* This hook deals with fixups for relocatable code and DI-mode objects
546 #undef TARGET_ASM_INTEGER
547 #define TARGET_ASM_INTEGER rs6000_assemble_integer
549 #ifdef HAVE_GAS_HIDDEN
550 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
551 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
554 #undef TARGET_HAVE_TLS
555 #define TARGET_HAVE_TLS HAVE_AS_TLS
557 #undef TARGET_CANNOT_FORCE_CONST_MEM
558 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
560 #undef TARGET_ASM_FUNCTION_PROLOGUE
561 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
562 #undef TARGET_ASM_FUNCTION_EPILOGUE
563 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
565 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
566 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE rs6000_use_dfa_pipeline_interface
567 #undef TARGET_SCHED_VARIABLE_ISSUE
568 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
570 #undef TARGET_SCHED_ISSUE_RATE
571 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
572 #undef TARGET_SCHED_ADJUST_COST
573 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
574 #undef TARGET_SCHED_ADJUST_PRIORITY
575 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
576 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
577 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
578 #undef TARGET_SCHED_FINISH
579 #define TARGET_SCHED_FINISH rs6000_sched_finish
581 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
582 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
584 #undef TARGET_INIT_BUILTINS
585 #define TARGET_INIT_BUILTINS rs6000_init_builtins
587 #undef TARGET_EXPAND_BUILTIN
588 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
590 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
591 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
593 #undef TARGET_INIT_LIBFUNCS
594 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
597 #undef TARGET_BINDS_LOCAL_P
598 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
601 #undef TARGET_ASM_OUTPUT_MI_THUNK
602 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
604 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
605 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
607 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
608 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
610 #undef TARGET_RTX_COSTS
611 #define TARGET_RTX_COSTS rs6000_rtx_costs
612 #undef TARGET_ADDRESS_COST
613 #define TARGET_ADDRESS_COST hook_int_rtx_0
615 #undef TARGET_VECTOR_OPAQUE_P
616 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
618 #undef TARGET_DWARF_REGISTER_SPAN
619 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
621 /* On rs6000, function arguments are promoted, as are function return
623 #undef TARGET_PROMOTE_FUNCTION_ARGS
624 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
625 #undef TARGET_PROMOTE_FUNCTION_RETURN
626 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
628 #undef TARGET_RETURN_IN_MEMORY
629 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
631 #undef TARGET_SETUP_INCOMING_VARARGS
632 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
634 /* Always strict argument naming on rs6000. */
635 #undef TARGET_STRICT_ARGUMENT_NAMING
636 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
637 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
638 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
639 #undef TARGET_SPLIT_COMPLEX_ARG
640 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
642 #undef TARGET_BUILD_BUILTIN_VA_LIST
643 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
645 struct gcc_target targetm = TARGET_INITIALIZER;
647 /* Override command line options. Mostly we process the processor
648 type and sometimes adjust other TARGET_ options. */
651 rs6000_override_options (const char *default_cpu)
654 struct rs6000_cpu_select *ptr;
657 /* Simplifications for entries below. */
660 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
661 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
664 /* This table occasionally claims that a processor does not support
665 a particular feature even though it does, but the feature is slower
666 than the alternative. Thus, it shouldn't be relied on as a
667 complete description of the processor's support.
669 Please keep this list in order, and don't forget to update the
670 documentation in invoke.texi when adding a new processor or
674 const char *const name; /* Canonical processor name. */
675 const enum processor_type processor; /* Processor type enum value. */
676 const int target_enable; /* Target flags to enable. */
677 } const processor_target_table[]
678 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
679 {"403", PROCESSOR_PPC403,
680 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
681 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
682 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
683 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
684 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
685 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
686 {"601", PROCESSOR_PPC601,
687 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
688 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
689 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
690 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
691 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
692 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
693 {"620", PROCESSOR_PPC620,
694 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
695 {"630", PROCESSOR_PPC630,
696 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
697 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
698 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
699 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
700 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
701 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
702 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
703 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
704 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
705 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
706 {"970", PROCESSOR_POWER4,
707 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
708 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
709 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
710 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
711 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
712 {"G5", PROCESSOR_POWER4,
713 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
714 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
715 {"power2", PROCESSOR_POWER,
716 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
717 {"power3", PROCESSOR_PPC630,
718 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
719 {"power4", PROCESSOR_POWER4,
720 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
721 {"power5", PROCESSOR_POWER5,
722 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
723 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
724 {"powerpc64", PROCESSOR_POWERPC64,
725 POWERPC_BASE_MASK | MASK_POWERPC64},
726 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
727 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
728 {"rios2", PROCESSOR_RIOS2,
729 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
730 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
731 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
732 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
735 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
737 /* Some OSs don't support saving the high part of 64-bit registers on
738 context switch. Other OSs don't support saving Altivec registers.
739 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
740 settings; if the user wants either, the user must explicitly specify
741 them and we won't interfere with the user's specification. */
744 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
745 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
746 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
749 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
750 #ifdef OS_MISSING_POWERPC64
751 if (OS_MISSING_POWERPC64)
752 set_masks &= ~MASK_POWERPC64;
754 #ifdef OS_MISSING_ALTIVEC
755 if (OS_MISSING_ALTIVEC)
756 set_masks &= ~MASK_ALTIVEC;
759 /* Don't override these by the processor default if given explicitly. */
760 set_masks &= ~(target_flags_explicit
761 & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT));
763 /* Identify the processor type. */
764 rs6000_select[0].string = default_cpu;
765 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
767 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
769 ptr = &rs6000_select[i];
770 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
772 for (j = 0; j < ptt_size; j++)
773 if (! strcmp (ptr->string, processor_target_table[j].name))
776 rs6000_cpu = processor_target_table[j].processor;
780 target_flags &= ~set_masks;
781 target_flags |= (processor_target_table[j].target_enable
788 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
795 /* If we are optimizing big endian systems for space, use the load/store
796 multiple and string instructions. */
797 if (BYTES_BIG_ENDIAN && optimize_size)
798 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
800 /* Don't allow -mmultiple or -mstring on little endian systems
801 unless the cpu is a 750, because the hardware doesn't support the
802 instructions used in little endian mode, and causes an alignment
803 trap. The 750 does not cause an alignment trap (except when the
804 target is unaligned). */
806 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
810 target_flags &= ~MASK_MULTIPLE;
811 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
812 warning ("-mmultiple is not supported on little endian systems");
817 target_flags &= ~MASK_STRING;
818 if ((target_flags_explicit & MASK_STRING) != 0)
819 warning ("-mstring is not supported on little endian systems");
823 /* Set debug flags */
824 if (rs6000_debug_name)
826 if (! strcmp (rs6000_debug_name, "all"))
827 rs6000_debug_stack = rs6000_debug_arg = 1;
828 else if (! strcmp (rs6000_debug_name, "stack"))
829 rs6000_debug_stack = 1;
830 else if (! strcmp (rs6000_debug_name, "arg"))
831 rs6000_debug_arg = 1;
833 error ("unknown -mdebug-%s switch", rs6000_debug_name);
836 if (rs6000_traceback_name)
838 if (! strncmp (rs6000_traceback_name, "full", 4))
839 rs6000_traceback = traceback_full;
840 else if (! strncmp (rs6000_traceback_name, "part", 4))
841 rs6000_traceback = traceback_part;
842 else if (! strncmp (rs6000_traceback_name, "no", 2))
843 rs6000_traceback = traceback_none;
845 error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'",
846 rs6000_traceback_name);
849 /* Set size of long double */
850 rs6000_long_double_type_size = 64;
851 if (rs6000_long_double_size_string)
854 int size = strtol (rs6000_long_double_size_string, &tail, 10);
855 if (*tail != '\0' || (size != 64 && size != 128))
856 error ("Unknown switch -mlong-double-%s",
857 rs6000_long_double_size_string);
859 rs6000_long_double_type_size = size;
862 /* Set Altivec ABI as default for powerpc64 linux. */
863 if (TARGET_ELF && TARGET_64BIT)
865 rs6000_altivec_abi = 1;
866 rs6000_altivec_vrsave = 1;
869 /* Handle -mabi= options. */
870 rs6000_parse_abi_options ();
872 /* Handle -malign-XXXXX option. */
873 rs6000_parse_alignment_option ();
875 /* Handle generic -mFOO=YES/NO options. */
876 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
877 &rs6000_altivec_vrsave);
878 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
880 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
881 rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string,
884 /* Handle -mtls-size option. */
885 rs6000_parse_tls_size_option ();
887 #ifdef SUBTARGET_OVERRIDE_OPTIONS
888 SUBTARGET_OVERRIDE_OPTIONS;
890 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
891 SUBSUBTARGET_OVERRIDE_OPTIONS;
896 /* The e500 does not have string instructions, and we set
897 MASK_STRING above when optimizing for size. */
898 if ((target_flags & MASK_STRING) != 0)
899 target_flags = target_flags & ~MASK_STRING;
901 /* No SPE means 64-bit long doubles, even if an E500. */
902 if (rs6000_spe_string != 0
903 && !strcmp (rs6000_spe_string, "no"))
904 rs6000_long_double_type_size = 64;
906 else if (rs6000_select[1].string != NULL)
908 /* For the powerpc-eabispe configuration, we set all these by
909 default, so let's unset them if we manually set another
910 CPU that is not the E500. */
911 if (rs6000_abi_string == 0)
913 if (rs6000_spe_string == 0)
915 if (rs6000_float_gprs_string == 0)
916 rs6000_float_gprs = 0;
917 if (rs6000_isel_string == 0)
919 if (rs6000_long_double_size_string == 0)
920 rs6000_long_double_type_size = 64;
923 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
924 && rs6000_cpu != PROCESSOR_POWER5);
925 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
926 || rs6000_cpu == PROCESSOR_POWER5);
928 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
929 using TARGET_OPTIONS to handle a toggle switch, but we're out of
930 bits in target_flags so TARGET_SWITCHES cannot be used.
931 Assumption here is that rs6000_longcall_switch points into the
932 text of the complete option, rather than being a copy, so we can
933 scan back for the presence or absence of the no- modifier. */
934 if (rs6000_longcall_switch)
936 const char *base = rs6000_longcall_switch;
937 while (base[-1] != 'm') base--;
939 if (*rs6000_longcall_switch != '\0')
940 error ("invalid option `%s'", base);
941 rs6000_default_long_calls = (base[0] != 'n');
944 /* Handle -m(no-)warn-altivec-long similarly. */
945 if (rs6000_warn_altivec_long_switch)
947 const char *base = rs6000_warn_altivec_long_switch;
948 while (base[-1] != 'm') base--;
950 if (*rs6000_warn_altivec_long_switch != '\0')
951 error ("invalid option `%s'", base);
952 rs6000_warn_altivec_long = (base[0] != 'n');
955 /* Handle -mprioritize-restricted-insns option. */
956 rs6000_sched_restricted_insns_priority
957 = (rs6000_sched_groups ? 1 : 0);
958 if (rs6000_sched_restricted_insns_priority_str)
959 rs6000_sched_restricted_insns_priority =
960 atoi (rs6000_sched_restricted_insns_priority_str);
962 /* Handle -msched-costly-dep option. */
963 rs6000_sched_costly_dep
964 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
965 if (rs6000_sched_costly_dep_str)
967 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
968 rs6000_sched_costly_dep = no_dep_costly;
969 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
970 rs6000_sched_costly_dep = all_deps_costly;
971 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
972 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
973 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
974 rs6000_sched_costly_dep = store_to_load_dep_costly;
976 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
979 /* Handle -minsert-sched-nops option. */
980 rs6000_sched_insert_nops
981 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
982 if (rs6000_sched_insert_nops_str)
984 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
985 rs6000_sched_insert_nops = sched_finish_none;
986 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
987 rs6000_sched_insert_nops = sched_finish_pad_groups;
988 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
989 rs6000_sched_insert_nops = sched_finish_regroup_exact;
991 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
994 #ifdef TARGET_REGNAMES
995 /* If the user desires alternate register names, copy in the
996 alternate names now. */
998 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1001 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1002 If -maix-struct-return or -msvr4-struct-return was explicitly
1003 used, don't override with the ABI default. */
1004 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1006 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1007 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1009 target_flags |= MASK_AIX_STRUCT_RET;
1012 if (TARGET_LONG_DOUBLE_128
1013 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1014 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1016 /* Allocate an alias set for register saves & restores from stack. */
1017 rs6000_sr_alias_set = new_alias_set ();
1020 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1022 /* We can only guarantee the availability of DI pseudo-ops when
1023 assembling for 64-bit targets. */
1026 targetm.asm_out.aligned_op.di = NULL;
1027 targetm.asm_out.unaligned_op.di = NULL;
1030 /* Set maximum branch target alignment at two instructions, eight bytes. */
1031 align_jumps_max_skip = 8;
1032 align_loops_max_skip = 8;
1034 /* Arrange to save and restore machine status around nested functions. */
1035 init_machine_status = rs6000_init_machine_status;
1037 /* We should always be splitting complex arguments, but we can't break
1038 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1039 if (DEFAULT_ABI != ABI_AIX)
1040 targetm.calls.split_complex_arg = NULL;
1043 /* Handle generic options of the form -mfoo=yes/no.
1044 NAME is the option name.
1045 VALUE is the option value.
1046 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1047 whether the option value is 'yes' or 'no' respectively. */
1049 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1053 else if (!strcmp (value, "yes"))
1055 else if (!strcmp (value, "no"))
1058 error ("unknown -m%s= option specified: '%s'", name, value);
1061 /* Handle -mabi= options. */
1063 rs6000_parse_abi_options (void)
1065 if (rs6000_abi_string == 0)
1067 else if (! strcmp (rs6000_abi_string, "altivec"))
1069 rs6000_altivec_abi = 1;
1072 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1073 rs6000_altivec_abi = 0;
1074 else if (! strcmp (rs6000_abi_string, "spe"))
1077 rs6000_altivec_abi = 0;
1078 if (!TARGET_SPE_ABI)
1079 error ("not configured for ABI: '%s'", rs6000_abi_string);
1082 else if (! strcmp (rs6000_abi_string, "no-spe"))
1085 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1088 /* Handle -malign-XXXXXX options. */
1090 rs6000_parse_alignment_option (void)
1092 if (rs6000_alignment_string == 0)
1094 else if (! strcmp (rs6000_alignment_string, "power"))
1095 rs6000_alignment_flags = MASK_ALIGN_POWER;
1096 else if (! strcmp (rs6000_alignment_string, "natural"))
1097 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1099 error ("unknown -malign-XXXXX option specified: '%s'",
1100 rs6000_alignment_string);
1103 /* Validate and record the size specified with the -mtls-size option. */
1106 rs6000_parse_tls_size_option (void)
1108 if (rs6000_tls_size_string == 0)
1110 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1111 rs6000_tls_size = 16;
1112 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1113 rs6000_tls_size = 32;
1114 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1115 rs6000_tls_size = 64;
1117 error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string);
1121 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1125 /* Do anything needed at the start of the asm file. */
1128 rs6000_file_start (void)
1132 const char *start = buffer;
1133 struct rs6000_cpu_select *ptr;
1134 const char *default_cpu = TARGET_CPU_DEFAULT;
1135 FILE *file = asm_out_file;
1137 default_file_start ();
1139 #ifdef TARGET_BI_ARCH
1140 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1144 if (flag_verbose_asm)
1146 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1147 rs6000_select[0].string = default_cpu;
1149 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1151 ptr = &rs6000_select[i];
1152 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1154 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1159 #ifdef USING_ELFOS_H
1160 switch (rs6000_sdata)
1162 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1163 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1164 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1165 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1168 if (rs6000_sdata && g_switch_value)
1170 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1181 /* Return nonzero if this function is known to have a null epilogue. */
1184 direct_return (void)
1186 if (reload_completed)
1188 rs6000_stack_t *info = rs6000_stack_info ();
1190 if (info->first_gp_reg_save == 32
1191 && info->first_fp_reg_save == 64
1192 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1193 && ! info->lr_save_p
1194 && ! info->cr_save_p
1195 && info->vrsave_mask == 0
1203 /* Returns 1 always. */
1206 any_operand (rtx op ATTRIBUTE_UNUSED,
1207 enum machine_mode mode ATTRIBUTE_UNUSED)
1212 /* Returns 1 if op is the count register. */
1214 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1216 if (GET_CODE (op) != REG)
1219 if (REGNO (op) == COUNT_REGISTER_REGNUM)
1222 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1228 /* Returns 1 if op is an altivec register. */
1230 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1233 return (register_operand (op, mode)
1234 && (GET_CODE (op) != REG
1235 || REGNO (op) > FIRST_PSEUDO_REGISTER
1236 || ALTIVEC_REGNO_P (REGNO (op))));
1240 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1242 if (GET_CODE (op) != REG)
1245 if (XER_REGNO_P (REGNO (op)))
1251 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1252 by such constants completes more quickly. */
1255 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1257 return ( GET_CODE (op) == CONST_INT
1258 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1261 /* Return 1 if OP is a constant that can fit in a D field. */
1264 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1266 return (GET_CODE (op) == CONST_INT
1267 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1270 /* Similar for an unsigned D field. */
1273 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1275 return (GET_CODE (op) == CONST_INT
1276 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1279 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1282 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1284 return (GET_CODE (op) == CONST_INT
1285 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1288 /* Returns 1 if OP is a CONST_INT that is a positive value
1289 and an exact power of 2. */
1292 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1294 return (GET_CODE (op) == CONST_INT
1296 && exact_log2 (INTVAL (op)) >= 0);
1299 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1303 gpc_reg_operand (rtx op, enum machine_mode mode)
1305 return (register_operand (op, mode)
1306 && (GET_CODE (op) != REG
1307 || (REGNO (op) >= ARG_POINTER_REGNUM
1308 && !XER_REGNO_P (REGNO (op)))
1309 || REGNO (op) < MQ_REGNO));
1312 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1316 cc_reg_operand (rtx op, enum machine_mode mode)
1318 return (register_operand (op, mode)
1319 && (GET_CODE (op) != REG
1320 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1321 || CR_REGNO_P (REGNO (op))));
1324 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1325 CR field that isn't CR0. */
1328 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1330 return (register_operand (op, mode)
1331 && (GET_CODE (op) != REG
1332 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1333 || CR_REGNO_NOT_CR0_P (REGNO (op))));
1336 /* Returns 1 if OP is either a constant integer valid for a D-field or
1337 a non-special register. If a register, it must be in the proper
1338 mode unless MODE is VOIDmode. */
1341 reg_or_short_operand (rtx op, enum machine_mode mode)
1343 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1346 /* Similar, except check if the negation of the constant would be
1347 valid for a D-field. */
1350 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1352 if (GET_CODE (op) == CONST_INT)
1353 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
1355 return gpc_reg_operand (op, mode);
1358 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1359 a non-special register. If a register, it must be in the proper
1360 mode unless MODE is VOIDmode. */
1363 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1365 if (gpc_reg_operand (op, mode))
1367 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1374 /* Return 1 if the operand is either a register or an integer whose
1375 high-order 16 bits are zero. */
1378 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1380 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1383 /* Return 1 is the operand is either a non-special register or ANY
1384 constant integer. */
1387 reg_or_cint_operand (rtx op, enum machine_mode mode)
1389 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1392 /* Return 1 is the operand is either a non-special register or ANY
1393 32-bit signed constant integer. */
1396 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
1398 return (gpc_reg_operand (op, mode)
1399 || (GET_CODE (op) == CONST_INT
1400 #if HOST_BITS_PER_WIDE_INT != 32
1401 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
1402 < (unsigned HOST_WIDE_INT) 0x100000000ll)
1407 /* Return 1 is the operand is either a non-special register or a 32-bit
1408 signed constant integer valid for 64-bit addition. */
1411 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
1413 return (gpc_reg_operand (op, mode)
1414 || (GET_CODE (op) == CONST_INT
1415 #if HOST_BITS_PER_WIDE_INT == 32
1416 && INTVAL (op) < 0x7fff8000
1418 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
1424 /* Return 1 is the operand is either a non-special register or a 32-bit
1425 signed constant integer valid for 64-bit subtraction. */
1428 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
1430 return (gpc_reg_operand (op, mode)
1431 || (GET_CODE (op) == CONST_INT
1432 #if HOST_BITS_PER_WIDE_INT == 32
1433 && (- INTVAL (op)) < 0x7fff8000
1435 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
1441 /* Return 1 is the operand is either a non-special register or ANY
1442 32-bit unsigned constant integer. */
1445 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
1447 if (GET_CODE (op) == CONST_INT)
1449 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
1451 if (GET_MODE_BITSIZE (mode) <= 32)
1454 if (INTVAL (op) < 0)
1458 return ((INTVAL (op) & GET_MODE_MASK (mode)
1459 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
1461 else if (GET_CODE (op) == CONST_DOUBLE)
1463 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1467 return CONST_DOUBLE_HIGH (op) == 0;
1470 return gpc_reg_operand (op, mode);
1473 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
1476 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1478 return (GET_CODE (op) == SYMBOL_REF
1479 || GET_CODE (op) == CONST
1480 || GET_CODE (op) == LABEL_REF);
1483 /* Return 1 if the operand is a simple references that can be loaded via
1484 the GOT (labels involving addition aren't allowed). */
1487 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1489 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
1492 /* Return the number of instructions it takes to form a constant in an
1493 integer register. */
1496 num_insns_constant_wide (HOST_WIDE_INT value)
1498 /* signed constant loadable with {cal|addi} */
1499 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1502 /* constant loadable with {cau|addis} */
1503 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1506 #if HOST_BITS_PER_WIDE_INT == 64
1507 else if (TARGET_POWERPC64)
1509 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1510 HOST_WIDE_INT high = value >> 31;
1512 if (high == 0 || high == -1)
1518 return num_insns_constant_wide (high) + 1;
1520 return (num_insns_constant_wide (high)
1521 + num_insns_constant_wide (low) + 1);
1530 num_insns_constant (rtx op, enum machine_mode mode)
1532 if (GET_CODE (op) == CONST_INT)
1534 #if HOST_BITS_PER_WIDE_INT == 64
1535 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1536 && mask64_operand (op, mode))
1540 return num_insns_constant_wide (INTVAL (op));
1543 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1548 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1549 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1550 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1553 else if (GET_CODE (op) == CONST_DOUBLE)
1559 int endian = (WORDS_BIG_ENDIAN == 0);
1561 if (mode == VOIDmode || mode == DImode)
1563 high = CONST_DOUBLE_HIGH (op);
1564 low = CONST_DOUBLE_LOW (op);
1568 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1569 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1571 low = l[1 - endian];
1575 return (num_insns_constant_wide (low)
1576 + num_insns_constant_wide (high));
1580 if (high == 0 && low >= 0)
1581 return num_insns_constant_wide (low);
1583 else if (high == -1 && low < 0)
1584 return num_insns_constant_wide (low);
1586 else if (mask64_operand (op, mode))
1590 return num_insns_constant_wide (high) + 1;
1593 return (num_insns_constant_wide (high)
1594 + num_insns_constant_wide (low) + 1);
1602 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
1603 register with one instruction per word. We only do this if we can
1604 safely read CONST_DOUBLE_{LOW,HIGH}. */
1607 easy_fp_constant (rtx op, enum machine_mode mode)
1609 if (GET_CODE (op) != CONST_DOUBLE
1610 || GET_MODE (op) != mode
1611 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
1614 /* Consider all constants with -msoft-float to be easy. */
1615 if ((TARGET_SOFT_FLOAT || !TARGET_FPRS)
1619 /* If we are using V.4 style PIC, consider all constants to be hard. */
1620 if (flag_pic && DEFAULT_ABI == ABI_V4)
1623 #ifdef TARGET_RELOCATABLE
1624 /* Similarly if we are using -mrelocatable, consider all constants
1626 if (TARGET_RELOCATABLE)
1635 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1636 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
1638 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1639 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
1640 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
1641 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
1644 else if (mode == DFmode)
1649 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1650 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
1652 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1653 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
1656 else if (mode == SFmode)
1661 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1662 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1664 return num_insns_constant_wide (l) == 1;
1667 else if (mode == DImode)
1668 return ((TARGET_POWERPC64
1669 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
1670 || (num_insns_constant (op, DImode) <= 2));
1672 else if (mode == SImode)
1678 /* Returns the constant for the splat instrunction, if exists. */
1681 easy_vector_splat_const (int cst, enum machine_mode mode)
1686 if (EASY_VECTOR_15 (cst)
1687 || EASY_VECTOR_15_ADD_SELF (cst))
1689 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1693 if (EASY_VECTOR_15 (cst)
1694 || EASY_VECTOR_15_ADD_SELF (cst))
1696 if ((cst & 0xff) != ((cst >> 8) & 0xff))
1700 if (EASY_VECTOR_15 (cst)
1701 || EASY_VECTOR_15_ADD_SELF (cst))
1710 /* Return nonzero if all elements of a vector have the same value. */
1713 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1717 units = CONST_VECTOR_NUNITS (op);
1719 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1720 for (i = 1; i < units; ++i)
1721 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1723 if (i == units && easy_vector_splat_const (cst, mode))
1728 /* Return 1 if the operand is a CONST_INT and can be put into a
1729 register without using memory. */
1732 easy_vector_constant (rtx op, enum machine_mode mode)
1736 if (GET_CODE (op) != CONST_VECTOR
1741 if (zero_constant (op, mode)
1742 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
1743 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
1746 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
1749 if (TARGET_SPE && mode == V1DImode)
1752 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1753 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
1755 /* Limit SPE vectors to 15 bits signed. These we can generate with:
1757 evmergelo r0, r0, r0
1760 I don't know how efficient it would be to allow bigger constants,
1761 considering we'll have an extra 'ori' for every 'li'. I doubt 5
1762 instructions is better than a 64-bit memory load, but I don't
1763 have the e500 timing specs. */
1764 if (TARGET_SPE && mode == V2SImode
1765 && cst >= -0x7fff && cst <= 0x7fff
1766 && cst2 >= -0x7fff && cst2 <= 0x7fff)
1770 && easy_vector_same (op, mode))
1772 cst = easy_vector_splat_const (cst, mode);
1773 if (EASY_VECTOR_15_ADD_SELF (cst)
1774 || EASY_VECTOR_15 (cst))
1780 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
1783 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
1787 && GET_CODE (op) == CONST_VECTOR
1788 && easy_vector_same (op, mode))
1790 cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode);
1791 if (EASY_VECTOR_15_ADD_SELF (cst))
1797 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
1800 gen_easy_vector_constant_add_self (rtx op)
1804 units = GET_MODE_NUNITS (GET_MODE (op));
1805 v = rtvec_alloc (units);
1807 for (i = 0; i < units; i++)
1809 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
1810 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
1814 output_vec_const_move (rtx *operands)
1817 enum machine_mode mode;
1823 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
1824 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
1825 mode = GET_MODE (dest);
1829 if (zero_constant (vec, mode))
1830 return "vxor %0,%0,%0";
1831 else if (easy_vector_constant (vec, mode))
1833 operands[1] = GEN_INT (cst);
1837 if (EASY_VECTOR_15 (cst))
1839 operands[1] = GEN_INT (cst);
1840 return "vspltisw %0,%1";
1842 else if (EASY_VECTOR_15_ADD_SELF (cst))
1846 if (EASY_VECTOR_15 (cst))
1848 operands[1] = GEN_INT (cst);
1849 return "vspltish %0,%1";
1851 else if (EASY_VECTOR_15_ADD_SELF (cst))
1855 if (EASY_VECTOR_15 (cst))
1857 operands[1] = GEN_INT (cst);
1858 return "vspltisb %0,%1";
1860 else if (EASY_VECTOR_15_ADD_SELF (cst))
1872 /* Vector constant 0 is handled as a splitter of V2SI, and in the
1873 pattern of V1DI, V4HI, and V2SF.
1875 FIXME: We should probably return # and add post reload
1876 splitters for these, but this way is so easy ;-).
1878 operands[1] = GEN_INT (cst);
1879 operands[2] = GEN_INT (cst2);
1881 return "li %0,%1\n\tevmergelo %0,%0,%0";
1883 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
1889 /* Return 1 if the operand is the constant 0. This works for scalars
1890 as well as vectors. */
1892 zero_constant (rtx op, enum machine_mode mode)
1894 return op == CONST0_RTX (mode);
1897 /* Return 1 if the operand is 0.0. */
1899 zero_fp_constant (rtx op, enum machine_mode mode)
1901 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
1904 /* Return 1 if the operand is in volatile memory. Note that during
1905 the RTL generation phase, memory_operand does not return TRUE for
1906 volatile memory references. So this function allows us to
1907 recognize volatile references where its safe. */
1910 volatile_mem_operand (rtx op, enum machine_mode mode)
1912 if (GET_CODE (op) != MEM)
1915 if (!MEM_VOLATILE_P (op))
1918 if (mode != GET_MODE (op))
1921 if (reload_completed)
1922 return memory_operand (op, mode);
1924 if (reload_in_progress)
1925 return strict_memory_address_p (mode, XEXP (op, 0));
1927 return memory_address_p (mode, XEXP (op, 0));
1930 /* Return 1 if the operand is an offsettable memory operand. */
1933 offsettable_mem_operand (rtx op, enum machine_mode mode)
1935 return ((GET_CODE (op) == MEM)
1936 && offsettable_address_p (reload_completed || reload_in_progress,
1937 mode, XEXP (op, 0)));
1940 /* Return 1 if the operand is either an easy FP constant (see above) or
1944 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
1946 return memory_operand (op, mode) || easy_fp_constant (op, mode);
1949 /* Return 1 if the operand is either a non-special register or an item
1950 that can be used as the operand of a `mode' add insn. */
1953 add_operand (rtx op, enum machine_mode mode)
1955 if (GET_CODE (op) == CONST_INT)
1956 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1957 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1959 return gpc_reg_operand (op, mode);
1962 /* Return 1 if OP is a constant but not a valid add_operand. */
1965 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1967 return (GET_CODE (op) == CONST_INT
1968 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1969 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1972 /* Return 1 if the operand is a non-special register or a constant that
1973 can be used as the operand of an OR or XOR insn on the RS/6000. */
1976 logical_operand (rtx op, enum machine_mode mode)
1978 HOST_WIDE_INT opl, oph;
1980 if (gpc_reg_operand (op, mode))
1983 if (GET_CODE (op) == CONST_INT)
1985 opl = INTVAL (op) & GET_MODE_MASK (mode);
1987 #if HOST_BITS_PER_WIDE_INT <= 32
1988 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
1992 else if (GET_CODE (op) == CONST_DOUBLE)
1994 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1997 opl = CONST_DOUBLE_LOW (op);
1998 oph = CONST_DOUBLE_HIGH (op);
2005 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
2006 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
2009 /* Return 1 if C is a constant that is not a logical operand (as
2010 above), but could be split into one. */
2013 non_logical_cint_operand (rtx op, enum machine_mode mode)
2015 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
2016 && ! logical_operand (op, mode)
2017 && reg_or_logical_cint_operand (op, mode));
2020 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2021 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
2022 Reject all ones and all zeros, since these should have been optimized
2023 away and confuse the making of MB and ME. */
2026 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2028 HOST_WIDE_INT c, lsb;
2030 if (GET_CODE (op) != CONST_INT)
2035 /* Fail in 64-bit mode if the mask wraps around because the upper
2036 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
2037 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
2040 /* We don't change the number of transitions by inverting,
2041 so make sure we start with the LS bit zero. */
2045 /* Reject all zeros or all ones. */
2049 /* Find the first transition. */
2052 /* Invert to look for a second transition. */
2055 /* Erase first transition. */
2058 /* Find the second transition (if any). */
2061 /* Match if all the bits above are 1's (or c is zero). */
2065 /* Return 1 for the PowerPC64 rlwinm corner case. */
2068 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2070 HOST_WIDE_INT c, lsb;
2072 if (GET_CODE (op) != CONST_INT)
2077 if ((c & 0x80000001) != 0x80000001)
2091 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2092 It is if there are no more than one 1->0 or 0->1 transitions.
2093 Reject all zeros, since zero should have been optimized away and
2094 confuses the making of MB and ME. */
2097 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2099 if (GET_CODE (op) == CONST_INT)
2101 HOST_WIDE_INT c, lsb;
2105 /* Reject all zeros. */
2109 /* We don't change the number of transitions by inverting,
2110 so make sure we start with the LS bit zero. */
2114 /* Find the transition, and check that all bits above are 1's. */
2117 /* Match if all the bits above are 1's (or c is zero). */
2123 /* Like mask64_operand, but allow up to three transitions. This
2124 predicate is used by insn patterns that generate two rldicl or
2125 rldicr machine insns. */
2128 mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2130 if (GET_CODE (op) == CONST_INT)
2132 HOST_WIDE_INT c, lsb;
2136 /* Disallow all zeros. */
2140 /* We don't change the number of transitions by inverting,
2141 so make sure we start with the LS bit zero. */
2145 /* Find the first transition. */
2148 /* Invert to look for a second transition. */
2151 /* Erase first transition. */
2154 /* Find the second transition. */
2157 /* Invert to look for a third transition. */
2160 /* Erase second transition. */
2163 /* Find the third transition (if any). */
2166 /* Match if all the bits above are 1's (or c is zero). */
2172 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2173 implement ANDing by the mask IN. */
2175 build_mask64_2_operands (rtx in, rtx *out)
2177 #if HOST_BITS_PER_WIDE_INT >= 64
2178 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2181 if (GET_CODE (in) != CONST_INT)
2187 /* Assume c initially something like 0x00fff000000fffff. The idea
2188 is to rotate the word so that the middle ^^^^^^ group of zeros
2189 is at the MS end and can be cleared with an rldicl mask. We then
2190 rotate back and clear off the MS ^^ group of zeros with a
2192 c = ~c; /* c == 0xff000ffffff00000 */
2193 lsb = c & -c; /* lsb == 0x0000000000100000 */
2194 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2195 c = ~c; /* c == 0x00fff000000fffff */
2196 c &= -lsb; /* c == 0x00fff00000000000 */
2197 lsb = c & -c; /* lsb == 0x0000100000000000 */
2198 c = ~c; /* c == 0xff000fffffffffff */
2199 c &= -lsb; /* c == 0xff00000000000000 */
2201 while ((lsb >>= 1) != 0)
2202 shift++; /* shift == 44 on exit from loop */
2203 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2204 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2205 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2209 /* Assume c initially something like 0xff000f0000000000. The idea
2210 is to rotate the word so that the ^^^ middle group of zeros
2211 is at the LS end and can be cleared with an rldicr mask. We then
2212 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2214 lsb = c & -c; /* lsb == 0x0000010000000000 */
2215 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2216 c = ~c; /* c == 0x00fff0ffffffffff */
2217 c &= -lsb; /* c == 0x00fff00000000000 */
2218 lsb = c & -c; /* lsb == 0x0000100000000000 */
2219 c = ~c; /* c == 0xff000fffffffffff */
2220 c &= -lsb; /* c == 0xff00000000000000 */
2222 while ((lsb >>= 1) != 0)
2223 shift++; /* shift == 44 on exit from loop */
2224 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2225 m1 >>= shift; /* m1 == 0x0000000000000fff */
2226 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2229 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2230 masks will be all 1's. We are guaranteed more than one transition. */
2231 out[0] = GEN_INT (64 - shift);
2232 out[1] = GEN_INT (m1);
2233 out[2] = GEN_INT (shift);
2234 out[3] = GEN_INT (m2);
2242 /* Return 1 if the operand is either a non-special register or a constant
2243 that can be used as the operand of a PowerPC64 logical AND insn. */
2246 and64_operand (rtx op, enum machine_mode mode)
2248 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2249 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2251 return (logical_operand (op, mode) || mask64_operand (op, mode));
2254 /* Like the above, but also match constants that can be implemented
2255 with two rldicl or rldicr insns. */
2258 and64_2_operand (rtx op, enum machine_mode mode)
2260 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2261 return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
2263 return logical_operand (op, mode) || mask64_2_operand (op, mode);
2266 /* Return 1 if the operand is either a non-special register or a
2267 constant that can be used as the operand of an RS/6000 logical AND insn. */
2270 and_operand (rtx op, enum machine_mode mode)
2272 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2273 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2275 return (logical_operand (op, mode) || mask_operand (op, mode));
2278 /* Return 1 if the operand is a general register or memory operand. */
2281 reg_or_mem_operand (rtx op, enum machine_mode mode)
2283 return (gpc_reg_operand (op, mode)
2284 || memory_operand (op, mode)
2285 || macho_lo_sum_memory_operand (op, mode)
2286 || volatile_mem_operand (op, mode));
2289 /* Return 1 if the operand is a general register or memory operand without
2290 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2294 lwa_operand (rtx op, enum machine_mode mode)
2298 if (reload_completed && GET_CODE (inner) == SUBREG)
2299 inner = SUBREG_REG (inner);
2301 return gpc_reg_operand (inner, mode)
2302 || (memory_operand (inner, mode)
2303 && GET_CODE (XEXP (inner, 0)) != PRE_INC
2304 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2305 && (GET_CODE (XEXP (inner, 0)) != PLUS
2306 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2307 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2310 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2313 symbol_ref_operand (rtx op, enum machine_mode mode)
2315 if (mode != VOIDmode && GET_MODE (op) != mode)
2319 if (GET_CODE (op) == SYMBOL_REF && TARGET_MACHO && MACHOPIC_INDIRECT)
2321 /* Macho says it has to go through a stub or be local
2322 when indirect mode. Stubs are considered local. */
2323 const char *t = XSTR (op, 0);
2324 /* "&" means that it is it a local defined symbol
2325 so it is okay to call to. */
2329 /* "!T" means that the function is local defined. */
2330 return (t[0] == '!' && t[1] == 'T');
2335 return (GET_CODE (op) == SYMBOL_REF
2336 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2339 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2340 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2343 call_operand (rtx op, enum machine_mode mode)
2345 if (mode != VOIDmode && GET_MODE (op) != mode)
2348 return (GET_CODE (op) == SYMBOL_REF
2349 || (GET_CODE (op) == REG
2350 && (REGNO (op) == LINK_REGISTER_REGNUM
2351 || REGNO (op) == COUNT_REGISTER_REGNUM
2352 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2355 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2359 current_file_function_operand (rtx op,
2360 enum machine_mode mode ATTRIBUTE_UNUSED)
2362 return (GET_CODE (op) == SYMBOL_REF
2363 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2364 && (SYMBOL_REF_LOCAL_P (op)
2365 || (op == XEXP (DECL_RTL (current_function_decl), 0))));
2368 /* Return 1 if this operand is a valid input for a move insn. */
2371 input_operand (rtx op, enum machine_mode mode)
2373 /* Memory is always valid. */
2374 if (memory_operand (op, mode))
2377 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
2378 if (GET_CODE (op) == CONSTANT_P_RTX)
2381 /* For floating-point, easy constants are valid. */
2382 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2384 && easy_fp_constant (op, mode))
2387 /* Allow any integer constant. */
2388 if (GET_MODE_CLASS (mode) == MODE_INT
2389 && (GET_CODE (op) == CONST_INT
2390 || GET_CODE (op) == CONST_DOUBLE))
2393 /* Allow easy vector constants. */
2394 if (GET_CODE (op) == CONST_VECTOR
2395 && easy_vector_constant (op, mode))
2398 /* For floating-point or multi-word mode, the only remaining valid type
2400 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2401 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
2402 return register_operand (op, mode);
2404 /* The only cases left are integral modes one word or smaller (we
2405 do not get called for MODE_CC values). These can be in any
2407 if (register_operand (op, mode))
2410 /* A SYMBOL_REF referring to the TOC is valid. */
2411 if (legitimate_constant_pool_address_p (op))
2414 /* A constant pool expression (relative to the TOC) is valid */
2415 if (toc_relative_expr_p (op))
2418 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
2420 if (DEFAULT_ABI == ABI_V4
2421 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
2422 && small_data_operand (op, Pmode))
2429 /* Darwin, AIX increases natural record alignment to doubleword if the first
2430 field is an FP double while the FP fields remain word aligned. */
2433 rs6000_special_round_type_align (tree type, int computed, int specified)
2435 tree field = TYPE_FIELDS (type);
2437 /* Skip all the static variables only if ABI is greater than
2439 while (field != NULL && TREE_CODE (field) == VAR_DECL)
2440 field = TREE_CHAIN (field);
2442 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
2443 return MAX (computed, specified);
2445 return MAX (MAX (computed, specified), 64);
2448 /* Return 1 for an operand in small memory on V.4/eabi. */
2451 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2452 enum machine_mode mode ATTRIBUTE_UNUSED)
2457 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2460 if (DEFAULT_ABI != ABI_V4)
2463 if (GET_CODE (op) == SYMBOL_REF)
2466 else if (GET_CODE (op) != CONST
2467 || GET_CODE (XEXP (op, 0)) != PLUS
2468 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2469 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2474 rtx sum = XEXP (op, 0);
2475 HOST_WIDE_INT summand;
2477 /* We have to be careful here, because it is the referenced address
2478 that must be 32k from _SDA_BASE_, not just the symbol. */
2479 summand = INTVAL (XEXP (sum, 1));
2480 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2483 sym_ref = XEXP (sum, 0);
2486 return SYMBOL_REF_SMALL_P (sym_ref);
2492 /* Return true, if operand is a memory operand and has a
2493 displacement divisible by 4. */
2496 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2501 if (!memory_operand (op, mode))
2504 addr = XEXP (op, 0);
2505 if (GET_CODE (addr) == PLUS
2506 && GET_CODE (XEXP (addr, 0)) == REG
2507 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
2508 off = INTVAL (XEXP (addr, 1));
2510 return (off % 4) == 0;
2513 /* Return true if either operand is a general purpose register. */
2516 gpr_or_gpr_p (rtx op0, rtx op1)
2518 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2519 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2523 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2526 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2528 switch (GET_CODE(op))
2531 if (RS6000_SYMBOL_REF_TLS_P (op))
2533 else if (CONSTANT_POOL_ADDRESS_P (op))
2535 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2543 else if (! strcmp (XSTR (op, 0), toc_label_name))
2552 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2553 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2555 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2564 constant_pool_expr_p (rtx op)
2568 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2572 toc_relative_expr_p (rtx op)
2576 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2579 /* SPE offset addressing is limited to 5-bits worth of double words. */
2580 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2583 legitimate_constant_pool_address_p (rtx x)
2586 && GET_CODE (x) == PLUS
2587 && GET_CODE (XEXP (x, 0)) == REG
2588 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2589 && constant_pool_expr_p (XEXP (x, 1)));
2593 legitimate_small_data_p (enum machine_mode mode, rtx x)
2595 return (DEFAULT_ABI == ABI_V4
2596 && !flag_pic && !TARGET_TOC
2597 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2598 && small_data_operand (x, mode));
2602 legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2604 unsigned HOST_WIDE_INT offset, extra;
2606 if (GET_CODE (x) != PLUS)
2608 if (GET_CODE (XEXP (x, 0)) != REG)
2610 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2612 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2615 offset = INTVAL (XEXP (x, 1));
2623 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2624 which leaves the only valid constant offset of zero, which by
2625 canonicalization rules is also invalid. */
2632 /* SPE vector modes. */
2633 return SPE_CONST_OFFSET_OK (offset);
2637 if (mode == DFmode || !TARGET_POWERPC64)
2639 else if (offset & 3)
2645 if (mode == TFmode || !TARGET_POWERPC64)
2647 else if (offset & 3)
2658 return (offset < 0x10000) && (offset + extra < 0x10000);
2662 legitimate_indexed_address_p (rtx x, int strict)
2666 if (GET_CODE (x) != PLUS)
2671 if (!REG_P (op0) || !REG_P (op1))
2674 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2675 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2676 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2677 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2681 legitimate_indirect_address_p (rtx x, int strict)
2683 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2687 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2689 if (!TARGET_MACHO || !flag_pic
2690 || mode != SImode || GET_CODE(x) != MEM)
2694 if (GET_CODE (x) != LO_SUM)
2696 if (GET_CODE (XEXP (x, 0)) != REG)
2698 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2702 return CONSTANT_P (x);
2706 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2708 if (GET_CODE (x) != LO_SUM)
2710 if (GET_CODE (XEXP (x, 0)) != REG)
2712 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2716 if (TARGET_ELF || TARGET_MACHO)
2718 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2722 if (GET_MODE_NUNITS (mode) != 1)
2724 if (GET_MODE_BITSIZE (mode) > 32
2725 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode))
2728 return CONSTANT_P (x);
2735 /* Try machine-dependent ways of modifying an illegitimate address
2736 to be legitimate. If we find one, return the new, valid address.
2737 This is used from only one place: `memory_address' in explow.c.
2739 OLDX is the address as it was before break_out_memory_refs was
2740 called. In some cases it is useful to look at this to decide what
2743 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2745 It is always safe for this function to do nothing. It exists to
2746 recognize opportunities to optimize the output.
2748 On RS/6000, first check for the sum of a register with a constant
2749 integer that is out of range. If so, generate code to add the
2750 constant with the low-order 16 bits masked to the register and force
2751 this result into another register (this can be done with `cau').
2752 Then generate an address of REG+(CONST&0xffff), allowing for the
2753 possibility of bit 16 being a one.
2755 Then check for the sum of a register and something not constant, try to
2756 load the other things into a register and return the sum. */
2759 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2760 enum machine_mode mode)
2762 if (GET_CODE (x) == SYMBOL_REF)
2764 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2766 return rs6000_legitimize_tls_address (x, model);
2769 if (GET_CODE (x) == PLUS
2770 && GET_CODE (XEXP (x, 0)) == REG
2771 && GET_CODE (XEXP (x, 1)) == CONST_INT
2772 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2774 HOST_WIDE_INT high_int, low_int;
2776 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2777 high_int = INTVAL (XEXP (x, 1)) - low_int;
2778 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2779 GEN_INT (high_int)), 0);
2780 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2782 else if (GET_CODE (x) == PLUS
2783 && GET_CODE (XEXP (x, 0)) == REG
2784 && GET_CODE (XEXP (x, 1)) != CONST_INT
2785 && GET_MODE_NUNITS (mode) == 1
2786 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2788 || (mode != DFmode && mode != TFmode))
2789 && (TARGET_POWERPC64 || mode != DImode)
2792 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2793 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2795 else if (ALTIVEC_VECTOR_MODE (mode))
2799 /* Make sure both operands are registers. */
2800 if (GET_CODE (x) == PLUS)
2801 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2802 force_reg (Pmode, XEXP (x, 1)));
2804 reg = force_reg (Pmode, x);
2807 else if (SPE_VECTOR_MODE (mode))
2809 /* We accept [reg + reg] and [reg + OFFSET]. */
2811 if (GET_CODE (x) == PLUS)
2813 rtx op1 = XEXP (x, 0);
2814 rtx op2 = XEXP (x, 1);
2816 op1 = force_reg (Pmode, op1);
2818 if (GET_CODE (op2) != REG
2819 && (GET_CODE (op2) != CONST_INT
2820 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2821 op2 = force_reg (Pmode, op2);
2823 return gen_rtx_PLUS (Pmode, op1, op2);
2826 return force_reg (Pmode, x);
2832 && GET_CODE (x) != CONST_INT
2833 && GET_CODE (x) != CONST_DOUBLE
2835 && GET_MODE_NUNITS (mode) == 1
2836 && (GET_MODE_BITSIZE (mode) <= 32
2837 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2839 rtx reg = gen_reg_rtx (Pmode);
2840 emit_insn (gen_elf_high (reg, x));
2841 return gen_rtx_LO_SUM (Pmode, reg, x);
2843 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2846 && ! MACHO_DYNAMIC_NO_PIC_P
2848 && GET_CODE (x) != CONST_INT
2849 && GET_CODE (x) != CONST_DOUBLE
2851 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2855 rtx reg = gen_reg_rtx (Pmode);
2856 emit_insn (gen_macho_high (reg, x));
2857 return gen_rtx_LO_SUM (Pmode, reg, x);
2860 && constant_pool_expr_p (x)
2861 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2863 return create_TOC_reference (x);
2869 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
2870 We need to emit DTP-relative relocations. */
2873 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2878 fputs ("\t.long\t", file);
2881 fputs (DOUBLE_INT_ASM_OP, file);
2886 output_addr_const (file, x);
2887 fputs ("@dtprel+0x8000", file);
2890 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2892 static GTY(()) rtx rs6000_tls_symbol;
2894 rs6000_tls_get_addr (void)
2896 if (!rs6000_tls_symbol)
2897 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2899 return rs6000_tls_symbol;
2902 /* Construct the SYMBOL_REF for TLS GOT references. */
2904 static GTY(()) rtx rs6000_got_symbol;
2906 rs6000_got_sym (void)
2908 if (!rs6000_got_symbol)
2910 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2911 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2912 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2915 return rs6000_got_symbol;
2918 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2919 this (thread-local) address. */
2922 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2926 dest = gen_reg_rtx (Pmode);
2927 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2933 tlsreg = gen_rtx_REG (Pmode, 13);
2934 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2938 tlsreg = gen_rtx_REG (Pmode, 2);
2939 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2943 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2947 tmp = gen_reg_rtx (Pmode);
2950 tlsreg = gen_rtx_REG (Pmode, 13);
2951 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2955 tlsreg = gen_rtx_REG (Pmode, 2);
2956 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2960 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2962 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2967 rtx r3, got, tga, tmp1, tmp2, eqv;
2970 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2974 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2977 rtx gsym = rs6000_got_sym ();
2978 got = gen_reg_rtx (Pmode);
2980 rs6000_emit_move (got, gsym, Pmode);
2984 static int tls_got_labelno = 0;
2985 rtx tempLR, lab, tmp3, mem;
2988 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
2989 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
2990 tempLR = gen_reg_rtx (Pmode);
2991 tmp1 = gen_reg_rtx (Pmode);
2992 tmp2 = gen_reg_rtx (Pmode);
2993 tmp3 = gen_reg_rtx (Pmode);
2994 mem = gen_rtx_MEM (Pmode, tmp1);
2995 RTX_UNCHANGING_P (mem) = 1;
2997 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
2999 emit_move_insn (tmp1, tempLR);
3000 emit_move_insn (tmp2, mem);
3001 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3002 last = emit_move_insn (got, tmp3);
3003 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3005 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3007 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3013 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3015 r3 = gen_rtx_REG (Pmode, 3);
3017 insn = gen_tls_gd_64 (r3, got, addr);
3019 insn = gen_tls_gd_32 (r3, got, addr);
3022 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3023 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3024 insn = emit_call_insn (insn);
3025 CONST_OR_PURE_CALL_P (insn) = 1;
3026 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3027 insn = get_insns ();
3029 emit_libcall_block (insn, dest, r3, addr);
3031 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3033 r3 = gen_rtx_REG (Pmode, 3);
3035 insn = gen_tls_ld_64 (r3, got);
3037 insn = gen_tls_ld_32 (r3, got);
3040 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3041 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3042 insn = emit_call_insn (insn);
3043 CONST_OR_PURE_CALL_P (insn) = 1;
3044 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3045 insn = get_insns ();
3047 tmp1 = gen_reg_rtx (Pmode);
3048 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3050 emit_libcall_block (insn, tmp1, r3, eqv);
3051 if (rs6000_tls_size == 16)
3054 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3056 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3058 else if (rs6000_tls_size == 32)
3060 tmp2 = gen_reg_rtx (Pmode);
3062 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3064 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3067 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3069 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3073 tmp2 = gen_reg_rtx (Pmode);
3075 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3077 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3079 insn = gen_rtx_SET (Pmode, dest,
3080 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3086 /* IE, or 64 bit offset LE. */
3087 tmp2 = gen_reg_rtx (Pmode);
3089 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3091 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3094 insn = gen_tls_tls_64 (dest, tmp2, addr);
3096 insn = gen_tls_tls_32 (dest, tmp2, addr);
3104 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
3105 instruction definitions. */
3108 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
3110 return RS6000_SYMBOL_REF_TLS_P (x);
3113 /* Return 1 if X contains a thread-local symbol. */
3116 rs6000_tls_referenced_p (rtx x)
3118 if (! TARGET_HAVE_TLS)
3121 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3124 /* Return 1 if *X is a thread-local symbol. This is the same as
3125 rs6000_tls_symbol_ref except for the type of the unused argument. */
3128 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3130 return RS6000_SYMBOL_REF_TLS_P (*x);
3133 /* The convention appears to be to define this wherever it is used.
3134 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3135 is now used here. */
3136 #ifndef REG_MODE_OK_FOR_BASE_P
3137 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3140 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3141 replace the input X, or the original X if no replacement is called for.
3142 The output parameter *WIN is 1 if the calling macro should goto WIN,
3145 For RS/6000, we wish to handle large displacements off a base
3146 register by splitting the addend across an addiu/addis and the mem insn.
3147 This cuts number of extra insns needed from 3 to 1.
3149 On Darwin, we use this to generate code for floating point constants.
3150 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3151 The Darwin code is inside #if TARGET_MACHO because only then is
3152 machopic_function_base_name() defined. */
3154 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3155 int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win)
3157 /* We must recognize output that we have already generated ourselves. */
3158 if (GET_CODE (x) == PLUS
3159 && GET_CODE (XEXP (x, 0)) == PLUS
3160 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3161 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3162 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3164 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3165 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3166 opnum, (enum reload_type)type);
3172 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3173 && GET_CODE (x) == LO_SUM
3174 && GET_CODE (XEXP (x, 0)) == PLUS
3175 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3176 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3177 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3178 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3179 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3180 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3181 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3183 /* Result of previous invocation of this function on Darwin
3184 floating point constant. */
3185 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3186 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3187 opnum, (enum reload_type)type);
3192 if (GET_CODE (x) == PLUS
3193 && GET_CODE (XEXP (x, 0)) == REG
3194 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3195 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3196 && GET_CODE (XEXP (x, 1)) == CONST_INT
3197 && !SPE_VECTOR_MODE (mode)
3198 && !ALTIVEC_VECTOR_MODE (mode))
3200 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3201 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3203 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3205 /* Check for 32-bit overflow. */
3206 if (high + low != val)
3212 /* Reload the high part into a base reg; leave the low part
3213 in the mem directly. */
3215 x = gen_rtx_PLUS (GET_MODE (x),
3216 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3220 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3221 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3222 opnum, (enum reload_type)type);
3227 if (GET_CODE (x) == SYMBOL_REF
3228 && DEFAULT_ABI == ABI_DARWIN
3229 && !ALTIVEC_VECTOR_MODE (mode)
3230 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3231 /* Don't do this for TFmode, since the result isn't offsettable. */
3236 rtx offset = gen_rtx_CONST (Pmode,
3237 gen_rtx_MINUS (Pmode, x,
3238 gen_rtx_SYMBOL_REF (Pmode,
3239 machopic_function_base_name ())));
3240 x = gen_rtx_LO_SUM (GET_MODE (x),
3241 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3242 gen_rtx_HIGH (Pmode, offset)), offset);
3245 x = gen_rtx_LO_SUM (GET_MODE (x),
3246 gen_rtx_HIGH (Pmode, x), x);
3248 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3249 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3250 opnum, (enum reload_type)type);
3256 && constant_pool_expr_p (x)
3257 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3259 (x) = create_TOC_reference (x);
3267 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3268 that is a valid memory address for an instruction.
3269 The MODE argument is the machine mode for the MEM expression
3270 that wants to use this address.
3272 On the RS/6000, there are four valid address: a SYMBOL_REF that
3273 refers to a constant pool entry of an address (or the sum of it
3274 plus a constant), a short (16-bit signed) constant plus a register,
3275 the sum of two registers, or a register indirect, possibly with an
3276 auto-increment. For DFmode and DImode with a constant plus register,
3277 we must ensure that both words are addressable or PowerPC64 with offset
3280 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3281 32-bit DImode, TImode), indexed addressing cannot be used because
3282 adjacent memory cells are accessed by adding word-sized offsets
3283 during assembly output. */
3285 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3287 if (RS6000_SYMBOL_REF_TLS_P (x))
3289 if (legitimate_indirect_address_p (x, reg_ok_strict))
3291 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3292 && !ALTIVEC_VECTOR_MODE (mode)
3293 && !SPE_VECTOR_MODE (mode)
3295 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3297 if (legitimate_small_data_p (mode, x))
3299 if (legitimate_constant_pool_address_p (x))
3301 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3303 && GET_CODE (x) == PLUS
3304 && GET_CODE (XEXP (x, 0)) == REG
3305 && (XEXP (x, 0) == virtual_stack_vars_rtx
3306 || XEXP (x, 0) == arg_pointer_rtx)
3307 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3309 if (legitimate_offset_address_p (mode, x, reg_ok_strict))
3312 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3314 || (mode != DFmode && mode != TFmode))
3315 && (TARGET_POWERPC64 || mode != DImode)
3316 && legitimate_indexed_address_p (x, reg_ok_strict))
3318 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3323 /* Go to LABEL if ADDR (a legitimate address expression)
3324 has an effect that depends on the machine mode it is used for.
3326 On the RS/6000 this is true of all integral offsets (since AltiVec
3327 modes don't allow them) or is a pre-increment or decrement.
3329 ??? Except that due to conceptual problems in offsettable_address_p
3330 we can't really report the problems of integral offsets. So leave
3331 this assuming that the adjustable offset must be valid for the
3332 sub-words of a TFmode operand, which is what we had before. */
3335 rs6000_mode_dependent_address (rtx addr)
3337 switch (GET_CODE (addr))
3340 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3342 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3343 return val + 12 + 0x8000 >= 0x10000;
3352 return TARGET_UPDATE;
3361 /* Try to output insns to set TARGET equal to the constant C if it can
3362 be done in less than N insns. Do all computations in MODE.
3363 Returns the place where the output has been placed if it can be
3364 done and the insns have been emitted. If it would take more than N
3365 insns, zero is returned and no insns and emitted. */
3368 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3369 rtx source, int n ATTRIBUTE_UNUSED)
3371 rtx result, insn, set;
3372 HOST_WIDE_INT c0, c1;
3374 if (mode == QImode || mode == HImode)
3377 dest = gen_reg_rtx (mode);
3378 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3381 else if (mode == SImode)
3383 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3385 emit_insn (gen_rtx_SET (VOIDmode, result,
3386 GEN_INT (INTVAL (source)
3387 & (~ (HOST_WIDE_INT) 0xffff))));
3388 emit_insn (gen_rtx_SET (VOIDmode, dest,
3389 gen_rtx_IOR (SImode, result,
3390 GEN_INT (INTVAL (source) & 0xffff))));
3393 else if (mode == DImode)
3395 if (GET_CODE (source) == CONST_INT)
3397 c0 = INTVAL (source);
3400 else if (GET_CODE (source) == CONST_DOUBLE)
3402 #if HOST_BITS_PER_WIDE_INT >= 64
3403 c0 = CONST_DOUBLE_LOW (source);
3406 c0 = CONST_DOUBLE_LOW (source);
3407 c1 = CONST_DOUBLE_HIGH (source);
3413 result = rs6000_emit_set_long_const (dest, c0, c1);
3418 insn = get_last_insn ();
3419 set = single_set (insn);
3420 if (! CONSTANT_P (SET_SRC (set)))
3421 set_unique_reg_note (insn, REG_EQUAL, source);
3426 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3427 fall back to a straight forward decomposition. We do this to avoid
3428 exponential run times encountered when looking for longer sequences
3429 with rs6000_emit_set_const. */
3431 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3433 if (!TARGET_POWERPC64)
3435 rtx operand1, operand2;
3437 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3439 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3441 emit_move_insn (operand1, GEN_INT (c1));
3442 emit_move_insn (operand2, GEN_INT (c2));
3446 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3449 ud2 = (c1 & 0xffff0000) >> 16;
3450 #if HOST_BITS_PER_WIDE_INT >= 64
3454 ud4 = (c2 & 0xffff0000) >> 16;
3456 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3457 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3460 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3462 emit_move_insn (dest, GEN_INT (ud1));
3465 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3466 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3469 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3472 emit_move_insn (dest, GEN_INT (ud2 << 16));
3474 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3476 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3477 || (ud4 == 0 && ! (ud3 & 0x8000)))
3480 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3483 emit_move_insn (dest, GEN_INT (ud3 << 16));
3486 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3487 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3489 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3494 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3497 emit_move_insn (dest, GEN_INT (ud4 << 16));
3500 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3502 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3504 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3505 GEN_INT (ud2 << 16)));
3507 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3513 /* Emit a move from SOURCE to DEST in mode MODE. */
3515 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3519 operands[1] = source;
3521 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3522 if (GET_CODE (operands[1]) == CONST_DOUBLE
3523 && ! FLOAT_MODE_P (mode)
3524 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3526 /* FIXME. This should never happen. */
3527 /* Since it seems that it does, do the safe thing and convert
3529 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3531 if (GET_CODE (operands[1]) == CONST_DOUBLE
3532 && ! FLOAT_MODE_P (mode)
3533 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3534 && CONST_DOUBLE_LOW (operands[1]) >= 0)
3535 || (CONST_DOUBLE_HIGH (operands[1]) == -1
3536 && CONST_DOUBLE_LOW (operands[1]) < 0)))
3539 /* Check if GCC is setting up a block move that will end up using FP
3540 registers as temporaries. We must make sure this is acceptable. */
3541 if (GET_CODE (operands[0]) == MEM
3542 && GET_CODE (operands[1]) == MEM
3544 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3545 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3546 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3547 ? 32 : MEM_ALIGN (operands[0])))
3548 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3550 : MEM_ALIGN (operands[1]))))
3551 && ! MEM_VOLATILE_P (operands [0])
3552 && ! MEM_VOLATILE_P (operands [1]))
3554 emit_move_insn (adjust_address (operands[0], SImode, 0),
3555 adjust_address (operands[1], SImode, 0));
3556 emit_move_insn (adjust_address (operands[0], SImode, 4),
3557 adjust_address (operands[1], SImode, 4));
3561 if (!no_new_pseudos)
3563 if (GET_CODE (operands[1]) == MEM && optimize > 0
3564 && (mode == QImode || mode == HImode || mode == SImode)
3565 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode))
3567 rtx reg = gen_reg_rtx (word_mode);
3569 emit_insn (gen_rtx_SET (word_mode, reg,
3570 gen_rtx_ZERO_EXTEND (word_mode,
3572 operands[1] = gen_lowpart (mode, reg);
3574 if (GET_CODE (operands[0]) != REG)
3575 operands[1] = force_reg (mode, operands[1]);
3578 if (mode == SFmode && ! TARGET_POWERPC
3579 && TARGET_HARD_FLOAT && TARGET_FPRS
3580 && GET_CODE (operands[0]) == MEM)
3584 if (reload_in_progress || reload_completed)
3585 regnum = true_regnum (operands[1]);
3586 else if (GET_CODE (operands[1]) == REG)
3587 regnum = REGNO (operands[1]);
3591 /* If operands[1] is a register, on POWER it may have
3592 double-precision data in it, so truncate it to single
3594 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3597 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3598 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3599 operands[1] = newreg;
3603 /* Recognize the case where operand[1] is a reference to thread-local
3604 data and load its address to a register. */
3605 if (GET_CODE (operands[1]) == SYMBOL_REF)
3607 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3609 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3612 /* Handle the case where reload calls us with an invalid address. */
3613 if (reload_in_progress && mode == Pmode
3614 && (! general_operand (operands[1], mode)
3615 || ! nonimmediate_operand (operands[0], mode)))
3618 /* Handle the case of CONSTANT_P_RTX. */
3619 if (GET_CODE (operands[1]) == CONSTANT_P_RTX)
3622 /* 128-bit constant floating-point values on Darwin should really be
3623 loaded as two parts. */
3624 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3625 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3626 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3628 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3629 know how to get a DFmode SUBREG of a TFmode. */
3630 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3631 simplify_gen_subreg (DImode, operands[1], mode, 0),
3633 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3634 GET_MODE_SIZE (DImode)),
3635 simplify_gen_subreg (DImode, operands[1], mode,
3636 GET_MODE_SIZE (DImode)),
3641 /* FIXME: In the long term, this switch statement should go away
3642 and be replaced by a sequence of tests based on things like
3648 if (CONSTANT_P (operands[1])
3649 && GET_CODE (operands[1]) != CONST_INT)
3650 operands[1] = force_const_mem (mode, operands[1]);
3656 if (CONSTANT_P (operands[1])
3657 && ! easy_fp_constant (operands[1], mode))
3658 operands[1] = force_const_mem (mode, operands[1]);
3669 if (CONSTANT_P (operands[1])
3670 && !easy_vector_constant (operands[1], mode))
3671 operands[1] = force_const_mem (mode, operands[1]);
3676 /* Use default pattern for address of ELF small data */
3679 && DEFAULT_ABI == ABI_V4
3680 && (GET_CODE (operands[1]) == SYMBOL_REF
3681 || GET_CODE (operands[1]) == CONST)
3682 && small_data_operand (operands[1], mode))
3684 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3688 if (DEFAULT_ABI == ABI_V4
3689 && mode == Pmode && mode == SImode
3690 && flag_pic == 1 && got_operand (operands[1], mode))
3692 emit_insn (gen_movsi_got (operands[0], operands[1]));
3696 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3700 && CONSTANT_P (operands[1])
3701 && GET_CODE (operands[1]) != HIGH
3702 && GET_CODE (operands[1]) != CONST_INT)
3704 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3706 /* If this is a function address on -mcall-aixdesc,
3707 convert it to the address of the descriptor. */
3708 if (DEFAULT_ABI == ABI_AIX
3709 && GET_CODE (operands[1]) == SYMBOL_REF
3710 && XSTR (operands[1], 0)[0] == '.')
3712 const char *name = XSTR (operands[1], 0);
3714 while (*name == '.')
3716 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3717 CONSTANT_POOL_ADDRESS_P (new_ref)
3718 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3719 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3720 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3721 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3722 operands[1] = new_ref;
3725 if (DEFAULT_ABI == ABI_DARWIN)
3728 if (MACHO_DYNAMIC_NO_PIC_P)
3730 /* Take care of any required data indirection. */
3731 operands[1] = rs6000_machopic_legitimize_pic_address (
3732 operands[1], mode, operands[0]);
3733 if (operands[0] != operands[1])
3734 emit_insn (gen_rtx_SET (VOIDmode,
3735 operands[0], operands[1]));
3739 emit_insn (gen_macho_high (target, operands[1]));
3740 emit_insn (gen_macho_low (operands[0], target, operands[1]));
3744 emit_insn (gen_elf_high (target, operands[1]));
3745 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3749 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3750 and we have put it in the TOC, we just need to make a TOC-relative
3753 && GET_CODE (operands[1]) == SYMBOL_REF
3754 && constant_pool_expr_p (operands[1])
3755 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3756 get_pool_mode (operands[1])))
3758 operands[1] = create_TOC_reference (operands[1]);
3760 else if (mode == Pmode
3761 && CONSTANT_P (operands[1])
3762 && ((GET_CODE (operands[1]) != CONST_INT
3763 && ! easy_fp_constant (operands[1], mode))
3764 || (GET_CODE (operands[1]) == CONST_INT
3765 && num_insns_constant (operands[1], mode) > 2)
3766 || (GET_CODE (operands[0]) == REG
3767 && FP_REGNO_P (REGNO (operands[0]))))
3768 && GET_CODE (operands[1]) != HIGH
3769 && ! legitimate_constant_pool_address_p (operands[1])
3770 && ! toc_relative_expr_p (operands[1]))
3772 /* Emit a USE operation so that the constant isn't deleted if
3773 expensive optimizations are turned on because nobody
3774 references it. This should only be done for operands that
3775 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3776 This should not be done for operands that contain LABEL_REFs.
3777 For now, we just handle the obvious case. */
3778 if (GET_CODE (operands[1]) != LABEL_REF)
3779 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3782 /* Darwin uses a special PIC legitimizer. */
3783 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3786 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3788 if (operands[0] != operands[1])
3789 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3794 /* If we are to limit the number of things we put in the TOC and
3795 this is a symbol plus a constant we can add in one insn,
3796 just put the symbol in the TOC and add the constant. Don't do
3797 this if reload is in progress. */
3798 if (GET_CODE (operands[1]) == CONST
3799 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3800 && GET_CODE (XEXP (operands[1], 0)) == PLUS
3801 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
3802 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3803 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3804 && ! side_effects_p (operands[0]))
3807 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
3808 rtx other = XEXP (XEXP (operands[1], 0), 1);
3810 sym = force_reg (mode, sym);
3812 emit_insn (gen_addsi3 (operands[0], sym, other));
3814 emit_insn (gen_adddi3 (operands[0], sym, other));
3818 operands[1] = force_const_mem (mode, operands[1]);
3821 && constant_pool_expr_p (XEXP (operands[1], 0))
3822 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3823 get_pool_constant (XEXP (operands[1], 0)),
3824 get_pool_mode (XEXP (operands[1], 0))))
3827 = gen_rtx_MEM (mode,
3828 create_TOC_reference (XEXP (operands[1], 0)));
3829 set_mem_alias_set (operands[1], get_TOC_alias_set ());
3830 RTX_UNCHANGING_P (operands[1]) = 1;
3836 if (GET_CODE (operands[0]) == MEM
3837 && GET_CODE (XEXP (operands[0], 0)) != REG
3838 && ! reload_in_progress)
3840 = replace_equiv_address (operands[0],
3841 copy_addr_to_reg (XEXP (operands[0], 0)));
3843 if (GET_CODE (operands[1]) == MEM
3844 && GET_CODE (XEXP (operands[1], 0)) != REG
3845 && ! reload_in_progress)
3847 = replace_equiv_address (operands[1],
3848 copy_addr_to_reg (XEXP (operands[1], 0)));
3851 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3853 gen_rtx_SET (VOIDmode,
3854 operands[0], operands[1]),
3855 gen_rtx_CLOBBER (VOIDmode,
3856 gen_rtx_SCRATCH (SImode)))));
3865 /* Above, we may have called force_const_mem which may have returned
3866 an invalid address. If we can, fix this up; otherwise, reload will
3867 have to deal with it. */
3868 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3869 operands[1] = validize_mem (operands[1]);
3872 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3875 /* Nonzero if we can use a floating-point register to pass this arg. */
3876 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3877 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3878 && (CUM)->fregno <= FP_ARG_MAX_REG \
3879 && TARGET_HARD_FLOAT && TARGET_FPRS)
3881 /* Nonzero if we can use an AltiVec register to pass this arg. */
3882 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3883 (ALTIVEC_VECTOR_MODE (MODE) \
3884 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3885 && TARGET_ALTIVEC_ABI \
3888 /* Return a nonzero value to say to return the function value in
3889 memory, just as large structures are always returned. TYPE will be
3890 the data type of the value, and FNTYPE will be the type of the
3891 function doing the returning, or @code{NULL} for libcalls.
3893 The AIX ABI for the RS/6000 specifies that all structures are
3894 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3895 specifies that structures <= 8 bytes are returned in r3/r4, but a
3896 draft put them in memory, and GCC used to implement the draft
3897 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3898 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3899 compatibility can change DRAFT_V4_STRUCT_RET to override the
3900 default, and -m switches get the final word. See
3901 rs6000_override_options for more details.
3903 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3904 long double support is enabled. These values are returned in memory.
3906 int_size_in_bytes returns -1 for variable size objects, which go in
3907 memory always. The cast to unsigned makes -1 > 8. */
3910 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3912 if (AGGREGATE_TYPE_P (type)
3913 && (TARGET_AIX_STRUCT_RET
3914 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3916 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3921 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3922 for a call to a function whose data type is FNTYPE.
3923 For a library call, FNTYPE is 0.
3925 For incoming args we set the number of arguments in the prototype large
3926 so we never return a PARALLEL. */
3929 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3930 rtx libname ATTRIBUTE_UNUSED, int incoming,
3931 int libcall, int n_named_args)
3933 static CUMULATIVE_ARGS zero_cumulative;
3935 *cum = zero_cumulative;
3937 cum->fregno = FP_ARG_MIN_REG;
3938 cum->vregno = ALTIVEC_ARG_MIN_REG;
3939 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3940 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3941 ? CALL_LIBCALL : CALL_NORMAL);
3942 cum->sysv_gregno = GP_ARG_MIN_REG;
3943 cum->stdarg = fntype
3944 && (TYPE_ARG_TYPES (fntype) != 0
3945 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3946 != void_type_node));
3948 cum->nargs_prototype = 0;
3949 if (incoming || cum->prototype)
3950 cum->nargs_prototype = n_named_args;
3952 /* Check for a longcall attribute. */
3954 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3955 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
3956 cum->call_cookie = CALL_LONG;
3958 if (TARGET_DEBUG_ARG)
3960 fprintf (stderr, "\ninit_cumulative_args:");
3963 tree ret_type = TREE_TYPE (fntype);
3964 fprintf (stderr, " ret code = %s,",
3965 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3968 if (cum->call_cookie & CALL_LONG)
3969 fprintf (stderr, " longcall,");
3971 fprintf (stderr, " proto = %d, nargs = %d\n",
3972 cum->prototype, cum->nargs_prototype);
3977 && TARGET_ALTIVEC_ABI
3978 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
3980 error ("Cannot return value in vector register because"
3981 " altivec instructions are disabled, use -maltivec"
3982 " to enable them.");
3986 /* If defined, a C expression which determines whether, and in which
3987 direction, to pad out an argument with extra space. The value
3988 should be of type `enum direction': either `upward' to pad above
3989 the argument, `downward' to pad below, or `none' to inhibit
3992 For the AIX ABI structs are always stored left shifted in their
3996 function_arg_padding (enum machine_mode mode, tree type)
3998 #ifndef AGGREGATE_PADDING_FIXED
3999 #define AGGREGATE_PADDING_FIXED 0
4001 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4002 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4005 if (!AGGREGATE_PADDING_FIXED)
4007 /* GCC used to pass structures of the same size as integer types as
4008 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4009 ie. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4010 passed padded downward, except that -mstrict-align further
4011 muddied the water in that multi-component structures of 2 and 4
4012 bytes in size were passed padded upward.
4014 The following arranges for best compatibility with previous
4015 versions of gcc, but removes the -mstrict-align dependency. */
4016 if (BYTES_BIG_ENDIAN)
4018 HOST_WIDE_INT size = 0;
4020 if (mode == BLKmode)
4022 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4023 size = int_size_in_bytes (type);
4026 size = GET_MODE_SIZE (mode);
4028 if (size == 1 || size == 2 || size == 4)
4034 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4036 if (type != 0 && AGGREGATE_TYPE_P (type))
4040 /* Fall back to the default. */
4041 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4044 /* If defined, a C expression that gives the alignment boundary, in bits,
4045 of an argument with the specified mode and type. If it is not defined,
4046 PARM_BOUNDARY is used for all arguments.
4048 V.4 wants long longs to be double word aligned. */
4051 function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED)
4053 if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode))
4055 else if (SPE_VECTOR_MODE (mode))
4057 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4060 return PARM_BOUNDARY;
4063 /* Compute the size (in words) of a function argument. */
4065 static unsigned long
4066 rs6000_arg_size (enum machine_mode mode, tree type)
4070 if (mode != BLKmode)
4071 size = GET_MODE_SIZE (mode);
4073 size = int_size_in_bytes (type);
4076 return (size + 3) >> 2;
4078 return (size + 7) >> 3;
4081 /* Update the data in CUM to advance over an argument
4082 of mode MODE and data type TYPE.
4083 (TYPE is null for libcalls where that information may not be available.) */
4086 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4087 tree type, int named)
4089 cum->nargs_prototype--;
4091 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4093 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4096 if (!TARGET_ALTIVEC)
4097 error ("Cannot pass argument in vector register because"
4098 " altivec instructions are disabled, use -maltivec"
4099 " to enable them.");
4101 /* PowerPC64 Linux and AIX allocates GPRs for a vector argument
4102 even if it is going to be passed in a vector register.
4103 Darwin does the same for variable-argument functions. */
4104 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4105 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4109 /* Vector parameters must be 16-byte aligned. This places
4110 them at 2 mod 4 in terms of words in 32-bit mode, since
4111 the parameter save area starts at offset 24 from the
4112 stack. In 64-bit mode, they just have to start on an
4113 even word, since the parameter save area is 16-byte
4114 aligned. Space for GPRs is reserved even if the argument
4115 will be passed in memory. */
4117 align = ((6 - (cum->words & 3)) & 3);
4119 align = cum->words & 1;
4120 cum->words += align + rs6000_arg_size (mode, type);
4122 if (TARGET_DEBUG_ARG)
4124 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4126 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4127 cum->nargs_prototype, cum->prototype,
4128 GET_MODE_NAME (mode));
4132 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4134 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4136 else if (DEFAULT_ABI == ABI_V4)
4138 if (TARGET_HARD_FLOAT && TARGET_FPRS
4139 && (mode == SFmode || mode == DFmode))
4141 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4146 cum->words += cum->words & 1;
4147 cum->words += rs6000_arg_size (mode, type);
4153 int gregno = cum->sysv_gregno;
4155 /* Aggregates and IEEE quad get passed by reference. */
4156 if ((type && AGGREGATE_TYPE_P (type))
4160 n_words = rs6000_arg_size (mode, type);
4162 /* Long long and SPE vectors are put in odd registers. */
4163 if (n_words == 2 && (gregno & 1) == 0)
4166 /* Long long and SPE vectors are not split between registers
4168 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4170 /* Long long is aligned on the stack. */
4172 cum->words += cum->words & 1;
4173 cum->words += n_words;
4176 /* Note: continuing to accumulate gregno past when we've started
4177 spilling to the stack indicates the fact that we've started
4178 spilling to the stack to expand_builtin_saveregs. */
4179 cum->sysv_gregno = gregno + n_words;
4182 if (TARGET_DEBUG_ARG)
4184 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4185 cum->words, cum->fregno);
4186 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4187 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4188 fprintf (stderr, "mode = %4s, named = %d\n",
4189 GET_MODE_NAME (mode), named);
4194 int align = (TARGET_32BIT && (cum->words & 1) != 0
4195 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
4197 cum->words += align + rs6000_arg_size (mode, type);
4199 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4200 && TARGET_HARD_FLOAT && TARGET_FPRS)
4201 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4203 if (TARGET_DEBUG_ARG)
4205 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4206 cum->words, cum->fregno);
4207 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4208 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4209 fprintf (stderr, "named = %d, align = %d\n", named, align);
4214 /* Determine where to put a SIMD argument on the SPE. */
4217 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4222 int gregno = cum->sysv_gregno;
4223 int n_words = rs6000_arg_size (mode, type);
4225 /* SPE vectors are put in odd registers. */
4226 if (n_words == 2 && (gregno & 1) == 0)
4229 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4232 enum machine_mode m = SImode;
4234 r1 = gen_rtx_REG (m, gregno);
4235 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4236 r2 = gen_rtx_REG (m, gregno + 1);
4237 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4238 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4245 if (cum->sysv_gregno <= GP_ARG_MAX_REG)
4246 return gen_rtx_REG (mode, cum->sysv_gregno);
4252 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4255 rs6000_mixed_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4256 tree type, int align_words)
4260 /* -mpowerpc64 with 32bit ABI splits up a DFmode argument
4261 in vararg list into zero, one or two GPRs */
4262 if (align_words >= GP_ARG_NUM_REG)
4263 return gen_rtx_PARALLEL (DFmode,
4265 gen_rtx_EXPR_LIST (VOIDmode,
4266 NULL_RTX, const0_rtx),
4267 gen_rtx_EXPR_LIST (VOIDmode,
4271 else if (align_words + rs6000_arg_size (mode, type)
4273 /* If this is partially on the stack, then we only
4274 include the portion actually in registers here. */
4275 return gen_rtx_PARALLEL (DFmode,
4277 gen_rtx_EXPR_LIST (VOIDmode,
4278 gen_rtx_REG (SImode,
4282 gen_rtx_EXPR_LIST (VOIDmode,
4287 /* split a DFmode arg into two GPRs */
4288 return gen_rtx_PARALLEL (DFmode,
4290 gen_rtx_EXPR_LIST (VOIDmode,
4291 gen_rtx_REG (SImode,
4295 gen_rtx_EXPR_LIST (VOIDmode,
4296 gen_rtx_REG (SImode,
4300 gen_rtx_EXPR_LIST (VOIDmode,
4301 gen_rtx_REG (mode, cum->fregno),
4304 /* -mpowerpc64 with 32bit ABI splits up a DImode argument into one
4306 else if (mode == DImode)
4308 if (align_words < GP_ARG_NUM_REG - 1)
4309 return gen_rtx_PARALLEL (DImode,
4311 gen_rtx_EXPR_LIST (VOIDmode,
4312 gen_rtx_REG (SImode,
4316 gen_rtx_EXPR_LIST (VOIDmode,
4317 gen_rtx_REG (SImode,
4321 else if (align_words == GP_ARG_NUM_REG - 1)
4322 return gen_rtx_PARALLEL (DImode,
4324 gen_rtx_EXPR_LIST (VOIDmode,
4325 NULL_RTX, const0_rtx),
4326 gen_rtx_EXPR_LIST (VOIDmode,
4327 gen_rtx_REG (SImode,
4332 else if (mode == BLKmode && align_words <= (GP_ARG_NUM_REG - 1))
4335 int size = int_size_in_bytes (type);
4336 int no_units = ((size - 1) / 4) + 1;
4337 int max_no_words = GP_ARG_NUM_REG - align_words;
4338 int rtlvec_len = no_units < max_no_words ? no_units : max_no_words;
4339 rtx *rtlvec = (rtx *) alloca (rtlvec_len * sizeof (rtx));
4341 memset ((char *) rtlvec, 0, rtlvec_len * sizeof (rtx));
4343 for (k=0; k < rtlvec_len; k++)
4344 rtlvec[k] = gen_rtx_EXPR_LIST (VOIDmode,
4345 gen_rtx_REG (SImode,
4348 k == 0 ? const0_rtx : GEN_INT (k*4));
4350 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k, rtlvec));
4356 /* Determine where to put an argument to a function.
4357 Value is zero to push the argument on the stack,
4358 or a hard register in which to store the argument.
4360 MODE is the argument's machine mode.
4361 TYPE is the data type of the argument (as a tree).
4362 This is null for libcalls where that information may
4364 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4365 the preceding args and about the function being called.
4366 NAMED is nonzero if this argument is a named parameter
4367 (otherwise it is an extra parameter matching an ellipsis).
4369 On RS/6000 the first eight words of non-FP are normally in registers
4370 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4371 Under V.4, the first 8 FP args are in registers.
4373 If this is floating-point and no prototype is specified, we use
4374 both an FP and integer register (or possibly FP reg and stack). Library
4375 functions (when CALL_LIBCALL is set) always have the proper types for args,
4376 so we can pass the FP value just in one register. emit_library_function
4377 doesn't support PARALLEL anyway. */
4380 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4381 tree type, int named)
4383 enum rs6000_abi abi = DEFAULT_ABI;
4385 /* Return a marker to indicate whether CR1 needs to set or clear the
4386 bit that V.4 uses to say fp args were passed in registers.
4387 Assume that we don't need the marker for software floating point,
4388 or compiler generated library calls. */
4389 if (mode == VOIDmode)
4392 && cum->nargs_prototype < 0
4393 && (cum->call_cookie & CALL_LIBCALL) == 0
4394 && (cum->prototype || TARGET_NO_PROTOTYPE))
4396 /* For the SPE, we need to crxor CR6 always. */
4398 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4399 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4400 return GEN_INT (cum->call_cookie
4401 | ((cum->fregno == FP_ARG_MIN_REG)
4402 ? CALL_V4_SET_FP_ARGS
4403 : CALL_V4_CLEAR_FP_ARGS));
4406 return GEN_INT (cum->call_cookie);
4409 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4410 if (TARGET_64BIT && ! cum->prototype)
4412 /* Vector parameters get passed in vector register
4413 and also in GPRs or memory, in absence of prototype. */
4416 align_words = (cum->words + 1) & ~1;
4418 if (align_words >= GP_ARG_NUM_REG)
4424 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4426 return gen_rtx_PARALLEL (mode,
4428 gen_rtx_EXPR_LIST (VOIDmode,
4430 gen_rtx_EXPR_LIST (VOIDmode,
4431 gen_rtx_REG (mode, cum->vregno),
4435 return gen_rtx_REG (mode, cum->vregno);
4436 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4438 if (named || abi == ABI_V4)
4442 /* Vector parameters to varargs functions under AIX or Darwin
4443 get passed in memory and possibly also in GPRs. */
4444 int align, align_words;
4445 enum machine_mode part_mode = mode;
4447 /* Vector parameters must be 16-byte aligned. This places them at
4448 2 mod 4 in terms of words in 32-bit mode, since the parameter
4449 save area starts at offset 24 from the stack. In 64-bit mode,
4450 they just have to start on an even word, since the parameter
4451 save area is 16-byte aligned. */
4453 align = ((6 - (cum->words & 3)) & 3);
4455 align = cum->words & 1;
4456 align_words = cum->words + align;
4458 /* Out of registers? Memory, then. */
4459 if (align_words >= GP_ARG_NUM_REG)
4462 /* The vector value goes in GPRs. Only the part of the
4463 value in GPRs is reported here. */
4464 if (align_words + CLASS_MAX_NREGS (mode, GENERAL_REGS)
4466 /* Fortunately, there are only two possibilities, the value
4467 is either wholly in GPRs or half in GPRs and half not. */
4470 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
4473 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
4474 return rs6000_spe_function_arg (cum, mode, type);
4475 else if (abi == ABI_V4)
4477 if (TARGET_HARD_FLOAT && TARGET_FPRS
4478 && (mode == SFmode || mode == DFmode))
4480 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4481 return gen_rtx_REG (mode, cum->fregno);
4488 int gregno = cum->sysv_gregno;
4490 /* Aggregates and IEEE quad get passed by reference. */
4491 if ((type && AGGREGATE_TYPE_P (type))
4495 n_words = rs6000_arg_size (mode, type);
4497 /* Long long and SPE vectors are put in odd registers. */
4498 if (n_words == 2 && (gregno & 1) == 0)
4501 /* Long long does not split between registers and stack. */
4502 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4503 return gen_rtx_REG (mode, gregno);
4510 int align = (TARGET_32BIT && (cum->words & 1) != 0
4511 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
4512 int align_words = cum->words + align;
4514 if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
4517 if (TARGET_32BIT && TARGET_POWERPC64
4518 && (mode == DImode || mode == BLKmode))
4519 return rs6000_mixed_function_arg (cum, mode, type, align_words);
4521 if (USE_FP_FOR_ARG_P (cum, mode, type))
4526 enum machine_mode fmode = mode;
4528 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4530 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4532 /* Long double split over regs and memory. */
4533 if (fmode == TFmode)
4536 /* Currently, we only ever need one reg here because complex
4537 doubles are split. */
4538 if (cum->fregno != FP_ARG_MAX_REG - 1)
4541 fpr[1] = gen_rtx_REG (fmode, cum->fregno);
4543 /* Do we also need to pass this arg in the parameter save
4546 && (cum->nargs_prototype <= 0
4547 || (DEFAULT_ABI == ABI_AIX
4549 && align_words >= GP_ARG_NUM_REG)));
4551 if (!needs_psave && mode == fmode)
4554 if (TARGET_32BIT && TARGET_POWERPC64
4555 && mode == DFmode && cum->stdarg)
4556 return rs6000_mixed_function_arg (cum, mode, type, align_words);
4558 /* Describe where this piece goes. */
4560 *r = gen_rtx_EXPR_LIST (VOIDmode, *r, const0_rtx);
4565 /* Now describe the part that goes in gprs or the stack.
4566 This piece must come first, before the fprs. */
4568 if (align_words < GP_ARG_NUM_REG)
4570 unsigned long n_words = rs6000_arg_size (mode, type);
4571 enum machine_mode rmode = mode;
4573 if (align_words + n_words > GP_ARG_NUM_REG)
4574 /* If this is partially on the stack, then we only
4575 include the portion actually in registers here.
4576 We know this can only be one register because
4577 complex doubles are splt. */
4579 reg = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
4581 *--r = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4585 return gen_rtx_PARALLEL (mode, gen_rtvec_v (n, r));
4587 else if (align_words < GP_ARG_NUM_REG)
4588 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4594 /* For an arg passed partly in registers and partly in memory,
4595 this is the number of registers used.
4596 For args passed entirely in registers or entirely in memory, zero. */
4599 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4600 tree type, int named)
4604 if (DEFAULT_ABI == ABI_V4)
4607 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
4608 && cum->nargs_prototype >= 0)
4611 if (USE_FP_FOR_ARG_P (cum, mode, type))
4613 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
4614 ret = FP_ARG_MAX_REG - cum->fregno;
4615 else if (cum->nargs_prototype >= 0)
4619 if (cum->words < GP_ARG_NUM_REG
4620 && GP_ARG_NUM_REG < cum->words + rs6000_arg_size (mode, type))
4621 ret = GP_ARG_NUM_REG - cum->words;
4623 if (ret != 0 && TARGET_DEBUG_ARG)
4624 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
4629 /* A C expression that indicates when an argument must be passed by
4630 reference. If nonzero for an argument, a copy of that argument is
4631 made in memory and a pointer to the argument is passed instead of
4632 the argument itself. The pointer is passed in whatever way is
4633 appropriate for passing a pointer to that type.
4635 Under V.4, structures and unions are passed by reference.
4637 As an extension to all ABIs, variable sized types are passed by
4641 function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4642 enum machine_mode mode ATTRIBUTE_UNUSED,
4643 tree type, int named ATTRIBUTE_UNUSED)
4645 if (DEFAULT_ABI == ABI_V4
4646 && ((type && AGGREGATE_TYPE_P (type))
4649 if (TARGET_DEBUG_ARG)
4650 fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
4654 return type && int_size_in_bytes (type) < 0;
4658 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
4661 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
4666 for (i = 0; i < nregs; i++)
4668 rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
4669 if (reload_completed)
4671 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
4674 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
4675 i * GET_MODE_SIZE(reg_mode));
4678 tem = replace_equiv_address (tem, XEXP (tem, 0));
4680 if (tem == NULL_RTX)
4683 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
4688 /* Perform any needed actions needed for a function that is receiving a
4689 variable number of arguments.
4693 MODE and TYPE are the mode and type of the current parameter.
4695 PRETEND_SIZE is a variable that should be set to the amount of stack
4696 that must be pushed by the prolog to pretend that our caller pushed
4699 Normally, this macro will push all remaining incoming registers on the
4700 stack and set PRETEND_SIZE to the length of the registers pushed. */
4703 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4704 tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
4706 CUMULATIVE_ARGS next_cum;
4707 int reg_size = TARGET_32BIT ? 4 : 8;
4708 rtx save_area = NULL_RTX, mem;
4709 int first_reg_offset, set;
4711 /* Skip the last named argument. */
4713 function_arg_advance (&next_cum, mode, type, 1);
4715 if (DEFAULT_ABI == ABI_V4)
4717 /* Indicate to allocate space on the stack for varargs save area. */
4718 cfun->machine->sysv_varargs_p = 1;
4720 save_area = plus_constant (virtual_stack_vars_rtx,
4721 - RS6000_VARARGS_SIZE);
4723 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4727 first_reg_offset = next_cum.words;
4728 save_area = virtual_incoming_args_rtx;
4729 cfun->machine->sysv_varargs_p = 0;
4731 if (MUST_PASS_IN_STACK (mode, type))
4732 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
4735 set = get_varargs_alias_set ();
4736 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
4738 mem = gen_rtx_MEM (BLKmode,
4739 plus_constant (save_area,
4740 first_reg_offset * reg_size)),
4741 set_mem_alias_set (mem, set);
4742 set_mem_align (mem, BITS_PER_WORD);
4744 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
4745 GP_ARG_NUM_REG - first_reg_offset);
4748 /* Save FP registers if needed. */
4749 if (DEFAULT_ABI == ABI_V4
4750 && TARGET_HARD_FLOAT && TARGET_FPRS
4752 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
4754 int fregno = next_cum.fregno;
4755 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4756 rtx lab = gen_label_rtx ();
4757 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4759 emit_jump_insn (gen_rtx_SET (VOIDmode,
4761 gen_rtx_IF_THEN_ELSE (VOIDmode,
4762 gen_rtx_NE (VOIDmode, cr1,
4764 gen_rtx_LABEL_REF (VOIDmode, lab),
4767 while (fregno <= FP_ARG_V4_MAX_REG)
4769 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
4770 set_mem_alias_set (mem, set);
4771 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
4780 /* Create the va_list data type. */
4783 rs6000_build_builtin_va_list (void)
4785 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
4787 /* For AIX, prefer 'char *' because that's what the system
4788 header files like. */
4789 if (DEFAULT_ABI != ABI_V4)
4790 return build_pointer_type (char_type_node);
4792 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4793 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4795 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
4796 unsigned_char_type_node);
4797 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
4798 unsigned_char_type_node);
4799 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
4801 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
4802 short_unsigned_type_node);
4803 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4805 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4808 DECL_FIELD_CONTEXT (f_gpr) = record;
4809 DECL_FIELD_CONTEXT (f_fpr) = record;
4810 DECL_FIELD_CONTEXT (f_res) = record;
4811 DECL_FIELD_CONTEXT (f_ovf) = record;
4812 DECL_FIELD_CONTEXT (f_sav) = record;
4814 TREE_CHAIN (record) = type_decl;
4815 TYPE_NAME (record) = type_decl;
4816 TYPE_FIELDS (record) = f_gpr;
4817 TREE_CHAIN (f_gpr) = f_fpr;
4818 TREE_CHAIN (f_fpr) = f_res;
4819 TREE_CHAIN (f_res) = f_ovf;
4820 TREE_CHAIN (f_ovf) = f_sav;
4822 layout_type (record);
4824 /* The correct type is an array type of one element. */
4825 return build_array_type (record, build_index_type (size_zero_node));
4828 /* Implement va_start. */
4831 rs6000_va_start (tree valist, rtx nextarg)
4833 HOST_WIDE_INT words, n_gpr, n_fpr;
4834 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4835 tree gpr, fpr, ovf, sav, t;
4837 /* Only SVR4 needs something special. */
4838 if (DEFAULT_ABI != ABI_V4)
4840 std_expand_builtin_va_start (valist, nextarg);
4844 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4845 f_fpr = TREE_CHAIN (f_gpr);
4846 f_res = TREE_CHAIN (f_fpr);
4847 f_ovf = TREE_CHAIN (f_res);
4848 f_sav = TREE_CHAIN (f_ovf);
4850 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4851 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4852 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4853 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4854 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4856 /* Count number of gp and fp argument registers used. */
4857 words = current_function_args_info.words;
4858 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
4859 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
4861 if (TARGET_DEBUG_ARG)
4862 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
4863 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
4864 words, n_gpr, n_fpr);
4866 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0));
4867 TREE_SIDE_EFFECTS (t) = 1;
4868 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4870 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0));
4871 TREE_SIDE_EFFECTS (t) = 1;
4872 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4874 /* Find the overflow area. */
4875 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
4877 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
4878 build_int_2 (words * UNITS_PER_WORD, 0));
4879 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4880 TREE_SIDE_EFFECTS (t) = 1;
4881 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4883 /* Find the register save area. */
4884 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
4885 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
4886 build_int_2 (-RS6000_VARARGS_SIZE, -1));
4887 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
4888 TREE_SIDE_EFFECTS (t) = 1;
4889 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4892 /* Implement va_arg. */
4895 rs6000_va_arg (tree valist, tree type)
4897 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4898 tree gpr, fpr, ovf, sav, reg, t, u;
4899 int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale;
4900 rtx lab_false, lab_over, addr_rtx, r;
4902 if (DEFAULT_ABI != ABI_V4)
4904 /* Variable sized types are passed by reference. */
4905 if (int_size_in_bytes (type) < 0)
4907 u = build_pointer_type (type);
4909 /* Args grow upward. */
4910 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
4911 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4912 TREE_SIDE_EFFECTS (t) = 1;
4914 t = build1 (NOP_EXPR, build_pointer_type (u), t);
4915 TREE_SIDE_EFFECTS (t) = 1;
4917 t = build1 (INDIRECT_REF, u, t);
4918 TREE_SIDE_EFFECTS (t) = 1;
4920 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4922 if (targetm.calls.split_complex_arg
4923 && TREE_CODE (type) == COMPLEX_TYPE)
4925 tree elem_type = TREE_TYPE (type);
4926 enum machine_mode elem_mode = TYPE_MODE (elem_type);
4927 int elem_size = GET_MODE_SIZE (elem_mode);
4929 if (elem_size < UNITS_PER_WORD)
4931 rtx real_part, imag_part, dest_real, rr;
4933 real_part = rs6000_va_arg (valist, elem_type);
4934 imag_part = rs6000_va_arg (valist, elem_type);
4936 /* We're not returning the value here, but the address.
4937 real_part and imag_part are not contiguous, and we know
4938 there is space available to pack real_part next to
4939 imag_part. float _Complex is not promoted to
4940 double _Complex by the default promotion rules that
4941 promote float to double. */
4942 if (2 * elem_size > UNITS_PER_WORD)
4945 real_part = gen_rtx_MEM (elem_mode, real_part);
4946 imag_part = gen_rtx_MEM (elem_mode, imag_part);
4948 dest_real = adjust_address (imag_part, elem_mode, -elem_size);
4949 rr = gen_reg_rtx (elem_mode);
4950 emit_move_insn (rr, real_part);
4951 emit_move_insn (dest_real, rr);
4953 return XEXP (dest_real, 0);
4957 return std_expand_builtin_va_arg (valist, type);
4960 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4961 f_fpr = TREE_CHAIN (f_gpr);
4962 f_res = TREE_CHAIN (f_fpr);
4963 f_ovf = TREE_CHAIN (f_res);
4964 f_sav = TREE_CHAIN (f_ovf);
4966 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4967 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4968 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4969 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4970 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4972 size = int_size_in_bytes (type);
4973 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4975 if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode)
4977 /* Aggregates and long doubles are passed by reference. */
4983 size = UNITS_PER_WORD;
4986 else if (FLOAT_TYPE_P (type) && TARGET_HARD_FLOAT && TARGET_FPRS)
4988 /* FP args go in FP registers, if present. */
4997 /* Otherwise into GP registers. */
5005 /* Pull the value out of the saved registers.... */
5007 lab_false = gen_label_rtx ();
5008 lab_over = gen_label_rtx ();
5009 addr_rtx = gen_reg_rtx (Pmode);
5011 /* AltiVec vectors never go in registers. */
5012 if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE)
5014 TREE_THIS_VOLATILE (reg) = 1;
5015 emit_cmp_and_jump_insns
5016 (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
5017 GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1,
5020 /* Long long is aligned in the registers. */
5023 u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5024 build_int_2 (n_reg - 1, 0));
5025 u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
5026 u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
5027 TREE_SIDE_EFFECTS (u) = 1;
5028 expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
5032 t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
5036 u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
5037 build_int_2 (n_reg, 0));
5038 TREE_SIDE_EFFECTS (u) = 1;
5040 u = build1 (CONVERT_EXPR, integer_type_node, u);
5041 TREE_SIDE_EFFECTS (u) = 1;
5043 u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
5044 TREE_SIDE_EFFECTS (u) = 1;
5046 t = build (PLUS_EXPR, ptr_type_node, t, u);
5047 TREE_SIDE_EFFECTS (t) = 1;
5049 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
5051 emit_move_insn (addr_rtx, r);
5053 emit_jump_insn (gen_jump (lab_over));
5057 emit_label (lab_false);
5059 /* ... otherwise out of the overflow area. */
5061 /* Make sure we don't find reg 7 for the next int arg.
5063 All AltiVec vectors go in the overflow area. So in the AltiVec
5064 case we need to get the vectors from the overflow area, but
5065 remember where the GPRs and FPRs are. */
5066 if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE
5067 || !TARGET_ALTIVEC))
5069 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
5070 TREE_SIDE_EFFECTS (t) = 1;
5071 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5074 /* Care for on-stack alignment if needed. */
5081 /* AltiVec vectors are 16 byte aligned. */
5082 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
5087 t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0));
5088 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1));
5092 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
5094 emit_move_insn (addr_rtx, r);
5096 t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0));
5097 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5098 TREE_SIDE_EFFECTS (t) = 1;
5099 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5101 emit_label (lab_over);
5105 r = gen_rtx_MEM (Pmode, addr_rtx);
5106 set_mem_alias_set (r, get_varargs_alias_set ());
5107 emit_move_insn (addr_rtx, r);
5115 #define def_builtin(MASK, NAME, TYPE, CODE) \
5117 if ((MASK) & target_flags) \
5118 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5122 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5124 static const struct builtin_description bdesc_3arg[] =
5126 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5127 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5128 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5129 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5130 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5131 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5132 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5133 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5134 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5135 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5136 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5137 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5138 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5139 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5140 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5141 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5142 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5143 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5144 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5145 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5146 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5147 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5148 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5151 /* DST operations: void foo (void *, const int, const char). */
5153 static const struct builtin_description bdesc_dst[] =
5155 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5156 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5157 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5158 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
5161 /* Simple binary operations: VECc = foo (VECa, VECb). */
5163 static struct builtin_description bdesc_2arg[] =
5165 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5166 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5167 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5168 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5169 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5170 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5171 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5172 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5173 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5174 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5175 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5176 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5177 { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5178 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5179 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5180 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5181 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5182 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5183 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5184 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5185 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5186 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5187 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5188 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5189 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5190 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5191 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5192 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5193 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5194 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5195 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5196 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5197 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5198 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5199 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5200 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5201 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5202 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5203 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5204 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5205 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5206 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5207 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5208 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5209 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5210 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5211 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5212 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5213 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5214 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5215 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5216 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5217 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5218 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5219 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5220 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
5221 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5222 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5223 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5224 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5225 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5226 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5227 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5228 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
5229 { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
5230 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
5231 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5232 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5233 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5234 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5235 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5236 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5237 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5238 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5239 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5240 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5241 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5242 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5243 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5244 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5245 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5246 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5247 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5248 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5249 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
5250 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5251 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5252 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
5253 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5254 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5255 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5256 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5257 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5258 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5259 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5260 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
5261 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5262 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5263 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5264 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
5265 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5266 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5267 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5268 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5269 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5270 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5271 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5272 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5273 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5274 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5275 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5276 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5277 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5279 /* Place holder, leave as first spe builtin. */
5280 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5281 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5282 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5283 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5284 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5285 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5286 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5287 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5288 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5289 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5290 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5291 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5292 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5293 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5294 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5295 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5296 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5297 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5298 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5299 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5300 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5301 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5302 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5303 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5304 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5305 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5306 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5307 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5308 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5309 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5310 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5311 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5312 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5313 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5314 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5315 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5316 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5317 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5318 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5319 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5320 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5321 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5322 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5323 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5324 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5325 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5326 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5327 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5328 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5329 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5330 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5331 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5332 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5333 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5334 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5335 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5336 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5337 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5338 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5339 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5340 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5341 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5342 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5343 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5344 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5345 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5346 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5347 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5348 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5349 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5350 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5351 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5352 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5353 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
5354 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5355 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
5356 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5357 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5358 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5359 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5360 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5361 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5362 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5363 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5364 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5365 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5366 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5367 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5368 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5369 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5370 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5371 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5372 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5373 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5374 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5375 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5376 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5377 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5378 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5379 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5380 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5381 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5382 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5383 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5384 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5385 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5386 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5387 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5388 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5390 /* SPE binary operations expecting a 5-bit unsigned literal. */
5391 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5393 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5394 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5395 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5396 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5397 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5398 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5399 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5400 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5401 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5402 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5403 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5404 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5405 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5406 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5407 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5408 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5409 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5410 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5411 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5412 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5413 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5414 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5415 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5416 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5417 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5418 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5420 /* Place-holder. Leave as last binary SPE builtin. */
5421 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
5424 /* AltiVec predicates. */
5426 struct builtin_description_predicates
5428 const unsigned int mask;
5429 const enum insn_code icode;
5431 const char *const name;
5432 const enum rs6000_builtins code;
5435 static const struct builtin_description_predicates bdesc_altivec_preds[] =
5437 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5438 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5439 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5440 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5441 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5442 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5443 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5444 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5445 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5446 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5447 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5448 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5449 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
5452 /* SPE predicates. */
5453 static struct builtin_description bdesc_spe_predicates[] =
5455 /* Place-holder. Leave as first. */
5456 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5457 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5458 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5459 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5460 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5461 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5462 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5463 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5464 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5465 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5466 /* Place-holder. Leave as last. */
5467 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5470 /* SPE evsel predicates. */
5471 static struct builtin_description bdesc_spe_evsel[] =
5473 /* Place-holder. Leave as first. */
5474 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5475 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5476 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5477 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5478 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5479 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5480 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5481 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5482 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5483 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5484 /* Place-holder. Leave as last. */
5485 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5488 /* ABS* operations. */
5490 static const struct builtin_description bdesc_abs[] =
5492 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5493 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5494 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5495 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5496 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5497 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5498 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5501 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5504 static struct builtin_description bdesc_1arg[] =
5506 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5507 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5508 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5509 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5510 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5511 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5512 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5513 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
5514 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5515 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5516 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
5517 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5518 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5519 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5520 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5521 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5522 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
5524 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5525 end with SPE_BUILTIN_EVSUBFUSIAAW. */
5526 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5527 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5528 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5529 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5530 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5531 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5532 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5533 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5534 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5535 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5536 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5537 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5538 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5539 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5540 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5541 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5542 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5543 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5544 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5545 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5546 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5547 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5548 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
5549 { 0, CODE_FOR_spe_evneg, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
5550 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5551 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5552 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5553 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
5555 /* Place-holder. Leave as last unary SPE builtin. */
5556 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
5560 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
5563 tree arg0 = TREE_VALUE (arglist);
5564 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5565 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5566 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5568 if (icode == CODE_FOR_nothing)
5569 /* Builtin not supported on this processor. */
5572 /* If we got invalid arguments bail out before generating bad rtl. */
5573 if (arg0 == error_mark_node)
5576 if (icode == CODE_FOR_altivec_vspltisb
5577 || icode == CODE_FOR_altivec_vspltish
5578 || icode == CODE_FOR_altivec_vspltisw
5579 || icode == CODE_FOR_spe_evsplatfi
5580 || icode == CODE_FOR_spe_evsplati)
5582 /* Only allow 5-bit *signed* literals. */
5583 if (GET_CODE (op0) != CONST_INT
5584 || INTVAL (op0) > 0x1f
5585 || INTVAL (op0) < -0x1f)
5587 error ("argument 1 must be a 5-bit signed literal");
5593 || GET_MODE (target) != tmode
5594 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5595 target = gen_reg_rtx (tmode);
5597 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5598 op0 = copy_to_mode_reg (mode0, op0);
5600 pat = GEN_FCN (icode) (target, op0);
5609 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
5611 rtx pat, scratch1, scratch2;
5612 tree arg0 = TREE_VALUE (arglist);
5613 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5614 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5615 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5617 /* If we have invalid arguments, bail out before generating bad rtl. */
5618 if (arg0 == error_mark_node)
5622 || GET_MODE (target) != tmode
5623 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5624 target = gen_reg_rtx (tmode);
5626 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5627 op0 = copy_to_mode_reg (mode0, op0);
5629 scratch1 = gen_reg_rtx (mode0);
5630 scratch2 = gen_reg_rtx (mode0);
5632 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
5641 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
5644 tree arg0 = TREE_VALUE (arglist);
5645 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5646 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5647 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5648 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5649 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5650 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5652 if (icode == CODE_FOR_nothing)
5653 /* Builtin not supported on this processor. */
5656 /* If we got invalid arguments bail out before generating bad rtl. */
5657 if (arg0 == error_mark_node || arg1 == error_mark_node)
5660 if (icode == CODE_FOR_altivec_vcfux
5661 || icode == CODE_FOR_altivec_vcfsx
5662 || icode == CODE_FOR_altivec_vctsxs
5663 || icode == CODE_FOR_altivec_vctuxs
5664 || icode == CODE_FOR_altivec_vspltb
5665 || icode == CODE_FOR_altivec_vsplth
5666 || icode == CODE_FOR_altivec_vspltw
5667 || icode == CODE_FOR_spe_evaddiw
5668 || icode == CODE_FOR_spe_evldd
5669 || icode == CODE_FOR_spe_evldh
5670 || icode == CODE_FOR_spe_evldw
5671 || icode == CODE_FOR_spe_evlhhesplat
5672 || icode == CODE_FOR_spe_evlhhossplat
5673 || icode == CODE_FOR_spe_evlhhousplat
5674 || icode == CODE_FOR_spe_evlwhe
5675 || icode == CODE_FOR_spe_evlwhos
5676 || icode == CODE_FOR_spe_evlwhou
5677 || icode == CODE_FOR_spe_evlwhsplat
5678 || icode == CODE_FOR_spe_evlwwsplat
5679 || icode == CODE_FOR_spe_evrlwi
5680 || icode == CODE_FOR_spe_evslwi
5681 || icode == CODE_FOR_spe_evsrwis
5682 || icode == CODE_FOR_spe_evsubifw
5683 || icode == CODE_FOR_spe_evsrwiu)
5685 /* Only allow 5-bit unsigned literals. */
5687 if (TREE_CODE (arg1) != INTEGER_CST
5688 || TREE_INT_CST_LOW (arg1) & ~0x1f)
5690 error ("argument 2 must be a 5-bit unsigned literal");
5696 || GET_MODE (target) != tmode
5697 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5698 target = gen_reg_rtx (tmode);
5700 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5701 op0 = copy_to_mode_reg (mode0, op0);
5702 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5703 op1 = copy_to_mode_reg (mode1, op1);
5705 pat = GEN_FCN (icode) (target, op0, op1);
5714 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
5715 tree arglist, rtx target)
5718 tree cr6_form = TREE_VALUE (arglist);
5719 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
5720 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5721 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5722 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5723 enum machine_mode tmode = SImode;
5724 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5725 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5728 if (TREE_CODE (cr6_form) != INTEGER_CST)
5730 error ("argument 1 of __builtin_altivec_predicate must be a constant");
5734 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
5739 /* If we have invalid arguments, bail out before generating bad rtl. */
5740 if (arg0 == error_mark_node || arg1 == error_mark_node)
5744 || GET_MODE (target) != tmode
5745 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5746 target = gen_reg_rtx (tmode);
5748 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5749 op0 = copy_to_mode_reg (mode0, op0);
5750 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5751 op1 = copy_to_mode_reg (mode1, op1);
5753 scratch = gen_reg_rtx (mode0);
5755 pat = GEN_FCN (icode) (scratch, op0, op1,
5756 gen_rtx_SYMBOL_REF (Pmode, opcode));
5761 /* The vec_any* and vec_all* predicates use the same opcodes for two
5762 different operations, but the bits in CR6 will be different
5763 depending on what information we want. So we have to play tricks
5764 with CR6 to get the right bits out.
5766 If you think this is disgusting, look at the specs for the
5767 AltiVec predicates. */
5769 switch (cr6_form_int)
5772 emit_insn (gen_cr6_test_for_zero (target));
5775 emit_insn (gen_cr6_test_for_zero_reverse (target));
5778 emit_insn (gen_cr6_test_for_lt (target));
5781 emit_insn (gen_cr6_test_for_lt_reverse (target));
5784 error ("argument 1 of __builtin_altivec_predicate is out of range");
5792 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
5795 tree arg0 = TREE_VALUE (arglist);
5796 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5797 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5798 enum machine_mode mode0 = Pmode;
5799 enum machine_mode mode1 = Pmode;
5800 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5801 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5803 if (icode == CODE_FOR_nothing)
5804 /* Builtin not supported on this processor. */
5807 /* If we got invalid arguments bail out before generating bad rtl. */
5808 if (arg0 == error_mark_node || arg1 == error_mark_node)
5812 || GET_MODE (target) != tmode
5813 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5814 target = gen_reg_rtx (tmode);
5816 op1 = copy_to_mode_reg (mode1, op1);
5818 if (op0 == const0_rtx)
5820 addr = gen_rtx_MEM (tmode, op1);
5824 op0 = copy_to_mode_reg (mode0, op0);
5825 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
5828 pat = GEN_FCN (icode) (target, addr);
5838 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
5840 tree arg0 = TREE_VALUE (arglist);
5841 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5842 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5843 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5844 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5845 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5847 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5848 enum machine_mode mode1 = Pmode;
5849 enum machine_mode mode2 = Pmode;
5851 /* Invalid arguments. Bail before doing anything stoopid! */
5852 if (arg0 == error_mark_node
5853 || arg1 == error_mark_node
5854 || arg2 == error_mark_node)
5857 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
5858 op0 = copy_to_mode_reg (tmode, op0);
5860 op2 = copy_to_mode_reg (mode2, op2);
5862 if (op1 == const0_rtx)
5864 addr = gen_rtx_MEM (tmode, op2);
5868 op1 = copy_to_mode_reg (mode1, op1);
5869 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
5872 pat = GEN_FCN (icode) (addr, op0);
5879 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
5882 tree arg0 = TREE_VALUE (arglist);
5883 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5884 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5885 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5886 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5887 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5888 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5889 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5890 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5891 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
5893 if (icode == CODE_FOR_nothing)
5894 /* Builtin not supported on this processor. */
5897 /* If we got invalid arguments bail out before generating bad rtl. */
5898 if (arg0 == error_mark_node
5899 || arg1 == error_mark_node
5900 || arg2 == error_mark_node)
5903 if (icode == CODE_FOR_altivec_vsldoi_4sf
5904 || icode == CODE_FOR_altivec_vsldoi_4si
5905 || icode == CODE_FOR_altivec_vsldoi_8hi
5906 || icode == CODE_FOR_altivec_vsldoi_16qi)
5908 /* Only allow 4-bit unsigned literals. */
5910 if (TREE_CODE (arg2) != INTEGER_CST
5911 || TREE_INT_CST_LOW (arg2) & ~0xf)
5913 error ("argument 3 must be a 4-bit unsigned literal");
5919 || GET_MODE (target) != tmode
5920 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5921 target = gen_reg_rtx (tmode);
5923 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5924 op0 = copy_to_mode_reg (mode0, op0);
5925 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5926 op1 = copy_to_mode_reg (mode1, op1);
5927 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
5928 op2 = copy_to_mode_reg (mode2, op2);
5930 pat = GEN_FCN (icode) (target, op0, op1, op2);
5938 /* Expand the lvx builtins. */
5940 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
5942 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5943 tree arglist = TREE_OPERAND (exp, 1);
5944 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5946 enum machine_mode tmode, mode0;
5948 enum insn_code icode;
5952 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
5953 icode = CODE_FOR_altivec_lvx_16qi;
5955 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
5956 icode = CODE_FOR_altivec_lvx_8hi;
5958 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
5959 icode = CODE_FOR_altivec_lvx_4si;
5961 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
5962 icode = CODE_FOR_altivec_lvx_4sf;
5971 arg0 = TREE_VALUE (arglist);
5972 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5973 tmode = insn_data[icode].operand[0].mode;
5974 mode0 = insn_data[icode].operand[1].mode;
5977 || GET_MODE (target) != tmode
5978 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5979 target = gen_reg_rtx (tmode);
5981 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5982 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5984 pat = GEN_FCN (icode) (target, op0);
5991 /* Expand the stvx builtins. */
5993 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
5996 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5997 tree arglist = TREE_OPERAND (exp, 1);
5998 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6000 enum machine_mode mode0, mode1;
6002 enum insn_code icode;
6006 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6007 icode = CODE_FOR_altivec_stvx_16qi;
6009 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6010 icode = CODE_FOR_altivec_stvx_8hi;
6012 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6013 icode = CODE_FOR_altivec_stvx_4si;
6015 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6016 icode = CODE_FOR_altivec_stvx_4sf;
6023 arg0 = TREE_VALUE (arglist);
6024 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6025 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6026 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6027 mode0 = insn_data[icode].operand[0].mode;
6028 mode1 = insn_data[icode].operand[1].mode;
6030 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6031 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6032 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6033 op1 = copy_to_mode_reg (mode1, op1);
6035 pat = GEN_FCN (icode) (op0, op1);
6043 /* Expand the dst builtins. */
6045 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6048 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6049 tree arglist = TREE_OPERAND (exp, 1);
6050 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6051 tree arg0, arg1, arg2;
6052 enum machine_mode mode0, mode1, mode2;
6053 rtx pat, op0, op1, op2;
6054 struct builtin_description *d;
6059 /* Handle DST variants. */
6060 d = (struct builtin_description *) bdesc_dst;
6061 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6062 if (d->code == fcode)
6064 arg0 = TREE_VALUE (arglist);
6065 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6066 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6067 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6068 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6069 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6070 mode0 = insn_data[d->icode].operand[0].mode;
6071 mode1 = insn_data[d->icode].operand[1].mode;
6072 mode2 = insn_data[d->icode].operand[2].mode;
6074 /* Invalid arguments, bail out before generating bad rtl. */
6075 if (arg0 == error_mark_node
6076 || arg1 == error_mark_node
6077 || arg2 == error_mark_node)
6082 if (TREE_CODE (arg2) != INTEGER_CST
6083 || TREE_INT_CST_LOW (arg2) & ~0x3)
6085 error ("argument to `%s' must be a 2-bit unsigned literal", d->name);
6089 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
6090 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6091 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6092 op1 = copy_to_mode_reg (mode1, op1);
6094 pat = GEN_FCN (d->icode) (op0, op1, op2);
6104 /* Expand the builtin in EXP and store the result in TARGET. Store
6105 true in *EXPANDEDP if we found a builtin to expand. */
6107 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
6109 struct builtin_description *d;
6110 struct builtin_description_predicates *dp;
6112 enum insn_code icode;
6113 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6114 tree arglist = TREE_OPERAND (exp, 1);
6117 enum machine_mode tmode, mode0;
6118 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6120 target = altivec_expand_ld_builtin (exp, target, expandedp);
6124 target = altivec_expand_st_builtin (exp, target, expandedp);
6128 target = altivec_expand_dst_builtin (exp, target, expandedp);
6136 case ALTIVEC_BUILTIN_STVX:
6137 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6138 case ALTIVEC_BUILTIN_STVEBX:
6139 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6140 case ALTIVEC_BUILTIN_STVEHX:
6141 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6142 case ALTIVEC_BUILTIN_STVEWX:
6143 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6144 case ALTIVEC_BUILTIN_STVXL:
6145 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
6147 case ALTIVEC_BUILTIN_MFVSCR:
6148 icode = CODE_FOR_altivec_mfvscr;
6149 tmode = insn_data[icode].operand[0].mode;
6152 || GET_MODE (target) != tmode
6153 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6154 target = gen_reg_rtx (tmode);
6156 pat = GEN_FCN (icode) (target);
6162 case ALTIVEC_BUILTIN_MTVSCR:
6163 icode = CODE_FOR_altivec_mtvscr;
6164 arg0 = TREE_VALUE (arglist);
6165 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6166 mode0 = insn_data[icode].operand[0].mode;
6168 /* If we got invalid arguments bail out before generating bad rtl. */
6169 if (arg0 == error_mark_node)
6172 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6173 op0 = copy_to_mode_reg (mode0, op0);
6175 pat = GEN_FCN (icode) (op0);
6180 case ALTIVEC_BUILTIN_DSSALL:
6181 emit_insn (gen_altivec_dssall ());
6184 case ALTIVEC_BUILTIN_DSS:
6185 icode = CODE_FOR_altivec_dss;
6186 arg0 = TREE_VALUE (arglist);
6188 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6189 mode0 = insn_data[icode].operand[0].mode;
6191 /* If we got invalid arguments bail out before generating bad rtl. */
6192 if (arg0 == error_mark_node)
6195 if (TREE_CODE (arg0) != INTEGER_CST
6196 || TREE_INT_CST_LOW (arg0) & ~0x3)
6198 error ("argument to dss must be a 2-bit unsigned literal");
6202 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6203 op0 = copy_to_mode_reg (mode0, op0);
6205 emit_insn (gen_altivec_dss (op0));
6208 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
6209 arg0 = TREE_VALUE (arglist);
6210 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR)
6211 arg0 = TREE_OPERAND (arg0, 0);
6212 error ("invalid parameter combination for `%s' AltiVec intrinsic",
6213 TREE_STRING_POINTER (arg0));
6218 /* Expand abs* operations. */
6219 d = (struct builtin_description *) bdesc_abs;
6220 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6221 if (d->code == fcode)
6222 return altivec_expand_abs_builtin (d->icode, arglist, target);
6224 /* Expand the AltiVec predicates. */
6225 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6226 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6227 if (dp->code == fcode)
6228 return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target);
6230 /* LV* are funky. We initialized them differently. */
6233 case ALTIVEC_BUILTIN_LVSL:
6234 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
6236 case ALTIVEC_BUILTIN_LVSR:
6237 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
6239 case ALTIVEC_BUILTIN_LVEBX:
6240 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
6242 case ALTIVEC_BUILTIN_LVEHX:
6243 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
6245 case ALTIVEC_BUILTIN_LVEWX:
6246 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
6248 case ALTIVEC_BUILTIN_LVXL:
6249 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
6251 case ALTIVEC_BUILTIN_LVX:
6252 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
6263 /* Binops that need to be initialized manually, but can be expanded
6264 automagically by rs6000_expand_binop_builtin. */
6265 static struct builtin_description bdesc_2arg_spe[] =
6267 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6268 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6269 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6270 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6271 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6272 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6273 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6274 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6275 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6276 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6277 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6278 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6279 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6280 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6281 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6282 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6283 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6284 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6285 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6286 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6287 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6288 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6291 /* Expand the builtin in EXP and store the result in TARGET. Store
6292 true in *EXPANDEDP if we found a builtin to expand.
6294 This expands the SPE builtins that are not simple unary and binary
6297 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
6299 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6300 tree arglist = TREE_OPERAND (exp, 1);
6302 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6303 enum insn_code icode;
6304 enum machine_mode tmode, mode0;
6306 struct builtin_description *d;
6311 /* Syntax check for a 5-bit unsigned immediate. */
6314 case SPE_BUILTIN_EVSTDD:
6315 case SPE_BUILTIN_EVSTDH:
6316 case SPE_BUILTIN_EVSTDW:
6317 case SPE_BUILTIN_EVSTWHE:
6318 case SPE_BUILTIN_EVSTWHO:
6319 case SPE_BUILTIN_EVSTWWE:
6320 case SPE_BUILTIN_EVSTWWO:
6321 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6322 if (TREE_CODE (arg1) != INTEGER_CST
6323 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6325 error ("argument 2 must be a 5-bit unsigned literal");
6333 /* The evsplat*i instructions are not quite generic. */
6336 case SPE_BUILTIN_EVSPLATFI:
6337 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6339 case SPE_BUILTIN_EVSPLATI:
6340 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6346 d = (struct builtin_description *) bdesc_2arg_spe;
6347 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6348 if (d->code == fcode)
6349 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6351 d = (struct builtin_description *) bdesc_spe_predicates;
6352 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6353 if (d->code == fcode)
6354 return spe_expand_predicate_builtin (d->icode, arglist, target);
6356 d = (struct builtin_description *) bdesc_spe_evsel;
6357 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6358 if (d->code == fcode)
6359 return spe_expand_evsel_builtin (d->icode, arglist, target);
6363 case SPE_BUILTIN_EVSTDDX:
6364 return altivec_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
6365 case SPE_BUILTIN_EVSTDHX:
6366 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
6367 case SPE_BUILTIN_EVSTDWX:
6368 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
6369 case SPE_BUILTIN_EVSTWHEX:
6370 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
6371 case SPE_BUILTIN_EVSTWHOX:
6372 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
6373 case SPE_BUILTIN_EVSTWWEX:
6374 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
6375 case SPE_BUILTIN_EVSTWWOX:
6376 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
6377 case SPE_BUILTIN_EVSTDD:
6378 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
6379 case SPE_BUILTIN_EVSTDH:
6380 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
6381 case SPE_BUILTIN_EVSTDW:
6382 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
6383 case SPE_BUILTIN_EVSTWHE:
6384 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
6385 case SPE_BUILTIN_EVSTWHO:
6386 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
6387 case SPE_BUILTIN_EVSTWWE:
6388 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
6389 case SPE_BUILTIN_EVSTWWO:
6390 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
6391 case SPE_BUILTIN_MFSPEFSCR:
6392 icode = CODE_FOR_spe_mfspefscr;
6393 tmode = insn_data[icode].operand[0].mode;
6396 || GET_MODE (target) != tmode
6397 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6398 target = gen_reg_rtx (tmode);
6400 pat = GEN_FCN (icode) (target);
6405 case SPE_BUILTIN_MTSPEFSCR:
6406 icode = CODE_FOR_spe_mtspefscr;
6407 arg0 = TREE_VALUE (arglist);
6408 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6409 mode0 = insn_data[icode].operand[0].mode;
6411 if (arg0 == error_mark_node)
6414 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6415 op0 = copy_to_mode_reg (mode0, op0);
6417 pat = GEN_FCN (icode) (op0);
6430 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
6432 rtx pat, scratch, tmp;
6433 tree form = TREE_VALUE (arglist);
6434 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6435 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6436 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6437 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6438 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6439 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6443 if (TREE_CODE (form) != INTEGER_CST)
6445 error ("argument 1 of __builtin_spe_predicate must be a constant");
6449 form_int = TREE_INT_CST_LOW (form);
6454 if (arg0 == error_mark_node || arg1 == error_mark_node)
6458 || GET_MODE (target) != SImode
6459 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6460 target = gen_reg_rtx (SImode);
6462 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6463 op0 = copy_to_mode_reg (mode0, op0);
6464 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6465 op1 = copy_to_mode_reg (mode1, op1);
6467 scratch = gen_reg_rtx (CCmode);
6469 pat = GEN_FCN (icode) (scratch, op0, op1);
6474 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6475 _lower_. We use one compare, but look in different bits of the
6476 CR for each variant.
6478 There are 2 elements in each SPE simd type (upper/lower). The CR
6479 bits are set as follows:
6481 BIT0 | BIT 1 | BIT 2 | BIT 3
6482 U | L | (U | L) | (U & L)
6484 So, for an "all" relationship, BIT 3 would be set.
6485 For an "any" relationship, BIT 2 would be set. Etc.
6487 Following traditional nomenclature, these bits map to:
6489 BIT0 | BIT 1 | BIT 2 | BIT 3
6492 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6497 /* All variant. OV bit. */
6499 /* We need to get to the OV bit, which is the ORDERED bit. We
6500 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6501 that's ugly and will trigger a validate_condition_mode abort.
6502 So let's just use another pattern. */
6503 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6505 /* Any variant. EQ bit. */
6509 /* Upper variant. LT bit. */
6513 /* Lower variant. GT bit. */
6518 error ("argument 1 of __builtin_spe_predicate is out of range");
6522 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6523 emit_move_insn (target, tmp);
6528 /* The evsel builtins look like this:
6530 e = __builtin_spe_evsel_OP (a, b, c, d);
6534 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6535 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6539 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
6542 tree arg0 = TREE_VALUE (arglist);
6543 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6544 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6545 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6546 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6547 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6548 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6549 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6550 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6551 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6556 if (arg0 == error_mark_node || arg1 == error_mark_node
6557 || arg2 == error_mark_node || arg3 == error_mark_node)
6561 || GET_MODE (target) != mode0
6562 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6563 target = gen_reg_rtx (mode0);
6565 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6566 op0 = copy_to_mode_reg (mode0, op0);
6567 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6568 op1 = copy_to_mode_reg (mode0, op1);
6569 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6570 op2 = copy_to_mode_reg (mode0, op2);
6571 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6572 op3 = copy_to_mode_reg (mode0, op3);
6574 /* Generate the compare. */
6575 scratch = gen_reg_rtx (CCmode);
6576 pat = GEN_FCN (icode) (scratch, op0, op1);
6581 if (mode0 == V2SImode)
6582 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
6584 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
6589 /* Expand an expression EXP that calls a built-in function,
6590 with result going to TARGET if that's convenient
6591 (and in mode MODE if that's convenient).
6592 SUBTARGET may be used as the target for computing one of EXP's operands.
6593 IGNORE is nonzero if the value is to be ignored. */
6596 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
6597 enum machine_mode mode ATTRIBUTE_UNUSED,
6598 int ignore ATTRIBUTE_UNUSED)
6600 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6601 tree arglist = TREE_OPERAND (exp, 1);
6602 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6603 struct builtin_description *d;
6610 ret = altivec_expand_builtin (exp, target, &success);
6617 ret = spe_expand_builtin (exp, target, &success);
6623 if (TARGET_ALTIVEC || TARGET_SPE)
6625 /* Handle simple unary operations. */
6626 d = (struct builtin_description *) bdesc_1arg;
6627 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
6628 if (d->code == fcode)
6629 return rs6000_expand_unop_builtin (d->icode, arglist, target);
6631 /* Handle simple binary operations. */
6632 d = (struct builtin_description *) bdesc_2arg;
6633 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
6634 if (d->code == fcode)
6635 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6637 /* Handle simple ternary operations. */
6638 d = (struct builtin_description *) bdesc_3arg;
6639 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
6640 if (d->code == fcode)
6641 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
6649 rs6000_init_builtins (void)
6651 V2SI_type_node = build_vector_type (intSI_type_node, 2);
6652 V2SF_type_node = build_vector_type (float_type_node, 2);
6653 V4HI_type_node = build_vector_type (intHI_type_node, 4);
6654 V4SI_type_node = build_vector_type (intSI_type_node, 4);
6655 V4SF_type_node = build_vector_type (float_type_node, 4);
6656 V8HI_type_node = build_vector_type (intHI_type_node, 8);
6657 V16QI_type_node = build_vector_type (intQI_type_node, 16);
6659 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
6660 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
6661 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
6663 opaque_V2SI_type_node = copy_node (V2SI_type_node);
6664 opaque_V2SF_type_node = copy_node (V2SF_type_node);
6665 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
6667 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
6668 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
6669 'vector unsigned short'. */
6671 bool_char_type_node = copy_node (unsigned_intQI_type_node);
6672 TYPE_MAIN_VARIANT (bool_char_type_node) = bool_char_type_node;
6673 bool_short_type_node = copy_node (unsigned_intHI_type_node);
6674 TYPE_MAIN_VARIANT (bool_short_type_node) = bool_short_type_node;
6675 bool_int_type_node = copy_node (unsigned_intSI_type_node);
6676 TYPE_MAIN_VARIANT (bool_int_type_node) = bool_int_type_node;
6677 pixel_type_node = copy_node (unsigned_intHI_type_node);
6678 TYPE_MAIN_VARIANT (pixel_type_node) = pixel_type_node;
6680 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6681 get_identifier ("__bool char"),
6682 bool_char_type_node));
6683 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6684 get_identifier ("__bool short"),
6685 bool_short_type_node));
6686 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6687 get_identifier ("__bool int"),
6688 bool_int_type_node));
6689 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6690 get_identifier ("__pixel"),
6693 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
6694 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
6695 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
6696 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
6698 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6699 get_identifier ("__vector unsigned char"),
6700 unsigned_V16QI_type_node));
6701 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6702 get_identifier ("__vector signed char"),
6704 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6705 get_identifier ("__vector __bool char"),
6706 bool_V16QI_type_node));
6708 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6709 get_identifier ("__vector unsigned short"),
6710 unsigned_V8HI_type_node));
6711 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6712 get_identifier ("__vector signed short"),
6714 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6715 get_identifier ("__vector __bool short"),
6716 bool_V8HI_type_node));
6718 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6719 get_identifier ("__vector unsigned int"),
6720 unsigned_V4SI_type_node));
6721 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6722 get_identifier ("__vector signed int"),
6724 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6725 get_identifier ("__vector __bool int"),
6726 bool_V4SI_type_node));
6728 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6729 get_identifier ("__vector float"),
6731 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6732 get_identifier ("__vector __pixel"),
6733 pixel_V8HI_type_node));
6736 spe_init_builtins ();
6738 altivec_init_builtins ();
6739 if (TARGET_ALTIVEC || TARGET_SPE)
6740 rs6000_common_init_builtins ();
6743 /* Search through a set of builtins and enable the mask bits.
6744 DESC is an array of builtins.
6745 SIZE is the total number of builtins.
6746 START is the builtin enum at which to start.
6747 END is the builtin enum at which to end. */
6749 enable_mask_for_builtins (struct builtin_description *desc, int size,
6750 enum rs6000_builtins start,
6751 enum rs6000_builtins end)
6755 for (i = 0; i < size; ++i)
6756 if (desc[i].code == start)
6762 for (; i < size; ++i)
6764 /* Flip all the bits on. */
6765 desc[i].mask = target_flags;
6766 if (desc[i].code == end)
6772 spe_init_builtins (void)
6774 tree endlink = void_list_node;
6775 tree puint_type_node = build_pointer_type (unsigned_type_node);
6776 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
6777 struct builtin_description *d;
6780 tree v2si_ftype_4_v2si
6781 = build_function_type
6782 (opaque_V2SI_type_node,
6783 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6784 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6785 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6786 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6789 tree v2sf_ftype_4_v2sf
6790 = build_function_type
6791 (opaque_V2SF_type_node,
6792 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6793 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6794 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6795 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6798 tree int_ftype_int_v2si_v2si
6799 = build_function_type
6801 tree_cons (NULL_TREE, integer_type_node,
6802 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6803 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6806 tree int_ftype_int_v2sf_v2sf
6807 = build_function_type
6809 tree_cons (NULL_TREE, integer_type_node,
6810 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6811 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6814 tree void_ftype_v2si_puint_int
6815 = build_function_type (void_type_node,
6816 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6817 tree_cons (NULL_TREE, puint_type_node,
6818 tree_cons (NULL_TREE,
6822 tree void_ftype_v2si_puint_char
6823 = build_function_type (void_type_node,
6824 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6825 tree_cons (NULL_TREE, puint_type_node,
6826 tree_cons (NULL_TREE,
6830 tree void_ftype_v2si_pv2si_int
6831 = build_function_type (void_type_node,
6832 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6833 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6834 tree_cons (NULL_TREE,
6838 tree void_ftype_v2si_pv2si_char
6839 = build_function_type (void_type_node,
6840 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6841 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6842 tree_cons (NULL_TREE,
6847 = build_function_type (void_type_node,
6848 tree_cons (NULL_TREE, integer_type_node, endlink));
6851 = build_function_type (integer_type_node, endlink);
6853 tree v2si_ftype_pv2si_int
6854 = build_function_type (opaque_V2SI_type_node,
6855 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6856 tree_cons (NULL_TREE, integer_type_node,
6859 tree v2si_ftype_puint_int
6860 = build_function_type (opaque_V2SI_type_node,
6861 tree_cons (NULL_TREE, puint_type_node,
6862 tree_cons (NULL_TREE, integer_type_node,
6865 tree v2si_ftype_pushort_int
6866 = build_function_type (opaque_V2SI_type_node,
6867 tree_cons (NULL_TREE, pushort_type_node,
6868 tree_cons (NULL_TREE, integer_type_node,
6871 tree v2si_ftype_signed_char
6872 = build_function_type (opaque_V2SI_type_node,
6873 tree_cons (NULL_TREE, signed_char_type_node,
6876 /* The initialization of the simple binary and unary builtins is
6877 done in rs6000_common_init_builtins, but we have to enable the
6878 mask bits here manually because we have run out of `target_flags'
6879 bits. We really need to redesign this mask business. */
6881 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
6882 ARRAY_SIZE (bdesc_2arg),
6885 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
6886 ARRAY_SIZE (bdesc_1arg),
6888 SPE_BUILTIN_EVSUBFUSIAAW);
6889 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
6890 ARRAY_SIZE (bdesc_spe_predicates),
6891 SPE_BUILTIN_EVCMPEQ,
6892 SPE_BUILTIN_EVFSTSTLT);
6893 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
6894 ARRAY_SIZE (bdesc_spe_evsel),
6895 SPE_BUILTIN_EVSEL_CMPGTS,
6896 SPE_BUILTIN_EVSEL_FSTSTEQ);
6898 (*lang_hooks.decls.pushdecl)
6899 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
6900 opaque_V2SI_type_node));
6902 /* Initialize irregular SPE builtins. */
6904 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
6905 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
6906 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
6907 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
6908 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
6909 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
6910 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
6911 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
6912 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
6913 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
6914 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
6915 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
6916 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
6917 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
6918 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
6919 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
6920 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
6921 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
6924 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
6925 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
6926 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
6927 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
6928 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
6929 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
6930 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
6931 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
6932 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
6933 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
6934 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
6935 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
6936 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
6937 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
6938 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
6939 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
6940 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
6941 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
6942 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
6943 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
6944 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
6945 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
6948 d = (struct builtin_description *) bdesc_spe_predicates;
6949 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
6953 switch (insn_data[d->icode].operand[1].mode)
6956 type = int_ftype_int_v2si_v2si;
6959 type = int_ftype_int_v2sf_v2sf;
6965 def_builtin (d->mask, d->name, type, d->code);
6968 /* Evsel predicates. */
6969 d = (struct builtin_description *) bdesc_spe_evsel;
6970 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
6974 switch (insn_data[d->icode].operand[1].mode)
6977 type = v2si_ftype_4_v2si;
6980 type = v2sf_ftype_4_v2sf;
6986 def_builtin (d->mask, d->name, type, d->code);
6991 altivec_init_builtins (void)
6993 struct builtin_description *d;
6994 struct builtin_description_predicates *dp;
6996 tree pfloat_type_node = build_pointer_type (float_type_node);
6997 tree pint_type_node = build_pointer_type (integer_type_node);
6998 tree pshort_type_node = build_pointer_type (short_integer_type_node);
6999 tree pchar_type_node = build_pointer_type (char_type_node);
7001 tree pvoid_type_node = build_pointer_type (void_type_node);
7003 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7004 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7005 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7006 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7008 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7010 tree int_ftype_int_v4si_v4si
7011 = build_function_type_list (integer_type_node,
7012 integer_type_node, V4SI_type_node,
7013 V4SI_type_node, NULL_TREE);
7014 tree v4sf_ftype_pcfloat
7015 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
7016 tree void_ftype_pfloat_v4sf
7017 = build_function_type_list (void_type_node,
7018 pfloat_type_node, V4SF_type_node, NULL_TREE);
7019 tree v4si_ftype_pcint
7020 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7021 tree void_ftype_pint_v4si
7022 = build_function_type_list (void_type_node,
7023 pint_type_node, V4SI_type_node, NULL_TREE);
7024 tree v8hi_ftype_pcshort
7025 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
7026 tree void_ftype_pshort_v8hi
7027 = build_function_type_list (void_type_node,
7028 pshort_type_node, V8HI_type_node, NULL_TREE);
7029 tree v16qi_ftype_pcchar
7030 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
7031 tree void_ftype_pchar_v16qi
7032 = build_function_type_list (void_type_node,
7033 pchar_type_node, V16QI_type_node, NULL_TREE);
7034 tree void_ftype_v4si
7035 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
7036 tree v8hi_ftype_void
7037 = build_function_type (V8HI_type_node, void_list_node);
7038 tree void_ftype_void
7039 = build_function_type (void_type_node, void_list_node);
7041 = build_function_type_list (void_type_node, char_type_node, NULL_TREE);
7043 tree v16qi_ftype_long_pcvoid
7044 = build_function_type_list (V16QI_type_node,
7045 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7046 tree v8hi_ftype_long_pcvoid
7047 = build_function_type_list (V8HI_type_node,
7048 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7049 tree v4si_ftype_long_pcvoid
7050 = build_function_type_list (V4SI_type_node,
7051 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7053 tree void_ftype_v4si_long_pvoid
7054 = build_function_type_list (void_type_node,
7055 V4SI_type_node, long_integer_type_node,
7056 pvoid_type_node, NULL_TREE);
7057 tree void_ftype_v16qi_long_pvoid
7058 = build_function_type_list (void_type_node,
7059 V16QI_type_node, long_integer_type_node,
7060 pvoid_type_node, NULL_TREE);
7061 tree void_ftype_v8hi_long_pvoid
7062 = build_function_type_list (void_type_node,
7063 V8HI_type_node, long_integer_type_node,
7064 pvoid_type_node, NULL_TREE);
7065 tree int_ftype_int_v8hi_v8hi
7066 = build_function_type_list (integer_type_node,
7067 integer_type_node, V8HI_type_node,
7068 V8HI_type_node, NULL_TREE);
7069 tree int_ftype_int_v16qi_v16qi
7070 = build_function_type_list (integer_type_node,
7071 integer_type_node, V16QI_type_node,
7072 V16QI_type_node, NULL_TREE);
7073 tree int_ftype_int_v4sf_v4sf
7074 = build_function_type_list (integer_type_node,
7075 integer_type_node, V4SF_type_node,
7076 V4SF_type_node, NULL_TREE);
7077 tree v4si_ftype_v4si
7078 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7079 tree v8hi_ftype_v8hi
7080 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7081 tree v16qi_ftype_v16qi
7082 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7083 tree v4sf_ftype_v4sf
7084 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7085 tree void_ftype_pcvoid_int_int
7086 = build_function_type_list (void_type_node,
7087 pcvoid_type_node, integer_type_node,
7088 integer_type_node, NULL_TREE);
7089 tree int_ftype_pcchar
7090 = build_function_type_list (integer_type_node,
7091 pcchar_type_node, NULL_TREE);
7093 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7094 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7095 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7096 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7097 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7098 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7099 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7100 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7101 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7102 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7103 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7104 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7105 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7106 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7107 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7108 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
7109 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7110 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7111 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
7112 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS);
7113 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7114 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7115 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7116 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7117 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7118 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7119 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7120 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7121 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7122 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7123 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7124 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
7126 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
7127 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
7128 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
7130 /* Add the DST variants. */
7131 d = (struct builtin_description *) bdesc_dst;
7132 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7133 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
7135 /* Initialize the predicates. */
7136 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7137 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7139 enum machine_mode mode1;
7142 mode1 = insn_data[dp->icode].operand[1].mode;
7147 type = int_ftype_int_v4si_v4si;
7150 type = int_ftype_int_v8hi_v8hi;
7153 type = int_ftype_int_v16qi_v16qi;
7156 type = int_ftype_int_v4sf_v4sf;
7162 def_builtin (dp->mask, dp->name, type, dp->code);
7165 /* Initialize the abs* operators. */
7166 d = (struct builtin_description *) bdesc_abs;
7167 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7169 enum machine_mode mode0;
7172 mode0 = insn_data[d->icode].operand[0].mode;
7177 type = v4si_ftype_v4si;
7180 type = v8hi_ftype_v8hi;
7183 type = v16qi_ftype_v16qi;
7186 type = v4sf_ftype_v4sf;
7192 def_builtin (d->mask, d->name, type, d->code);
7197 rs6000_common_init_builtins (void)
7199 struct builtin_description *d;
7202 tree v4sf_ftype_v4sf_v4sf_v16qi
7203 = build_function_type_list (V4SF_type_node,
7204 V4SF_type_node, V4SF_type_node,
7205 V16QI_type_node, NULL_TREE);
7206 tree v4si_ftype_v4si_v4si_v16qi
7207 = build_function_type_list (V4SI_type_node,
7208 V4SI_type_node, V4SI_type_node,
7209 V16QI_type_node, NULL_TREE);
7210 tree v8hi_ftype_v8hi_v8hi_v16qi
7211 = build_function_type_list (V8HI_type_node,
7212 V8HI_type_node, V8HI_type_node,
7213 V16QI_type_node, NULL_TREE);
7214 tree v16qi_ftype_v16qi_v16qi_v16qi
7215 = build_function_type_list (V16QI_type_node,
7216 V16QI_type_node, V16QI_type_node,
7217 V16QI_type_node, NULL_TREE);
7219 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
7221 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
7222 tree v16qi_ftype_int
7223 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
7224 tree v8hi_ftype_v16qi
7225 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
7226 tree v4sf_ftype_v4sf
7227 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7229 tree v2si_ftype_v2si_v2si
7230 = build_function_type_list (opaque_V2SI_type_node,
7231 opaque_V2SI_type_node,
7232 opaque_V2SI_type_node, NULL_TREE);
7234 tree v2sf_ftype_v2sf_v2sf
7235 = build_function_type_list (opaque_V2SF_type_node,
7236 opaque_V2SF_type_node,
7237 opaque_V2SF_type_node, NULL_TREE);
7239 tree v2si_ftype_int_int
7240 = build_function_type_list (opaque_V2SI_type_node,
7241 integer_type_node, integer_type_node,
7244 tree v2si_ftype_v2si
7245 = build_function_type_list (opaque_V2SI_type_node,
7246 opaque_V2SI_type_node, NULL_TREE);
7248 tree v2sf_ftype_v2sf
7249 = build_function_type_list (opaque_V2SF_type_node,
7250 opaque_V2SF_type_node, NULL_TREE);
7252 tree v2sf_ftype_v2si
7253 = build_function_type_list (opaque_V2SF_type_node,
7254 opaque_V2SI_type_node, NULL_TREE);
7256 tree v2si_ftype_v2sf
7257 = build_function_type_list (opaque_V2SI_type_node,
7258 opaque_V2SF_type_node, NULL_TREE);
7260 tree v2si_ftype_v2si_char
7261 = build_function_type_list (opaque_V2SI_type_node,
7262 opaque_V2SI_type_node,
7263 char_type_node, NULL_TREE);
7265 tree v2si_ftype_int_char
7266 = build_function_type_list (opaque_V2SI_type_node,
7267 integer_type_node, char_type_node, NULL_TREE);
7269 tree v2si_ftype_char
7270 = build_function_type_list (opaque_V2SI_type_node,
7271 char_type_node, NULL_TREE);
7273 tree int_ftype_int_int
7274 = build_function_type_list (integer_type_node,
7275 integer_type_node, integer_type_node,
7278 tree v4si_ftype_v4si_v4si
7279 = build_function_type_list (V4SI_type_node,
7280 V4SI_type_node, V4SI_type_node, NULL_TREE);
7281 tree v4sf_ftype_v4si_int
7282 = build_function_type_list (V4SF_type_node,
7283 V4SI_type_node, integer_type_node, NULL_TREE);
7284 tree v4si_ftype_v4sf_int
7285 = build_function_type_list (V4SI_type_node,
7286 V4SF_type_node, integer_type_node, NULL_TREE);
7287 tree v4si_ftype_v4si_int
7288 = build_function_type_list (V4SI_type_node,
7289 V4SI_type_node, integer_type_node, NULL_TREE);
7290 tree v8hi_ftype_v8hi_int
7291 = build_function_type_list (V8HI_type_node,
7292 V8HI_type_node, integer_type_node, NULL_TREE);
7293 tree v16qi_ftype_v16qi_int
7294 = build_function_type_list (V16QI_type_node,
7295 V16QI_type_node, integer_type_node, NULL_TREE);
7296 tree v16qi_ftype_v16qi_v16qi_int
7297 = build_function_type_list (V16QI_type_node,
7298 V16QI_type_node, V16QI_type_node,
7299 integer_type_node, NULL_TREE);
7300 tree v8hi_ftype_v8hi_v8hi_int
7301 = build_function_type_list (V8HI_type_node,
7302 V8HI_type_node, V8HI_type_node,
7303 integer_type_node, NULL_TREE);
7304 tree v4si_ftype_v4si_v4si_int
7305 = build_function_type_list (V4SI_type_node,
7306 V4SI_type_node, V4SI_type_node,
7307 integer_type_node, NULL_TREE);
7308 tree v4sf_ftype_v4sf_v4sf_int
7309 = build_function_type_list (V4SF_type_node,
7310 V4SF_type_node, V4SF_type_node,
7311 integer_type_node, NULL_TREE);
7312 tree v4sf_ftype_v4sf_v4sf
7313 = build_function_type_list (V4SF_type_node,
7314 V4SF_type_node, V4SF_type_node, NULL_TREE);
7315 tree v4sf_ftype_v4sf_v4sf_v4si
7316 = build_function_type_list (V4SF_type_node,
7317 V4SF_type_node, V4SF_type_node,
7318 V4SI_type_node, NULL_TREE);
7319 tree v4sf_ftype_v4sf_v4sf_v4sf
7320 = build_function_type_list (V4SF_type_node,
7321 V4SF_type_node, V4SF_type_node,
7322 V4SF_type_node, NULL_TREE);
7323 tree v4si_ftype_v4si_v4si_v4si
7324 = build_function_type_list (V4SI_type_node,
7325 V4SI_type_node, V4SI_type_node,
7326 V4SI_type_node, NULL_TREE);
7327 tree v8hi_ftype_v8hi_v8hi
7328 = build_function_type_list (V8HI_type_node,
7329 V8HI_type_node, V8HI_type_node, NULL_TREE);
7330 tree v8hi_ftype_v8hi_v8hi_v8hi
7331 = build_function_type_list (V8HI_type_node,
7332 V8HI_type_node, V8HI_type_node,
7333 V8HI_type_node, NULL_TREE);
7334 tree v4si_ftype_v8hi_v8hi_v4si
7335 = build_function_type_list (V4SI_type_node,
7336 V8HI_type_node, V8HI_type_node,
7337 V4SI_type_node, NULL_TREE);
7338 tree v4si_ftype_v16qi_v16qi_v4si
7339 = build_function_type_list (V4SI_type_node,
7340 V16QI_type_node, V16QI_type_node,
7341 V4SI_type_node, NULL_TREE);
7342 tree v16qi_ftype_v16qi_v16qi
7343 = build_function_type_list (V16QI_type_node,
7344 V16QI_type_node, V16QI_type_node, NULL_TREE);
7345 tree v4si_ftype_v4sf_v4sf
7346 = build_function_type_list (V4SI_type_node,
7347 V4SF_type_node, V4SF_type_node, NULL_TREE);
7348 tree v8hi_ftype_v16qi_v16qi
7349 = build_function_type_list (V8HI_type_node,
7350 V16QI_type_node, V16QI_type_node, NULL_TREE);
7351 tree v4si_ftype_v8hi_v8hi
7352 = build_function_type_list (V4SI_type_node,
7353 V8HI_type_node, V8HI_type_node, NULL_TREE);
7354 tree v8hi_ftype_v4si_v4si
7355 = build_function_type_list (V8HI_type_node,
7356 V4SI_type_node, V4SI_type_node, NULL_TREE);
7357 tree v16qi_ftype_v8hi_v8hi
7358 = build_function_type_list (V16QI_type_node,
7359 V8HI_type_node, V8HI_type_node, NULL_TREE);
7360 tree v4si_ftype_v16qi_v4si
7361 = build_function_type_list (V4SI_type_node,
7362 V16QI_type_node, V4SI_type_node, NULL_TREE);
7363 tree v4si_ftype_v16qi_v16qi
7364 = build_function_type_list (V4SI_type_node,
7365 V16QI_type_node, V16QI_type_node, NULL_TREE);
7366 tree v4si_ftype_v8hi_v4si
7367 = build_function_type_list (V4SI_type_node,
7368 V8HI_type_node, V4SI_type_node, NULL_TREE);
7369 tree v4si_ftype_v8hi
7370 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
7371 tree int_ftype_v4si_v4si
7372 = build_function_type_list (integer_type_node,
7373 V4SI_type_node, V4SI_type_node, NULL_TREE);
7374 tree int_ftype_v4sf_v4sf
7375 = build_function_type_list (integer_type_node,
7376 V4SF_type_node, V4SF_type_node, NULL_TREE);
7377 tree int_ftype_v16qi_v16qi
7378 = build_function_type_list (integer_type_node,
7379 V16QI_type_node, V16QI_type_node, NULL_TREE);
7380 tree int_ftype_v8hi_v8hi
7381 = build_function_type_list (integer_type_node,
7382 V8HI_type_node, V8HI_type_node, NULL_TREE);
7384 /* Add the simple ternary operators. */
7385 d = (struct builtin_description *) bdesc_3arg;
7386 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7389 enum machine_mode mode0, mode1, mode2, mode3;
7392 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7395 mode0 = insn_data[d->icode].operand[0].mode;
7396 mode1 = insn_data[d->icode].operand[1].mode;
7397 mode2 = insn_data[d->icode].operand[2].mode;
7398 mode3 = insn_data[d->icode].operand[3].mode;
7400 /* When all four are of the same mode. */
7401 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7406 type = v4si_ftype_v4si_v4si_v4si;
7409 type = v4sf_ftype_v4sf_v4sf_v4sf;
7412 type = v8hi_ftype_v8hi_v8hi_v8hi;
7415 type = v16qi_ftype_v16qi_v16qi_v16qi;
7421 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
7426 type = v4si_ftype_v4si_v4si_v16qi;
7429 type = v4sf_ftype_v4sf_v4sf_v16qi;
7432 type = v8hi_ftype_v8hi_v8hi_v16qi;
7435 type = v16qi_ftype_v16qi_v16qi_v16qi;
7441 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
7442 && mode3 == V4SImode)
7443 type = v4si_ftype_v16qi_v16qi_v4si;
7444 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
7445 && mode3 == V4SImode)
7446 type = v4si_ftype_v8hi_v8hi_v4si;
7447 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
7448 && mode3 == V4SImode)
7449 type = v4sf_ftype_v4sf_v4sf_v4si;
7451 /* vchar, vchar, vchar, 4 bit literal. */
7452 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7454 type = v16qi_ftype_v16qi_v16qi_int;
7456 /* vshort, vshort, vshort, 4 bit literal. */
7457 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7459 type = v8hi_ftype_v8hi_v8hi_int;
7461 /* vint, vint, vint, 4 bit literal. */
7462 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7464 type = v4si_ftype_v4si_v4si_int;
7466 /* vfloat, vfloat, vfloat, 4 bit literal. */
7467 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7469 type = v4sf_ftype_v4sf_v4sf_int;
7474 def_builtin (d->mask, d->name, type, d->code);
7477 /* Add the simple binary operators. */
7478 d = (struct builtin_description *) bdesc_2arg;
7479 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7481 enum machine_mode mode0, mode1, mode2;
7484 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7487 mode0 = insn_data[d->icode].operand[0].mode;
7488 mode1 = insn_data[d->icode].operand[1].mode;
7489 mode2 = insn_data[d->icode].operand[2].mode;
7491 /* When all three operands are of the same mode. */
7492 if (mode0 == mode1 && mode1 == mode2)
7497 type = v4sf_ftype_v4sf_v4sf;
7500 type = v4si_ftype_v4si_v4si;
7503 type = v16qi_ftype_v16qi_v16qi;
7506 type = v8hi_ftype_v8hi_v8hi;
7509 type = v2si_ftype_v2si_v2si;
7512 type = v2sf_ftype_v2sf_v2sf;
7515 type = int_ftype_int_int;
7522 /* A few other combos we really don't want to do manually. */
7524 /* vint, vfloat, vfloat. */
7525 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
7526 type = v4si_ftype_v4sf_v4sf;
7528 /* vshort, vchar, vchar. */
7529 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
7530 type = v8hi_ftype_v16qi_v16qi;
7532 /* vint, vshort, vshort. */
7533 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
7534 type = v4si_ftype_v8hi_v8hi;
7536 /* vshort, vint, vint. */
7537 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
7538 type = v8hi_ftype_v4si_v4si;
7540 /* vchar, vshort, vshort. */
7541 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
7542 type = v16qi_ftype_v8hi_v8hi;
7544 /* vint, vchar, vint. */
7545 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
7546 type = v4si_ftype_v16qi_v4si;
7548 /* vint, vchar, vchar. */
7549 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
7550 type = v4si_ftype_v16qi_v16qi;
7552 /* vint, vshort, vint. */
7553 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
7554 type = v4si_ftype_v8hi_v4si;
7556 /* vint, vint, 5 bit literal. */
7557 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
7558 type = v4si_ftype_v4si_int;
7560 /* vshort, vshort, 5 bit literal. */
7561 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
7562 type = v8hi_ftype_v8hi_int;
7564 /* vchar, vchar, 5 bit literal. */
7565 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
7566 type = v16qi_ftype_v16qi_int;
7568 /* vfloat, vint, 5 bit literal. */
7569 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
7570 type = v4sf_ftype_v4si_int;
7572 /* vint, vfloat, 5 bit literal. */
7573 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
7574 type = v4si_ftype_v4sf_int;
7576 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
7577 type = v2si_ftype_int_int;
7579 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
7580 type = v2si_ftype_v2si_char;
7582 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
7583 type = v2si_ftype_int_char;
7586 else if (mode0 == SImode)
7591 type = int_ftype_v4si_v4si;
7594 type = int_ftype_v4sf_v4sf;
7597 type = int_ftype_v16qi_v16qi;
7600 type = int_ftype_v8hi_v8hi;
7610 def_builtin (d->mask, d->name, type, d->code);
7613 /* Add the simple unary operators. */
7614 d = (struct builtin_description *) bdesc_1arg;
7615 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7617 enum machine_mode mode0, mode1;
7620 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7623 mode0 = insn_data[d->icode].operand[0].mode;
7624 mode1 = insn_data[d->icode].operand[1].mode;
7626 if (mode0 == V4SImode && mode1 == QImode)
7627 type = v4si_ftype_int;
7628 else if (mode0 == V8HImode && mode1 == QImode)
7629 type = v8hi_ftype_int;
7630 else if (mode0 == V16QImode && mode1 == QImode)
7631 type = v16qi_ftype_int;
7632 else if (mode0 == V4SFmode && mode1 == V4SFmode)
7633 type = v4sf_ftype_v4sf;
7634 else if (mode0 == V8HImode && mode1 == V16QImode)
7635 type = v8hi_ftype_v16qi;
7636 else if (mode0 == V4SImode && mode1 == V8HImode)
7637 type = v4si_ftype_v8hi;
7638 else if (mode0 == V2SImode && mode1 == V2SImode)
7639 type = v2si_ftype_v2si;
7640 else if (mode0 == V2SFmode && mode1 == V2SFmode)
7641 type = v2sf_ftype_v2sf;
7642 else if (mode0 == V2SFmode && mode1 == V2SImode)
7643 type = v2sf_ftype_v2si;
7644 else if (mode0 == V2SImode && mode1 == V2SFmode)
7645 type = v2si_ftype_v2sf;
7646 else if (mode0 == V2SImode && mode1 == QImode)
7647 type = v2si_ftype_char;
7651 def_builtin (d->mask, d->name, type, d->code);
7656 rs6000_init_libfuncs (void)
7658 if (!TARGET_HARD_FLOAT)
7661 if (DEFAULT_ABI != ABI_V4)
7663 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
7665 /* AIX library routines for float->int conversion. */
7666 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
7667 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
7668 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
7669 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
7672 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
7673 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
7674 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
7675 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
7676 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
7680 /* 32-bit SVR4 quad floating point routines. */
7682 set_optab_libfunc (add_optab, TFmode, "_q_add");
7683 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
7684 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
7685 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
7686 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
7687 if (TARGET_PPC_GPOPT || TARGET_POWER2)
7688 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
7690 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
7691 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
7692 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
7693 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
7694 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
7695 set_optab_libfunc (le_optab, TFmode, "_q_fle");
7697 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
7698 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
7699 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
7700 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
7701 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
7702 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
7703 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
7707 /* Expand a block move operation, and return 1 if successful. Return 0
7708 if we should let the compiler generate normal code.
7710 operands[0] is the destination
7711 operands[1] is the source
7712 operands[2] is the length
7713 operands[3] is the alignment */
7715 #define MAX_MOVE_REG 4
7718 expand_block_move (rtx operands[])
7720 rtx orig_dest = operands[0];
7721 rtx orig_src = operands[1];
7722 rtx bytes_rtx = operands[2];
7723 rtx align_rtx = operands[3];
7724 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
7729 rtx stores[MAX_MOVE_REG];
7732 /* If this is not a fixed size move, just call memcpy */
7736 /* If this is not a fixed size alignment, abort */
7737 if (GET_CODE (align_rtx) != CONST_INT)
7739 align = INTVAL (align_rtx);
7741 /* Anything to move? */
7742 bytes = INTVAL (bytes_rtx);
7746 /* store_one_arg depends on expand_block_move to handle at least the size of
7747 reg_parm_stack_space. */
7748 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7751 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7754 rtx (*movstrsi) (rtx, rtx, rtx, rtx);
7755 rtx (*mov) (rtx, rtx);
7757 enum machine_mode mode = BLKmode;
7761 && bytes > 24 /* move up to 32 bytes at a time */
7769 && ! fixed_regs[12])
7771 move_bytes = (bytes > 32) ? 32 : bytes;
7772 gen_func.movstrsi = gen_movstrsi_8reg;
7774 else if (TARGET_STRING
7775 && bytes > 16 /* move up to 24 bytes at a time */
7781 && ! fixed_regs[10])
7783 move_bytes = (bytes > 24) ? 24 : bytes;
7784 gen_func.movstrsi = gen_movstrsi_6reg;
7786 else if (TARGET_STRING
7787 && bytes > 8 /* move up to 16 bytes at a time */
7793 move_bytes = (bytes > 16) ? 16 : bytes;
7794 gen_func.movstrsi = gen_movstrsi_4reg;
7796 else if (bytes >= 8 && TARGET_POWERPC64
7797 /* 64-bit loads and stores require word-aligned
7799 && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
7803 gen_func.mov = gen_movdi;
7805 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
7806 { /* move up to 8 bytes at a time */
7807 move_bytes = (bytes > 8) ? 8 : bytes;
7808 gen_func.movstrsi = gen_movstrsi_2reg;
7810 else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
7811 { /* move 4 bytes */
7814 gen_func.mov = gen_movsi;
7816 else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT))
7817 { /* move 2 bytes */
7820 gen_func.mov = gen_movhi;
7822 else if (TARGET_STRING && bytes > 1)
7823 { /* move up to 4 bytes at a time */
7824 move_bytes = (bytes > 4) ? 4 : bytes;
7825 gen_func.movstrsi = gen_movstrsi_1reg;
7827 else /* move 1 byte at a time */
7831 gen_func.mov = gen_movqi;
7834 src = adjust_address (orig_src, mode, offset);
7835 dest = adjust_address (orig_dest, mode, offset);
7837 if (mode != BLKmode)
7839 rtx tmp_reg = gen_reg_rtx (mode);
7841 emit_insn ((*gen_func.mov) (tmp_reg, src));
7842 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
7845 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
7848 for (i = 0; i < num_reg; i++)
7849 emit_insn (stores[i]);
7853 if (mode == BLKmode)
7855 /* Move the address into scratch registers. The movstrsi
7856 patterns require zero offset. */
7857 if (!REG_P (XEXP (src, 0)))
7859 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
7860 src = replace_equiv_address (src, src_reg);
7862 set_mem_size (src, GEN_INT (move_bytes));
7864 if (!REG_P (XEXP (dest, 0)))
7866 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
7867 dest = replace_equiv_address (dest, dest_reg);
7869 set_mem_size (dest, GEN_INT (move_bytes));
7871 emit_insn ((*gen_func.movstrsi) (dest, src,
7872 GEN_INT (move_bytes & 31),
7881 /* Return 1 if OP is a load multiple operation. It is known to be a
7882 PARALLEL and the first section will be tested. */
7885 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7887 int count = XVECLEN (op, 0);
7888 unsigned int dest_regno;
7892 /* Perform a quick check so we don't blow up below. */
7894 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7895 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7896 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
7899 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7900 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
7902 for (i = 1; i < count; i++)
7904 rtx elt = XVECEXP (op, 0, i);
7906 if (GET_CODE (elt) != SET
7907 || GET_CODE (SET_DEST (elt)) != REG
7908 || GET_MODE (SET_DEST (elt)) != SImode
7909 || REGNO (SET_DEST (elt)) != dest_regno + i
7910 || GET_CODE (SET_SRC (elt)) != MEM
7911 || GET_MODE (SET_SRC (elt)) != SImode
7912 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
7913 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
7914 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
7915 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
7922 /* Similar, but tests for store multiple. Here, the second vector element
7923 is a CLOBBER. It will be tested later. */
7926 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7928 int count = XVECLEN (op, 0) - 1;
7929 unsigned int src_regno;
7933 /* Perform a quick check so we don't blow up below. */
7935 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7936 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
7937 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
7940 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7941 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
7943 for (i = 1; i < count; i++)
7945 rtx elt = XVECEXP (op, 0, i + 1);
7947 if (GET_CODE (elt) != SET
7948 || GET_CODE (SET_SRC (elt)) != REG
7949 || GET_MODE (SET_SRC (elt)) != SImode
7950 || REGNO (SET_SRC (elt)) != src_regno + i
7951 || GET_CODE (SET_DEST (elt)) != MEM
7952 || GET_MODE (SET_DEST (elt)) != SImode
7953 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
7954 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
7955 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
7956 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
7963 /* Return a string to perform a load_multiple operation.
7964 operands[0] is the vector.
7965 operands[1] is the source address.
7966 operands[2] is the first destination register. */
7969 rs6000_output_load_multiple (rtx operands[3])
7971 /* We have to handle the case where the pseudo used to contain the address
7972 is assigned to one of the output registers. */
7974 int words = XVECLEN (operands[0], 0);
7977 if (XVECLEN (operands[0], 0) == 1)
7978 return "{l|lwz} %2,0(%1)";
7980 for (i = 0; i < words; i++)
7981 if (refers_to_regno_p (REGNO (operands[2]) + i,
7982 REGNO (operands[2]) + i + 1, operands[1], 0))
7986 xop[0] = GEN_INT (4 * (words-1));
7987 xop[1] = operands[1];
7988 xop[2] = operands[2];
7989 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
7994 xop[0] = GEN_INT (4 * (words-1));
7995 xop[1] = operands[1];
7996 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7997 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8002 for (j = 0; j < words; j++)
8005 xop[0] = GEN_INT (j * 4);
8006 xop[1] = operands[1];
8007 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8008 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8010 xop[0] = GEN_INT (i * 4);
8011 xop[1] = operands[1];
8012 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8017 return "{lsi|lswi} %2,%1,%N0";
8020 /* Return 1 for a parallel vrsave operation. */
8023 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8025 int count = XVECLEN (op, 0);
8026 unsigned int dest_regno, src_regno;
8030 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8031 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
8032 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
8035 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
8036 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
8038 if (dest_regno != VRSAVE_REGNO
8039 && src_regno != VRSAVE_REGNO)
8042 for (i = 1; i < count; i++)
8044 rtx elt = XVECEXP (op, 0, i);
8046 if (GET_CODE (elt) != CLOBBER
8047 && GET_CODE (elt) != SET)
8054 /* Return 1 for an PARALLEL suitable for mfcr. */
8057 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8059 int count = XVECLEN (op, 0);
8062 /* Perform a quick check so we don't blow up below. */
8064 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8065 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
8066 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
8069 for (i = 0; i < count; i++)
8071 rtx exp = XVECEXP (op, 0, i);
8076 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
8078 if (GET_CODE (src_reg) != REG
8079 || GET_MODE (src_reg) != CCmode
8080 || ! CR_REGNO_P (REGNO (src_reg)))
8083 if (GET_CODE (exp) != SET
8084 || GET_CODE (SET_DEST (exp)) != REG
8085 || GET_MODE (SET_DEST (exp)) != SImode
8086 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
8088 unspec = SET_SRC (exp);
8089 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
8091 if (GET_CODE (unspec) != UNSPEC
8092 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
8093 || XVECLEN (unspec, 0) != 2
8094 || XVECEXP (unspec, 0, 0) != src_reg
8095 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
8096 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
8102 /* Return 1 for an PARALLEL suitable for mtcrf. */
8105 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8107 int count = XVECLEN (op, 0);
8111 /* Perform a quick check so we don't blow up below. */
8113 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8114 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
8115 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
8117 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
8119 if (GET_CODE (src_reg) != REG
8120 || GET_MODE (src_reg) != SImode
8121 || ! INT_REGNO_P (REGNO (src_reg)))
8124 for (i = 0; i < count; i++)
8126 rtx exp = XVECEXP (op, 0, i);
8130 if (GET_CODE (exp) != SET
8131 || GET_CODE (SET_DEST (exp)) != REG
8132 || GET_MODE (SET_DEST (exp)) != CCmode
8133 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
8135 unspec = SET_SRC (exp);
8136 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
8138 if (GET_CODE (unspec) != UNSPEC
8139 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
8140 || XVECLEN (unspec, 0) != 2
8141 || XVECEXP (unspec, 0, 0) != src_reg
8142 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
8143 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
8149 /* Return 1 for an PARALLEL suitable for lmw. */
8152 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8154 int count = XVECLEN (op, 0);
8155 unsigned int dest_regno;
8157 unsigned int base_regno;
8158 HOST_WIDE_INT offset;
8161 /* Perform a quick check so we don't blow up below. */
8163 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8164 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
8165 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
8168 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
8169 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
8172 || count != 32 - (int) dest_regno)
8175 if (legitimate_indirect_address_p (src_addr, 0))
8178 base_regno = REGNO (src_addr);
8179 if (base_regno == 0)
8182 else if (legitimate_offset_address_p (SImode, src_addr, 0))
8184 offset = INTVAL (XEXP (src_addr, 1));
8185 base_regno = REGNO (XEXP (src_addr, 0));
8190 for (i = 0; i < count; i++)
8192 rtx elt = XVECEXP (op, 0, i);
8195 HOST_WIDE_INT newoffset;
8197 if (GET_CODE (elt) != SET
8198 || GET_CODE (SET_DEST (elt)) != REG
8199 || GET_MODE (SET_DEST (elt)) != SImode
8200 || REGNO (SET_DEST (elt)) != dest_regno + i
8201 || GET_CODE (SET_SRC (elt)) != MEM
8202 || GET_MODE (SET_SRC (elt)) != SImode)
8204 newaddr = XEXP (SET_SRC (elt), 0);
8205 if (legitimate_indirect_address_p (newaddr, 0))
8210 else if (legitimate_offset_address_p (SImode, newaddr, 0))
8212 addr_reg = XEXP (newaddr, 0);
8213 newoffset = INTVAL (XEXP (newaddr, 1));
8217 if (REGNO (addr_reg) != base_regno
8218 || newoffset != offset + 4 * i)
8225 /* Return 1 for an PARALLEL suitable for stmw. */
8228 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8230 int count = XVECLEN (op, 0);
8231 unsigned int src_regno;
8233 unsigned int base_regno;
8234 HOST_WIDE_INT offset;
8237 /* Perform a quick check so we don't blow up below. */
8239 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8240 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
8241 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
8244 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
8245 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
8248 || count != 32 - (int) src_regno)
8251 if (legitimate_indirect_address_p (dest_addr, 0))
8254 base_regno = REGNO (dest_addr);
8255 if (base_regno == 0)
8258 else if (legitimate_offset_address_p (SImode, dest_addr, 0))
8260 offset = INTVAL (XEXP (dest_addr, 1));
8261 base_regno = REGNO (XEXP (dest_addr, 0));
8266 for (i = 0; i < count; i++)
8268 rtx elt = XVECEXP (op, 0, i);
8271 HOST_WIDE_INT newoffset;
8273 if (GET_CODE (elt) != SET
8274 || GET_CODE (SET_SRC (elt)) != REG
8275 || GET_MODE (SET_SRC (elt)) != SImode
8276 || REGNO (SET_SRC (elt)) != src_regno + i
8277 || GET_CODE (SET_DEST (elt)) != MEM
8278 || GET_MODE (SET_DEST (elt)) != SImode)
8280 newaddr = XEXP (SET_DEST (elt), 0);
8281 if (legitimate_indirect_address_p (newaddr, 0))
8286 else if (legitimate_offset_address_p (SImode, newaddr, 0))
8288 addr_reg = XEXP (newaddr, 0);
8289 newoffset = INTVAL (XEXP (newaddr, 1));
8293 if (REGNO (addr_reg) != base_regno
8294 || newoffset != offset + 4 * i)
8301 /* A validation routine: say whether CODE, a condition code, and MODE
8302 match. The other alternatives either don't make sense or should
8303 never be generated. */
8306 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
8308 if ((GET_RTX_CLASS (code) != RTX_COMPARE
8309 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
8310 || GET_MODE_CLASS (mode) != MODE_CC)
8313 /* These don't make sense. */
8314 if ((code == GT || code == LT || code == GE || code == LE)
8315 && mode == CCUNSmode)
8318 if ((code == GTU || code == LTU || code == GEU || code == LEU)
8319 && mode != CCUNSmode)
8322 if (mode != CCFPmode
8323 && (code == ORDERED || code == UNORDERED
8324 || code == UNEQ || code == LTGT
8325 || code == UNGT || code == UNLT
8326 || code == UNGE || code == UNLE))
8329 /* These should never be generated except for
8330 flag_finite_math_only. */
8331 if (mode == CCFPmode
8332 && ! flag_finite_math_only
8333 && (code == LE || code == GE
8334 || code == UNEQ || code == LTGT
8335 || code == UNGT || code == UNLT))
8338 /* These are invalid; the information is not there. */
8339 if (mode == CCEQmode
8340 && code != EQ && code != NE)
8344 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
8345 We only check the opcode against the mode of the CC value here. */
8348 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8350 enum rtx_code code = GET_CODE (op);
8351 enum machine_mode cc_mode;
8353 if (!COMPARISON_P (op))
8356 cc_mode = GET_MODE (XEXP (op, 0));
8357 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
8360 validate_condition_mode (code, cc_mode);
8365 /* Return 1 if OP is a comparison operation that is valid for a branch
8366 insn and which is true if the corresponding bit in the CC register
8370 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
8374 if (! branch_comparison_operator (op, mode))
8377 code = GET_CODE (op);
8378 return (code == EQ || code == LT || code == GT
8379 || (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE)
8380 || code == LTU || code == GTU
8381 || code == UNORDERED);
8384 /* Return 1 if OP is a comparison operation that is valid for an scc
8385 insn: it must be a positive comparison. */
8388 scc_comparison_operator (rtx op, enum machine_mode mode)
8390 return branch_positive_comparison_operator (op, mode);
8394 trap_comparison_operator (rtx op, enum machine_mode mode)
8396 if (mode != VOIDmode && mode != GET_MODE (op))
8398 return COMPARISON_P (op);
8402 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8404 enum rtx_code code = GET_CODE (op);
8405 return (code == AND || code == IOR || code == XOR);
8409 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8411 enum rtx_code code = GET_CODE (op);
8412 return (code == IOR || code == XOR);
8416 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8418 enum rtx_code code = GET_CODE (op);
8419 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
8422 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8423 mask required to convert the result of a rotate insn into a shift
8424 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
8427 includes_lshift_p (rtx shiftop, rtx andop)
8429 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8431 shift_mask <<= INTVAL (shiftop);
8433 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8436 /* Similar, but for right shift. */
8439 includes_rshift_p (rtx shiftop, rtx andop)
8441 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8443 shift_mask >>= INTVAL (shiftop);
8445 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8448 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8449 to perform a left shift. It must have exactly SHIFTOP least
8450 significant 0's, then one or more 1's, then zero or more 0's. */
8453 includes_rldic_lshift_p (rtx shiftop, rtx andop)
8455 if (GET_CODE (andop) == CONST_INT)
8457 HOST_WIDE_INT c, lsb, shift_mask;
8460 if (c == 0 || c == ~0)
8464 shift_mask <<= INTVAL (shiftop);
8466 /* Find the least significant one bit. */
8469 /* It must coincide with the LSB of the shift mask. */
8470 if (-lsb != shift_mask)
8473 /* Invert to look for the next transition (if any). */
8476 /* Remove the low group of ones (originally low group of zeros). */
8479 /* Again find the lsb, and check we have all 1's above. */
8483 else if (GET_CODE (andop) == CONST_DOUBLE
8484 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8486 HOST_WIDE_INT low, high, lsb;
8487 HOST_WIDE_INT shift_mask_low, shift_mask_high;
8489 low = CONST_DOUBLE_LOW (andop);
8490 if (HOST_BITS_PER_WIDE_INT < 64)
8491 high = CONST_DOUBLE_HIGH (andop);
8493 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
8494 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
8497 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8499 shift_mask_high = ~0;
8500 if (INTVAL (shiftop) > 32)
8501 shift_mask_high <<= INTVAL (shiftop) - 32;
8505 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8512 return high == -lsb;
8515 shift_mask_low = ~0;
8516 shift_mask_low <<= INTVAL (shiftop);
8520 if (-lsb != shift_mask_low)
8523 if (HOST_BITS_PER_WIDE_INT < 64)
8528 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8531 return high == -lsb;
8535 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8541 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8542 to perform a left shift. It must have SHIFTOP or more least
8543 significant 0's, with the remainder of the word 1's. */
8546 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
8548 if (GET_CODE (andop) == CONST_INT)
8550 HOST_WIDE_INT c, lsb, shift_mask;
8553 shift_mask <<= INTVAL (shiftop);
8556 /* Find the least significant one bit. */
8559 /* It must be covered by the shift mask.
8560 This test also rejects c == 0. */
8561 if ((lsb & shift_mask) == 0)
8564 /* Check we have all 1's above the transition, and reject all 1's. */
8565 return c == -lsb && lsb != 1;
8567 else if (GET_CODE (andop) == CONST_DOUBLE
8568 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8570 HOST_WIDE_INT low, lsb, shift_mask_low;
8572 low = CONST_DOUBLE_LOW (andop);
8574 if (HOST_BITS_PER_WIDE_INT < 64)
8576 HOST_WIDE_INT high, shift_mask_high;
8578 high = CONST_DOUBLE_HIGH (andop);
8582 shift_mask_high = ~0;
8583 if (INTVAL (shiftop) > 32)
8584 shift_mask_high <<= INTVAL (shiftop) - 32;
8588 if ((lsb & shift_mask_high) == 0)
8591 return high == -lsb;
8597 shift_mask_low = ~0;
8598 shift_mask_low <<= INTVAL (shiftop);
8602 if ((lsb & shift_mask_low) == 0)
8605 return low == -lsb && lsb != 1;
8611 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
8612 for lfq and stfq insns.
8614 Note reg1 and reg2 *must* be hard registers. To be sure we will
8615 abort if we are passed pseudo registers. */
8618 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
8620 /* We might have been passed a SUBREG. */
8621 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8624 return (REGNO (reg1) == REGNO (reg2) - 1);
8627 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8628 addr1 and addr2 must be in consecutive memory locations
8629 (addr2 == addr1 + 8). */
8632 addrs_ok_for_quad_peep (rtx addr1, rtx addr2)
8637 /* Extract an offset (if used) from the first addr. */
8638 if (GET_CODE (addr1) == PLUS)
8640 /* If not a REG, return zero. */
8641 if (GET_CODE (XEXP (addr1, 0)) != REG)
8645 reg1 = REGNO (XEXP (addr1, 0));
8646 /* The offset must be constant! */
8647 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8649 offset1 = INTVAL (XEXP (addr1, 1));
8652 else if (GET_CODE (addr1) != REG)
8656 reg1 = REGNO (addr1);
8657 /* This was a simple (mem (reg)) expression. Offset is 0. */
8661 /* Make sure the second address is a (mem (plus (reg) (const_int)))
8662 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
8663 register as addr1. */
8664 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
8666 if (GET_CODE (addr2) != PLUS)
8669 if (GET_CODE (XEXP (addr2, 0)) != REG
8670 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8673 if (reg1 != REGNO (XEXP (addr2, 0)))
8676 /* The offset for the second addr must be 8 more than the first addr. */
8677 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8680 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
8685 /* Return the register class of a scratch register needed to copy IN into
8686 or out of a register in CLASS in MODE. If it can be done directly,
8687 NO_REGS is returned. */
8690 secondary_reload_class (enum reg_class class,
8691 enum machine_mode mode ATTRIBUTE_UNUSED,
8696 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8698 && MACHOPIC_INDIRECT
8702 /* We cannot copy a symbolic operand directly into anything
8703 other than BASE_REGS for TARGET_ELF. So indicate that a
8704 register from BASE_REGS is needed as an intermediate
8707 On Darwin, pic addresses require a load from memory, which
8708 needs a base register. */
8709 if (class != BASE_REGS
8710 && (GET_CODE (in) == SYMBOL_REF
8711 || GET_CODE (in) == HIGH
8712 || GET_CODE (in) == LABEL_REF
8713 || GET_CODE (in) == CONST))
8717 if (GET_CODE (in) == REG)
8720 if (regno >= FIRST_PSEUDO_REGISTER)
8722 regno = true_regnum (in);
8723 if (regno >= FIRST_PSEUDO_REGISTER)
8727 else if (GET_CODE (in) == SUBREG)
8729 regno = true_regnum (in);
8730 if (regno >= FIRST_PSEUDO_REGISTER)
8736 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8738 if (class == GENERAL_REGS || class == BASE_REGS
8739 || (regno >= 0 && INT_REGNO_P (regno)))
8742 /* Constants, memory, and FP registers can go into FP registers. */
8743 if ((regno == -1 || FP_REGNO_P (regno))
8744 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8747 /* Memory, and AltiVec registers can go into AltiVec registers. */
8748 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8749 && class == ALTIVEC_REGS)
8752 /* We can copy among the CR registers. */
8753 if ((class == CR_REGS || class == CR0_REGS)
8754 && regno >= 0 && CR_REGNO_P (regno))
8757 /* Otherwise, we need GENERAL_REGS. */
8758 return GENERAL_REGS;
8761 /* Given a comparison operation, return the bit number in CCR to test. We
8762 know this is a valid comparison.
8764 SCC_P is 1 if this is for an scc. That means that %D will have been
8765 used instead of %C, so the bits will be in different places.
8767 Return -1 if OP isn't a valid comparison for some reason. */
8770 ccr_bit (rtx op, int scc_p)
8772 enum rtx_code code = GET_CODE (op);
8773 enum machine_mode cc_mode;
8778 if (!COMPARISON_P (op))
8783 if (GET_CODE (reg) != REG
8784 || ! CR_REGNO_P (REGNO (reg)))
8787 cc_mode = GET_MODE (reg);
8788 cc_regnum = REGNO (reg);
8789 base_bit = 4 * (cc_regnum - CR0_REGNO);
8791 validate_condition_mode (code, cc_mode);
8793 /* When generating a sCOND operation, only positive conditions are
8795 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8796 && code != GTU && code != LTU)
8802 if (TARGET_E500 && !TARGET_FPRS
8803 && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
8804 return base_bit + 1;
8805 return scc_p ? base_bit + 3 : base_bit + 2;
8807 if (TARGET_E500 && !TARGET_FPRS
8808 && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
8809 return base_bit + 1;
8810 return base_bit + 2;
8811 case GT: case GTU: case UNLE:
8812 return base_bit + 1;
8813 case LT: case LTU: case UNGE:
8815 case ORDERED: case UNORDERED:
8816 return base_bit + 3;
8819 /* If scc, we will have done a cror to put the bit in the
8820 unordered position. So test that bit. For integer, this is ! LT
8821 unless this is an scc insn. */
8822 return scc_p ? base_bit + 3 : base_bit;
8825 return scc_p ? base_bit + 3 : base_bit + 1;
8832 /* Return the GOT register. */
8835 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
8837 /* The second flow pass currently (June 1999) can't update
8838 regs_ever_live without disturbing other parts of the compiler, so
8839 update it here to make the prolog/epilogue code happy. */
8840 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
8841 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
8843 current_function_uses_pic_offset_table = 1;
8845 return pic_offset_table_rtx;
8848 /* Function to init struct machine_function.
8849 This will be called, via a pointer variable,
8850 from push_function_context. */
8852 static struct machine_function *
8853 rs6000_init_machine_status (void)
8855 return ggc_alloc_cleared (sizeof (machine_function));
8858 /* These macros test for integers and extract the low-order bits. */
8860 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
8861 && GET_MODE (X) == VOIDmode)
8863 #define INT_LOWPART(X) \
8864 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
8870 unsigned long val = INT_LOWPART (op);
8872 /* If the high bit is zero, the value is the first 1 bit we find
8874 if ((val & 0x80000000) == 0)
8876 if ((val & 0xffffffff) == 0)
8880 while (((val <<= 1) & 0x80000000) == 0)
8885 /* If the high bit is set and the low bit is not, or the mask is all
8886 1's, the value is zero. */
8887 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
8890 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
8893 while (((val >>= 1) & 1) != 0)
8903 unsigned long val = INT_LOWPART (op);
8905 /* If the low bit is zero, the value is the first 1 bit we find from
8909 if ((val & 0xffffffff) == 0)
8913 while (((val >>= 1) & 1) == 0)
8919 /* If the low bit is set and the high bit is not, or the mask is all
8920 1's, the value is 31. */
8921 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
8924 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
8927 while (((val <<= 1) & 0x80000000) != 0)
8933 /* Locate some local-dynamic symbol still in use by this function
8934 so that we can print its name in some tls_ld pattern. */
8937 rs6000_get_some_local_dynamic_name (void)
8941 if (cfun->machine->some_ld_name)
8942 return cfun->machine->some_ld_name;
8944 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8946 && for_each_rtx (&PATTERN (insn),
8947 rs6000_get_some_local_dynamic_name_1, 0))
8948 return cfun->machine->some_ld_name;
8953 /* Helper function for rs6000_get_some_local_dynamic_name. */
8956 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8960 if (GET_CODE (x) == SYMBOL_REF)
8962 const char *str = XSTR (x, 0);
8963 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8965 cfun->machine->some_ld_name = str;
8973 /* Print an operand. Recognize special options, documented below. */
8976 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
8977 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
8979 #define SMALL_DATA_RELOC "sda21"
8980 #define SMALL_DATA_REG 0
8984 print_operand (FILE *file, rtx x, int code)
8988 unsigned HOST_WIDE_INT uval;
8993 /* Write out an instruction after the call which may be replaced
8994 with glue code by the loader. This depends on the AIX version. */
8995 asm_fprintf (file, RS6000_CALL_GLUE);
8998 /* %a is output_address. */
9001 /* If X is a constant integer whose low-order 5 bits are zero,
9002 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
9003 in the AIX assembler where "sri" with a zero shift count
9004 writes a trash instruction. */
9005 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
9012 /* If constant, low-order 16 bits of constant, unsigned.
9013 Otherwise, write normally. */
9015 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9017 print_operand (file, x, 0);
9021 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9022 for 64-bit mask direction. */
9023 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
9026 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9030 /* X is a CR register. Print the number of the EQ bit of the CR */
9031 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9032 output_operand_lossage ("invalid %%E value");
9034 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
9038 /* X is a CR register. Print the shift count needed to move it
9039 to the high-order four bits. */
9040 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9041 output_operand_lossage ("invalid %%f value");
9043 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9047 /* Similar, but print the count for the rotate in the opposite
9049 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9050 output_operand_lossage ("invalid %%F value");
9052 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9056 /* X is a constant integer. If it is negative, print "m",
9057 otherwise print "z". This is to make an aze or ame insn. */
9058 if (GET_CODE (x) != CONST_INT)
9059 output_operand_lossage ("invalid %%G value");
9060 else if (INTVAL (x) >= 0)
9067 /* If constant, output low-order five bits. Otherwise, write
9070 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9072 print_operand (file, x, 0);
9076 /* If constant, output low-order six bits. Otherwise, write
9079 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
9081 print_operand (file, x, 0);
9085 /* Print `i' if this is a constant, else nothing. */
9091 /* Write the bit number in CCR for jump. */
9094 output_operand_lossage ("invalid %%j code");
9096 fprintf (file, "%d", i);
9100 /* Similar, but add one for shift count in rlinm for scc and pass
9101 scc flag to `ccr_bit'. */
9104 output_operand_lossage ("invalid %%J code");
9106 /* If we want bit 31, write a shift count of zero, not 32. */
9107 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9111 /* X must be a constant. Write the 1's complement of the
9114 output_operand_lossage ("invalid %%k value");
9116 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9120 /* X must be a symbolic constant on ELF. Write an
9121 expression suitable for an 'addi' that adds in the low 16
9123 if (GET_CODE (x) != CONST)
9125 print_operand_address (file, x);
9130 if (GET_CODE (XEXP (x, 0)) != PLUS
9131 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9132 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9133 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
9134 output_operand_lossage ("invalid %%K value");
9135 print_operand_address (file, XEXP (XEXP (x, 0), 0));
9137 /* For GNU as, there must be a non-alphanumeric character
9138 between 'l' and the number. The '-' is added by
9139 print_operand() already. */
9140 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9142 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9146 /* %l is output_asm_label. */
9149 /* Write second word of DImode or DFmode reference. Works on register
9150 or non-indexed memory only. */
9151 if (GET_CODE (x) == REG)
9152 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
9153 else if (GET_CODE (x) == MEM)
9155 /* Handle possible auto-increment. Since it is pre-increment and
9156 we have already done it, we can just use an offset of word. */
9157 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9158 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9159 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9162 output_address (XEXP (adjust_address_nv (x, SImode,
9166 if (small_data_operand (x, GET_MODE (x)))
9167 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9168 reg_names[SMALL_DATA_REG]);
9173 /* MB value for a mask operand. */
9174 if (! mask_operand (x, SImode))
9175 output_operand_lossage ("invalid %%m value");
9177 fprintf (file, "%d", extract_MB (x));
9181 /* ME value for a mask operand. */
9182 if (! mask_operand (x, SImode))
9183 output_operand_lossage ("invalid %%M value");
9185 fprintf (file, "%d", extract_ME (x));
9188 /* %n outputs the negative of its operand. */
9191 /* Write the number of elements in the vector times 4. */
9192 if (GET_CODE (x) != PARALLEL)
9193 output_operand_lossage ("invalid %%N value");
9195 fprintf (file, "%d", XVECLEN (x, 0) * 4);
9199 /* Similar, but subtract 1 first. */
9200 if (GET_CODE (x) != PARALLEL)
9201 output_operand_lossage ("invalid %%O value");
9203 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9207 /* X is a CONST_INT that is a power of two. Output the logarithm. */
9209 || INT_LOWPART (x) < 0
9210 || (i = exact_log2 (INT_LOWPART (x))) < 0)
9211 output_operand_lossage ("invalid %%p value");
9213 fprintf (file, "%d", i);
9217 /* The operand must be an indirect memory reference. The result
9218 is the register name. */
9219 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9220 || REGNO (XEXP (x, 0)) >= 32)
9221 output_operand_lossage ("invalid %%P value");
9223 fprintf (file, "%s", reg_names[REGNO (XEXP (x, 0))]);
9227 /* This outputs the logical code corresponding to a boolean
9228 expression. The expression may have one or both operands
9229 negated (if one, only the first one). For condition register
9230 logical operations, it will also treat the negated
9231 CR codes as NOTs, but not handle NOTs of them. */
9233 const char *const *t = 0;
9235 enum rtx_code code = GET_CODE (x);
9236 static const char * const tbl[3][3] = {
9237 { "and", "andc", "nor" },
9238 { "or", "orc", "nand" },
9239 { "xor", "eqv", "xor" } };
9243 else if (code == IOR)
9245 else if (code == XOR)
9248 output_operand_lossage ("invalid %%q value");
9250 if (GET_CODE (XEXP (x, 0)) != NOT)
9254 if (GET_CODE (XEXP (x, 1)) == NOT)
9272 /* X is a CR register. Print the mask for `mtcrf'. */
9273 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9274 output_operand_lossage ("invalid %%R value");
9276 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9280 /* Low 5 bits of 32 - value */
9282 output_operand_lossage ("invalid %%s value");
9284 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9288 /* PowerPC64 mask position. All 0's is excluded.
9289 CONST_INT 32-bit mask is considered sign-extended so any
9290 transition must occur within the CONST_INT, not on the boundary. */
9291 if (! mask64_operand (x, DImode))
9292 output_operand_lossage ("invalid %%S value");
9294 uval = INT_LOWPART (x);
9296 if (uval & 1) /* Clear Left */
9298 #if HOST_BITS_PER_WIDE_INT > 64
9299 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9303 else /* Clear Right */
9306 #if HOST_BITS_PER_WIDE_INT > 64
9307 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9315 fprintf (file, "%d", i);
9319 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
9320 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
9323 /* Bit 3 is OV bit. */
9324 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9326 /* If we want bit 31, write a shift count of zero, not 32. */
9327 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9331 /* Print the symbolic name of a branch target register. */
9332 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9333 && REGNO (x) != COUNT_REGISTER_REGNUM))
9334 output_operand_lossage ("invalid %%T value");
9335 else if (REGNO (x) == LINK_REGISTER_REGNUM)
9336 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9338 fputs ("ctr", file);
9342 /* High-order 16 bits of constant for use in unsigned operand. */
9344 output_operand_lossage ("invalid %%u value");
9346 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9347 (INT_LOWPART (x) >> 16) & 0xffff);
9351 /* High-order 16 bits of constant for use in signed operand. */
9353 output_operand_lossage ("invalid %%v value");
9355 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9356 (INT_LOWPART (x) >> 16) & 0xffff);
9360 /* Print `u' if this has an auto-increment or auto-decrement. */
9361 if (GET_CODE (x) == MEM
9362 && (GET_CODE (XEXP (x, 0)) == PRE_INC
9363 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
9368 /* Print the trap code for this operand. */
9369 switch (GET_CODE (x))
9372 fputs ("eq", file); /* 4 */
9375 fputs ("ne", file); /* 24 */
9378 fputs ("lt", file); /* 16 */
9381 fputs ("le", file); /* 20 */
9384 fputs ("gt", file); /* 8 */
9387 fputs ("ge", file); /* 12 */
9390 fputs ("llt", file); /* 2 */
9393 fputs ("lle", file); /* 6 */
9396 fputs ("lgt", file); /* 1 */
9399 fputs ("lge", file); /* 5 */
9407 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
9410 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
9411 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9413 print_operand (file, x, 0);
9417 /* MB value for a PowerPC64 rldic operand. */
9418 val = (GET_CODE (x) == CONST_INT
9419 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9424 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9425 if ((val <<= 1) < 0)
9428 #if HOST_BITS_PER_WIDE_INT == 32
9429 if (GET_CODE (x) == CONST_INT && i >= 0)
9430 i += 32; /* zero-extend high-part was all 0's */
9431 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9433 val = CONST_DOUBLE_LOW (x);
9440 for ( ; i < 64; i++)
9441 if ((val <<= 1) < 0)
9446 fprintf (file, "%d", i + 1);
9450 if (GET_CODE (x) == MEM
9451 && legitimate_indexed_address_p (XEXP (x, 0), 0))
9456 /* Like 'L', for third word of TImode */
9457 if (GET_CODE (x) == REG)
9458 fprintf (file, "%s", reg_names[REGNO (x) + 2]);
9459 else if (GET_CODE (x) == MEM)
9461 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9462 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9463 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9465 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
9466 if (small_data_operand (x, GET_MODE (x)))
9467 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9468 reg_names[SMALL_DATA_REG]);
9473 /* X is a SYMBOL_REF. Write out the name preceded by a
9474 period and without any trailing data in brackets. Used for function
9475 names. If we are configured for System V (or the embedded ABI) on
9476 the PowerPC, do not emit the period, since those systems do not use
9477 TOCs and the like. */
9478 if (GET_CODE (x) != SYMBOL_REF)
9481 if (XSTR (x, 0)[0] != '.')
9483 switch (DEFAULT_ABI)
9498 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
9500 assemble_name (file, XSTR (x, 0));
9504 /* Like 'L', for last word of TImode. */
9505 if (GET_CODE (x) == REG)
9506 fprintf (file, "%s", reg_names[REGNO (x) + 3]);
9507 else if (GET_CODE (x) == MEM)
9509 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9510 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9511 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9513 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
9514 if (small_data_operand (x, GET_MODE (x)))
9515 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9516 reg_names[SMALL_DATA_REG]);
9520 /* Print AltiVec or SPE memory operand. */
9525 if (GET_CODE (x) != MEM)
9533 if (GET_CODE (tmp) == REG)
9535 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9538 /* Handle [reg+UIMM]. */
9539 else if (GET_CODE (tmp) == PLUS &&
9540 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9544 if (GET_CODE (XEXP (tmp, 0)) != REG)
9547 x = INTVAL (XEXP (tmp, 1));
9548 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9552 /* Fall through. Must be [reg+reg]. */
9554 if (GET_CODE (tmp) == REG)
9555 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
9556 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9558 if (REGNO (XEXP (tmp, 0)) == 0)
9559 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9560 reg_names[ REGNO (XEXP (tmp, 0)) ]);
9562 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9563 reg_names[ REGNO (XEXP (tmp, 1)) ]);
9571 if (GET_CODE (x) == REG)
9572 fprintf (file, "%s", reg_names[REGNO (x)]);
9573 else if (GET_CODE (x) == MEM)
9575 /* We need to handle PRE_INC and PRE_DEC here, since we need to
9576 know the width from the mode. */
9577 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
9578 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9579 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9580 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
9581 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9582 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9584 output_address (XEXP (x, 0));
9587 output_addr_const (file, x);
9591 assemble_name (file, rs6000_get_some_local_dynamic_name ());
9595 output_operand_lossage ("invalid %%xn code");
9599 /* Print the address of an operand. */
9602 print_operand_address (FILE *file, rtx x)
9604 if (GET_CODE (x) == REG)
9605 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9606 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9607 || GET_CODE (x) == LABEL_REF)
9609 output_addr_const (file, x);
9610 if (small_data_operand (x, GET_MODE (x)))
9611 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9612 reg_names[SMALL_DATA_REG]);
9613 else if (TARGET_TOC)
9616 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9618 if (REGNO (XEXP (x, 0)) == 0)
9619 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9620 reg_names[ REGNO (XEXP (x, 0)) ]);
9622 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9623 reg_names[ REGNO (XEXP (x, 1)) ]);
9625 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
9626 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9627 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
9629 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9630 && CONSTANT_P (XEXP (x, 1)))
9632 output_addr_const (file, XEXP (x, 1));
9633 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9637 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9638 && CONSTANT_P (XEXP (x, 1)))
9640 fprintf (file, "lo16(");
9641 output_addr_const (file, XEXP (x, 1));
9642 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9645 else if (legitimate_constant_pool_address_p (x))
9647 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9649 rtx contains_minus = XEXP (x, 1);
9653 /* Find the (minus (sym) (toc)) buried in X, and temporarily
9654 turn it into (sym) for output_addr_const. */
9655 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9656 contains_minus = XEXP (contains_minus, 0);
9658 minus = XEXP (contains_minus, 0);
9659 symref = XEXP (minus, 0);
9660 XEXP (contains_minus, 0) = symref;
9665 name = XSTR (symref, 0);
9666 newname = alloca (strlen (name) + sizeof ("@toc"));
9667 strcpy (newname, name);
9668 strcat (newname, "@toc");
9669 XSTR (symref, 0) = newname;
9671 output_addr_const (file, XEXP (x, 1));
9673 XSTR (symref, 0) = name;
9674 XEXP (contains_minus, 0) = minus;
9677 output_addr_const (file, XEXP (x, 1));
9679 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9685 /* Target hook for assembling integer objects. The PowerPC version has
9686 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9687 is defined. It also needs to handle DI-mode objects on 64-bit
9691 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
9693 #ifdef RELOCATABLE_NEEDS_FIXUP
9694 /* Special handling for SI values. */
9695 if (size == 4 && aligned_p)
9697 extern int in_toc_section (void);
9698 static int recurse = 0;
9700 /* For -mrelocatable, we mark all addresses that need to be fixed up
9701 in the .fixup section. */
9702 if (TARGET_RELOCATABLE
9703 && !in_toc_section ()
9704 && !in_text_section ()
9705 && !in_text_unlikely_section ()
9707 && GET_CODE (x) != CONST_INT
9708 && GET_CODE (x) != CONST_DOUBLE
9714 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9716 ASM_OUTPUT_LABEL (asm_out_file, buf);
9717 fprintf (asm_out_file, "\t.long\t(");
9718 output_addr_const (asm_out_file, x);
9719 fprintf (asm_out_file, ")@fixup\n");
9720 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9721 ASM_OUTPUT_ALIGN (asm_out_file, 2);
9722 fprintf (asm_out_file, "\t.long\t");
9723 assemble_name (asm_out_file, buf);
9724 fprintf (asm_out_file, "\n\t.previous\n");
9728 /* Remove initial .'s to turn a -mcall-aixdesc function
9729 address into the address of the descriptor, not the function
9731 else if (GET_CODE (x) == SYMBOL_REF
9732 && XSTR (x, 0)[0] == '.'
9733 && DEFAULT_ABI == ABI_AIX)
9735 const char *name = XSTR (x, 0);
9736 while (*name == '.')
9739 fprintf (asm_out_file, "\t.long\t%s\n", name);
9743 #endif /* RELOCATABLE_NEEDS_FIXUP */
9744 return default_assemble_integer (x, size, aligned_p);
9747 #ifdef HAVE_GAS_HIDDEN
9748 /* Emit an assembler directive to set symbol visibility for DECL to
9752 rs6000_assemble_visibility (tree decl, int vis)
9754 /* Functions need to have their entry point symbol visibility set as
9755 well as their descriptor symbol visibility. */
9756 if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL)
9758 static const char * const visibility_types[] = {
9759 NULL, "internal", "hidden", "protected"
9762 const char *name, *type;
9764 name = ((* targetm.strip_name_encoding)
9765 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
9766 type = visibility_types[vis];
9768 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9769 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
9772 default_assemble_visibility (decl, vis);
9777 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
9779 /* Reversal of FP compares takes care -- an ordered compare
9780 becomes an unordered compare and vice versa. */
9781 if (mode == CCFPmode
9782 && (!flag_finite_math_only
9783 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
9784 || code == UNEQ || code == LTGT))
9785 return reverse_condition_maybe_unordered (code);
9787 return reverse_condition (code);
9790 /* Generate a compare for CODE. Return a brand-new rtx that
9791 represents the result of the compare. */
9794 rs6000_generate_compare (enum rtx_code code)
9796 enum machine_mode comp_mode;
9799 if (rs6000_compare_fp_p)
9800 comp_mode = CCFPmode;
9801 else if (code == GTU || code == LTU
9802 || code == GEU || code == LEU)
9803 comp_mode = CCUNSmode;
9807 /* First, the compare. */
9808 compare_result = gen_reg_rtx (comp_mode);
9810 /* SPE FP compare instructions on the GPRs. Yuck! */
9811 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
9812 && rs6000_compare_fp_p)
9814 rtx cmp, or1, or2, or_result, compare_result2;
9822 cmp = flag_finite_math_only
9823 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
9825 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
9826 rs6000_compare_op1);
9834 cmp = flag_finite_math_only
9835 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
9837 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
9838 rs6000_compare_op1);
9846 cmp = flag_finite_math_only
9847 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
9849 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
9850 rs6000_compare_op1);
9856 /* Synthesize LE and GE from LT/GT || EQ. */
9857 if (code == LE || code == GE || code == LEU || code == GEU)
9859 /* Synthesize GE/LE frome GT/LT || EQ. */
9865 case LE: code = LT; break;
9866 case GE: code = GT; break;
9867 case LEU: code = LT; break;
9868 case GEU: code = GT; break;
9872 or1 = gen_reg_rtx (SImode);
9873 or2 = gen_reg_rtx (SImode);
9874 or_result = gen_reg_rtx (CCEQmode);
9875 compare_result2 = gen_reg_rtx (CCFPmode);
9878 cmp = flag_finite_math_only
9879 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
9881 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
9882 rs6000_compare_op1);
9885 /* The MC8540 FP compare instructions set the CR bits
9886 differently than other PPC compare instructions. For
9887 that matter, there is no generic test instruction, but a
9888 testgt, testlt, and testeq. For a true condition, bit 2
9889 is set (x1xx) in the CR. Following the traditional CR
9895 ... bit 2 would be a GT CR alias, so later on we
9896 look in the GT bits for the branch instructions.
9897 However, we must be careful to emit correct RTL in
9898 the meantime, so optimizations don't get confused. */
9900 or1 = gen_rtx_NE (SImode, compare_result, const0_rtx);
9901 or2 = gen_rtx_NE (SImode, compare_result2, const0_rtx);
9903 /* OR them together. */
9904 cmp = gen_rtx_SET (VOIDmode, or_result,
9905 gen_rtx_COMPARE (CCEQmode,
9906 gen_rtx_IOR (SImode, or1, or2),
9908 compare_result = or_result;
9913 /* We only care about 1 bit (x1xx), so map everything to NE to
9914 maintain rtl sanity. We'll get to the right bit (x1xx) at
9915 code output time. */
9916 if (code == NE || code == LTGT)
9917 /* Do the inverse here because we have no cmpne
9918 instruction. We use the cmpeq instruction and expect
9919 to get a 0 instead. */
9928 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
9929 gen_rtx_COMPARE (comp_mode,
9931 rs6000_compare_op1)));
9933 /* Some kinds of FP comparisons need an OR operation;
9934 under flag_finite_math_only we don't bother. */
9935 if (rs6000_compare_fp_p
9936 && ! flag_finite_math_only
9937 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
9938 && (code == LE || code == GE
9939 || code == UNEQ || code == LTGT
9940 || code == UNGT || code == UNLT))
9942 enum rtx_code or1, or2;
9943 rtx or1_rtx, or2_rtx, compare2_rtx;
9944 rtx or_result = gen_reg_rtx (CCEQmode);
9948 case LE: or1 = LT; or2 = EQ; break;
9949 case GE: or1 = GT; or2 = EQ; break;
9950 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
9951 case LTGT: or1 = LT; or2 = GT; break;
9952 case UNGT: or1 = UNORDERED; or2 = GT; break;
9953 case UNLT: or1 = UNORDERED; or2 = LT; break;
9956 validate_condition_mode (or1, comp_mode);
9957 validate_condition_mode (or2, comp_mode);
9958 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
9959 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
9960 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
9961 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
9963 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
9965 compare_result = or_result;
9969 validate_condition_mode (code, GET_MODE (compare_result));
9971 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
9975 /* Emit the RTL for an sCOND pattern. */
9978 rs6000_emit_sCOND (enum rtx_code code, rtx result)
9981 enum machine_mode op_mode;
9982 enum rtx_code cond_code;
9984 condition_rtx = rs6000_generate_compare (code);
9985 cond_code = GET_CODE (condition_rtx);
9988 || cond_code == GE || cond_code == LE
9989 || cond_code == GEU || cond_code == LEU
9990 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
9992 rtx not_result = gen_reg_rtx (CCEQmode);
9993 rtx not_op, rev_cond_rtx;
9994 enum machine_mode cc_mode;
9996 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
9998 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
9999 SImode, XEXP (condition_rtx, 0), const0_rtx);
10000 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10001 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10002 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10005 op_mode = GET_MODE (rs6000_compare_op0);
10006 if (op_mode == VOIDmode)
10007 op_mode = GET_MODE (rs6000_compare_op1);
10009 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10011 PUT_MODE (condition_rtx, DImode);
10012 convert_move (result, condition_rtx, 0);
10016 PUT_MODE (condition_rtx, SImode);
10017 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10021 /* Emit a branch of kind CODE to location LOC. */
10024 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
10026 rtx condition_rtx, loc_ref;
10028 condition_rtx = rs6000_generate_compare (code);
10029 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10030 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10031 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10032 loc_ref, pc_rtx)));
10035 /* Return the string to output a conditional branch to LABEL, which is
10036 the operand number of the label, or -1 if the branch is really a
10037 conditional return.
10039 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10040 condition code register and its mode specifies what kind of
10041 comparison we made.
10043 REVERSED is nonzero if we should reverse the sense of the comparison.
10045 INSN is the insn. */
10048 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
10050 static char string[64];
10051 enum rtx_code code = GET_CODE (op);
10052 rtx cc_reg = XEXP (op, 0);
10053 enum machine_mode mode = GET_MODE (cc_reg);
10054 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
10055 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
10056 int really_reversed = reversed ^ need_longbranch;
10062 validate_condition_mode (code, mode);
10064 /* Work out which way this really branches. We could use
10065 reverse_condition_maybe_unordered here always but this
10066 makes the resulting assembler clearer. */
10067 if (really_reversed)
10069 /* Reversal of FP compares takes care -- an ordered compare
10070 becomes an unordered compare and vice versa. */
10071 if (mode == CCFPmode)
10072 code = reverse_condition_maybe_unordered (code);
10074 code = reverse_condition (code);
10077 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
10079 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10082 /* Opposite of GT. */
10084 else if (code == NE)
10092 /* Not all of these are actually distinct opcodes, but
10093 we distinguish them for clarity of the resulting assembler. */
10094 case NE: case LTGT:
10095 ccode = "ne"; break;
10096 case EQ: case UNEQ:
10097 ccode = "eq"; break;
10099 ccode = "ge"; break;
10100 case GT: case GTU: case UNGT:
10101 ccode = "gt"; break;
10103 ccode = "le"; break;
10104 case LT: case LTU: case UNLT:
10105 ccode = "lt"; break;
10106 case UNORDERED: ccode = "un"; break;
10107 case ORDERED: ccode = "nu"; break;
10108 case UNGE: ccode = "nl"; break;
10109 case UNLE: ccode = "ng"; break;
10114 /* Maybe we have a guess as to how likely the branch is.
10115 The old mnemonics don't have a way to specify this information. */
10117 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10118 if (note != NULL_RTX)
10120 /* PROB is the difference from 50%. */
10121 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
10123 /* Only hint for highly probable/improbable branches on newer
10124 cpus as static prediction overrides processor dynamic
10125 prediction. For older cpus we may as well always hint, but
10126 assume not taken for branches that are very close to 50% as a
10127 mispredicted taken branch is more expensive than a
10128 mispredicted not-taken branch. */
10129 if (rs6000_always_hint
10130 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10132 if (abs (prob) > REG_BR_PROB_BASE / 20
10133 && ((prob > 0) ^ need_longbranch))
10141 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
10143 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
10145 /* We need to escape any '%' characters in the reg_names string.
10146 Assume they'd only be the first character.... */
10147 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10149 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
10153 /* If the branch distance was too far, we may have to use an
10154 unconditional branch to go the distance. */
10155 if (need_longbranch)
10156 s += sprintf (s, ",$+8\n\tb %s", label);
10158 s += sprintf (s, ",%s", label);
10164 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
10165 operands of the last comparison is nonzero/true, FALSE_COND if it
10166 is zero/false. Return 0 if the hardware has no such operation. */
10169 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10171 enum rtx_code code = GET_CODE (op);
10172 rtx op0 = rs6000_compare_op0;
10173 rtx op1 = rs6000_compare_op1;
10174 REAL_VALUE_TYPE c1;
10175 enum machine_mode compare_mode = GET_MODE (op0);
10176 enum machine_mode result_mode = GET_MODE (dest);
10179 /* These modes should always match. */
10180 if (GET_MODE (op1) != compare_mode
10181 /* In the isel case however, we can use a compare immediate, so
10182 op1 may be a small constant. */
10183 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
10185 if (GET_MODE (true_cond) != result_mode)
10187 if (GET_MODE (false_cond) != result_mode)
10190 /* First, work out if the hardware can do this at all, or
10191 if it's too slow.... */
10192 if (! rs6000_compare_fp_p)
10195 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
10199 /* Eliminate half of the comparisons by switching operands, this
10200 makes the remaining code simpler. */
10201 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
10202 || code == LTGT || code == LT || code == UNLE)
10204 code = reverse_condition_maybe_unordered (code);
10206 true_cond = false_cond;
10210 /* UNEQ and LTGT take four instructions for a comparison with zero,
10211 it'll probably be faster to use a branch here too. */
10212 if (code == UNEQ && HONOR_NANS (compare_mode))
10215 if (GET_CODE (op1) == CONST_DOUBLE)
10216 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
10218 /* We're going to try to implement comparisons by performing
10219 a subtract, then comparing against zero. Unfortunately,
10220 Inf - Inf is NaN which is not zero, and so if we don't
10221 know that the operand is finite and the comparison
10222 would treat EQ different to UNORDERED, we can't do it. */
10223 if (HONOR_INFINITIES (compare_mode)
10224 && code != GT && code != UNGE
10225 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
10226 /* Constructs of the form (a OP b ? a : b) are safe. */
10227 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
10228 || (! rtx_equal_p (op0, true_cond)
10229 && ! rtx_equal_p (op1, true_cond))))
10231 /* At this point we know we can use fsel. */
10233 /* Reduce the comparison to a comparison against zero. */
10234 temp = gen_reg_rtx (compare_mode);
10235 emit_insn (gen_rtx_SET (VOIDmode, temp,
10236 gen_rtx_MINUS (compare_mode, op0, op1)));
10238 op1 = CONST0_RTX (compare_mode);
10240 /* If we don't care about NaNs we can reduce some of the comparisons
10241 down to faster ones. */
10242 if (! HONOR_NANS (compare_mode))
10248 true_cond = false_cond;
10261 /* Now, reduce everything down to a GE. */
10268 temp = gen_reg_rtx (compare_mode);
10269 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10274 temp = gen_reg_rtx (compare_mode);
10275 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
10280 temp = gen_reg_rtx (compare_mode);
10281 emit_insn (gen_rtx_SET (VOIDmode, temp,
10282 gen_rtx_NEG (compare_mode,
10283 gen_rtx_ABS (compare_mode, op0))));
10288 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
10289 temp = gen_reg_rtx (result_mode);
10290 emit_insn (gen_rtx_SET (VOIDmode, temp,
10291 gen_rtx_IF_THEN_ELSE (result_mode,
10292 gen_rtx_GE (VOIDmode,
10294 true_cond, false_cond)));
10295 false_cond = true_cond;
10298 temp = gen_reg_rtx (compare_mode);
10299 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10304 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
10305 temp = gen_reg_rtx (result_mode);
10306 emit_insn (gen_rtx_SET (VOIDmode, temp,
10307 gen_rtx_IF_THEN_ELSE (result_mode,
10308 gen_rtx_GE (VOIDmode,
10310 true_cond, false_cond)));
10311 true_cond = false_cond;
10314 temp = gen_reg_rtx (compare_mode);
10315 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10323 emit_insn (gen_rtx_SET (VOIDmode, dest,
10324 gen_rtx_IF_THEN_ELSE (result_mode,
10325 gen_rtx_GE (VOIDmode,
10327 true_cond, false_cond)));
10331 /* Same as above, but for ints (isel). */
10334 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10336 rtx condition_rtx, cr;
10338 /* All isel implementations thus far are 32-bits. */
10339 if (GET_MODE (rs6000_compare_op0) != SImode)
10342 /* We still have to do the compare, because isel doesn't do a
10343 compare, it just looks at the CRx bits set by a previous compare
10345 condition_rtx = rs6000_generate_compare (GET_CODE (op));
10346 cr = XEXP (condition_rtx, 0);
10348 if (GET_MODE (cr) == CCmode)
10349 emit_insn (gen_isel_signed (dest, condition_rtx,
10350 true_cond, false_cond, cr));
10352 emit_insn (gen_isel_unsigned (dest, condition_rtx,
10353 true_cond, false_cond, cr));
10359 output_isel (rtx *operands)
10361 enum rtx_code code;
10363 code = GET_CODE (operands[1]);
10364 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
10366 PUT_CODE (operands[1], reverse_condition (code));
10367 return "isel %0,%3,%2,%j1";
10370 return "isel %0,%2,%3,%j1";
10374 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
10376 enum machine_mode mode = GET_MODE (op0);
10380 if (code == SMAX || code == SMIN)
10385 if (code == SMAX || code == UMAX)
10386 target = emit_conditional_move (dest, c, op0, op1, mode,
10387 op0, op1, mode, 0);
10389 target = emit_conditional_move (dest, c, op0, op1, mode,
10390 op1, op0, mode, 0);
10391 if (target == NULL_RTX)
10393 if (target != dest)
10394 emit_move_insn (dest, target);
10397 /* Emit instructions to move SRC to DST. Called by splitters for
10398 multi-register moves. It will emit at most one instruction for
10399 each register that is accessed; that is, it won't emit li/lis pairs
10400 (or equivalent for 64-bit code). One of SRC or DST must be a hard
10404 rs6000_split_multireg_move (rtx dst, rtx src)
10406 /* The register number of the first register being moved. */
10408 /* The mode that is to be moved. */
10409 enum machine_mode mode;
10410 /* The mode that the move is being done in, and its size. */
10411 enum machine_mode reg_mode;
10413 /* The number of registers that will be moved. */
10416 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10417 mode = GET_MODE (dst);
10418 nregs = HARD_REGNO_NREGS (reg, mode);
10419 if (FP_REGNO_P (reg))
10421 else if (ALTIVEC_REGNO_P (reg))
10422 reg_mode = V16QImode;
10424 reg_mode = word_mode;
10425 reg_mode_size = GET_MODE_SIZE (reg_mode);
10427 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
10430 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
10432 /* Move register range backwards, if we might have destructive
10435 for (i = nregs - 1; i >= 0; i--)
10436 emit_insn (gen_rtx_SET (VOIDmode,
10437 simplify_gen_subreg (reg_mode, dst, mode,
10438 i * reg_mode_size),
10439 simplify_gen_subreg (reg_mode, src, mode,
10440 i * reg_mode_size)));
10446 bool used_update = false;
10448 if (GET_CODE (src) == MEM && INT_REGNO_P (reg))
10452 if (GET_CODE (XEXP (src, 0)) == PRE_INC
10453 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
10456 breg = XEXP (XEXP (src, 0), 0);
10457 delta_rtx = GET_CODE (XEXP (src, 0)) == PRE_INC
10458 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
10459 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)));
10460 emit_insn (TARGET_32BIT
10461 ? gen_addsi3 (breg, breg, delta_rtx)
10462 : gen_adddi3 (breg, breg, delta_rtx));
10463 src = gen_rtx_MEM (mode, breg);
10466 /* We have now address involving an base register only.
10467 If we use one of the registers to address memory,
10468 we have change that register last. */
10470 breg = (GET_CODE (XEXP (src, 0)) == PLUS
10471 ? XEXP (XEXP (src, 0), 0)
10477 if (REGNO (breg) >= REGNO (dst)
10478 && REGNO (breg) < REGNO (dst) + nregs)
10479 j = REGNO (breg) - REGNO (dst);
10482 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
10486 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
10487 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
10490 breg = XEXP (XEXP (dst, 0), 0);
10491 delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC
10492 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
10493 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)));
10495 /* We have to update the breg before doing the store.
10496 Use store with update, if available. */
10500 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
10501 emit_insn (TARGET_32BIT
10502 ? gen_movsi_update (breg, breg, delta_rtx, nsrc)
10503 : gen_movdi_update (breg, breg, delta_rtx, nsrc));
10504 used_update = true;
10507 emit_insn (TARGET_32BIT
10508 ? gen_addsi3 (breg, breg, delta_rtx)
10509 : gen_adddi3 (breg, breg, delta_rtx));
10510 dst = gen_rtx_MEM (mode, breg);
10514 for (i = 0; i < nregs; i++)
10516 /* Calculate index to next subword. */
10521 /* If compiler already emited move of first word by
10522 store with update, no need to do anything. */
10523 if (j == 0 && used_update)
10526 emit_insn (gen_rtx_SET (VOIDmode,
10527 simplify_gen_subreg (reg_mode, dst, mode,
10528 j * reg_mode_size),
10529 simplify_gen_subreg (reg_mode, src, mode,
10530 j * reg_mode_size)));
10536 /* This page contains routines that are used to determine what the
10537 function prologue and epilogue code will do and write them out. */
10539 /* Return the first fixed-point register that is required to be
10540 saved. 32 if none. */
10543 first_reg_to_save (void)
10547 /* Find lowest numbered live register. */
10548 for (first_reg = 13; first_reg <= 31; first_reg++)
10549 if (regs_ever_live[first_reg]
10550 && (! call_used_regs[first_reg]
10551 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
10552 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
10553 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))))
10558 && current_function_uses_pic_offset_table
10559 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
10560 return RS6000_PIC_OFFSET_TABLE_REGNUM;
10566 /* Similar, for FP regs. */
10569 first_fp_reg_to_save (void)
10573 /* Find lowest numbered live register. */
10574 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
10575 if (regs_ever_live[first_reg])
10581 /* Similar, for AltiVec regs. */
10584 first_altivec_reg_to_save (void)
10588 /* Stack frame remains as is unless we are in AltiVec ABI. */
10589 if (! TARGET_ALTIVEC_ABI)
10590 return LAST_ALTIVEC_REGNO + 1;
10592 /* Find lowest numbered live register. */
10593 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
10594 if (regs_ever_live[i])
10600 /* Return a 32-bit mask of the AltiVec registers we need to set in
10601 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
10602 the 32-bit word is 0. */
10604 static unsigned int
10605 compute_vrsave_mask (void)
10607 unsigned int i, mask = 0;
10609 /* First, find out if we use _any_ altivec registers. */
10610 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10611 if (regs_ever_live[i])
10612 mask |= ALTIVEC_REG_BIT (i);
10617 /* Next, remove the argument registers from the set. These must
10618 be in the VRSAVE mask set by the caller, so we don't need to add
10619 them in again. More importantly, the mask we compute here is
10620 used to generate CLOBBERs in the set_vrsave insn, and we do not
10621 wish the argument registers to die. */
10622 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
10623 mask &= ~ALTIVEC_REG_BIT (i);
10625 /* Similarly, remove the return value from the set. */
10628 diddle_return_value (is_altivec_return_reg, &yes);
10630 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
10637 is_altivec_return_reg (rtx reg, void *xyes)
10639 bool *yes = (bool *) xyes;
10640 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
10645 /* Calculate the stack information for the current function. This is
10646 complicated by having two separate calling sequences, the AIX calling
10647 sequence and the V.4 calling sequence.
10649 AIX (and Darwin/Mac OS X) stack frames look like:
10651 SP----> +---------------------------------------+
10652 | back chain to caller | 0 0
10653 +---------------------------------------+
10654 | saved CR | 4 8 (8-11)
10655 +---------------------------------------+
10657 +---------------------------------------+
10658 | reserved for compilers | 12 24
10659 +---------------------------------------+
10660 | reserved for binders | 16 32
10661 +---------------------------------------+
10662 | saved TOC pointer | 20 40
10663 +---------------------------------------+
10664 | Parameter save area (P) | 24 48
10665 +---------------------------------------+
10666 | Alloca space (A) | 24+P etc.
10667 +---------------------------------------+
10668 | Local variable space (L) | 24+P+A
10669 +---------------------------------------+
10670 | Float/int conversion temporary (X) | 24+P+A+L
10671 +---------------------------------------+
10672 | Save area for AltiVec registers (W) | 24+P+A+L+X
10673 +---------------------------------------+
10674 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
10675 +---------------------------------------+
10676 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
10677 +---------------------------------------+
10678 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
10679 +---------------------------------------+
10680 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
10681 +---------------------------------------+
10682 old SP->| back chain to caller's caller |
10683 +---------------------------------------+
10685 The required alignment for AIX configurations is two words (i.e., 8
10689 V.4 stack frames look like:
10691 SP----> +---------------------------------------+
10692 | back chain to caller | 0
10693 +---------------------------------------+
10694 | caller's saved LR | 4
10695 +---------------------------------------+
10696 | Parameter save area (P) | 8
10697 +---------------------------------------+
10698 | Alloca space (A) | 8+P
10699 +---------------------------------------+
10700 | Varargs save area (V) | 8+P+A
10701 +---------------------------------------+
10702 | Local variable space (L) | 8+P+A+V
10703 +---------------------------------------+
10704 | Float/int conversion temporary (X) | 8+P+A+V+L
10705 +---------------------------------------+
10706 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
10707 +---------------------------------------+
10708 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
10709 +---------------------------------------+
10710 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
10711 +---------------------------------------+
10712 | SPE: area for 64-bit GP registers |
10713 +---------------------------------------+
10714 | SPE alignment padding |
10715 +---------------------------------------+
10716 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
10717 +---------------------------------------+
10718 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
10719 +---------------------------------------+
10720 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
10721 +---------------------------------------+
10722 old SP->| back chain to caller's caller |
10723 +---------------------------------------+
10725 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
10726 given. (But note below and in sysv4.h that we require only 8 and
10727 may round up the size of our stack frame anyways. The historical
10728 reason is early versions of powerpc-linux which didn't properly
10729 align the stack at program startup. A happy side-effect is that
10730 -mno-eabi libraries can be used with -meabi programs.)
10732 The EABI configuration defaults to the V.4 layout. However,
10733 the stack alignment requirements may differ. If -mno-eabi is not
10734 given, the required stack alignment is 8 bytes; if -mno-eabi is
10735 given, the required alignment is 16 bytes. (But see V.4 comment
10738 #ifndef ABI_STACK_BOUNDARY
10739 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
10742 static rs6000_stack_t *
10743 rs6000_stack_info (void)
10745 static rs6000_stack_t info, zero_info;
10746 rs6000_stack_t *info_ptr = &info;
10747 int reg_size = TARGET_32BIT ? 4 : 8;
10749 HOST_WIDE_INT total_raw_size;
10751 /* Zero all fields portably. */
10756 /* Cache value so we don't rescan instruction chain over and over. */
10757 if (cfun->machine->insn_chain_scanned_p == 0)
10759 cfun->machine->insn_chain_scanned_p = 1;
10760 info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
10764 /* Select which calling sequence. */
10765 info_ptr->abi = DEFAULT_ABI;
10767 /* Calculate which registers need to be saved & save area size. */
10768 info_ptr->first_gp_reg_save = first_reg_to_save ();
10769 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
10770 even if it currently looks like we won't. */
10771 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
10772 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
10773 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
10774 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
10775 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
10777 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
10779 /* For the SPE, we have an additional upper 32-bits on each GPR.
10780 Ideally we should save the entire 64-bits only when the upper
10781 half is used in SIMD instructions. Since we only record
10782 registers live (not the size they are used in), this proves
10783 difficult because we'd have to traverse the instruction chain at
10784 the right time, taking reload into account. This is a real pain,
10785 so we opt to save the GPRs in 64-bits always if but one register
10786 gets used in 64-bits. Otherwise, all the registers in the frame
10787 get saved in 32-bits.
10789 So... since when we save all GPRs (except the SP) in 64-bits, the
10790 traditional GP save area will be empty. */
10791 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10792 info_ptr->gp_size = 0;
10794 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
10795 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
10797 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
10798 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
10799 - info_ptr->first_altivec_reg_save);
10801 /* Does this function call anything? */
10802 info_ptr->calls_p = (! current_function_is_leaf
10803 || cfun->machine->ra_needs_full_frame);
10805 /* Determine if we need to save the link register. */
10806 if (rs6000_ra_ever_killed ()
10807 || (DEFAULT_ABI == ABI_AIX
10808 && current_function_profile
10809 && !TARGET_PROFILE_KERNEL)
10810 #ifdef TARGET_RELOCATABLE
10811 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
10813 || (info_ptr->first_fp_reg_save != 64
10814 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
10815 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
10816 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
10817 || (DEFAULT_ABI == ABI_DARWIN
10819 && current_function_uses_pic_offset_table)
10820 || info_ptr->calls_p)
10822 info_ptr->lr_save_p = 1;
10823 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
10826 /* Determine if we need to save the condition code registers. */
10827 if (regs_ever_live[CR2_REGNO]
10828 || regs_ever_live[CR3_REGNO]
10829 || regs_ever_live[CR4_REGNO])
10831 info_ptr->cr_save_p = 1;
10832 if (DEFAULT_ABI == ABI_V4)
10833 info_ptr->cr_size = reg_size;
10836 /* If the current function calls __builtin_eh_return, then we need
10837 to allocate stack space for registers that will hold data for
10838 the exception handler. */
10839 if (current_function_calls_eh_return)
10842 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
10845 /* SPE saves EH registers in 64-bits. */
10846 ehrd_size = i * (TARGET_SPE_ABI
10847 && info_ptr->spe_64bit_regs_used != 0
10848 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
10853 /* Determine various sizes. */
10854 info_ptr->reg_size = reg_size;
10855 info_ptr->fixed_size = RS6000_SAVE_AREA;
10856 info_ptr->varargs_size = RS6000_VARARGS_AREA;
10857 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
10858 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
10861 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10862 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
10864 info_ptr->spe_gp_size = 0;
10866 if (TARGET_ALTIVEC_ABI)
10867 info_ptr->vrsave_mask = compute_vrsave_mask ();
10869 info_ptr->vrsave_mask = 0;
10871 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
10872 info_ptr->vrsave_size = 4;
10874 info_ptr->vrsave_size = 0;
10876 /* Calculate the offsets. */
10877 switch (DEFAULT_ABI)
10885 info_ptr->fp_save_offset = - info_ptr->fp_size;
10886 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
10888 if (TARGET_ALTIVEC_ABI)
10890 info_ptr->vrsave_save_offset
10891 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
10893 /* Align stack so vector save area is on a quadword boundary. */
10894 if (info_ptr->altivec_size != 0)
10895 info_ptr->altivec_padding_size
10896 = 16 - (-info_ptr->vrsave_save_offset % 16);
10898 info_ptr->altivec_padding_size = 0;
10900 info_ptr->altivec_save_offset
10901 = info_ptr->vrsave_save_offset
10902 - info_ptr->altivec_padding_size
10903 - info_ptr->altivec_size;
10905 /* Adjust for AltiVec case. */
10906 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
10909 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
10910 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
10911 info_ptr->lr_save_offset = 2*reg_size;
10915 info_ptr->fp_save_offset = - info_ptr->fp_size;
10916 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
10917 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
10919 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10921 /* Align stack so SPE GPR save area is aligned on a
10922 double-word boundary. */
10923 if (info_ptr->spe_gp_size != 0)
10924 info_ptr->spe_padding_size
10925 = 8 - (-info_ptr->cr_save_offset % 8);
10927 info_ptr->spe_padding_size = 0;
10929 info_ptr->spe_gp_save_offset
10930 = info_ptr->cr_save_offset
10931 - info_ptr->spe_padding_size
10932 - info_ptr->spe_gp_size;
10934 /* Adjust for SPE case. */
10935 info_ptr->toc_save_offset
10936 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
10938 else if (TARGET_ALTIVEC_ABI)
10940 info_ptr->vrsave_save_offset
10941 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
10943 /* Align stack so vector save area is on a quadword boundary. */
10944 if (info_ptr->altivec_size != 0)
10945 info_ptr->altivec_padding_size
10946 = 16 - (-info_ptr->vrsave_save_offset % 16);
10948 info_ptr->altivec_padding_size = 0;
10950 info_ptr->altivec_save_offset
10951 = info_ptr->vrsave_save_offset
10952 - info_ptr->altivec_padding_size
10953 - info_ptr->altivec_size;
10955 /* Adjust for AltiVec case. */
10956 info_ptr->toc_save_offset
10957 = info_ptr->altivec_save_offset - info_ptr->toc_size;
10960 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
10961 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
10962 info_ptr->lr_save_offset = reg_size;
10966 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
10967 + info_ptr->gp_size
10968 + info_ptr->altivec_size
10969 + info_ptr->altivec_padding_size
10970 + info_ptr->spe_gp_size
10971 + info_ptr->spe_padding_size
10973 + info_ptr->cr_size
10974 + info_ptr->lr_size
10975 + info_ptr->vrsave_size
10976 + info_ptr->toc_size,
10977 (TARGET_ALTIVEC_ABI || ABI_DARWIN)
10980 total_raw_size = (info_ptr->vars_size
10981 + info_ptr->parm_size
10982 + info_ptr->save_size
10983 + info_ptr->varargs_size
10984 + info_ptr->fixed_size);
10986 info_ptr->total_size =
10987 RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT);
10989 /* Determine if we need to allocate any stack frame:
10991 For AIX we need to push the stack if a frame pointer is needed
10992 (because the stack might be dynamically adjusted), if we are
10993 debugging, if we make calls, or if the sum of fp_save, gp_save,
10994 and local variables are more than the space needed to save all
10995 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
10996 + 18*8 = 288 (GPR13 reserved).
10998 For V.4 we don't have the stack cushion that AIX uses, but assume
10999 that the debugger can handle stackless frames. */
11001 if (info_ptr->calls_p)
11002 info_ptr->push_p = 1;
11004 else if (DEFAULT_ABI == ABI_V4)
11005 info_ptr->push_p = total_raw_size > info_ptr->fixed_size;
11007 else if (frame_pointer_needed)
11008 info_ptr->push_p = 1;
11010 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
11011 info_ptr->push_p = 1;
11015 = total_raw_size - info_ptr->fixed_size > (TARGET_32BIT ? 220 : 288);
11017 /* Zero offsets if we're not saving those registers. */
11018 if (info_ptr->fp_size == 0)
11019 info_ptr->fp_save_offset = 0;
11021 if (info_ptr->gp_size == 0)
11022 info_ptr->gp_save_offset = 0;
11024 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
11025 info_ptr->altivec_save_offset = 0;
11027 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
11028 info_ptr->vrsave_save_offset = 0;
11030 if (! TARGET_SPE_ABI
11031 || info_ptr->spe_64bit_regs_used == 0
11032 || info_ptr->spe_gp_size == 0)
11033 info_ptr->spe_gp_save_offset = 0;
11035 if (! info_ptr->lr_save_p)
11036 info_ptr->lr_save_offset = 0;
11038 if (! info_ptr->cr_save_p)
11039 info_ptr->cr_save_offset = 0;
11041 if (! info_ptr->toc_save_p)
11042 info_ptr->toc_save_offset = 0;
11047 /* Return true if the current function uses any GPRs in 64-bit SIMD
11051 spe_func_has_64bit_regs_p (void)
11055 /* Functions that save and restore all the call-saved registers will
11056 need to save/restore the registers in 64-bits. */
11057 if (current_function_calls_eh_return
11058 || current_function_calls_setjmp
11059 || current_function_has_nonlocal_goto)
11062 insns = get_insns ();
11064 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
11070 i = PATTERN (insn);
11071 if (GET_CODE (i) == SET
11072 && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i))))
11081 debug_stack_info (rs6000_stack_t *info)
11083 const char *abi_string;
11086 info = rs6000_stack_info ();
11088 fprintf (stderr, "\nStack information for function %s:\n",
11089 ((current_function_decl && DECL_NAME (current_function_decl))
11090 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
11095 default: abi_string = "Unknown"; break;
11096 case ABI_NONE: abi_string = "NONE"; break;
11097 case ABI_AIX: abi_string = "AIX"; break;
11098 case ABI_DARWIN: abi_string = "Darwin"; break;
11099 case ABI_V4: abi_string = "V.4"; break;
11102 fprintf (stderr, "\tABI = %5s\n", abi_string);
11104 if (TARGET_ALTIVEC_ABI)
11105 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
11107 if (TARGET_SPE_ABI)
11108 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
11110 if (info->first_gp_reg_save != 32)
11111 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
11113 if (info->first_fp_reg_save != 64)
11114 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
11116 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
11117 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
11118 info->first_altivec_reg_save);
11120 if (info->lr_save_p)
11121 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
11123 if (info->cr_save_p)
11124 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
11126 if (info->toc_save_p)
11127 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
11129 if (info->vrsave_mask)
11130 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
11133 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
11136 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
11138 if (info->gp_save_offset)
11139 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
11141 if (info->fp_save_offset)
11142 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
11144 if (info->altivec_save_offset)
11145 fprintf (stderr, "\taltivec_save_offset = %5d\n",
11146 info->altivec_save_offset);
11148 if (info->spe_gp_save_offset)
11149 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
11150 info->spe_gp_save_offset);
11152 if (info->vrsave_save_offset)
11153 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
11154 info->vrsave_save_offset);
11156 if (info->lr_save_offset)
11157 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
11159 if (info->cr_save_offset)
11160 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
11162 if (info->toc_save_offset)
11163 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
11165 if (info->varargs_save_offset)
11166 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
11168 if (info->total_size)
11169 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11172 if (info->varargs_size)
11173 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
11175 if (info->vars_size)
11176 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11179 if (info->parm_size)
11180 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
11182 if (info->fixed_size)
11183 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
11186 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
11188 if (info->spe_gp_size)
11189 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
11192 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
11194 if (info->altivec_size)
11195 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
11197 if (info->vrsave_size)
11198 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
11200 if (info->altivec_padding_size)
11201 fprintf (stderr, "\taltivec_padding_size= %5d\n",
11202 info->altivec_padding_size);
11204 if (info->spe_padding_size)
11205 fprintf (stderr, "\tspe_padding_size = %5d\n",
11206 info->spe_padding_size);
11209 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
11212 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
11214 if (info->toc_size)
11215 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
11217 if (info->save_size)
11218 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
11220 if (info->reg_size != 4)
11221 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
11223 fprintf (stderr, "\n");
11227 rs6000_return_addr (int count, rtx frame)
11229 /* Currently we don't optimize very well between prolog and body
11230 code and for PIC code the code can be actually quite bad, so
11231 don't try to be too clever here. */
11232 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
11234 cfun->machine->ra_needs_full_frame = 1;
11241 plus_constant (copy_to_reg
11242 (gen_rtx_MEM (Pmode,
11243 memory_address (Pmode, frame))),
11244 RETURN_ADDRESS_OFFSET)));
11247 cfun->machine->ra_need_lr = 1;
11248 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
11251 /* Say whether a function is a candidate for sibcall handling or not.
11252 We do not allow indirect calls to be optimized into sibling calls.
11253 Also, we can't do it if there are any vector parameters; there's
11254 nowhere to put the VRsave code so it works; note that functions with
11255 vector parameters are required to have a prototype, so the argument
11256 type info must be available here. (The tail recursion case can work
11257 with vector parameters, but there's no way to distinguish here.) */
11259 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
11264 if (TARGET_ALTIVEC_VRSAVE)
11266 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
11267 type; type = TREE_CHAIN (type))
11269 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
11273 if (DEFAULT_ABI == ABI_DARWIN
11274 || (*targetm.binds_local_p) (decl))
11276 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
11278 if (!lookup_attribute ("longcall", attr_list)
11279 || lookup_attribute ("shortcall", attr_list))
11287 rs6000_ra_ever_killed (void)
11293 if (current_function_is_thunk)
11296 /* regs_ever_live has LR marked as used if any sibcalls are present,
11297 but this should not force saving and restoring in the
11298 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
11299 clobbers LR, so that is inappropriate. */
11301 /* Also, the prologue can generate a store into LR that
11302 doesn't really count, like this:
11305 bcl to set PIC register
11309 When we're called from the epilogue, we need to avoid counting
11310 this as a store. */
11312 push_topmost_sequence ();
11313 top = get_insns ();
11314 pop_topmost_sequence ();
11315 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11317 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
11321 if (FIND_REG_INC_NOTE (insn, reg))
11323 else if (GET_CODE (insn) == CALL_INSN
11324 && !SIBLING_CALL_P (insn))
11326 else if (set_of (reg, insn) != NULL_RTX
11327 && !prologue_epilogue_contains (insn))
11334 /* Add a REG_MAYBE_DEAD note to the insn. */
11336 rs6000_maybe_dead (rtx insn)
11338 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
11343 /* Emit instructions needed to load the TOC register.
11344 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
11345 a constant pool; or for SVR4 -fpic. */
11348 rs6000_emit_load_toc_table (int fromprolog)
11351 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11353 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11355 rtx temp = (fromprolog
11356 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11357 : gen_reg_rtx (Pmode));
11358 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
11360 rs6000_maybe_dead (insn);
11361 insn = emit_move_insn (dest, temp);
11363 rs6000_maybe_dead (insn);
11365 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
11368 rtx tempLR = (fromprolog
11369 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11370 : gen_reg_rtx (Pmode));
11371 rtx temp0 = (fromprolog
11372 ? gen_rtx_REG (Pmode, 0)
11373 : gen_reg_rtx (Pmode));
11376 /* possibly create the toc section */
11377 if (! toc_initialized)
11380 function_section (current_function_decl);
11387 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
11388 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11390 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
11391 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11393 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
11395 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
11396 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
11403 static int reload_toc_labelno = 0;
11405 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
11407 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
11408 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11410 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
11411 emit_move_insn (dest, tempLR);
11412 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
11414 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
11416 rs6000_maybe_dead (insn);
11418 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
11420 /* This is for AIX code running in non-PIC ELF32. */
11423 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
11424 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11426 insn = emit_insn (gen_elf_high (dest, realsym));
11428 rs6000_maybe_dead (insn);
11429 insn = emit_insn (gen_elf_low (dest, dest, realsym));
11431 rs6000_maybe_dead (insn);
11433 else if (DEFAULT_ABI == ABI_AIX)
11436 insn = emit_insn (gen_load_toc_aix_si (dest));
11438 insn = emit_insn (gen_load_toc_aix_di (dest));
11440 rs6000_maybe_dead (insn);
11446 /* Emit instructions to restore the link register after determining where
11447 its value has been stored. */
11450 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
11452 rs6000_stack_t *info = rs6000_stack_info ();
11455 operands[0] = source;
11456 operands[1] = scratch;
11458 if (info->lr_save_p)
11460 rtx frame_rtx = stack_pointer_rtx;
11461 HOST_WIDE_INT sp_offset = 0;
11464 if (frame_pointer_needed
11465 || current_function_calls_alloca
11466 || info->total_size > 32767)
11468 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
11469 frame_rtx = operands[1];
11471 else if (info->push_p)
11472 sp_offset = info->total_size;
11474 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
11475 tmp = gen_rtx_MEM (Pmode, tmp);
11476 emit_move_insn (tmp, operands[0]);
11479 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
11482 static GTY(()) int set = -1;
11485 get_TOC_alias_set (void)
11488 set = new_alias_set ();
11492 /* This returns nonzero if the current function uses the TOC. This is
11493 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
11494 is generated by the ABI_V4 load_toc_* patterns. */
11501 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11504 rtx pat = PATTERN (insn);
11507 if (GET_CODE (pat) == PARALLEL)
11508 for (i = 0; i < XVECLEN (pat, 0); i++)
11510 rtx sub = XVECEXP (pat, 0, i);
11511 if (GET_CODE (sub) == USE)
11513 sub = XEXP (sub, 0);
11514 if (GET_CODE (sub) == UNSPEC
11515 && XINT (sub, 1) == UNSPEC_TOC)
11525 create_TOC_reference (rtx symbol)
11527 return gen_rtx_PLUS (Pmode,
11528 gen_rtx_REG (Pmode, TOC_REGISTER),
11529 gen_rtx_CONST (Pmode,
11530 gen_rtx_MINUS (Pmode, symbol,
11531 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
11534 /* If _Unwind_* has been called from within the same module,
11535 toc register is not guaranteed to be saved to 40(1) on function
11536 entry. Save it there in that case. */
11539 rs6000_aix_emit_builtin_unwind_init (void)
11542 rtx stack_top = gen_reg_rtx (Pmode);
11543 rtx opcode_addr = gen_reg_rtx (Pmode);
11544 rtx opcode = gen_reg_rtx (SImode);
11545 rtx tocompare = gen_reg_rtx (SImode);
11546 rtx no_toc_save_needed = gen_label_rtx ();
11548 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
11549 emit_move_insn (stack_top, mem);
11551 mem = gen_rtx_MEM (Pmode,
11552 gen_rtx_PLUS (Pmode, stack_top,
11553 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
11554 emit_move_insn (opcode_addr, mem);
11555 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
11556 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
11557 : 0xE8410028, SImode));
11559 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
11560 SImode, NULL_RTX, NULL_RTX,
11561 no_toc_save_needed);
11563 mem = gen_rtx_MEM (Pmode,
11564 gen_rtx_PLUS (Pmode, stack_top,
11565 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
11566 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
11567 emit_label (no_toc_save_needed);
11570 /* This ties together stack memory (MEM with an alias set of
11571 rs6000_sr_alias_set) and the change to the stack pointer. */
11574 rs6000_emit_stack_tie (void)
11576 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
11578 set_mem_alias_set (mem, rs6000_sr_alias_set);
11579 emit_insn (gen_stack_tie (mem));
11582 /* Emit the correct code for allocating stack space, as insns.
11583 If COPY_R12, make sure a copy of the old frame is left in r12.
11584 The generated code may use hard register 0 as a temporary. */
11587 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
11590 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11591 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
11592 rtx todec = GEN_INT (-size);
11594 if (current_function_limit_stack)
11596 if (REG_P (stack_limit_rtx)
11597 && REGNO (stack_limit_rtx) > 1
11598 && REGNO (stack_limit_rtx) <= 31)
11600 emit_insn (TARGET_32BIT
11601 ? gen_addsi3 (tmp_reg,
11604 : gen_adddi3 (tmp_reg,
11608 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11611 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
11613 && DEFAULT_ABI == ABI_V4)
11615 rtx toload = gen_rtx_CONST (VOIDmode,
11616 gen_rtx_PLUS (Pmode,
11620 emit_insn (gen_elf_high (tmp_reg, toload));
11621 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
11622 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11626 warning ("stack limit expression is not supported");
11629 if (copy_r12 || ! TARGET_UPDATE)
11630 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
11636 /* Need a note here so that try_split doesn't get confused. */
11637 if (get_last_insn() == NULL_RTX)
11638 emit_note (NOTE_INSN_DELETED);
11639 insn = emit_move_insn (tmp_reg, todec);
11640 try_split (PATTERN (insn), insn, 0);
11644 insn = emit_insn (TARGET_32BIT
11645 ? gen_movsi_update (stack_reg, stack_reg,
11647 : gen_movdi_update (stack_reg, stack_reg,
11648 todec, stack_reg));
11652 insn = emit_insn (TARGET_32BIT
11653 ? gen_addsi3 (stack_reg, stack_reg, todec)
11654 : gen_adddi3 (stack_reg, stack_reg, todec));
11655 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
11656 gen_rtx_REG (Pmode, 12));
11659 RTX_FRAME_RELATED_P (insn) = 1;
11661 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11662 gen_rtx_SET (VOIDmode, stack_reg,
11663 gen_rtx_PLUS (Pmode, stack_reg,
11668 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
11669 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
11670 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
11671 deduce these equivalences by itself so it wasn't necessary to hold
11672 its hand so much. */
11675 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
11676 rtx reg2, rtx rreg)
11680 /* copy_rtx will not make unique copies of registers, so we need to
11681 ensure we don't have unwanted sharing here. */
11683 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11686 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11688 real = copy_rtx (PATTERN (insn));
11690 if (reg2 != NULL_RTX)
11691 real = replace_rtx (real, reg2, rreg);
11693 real = replace_rtx (real, reg,
11694 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
11695 STACK_POINTER_REGNUM),
11698 /* We expect that 'real' is either a SET or a PARALLEL containing
11699 SETs (and possibly other stuff). In a PARALLEL, all the SETs
11700 are important so they all have to be marked RTX_FRAME_RELATED_P. */
11702 if (GET_CODE (real) == SET)
11706 temp = simplify_rtx (SET_SRC (set));
11708 SET_SRC (set) = temp;
11709 temp = simplify_rtx (SET_DEST (set));
11711 SET_DEST (set) = temp;
11712 if (GET_CODE (SET_DEST (set)) == MEM)
11714 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11716 XEXP (SET_DEST (set), 0) = temp;
11719 else if (GET_CODE (real) == PARALLEL)
11722 for (i = 0; i < XVECLEN (real, 0); i++)
11723 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
11725 rtx set = XVECEXP (real, 0, i);
11727 temp = simplify_rtx (SET_SRC (set));
11729 SET_SRC (set) = temp;
11730 temp = simplify_rtx (SET_DEST (set));
11732 SET_DEST (set) = temp;
11733 if (GET_CODE (SET_DEST (set)) == MEM)
11735 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11737 XEXP (SET_DEST (set), 0) = temp;
11739 RTX_FRAME_RELATED_P (set) = 1;
11746 real = spe_synthesize_frame_save (real);
11748 RTX_FRAME_RELATED_P (insn) = 1;
11749 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11754 /* Given an SPE frame note, return a PARALLEL of SETs with the
11755 original note, plus a synthetic register save. */
11758 spe_synthesize_frame_save (rtx real)
11760 rtx synth, offset, reg, real2;
11762 if (GET_CODE (real) != SET
11763 || GET_MODE (SET_SRC (real)) != V2SImode)
11766 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
11767 frame related note. The parallel contains a set of the register
11768 being saved, and another set to a synthetic register (n+1200).
11769 This is so we can differentiate between 64-bit and 32-bit saves.
11770 Words cannot describe this nastiness. */
11772 if (GET_CODE (SET_DEST (real)) != MEM
11773 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
11774 || GET_CODE (SET_SRC (real)) != REG)
11778 (set (mem (plus (reg x) (const y)))
11781 (set (mem (plus (reg x) (const y+4)))
11785 real2 = copy_rtx (real);
11786 PUT_MODE (SET_DEST (real2), SImode);
11787 reg = SET_SRC (real2);
11788 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
11789 synth = copy_rtx (real2);
11791 if (BYTES_BIG_ENDIAN)
11793 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
11794 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
11797 reg = SET_SRC (synth);
11799 synth = replace_rtx (synth, reg,
11800 gen_rtx_REG (SImode, REGNO (reg) + 1200));
11802 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
11803 synth = replace_rtx (synth, offset,
11804 GEN_INT (INTVAL (offset)
11805 + (BYTES_BIG_ENDIAN ? 0 : 4)));
11807 RTX_FRAME_RELATED_P (synth) = 1;
11808 RTX_FRAME_RELATED_P (real2) = 1;
11809 if (BYTES_BIG_ENDIAN)
11810 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
11812 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
11817 /* Returns an insn that has a vrsave set operation with the
11818 appropriate CLOBBERs. */
11821 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
11824 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
11825 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
11828 = gen_rtx_SET (VOIDmode,
11830 gen_rtx_UNSPEC_VOLATILE (SImode,
11831 gen_rtvec (2, reg, vrsave),
11836 /* We need to clobber the registers in the mask so the scheduler
11837 does not move sets to VRSAVE before sets of AltiVec registers.
11839 However, if the function receives nonlocal gotos, reload will set
11840 all call saved registers live. We will end up with:
11842 (set (reg 999) (mem))
11843 (parallel [ (set (reg vrsave) (unspec blah))
11844 (clobber (reg 999))])
11846 The clobber will cause the store into reg 999 to be dead, and
11847 flow will attempt to delete an epilogue insn. In this case, we
11848 need an unspec use/set of the register. */
11850 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11851 if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0)
11853 if (!epiloguep || call_used_regs [i])
11854 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
11855 gen_rtx_REG (V4SImode, i));
11858 rtx reg = gen_rtx_REG (V4SImode, i);
11861 = gen_rtx_SET (VOIDmode,
11863 gen_rtx_UNSPEC (V4SImode,
11864 gen_rtvec (1, reg), 27));
11868 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
11870 for (i = 0; i < nclobs; ++i)
11871 XVECEXP (insn, 0, i) = clobs[i];
11876 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
11877 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
11880 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
11881 unsigned int regno, int offset, HOST_WIDE_INT total_size)
11883 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
11884 rtx replacea, replaceb;
11886 int_rtx = GEN_INT (offset);
11888 /* Some cases that need register indexed addressing. */
11889 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
11891 && SPE_VECTOR_MODE (mode)
11892 && !SPE_CONST_OFFSET_OK (offset)))
11894 /* Whomever calls us must make sure r11 is available in the
11895 flow path of instructions in the prologue. */
11896 offset_rtx = gen_rtx_REG (Pmode, 11);
11897 emit_move_insn (offset_rtx, int_rtx);
11899 replacea = offset_rtx;
11900 replaceb = int_rtx;
11904 offset_rtx = int_rtx;
11905 replacea = NULL_RTX;
11906 replaceb = NULL_RTX;
11909 reg = gen_rtx_REG (mode, regno);
11910 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
11911 mem = gen_rtx_MEM (mode, addr);
11912 set_mem_alias_set (mem, rs6000_sr_alias_set);
11914 insn = emit_move_insn (mem, reg);
11916 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
11919 /* Emit an offset memory reference suitable for a frame store, while
11920 converting to a valid addressing mode. */
11923 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
11925 rtx int_rtx, offset_rtx;
11927 int_rtx = GEN_INT (offset);
11929 if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
11931 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
11932 emit_move_insn (offset_rtx, int_rtx);
11935 offset_rtx = int_rtx;
11937 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
11940 /* Emit function prologue as insns. */
11943 rs6000_emit_prologue (void)
11945 rs6000_stack_t *info = rs6000_stack_info ();
11946 enum machine_mode reg_mode = Pmode;
11947 int reg_size = TARGET_32BIT ? 4 : 8;
11948 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11949 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
11950 rtx frame_reg_rtx = sp_reg_rtx;
11951 rtx cr_save_rtx = NULL_RTX;
11953 int saving_FPRs_inline;
11954 int using_store_multiple;
11955 HOST_WIDE_INT sp_offset = 0;
11957 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
11959 reg_mode = V2SImode;
11963 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
11964 && (!TARGET_SPE_ABI
11965 || info->spe_64bit_regs_used == 0)
11966 && info->first_gp_reg_save < 31);
11967 saving_FPRs_inline = (info->first_fp_reg_save == 64
11968 || FP_SAVE_INLINE (info->first_fp_reg_save)
11969 || current_function_calls_eh_return
11970 || cfun->machine->ra_need_lr);
11972 /* For V.4, update stack before we do any saving and set back pointer. */
11974 && (DEFAULT_ABI == ABI_V4
11975 || current_function_calls_eh_return))
11977 if (info->total_size < 32767)
11978 sp_offset = info->total_size;
11980 frame_reg_rtx = frame_ptr_rtx;
11981 rs6000_emit_allocate_stack (info->total_size,
11982 (frame_reg_rtx != sp_reg_rtx
11983 && (info->cr_save_p
11985 || info->first_fp_reg_save < 64
11986 || info->first_gp_reg_save < 32
11988 if (frame_reg_rtx != sp_reg_rtx)
11989 rs6000_emit_stack_tie ();
11992 /* Save AltiVec registers if needed. */
11993 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
11997 /* There should be a non inline version of this, for when we
11998 are saving lots of vector registers. */
11999 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12000 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12002 rtx areg, savereg, mem;
12005 offset = info->altivec_save_offset + sp_offset
12006 + 16 * (i - info->first_altivec_reg_save);
12008 savereg = gen_rtx_REG (V4SImode, i);
12010 areg = gen_rtx_REG (Pmode, 0);
12011 emit_move_insn (areg, GEN_INT (offset));
12013 /* AltiVec addressing mode is [reg+reg]. */
12014 mem = gen_rtx_MEM (V4SImode,
12015 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
12017 set_mem_alias_set (mem, rs6000_sr_alias_set);
12019 insn = emit_move_insn (mem, savereg);
12021 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12022 areg, GEN_INT (offset));
12026 /* VRSAVE is a bit vector representing which AltiVec registers
12027 are used. The OS uses this to determine which vector
12028 registers to save on a context switch. We need to save
12029 VRSAVE on the stack frame, add whatever AltiVec registers we
12030 used in this function, and do the corresponding magic in the
12033 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
12034 && info->vrsave_mask != 0)
12036 rtx reg, mem, vrsave;
12039 /* Get VRSAVE onto a GPR. */
12040 reg = gen_rtx_REG (SImode, 12);
12041 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
12043 emit_insn (gen_get_vrsave_internal (reg));
12045 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
12048 offset = info->vrsave_save_offset + sp_offset;
12050 = gen_rtx_MEM (SImode,
12051 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
12052 set_mem_alias_set (mem, rs6000_sr_alias_set);
12053 insn = emit_move_insn (mem, reg);
12055 /* Include the registers in the mask. */
12056 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
12058 insn = emit_insn (generate_set_vrsave (reg, info, 0));
12061 /* If we use the link register, get it into r0. */
12062 if (info->lr_save_p)
12063 emit_move_insn (gen_rtx_REG (Pmode, 0),
12064 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12066 /* If we need to save CR, put it into r12. */
12067 if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
12069 cr_save_rtx = gen_rtx_REG (SImode, 12);
12070 emit_insn (gen_movesi_from_cr (cr_save_rtx));
12073 /* Do any required saving of fpr's. If only one or two to save, do
12074 it ourselves. Otherwise, call function. */
12075 if (saving_FPRs_inline)
12078 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12079 if ((regs_ever_live[info->first_fp_reg_save+i]
12080 && ! call_used_regs[info->first_fp_reg_save+i]))
12081 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
12082 info->first_fp_reg_save + i,
12083 info->fp_save_offset + sp_offset + 8 * i,
12086 else if (info->first_fp_reg_save != 64)
12090 const char *alloc_rname;
12092 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
12094 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
12095 gen_rtx_REG (Pmode,
12096 LINK_REGISTER_REGNUM));
12097 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
12098 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
12099 alloc_rname = ggc_strdup (rname);
12100 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12101 gen_rtx_SYMBOL_REF (Pmode,
12103 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12105 rtx addr, reg, mem;
12106 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12107 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12108 GEN_INT (info->fp_save_offset
12109 + sp_offset + 8*i));
12110 mem = gen_rtx_MEM (DFmode, addr);
12111 set_mem_alias_set (mem, rs6000_sr_alias_set);
12113 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
12115 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12116 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12117 NULL_RTX, NULL_RTX);
12120 /* Save GPRs. This is done as a PARALLEL if we are using
12121 the store-multiple instructions. */
12122 if (using_store_multiple)
12126 p = rtvec_alloc (32 - info->first_gp_reg_save);
12127 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12129 rtx addr, reg, mem;
12130 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12131 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12132 GEN_INT (info->gp_save_offset
12135 mem = gen_rtx_MEM (reg_mode, addr);
12136 set_mem_alias_set (mem, rs6000_sr_alias_set);
12138 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
12140 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12141 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12142 NULL_RTX, NULL_RTX);
12147 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12148 if ((regs_ever_live[info->first_gp_reg_save+i]
12149 && ! call_used_regs[info->first_gp_reg_save+i])
12150 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12151 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12152 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12154 rtx addr, reg, mem;
12155 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12157 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12159 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12162 if (!SPE_CONST_OFFSET_OK (offset))
12164 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12165 emit_move_insn (b, GEN_INT (offset));
12168 b = GEN_INT (offset);
12170 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12171 mem = gen_rtx_MEM (V2SImode, addr);
12172 set_mem_alias_set (mem, rs6000_sr_alias_set);
12173 insn = emit_move_insn (mem, reg);
12175 if (GET_CODE (b) == CONST_INT)
12176 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12177 NULL_RTX, NULL_RTX);
12179 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12180 b, GEN_INT (offset));
12184 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12185 GEN_INT (info->gp_save_offset
12188 mem = gen_rtx_MEM (reg_mode, addr);
12189 set_mem_alias_set (mem, rs6000_sr_alias_set);
12191 insn = emit_move_insn (mem, reg);
12192 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12193 NULL_RTX, NULL_RTX);
12198 /* ??? There's no need to emit actual instructions here, but it's the
12199 easiest way to get the frame unwind information emitted. */
12200 if (current_function_calls_eh_return)
12202 unsigned int i, regno;
12204 /* In AIX ABI we need to pretend we save r2 here. */
12207 rtx addr, reg, mem;
12209 reg = gen_rtx_REG (reg_mode, 2);
12210 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12211 GEN_INT (sp_offset + 5 * reg_size));
12212 mem = gen_rtx_MEM (reg_mode, addr);
12213 set_mem_alias_set (mem, rs6000_sr_alias_set);
12215 insn = emit_move_insn (mem, reg);
12216 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12217 NULL_RTX, NULL_RTX);
12218 PATTERN (insn) = gen_blockage ();
12223 regno = EH_RETURN_DATA_REGNO (i);
12224 if (regno == INVALID_REGNUM)
12227 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
12228 info->ehrd_offset + sp_offset
12229 + reg_size * (int) i,
12234 /* Save lr if we used it. */
12235 if (info->lr_save_p)
12237 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12238 GEN_INT (info->lr_save_offset + sp_offset));
12239 rtx reg = gen_rtx_REG (Pmode, 0);
12240 rtx mem = gen_rtx_MEM (Pmode, addr);
12241 /* This should not be of rs6000_sr_alias_set, because of
12242 __builtin_return_address. */
12244 insn = emit_move_insn (mem, reg);
12245 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12246 reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12249 /* Save CR if we use any that must be preserved. */
12250 if (info->cr_save_p)
12252 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12253 GEN_INT (info->cr_save_offset + sp_offset));
12254 rtx mem = gen_rtx_MEM (SImode, addr);
12256 set_mem_alias_set (mem, rs6000_sr_alias_set);
12258 /* If r12 was used to hold the original sp, copy cr into r0 now
12260 if (REGNO (frame_reg_rtx) == 12)
12262 cr_save_rtx = gen_rtx_REG (SImode, 0);
12263 emit_insn (gen_movesi_from_cr (cr_save_rtx));
12265 insn = emit_move_insn (mem, cr_save_rtx);
12267 /* Now, there's no way that dwarf2out_frame_debug_expr is going
12268 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
12269 But that's OK. All we have to do is specify that _one_ condition
12270 code register is saved in this stack slot. The thrower's epilogue
12271 will then restore all the call-saved registers.
12272 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
12273 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12274 cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO));
12277 /* Update stack and set back pointer unless this is V.4,
12278 for which it was done previously. */
12280 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
12281 rs6000_emit_allocate_stack (info->total_size, FALSE);
12283 /* Set frame pointer, if needed. */
12284 if (frame_pointer_needed)
12286 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
12288 RTX_FRAME_RELATED_P (insn) = 1;
12291 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
12292 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
12293 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
12294 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
12296 /* If emit_load_toc_table will use the link register, we need to save
12297 it. We use R12 for this purpose because emit_load_toc_table
12298 can use register 0. This allows us to use a plain 'blr' to return
12299 from the procedure more often. */
12300 int save_LR_around_toc_setup = (TARGET_ELF
12301 && DEFAULT_ABI != ABI_AIX
12303 && ! info->lr_save_p
12304 && EXIT_BLOCK_PTR->pred != NULL);
12305 if (save_LR_around_toc_setup)
12307 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
12308 rs6000_maybe_dead (emit_move_insn (frame_ptr_rtx, lr));
12309 rs6000_emit_load_toc_table (TRUE);
12310 rs6000_maybe_dead (emit_move_insn (lr, frame_ptr_rtx));
12313 rs6000_emit_load_toc_table (TRUE);
12317 if (DEFAULT_ABI == ABI_DARWIN
12318 && flag_pic && current_function_uses_pic_offset_table)
12320 rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
12321 const char *picbase = machopic_function_base_name ();
12322 rtx src = gen_rtx_SYMBOL_REF (Pmode, picbase);
12324 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest, src)));
12326 rs6000_maybe_dead (
12327 emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM),
12328 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)));
12333 /* Write function prologue. */
12336 rs6000_output_function_prologue (FILE *file,
12337 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12339 rs6000_stack_t *info = rs6000_stack_info ();
12341 if (TARGET_DEBUG_STACK)
12342 debug_stack_info (info);
12344 /* Write .extern for any function we will call to save and restore
12346 if (info->first_fp_reg_save < 64
12347 && !FP_SAVE_INLINE (info->first_fp_reg_save))
12348 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
12349 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
12350 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
12351 RESTORE_FP_SUFFIX);
12353 /* Write .extern for AIX common mode routines, if needed. */
12354 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
12356 fputs ("\t.extern __mulh\n", file);
12357 fputs ("\t.extern __mull\n", file);
12358 fputs ("\t.extern __divss\n", file);
12359 fputs ("\t.extern __divus\n", file);
12360 fputs ("\t.extern __quoss\n", file);
12361 fputs ("\t.extern __quous\n", file);
12362 common_mode_defined = 1;
12365 if (! HAVE_prologue)
12369 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
12370 the "toplevel" insn chain. */
12371 emit_note (NOTE_INSN_DELETED);
12372 rs6000_emit_prologue ();
12373 emit_note (NOTE_INSN_DELETED);
12375 /* Expand INSN_ADDRESSES so final() doesn't crash. */
12379 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12381 INSN_ADDRESSES_NEW (insn, addr);
12386 if (TARGET_DEBUG_STACK)
12387 debug_rtx_list (get_insns (), 100);
12388 final (get_insns (), file, FALSE, FALSE);
12392 rs6000_pic_labelno++;
12395 /* Emit function epilogue as insns.
12397 At present, dwarf2out_frame_debug_expr doesn't understand
12398 register restores, so we don't bother setting RTX_FRAME_RELATED_P
12399 anywhere in the epilogue. Most of the insns below would in any case
12400 need special notes to explain where r11 is in relation to the stack. */
12403 rs6000_emit_epilogue (int sibcall)
12405 rs6000_stack_t *info;
12406 int restoring_FPRs_inline;
12407 int using_load_multiple;
12408 int using_mfcr_multiple;
12409 int use_backchain_to_restore_sp;
12411 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
12412 rtx frame_reg_rtx = sp_reg_rtx;
12413 enum machine_mode reg_mode = Pmode;
12414 int reg_size = TARGET_32BIT ? 4 : 8;
12417 info = rs6000_stack_info ();
12419 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12421 reg_mode = V2SImode;
12425 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12426 && (!TARGET_SPE_ABI
12427 || info->spe_64bit_regs_used == 0)
12428 && info->first_gp_reg_save < 31);
12429 restoring_FPRs_inline = (sibcall
12430 || current_function_calls_eh_return
12431 || info->first_fp_reg_save == 64
12432 || FP_SAVE_INLINE (info->first_fp_reg_save));
12433 use_backchain_to_restore_sp = (frame_pointer_needed
12434 || current_function_calls_alloca
12435 || info->total_size > 32767);
12436 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
12437 || rs6000_cpu == PROCESSOR_PPC603
12438 || rs6000_cpu == PROCESSOR_PPC750
12441 /* If we have a frame pointer, a call to alloca, or a large stack
12442 frame, restore the old stack pointer using the backchain. Otherwise,
12443 we know what size to update it with. */
12444 if (use_backchain_to_restore_sp)
12446 /* Under V.4, don't reset the stack pointer until after we're done
12447 loading the saved registers. */
12448 if (DEFAULT_ABI == ABI_V4)
12449 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
12451 emit_move_insn (frame_reg_rtx,
12452 gen_rtx_MEM (Pmode, sp_reg_rtx));
12455 else if (info->push_p)
12457 if (DEFAULT_ABI == ABI_V4
12458 || current_function_calls_eh_return)
12459 sp_offset = info->total_size;
12462 emit_insn (TARGET_32BIT
12463 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12464 GEN_INT (info->total_size))
12465 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12466 GEN_INT (info->total_size)));
12470 /* Restore AltiVec registers if needed. */
12471 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
12475 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12476 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12478 rtx addr, areg, mem;
12480 areg = gen_rtx_REG (Pmode, 0);
12482 (areg, GEN_INT (info->altivec_save_offset
12484 + 16 * (i - info->first_altivec_reg_save)));
12486 /* AltiVec addressing mode is [reg+reg]. */
12487 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
12488 mem = gen_rtx_MEM (V4SImode, addr);
12489 set_mem_alias_set (mem, rs6000_sr_alias_set);
12491 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
12495 /* Restore VRSAVE if needed. */
12496 if (TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE
12497 && info->vrsave_mask != 0)
12499 rtx addr, mem, reg;
12501 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12502 GEN_INT (info->vrsave_save_offset + sp_offset));
12503 mem = gen_rtx_MEM (SImode, addr);
12504 set_mem_alias_set (mem, rs6000_sr_alias_set);
12505 reg = gen_rtx_REG (SImode, 12);
12506 emit_move_insn (reg, mem);
12508 emit_insn (generate_set_vrsave (reg, info, 1));
12511 /* Get the old lr if we saved it. */
12512 if (info->lr_save_p)
12514 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
12515 info->lr_save_offset + sp_offset);
12517 set_mem_alias_set (mem, rs6000_sr_alias_set);
12519 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
12522 /* Get the old cr if we saved it. */
12523 if (info->cr_save_p)
12525 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12526 GEN_INT (info->cr_save_offset + sp_offset));
12527 rtx mem = gen_rtx_MEM (SImode, addr);
12529 set_mem_alias_set (mem, rs6000_sr_alias_set);
12531 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
12534 /* Set LR here to try to overlap restores below. */
12535 if (info->lr_save_p)
12536 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
12537 gen_rtx_REG (Pmode, 0));
12539 /* Load exception handler data registers, if needed. */
12540 if (current_function_calls_eh_return)
12542 unsigned int i, regno;
12546 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12547 GEN_INT (sp_offset + 5 * reg_size));
12548 rtx mem = gen_rtx_MEM (reg_mode, addr);
12550 set_mem_alias_set (mem, rs6000_sr_alias_set);
12552 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
12559 regno = EH_RETURN_DATA_REGNO (i);
12560 if (regno == INVALID_REGNUM)
12563 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
12564 info->ehrd_offset + sp_offset
12565 + reg_size * (int) i);
12566 set_mem_alias_set (mem, rs6000_sr_alias_set);
12568 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
12572 /* Restore GPRs. This is done as a PARALLEL if we are using
12573 the load-multiple instructions. */
12574 if (using_load_multiple)
12577 p = rtvec_alloc (32 - info->first_gp_reg_save);
12578 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12580 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12581 GEN_INT (info->gp_save_offset
12584 rtx mem = gen_rtx_MEM (reg_mode, addr);
12586 set_mem_alias_set (mem, rs6000_sr_alias_set);
12589 gen_rtx_SET (VOIDmode,
12590 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
12593 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12596 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12597 if ((regs_ever_live[info->first_gp_reg_save+i]
12598 && ! call_used_regs[info->first_gp_reg_save+i])
12599 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12600 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12601 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12603 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12604 GEN_INT (info->gp_save_offset
12607 rtx mem = gen_rtx_MEM (reg_mode, addr);
12609 /* Restore 64-bit quantities for SPE. */
12610 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12612 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12615 if (!SPE_CONST_OFFSET_OK (offset))
12617 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12618 emit_move_insn (b, GEN_INT (offset));
12621 b = GEN_INT (offset);
12623 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12624 mem = gen_rtx_MEM (V2SImode, addr);
12627 set_mem_alias_set (mem, rs6000_sr_alias_set);
12629 emit_move_insn (gen_rtx_REG (reg_mode,
12630 info->first_gp_reg_save + i), mem);
12633 /* Restore fpr's if we need to do it without calling a function. */
12634 if (restoring_FPRs_inline)
12635 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12636 if ((regs_ever_live[info->first_fp_reg_save+i]
12637 && ! call_used_regs[info->first_fp_reg_save+i]))
12640 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12641 GEN_INT (info->fp_save_offset
12644 mem = gen_rtx_MEM (DFmode, addr);
12645 set_mem_alias_set (mem, rs6000_sr_alias_set);
12647 emit_move_insn (gen_rtx_REG (DFmode,
12648 info->first_fp_reg_save + i),
12652 /* If we saved cr, restore it here. Just those that were used. */
12653 if (info->cr_save_p)
12655 rtx r12_rtx = gen_rtx_REG (SImode, 12);
12658 if (using_mfcr_multiple)
12660 for (i = 0; i < 8; i++)
12661 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12667 if (using_mfcr_multiple && count > 1)
12672 p = rtvec_alloc (count);
12675 for (i = 0; i < 8; i++)
12676 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12678 rtvec r = rtvec_alloc (2);
12679 RTVEC_ELT (r, 0) = r12_rtx;
12680 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
12681 RTVEC_ELT (p, ndx) =
12682 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
12683 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
12686 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12691 for (i = 0; i < 8; i++)
12692 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12694 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
12700 /* If this is V.4, unwind the stack pointer after all of the loads
12701 have been done. We need to emit a block here so that sched
12702 doesn't decide to move the sp change before the register restores
12703 (which may not have any obvious dependency on the stack). This
12704 doesn't hurt performance, because there is no scheduling that can
12705 be done after this point. */
12706 if (DEFAULT_ABI == ABI_V4
12707 || current_function_calls_eh_return)
12709 if (frame_reg_rtx != sp_reg_rtx)
12710 rs6000_emit_stack_tie ();
12712 if (use_backchain_to_restore_sp)
12714 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
12716 else if (sp_offset != 0)
12718 emit_insn (TARGET_32BIT
12719 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12720 GEN_INT (sp_offset))
12721 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12722 GEN_INT (sp_offset)));
12726 if (current_function_calls_eh_return)
12728 rtx sa = EH_RETURN_STACKADJ_RTX;
12729 emit_insn (TARGET_32BIT
12730 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
12731 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
12737 if (! restoring_FPRs_inline)
12738 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
12740 p = rtvec_alloc (2);
12742 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
12743 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12744 gen_rtx_REG (Pmode,
12745 LINK_REGISTER_REGNUM));
12747 /* If we have to restore more than two FP registers, branch to the
12748 restore function. It will return to our caller. */
12749 if (! restoring_FPRs_inline)
12753 const char *alloc_rname;
12755 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
12756 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
12757 alloc_rname = ggc_strdup (rname);
12758 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
12759 gen_rtx_SYMBOL_REF (Pmode,
12762 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12765 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
12766 GEN_INT (info->fp_save_offset + 8*i));
12767 mem = gen_rtx_MEM (DFmode, addr);
12768 set_mem_alias_set (mem, rs6000_sr_alias_set);
12770 RTVEC_ELT (p, i+3) =
12771 gen_rtx_SET (VOIDmode,
12772 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
12777 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
12781 /* Write function epilogue. */
12784 rs6000_output_function_epilogue (FILE *file,
12785 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12787 rs6000_stack_t *info = rs6000_stack_info ();
12789 if (! HAVE_epilogue)
12791 rtx insn = get_last_insn ();
12792 /* If the last insn was a BARRIER, we don't have to write anything except
12793 the trace table. */
12794 if (GET_CODE (insn) == NOTE)
12795 insn = prev_nonnote_insn (insn);
12796 if (insn == 0 || GET_CODE (insn) != BARRIER)
12798 /* This is slightly ugly, but at least we don't have two
12799 copies of the epilogue-emitting code. */
12802 /* A NOTE_INSN_DELETED is supposed to be at the start
12803 and end of the "toplevel" insn chain. */
12804 emit_note (NOTE_INSN_DELETED);
12805 rs6000_emit_epilogue (FALSE);
12806 emit_note (NOTE_INSN_DELETED);
12808 /* Expand INSN_ADDRESSES so final() doesn't crash. */
12812 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12814 INSN_ADDRESSES_NEW (insn, addr);
12819 if (TARGET_DEBUG_STACK)
12820 debug_rtx_list (get_insns (), 100);
12821 final (get_insns (), file, FALSE, FALSE);
12827 macho_branch_islands ();
12828 /* Mach-O doesn't support labels at the end of objects, so if
12829 it looks like we might want one, insert a NOP. */
12831 rtx insn = get_last_insn ();
12834 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
12835 insn = PREV_INSN (insn);
12839 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
12840 fputs ("\tnop\n", file);
12844 /* Output a traceback table here. See /usr/include/sys/debug.h for info
12847 We don't output a traceback table if -finhibit-size-directive was
12848 used. The documentation for -finhibit-size-directive reads
12849 ``don't output a @code{.size} assembler directive, or anything
12850 else that would cause trouble if the function is split in the
12851 middle, and the two halves are placed at locations far apart in
12852 memory.'' The traceback table has this property, since it
12853 includes the offset from the start of the function to the
12854 traceback table itself.
12856 System V.4 Powerpc's (and the embedded ABI derived from it) use a
12857 different traceback table. */
12858 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
12859 && rs6000_traceback != traceback_none)
12861 const char *fname = NULL;
12862 const char *language_string = lang_hooks.name;
12863 int fixed_parms = 0, float_parms = 0, parm_info = 0;
12865 int optional_tbtab;
12867 if (rs6000_traceback == traceback_full)
12868 optional_tbtab = 1;
12869 else if (rs6000_traceback == traceback_part)
12870 optional_tbtab = 0;
12872 optional_tbtab = !optimize_size && !TARGET_ELF;
12874 if (optional_tbtab)
12876 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
12877 while (*fname == '.') /* V.4 encodes . in the name */
12880 /* Need label immediately before tbtab, so we can compute
12881 its offset from the function start. */
12882 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
12883 ASM_OUTPUT_LABEL (file, fname);
12886 /* The .tbtab pseudo-op can only be used for the first eight
12887 expressions, since it can't handle the possibly variable
12888 length fields that follow. However, if you omit the optional
12889 fields, the assembler outputs zeros for all optional fields
12890 anyways, giving each variable length field is minimum length
12891 (as defined in sys/debug.h). Thus we can not use the .tbtab
12892 pseudo-op at all. */
12894 /* An all-zero word flags the start of the tbtab, for debuggers
12895 that have to find it by searching forward from the entry
12896 point or from the current pc. */
12897 fputs ("\t.long 0\n", file);
12899 /* Tbtab format type. Use format type 0. */
12900 fputs ("\t.byte 0,", file);
12902 /* Language type. Unfortunately, there does not seem to be any
12903 official way to discover the language being compiled, so we
12904 use language_string.
12905 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
12906 Java is 13. Objective-C is 14. */
12907 if (! strcmp (language_string, "GNU C"))
12909 else if (! strcmp (language_string, "GNU F77"))
12911 else if (! strcmp (language_string, "GNU Pascal"))
12913 else if (! strcmp (language_string, "GNU Ada"))
12915 else if (! strcmp (language_string, "GNU C++"))
12917 else if (! strcmp (language_string, "GNU Java"))
12919 else if (! strcmp (language_string, "GNU Objective-C"))
12923 fprintf (file, "%d,", i);
12925 /* 8 single bit fields: global linkage (not set for C extern linkage,
12926 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
12927 from start of procedure stored in tbtab, internal function, function
12928 has controlled storage, function has no toc, function uses fp,
12929 function logs/aborts fp operations. */
12930 /* Assume that fp operations are used if any fp reg must be saved. */
12931 fprintf (file, "%d,",
12932 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
12934 /* 6 bitfields: function is interrupt handler, name present in
12935 proc table, function calls alloca, on condition directives
12936 (controls stack walks, 3 bits), saves condition reg, saves
12938 /* The `function calls alloca' bit seems to be set whenever reg 31 is
12939 set up as a frame pointer, even when there is no alloca call. */
12940 fprintf (file, "%d,",
12941 ((optional_tbtab << 6)
12942 | ((optional_tbtab & frame_pointer_needed) << 5)
12943 | (info->cr_save_p << 1)
12944 | (info->lr_save_p)));
12946 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
12948 fprintf (file, "%d,",
12949 (info->push_p << 7) | (64 - info->first_fp_reg_save));
12951 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
12952 fprintf (file, "%d,", (32 - first_reg_to_save ()));
12954 if (optional_tbtab)
12956 /* Compute the parameter info from the function decl argument
12959 int next_parm_info_bit = 31;
12961 for (decl = DECL_ARGUMENTS (current_function_decl);
12962 decl; decl = TREE_CHAIN (decl))
12964 rtx parameter = DECL_INCOMING_RTL (decl);
12965 enum machine_mode mode = GET_MODE (parameter);
12967 if (GET_CODE (parameter) == REG)
12969 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
12975 if (mode == SFmode)
12977 else if (mode == DFmode || mode == TFmode)
12982 /* If only one bit will fit, don't or in this entry. */
12983 if (next_parm_info_bit > 0)
12984 parm_info |= (bits << (next_parm_info_bit - 1));
12985 next_parm_info_bit -= 2;
12989 fixed_parms += ((GET_MODE_SIZE (mode)
12990 + (UNITS_PER_WORD - 1))
12992 next_parm_info_bit -= 1;
12998 /* Number of fixed point parameters. */
12999 /* This is actually the number of words of fixed point parameters; thus
13000 an 8 byte struct counts as 2; and thus the maximum value is 8. */
13001 fprintf (file, "%d,", fixed_parms);
13003 /* 2 bitfields: number of floating point parameters (7 bits), parameters
13005 /* This is actually the number of fp registers that hold parameters;
13006 and thus the maximum value is 13. */
13007 /* Set parameters on stack bit if parameters are not in their original
13008 registers, regardless of whether they are on the stack? Xlc
13009 seems to set the bit when not optimizing. */
13010 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
13012 if (! optional_tbtab)
13015 /* Optional fields follow. Some are variable length. */
13017 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
13018 11 double float. */
13019 /* There is an entry for each parameter in a register, in the order that
13020 they occur in the parameter list. Any intervening arguments on the
13021 stack are ignored. If the list overflows a long (max possible length
13022 34 bits) then completely leave off all elements that don't fit. */
13023 /* Only emit this long if there was at least one parameter. */
13024 if (fixed_parms || float_parms)
13025 fprintf (file, "\t.long %d\n", parm_info);
13027 /* Offset from start of code to tb table. */
13028 fputs ("\t.long ", file);
13029 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13031 RS6000_OUTPUT_BASENAME (file, fname);
13033 assemble_name (file, fname);
13035 fputs ("-.", file);
13037 RS6000_OUTPUT_BASENAME (file, fname);
13039 assemble_name (file, fname);
13043 /* Interrupt handler mask. */
13044 /* Omit this long, since we never set the interrupt handler bit
13047 /* Number of CTL (controlled storage) anchors. */
13048 /* Omit this long, since the has_ctl bit is never set above. */
13050 /* Displacement into stack of each CTL anchor. */
13051 /* Omit this list of longs, because there are no CTL anchors. */
13053 /* Length of function name. */
13056 fprintf (file, "\t.short %d\n", (int) strlen (fname));
13058 /* Function name. */
13059 assemble_string (fname, strlen (fname));
13061 /* Register for alloca automatic storage; this is always reg 31.
13062 Only emit this if the alloca bit was set above. */
13063 if (frame_pointer_needed)
13064 fputs ("\t.byte 31\n", file);
13066 fputs ("\t.align 2\n", file);
13070 /* A C compound statement that outputs the assembler code for a thunk
13071 function, used to implement C++ virtual function calls with
13072 multiple inheritance. The thunk acts as a wrapper around a virtual
13073 function, adjusting the implicit object parameter before handing
13074 control off to the real function.
13076 First, emit code to add the integer DELTA to the location that
13077 contains the incoming first argument. Assume that this argument
13078 contains a pointer, and is the one used to pass the `this' pointer
13079 in C++. This is the incoming argument *before* the function
13080 prologue, e.g. `%o0' on a sparc. The addition must preserve the
13081 values of all other incoming arguments.
13083 After the addition, emit code to jump to FUNCTION, which is a
13084 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
13085 not touch the return address. Hence returning from FUNCTION will
13086 return to whoever called the current `thunk'.
13088 The effect must be as if FUNCTION had been called directly with the
13089 adjusted first argument. This macro is responsible for emitting
13090 all of the code for a thunk function; output_function_prologue()
13091 and output_function_epilogue() are not invoked.
13093 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
13094 been extracted from it.) It might possibly be useful on some
13095 targets, but probably not.
13097 If you do not define this macro, the target-independent code in the
13098 C++ frontend will generate a less efficient heavyweight thunk that
13099 calls FUNCTION instead of jumping to it. The generic approach does
13100 not support varargs. */
13103 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
13104 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
13107 rtx this, insn, funexp;
13109 reload_completed = 1;
13110 epilogue_completed = 1;
13111 no_new_pseudos = 1;
13113 /* Mark the end of the (empty) prologue. */
13114 emit_note (NOTE_INSN_PROLOGUE_END);
13116 /* Find the "this" pointer. If the function returns a structure,
13117 the structure return pointer is in r3. */
13118 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
13119 this = gen_rtx_REG (Pmode, 4);
13121 this = gen_rtx_REG (Pmode, 3);
13123 /* Apply the constant offset, if required. */
13126 rtx delta_rtx = GEN_INT (delta);
13127 emit_insn (TARGET_32BIT
13128 ? gen_addsi3 (this, this, delta_rtx)
13129 : gen_adddi3 (this, this, delta_rtx));
13132 /* Apply the offset from the vtable, if required. */
13135 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
13136 rtx tmp = gen_rtx_REG (Pmode, 12);
13138 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
13139 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
13141 emit_insn (TARGET_32BIT
13142 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
13143 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
13144 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
13148 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
13150 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
13152 emit_insn (TARGET_32BIT
13153 ? gen_addsi3 (this, this, tmp)
13154 : gen_adddi3 (this, this, tmp));
13157 /* Generate a tail call to the target function. */
13158 if (!TREE_USED (function))
13160 assemble_external (function);
13161 TREE_USED (function) = 1;
13163 funexp = XEXP (DECL_RTL (function), 0);
13164 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
13167 if (MACHOPIC_INDIRECT)
13168 funexp = machopic_indirect_call_target (funexp);
13171 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
13172 generate sibcall RTL explicitly to avoid constraint abort. */
13173 insn = emit_call_insn (
13174 gen_rtx_PARALLEL (VOIDmode,
13176 gen_rtx_CALL (VOIDmode,
13177 funexp, const0_rtx),
13178 gen_rtx_USE (VOIDmode, const0_rtx),
13179 gen_rtx_USE (VOIDmode,
13180 gen_rtx_REG (SImode,
13181 LINK_REGISTER_REGNUM)),
13182 gen_rtx_RETURN (VOIDmode))));
13183 SIBLING_CALL_P (insn) = 1;
13186 /* Run just enough of rest_of_compilation to get the insns emitted.
13187 There's not really enough bulk here to make other passes such as
13188 instruction scheduling worth while. Note that use_thunk calls
13189 assemble_start_function and assemble_end_function. */
13190 insn = get_insns ();
13191 insn_locators_initialize ();
13192 shorten_branches (insn);
13193 final_start_function (insn, file, 1);
13194 final (insn, file, 1, 0);
13195 final_end_function ();
13197 reload_completed = 0;
13198 epilogue_completed = 0;
13199 no_new_pseudos = 0;
13202 /* A quick summary of the various types of 'constant-pool tables'
13205 Target Flags Name One table per
13206 AIX (none) AIX TOC object file
13207 AIX -mfull-toc AIX TOC object file
13208 AIX -mminimal-toc AIX minimal TOC translation unit
13209 SVR4/EABI (none) SVR4 SDATA object file
13210 SVR4/EABI -fpic SVR4 pic object file
13211 SVR4/EABI -fPIC SVR4 PIC translation unit
13212 SVR4/EABI -mrelocatable EABI TOC function
13213 SVR4/EABI -maix AIX TOC object file
13214 SVR4/EABI -maix -mminimal-toc
13215 AIX minimal TOC translation unit
13217 Name Reg. Set by entries contains:
13218 made by addrs? fp? sum?
13220 AIX TOC 2 crt0 as Y option option
13221 AIX minimal TOC 30 prolog gcc Y Y option
13222 SVR4 SDATA 13 crt0 gcc N Y N
13223 SVR4 pic 30 prolog ld Y not yet N
13224 SVR4 PIC 30 prolog gcc Y option option
13225 EABI TOC 30 prolog gcc Y option option
13229 /* Hash functions for the hash table. */
13232 rs6000_hash_constant (rtx k)
13234 enum rtx_code code = GET_CODE (k);
13235 enum machine_mode mode = GET_MODE (k);
13236 unsigned result = (code << 3) ^ mode;
13237 const char *format;
13240 format = GET_RTX_FORMAT (code);
13241 flen = strlen (format);
13247 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
13250 if (mode != VOIDmode)
13251 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
13263 for (; fidx < flen; fidx++)
13264 switch (format[fidx])
13269 const char *str = XSTR (k, fidx);
13270 len = strlen (str);
13271 result = result * 613 + len;
13272 for (i = 0; i < len; i++)
13273 result = result * 613 + (unsigned) str[i];
13278 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
13282 result = result * 613 + (unsigned) XINT (k, fidx);
13285 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
13286 result = result * 613 + (unsigned) XWINT (k, fidx);
13290 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
13291 result = result * 613 + (unsigned) (XWINT (k, fidx)
13305 toc_hash_function (const void *hash_entry)
13307 const struct toc_hash_struct *thc =
13308 (const struct toc_hash_struct *) hash_entry;
13309 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
13312 /* Compare H1 and H2 for equivalence. */
13315 toc_hash_eq (const void *h1, const void *h2)
13317 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
13318 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
13320 if (((const struct toc_hash_struct *) h1)->key_mode
13321 != ((const struct toc_hash_struct *) h2)->key_mode)
13324 return rtx_equal_p (r1, r2);
13327 /* These are the names given by the C++ front-end to vtables, and
13328 vtable-like objects. Ideally, this logic should not be here;
13329 instead, there should be some programmatic way of inquiring as
13330 to whether or not an object is a vtable. */
13332 #define VTABLE_NAME_P(NAME) \
13333 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
13334 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
13335 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
13336 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
13337 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
13340 rs6000_output_symbol_ref (FILE *file, rtx x)
13342 /* Currently C++ toc references to vtables can be emitted before it
13343 is decided whether the vtable is public or private. If this is
13344 the case, then the linker will eventually complain that there is
13345 a reference to an unknown section. Thus, for vtables only,
13346 we emit the TOC reference to reference the symbol and not the
13348 const char *name = XSTR (x, 0);
13350 if (VTABLE_NAME_P (name))
13352 RS6000_OUTPUT_BASENAME (file, name);
13355 assemble_name (file, name);
13358 /* Output a TOC entry. We derive the entry name from what is being
13362 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
13365 const char *name = buf;
13366 const char *real_name;
13373 /* When the linker won't eliminate them, don't output duplicate
13374 TOC entries (this happens on AIX if there is any kind of TOC,
13375 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
13377 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
13379 struct toc_hash_struct *h;
13382 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
13383 time because GGC is not initialized at that point. */
13384 if (toc_hash_table == NULL)
13385 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
13386 toc_hash_eq, NULL);
13388 h = ggc_alloc (sizeof (*h));
13390 h->key_mode = mode;
13391 h->labelno = labelno;
13393 found = htab_find_slot (toc_hash_table, h, 1);
13394 if (*found == NULL)
13396 else /* This is indeed a duplicate.
13397 Set this label equal to that label. */
13399 fputs ("\t.set ", file);
13400 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
13401 fprintf (file, "%d,", labelno);
13402 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
13403 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
13409 /* If we're going to put a double constant in the TOC, make sure it's
13410 aligned properly when strict alignment is on. */
13411 if (GET_CODE (x) == CONST_DOUBLE
13412 && STRICT_ALIGNMENT
13413 && GET_MODE_BITSIZE (mode) >= 64
13414 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
13415 ASM_OUTPUT_ALIGN (file, 3);
13418 (*targetm.asm_out.internal_label) (file, "LC", labelno);
13420 /* Handle FP constants specially. Note that if we have a minimal
13421 TOC, things we put here aren't actually in the TOC, so we can allow
13423 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
13425 REAL_VALUE_TYPE rv;
13428 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13429 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
13433 if (TARGET_MINIMAL_TOC)
13434 fputs (DOUBLE_INT_ASM_OP, file);
13436 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13437 k[0] & 0xffffffff, k[1] & 0xffffffff,
13438 k[2] & 0xffffffff, k[3] & 0xffffffff);
13439 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
13440 k[0] & 0xffffffff, k[1] & 0xffffffff,
13441 k[2] & 0xffffffff, k[3] & 0xffffffff);
13446 if (TARGET_MINIMAL_TOC)
13447 fputs ("\t.long ", file);
13449 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13450 k[0] & 0xffffffff, k[1] & 0xffffffff,
13451 k[2] & 0xffffffff, k[3] & 0xffffffff);
13452 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
13453 k[0] & 0xffffffff, k[1] & 0xffffffff,
13454 k[2] & 0xffffffff, k[3] & 0xffffffff);
13458 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
13460 REAL_VALUE_TYPE rv;
13463 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13464 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
13468 if (TARGET_MINIMAL_TOC)
13469 fputs (DOUBLE_INT_ASM_OP, file);
13471 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13472 k[0] & 0xffffffff, k[1] & 0xffffffff);
13473 fprintf (file, "0x%lx%08lx\n",
13474 k[0] & 0xffffffff, k[1] & 0xffffffff);
13479 if (TARGET_MINIMAL_TOC)
13480 fputs ("\t.long ", file);
13482 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13483 k[0] & 0xffffffff, k[1] & 0xffffffff);
13484 fprintf (file, "0x%lx,0x%lx\n",
13485 k[0] & 0xffffffff, k[1] & 0xffffffff);
13489 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
13491 REAL_VALUE_TYPE rv;
13494 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13495 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
13499 if (TARGET_MINIMAL_TOC)
13500 fputs (DOUBLE_INT_ASM_OP, file);
13502 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13503 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
13508 if (TARGET_MINIMAL_TOC)
13509 fputs ("\t.long ", file);
13511 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13512 fprintf (file, "0x%lx\n", l & 0xffffffff);
13516 else if (GET_MODE (x) == VOIDmode
13517 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
13519 unsigned HOST_WIDE_INT low;
13520 HOST_WIDE_INT high;
13522 if (GET_CODE (x) == CONST_DOUBLE)
13524 low = CONST_DOUBLE_LOW (x);
13525 high = CONST_DOUBLE_HIGH (x);
13528 #if HOST_BITS_PER_WIDE_INT == 32
13531 high = (low & 0x80000000) ? ~0 : 0;
13535 low = INTVAL (x) & 0xffffffff;
13536 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
13540 /* TOC entries are always Pmode-sized, but since this
13541 is a bigendian machine then if we're putting smaller
13542 integer constants in the TOC we have to pad them.
13543 (This is still a win over putting the constants in
13544 a separate constant pool, because then we'd have
13545 to have both a TOC entry _and_ the actual constant.)
13547 For a 32-bit target, CONST_INT values are loaded and shifted
13548 entirely within `low' and can be stored in one TOC entry. */
13550 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
13551 abort ();/* It would be easy to make this work, but it doesn't now. */
13553 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
13555 #if HOST_BITS_PER_WIDE_INT == 32
13556 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
13557 POINTER_SIZE, &low, &high, 0);
13560 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
13561 high = (HOST_WIDE_INT) low >> 32;
13568 if (TARGET_MINIMAL_TOC)
13569 fputs (DOUBLE_INT_ASM_OP, file);
13571 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13572 (long) high & 0xffffffff, (long) low & 0xffffffff);
13573 fprintf (file, "0x%lx%08lx\n",
13574 (long) high & 0xffffffff, (long) low & 0xffffffff);
13579 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
13581 if (TARGET_MINIMAL_TOC)
13582 fputs ("\t.long ", file);
13584 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13585 (long) high & 0xffffffff, (long) low & 0xffffffff);
13586 fprintf (file, "0x%lx,0x%lx\n",
13587 (long) high & 0xffffffff, (long) low & 0xffffffff);
13591 if (TARGET_MINIMAL_TOC)
13592 fputs ("\t.long ", file);
13594 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
13595 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
13601 if (GET_CODE (x) == CONST)
13603 if (GET_CODE (XEXP (x, 0)) != PLUS)
13606 base = XEXP (XEXP (x, 0), 0);
13607 offset = INTVAL (XEXP (XEXP (x, 0), 1));
13610 if (GET_CODE (base) == SYMBOL_REF)
13611 name = XSTR (base, 0);
13612 else if (GET_CODE (base) == LABEL_REF)
13613 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
13614 else if (GET_CODE (base) == CODE_LABEL)
13615 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
13619 real_name = (*targetm.strip_name_encoding) (name);
13620 if (TARGET_MINIMAL_TOC)
13621 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
13624 fprintf (file, "\t.tc %s", real_name);
13627 fprintf (file, ".N%d", - offset);
13629 fprintf (file, ".P%d", offset);
13631 fputs ("[TC],", file);
13634 /* Currently C++ toc references to vtables can be emitted before it
13635 is decided whether the vtable is public or private. If this is
13636 the case, then the linker will eventually complain that there is
13637 a TOC reference to an unknown section. Thus, for vtables only,
13638 we emit the TOC reference to reference the symbol and not the
13640 if (VTABLE_NAME_P (name))
13642 RS6000_OUTPUT_BASENAME (file, name);
13644 fprintf (file, "%d", offset);
13645 else if (offset > 0)
13646 fprintf (file, "+%d", offset);
13649 output_addr_const (file, x);
13653 /* Output an assembler pseudo-op to write an ASCII string of N characters
13654 starting at P to FILE.
13656 On the RS/6000, we have to do this using the .byte operation and
13657 write out special characters outside the quoted string.
13658 Also, the assembler is broken; very long strings are truncated,
13659 so we must artificially break them up early. */
13662 output_ascii (FILE *file, const char *p, int n)
13665 int i, count_string;
13666 const char *for_string = "\t.byte \"";
13667 const char *for_decimal = "\t.byte ";
13668 const char *to_close = NULL;
13671 for (i = 0; i < n; i++)
13674 if (c >= ' ' && c < 0177)
13677 fputs (for_string, file);
13680 /* Write two quotes to get one. */
13688 for_decimal = "\"\n\t.byte ";
13692 if (count_string >= 512)
13694 fputs (to_close, file);
13696 for_string = "\t.byte \"";
13697 for_decimal = "\t.byte ";
13705 fputs (for_decimal, file);
13706 fprintf (file, "%d", c);
13708 for_string = "\n\t.byte \"";
13709 for_decimal = ", ";
13715 /* Now close the string if we have written one. Then end the line. */
13717 fputs (to_close, file);
13720 /* Generate a unique section name for FILENAME for a section type
13721 represented by SECTION_DESC. Output goes into BUF.
13723 SECTION_DESC can be any string, as long as it is different for each
13724 possible section type.
13726 We name the section in the same manner as xlc. The name begins with an
13727 underscore followed by the filename (after stripping any leading directory
13728 names) with the last period replaced by the string SECTION_DESC. If
13729 FILENAME does not contain a period, SECTION_DESC is appended to the end of
13733 rs6000_gen_section_name (char **buf, const char *filename,
13734 const char *section_desc)
13736 const char *q, *after_last_slash, *last_period = 0;
13740 after_last_slash = filename;
13741 for (q = filename; *q; q++)
13744 after_last_slash = q + 1;
13745 else if (*q == '.')
13749 len = strlen (after_last_slash) + strlen (section_desc) + 2;
13750 *buf = (char *) xmalloc (len);
13755 for (q = after_last_slash; *q; q++)
13757 if (q == last_period)
13759 strcpy (p, section_desc);
13760 p += strlen (section_desc);
13764 else if (ISALNUM (*q))
13768 if (last_period == 0)
13769 strcpy (p, section_desc);
13774 /* Emit profile function. */
13777 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
13779 if (TARGET_PROFILE_KERNEL)
13782 if (DEFAULT_ABI == ABI_AIX)
13784 #ifndef NO_PROFILE_COUNTERS
13785 # define NO_PROFILE_COUNTERS 0
13787 if (NO_PROFILE_COUNTERS)
13788 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
13792 const char *label_name;
13795 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13796 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
13797 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
13799 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
13803 else if (DEFAULT_ABI == ABI_DARWIN)
13805 const char *mcount_name = RS6000_MCOUNT;
13806 int caller_addr_regno = LINK_REGISTER_REGNUM;
13808 /* Be conservative and always set this, at least for now. */
13809 current_function_uses_pic_offset_table = 1;
13812 /* For PIC code, set up a stub and collect the caller's address
13813 from r0, which is where the prologue puts it. */
13814 if (MACHOPIC_INDIRECT)
13816 mcount_name = machopic_stub_name (mcount_name);
13817 if (current_function_uses_pic_offset_table)
13818 caller_addr_regno = 0;
13821 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
13823 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
13827 /* Write function profiler code. */
13830 output_function_profiler (FILE *file, int labelno)
13835 switch (DEFAULT_ABI)
13844 warning ("no profiling of 64-bit code for this ABI");
13847 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13848 fprintf (file, "\tmflr %s\n", reg_names[0]);
13851 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
13852 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13853 reg_names[0], save_lr, reg_names[1]);
13854 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
13855 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
13856 assemble_name (file, buf);
13857 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
13859 else if (flag_pic > 1)
13861 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13862 reg_names[0], save_lr, reg_names[1]);
13863 /* Now, we need to get the address of the label. */
13864 fputs ("\tbl 1f\n\t.long ", file);
13865 assemble_name (file, buf);
13866 fputs ("-.\n1:", file);
13867 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
13868 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
13869 reg_names[0], reg_names[11]);
13870 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
13871 reg_names[0], reg_names[0], reg_names[11]);
13875 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
13876 assemble_name (file, buf);
13877 fputs ("@ha\n", file);
13878 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13879 reg_names[0], save_lr, reg_names[1]);
13880 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
13881 assemble_name (file, buf);
13882 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
13885 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
13886 fprintf (file, "\tbl %s%s\n",
13887 RS6000_MCOUNT, flag_pic ? "@plt" : "");
13892 if (!TARGET_PROFILE_KERNEL)
13894 /* Don't do anything, done in output_profile_hook (). */
13901 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
13902 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
13904 if (current_function_needs_context)
13906 asm_fprintf (file, "\tstd %s,24(%s)\n",
13907 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13908 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13909 asm_fprintf (file, "\tld %s,24(%s)\n",
13910 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13913 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13921 rs6000_use_dfa_pipeline_interface (void)
13926 /* Power4 load update and store update instructions are cracked into a
13927 load or store and an integer insn which are executed in the same cycle.
13928 Branches have their own dispatch slot which does not count against the
13929 GCC issue rate, but it changes the program flow so there are no other
13930 instructions to issue in this cycle. */
13933 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
13934 int verbose ATTRIBUTE_UNUSED,
13935 rtx insn, int more)
13937 if (GET_CODE (PATTERN (insn)) == USE
13938 || GET_CODE (PATTERN (insn)) == CLOBBER)
13941 if (rs6000_sched_groups)
13943 if (is_microcoded_insn (insn))
13945 else if (is_cracked_insn (insn))
13946 return more > 2 ? more - 2 : 0;
13952 /* Adjust the cost of a scheduling dependency. Return the new cost of
13953 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
13956 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED,
13959 if (! recog_memoized (insn))
13962 if (REG_NOTE_KIND (link) != 0)
13965 if (REG_NOTE_KIND (link) == 0)
13967 /* Data dependency; DEP_INSN writes a register that INSN reads
13968 some cycles later. */
13969 switch (get_attr_type (insn))
13972 /* Tell the first scheduling pass about the latency between
13973 a mtctr and bctr (and mtlr and br/blr). The first
13974 scheduling pass will not know about this latency since
13975 the mtctr instruction, which has the latency associated
13976 to it, will be generated by reload. */
13977 return TARGET_POWER ? 5 : 4;
13979 /* Leave some extra cycles between a compare and its
13980 dependent branch, to inhibit expensive mispredicts. */
13981 if ((rs6000_cpu_attr == CPU_PPC603
13982 || rs6000_cpu_attr == CPU_PPC604
13983 || rs6000_cpu_attr == CPU_PPC604E
13984 || rs6000_cpu_attr == CPU_PPC620
13985 || rs6000_cpu_attr == CPU_PPC630
13986 || rs6000_cpu_attr == CPU_PPC750
13987 || rs6000_cpu_attr == CPU_PPC7400
13988 || rs6000_cpu_attr == CPU_PPC7450
13989 || rs6000_cpu_attr == CPU_POWER4
13990 || rs6000_cpu_attr == CPU_POWER5)
13991 && recog_memoized (dep_insn)
13992 && (INSN_CODE (dep_insn) >= 0)
13993 && (get_attr_type (dep_insn) == TYPE_CMP
13994 || get_attr_type (dep_insn) == TYPE_COMPARE
13995 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
13996 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
13997 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
13998 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
13999 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
14000 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
14005 /* Fall out to return default cost. */
14011 /* The function returns a true if INSN is microcoded.
14012 Return false otherwise. */
14015 is_microcoded_insn (rtx insn)
14017 if (!insn || !INSN_P (insn)
14018 || GET_CODE (PATTERN (insn)) == USE
14019 || GET_CODE (PATTERN (insn)) == CLOBBER)
14022 if (rs6000_sched_groups)
14024 enum attr_type type = get_attr_type (insn);
14025 if (type == TYPE_LOAD_EXT_U
14026 || type == TYPE_LOAD_EXT_UX
14027 || type == TYPE_LOAD_UX
14028 || type == TYPE_STORE_UX
14029 || type == TYPE_MFCR)
14036 /* The function returns a nonzero value if INSN can be scheduled only
14037 as the first insn in a dispatch group ("dispatch-slot restricted").
14038 In this case, the returned value indicates how many dispatch slots
14039 the insn occupies (at the beginning of the group).
14040 Return 0 otherwise. */
14043 is_dispatch_slot_restricted (rtx insn)
14045 enum attr_type type;
14047 if (!rs6000_sched_groups)
14051 || insn == NULL_RTX
14052 || GET_CODE (insn) == NOTE
14053 || GET_CODE (PATTERN (insn)) == USE
14054 || GET_CODE (PATTERN (insn)) == CLOBBER)
14057 type = get_attr_type (insn);
14064 case TYPE_DELAYED_CR:
14065 case TYPE_CR_LOGICAL:
14073 if (rs6000_cpu == PROCESSOR_POWER5
14074 && is_cracked_insn (insn))
14080 /* The function returns true if INSN is cracked into 2 instructions
14081 by the processor (and therefore occupies 2 issue slots). */
14084 is_cracked_insn (rtx insn)
14086 if (!insn || !INSN_P (insn)
14087 || GET_CODE (PATTERN (insn)) == USE
14088 || GET_CODE (PATTERN (insn)) == CLOBBER)
14091 if (rs6000_sched_groups)
14093 enum attr_type type = get_attr_type (insn);
14094 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
14095 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
14096 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
14097 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
14098 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
14099 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
14100 || type == TYPE_IDIV || type == TYPE_LDIV
14101 || type == TYPE_INSERT_WORD)
14108 /* The function returns true if INSN can be issued only from
14109 the branch slot. */
14112 is_branch_slot_insn (rtx insn)
14114 if (!insn || !INSN_P (insn)
14115 || GET_CODE (PATTERN (insn)) == USE
14116 || GET_CODE (PATTERN (insn)) == CLOBBER)
14119 if (rs6000_sched_groups)
14121 enum attr_type type = get_attr_type (insn);
14122 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
14130 /* A C statement (sans semicolon) to update the integer scheduling
14131 priority INSN_PRIORITY (INSN). Increase the priority to execute the
14132 INSN earlier, reduce the priority to execute INSN later. Do not
14133 define this macro if you do not need to adjust the scheduling
14134 priorities of insns. */
14137 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
14139 /* On machines (like the 750) which have asymmetric integer units,
14140 where one integer unit can do multiply and divides and the other
14141 can't, reduce the priority of multiply/divide so it is scheduled
14142 before other integer operations. */
14145 if (! INSN_P (insn))
14148 if (GET_CODE (PATTERN (insn)) == USE)
14151 switch (rs6000_cpu_attr) {
14153 switch (get_attr_type (insn))
14160 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
14161 priority, priority);
14162 if (priority >= 0 && priority < 0x01000000)
14169 if (is_dispatch_slot_restricted (insn)
14170 && reload_completed
14171 && current_sched_info->sched_max_insns_priority
14172 && rs6000_sched_restricted_insns_priority)
14175 /* Prioritize insns that can be dispatched only in the first dispatch slot. */
14176 if (rs6000_sched_restricted_insns_priority == 1)
14177 /* Attach highest priority to insn. This means that in
14178 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
14179 precede 'priority' (critical path) considerations. */
14180 return current_sched_info->sched_max_insns_priority;
14181 else if (rs6000_sched_restricted_insns_priority == 2)
14182 /* Increase priority of insn by a minimal amount. This means that in
14183 haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations
14184 precede dispatch-slot restriction considerations. */
14185 return (priority + 1);
14191 /* Return how many instructions the machine can issue per cycle. */
14194 rs6000_issue_rate (void)
14196 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
14197 if (!reload_completed)
14200 switch (rs6000_cpu_attr) {
14201 case CPU_RIOS1: /* ? */
14203 case CPU_PPC601: /* ? */
14226 /* Return how many instructions to look ahead for better insn
14230 rs6000_use_sched_lookahead (void)
14232 if (rs6000_cpu_attr == CPU_PPC8540)
14237 /* Determine is PAT refers to memory. */
14240 is_mem_ref (rtx pat)
14246 if (GET_CODE (pat) == MEM)
14249 /* Recursively process the pattern. */
14250 fmt = GET_RTX_FORMAT (GET_CODE (pat));
14252 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
14255 ret |= is_mem_ref (XEXP (pat, i));
14256 else if (fmt[i] == 'E')
14257 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
14258 ret |= is_mem_ref (XVECEXP (pat, i, j));
14264 /* Determine if PAT is a PATTERN of a load insn. */
14267 is_load_insn1 (rtx pat)
14269 if (!pat || pat == NULL_RTX)
14272 if (GET_CODE (pat) == SET)
14273 return is_mem_ref (SET_SRC (pat));
14275 if (GET_CODE (pat) == PARALLEL)
14279 for (i = 0; i < XVECLEN (pat, 0); i++)
14280 if (is_load_insn1 (XVECEXP (pat, 0, i)))
14287 /* Determine if INSN loads from memory. */
14290 is_load_insn (rtx insn)
14292 if (!insn || !INSN_P (insn))
14295 if (GET_CODE (insn) == CALL_INSN)
14298 return is_load_insn1 (PATTERN (insn));
14301 /* Determine if PAT is a PATTERN of a store insn. */
14304 is_store_insn1 (rtx pat)
14306 if (!pat || pat == NULL_RTX)
14309 if (GET_CODE (pat) == SET)
14310 return is_mem_ref (SET_DEST (pat));
14312 if (GET_CODE (pat) == PARALLEL)
14316 for (i = 0; i < XVECLEN (pat, 0); i++)
14317 if (is_store_insn1 (XVECEXP (pat, 0, i)))
14324 /* Determine if INSN stores to memory. */
14327 is_store_insn (rtx insn)
14329 if (!insn || !INSN_P (insn))
14332 return is_store_insn1 (PATTERN (insn));
14335 /* Returns whether the dependence between INSN and NEXT is considered
14336 costly by the given target. */
14339 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distance)
14341 /* If the flag is not enbled - no dependence is considered costly;
14342 allow all dependent insns in the same group.
14343 This is the most aggressive option. */
14344 if (rs6000_sched_costly_dep == no_dep_costly)
14347 /* If the flag is set to 1 - a dependence is always considered costly;
14348 do not allow dependent instructions in the same group.
14349 This is the most conservative option. */
14350 if (rs6000_sched_costly_dep == all_deps_costly)
14353 if (rs6000_sched_costly_dep == store_to_load_dep_costly
14354 && is_load_insn (next)
14355 && is_store_insn (insn))
14356 /* Prevent load after store in the same group. */
14359 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
14360 && is_load_insn (next)
14361 && is_store_insn (insn)
14362 && (!link || (int) REG_NOTE_KIND (link) == 0))
14363 /* Prevent load after store in the same group if it is a true dependence. */
14366 /* The flag is set to X; dependences with latency >= X are considered costly,
14367 and will not be scheduled in the same group. */
14368 if (rs6000_sched_costly_dep <= max_dep_latency
14369 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
14375 /* Return the next insn after INSN that is found before TAIL is reached,
14376 skipping any "non-active" insns - insns that will not actually occupy
14377 an issue slot. Return NULL_RTX if such an insn is not found. */
14380 get_next_active_insn (rtx insn, rtx tail)
14384 if (!insn || insn == tail)
14387 next_insn = NEXT_INSN (insn);
14390 && next_insn != tail
14391 && (GET_CODE(next_insn) == NOTE
14392 || GET_CODE (PATTERN (next_insn)) == USE
14393 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
14395 next_insn = NEXT_INSN (next_insn);
14398 if (!next_insn || next_insn == tail)
14404 /* Return whether the presence of INSN causes a dispatch group termination
14405 of group WHICH_GROUP.
14407 If WHICH_GROUP == current_group, this function will return true if INSN
14408 causes the termination of the current group (i.e, the dispatch group to
14409 which INSN belongs). This means that INSN will be the last insn in the
14410 group it belongs to.
14412 If WHICH_GROUP == previous_group, this function will return true if INSN
14413 causes the termination of the previous group (i.e, the dispatch group that
14414 precedes the group to which INSN belongs). This means that INSN will be
14415 the first insn in the group it belongs to). */
14418 insn_terminates_group_p (rtx insn, enum group_termination which_group)
14420 enum attr_type type;
14425 type = get_attr_type (insn);
14427 if (is_microcoded_insn (insn))
14430 if (which_group == current_group)
14432 if (is_branch_slot_insn (insn))
14436 else if (which_group == previous_group)
14438 if (is_dispatch_slot_restricted (insn))
14446 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
14447 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
14450 is_costly_group (rtx *group_insns, rtx next_insn)
14455 int issue_rate = rs6000_issue_rate ();
14457 for (i = 0; i < issue_rate; i++)
14459 rtx insn = group_insns[i];
14462 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
14464 rtx next = XEXP (link, 0);
14465 if (next == next_insn)
14467 cost = insn_cost (insn, link, next_insn);
14468 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
14477 /* Utility of the function redefine_groups.
14478 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
14479 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
14480 to keep it "far" (in a separate group) from GROUP_INSNS, following
14481 one of the following schemes, depending on the value of the flag
14482 -minsert_sched_nops = X:
14483 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
14484 in order to force NEXT_INSN into a separate group.
14485 (2) X < sched_finish_regroup_exact: insert exactly X nops.
14486 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
14487 insertion (has a group just ended, how many vacant issue slots remain in the
14488 last group, and how many dispatch groups were encountered so far). */
14491 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn,
14492 bool *group_end, int can_issue_more, int *group_count)
14496 int issue_rate = rs6000_issue_rate ();
14497 bool end = *group_end;
14500 if (next_insn == NULL_RTX)
14501 return can_issue_more;
14503 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
14504 return can_issue_more;
14506 force = is_costly_group (group_insns, next_insn);
14508 return can_issue_more;
14510 if (sched_verbose > 6)
14511 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
14512 *group_count ,can_issue_more);
14514 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
14517 can_issue_more = 0;
14519 /* Since only a branch can be issued in the last issue_slot, it is
14520 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
14521 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
14522 in this case the last nop will start a new group and the branch will be
14523 forced to the new group. */
14524 if (can_issue_more && !is_branch_slot_insn (next_insn))
14527 while (can_issue_more > 0)
14530 emit_insn_before (nop, next_insn);
14538 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
14540 int n_nops = rs6000_sched_insert_nops;
14542 /* Nops can't be issued from the branch slot, so the effective
14543 issue_rate for nops is 'issue_rate - 1'. */
14544 if (can_issue_more == 0)
14545 can_issue_more = issue_rate;
14547 if (can_issue_more == 0)
14549 can_issue_more = issue_rate - 1;
14552 for (i = 0; i < issue_rate; i++)
14554 group_insns[i] = 0;
14561 emit_insn_before (nop, next_insn);
14562 if (can_issue_more == issue_rate - 1) /* new group begins */
14565 if (can_issue_more == 0)
14567 can_issue_more = issue_rate - 1;
14570 for (i = 0; i < issue_rate; i++)
14572 group_insns[i] = 0;
14578 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
14581 *group_end = /* Is next_insn going to start a new group? */
14583 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14584 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14585 || (can_issue_more < issue_rate &&
14586 insn_terminates_group_p (next_insn, previous_group)));
14587 if (*group_end && end)
14590 if (sched_verbose > 6)
14591 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
14592 *group_count, can_issue_more);
14593 return can_issue_more;
14596 return can_issue_more;
14599 /* This function tries to synch the dispatch groups that the compiler "sees"
14600 with the dispatch groups that the processor dispatcher is expected to
14601 form in practice. It tries to achieve this synchronization by forcing the
14602 estimated processor grouping on the compiler (as opposed to the function
14603 'pad_goups' which tries to force the scheduler's grouping on the processor).
14605 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
14606 examines the (estimated) dispatch groups that will be formed by the processor
14607 dispatcher. It marks these group boundaries to reflect the estimated
14608 processor grouping, overriding the grouping that the scheduler had marked.
14609 Depending on the value of the flag '-minsert-sched-nops' this function can
14610 force certain insns into separate groups or force a certain distance between
14611 them by inserting nops, for example, if there exists a "costly dependence"
14614 The function estimates the group boundaries that the processor will form as
14615 folllows: It keeps track of how many vacant issue slots are available after
14616 each insn. A subsequent insn will start a new group if one of the following
14618 - no more vacant issue slots remain in the current dispatch group.
14619 - only the last issue slot, which is the branch slot, is vacant, but the next
14620 insn is not a branch.
14621 - only the last 2 or less issue slots, including the branch slot, are vacant,
14622 which means that a cracked insn (which occupies two issue slots) can't be
14623 issued in this group.
14624 - less than 'issue_rate' slots are vacant, and the next insn always needs to
14625 start a new group. */
14628 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14630 rtx insn, next_insn;
14632 int can_issue_more;
14635 int group_count = 0;
14639 issue_rate = rs6000_issue_rate ();
14640 group_insns = alloca (issue_rate * sizeof (rtx));
14641 for (i = 0; i < issue_rate; i++)
14643 group_insns[i] = 0;
14645 can_issue_more = issue_rate;
14647 insn = get_next_active_insn (prev_head_insn, tail);
14650 while (insn != NULL_RTX)
14652 slot = (issue_rate - can_issue_more);
14653 group_insns[slot] = insn;
14655 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14656 if (insn_terminates_group_p (insn, current_group))
14657 can_issue_more = 0;
14659 next_insn = get_next_active_insn (insn, tail);
14660 if (next_insn == NULL_RTX)
14661 return group_count + 1;
14663 group_end = /* Is next_insn going to start a new group? */
14664 (can_issue_more == 0
14665 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14666 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14667 || (can_issue_more < issue_rate &&
14668 insn_terminates_group_p (next_insn, previous_group)));
14670 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
14671 next_insn, &group_end, can_issue_more, &group_count);
14676 can_issue_more = 0;
14677 for (i = 0; i < issue_rate; i++)
14679 group_insns[i] = 0;
14683 if (GET_MODE (next_insn) == TImode && can_issue_more)
14684 PUT_MODE(next_insn, VOIDmode);
14685 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
14686 PUT_MODE (next_insn, TImode);
14689 if (can_issue_more == 0)
14690 can_issue_more = issue_rate;
14693 return group_count;
14696 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
14697 dispatch group boundaries that the scheduler had marked. Pad with nops
14698 any dispatch groups which have vacant issue slots, in order to force the
14699 scheduler's grouping on the processor dispatcher. The function
14700 returns the number of dispatch groups found. */
14703 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14705 rtx insn, next_insn;
14708 int can_issue_more;
14710 int group_count = 0;
14712 /* Initialize issue_rate. */
14713 issue_rate = rs6000_issue_rate ();
14714 can_issue_more = issue_rate;
14716 insn = get_next_active_insn (prev_head_insn, tail);
14717 next_insn = get_next_active_insn (insn, tail);
14719 while (insn != NULL_RTX)
14722 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14724 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
14726 if (next_insn == NULL_RTX)
14731 /* If the scheduler had marked group termination at this location
14732 (between insn and next_indn), and neither insn nor next_insn will
14733 force group termination, pad the group with nops to force group
14736 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
14737 && !insn_terminates_group_p (insn, current_group)
14738 && !insn_terminates_group_p (next_insn, previous_group))
14740 if (!is_branch_slot_insn(next_insn))
14743 while (can_issue_more)
14746 emit_insn_before (nop, next_insn);
14751 can_issue_more = issue_rate;
14756 next_insn = get_next_active_insn (insn, tail);
14759 return group_count;
14762 /* The following function is called at the end of scheduling BB.
14763 After reload, it inserts nops at insn group bundling. */
14766 rs6000_sched_finish (FILE *dump, int sched_verbose)
14771 fprintf (dump, "=== Finishing schedule.\n");
14773 if (reload_completed && rs6000_sched_groups)
14775 if (rs6000_sched_insert_nops == sched_finish_none)
14778 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
14779 n_groups = pad_groups (dump, sched_verbose,
14780 current_sched_info->prev_head,
14781 current_sched_info->next_tail);
14783 n_groups = redefine_groups (dump, sched_verbose,
14784 current_sched_info->prev_head,
14785 current_sched_info->next_tail);
14787 if (sched_verbose >= 6)
14789 fprintf (dump, "ngroups = %d\n", n_groups);
14790 print_rtl (dump, current_sched_info->prev_head);
14791 fprintf (dump, "Done finish_sched\n");
14796 /* Length in units of the trampoline for entering a nested function. */
14799 rs6000_trampoline_size (void)
14803 switch (DEFAULT_ABI)
14809 ret = (TARGET_32BIT) ? 12 : 24;
14814 ret = (TARGET_32BIT) ? 40 : 48;
14821 /* Emit RTL insns to initialize the variable parts of a trampoline.
14822 FNADDR is an RTX for the address of the function's pure code.
14823 CXT is an RTX for the static chain value for the function. */
14826 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
14828 enum machine_mode pmode = Pmode;
14829 int regsize = (TARGET_32BIT) ? 4 : 8;
14830 rtx ctx_reg = force_reg (pmode, cxt);
14832 switch (DEFAULT_ABI)
14837 /* Macros to shorten the code expansions below. */
14838 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
14839 #define MEM_PLUS(addr,offset) \
14840 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
14842 /* Under AIX, just build the 3 word function descriptor */
14845 rtx fn_reg = gen_reg_rtx (pmode);
14846 rtx toc_reg = gen_reg_rtx (pmode);
14847 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
14848 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
14849 emit_move_insn (MEM_DEREF (addr), fn_reg);
14850 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
14851 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
14855 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
14858 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
14859 FALSE, VOIDmode, 4,
14861 GEN_INT (rs6000_trampoline_size ()), SImode,
14871 /* Table of valid machine attributes. */
14873 const struct attribute_spec rs6000_attribute_table[] =
14875 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
14876 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
14877 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
14878 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
14879 { NULL, 0, 0, false, false, false, NULL }
14882 /* Handle the "altivec" attribute. The attribute may have
14883 arguments as follows:
14885 __attribute__((altivec(vector__)))
14886 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
14887 __attribute__((altivec(bool__))) (always followed by 'unsigned')
14889 and may appear more than once (e.g., 'vector bool char') in a
14890 given declaration. */
14893 rs6000_handle_altivec_attribute (tree *node, tree name, tree args,
14894 int flags ATTRIBUTE_UNUSED,
14895 bool *no_add_attrs)
14897 tree type = *node, result = NULL_TREE;
14898 enum machine_mode mode;
14901 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
14902 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
14903 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
14906 while (POINTER_TYPE_P (type)
14907 || TREE_CODE (type) == FUNCTION_TYPE
14908 || TREE_CODE (type) == METHOD_TYPE
14909 || TREE_CODE (type) == ARRAY_TYPE)
14910 type = TREE_TYPE (type);
14912 mode = TYPE_MODE (type);
14914 if (rs6000_warn_altivec_long
14915 && (type == long_unsigned_type_node || type == long_integer_type_node))
14916 warning ("use of 'long' in AltiVec types is deprecated; use 'int'");
14918 switch (altivec_type)
14921 unsigned_p = TYPE_UNSIGNED (type);
14925 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
14928 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
14931 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
14933 case SFmode: result = V4SF_type_node; break;
14934 /* If the user says 'vector int bool', we may be handed the 'bool'
14935 attribute _before_ the 'vector' attribute, and so select the proper
14936 type in the 'b' case below. */
14937 case V4SImode: case V8HImode: case V16QImode: result = type;
14944 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
14945 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
14946 case QImode: case V16QImode: result = bool_V16QI_type_node;
14953 case V8HImode: result = pixel_V8HI_type_node;
14959 *no_add_attrs = true; /* No need to hang on to the attribute. */
14962 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
14964 *node = reconstruct_complex_type (*node, result);
14969 /* AltiVec defines four built-in scalar types that serve as vector
14970 elements; we must teach the compiler how to mangle them. */
14972 static const char *
14973 rs6000_mangle_fundamental_type (tree type)
14975 if (type == bool_char_type_node) return "U6__boolc";
14976 if (type == bool_short_type_node) return "U6__bools";
14977 if (type == pixel_type_node) return "u7__pixel";
14978 if (type == bool_int_type_node) return "U6__booli";
14980 /* For all other types, use normal C++ mangling. */
14984 /* Handle a "longcall" or "shortcall" attribute; arguments as in
14985 struct attribute_spec.handler. */
14988 rs6000_handle_longcall_attribute (tree *node, tree name,
14989 tree args ATTRIBUTE_UNUSED,
14990 int flags ATTRIBUTE_UNUSED,
14991 bool *no_add_attrs)
14993 if (TREE_CODE (*node) != FUNCTION_TYPE
14994 && TREE_CODE (*node) != FIELD_DECL
14995 && TREE_CODE (*node) != TYPE_DECL)
14997 warning ("`%s' attribute only applies to functions",
14998 IDENTIFIER_POINTER (name));
14999 *no_add_attrs = true;
15005 /* Set longcall attributes on all functions declared when
15006 rs6000_default_long_calls is true. */
15008 rs6000_set_default_type_attributes (tree type)
15010 if (rs6000_default_long_calls
15011 && (TREE_CODE (type) == FUNCTION_TYPE
15012 || TREE_CODE (type) == METHOD_TYPE))
15013 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
15015 TYPE_ATTRIBUTES (type));
15018 /* Return a reference suitable for calling a function with the
15019 longcall attribute. */
15022 rs6000_longcall_ref (rtx call_ref)
15024 const char *call_name;
15027 if (GET_CODE (call_ref) != SYMBOL_REF)
15030 /* System V adds '.' to the internal name, so skip them. */
15031 call_name = XSTR (call_ref, 0);
15032 if (*call_name == '.')
15034 while (*call_name == '.')
15037 node = get_identifier (call_name);
15038 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
15041 return force_reg (Pmode, call_ref);
15044 #ifdef USING_ELFOS_H
15046 /* A C statement or statements to switch to the appropriate section
15047 for output of RTX in mode MODE. You can assume that RTX is some
15048 kind of constant in RTL. The argument MODE is redundant except in
15049 the case of a `const_int' rtx. Select the section by calling
15050 `text_section' or one of the alternatives for other sections.
15052 Do not define this macro if you put all constants in the read-only
15056 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
15057 unsigned HOST_WIDE_INT align)
15059 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15062 default_elf_select_rtx_section (mode, x, align);
15065 /* A C statement or statements to switch to the appropriate
15066 section for output of DECL. DECL is either a `VAR_DECL' node
15067 or a constant of some sort. RELOC indicates whether forming
15068 the initial value of DECL requires link-time relocations. */
15071 rs6000_elf_select_section (tree decl, int reloc,
15072 unsigned HOST_WIDE_INT align)
15074 /* Pretend that we're always building for a shared library when
15075 ABI_AIX, because otherwise we end up with dynamic relocations
15076 in read-only sections. This happens for function pointers,
15077 references to vtables in typeinfo, and probably other cases. */
15078 default_elf_select_section_1 (decl, reloc, align,
15079 flag_pic || DEFAULT_ABI == ABI_AIX);
15082 /* A C statement to build up a unique section name, expressed as a
15083 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
15084 RELOC indicates whether the initial value of EXP requires
15085 link-time relocations. If you do not define this macro, GCC will use
15086 the symbol name prefixed by `.' as the section name. Note - this
15087 macro can now be called for uninitialized data items as well as
15088 initialized data and functions. */
15091 rs6000_elf_unique_section (tree decl, int reloc)
15093 /* As above, pretend that we're always building for a shared library
15094 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
15095 default_unique_section_1 (decl, reloc,
15096 flag_pic || DEFAULT_ABI == ABI_AIX);
15099 /* For a SYMBOL_REF, set generic flags and then perform some
15100 target-specific processing.
15102 When the AIX ABI is requested on a non-AIX system, replace the
15103 function name with the real name (with a leading .) rather than the
15104 function descriptor name. This saves a lot of overriding code to
15105 read the prefixes. */
15108 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
15110 default_encode_section_info (decl, rtl, first);
15113 && TREE_CODE (decl) == FUNCTION_DECL
15115 && DEFAULT_ABI == ABI_AIX)
15117 rtx sym_ref = XEXP (rtl, 0);
15118 size_t len = strlen (XSTR (sym_ref, 0));
15119 char *str = alloca (len + 2);
15121 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
15122 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
15127 rs6000_elf_in_small_data_p (tree decl)
15129 if (rs6000_sdata == SDATA_NONE)
15132 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
15134 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
15135 if (strcmp (section, ".sdata") == 0
15136 || strcmp (section, ".sdata2") == 0
15137 || strcmp (section, ".sbss") == 0
15138 || strcmp (section, ".sbss2") == 0
15139 || strcmp (section, ".PPC.EMB.sdata0") == 0
15140 || strcmp (section, ".PPC.EMB.sbss0") == 0)
15145 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
15148 && (unsigned HOST_WIDE_INT) size <= g_switch_value
15149 /* If it's not public, and we're not going to reference it there,
15150 there's no need to put it in the small data section. */
15151 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
15158 #endif /* USING_ELFOS_H */
15161 /* Return a REG that occurs in ADDR with coefficient 1.
15162 ADDR can be effectively incremented by incrementing REG.
15164 r0 is special and we must not select it as an address
15165 register by this routine since our caller will try to
15166 increment the returned register via an "la" instruction. */
15169 find_addr_reg (rtx addr)
15171 while (GET_CODE (addr) == PLUS)
15173 if (GET_CODE (XEXP (addr, 0)) == REG
15174 && REGNO (XEXP (addr, 0)) != 0)
15175 addr = XEXP (addr, 0);
15176 else if (GET_CODE (XEXP (addr, 1)) == REG
15177 && REGNO (XEXP (addr, 1)) != 0)
15178 addr = XEXP (addr, 1);
15179 else if (CONSTANT_P (XEXP (addr, 0)))
15180 addr = XEXP (addr, 1);
15181 else if (CONSTANT_P (XEXP (addr, 1)))
15182 addr = XEXP (addr, 0);
15186 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
15192 rs6000_fatal_bad_address (rtx op)
15194 fatal_insn ("bad address", op);
15200 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
15201 reference and a constant. */
15204 symbolic_operand (rtx op)
15206 switch (GET_CODE (op))
15213 return (GET_CODE (op) == SYMBOL_REF ||
15214 (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
15215 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
15216 && GET_CODE (XEXP (op, 1)) == CONST_INT);
15225 static tree branch_island_list = 0;
15227 /* Remember to generate a branch island for far calls to the given
15231 add_compiler_branch_island (tree label_name, tree function_name, int line_number)
15233 tree branch_island = build_tree_list (function_name, label_name);
15234 TREE_TYPE (branch_island) = build_int_2 (line_number, 0);
15235 TREE_CHAIN (branch_island) = branch_island_list;
15236 branch_island_list = branch_island;
15239 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
15240 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
15241 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
15242 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
15244 /* Generate far-jump branch islands for everything on the
15245 branch_island_list. Invoked immediately after the last instruction
15246 of the epilogue has been emitted; the branch-islands must be
15247 appended to, and contiguous with, the function body. Mach-O stubs
15248 are generated in machopic_output_stub(). */
15251 macho_branch_islands (void)
15254 tree branch_island;
15256 for (branch_island = branch_island_list;
15258 branch_island = TREE_CHAIN (branch_island))
15260 const char *label =
15261 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
15263 darwin_strip_name_encoding (
15264 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)));
15265 char name_buf[512];
15266 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
15267 if (name[0] == '*' || name[0] == '&')
15268 strcpy (name_buf, name+1);
15272 strcpy (name_buf+1, name);
15274 strcpy (tmp_buf, "\n");
15275 strcat (tmp_buf, label);
15276 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
15277 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
15278 fprintf (asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
15279 BRANCH_ISLAND_LINE_NUMBER(branch_island));
15280 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
15283 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
15284 strcat (tmp_buf, label);
15285 strcat (tmp_buf, "_pic\n");
15286 strcat (tmp_buf, label);
15287 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
15289 strcat (tmp_buf, "\taddis r11,r11,ha16(");
15290 strcat (tmp_buf, name_buf);
15291 strcat (tmp_buf, " - ");
15292 strcat (tmp_buf, label);
15293 strcat (tmp_buf, "_pic)\n");
15295 strcat (tmp_buf, "\tmtlr r0\n");
15297 strcat (tmp_buf, "\taddi r12,r11,lo16(");
15298 strcat (tmp_buf, name_buf);
15299 strcat (tmp_buf, " - ");
15300 strcat (tmp_buf, label);
15301 strcat (tmp_buf, "_pic)\n");
15303 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
15307 strcat (tmp_buf, ":\nlis r12,hi16(");
15308 strcat (tmp_buf, name_buf);
15309 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
15310 strcat (tmp_buf, name_buf);
15311 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
15313 output_asm_insn (tmp_buf, 0);
15314 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
15315 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
15316 fprintf(asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
15317 BRANCH_ISLAND_LINE_NUMBER (branch_island));
15318 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
15321 branch_island_list = 0;
15324 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
15325 already there or not. */
15328 no_previous_def (tree function_name)
15330 tree branch_island;
15331 for (branch_island = branch_island_list;
15333 branch_island = TREE_CHAIN (branch_island))
15334 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
15339 /* GET_PREV_LABEL gets the label name from the previous definition of
15343 get_prev_label (tree function_name)
15345 tree branch_island;
15346 for (branch_island = branch_island_list;
15348 branch_island = TREE_CHAIN (branch_island))
15349 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
15350 return BRANCH_ISLAND_LABEL_NAME (branch_island);
15354 /* INSN is either a function call or a millicode call. It may have an
15355 unconditional jump in its delay slot.
15357 CALL_DEST is the routine we are calling. */
15360 output_call (rtx insn, rtx *operands, int dest_operand_number, int cookie_operand_number)
15362 static char buf[256];
15363 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
15364 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
15367 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
15369 if (no_previous_def (funname))
15371 int line_number = 0;
15372 rtx label_rtx = gen_label_rtx ();
15373 char *label_buf, temp_buf[256];
15374 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
15375 CODE_LABEL_NUMBER (label_rtx));
15376 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
15377 labelname = get_identifier (label_buf);
15378 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
15380 line_number = NOTE_LINE_NUMBER (insn);
15381 add_compiler_branch_island (labelname, funname, line_number);
15384 labelname = get_prev_label (funname);
15386 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
15387 instruction will reach 'foo', otherwise link as 'bl L42'".
15388 "L42" should be a 'branch island', that will do a far jump to
15389 'foo'. Branch islands are generated in
15390 macho_branch_islands(). */
15391 sprintf (buf, "jbsr %%z%d,%.246s",
15392 dest_operand_number, IDENTIFIER_POINTER (labelname));
15395 sprintf (buf, "bl %%z%d", dest_operand_number);
15399 #endif /* TARGET_MACHO */
15401 /* Generate PIC and indirect symbol stubs. */
15404 machopic_output_stub (FILE *file, const char *symb, const char *stub)
15406 unsigned int length;
15407 char *symbol_name, *lazy_ptr_name;
15408 char *local_label_0;
15409 static int label = 0;
15411 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
15412 symb = (*targetm.strip_name_encoding) (symb);
15415 length = strlen (symb);
15416 symbol_name = alloca (length + 32);
15417 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
15419 lazy_ptr_name = alloca (length + 32);
15420 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
15423 machopic_picsymbol_stub1_section ();
15425 machopic_symbol_stub1_section ();
15426 fprintf (file, "\t.align 2\n");
15428 fprintf (file, "%s:\n", stub);
15429 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
15434 local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
15435 sprintf (local_label_0, "\"L%011d$spb\"", label);
15437 fprintf (file, "\tmflr r0\n");
15438 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
15439 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
15440 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
15441 lazy_ptr_name, local_label_0);
15442 fprintf (file, "\tmtlr r0\n");
15443 fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n",
15444 lazy_ptr_name, local_label_0);
15445 fprintf (file, "\tmtctr r12\n");
15446 fprintf (file, "\tbctr\n");
15450 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
15451 fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
15452 fprintf (file, "\tmtctr r12\n");
15453 fprintf (file, "\tbctr\n");
15456 machopic_lazy_symbol_ptr_section ();
15457 fprintf (file, "%s:\n", lazy_ptr_name);
15458 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
15459 fprintf (file, "\t.long dyld_stub_binding_helper\n");
15462 /* Legitimize PIC addresses. If the address is already
15463 position-independent, we return ORIG. Newly generated
15464 position-independent addresses go into a reg. This is REG if non
15465 zero, otherwise we allocate register(s) as necessary. */
15467 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
15470 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
15475 if (reg == NULL && ! reload_in_progress && ! reload_completed)
15476 reg = gen_reg_rtx (Pmode);
15478 if (GET_CODE (orig) == CONST)
15480 if (GET_CODE (XEXP (orig, 0)) == PLUS
15481 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
15484 if (GET_CODE (XEXP (orig, 0)) == PLUS)
15486 /* Use a different reg for the intermediate value, as
15487 it will be marked UNCHANGING. */
15488 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
15491 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
15494 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
15500 if (GET_CODE (offset) == CONST_INT)
15502 if (SMALL_INT (offset))
15503 return plus_constant (base, INTVAL (offset));
15504 else if (! reload_in_progress && ! reload_completed)
15505 offset = force_reg (Pmode, offset);
15508 rtx mem = force_const_mem (Pmode, orig);
15509 return machopic_legitimize_pic_address (mem, Pmode, reg);
15512 return gen_rtx_PLUS (Pmode, base, offset);
15515 /* Fall back on generic machopic code. */
15516 return machopic_legitimize_pic_address (orig, mode, reg);
15519 /* This is just a placeholder to make linking work without having to
15520 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
15521 ever needed for Darwin (not too likely!) this would have to get a
15522 real definition. */
15529 #endif /* TARGET_MACHO */
15532 static unsigned int
15533 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
15535 return default_section_type_flags_1 (decl, name, reloc,
15536 flag_pic || DEFAULT_ABI == ABI_AIX);
15539 /* Record an element in the table of global constructors. SYMBOL is
15540 a SYMBOL_REF of the function to be called; PRIORITY is a number
15541 between 0 and MAX_INIT_PRIORITY.
15543 This differs from default_named_section_asm_out_constructor in
15544 that we have special handling for -mrelocatable. */
15547 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
15549 const char *section = ".ctors";
15552 if (priority != DEFAULT_INIT_PRIORITY)
15554 sprintf (buf, ".ctors.%.5u",
15555 /* Invert the numbering so the linker puts us in the proper
15556 order; constructors are run from right to left, and the
15557 linker sorts in increasing order. */
15558 MAX_INIT_PRIORITY - priority);
15562 named_section_flags (section, SECTION_WRITE);
15563 assemble_align (POINTER_SIZE);
15565 if (TARGET_RELOCATABLE)
15567 fputs ("\t.long (", asm_out_file);
15568 output_addr_const (asm_out_file, symbol);
15569 fputs (")@fixup\n", asm_out_file);
15572 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15576 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
15578 const char *section = ".dtors";
15581 if (priority != DEFAULT_INIT_PRIORITY)
15583 sprintf (buf, ".dtors.%.5u",
15584 /* Invert the numbering so the linker puts us in the proper
15585 order; constructors are run from right to left, and the
15586 linker sorts in increasing order. */
15587 MAX_INIT_PRIORITY - priority);
15591 named_section_flags (section, SECTION_WRITE);
15592 assemble_align (POINTER_SIZE);
15594 if (TARGET_RELOCATABLE)
15596 fputs ("\t.long (", asm_out_file);
15597 output_addr_const (asm_out_file, symbol);
15598 fputs (")@fixup\n", asm_out_file);
15601 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15605 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
15609 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
15610 ASM_OUTPUT_LABEL (file, name);
15611 fputs (DOUBLE_INT_ASM_OP, file);
15613 assemble_name (file, name);
15614 fputs (",.TOC.@tocbase,0\n\t.previous\n\t.size\t", file);
15615 assemble_name (file, name);
15616 fputs (",24\n\t.type\t.", file);
15617 assemble_name (file, name);
15618 fputs (",@function\n", file);
15619 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
15621 fputs ("\t.globl\t.", file);
15622 assemble_name (file, name);
15625 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15627 ASM_OUTPUT_LABEL (file, name);
15631 if (TARGET_RELOCATABLE
15632 && (get_pool_size () != 0 || current_function_profile)
15637 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
15639 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
15640 fprintf (file, "\t.long ");
15641 assemble_name (file, buf);
15643 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15644 assemble_name (file, buf);
15648 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
15649 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15651 if (DEFAULT_ABI == ABI_AIX)
15653 const char *desc_name, *orig_name;
15655 orig_name = (*targetm.strip_name_encoding) (name);
15656 desc_name = orig_name;
15657 while (*desc_name == '.')
15660 if (TREE_PUBLIC (decl))
15661 fprintf (file, "\t.globl %s\n", desc_name);
15663 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
15664 fprintf (file, "%s:\n", desc_name);
15665 fprintf (file, "\t.long %s\n", orig_name);
15666 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
15667 if (DEFAULT_ABI == ABI_AIX)
15668 fputs ("\t.long 0\n", file);
15669 fprintf (file, "\t.previous\n");
15671 ASM_OUTPUT_LABEL (file, name);
15677 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
15679 fputs (GLOBAL_ASM_OP, stream);
15680 RS6000_OUTPUT_BASENAME (stream, name);
15681 putc ('\n', stream);
15685 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags)
15688 static const char * const suffix[3] = { "PR", "RO", "RW" };
15690 if (flags & SECTION_CODE)
15692 else if (flags & SECTION_WRITE)
15697 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
15698 (flags & SECTION_CODE) ? "." : "",
15699 name, suffix[smclass], flags & SECTION_ENTSIZE);
15703 rs6000_xcoff_select_section (tree decl, int reloc,
15704 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15706 if (decl_readonly_section_1 (decl, reloc, 1))
15708 if (TREE_PUBLIC (decl))
15709 read_only_data_section ();
15711 read_only_private_data_section ();
15715 if (TREE_PUBLIC (decl))
15718 private_data_section ();
15723 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
15727 /* Use select_section for private and uninitialized data. */
15728 if (!TREE_PUBLIC (decl)
15729 || DECL_COMMON (decl)
15730 || DECL_INITIAL (decl) == NULL_TREE
15731 || DECL_INITIAL (decl) == error_mark_node
15732 || (flag_zero_initialized_in_bss
15733 && initializer_zerop (DECL_INITIAL (decl))))
15736 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
15737 name = (*targetm.strip_name_encoding) (name);
15738 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
15741 /* Select section for constant in constant pool.
15743 On RS/6000, all constants are in the private read-only data area.
15744 However, if this is being placed in the TOC it must be output as a
15748 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
15749 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15751 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15754 read_only_private_data_section ();
15757 /* Remove any trailing [DS] or the like from the symbol name. */
15759 static const char *
15760 rs6000_xcoff_strip_name_encoding (const char *name)
15765 len = strlen (name);
15766 if (name[len - 1] == ']')
15767 return ggc_alloc_string (name, len - 4);
15772 /* Section attributes. AIX is always PIC. */
15774 static unsigned int
15775 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
15777 unsigned int align;
15778 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
15780 /* Align to at least UNIT size. */
15781 if (flags & SECTION_CODE)
15782 align = MIN_UNITS_PER_WORD;
15784 /* Increase alignment of large objects if not already stricter. */
15785 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
15786 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
15787 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
15789 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
15792 /* Output at beginning of assembler file.
15794 Initialize the section names for the RS/6000 at this point.
15796 Specify filename, including full path, to assembler.
15798 We want to go into the TOC section so at least one .toc will be emitted.
15799 Also, in order to output proper .bs/.es pairs, we need at least one static
15800 [RW] section emitted.
15802 Finally, declare mcount when profiling to make the assembler happy. */
15805 rs6000_xcoff_file_start (void)
15807 rs6000_gen_section_name (&xcoff_bss_section_name,
15808 main_input_filename, ".bss_");
15809 rs6000_gen_section_name (&xcoff_private_data_section_name,
15810 main_input_filename, ".rw_");
15811 rs6000_gen_section_name (&xcoff_read_only_section_name,
15812 main_input_filename, ".ro_");
15814 fputs ("\t.file\t", asm_out_file);
15815 output_quoted_string (asm_out_file, main_input_filename);
15816 fputc ('\n', asm_out_file);
15818 if (write_symbols != NO_DEBUG)
15819 private_data_section ();
15822 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
15823 rs6000_file_start ();
15826 /* Output at end of assembler file.
15827 On the RS/6000, referencing data should automatically pull in text. */
15830 rs6000_xcoff_file_end (void)
15833 fputs ("_section_.text:\n", asm_out_file);
15835 fputs (TARGET_32BIT
15836 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
15839 #endif /* TARGET_XCOFF */
15842 /* Cross-module name binding. Darwin does not support overriding
15843 functions at dynamic-link time. */
15846 rs6000_binds_local_p (tree decl)
15848 return default_binds_local_p_1 (decl, 0);
15852 /* Compute a (partial) cost for rtx X. Return true if the complete
15853 cost has been computed, and false if subexpressions should be
15854 scanned. In either case, *TOTAL contains the cost result. */
15857 rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED,
15862 /* On the RS/6000, if it is valid in the insn, it is free.
15863 So this always returns 0. */
15874 *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15875 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1))
15876 + 0x8000) >= 0x10000)
15877 && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15878 ? COSTS_N_INSNS (2)
15879 : COSTS_N_INSNS (1));
15885 *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15886 && (INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0
15887 && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15888 ? COSTS_N_INSNS (2)
15889 : COSTS_N_INSNS (1));
15895 *total = COSTS_N_INSNS (2);
15898 switch (rs6000_cpu)
15900 case PROCESSOR_RIOS1:
15901 case PROCESSOR_PPC405:
15902 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15903 ? COSTS_N_INSNS (5)
15904 : (INTVAL (XEXP (x, 1)) >= -256
15905 && INTVAL (XEXP (x, 1)) <= 255)
15906 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15909 case PROCESSOR_PPC440:
15910 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15911 ? COSTS_N_INSNS (3)
15912 : COSTS_N_INSNS (2));
15915 case PROCESSOR_RS64A:
15916 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15917 ? GET_MODE (XEXP (x, 1)) != DImode
15918 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34)
15919 : (INTVAL (XEXP (x, 1)) >= -256
15920 && INTVAL (XEXP (x, 1)) <= 255)
15921 ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12));
15924 case PROCESSOR_RIOS2:
15925 case PROCESSOR_MPCCORE:
15926 case PROCESSOR_PPC604e:
15927 *total = COSTS_N_INSNS (2);
15930 case PROCESSOR_PPC601:
15931 *total = COSTS_N_INSNS (5);
15934 case PROCESSOR_PPC603:
15935 case PROCESSOR_PPC7400:
15936 case PROCESSOR_PPC750:
15937 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15938 ? COSTS_N_INSNS (5)
15939 : (INTVAL (XEXP (x, 1)) >= -256
15940 && INTVAL (XEXP (x, 1)) <= 255)
15941 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3));
15944 case PROCESSOR_PPC7450:
15945 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15946 ? COSTS_N_INSNS (4)
15947 : COSTS_N_INSNS (3));
15950 case PROCESSOR_PPC403:
15951 case PROCESSOR_PPC604:
15952 case PROCESSOR_PPC8540:
15953 *total = COSTS_N_INSNS (4);
15956 case PROCESSOR_PPC620:
15957 case PROCESSOR_PPC630:
15958 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15959 ? GET_MODE (XEXP (x, 1)) != DImode
15960 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7)
15961 : (INTVAL (XEXP (x, 1)) >= -256
15962 && INTVAL (XEXP (x, 1)) <= 255)
15963 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15966 case PROCESSOR_POWER4:
15967 case PROCESSOR_POWER5:
15968 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15969 ? GET_MODE (XEXP (x, 1)) != DImode
15970 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)
15971 : COSTS_N_INSNS (2));
15980 if (GET_CODE (XEXP (x, 1)) == CONST_INT
15981 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
15983 *total = COSTS_N_INSNS (2);
15990 switch (rs6000_cpu)
15992 case PROCESSOR_RIOS1:
15993 *total = COSTS_N_INSNS (19);
15996 case PROCESSOR_RIOS2:
15997 *total = COSTS_N_INSNS (13);
16000 case PROCESSOR_RS64A:
16001 *total = (GET_MODE (XEXP (x, 1)) != DImode
16002 ? COSTS_N_INSNS (65)
16003 : COSTS_N_INSNS (67));
16006 case PROCESSOR_MPCCORE:
16007 *total = COSTS_N_INSNS (6);
16010 case PROCESSOR_PPC403:
16011 *total = COSTS_N_INSNS (33);
16014 case PROCESSOR_PPC405:
16015 *total = COSTS_N_INSNS (35);
16018 case PROCESSOR_PPC440:
16019 *total = COSTS_N_INSNS (34);
16022 case PROCESSOR_PPC601:
16023 *total = COSTS_N_INSNS (36);
16026 case PROCESSOR_PPC603:
16027 *total = COSTS_N_INSNS (37);
16030 case PROCESSOR_PPC604:
16031 case PROCESSOR_PPC604e:
16032 *total = COSTS_N_INSNS (20);
16035 case PROCESSOR_PPC620:
16036 case PROCESSOR_PPC630:
16037 *total = (GET_MODE (XEXP (x, 1)) != DImode
16038 ? COSTS_N_INSNS (21)
16039 : COSTS_N_INSNS (37));
16042 case PROCESSOR_PPC750:
16043 case PROCESSOR_PPC8540:
16044 case PROCESSOR_PPC7400:
16045 *total = COSTS_N_INSNS (19);
16048 case PROCESSOR_PPC7450:
16049 *total = COSTS_N_INSNS (23);
16052 case PROCESSOR_POWER4:
16053 case PROCESSOR_POWER5:
16054 *total = (GET_MODE (XEXP (x, 1)) != DImode
16055 ? COSTS_N_INSNS (18)
16056 : COSTS_N_INSNS (34));
16064 *total = COSTS_N_INSNS (4);
16068 /* MEM should be slightly more expensive than (plus (reg) (const)). */
16077 /* A C expression returning the cost of moving data from a register of class
16078 CLASS1 to one of CLASS2. */
16081 rs6000_register_move_cost (enum machine_mode mode,
16082 enum reg_class from, enum reg_class to)
16084 /* Moves from/to GENERAL_REGS. */
16085 if (reg_classes_intersect_p (to, GENERAL_REGS)
16086 || reg_classes_intersect_p (from, GENERAL_REGS))
16088 if (! reg_classes_intersect_p (to, GENERAL_REGS))
16091 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
16092 return (rs6000_memory_move_cost (mode, from, 0)
16093 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
16095 /* It's more expensive to move CR_REGS than CR0_REGS because of the shift.... */
16096 else if (from == CR_REGS)
16100 /* A move will cost one instruction per GPR moved. */
16101 return 2 * HARD_REGNO_NREGS (0, mode);
16104 /* Moving between two similar registers is just one instruction. */
16105 else if (reg_classes_intersect_p (to, from))
16106 return mode == TFmode ? 4 : 2;
16108 /* Everything else has to go through GENERAL_REGS. */
16110 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
16111 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
16114 /* A C expressions returning the cost of moving data of MODE from a register to
16118 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
16119 int in ATTRIBUTE_UNUSED)
16121 if (reg_classes_intersect_p (class, GENERAL_REGS))
16122 return 4 * HARD_REGNO_NREGS (0, mode);
16123 else if (reg_classes_intersect_p (class, FLOAT_REGS))
16124 return 4 * HARD_REGNO_NREGS (32, mode);
16125 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
16126 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
16128 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
16131 /* Return an RTX representing where to find the function value of a
16132 function returning MODE. */
16134 rs6000_complex_function_value (enum machine_mode mode)
16136 unsigned int regno;
16138 enum machine_mode inner = GET_MODE_INNER (mode);
16139 unsigned int inner_bytes = GET_MODE_SIZE (inner);
16141 if (FLOAT_MODE_P (mode))
16142 regno = FP_ARG_RETURN;
16145 regno = GP_ARG_RETURN;
16147 /* 32-bit is OK since it'll go in r3/r4. */
16148 if (TARGET_32BIT && inner_bytes >= 4)
16149 return gen_rtx_REG (mode, regno);
16152 if (inner_bytes >= 8)
16153 return gen_rtx_REG (mode, regno);
16155 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
16157 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
16158 GEN_INT (inner_bytes));
16159 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
16162 /* Define how to find the value returned by a function.
16163 VALTYPE is the data type of the value (as a tree).
16164 If the precise function being called is known, FUNC is its FUNCTION_DECL;
16165 otherwise, FUNC is 0.
16167 On the SPE, both FPs and vectors are returned in r3.
16169 On RS/6000 an integer value is in r3 and a floating-point value is in
16170 fp1, unless -msoft-float. */
16173 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
16175 enum machine_mode mode;
16176 unsigned int regno;
16178 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
16180 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
16181 return gen_rtx_PARALLEL (DImode,
16183 gen_rtx_EXPR_LIST (VOIDmode,
16184 gen_rtx_REG (SImode, GP_ARG_RETURN),
16186 gen_rtx_EXPR_LIST (VOIDmode,
16187 gen_rtx_REG (SImode,
16188 GP_ARG_RETURN + 1),
16192 if ((INTEGRAL_TYPE_P (valtype)
16193 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
16194 || POINTER_TYPE_P (valtype))
16195 mode = TARGET_32BIT ? SImode : DImode;
16197 mode = TYPE_MODE (valtype);
16199 if (TREE_CODE (valtype) == REAL_TYPE && TARGET_HARD_FLOAT && TARGET_FPRS)
16200 regno = FP_ARG_RETURN;
16201 else if (TREE_CODE (valtype) == COMPLEX_TYPE
16202 && TARGET_HARD_FLOAT
16203 && targetm.calls.split_complex_arg)
16204 return rs6000_complex_function_value (mode);
16205 else if (TREE_CODE (valtype) == VECTOR_TYPE && TARGET_ALTIVEC)
16206 regno = ALTIVEC_ARG_RETURN;
16208 regno = GP_ARG_RETURN;
16210 return gen_rtx_REG (mode, regno);
16213 /* Define how to find the value returned by a library function
16214 assuming the value has mode MODE. */
16216 rs6000_libcall_value (enum machine_mode mode)
16218 unsigned int regno;
16220 if (GET_MODE_CLASS (mode) == MODE_FLOAT
16221 && TARGET_HARD_FLOAT && TARGET_FPRS)
16222 regno = FP_ARG_RETURN;
16223 else if (ALTIVEC_VECTOR_MODE (mode))
16224 regno = ALTIVEC_ARG_RETURN;
16225 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
16226 return rs6000_complex_function_value (mode);
16228 regno = GP_ARG_RETURN;
16230 return gen_rtx_REG (mode, regno);
16233 /* Define the offset between two registers, FROM to be eliminated and its
16234 replacement TO, at the start of a routine. */
16236 rs6000_initial_elimination_offset (int from, int to)
16238 rs6000_stack_t *info = rs6000_stack_info ();
16239 HOST_WIDE_INT offset;
16241 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
16242 offset = info->push_p ? 0 : -info->total_size;
16243 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
16244 offset = info->total_size;
16245 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
16246 offset = info->push_p ? info->total_size : 0;
16247 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
16255 /* Return true if TYPE is of type __ev64_opaque__. */
16258 is_ev64_opaque_type (tree type)
16261 && (type == opaque_V2SI_type_node
16262 || type == opaque_V2SF_type_node
16263 || type == opaque_p_V2SI_type_node));
16267 rs6000_dwarf_register_span (rtx reg)
16271 if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg)))
16274 regno = REGNO (reg);
16276 /* The duality of the SPE register size wreaks all kinds of havoc.
16277 This is a way of distinguishing r0 in 32-bits from r0 in
16280 gen_rtx_PARALLEL (VOIDmode,
16283 gen_rtx_REG (SImode, regno + 1200),
16284 gen_rtx_REG (SImode, regno))
16286 gen_rtx_REG (SImode, regno),
16287 gen_rtx_REG (SImode, regno + 1200)));
16290 /* Map internal gcc register numbers to DWARF2 register numbers. */
16293 rs6000_dbx_register_number (unsigned int regno)
16295 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
16297 if (regno == MQ_REGNO)
16299 if (regno == LINK_REGISTER_REGNUM)
16301 if (regno == COUNT_REGISTER_REGNUM)
16303 if (CR_REGNO_P (regno))
16304 return regno - CR0_REGNO + 86;
16305 if (regno == XER_REGNO)
16307 if (ALTIVEC_REGNO_P (regno))
16308 return regno - FIRST_ALTIVEC_REGNO + 1124;
16309 if (regno == VRSAVE_REGNO)
16311 if (regno == VSCR_REGNO)
16313 if (regno == SPE_ACC_REGNO)
16315 if (regno == SPEFSCR_REGNO)
16317 /* SPE high reg number. We get these values of regno from
16318 rs6000_dwarf_register_span. */
16319 if (regno >= 1200 && regno < 1232)
16325 #include "gt-rs6000.h"