1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
39 extern char *language_string;
40 extern int profile_block_flag;
42 #define min(A,B) ((A) < (B) ? (A) : (B))
43 #define max(A,B) ((A) > (B) ? (A) : (B))
47 enum processor_type rs6000_cpu;
48 char *rs6000_cpu_string;
50 /* Set to non-zero by "fix" operation to indicate that itrunc and
51 uitrunc must be defined. */
53 int rs6000_trunc_used;
55 /* Set to non-zero once they have been defined. */
57 static int trunc_defined;
59 /* Set to non-zero once AIX common-mode calls have been defined. */
60 static int common_mode_defined;
61 /* Save information from a "cmpxx" operation until the branch or scc is
64 rtx rs6000_compare_op0, rs6000_compare_op1;
65 int rs6000_compare_fp_p;
67 /* Override command line options. Mostly we process the processor
68 type and sometimes adjust other TARGET_ options. */
71 rs6000_override_options ()
75 /* Simplify the entries below by making a mask for any POWER
76 variant and any PowerPC variant. */
78 #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE)
79 #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
80 | MASK_PPC_GFXOPT | MASK_POWERPC64)
81 #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
85 char *name; /* Canonical processor name. */
86 enum processor_type processor; /* Processor type enum value. */
87 int target_enable; /* Target flags to enable. */
88 int target_disable; /* Target flags to disable. */
89 } processor_target_table[]
90 = {{"common", PROCESSOR_COMMON, 0, POWER_MASKS | POWERPC_MASKS},
91 {"power", PROCESSOR_POWER,
92 MASK_POWER | MASK_MULTIPLE,
93 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
94 {"powerpc", PROCESSOR_POWERPC,
95 MASK_POWERPC | MASK_NEW_MNEMONICS,
96 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
97 {"rios", PROCESSOR_RIOS1,
98 MASK_POWER | MASK_MULTIPLE,
99 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
100 {"rios1", PROCESSOR_RIOS1,
101 MASK_POWER | MASK_MULTIPLE,
102 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
103 {"rsc", PROCESSOR_PPC601,
104 MASK_POWER | MASK_MULTIPLE,
105 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
106 {"rsc1", PROCESSOR_PPC601,
107 MASK_POWER | MASK_MULTIPLE,
108 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
109 {"rios2", PROCESSOR_RIOS2,
110 MASK_POWER | MASK_MULTIPLE | MASK_POWER2,
111 POWERPC_MASKS | MASK_NEW_MNEMONICS},
112 {"601", PROCESSOR_PPC601,
113 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE,
114 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
115 {"mpc601", PROCESSOR_PPC601,
116 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE,
117 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
118 {"ppc601", PROCESSOR_PPC601,
119 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE,
120 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
121 {"603", PROCESSOR_PPC603,
122 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
123 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
124 {"mpc603", PROCESSOR_PPC603,
125 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
126 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
127 {"ppc603", PROCESSOR_PPC603,
128 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
129 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
130 {"604", PROCESSOR_PPC604,
131 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
132 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
133 {"mpc604", PROCESSOR_PPC604,
134 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
135 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
136 {"ppc604", PROCESSOR_PPC604,
137 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
138 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}};
140 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
142 profile_block_flag = 0;
144 /* Identify the processor type */
145 if (rs6000_cpu_string == 0)
146 rs6000_cpu = PROCESSOR_DEFAULT;
149 for (i = 0; i < ptt_size; i++)
150 if (! strcmp (rs6000_cpu_string, processor_target_table[i].name))
152 rs6000_cpu = processor_target_table[i].processor;
153 target_flags |= processor_target_table[i].target_enable;
154 target_flags &= ~processor_target_table[i].target_disable;
160 error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string);
161 rs6000_cpu_string = "default";
162 rs6000_cpu = PROCESSOR_DEFAULT;
167 /* Return non-zero if this function is known to have a null epilogue. */
172 return (reload_completed
173 && first_reg_to_save () == 32
174 && first_fp_reg_to_save () == 64
175 && ! regs_ever_live[65]
176 && ! rs6000_pushes_stack ());
179 /* Returns 1 always. */
182 any_operand (op, mode)
184 enum machine_mode mode;
189 /* Return 1 if OP is a constant that can fit in a D field. */
192 short_cint_operand (op, mode)
194 enum machine_mode mode;
196 return (GET_CODE (op) == CONST_INT
197 && (unsigned) (INTVAL (op) + 0x8000) < 0x10000);
200 /* Similar for a unsigned D field. */
203 u_short_cint_operand (op, mode)
205 enum machine_mode mode;
207 return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0);
210 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
213 non_short_cint_operand (op, mode)
215 enum machine_mode mode;
217 return (GET_CODE (op) == CONST_INT
218 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000);
221 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
225 gpc_reg_operand (op, mode)
227 enum machine_mode mode;
229 return (register_operand (op, mode)
230 && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64));
233 /* Returns 1 if OP is either a pseudo-register or a register denoting a
237 cc_reg_operand (op, mode)
239 enum machine_mode mode;
241 return (register_operand (op, mode)
242 && (GET_CODE (op) != REG
243 || REGNO (op) >= FIRST_PSEUDO_REGISTER
244 || CR_REGNO_P (REGNO (op))));
247 /* Returns 1 if OP is either a constant integer valid for a D-field or a
248 non-special register. If a register, it must be in the proper mode unless
252 reg_or_short_operand (op, mode)
254 enum machine_mode mode;
256 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
259 /* Similar, except check if the negation of the constant would be valid for
263 reg_or_neg_short_operand (op, mode)
265 enum machine_mode mode;
267 if (GET_CODE (op) == CONST_INT)
268 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
270 return gpc_reg_operand (op, mode);
273 /* Return 1 if the operand is either a register or an integer whose high-order
277 reg_or_u_short_operand (op, mode)
279 enum machine_mode mode;
281 if (GET_CODE (op) == CONST_INT
282 && (INTVAL (op) & 0xffff0000) == 0)
285 return gpc_reg_operand (op, mode);
288 /* Return 1 is the operand is either a non-special register or ANY
292 reg_or_cint_operand (op, mode)
294 enum machine_mode mode;
296 return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode);
299 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register
300 with one instruction per word. We only do this if we can safely read
301 CONST_DOUBLE_{LOW,HIGH}. */
304 easy_fp_constant (op, mode)
306 register enum machine_mode mode;
310 if (GET_CODE (op) != CONST_DOUBLE
311 || GET_MODE (op) != mode
312 || GET_MODE_CLASS (mode) != MODE_FLOAT)
315 high = operand_subword (op, 0, 0, mode);
316 low = operand_subword (op, 1, 0, mode);
318 if (high == 0 || ! input_operand (high, word_mode))
321 return (mode == SFmode
322 || (low != 0 && input_operand (low, word_mode)));
325 /* Return 1 if the operand is either a floating-point register, a pseudo
326 register, or memory. */
329 fp_reg_or_mem_operand (op, mode)
331 enum machine_mode mode;
333 return (memory_operand (op, mode)
334 || (register_operand (op, mode)
335 && (GET_CODE (op) != REG
336 || REGNO (op) >= FIRST_PSEUDO_REGISTER
337 || FP_REGNO_P (REGNO (op)))));
340 /* Return 1 if the operand is either an easy FP constant (see above) or
344 mem_or_easy_const_operand (op, mode)
346 enum machine_mode mode;
348 return memory_operand (op, mode) || easy_fp_constant (op, mode);
351 /* Return 1 if the operand is either a non-special register or an item
352 that can be used as the operand of an SI add insn. */
355 add_operand (op, mode)
357 enum machine_mode mode;
359 return (reg_or_short_operand (op, mode)
360 || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0));
363 /* Return 1 if OP is a constant but not a valid add_operand. */
366 non_add_cint_operand (op, mode)
368 enum machine_mode mode;
370 return (GET_CODE (op) == CONST_INT
371 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000
372 && (INTVAL (op) & 0xffff) != 0);
375 /* Return 1 if the operand is a non-special register or a constant that
376 can be used as the operand of an OR or XOR insn on the RS/6000. */
379 logical_operand (op, mode)
381 enum machine_mode mode;
383 return (gpc_reg_operand (op, mode)
384 || (GET_CODE (op) == CONST_INT
385 && ((INTVAL (op) & 0xffff0000) == 0
386 || (INTVAL (op) & 0xffff) == 0)));
389 /* Return 1 if C is a constant that is not a logical operand (as
393 non_logical_cint_operand (op, mode)
395 enum machine_mode mode;
397 return (GET_CODE (op) == CONST_INT
398 && (INTVAL (op) & 0xffff0000) != 0
399 && (INTVAL (op) & 0xffff) != 0);
402 /* Return 1 if C is a constant that can be encoded in a mask on the
403 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
404 Reject all ones and all zeros, since these should have been optimized
405 away and confuse the making of MB and ME. */
415 if (c == 0 || c == ~0)
418 last_bit_value = c & 1;
420 for (i = 1; i < 32; i++)
421 if (((c >>= 1) & 1) != last_bit_value)
422 last_bit_value ^= 1, transitions++;
424 return transitions <= 2;
427 /* Return 1 if the operand is a constant that is a mask on the RS/6000. */
430 mask_operand (op, mode)
432 enum machine_mode mode;
434 return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op));
437 /* Return 1 if the operand is either a non-special register or a
438 constant that can be used as the operand of an RS/6000 logical AND insn. */
441 and_operand (op, mode)
443 enum machine_mode mode;
445 return (reg_or_short_operand (op, mode)
446 || logical_operand (op, mode)
447 || mask_operand (op, mode));
450 /* Return 1 if the operand is a constant but not a valid operand for an AND
454 non_and_cint_operand (op, mode)
456 enum machine_mode mode;
458 return GET_CODE (op) == CONST_INT && ! and_operand (op, mode);
461 /* Return 1 if the operand is a general register or memory operand. */
464 reg_or_mem_operand (op, mode)
466 register enum machine_mode mode;
468 return gpc_reg_operand (op, mode) || memory_operand (op, mode);
471 /* Return 1 if the operand is a general register or memory operand without
472 pre-inc or pre_dec which produces invalid form of PowerPC lwa
476 lwa_operand (op, mode)
478 register enum machine_mode mode;
482 if (reload_completed && GET_CODE (inner) == SUBREG)
483 inner = SUBREG_REG (inner);
485 return gpc_reg_operand (inner, mode)
486 || (memory_operand (inner, mode)
487 && GET_CODE (XEXP (inner, 0)) != PRE_INC
488 && GET_CODE (XEXP (inner, 0)) != PRE_DEC);
491 /* Return 1 if the operand, used inside a MEM, is a valid first argument
492 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
496 call_operand (op, mode)
498 enum machine_mode mode;
500 if (mode != VOIDmode && GET_MODE (op) != mode)
503 return (GET_CODE (op) == SYMBOL_REF
504 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER));
508 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
512 current_file_function_operand (op, mode)
514 enum machine_mode mode;
516 return (GET_CODE (op) == SYMBOL_REF
517 && (SYMBOL_REF_FLAG (op)
518 || op == XEXP (DECL_RTL (current_function_decl), 0)));
522 /* Return 1 if this operand is a valid input for a move insn. */
525 input_operand (op, mode)
527 enum machine_mode mode;
529 /* Memory is always valid. */
530 if (memory_operand (op, mode))
533 /* For floating-point, easy constants are valid. */
534 if (GET_MODE_CLASS (mode) == MODE_FLOAT
536 && easy_fp_constant (op, mode))
539 /* For floating-point or multi-word mode, the only remaining valid type
541 if (GET_MODE_CLASS (mode) == MODE_FLOAT
542 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
543 return register_operand (op, mode);
545 /* The only cases left are integral modes one word or smaller (we
546 do not get called for MODE_CC values). These can be in any
548 if (register_operand (op, mode))
551 /* For HImode and QImode, any constant is valid. */
552 if ((mode == HImode || mode == QImode)
553 && GET_CODE (op) == CONST_INT)
556 /* A SYMBOL_REF referring to the TOC is valid. */
557 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
560 /* Otherwise, we will be doing this SET with an add, so anything valid
561 for an add will be valid. */
562 return add_operand (op, mode);
565 /* Return 1 if OP is a load multiple operation. It is known to be a
566 PARALLEL and the first section will be tested. */
569 load_multiple_operation (op, mode)
571 enum machine_mode mode;
573 int count = XVECLEN (op, 0);
578 /* Perform a quick check so we don't blow up below. */
580 || GET_CODE (XVECEXP (op, 0, 0)) != SET
581 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
582 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
585 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
586 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
588 for (i = 1; i < count; i++)
590 rtx elt = XVECEXP (op, 0, i);
592 if (GET_CODE (elt) != SET
593 || GET_CODE (SET_DEST (elt)) != REG
594 || GET_MODE (SET_DEST (elt)) != SImode
595 || REGNO (SET_DEST (elt)) != dest_regno + i
596 || GET_CODE (SET_SRC (elt)) != MEM
597 || GET_MODE (SET_SRC (elt)) != SImode
598 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
599 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
600 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
601 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
608 /* Similar, but tests for store multiple. Here, the second vector element
609 is a CLOBBER. It will be tested later. */
612 store_multiple_operation (op, mode)
614 enum machine_mode mode;
616 int count = XVECLEN (op, 0) - 1;
621 /* Perform a quick check so we don't blow up below. */
623 || GET_CODE (XVECEXP (op, 0, 0)) != SET
624 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
625 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
628 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
629 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
631 for (i = 1; i < count; i++)
633 rtx elt = XVECEXP (op, 0, i + 1);
635 if (GET_CODE (elt) != SET
636 || GET_CODE (SET_SRC (elt)) != REG
637 || GET_MODE (SET_SRC (elt)) != SImode
638 || REGNO (SET_SRC (elt)) != src_regno + i
639 || GET_CODE (SET_DEST (elt)) != MEM
640 || GET_MODE (SET_DEST (elt)) != SImode
641 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
642 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
643 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
644 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
651 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
652 We only check the opcode against the mode of the CC value here. */
655 branch_comparison_operator (op, mode)
657 enum machine_mode mode;
659 enum rtx_code code = GET_CODE (op);
660 enum machine_mode cc_mode;
662 if (GET_RTX_CLASS (code) != '<')
665 cc_mode = GET_MODE (XEXP (op, 0));
666 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
669 if ((code == GT || code == LT || code == GE || code == LE)
670 && cc_mode == CCUNSmode)
673 if ((code == GTU || code == LTU || code == GEU || code == LEU)
674 && (cc_mode != CCUNSmode))
680 /* Return 1 if OP is a comparison operation that is valid for an scc insn.
681 We check the opcode against the mode of the CC value and disallow EQ or
682 NE comparisons for integers. */
685 scc_comparison_operator (op, mode)
687 enum machine_mode mode;
689 enum rtx_code code = GET_CODE (op);
690 enum machine_mode cc_mode;
692 if (GET_MODE (op) != mode && mode != VOIDmode)
695 if (GET_RTX_CLASS (code) != '<')
698 cc_mode = GET_MODE (XEXP (op, 0));
699 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
702 if (code == NE && cc_mode != CCFPmode)
705 if ((code == GT || code == LT || code == GE || code == LE)
706 && cc_mode == CCUNSmode)
709 if ((code == GTU || code == LTU || code == GEU || code == LEU)
710 && (cc_mode != CCUNSmode))
713 if (cc_mode == CCEQmode && code != EQ && code != NE)
719 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
720 mask required to convert the result of a rotate insn into a shift
721 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
724 includes_lshift_p (shiftop, andop)
725 register rtx shiftop;
728 int shift_mask = (~0 << INTVAL (shiftop));
730 return (INTVAL (andop) & ~shift_mask) == 0;
733 /* Similar, but for right shift. */
736 includes_rshift_p (shiftop, andop)
737 register rtx shiftop;
740 unsigned shift_mask = ~0;
742 shift_mask >>= INTVAL (shiftop);
744 return (INTVAL (andop) & ~ shift_mask) == 0;
747 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
748 for lfq and stfq insns.
750 Note reg1 and reg2 *must* be hard registers. To be sure we will
751 abort if we are passed pseudo registers. */
754 registers_ok_for_quad_peep (reg1, reg2)
757 /* We might have been passed a SUBREG. */
758 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
761 return (REGNO (reg1) == REGNO (reg2) - 1);
764 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and
765 addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */
768 addrs_ok_for_quad_peep (addr1, addr2)
775 /* Extract an offset (if used) from the first addr. */
776 if (GET_CODE (addr1) == PLUS)
778 /* If not a REG, return zero. */
779 if (GET_CODE (XEXP (addr1, 0)) != REG)
783 reg1 = REGNO (XEXP (addr1, 0));
784 /* The offset must be constant! */
785 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
787 offset1 = INTVAL (XEXP (addr1, 1));
790 else if (GET_CODE (addr1) != REG)
794 reg1 = REGNO (addr1);
795 /* This was a simple (mem (reg)) expression. Offset is 0. */
799 /* Make sure the second address is a (mem (plus (reg) (const_int). */
800 if (GET_CODE (addr2) != PLUS)
803 if (GET_CODE (XEXP (addr2, 0)) != REG
804 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
807 if (reg1 != REGNO (XEXP (addr2, 0)))
810 /* The offset for the second addr must be 8 more than the first addr. */
811 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
814 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
819 /* Return the register class of a scratch register needed to copy IN into
820 or out of a register in CLASS in MODE. If it can be done directly,
821 NO_REGS is returned. */
824 secondary_reload_class (class, mode, in)
825 enum reg_class class;
826 enum machine_mode mode;
829 int regno = true_regnum (in);
831 if (regno >= FIRST_PSEUDO_REGISTER)
834 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
836 if (class == GENERAL_REGS || class == BASE_REGS
837 || (regno >= 0 && INT_REGNO_P (regno)))
840 /* Constants, memory, and FP registers can go into FP registers. */
841 if ((regno == -1 || FP_REGNO_P (regno))
842 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
845 /* We can copy among the CR registers. */
846 if ((class == CR_REGS || class == CR0_REGS)
847 && regno >= 0 && CR_REGNO_P (regno))
850 /* Otherwise, we need GENERAL_REGS. */
854 /* Given a comparison operation, return the bit number in CCR to test. We
855 know this is a valid comparison.
857 SCC_P is 1 if this is for an scc. That means that %D will have been
858 used instead of %C, so the bits will be in different places.
860 Return -1 if OP isn't a valid comparison for some reason. */
867 enum rtx_code code = GET_CODE (op);
868 enum machine_mode cc_mode;
872 if (GET_RTX_CLASS (code) != '<')
875 cc_mode = GET_MODE (XEXP (op, 0));
876 cc_regnum = REGNO (XEXP (op, 0));
877 base_bit = 4 * (cc_regnum - 68);
879 /* In CCEQmode cases we have made sure that the result is always in the
880 third bit of the CR field. */
882 if (cc_mode == CCEQmode)
888 return scc_p ? base_bit + 3 : base_bit + 2;
897 /* If floating-point, we will have done a cror to put the bit in the
898 unordered position. So test that bit. For integer, this is ! LT
899 unless this is an scc insn. */
900 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit;
903 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1;
910 /* Print an operand. Recognize special options, documented below. */
913 print_operand (file, x, code)
921 /* These macros test for integers and extract the low-order bits. */
923 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
924 && GET_MODE (X) == VOIDmode)
926 #define INT_LOWPART(X) \
927 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
932 /* Write out an instruction after the call which may be replaced
933 with glue code by the loader. This depends on the AIX version. */
934 asm_fprintf (file, RS6000_CALL_GLUE);
938 /* Write the register number of the TOC register. */
939 fputs (TARGET_MINIMAL_TOC ? "30" : "2", file);
943 /* If X is a constant integer whose low-order 5 bits are zero,
944 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
945 in the AIX assembler where "sri" with a zero shift count
946 write a trash instruction. */
947 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
954 /* Low-order 16 bits of constant, unsigned. */
956 output_operand_lossage ("invalid %%b value");
958 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
962 /* This is an optional cror needed for LE or GE floating-point
963 comparisons. Otherwise write nothing. */
964 if ((GET_CODE (x) == LE || GET_CODE (x) == GE)
965 && GET_MODE (XEXP (x, 0)) == CCFPmode)
967 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
969 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
970 base_bit + 2, base_bit + (GET_CODE (x) == GE));
975 /* Similar, except that this is for an scc, so we must be able to
976 encode the test in a single bit that is one. We do the above
977 for any LE, GE, GEU, or LEU and invert the bit for NE. */
978 if (GET_CODE (x) == LE || GET_CODE (x) == GE
979 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
981 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
983 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
985 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
988 else if (GET_CODE (x) == NE)
990 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
992 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
993 base_bit + 2, base_bit + 2);
998 /* X is a CR register. Print the number of the third bit of the CR */
999 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1000 output_operand_lossage ("invalid %%E value");
1002 fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3);
1006 /* X is a CR register. Print the shift count needed to move it
1007 to the high-order four bits. */
1008 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1009 output_operand_lossage ("invalid %%f value");
1011 fprintf (file, "%d", 4 * (REGNO (x) - 68));
1015 /* Similar, but print the count for the rotate in the opposite
1017 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1018 output_operand_lossage ("invalid %%F value");
1020 fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68));
1024 /* X is a constant integer. If it is negative, print "m",
1025 otherwise print "z". This is to make a aze or ame insn. */
1026 if (GET_CODE (x) != CONST_INT)
1027 output_operand_lossage ("invalid %%G value");
1028 else if (INTVAL (x) >= 0)
1035 /* If constant, output low-order five bits. Otherwise,
1038 fprintf (file, "%d", INT_LOWPART (x) & 31);
1040 print_operand (file, x, 0);
1044 /* Print `i' if this is a constant, else nothing. */
1050 /* Write the bit number in CCR for jump. */
1053 output_operand_lossage ("invalid %%j code");
1055 fprintf (file, "%d", i);
1059 /* Similar, but add one for shift count in rlinm for scc and pass
1060 scc flag to `ccr_bit'. */
1063 output_operand_lossage ("invalid %%J code");
1065 /* If we want bit 31, write a shift count of zero, not 32. */
1066 fprintf (file, "%d", i == 31 ? 0 : i + 1);
1070 /* X must be a constant. Write the 1's complement of the
1073 output_operand_lossage ("invalid %%k value");
1075 fprintf (file, "%d", ~ INT_LOWPART (x));
1079 /* Write second word of DImode or DFmode reference. Works on register
1080 or non-indexed memory only. */
1081 if (GET_CODE (x) == REG)
1082 fprintf (file, "%d", REGNO (x) + 1);
1083 else if (GET_CODE (x) == MEM)
1085 /* Handle possible auto-increment. Since it is pre-increment and
1086 we have already done it, we can just use an offset of four. */
1087 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1088 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1089 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1091 output_address (plus_constant (XEXP (x, 0), 4));
1096 /* MB value for a mask operand. */
1097 if (! mask_operand (x, VOIDmode))
1098 output_operand_lossage ("invalid %%m value");
1100 val = INT_LOWPART (x);
1102 /* If the high bit is set and the low bit is not, the value is zero.
1103 If the high bit is zero, the value is the first 1 bit we find from
1105 if (val < 0 && (val & 1) == 0)
1107 fprintf (file, "0");
1112 for (i = 1; i < 32; i++)
1113 if ((val <<= 1) < 0)
1115 fprintf (file, "%d", i);
1119 /* Otherwise, look for the first 0 bit from the right. The result is its
1120 number plus 1. We know the low-order bit is one. */
1121 for (i = 0; i < 32; i++)
1122 if (((val >>= 1) & 1) == 0)
1125 /* If we ended in ...01, I would be 0. The correct value is 31, so
1127 fprintf (file, "%d", 31 - i);
1131 /* ME value for a mask operand. */
1132 if (! mask_operand (x, VOIDmode))
1133 output_operand_lossage ("invalid %%m value");
1135 val = INT_LOWPART (x);
1137 /* If the low bit is set and the high bit is not, the value is 31.
1138 If the low bit is zero, the value is the first 1 bit we find from
1140 if ((val & 1) && val >= 0)
1145 else if ((val & 1) == 0)
1147 for (i = 0; i < 32; i++)
1148 if ((val >>= 1) & 1)
1151 /* If we had ....10, I would be 0. The result should be
1152 30, so we need 30 - i. */
1153 fprintf (file, "%d", 30 - i);
1157 /* Otherwise, look for the first 0 bit from the left. The result is its
1158 number minus 1. We know the high-order bit is one. */
1159 for (i = 0; i < 32; i++)
1160 if ((val <<= 1) >= 0)
1163 fprintf (file, "%d", i);
1167 /* Write the number of elements in the vector times 4. */
1168 if (GET_CODE (x) != PARALLEL)
1169 output_operand_lossage ("invalid %%N value");
1171 fprintf (file, "%d", XVECLEN (x, 0) * 4);
1175 /* Similar, but subtract 1 first. */
1176 if (GET_CODE (x) != PARALLEL)
1177 output_operand_lossage ("invalid %%N value");
1179 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
1183 /* X is a CONST_INT that is a power of two. Output the logarithm. */
1185 || (i = exact_log2 (INT_LOWPART (x))) < 0)
1186 output_operand_lossage ("invalid %%p value");
1188 fprintf (file, "%d", i);
1192 /* The operand must be an indirect memory reference. The result
1193 is the register number. */
1194 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
1195 || REGNO (XEXP (x, 0)) >= 32)
1196 output_operand_lossage ("invalid %%P value");
1198 fprintf (file, "%d", REGNO (XEXP (x, 0)));
1202 /* X is a CR register. Print the mask for `mtcrf'. */
1203 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1204 output_operand_lossage ("invalid %%R value");
1206 fprintf (file, "%d", 128 >> (REGNO (x) - 68));
1210 /* Low 5 bits of 32 - value */
1212 output_operand_lossage ("invalid %%s value");
1214 fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31);
1218 /* Write 12 if this jump operation will branch if true, 4 otherwise.
1219 All floating-point operations except NE branch true and integer
1220 EQ, LT, GT, LTU and GTU also branch true. */
1221 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1222 output_operand_lossage ("invalid %%t value");
1224 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1225 && GET_CODE (x) != NE)
1226 || GET_CODE (x) == EQ
1227 || GET_CODE (x) == LT || GET_CODE (x) == GT
1228 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
1235 /* Opposite of 't': write 4 if this jump operation will branch if true,
1237 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1238 output_operand_lossage ("invalid %%t value");
1240 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1241 && GET_CODE (x) != NE)
1242 || GET_CODE (x) == EQ
1243 || GET_CODE (x) == LT || GET_CODE (x) == GT
1244 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
1251 /* High-order 16 bits of constant. */
1253 output_operand_lossage ("invalid %%u value");
1255 fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff);
1259 /* Print `u' if this has an auto-increment or auto-decrement. */
1260 if (GET_CODE (x) == MEM
1261 && (GET_CODE (XEXP (x, 0)) == PRE_INC
1262 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
1267 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
1270 fprintf (file, "%d",
1271 (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000));
1273 print_operand (file, x, 0);
1277 /* If constant, low-order 16 bits of constant, unsigned.
1278 Otherwise, write normally. */
1280 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
1282 print_operand (file, x, 0);
1286 if (GET_CODE (x) == MEM
1287 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0)))
1292 /* Like 'L', for third word of TImode */
1293 if (GET_CODE (x) == REG)
1294 fprintf (file, "%d", REGNO (x) + 2);
1295 else if (GET_CODE (x) == MEM)
1297 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1298 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1299 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
1301 output_address (plus_constant (XEXP (x, 0), 8));
1306 /* X is a SYMBOL_REF. Write out the name preceded by a
1307 period and without any trailing data in brackets. Used for function
1308 names. If we are configured for System V (or the embedded ABI) on
1309 the PowerPC, do not emit the period, since those systems do not use
1310 TOCs and the like. */
1311 if (GET_CODE (x) != SYMBOL_REF)
1314 #ifndef USING_SVR4_H
1317 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
1321 /* Like 'L', for last word of TImode. */
1322 if (GET_CODE (x) == REG)
1323 fprintf (file, "%d", REGNO (x) + 3);
1324 else if (GET_CODE (x) == MEM)
1326 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1327 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1328 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
1330 output_address (plus_constant (XEXP (x, 0), 12));
1335 if (GET_CODE (x) == REG)
1336 fprintf (file, "%s", reg_names[REGNO (x)]);
1337 else if (GET_CODE (x) == MEM)
1339 /* We need to handle PRE_INC and PRE_DEC here, since we need to
1340 know the width from the mode. */
1341 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
1342 fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)),
1343 REGNO (XEXP (XEXP (x, 0), 0)));
1344 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
1345 fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)),
1346 REGNO (XEXP (XEXP (x, 0), 0)));
1348 output_address (XEXP (x, 0));
1351 output_addr_const (file, x);
1355 output_operand_lossage ("invalid %%xn code");
1359 /* Print the address of an operand. */
1362 print_operand_address (file, x)
1366 if (GET_CODE (x) == REG)
1367 fprintf (file, "0(%d)", REGNO (x));
1368 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
1370 output_addr_const (file, x);
1371 /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead
1372 of the toc pointer. */
1373 if (TARGET_MINIMAL_TOC)
1374 fprintf (file, "(30)");
1376 fprintf (file, "(2)");
1378 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
1380 if (REGNO (XEXP (x, 0)) == 0)
1381 fprintf (file, "%d,%d", REGNO (XEXP (x, 1)), REGNO (XEXP (x, 0)));
1383 fprintf (file, "%d,%d", REGNO (XEXP (x, 0)), REGNO (XEXP (x, 1)));
1385 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1386 fprintf (file, "%d(%d)", INTVAL (XEXP (x, 1)), REGNO (XEXP (x, 0)));
1391 /* This page contains routines that are used to determine what the function
1392 prologue and epilogue code will do and write them out. */
1394 /* Return the first fixed-point register that is required to be saved. 32 if
1398 first_reg_to_save ()
1402 /* Find lowest numbered live register. */
1403 for (first_reg = 13; first_reg <= 31; first_reg++)
1404 if (regs_ever_live[first_reg])
1407 /* If profiling, then we must save/restore every register that contains
1408 a parameter before/after the .mcount call. Use registers from 30 down
1409 to 23 to do this. Don't use the frame pointer in reg 31.
1411 For now, save enough room for all of the parameter registers. */
1419 /* Similar, for FP regs. */
1422 first_fp_reg_to_save ()
1426 /* Find lowest numbered live register. */
1427 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
1428 if (regs_ever_live[first_reg])
1434 /* Return 1 if we need to save CR. */
1439 return regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72];
1442 /* Compute the size of the save area in the stack, including the space for
1450 /* We have the six fixed words, plus the size of the register save
1451 areas, rounded to a double-word. */
1452 size = 6 + (32 - first_reg_to_save ()) + (64 - first_fp_reg_to_save ()) * 2;
1459 /* Return non-zero if this function makes calls. */
1462 rs6000_makes_calls ()
1466 /* If we are profiling, we will be making a call to mcount. */
1470 for (insn = get_insns (); insn; insn = next_insn (insn))
1471 if (GET_CODE (insn) == CALL_INSN)
1477 /* Return non-zero if this function needs to push space on the stack. */
1480 rs6000_pushes_stack ()
1482 int total_size = (rs6000_sa_size () + get_frame_size ()
1483 + current_function_outgoing_args_size);
1485 /* We need to push the stack if a frame pointer is needed (because the
1486 stack might be dynamically adjusted), if we are debugging, if the
1487 total stack size is more than 220 bytes, or if we make calls. */
1489 return (frame_pointer_needed || write_symbols != NO_DEBUG
1491 || rs6000_makes_calls ());
1495 /* Write out a System V.4 style traceback table before the prologue
1497 At present, only emit the basic tag table (ie, do not emit tag_types other
1498 than 0, which might use more than 1 tag word).
1500 The first tag word looks like:
1503 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1504 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1505 | 0 |ver| tag |e|s| alloca | # fprs | # gprs |s|l|c|f|
1506 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1511 svr4_traceback (file, name, decl)
1516 int first_reg = first_reg_to_save ();
1517 int first_fp_reg = first_fp_reg_to_save ();
1518 int pushes_stack = rs6000_pushes_stack ();
1520 long version = 0; /* version number */
1521 long tag_type = 0; /* function type */
1522 long extended_tag = 0; /* additional tag words needed */
1523 long spare = 0; /* reserved for future use */
1524 long alloca_reg; /* stack/frame register */
1525 long fpr_max = 64 - first_fp_reg; /* # of floating point registers saved */
1526 long gpr_max = 32 - first_reg; /* # of general purpose registers saved */
1527 long sp_max; /* 1 if the function aquires a stack frame */
1528 long lr_max; /* 1 if the function stores the link register */
1529 long cr_max; /* 1 if the function has a CR save word */
1530 long fpscr_max = 0; /* 1 if the function has a FPSCR save word */
1532 if (frame_pointer_needed)
1535 else if (pushes_stack != 0)
1541 lr_max = (regs_ever_live[65] || first_fp_reg < 62 || profile_flag);
1542 cr_max = (must_save_cr () != 0);
1543 sp_max = (pushes_stack != 0);
1545 tag = (((version & 3) << 24)
1546 | ((tag_type & 7) << 21)
1547 | ((extended_tag & 1) << 20)
1548 | ((spare & 1) << 19)
1549 | ((alloca_reg & 0x1f) << 14)
1550 | ((fpr_max & 0x1f) << 9)
1551 | ((gpr_max & 0x1f) << 4)
1552 | ((sp_max & 1) << 3)
1553 | ((lr_max & 1) << 2)
1554 | ((cr_max & 1) << 1)
1555 | ((fpscr_max & 1) << 0));
1557 fprintf (file, "\t.long 0x%lx\n", tag);
1560 #endif /* USING_SVR4_H */
1562 /* Write function prologue. */
1565 output_prolog (file, size)
1569 int first_reg = first_reg_to_save ();
1570 int must_push = rs6000_pushes_stack ();
1571 int first_fp_reg = first_fp_reg_to_save ();
1572 int basic_size = rs6000_sa_size ();
1573 int total_size = (basic_size + size + current_function_outgoing_args_size);
1575 /* Round size to multiple of 8 bytes. */
1576 total_size = (total_size + 7) & ~7;
1578 /* Write .extern for any function we will call to save and restore fp
1580 if (first_fp_reg < 62)
1581 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
1582 SAVE_FP_PREFIX, first_fp_reg - 32, SAVE_FP_SUFFIX,
1583 RESTORE_FP_PREFIX, first_fp_reg - 32, RESTORE_FP_SUFFIX);
1585 /* Write .extern for truncation routines, if needed. */
1586 if (rs6000_trunc_used && ! trunc_defined)
1588 fprintf (file, "\t.extern .%s\n\t.extern .%s\n",
1589 RS6000_ITRUNC, RS6000_UITRUNC);
1592 /* Write .extern for AIX common mode routines, if needed. */
1593 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
1595 fputs ("\t.extern __mulh\n", file);
1596 fputs ("\t.extern __mull\n", file);
1597 fputs ("\t.extern __divss\n", file);
1598 fputs ("\t.extern __divus\n", file);
1599 fputs ("\t.extern __quoss\n", file);
1600 fputs ("\t.extern __quous\n", file);
1601 common_mode_defined = 1;
1605 /* If we have a relocatable GOT section, we need to save the LR. */
1606 if (TARGET_RELOCATABLE && get_pool_size () != 0)
1607 regs_ever_live[65] = 1;
1610 /* If we have to call a function to save fpr's, or if we are doing profiling,
1611 then we will be using LR. */
1612 if (first_fp_reg < 62 || profile_flag)
1613 regs_ever_live[65] = 1;
1615 /* If we use the link register, get it into r0. */
1616 if (regs_ever_live[65])
1617 asm_fprintf (file, "\tmflr 0\n");
1619 /* If we need to save CR, put it into r12. */
1620 if (must_save_cr ())
1621 asm_fprintf (file, "\tmfcr 12\n");
1623 /* Do any required saving of fpr's. If only one or two to save, do it
1624 ourself. Otherwise, call function. Note that since they are statically
1625 linked, we do not need a nop following them. */
1626 if (first_fp_reg == 62)
1627 asm_fprintf (file, "\tstfd 30,-16(1)\n\tstfd 31,-8(1)\n");
1628 else if (first_fp_reg == 63)
1629 asm_fprintf (file, "\tstfd 31,-8(1)\n");
1630 else if (first_fp_reg != 64)
1631 asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX, first_fp_reg - 32, SAVE_FP_SUFFIX);
1633 /* Now save gpr's. */
1634 if (! TARGET_MULTIPLE || first_reg == 31)
1638 for (regno = first_reg,
1639 loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8;
1642 asm_fprintf (file, "\t{st|stw} %d,%d(1)\n", regno, loc);
1645 else if (first_reg != 32)
1646 asm_fprintf (file, "\t{stm|stmw} %d,%d(1)\n", first_reg,
1647 - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8);
1649 /* Save lr if we used it. */
1650 if (regs_ever_live[65])
1651 asm_fprintf (file, "\t{st|stw} 0,8(1)\n");
1653 /* Save CR if we use any that must be preserved. */
1654 if (must_save_cr ())
1655 asm_fprintf (file, "\t{st|stw} 12,4(1)\n");
1657 /* Update stack and set back pointer. */
1660 if (total_size < 32767)
1661 asm_fprintf (file, "\t{stu|stwu} 1,%d(1)\n", - total_size);
1664 asm_fprintf (file, "\t{liu|lis} 0,%d\n\t{oril|ori} 0,0,%d\n",
1665 (total_size >> 16) & 0xffff, total_size & 0xffff);
1667 asm_fprintf (file, "\tsubf 12,0,1\n");
1669 asm_fprintf (file, "\t{sf|subfc} 12,0,1\n");
1670 asm_fprintf (file, "\t{st|stw} 1,0(12)\n\tmr 1,12\n");
1674 /* Set frame pointer, if needed. */
1675 if (frame_pointer_needed)
1676 asm_fprintf (file, "\tmr 31,1\n");
1678 /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
1679 TOC_TABLE address into register 30. */
1680 if (TARGET_MINIMAL_TOC && get_pool_size () != 0)
1685 if (TARGET_RELOCATABLE)
1687 static int labelno = 0;
1689 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", labelno);
1690 fprintf (file, "\tbl ");
1691 assemble_name (file, buf);
1692 fprintf (file, "\n");
1694 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
1695 fprintf (file, (TARGET_POWERPC64) ? "\t.quad " : "\t.long ");
1696 assemble_name (file, buf);
1697 fprintf (file, "-.\n");
1699 ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", labelno);
1700 fprintf (file, "\tmflr 30\n");
1702 asm_fprintf (file, (TARGET_POWERPC64) ? "\tld 0,0(30)\n" : "\t{l|lwz} 0,0(30)\n");
1703 asm_fprintf (file, "\t{cax|add} 30,0,30\n");
1707 #endif /* USING_SVR4_H */
1709 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0);
1710 asm_fprintf (file, "\t{l|lwz} 30,");
1711 assemble_name (file, buf);
1712 asm_fprintf (file, "(2)\n");
1717 /* Write function epilogue. */
1720 output_epilog (file, size)
1724 int first_reg = first_reg_to_save ();
1725 int must_push = rs6000_pushes_stack ();
1726 int first_fp_reg = first_fp_reg_to_save ();
1727 int basic_size = rs6000_sa_size ();
1728 int total_size = (basic_size + size + current_function_outgoing_args_size);
1729 rtx insn = get_last_insn ();
1731 /* Round size to multiple of 8 bytes. */
1732 total_size = (total_size + 7) & ~7;
1734 /* If the last insn was a BARRIER, we don't have to write anything except
1736 if (GET_CODE (insn) == NOTE)
1737 insn = prev_nonnote_insn (insn);
1738 if (insn == 0 || GET_CODE (insn) != BARRIER)
1740 /* If we have a frame pointer, a call to alloca, or a large stack
1741 frame, restore the old stack pointer using the backchain. Otherwise,
1742 we know what size to update it with. */
1743 if (frame_pointer_needed || current_function_calls_alloca
1744 || total_size > 32767)
1745 asm_fprintf (file, "\t{l|lwz} 1,0(1)\n");
1747 asm_fprintf (file, "\t{cal 1,%d(1)|addi 1,1,%d}\n", total_size);
1749 /* Get the old lr if we saved it. */
1750 if (regs_ever_live[65])
1751 asm_fprintf (file, "\t{l|lwz} 0,8(1)\n");
1753 /* Get the old cr if we saved it. */
1754 if (must_save_cr ())
1755 asm_fprintf (file, "\t{l|lwz} 12,4(1)\n");
1757 /* Set LR here to try to overlap restores below. */
1758 if (regs_ever_live[65])
1759 asm_fprintf (file, "\tmtlr 0\n");
1761 /* Restore gpr's. */
1762 if (! TARGET_MULTIPLE || first_reg == 31)
1766 for (regno = first_reg,
1767 loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8;
1770 asm_fprintf (file, "\t{l|lwz} %d,%d(1)\n", regno, loc);
1773 else if (first_reg != 32)
1774 asm_fprintf (file, "\t{lm|lmw} %d,%d(1)\n", first_reg,
1775 - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8);
1777 /* Restore fpr's if we can do it without calling a function. */
1778 if (first_fp_reg == 62)
1779 asm_fprintf (file, "\tlfd 30,-16(1)\n\tlfd 31,-8(1)\n");
1780 else if (first_fp_reg == 63)
1781 asm_fprintf (file, "\tlfd 31,-8(1)\n");
1783 /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4
1785 if (must_save_cr ())
1786 asm_fprintf (file, "\tmtcrf %d,12\n",
1787 (regs_ever_live[70] != 0) * 0x20
1788 + (regs_ever_live[71] != 0) * 0x10
1789 + (regs_ever_live[72] != 0) * 0x8);
1791 /* If we have to restore more than two FP registers, branch to the
1792 restore function. It will return to our caller. */
1793 if (first_fp_reg < 62)
1794 asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX, first_fp_reg - 32, RESTORE_FP_SUFFIX);
1796 asm_fprintf (file, "\t{br|blr}\n");
1799 /* Output a traceback table here. See /usr/include/sys/debug.h for info
1802 We don't output a traceback table if -finhibit-size-directive was
1803 used. The documentation for -finhibit-size-directive reads
1804 ``don't output a @code{.size} assembler directive, or anything
1805 else that would cause trouble if the function is split in the
1806 middle, and the two halves are placed at locations far apart in
1807 memory.'' The traceback table has this property, since it
1808 includes the offset from the start of the function to the
1809 traceback table itself.
1811 System V.4 Powerpc's (and the embedded ABI derived from it) use a
1812 different traceback table located before the prologue. */
1813 #ifndef USING_SVR4_H
1814 if (! flag_inhibit_size_directive)
1816 char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
1817 int fixed_parms, float_parms, parm_info;
1820 /* Need label immediately before tbtab, so we can compute its offset
1821 from the function start. */
1824 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
1825 ASM_OUTPUT_LABEL (file, fname);
1827 /* The .tbtab pseudo-op can only be used for the first eight
1828 expressions, since it can't handle the possibly variable
1829 length fields that follow. However, if you omit the optional
1830 fields, the assembler outputs zeros for all optional fields
1831 anyways, giving each variable length field is minimum length
1832 (as defined in sys/debug.h). Thus we can not use the .tbtab
1833 pseudo-op at all. */
1835 /* An all-zero word flags the start of the tbtab, for debuggers
1836 that have to find it by searching forward from the entry
1837 point or from the current pc. */
1838 fprintf (file, "\t.long 0\n");
1840 /* Tbtab format type. Use format type 0. */
1841 fprintf (file, "\t.byte 0,");
1843 /* Language type. Unfortunately, there doesn't seem to be any
1844 official way to get this info, so we use language_string. C
1845 is 0. C++ is 9. No number defined for Obj-C, so use the
1846 value for C for now. */
1847 if (! strcmp (language_string, "GNU C")
1848 || ! strcmp (language_string, "GNU Obj-C"))
1850 else if (! strcmp (language_string, "GNU F77"))
1852 else if (! strcmp (language_string, "GNU Ada"))
1854 else if (! strcmp (language_string, "GNU PASCAL"))
1856 else if (! strcmp (language_string, "GNU C++"))
1860 fprintf (file, "%d,", i);
1862 /* 8 single bit fields: global linkage (not set for C extern linkage,
1863 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
1864 from start of procedure stored in tbtab, internal function, function
1865 has controlled storage, function has no toc, function uses fp,
1866 function logs/aborts fp operations. */
1867 /* Assume that fp operations are used if any fp reg must be saved. */
1868 fprintf (file, "%d,", (1 << 5) | ((first_fp_reg != 64) << 1));
1870 /* 6 bitfields: function is interrupt handler, name present in
1871 proc table, function calls alloca, on condition directives
1872 (controls stack walks, 3 bits), saves condition reg, saves
1874 /* The `function calls alloca' bit seems to be set whenever reg 31 is
1875 set up as a frame pointer, even when there is no alloca call. */
1876 fprintf (file, "%d,",
1877 ((1 << 6) | (frame_pointer_needed << 5)
1878 | (must_save_cr () << 1) | (regs_ever_live[65])));
1880 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
1882 fprintf (file, "%d,",
1883 (must_push << 7) | (64 - first_fp_reg_to_save ()));
1885 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
1886 fprintf (file, "%d,", (32 - first_reg_to_save ()));
1889 /* Compute the parameter info from the function decl argument
1892 int next_parm_info_bit;
1894 next_parm_info_bit = 31;
1899 for (decl = DECL_ARGUMENTS (current_function_decl);
1900 decl; decl = TREE_CHAIN (decl))
1902 rtx parameter = DECL_INCOMING_RTL (decl);
1903 enum machine_mode mode = GET_MODE (parameter);
1905 if (GET_CODE (parameter) == REG)
1907 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1915 else if (mode == DFmode)
1920 /* If only one bit will fit, don't or in this entry. */
1921 if (next_parm_info_bit > 0)
1922 parm_info |= (bits << (next_parm_info_bit - 1));
1923 next_parm_info_bit -= 2;
1927 fixed_parms += ((GET_MODE_SIZE (mode)
1928 + (UNITS_PER_WORD - 1))
1930 next_parm_info_bit -= 1;
1936 /* Number of fixed point parameters. */
1937 /* This is actually the number of words of fixed point parameters; thus
1938 an 8 byte struct counts as 2; and thus the maximum value is 8. */
1939 fprintf (file, "%d,", fixed_parms);
1941 /* 2 bitfields: number of floating point parameters (7 bits), parameters
1943 /* This is actually the number of fp registers that hold parameters;
1944 and thus the maximum value is 13. */
1945 /* Set parameters on stack bit if parameters are not in their original
1946 registers, regardless of whether they are on the stack? Xlc
1947 seems to set the bit when not optimizing. */
1948 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
1950 /* Optional fields follow. Some are variable length. */
1952 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
1954 /* There is an entry for each parameter in a register, in the order that
1955 they occur in the parameter list. Any intervening arguments on the
1956 stack are ignored. If the list overflows a long (max possible length
1957 34 bits) then completely leave off all elements that don't fit. */
1958 /* Only emit this long if there was at least one parameter. */
1959 if (fixed_parms || float_parms)
1960 fprintf (file, "\t.long %d\n", parm_info);
1962 /* Offset from start of code to tb table. */
1963 fprintf (file, "\t.long ");
1964 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
1965 RS6000_OUTPUT_BASENAME (file, fname);
1966 fprintf (file, "-.");
1967 RS6000_OUTPUT_BASENAME (file, fname);
1968 fprintf (file, "\n");
1970 /* Interrupt handler mask. */
1971 /* Omit this long, since we never set the interrupt handler bit
1974 /* Number of CTL (controlled storage) anchors. */
1975 /* Omit this long, since the has_ctl bit is never set above. */
1977 /* Displacement into stack of each CTL anchor. */
1978 /* Omit this list of longs, because there are no CTL anchors. */
1980 /* Length of function name. */
1981 fprintf (file, "\t.short %d\n", strlen (fname));
1983 /* Function name. */
1984 assemble_string (fname, strlen (fname));
1986 /* Register for alloca automatic storage; this is always reg 31.
1987 Only emit this if the alloca bit was set above. */
1988 if (frame_pointer_needed)
1989 fprintf (file, "\t.byte 31\n");
1991 #endif /* !USING_SVR4_H */
1994 /* Output a TOC entry. We derive the entry name from what is
1998 output_toc (file, x, labelno)
2009 if (TARGET_MINIMAL_TOC)
2011 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
2012 fprintf (file, "%d = .-", labelno);
2013 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC");
2014 fprintf (file, "1\n");
2017 #endif /* USING_SVR4_H */
2018 ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
2020 /* Handle FP constants specially. Note that if we have a minimal
2021 TOC, things we put here aren't actually in the TOC, so we can allow
2023 if (GET_CODE (x) == CONST_DOUBLE
2024 && GET_MODE (x) == DFmode
2025 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
2030 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2031 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
2032 if (TARGET_MINIMAL_TOC)
2033 fprintf (file, "\t.long %ld\n\t.long %ld\n", l[0], l[1]);
2035 fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n",
2036 l[0], l[1], l[0], l[1]);
2039 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode
2040 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
2042 rtx val = operand_subword (x, 0, 0, SFmode);
2044 if (val == 0 || GET_CODE (val) != CONST_INT)
2047 if (TARGET_MINIMAL_TOC)
2048 fprintf (file, "\t.long %d\n", INTVAL (val));
2050 fprintf (file, "\t.tc FS_%x[TC],%d\n", INTVAL (val), INTVAL (val));
2054 if (GET_CODE (x) == CONST)
2056 base = XEXP (XEXP (x, 0), 0);
2057 offset = INTVAL (XEXP (XEXP (x, 0), 1));
2060 if (GET_CODE (base) == SYMBOL_REF)
2061 name = XSTR (base, 0);
2062 else if (GET_CODE (base) == LABEL_REF)
2063 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
2064 else if (GET_CODE (base) == CODE_LABEL)
2065 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
2069 if (TARGET_MINIMAL_TOC)
2070 fprintf (file, "\t.long ");
2073 fprintf (file, "\t.tc ");
2074 RS6000_OUTPUT_BASENAME (file, name);
2077 fprintf (file, ".N%d", - offset);
2079 fprintf (file, ".P%d", offset);
2081 fprintf (file, "[TC],");
2083 output_addr_const (file, x);
2084 fprintf (file, "\n");
2087 /* Output an assembler pseudo-op to write an ASCII string of N characters
2088 starting at P to FILE.
2090 On the RS/6000, we have to do this using the .byte operation and
2091 write out special characters outside the quoted string.
2092 Also, the assembler is broken; very long strings are truncated,
2093 so we must artificially break them up early. */
2096 output_ascii (file, p, n)
2102 int i, count_string;
2103 char *for_string = "\t.byte \"";
2104 char *for_decimal = "\t.byte ";
2105 char *to_close = NULL;
2108 for (i = 0; i < n; i++)
2111 if (c >= ' ' && c < 0177)
2114 fputs (for_string, file);
2117 /* Write two quotes to get one. */
2125 for_decimal = "\"\n\t.byte ";
2129 if (count_string >= 512)
2131 fputs (to_close, file);
2133 for_string = "\t.byte \"";
2134 for_decimal = "\t.byte ";
2142 fputs (for_decimal, file);
2143 fprintf (file, "%d", c);
2145 for_string = "\n\t.byte \"";
2152 /* Now close the string if we have written one. Then end the line. */
2154 fprintf (file, to_close);
2157 /* Generate a unique section name for FILENAME for a section type
2158 represented by SECTION_DESC. Output goes into BUF.
2160 SECTION_DESC can be any string, as long as it is different for each
2161 possible section type.
2163 We name the section in the same manner as xlc. The name begins with an
2164 underscore followed by the filename (after stripping any leading directory
2165 names) with the last period replaced by the string SECTION_DESC. If
2166 FILENAME does not contain a period, SECTION_DESC is appended to the end of
2170 rs6000_gen_section_name (buf, filename, section_desc)
2175 char *q, *after_last_slash, *last_period;
2179 after_last_slash = filename;
2180 for (q = filename; *q; q++)
2183 after_last_slash = q + 1;
2188 len = strlen (after_last_slash) + strlen (section_desc) + 2;
2189 *buf = (char *) permalloc (len);
2194 for (q = after_last_slash; *q; q++)
2196 if (q == last_period)
2198 strcpy (p, section_desc);
2199 p += strlen (section_desc);
2202 else if (isalnum (*q))
2206 if (last_period == 0)
2207 strcpy (p, section_desc);
2212 /* Write function profiler code. */
2215 output_function_profiler (file, labelno)
2222 /* The last used parameter register. */
2227 /* Set up a TOC entry for the profiler label. */
2229 ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno);
2230 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
2231 if (TARGET_MINIMAL_TOC)
2233 fprintf (file, "\t.long ");
2234 assemble_name (file, buf);
2235 fprintf (file, "\n");
2239 fprintf (file, "\t.tc\t");
2240 assemble_name (file, buf);
2241 fprintf (file, "[TC],");
2242 assemble_name (file, buf);
2243 fprintf (file, "\n");
2247 /* Figure out last used parameter register. The proper thing to do is
2248 to walk incoming args of the function. A function might have live
2249 parameter registers even if it has no incoming args. */
2251 for (last_parm_reg = 10;
2252 last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
2256 /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since
2257 it might be set up as the frame pointer. */
2259 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
2260 fprintf (file, "\tai %d,%d,0\n", j, i);
2262 /* Load location address into r3, and call mcount. */
2264 ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno);
2265 fprintf (file, "\tl 3,");
2266 assemble_name (file, buf);
2267 fprintf (file, "(2)\n\tbl .mcount\n");
2269 /* Restore parameter registers. */
2271 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
2272 fprintf (file, "\tai %d,%d,0\n", i, j);
2276 /* Adjust the cost of a scheduling dependency. Return the new cost of
2277 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
2280 rs6000_adjust_cost (insn, link, dep_insn, cost)
2286 if (! recog_memoized (insn))
2289 if (REG_NOTE_KIND (link) != 0)
2292 if (REG_NOTE_KIND (link) == 0)
2294 /* Data dependency; DEP_INSN writes a register that INSN reads some
2297 /* Tell the first scheduling pass about the latency between a mtctr
2298 and bctr (and mtlr and br/blr). The first scheduling pass will not
2299 know about this latency since the mtctr instruction, which has the
2300 latency associated to it, will be generated by reload. */
2301 if (get_attr_type (insn) == TYPE_JMPREG)
2302 return TARGET_POWER ? 5 : 4;
2304 /* Fall out to return default cost. */