1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
56 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
59 #ifndef TARGET_NO_PROTOTYPE
60 #define TARGET_NO_PROTOTYPE 0
63 #define EASY_VECTOR_15(n, x, y) ((n) >= -16 && (n) <= 15 \
64 && easy_vector_same (x, y))
66 #define EASY_VECTOR_15_ADD_SELF(n, x, y) ((n) >= 0x10 && (n) <= 0x1e \
68 && easy_vector_same (x, y))
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int toc_save_p; /* true if the TOC needs to be saved */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
116 /* Target cpu type */
118 enum processor_type rs6000_cpu;
119 struct rs6000_cpu_select rs6000_select[3] =
121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
127 /* Support adjust_priority scheduler hook
128 and -mprioritize-restricted-insns= option. */
129 const char *rs6000_sched_restricted_insns_priority_str;
130 int rs6000_sched_restricted_insns_priority;
132 /* Support for -msched-costly-dep option. */
133 const char *rs6000_sched_costly_dep_str;
134 enum rs6000_dependence_cost rs6000_sched_costly_dep;
136 /* Support for -minsert-sched-nops option. */
137 const char *rs6000_sched_insert_nops_str;
138 enum rs6000_nop_insertion rs6000_sched_insert_nops;
140 /* Size of long double */
141 const char *rs6000_long_double_size_string;
142 int rs6000_long_double_type_size;
144 /* Whether -mabi=altivec has appeared */
145 int rs6000_altivec_abi;
147 /* Whether VRSAVE instructions should be generated. */
148 int rs6000_altivec_vrsave;
150 /* String from -mvrsave= option. */
151 const char *rs6000_altivec_vrsave_string;
153 /* Nonzero if we want SPE ABI extensions. */
156 /* Whether isel instructions should be generated. */
159 /* Whether SPE simd instructions should be generated. */
162 /* Nonzero if floating point operations are done in the GPRs. */
163 int rs6000_float_gprs = 0;
165 /* String from -mfloat-gprs=. */
166 const char *rs6000_float_gprs_string;
168 /* String from -misel=. */
169 const char *rs6000_isel_string;
171 /* String from -mspe=. */
172 const char *rs6000_spe_string;
174 /* Set to nonzero once AIX common-mode calls have been defined. */
175 static GTY(()) int common_mode_defined;
177 /* Save information from a "cmpxx" operation until the branch or scc is
179 rtx rs6000_compare_op0, rs6000_compare_op1;
180 int rs6000_compare_fp_p;
182 /* Label number of label created for -mrelocatable, to call to so we can
183 get the address of the GOT section */
184 int rs6000_pic_labelno;
187 /* Which abi to adhere to */
188 const char *rs6000_abi_name;
190 /* Semantics of the small data area */
191 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
193 /* Which small data model to use */
194 const char *rs6000_sdata_name = (char *)0;
196 /* Counter for labels which are to be placed in .fixup. */
197 int fixuplabelno = 0;
200 /* Bit size of immediate TLS offsets and string from which it is decoded. */
201 int rs6000_tls_size = 32;
202 const char *rs6000_tls_size_string;
204 /* ABI enumeration available for subtarget to use. */
205 enum rs6000_abi rs6000_current_abi;
207 /* ABI string from -mabi= option. */
208 const char *rs6000_abi_string;
211 const char *rs6000_debug_name;
212 int rs6000_debug_stack; /* debug stack applications */
213 int rs6000_debug_arg; /* debug argument handling */
216 static GTY(()) tree opaque_V2SI_type_node;
217 static GTY(()) tree opaque_V2SF_type_node;
218 static GTY(()) tree opaque_p_V2SI_type_node;
220 const char *rs6000_traceback_name;
222 traceback_default = 0,
228 /* Flag to say the TOC is initialized */
230 char toc_label_name[10];
232 /* Alias set for saves and restores from the rs6000 stack. */
233 static int rs6000_sr_alias_set;
235 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
236 The only place that looks at this is rs6000_set_default_type_attributes;
237 everywhere else should rely on the presence or absence of a longcall
238 attribute on the function declaration. */
239 int rs6000_default_long_calls;
240 const char *rs6000_longcall_switch;
242 /* Control alignment for fields within structures. */
243 /* String from -malign-XXXXX. */
244 const char *rs6000_alignment_string;
245 int rs6000_alignment_flags;
247 struct builtin_description
249 /* mask is not const because we're going to alter it below. This
250 nonsense will go away when we rewrite the -march infrastructure
251 to give us more target flag bits. */
253 const enum insn_code icode;
254 const char *const name;
255 const enum rs6000_builtins code;
258 static bool rs6000_function_ok_for_sibcall (tree, tree);
259 static int num_insns_constant_wide (HOST_WIDE_INT);
260 static void validate_condition_mode (enum rtx_code, enum machine_mode);
261 static rtx rs6000_generate_compare (enum rtx_code);
262 static void rs6000_maybe_dead (rtx);
263 static void rs6000_emit_stack_tie (void);
264 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
265 static rtx spe_synthesize_frame_save (rtx);
266 static bool spe_func_has_64bit_regs_p (void);
267 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
269 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
270 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
271 static unsigned rs6000_hash_constant (rtx);
272 static unsigned toc_hash_function (const void *);
273 static int toc_hash_eq (const void *, const void *);
274 static int constant_pool_expr_1 (rtx, int *, int *);
275 static bool constant_pool_expr_p (rtx);
276 static bool toc_relative_expr_p (rtx);
277 static bool legitimate_small_data_p (enum machine_mode, rtx);
278 static bool legitimate_offset_address_p (enum machine_mode, rtx, int);
279 static bool legitimate_indexed_address_p (rtx, int);
280 static bool legitimate_indirect_address_p (rtx, int);
281 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
282 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
283 static struct machine_function * rs6000_init_machine_status (void);
284 static bool rs6000_assemble_integer (rtx, unsigned int, int);
285 #ifdef HAVE_GAS_HIDDEN
286 static void rs6000_assemble_visibility (tree, int);
288 static int rs6000_ra_ever_killed (void);
289 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
290 extern const struct attribute_spec rs6000_attribute_table[];
291 static void rs6000_set_default_type_attributes (tree);
292 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
293 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
294 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
296 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
297 static bool rs6000_return_in_memory (tree, tree);
298 static void rs6000_file_start (void);
300 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
301 static void rs6000_elf_asm_out_constructor (rtx, int);
302 static void rs6000_elf_asm_out_destructor (rtx, int);
303 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
304 static void rs6000_elf_unique_section (tree, int);
305 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
306 unsigned HOST_WIDE_INT);
307 static void rs6000_elf_encode_section_info (tree, rtx, int)
309 static bool rs6000_elf_in_small_data_p (tree);
312 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
313 static void rs6000_xcoff_asm_named_section (const char *, unsigned int);
314 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
315 static void rs6000_xcoff_unique_section (tree, int);
316 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
317 unsigned HOST_WIDE_INT);
318 static const char * rs6000_xcoff_strip_name_encoding (const char *);
319 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
320 static void rs6000_xcoff_file_start (void);
321 static void rs6000_xcoff_file_end (void);
324 static bool rs6000_binds_local_p (tree);
326 static int rs6000_use_dfa_pipeline_interface (void);
327 static int rs6000_variable_issue (FILE *, int, rtx, int);
328 static bool rs6000_rtx_costs (rtx, int, int, int *);
329 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
330 static bool is_microcoded_insn (rtx);
331 static int is_dispatch_slot_restricted (rtx);
332 static bool is_cracked_insn (rtx);
333 static bool is_branch_slot_insn (rtx);
334 static int rs6000_adjust_priority (rtx, int);
335 static int rs6000_issue_rate (void);
336 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
337 static rtx get_next_active_insn (rtx, rtx);
338 static bool insn_terminates_group_p (rtx , enum group_termination);
339 static bool is_costly_group (rtx *, rtx);
340 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
341 static int redefine_groups (FILE *, int, rtx, rtx);
342 static int pad_groups (FILE *, int, rtx, rtx);
343 static void rs6000_sched_finish (FILE *, int);
344 static int rs6000_use_sched_lookahead (void);
346 static void rs6000_init_builtins (void);
347 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
348 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
349 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
350 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
351 static void altivec_init_builtins (void);
352 static void rs6000_common_init_builtins (void);
353 static void rs6000_init_libfuncs (void);
355 static void enable_mask_for_builtins (struct builtin_description *, int,
356 enum rs6000_builtins,
357 enum rs6000_builtins);
358 static void spe_init_builtins (void);
359 static rtx spe_expand_builtin (tree, rtx, bool *);
360 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
361 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
362 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
363 static rs6000_stack_t *rs6000_stack_info (void);
364 static void debug_stack_info (rs6000_stack_t *);
366 static rtx altivec_expand_builtin (tree, rtx, bool *);
367 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
368 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
369 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
370 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
371 static rtx altivec_expand_predicate_builtin (enum insn_code,
372 const char *, tree, rtx);
373 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
374 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
375 static void rs6000_parse_abi_options (void);
376 static void rs6000_parse_alignment_option (void);
377 static void rs6000_parse_tls_size_option (void);
378 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
379 static int first_altivec_reg_to_save (void);
380 static unsigned int compute_vrsave_mask (void);
381 static void is_altivec_return_reg (rtx, void *);
382 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
383 int easy_vector_constant (rtx, enum machine_mode);
384 static int easy_vector_same (rtx, enum machine_mode);
385 static bool is_ev64_opaque_type (tree);
386 static rtx rs6000_dwarf_register_span (rtx);
387 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
388 static rtx rs6000_tls_get_addr (void);
389 static rtx rs6000_got_sym (void);
390 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
391 static const char *rs6000_get_some_local_dynamic_name (void);
392 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
393 static rtx rs6000_complex_function_value (enum machine_mode);
394 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
395 enum machine_mode, tree);
396 static rtx rs6000_mixed_function_arg (CUMULATIVE_ARGS *,
397 enum machine_mode, tree, int);
398 static void rs6000_move_block_from_reg(int regno, rtx x, int nregs);
399 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
400 enum machine_mode, tree,
403 static void macho_branch_islands (void);
404 static void add_compiler_branch_island (tree, tree, int);
405 static int no_previous_def (tree function_name);
406 static tree get_prev_label (tree function_name);
409 static tree rs6000_build_builtin_va_list (void);
411 /* Hash table stuff for keeping track of TOC entries. */
413 struct toc_hash_struct GTY(())
415 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
416 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
418 enum machine_mode key_mode;
422 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
424 /* Default register names. */
425 char rs6000_reg_names[][8] =
427 "0", "1", "2", "3", "4", "5", "6", "7",
428 "8", "9", "10", "11", "12", "13", "14", "15",
429 "16", "17", "18", "19", "20", "21", "22", "23",
430 "24", "25", "26", "27", "28", "29", "30", "31",
431 "0", "1", "2", "3", "4", "5", "6", "7",
432 "8", "9", "10", "11", "12", "13", "14", "15",
433 "16", "17", "18", "19", "20", "21", "22", "23",
434 "24", "25", "26", "27", "28", "29", "30", "31",
435 "mq", "lr", "ctr","ap",
436 "0", "1", "2", "3", "4", "5", "6", "7",
438 /* AltiVec registers. */
439 "0", "1", "2", "3", "4", "5", "6", "7",
440 "8", "9", "10", "11", "12", "13", "14", "15",
441 "16", "17", "18", "19", "20", "21", "22", "23",
442 "24", "25", "26", "27", "28", "29", "30", "31",
448 #ifdef TARGET_REGNAMES
449 static const char alt_reg_names[][8] =
451 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
452 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
453 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
454 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
455 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
456 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
457 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
458 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
459 "mq", "lr", "ctr", "ap",
460 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
462 /* AltiVec registers. */
463 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
464 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
465 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
466 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
473 #ifndef MASK_STRICT_ALIGN
474 #define MASK_STRICT_ALIGN 0
476 #ifndef TARGET_PROFILE_KERNEL
477 #define TARGET_PROFILE_KERNEL 0
480 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
481 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
483 /* Return 1 for a symbol ref for a thread-local storage symbol. */
484 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
485 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
487 /* Initialize the GCC target structure. */
488 #undef TARGET_ATTRIBUTE_TABLE
489 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
490 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
491 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
493 #undef TARGET_ASM_ALIGNED_DI_OP
494 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
496 /* Default unaligned ops are only provided for ELF. Find the ops needed
497 for non-ELF systems. */
498 #ifndef OBJECT_FORMAT_ELF
500 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
502 #undef TARGET_ASM_UNALIGNED_HI_OP
503 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
504 #undef TARGET_ASM_UNALIGNED_SI_OP
505 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
506 #undef TARGET_ASM_UNALIGNED_DI_OP
507 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
510 #undef TARGET_ASM_UNALIGNED_HI_OP
511 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
512 #undef TARGET_ASM_UNALIGNED_SI_OP
513 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
517 /* This hook deals with fixups for relocatable code and DI-mode objects
519 #undef TARGET_ASM_INTEGER
520 #define TARGET_ASM_INTEGER rs6000_assemble_integer
522 #ifdef HAVE_GAS_HIDDEN
523 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
524 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
527 #undef TARGET_HAVE_TLS
528 #define TARGET_HAVE_TLS HAVE_AS_TLS
530 #undef TARGET_CANNOT_FORCE_CONST_MEM
531 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
533 #undef TARGET_ASM_FUNCTION_PROLOGUE
534 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
535 #undef TARGET_ASM_FUNCTION_EPILOGUE
536 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
538 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
539 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE rs6000_use_dfa_pipeline_interface
540 #undef TARGET_SCHED_VARIABLE_ISSUE
541 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
543 #undef TARGET_SCHED_ISSUE_RATE
544 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
545 #undef TARGET_SCHED_ADJUST_COST
546 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
547 #undef TARGET_SCHED_ADJUST_PRIORITY
548 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
549 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
550 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
551 #undef TARGET_SCHED_FINISH
552 #define TARGET_SCHED_FINISH rs6000_sched_finish
554 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
555 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
557 #undef TARGET_INIT_BUILTINS
558 #define TARGET_INIT_BUILTINS rs6000_init_builtins
560 #undef TARGET_EXPAND_BUILTIN
561 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
563 #undef TARGET_INIT_LIBFUNCS
564 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
567 #undef TARGET_BINDS_LOCAL_P
568 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
571 #undef TARGET_ASM_OUTPUT_MI_THUNK
572 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
574 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
575 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
577 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
578 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
580 #undef TARGET_RTX_COSTS
581 #define TARGET_RTX_COSTS rs6000_rtx_costs
582 #undef TARGET_ADDRESS_COST
583 #define TARGET_ADDRESS_COST hook_int_rtx_0
585 #undef TARGET_VECTOR_OPAQUE_P
586 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
588 #undef TARGET_DWARF_REGISTER_SPAN
589 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
591 /* On rs6000, function arguments are promoted, as are function return
593 #undef TARGET_PROMOTE_FUNCTION_ARGS
594 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
595 #undef TARGET_PROMOTE_FUNCTION_RETURN
596 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
598 /* Structure return values are passed as an extra parameter. */
599 #undef TARGET_STRUCT_VALUE_RTX
600 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
602 #undef TARGET_RETURN_IN_MEMORY
603 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
605 #undef TARGET_SETUP_INCOMING_VARARGS
606 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
608 /* Always strict argument naming on rs6000. */
609 #undef TARGET_STRICT_ARGUMENT_NAMING
610 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
611 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
612 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
614 #undef TARGET_BUILD_BUILTIN_VA_LIST
615 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
617 struct gcc_target targetm = TARGET_INITIALIZER;
619 /* Override command line options. Mostly we process the processor
620 type and sometimes adjust other TARGET_ options. */
623 rs6000_override_options (const char *default_cpu)
626 struct rs6000_cpu_select *ptr;
629 /* Simplifications for entries below. */
632 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
633 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
636 /* This table occasionally claims that a processor does not support
637 a particular feature even though it does, but the feature is slower
638 than the alternative. Thus, it shouldn't be relied on as a
639 complete description of the processor's support.
641 Please keep this list in order, and don't forget to update the
642 documentation in invoke.texi when adding a new processor or
646 const char *const name; /* Canonical processor name. */
647 const enum processor_type processor; /* Processor type enum value. */
648 const int target_enable; /* Target flags to enable. */
649 } const processor_target_table[]
650 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
651 {"403", PROCESSOR_PPC403,
652 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
653 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
654 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
655 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
656 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
657 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
658 {"601", PROCESSOR_PPC601,
659 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
660 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
661 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
662 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
663 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
664 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
665 {"620", PROCESSOR_PPC620,
666 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
667 {"630", PROCESSOR_PPC630,
668 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
669 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
670 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
671 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
672 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
673 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
674 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
675 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
676 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
677 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
678 {"970", PROCESSOR_POWER4,
679 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
680 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
681 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
682 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
683 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
684 {"G5", PROCESSOR_POWER4,
685 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
686 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
687 {"power2", PROCESSOR_POWER,
688 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
689 {"power3", PROCESSOR_PPC630,
690 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
691 {"power4", PROCESSOR_POWER4,
692 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
693 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
694 {"powerpc64", PROCESSOR_POWERPC64,
695 POWERPC_BASE_MASK | MASK_POWERPC64},
696 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
697 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
698 {"rios2", PROCESSOR_RIOS2,
699 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
700 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
701 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
702 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
705 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
707 /* Save current -mmultiple/-mno-multiple status. */
708 int multiple = TARGET_MULTIPLE;
709 /* Save current -mstring/-mno-string status. */
710 int string = TARGET_STRING;
712 /* Some OSs don't support saving the high part of 64-bit registers on
713 context switch. Other OSs don't support saving Altivec registers.
714 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
715 settings; if the user wants either, the user must explicitly specify
716 them and we won't interfere with the user's specification. */
719 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
720 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
721 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
724 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
725 #ifdef OS_MISSING_POWERPC64
726 if (OS_MISSING_POWERPC64)
727 set_masks &= ~MASK_POWERPC64;
729 #ifdef OS_MISSING_ALTIVEC
730 if (OS_MISSING_ALTIVEC)
731 set_masks &= ~MASK_ALTIVEC;
734 /* Identify the processor type. */
735 rs6000_select[0].string = default_cpu;
736 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
738 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
740 ptr = &rs6000_select[i];
741 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
743 for (j = 0; j < ptt_size; j++)
744 if (! strcmp (ptr->string, processor_target_table[j].name))
747 rs6000_cpu = processor_target_table[j].processor;
751 target_flags &= ~set_masks;
752 target_flags |= (processor_target_table[j].target_enable
759 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
766 /* If we are optimizing big endian systems for space, use the load/store
767 multiple and string instructions. */
768 if (BYTES_BIG_ENDIAN && optimize_size)
769 target_flags |= MASK_MULTIPLE | MASK_STRING;
771 /* If -mmultiple or -mno-multiple was explicitly used, don't
772 override with the processor default */
773 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
774 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
776 /* If -mstring or -mno-string was explicitly used, don't override
777 with the processor default. */
778 if ((target_flags_explicit & MASK_STRING) != 0)
779 target_flags = (target_flags & ~MASK_STRING) | string;
781 /* Don't allow -mmultiple or -mstring on little endian systems
782 unless the cpu is a 750, because the hardware doesn't support the
783 instructions used in little endian mode, and causes an alignment
784 trap. The 750 does not cause an alignment trap (except when the
785 target is unaligned). */
787 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
791 target_flags &= ~MASK_MULTIPLE;
792 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
793 warning ("-mmultiple is not supported on little endian systems");
798 target_flags &= ~MASK_STRING;
799 if ((target_flags_explicit & MASK_STRING) != 0)
800 warning ("-mstring is not supported on little endian systems");
804 /* Set debug flags */
805 if (rs6000_debug_name)
807 if (! strcmp (rs6000_debug_name, "all"))
808 rs6000_debug_stack = rs6000_debug_arg = 1;
809 else if (! strcmp (rs6000_debug_name, "stack"))
810 rs6000_debug_stack = 1;
811 else if (! strcmp (rs6000_debug_name, "arg"))
812 rs6000_debug_arg = 1;
814 error ("unknown -mdebug-%s switch", rs6000_debug_name);
817 if (rs6000_traceback_name)
819 if (! strncmp (rs6000_traceback_name, "full", 4))
820 rs6000_traceback = traceback_full;
821 else if (! strncmp (rs6000_traceback_name, "part", 4))
822 rs6000_traceback = traceback_part;
823 else if (! strncmp (rs6000_traceback_name, "no", 2))
824 rs6000_traceback = traceback_none;
826 error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'",
827 rs6000_traceback_name);
830 /* Set size of long double */
831 rs6000_long_double_type_size = 64;
832 if (rs6000_long_double_size_string)
835 int size = strtol (rs6000_long_double_size_string, &tail, 10);
836 if (*tail != '\0' || (size != 64 && size != 128))
837 error ("Unknown switch -mlong-double-%s",
838 rs6000_long_double_size_string);
840 rs6000_long_double_type_size = size;
843 /* Handle -mabi= options. */
844 rs6000_parse_abi_options ();
846 /* Handle -malign-XXXXX option. */
847 rs6000_parse_alignment_option ();
849 /* Handle generic -mFOO=YES/NO options. */
850 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
851 &rs6000_altivec_vrsave);
852 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
854 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
855 rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string,
858 /* Handle -mtls-size option. */
859 rs6000_parse_tls_size_option ();
861 #ifdef SUBTARGET_OVERRIDE_OPTIONS
862 SUBTARGET_OVERRIDE_OPTIONS;
864 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
865 SUBSUBTARGET_OVERRIDE_OPTIONS;
870 /* The e500 does not have string instructions, and we set
871 MASK_STRING above when optimizing for size. */
872 if ((target_flags & MASK_STRING) != 0)
873 target_flags = target_flags & ~MASK_STRING;
875 /* No SPE means 64-bit long doubles, even if an E500. */
876 if (rs6000_spe_string != 0
877 && !strcmp (rs6000_spe_string, "no"))
878 rs6000_long_double_type_size = 64;
880 else if (rs6000_select[1].string != NULL)
882 /* For the powerpc-eabispe configuration, we set all these by
883 default, so let's unset them if we manually set another
884 CPU that is not the E500. */
885 if (rs6000_abi_string == 0)
887 if (rs6000_spe_string == 0)
889 if (rs6000_float_gprs_string == 0)
890 rs6000_float_gprs = 0;
891 if (rs6000_isel_string == 0)
893 if (rs6000_long_double_size_string == 0)
894 rs6000_long_double_type_size = 64;
897 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
898 using TARGET_OPTIONS to handle a toggle switch, but we're out of
899 bits in target_flags so TARGET_SWITCHES cannot be used.
900 Assumption here is that rs6000_longcall_switch points into the
901 text of the complete option, rather than being a copy, so we can
902 scan back for the presence or absence of the no- modifier. */
903 if (rs6000_longcall_switch)
905 const char *base = rs6000_longcall_switch;
906 while (base[-1] != 'm') base--;
908 if (*rs6000_longcall_switch != '\0')
909 error ("invalid option `%s'", base);
910 rs6000_default_long_calls = (base[0] != 'n');
913 /* Handle -mprioritize-restricted-insns option. */
914 rs6000_sched_restricted_insns_priority = DEFAULT_RESTRICTED_INSNS_PRIORITY;
915 if (rs6000_sched_restricted_insns_priority_str)
916 rs6000_sched_restricted_insns_priority =
917 atoi (rs6000_sched_restricted_insns_priority_str);
919 /* Handle -msched-costly-dep option. */
920 rs6000_sched_costly_dep = DEFAULT_SCHED_COSTLY_DEP;
921 if (rs6000_sched_costly_dep_str)
923 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
924 rs6000_sched_costly_dep = no_dep_costly;
925 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
926 rs6000_sched_costly_dep = all_deps_costly;
927 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
928 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
929 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
930 rs6000_sched_costly_dep = store_to_load_dep_costly;
932 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
935 /* Handle -minsert-sched-nops option. */
936 rs6000_sched_insert_nops = DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME;
937 if (rs6000_sched_insert_nops_str)
939 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
940 rs6000_sched_insert_nops = sched_finish_none;
941 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
942 rs6000_sched_insert_nops = sched_finish_pad_groups;
943 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
944 rs6000_sched_insert_nops = sched_finish_regroup_exact;
946 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
949 #ifdef TARGET_REGNAMES
950 /* If the user desires alternate register names, copy in the
951 alternate names now. */
953 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
956 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
957 If -maix-struct-return or -msvr4-struct-return was explicitly
958 used, don't override with the ABI default. */
959 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
961 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
962 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
964 target_flags |= MASK_AIX_STRUCT_RET;
967 if (TARGET_LONG_DOUBLE_128
968 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
969 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
971 /* Allocate an alias set for register saves & restores from stack. */
972 rs6000_sr_alias_set = new_alias_set ();
975 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
977 /* We can only guarantee the availability of DI pseudo-ops when
978 assembling for 64-bit targets. */
981 targetm.asm_out.aligned_op.di = NULL;
982 targetm.asm_out.unaligned_op.di = NULL;
985 /* Set maximum branch target alignment at two instructions, eight bytes. */
986 align_jumps_max_skip = 8;
987 align_loops_max_skip = 8;
989 /* Arrange to save and restore machine status around nested functions. */
990 init_machine_status = rs6000_init_machine_status;
993 /* Handle generic options of the form -mfoo=yes/no.
994 NAME is the option name.
995 VALUE is the option value.
996 FLAG is the pointer to the flag where to store a 1 or 0, depending on
997 whether the option value is 'yes' or 'no' respectively. */
999 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1003 else if (!strcmp (value, "yes"))
1005 else if (!strcmp (value, "no"))
1008 error ("unknown -m%s= option specified: '%s'", name, value);
1011 /* Handle -mabi= options. */
1013 rs6000_parse_abi_options (void)
1015 if (rs6000_abi_string == 0)
1017 else if (! strcmp (rs6000_abi_string, "altivec"))
1018 rs6000_altivec_abi = 1;
1019 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1020 rs6000_altivec_abi = 0;
1021 else if (! strcmp (rs6000_abi_string, "spe"))
1024 if (!TARGET_SPE_ABI)
1025 error ("not configured for ABI: '%s'", rs6000_abi_string);
1028 else if (! strcmp (rs6000_abi_string, "no-spe"))
1031 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1034 /* Handle -malign-XXXXXX options. */
1036 rs6000_parse_alignment_option (void)
1038 if (rs6000_alignment_string == 0)
1040 else if (! strcmp (rs6000_alignment_string, "power"))
1041 rs6000_alignment_flags = MASK_ALIGN_POWER;
1042 else if (! strcmp (rs6000_alignment_string, "natural"))
1043 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1045 error ("unknown -malign-XXXXX option specified: '%s'",
1046 rs6000_alignment_string);
1049 /* Validate and record the size specified with the -mtls-size option. */
1052 rs6000_parse_tls_size_option (void)
1054 if (rs6000_tls_size_string == 0)
1056 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1057 rs6000_tls_size = 16;
1058 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1059 rs6000_tls_size = 32;
1060 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1061 rs6000_tls_size = 64;
1063 error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string);
1067 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1071 /* Do anything needed at the start of the asm file. */
1074 rs6000_file_start (void)
1078 const char *start = buffer;
1079 struct rs6000_cpu_select *ptr;
1080 const char *default_cpu = TARGET_CPU_DEFAULT;
1081 FILE *file = asm_out_file;
1083 default_file_start ();
1085 #ifdef TARGET_BI_ARCH
1086 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1090 if (flag_verbose_asm)
1092 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1093 rs6000_select[0].string = default_cpu;
1095 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1097 ptr = &rs6000_select[i];
1098 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1100 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1105 #ifdef USING_ELFOS_H
1106 switch (rs6000_sdata)
1108 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1109 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1110 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1111 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1114 if (rs6000_sdata && g_switch_value)
1116 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1127 /* Return nonzero if this function is known to have a null epilogue. */
1130 direct_return (void)
1132 if (reload_completed)
1134 rs6000_stack_t *info = rs6000_stack_info ();
1136 if (info->first_gp_reg_save == 32
1137 && info->first_fp_reg_save == 64
1138 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1139 && ! info->lr_save_p
1140 && ! info->cr_save_p
1141 && info->vrsave_mask == 0
1149 /* Returns 1 always. */
1152 any_operand (rtx op ATTRIBUTE_UNUSED,
1153 enum machine_mode mode ATTRIBUTE_UNUSED)
1158 /* Returns 1 if op is the count register. */
1160 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1162 if (GET_CODE (op) != REG)
1165 if (REGNO (op) == COUNT_REGISTER_REGNUM)
1168 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1174 /* Returns 1 if op is an altivec register. */
1176 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1179 return (register_operand (op, mode)
1180 && (GET_CODE (op) != REG
1181 || REGNO (op) > FIRST_PSEUDO_REGISTER
1182 || ALTIVEC_REGNO_P (REGNO (op))));
1186 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1188 if (GET_CODE (op) != REG)
1191 if (XER_REGNO_P (REGNO (op)))
1197 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1198 by such constants completes more quickly. */
1201 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1203 return ( GET_CODE (op) == CONST_INT
1204 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1207 /* Return 1 if OP is a constant that can fit in a D field. */
1210 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1212 return (GET_CODE (op) == CONST_INT
1213 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1216 /* Similar for an unsigned D field. */
1219 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1221 return (GET_CODE (op) == CONST_INT
1222 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1225 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1228 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1230 return (GET_CODE (op) == CONST_INT
1231 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1234 /* Returns 1 if OP is a CONST_INT that is a positive value
1235 and an exact power of 2. */
1238 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1240 return (GET_CODE (op) == CONST_INT
1242 && exact_log2 (INTVAL (op)) >= 0);
1245 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1249 gpc_reg_operand (rtx op, enum machine_mode mode)
1251 return (register_operand (op, mode)
1252 && (GET_CODE (op) != REG
1253 || (REGNO (op) >= ARG_POINTER_REGNUM
1254 && !XER_REGNO_P (REGNO (op)))
1255 || REGNO (op) < MQ_REGNO));
1258 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1262 cc_reg_operand (rtx op, enum machine_mode mode)
1264 return (register_operand (op, mode)
1265 && (GET_CODE (op) != REG
1266 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1267 || CR_REGNO_P (REGNO (op))));
1270 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1271 CR field that isn't CR0. */
1274 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1276 return (register_operand (op, mode)
1277 && (GET_CODE (op) != REG
1278 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1279 || CR_REGNO_NOT_CR0_P (REGNO (op))));
1282 /* Returns 1 if OP is either a constant integer valid for a D-field or
1283 a non-special register. If a register, it must be in the proper
1284 mode unless MODE is VOIDmode. */
1287 reg_or_short_operand (rtx op, enum machine_mode mode)
1289 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1292 /* Similar, except check if the negation of the constant would be
1293 valid for a D-field. */
1296 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1298 if (GET_CODE (op) == CONST_INT)
1299 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
1301 return gpc_reg_operand (op, mode);
1304 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1305 a non-special register. If a register, it must be in the proper
1306 mode unless MODE is VOIDmode. */
1309 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1311 if (gpc_reg_operand (op, mode))
1313 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1320 /* Return 1 if the operand is either a register or an integer whose
1321 high-order 16 bits are zero. */
1324 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1326 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1329 /* Return 1 is the operand is either a non-special register or ANY
1330 constant integer. */
1333 reg_or_cint_operand (rtx op, enum machine_mode mode)
1335 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1338 /* Return 1 is the operand is either a non-special register or ANY
1339 32-bit signed constant integer. */
1342 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
1344 return (gpc_reg_operand (op, mode)
1345 || (GET_CODE (op) == CONST_INT
1346 #if HOST_BITS_PER_WIDE_INT != 32
1347 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
1348 < (unsigned HOST_WIDE_INT) 0x100000000ll)
1353 /* Return 1 is the operand is either a non-special register or a 32-bit
1354 signed constant integer valid for 64-bit addition. */
1357 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
1359 return (gpc_reg_operand (op, mode)
1360 || (GET_CODE (op) == CONST_INT
1361 #if HOST_BITS_PER_WIDE_INT == 32
1362 && INTVAL (op) < 0x7fff8000
1364 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
1370 /* Return 1 is the operand is either a non-special register or a 32-bit
1371 signed constant integer valid for 64-bit subtraction. */
1374 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
1376 return (gpc_reg_operand (op, mode)
1377 || (GET_CODE (op) == CONST_INT
1378 #if HOST_BITS_PER_WIDE_INT == 32
1379 && (- INTVAL (op)) < 0x7fff8000
1381 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
1387 /* Return 1 is the operand is either a non-special register or ANY
1388 32-bit unsigned constant integer. */
1391 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
1393 if (GET_CODE (op) == CONST_INT)
1395 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
1397 if (GET_MODE_BITSIZE (mode) <= 32)
1400 if (INTVAL (op) < 0)
1404 return ((INTVAL (op) & GET_MODE_MASK (mode)
1405 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
1407 else if (GET_CODE (op) == CONST_DOUBLE)
1409 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1413 return CONST_DOUBLE_HIGH (op) == 0;
1416 return gpc_reg_operand (op, mode);
1419 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
1422 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1424 return (GET_CODE (op) == SYMBOL_REF
1425 || GET_CODE (op) == CONST
1426 || GET_CODE (op) == LABEL_REF);
1429 /* Return 1 if the operand is a simple references that can be loaded via
1430 the GOT (labels involving addition aren't allowed). */
1433 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1435 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
1438 /* Return the number of instructions it takes to form a constant in an
1439 integer register. */
1442 num_insns_constant_wide (HOST_WIDE_INT value)
1444 /* signed constant loadable with {cal|addi} */
1445 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1448 /* constant loadable with {cau|addis} */
1449 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1452 #if HOST_BITS_PER_WIDE_INT == 64
1453 else if (TARGET_POWERPC64)
1455 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1456 HOST_WIDE_INT high = value >> 31;
1458 if (high == 0 || high == -1)
1464 return num_insns_constant_wide (high) + 1;
1466 return (num_insns_constant_wide (high)
1467 + num_insns_constant_wide (low) + 1);
1476 num_insns_constant (rtx op, enum machine_mode mode)
1478 if (GET_CODE (op) == CONST_INT)
1480 #if HOST_BITS_PER_WIDE_INT == 64
1481 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1482 && mask64_operand (op, mode))
1486 return num_insns_constant_wide (INTVAL (op));
1489 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1494 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1495 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1496 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1499 else if (GET_CODE (op) == CONST_DOUBLE)
1505 int endian = (WORDS_BIG_ENDIAN == 0);
1507 if (mode == VOIDmode || mode == DImode)
1509 high = CONST_DOUBLE_HIGH (op);
1510 low = CONST_DOUBLE_LOW (op);
1514 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1515 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1517 low = l[1 - endian];
1521 return (num_insns_constant_wide (low)
1522 + num_insns_constant_wide (high));
1526 if (high == 0 && low >= 0)
1527 return num_insns_constant_wide (low);
1529 else if (high == -1 && low < 0)
1530 return num_insns_constant_wide (low);
1532 else if (mask64_operand (op, mode))
1536 return num_insns_constant_wide (high) + 1;
1539 return (num_insns_constant_wide (high)
1540 + num_insns_constant_wide (low) + 1);
1548 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
1549 register with one instruction per word. We only do this if we can
1550 safely read CONST_DOUBLE_{LOW,HIGH}. */
1553 easy_fp_constant (rtx op, enum machine_mode mode)
1555 if (GET_CODE (op) != CONST_DOUBLE
1556 || GET_MODE (op) != mode
1557 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
1560 /* Consider all constants with -msoft-float to be easy. */
1561 if ((TARGET_SOFT_FLOAT || !TARGET_FPRS)
1565 /* If we are using V.4 style PIC, consider all constants to be hard. */
1566 if (flag_pic && DEFAULT_ABI == ABI_V4)
1569 #ifdef TARGET_RELOCATABLE
1570 /* Similarly if we are using -mrelocatable, consider all constants
1572 if (TARGET_RELOCATABLE)
1581 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1582 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
1584 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1585 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
1586 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
1587 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
1590 else if (mode == DFmode)
1595 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1596 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
1598 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1599 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
1602 else if (mode == SFmode)
1607 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1608 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1610 return num_insns_constant_wide (l) == 1;
1613 else if (mode == DImode)
1614 return ((TARGET_POWERPC64
1615 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
1616 || (num_insns_constant (op, DImode) <= 2));
1618 else if (mode == SImode)
1624 /* Return nonzero if all elements of a vector have the same value. */
1627 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1631 units = CONST_VECTOR_NUNITS (op);
1633 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1634 for (i = 1; i < units; ++i)
1635 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1642 /* Return 1 if the operand is a CONST_INT and can be put into a
1643 register without using memory. */
1646 easy_vector_constant (rtx op, enum machine_mode mode)
1650 if (GET_CODE (op) != CONST_VECTOR
1655 if (zero_constant (op, mode)
1656 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
1657 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
1660 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
1663 if (TARGET_SPE && mode == V1DImode)
1666 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1667 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
1669 /* Limit SPE vectors to 15 bits signed. These we can generate with:
1671 evmergelo r0, r0, r0
1674 I don't know how efficient it would be to allow bigger constants,
1675 considering we'll have an extra 'ori' for every 'li'. I doubt 5
1676 instructions is better than a 64-bit memory load, but I don't
1677 have the e500 timing specs. */
1678 if (TARGET_SPE && mode == V2SImode
1679 && cst >= -0x7fff && cst <= 0x7fff
1680 && cst2 >= -0x7fff && cst2 <= 0x7fff)
1687 if (EASY_VECTOR_15 (cst, op, mode))
1689 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1693 if (EASY_VECTOR_15 (cst, op, mode))
1695 if ((cst & 0xff) != ((cst >> 8) & 0xff))
1699 if (EASY_VECTOR_15 (cst, op, mode))
1705 if (TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode))
1711 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
1714 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
1718 if (!easy_vector_constant (op, mode))
1721 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1723 return TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode);
1727 output_vec_const_move (rtx *operands)
1730 enum machine_mode mode;
1736 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
1737 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
1738 mode = GET_MODE (dest);
1742 if (zero_constant (vec, mode))
1743 return "vxor %0,%0,%0";
1744 else if (EASY_VECTOR_15_ADD_SELF (cst, vec, mode))
1746 else if (easy_vector_constant (vec, mode))
1748 operands[1] = GEN_INT (cst);
1752 if (EASY_VECTOR_15 (cst, vec, mode))
1754 operands[1] = GEN_INT (cst);
1755 return "vspltisw %0,%1";
1759 if (EASY_VECTOR_15 (cst, vec, mode))
1761 operands[1] = GEN_INT (cst);
1762 return "vspltish %0,%1";
1766 if (EASY_VECTOR_15 (cst, vec, mode))
1768 operands[1] = GEN_INT (cst);
1769 return "vspltisb %0,%1";
1781 /* Vector constant 0 is handled as a splitter of V2SI, and in the
1782 pattern of V1DI, V4HI, and V2SF.
1784 FIXME: We should probably return # and add post reload
1785 splitters for these, but this way is so easy ;-).
1787 operands[1] = GEN_INT (cst);
1788 operands[2] = GEN_INT (cst2);
1790 return "li %0,%1\n\tevmergelo %0,%0,%0";
1792 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
1798 /* Return 1 if the operand is the constant 0. This works for scalars
1799 as well as vectors. */
1801 zero_constant (rtx op, enum machine_mode mode)
1803 return op == CONST0_RTX (mode);
1806 /* Return 1 if the operand is 0.0. */
1808 zero_fp_constant (rtx op, enum machine_mode mode)
1810 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
1813 /* Return 1 if the operand is in volatile memory. Note that during
1814 the RTL generation phase, memory_operand does not return TRUE for
1815 volatile memory references. So this function allows us to
1816 recognize volatile references where its safe. */
1819 volatile_mem_operand (rtx op, enum machine_mode mode)
1821 if (GET_CODE (op) != MEM)
1824 if (!MEM_VOLATILE_P (op))
1827 if (mode != GET_MODE (op))
1830 if (reload_completed)
1831 return memory_operand (op, mode);
1833 if (reload_in_progress)
1834 return strict_memory_address_p (mode, XEXP (op, 0));
1836 return memory_address_p (mode, XEXP (op, 0));
1839 /* Return 1 if the operand is an offsettable memory operand. */
1842 offsettable_mem_operand (rtx op, enum machine_mode mode)
1844 return ((GET_CODE (op) == MEM)
1845 && offsettable_address_p (reload_completed || reload_in_progress,
1846 mode, XEXP (op, 0)));
1849 /* Return 1 if the operand is either an easy FP constant (see above) or
1853 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
1855 return memory_operand (op, mode) || easy_fp_constant (op, mode);
1858 /* Return 1 if the operand is either a non-special register or an item
1859 that can be used as the operand of a `mode' add insn. */
1862 add_operand (rtx op, enum machine_mode mode)
1864 if (GET_CODE (op) == CONST_INT)
1865 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1866 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1868 return gpc_reg_operand (op, mode);
1871 /* Return 1 if OP is a constant but not a valid add_operand. */
1874 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1876 return (GET_CODE (op) == CONST_INT
1877 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1878 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1881 /* Return 1 if the operand is a non-special register or a constant that
1882 can be used as the operand of an OR or XOR insn on the RS/6000. */
1885 logical_operand (rtx op, enum machine_mode mode)
1887 HOST_WIDE_INT opl, oph;
1889 if (gpc_reg_operand (op, mode))
1892 if (GET_CODE (op) == CONST_INT)
1894 opl = INTVAL (op) & GET_MODE_MASK (mode);
1896 #if HOST_BITS_PER_WIDE_INT <= 32
1897 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
1901 else if (GET_CODE (op) == CONST_DOUBLE)
1903 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1906 opl = CONST_DOUBLE_LOW (op);
1907 oph = CONST_DOUBLE_HIGH (op);
1914 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
1915 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
1918 /* Return 1 if C is a constant that is not a logical operand (as
1919 above), but could be split into one. */
1922 non_logical_cint_operand (rtx op, enum machine_mode mode)
1924 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
1925 && ! logical_operand (op, mode)
1926 && reg_or_logical_cint_operand (op, mode));
1929 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
1930 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
1931 Reject all ones and all zeros, since these should have been optimized
1932 away and confuse the making of MB and ME. */
1935 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1937 HOST_WIDE_INT c, lsb;
1939 if (GET_CODE (op) != CONST_INT)
1944 /* Fail in 64-bit mode if the mask wraps around because the upper
1945 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
1946 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
1949 /* We don't change the number of transitions by inverting,
1950 so make sure we start with the LS bit zero. */
1954 /* Reject all zeros or all ones. */
1958 /* Find the first transition. */
1961 /* Invert to look for a second transition. */
1964 /* Erase first transition. */
1967 /* Find the second transition (if any). */
1970 /* Match if all the bits above are 1's (or c is zero). */
1974 /* Return 1 for the PowerPC64 rlwinm corner case. */
1977 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1979 HOST_WIDE_INT c, lsb;
1981 if (GET_CODE (op) != CONST_INT)
1986 if ((c & 0x80000001) != 0x80000001)
2000 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2001 It is if there are no more than one 1->0 or 0->1 transitions.
2002 Reject all zeros, since zero should have been optimized away and
2003 confuses the making of MB and ME. */
2006 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2008 if (GET_CODE (op) == CONST_INT)
2010 HOST_WIDE_INT c, lsb;
2014 /* Reject all zeros. */
2018 /* We don't change the number of transitions by inverting,
2019 so make sure we start with the LS bit zero. */
2023 /* Find the transition, and check that all bits above are 1's. */
2026 /* Match if all the bits above are 1's (or c is zero). */
2032 /* Like mask64_operand, but allow up to three transitions. This
2033 predicate is used by insn patterns that generate two rldicl or
2034 rldicr machine insns. */
2037 mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2039 if (GET_CODE (op) == CONST_INT)
2041 HOST_WIDE_INT c, lsb;
2045 /* Disallow all zeros. */
2049 /* We don't change the number of transitions by inverting,
2050 so make sure we start with the LS bit zero. */
2054 /* Find the first transition. */
2057 /* Invert to look for a second transition. */
2060 /* Erase first transition. */
2063 /* Find the second transition. */
2066 /* Invert to look for a third transition. */
2069 /* Erase second transition. */
2072 /* Find the third transition (if any). */
2075 /* Match if all the bits above are 1's (or c is zero). */
2081 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2082 implement ANDing by the mask IN. */
2084 build_mask64_2_operands (rtx in, rtx *out)
2086 #if HOST_BITS_PER_WIDE_INT >= 64
2087 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2090 if (GET_CODE (in) != CONST_INT)
2096 /* Assume c initially something like 0x00fff000000fffff. The idea
2097 is to rotate the word so that the middle ^^^^^^ group of zeros
2098 is at the MS end and can be cleared with an rldicl mask. We then
2099 rotate back and clear off the MS ^^ group of zeros with a
2101 c = ~c; /* c == 0xff000ffffff00000 */
2102 lsb = c & -c; /* lsb == 0x0000000000100000 */
2103 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2104 c = ~c; /* c == 0x00fff000000fffff */
2105 c &= -lsb; /* c == 0x00fff00000000000 */
2106 lsb = c & -c; /* lsb == 0x0000100000000000 */
2107 c = ~c; /* c == 0xff000fffffffffff */
2108 c &= -lsb; /* c == 0xff00000000000000 */
2110 while ((lsb >>= 1) != 0)
2111 shift++; /* shift == 44 on exit from loop */
2112 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2113 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2114 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2118 /* Assume c initially something like 0xff000f0000000000. The idea
2119 is to rotate the word so that the ^^^ middle group of zeros
2120 is at the LS end and can be cleared with an rldicr mask. We then
2121 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2123 lsb = c & -c; /* lsb == 0x0000010000000000 */
2124 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2125 c = ~c; /* c == 0x00fff0ffffffffff */
2126 c &= -lsb; /* c == 0x00fff00000000000 */
2127 lsb = c & -c; /* lsb == 0x0000100000000000 */
2128 c = ~c; /* c == 0xff000fffffffffff */
2129 c &= -lsb; /* c == 0xff00000000000000 */
2131 while ((lsb >>= 1) != 0)
2132 shift++; /* shift == 44 on exit from loop */
2133 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2134 m1 >>= shift; /* m1 == 0x0000000000000fff */
2135 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2138 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2139 masks will be all 1's. We are guaranteed more than one transition. */
2140 out[0] = GEN_INT (64 - shift);
2141 out[1] = GEN_INT (m1);
2142 out[2] = GEN_INT (shift);
2143 out[3] = GEN_INT (m2);
2151 /* Return 1 if the operand is either a non-special register or a constant
2152 that can be used as the operand of a PowerPC64 logical AND insn. */
2155 and64_operand (rtx op, enum machine_mode mode)
2157 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2158 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2160 return (logical_operand (op, mode) || mask64_operand (op, mode));
2163 /* Like the above, but also match constants that can be implemented
2164 with two rldicl or rldicr insns. */
2167 and64_2_operand (rtx op, enum machine_mode mode)
2169 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2170 return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
2172 return logical_operand (op, mode) || mask64_2_operand (op, mode);
2175 /* Return 1 if the operand is either a non-special register or a
2176 constant that can be used as the operand of an RS/6000 logical AND insn. */
2179 and_operand (rtx op, enum machine_mode mode)
2181 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2182 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2184 return (logical_operand (op, mode) || mask_operand (op, mode));
2187 /* Return 1 if the operand is a general register or memory operand. */
2190 reg_or_mem_operand (rtx op, enum machine_mode mode)
2192 return (gpc_reg_operand (op, mode)
2193 || memory_operand (op, mode)
2194 || macho_lo_sum_memory_operand (op, mode)
2195 || volatile_mem_operand (op, mode));
2198 /* Return 1 if the operand is a general register or memory operand without
2199 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2203 lwa_operand (rtx op, enum machine_mode mode)
2207 if (reload_completed && GET_CODE (inner) == SUBREG)
2208 inner = SUBREG_REG (inner);
2210 return gpc_reg_operand (inner, mode)
2211 || (memory_operand (inner, mode)
2212 && GET_CODE (XEXP (inner, 0)) != PRE_INC
2213 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2214 && (GET_CODE (XEXP (inner, 0)) != PLUS
2215 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2216 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2219 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2222 symbol_ref_operand (rtx op, enum machine_mode mode)
2224 if (mode != VOIDmode && GET_MODE (op) != mode)
2227 return (GET_CODE (op) == SYMBOL_REF
2228 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2231 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2232 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2235 call_operand (rtx op, enum machine_mode mode)
2237 if (mode != VOIDmode && GET_MODE (op) != mode)
2240 return (GET_CODE (op) == SYMBOL_REF
2241 || (GET_CODE (op) == REG
2242 && (REGNO (op) == LINK_REGISTER_REGNUM
2243 || REGNO (op) == COUNT_REGISTER_REGNUM
2244 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2247 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2251 current_file_function_operand (rtx op,
2252 enum machine_mode mode ATTRIBUTE_UNUSED)
2254 return (GET_CODE (op) == SYMBOL_REF
2255 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2256 && (SYMBOL_REF_LOCAL_P (op)
2257 || (op == XEXP (DECL_RTL (current_function_decl), 0))));
2260 /* Return 1 if this operand is a valid input for a move insn. */
2263 input_operand (rtx op, enum machine_mode mode)
2265 /* Memory is always valid. */
2266 if (memory_operand (op, mode))
2269 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
2270 if (GET_CODE (op) == CONSTANT_P_RTX)
2273 /* For floating-point, easy constants are valid. */
2274 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2276 && easy_fp_constant (op, mode))
2279 /* Allow any integer constant. */
2280 if (GET_MODE_CLASS (mode) == MODE_INT
2281 && (GET_CODE (op) == CONST_INT
2282 || GET_CODE (op) == CONST_DOUBLE))
2285 /* Allow easy vector constants. */
2286 if (GET_CODE (op) == CONST_VECTOR
2287 && easy_vector_constant (op, mode))
2290 /* For floating-point or multi-word mode, the only remaining valid type
2292 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2293 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
2294 return register_operand (op, mode);
2296 /* The only cases left are integral modes one word or smaller (we
2297 do not get called for MODE_CC values). These can be in any
2299 if (register_operand (op, mode))
2302 /* A SYMBOL_REF referring to the TOC is valid. */
2303 if (legitimate_constant_pool_address_p (op))
2306 /* A constant pool expression (relative to the TOC) is valid */
2307 if (toc_relative_expr_p (op))
2310 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
2312 if (DEFAULT_ABI == ABI_V4
2313 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
2314 && small_data_operand (op, Pmode))
2320 /* Return 1 for an operand in small memory on V.4/eabi. */
2323 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2324 enum machine_mode mode ATTRIBUTE_UNUSED)
2329 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2332 if (DEFAULT_ABI != ABI_V4)
2335 if (GET_CODE (op) == SYMBOL_REF)
2338 else if (GET_CODE (op) != CONST
2339 || GET_CODE (XEXP (op, 0)) != PLUS
2340 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2341 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2346 rtx sum = XEXP (op, 0);
2347 HOST_WIDE_INT summand;
2349 /* We have to be careful here, because it is the referenced address
2350 that must be 32k from _SDA_BASE_, not just the symbol. */
2351 summand = INTVAL (XEXP (sum, 1));
2352 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2355 sym_ref = XEXP (sum, 0);
2358 return SYMBOL_REF_SMALL_P (sym_ref);
2364 /* Return true if either operand is a general purpose register. */
2367 gpr_or_gpr_p (rtx op0, rtx op1)
2369 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2370 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2374 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2377 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2379 switch (GET_CODE(op))
2382 if (RS6000_SYMBOL_REF_TLS_P (op))
2384 else if (CONSTANT_POOL_ADDRESS_P (op))
2386 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2394 else if (! strcmp (XSTR (op, 0), toc_label_name))
2403 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2404 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2406 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2415 constant_pool_expr_p (rtx op)
2419 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2423 toc_relative_expr_p (rtx op)
2427 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2430 /* SPE offset addressing is limited to 5-bits worth of double words. */
2431 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2434 legitimate_constant_pool_address_p (rtx x)
2437 && GET_CODE (x) == PLUS
2438 && GET_CODE (XEXP (x, 0)) == REG
2439 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2440 && constant_pool_expr_p (XEXP (x, 1)));
2444 legitimate_small_data_p (enum machine_mode mode, rtx x)
2446 return (DEFAULT_ABI == ABI_V4
2447 && !flag_pic && !TARGET_TOC
2448 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2449 && small_data_operand (x, mode));
2453 legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2455 unsigned HOST_WIDE_INT offset, extra;
2457 if (GET_CODE (x) != PLUS)
2459 if (GET_CODE (XEXP (x, 0)) != REG)
2461 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2463 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2466 offset = INTVAL (XEXP (x, 1));
2474 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2475 which leaves the only valid constant offset of zero, which by
2476 canonicalization rules is also invalid. */
2483 /* SPE vector modes. */
2484 return SPE_CONST_OFFSET_OK (offset);
2488 if (mode == DFmode || !TARGET_POWERPC64)
2490 else if (offset & 3)
2496 if (mode == TFmode || !TARGET_POWERPC64)
2498 else if (offset & 3)
2508 return (offset + extra >= offset) && (offset + extra + 0x8000 < 0x10000);
2512 legitimate_indexed_address_p (rtx x, int strict)
2516 if (GET_CODE (x) != PLUS)
2521 if (!REG_P (op0) || !REG_P (op1))
2524 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2525 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2526 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2527 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2531 legitimate_indirect_address_p (rtx x, int strict)
2533 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2537 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2539 if (!TARGET_MACHO || !flag_pic
2540 || mode != SImode || GET_CODE(x) != MEM)
2544 if (GET_CODE (x) != LO_SUM)
2546 if (GET_CODE (XEXP (x, 0)) != REG)
2548 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2552 return CONSTANT_P (x);
2556 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2558 if (GET_CODE (x) != LO_SUM)
2560 if (GET_CODE (XEXP (x, 0)) != REG)
2562 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2566 if (TARGET_ELF || TARGET_MACHO)
2568 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2572 if (GET_MODE_NUNITS (mode) != 1)
2574 if (GET_MODE_BITSIZE (mode) > 32
2575 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode))
2578 return CONSTANT_P (x);
2585 /* Try machine-dependent ways of modifying an illegitimate address
2586 to be legitimate. If we find one, return the new, valid address.
2587 This is used from only one place: `memory_address' in explow.c.
2589 OLDX is the address as it was before break_out_memory_refs was
2590 called. In some cases it is useful to look at this to decide what
2593 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2595 It is always safe for this function to do nothing. It exists to
2596 recognize opportunities to optimize the output.
2598 On RS/6000, first check for the sum of a register with a constant
2599 integer that is out of range. If so, generate code to add the
2600 constant with the low-order 16 bits masked to the register and force
2601 this result into another register (this can be done with `cau').
2602 Then generate an address of REG+(CONST&0xffff), allowing for the
2603 possibility of bit 16 being a one.
2605 Then check for the sum of a register and something not constant, try to
2606 load the other things into a register and return the sum. */
2609 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2610 enum machine_mode mode)
2612 if (GET_CODE (x) == SYMBOL_REF)
2614 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2616 return rs6000_legitimize_tls_address (x, model);
2619 if (GET_CODE (x) == PLUS
2620 && GET_CODE (XEXP (x, 0)) == REG
2621 && GET_CODE (XEXP (x, 1)) == CONST_INT
2622 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2624 HOST_WIDE_INT high_int, low_int;
2626 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2627 high_int = INTVAL (XEXP (x, 1)) - low_int;
2628 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2629 GEN_INT (high_int)), 0);
2630 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2632 else if (GET_CODE (x) == PLUS
2633 && GET_CODE (XEXP (x, 0)) == REG
2634 && GET_CODE (XEXP (x, 1)) != CONST_INT
2635 && GET_MODE_NUNITS (mode) == 1
2636 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2638 || (mode != DFmode && mode != TFmode))
2639 && (TARGET_POWERPC64 || mode != DImode)
2642 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2643 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2645 else if (ALTIVEC_VECTOR_MODE (mode))
2649 /* Make sure both operands are registers. */
2650 if (GET_CODE (x) == PLUS)
2651 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2652 force_reg (Pmode, XEXP (x, 1)));
2654 reg = force_reg (Pmode, x);
2657 else if (SPE_VECTOR_MODE (mode))
2659 /* We accept [reg + reg] and [reg + OFFSET]. */
2661 if (GET_CODE (x) == PLUS)
2663 rtx op1 = XEXP (x, 0);
2664 rtx op2 = XEXP (x, 1);
2666 op1 = force_reg (Pmode, op1);
2668 if (GET_CODE (op2) != REG
2669 && (GET_CODE (op2) != CONST_INT
2670 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2671 op2 = force_reg (Pmode, op2);
2673 return gen_rtx_PLUS (Pmode, op1, op2);
2676 return force_reg (Pmode, x);
2682 && GET_CODE (x) != CONST_INT
2683 && GET_CODE (x) != CONST_DOUBLE
2685 && GET_MODE_NUNITS (mode) == 1
2686 && (GET_MODE_BITSIZE (mode) <= 32
2687 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2689 rtx reg = gen_reg_rtx (Pmode);
2690 emit_insn (gen_elf_high (reg, x));
2691 return gen_rtx_LO_SUM (Pmode, reg, x);
2693 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2696 && ! MACHO_DYNAMIC_NO_PIC_P
2698 && GET_CODE (x) != CONST_INT
2699 && GET_CODE (x) != CONST_DOUBLE
2701 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2705 rtx reg = gen_reg_rtx (Pmode);
2706 emit_insn (gen_macho_high (reg, x));
2707 return gen_rtx_LO_SUM (Pmode, reg, x);
2710 && constant_pool_expr_p (x)
2711 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2713 return create_TOC_reference (x);
2719 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2721 static GTY(()) rtx rs6000_tls_symbol;
2723 rs6000_tls_get_addr (void)
2725 if (!rs6000_tls_symbol)
2726 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2728 return rs6000_tls_symbol;
2731 /* Construct the SYMBOL_REF for TLS GOT references. */
2733 static GTY(()) rtx rs6000_got_symbol;
2735 rs6000_got_sym (void)
2737 if (!rs6000_got_symbol)
2739 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2740 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2741 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2744 return rs6000_got_symbol;
2747 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2748 this (thread-local) address. */
2751 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2755 dest = gen_reg_rtx (Pmode);
2756 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2762 tlsreg = gen_rtx_REG (Pmode, 13);
2763 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2767 tlsreg = gen_rtx_REG (Pmode, 2);
2768 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2772 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2776 tmp = gen_reg_rtx (Pmode);
2779 tlsreg = gen_rtx_REG (Pmode, 13);
2780 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2784 tlsreg = gen_rtx_REG (Pmode, 2);
2785 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2789 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2791 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2796 rtx r3, got, tga, tmp1, tmp2, eqv;
2799 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2803 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2806 rtx gsym = rs6000_got_sym ();
2807 got = gen_reg_rtx (Pmode);
2809 rs6000_emit_move (got, gsym, Pmode);
2813 static int tls_got_labelno = 0;
2814 rtx tempLR, lab, tmp3, mem;
2817 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
2818 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
2819 tempLR = gen_reg_rtx (Pmode);
2820 tmp1 = gen_reg_rtx (Pmode);
2821 tmp2 = gen_reg_rtx (Pmode);
2822 tmp3 = gen_reg_rtx (Pmode);
2823 mem = gen_rtx_MEM (Pmode, tmp1);
2824 RTX_UNCHANGING_P (mem) = 1;
2826 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
2828 emit_move_insn (tmp1, tempLR);
2829 emit_move_insn (tmp2, mem);
2830 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2831 last = emit_move_insn (got, tmp3);
2832 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2834 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2836 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2842 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2844 r3 = gen_rtx_REG (Pmode, 3);
2846 insn = gen_tls_gd_64 (r3, got, addr);
2848 insn = gen_tls_gd_32 (r3, got, addr);
2851 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2852 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2853 insn = emit_call_insn (insn);
2854 CONST_OR_PURE_CALL_P (insn) = 1;
2855 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2856 insn = get_insns ();
2858 emit_libcall_block (insn, dest, r3, addr);
2860 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2862 r3 = gen_rtx_REG (Pmode, 3);
2864 insn = gen_tls_ld_64 (r3, got);
2866 insn = gen_tls_ld_32 (r3, got);
2869 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2870 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2871 insn = emit_call_insn (insn);
2872 CONST_OR_PURE_CALL_P (insn) = 1;
2873 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2874 insn = get_insns ();
2876 tmp1 = gen_reg_rtx (Pmode);
2877 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2879 emit_libcall_block (insn, tmp1, r3, eqv);
2880 if (rs6000_tls_size == 16)
2883 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2885 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2887 else if (rs6000_tls_size == 32)
2889 tmp2 = gen_reg_rtx (Pmode);
2891 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2893 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2896 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2898 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2902 tmp2 = gen_reg_rtx (Pmode);
2904 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2906 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2908 insn = gen_rtx_SET (Pmode, dest,
2909 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2915 /* IE, or 64 bit offset LE. */
2916 tmp2 = gen_reg_rtx (Pmode);
2918 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2920 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2923 insn = gen_tls_tls_64 (dest, tmp2, addr);
2925 insn = gen_tls_tls_32 (dest, tmp2, addr);
2933 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
2934 instruction definitions. */
2937 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2939 return RS6000_SYMBOL_REF_TLS_P (x);
2942 /* Return 1 if X contains a thread-local symbol. */
2945 rs6000_tls_referenced_p (rtx x)
2947 if (! TARGET_HAVE_TLS)
2950 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2953 /* Return 1 if *X is a thread-local symbol. This is the same as
2954 rs6000_tls_symbol_ref except for the type of the unused argument. */
2957 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2959 return RS6000_SYMBOL_REF_TLS_P (*x);
2962 /* The convention appears to be to define this wherever it is used.
2963 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2964 is now used here. */
2965 #ifndef REG_MODE_OK_FOR_BASE_P
2966 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2969 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2970 replace the input X, or the original X if no replacement is called for.
2971 The output parameter *WIN is 1 if the calling macro should goto WIN,
2974 For RS/6000, we wish to handle large displacements off a base
2975 register by splitting the addend across an addiu/addis and the mem insn.
2976 This cuts number of extra insns needed from 3 to 1.
2978 On Darwin, we use this to generate code for floating point constants.
2979 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2980 The Darwin code is inside #if TARGET_MACHO because only then is
2981 machopic_function_base_name() defined. */
2983 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
2984 int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win)
2986 /* We must recognize output that we have already generated ourselves. */
2987 if (GET_CODE (x) == PLUS
2988 && GET_CODE (XEXP (x, 0)) == PLUS
2989 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2990 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2991 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2993 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2994 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2995 opnum, (enum reload_type)type);
3001 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3002 && GET_CODE (x) == LO_SUM
3003 && GET_CODE (XEXP (x, 0)) == PLUS
3004 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3005 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3006 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3007 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3008 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3009 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3010 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3012 /* Result of previous invocation of this function on Darwin
3013 floating point constant. */
3014 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3015 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3016 opnum, (enum reload_type)type);
3021 if (GET_CODE (x) == PLUS
3022 && GET_CODE (XEXP (x, 0)) == REG
3023 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3024 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3025 && GET_CODE (XEXP (x, 1)) == CONST_INT
3026 && !SPE_VECTOR_MODE (mode)
3027 && !ALTIVEC_VECTOR_MODE (mode))
3029 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3030 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3032 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3034 /* Check for 32-bit overflow. */
3035 if (high + low != val)
3041 /* Reload the high part into a base reg; leave the low part
3042 in the mem directly. */
3044 x = gen_rtx_PLUS (GET_MODE (x),
3045 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3049 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3050 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3051 opnum, (enum reload_type)type);
3056 if (GET_CODE (x) == SYMBOL_REF
3057 && DEFAULT_ABI == ABI_DARWIN
3058 && !ALTIVEC_VECTOR_MODE (mode)
3059 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3060 /* Don't do this for TFmode, since the result isn't offsettable. */
3065 rtx offset = gen_rtx_CONST (Pmode,
3066 gen_rtx_MINUS (Pmode, x,
3067 gen_rtx_SYMBOL_REF (Pmode,
3068 machopic_function_base_name ())));
3069 x = gen_rtx_LO_SUM (GET_MODE (x),
3070 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3071 gen_rtx_HIGH (Pmode, offset)), offset);
3074 x = gen_rtx_LO_SUM (GET_MODE (x),
3075 gen_rtx_HIGH (Pmode, x), x);
3077 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3078 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3079 opnum, (enum reload_type)type);
3085 && constant_pool_expr_p (x)
3086 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3088 (x) = create_TOC_reference (x);
3096 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3097 that is a valid memory address for an instruction.
3098 The MODE argument is the machine mode for the MEM expression
3099 that wants to use this address.
3101 On the RS/6000, there are four valid address: a SYMBOL_REF that
3102 refers to a constant pool entry of an address (or the sum of it
3103 plus a constant), a short (16-bit signed) constant plus a register,
3104 the sum of two registers, or a register indirect, possibly with an
3105 auto-increment. For DFmode and DImode with a constant plus register,
3106 we must ensure that both words are addressable or PowerPC64 with offset
3109 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3110 32-bit DImode, TImode), indexed addressing cannot be used because
3111 adjacent memory cells are accessed by adding word-sized offsets
3112 during assembly output. */
3114 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3116 if (RS6000_SYMBOL_REF_TLS_P (x))
3118 if (legitimate_indirect_address_p (x, reg_ok_strict))
3120 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3121 && !ALTIVEC_VECTOR_MODE (mode)
3122 && !SPE_VECTOR_MODE (mode)
3124 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3126 if (legitimate_small_data_p (mode, x))
3128 if (legitimate_constant_pool_address_p (x))
3130 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3132 && GET_CODE (x) == PLUS
3133 && GET_CODE (XEXP (x, 0)) == REG
3134 && XEXP (x, 0) == virtual_stack_vars_rtx
3135 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3137 if (legitimate_offset_address_p (mode, x, reg_ok_strict))
3140 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3142 || (mode != DFmode && mode != TFmode))
3143 && (TARGET_POWERPC64 || mode != DImode)
3144 && legitimate_indexed_address_p (x, reg_ok_strict))
3146 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3151 /* Go to LABEL if ADDR (a legitimate address expression)
3152 has an effect that depends on the machine mode it is used for.
3154 On the RS/6000 this is true of all integral offsets (since AltiVec
3155 modes don't allow them) or is a pre-increment or decrement.
3157 ??? Except that due to conceptual problems in offsettable_address_p
3158 we can't really report the problems of integral offsets. So leave
3159 this assuming that the adjustable offset must be valid for the
3160 sub-words of a TFmode operand, which is what we had before. */
3163 rs6000_mode_dependent_address (rtx addr)
3165 switch (GET_CODE (addr))
3168 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3170 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3171 return val + 12 + 0x8000 >= 0x10000;
3180 return TARGET_UPDATE;
3189 /* Try to output insns to set TARGET equal to the constant C if it can
3190 be done in less than N insns. Do all computations in MODE.
3191 Returns the place where the output has been placed if it can be
3192 done and the insns have been emitted. If it would take more than N
3193 insns, zero is returned and no insns and emitted. */
3196 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3197 rtx source, int n ATTRIBUTE_UNUSED)
3199 rtx result, insn, set;
3200 HOST_WIDE_INT c0, c1;
3202 if (mode == QImode || mode == HImode)
3205 dest = gen_reg_rtx (mode);
3206 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3209 else if (mode == SImode)
3211 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3213 emit_insn (gen_rtx_SET (VOIDmode, result,
3214 GEN_INT (INTVAL (source)
3215 & (~ (HOST_WIDE_INT) 0xffff))));
3216 emit_insn (gen_rtx_SET (VOIDmode, dest,
3217 gen_rtx_IOR (SImode, result,
3218 GEN_INT (INTVAL (source) & 0xffff))));
3221 else if (mode == DImode)
3223 if (GET_CODE (source) == CONST_INT)
3225 c0 = INTVAL (source);
3228 else if (GET_CODE (source) == CONST_DOUBLE)
3230 #if HOST_BITS_PER_WIDE_INT >= 64
3231 c0 = CONST_DOUBLE_LOW (source);
3234 c0 = CONST_DOUBLE_LOW (source);
3235 c1 = CONST_DOUBLE_HIGH (source);
3241 result = rs6000_emit_set_long_const (dest, c0, c1);
3246 insn = get_last_insn ();
3247 set = single_set (insn);
3248 if (! CONSTANT_P (SET_SRC (set)))
3249 set_unique_reg_note (insn, REG_EQUAL, source);
3254 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3255 fall back to a straight forward decomposition. We do this to avoid
3256 exponential run times encountered when looking for longer sequences
3257 with rs6000_emit_set_const. */
3259 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3261 if (!TARGET_POWERPC64)
3263 rtx operand1, operand2;
3265 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3267 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3269 emit_move_insn (operand1, GEN_INT (c1));
3270 emit_move_insn (operand2, GEN_INT (c2));
3274 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3277 ud2 = (c1 & 0xffff0000) >> 16;
3278 #if HOST_BITS_PER_WIDE_INT >= 64
3282 ud4 = (c2 & 0xffff0000) >> 16;
3284 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3285 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3288 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3290 emit_move_insn (dest, GEN_INT (ud1));
3293 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3294 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3297 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3300 emit_move_insn (dest, GEN_INT (ud2 << 16));
3302 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3304 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3305 || (ud4 == 0 && ! (ud3 & 0x8000)))
3308 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3311 emit_move_insn (dest, GEN_INT (ud3 << 16));
3314 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3315 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3317 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3322 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3325 emit_move_insn (dest, GEN_INT (ud4 << 16));
3328 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3330 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3332 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3333 GEN_INT (ud2 << 16)));
3335 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3341 /* Emit a move from SOURCE to DEST in mode MODE. */
3343 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3347 operands[1] = source;
3349 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3350 if (GET_CODE (operands[1]) == CONST_DOUBLE
3351 && ! FLOAT_MODE_P (mode)
3352 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3354 /* FIXME. This should never happen. */
3355 /* Since it seems that it does, do the safe thing and convert
3357 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3359 if (GET_CODE (operands[1]) == CONST_DOUBLE
3360 && ! FLOAT_MODE_P (mode)
3361 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3362 && CONST_DOUBLE_LOW (operands[1]) >= 0)
3363 || (CONST_DOUBLE_HIGH (operands[1]) == -1
3364 && CONST_DOUBLE_LOW (operands[1]) < 0)))
3367 /* Check if GCC is setting up a block move that will end up using FP
3368 registers as temporaries. We must make sure this is acceptable. */
3369 if (GET_CODE (operands[0]) == MEM
3370 && GET_CODE (operands[1]) == MEM
3372 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3373 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3374 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3375 ? 32 : MEM_ALIGN (operands[0])))
3376 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3378 : MEM_ALIGN (operands[1]))))
3379 && ! MEM_VOLATILE_P (operands [0])
3380 && ! MEM_VOLATILE_P (operands [1]))
3382 emit_move_insn (adjust_address (operands[0], SImode, 0),
3383 adjust_address (operands[1], SImode, 0));
3384 emit_move_insn (adjust_address (operands[0], SImode, 4),
3385 adjust_address (operands[1], SImode, 4));
3389 if (!no_new_pseudos)
3391 if (GET_CODE (operands[1]) == MEM && optimize > 0
3392 && (mode == QImode || mode == HImode || mode == SImode)
3393 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode))
3395 rtx reg = gen_reg_rtx (word_mode);
3397 emit_insn (gen_rtx_SET (word_mode, reg,
3398 gen_rtx_ZERO_EXTEND (word_mode,
3400 operands[1] = gen_lowpart (mode, reg);
3402 if (GET_CODE (operands[0]) != REG)
3403 operands[1] = force_reg (mode, operands[1]);
3406 if (mode == SFmode && ! TARGET_POWERPC
3407 && TARGET_HARD_FLOAT && TARGET_FPRS
3408 && GET_CODE (operands[0]) == MEM)
3412 if (reload_in_progress || reload_completed)
3413 regnum = true_regnum (operands[1]);
3414 else if (GET_CODE (operands[1]) == REG)
3415 regnum = REGNO (operands[1]);
3419 /* If operands[1] is a register, on POWER it may have
3420 double-precision data in it, so truncate it to single
3422 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3425 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3426 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3427 operands[1] = newreg;
3431 /* Recognize the case where operand[1] is a reference to thread-local
3432 data and load its address to a register. */
3433 if (GET_CODE (operands[1]) == SYMBOL_REF)
3435 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3437 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3440 /* Handle the case where reload calls us with an invalid address. */
3441 if (reload_in_progress && mode == Pmode
3442 && (! general_operand (operands[1], mode)
3443 || ! nonimmediate_operand (operands[0], mode)))
3446 /* Handle the case of CONSTANT_P_RTX. */
3447 if (GET_CODE (operands[1]) == CONSTANT_P_RTX)
3450 /* 128-bit constant floating-point values on Darwin should really be
3451 loaded as two parts. */
3452 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3453 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3454 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3456 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3457 know how to get a DFmode SUBREG of a TFmode. */
3458 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3459 simplify_gen_subreg (DImode, operands[1], mode, 0),
3461 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3462 GET_MODE_SIZE (DImode)),
3463 simplify_gen_subreg (DImode, operands[1], mode,
3464 GET_MODE_SIZE (DImode)),
3469 /* FIXME: In the long term, this switch statement should go away
3470 and be replaced by a sequence of tests based on things like
3476 if (CONSTANT_P (operands[1])
3477 && GET_CODE (operands[1]) != CONST_INT)
3478 operands[1] = force_const_mem (mode, operands[1]);
3484 if (CONSTANT_P (operands[1])
3485 && ! easy_fp_constant (operands[1], mode))
3486 operands[1] = force_const_mem (mode, operands[1]);
3497 if (CONSTANT_P (operands[1])
3498 && !easy_vector_constant (operands[1], mode))
3499 operands[1] = force_const_mem (mode, operands[1]);
3504 /* Use default pattern for address of ELF small data */
3507 && DEFAULT_ABI == ABI_V4
3508 && (GET_CODE (operands[1]) == SYMBOL_REF
3509 || GET_CODE (operands[1]) == CONST)
3510 && small_data_operand (operands[1], mode))
3512 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3516 if (DEFAULT_ABI == ABI_V4
3517 && mode == Pmode && mode == SImode
3518 && flag_pic == 1 && got_operand (operands[1], mode))
3520 emit_insn (gen_movsi_got (operands[0], operands[1]));
3524 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3528 && CONSTANT_P (operands[1])
3529 && GET_CODE (operands[1]) != HIGH
3530 && GET_CODE (operands[1]) != CONST_INT)
3532 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3534 /* If this is a function address on -mcall-aixdesc,
3535 convert it to the address of the descriptor. */
3536 if (DEFAULT_ABI == ABI_AIX
3537 && GET_CODE (operands[1]) == SYMBOL_REF
3538 && XSTR (operands[1], 0)[0] == '.')
3540 const char *name = XSTR (operands[1], 0);
3542 while (*name == '.')
3544 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3545 CONSTANT_POOL_ADDRESS_P (new_ref)
3546 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3547 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3548 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3549 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3550 operands[1] = new_ref;
3553 if (DEFAULT_ABI == ABI_DARWIN)
3556 if (MACHO_DYNAMIC_NO_PIC_P)
3558 /* Take care of any required data indirection. */
3559 operands[1] = rs6000_machopic_legitimize_pic_address (
3560 operands[1], mode, operands[0]);
3561 if (operands[0] != operands[1])
3562 emit_insn (gen_rtx_SET (VOIDmode,
3563 operands[0], operands[1]));
3567 emit_insn (gen_macho_high (target, operands[1]));
3568 emit_insn (gen_macho_low (operands[0], target, operands[1]));
3572 emit_insn (gen_elf_high (target, operands[1]));
3573 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3577 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3578 and we have put it in the TOC, we just need to make a TOC-relative
3581 && GET_CODE (operands[1]) == SYMBOL_REF
3582 && constant_pool_expr_p (operands[1])
3583 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3584 get_pool_mode (operands[1])))
3586 operands[1] = create_TOC_reference (operands[1]);
3588 else if (mode == Pmode
3589 && CONSTANT_P (operands[1])
3590 && ((GET_CODE (operands[1]) != CONST_INT
3591 && ! easy_fp_constant (operands[1], mode))
3592 || (GET_CODE (operands[1]) == CONST_INT
3593 && num_insns_constant (operands[1], mode) > 2)
3594 || (GET_CODE (operands[0]) == REG
3595 && FP_REGNO_P (REGNO (operands[0]))))
3596 && GET_CODE (operands[1]) != HIGH
3597 && ! legitimate_constant_pool_address_p (operands[1])
3598 && ! toc_relative_expr_p (operands[1]))
3600 /* Emit a USE operation so that the constant isn't deleted if
3601 expensive optimizations are turned on because nobody
3602 references it. This should only be done for operands that
3603 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3604 This should not be done for operands that contain LABEL_REFs.
3605 For now, we just handle the obvious case. */
3606 if (GET_CODE (operands[1]) != LABEL_REF)
3607 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3610 /* Darwin uses a special PIC legitimizer. */
3611 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3614 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3616 if (operands[0] != operands[1])
3617 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3622 /* If we are to limit the number of things we put in the TOC and
3623 this is a symbol plus a constant we can add in one insn,
3624 just put the symbol in the TOC and add the constant. Don't do
3625 this if reload is in progress. */
3626 if (GET_CODE (operands[1]) == CONST
3627 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3628 && GET_CODE (XEXP (operands[1], 0)) == PLUS
3629 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
3630 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3631 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3632 && ! side_effects_p (operands[0]))
3635 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
3636 rtx other = XEXP (XEXP (operands[1], 0), 1);
3638 sym = force_reg (mode, sym);
3640 emit_insn (gen_addsi3 (operands[0], sym, other));
3642 emit_insn (gen_adddi3 (operands[0], sym, other));
3646 operands[1] = force_const_mem (mode, operands[1]);
3649 && constant_pool_expr_p (XEXP (operands[1], 0))
3650 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3651 get_pool_constant (XEXP (operands[1], 0)),
3652 get_pool_mode (XEXP (operands[1], 0))))
3655 = gen_rtx_MEM (mode,
3656 create_TOC_reference (XEXP (operands[1], 0)));
3657 set_mem_alias_set (operands[1], get_TOC_alias_set ());
3658 RTX_UNCHANGING_P (operands[1]) = 1;
3664 if (GET_CODE (operands[0]) == MEM
3665 && GET_CODE (XEXP (operands[0], 0)) != REG
3666 && ! reload_in_progress)
3668 = replace_equiv_address (operands[0],
3669 copy_addr_to_reg (XEXP (operands[0], 0)));
3671 if (GET_CODE (operands[1]) == MEM
3672 && GET_CODE (XEXP (operands[1], 0)) != REG
3673 && ! reload_in_progress)
3675 = replace_equiv_address (operands[1],
3676 copy_addr_to_reg (XEXP (operands[1], 0)));
3679 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3681 gen_rtx_SET (VOIDmode,
3682 operands[0], operands[1]),
3683 gen_rtx_CLOBBER (VOIDmode,
3684 gen_rtx_SCRATCH (SImode)))));
3693 /* Above, we may have called force_const_mem which may have returned
3694 an invalid address. If we can, fix this up; otherwise, reload will
3695 have to deal with it. */
3696 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3697 operands[1] = validize_mem (operands[1]);
3700 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3703 /* Nonzero if we can use a floating-point register to pass this arg. */
3704 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3705 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3706 && (CUM)->fregno <= FP_ARG_MAX_REG \
3707 && TARGET_HARD_FLOAT && TARGET_FPRS)
3709 /* Nonzero if we can use an AltiVec register to pass this arg. */
3710 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3711 (ALTIVEC_VECTOR_MODE (MODE) \
3712 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3713 && TARGET_ALTIVEC_ABI \
3716 /* Return a nonzero value to say to return the function value in
3717 memory, just as large structures are always returned. TYPE will be
3718 the data type of the value, and FNTYPE will be the type of the
3719 function doing the returning, or @code{NULL} for libcalls.
3721 The AIX ABI for the RS/6000 specifies that all structures are
3722 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3723 specifies that structures <= 8 bytes are returned in r3/r4, but a
3724 draft put them in memory, and GCC used to implement the draft
3725 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3726 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3727 compatibility can change DRAFT_V4_STRUCT_RET to override the
3728 default, and -m switches get the final word. See
3729 rs6000_override_options for more details.
3731 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3732 long double support is enabled. These values are returned in memory.
3734 int_size_in_bytes returns -1 for variable size objects, which go in
3735 memory always. The cast to unsigned makes -1 > 8. */
3738 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3740 if (AGGREGATE_TYPE_P (type)
3741 && (TARGET_AIX_STRUCT_RET
3742 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3744 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3749 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3750 for a call to a function whose data type is FNTYPE.
3751 For a library call, FNTYPE is 0.
3753 For incoming args we set the number of arguments in the prototype large
3754 so we never return a PARALLEL. */
3757 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3758 rtx libname ATTRIBUTE_UNUSED, int incoming, int libcall)
3760 static CUMULATIVE_ARGS zero_cumulative;
3762 *cum = zero_cumulative;
3764 cum->fregno = FP_ARG_MIN_REG;
3765 cum->vregno = ALTIVEC_ARG_MIN_REG;
3766 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3767 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3768 ? CALL_LIBCALL : CALL_NORMAL);
3769 cum->sysv_gregno = GP_ARG_MIN_REG;
3770 cum->stdarg = fntype
3771 && (TYPE_ARG_TYPES (fntype) != 0
3772 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3773 != void_type_node));
3776 cum->nargs_prototype = 1000; /* don't return a PARALLEL */
3778 else if (cum->prototype)
3779 cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
3780 + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
3781 || rs6000_return_in_memory (TREE_TYPE (fntype),
3785 cum->nargs_prototype = 0;
3787 /* Check for a longcall attribute. */
3789 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3790 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
3791 cum->call_cookie = CALL_LONG;
3793 if (TARGET_DEBUG_ARG)
3795 fprintf (stderr, "\ninit_cumulative_args:");
3798 tree ret_type = TREE_TYPE (fntype);
3799 fprintf (stderr, " ret code = %s,",
3800 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3803 if (cum->call_cookie & CALL_LONG)
3804 fprintf (stderr, " longcall,");
3806 fprintf (stderr, " proto = %d, nargs = %d\n",
3807 cum->prototype, cum->nargs_prototype);
3811 /* If defined, a C expression which determines whether, and in which
3812 direction, to pad out an argument with extra space. The value
3813 should be of type `enum direction': either `upward' to pad above
3814 the argument, `downward' to pad below, or `none' to inhibit
3817 For the AIX ABI structs are always stored left shifted in their
3821 function_arg_padding (enum machine_mode mode, tree type)
3823 #ifndef AGGREGATE_PADDING_FIXED
3824 #define AGGREGATE_PADDING_FIXED 0
3826 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
3827 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
3830 if (!AGGREGATE_PADDING_FIXED)
3832 /* GCC used to pass structures of the same size as integer types as
3833 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
3834 ie. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
3835 passed padded downward, except that -mstrict-align further
3836 muddied the water in that multi-component structures of 2 and 4
3837 bytes in size were passed padded upward.
3839 The following arranges for best compatibility with previous
3840 versions of gcc, but removes the -mstrict-align dependency. */
3841 if (BYTES_BIG_ENDIAN)
3843 HOST_WIDE_INT size = 0;
3845 if (mode == BLKmode)
3847 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
3848 size = int_size_in_bytes (type);
3851 size = GET_MODE_SIZE (mode);
3853 if (size == 1 || size == 2 || size == 4)
3859 if (AGGREGATES_PAD_UPWARD_ALWAYS)
3861 if (type != 0 && AGGREGATE_TYPE_P (type))
3865 /* Fall back to the default. */
3866 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
3869 /* If defined, a C expression that gives the alignment boundary, in bits,
3870 of an argument with the specified mode and type. If it is not defined,
3871 PARM_BOUNDARY is used for all arguments.
3873 V.4 wants long longs to be double word aligned. */
3876 function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED)
3878 if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode))
3880 else if (SPE_VECTOR_MODE (mode))
3882 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
3885 return PARM_BOUNDARY;
3888 /* Update the data in CUM to advance over an argument
3889 of mode MODE and data type TYPE.
3890 (TYPE is null for libcalls where that information may not be available.) */
3893 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3894 tree type, int named)
3896 cum->nargs_prototype--;
3898 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
3900 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
3903 /* In variable-argument functions, vector arguments get GPRs allocated
3904 even if they are going to be passed in a vector register. */
3905 if (cum->stdarg && DEFAULT_ABI != ABI_V4)
3909 /* Vector parameters must be 16-byte aligned. This places
3910 them at 2 mod 4 in terms of words in 32-bit mode, since
3911 the parameter save area starts at offset 24 from the
3912 stack. In 64-bit mode, they just have to start on an
3913 even word, since the parameter save area is 16-byte
3914 aligned. Space for GPRs is reserved even if the argument
3915 will be passed in memory. */
3917 align = ((6 - (cum->words & 3)) & 3);
3919 align = cum->words & 1;
3920 cum->words += align + RS6000_ARG_SIZE (mode, type);
3922 if (TARGET_DEBUG_ARG)
3924 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
3926 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
3927 cum->nargs_prototype, cum->prototype,
3928 GET_MODE_NAME (mode));
3932 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
3934 && cum->sysv_gregno <= GP_ARG_MAX_REG)
3936 else if (DEFAULT_ABI == ABI_V4)
3938 if (TARGET_HARD_FLOAT && TARGET_FPRS
3939 && (mode == SFmode || mode == DFmode))
3941 if (cum->fregno <= FP_ARG_V4_MAX_REG)
3946 cum->words += cum->words & 1;
3947 cum->words += RS6000_ARG_SIZE (mode, type);
3953 int gregno = cum->sysv_gregno;
3955 /* Aggregates and IEEE quad get passed by reference. */
3956 if ((type && AGGREGATE_TYPE_P (type))
3960 n_words = RS6000_ARG_SIZE (mode, type);
3962 /* Long long and SPE vectors are put in odd registers. */
3963 if (n_words == 2 && (gregno & 1) == 0)
3966 /* Long long and SPE vectors are not split between registers
3968 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
3970 /* Long long is aligned on the stack. */
3972 cum->words += cum->words & 1;
3973 cum->words += n_words;
3976 /* Note: continuing to accumulate gregno past when we've started
3977 spilling to the stack indicates the fact that we've started
3978 spilling to the stack to expand_builtin_saveregs. */
3979 cum->sysv_gregno = gregno + n_words;
3982 if (TARGET_DEBUG_ARG)
3984 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
3985 cum->words, cum->fregno);
3986 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
3987 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
3988 fprintf (stderr, "mode = %4s, named = %d\n",
3989 GET_MODE_NAME (mode), named);
3994 int align = (TARGET_32BIT && (cum->words & 1) != 0
3995 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
3997 cum->words += align + RS6000_ARG_SIZE (mode, type);
3999 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4000 && TARGET_HARD_FLOAT && TARGET_FPRS)
4001 cum->fregno += (mode == TFmode ? 2 : 1);
4003 if (TARGET_DEBUG_ARG)
4005 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4006 cum->words, cum->fregno);
4007 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4008 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4009 fprintf (stderr, "named = %d, align = %d\n", named, align);
4014 /* Determine where to put a SIMD argument on the SPE. */
4017 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4022 int gregno = cum->sysv_gregno;
4023 int n_words = RS6000_ARG_SIZE (mode, type);
4025 /* SPE vectors are put in odd registers. */
4026 if (n_words == 2 && (gregno & 1) == 0)
4029 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4032 enum machine_mode m = SImode;
4034 r1 = gen_rtx_REG (m, gregno);
4035 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4036 r2 = gen_rtx_REG (m, gregno + 1);
4037 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4038 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4045 if (cum->sysv_gregno <= GP_ARG_MAX_REG)
4046 return gen_rtx_REG (mode, cum->sysv_gregno);
4052 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4055 rs6000_mixed_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4056 tree type, int align_words)
4060 /* -mpowerpc64 with 32bit ABI splits up a DFmode argument
4061 in vararg list into zero, one or two GPRs */
4062 if (align_words >= GP_ARG_NUM_REG)
4063 return gen_rtx_PARALLEL (DFmode,
4065 gen_rtx_EXPR_LIST (VOIDmode,
4066 NULL_RTX, const0_rtx),
4067 gen_rtx_EXPR_LIST (VOIDmode,
4071 else if (align_words + RS6000_ARG_SIZE (mode, type)
4073 /* If this is partially on the stack, then we only
4074 include the portion actually in registers here. */
4075 return gen_rtx_PARALLEL (DFmode,
4077 gen_rtx_EXPR_LIST (VOIDmode,
4078 gen_rtx_REG (SImode,
4082 gen_rtx_EXPR_LIST (VOIDmode,
4087 /* split a DFmode arg into two GPRs */
4088 return gen_rtx_PARALLEL (DFmode,
4090 gen_rtx_EXPR_LIST (VOIDmode,
4091 gen_rtx_REG (SImode,
4095 gen_rtx_EXPR_LIST (VOIDmode,
4096 gen_rtx_REG (SImode,
4100 gen_rtx_EXPR_LIST (VOIDmode,
4101 gen_rtx_REG (mode, cum->fregno),
4104 /* -mpowerpc64 with 32bit ABI splits up a DImode argument into one
4106 else if (mode == DImode)
4108 if (align_words < GP_ARG_NUM_REG - 1)
4109 return gen_rtx_PARALLEL (DImode,
4111 gen_rtx_EXPR_LIST (VOIDmode,
4112 gen_rtx_REG (SImode,
4116 gen_rtx_EXPR_LIST (VOIDmode,
4117 gen_rtx_REG (SImode,
4121 else if (align_words == GP_ARG_NUM_REG - 1)
4122 return gen_rtx_PARALLEL (DImode,
4124 gen_rtx_EXPR_LIST (VOIDmode,
4125 NULL_RTX, const0_rtx),
4126 gen_rtx_EXPR_LIST (VOIDmode,
4127 gen_rtx_REG (SImode,
4132 else if (mode == BLKmode && align_words <= (GP_ARG_NUM_REG - 1))
4135 int size = int_size_in_bytes (type);
4136 int no_units = ((size - 1) / 4) + 1;
4137 int max_no_words = GP_ARG_NUM_REG - align_words;
4138 int rtlvec_len = no_units < max_no_words ? no_units : max_no_words;
4139 rtx *rtlvec = (rtx *) alloca (rtlvec_len * sizeof (rtx));
4141 memset ((char *) rtlvec, 0, rtlvec_len * sizeof (rtx));
4143 for (k=0; k < rtlvec_len; k++)
4144 rtlvec[k] = gen_rtx_EXPR_LIST (VOIDmode,
4145 gen_rtx_REG (SImode,
4148 k == 0 ? const0_rtx : GEN_INT (k*4));
4150 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k, rtlvec));
4156 /* Determine where to put an argument to a function.
4157 Value is zero to push the argument on the stack,
4158 or a hard register in which to store the argument.
4160 MODE is the argument's machine mode.
4161 TYPE is the data type of the argument (as a tree).
4162 This is null for libcalls where that information may
4164 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4165 the preceding args and about the function being called.
4166 NAMED is nonzero if this argument is a named parameter
4167 (otherwise it is an extra parameter matching an ellipsis).
4169 On RS/6000 the first eight words of non-FP are normally in registers
4170 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4171 Under V.4, the first 8 FP args are in registers.
4173 If this is floating-point and no prototype is specified, we use
4174 both an FP and integer register (or possibly FP reg and stack). Library
4175 functions (when CALL_LIBCALL is set) always have the proper types for args,
4176 so we can pass the FP value just in one register. emit_library_function
4177 doesn't support PARALLEL anyway. */
4180 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4181 tree type, int named)
4183 enum rs6000_abi abi = DEFAULT_ABI;
4185 /* Return a marker to indicate whether CR1 needs to set or clear the
4186 bit that V.4 uses to say fp args were passed in registers.
4187 Assume that we don't need the marker for software floating point,
4188 or compiler generated library calls. */
4189 if (mode == VOIDmode)
4192 && cum->nargs_prototype < 0
4193 && (cum->call_cookie & CALL_LIBCALL) == 0
4194 && (cum->prototype || TARGET_NO_PROTOTYPE))
4196 /* For the SPE, we need to crxor CR6 always. */
4198 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4199 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4200 return GEN_INT (cum->call_cookie
4201 | ((cum->fregno == FP_ARG_MIN_REG)
4202 ? CALL_V4_SET_FP_ARGS
4203 : CALL_V4_CLEAR_FP_ARGS));
4206 return GEN_INT (cum->call_cookie);
4209 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4210 return gen_rtx_REG (mode, cum->vregno);
4211 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4213 if (named || abi == ABI_V4)
4217 /* Vector parameters to varargs functions under AIX or Darwin
4218 get passed in memory and possibly also in GPRs. */
4219 int align, align_words;
4220 enum machine_mode part_mode = mode;
4222 /* Vector parameters must be 16-byte aligned. This places them at
4223 2 mod 4 in terms of words in 32-bit mode, since the parameter
4224 save area starts at offset 24 from the stack. In 64-bit mode,
4225 they just have to start on an even word, since the parameter
4226 save area is 16-byte aligned. */
4228 align = ((6 - (cum->words & 3)) & 3);
4230 align = cum->words & 1;
4231 align_words = cum->words + align;
4233 /* Out of registers? Memory, then. */
4234 if (align_words >= GP_ARG_NUM_REG)
4237 /* The vector value goes in GPRs. Only the part of the
4238 value in GPRs is reported here. */
4239 if (align_words + CLASS_MAX_NREGS (mode, GENERAL_REGS)
4241 /* Fortunately, there are only two possibilities, the value
4242 is either wholly in GPRs or half in GPRs and half not. */
4245 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
4248 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
4249 return rs6000_spe_function_arg (cum, mode, type);
4250 else if (abi == ABI_V4)
4252 if (TARGET_HARD_FLOAT && TARGET_FPRS
4253 && (mode == SFmode || mode == DFmode))
4255 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4256 return gen_rtx_REG (mode, cum->fregno);
4263 int gregno = cum->sysv_gregno;
4265 /* Aggregates and IEEE quad get passed by reference. */
4266 if ((type && AGGREGATE_TYPE_P (type))
4270 n_words = RS6000_ARG_SIZE (mode, type);
4272 /* Long long and SPE vectors are put in odd registers. */
4273 if (n_words == 2 && (gregno & 1) == 0)
4276 /* Long long do not split between registers and stack. */
4277 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4278 return gen_rtx_REG (mode, gregno);
4285 int align = (TARGET_32BIT && (cum->words & 1) != 0
4286 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
4287 int align_words = cum->words + align;
4289 if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
4292 if (TARGET_32BIT && TARGET_POWERPC64
4293 && (mode == DFmode || mode == DImode || mode == BLKmode))
4294 return rs6000_mixed_function_arg (cum, mode, type, align_words);
4296 if (USE_FP_FOR_ARG_P (cum, mode, type))
4299 || ((cum->nargs_prototype > 0)
4300 /* IBM AIX extended its linkage convention definition always
4301 to require FP args after register save area hole on the
4303 && (DEFAULT_ABI != ABI_AIX
4305 || (align_words < GP_ARG_NUM_REG))))
4306 return gen_rtx_REG (mode, cum->fregno);
4308 return gen_rtx_PARALLEL (mode,
4310 gen_rtx_EXPR_LIST (VOIDmode,
4311 ((align_words >= GP_ARG_NUM_REG)
4314 + RS6000_ARG_SIZE (mode, type)
4316 /* If this is partially on the stack, then
4317 we only include the portion actually
4318 in registers here. */
4319 ? gen_rtx_REG (SImode,
4320 GP_ARG_MIN_REG + align_words)
4321 : gen_rtx_REG (mode,
4322 GP_ARG_MIN_REG + align_words))),
4324 gen_rtx_EXPR_LIST (VOIDmode,
4325 gen_rtx_REG (mode, cum->fregno),
4328 else if (align_words < GP_ARG_NUM_REG)
4329 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4335 /* For an arg passed partly in registers and partly in memory,
4336 this is the number of registers used.
4337 For args passed entirely in registers or entirely in memory, zero. */
4340 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4341 tree type, int named)
4343 if (DEFAULT_ABI == ABI_V4)
4346 if (USE_FP_FOR_ARG_P (cum, mode, type)
4347 || USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4349 if (cum->nargs_prototype >= 0)
4353 if (cum->words < GP_ARG_NUM_REG
4354 && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type)))
4356 int ret = GP_ARG_NUM_REG - cum->words;
4357 if (ret && TARGET_DEBUG_ARG)
4358 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
4366 /* A C expression that indicates when an argument must be passed by
4367 reference. If nonzero for an argument, a copy of that argument is
4368 made in memory and a pointer to the argument is passed instead of
4369 the argument itself. The pointer is passed in whatever way is
4370 appropriate for passing a pointer to that type.
4372 Under V.4, structures and unions are passed by reference.
4374 As an extension to all ABIs, variable sized types are passed by
4378 function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4379 enum machine_mode mode ATTRIBUTE_UNUSED,
4380 tree type, int named ATTRIBUTE_UNUSED)
4382 if (DEFAULT_ABI == ABI_V4
4383 && ((type && AGGREGATE_TYPE_P (type))
4386 if (TARGET_DEBUG_ARG)
4387 fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
4391 return type && int_size_in_bytes (type) < 0;
4395 rs6000_move_block_from_reg(int regno, rtx x, int nregs)
4398 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
4403 for (i = 0; i < nregs; i++)
4405 rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
4406 if (reload_completed)
4408 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
4411 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
4412 i * GET_MODE_SIZE(reg_mode));
4415 tem = replace_equiv_address (tem, XEXP (tem, 0));
4417 if (tem == NULL_RTX)
4420 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
4425 /* Perform any needed actions needed for a function that is receiving a
4426 variable number of arguments.
4430 MODE and TYPE are the mode and type of the current parameter.
4432 PRETEND_SIZE is a variable that should be set to the amount of stack
4433 that must be pushed by the prolog to pretend that our caller pushed
4436 Normally, this macro will push all remaining incoming registers on the
4437 stack and set PRETEND_SIZE to the length of the registers pushed. */
4440 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4441 tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
4443 CUMULATIVE_ARGS next_cum;
4444 int reg_size = TARGET_32BIT ? 4 : 8;
4445 rtx save_area = NULL_RTX, mem;
4446 int first_reg_offset, set;
4448 /* Skip the last named argument. */
4450 function_arg_advance (&next_cum, mode, type, 1);
4452 if (DEFAULT_ABI == ABI_V4)
4454 /* Indicate to allocate space on the stack for varargs save area. */
4455 cfun->machine->sysv_varargs_p = 1;
4457 save_area = plus_constant (virtual_stack_vars_rtx,
4458 - RS6000_VARARGS_SIZE);
4460 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4464 first_reg_offset = next_cum.words;
4465 save_area = virtual_incoming_args_rtx;
4466 cfun->machine->sysv_varargs_p = 0;
4468 if (MUST_PASS_IN_STACK (mode, type))
4469 first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type);
4472 set = get_varargs_alias_set ();
4473 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
4475 mem = gen_rtx_MEM (BLKmode,
4476 plus_constant (save_area,
4477 first_reg_offset * reg_size)),
4478 set_mem_alias_set (mem, set);
4479 set_mem_align (mem, BITS_PER_WORD);
4481 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
4482 GP_ARG_NUM_REG - first_reg_offset);
4485 /* Save FP registers if needed. */
4486 if (DEFAULT_ABI == ABI_V4
4487 && TARGET_HARD_FLOAT && TARGET_FPRS
4489 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
4491 int fregno = next_cum.fregno;
4492 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4493 rtx lab = gen_label_rtx ();
4494 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4496 emit_jump_insn (gen_rtx_SET (VOIDmode,
4498 gen_rtx_IF_THEN_ELSE (VOIDmode,
4499 gen_rtx_NE (VOIDmode, cr1,
4501 gen_rtx_LABEL_REF (VOIDmode, lab),
4504 while (fregno <= FP_ARG_V4_MAX_REG)
4506 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
4507 set_mem_alias_set (mem, set);
4508 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
4517 /* Create the va_list data type. */
4520 rs6000_build_builtin_va_list (void)
4522 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
4524 /* For AIX, prefer 'char *' because that's what the system
4525 header files like. */
4526 if (DEFAULT_ABI != ABI_V4)
4527 return build_pointer_type (char_type_node);
4529 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4530 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4532 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
4533 unsigned_char_type_node);
4534 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
4535 unsigned_char_type_node);
4536 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
4538 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
4539 short_unsigned_type_node);
4540 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4542 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4545 DECL_FIELD_CONTEXT (f_gpr) = record;
4546 DECL_FIELD_CONTEXT (f_fpr) = record;
4547 DECL_FIELD_CONTEXT (f_res) = record;
4548 DECL_FIELD_CONTEXT (f_ovf) = record;
4549 DECL_FIELD_CONTEXT (f_sav) = record;
4551 TREE_CHAIN (record) = type_decl;
4552 TYPE_NAME (record) = type_decl;
4553 TYPE_FIELDS (record) = f_gpr;
4554 TREE_CHAIN (f_gpr) = f_fpr;
4555 TREE_CHAIN (f_fpr) = f_res;
4556 TREE_CHAIN (f_res) = f_ovf;
4557 TREE_CHAIN (f_ovf) = f_sav;
4559 layout_type (record);
4561 /* The correct type is an array type of one element. */
4562 return build_array_type (record, build_index_type (size_zero_node));
4565 /* Implement va_start. */
4568 rs6000_va_start (tree valist, rtx nextarg)
4570 HOST_WIDE_INT words, n_gpr, n_fpr;
4571 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4572 tree gpr, fpr, ovf, sav, t;
4574 /* Only SVR4 needs something special. */
4575 if (DEFAULT_ABI != ABI_V4)
4577 std_expand_builtin_va_start (valist, nextarg);
4581 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4582 f_fpr = TREE_CHAIN (f_gpr);
4583 f_res = TREE_CHAIN (f_fpr);
4584 f_ovf = TREE_CHAIN (f_res);
4585 f_sav = TREE_CHAIN (f_ovf);
4587 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4588 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4589 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4590 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4591 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4593 /* Count number of gp and fp argument registers used. */
4594 words = current_function_args_info.words;
4595 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
4596 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
4598 if (TARGET_DEBUG_ARG)
4599 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
4600 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
4601 words, n_gpr, n_fpr);
4603 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0));
4604 TREE_SIDE_EFFECTS (t) = 1;
4605 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4607 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0));
4608 TREE_SIDE_EFFECTS (t) = 1;
4609 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4611 /* Find the overflow area. */
4612 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
4614 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
4615 build_int_2 (words * UNITS_PER_WORD, 0));
4616 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4617 TREE_SIDE_EFFECTS (t) = 1;
4618 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4620 /* Find the register save area. */
4621 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
4622 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
4623 build_int_2 (-RS6000_VARARGS_SIZE, -1));
4624 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
4625 TREE_SIDE_EFFECTS (t) = 1;
4626 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4629 /* Implement va_arg. */
4632 rs6000_va_arg (tree valist, tree type)
4634 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4635 tree gpr, fpr, ovf, sav, reg, t, u;
4636 int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale;
4637 rtx lab_false, lab_over, addr_rtx, r;
4639 if (DEFAULT_ABI != ABI_V4)
4641 /* Variable sized types are passed by reference. */
4642 if (int_size_in_bytes (type) < 0)
4644 u = build_pointer_type (type);
4646 /* Args grow upward. */
4647 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
4648 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4649 TREE_SIDE_EFFECTS (t) = 1;
4651 t = build1 (NOP_EXPR, build_pointer_type (u), t);
4652 TREE_SIDE_EFFECTS (t) = 1;
4654 t = build1 (INDIRECT_REF, u, t);
4655 TREE_SIDE_EFFECTS (t) = 1;
4657 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4661 /* Altivec arguments must be aligned to a 128-bit boundary. */
4662 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4664 tree vtype = TREE_TYPE (valist);
4665 tree new_valist, modify;
4667 /* Round address up to multiple of 16. Computes
4669 new_valist = fold (build (BIT_AND_EXPR, vtype,
4670 fold (build (PLUS_EXPR, vtype, valist,
4671 build_int_2 (15, 0))),
4672 build_int_2 (~15, -1)));
4674 /* Update valist. */
4675 modify = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
4677 TREE_SIDE_EFFECTS (modify) = 1;
4678 expand_expr (modify, const0_rtx, VOIDmode, EXPAND_NORMAL);
4681 return std_expand_builtin_va_arg (valist, type);
4685 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4686 f_fpr = TREE_CHAIN (f_gpr);
4687 f_res = TREE_CHAIN (f_fpr);
4688 f_ovf = TREE_CHAIN (f_res);
4689 f_sav = TREE_CHAIN (f_ovf);
4691 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4692 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4693 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4694 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4695 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4697 size = int_size_in_bytes (type);
4698 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4700 if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode)
4702 /* Aggregates and long doubles are passed by reference. */
4708 size = UNITS_PER_WORD;
4711 else if (FLOAT_TYPE_P (type) && TARGET_HARD_FLOAT && TARGET_FPRS)
4713 /* FP args go in FP registers, if present. */
4722 /* Otherwise into GP registers. */
4730 /* Pull the value out of the saved registers.... */
4732 lab_false = gen_label_rtx ();
4733 lab_over = gen_label_rtx ();
4734 addr_rtx = gen_reg_rtx (Pmode);
4736 /* AltiVec vectors never go in registers. */
4737 if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE)
4739 TREE_THIS_VOLATILE (reg) = 1;
4740 emit_cmp_and_jump_insns
4741 (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
4742 GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1,
4745 /* Long long is aligned in the registers. */
4748 u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
4749 build_int_2 (n_reg - 1, 0));
4750 u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
4751 u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
4752 TREE_SIDE_EFFECTS (u) = 1;
4753 expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
4757 t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
4761 u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
4762 build_int_2 (n_reg, 0));
4763 TREE_SIDE_EFFECTS (u) = 1;
4765 u = build1 (CONVERT_EXPR, integer_type_node, u);
4766 TREE_SIDE_EFFECTS (u) = 1;
4768 u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
4769 TREE_SIDE_EFFECTS (u) = 1;
4771 t = build (PLUS_EXPR, ptr_type_node, t, u);
4772 TREE_SIDE_EFFECTS (t) = 1;
4774 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4776 emit_move_insn (addr_rtx, r);
4778 emit_jump_insn (gen_jump (lab_over));
4782 emit_label (lab_false);
4784 /* ... otherwise out of the overflow area. */
4786 /* Make sure we don't find reg 7 for the next int arg.
4788 All AltiVec vectors go in the overflow area. So in the AltiVec
4789 case we need to get the vectors from the overflow area, but
4790 remember where the GPRs and FPRs are. */
4791 if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE
4792 || !TARGET_ALTIVEC))
4794 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
4795 TREE_SIDE_EFFECTS (t) = 1;
4796 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4799 /* Care for on-stack alignment if needed. */
4806 /* AltiVec vectors are 16 byte aligned. */
4807 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
4812 t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0));
4813 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1));
4817 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4819 emit_move_insn (addr_rtx, r);
4821 t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0));
4822 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4823 TREE_SIDE_EFFECTS (t) = 1;
4824 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4826 emit_label (lab_over);
4830 r = gen_rtx_MEM (Pmode, addr_rtx);
4831 set_mem_alias_set (r, get_varargs_alias_set ());
4832 emit_move_insn (addr_rtx, r);
4840 #define def_builtin(MASK, NAME, TYPE, CODE) \
4842 if ((MASK) & target_flags) \
4843 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
4847 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
4849 static const struct builtin_description bdesc_3arg[] =
4851 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
4852 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
4853 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
4854 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
4855 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
4856 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
4857 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
4858 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
4859 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
4860 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
4861 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
4862 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
4863 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
4864 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
4865 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
4866 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
4867 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
4868 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
4869 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
4870 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
4871 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
4872 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
4873 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
4876 /* DST operations: void foo (void *, const int, const char). */
4878 static const struct builtin_description bdesc_dst[] =
4880 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
4881 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
4882 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
4883 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
4886 /* Simple binary operations: VECc = foo (VECa, VECb). */
4888 static struct builtin_description bdesc_2arg[] =
4890 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
4891 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
4892 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
4893 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
4894 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
4895 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
4896 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
4897 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
4898 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
4899 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
4900 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
4901 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
4902 { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
4903 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
4904 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
4905 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
4906 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
4907 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
4908 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
4909 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
4910 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
4911 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
4912 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
4913 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
4914 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
4915 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
4916 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
4917 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
4918 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
4919 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
4920 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
4921 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
4922 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
4923 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
4924 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
4925 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
4926 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
4927 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
4928 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
4929 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
4930 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
4931 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
4932 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
4933 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
4934 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
4935 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
4936 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
4937 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
4938 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
4939 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
4940 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
4941 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
4942 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
4943 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
4944 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
4945 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
4946 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
4947 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
4948 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
4949 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
4950 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
4951 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
4952 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
4953 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
4954 { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
4955 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
4956 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
4957 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
4958 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
4959 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
4960 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
4961 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
4962 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
4963 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
4964 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
4965 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
4966 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
4967 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
4968 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
4969 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
4970 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
4971 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
4972 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
4973 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
4974 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
4975 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
4976 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
4977 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
4978 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
4979 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
4980 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
4981 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
4982 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
4983 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
4984 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
4985 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
4986 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
4987 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
4988 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
4989 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
4990 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
4991 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
4992 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
4993 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
4994 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
4995 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
4996 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
4997 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
4998 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
4999 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5000 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5001 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5002 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5004 /* Place holder, leave as first spe builtin. */
5005 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5006 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5007 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5008 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5009 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5010 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5011 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5012 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5013 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5014 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5015 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5016 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5017 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5018 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5019 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5020 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5021 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5022 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5023 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5024 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5025 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5026 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5027 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5028 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5029 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5030 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5031 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5032 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5033 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5034 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5035 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5036 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5037 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5038 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5039 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5040 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5041 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5042 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5043 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5044 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5045 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5046 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5047 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5048 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5049 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5050 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5051 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5052 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5053 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5054 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5055 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5056 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5057 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5058 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5059 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5060 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5061 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5062 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5063 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5064 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5065 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5066 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5067 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5068 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5069 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5070 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5071 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5072 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5073 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5074 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5075 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5076 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5077 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5078 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
5079 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5080 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
5081 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5082 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5083 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5084 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5085 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5086 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5087 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5088 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5089 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5090 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5091 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5092 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5093 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5094 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5095 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5096 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5097 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5098 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5099 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5100 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5101 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5102 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5103 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5104 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5105 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5106 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5107 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5108 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5109 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5110 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5111 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5112 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5113 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5115 /* SPE binary operations expecting a 5-bit unsigned literal. */
5116 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5118 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5119 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5120 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5121 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5122 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5123 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5124 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5125 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5126 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5127 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5128 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5129 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5130 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5131 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5132 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5133 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5134 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5135 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5136 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5137 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5138 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5139 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5140 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5141 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5142 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5143 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5145 /* Place-holder. Leave as last binary SPE builtin. */
5146 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
5149 /* AltiVec predicates. */
5151 struct builtin_description_predicates
5153 const unsigned int mask;
5154 const enum insn_code icode;
5156 const char *const name;
5157 const enum rs6000_builtins code;
5160 static const struct builtin_description_predicates bdesc_altivec_preds[] =
5162 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5163 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5164 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5165 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5166 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5167 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5168 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5169 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5170 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5171 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5172 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5173 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5174 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
5177 /* SPE predicates. */
5178 static struct builtin_description bdesc_spe_predicates[] =
5180 /* Place-holder. Leave as first. */
5181 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5182 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5183 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5184 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5185 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5186 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5187 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5188 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5189 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5190 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5191 /* Place-holder. Leave as last. */
5192 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5195 /* SPE evsel predicates. */
5196 static struct builtin_description bdesc_spe_evsel[] =
5198 /* Place-holder. Leave as first. */
5199 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5200 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5201 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5202 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5203 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5204 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5205 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5206 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5207 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5208 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5209 /* Place-holder. Leave as last. */
5210 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5213 /* ABS* operations. */
5215 static const struct builtin_description bdesc_abs[] =
5217 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5218 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5219 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5220 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5221 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5222 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5223 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5226 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5229 static struct builtin_description bdesc_1arg[] =
5231 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5232 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5233 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5234 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5235 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5236 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5237 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5238 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
5239 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5240 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5241 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
5242 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5243 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5244 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5245 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5246 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5247 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
5249 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5250 end with SPE_BUILTIN_EVSUBFUSIAAW. */
5251 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5252 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5253 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5254 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5255 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5256 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5257 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5258 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5259 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5260 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5261 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5262 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5263 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5264 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5265 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5266 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5267 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5268 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5269 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5270 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5271 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5272 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5273 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
5274 { 0, CODE_FOR_spe_evneg, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
5275 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5276 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5277 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5278 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
5280 /* Place-holder. Leave as last unary SPE builtin. */
5281 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
5285 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
5288 tree arg0 = TREE_VALUE (arglist);
5289 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5290 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5291 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5293 if (icode == CODE_FOR_nothing)
5294 /* Builtin not supported on this processor. */
5297 /* If we got invalid arguments bail out before generating bad rtl. */
5298 if (arg0 == error_mark_node)
5301 if (icode == CODE_FOR_altivec_vspltisb
5302 || icode == CODE_FOR_altivec_vspltish
5303 || icode == CODE_FOR_altivec_vspltisw
5304 || icode == CODE_FOR_spe_evsplatfi
5305 || icode == CODE_FOR_spe_evsplati)
5307 /* Only allow 5-bit *signed* literals. */
5308 if (GET_CODE (op0) != CONST_INT
5309 || INTVAL (op0) > 0x1f
5310 || INTVAL (op0) < -0x1f)
5312 error ("argument 1 must be a 5-bit signed literal");
5318 || GET_MODE (target) != tmode
5319 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5320 target = gen_reg_rtx (tmode);
5322 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5323 op0 = copy_to_mode_reg (mode0, op0);
5325 pat = GEN_FCN (icode) (target, op0);
5334 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
5336 rtx pat, scratch1, scratch2;
5337 tree arg0 = TREE_VALUE (arglist);
5338 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5339 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5340 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5342 /* If we have invalid arguments, bail out before generating bad rtl. */
5343 if (arg0 == error_mark_node)
5347 || GET_MODE (target) != tmode
5348 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5349 target = gen_reg_rtx (tmode);
5351 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5352 op0 = copy_to_mode_reg (mode0, op0);
5354 scratch1 = gen_reg_rtx (mode0);
5355 scratch2 = gen_reg_rtx (mode0);
5357 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
5366 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
5369 tree arg0 = TREE_VALUE (arglist);
5370 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5371 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5372 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5373 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5374 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5375 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5377 if (icode == CODE_FOR_nothing)
5378 /* Builtin not supported on this processor. */
5381 /* If we got invalid arguments bail out before generating bad rtl. */
5382 if (arg0 == error_mark_node || arg1 == error_mark_node)
5385 if (icode == CODE_FOR_altivec_vcfux
5386 || icode == CODE_FOR_altivec_vcfsx
5387 || icode == CODE_FOR_altivec_vctsxs
5388 || icode == CODE_FOR_altivec_vctuxs
5389 || icode == CODE_FOR_altivec_vspltb
5390 || icode == CODE_FOR_altivec_vsplth
5391 || icode == CODE_FOR_altivec_vspltw
5392 || icode == CODE_FOR_spe_evaddiw
5393 || icode == CODE_FOR_spe_evldd
5394 || icode == CODE_FOR_spe_evldh
5395 || icode == CODE_FOR_spe_evldw
5396 || icode == CODE_FOR_spe_evlhhesplat
5397 || icode == CODE_FOR_spe_evlhhossplat
5398 || icode == CODE_FOR_spe_evlhhousplat
5399 || icode == CODE_FOR_spe_evlwhe
5400 || icode == CODE_FOR_spe_evlwhos
5401 || icode == CODE_FOR_spe_evlwhou
5402 || icode == CODE_FOR_spe_evlwhsplat
5403 || icode == CODE_FOR_spe_evlwwsplat
5404 || icode == CODE_FOR_spe_evrlwi
5405 || icode == CODE_FOR_spe_evslwi
5406 || icode == CODE_FOR_spe_evsrwis
5407 || icode == CODE_FOR_spe_evsubifw
5408 || icode == CODE_FOR_spe_evsrwiu)
5410 /* Only allow 5-bit unsigned literals. */
5411 if (TREE_CODE (arg1) != INTEGER_CST
5412 || TREE_INT_CST_LOW (arg1) & ~0x1f)
5414 error ("argument 2 must be a 5-bit unsigned literal");
5420 || GET_MODE (target) != tmode
5421 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5422 target = gen_reg_rtx (tmode);
5424 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5425 op0 = copy_to_mode_reg (mode0, op0);
5426 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5427 op1 = copy_to_mode_reg (mode1, op1);
5429 pat = GEN_FCN (icode) (target, op0, op1);
5438 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
5439 tree arglist, rtx target)
5442 tree cr6_form = TREE_VALUE (arglist);
5443 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
5444 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5445 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5446 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5447 enum machine_mode tmode = SImode;
5448 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5449 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5452 if (TREE_CODE (cr6_form) != INTEGER_CST)
5454 error ("argument 1 of __builtin_altivec_predicate must be a constant");
5458 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
5463 /* If we have invalid arguments, bail out before generating bad rtl. */
5464 if (arg0 == error_mark_node || arg1 == error_mark_node)
5468 || GET_MODE (target) != tmode
5469 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5470 target = gen_reg_rtx (tmode);
5472 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5473 op0 = copy_to_mode_reg (mode0, op0);
5474 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5475 op1 = copy_to_mode_reg (mode1, op1);
5477 scratch = gen_reg_rtx (mode0);
5479 pat = GEN_FCN (icode) (scratch, op0, op1,
5480 gen_rtx (SYMBOL_REF, Pmode, opcode));
5485 /* The vec_any* and vec_all* predicates use the same opcodes for two
5486 different operations, but the bits in CR6 will be different
5487 depending on what information we want. So we have to play tricks
5488 with CR6 to get the right bits out.
5490 If you think this is disgusting, look at the specs for the
5491 AltiVec predicates. */
5493 switch (cr6_form_int)
5496 emit_insn (gen_cr6_test_for_zero (target));
5499 emit_insn (gen_cr6_test_for_zero_reverse (target));
5502 emit_insn (gen_cr6_test_for_lt (target));
5505 emit_insn (gen_cr6_test_for_lt_reverse (target));
5508 error ("argument 1 of __builtin_altivec_predicate is out of range");
5516 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
5519 tree arg0 = TREE_VALUE (arglist);
5520 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5521 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5522 enum machine_mode mode0 = Pmode;
5523 enum machine_mode mode1 = Pmode;
5524 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5525 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5527 if (icode == CODE_FOR_nothing)
5528 /* Builtin not supported on this processor. */
5531 /* If we got invalid arguments bail out before generating bad rtl. */
5532 if (arg0 == error_mark_node || arg1 == error_mark_node)
5536 || GET_MODE (target) != tmode
5537 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5538 target = gen_reg_rtx (tmode);
5540 op1 = copy_to_mode_reg (mode1, op1);
5542 if (op0 == const0_rtx)
5544 addr = gen_rtx_MEM (tmode, op1);
5548 op0 = copy_to_mode_reg (mode0, op0);
5549 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
5552 pat = GEN_FCN (icode) (target, addr);
5562 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
5564 tree arg0 = TREE_VALUE (arglist);
5565 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5566 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5567 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5568 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5569 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5571 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5572 enum machine_mode mode1 = Pmode;
5573 enum machine_mode mode2 = Pmode;
5575 /* Invalid arguments. Bail before doing anything stoopid! */
5576 if (arg0 == error_mark_node
5577 || arg1 == error_mark_node
5578 || arg2 == error_mark_node)
5581 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
5582 op0 = copy_to_mode_reg (tmode, op0);
5584 op2 = copy_to_mode_reg (mode2, op2);
5586 if (op1 == const0_rtx)
5588 addr = gen_rtx_MEM (tmode, op2);
5592 op1 = copy_to_mode_reg (mode1, op1);
5593 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
5596 pat = GEN_FCN (icode) (addr, op0);
5603 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
5606 tree arg0 = TREE_VALUE (arglist);
5607 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5608 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5609 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5610 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5611 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5612 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5613 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5614 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5615 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
5617 if (icode == CODE_FOR_nothing)
5618 /* Builtin not supported on this processor. */
5621 /* If we got invalid arguments bail out before generating bad rtl. */
5622 if (arg0 == error_mark_node
5623 || arg1 == error_mark_node
5624 || arg2 == error_mark_node)
5627 if (icode == CODE_FOR_altivec_vsldoi_4sf
5628 || icode == CODE_FOR_altivec_vsldoi_4si
5629 || icode == CODE_FOR_altivec_vsldoi_8hi
5630 || icode == CODE_FOR_altivec_vsldoi_16qi)
5632 /* Only allow 4-bit unsigned literals. */
5633 if (TREE_CODE (arg2) != INTEGER_CST
5634 || TREE_INT_CST_LOW (arg2) & ~0xf)
5636 error ("argument 3 must be a 4-bit unsigned literal");
5642 || GET_MODE (target) != tmode
5643 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5644 target = gen_reg_rtx (tmode);
5646 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5647 op0 = copy_to_mode_reg (mode0, op0);
5648 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5649 op1 = copy_to_mode_reg (mode1, op1);
5650 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
5651 op2 = copy_to_mode_reg (mode2, op2);
5653 pat = GEN_FCN (icode) (target, op0, op1, op2);
5661 /* Expand the lvx builtins. */
5663 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
5665 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5666 tree arglist = TREE_OPERAND (exp, 1);
5667 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5669 enum machine_mode tmode, mode0;
5671 enum insn_code icode;
5675 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
5676 icode = CODE_FOR_altivec_lvx_16qi;
5678 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
5679 icode = CODE_FOR_altivec_lvx_8hi;
5681 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
5682 icode = CODE_FOR_altivec_lvx_4si;
5684 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
5685 icode = CODE_FOR_altivec_lvx_4sf;
5694 arg0 = TREE_VALUE (arglist);
5695 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5696 tmode = insn_data[icode].operand[0].mode;
5697 mode0 = insn_data[icode].operand[1].mode;
5700 || GET_MODE (target) != tmode
5701 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5702 target = gen_reg_rtx (tmode);
5704 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5705 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5707 pat = GEN_FCN (icode) (target, op0);
5714 /* Expand the stvx builtins. */
5716 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
5719 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5720 tree arglist = TREE_OPERAND (exp, 1);
5721 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5723 enum machine_mode mode0, mode1;
5725 enum insn_code icode;
5729 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
5730 icode = CODE_FOR_altivec_stvx_16qi;
5732 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
5733 icode = CODE_FOR_altivec_stvx_8hi;
5735 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
5736 icode = CODE_FOR_altivec_stvx_4si;
5738 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
5739 icode = CODE_FOR_altivec_stvx_4sf;
5746 arg0 = TREE_VALUE (arglist);
5747 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5748 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5749 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5750 mode0 = insn_data[icode].operand[0].mode;
5751 mode1 = insn_data[icode].operand[1].mode;
5753 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
5754 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5755 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
5756 op1 = copy_to_mode_reg (mode1, op1);
5758 pat = GEN_FCN (icode) (op0, op1);
5766 /* Expand the dst builtins. */
5768 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
5771 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5772 tree arglist = TREE_OPERAND (exp, 1);
5773 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5774 tree arg0, arg1, arg2;
5775 enum machine_mode mode0, mode1, mode2;
5776 rtx pat, op0, op1, op2;
5777 struct builtin_description *d;
5782 /* Handle DST variants. */
5783 d = (struct builtin_description *) bdesc_dst;
5784 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
5785 if (d->code == fcode)
5787 arg0 = TREE_VALUE (arglist);
5788 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5789 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5790 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5791 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5792 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5793 mode0 = insn_data[d->icode].operand[0].mode;
5794 mode1 = insn_data[d->icode].operand[1].mode;
5795 mode2 = insn_data[d->icode].operand[2].mode;
5797 /* Invalid arguments, bail out before generating bad rtl. */
5798 if (arg0 == error_mark_node
5799 || arg1 == error_mark_node
5800 || arg2 == error_mark_node)
5803 if (TREE_CODE (arg2) != INTEGER_CST
5804 || TREE_INT_CST_LOW (arg2) & ~0x3)
5806 error ("argument to `%s' must be a 2-bit unsigned literal", d->name);
5810 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
5811 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5812 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
5813 op1 = copy_to_mode_reg (mode1, op1);
5815 pat = GEN_FCN (d->icode) (op0, op1, op2);
5826 /* Expand the builtin in EXP and store the result in TARGET. Store
5827 true in *EXPANDEDP if we found a builtin to expand. */
5829 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
5831 struct builtin_description *d;
5832 struct builtin_description_predicates *dp;
5834 enum insn_code icode;
5835 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5836 tree arglist = TREE_OPERAND (exp, 1);
5839 enum machine_mode tmode, mode0;
5840 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5842 target = altivec_expand_ld_builtin (exp, target, expandedp);
5846 target = altivec_expand_st_builtin (exp, target, expandedp);
5850 target = altivec_expand_dst_builtin (exp, target, expandedp);
5858 case ALTIVEC_BUILTIN_STVX:
5859 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
5860 case ALTIVEC_BUILTIN_STVEBX:
5861 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
5862 case ALTIVEC_BUILTIN_STVEHX:
5863 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
5864 case ALTIVEC_BUILTIN_STVEWX:
5865 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
5866 case ALTIVEC_BUILTIN_STVXL:
5867 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
5869 case ALTIVEC_BUILTIN_MFVSCR:
5870 icode = CODE_FOR_altivec_mfvscr;
5871 tmode = insn_data[icode].operand[0].mode;
5874 || GET_MODE (target) != tmode
5875 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5876 target = gen_reg_rtx (tmode);
5878 pat = GEN_FCN (icode) (target);
5884 case ALTIVEC_BUILTIN_MTVSCR:
5885 icode = CODE_FOR_altivec_mtvscr;
5886 arg0 = TREE_VALUE (arglist);
5887 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5888 mode0 = insn_data[icode].operand[0].mode;
5890 /* If we got invalid arguments bail out before generating bad rtl. */
5891 if (arg0 == error_mark_node)
5894 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
5895 op0 = copy_to_mode_reg (mode0, op0);
5897 pat = GEN_FCN (icode) (op0);
5902 case ALTIVEC_BUILTIN_DSSALL:
5903 emit_insn (gen_altivec_dssall ());
5906 case ALTIVEC_BUILTIN_DSS:
5907 icode = CODE_FOR_altivec_dss;
5908 arg0 = TREE_VALUE (arglist);
5909 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5910 mode0 = insn_data[icode].operand[0].mode;
5912 /* If we got invalid arguments bail out before generating bad rtl. */
5913 if (arg0 == error_mark_node)
5916 if (TREE_CODE (arg0) != INTEGER_CST
5917 || TREE_INT_CST_LOW (arg0) & ~0x3)
5919 error ("argument to dss must be a 2-bit unsigned literal");
5923 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
5924 op0 = copy_to_mode_reg (mode0, op0);
5926 emit_insn (gen_altivec_dss (op0));
5930 /* Expand abs* operations. */
5931 d = (struct builtin_description *) bdesc_abs;
5932 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
5933 if (d->code == fcode)
5934 return altivec_expand_abs_builtin (d->icode, arglist, target);
5936 /* Expand the AltiVec predicates. */
5937 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
5938 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
5939 if (dp->code == fcode)
5940 return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target);
5942 /* LV* are funky. We initialized them differently. */
5945 case ALTIVEC_BUILTIN_LVSL:
5946 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
5948 case ALTIVEC_BUILTIN_LVSR:
5949 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
5951 case ALTIVEC_BUILTIN_LVEBX:
5952 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
5954 case ALTIVEC_BUILTIN_LVEHX:
5955 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
5957 case ALTIVEC_BUILTIN_LVEWX:
5958 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
5960 case ALTIVEC_BUILTIN_LVXL:
5961 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
5963 case ALTIVEC_BUILTIN_LVX:
5964 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
5975 /* Binops that need to be initialized manually, but can be expanded
5976 automagically by rs6000_expand_binop_builtin. */
5977 static struct builtin_description bdesc_2arg_spe[] =
5979 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
5980 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
5981 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
5982 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
5983 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
5984 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
5985 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
5986 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
5987 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
5988 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
5989 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
5990 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
5991 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
5992 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
5993 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
5994 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
5995 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
5996 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
5997 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
5998 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
5999 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6000 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6003 /* Expand the builtin in EXP and store the result in TARGET. Store
6004 true in *EXPANDEDP if we found a builtin to expand.
6006 This expands the SPE builtins that are not simple unary and binary
6009 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
6011 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6012 tree arglist = TREE_OPERAND (exp, 1);
6014 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6015 enum insn_code icode;
6016 enum machine_mode tmode, mode0;
6018 struct builtin_description *d;
6023 /* Syntax check for a 5-bit unsigned immediate. */
6026 case SPE_BUILTIN_EVSTDD:
6027 case SPE_BUILTIN_EVSTDH:
6028 case SPE_BUILTIN_EVSTDW:
6029 case SPE_BUILTIN_EVSTWHE:
6030 case SPE_BUILTIN_EVSTWHO:
6031 case SPE_BUILTIN_EVSTWWE:
6032 case SPE_BUILTIN_EVSTWWO:
6033 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6034 if (TREE_CODE (arg1) != INTEGER_CST
6035 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6037 error ("argument 2 must be a 5-bit unsigned literal");
6045 /* The evsplat*i instructions are not quite generic. */
6048 case SPE_BUILTIN_EVSPLATFI:
6049 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6051 case SPE_BUILTIN_EVSPLATI:
6052 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6058 d = (struct builtin_description *) bdesc_2arg_spe;
6059 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6060 if (d->code == fcode)
6061 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6063 d = (struct builtin_description *) bdesc_spe_predicates;
6064 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6065 if (d->code == fcode)
6066 return spe_expand_predicate_builtin (d->icode, arglist, target);
6068 d = (struct builtin_description *) bdesc_spe_evsel;
6069 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6070 if (d->code == fcode)
6071 return spe_expand_evsel_builtin (d->icode, arglist, target);
6075 case SPE_BUILTIN_EVSTDDX:
6076 return altivec_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
6077 case SPE_BUILTIN_EVSTDHX:
6078 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
6079 case SPE_BUILTIN_EVSTDWX:
6080 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
6081 case SPE_BUILTIN_EVSTWHEX:
6082 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
6083 case SPE_BUILTIN_EVSTWHOX:
6084 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
6085 case SPE_BUILTIN_EVSTWWEX:
6086 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
6087 case SPE_BUILTIN_EVSTWWOX:
6088 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
6089 case SPE_BUILTIN_EVSTDD:
6090 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
6091 case SPE_BUILTIN_EVSTDH:
6092 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
6093 case SPE_BUILTIN_EVSTDW:
6094 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
6095 case SPE_BUILTIN_EVSTWHE:
6096 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
6097 case SPE_BUILTIN_EVSTWHO:
6098 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
6099 case SPE_BUILTIN_EVSTWWE:
6100 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
6101 case SPE_BUILTIN_EVSTWWO:
6102 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
6103 case SPE_BUILTIN_MFSPEFSCR:
6104 icode = CODE_FOR_spe_mfspefscr;
6105 tmode = insn_data[icode].operand[0].mode;
6108 || GET_MODE (target) != tmode
6109 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6110 target = gen_reg_rtx (tmode);
6112 pat = GEN_FCN (icode) (target);
6117 case SPE_BUILTIN_MTSPEFSCR:
6118 icode = CODE_FOR_spe_mtspefscr;
6119 arg0 = TREE_VALUE (arglist);
6120 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6121 mode0 = insn_data[icode].operand[0].mode;
6123 if (arg0 == error_mark_node)
6126 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6127 op0 = copy_to_mode_reg (mode0, op0);
6129 pat = GEN_FCN (icode) (op0);
6142 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
6144 rtx pat, scratch, tmp;
6145 tree form = TREE_VALUE (arglist);
6146 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6147 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6148 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6149 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6150 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6151 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6155 if (TREE_CODE (form) != INTEGER_CST)
6157 error ("argument 1 of __builtin_spe_predicate must be a constant");
6161 form_int = TREE_INT_CST_LOW (form);
6166 if (arg0 == error_mark_node || arg1 == error_mark_node)
6170 || GET_MODE (target) != SImode
6171 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6172 target = gen_reg_rtx (SImode);
6174 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6175 op0 = copy_to_mode_reg (mode0, op0);
6176 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6177 op1 = copy_to_mode_reg (mode1, op1);
6179 scratch = gen_reg_rtx (CCmode);
6181 pat = GEN_FCN (icode) (scratch, op0, op1);
6186 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6187 _lower_. We use one compare, but look in different bits of the
6188 CR for each variant.
6190 There are 2 elements in each SPE simd type (upper/lower). The CR
6191 bits are set as follows:
6193 BIT0 | BIT 1 | BIT 2 | BIT 3
6194 U | L | (U | L) | (U & L)
6196 So, for an "all" relationship, BIT 3 would be set.
6197 For an "any" relationship, BIT 2 would be set. Etc.
6199 Following traditional nomenclature, these bits map to:
6201 BIT0 | BIT 1 | BIT 2 | BIT 3
6204 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6209 /* All variant. OV bit. */
6211 /* We need to get to the OV bit, which is the ORDERED bit. We
6212 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6213 that's ugly and will trigger a validate_condition_mode abort.
6214 So let's just use another pattern. */
6215 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6217 /* Any variant. EQ bit. */
6221 /* Upper variant. LT bit. */
6225 /* Lower variant. GT bit. */
6230 error ("argument 1 of __builtin_spe_predicate is out of range");
6234 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6235 emit_move_insn (target, tmp);
6240 /* The evsel builtins look like this:
6242 e = __builtin_spe_evsel_OP (a, b, c, d);
6246 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6247 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6251 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
6254 tree arg0 = TREE_VALUE (arglist);
6255 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6256 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6257 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6258 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6259 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6260 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6261 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6262 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6263 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6268 if (arg0 == error_mark_node || arg1 == error_mark_node
6269 || arg2 == error_mark_node || arg3 == error_mark_node)
6273 || GET_MODE (target) != mode0
6274 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6275 target = gen_reg_rtx (mode0);
6277 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6278 op0 = copy_to_mode_reg (mode0, op0);
6279 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6280 op1 = copy_to_mode_reg (mode0, op1);
6281 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6282 op2 = copy_to_mode_reg (mode0, op2);
6283 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6284 op3 = copy_to_mode_reg (mode0, op3);
6286 /* Generate the compare. */
6287 scratch = gen_reg_rtx (CCmode);
6288 pat = GEN_FCN (icode) (scratch, op0, op1);
6293 if (mode0 == V2SImode)
6294 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
6296 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
6301 /* Expand an expression EXP that calls a built-in function,
6302 with result going to TARGET if that's convenient
6303 (and in mode MODE if that's convenient).
6304 SUBTARGET may be used as the target for computing one of EXP's operands.
6305 IGNORE is nonzero if the value is to be ignored. */
6308 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
6309 enum machine_mode mode ATTRIBUTE_UNUSED,
6310 int ignore ATTRIBUTE_UNUSED)
6312 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6313 tree arglist = TREE_OPERAND (exp, 1);
6314 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6315 struct builtin_description *d;
6322 ret = altivec_expand_builtin (exp, target, &success);
6329 ret = spe_expand_builtin (exp, target, &success);
6335 if (TARGET_ALTIVEC || TARGET_SPE)
6337 /* Handle simple unary operations. */
6338 d = (struct builtin_description *) bdesc_1arg;
6339 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
6340 if (d->code == fcode)
6341 return rs6000_expand_unop_builtin (d->icode, arglist, target);
6343 /* Handle simple binary operations. */
6344 d = (struct builtin_description *) bdesc_2arg;
6345 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
6346 if (d->code == fcode)
6347 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6349 /* Handle simple ternary operations. */
6350 d = (struct builtin_description *) bdesc_3arg;
6351 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
6352 if (d->code == fcode)
6353 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
6361 rs6000_init_builtins (void)
6363 opaque_V2SI_type_node = copy_node (V2SI_type_node);
6364 opaque_V2SF_type_node = copy_node (V2SF_type_node);
6365 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
6368 spe_init_builtins ();
6370 altivec_init_builtins ();
6371 if (TARGET_ALTIVEC || TARGET_SPE)
6372 rs6000_common_init_builtins ();
6375 /* Search through a set of builtins and enable the mask bits.
6376 DESC is an array of builtins.
6377 SIZE is the total number of builtins.
6378 START is the builtin enum at which to start.
6379 END is the builtin enum at which to end. */
6381 enable_mask_for_builtins (struct builtin_description *desc, int size,
6382 enum rs6000_builtins start,
6383 enum rs6000_builtins end)
6387 for (i = 0; i < size; ++i)
6388 if (desc[i].code == start)
6394 for (; i < size; ++i)
6396 /* Flip all the bits on. */
6397 desc[i].mask = target_flags;
6398 if (desc[i].code == end)
6404 spe_init_builtins (void)
6406 tree endlink = void_list_node;
6407 tree puint_type_node = build_pointer_type (unsigned_type_node);
6408 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
6409 struct builtin_description *d;
6412 tree v2si_ftype_4_v2si
6413 = build_function_type
6414 (opaque_V2SI_type_node,
6415 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6416 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6417 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6418 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6421 tree v2sf_ftype_4_v2sf
6422 = build_function_type
6423 (opaque_V2SF_type_node,
6424 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6425 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6426 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6427 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6430 tree int_ftype_int_v2si_v2si
6431 = build_function_type
6433 tree_cons (NULL_TREE, integer_type_node,
6434 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6435 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6438 tree int_ftype_int_v2sf_v2sf
6439 = build_function_type
6441 tree_cons (NULL_TREE, integer_type_node,
6442 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6443 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6446 tree void_ftype_v2si_puint_int
6447 = build_function_type (void_type_node,
6448 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6449 tree_cons (NULL_TREE, puint_type_node,
6450 tree_cons (NULL_TREE,
6454 tree void_ftype_v2si_puint_char
6455 = build_function_type (void_type_node,
6456 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6457 tree_cons (NULL_TREE, puint_type_node,
6458 tree_cons (NULL_TREE,
6462 tree void_ftype_v2si_pv2si_int
6463 = build_function_type (void_type_node,
6464 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6465 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6466 tree_cons (NULL_TREE,
6470 tree void_ftype_v2si_pv2si_char
6471 = build_function_type (void_type_node,
6472 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6473 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6474 tree_cons (NULL_TREE,
6479 = build_function_type (void_type_node,
6480 tree_cons (NULL_TREE, integer_type_node, endlink));
6483 = build_function_type (integer_type_node, endlink);
6485 tree v2si_ftype_pv2si_int
6486 = build_function_type (opaque_V2SI_type_node,
6487 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6488 tree_cons (NULL_TREE, integer_type_node,
6491 tree v2si_ftype_puint_int
6492 = build_function_type (opaque_V2SI_type_node,
6493 tree_cons (NULL_TREE, puint_type_node,
6494 tree_cons (NULL_TREE, integer_type_node,
6497 tree v2si_ftype_pushort_int
6498 = build_function_type (opaque_V2SI_type_node,
6499 tree_cons (NULL_TREE, pushort_type_node,
6500 tree_cons (NULL_TREE, integer_type_node,
6503 tree v2si_ftype_signed_char
6504 = build_function_type (opaque_V2SI_type_node,
6505 tree_cons (NULL_TREE, signed_char_type_node,
6508 /* The initialization of the simple binary and unary builtins is
6509 done in rs6000_common_init_builtins, but we have to enable the
6510 mask bits here manually because we have run out of `target_flags'
6511 bits. We really need to redesign this mask business. */
6513 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
6514 ARRAY_SIZE (bdesc_2arg),
6517 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
6518 ARRAY_SIZE (bdesc_1arg),
6520 SPE_BUILTIN_EVSUBFUSIAAW);
6521 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
6522 ARRAY_SIZE (bdesc_spe_predicates),
6523 SPE_BUILTIN_EVCMPEQ,
6524 SPE_BUILTIN_EVFSTSTLT);
6525 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
6526 ARRAY_SIZE (bdesc_spe_evsel),
6527 SPE_BUILTIN_EVSEL_CMPGTS,
6528 SPE_BUILTIN_EVSEL_FSTSTEQ);
6530 (*lang_hooks.decls.pushdecl)
6531 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
6532 opaque_V2SI_type_node));
6534 /* Initialize irregular SPE builtins. */
6536 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
6537 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
6538 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
6539 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
6540 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
6541 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
6542 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
6543 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
6544 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
6545 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
6546 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
6547 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
6548 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
6549 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
6550 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
6551 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
6552 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
6553 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
6556 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
6557 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
6558 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
6559 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
6560 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
6561 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
6562 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
6563 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
6564 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
6565 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
6566 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
6567 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
6568 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
6569 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
6570 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
6571 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
6572 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
6573 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
6574 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
6575 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
6576 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
6577 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
6580 d = (struct builtin_description *) bdesc_spe_predicates;
6581 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
6585 switch (insn_data[d->icode].operand[1].mode)
6588 type = int_ftype_int_v2si_v2si;
6591 type = int_ftype_int_v2sf_v2sf;
6597 def_builtin (d->mask, d->name, type, d->code);
6600 /* Evsel predicates. */
6601 d = (struct builtin_description *) bdesc_spe_evsel;
6602 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
6606 switch (insn_data[d->icode].operand[1].mode)
6609 type = v2si_ftype_4_v2si;
6612 type = v2sf_ftype_4_v2sf;
6618 def_builtin (d->mask, d->name, type, d->code);
6623 altivec_init_builtins (void)
6625 struct builtin_description *d;
6626 struct builtin_description_predicates *dp;
6628 tree pfloat_type_node = build_pointer_type (float_type_node);
6629 tree pint_type_node = build_pointer_type (integer_type_node);
6630 tree pshort_type_node = build_pointer_type (short_integer_type_node);
6631 tree pchar_type_node = build_pointer_type (char_type_node);
6633 tree pvoid_type_node = build_pointer_type (void_type_node);
6635 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
6636 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
6637 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
6638 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
6640 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
6642 tree int_ftype_int_v4si_v4si
6643 = build_function_type_list (integer_type_node,
6644 integer_type_node, V4SI_type_node,
6645 V4SI_type_node, NULL_TREE);
6646 tree v4sf_ftype_pcfloat
6647 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
6648 tree void_ftype_pfloat_v4sf
6649 = build_function_type_list (void_type_node,
6650 pfloat_type_node, V4SF_type_node, NULL_TREE);
6651 tree v4si_ftype_pcint
6652 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
6653 tree void_ftype_pint_v4si
6654 = build_function_type_list (void_type_node,
6655 pint_type_node, V4SI_type_node, NULL_TREE);
6656 tree v8hi_ftype_pcshort
6657 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
6658 tree void_ftype_pshort_v8hi
6659 = build_function_type_list (void_type_node,
6660 pshort_type_node, V8HI_type_node, NULL_TREE);
6661 tree v16qi_ftype_pcchar
6662 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
6663 tree void_ftype_pchar_v16qi
6664 = build_function_type_list (void_type_node,
6665 pchar_type_node, V16QI_type_node, NULL_TREE);
6666 tree void_ftype_v4si
6667 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
6668 tree v8hi_ftype_void
6669 = build_function_type (V8HI_type_node, void_list_node);
6670 tree void_ftype_void
6671 = build_function_type (void_type_node, void_list_node);
6673 = build_function_type_list (void_type_node, char_type_node, NULL_TREE);
6675 tree v16qi_ftype_long_pcvoid
6676 = build_function_type_list (V16QI_type_node,
6677 long_integer_type_node, pcvoid_type_node, NULL_TREE);
6678 tree v8hi_ftype_long_pcvoid
6679 = build_function_type_list (V8HI_type_node,
6680 long_integer_type_node, pcvoid_type_node, NULL_TREE);
6681 tree v4si_ftype_long_pcvoid
6682 = build_function_type_list (V4SI_type_node,
6683 long_integer_type_node, pcvoid_type_node, NULL_TREE);
6685 tree void_ftype_v4si_long_pvoid
6686 = build_function_type_list (void_type_node,
6687 V4SI_type_node, long_integer_type_node,
6688 pvoid_type_node, NULL_TREE);
6689 tree void_ftype_v16qi_long_pvoid
6690 = build_function_type_list (void_type_node,
6691 V16QI_type_node, long_integer_type_node,
6692 pvoid_type_node, NULL_TREE);
6693 tree void_ftype_v8hi_long_pvoid
6694 = build_function_type_list (void_type_node,
6695 V8HI_type_node, long_integer_type_node,
6696 pvoid_type_node, NULL_TREE);
6697 tree int_ftype_int_v8hi_v8hi
6698 = build_function_type_list (integer_type_node,
6699 integer_type_node, V8HI_type_node,
6700 V8HI_type_node, NULL_TREE);
6701 tree int_ftype_int_v16qi_v16qi
6702 = build_function_type_list (integer_type_node,
6703 integer_type_node, V16QI_type_node,
6704 V16QI_type_node, NULL_TREE);
6705 tree int_ftype_int_v4sf_v4sf
6706 = build_function_type_list (integer_type_node,
6707 integer_type_node, V4SF_type_node,
6708 V4SF_type_node, NULL_TREE);
6709 tree v4si_ftype_v4si
6710 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
6711 tree v8hi_ftype_v8hi
6712 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
6713 tree v16qi_ftype_v16qi
6714 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
6715 tree v4sf_ftype_v4sf
6716 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
6717 tree void_ftype_pcvoid_int_char
6718 = build_function_type_list (void_type_node,
6719 pcvoid_type_node, integer_type_node,
6720 char_type_node, NULL_TREE);
6722 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
6723 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
6724 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
6725 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
6726 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
6727 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
6728 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
6729 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
6730 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
6731 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
6732 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
6733 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
6734 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
6735 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
6736 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
6737 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
6738 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
6739 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
6740 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
6741 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS);
6742 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
6743 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
6744 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
6745 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
6746 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
6747 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
6748 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
6749 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
6750 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
6751 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
6752 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
6753 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
6755 /* Add the DST variants. */
6756 d = (struct builtin_description *) bdesc_dst;
6757 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6758 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_char, d->code);
6760 /* Initialize the predicates. */
6761 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6762 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6764 enum machine_mode mode1;
6767 mode1 = insn_data[dp->icode].operand[1].mode;
6772 type = int_ftype_int_v4si_v4si;
6775 type = int_ftype_int_v8hi_v8hi;
6778 type = int_ftype_int_v16qi_v16qi;
6781 type = int_ftype_int_v4sf_v4sf;
6787 def_builtin (dp->mask, dp->name, type, dp->code);
6790 /* Initialize the abs* operators. */
6791 d = (struct builtin_description *) bdesc_abs;
6792 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6794 enum machine_mode mode0;
6797 mode0 = insn_data[d->icode].operand[0].mode;
6802 type = v4si_ftype_v4si;
6805 type = v8hi_ftype_v8hi;
6808 type = v16qi_ftype_v16qi;
6811 type = v4sf_ftype_v4sf;
6817 def_builtin (d->mask, d->name, type, d->code);
6822 rs6000_common_init_builtins (void)
6824 struct builtin_description *d;
6827 tree v4sf_ftype_v4sf_v4sf_v16qi
6828 = build_function_type_list (V4SF_type_node,
6829 V4SF_type_node, V4SF_type_node,
6830 V16QI_type_node, NULL_TREE);
6831 tree v4si_ftype_v4si_v4si_v16qi
6832 = build_function_type_list (V4SI_type_node,
6833 V4SI_type_node, V4SI_type_node,
6834 V16QI_type_node, NULL_TREE);
6835 tree v8hi_ftype_v8hi_v8hi_v16qi
6836 = build_function_type_list (V8HI_type_node,
6837 V8HI_type_node, V8HI_type_node,
6838 V16QI_type_node, NULL_TREE);
6839 tree v16qi_ftype_v16qi_v16qi_v16qi
6840 = build_function_type_list (V16QI_type_node,
6841 V16QI_type_node, V16QI_type_node,
6842 V16QI_type_node, NULL_TREE);
6843 tree v4si_ftype_char
6844 = build_function_type_list (V4SI_type_node, char_type_node, NULL_TREE);
6845 tree v8hi_ftype_char
6846 = build_function_type_list (V8HI_type_node, char_type_node, NULL_TREE);
6847 tree v16qi_ftype_char
6848 = build_function_type_list (V16QI_type_node, char_type_node, NULL_TREE);
6849 tree v8hi_ftype_v16qi
6850 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
6851 tree v4sf_ftype_v4sf
6852 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
6854 tree v2si_ftype_v2si_v2si
6855 = build_function_type_list (opaque_V2SI_type_node,
6856 opaque_V2SI_type_node,
6857 opaque_V2SI_type_node, NULL_TREE);
6859 tree v2sf_ftype_v2sf_v2sf
6860 = build_function_type_list (opaque_V2SF_type_node,
6861 opaque_V2SF_type_node,
6862 opaque_V2SF_type_node, NULL_TREE);
6864 tree v2si_ftype_int_int
6865 = build_function_type_list (opaque_V2SI_type_node,
6866 integer_type_node, integer_type_node,
6869 tree v2si_ftype_v2si
6870 = build_function_type_list (opaque_V2SI_type_node,
6871 opaque_V2SI_type_node, NULL_TREE);
6873 tree v2sf_ftype_v2sf
6874 = build_function_type_list (opaque_V2SF_type_node,
6875 opaque_V2SF_type_node, NULL_TREE);
6877 tree v2sf_ftype_v2si
6878 = build_function_type_list (opaque_V2SF_type_node,
6879 opaque_V2SI_type_node, NULL_TREE);
6881 tree v2si_ftype_v2sf
6882 = build_function_type_list (opaque_V2SI_type_node,
6883 opaque_V2SF_type_node, NULL_TREE);
6885 tree v2si_ftype_v2si_char
6886 = build_function_type_list (opaque_V2SI_type_node,
6887 opaque_V2SI_type_node,
6888 char_type_node, NULL_TREE);
6890 tree v2si_ftype_int_char
6891 = build_function_type_list (opaque_V2SI_type_node,
6892 integer_type_node, char_type_node, NULL_TREE);
6894 tree v2si_ftype_char
6895 = build_function_type_list (opaque_V2SI_type_node,
6896 char_type_node, NULL_TREE);
6898 tree int_ftype_int_int
6899 = build_function_type_list (integer_type_node,
6900 integer_type_node, integer_type_node,
6903 tree v4si_ftype_v4si_v4si
6904 = build_function_type_list (V4SI_type_node,
6905 V4SI_type_node, V4SI_type_node, NULL_TREE);
6906 tree v4sf_ftype_v4si_char
6907 = build_function_type_list (V4SF_type_node,
6908 V4SI_type_node, char_type_node, NULL_TREE);
6909 tree v4si_ftype_v4sf_char
6910 = build_function_type_list (V4SI_type_node,
6911 V4SF_type_node, char_type_node, NULL_TREE);
6912 tree v4si_ftype_v4si_char
6913 = build_function_type_list (V4SI_type_node,
6914 V4SI_type_node, char_type_node, NULL_TREE);
6915 tree v8hi_ftype_v8hi_char
6916 = build_function_type_list (V8HI_type_node,
6917 V8HI_type_node, char_type_node, NULL_TREE);
6918 tree v16qi_ftype_v16qi_char
6919 = build_function_type_list (V16QI_type_node,
6920 V16QI_type_node, char_type_node, NULL_TREE);
6921 tree v16qi_ftype_v16qi_v16qi_char
6922 = build_function_type_list (V16QI_type_node,
6923 V16QI_type_node, V16QI_type_node,
6924 char_type_node, NULL_TREE);
6925 tree v8hi_ftype_v8hi_v8hi_char
6926 = build_function_type_list (V8HI_type_node,
6927 V8HI_type_node, V8HI_type_node,
6928 char_type_node, NULL_TREE);
6929 tree v4si_ftype_v4si_v4si_char
6930 = build_function_type_list (V4SI_type_node,
6931 V4SI_type_node, V4SI_type_node,
6932 char_type_node, NULL_TREE);
6933 tree v4sf_ftype_v4sf_v4sf_char
6934 = build_function_type_list (V4SF_type_node,
6935 V4SF_type_node, V4SF_type_node,
6936 char_type_node, NULL_TREE);
6937 tree v4sf_ftype_v4sf_v4sf
6938 = build_function_type_list (V4SF_type_node,
6939 V4SF_type_node, V4SF_type_node, NULL_TREE);
6940 tree v4sf_ftype_v4sf_v4sf_v4si
6941 = build_function_type_list (V4SF_type_node,
6942 V4SF_type_node, V4SF_type_node,
6943 V4SI_type_node, NULL_TREE);
6944 tree v4sf_ftype_v4sf_v4sf_v4sf
6945 = build_function_type_list (V4SF_type_node,
6946 V4SF_type_node, V4SF_type_node,
6947 V4SF_type_node, NULL_TREE);
6948 tree v4si_ftype_v4si_v4si_v4si
6949 = build_function_type_list (V4SI_type_node,
6950 V4SI_type_node, V4SI_type_node,
6951 V4SI_type_node, NULL_TREE);
6952 tree v8hi_ftype_v8hi_v8hi
6953 = build_function_type_list (V8HI_type_node,
6954 V8HI_type_node, V8HI_type_node, NULL_TREE);
6955 tree v8hi_ftype_v8hi_v8hi_v8hi
6956 = build_function_type_list (V8HI_type_node,
6957 V8HI_type_node, V8HI_type_node,
6958 V8HI_type_node, NULL_TREE);
6959 tree v4si_ftype_v8hi_v8hi_v4si
6960 = build_function_type_list (V4SI_type_node,
6961 V8HI_type_node, V8HI_type_node,
6962 V4SI_type_node, NULL_TREE);
6963 tree v4si_ftype_v16qi_v16qi_v4si
6964 = build_function_type_list (V4SI_type_node,
6965 V16QI_type_node, V16QI_type_node,
6966 V4SI_type_node, NULL_TREE);
6967 tree v16qi_ftype_v16qi_v16qi
6968 = build_function_type_list (V16QI_type_node,
6969 V16QI_type_node, V16QI_type_node, NULL_TREE);
6970 tree v4si_ftype_v4sf_v4sf
6971 = build_function_type_list (V4SI_type_node,
6972 V4SF_type_node, V4SF_type_node, NULL_TREE);
6973 tree v8hi_ftype_v16qi_v16qi
6974 = build_function_type_list (V8HI_type_node,
6975 V16QI_type_node, V16QI_type_node, NULL_TREE);
6976 tree v4si_ftype_v8hi_v8hi
6977 = build_function_type_list (V4SI_type_node,
6978 V8HI_type_node, V8HI_type_node, NULL_TREE);
6979 tree v8hi_ftype_v4si_v4si
6980 = build_function_type_list (V8HI_type_node,
6981 V4SI_type_node, V4SI_type_node, NULL_TREE);
6982 tree v16qi_ftype_v8hi_v8hi
6983 = build_function_type_list (V16QI_type_node,
6984 V8HI_type_node, V8HI_type_node, NULL_TREE);
6985 tree v4si_ftype_v16qi_v4si
6986 = build_function_type_list (V4SI_type_node,
6987 V16QI_type_node, V4SI_type_node, NULL_TREE);
6988 tree v4si_ftype_v16qi_v16qi
6989 = build_function_type_list (V4SI_type_node,
6990 V16QI_type_node, V16QI_type_node, NULL_TREE);
6991 tree v4si_ftype_v8hi_v4si
6992 = build_function_type_list (V4SI_type_node,
6993 V8HI_type_node, V4SI_type_node, NULL_TREE);
6994 tree v4si_ftype_v8hi
6995 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
6996 tree int_ftype_v4si_v4si
6997 = build_function_type_list (integer_type_node,
6998 V4SI_type_node, V4SI_type_node, NULL_TREE);
6999 tree int_ftype_v4sf_v4sf
7000 = build_function_type_list (integer_type_node,
7001 V4SF_type_node, V4SF_type_node, NULL_TREE);
7002 tree int_ftype_v16qi_v16qi
7003 = build_function_type_list (integer_type_node,
7004 V16QI_type_node, V16QI_type_node, NULL_TREE);
7005 tree int_ftype_v8hi_v8hi
7006 = build_function_type_list (integer_type_node,
7007 V8HI_type_node, V8HI_type_node, NULL_TREE);
7009 /* Add the simple ternary operators. */
7010 d = (struct builtin_description *) bdesc_3arg;
7011 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7014 enum machine_mode mode0, mode1, mode2, mode3;
7017 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7020 mode0 = insn_data[d->icode].operand[0].mode;
7021 mode1 = insn_data[d->icode].operand[1].mode;
7022 mode2 = insn_data[d->icode].operand[2].mode;
7023 mode3 = insn_data[d->icode].operand[3].mode;
7025 /* When all four are of the same mode. */
7026 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7031 type = v4si_ftype_v4si_v4si_v4si;
7034 type = v4sf_ftype_v4sf_v4sf_v4sf;
7037 type = v8hi_ftype_v8hi_v8hi_v8hi;
7040 type = v16qi_ftype_v16qi_v16qi_v16qi;
7046 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
7051 type = v4si_ftype_v4si_v4si_v16qi;
7054 type = v4sf_ftype_v4sf_v4sf_v16qi;
7057 type = v8hi_ftype_v8hi_v8hi_v16qi;
7060 type = v16qi_ftype_v16qi_v16qi_v16qi;
7066 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
7067 && mode3 == V4SImode)
7068 type = v4si_ftype_v16qi_v16qi_v4si;
7069 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
7070 && mode3 == V4SImode)
7071 type = v4si_ftype_v8hi_v8hi_v4si;
7072 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
7073 && mode3 == V4SImode)
7074 type = v4sf_ftype_v4sf_v4sf_v4si;
7076 /* vchar, vchar, vchar, 4 bit literal. */
7077 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7079 type = v16qi_ftype_v16qi_v16qi_char;
7081 /* vshort, vshort, vshort, 4 bit literal. */
7082 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7084 type = v8hi_ftype_v8hi_v8hi_char;
7086 /* vint, vint, vint, 4 bit literal. */
7087 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7089 type = v4si_ftype_v4si_v4si_char;
7091 /* vfloat, vfloat, vfloat, 4 bit literal. */
7092 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7094 type = v4sf_ftype_v4sf_v4sf_char;
7099 def_builtin (d->mask, d->name, type, d->code);
7102 /* Add the simple binary operators. */
7103 d = (struct builtin_description *) bdesc_2arg;
7104 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7106 enum machine_mode mode0, mode1, mode2;
7109 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7112 mode0 = insn_data[d->icode].operand[0].mode;
7113 mode1 = insn_data[d->icode].operand[1].mode;
7114 mode2 = insn_data[d->icode].operand[2].mode;
7116 /* When all three operands are of the same mode. */
7117 if (mode0 == mode1 && mode1 == mode2)
7122 type = v4sf_ftype_v4sf_v4sf;
7125 type = v4si_ftype_v4si_v4si;
7128 type = v16qi_ftype_v16qi_v16qi;
7131 type = v8hi_ftype_v8hi_v8hi;
7134 type = v2si_ftype_v2si_v2si;
7137 type = v2sf_ftype_v2sf_v2sf;
7140 type = int_ftype_int_int;
7147 /* A few other combos we really don't want to do manually. */
7149 /* vint, vfloat, vfloat. */
7150 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
7151 type = v4si_ftype_v4sf_v4sf;
7153 /* vshort, vchar, vchar. */
7154 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
7155 type = v8hi_ftype_v16qi_v16qi;
7157 /* vint, vshort, vshort. */
7158 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
7159 type = v4si_ftype_v8hi_v8hi;
7161 /* vshort, vint, vint. */
7162 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
7163 type = v8hi_ftype_v4si_v4si;
7165 /* vchar, vshort, vshort. */
7166 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
7167 type = v16qi_ftype_v8hi_v8hi;
7169 /* vint, vchar, vint. */
7170 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
7171 type = v4si_ftype_v16qi_v4si;
7173 /* vint, vchar, vchar. */
7174 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
7175 type = v4si_ftype_v16qi_v16qi;
7177 /* vint, vshort, vint. */
7178 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
7179 type = v4si_ftype_v8hi_v4si;
7181 /* vint, vint, 5 bit literal. */
7182 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
7183 type = v4si_ftype_v4si_char;
7185 /* vshort, vshort, 5 bit literal. */
7186 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
7187 type = v8hi_ftype_v8hi_char;
7189 /* vchar, vchar, 5 bit literal. */
7190 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
7191 type = v16qi_ftype_v16qi_char;
7193 /* vfloat, vint, 5 bit literal. */
7194 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
7195 type = v4sf_ftype_v4si_char;
7197 /* vint, vfloat, 5 bit literal. */
7198 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
7199 type = v4si_ftype_v4sf_char;
7201 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
7202 type = v2si_ftype_int_int;
7204 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
7205 type = v2si_ftype_v2si_char;
7207 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
7208 type = v2si_ftype_int_char;
7211 else if (mode0 == SImode)
7216 type = int_ftype_v4si_v4si;
7219 type = int_ftype_v4sf_v4sf;
7222 type = int_ftype_v16qi_v16qi;
7225 type = int_ftype_v8hi_v8hi;
7235 def_builtin (d->mask, d->name, type, d->code);
7238 /* Add the simple unary operators. */
7239 d = (struct builtin_description *) bdesc_1arg;
7240 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7242 enum machine_mode mode0, mode1;
7245 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7248 mode0 = insn_data[d->icode].operand[0].mode;
7249 mode1 = insn_data[d->icode].operand[1].mode;
7251 if (mode0 == V4SImode && mode1 == QImode)
7252 type = v4si_ftype_char;
7253 else if (mode0 == V8HImode && mode1 == QImode)
7254 type = v8hi_ftype_char;
7255 else if (mode0 == V16QImode && mode1 == QImode)
7256 type = v16qi_ftype_char;
7257 else if (mode0 == V4SFmode && mode1 == V4SFmode)
7258 type = v4sf_ftype_v4sf;
7259 else if (mode0 == V8HImode && mode1 == V16QImode)
7260 type = v8hi_ftype_v16qi;
7261 else if (mode0 == V4SImode && mode1 == V8HImode)
7262 type = v4si_ftype_v8hi;
7263 else if (mode0 == V2SImode && mode1 == V2SImode)
7264 type = v2si_ftype_v2si;
7265 else if (mode0 == V2SFmode && mode1 == V2SFmode)
7266 type = v2sf_ftype_v2sf;
7267 else if (mode0 == V2SFmode && mode1 == V2SImode)
7268 type = v2sf_ftype_v2si;
7269 else if (mode0 == V2SImode && mode1 == V2SFmode)
7270 type = v2si_ftype_v2sf;
7271 else if (mode0 == V2SImode && mode1 == QImode)
7272 type = v2si_ftype_char;
7276 def_builtin (d->mask, d->name, type, d->code);
7281 rs6000_init_libfuncs (void)
7283 if (!TARGET_HARD_FLOAT)
7286 if (DEFAULT_ABI != ABI_V4)
7288 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
7290 /* AIX library routines for float->int conversion. */
7291 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
7292 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
7295 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
7296 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
7297 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
7298 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
7299 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
7303 /* 32-bit SVR4 quad floating point routines. */
7305 set_optab_libfunc (add_optab, TFmode, "_q_add");
7306 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
7307 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
7308 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
7309 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
7310 if (TARGET_PPC_GPOPT || TARGET_POWER2)
7311 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
7313 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
7314 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
7315 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
7316 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
7317 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
7318 set_optab_libfunc (le_optab, TFmode, "_q_fle");
7320 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
7321 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
7322 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
7323 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
7324 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
7325 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
7326 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
7330 /* Expand a block move operation, and return 1 if successful. Return 0
7331 if we should let the compiler generate normal code.
7333 operands[0] is the destination
7334 operands[1] is the source
7335 operands[2] is the length
7336 operands[3] is the alignment */
7338 #define MAX_MOVE_REG 4
7341 expand_block_move (rtx operands[])
7343 rtx orig_dest = operands[0];
7344 rtx orig_src = operands[1];
7345 rtx bytes_rtx = operands[2];
7346 rtx align_rtx = operands[3];
7347 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
7352 rtx stores[MAX_MOVE_REG];
7355 /* If this is not a fixed size move, just call memcpy */
7359 /* If this is not a fixed size alignment, abort */
7360 if (GET_CODE (align_rtx) != CONST_INT)
7362 align = INTVAL (align_rtx);
7364 /* Anything to move? */
7365 bytes = INTVAL (bytes_rtx);
7369 /* store_one_arg depends on expand_block_move to handle at least the size of
7370 reg_parm_stack_space. */
7371 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7374 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7377 rtx (*movstrsi) (rtx, rtx, rtx, rtx);
7378 rtx (*mov) (rtx, rtx);
7380 enum machine_mode mode = BLKmode;
7384 && bytes > 24 /* move up to 32 bytes at a time */
7392 && ! fixed_regs[12])
7394 move_bytes = (bytes > 32) ? 32 : bytes;
7395 gen_func.movstrsi = gen_movstrsi_8reg;
7397 else if (TARGET_STRING
7398 && bytes > 16 /* move up to 24 bytes at a time */
7404 && ! fixed_regs[10])
7406 move_bytes = (bytes > 24) ? 24 : bytes;
7407 gen_func.movstrsi = gen_movstrsi_6reg;
7409 else if (TARGET_STRING
7410 && bytes > 8 /* move up to 16 bytes at a time */
7416 move_bytes = (bytes > 16) ? 16 : bytes;
7417 gen_func.movstrsi = gen_movstrsi_4reg;
7419 else if (bytes >= 8 && TARGET_POWERPC64
7420 /* 64-bit loads and stores require word-aligned
7422 && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
7426 gen_func.mov = gen_movdi;
7428 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
7429 { /* move up to 8 bytes at a time */
7430 move_bytes = (bytes > 8) ? 8 : bytes;
7431 gen_func.movstrsi = gen_movstrsi_2reg;
7433 else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
7434 { /* move 4 bytes */
7437 gen_func.mov = gen_movsi;
7439 else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT))
7440 { /* move 2 bytes */
7443 gen_func.mov = gen_movhi;
7445 else if (TARGET_STRING && bytes > 1)
7446 { /* move up to 4 bytes at a time */
7447 move_bytes = (bytes > 4) ? 4 : bytes;
7448 gen_func.movstrsi = gen_movstrsi_1reg;
7450 else /* move 1 byte at a time */
7454 gen_func.mov = gen_movqi;
7457 src = adjust_address (orig_src, mode, offset);
7458 dest = adjust_address (orig_dest, mode, offset);
7460 if (mode != BLKmode)
7462 rtx tmp_reg = gen_reg_rtx (mode);
7464 emit_insn ((*gen_func.mov) (tmp_reg, src));
7465 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
7468 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
7471 for (i = 0; i < num_reg; i++)
7472 emit_insn (stores[i]);
7476 if (mode == BLKmode)
7478 /* Move the address into scratch registers. The movstrsi
7479 patterns require zero offset. */
7480 if (!REG_P (XEXP (src, 0)))
7482 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
7483 src = replace_equiv_address (src, src_reg);
7485 set_mem_size (src, GEN_INT (move_bytes));
7487 if (!REG_P (XEXP (dest, 0)))
7489 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
7490 dest = replace_equiv_address (dest, dest_reg);
7492 set_mem_size (dest, GEN_INT (move_bytes));
7494 emit_insn ((*gen_func.movstrsi) (dest, src,
7495 GEN_INT (move_bytes & 31),
7504 /* Return 1 if OP is a load multiple operation. It is known to be a
7505 PARALLEL and the first section will be tested. */
7508 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7510 int count = XVECLEN (op, 0);
7511 unsigned int dest_regno;
7515 /* Perform a quick check so we don't blow up below. */
7517 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7518 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7519 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
7522 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7523 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
7525 for (i = 1; i < count; i++)
7527 rtx elt = XVECEXP (op, 0, i);
7529 if (GET_CODE (elt) != SET
7530 || GET_CODE (SET_DEST (elt)) != REG
7531 || GET_MODE (SET_DEST (elt)) != SImode
7532 || REGNO (SET_DEST (elt)) != dest_regno + i
7533 || GET_CODE (SET_SRC (elt)) != MEM
7534 || GET_MODE (SET_SRC (elt)) != SImode
7535 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
7536 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
7537 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
7538 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
7545 /* Similar, but tests for store multiple. Here, the second vector element
7546 is a CLOBBER. It will be tested later. */
7549 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7551 int count = XVECLEN (op, 0) - 1;
7552 unsigned int src_regno;
7556 /* Perform a quick check so we don't blow up below. */
7558 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7559 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
7560 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
7563 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7564 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
7566 for (i = 1; i < count; i++)
7568 rtx elt = XVECEXP (op, 0, i + 1);
7570 if (GET_CODE (elt) != SET
7571 || GET_CODE (SET_SRC (elt)) != REG
7572 || GET_MODE (SET_SRC (elt)) != SImode
7573 || REGNO (SET_SRC (elt)) != src_regno + i
7574 || GET_CODE (SET_DEST (elt)) != MEM
7575 || GET_MODE (SET_DEST (elt)) != SImode
7576 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
7577 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
7578 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
7579 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
7586 /* Return a string to perform a load_multiple operation.
7587 operands[0] is the vector.
7588 operands[1] is the source address.
7589 operands[2] is the first destination register. */
7592 rs6000_output_load_multiple (rtx operands[3])
7594 /* We have to handle the case where the pseudo used to contain the address
7595 is assigned to one of the output registers. */
7597 int words = XVECLEN (operands[0], 0);
7600 if (XVECLEN (operands[0], 0) == 1)
7601 return "{l|lwz} %2,0(%1)";
7603 for (i = 0; i < words; i++)
7604 if (refers_to_regno_p (REGNO (operands[2]) + i,
7605 REGNO (operands[2]) + i + 1, operands[1], 0))
7609 xop[0] = GEN_INT (4 * (words-1));
7610 xop[1] = operands[1];
7611 xop[2] = operands[2];
7612 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
7617 xop[0] = GEN_INT (4 * (words-1));
7618 xop[1] = operands[1];
7619 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7620 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
7625 for (j = 0; j < words; j++)
7628 xop[0] = GEN_INT (j * 4);
7629 xop[1] = operands[1];
7630 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
7631 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
7633 xop[0] = GEN_INT (i * 4);
7634 xop[1] = operands[1];
7635 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
7640 return "{lsi|lswi} %2,%1,%N0";
7643 /* Return 1 for a parallel vrsave operation. */
7646 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7648 int count = XVECLEN (op, 0);
7649 unsigned int dest_regno, src_regno;
7653 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7654 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7655 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
7658 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7659 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7661 if (dest_regno != VRSAVE_REGNO
7662 && src_regno != VRSAVE_REGNO)
7665 for (i = 1; i < count; i++)
7667 rtx elt = XVECEXP (op, 0, i);
7669 if (GET_CODE (elt) != CLOBBER
7670 && GET_CODE (elt) != SET)
7677 /* Return 1 for an PARALLEL suitable for mfcr. */
7680 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7682 int count = XVECLEN (op, 0);
7685 /* Perform a quick check so we don't blow up below. */
7687 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7688 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
7689 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
7692 for (i = 0; i < count; i++)
7694 rtx exp = XVECEXP (op, 0, i);
7699 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
7701 if (GET_CODE (src_reg) != REG
7702 || GET_MODE (src_reg) != CCmode
7703 || ! CR_REGNO_P (REGNO (src_reg)))
7706 if (GET_CODE (exp) != SET
7707 || GET_CODE (SET_DEST (exp)) != REG
7708 || GET_MODE (SET_DEST (exp)) != SImode
7709 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
7711 unspec = SET_SRC (exp);
7712 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
7714 if (GET_CODE (unspec) != UNSPEC
7715 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
7716 || XVECLEN (unspec, 0) != 2
7717 || XVECEXP (unspec, 0, 0) != src_reg
7718 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
7719 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
7725 /* Return 1 for an PARALLEL suitable for mtcrf. */
7728 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7730 int count = XVECLEN (op, 0);
7734 /* Perform a quick check so we don't blow up below. */
7736 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7737 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
7738 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
7740 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
7742 if (GET_CODE (src_reg) != REG
7743 || GET_MODE (src_reg) != SImode
7744 || ! INT_REGNO_P (REGNO (src_reg)))
7747 for (i = 0; i < count; i++)
7749 rtx exp = XVECEXP (op, 0, i);
7753 if (GET_CODE (exp) != SET
7754 || GET_CODE (SET_DEST (exp)) != REG
7755 || GET_MODE (SET_DEST (exp)) != CCmode
7756 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
7758 unspec = SET_SRC (exp);
7759 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
7761 if (GET_CODE (unspec) != UNSPEC
7762 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
7763 || XVECLEN (unspec, 0) != 2
7764 || XVECEXP (unspec, 0, 0) != src_reg
7765 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
7766 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
7772 /* Return 1 for an PARALLEL suitable for lmw. */
7775 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7777 int count = XVECLEN (op, 0);
7778 unsigned int dest_regno;
7780 unsigned int base_regno;
7781 HOST_WIDE_INT offset;
7784 /* Perform a quick check so we don't blow up below. */
7786 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7787 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7788 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
7791 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7792 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
7795 || count != 32 - (int) dest_regno)
7798 if (legitimate_indirect_address_p (src_addr, 0))
7801 base_regno = REGNO (src_addr);
7802 if (base_regno == 0)
7805 else if (legitimate_offset_address_p (SImode, src_addr, 0))
7807 offset = INTVAL (XEXP (src_addr, 1));
7808 base_regno = REGNO (XEXP (src_addr, 0));
7813 for (i = 0; i < count; i++)
7815 rtx elt = XVECEXP (op, 0, i);
7818 HOST_WIDE_INT newoffset;
7820 if (GET_CODE (elt) != SET
7821 || GET_CODE (SET_DEST (elt)) != REG
7822 || GET_MODE (SET_DEST (elt)) != SImode
7823 || REGNO (SET_DEST (elt)) != dest_regno + i
7824 || GET_CODE (SET_SRC (elt)) != MEM
7825 || GET_MODE (SET_SRC (elt)) != SImode)
7827 newaddr = XEXP (SET_SRC (elt), 0);
7828 if (legitimate_indirect_address_p (newaddr, 0))
7833 else if (legitimate_offset_address_p (SImode, newaddr, 0))
7835 addr_reg = XEXP (newaddr, 0);
7836 newoffset = INTVAL (XEXP (newaddr, 1));
7840 if (REGNO (addr_reg) != base_regno
7841 || newoffset != offset + 4 * i)
7848 /* Return 1 for an PARALLEL suitable for stmw. */
7851 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7853 int count = XVECLEN (op, 0);
7854 unsigned int src_regno;
7856 unsigned int base_regno;
7857 HOST_WIDE_INT offset;
7860 /* Perform a quick check so we don't blow up below. */
7862 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7863 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
7864 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
7867 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7868 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
7871 || count != 32 - (int) src_regno)
7874 if (legitimate_indirect_address_p (dest_addr, 0))
7877 base_regno = REGNO (dest_addr);
7878 if (base_regno == 0)
7881 else if (legitimate_offset_address_p (SImode, dest_addr, 0))
7883 offset = INTVAL (XEXP (dest_addr, 1));
7884 base_regno = REGNO (XEXP (dest_addr, 0));
7889 for (i = 0; i < count; i++)
7891 rtx elt = XVECEXP (op, 0, i);
7894 HOST_WIDE_INT newoffset;
7896 if (GET_CODE (elt) != SET
7897 || GET_CODE (SET_SRC (elt)) != REG
7898 || GET_MODE (SET_SRC (elt)) != SImode
7899 || REGNO (SET_SRC (elt)) != src_regno + i
7900 || GET_CODE (SET_DEST (elt)) != MEM
7901 || GET_MODE (SET_DEST (elt)) != SImode)
7903 newaddr = XEXP (SET_DEST (elt), 0);
7904 if (legitimate_indirect_address_p (newaddr, 0))
7909 else if (legitimate_offset_address_p (SImode, newaddr, 0))
7911 addr_reg = XEXP (newaddr, 0);
7912 newoffset = INTVAL (XEXP (newaddr, 1));
7916 if (REGNO (addr_reg) != base_regno
7917 || newoffset != offset + 4 * i)
7924 /* A validation routine: say whether CODE, a condition code, and MODE
7925 match. The other alternatives either don't make sense or should
7926 never be generated. */
7929 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
7931 if (GET_RTX_CLASS (code) != '<'
7932 || GET_MODE_CLASS (mode) != MODE_CC)
7935 /* These don't make sense. */
7936 if ((code == GT || code == LT || code == GE || code == LE)
7937 && mode == CCUNSmode)
7940 if ((code == GTU || code == LTU || code == GEU || code == LEU)
7941 && mode != CCUNSmode)
7944 if (mode != CCFPmode
7945 && (code == ORDERED || code == UNORDERED
7946 || code == UNEQ || code == LTGT
7947 || code == UNGT || code == UNLT
7948 || code == UNGE || code == UNLE))
7951 /* These should never be generated except for
7952 flag_finite_math_only. */
7953 if (mode == CCFPmode
7954 && ! flag_finite_math_only
7955 && (code == LE || code == GE
7956 || code == UNEQ || code == LTGT
7957 || code == UNGT || code == UNLT))
7960 /* These are invalid; the information is not there. */
7961 if (mode == CCEQmode
7962 && code != EQ && code != NE)
7966 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
7967 We only check the opcode against the mode of the CC value here. */
7970 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7972 enum rtx_code code = GET_CODE (op);
7973 enum machine_mode cc_mode;
7975 if (GET_RTX_CLASS (code) != '<')
7978 cc_mode = GET_MODE (XEXP (op, 0));
7979 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
7982 validate_condition_mode (code, cc_mode);
7987 /* Return 1 if OP is a comparison operation that is valid for a branch
7988 insn and which is true if the corresponding bit in the CC register
7992 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
7996 if (! branch_comparison_operator (op, mode))
7999 code = GET_CODE (op);
8000 return (code == EQ || code == LT || code == GT
8001 || (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE)
8002 || code == LTU || code == GTU
8003 || code == UNORDERED);
8006 /* Return 1 if OP is a comparison operation that is valid for an scc
8007 insn: it must be a positive comparison. */
8010 scc_comparison_operator (rtx op, enum machine_mode mode)
8012 return branch_positive_comparison_operator (op, mode);
8016 trap_comparison_operator (rtx op, enum machine_mode mode)
8018 if (mode != VOIDmode && mode != GET_MODE (op))
8020 return GET_RTX_CLASS (GET_CODE (op)) == '<';
8024 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8026 enum rtx_code code = GET_CODE (op);
8027 return (code == AND || code == IOR || code == XOR);
8031 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8033 enum rtx_code code = GET_CODE (op);
8034 return (code == IOR || code == XOR);
8038 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8040 enum rtx_code code = GET_CODE (op);
8041 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
8044 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8045 mask required to convert the result of a rotate insn into a shift
8046 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
8049 includes_lshift_p (rtx shiftop, rtx andop)
8051 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8053 shift_mask <<= INTVAL (shiftop);
8055 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8058 /* Similar, but for right shift. */
8061 includes_rshift_p (rtx shiftop, rtx andop)
8063 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8065 shift_mask >>= INTVAL (shiftop);
8067 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8070 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8071 to perform a left shift. It must have exactly SHIFTOP least
8072 significant 0's, then one or more 1's, then zero or more 0's. */
8075 includes_rldic_lshift_p (rtx shiftop, rtx andop)
8077 if (GET_CODE (andop) == CONST_INT)
8079 HOST_WIDE_INT c, lsb, shift_mask;
8082 if (c == 0 || c == ~0)
8086 shift_mask <<= INTVAL (shiftop);
8088 /* Find the least significant one bit. */
8091 /* It must coincide with the LSB of the shift mask. */
8092 if (-lsb != shift_mask)
8095 /* Invert to look for the next transition (if any). */
8098 /* Remove the low group of ones (originally low group of zeros). */
8101 /* Again find the lsb, and check we have all 1's above. */
8105 else if (GET_CODE (andop) == CONST_DOUBLE
8106 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8108 HOST_WIDE_INT low, high, lsb;
8109 HOST_WIDE_INT shift_mask_low, shift_mask_high;
8111 low = CONST_DOUBLE_LOW (andop);
8112 if (HOST_BITS_PER_WIDE_INT < 64)
8113 high = CONST_DOUBLE_HIGH (andop);
8115 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
8116 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
8119 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8121 shift_mask_high = ~0;
8122 if (INTVAL (shiftop) > 32)
8123 shift_mask_high <<= INTVAL (shiftop) - 32;
8127 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8134 return high == -lsb;
8137 shift_mask_low = ~0;
8138 shift_mask_low <<= INTVAL (shiftop);
8142 if (-lsb != shift_mask_low)
8145 if (HOST_BITS_PER_WIDE_INT < 64)
8150 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8153 return high == -lsb;
8157 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8163 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8164 to perform a left shift. It must have SHIFTOP or more least
8165 significant 0's, with the remainder of the word 1's. */
8168 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
8170 if (GET_CODE (andop) == CONST_INT)
8172 HOST_WIDE_INT c, lsb, shift_mask;
8175 shift_mask <<= INTVAL (shiftop);
8178 /* Find the least significant one bit. */
8181 /* It must be covered by the shift mask.
8182 This test also rejects c == 0. */
8183 if ((lsb & shift_mask) == 0)
8186 /* Check we have all 1's above the transition, and reject all 1's. */
8187 return c == -lsb && lsb != 1;
8189 else if (GET_CODE (andop) == CONST_DOUBLE
8190 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8192 HOST_WIDE_INT low, lsb, shift_mask_low;
8194 low = CONST_DOUBLE_LOW (andop);
8196 if (HOST_BITS_PER_WIDE_INT < 64)
8198 HOST_WIDE_INT high, shift_mask_high;
8200 high = CONST_DOUBLE_HIGH (andop);
8204 shift_mask_high = ~0;
8205 if (INTVAL (shiftop) > 32)
8206 shift_mask_high <<= INTVAL (shiftop) - 32;
8210 if ((lsb & shift_mask_high) == 0)
8213 return high == -lsb;
8219 shift_mask_low = ~0;
8220 shift_mask_low <<= INTVAL (shiftop);
8224 if ((lsb & shift_mask_low) == 0)
8227 return low == -lsb && lsb != 1;
8233 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
8234 for lfq and stfq insns.
8236 Note reg1 and reg2 *must* be hard registers. To be sure we will
8237 abort if we are passed pseudo registers. */
8240 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
8242 /* We might have been passed a SUBREG. */
8243 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8246 return (REGNO (reg1) == REGNO (reg2) - 1);
8249 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8250 addr1 and addr2 must be in consecutive memory locations
8251 (addr2 == addr1 + 8). */
8254 addrs_ok_for_quad_peep (rtx addr1, rtx addr2)
8259 /* Extract an offset (if used) from the first addr. */
8260 if (GET_CODE (addr1) == PLUS)
8262 /* If not a REG, return zero. */
8263 if (GET_CODE (XEXP (addr1, 0)) != REG)
8267 reg1 = REGNO (XEXP (addr1, 0));
8268 /* The offset must be constant! */
8269 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8271 offset1 = INTVAL (XEXP (addr1, 1));
8274 else if (GET_CODE (addr1) != REG)
8278 reg1 = REGNO (addr1);
8279 /* This was a simple (mem (reg)) expression. Offset is 0. */
8283 /* Make sure the second address is a (mem (plus (reg) (const_int)))
8284 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
8285 register as addr1. */
8286 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
8288 if (GET_CODE (addr2) != PLUS)
8291 if (GET_CODE (XEXP (addr2, 0)) != REG
8292 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8295 if (reg1 != REGNO (XEXP (addr2, 0)))
8298 /* The offset for the second addr must be 8 more than the first addr. */
8299 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8302 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
8307 /* Return the register class of a scratch register needed to copy IN into
8308 or out of a register in CLASS in MODE. If it can be done directly,
8309 NO_REGS is returned. */
8312 secondary_reload_class (enum reg_class class,
8313 enum machine_mode mode ATTRIBUTE_UNUSED,
8318 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8320 && MACHOPIC_INDIRECT
8324 /* We cannot copy a symbolic operand directly into anything
8325 other than BASE_REGS for TARGET_ELF. So indicate that a
8326 register from BASE_REGS is needed as an intermediate
8329 On Darwin, pic addresses require a load from memory, which
8330 needs a base register. */
8331 if (class != BASE_REGS
8332 && (GET_CODE (in) == SYMBOL_REF
8333 || GET_CODE (in) == HIGH
8334 || GET_CODE (in) == LABEL_REF
8335 || GET_CODE (in) == CONST))
8339 if (GET_CODE (in) == REG)
8342 if (regno >= FIRST_PSEUDO_REGISTER)
8344 regno = true_regnum (in);
8345 if (regno >= FIRST_PSEUDO_REGISTER)
8349 else if (GET_CODE (in) == SUBREG)
8351 regno = true_regnum (in);
8352 if (regno >= FIRST_PSEUDO_REGISTER)
8358 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8360 if (class == GENERAL_REGS || class == BASE_REGS
8361 || (regno >= 0 && INT_REGNO_P (regno)))
8364 /* Constants, memory, and FP registers can go into FP registers. */
8365 if ((regno == -1 || FP_REGNO_P (regno))
8366 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8369 /* Memory, and AltiVec registers can go into AltiVec registers. */
8370 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8371 && class == ALTIVEC_REGS)
8374 /* We can copy among the CR registers. */
8375 if ((class == CR_REGS || class == CR0_REGS)
8376 && regno >= 0 && CR_REGNO_P (regno))
8379 /* Otherwise, we need GENERAL_REGS. */
8380 return GENERAL_REGS;
8383 /* Given a comparison operation, return the bit number in CCR to test. We
8384 know this is a valid comparison.
8386 SCC_P is 1 if this is for an scc. That means that %D will have been
8387 used instead of %C, so the bits will be in different places.
8389 Return -1 if OP isn't a valid comparison for some reason. */
8392 ccr_bit (rtx op, int scc_p)
8394 enum rtx_code code = GET_CODE (op);
8395 enum machine_mode cc_mode;
8400 if (GET_RTX_CLASS (code) != '<')
8405 if (GET_CODE (reg) != REG
8406 || ! CR_REGNO_P (REGNO (reg)))
8409 cc_mode = GET_MODE (reg);
8410 cc_regnum = REGNO (reg);
8411 base_bit = 4 * (cc_regnum - CR0_REGNO);
8413 validate_condition_mode (code, cc_mode);
8415 /* When generating a sCOND operation, only positive conditions are
8417 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8418 && code != GTU && code != LTU)
8424 if (TARGET_E500 && !TARGET_FPRS
8425 && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
8426 return base_bit + 1;
8427 return scc_p ? base_bit + 3 : base_bit + 2;
8429 if (TARGET_E500 && !TARGET_FPRS
8430 && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
8431 return base_bit + 1;
8432 return base_bit + 2;
8433 case GT: case GTU: case UNLE:
8434 return base_bit + 1;
8435 case LT: case LTU: case UNGE:
8437 case ORDERED: case UNORDERED:
8438 return base_bit + 3;
8441 /* If scc, we will have done a cror to put the bit in the
8442 unordered position. So test that bit. For integer, this is ! LT
8443 unless this is an scc insn. */
8444 return scc_p ? base_bit + 3 : base_bit;
8447 return scc_p ? base_bit + 3 : base_bit + 1;
8454 /* Return the GOT register. */
8457 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
8459 /* The second flow pass currently (June 1999) can't update
8460 regs_ever_live without disturbing other parts of the compiler, so
8461 update it here to make the prolog/epilogue code happy. */
8462 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
8463 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
8465 current_function_uses_pic_offset_table = 1;
8467 return pic_offset_table_rtx;
8470 /* Function to init struct machine_function.
8471 This will be called, via a pointer variable,
8472 from push_function_context. */
8474 static struct machine_function *
8475 rs6000_init_machine_status (void)
8477 return ggc_alloc_cleared (sizeof (machine_function));
8480 /* These macros test for integers and extract the low-order bits. */
8482 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
8483 && GET_MODE (X) == VOIDmode)
8485 #define INT_LOWPART(X) \
8486 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
8492 unsigned long val = INT_LOWPART (op);
8494 /* If the high bit is zero, the value is the first 1 bit we find
8496 if ((val & 0x80000000) == 0)
8498 if ((val & 0xffffffff) == 0)
8502 while (((val <<= 1) & 0x80000000) == 0)
8507 /* If the high bit is set and the low bit is not, or the mask is all
8508 1's, the value is zero. */
8509 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
8512 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
8515 while (((val >>= 1) & 1) != 0)
8525 unsigned long val = INT_LOWPART (op);
8527 /* If the low bit is zero, the value is the first 1 bit we find from
8531 if ((val & 0xffffffff) == 0)
8535 while (((val >>= 1) & 1) == 0)
8541 /* If the low bit is set and the high bit is not, or the mask is all
8542 1's, the value is 31. */
8543 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
8546 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
8549 while (((val <<= 1) & 0x80000000) != 0)
8555 /* Locate some local-dynamic symbol still in use by this function
8556 so that we can print its name in some tls_ld pattern. */
8559 rs6000_get_some_local_dynamic_name (void)
8563 if (cfun->machine->some_ld_name)
8564 return cfun->machine->some_ld_name;
8566 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8568 && for_each_rtx (&PATTERN (insn),
8569 rs6000_get_some_local_dynamic_name_1, 0))
8570 return cfun->machine->some_ld_name;
8575 /* Helper function for rs6000_get_some_local_dynamic_name. */
8578 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8582 if (GET_CODE (x) == SYMBOL_REF)
8584 const char *str = XSTR (x, 0);
8585 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8587 cfun->machine->some_ld_name = str;
8595 /* Print an operand. Recognize special options, documented below. */
8598 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
8599 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
8601 #define SMALL_DATA_RELOC "sda21"
8602 #define SMALL_DATA_REG 0
8606 print_operand (FILE *file, rtx x, int code)
8610 unsigned HOST_WIDE_INT uval;
8615 /* Write out an instruction after the call which may be replaced
8616 with glue code by the loader. This depends on the AIX version. */
8617 asm_fprintf (file, RS6000_CALL_GLUE);
8620 /* %a is output_address. */
8623 /* If X is a constant integer whose low-order 5 bits are zero,
8624 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
8625 in the AIX assembler where "sri" with a zero shift count
8626 writes a trash instruction. */
8627 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
8634 /* If constant, low-order 16 bits of constant, unsigned.
8635 Otherwise, write normally. */
8637 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
8639 print_operand (file, x, 0);
8643 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
8644 for 64-bit mask direction. */
8645 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
8648 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
8652 /* X is a CR register. Print the number of the EQ bit of the CR */
8653 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8654 output_operand_lossage ("invalid %%E value");
8656 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
8660 /* X is a CR register. Print the shift count needed to move it
8661 to the high-order four bits. */
8662 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8663 output_operand_lossage ("invalid %%f value");
8665 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
8669 /* Similar, but print the count for the rotate in the opposite
8671 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8672 output_operand_lossage ("invalid %%F value");
8674 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
8678 /* X is a constant integer. If it is negative, print "m",
8679 otherwise print "z". This is to make an aze or ame insn. */
8680 if (GET_CODE (x) != CONST_INT)
8681 output_operand_lossage ("invalid %%G value");
8682 else if (INTVAL (x) >= 0)
8689 /* If constant, output low-order five bits. Otherwise, write
8692 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
8694 print_operand (file, x, 0);
8698 /* If constant, output low-order six bits. Otherwise, write
8701 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
8703 print_operand (file, x, 0);
8707 /* Print `i' if this is a constant, else nothing. */
8713 /* Write the bit number in CCR for jump. */
8716 output_operand_lossage ("invalid %%j code");
8718 fprintf (file, "%d", i);
8722 /* Similar, but add one for shift count in rlinm for scc and pass
8723 scc flag to `ccr_bit'. */
8726 output_operand_lossage ("invalid %%J code");
8728 /* If we want bit 31, write a shift count of zero, not 32. */
8729 fprintf (file, "%d", i == 31 ? 0 : i + 1);
8733 /* X must be a constant. Write the 1's complement of the
8736 output_operand_lossage ("invalid %%k value");
8738 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
8742 /* X must be a symbolic constant on ELF. Write an
8743 expression suitable for an 'addi' that adds in the low 16
8745 if (GET_CODE (x) != CONST)
8747 print_operand_address (file, x);
8752 if (GET_CODE (XEXP (x, 0)) != PLUS
8753 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
8754 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
8755 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
8756 output_operand_lossage ("invalid %%K value");
8757 print_operand_address (file, XEXP (XEXP (x, 0), 0));
8759 /* For GNU as, there must be a non-alphanumeric character
8760 between 'l' and the number. The '-' is added by
8761 print_operand() already. */
8762 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
8764 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
8768 /* %l is output_asm_label. */
8771 /* Write second word of DImode or DFmode reference. Works on register
8772 or non-indexed memory only. */
8773 if (GET_CODE (x) == REG)
8774 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
8775 else if (GET_CODE (x) == MEM)
8777 /* Handle possible auto-increment. Since it is pre-increment and
8778 we have already done it, we can just use an offset of word. */
8779 if (GET_CODE (XEXP (x, 0)) == PRE_INC
8780 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
8781 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
8784 output_address (XEXP (adjust_address_nv (x, SImode,
8788 if (small_data_operand (x, GET_MODE (x)))
8789 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
8790 reg_names[SMALL_DATA_REG]);
8795 /* MB value for a mask operand. */
8796 if (! mask_operand (x, SImode))
8797 output_operand_lossage ("invalid %%m value");
8799 fprintf (file, "%d", extract_MB (x));
8803 /* ME value for a mask operand. */
8804 if (! mask_operand (x, SImode))
8805 output_operand_lossage ("invalid %%M value");
8807 fprintf (file, "%d", extract_ME (x));
8810 /* %n outputs the negative of its operand. */
8813 /* Write the number of elements in the vector times 4. */
8814 if (GET_CODE (x) != PARALLEL)
8815 output_operand_lossage ("invalid %%N value");
8817 fprintf (file, "%d", XVECLEN (x, 0) * 4);
8821 /* Similar, but subtract 1 first. */
8822 if (GET_CODE (x) != PARALLEL)
8823 output_operand_lossage ("invalid %%O value");
8825 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
8829 /* X is a CONST_INT that is a power of two. Output the logarithm. */
8831 || INT_LOWPART (x) < 0
8832 || (i = exact_log2 (INT_LOWPART (x))) < 0)
8833 output_operand_lossage ("invalid %%p value");
8835 fprintf (file, "%d", i);
8839 /* The operand must be an indirect memory reference. The result
8840 is the register number. */
8841 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
8842 || REGNO (XEXP (x, 0)) >= 32)
8843 output_operand_lossage ("invalid %%P value");
8845 fprintf (file, "%d", REGNO (XEXP (x, 0)));
8849 /* This outputs the logical code corresponding to a boolean
8850 expression. The expression may have one or both operands
8851 negated (if one, only the first one). For condition register
8852 logical operations, it will also treat the negated
8853 CR codes as NOTs, but not handle NOTs of them. */
8855 const char *const *t = 0;
8857 enum rtx_code code = GET_CODE (x);
8858 static const char * const tbl[3][3] = {
8859 { "and", "andc", "nor" },
8860 { "or", "orc", "nand" },
8861 { "xor", "eqv", "xor" } };
8865 else if (code == IOR)
8867 else if (code == XOR)
8870 output_operand_lossage ("invalid %%q value");
8872 if (GET_CODE (XEXP (x, 0)) != NOT)
8876 if (GET_CODE (XEXP (x, 1)) == NOT)
8894 /* X is a CR register. Print the mask for `mtcrf'. */
8895 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8896 output_operand_lossage ("invalid %%R value");
8898 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
8902 /* Low 5 bits of 32 - value */
8904 output_operand_lossage ("invalid %%s value");
8906 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
8910 /* PowerPC64 mask position. All 0's is excluded.
8911 CONST_INT 32-bit mask is considered sign-extended so any
8912 transition must occur within the CONST_INT, not on the boundary. */
8913 if (! mask64_operand (x, DImode))
8914 output_operand_lossage ("invalid %%S value");
8916 uval = INT_LOWPART (x);
8918 if (uval & 1) /* Clear Left */
8920 #if HOST_BITS_PER_WIDE_INT > 64
8921 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
8925 else /* Clear Right */
8928 #if HOST_BITS_PER_WIDE_INT > 64
8929 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
8937 fprintf (file, "%d", i);
8941 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
8942 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
8945 /* Bit 3 is OV bit. */
8946 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
8948 /* If we want bit 31, write a shift count of zero, not 32. */
8949 fprintf (file, "%d", i == 31 ? 0 : i + 1);
8953 /* Print the symbolic name of a branch target register. */
8954 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
8955 && REGNO (x) != COUNT_REGISTER_REGNUM))
8956 output_operand_lossage ("invalid %%T value");
8957 else if (REGNO (x) == LINK_REGISTER_REGNUM)
8958 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
8960 fputs ("ctr", file);
8964 /* High-order 16 bits of constant for use in unsigned operand. */
8966 output_operand_lossage ("invalid %%u value");
8968 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
8969 (INT_LOWPART (x) >> 16) & 0xffff);
8973 /* High-order 16 bits of constant for use in signed operand. */
8975 output_operand_lossage ("invalid %%v value");
8977 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
8978 (INT_LOWPART (x) >> 16) & 0xffff);
8982 /* Print `u' if this has an auto-increment or auto-decrement. */
8983 if (GET_CODE (x) == MEM
8984 && (GET_CODE (XEXP (x, 0)) == PRE_INC
8985 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
8990 /* Print the trap code for this operand. */
8991 switch (GET_CODE (x))
8994 fputs ("eq", file); /* 4 */
8997 fputs ("ne", file); /* 24 */
9000 fputs ("lt", file); /* 16 */
9003 fputs ("le", file); /* 20 */
9006 fputs ("gt", file); /* 8 */
9009 fputs ("ge", file); /* 12 */
9012 fputs ("llt", file); /* 2 */
9015 fputs ("lle", file); /* 6 */
9018 fputs ("lgt", file); /* 1 */
9021 fputs ("lge", file); /* 5 */
9029 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
9032 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
9033 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9035 print_operand (file, x, 0);
9039 /* MB value for a PowerPC64 rldic operand. */
9040 val = (GET_CODE (x) == CONST_INT
9041 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9046 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9047 if ((val <<= 1) < 0)
9050 #if HOST_BITS_PER_WIDE_INT == 32
9051 if (GET_CODE (x) == CONST_INT && i >= 0)
9052 i += 32; /* zero-extend high-part was all 0's */
9053 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9055 val = CONST_DOUBLE_LOW (x);
9062 for ( ; i < 64; i++)
9063 if ((val <<= 1) < 0)
9068 fprintf (file, "%d", i + 1);
9072 if (GET_CODE (x) == MEM
9073 && legitimate_indexed_address_p (XEXP (x, 0), 0))
9078 /* Like 'L', for third word of TImode */
9079 if (GET_CODE (x) == REG)
9080 fprintf (file, "%s", reg_names[REGNO (x) + 2]);
9081 else if (GET_CODE (x) == MEM)
9083 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9084 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9085 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9087 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
9088 if (small_data_operand (x, GET_MODE (x)))
9089 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9090 reg_names[SMALL_DATA_REG]);
9095 /* X is a SYMBOL_REF. Write out the name preceded by a
9096 period and without any trailing data in brackets. Used for function
9097 names. If we are configured for System V (or the embedded ABI) on
9098 the PowerPC, do not emit the period, since those systems do not use
9099 TOCs and the like. */
9100 if (GET_CODE (x) != SYMBOL_REF)
9103 if (XSTR (x, 0)[0] != '.')
9105 switch (DEFAULT_ABI)
9120 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
9122 assemble_name (file, XSTR (x, 0));
9126 /* Like 'L', for last word of TImode. */
9127 if (GET_CODE (x) == REG)
9128 fprintf (file, "%s", reg_names[REGNO (x) + 3]);
9129 else if (GET_CODE (x) == MEM)
9131 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9132 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9133 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9135 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
9136 if (small_data_operand (x, GET_MODE (x)))
9137 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9138 reg_names[SMALL_DATA_REG]);
9142 /* Print AltiVec or SPE memory operand. */
9147 if (GET_CODE (x) != MEM)
9155 if (GET_CODE (tmp) == REG)
9157 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9160 /* Handle [reg+UIMM]. */
9161 else if (GET_CODE (tmp) == PLUS &&
9162 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9166 if (GET_CODE (XEXP (tmp, 0)) != REG)
9169 x = INTVAL (XEXP (tmp, 1));
9170 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9174 /* Fall through. Must be [reg+reg]. */
9176 if (GET_CODE (tmp) == REG)
9177 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
9178 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9180 if (REGNO (XEXP (tmp, 0)) == 0)
9181 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9182 reg_names[ REGNO (XEXP (tmp, 0)) ]);
9184 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9185 reg_names[ REGNO (XEXP (tmp, 1)) ]);
9193 if (GET_CODE (x) == REG)
9194 fprintf (file, "%s", reg_names[REGNO (x)]);
9195 else if (GET_CODE (x) == MEM)
9197 /* We need to handle PRE_INC and PRE_DEC here, since we need to
9198 know the width from the mode. */
9199 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
9200 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9201 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9202 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
9203 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9204 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9206 output_address (XEXP (x, 0));
9209 output_addr_const (file, x);
9213 assemble_name (file, rs6000_get_some_local_dynamic_name ());
9217 output_operand_lossage ("invalid %%xn code");
9221 /* Print the address of an operand. */
9224 print_operand_address (FILE *file, rtx x)
9226 if (GET_CODE (x) == REG)
9227 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9228 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9229 || GET_CODE (x) == LABEL_REF)
9231 output_addr_const (file, x);
9232 if (small_data_operand (x, GET_MODE (x)))
9233 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9234 reg_names[SMALL_DATA_REG]);
9235 else if (TARGET_TOC)
9238 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9240 if (REGNO (XEXP (x, 0)) == 0)
9241 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9242 reg_names[ REGNO (XEXP (x, 0)) ]);
9244 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9245 reg_names[ REGNO (XEXP (x, 1)) ]);
9247 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
9248 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9249 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
9251 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9252 && CONSTANT_P (XEXP (x, 1)))
9254 output_addr_const (file, XEXP (x, 1));
9255 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9259 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9260 && CONSTANT_P (XEXP (x, 1)))
9262 fprintf (file, "lo16(");
9263 output_addr_const (file, XEXP (x, 1));
9264 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9267 else if (legitimate_constant_pool_address_p (x))
9269 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9271 rtx contains_minus = XEXP (x, 1);
9275 /* Find the (minus (sym) (toc)) buried in X, and temporarily
9276 turn it into (sym) for output_addr_const. */
9277 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9278 contains_minus = XEXP (contains_minus, 0);
9280 minus = XEXP (contains_minus, 0);
9281 symref = XEXP (minus, 0);
9282 XEXP (contains_minus, 0) = symref;
9287 name = XSTR (symref, 0);
9288 newname = alloca (strlen (name) + sizeof ("@toc"));
9289 strcpy (newname, name);
9290 strcat (newname, "@toc");
9291 XSTR (symref, 0) = newname;
9293 output_addr_const (file, XEXP (x, 1));
9295 XSTR (symref, 0) = name;
9296 XEXP (contains_minus, 0) = minus;
9299 output_addr_const (file, XEXP (x, 1));
9301 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9307 /* Target hook for assembling integer objects. The PowerPC version has
9308 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9309 is defined. It also needs to handle DI-mode objects on 64-bit
9313 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
9315 #ifdef RELOCATABLE_NEEDS_FIXUP
9316 /* Special handling for SI values. */
9317 if (size == 4 && aligned_p)
9319 extern int in_toc_section (void);
9320 static int recurse = 0;
9322 /* For -mrelocatable, we mark all addresses that need to be fixed up
9323 in the .fixup section. */
9324 if (TARGET_RELOCATABLE
9325 && !in_toc_section ()
9326 && !in_text_section ()
9328 && GET_CODE (x) != CONST_INT
9329 && GET_CODE (x) != CONST_DOUBLE
9335 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9337 ASM_OUTPUT_LABEL (asm_out_file, buf);
9338 fprintf (asm_out_file, "\t.long\t(");
9339 output_addr_const (asm_out_file, x);
9340 fprintf (asm_out_file, ")@fixup\n");
9341 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9342 ASM_OUTPUT_ALIGN (asm_out_file, 2);
9343 fprintf (asm_out_file, "\t.long\t");
9344 assemble_name (asm_out_file, buf);
9345 fprintf (asm_out_file, "\n\t.previous\n");
9349 /* Remove initial .'s to turn a -mcall-aixdesc function
9350 address into the address of the descriptor, not the function
9352 else if (GET_CODE (x) == SYMBOL_REF
9353 && XSTR (x, 0)[0] == '.'
9354 && DEFAULT_ABI == ABI_AIX)
9356 const char *name = XSTR (x, 0);
9357 while (*name == '.')
9360 fprintf (asm_out_file, "\t.long\t%s\n", name);
9364 #endif /* RELOCATABLE_NEEDS_FIXUP */
9365 return default_assemble_integer (x, size, aligned_p);
9368 #ifdef HAVE_GAS_HIDDEN
9369 /* Emit an assembler directive to set symbol visibility for DECL to
9373 rs6000_assemble_visibility (tree decl, int vis)
9375 /* Functions need to have their entry point symbol visibility set as
9376 well as their descriptor symbol visibility. */
9377 if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL)
9379 static const char * const visibility_types[] = {
9380 NULL, "internal", "hidden", "protected"
9383 const char *name, *type;
9385 name = ((* targetm.strip_name_encoding)
9386 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
9387 type = visibility_types[vis];
9389 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9390 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
9393 default_assemble_visibility (decl, vis);
9398 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
9400 /* Reversal of FP compares takes care -- an ordered compare
9401 becomes an unordered compare and vice versa. */
9402 if (mode == CCFPmode
9403 && (!flag_finite_math_only
9404 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
9405 || code == UNEQ || code == LTGT))
9406 return reverse_condition_maybe_unordered (code);
9408 return reverse_condition (code);
9411 /* Generate a compare for CODE. Return a brand-new rtx that
9412 represents the result of the compare. */
9415 rs6000_generate_compare (enum rtx_code code)
9417 enum machine_mode comp_mode;
9420 if (rs6000_compare_fp_p)
9421 comp_mode = CCFPmode;
9422 else if (code == GTU || code == LTU
9423 || code == GEU || code == LEU)
9424 comp_mode = CCUNSmode;
9428 /* First, the compare. */
9429 compare_result = gen_reg_rtx (comp_mode);
9431 /* SPE FP compare instructions on the GPRs. Yuck! */
9432 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
9433 && rs6000_compare_fp_p)
9435 rtx cmp, or1, or2, or_result, compare_result2;
9443 cmp = flag_finite_math_only
9444 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
9446 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
9447 rs6000_compare_op1);
9455 cmp = flag_finite_math_only
9456 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
9458 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
9459 rs6000_compare_op1);
9467 cmp = flag_finite_math_only
9468 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
9470 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
9471 rs6000_compare_op1);
9477 /* Synthesize LE and GE from LT/GT || EQ. */
9478 if (code == LE || code == GE || code == LEU || code == GEU)
9480 /* Synthesize GE/LE frome GT/LT || EQ. */
9486 case LE: code = LT; break;
9487 case GE: code = GT; break;
9488 case LEU: code = LT; break;
9489 case GEU: code = GT; break;
9493 or1 = gen_reg_rtx (SImode);
9494 or2 = gen_reg_rtx (SImode);
9495 or_result = gen_reg_rtx (CCEQmode);
9496 compare_result2 = gen_reg_rtx (CCFPmode);
9499 cmp = flag_finite_math_only
9500 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
9502 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
9503 rs6000_compare_op1);
9506 /* The MC8540 FP compare instructions set the CR bits
9507 differently than other PPC compare instructions. For
9508 that matter, there is no generic test instruction, but a
9509 testgt, testlt, and testeq. For a true condition, bit 2
9510 is set (x1xx) in the CR. Following the traditional CR
9516 ... bit 2 would be a GT CR alias, so later on we
9517 look in the GT bits for the branch instructions.
9518 However, we must be careful to emit correct RTL in
9519 the meantime, so optimizations don't get confused. */
9521 or1 = gen_rtx (NE, SImode, compare_result, const0_rtx);
9522 or2 = gen_rtx (NE, SImode, compare_result2, const0_rtx);
9524 /* OR them together. */
9525 cmp = gen_rtx_SET (VOIDmode, or_result,
9526 gen_rtx_COMPARE (CCEQmode,
9527 gen_rtx_IOR (SImode, or1, or2),
9529 compare_result = or_result;
9534 /* We only care about 1 bit (x1xx), so map everything to NE to
9535 maintain rtl sanity. We'll get to the right bit (x1xx) at
9536 code output time. */
9537 if (code == NE || code == LTGT)
9538 /* Do the inverse here because we have no cmpne
9539 instruction. We use the cmpeq instruction and expect
9540 to get a 0 instead. */
9549 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
9550 gen_rtx_COMPARE (comp_mode,
9552 rs6000_compare_op1)));
9554 /* Some kinds of FP comparisons need an OR operation;
9555 under flag_finite_math_only we don't bother. */
9556 if (rs6000_compare_fp_p
9557 && ! flag_finite_math_only
9558 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
9559 && (code == LE || code == GE
9560 || code == UNEQ || code == LTGT
9561 || code == UNGT || code == UNLT))
9563 enum rtx_code or1, or2;
9564 rtx or1_rtx, or2_rtx, compare2_rtx;
9565 rtx or_result = gen_reg_rtx (CCEQmode);
9569 case LE: or1 = LT; or2 = EQ; break;
9570 case GE: or1 = GT; or2 = EQ; break;
9571 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
9572 case LTGT: or1 = LT; or2 = GT; break;
9573 case UNGT: or1 = UNORDERED; or2 = GT; break;
9574 case UNLT: or1 = UNORDERED; or2 = LT; break;
9577 validate_condition_mode (or1, comp_mode);
9578 validate_condition_mode (or2, comp_mode);
9579 or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx);
9580 or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx);
9581 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
9582 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
9584 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
9586 compare_result = or_result;
9590 validate_condition_mode (code, GET_MODE (compare_result));
9592 return gen_rtx (code, VOIDmode, compare_result, const0_rtx);
9596 /* Emit the RTL for an sCOND pattern. */
9599 rs6000_emit_sCOND (enum rtx_code code, rtx result)
9602 enum machine_mode op_mode;
9603 enum rtx_code cond_code;
9605 condition_rtx = rs6000_generate_compare (code);
9606 cond_code = GET_CODE (condition_rtx);
9609 || cond_code == GE || cond_code == LE
9610 || cond_code == GEU || cond_code == LEU
9611 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
9613 rtx not_result = gen_reg_rtx (CCEQmode);
9614 rtx not_op, rev_cond_rtx;
9615 enum machine_mode cc_mode;
9617 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
9619 rev_cond_rtx = gen_rtx (rs6000_reverse_condition (cc_mode, cond_code),
9620 SImode, XEXP (condition_rtx, 0), const0_rtx);
9621 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
9622 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
9623 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
9626 op_mode = GET_MODE (rs6000_compare_op0);
9627 if (op_mode == VOIDmode)
9628 op_mode = GET_MODE (rs6000_compare_op1);
9630 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
9632 PUT_MODE (condition_rtx, DImode);
9633 convert_move (result, condition_rtx, 0);
9637 PUT_MODE (condition_rtx, SImode);
9638 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
9642 /* Emit a branch of kind CODE to location LOC. */
9645 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
9647 rtx condition_rtx, loc_ref;
9649 condition_rtx = rs6000_generate_compare (code);
9650 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
9651 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
9652 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
9656 /* Return the string to output a conditional branch to LABEL, which is
9657 the operand number of the label, or -1 if the branch is really a
9660 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
9661 condition code register and its mode specifies what kind of
9664 REVERSED is nonzero if we should reverse the sense of the comparison.
9666 INSN is the insn. */
9669 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
9671 static char string[64];
9672 enum rtx_code code = GET_CODE (op);
9673 rtx cc_reg = XEXP (op, 0);
9674 enum machine_mode mode = GET_MODE (cc_reg);
9675 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
9676 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
9677 int really_reversed = reversed ^ need_longbranch;
9683 validate_condition_mode (code, mode);
9685 /* Work out which way this really branches. We could use
9686 reverse_condition_maybe_unordered here always but this
9687 makes the resulting assembler clearer. */
9688 if (really_reversed)
9690 /* Reversal of FP compares takes care -- an ordered compare
9691 becomes an unordered compare and vice versa. */
9692 if (mode == CCFPmode)
9693 code = reverse_condition_maybe_unordered (code);
9695 code = reverse_condition (code);
9698 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
9700 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
9703 /* Opposite of GT. */
9705 else if (code == NE)
9713 /* Not all of these are actually distinct opcodes, but
9714 we distinguish them for clarity of the resulting assembler. */
9716 ccode = "ne"; break;
9718 ccode = "eq"; break;
9720 ccode = "ge"; break;
9721 case GT: case GTU: case UNGT:
9722 ccode = "gt"; break;
9724 ccode = "le"; break;
9725 case LT: case LTU: case UNLT:
9726 ccode = "lt"; break;
9727 case UNORDERED: ccode = "un"; break;
9728 case ORDERED: ccode = "nu"; break;
9729 case UNGE: ccode = "nl"; break;
9730 case UNLE: ccode = "ng"; break;
9735 /* Maybe we have a guess as to how likely the branch is.
9736 The old mnemonics don't have a way to specify this information. */
9738 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
9739 if (note != NULL_RTX)
9741 /* PROB is the difference from 50%. */
9742 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
9743 bool always_hint = rs6000_cpu != PROCESSOR_POWER4;
9745 /* Only hint for highly probable/improbable branches on newer
9746 cpus as static prediction overrides processor dynamic
9747 prediction. For older cpus we may as well always hint, but
9748 assume not taken for branches that are very close to 50% as a
9749 mispredicted taken branch is more expensive than a
9750 mispredicted not-taken branch. */
9752 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
9754 if (abs (prob) > REG_BR_PROB_BASE / 20
9755 && ((prob > 0) ^ need_longbranch))
9763 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
9765 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
9767 /* We need to escape any '%' characters in the reg_names string.
9768 Assume they'd only be the first character.... */
9769 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
9771 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
9775 /* If the branch distance was too far, we may have to use an
9776 unconditional branch to go the distance. */
9777 if (need_longbranch)
9778 s += sprintf (s, ",$+8\n\tb %s", label);
9780 s += sprintf (s, ",%s", label);
9786 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
9787 operands of the last comparison is nonzero/true, FALSE_COND if it
9788 is zero/false. Return 0 if the hardware has no such operation. */
9791 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
9793 enum rtx_code code = GET_CODE (op);
9794 rtx op0 = rs6000_compare_op0;
9795 rtx op1 = rs6000_compare_op1;
9797 enum machine_mode compare_mode = GET_MODE (op0);
9798 enum machine_mode result_mode = GET_MODE (dest);
9801 /* These modes should always match. */
9802 if (GET_MODE (op1) != compare_mode
9803 /* In the isel case however, we can use a compare immediate, so
9804 op1 may be a small constant. */
9805 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
9807 if (GET_MODE (true_cond) != result_mode)
9809 if (GET_MODE (false_cond) != result_mode)
9812 /* First, work out if the hardware can do this at all, or
9813 if it's too slow.... */
9814 if (! rs6000_compare_fp_p)
9817 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
9821 /* Eliminate half of the comparisons by switching operands, this
9822 makes the remaining code simpler. */
9823 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
9824 || code == LTGT || code == LT || code == UNLE)
9826 code = reverse_condition_maybe_unordered (code);
9828 true_cond = false_cond;
9832 /* UNEQ and LTGT take four instructions for a comparison with zero,
9833 it'll probably be faster to use a branch here too. */
9834 if (code == UNEQ && HONOR_NANS (compare_mode))
9837 if (GET_CODE (op1) == CONST_DOUBLE)
9838 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
9840 /* We're going to try to implement comparisons by performing
9841 a subtract, then comparing against zero. Unfortunately,
9842 Inf - Inf is NaN which is not zero, and so if we don't
9843 know that the operand is finite and the comparison
9844 would treat EQ different to UNORDERED, we can't do it. */
9845 if (HONOR_INFINITIES (compare_mode)
9846 && code != GT && code != UNGE
9847 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
9848 /* Constructs of the form (a OP b ? a : b) are safe. */
9849 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
9850 || (! rtx_equal_p (op0, true_cond)
9851 && ! rtx_equal_p (op1, true_cond))))
9853 /* At this point we know we can use fsel. */
9855 /* Reduce the comparison to a comparison against zero. */
9856 temp = gen_reg_rtx (compare_mode);
9857 emit_insn (gen_rtx_SET (VOIDmode, temp,
9858 gen_rtx_MINUS (compare_mode, op0, op1)));
9860 op1 = CONST0_RTX (compare_mode);
9862 /* If we don't care about NaNs we can reduce some of the comparisons
9863 down to faster ones. */
9864 if (! HONOR_NANS (compare_mode))
9870 true_cond = false_cond;
9883 /* Now, reduce everything down to a GE. */
9890 temp = gen_reg_rtx (compare_mode);
9891 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
9896 temp = gen_reg_rtx (compare_mode);
9897 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
9902 temp = gen_reg_rtx (compare_mode);
9903 emit_insn (gen_rtx_SET (VOIDmode, temp,
9904 gen_rtx_NEG (compare_mode,
9905 gen_rtx_ABS (compare_mode, op0))));
9910 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
9911 temp = gen_reg_rtx (result_mode);
9912 emit_insn (gen_rtx_SET (VOIDmode, temp,
9913 gen_rtx_IF_THEN_ELSE (result_mode,
9914 gen_rtx_GE (VOIDmode,
9916 true_cond, false_cond)));
9917 false_cond = true_cond;
9920 temp = gen_reg_rtx (compare_mode);
9921 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
9926 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
9927 temp = gen_reg_rtx (result_mode);
9928 emit_insn (gen_rtx_SET (VOIDmode, temp,
9929 gen_rtx_IF_THEN_ELSE (result_mode,
9930 gen_rtx_GE (VOIDmode,
9932 true_cond, false_cond)));
9933 true_cond = false_cond;
9936 temp = gen_reg_rtx (compare_mode);
9937 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
9945 emit_insn (gen_rtx_SET (VOIDmode, dest,
9946 gen_rtx_IF_THEN_ELSE (result_mode,
9947 gen_rtx_GE (VOIDmode,
9949 true_cond, false_cond)));
9953 /* Same as above, but for ints (isel). */
9956 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
9958 rtx condition_rtx, cr;
9960 /* All isel implementations thus far are 32-bits. */
9961 if (GET_MODE (rs6000_compare_op0) != SImode)
9964 /* We still have to do the compare, because isel doesn't do a
9965 compare, it just looks at the CRx bits set by a previous compare
9967 condition_rtx = rs6000_generate_compare (GET_CODE (op));
9968 cr = XEXP (condition_rtx, 0);
9970 if (GET_MODE (cr) == CCmode)
9971 emit_insn (gen_isel_signed (dest, condition_rtx,
9972 true_cond, false_cond, cr));
9974 emit_insn (gen_isel_unsigned (dest, condition_rtx,
9975 true_cond, false_cond, cr));
9981 output_isel (rtx *operands)
9985 code = GET_CODE (operands[1]);
9986 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
9988 PUT_CODE (operands[1], reverse_condition (code));
9989 return "isel %0,%3,%2,%j1";
9992 return "isel %0,%2,%3,%j1";
9996 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
9998 enum machine_mode mode = GET_MODE (op0);
10002 if (code == SMAX || code == SMIN)
10007 if (code == SMAX || code == UMAX)
10008 target = emit_conditional_move (dest, c, op0, op1, mode,
10009 op0, op1, mode, 0);
10011 target = emit_conditional_move (dest, c, op0, op1, mode,
10012 op1, op0, mode, 0);
10013 if (target == NULL_RTX)
10015 if (target != dest)
10016 emit_move_insn (dest, target);
10019 /* Emit instructions to move SRC to DST. Called by splitters for
10020 multi-register moves. It will emit at most one instruction for
10021 each register that is accessed; that is, it won't emit li/lis pairs
10022 (or equivalent for 64-bit code). One of SRC or DST must be a hard
10026 rs6000_split_multireg_move (rtx dst, rtx src)
10028 /* The register number of the first register being moved. */
10030 /* The mode that is to be moved. */
10031 enum machine_mode mode;
10032 /* The mode that the move is being done in, and its size. */
10033 enum machine_mode reg_mode;
10035 /* The number of registers that will be moved. */
10038 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10039 mode = GET_MODE (dst);
10040 nregs = HARD_REGNO_NREGS (reg, mode);
10041 if (FP_REGNO_P (reg))
10043 else if (ALTIVEC_REGNO_P (reg))
10044 reg_mode = V16QImode;
10046 reg_mode = word_mode;
10047 reg_mode_size = GET_MODE_SIZE (reg_mode);
10049 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
10052 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
10054 /* Move register range backwards, if we might have destructive
10057 for (i = nregs - 1; i >= 0; i--)
10058 emit_insn (gen_rtx_SET (VOIDmode,
10059 simplify_gen_subreg (reg_mode, dst, mode,
10060 i * reg_mode_size),
10061 simplify_gen_subreg (reg_mode, src, mode,
10062 i * reg_mode_size)));
10068 bool used_update = false;
10070 if (GET_CODE (src) == MEM && INT_REGNO_P (reg))
10074 if (GET_CODE (XEXP (src, 0)) == PRE_INC
10075 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
10078 breg = XEXP (XEXP (src, 0), 0);
10079 delta_rtx = GET_CODE (XEXP (src, 0)) == PRE_INC
10080 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
10081 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)));
10082 emit_insn (TARGET_32BIT
10083 ? gen_addsi3 (breg, breg, delta_rtx)
10084 : gen_adddi3 (breg, breg, delta_rtx));
10085 src = gen_rtx_MEM (mode, breg);
10088 /* We have now address involving an base register only.
10089 If we use one of the registers to address memory,
10090 we have change that register last. */
10092 breg = (GET_CODE (XEXP (src, 0)) == PLUS
10093 ? XEXP (XEXP (src, 0), 0)
10099 if (REGNO (breg) >= REGNO (dst)
10100 && REGNO (breg) < REGNO (dst) + nregs)
10101 j = REGNO (breg) - REGNO (dst);
10104 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
10108 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
10109 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
10112 breg = XEXP (XEXP (dst, 0), 0);
10113 delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC
10114 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
10115 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)));
10117 /* We have to update the breg before doing the store.
10118 Use store with update, if available. */
10122 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
10123 emit_insn (TARGET_32BIT
10124 ? gen_movsi_update (breg, breg, delta_rtx, nsrc)
10125 : gen_movdi_update (breg, breg, delta_rtx, nsrc));
10126 used_update = true;
10129 emit_insn (TARGET_32BIT
10130 ? gen_addsi3 (breg, breg, delta_rtx)
10131 : gen_adddi3 (breg, breg, delta_rtx));
10132 dst = gen_rtx_MEM (mode, breg);
10136 for (i = 0; i < nregs; i++)
10138 /* Calculate index to next subword. */
10143 /* If compiler already emited move of first word by
10144 store with update, no need to do anything. */
10145 if (j == 0 && used_update)
10148 emit_insn (gen_rtx_SET (VOIDmode,
10149 simplify_gen_subreg (reg_mode, dst, mode,
10150 j * reg_mode_size),
10151 simplify_gen_subreg (reg_mode, src, mode,
10152 j * reg_mode_size)));
10158 /* This page contains routines that are used to determine what the
10159 function prologue and epilogue code will do and write them out. */
10161 /* Return the first fixed-point register that is required to be
10162 saved. 32 if none. */
10165 first_reg_to_save (void)
10169 /* Find lowest numbered live register. */
10170 for (first_reg = 13; first_reg <= 31; first_reg++)
10171 if (regs_ever_live[first_reg]
10172 && (! call_used_regs[first_reg]
10173 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
10174 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
10175 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))))
10180 && current_function_uses_pic_offset_table
10181 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
10182 return RS6000_PIC_OFFSET_TABLE_REGNUM;
10188 /* Similar, for FP regs. */
10191 first_fp_reg_to_save (void)
10195 /* Find lowest numbered live register. */
10196 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
10197 if (regs_ever_live[first_reg])
10203 /* Similar, for AltiVec regs. */
10206 first_altivec_reg_to_save (void)
10210 /* Stack frame remains as is unless we are in AltiVec ABI. */
10211 if (! TARGET_ALTIVEC_ABI)
10212 return LAST_ALTIVEC_REGNO + 1;
10214 /* Find lowest numbered live register. */
10215 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
10216 if (regs_ever_live[i])
10222 /* Return a 32-bit mask of the AltiVec registers we need to set in
10223 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
10224 the 32-bit word is 0. */
10226 static unsigned int
10227 compute_vrsave_mask (void)
10229 unsigned int i, mask = 0;
10231 /* First, find out if we use _any_ altivec registers. */
10232 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10233 if (regs_ever_live[i])
10234 mask |= ALTIVEC_REG_BIT (i);
10239 /* Next, remove the argument registers from the set. These must
10240 be in the VRSAVE mask set by the caller, so we don't need to add
10241 them in again. More importantly, the mask we compute here is
10242 used to generate CLOBBERs in the set_vrsave insn, and we do not
10243 wish the argument registers to die. */
10244 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
10245 mask &= ~ALTIVEC_REG_BIT (i);
10247 /* Similarly, remove the return value from the set. */
10250 diddle_return_value (is_altivec_return_reg, &yes);
10252 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
10259 is_altivec_return_reg (rtx reg, void *xyes)
10261 bool *yes = (bool *) xyes;
10262 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
10267 /* Calculate the stack information for the current function. This is
10268 complicated by having two separate calling sequences, the AIX calling
10269 sequence and the V.4 calling sequence.
10271 AIX (and Darwin/Mac OS X) stack frames look like:
10273 SP----> +---------------------------------------+
10274 | back chain to caller | 0 0
10275 +---------------------------------------+
10276 | saved CR | 4 8 (8-11)
10277 +---------------------------------------+
10279 +---------------------------------------+
10280 | reserved for compilers | 12 24
10281 +---------------------------------------+
10282 | reserved for binders | 16 32
10283 +---------------------------------------+
10284 | saved TOC pointer | 20 40
10285 +---------------------------------------+
10286 | Parameter save area (P) | 24 48
10287 +---------------------------------------+
10288 | Alloca space (A) | 24+P etc.
10289 +---------------------------------------+
10290 | Local variable space (L) | 24+P+A
10291 +---------------------------------------+
10292 | Float/int conversion temporary (X) | 24+P+A+L
10293 +---------------------------------------+
10294 | Save area for AltiVec registers (W) | 24+P+A+L+X
10295 +---------------------------------------+
10296 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
10297 +---------------------------------------+
10298 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
10299 +---------------------------------------+
10300 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
10301 +---------------------------------------+
10302 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
10303 +---------------------------------------+
10304 old SP->| back chain to caller's caller |
10305 +---------------------------------------+
10307 The required alignment for AIX configurations is two words (i.e., 8
10311 V.4 stack frames look like:
10313 SP----> +---------------------------------------+
10314 | back chain to caller | 0
10315 +---------------------------------------+
10316 | caller's saved LR | 4
10317 +---------------------------------------+
10318 | Parameter save area (P) | 8
10319 +---------------------------------------+
10320 | Alloca space (A) | 8+P
10321 +---------------------------------------+
10322 | Varargs save area (V) | 8+P+A
10323 +---------------------------------------+
10324 | Local variable space (L) | 8+P+A+V
10325 +---------------------------------------+
10326 | Float/int conversion temporary (X) | 8+P+A+V+L
10327 +---------------------------------------+
10328 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
10329 +---------------------------------------+
10330 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
10331 +---------------------------------------+
10332 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
10333 +---------------------------------------+
10334 | SPE: area for 64-bit GP registers |
10335 +---------------------------------------+
10336 | SPE alignment padding |
10337 +---------------------------------------+
10338 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
10339 +---------------------------------------+
10340 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
10341 +---------------------------------------+
10342 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
10343 +---------------------------------------+
10344 old SP->| back chain to caller's caller |
10345 +---------------------------------------+
10347 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
10348 given. (But note below and in sysv4.h that we require only 8 and
10349 may round up the size of our stack frame anyways. The historical
10350 reason is early versions of powerpc-linux which didn't properly
10351 align the stack at program startup. A happy side-effect is that
10352 -mno-eabi libraries can be used with -meabi programs.)
10354 The EABI configuration defaults to the V.4 layout. However,
10355 the stack alignment requirements may differ. If -mno-eabi is not
10356 given, the required stack alignment is 8 bytes; if -mno-eabi is
10357 given, the required alignment is 16 bytes. (But see V.4 comment
10360 #ifndef ABI_STACK_BOUNDARY
10361 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
10364 static rs6000_stack_t *
10365 rs6000_stack_info (void)
10367 static rs6000_stack_t info, zero_info;
10368 rs6000_stack_t *info_ptr = &info;
10369 int reg_size = TARGET_POWERPC64 ? 8 : 4;
10371 HOST_WIDE_INT total_raw_size;
10373 /* Zero all fields portably. */
10378 /* Cache value so we don't rescan instruction chain over and over. */
10379 if (cfun->machine->insn_chain_scanned_p == 0)
10381 cfun->machine->insn_chain_scanned_p = 1;
10382 info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
10386 /* Select which calling sequence. */
10387 info_ptr->abi = DEFAULT_ABI;
10389 /* Calculate which registers need to be saved & save area size. */
10390 info_ptr->first_gp_reg_save = first_reg_to_save ();
10391 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
10392 even if it currently looks like we won't. */
10393 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
10394 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
10395 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
10396 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
10397 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
10399 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
10401 /* For the SPE, we have an additional upper 32-bits on each GPR.
10402 Ideally we should save the entire 64-bits only when the upper
10403 half is used in SIMD instructions. Since we only record
10404 registers live (not the size they are used in), this proves
10405 difficult because we'd have to traverse the instruction chain at
10406 the right time, taking reload into account. This is a real pain,
10407 so we opt to save the GPRs in 64-bits always if but one register
10408 gets used in 64-bits. Otherwise, all the registers in the frame
10409 get saved in 32-bits.
10411 So... since when we save all GPRs (except the SP) in 64-bits, the
10412 traditional GP save area will be empty. */
10413 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10414 info_ptr->gp_size = 0;
10416 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
10417 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
10419 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
10420 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
10421 - info_ptr->first_altivec_reg_save);
10423 /* Does this function call anything? */
10424 info_ptr->calls_p = (! current_function_is_leaf
10425 || cfun->machine->ra_needs_full_frame);
10427 /* Determine if we need to save the link register. */
10428 if (rs6000_ra_ever_killed ()
10429 || (DEFAULT_ABI == ABI_AIX
10430 && current_function_profile
10431 && !TARGET_PROFILE_KERNEL)
10432 #ifdef TARGET_RELOCATABLE
10433 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
10435 || (info_ptr->first_fp_reg_save != 64
10436 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
10437 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
10438 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
10439 || (DEFAULT_ABI == ABI_DARWIN
10441 && current_function_uses_pic_offset_table)
10442 || info_ptr->calls_p)
10444 info_ptr->lr_save_p = 1;
10445 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
10448 /* Determine if we need to save the condition code registers. */
10449 if (regs_ever_live[CR2_REGNO]
10450 || regs_ever_live[CR3_REGNO]
10451 || regs_ever_live[CR4_REGNO])
10453 info_ptr->cr_save_p = 1;
10454 if (DEFAULT_ABI == ABI_V4)
10455 info_ptr->cr_size = reg_size;
10458 /* If the current function calls __builtin_eh_return, then we need
10459 to allocate stack space for registers that will hold data for
10460 the exception handler. */
10461 if (current_function_calls_eh_return)
10464 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
10467 /* SPE saves EH registers in 64-bits. */
10468 ehrd_size = i * (TARGET_SPE_ABI
10469 && info_ptr->spe_64bit_regs_used != 0
10470 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
10475 /* Determine various sizes. */
10476 info_ptr->reg_size = reg_size;
10477 info_ptr->fixed_size = RS6000_SAVE_AREA;
10478 info_ptr->varargs_size = RS6000_VARARGS_AREA;
10479 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
10480 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
10483 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10484 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
10486 info_ptr->spe_gp_size = 0;
10488 if (TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE)
10490 info_ptr->vrsave_mask = compute_vrsave_mask ();
10491 info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0;
10495 info_ptr->vrsave_mask = 0;
10496 info_ptr->vrsave_size = 0;
10499 /* Calculate the offsets. */
10500 switch (DEFAULT_ABI)
10508 info_ptr->fp_save_offset = - info_ptr->fp_size;
10509 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
10511 if (TARGET_ALTIVEC_ABI)
10513 info_ptr->vrsave_save_offset
10514 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
10516 /* Align stack so vector save area is on a quadword boundary. */
10517 if (info_ptr->altivec_size != 0)
10518 info_ptr->altivec_padding_size
10519 = 16 - (-info_ptr->vrsave_save_offset % 16);
10521 info_ptr->altivec_padding_size = 0;
10523 info_ptr->altivec_save_offset
10524 = info_ptr->vrsave_save_offset
10525 - info_ptr->altivec_padding_size
10526 - info_ptr->altivec_size;
10528 /* Adjust for AltiVec case. */
10529 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
10532 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
10533 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
10534 info_ptr->lr_save_offset = 2*reg_size;
10538 info_ptr->fp_save_offset = - info_ptr->fp_size;
10539 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
10540 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
10542 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10544 /* Align stack so SPE GPR save area is aligned on a
10545 double-word boundary. */
10546 if (info_ptr->spe_gp_size != 0)
10547 info_ptr->spe_padding_size
10548 = 8 - (-info_ptr->cr_save_offset % 8);
10550 info_ptr->spe_padding_size = 0;
10552 info_ptr->spe_gp_save_offset
10553 = info_ptr->cr_save_offset
10554 - info_ptr->spe_padding_size
10555 - info_ptr->spe_gp_size;
10557 /* Adjust for SPE case. */
10558 info_ptr->toc_save_offset
10559 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
10561 else if (TARGET_ALTIVEC_ABI)
10563 info_ptr->vrsave_save_offset
10564 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
10566 /* Align stack so vector save area is on a quadword boundary. */
10567 if (info_ptr->altivec_size != 0)
10568 info_ptr->altivec_padding_size
10569 = 16 - (-info_ptr->vrsave_save_offset % 16);
10571 info_ptr->altivec_padding_size = 0;
10573 info_ptr->altivec_save_offset
10574 = info_ptr->vrsave_save_offset
10575 - info_ptr->altivec_padding_size
10576 - info_ptr->altivec_size;
10578 /* Adjust for AltiVec case. */
10579 info_ptr->toc_save_offset
10580 = info_ptr->altivec_save_offset - info_ptr->toc_size;
10583 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
10584 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
10585 info_ptr->lr_save_offset = reg_size;
10589 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
10590 + info_ptr->gp_size
10591 + info_ptr->altivec_size
10592 + info_ptr->altivec_padding_size
10593 + info_ptr->spe_gp_size
10594 + info_ptr->spe_padding_size
10596 + info_ptr->cr_size
10597 + info_ptr->lr_size
10598 + info_ptr->vrsave_size
10599 + info_ptr->toc_size,
10600 (TARGET_ALTIVEC_ABI || ABI_DARWIN)
10603 total_raw_size = (info_ptr->vars_size
10604 + info_ptr->parm_size
10605 + info_ptr->save_size
10606 + info_ptr->varargs_size
10607 + info_ptr->fixed_size);
10609 info_ptr->total_size =
10610 RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT);
10612 /* Determine if we need to allocate any stack frame:
10614 For AIX we need to push the stack if a frame pointer is needed
10615 (because the stack might be dynamically adjusted), if we are
10616 debugging, if we make calls, or if the sum of fp_save, gp_save,
10617 and local variables are more than the space needed to save all
10618 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
10619 + 18*8 = 288 (GPR13 reserved).
10621 For V.4 we don't have the stack cushion that AIX uses, but assume
10622 that the debugger can handle stackless frames. */
10624 if (info_ptr->calls_p)
10625 info_ptr->push_p = 1;
10627 else if (DEFAULT_ABI == ABI_V4)
10628 info_ptr->push_p = total_raw_size > info_ptr->fixed_size;
10630 else if (frame_pointer_needed)
10631 info_ptr->push_p = 1;
10633 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
10634 info_ptr->push_p = 1;
10638 = total_raw_size - info_ptr->fixed_size > (TARGET_32BIT ? 220 : 288);
10640 /* Zero offsets if we're not saving those registers. */
10641 if (info_ptr->fp_size == 0)
10642 info_ptr->fp_save_offset = 0;
10644 if (info_ptr->gp_size == 0)
10645 info_ptr->gp_save_offset = 0;
10647 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
10648 info_ptr->altivec_save_offset = 0;
10650 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
10651 info_ptr->vrsave_save_offset = 0;
10653 if (! TARGET_SPE_ABI
10654 || info_ptr->spe_64bit_regs_used == 0
10655 || info_ptr->spe_gp_size == 0)
10656 info_ptr->spe_gp_save_offset = 0;
10658 if (! info_ptr->lr_save_p)
10659 info_ptr->lr_save_offset = 0;
10661 if (! info_ptr->cr_save_p)
10662 info_ptr->cr_save_offset = 0;
10664 if (! info_ptr->toc_save_p)
10665 info_ptr->toc_save_offset = 0;
10670 /* Return true if the current function uses any GPRs in 64-bit SIMD
10674 spe_func_has_64bit_regs_p (void)
10678 /* Functions that save and restore all the call-saved registers will
10679 need to save/restore the registers in 64-bits. */
10680 if (current_function_calls_eh_return
10681 || current_function_calls_setjmp
10682 || current_function_has_nonlocal_goto)
10685 insns = get_insns ();
10687 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
10693 i = PATTERN (insn);
10694 if (GET_CODE (i) == SET
10695 && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i))))
10704 debug_stack_info (rs6000_stack_t *info)
10706 const char *abi_string;
10709 info = rs6000_stack_info ();
10711 fprintf (stderr, "\nStack information for function %s:\n",
10712 ((current_function_decl && DECL_NAME (current_function_decl))
10713 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
10718 default: abi_string = "Unknown"; break;
10719 case ABI_NONE: abi_string = "NONE"; break;
10720 case ABI_AIX: abi_string = "AIX"; break;
10721 case ABI_DARWIN: abi_string = "Darwin"; break;
10722 case ABI_V4: abi_string = "V.4"; break;
10725 fprintf (stderr, "\tABI = %5s\n", abi_string);
10727 if (TARGET_ALTIVEC_ABI)
10728 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
10730 if (TARGET_SPE_ABI)
10731 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
10733 if (info->first_gp_reg_save != 32)
10734 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
10736 if (info->first_fp_reg_save != 64)
10737 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
10739 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
10740 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
10741 info->first_altivec_reg_save);
10743 if (info->lr_save_p)
10744 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
10746 if (info->cr_save_p)
10747 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
10749 if (info->toc_save_p)
10750 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
10752 if (info->vrsave_mask)
10753 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
10756 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
10759 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
10761 if (info->gp_save_offset)
10762 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
10764 if (info->fp_save_offset)
10765 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
10767 if (info->altivec_save_offset)
10768 fprintf (stderr, "\taltivec_save_offset = %5d\n",
10769 info->altivec_save_offset);
10771 if (info->spe_gp_save_offset)
10772 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
10773 info->spe_gp_save_offset);
10775 if (info->vrsave_save_offset)
10776 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
10777 info->vrsave_save_offset);
10779 if (info->lr_save_offset)
10780 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
10782 if (info->cr_save_offset)
10783 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
10785 if (info->toc_save_offset)
10786 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
10788 if (info->varargs_save_offset)
10789 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
10791 if (info->total_size)
10792 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
10795 if (info->varargs_size)
10796 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
10798 if (info->vars_size)
10799 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
10802 if (info->parm_size)
10803 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
10805 if (info->fixed_size)
10806 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
10809 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
10811 if (info->spe_gp_size)
10812 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
10815 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
10817 if (info->altivec_size)
10818 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
10820 if (info->vrsave_size)
10821 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
10823 if (info->altivec_padding_size)
10824 fprintf (stderr, "\taltivec_padding_size= %5d\n",
10825 info->altivec_padding_size);
10827 if (info->spe_padding_size)
10828 fprintf (stderr, "\tspe_padding_size = %5d\n",
10829 info->spe_padding_size);
10832 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
10835 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
10837 if (info->toc_size)
10838 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
10840 if (info->save_size)
10841 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
10843 if (info->reg_size != 4)
10844 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
10846 fprintf (stderr, "\n");
10850 rs6000_return_addr (int count, rtx frame)
10852 /* Currently we don't optimize very well between prolog and body
10853 code and for PIC code the code can be actually quite bad, so
10854 don't try to be too clever here. */
10855 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
10857 cfun->machine->ra_needs_full_frame = 1;
10864 plus_constant (copy_to_reg
10865 (gen_rtx_MEM (Pmode,
10866 memory_address (Pmode, frame))),
10867 RETURN_ADDRESS_OFFSET)));
10870 cfun->machine->ra_need_lr = 1;
10871 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
10874 /* Say whether a function is a candidate for sibcall handling or not.
10875 We do not allow indirect calls to be optimized into sibling calls.
10876 Also, we can't do it if there are any vector parameters; there's
10877 nowhere to put the VRsave code so it works; note that functions with
10878 vector parameters are required to have a prototype, so the argument
10879 type info must be available here. (The tail recursion case can work
10880 with vector parameters, but there's no way to distinguish here.) */
10882 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10887 if (TARGET_ALTIVEC_VRSAVE)
10889 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
10890 type; type = TREE_CHAIN (type))
10892 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
10896 if (DEFAULT_ABI == ABI_DARWIN
10897 || (*targetm.binds_local_p) (decl))
10899 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
10901 if (!lookup_attribute ("longcall", attr_list)
10902 || lookup_attribute ("shortcall", attr_list))
10910 rs6000_ra_ever_killed (void)
10916 /* Irritatingly, there are two kinds of thunks -- those created with
10917 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
10918 through the regular part of the compiler. This is a very hacky
10919 way to tell them apart. */
10920 if (current_function_is_thunk && !no_new_pseudos)
10923 /* regs_ever_live has LR marked as used if any sibcalls are present,
10924 but this should not force saving and restoring in the
10925 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
10926 clobbers LR, so that is inappropriate. */
10928 /* Also, the prologue can generate a store into LR that
10929 doesn't really count, like this:
10932 bcl to set PIC register
10936 When we're called from the epilogue, we need to avoid counting
10937 this as a store. */
10939 push_topmost_sequence ();
10940 top = get_insns ();
10941 pop_topmost_sequence ();
10942 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
10944 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
10948 if (FIND_REG_INC_NOTE (insn, reg))
10950 else if (GET_CODE (insn) == CALL_INSN
10951 && !SIBLING_CALL_P (insn))
10953 else if (set_of (reg, insn) != NULL_RTX
10954 && !prologue_epilogue_contains (insn))
10961 /* Add a REG_MAYBE_DEAD note to the insn. */
10963 rs6000_maybe_dead (rtx insn)
10965 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
10970 /* Emit instructions needed to load the TOC register.
10971 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
10972 a constant pool; or for SVR4 -fpic. */
10975 rs6000_emit_load_toc_table (int fromprolog)
10978 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10980 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10982 rtx temp = (fromprolog
10983 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
10984 : gen_reg_rtx (Pmode));
10985 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
10987 rs6000_maybe_dead (insn);
10988 insn = emit_move_insn (dest, temp);
10990 rs6000_maybe_dead (insn);
10992 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
10995 rtx tempLR = (fromprolog
10996 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
10997 : gen_reg_rtx (Pmode));
10998 rtx temp0 = (fromprolog
10999 ? gen_rtx_REG (Pmode, 0)
11000 : gen_reg_rtx (Pmode));
11003 /* possibly create the toc section */
11004 if (! toc_initialized)
11007 function_section (current_function_decl);
11014 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
11015 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11017 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
11018 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11020 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
11022 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
11023 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
11030 static int reload_toc_labelno = 0;
11032 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
11034 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
11035 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11037 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
11038 emit_move_insn (dest, tempLR);
11039 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
11041 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
11043 rs6000_maybe_dead (insn);
11045 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
11047 /* This is for AIX code running in non-PIC ELF32. */
11050 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
11051 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11053 insn = emit_insn (gen_elf_high (dest, realsym));
11055 rs6000_maybe_dead (insn);
11056 insn = emit_insn (gen_elf_low (dest, dest, realsym));
11058 rs6000_maybe_dead (insn);
11060 else if (DEFAULT_ABI == ABI_AIX)
11063 insn = emit_insn (gen_load_toc_aix_si (dest));
11065 insn = emit_insn (gen_load_toc_aix_di (dest));
11067 rs6000_maybe_dead (insn);
11073 /* Emit instructions to restore the link register after determining where
11074 its value has been stored. */
11077 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
11079 rs6000_stack_t *info = rs6000_stack_info ();
11082 operands[0] = source;
11083 operands[1] = scratch;
11085 if (info->lr_save_p)
11087 rtx frame_rtx = stack_pointer_rtx;
11088 HOST_WIDE_INT sp_offset = 0;
11091 if (frame_pointer_needed
11092 || current_function_calls_alloca
11093 || info->total_size > 32767)
11095 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
11096 frame_rtx = operands[1];
11098 else if (info->push_p)
11099 sp_offset = info->total_size;
11101 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
11102 tmp = gen_rtx_MEM (Pmode, tmp);
11103 emit_move_insn (tmp, operands[0]);
11106 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
11110 get_TOC_alias_set (void)
11112 static int set = -1;
11114 set = new_alias_set ();
11118 /* This returns nonzero if the current function uses the TOC. This is
11119 determined by the presence of (unspec ... UNSPEC_TOC) or
11120 use (unspec ... UNSPEC_TOC), which are generated by the various
11121 load_toc_* patterns. */
11128 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11131 rtx pat = PATTERN (insn);
11134 if (GET_CODE (pat) == PARALLEL)
11135 for (i = 0; i < XVECLEN (pat, 0); i++)
11137 rtx sub = XVECEXP (pat, 0, i);
11138 if (GET_CODE (sub) == USE)
11140 sub = XEXP (sub, 0);
11141 if (GET_CODE (sub) == UNSPEC
11142 && XINT (sub, 1) == UNSPEC_TOC)
11151 create_TOC_reference (rtx symbol)
11153 return gen_rtx_PLUS (Pmode,
11154 gen_rtx_REG (Pmode, TOC_REGISTER),
11155 gen_rtx_CONST (Pmode,
11156 gen_rtx_MINUS (Pmode, symbol,
11157 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
11160 /* If _Unwind_* has been called from within the same module,
11161 toc register is not guaranteed to be saved to 40(1) on function
11162 entry. Save it there in that case. */
11165 rs6000_aix_emit_builtin_unwind_init (void)
11168 rtx stack_top = gen_reg_rtx (Pmode);
11169 rtx opcode_addr = gen_reg_rtx (Pmode);
11170 rtx opcode = gen_reg_rtx (SImode);
11171 rtx tocompare = gen_reg_rtx (SImode);
11172 rtx no_toc_save_needed = gen_label_rtx ();
11174 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
11175 emit_move_insn (stack_top, mem);
11177 mem = gen_rtx_MEM (Pmode,
11178 gen_rtx_PLUS (Pmode, stack_top,
11179 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
11180 emit_move_insn (opcode_addr, mem);
11181 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
11182 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
11183 : 0xE8410028, SImode));
11185 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
11186 SImode, NULL_RTX, NULL_RTX,
11187 no_toc_save_needed);
11189 mem = gen_rtx_MEM (Pmode,
11190 gen_rtx_PLUS (Pmode, stack_top,
11191 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
11192 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
11193 emit_label (no_toc_save_needed);
11196 /* This ties together stack memory (MEM with an alias set of
11197 rs6000_sr_alias_set) and the change to the stack pointer. */
11200 rs6000_emit_stack_tie (void)
11202 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
11204 set_mem_alias_set (mem, rs6000_sr_alias_set);
11205 emit_insn (gen_stack_tie (mem));
11208 /* Emit the correct code for allocating stack space, as insns.
11209 If COPY_R12, make sure a copy of the old frame is left in r12.
11210 The generated code may use hard register 0 as a temporary. */
11213 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
11216 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11217 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
11218 rtx todec = GEN_INT (-size);
11220 if (current_function_limit_stack)
11222 if (REG_P (stack_limit_rtx)
11223 && REGNO (stack_limit_rtx) > 1
11224 && REGNO (stack_limit_rtx) <= 31)
11226 emit_insn (TARGET_32BIT
11227 ? gen_addsi3 (tmp_reg,
11230 : gen_adddi3 (tmp_reg,
11234 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11237 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
11239 && DEFAULT_ABI == ABI_V4)
11241 rtx toload = gen_rtx_CONST (VOIDmode,
11242 gen_rtx_PLUS (Pmode,
11246 emit_insn (gen_elf_high (tmp_reg, toload));
11247 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
11248 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11252 warning ("stack limit expression is not supported");
11255 if (copy_r12 || ! TARGET_UPDATE)
11256 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
11262 /* Need a note here so that try_split doesn't get confused. */
11263 if (get_last_insn() == NULL_RTX)
11264 emit_note (NOTE_INSN_DELETED);
11265 insn = emit_move_insn (tmp_reg, todec);
11266 try_split (PATTERN (insn), insn, 0);
11270 insn = emit_insn (TARGET_32BIT
11271 ? gen_movsi_update (stack_reg, stack_reg,
11273 : gen_movdi_update (stack_reg, stack_reg,
11274 todec, stack_reg));
11278 insn = emit_insn (TARGET_32BIT
11279 ? gen_addsi3 (stack_reg, stack_reg, todec)
11280 : gen_adddi3 (stack_reg, stack_reg, todec));
11281 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
11282 gen_rtx_REG (Pmode, 12));
11285 RTX_FRAME_RELATED_P (insn) = 1;
11287 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11288 gen_rtx_SET (VOIDmode, stack_reg,
11289 gen_rtx_PLUS (Pmode, stack_reg,
11294 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
11295 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
11296 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
11297 deduce these equivalences by itself so it wasn't necessary to hold
11298 its hand so much. */
11301 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
11302 rtx reg2, rtx rreg)
11306 /* copy_rtx will not make unique copies of registers, so we need to
11307 ensure we don't have unwanted sharing here. */
11309 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11312 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11314 real = copy_rtx (PATTERN (insn));
11316 if (reg2 != NULL_RTX)
11317 real = replace_rtx (real, reg2, rreg);
11319 real = replace_rtx (real, reg,
11320 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
11321 STACK_POINTER_REGNUM),
11324 /* We expect that 'real' is either a SET or a PARALLEL containing
11325 SETs (and possibly other stuff). In a PARALLEL, all the SETs
11326 are important so they all have to be marked RTX_FRAME_RELATED_P. */
11328 if (GET_CODE (real) == SET)
11332 temp = simplify_rtx (SET_SRC (set));
11334 SET_SRC (set) = temp;
11335 temp = simplify_rtx (SET_DEST (set));
11337 SET_DEST (set) = temp;
11338 if (GET_CODE (SET_DEST (set)) == MEM)
11340 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11342 XEXP (SET_DEST (set), 0) = temp;
11345 else if (GET_CODE (real) == PARALLEL)
11348 for (i = 0; i < XVECLEN (real, 0); i++)
11349 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
11351 rtx set = XVECEXP (real, 0, i);
11353 temp = simplify_rtx (SET_SRC (set));
11355 SET_SRC (set) = temp;
11356 temp = simplify_rtx (SET_DEST (set));
11358 SET_DEST (set) = temp;
11359 if (GET_CODE (SET_DEST (set)) == MEM)
11361 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11363 XEXP (SET_DEST (set), 0) = temp;
11365 RTX_FRAME_RELATED_P (set) = 1;
11372 real = spe_synthesize_frame_save (real);
11374 RTX_FRAME_RELATED_P (insn) = 1;
11375 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11380 /* Given an SPE frame note, return a PARALLEL of SETs with the
11381 original note, plus a synthetic register save. */
11384 spe_synthesize_frame_save (rtx real)
11386 rtx synth, offset, reg, real2;
11388 if (GET_CODE (real) != SET
11389 || GET_MODE (SET_SRC (real)) != V2SImode)
11392 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
11393 frame related note. The parallel contains a set of the register
11394 being saved, and another set to a synthetic register (n+1200).
11395 This is so we can differentiate between 64-bit and 32-bit saves.
11396 Words cannot describe this nastiness. */
11398 if (GET_CODE (SET_DEST (real)) != MEM
11399 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
11400 || GET_CODE (SET_SRC (real)) != REG)
11404 (set (mem (plus (reg x) (const y)))
11407 (set (mem (plus (reg x) (const y+4)))
11411 real2 = copy_rtx (real);
11412 PUT_MODE (SET_DEST (real2), SImode);
11413 reg = SET_SRC (real2);
11414 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
11415 synth = copy_rtx (real2);
11417 if (BYTES_BIG_ENDIAN)
11419 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
11420 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
11423 reg = SET_SRC (synth);
11425 synth = replace_rtx (synth, reg,
11426 gen_rtx_REG (SImode, REGNO (reg) + 1200));
11428 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
11429 synth = replace_rtx (synth, offset,
11430 GEN_INT (INTVAL (offset)
11431 + (BYTES_BIG_ENDIAN ? 0 : 4)));
11433 RTX_FRAME_RELATED_P (synth) = 1;
11434 RTX_FRAME_RELATED_P (real2) = 1;
11435 if (BYTES_BIG_ENDIAN)
11436 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
11438 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
11443 /* Returns an insn that has a vrsave set operation with the
11444 appropriate CLOBBERs. */
11447 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
11450 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
11451 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
11454 = gen_rtx_SET (VOIDmode,
11456 gen_rtx_UNSPEC_VOLATILE (SImode,
11457 gen_rtvec (2, reg, vrsave),
11462 /* We need to clobber the registers in the mask so the scheduler
11463 does not move sets to VRSAVE before sets of AltiVec registers.
11465 However, if the function receives nonlocal gotos, reload will set
11466 all call saved registers live. We will end up with:
11468 (set (reg 999) (mem))
11469 (parallel [ (set (reg vrsave) (unspec blah))
11470 (clobber (reg 999))])
11472 The clobber will cause the store into reg 999 to be dead, and
11473 flow will attempt to delete an epilogue insn. In this case, we
11474 need an unspec use/set of the register. */
11476 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11477 if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0)
11479 if (!epiloguep || call_used_regs [i])
11480 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
11481 gen_rtx_REG (V4SImode, i));
11484 rtx reg = gen_rtx_REG (V4SImode, i);
11487 = gen_rtx_SET (VOIDmode,
11489 gen_rtx_UNSPEC (V4SImode,
11490 gen_rtvec (1, reg), 27));
11494 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
11496 for (i = 0; i < nclobs; ++i)
11497 XVECEXP (insn, 0, i) = clobs[i];
11502 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
11503 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
11506 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
11507 unsigned int regno, int offset, HOST_WIDE_INT total_size)
11509 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
11510 rtx replacea, replaceb;
11512 int_rtx = GEN_INT (offset);
11514 /* Some cases that need register indexed addressing. */
11515 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
11517 && SPE_VECTOR_MODE (mode)
11518 && !SPE_CONST_OFFSET_OK (offset)))
11520 /* Whomever calls us must make sure r11 is available in the
11521 flow path of instructions in the prologue. */
11522 offset_rtx = gen_rtx_REG (Pmode, 11);
11523 emit_move_insn (offset_rtx, int_rtx);
11525 replacea = offset_rtx;
11526 replaceb = int_rtx;
11530 offset_rtx = int_rtx;
11531 replacea = NULL_RTX;
11532 replaceb = NULL_RTX;
11535 reg = gen_rtx_REG (mode, regno);
11536 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
11537 mem = gen_rtx_MEM (mode, addr);
11538 set_mem_alias_set (mem, rs6000_sr_alias_set);
11540 insn = emit_move_insn (mem, reg);
11542 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
11545 /* Emit an offset memory reference suitable for a frame store, while
11546 converting to a valid addressing mode. */
11549 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
11551 rtx int_rtx, offset_rtx;
11553 int_rtx = GEN_INT (offset);
11555 if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
11557 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
11558 emit_move_insn (offset_rtx, int_rtx);
11561 offset_rtx = int_rtx;
11563 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
11566 /* Emit function prologue as insns. */
11569 rs6000_emit_prologue (void)
11571 rs6000_stack_t *info = rs6000_stack_info ();
11572 enum machine_mode reg_mode = Pmode;
11573 int reg_size = UNITS_PER_WORD;
11574 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11575 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
11576 rtx frame_reg_rtx = sp_reg_rtx;
11577 rtx cr_save_rtx = NULL_RTX;
11579 int saving_FPRs_inline;
11580 int using_store_multiple;
11581 HOST_WIDE_INT sp_offset = 0;
11583 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
11585 reg_mode = V2SImode;
11589 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
11590 && (!TARGET_SPE_ABI
11591 || info->spe_64bit_regs_used == 0)
11592 && info->first_gp_reg_save < 31);
11593 saving_FPRs_inline = (info->first_fp_reg_save == 64
11594 || FP_SAVE_INLINE (info->first_fp_reg_save)
11595 || current_function_calls_eh_return
11596 || cfun->machine->ra_need_lr);
11598 /* For V.4, update stack before we do any saving and set back pointer. */
11600 && (DEFAULT_ABI == ABI_V4
11601 || current_function_calls_eh_return))
11603 if (info->total_size < 32767)
11604 sp_offset = info->total_size;
11606 frame_reg_rtx = frame_ptr_rtx;
11607 rs6000_emit_allocate_stack (info->total_size,
11608 (frame_reg_rtx != sp_reg_rtx
11609 && (info->cr_save_p
11611 || info->first_fp_reg_save < 64
11612 || info->first_gp_reg_save < 32
11614 if (frame_reg_rtx != sp_reg_rtx)
11615 rs6000_emit_stack_tie ();
11618 /* Save AltiVec registers if needed. */
11619 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
11623 /* There should be a non inline version of this, for when we
11624 are saving lots of vector registers. */
11625 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
11626 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
11628 rtx areg, savereg, mem;
11631 offset = info->altivec_save_offset + sp_offset
11632 + 16 * (i - info->first_altivec_reg_save);
11634 savereg = gen_rtx_REG (V4SImode, i);
11636 areg = gen_rtx_REG (Pmode, 0);
11637 emit_move_insn (areg, GEN_INT (offset));
11639 /* AltiVec addressing mode is [reg+reg]. */
11640 mem = gen_rtx_MEM (V4SImode,
11641 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
11643 set_mem_alias_set (mem, rs6000_sr_alias_set);
11645 insn = emit_move_insn (mem, savereg);
11647 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11648 areg, GEN_INT (offset));
11652 /* VRSAVE is a bit vector representing which AltiVec registers
11653 are used. The OS uses this to determine which vector
11654 registers to save on a context switch. We need to save
11655 VRSAVE on the stack frame, add whatever AltiVec registers we
11656 used in this function, and do the corresponding magic in the
11659 if (TARGET_ALTIVEC && info->vrsave_mask != 0)
11661 rtx reg, mem, vrsave;
11664 /* Get VRSAVE onto a GPR. */
11665 reg = gen_rtx_REG (SImode, 12);
11666 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
11668 emit_insn (gen_get_vrsave_internal (reg));
11670 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
11673 offset = info->vrsave_save_offset + sp_offset;
11675 = gen_rtx_MEM (SImode,
11676 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
11677 set_mem_alias_set (mem, rs6000_sr_alias_set);
11678 insn = emit_move_insn (mem, reg);
11680 /* Include the registers in the mask. */
11681 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
11683 insn = emit_insn (generate_set_vrsave (reg, info, 0));
11686 /* If we use the link register, get it into r0. */
11687 if (info->lr_save_p)
11688 emit_move_insn (gen_rtx_REG (Pmode, 0),
11689 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
11691 /* If we need to save CR, put it into r12. */
11692 if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
11694 cr_save_rtx = gen_rtx_REG (SImode, 12);
11695 emit_insn (gen_movesi_from_cr (cr_save_rtx));
11698 /* Do any required saving of fpr's. If only one or two to save, do
11699 it ourselves. Otherwise, call function. */
11700 if (saving_FPRs_inline)
11703 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
11704 if ((regs_ever_live[info->first_fp_reg_save+i]
11705 && ! call_used_regs[info->first_fp_reg_save+i]))
11706 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
11707 info->first_fp_reg_save + i,
11708 info->fp_save_offset + sp_offset + 8 * i,
11711 else if (info->first_fp_reg_save != 64)
11715 const char *alloc_rname;
11717 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
11719 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
11720 gen_rtx_REG (Pmode,
11721 LINK_REGISTER_REGNUM));
11722 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
11723 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
11724 alloc_rname = ggc_strdup (rname);
11725 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
11726 gen_rtx_SYMBOL_REF (Pmode,
11728 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
11730 rtx addr, reg, mem;
11731 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
11732 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11733 GEN_INT (info->fp_save_offset
11734 + sp_offset + 8*i));
11735 mem = gen_rtx_MEM (DFmode, addr);
11736 set_mem_alias_set (mem, rs6000_sr_alias_set);
11738 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
11740 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
11741 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11742 NULL_RTX, NULL_RTX);
11745 /* Save GPRs. This is done as a PARALLEL if we are using
11746 the store-multiple instructions. */
11747 if (using_store_multiple)
11751 p = rtvec_alloc (32 - info->first_gp_reg_save);
11752 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
11754 rtx addr, reg, mem;
11755 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
11756 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11757 GEN_INT (info->gp_save_offset
11760 mem = gen_rtx_MEM (reg_mode, addr);
11761 set_mem_alias_set (mem, rs6000_sr_alias_set);
11763 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
11765 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
11766 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11767 NULL_RTX, NULL_RTX);
11772 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
11773 if ((regs_ever_live[info->first_gp_reg_save+i]
11774 && ! call_used_regs[info->first_gp_reg_save+i])
11775 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
11776 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
11777 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
11779 rtx addr, reg, mem;
11780 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
11782 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
11784 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
11787 if (!SPE_CONST_OFFSET_OK (offset))
11789 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
11790 emit_move_insn (b, GEN_INT (offset));
11793 b = GEN_INT (offset);
11795 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
11796 mem = gen_rtx_MEM (V2SImode, addr);
11797 set_mem_alias_set (mem, rs6000_sr_alias_set);
11798 insn = emit_move_insn (mem, reg);
11800 if (GET_CODE (b) == CONST_INT)
11801 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11802 NULL_RTX, NULL_RTX);
11804 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11805 b, GEN_INT (offset));
11809 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11810 GEN_INT (info->gp_save_offset
11813 mem = gen_rtx_MEM (reg_mode, addr);
11814 set_mem_alias_set (mem, rs6000_sr_alias_set);
11816 insn = emit_move_insn (mem, reg);
11817 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11818 NULL_RTX, NULL_RTX);
11823 /* ??? There's no need to emit actual instructions here, but it's the
11824 easiest way to get the frame unwind information emitted. */
11825 if (current_function_calls_eh_return)
11827 unsigned int i, regno;
11829 /* In AIX ABI we need to pretend we save r2 here. */
11832 rtx addr, reg, mem;
11834 reg = gen_rtx_REG (reg_mode, 2);
11835 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11836 GEN_INT (sp_offset + 5 * reg_size));
11837 mem = gen_rtx_MEM (reg_mode, addr);
11838 set_mem_alias_set (mem, rs6000_sr_alias_set);
11840 insn = emit_move_insn (mem, reg);
11841 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11842 NULL_RTX, NULL_RTX);
11843 PATTERN (insn) = gen_blockage ();
11848 regno = EH_RETURN_DATA_REGNO (i);
11849 if (regno == INVALID_REGNUM)
11852 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
11853 info->ehrd_offset + sp_offset
11854 + reg_size * (int) i,
11859 /* Save lr if we used it. */
11860 if (info->lr_save_p)
11862 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11863 GEN_INT (info->lr_save_offset + sp_offset));
11864 rtx reg = gen_rtx_REG (Pmode, 0);
11865 rtx mem = gen_rtx_MEM (Pmode, addr);
11866 /* This should not be of rs6000_sr_alias_set, because of
11867 __builtin_return_address. */
11869 insn = emit_move_insn (mem, reg);
11870 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11871 reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
11874 /* Save CR if we use any that must be preserved. */
11875 if (info->cr_save_p)
11877 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11878 GEN_INT (info->cr_save_offset + sp_offset));
11879 rtx mem = gen_rtx_MEM (SImode, addr);
11881 set_mem_alias_set (mem, rs6000_sr_alias_set);
11883 /* If r12 was used to hold the original sp, copy cr into r0 now
11885 if (REGNO (frame_reg_rtx) == 12)
11887 cr_save_rtx = gen_rtx_REG (SImode, 0);
11888 emit_insn (gen_movesi_from_cr (cr_save_rtx));
11890 insn = emit_move_insn (mem, cr_save_rtx);
11892 /* Now, there's no way that dwarf2out_frame_debug_expr is going
11893 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
11894 But that's OK. All we have to do is specify that _one_ condition
11895 code register is saved in this stack slot. The thrower's epilogue
11896 will then restore all the call-saved registers.
11897 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
11898 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11899 cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO));
11902 /* Update stack and set back pointer unless this is V.4,
11903 for which it was done previously. */
11905 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
11906 rs6000_emit_allocate_stack (info->total_size, FALSE);
11908 /* Set frame pointer, if needed. */
11909 if (frame_pointer_needed)
11911 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
11913 RTX_FRAME_RELATED_P (insn) = 1;
11916 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
11917 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
11918 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
11919 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
11921 /* If emit_load_toc_table will use the link register, we need to save
11922 it. We use R12 for this purpose because emit_load_toc_table
11923 can use register 0. This allows us to use a plain 'blr' to return
11924 from the procedure more often. */
11925 int save_LR_around_toc_setup = (TARGET_ELF
11926 && DEFAULT_ABI != ABI_AIX
11928 && ! info->lr_save_p
11929 && EXIT_BLOCK_PTR->pred != NULL);
11930 if (save_LR_around_toc_setup)
11932 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11933 rs6000_maybe_dead (emit_move_insn (frame_ptr_rtx, lr));
11934 rs6000_emit_load_toc_table (TRUE);
11935 rs6000_maybe_dead (emit_move_insn (lr, frame_ptr_rtx));
11938 rs6000_emit_load_toc_table (TRUE);
11942 if (DEFAULT_ABI == ABI_DARWIN
11943 && flag_pic && current_function_uses_pic_offset_table)
11945 rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11946 const char *picbase = machopic_function_base_name ();
11947 rtx src = gen_rtx_SYMBOL_REF (Pmode, picbase);
11949 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest, src)));
11951 rs6000_maybe_dead (
11952 emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM),
11953 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)));
11958 /* Write function prologue. */
11961 rs6000_output_function_prologue (FILE *file,
11962 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11964 rs6000_stack_t *info = rs6000_stack_info ();
11966 if (TARGET_DEBUG_STACK)
11967 debug_stack_info (info);
11969 /* Write .extern for any function we will call to save and restore
11971 if (info->first_fp_reg_save < 64
11972 && !FP_SAVE_INLINE (info->first_fp_reg_save))
11973 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
11974 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
11975 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
11976 RESTORE_FP_SUFFIX);
11978 /* Write .extern for AIX common mode routines, if needed. */
11979 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
11981 fputs ("\t.extern __mulh\n", file);
11982 fputs ("\t.extern __mull\n", file);
11983 fputs ("\t.extern __divss\n", file);
11984 fputs ("\t.extern __divus\n", file);
11985 fputs ("\t.extern __quoss\n", file);
11986 fputs ("\t.extern __quous\n", file);
11987 common_mode_defined = 1;
11990 if (! HAVE_prologue)
11994 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
11995 the "toplevel" insn chain. */
11996 emit_note (NOTE_INSN_DELETED);
11997 rs6000_emit_prologue ();
11998 emit_note (NOTE_INSN_DELETED);
12000 /* Expand INSN_ADDRESSES so final() doesn't crash. */
12004 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12006 INSN_ADDRESSES_NEW (insn, addr);
12011 if (TARGET_DEBUG_STACK)
12012 debug_rtx_list (get_insns (), 100);
12013 final (get_insns (), file, FALSE, FALSE);
12017 rs6000_pic_labelno++;
12020 /* Emit function epilogue as insns.
12022 At present, dwarf2out_frame_debug_expr doesn't understand
12023 register restores, so we don't bother setting RTX_FRAME_RELATED_P
12024 anywhere in the epilogue. Most of the insns below would in any case
12025 need special notes to explain where r11 is in relation to the stack. */
12028 rs6000_emit_epilogue (int sibcall)
12030 rs6000_stack_t *info;
12031 int restoring_FPRs_inline;
12032 int using_load_multiple;
12033 int using_mfcr_multiple;
12034 int use_backchain_to_restore_sp;
12036 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
12037 rtx frame_reg_rtx = sp_reg_rtx;
12038 enum machine_mode reg_mode = Pmode;
12039 int reg_size = UNITS_PER_WORD;
12042 info = rs6000_stack_info ();
12044 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12046 reg_mode = V2SImode;
12050 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12051 && (!TARGET_SPE_ABI
12052 || info->spe_64bit_regs_used == 0)
12053 && info->first_gp_reg_save < 31);
12054 restoring_FPRs_inline = (sibcall
12055 || current_function_calls_eh_return
12056 || info->first_fp_reg_save == 64
12057 || FP_SAVE_INLINE (info->first_fp_reg_save));
12058 use_backchain_to_restore_sp = (frame_pointer_needed
12059 || current_function_calls_alloca
12060 || info->total_size > 32767);
12061 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
12062 || rs6000_cpu == PROCESSOR_PPC603
12063 || rs6000_cpu == PROCESSOR_PPC750
12066 /* If we have a frame pointer, a call to alloca, or a large stack
12067 frame, restore the old stack pointer using the backchain. Otherwise,
12068 we know what size to update it with. */
12069 if (use_backchain_to_restore_sp)
12071 /* Under V.4, don't reset the stack pointer until after we're done
12072 loading the saved registers. */
12073 if (DEFAULT_ABI == ABI_V4)
12074 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
12076 emit_move_insn (frame_reg_rtx,
12077 gen_rtx_MEM (Pmode, sp_reg_rtx));
12080 else if (info->push_p)
12082 if (DEFAULT_ABI == ABI_V4
12083 || current_function_calls_eh_return)
12084 sp_offset = info->total_size;
12087 emit_insn (TARGET_32BIT
12088 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12089 GEN_INT (info->total_size))
12090 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12091 GEN_INT (info->total_size)));
12095 /* Restore AltiVec registers if needed. */
12096 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
12100 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12101 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12103 rtx addr, areg, mem;
12105 areg = gen_rtx_REG (Pmode, 0);
12107 (areg, GEN_INT (info->altivec_save_offset
12109 + 16 * (i - info->first_altivec_reg_save)));
12111 /* AltiVec addressing mode is [reg+reg]. */
12112 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
12113 mem = gen_rtx_MEM (V4SImode, addr);
12114 set_mem_alias_set (mem, rs6000_sr_alias_set);
12116 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
12120 /* Restore VRSAVE if needed. */
12121 if (TARGET_ALTIVEC_ABI && info->vrsave_mask != 0)
12123 rtx addr, mem, reg;
12125 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12126 GEN_INT (info->vrsave_save_offset + sp_offset));
12127 mem = gen_rtx_MEM (SImode, addr);
12128 set_mem_alias_set (mem, rs6000_sr_alias_set);
12129 reg = gen_rtx_REG (SImode, 12);
12130 emit_move_insn (reg, mem);
12132 emit_insn (generate_set_vrsave (reg, info, 1));
12135 /* Get the old lr if we saved it. */
12136 if (info->lr_save_p)
12138 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
12139 info->lr_save_offset + sp_offset);
12141 set_mem_alias_set (mem, rs6000_sr_alias_set);
12143 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
12146 /* Get the old cr if we saved it. */
12147 if (info->cr_save_p)
12149 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12150 GEN_INT (info->cr_save_offset + sp_offset));
12151 rtx mem = gen_rtx_MEM (SImode, addr);
12153 set_mem_alias_set (mem, rs6000_sr_alias_set);
12155 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
12158 /* Set LR here to try to overlap restores below. */
12159 if (info->lr_save_p)
12160 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
12161 gen_rtx_REG (Pmode, 0));
12163 /* Load exception handler data registers, if needed. */
12164 if (current_function_calls_eh_return)
12166 unsigned int i, regno;
12170 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12171 GEN_INT (sp_offset + 5 * reg_size));
12172 rtx mem = gen_rtx_MEM (reg_mode, addr);
12174 set_mem_alias_set (mem, rs6000_sr_alias_set);
12176 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
12183 regno = EH_RETURN_DATA_REGNO (i);
12184 if (regno == INVALID_REGNUM)
12187 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
12188 info->ehrd_offset + sp_offset
12189 + reg_size * (int) i);
12190 set_mem_alias_set (mem, rs6000_sr_alias_set);
12192 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
12196 /* Restore GPRs. This is done as a PARALLEL if we are using
12197 the load-multiple instructions. */
12198 if (using_load_multiple)
12201 p = rtvec_alloc (32 - info->first_gp_reg_save);
12202 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12204 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12205 GEN_INT (info->gp_save_offset
12208 rtx mem = gen_rtx_MEM (reg_mode, addr);
12210 set_mem_alias_set (mem, rs6000_sr_alias_set);
12213 gen_rtx_SET (VOIDmode,
12214 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
12217 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12220 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12221 if ((regs_ever_live[info->first_gp_reg_save+i]
12222 && ! call_used_regs[info->first_gp_reg_save+i])
12223 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12224 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12225 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12227 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12228 GEN_INT (info->gp_save_offset
12231 rtx mem = gen_rtx_MEM (reg_mode, addr);
12233 /* Restore 64-bit quantities for SPE. */
12234 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12236 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12239 if (!SPE_CONST_OFFSET_OK (offset))
12241 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12242 emit_move_insn (b, GEN_INT (offset));
12245 b = GEN_INT (offset);
12247 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12248 mem = gen_rtx_MEM (V2SImode, addr);
12251 set_mem_alias_set (mem, rs6000_sr_alias_set);
12253 emit_move_insn (gen_rtx_REG (reg_mode,
12254 info->first_gp_reg_save + i), mem);
12257 /* Restore fpr's if we need to do it without calling a function. */
12258 if (restoring_FPRs_inline)
12259 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12260 if ((regs_ever_live[info->first_fp_reg_save+i]
12261 && ! call_used_regs[info->first_fp_reg_save+i]))
12264 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12265 GEN_INT (info->fp_save_offset
12268 mem = gen_rtx_MEM (DFmode, addr);
12269 set_mem_alias_set (mem, rs6000_sr_alias_set);
12271 emit_move_insn (gen_rtx_REG (DFmode,
12272 info->first_fp_reg_save + i),
12276 /* If we saved cr, restore it here. Just those that were used. */
12277 if (info->cr_save_p)
12279 rtx r12_rtx = gen_rtx_REG (SImode, 12);
12282 if (using_mfcr_multiple)
12284 for (i = 0; i < 8; i++)
12285 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12291 if (using_mfcr_multiple && count > 1)
12296 p = rtvec_alloc (count);
12299 for (i = 0; i < 8; i++)
12300 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12302 rtvec r = rtvec_alloc (2);
12303 RTVEC_ELT (r, 0) = r12_rtx;
12304 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
12305 RTVEC_ELT (p, ndx) =
12306 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
12307 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
12310 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12315 for (i = 0; i < 8; i++)
12316 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12318 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
12324 /* If this is V.4, unwind the stack pointer after all of the loads
12325 have been done. We need to emit a block here so that sched
12326 doesn't decide to move the sp change before the register restores
12327 (which may not have any obvious dependency on the stack). This
12328 doesn't hurt performance, because there is no scheduling that can
12329 be done after this point. */
12330 if (DEFAULT_ABI == ABI_V4
12331 || current_function_calls_eh_return)
12333 if (frame_reg_rtx != sp_reg_rtx)
12334 rs6000_emit_stack_tie ();
12336 if (use_backchain_to_restore_sp)
12338 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
12340 else if (sp_offset != 0)
12342 emit_insn (TARGET_32BIT
12343 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12344 GEN_INT (sp_offset))
12345 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12346 GEN_INT (sp_offset)));
12350 if (current_function_calls_eh_return)
12352 rtx sa = EH_RETURN_STACKADJ_RTX;
12353 emit_insn (TARGET_32BIT
12354 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
12355 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
12361 if (! restoring_FPRs_inline)
12362 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
12364 p = rtvec_alloc (2);
12366 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
12367 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12368 gen_rtx_REG (Pmode,
12369 LINK_REGISTER_REGNUM));
12371 /* If we have to restore more than two FP registers, branch to the
12372 restore function. It will return to our caller. */
12373 if (! restoring_FPRs_inline)
12377 const char *alloc_rname;
12379 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
12380 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
12381 alloc_rname = ggc_strdup (rname);
12382 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
12383 gen_rtx_SYMBOL_REF (Pmode,
12386 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12389 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
12390 GEN_INT (info->fp_save_offset + 8*i));
12391 mem = gen_rtx_MEM (DFmode, addr);
12392 set_mem_alias_set (mem, rs6000_sr_alias_set);
12394 RTVEC_ELT (p, i+3) =
12395 gen_rtx_SET (VOIDmode,
12396 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
12401 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
12405 /* Write function epilogue. */
12408 rs6000_output_function_epilogue (FILE *file,
12409 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12411 rs6000_stack_t *info = rs6000_stack_info ();
12413 if (! HAVE_epilogue)
12415 rtx insn = get_last_insn ();
12416 /* If the last insn was a BARRIER, we don't have to write anything except
12417 the trace table. */
12418 if (GET_CODE (insn) == NOTE)
12419 insn = prev_nonnote_insn (insn);
12420 if (insn == 0 || GET_CODE (insn) != BARRIER)
12422 /* This is slightly ugly, but at least we don't have two
12423 copies of the epilogue-emitting code. */
12426 /* A NOTE_INSN_DELETED is supposed to be at the start
12427 and end of the "toplevel" insn chain. */
12428 emit_note (NOTE_INSN_DELETED);
12429 rs6000_emit_epilogue (FALSE);
12430 emit_note (NOTE_INSN_DELETED);
12432 /* Expand INSN_ADDRESSES so final() doesn't crash. */
12436 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12438 INSN_ADDRESSES_NEW (insn, addr);
12443 if (TARGET_DEBUG_STACK)
12444 debug_rtx_list (get_insns (), 100);
12445 final (get_insns (), file, FALSE, FALSE);
12451 macho_branch_islands ();
12452 /* Mach-O doesn't support labels at the end of objects, so if
12453 it looks like we might want one, insert a NOP. */
12455 rtx insn = get_last_insn ();
12458 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
12459 insn = PREV_INSN (insn);
12463 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
12464 fputs ("\tnop\n", file);
12468 /* Output a traceback table here. See /usr/include/sys/debug.h for info
12471 We don't output a traceback table if -finhibit-size-directive was
12472 used. The documentation for -finhibit-size-directive reads
12473 ``don't output a @code{.size} assembler directive, or anything
12474 else that would cause trouble if the function is split in the
12475 middle, and the two halves are placed at locations far apart in
12476 memory.'' The traceback table has this property, since it
12477 includes the offset from the start of the function to the
12478 traceback table itself.
12480 System V.4 Powerpc's (and the embedded ABI derived from it) use a
12481 different traceback table. */
12482 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
12483 && rs6000_traceback != traceback_none)
12485 const char *fname = NULL;
12486 const char *language_string = lang_hooks.name;
12487 int fixed_parms = 0, float_parms = 0, parm_info = 0;
12489 int optional_tbtab;
12491 if (rs6000_traceback == traceback_full)
12492 optional_tbtab = 1;
12493 else if (rs6000_traceback == traceback_part)
12494 optional_tbtab = 0;
12496 optional_tbtab = !optimize_size && !TARGET_ELF;
12498 if (optional_tbtab)
12500 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
12501 while (*fname == '.') /* V.4 encodes . in the name */
12504 /* Need label immediately before tbtab, so we can compute
12505 its offset from the function start. */
12506 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
12507 ASM_OUTPUT_LABEL (file, fname);
12510 /* The .tbtab pseudo-op can only be used for the first eight
12511 expressions, since it can't handle the possibly variable
12512 length fields that follow. However, if you omit the optional
12513 fields, the assembler outputs zeros for all optional fields
12514 anyways, giving each variable length field is minimum length
12515 (as defined in sys/debug.h). Thus we can not use the .tbtab
12516 pseudo-op at all. */
12518 /* An all-zero word flags the start of the tbtab, for debuggers
12519 that have to find it by searching forward from the entry
12520 point or from the current pc. */
12521 fputs ("\t.long 0\n", file);
12523 /* Tbtab format type. Use format type 0. */
12524 fputs ("\t.byte 0,", file);
12526 /* Language type. Unfortunately, there does not seem to be any
12527 official way to discover the language being compiled, so we
12528 use language_string.
12529 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
12530 Java is 13. Objective-C is 14. */
12531 if (! strcmp (language_string, "GNU C"))
12533 else if (! strcmp (language_string, "GNU F77"))
12535 else if (! strcmp (language_string, "GNU Pascal"))
12537 else if (! strcmp (language_string, "GNU Ada"))
12539 else if (! strcmp (language_string, "GNU C++"))
12541 else if (! strcmp (language_string, "GNU Java"))
12543 else if (! strcmp (language_string, "GNU Objective-C"))
12547 fprintf (file, "%d,", i);
12549 /* 8 single bit fields: global linkage (not set for C extern linkage,
12550 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
12551 from start of procedure stored in tbtab, internal function, function
12552 has controlled storage, function has no toc, function uses fp,
12553 function logs/aborts fp operations. */
12554 /* Assume that fp operations are used if any fp reg must be saved. */
12555 fprintf (file, "%d,",
12556 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
12558 /* 6 bitfields: function is interrupt handler, name present in
12559 proc table, function calls alloca, on condition directives
12560 (controls stack walks, 3 bits), saves condition reg, saves
12562 /* The `function calls alloca' bit seems to be set whenever reg 31 is
12563 set up as a frame pointer, even when there is no alloca call. */
12564 fprintf (file, "%d,",
12565 ((optional_tbtab << 6)
12566 | ((optional_tbtab & frame_pointer_needed) << 5)
12567 | (info->cr_save_p << 1)
12568 | (info->lr_save_p)));
12570 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
12572 fprintf (file, "%d,",
12573 (info->push_p << 7) | (64 - info->first_fp_reg_save));
12575 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
12576 fprintf (file, "%d,", (32 - first_reg_to_save ()));
12578 if (optional_tbtab)
12580 /* Compute the parameter info from the function decl argument
12583 int next_parm_info_bit = 31;
12585 for (decl = DECL_ARGUMENTS (current_function_decl);
12586 decl; decl = TREE_CHAIN (decl))
12588 rtx parameter = DECL_INCOMING_RTL (decl);
12589 enum machine_mode mode = GET_MODE (parameter);
12591 if (GET_CODE (parameter) == REG)
12593 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
12599 if (mode == SFmode)
12601 else if (mode == DFmode || mode == TFmode)
12606 /* If only one bit will fit, don't or in this entry. */
12607 if (next_parm_info_bit > 0)
12608 parm_info |= (bits << (next_parm_info_bit - 1));
12609 next_parm_info_bit -= 2;
12613 fixed_parms += ((GET_MODE_SIZE (mode)
12614 + (UNITS_PER_WORD - 1))
12616 next_parm_info_bit -= 1;
12622 /* Number of fixed point parameters. */
12623 /* This is actually the number of words of fixed point parameters; thus
12624 an 8 byte struct counts as 2; and thus the maximum value is 8. */
12625 fprintf (file, "%d,", fixed_parms);
12627 /* 2 bitfields: number of floating point parameters (7 bits), parameters
12629 /* This is actually the number of fp registers that hold parameters;
12630 and thus the maximum value is 13. */
12631 /* Set parameters on stack bit if parameters are not in their original
12632 registers, regardless of whether they are on the stack? Xlc
12633 seems to set the bit when not optimizing. */
12634 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
12636 if (! optional_tbtab)
12639 /* Optional fields follow. Some are variable length. */
12641 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
12642 11 double float. */
12643 /* There is an entry for each parameter in a register, in the order that
12644 they occur in the parameter list. Any intervening arguments on the
12645 stack are ignored. If the list overflows a long (max possible length
12646 34 bits) then completely leave off all elements that don't fit. */
12647 /* Only emit this long if there was at least one parameter. */
12648 if (fixed_parms || float_parms)
12649 fprintf (file, "\t.long %d\n", parm_info);
12651 /* Offset from start of code to tb table. */
12652 fputs ("\t.long ", file);
12653 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
12655 RS6000_OUTPUT_BASENAME (file, fname);
12657 assemble_name (file, fname);
12659 fputs ("-.", file);
12661 RS6000_OUTPUT_BASENAME (file, fname);
12663 assemble_name (file, fname);
12667 /* Interrupt handler mask. */
12668 /* Omit this long, since we never set the interrupt handler bit
12671 /* Number of CTL (controlled storage) anchors. */
12672 /* Omit this long, since the has_ctl bit is never set above. */
12674 /* Displacement into stack of each CTL anchor. */
12675 /* Omit this list of longs, because there are no CTL anchors. */
12677 /* Length of function name. */
12680 fprintf (file, "\t.short %d\n", (int) strlen (fname));
12682 /* Function name. */
12683 assemble_string (fname, strlen (fname));
12685 /* Register for alloca automatic storage; this is always reg 31.
12686 Only emit this if the alloca bit was set above. */
12687 if (frame_pointer_needed)
12688 fputs ("\t.byte 31\n", file);
12690 fputs ("\t.align 2\n", file);
12694 /* A C compound statement that outputs the assembler code for a thunk
12695 function, used to implement C++ virtual function calls with
12696 multiple inheritance. The thunk acts as a wrapper around a virtual
12697 function, adjusting the implicit object parameter before handing
12698 control off to the real function.
12700 First, emit code to add the integer DELTA to the location that
12701 contains the incoming first argument. Assume that this argument
12702 contains a pointer, and is the one used to pass the `this' pointer
12703 in C++. This is the incoming argument *before* the function
12704 prologue, e.g. `%o0' on a sparc. The addition must preserve the
12705 values of all other incoming arguments.
12707 After the addition, emit code to jump to FUNCTION, which is a
12708 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
12709 not touch the return address. Hence returning from FUNCTION will
12710 return to whoever called the current `thunk'.
12712 The effect must be as if FUNCTION had been called directly with the
12713 adjusted first argument. This macro is responsible for emitting
12714 all of the code for a thunk function; output_function_prologue()
12715 and output_function_epilogue() are not invoked.
12717 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
12718 been extracted from it.) It might possibly be useful on some
12719 targets, but probably not.
12721 If you do not define this macro, the target-independent code in the
12722 C++ frontend will generate a less efficient heavyweight thunk that
12723 calls FUNCTION instead of jumping to it. The generic approach does
12724 not support varargs. */
12727 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
12728 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
12731 rtx this, insn, funexp;
12733 reload_completed = 1;
12734 epilogue_completed = 1;
12735 no_new_pseudos = 1;
12737 /* Mark the end of the (empty) prologue. */
12738 emit_note (NOTE_INSN_PROLOGUE_END);
12740 /* Find the "this" pointer. If the function returns a structure,
12741 the structure return pointer is in r3. */
12742 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
12743 this = gen_rtx_REG (Pmode, 4);
12745 this = gen_rtx_REG (Pmode, 3);
12747 /* Apply the constant offset, if required. */
12750 rtx delta_rtx = GEN_INT (delta);
12751 emit_insn (TARGET_32BIT
12752 ? gen_addsi3 (this, this, delta_rtx)
12753 : gen_adddi3 (this, this, delta_rtx));
12756 /* Apply the offset from the vtable, if required. */
12759 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
12760 rtx tmp = gen_rtx_REG (Pmode, 12);
12762 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
12763 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
12765 emit_insn (TARGET_32BIT
12766 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
12767 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
12768 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
12772 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
12774 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
12776 emit_insn (TARGET_32BIT
12777 ? gen_addsi3 (this, this, tmp)
12778 : gen_adddi3 (this, this, tmp));
12781 /* Generate a tail call to the target function. */
12782 if (!TREE_USED (function))
12784 assemble_external (function);
12785 TREE_USED (function) = 1;
12787 funexp = XEXP (DECL_RTL (function), 0);
12788 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
12791 if (MACHOPIC_INDIRECT)
12792 funexp = machopic_indirect_call_target (funexp);
12795 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
12796 generate sibcall RTL explicitly to avoid constraint abort. */
12797 insn = emit_call_insn (
12798 gen_rtx_PARALLEL (VOIDmode,
12800 gen_rtx_CALL (VOIDmode,
12801 funexp, const0_rtx),
12802 gen_rtx_USE (VOIDmode, const0_rtx),
12803 gen_rtx_USE (VOIDmode,
12804 gen_rtx_REG (SImode,
12805 LINK_REGISTER_REGNUM)),
12806 gen_rtx_RETURN (VOIDmode))));
12807 SIBLING_CALL_P (insn) = 1;
12810 /* Run just enough of rest_of_compilation to get the insns emitted.
12811 There's not really enough bulk here to make other passes such as
12812 instruction scheduling worth while. Note that use_thunk calls
12813 assemble_start_function and assemble_end_function. */
12814 insn = get_insns ();
12815 insn_locators_initialize ();
12816 shorten_branches (insn);
12817 final_start_function (insn, file, 1);
12818 final (insn, file, 1, 0);
12819 final_end_function ();
12821 reload_completed = 0;
12822 epilogue_completed = 0;
12823 no_new_pseudos = 0;
12826 /* A quick summary of the various types of 'constant-pool tables'
12829 Target Flags Name One table per
12830 AIX (none) AIX TOC object file
12831 AIX -mfull-toc AIX TOC object file
12832 AIX -mminimal-toc AIX minimal TOC translation unit
12833 SVR4/EABI (none) SVR4 SDATA object file
12834 SVR4/EABI -fpic SVR4 pic object file
12835 SVR4/EABI -fPIC SVR4 PIC translation unit
12836 SVR4/EABI -mrelocatable EABI TOC function
12837 SVR4/EABI -maix AIX TOC object file
12838 SVR4/EABI -maix -mminimal-toc
12839 AIX minimal TOC translation unit
12841 Name Reg. Set by entries contains:
12842 made by addrs? fp? sum?
12844 AIX TOC 2 crt0 as Y option option
12845 AIX minimal TOC 30 prolog gcc Y Y option
12846 SVR4 SDATA 13 crt0 gcc N Y N
12847 SVR4 pic 30 prolog ld Y not yet N
12848 SVR4 PIC 30 prolog gcc Y option option
12849 EABI TOC 30 prolog gcc Y option option
12853 /* Hash functions for the hash table. */
12856 rs6000_hash_constant (rtx k)
12858 enum rtx_code code = GET_CODE (k);
12859 enum machine_mode mode = GET_MODE (k);
12860 unsigned result = (code << 3) ^ mode;
12861 const char *format;
12864 format = GET_RTX_FORMAT (code);
12865 flen = strlen (format);
12871 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
12874 if (mode != VOIDmode)
12875 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
12887 for (; fidx < flen; fidx++)
12888 switch (format[fidx])
12893 const char *str = XSTR (k, fidx);
12894 len = strlen (str);
12895 result = result * 613 + len;
12896 for (i = 0; i < len; i++)
12897 result = result * 613 + (unsigned) str[i];
12902 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
12906 result = result * 613 + (unsigned) XINT (k, fidx);
12909 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
12910 result = result * 613 + (unsigned) XWINT (k, fidx);
12914 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
12915 result = result * 613 + (unsigned) (XWINT (k, fidx)
12929 toc_hash_function (const void *hash_entry)
12931 const struct toc_hash_struct *thc =
12932 (const struct toc_hash_struct *) hash_entry;
12933 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
12936 /* Compare H1 and H2 for equivalence. */
12939 toc_hash_eq (const void *h1, const void *h2)
12941 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
12942 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
12944 if (((const struct toc_hash_struct *) h1)->key_mode
12945 != ((const struct toc_hash_struct *) h2)->key_mode)
12948 return rtx_equal_p (r1, r2);
12951 /* These are the names given by the C++ front-end to vtables, and
12952 vtable-like objects. Ideally, this logic should not be here;
12953 instead, there should be some programmatic way of inquiring as
12954 to whether or not an object is a vtable. */
12956 #define VTABLE_NAME_P(NAME) \
12957 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
12958 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
12959 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
12960 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
12963 rs6000_output_symbol_ref (FILE *file, rtx x)
12965 /* Currently C++ toc references to vtables can be emitted before it
12966 is decided whether the vtable is public or private. If this is
12967 the case, then the linker will eventually complain that there is
12968 a reference to an unknown section. Thus, for vtables only,
12969 we emit the TOC reference to reference the symbol and not the
12971 const char *name = XSTR (x, 0);
12973 if (VTABLE_NAME_P (name))
12975 RS6000_OUTPUT_BASENAME (file, name);
12978 assemble_name (file, name);
12981 /* Output a TOC entry. We derive the entry name from what is being
12985 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
12988 const char *name = buf;
12989 const char *real_name;
12996 /* When the linker won't eliminate them, don't output duplicate
12997 TOC entries (this happens on AIX if there is any kind of TOC,
12998 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
13000 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
13002 struct toc_hash_struct *h;
13005 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
13006 time because GGC is not initialized at that point. */
13007 if (toc_hash_table == NULL)
13008 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
13009 toc_hash_eq, NULL);
13011 h = ggc_alloc (sizeof (*h));
13013 h->key_mode = mode;
13014 h->labelno = labelno;
13016 found = htab_find_slot (toc_hash_table, h, 1);
13017 if (*found == NULL)
13019 else /* This is indeed a duplicate.
13020 Set this label equal to that label. */
13022 fputs ("\t.set ", file);
13023 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
13024 fprintf (file, "%d,", labelno);
13025 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
13026 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
13032 /* If we're going to put a double constant in the TOC, make sure it's
13033 aligned properly when strict alignment is on. */
13034 if (GET_CODE (x) == CONST_DOUBLE
13035 && STRICT_ALIGNMENT
13036 && GET_MODE_BITSIZE (mode) >= 64
13037 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
13038 ASM_OUTPUT_ALIGN (file, 3);
13041 (*targetm.asm_out.internal_label) (file, "LC", labelno);
13043 /* Handle FP constants specially. Note that if we have a minimal
13044 TOC, things we put here aren't actually in the TOC, so we can allow
13046 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
13048 REAL_VALUE_TYPE rv;
13051 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13052 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
13056 if (TARGET_MINIMAL_TOC)
13057 fputs (DOUBLE_INT_ASM_OP, file);
13059 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13060 k[0] & 0xffffffff, k[1] & 0xffffffff,
13061 k[2] & 0xffffffff, k[3] & 0xffffffff);
13062 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
13063 k[0] & 0xffffffff, k[1] & 0xffffffff,
13064 k[2] & 0xffffffff, k[3] & 0xffffffff);
13069 if (TARGET_MINIMAL_TOC)
13070 fputs ("\t.long ", file);
13072 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13073 k[0] & 0xffffffff, k[1] & 0xffffffff,
13074 k[2] & 0xffffffff, k[3] & 0xffffffff);
13075 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
13076 k[0] & 0xffffffff, k[1] & 0xffffffff,
13077 k[2] & 0xffffffff, k[3] & 0xffffffff);
13081 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
13083 REAL_VALUE_TYPE rv;
13086 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13087 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
13091 if (TARGET_MINIMAL_TOC)
13092 fputs (DOUBLE_INT_ASM_OP, file);
13094 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13095 k[0] & 0xffffffff, k[1] & 0xffffffff);
13096 fprintf (file, "0x%lx%08lx\n",
13097 k[0] & 0xffffffff, k[1] & 0xffffffff);
13102 if (TARGET_MINIMAL_TOC)
13103 fputs ("\t.long ", file);
13105 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13106 k[0] & 0xffffffff, k[1] & 0xffffffff);
13107 fprintf (file, "0x%lx,0x%lx\n",
13108 k[0] & 0xffffffff, k[1] & 0xffffffff);
13112 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
13114 REAL_VALUE_TYPE rv;
13117 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13118 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
13122 if (TARGET_MINIMAL_TOC)
13123 fputs (DOUBLE_INT_ASM_OP, file);
13125 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13126 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
13131 if (TARGET_MINIMAL_TOC)
13132 fputs ("\t.long ", file);
13134 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13135 fprintf (file, "0x%lx\n", l & 0xffffffff);
13139 else if (GET_MODE (x) == VOIDmode
13140 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
13142 unsigned HOST_WIDE_INT low;
13143 HOST_WIDE_INT high;
13145 if (GET_CODE (x) == CONST_DOUBLE)
13147 low = CONST_DOUBLE_LOW (x);
13148 high = CONST_DOUBLE_HIGH (x);
13151 #if HOST_BITS_PER_WIDE_INT == 32
13154 high = (low & 0x80000000) ? ~0 : 0;
13158 low = INTVAL (x) & 0xffffffff;
13159 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
13163 /* TOC entries are always Pmode-sized, but since this
13164 is a bigendian machine then if we're putting smaller
13165 integer constants in the TOC we have to pad them.
13166 (This is still a win over putting the constants in
13167 a separate constant pool, because then we'd have
13168 to have both a TOC entry _and_ the actual constant.)
13170 For a 32-bit target, CONST_INT values are loaded and shifted
13171 entirely within `low' and can be stored in one TOC entry. */
13173 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
13174 abort ();/* It would be easy to make this work, but it doesn't now. */
13176 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
13178 #if HOST_BITS_PER_WIDE_INT == 32
13179 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
13180 POINTER_SIZE, &low, &high, 0);
13183 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
13184 high = (HOST_WIDE_INT) low >> 32;
13191 if (TARGET_MINIMAL_TOC)
13192 fputs (DOUBLE_INT_ASM_OP, file);
13194 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13195 (long) high & 0xffffffff, (long) low & 0xffffffff);
13196 fprintf (file, "0x%lx%08lx\n",
13197 (long) high & 0xffffffff, (long) low & 0xffffffff);
13202 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
13204 if (TARGET_MINIMAL_TOC)
13205 fputs ("\t.long ", file);
13207 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13208 (long) high & 0xffffffff, (long) low & 0xffffffff);
13209 fprintf (file, "0x%lx,0x%lx\n",
13210 (long) high & 0xffffffff, (long) low & 0xffffffff);
13214 if (TARGET_MINIMAL_TOC)
13215 fputs ("\t.long ", file);
13217 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
13218 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
13224 if (GET_CODE (x) == CONST)
13226 if (GET_CODE (XEXP (x, 0)) != PLUS)
13229 base = XEXP (XEXP (x, 0), 0);
13230 offset = INTVAL (XEXP (XEXP (x, 0), 1));
13233 if (GET_CODE (base) == SYMBOL_REF)
13234 name = XSTR (base, 0);
13235 else if (GET_CODE (base) == LABEL_REF)
13236 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
13237 else if (GET_CODE (base) == CODE_LABEL)
13238 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
13242 real_name = (*targetm.strip_name_encoding) (name);
13243 if (TARGET_MINIMAL_TOC)
13244 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
13247 fprintf (file, "\t.tc %s", real_name);
13250 fprintf (file, ".N%d", - offset);
13252 fprintf (file, ".P%d", offset);
13254 fputs ("[TC],", file);
13257 /* Currently C++ toc references to vtables can be emitted before it
13258 is decided whether the vtable is public or private. If this is
13259 the case, then the linker will eventually complain that there is
13260 a TOC reference to an unknown section. Thus, for vtables only,
13261 we emit the TOC reference to reference the symbol and not the
13263 if (VTABLE_NAME_P (name))
13265 RS6000_OUTPUT_BASENAME (file, name);
13267 fprintf (file, "%d", offset);
13268 else if (offset > 0)
13269 fprintf (file, "+%d", offset);
13272 output_addr_const (file, x);
13276 /* Output an assembler pseudo-op to write an ASCII string of N characters
13277 starting at P to FILE.
13279 On the RS/6000, we have to do this using the .byte operation and
13280 write out special characters outside the quoted string.
13281 Also, the assembler is broken; very long strings are truncated,
13282 so we must artificially break them up early. */
13285 output_ascii (FILE *file, const char *p, int n)
13288 int i, count_string;
13289 const char *for_string = "\t.byte \"";
13290 const char *for_decimal = "\t.byte ";
13291 const char *to_close = NULL;
13294 for (i = 0; i < n; i++)
13297 if (c >= ' ' && c < 0177)
13300 fputs (for_string, file);
13303 /* Write two quotes to get one. */
13311 for_decimal = "\"\n\t.byte ";
13315 if (count_string >= 512)
13317 fputs (to_close, file);
13319 for_string = "\t.byte \"";
13320 for_decimal = "\t.byte ";
13328 fputs (for_decimal, file);
13329 fprintf (file, "%d", c);
13331 for_string = "\n\t.byte \"";
13332 for_decimal = ", ";
13338 /* Now close the string if we have written one. Then end the line. */
13340 fputs (to_close, file);
13343 /* Generate a unique section name for FILENAME for a section type
13344 represented by SECTION_DESC. Output goes into BUF.
13346 SECTION_DESC can be any string, as long as it is different for each
13347 possible section type.
13349 We name the section in the same manner as xlc. The name begins with an
13350 underscore followed by the filename (after stripping any leading directory
13351 names) with the last period replaced by the string SECTION_DESC. If
13352 FILENAME does not contain a period, SECTION_DESC is appended to the end of
13356 rs6000_gen_section_name (char **buf, const char *filename,
13357 const char *section_desc)
13359 const char *q, *after_last_slash, *last_period = 0;
13363 after_last_slash = filename;
13364 for (q = filename; *q; q++)
13367 after_last_slash = q + 1;
13368 else if (*q == '.')
13372 len = strlen (after_last_slash) + strlen (section_desc) + 2;
13373 *buf = (char *) xmalloc (len);
13378 for (q = after_last_slash; *q; q++)
13380 if (q == last_period)
13382 strcpy (p, section_desc);
13383 p += strlen (section_desc);
13387 else if (ISALNUM (*q))
13391 if (last_period == 0)
13392 strcpy (p, section_desc);
13397 /* Emit profile function. */
13400 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
13402 if (TARGET_PROFILE_KERNEL)
13405 if (DEFAULT_ABI == ABI_AIX)
13407 #ifndef NO_PROFILE_COUNTERS
13408 # define NO_PROFILE_COUNTERS 0
13410 if (NO_PROFILE_COUNTERS)
13411 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
13415 const char *label_name;
13418 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13419 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
13420 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
13422 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
13426 else if (DEFAULT_ABI == ABI_DARWIN)
13428 const char *mcount_name = RS6000_MCOUNT;
13429 int caller_addr_regno = LINK_REGISTER_REGNUM;
13431 /* Be conservative and always set this, at least for now. */
13432 current_function_uses_pic_offset_table = 1;
13435 /* For PIC code, set up a stub and collect the caller's address
13436 from r0, which is where the prologue puts it. */
13437 if (MACHOPIC_INDIRECT)
13439 mcount_name = machopic_stub_name (mcount_name);
13440 if (current_function_uses_pic_offset_table)
13441 caller_addr_regno = 0;
13444 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
13446 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
13450 /* Write function profiler code. */
13453 output_function_profiler (FILE *file, int labelno)
13458 switch (DEFAULT_ABI)
13467 warning ("no profiling of 64-bit code for this ABI");
13470 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13471 fprintf (file, "\tmflr %s\n", reg_names[0]);
13474 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
13475 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13476 reg_names[0], save_lr, reg_names[1]);
13477 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
13478 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
13479 assemble_name (file, buf);
13480 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
13482 else if (flag_pic > 1)
13484 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13485 reg_names[0], save_lr, reg_names[1]);
13486 /* Now, we need to get the address of the label. */
13487 fputs ("\tbl 1f\n\t.long ", file);
13488 assemble_name (file, buf);
13489 fputs ("-.\n1:", file);
13490 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
13491 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
13492 reg_names[0], reg_names[11]);
13493 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
13494 reg_names[0], reg_names[0], reg_names[11]);
13498 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
13499 assemble_name (file, buf);
13500 fputs ("@ha\n", file);
13501 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13502 reg_names[0], save_lr, reg_names[1]);
13503 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
13504 assemble_name (file, buf);
13505 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
13508 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
13509 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13514 if (!TARGET_PROFILE_KERNEL)
13516 /* Don't do anything, done in output_profile_hook (). */
13523 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
13524 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
13526 if (current_function_needs_context)
13528 asm_fprintf (file, "\tstd %s,24(%s)\n",
13529 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13530 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13531 asm_fprintf (file, "\tld %s,24(%s)\n",
13532 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13535 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13543 rs6000_use_dfa_pipeline_interface (void)
13548 /* Power4 load update and store update instructions are cracked into a
13549 load or store and an integer insn which are executed in the same cycle.
13550 Branches have their own dispatch slot which does not count against the
13551 GCC issue rate, but it changes the program flow so there are no other
13552 instructions to issue in this cycle. */
13555 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
13556 int verbose ATTRIBUTE_UNUSED,
13557 rtx insn, int more)
13559 if (GET_CODE (PATTERN (insn)) == USE
13560 || GET_CODE (PATTERN (insn)) == CLOBBER)
13563 if (rs6000_cpu == PROCESSOR_POWER4)
13565 if (is_microcoded_insn (insn))
13567 else if (is_cracked_insn (insn))
13568 return more > 2 ? more - 2 : 0;
13574 /* Adjust the cost of a scheduling dependency. Return the new cost of
13575 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
13578 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED,
13581 if (! recog_memoized (insn))
13584 if (REG_NOTE_KIND (link) != 0)
13587 if (REG_NOTE_KIND (link) == 0)
13589 /* Data dependency; DEP_INSN writes a register that INSN reads
13590 some cycles later. */
13591 switch (get_attr_type (insn))
13594 /* Tell the first scheduling pass about the latency between
13595 a mtctr and bctr (and mtlr and br/blr). The first
13596 scheduling pass will not know about this latency since
13597 the mtctr instruction, which has the latency associated
13598 to it, will be generated by reload. */
13599 return TARGET_POWER ? 5 : 4;
13601 /* Leave some extra cycles between a compare and its
13602 dependent branch, to inhibit expensive mispredicts. */
13603 if ((rs6000_cpu_attr == CPU_PPC603
13604 || rs6000_cpu_attr == CPU_PPC604
13605 || rs6000_cpu_attr == CPU_PPC604E
13606 || rs6000_cpu_attr == CPU_PPC620
13607 || rs6000_cpu_attr == CPU_PPC630
13608 || rs6000_cpu_attr == CPU_PPC750
13609 || rs6000_cpu_attr == CPU_PPC7400
13610 || rs6000_cpu_attr == CPU_PPC7450
13611 || rs6000_cpu_attr == CPU_POWER4)
13612 && recog_memoized (dep_insn)
13613 && (INSN_CODE (dep_insn) >= 0)
13614 && (get_attr_type (dep_insn) == TYPE_CMP
13615 || get_attr_type (dep_insn) == TYPE_COMPARE
13616 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
13617 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
13618 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
13619 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
13620 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
13621 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
13626 /* Fall out to return default cost. */
13632 /* The function returns a true if INSN is microcoded.
13633 Return false otherwise. */
13636 is_microcoded_insn (rtx insn)
13638 if (!insn || !INSN_P (insn)
13639 || GET_CODE (PATTERN (insn)) == USE
13640 || GET_CODE (PATTERN (insn)) == CLOBBER)
13643 if (rs6000_cpu == PROCESSOR_POWER4)
13645 enum attr_type type = get_attr_type (insn);
13646 if (type == TYPE_LOAD_EXT_U
13647 || type == TYPE_LOAD_EXT_UX
13648 || type == TYPE_LOAD_UX
13649 || type == TYPE_STORE_UX
13650 || type == TYPE_MFCR)
13657 /* The function returns a nonzero value if INSN can be scheduled only
13658 as the first insn in a dispatch group ("dispatch-slot restricted").
13659 In this case, the returned value indicates how many dispatch slots
13660 the insn occupies (at the beginning of the group).
13661 Return 0 otherwise. */
13664 is_dispatch_slot_restricted (rtx insn)
13666 enum attr_type type;
13668 if (rs6000_cpu != PROCESSOR_POWER4)
13672 || insn == NULL_RTX
13673 || GET_CODE (insn) == NOTE
13674 || GET_CODE (PATTERN (insn)) == USE
13675 || GET_CODE (PATTERN (insn)) == CLOBBER)
13678 type = get_attr_type (insn);
13684 case TYPE_DELAYED_CR:
13685 case TYPE_CR_LOGICAL:
13697 /* The function returns true if INSN is cracked into 2 instructions
13698 by the processor (and therefore occupies 2 issue slots). */
13701 is_cracked_insn (rtx insn)
13703 if (!insn || !INSN_P (insn)
13704 || GET_CODE (PATTERN (insn)) == USE
13705 || GET_CODE (PATTERN (insn)) == CLOBBER)
13708 if (rs6000_cpu == PROCESSOR_POWER4)
13710 enum attr_type type = get_attr_type (insn);
13711 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
13712 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
13713 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
13714 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
13715 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
13716 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
13717 || type == TYPE_IDIV || type == TYPE_LDIV
13718 || type == TYPE_INSERT_WORD)
13725 /* The function returns true if INSN can be issued only from
13726 the branch slot. */
13729 is_branch_slot_insn (rtx insn)
13731 if (!insn || !INSN_P (insn)
13732 || GET_CODE (PATTERN (insn)) == USE
13733 || GET_CODE (PATTERN (insn)) == CLOBBER)
13736 if (rs6000_cpu == PROCESSOR_POWER4)
13738 enum attr_type type = get_attr_type (insn);
13739 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
13747 /* A C statement (sans semicolon) to update the integer scheduling
13748 priority INSN_PRIORITY (INSN). Increase the priority to execute the
13749 INSN earlier, reduce the priority to execute INSN later. Do not
13750 define this macro if you do not need to adjust the scheduling
13751 priorities of insns. */
13754 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
13756 /* On machines (like the 750) which have asymmetric integer units,
13757 where one integer unit can do multiply and divides and the other
13758 can't, reduce the priority of multiply/divide so it is scheduled
13759 before other integer operations. */
13762 if (! INSN_P (insn))
13765 if (GET_CODE (PATTERN (insn)) == USE)
13768 switch (rs6000_cpu_attr) {
13770 switch (get_attr_type (insn))
13777 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
13778 priority, priority);
13779 if (priority >= 0 && priority < 0x01000000)
13786 if (is_dispatch_slot_restricted (insn)
13787 && reload_completed
13788 && current_sched_info->sched_max_insns_priority
13789 && rs6000_sched_restricted_insns_priority)
13792 /* Prioritize insns that can be dispatched only in the first dispatch slot. */
13793 if (rs6000_sched_restricted_insns_priority == 1)
13794 /* Attach highest priority to insn. This means that in
13795 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
13796 precede 'priority' (critical path) considerations. */
13797 return current_sched_info->sched_max_insns_priority;
13798 else if (rs6000_sched_restricted_insns_priority == 2)
13799 /* Increase priority of insn by a minimal amount. This means that in
13800 haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations
13801 precede dispatch-slot restriction considerations. */
13802 return (priority + 1);
13808 /* Return how many instructions the machine can issue per cycle. */
13811 rs6000_issue_rate (void)
13813 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
13814 if (!reload_completed)
13817 switch (rs6000_cpu_attr) {
13818 case CPU_RIOS1: /* ? */
13820 case CPU_PPC601: /* ? */
13842 /* Return how many instructions to look ahead for better insn
13846 rs6000_use_sched_lookahead (void)
13848 if (rs6000_cpu_attr == CPU_PPC8540)
13853 /* Determine is PAT refers to memory. */
13856 is_mem_ref (rtx pat)
13862 if (GET_CODE (pat) == MEM)
13865 /* Recursively process the pattern. */
13866 fmt = GET_RTX_FORMAT (GET_CODE (pat));
13868 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
13871 ret |= is_mem_ref (XEXP (pat, i));
13872 else if (fmt[i] == 'E')
13873 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
13874 ret |= is_mem_ref (XVECEXP (pat, i, j));
13880 /* Determine if PAT is a PATTERN of a load insn. */
13883 is_load_insn1 (rtx pat)
13885 if (!pat || pat == NULL_RTX)
13888 if (GET_CODE (pat) == SET)
13889 return is_mem_ref (SET_SRC (pat));
13891 if (GET_CODE (pat) == PARALLEL)
13895 for (i = 0; i < XVECLEN (pat, 0); i++)
13896 if (is_load_insn1 (XVECEXP (pat, 0, i)))
13903 /* Determine if INSN loads from memory. */
13906 is_load_insn (rtx insn)
13908 if (!insn || !INSN_P (insn))
13911 if (GET_CODE (insn) == CALL_INSN)
13914 return is_load_insn1 (PATTERN (insn));
13917 /* Determine if PAT is a PATTERN of a store insn. */
13920 is_store_insn1 (rtx pat)
13922 if (!pat || pat == NULL_RTX)
13925 if (GET_CODE (pat) == SET)
13926 return is_mem_ref (SET_DEST (pat));
13928 if (GET_CODE (pat) == PARALLEL)
13932 for (i = 0; i < XVECLEN (pat, 0); i++)
13933 if (is_store_insn1 (XVECEXP (pat, 0, i)))
13940 /* Determine if INSN stores to memory. */
13943 is_store_insn (rtx insn)
13945 if (!insn || !INSN_P (insn))
13948 return is_store_insn1 (PATTERN (insn));
13951 /* Returns whether the dependence between INSN and NEXT is considered
13952 costly by the given target. */
13955 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distance)
13957 /* If the flag is not enbled - no dependence is considered costly;
13958 allow all dependent insns in the same group.
13959 This is the most aggressive option. */
13960 if (rs6000_sched_costly_dep == no_dep_costly)
13963 /* If the flag is set to 1 - a dependence is always considered costly;
13964 do not allow dependent instructions in the same group.
13965 This is the most conservative option. */
13966 if (rs6000_sched_costly_dep == all_deps_costly)
13969 if (rs6000_sched_costly_dep == store_to_load_dep_costly
13970 && is_load_insn (next)
13971 && is_store_insn (insn))
13972 /* Prevent load after store in the same group. */
13975 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
13976 && is_load_insn (next)
13977 && is_store_insn (insn)
13978 && (!link || (int) REG_NOTE_KIND (link) == 0))
13979 /* Prevent load after store in the same group if it is a true dependence. */
13982 /* The flag is set to X; dependences with latency >= X are considered costly,
13983 and will not be scheduled in the same group. */
13984 if (rs6000_sched_costly_dep <= max_dep_latency
13985 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
13991 /* Return the next insn after INSN that is found before TAIL is reached,
13992 skipping any "non-active" insns - insns that will not actually occupy
13993 an issue slot. Return NULL_RTX if such an insn is not found. */
13996 get_next_active_insn (rtx insn, rtx tail)
14000 if (!insn || insn == tail)
14003 next_insn = NEXT_INSN (insn);
14006 && next_insn != tail
14007 && (GET_CODE(next_insn) == NOTE
14008 || GET_CODE (PATTERN (next_insn)) == USE
14009 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
14011 next_insn = NEXT_INSN (next_insn);
14014 if (!next_insn || next_insn == tail)
14020 /* Return whether the presence of INSN causes a dispatch group termination
14021 of group WHICH_GROUP.
14023 If WHICH_GROUP == current_group, this function will return true if INSN
14024 causes the termination of the current group (i.e, the dispatch group to
14025 which INSN belongs). This means that INSN will be the last insn in the
14026 group it belongs to.
14028 If WHICH_GROUP == previous_group, this function will return true if INSN
14029 causes the termination of the previous group (i.e, the dispatch group that
14030 precedes the group to which INSN belongs). This means that INSN will be
14031 the first insn in the group it belongs to). */
14034 insn_terminates_group_p (rtx insn, enum group_termination which_group)
14036 enum attr_type type;
14041 type = get_attr_type (insn);
14043 if (is_microcoded_insn (insn))
14046 if (which_group == current_group)
14048 if (is_branch_slot_insn (insn))
14052 else if (which_group == previous_group)
14054 if (is_dispatch_slot_restricted (insn))
14062 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
14063 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
14066 is_costly_group (rtx *group_insns, rtx next_insn)
14071 int issue_rate = rs6000_issue_rate ();
14073 for (i = 0; i < issue_rate; i++)
14075 rtx insn = group_insns[i];
14078 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
14080 rtx next = XEXP (link, 0);
14081 if (next == next_insn)
14083 cost = insn_cost (insn, link, next_insn);
14084 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
14093 /* Utility of the function redefine_groups.
14094 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
14095 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
14096 to keep it "far" (in a separate group) from GROUP_INSNS, following
14097 one of the following schemes, depending on the value of the flag
14098 -minsert_sched_nops = X:
14099 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
14100 in order to force NEXT_INSN into a separate group.
14101 (2) X < sched_finish_regroup_exact: insert exactly X nops.
14102 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
14103 insertion (has a group just ended, how many vacant issue slots remain in the
14104 last group, and how many dispatch groups were encountered so far). */
14107 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn,
14108 bool *group_end, int can_issue_more, int *group_count)
14112 int issue_rate = rs6000_issue_rate ();
14113 bool end = *group_end;
14116 if (next_insn == NULL_RTX)
14117 return can_issue_more;
14119 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
14120 return can_issue_more;
14122 force = is_costly_group (group_insns, next_insn);
14124 return can_issue_more;
14126 if (sched_verbose > 6)
14127 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
14128 *group_count ,can_issue_more);
14130 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
14133 can_issue_more = 0;
14135 /* Since only a branch can be issued in the last issue_slot, it is
14136 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
14137 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
14138 in this case the last nop will start a new group and the branch will be
14139 forced to the new group. */
14140 if (can_issue_more && !is_branch_slot_insn (next_insn))
14143 while (can_issue_more > 0)
14146 emit_insn_before (nop, next_insn);
14154 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
14156 int n_nops = rs6000_sched_insert_nops;
14158 /* Nops can't be issued from the branch slot, so the effective
14159 issue_rate for nops is 'issue_rate - 1'. */
14160 if (can_issue_more == 0)
14161 can_issue_more = issue_rate;
14163 if (can_issue_more == 0)
14165 can_issue_more = issue_rate - 1;
14168 for (i = 0; i < issue_rate; i++)
14170 group_insns[i] = 0;
14177 emit_insn_before (nop, next_insn);
14178 if (can_issue_more == issue_rate - 1) /* new group begins */
14181 if (can_issue_more == 0)
14183 can_issue_more = issue_rate - 1;
14186 for (i = 0; i < issue_rate; i++)
14188 group_insns[i] = 0;
14194 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
14197 *group_end = /* Is next_insn going to start a new group? */
14199 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14200 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14201 || (can_issue_more < issue_rate &&
14202 insn_terminates_group_p (next_insn, previous_group)));
14203 if (*group_end && end)
14206 if (sched_verbose > 6)
14207 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
14208 *group_count, can_issue_more);
14209 return can_issue_more;
14212 return can_issue_more;
14215 /* This function tries to synch the dispatch groups that the compiler "sees"
14216 with the dispatch groups that the processor dispatcher is expected to
14217 form in practice. It tries to achieve this synchronization by forcing the
14218 estimated processor grouping on the compiler (as opposed to the function
14219 'pad_goups' which tries to force the scheduler's grouping on the processor).
14221 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
14222 examines the (estimated) dispatch groups that will be formed by the processor
14223 dispatcher. It marks these group boundaries to reflect the estimated
14224 processor grouping, overriding the grouping that the scheduler had marked.
14225 Depending on the value of the flag '-minsert-sched-nops' this function can
14226 force certain insns into separate groups or force a certain distance between
14227 them by inserting nops, for example, if there exists a "costly dependence"
14230 The function estimates the group boundaries that the processor will form as
14231 folllows: It keeps track of how many vacant issue slots are available after
14232 each insn. A subsequent insn will start a new group if one of the following
14234 - no more vacant issue slots remain in the current dispatch group.
14235 - only the last issue slot, which is the branch slot, is vacant, but the next
14236 insn is not a branch.
14237 - only the last 2 or less issue slots, including the branch slot, are vacant,
14238 which means that a cracked insn (which occupies two issue slots) can't be
14239 issued in this group.
14240 - less than 'issue_rate' slots are vacant, and the next insn always needs to
14241 start a new group. */
14244 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14246 rtx insn, next_insn;
14248 int can_issue_more;
14251 int group_count = 0;
14255 issue_rate = rs6000_issue_rate ();
14256 group_insns = alloca (issue_rate * sizeof (rtx));
14257 for (i = 0; i < issue_rate; i++)
14259 group_insns[i] = 0;
14261 can_issue_more = issue_rate;
14263 insn = get_next_active_insn (prev_head_insn, tail);
14266 while (insn != NULL_RTX)
14268 slot = (issue_rate - can_issue_more);
14269 group_insns[slot] = insn;
14271 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14272 if (insn_terminates_group_p (insn, current_group))
14273 can_issue_more = 0;
14275 next_insn = get_next_active_insn (insn, tail);
14276 if (next_insn == NULL_RTX)
14277 return group_count + 1;
14279 group_end = /* Is next_insn going to start a new group? */
14280 (can_issue_more == 0
14281 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14282 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14283 || (can_issue_more < issue_rate &&
14284 insn_terminates_group_p (next_insn, previous_group)));
14286 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
14287 next_insn, &group_end, can_issue_more, &group_count);
14292 can_issue_more = 0;
14293 for (i = 0; i < issue_rate; i++)
14295 group_insns[i] = 0;
14299 if (GET_MODE (next_insn) == TImode && can_issue_more)
14300 PUT_MODE(next_insn, VOIDmode);
14301 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
14302 PUT_MODE (next_insn, TImode);
14305 if (can_issue_more == 0)
14306 can_issue_more = issue_rate;
14309 return group_count;
14312 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
14313 dispatch group boundaries that the scheduler had marked. Pad with nops
14314 any dispatch groups which have vacant issue slots, in order to force the
14315 scheduler's grouping on the processor dispatcher. The function
14316 returns the number of dispatch groups found. */
14319 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14321 rtx insn, next_insn;
14324 int can_issue_more;
14326 int group_count = 0;
14328 /* Initialize issue_rate. */
14329 issue_rate = rs6000_issue_rate ();
14330 can_issue_more = issue_rate;
14332 insn = get_next_active_insn (prev_head_insn, tail);
14333 next_insn = get_next_active_insn (insn, tail);
14335 while (insn != NULL_RTX)
14338 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14340 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
14342 if (next_insn == NULL_RTX)
14347 /* If the scheduler had marked group termination at this location
14348 (between insn and next_indn), and neither insn nor next_insn will
14349 force group termination, pad the group with nops to force group
14352 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
14353 && !insn_terminates_group_p (insn, current_group)
14354 && !insn_terminates_group_p (next_insn, previous_group))
14356 if (!is_branch_slot_insn(next_insn))
14359 while (can_issue_more)
14362 emit_insn_before (nop, next_insn);
14367 can_issue_more = issue_rate;
14372 next_insn = get_next_active_insn (insn, tail);
14375 return group_count;
14378 /* The following function is called at the end of scheduling BB.
14379 After reload, it inserts nops at insn group bundling. */
14382 rs6000_sched_finish (FILE *dump, int sched_verbose)
14387 fprintf (dump, "=== Finishing schedule.\n");
14389 if (reload_completed && rs6000_cpu == PROCESSOR_POWER4)
14391 if (rs6000_sched_insert_nops == sched_finish_none)
14394 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
14395 n_groups = pad_groups (dump, sched_verbose,
14396 current_sched_info->prev_head,
14397 current_sched_info->next_tail);
14399 n_groups = redefine_groups (dump, sched_verbose,
14400 current_sched_info->prev_head,
14401 current_sched_info->next_tail);
14403 if (sched_verbose >= 6)
14405 fprintf (dump, "ngroups = %d\n", n_groups);
14406 print_rtl (dump, current_sched_info->prev_head);
14407 fprintf (dump, "Done finish_sched\n");
14412 /* Length in units of the trampoline for entering a nested function. */
14415 rs6000_trampoline_size (void)
14419 switch (DEFAULT_ABI)
14425 ret = (TARGET_32BIT) ? 12 : 24;
14430 ret = (TARGET_32BIT) ? 40 : 48;
14437 /* Emit RTL insns to initialize the variable parts of a trampoline.
14438 FNADDR is an RTX for the address of the function's pure code.
14439 CXT is an RTX for the static chain value for the function. */
14442 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
14444 enum machine_mode pmode = Pmode;
14445 int regsize = (TARGET_32BIT) ? 4 : 8;
14446 rtx ctx_reg = force_reg (pmode, cxt);
14448 switch (DEFAULT_ABI)
14453 /* Macros to shorten the code expansions below. */
14454 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
14455 #define MEM_PLUS(addr,offset) \
14456 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
14458 /* Under AIX, just build the 3 word function descriptor */
14461 rtx fn_reg = gen_reg_rtx (pmode);
14462 rtx toc_reg = gen_reg_rtx (pmode);
14463 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
14464 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
14465 emit_move_insn (MEM_DEREF (addr), fn_reg);
14466 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
14467 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
14471 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
14474 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
14475 FALSE, VOIDmode, 4,
14477 GEN_INT (rs6000_trampoline_size ()), SImode,
14487 /* Table of valid machine attributes. */
14489 const struct attribute_spec rs6000_attribute_table[] =
14491 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
14492 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
14493 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
14494 { NULL, 0, 0, false, false, false, NULL }
14497 /* Handle a "longcall" or "shortcall" attribute; arguments as in
14498 struct attribute_spec.handler. */
14501 rs6000_handle_longcall_attribute (tree *node, tree name,
14502 tree args ATTRIBUTE_UNUSED,
14503 int flags ATTRIBUTE_UNUSED,
14504 bool *no_add_attrs)
14506 if (TREE_CODE (*node) != FUNCTION_TYPE
14507 && TREE_CODE (*node) != FIELD_DECL
14508 && TREE_CODE (*node) != TYPE_DECL)
14510 warning ("`%s' attribute only applies to functions",
14511 IDENTIFIER_POINTER (name));
14512 *no_add_attrs = true;
14518 /* Set longcall attributes on all functions declared when
14519 rs6000_default_long_calls is true. */
14521 rs6000_set_default_type_attributes (tree type)
14523 if (rs6000_default_long_calls
14524 && (TREE_CODE (type) == FUNCTION_TYPE
14525 || TREE_CODE (type) == METHOD_TYPE))
14526 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
14528 TYPE_ATTRIBUTES (type));
14531 /* Return a reference suitable for calling a function with the
14532 longcall attribute. */
14535 rs6000_longcall_ref (rtx call_ref)
14537 const char *call_name;
14540 if (GET_CODE (call_ref) != SYMBOL_REF)
14543 /* System V adds '.' to the internal name, so skip them. */
14544 call_name = XSTR (call_ref, 0);
14545 if (*call_name == '.')
14547 while (*call_name == '.')
14550 node = get_identifier (call_name);
14551 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
14554 return force_reg (Pmode, call_ref);
14557 #ifdef USING_ELFOS_H
14559 /* A C statement or statements to switch to the appropriate section
14560 for output of RTX in mode MODE. You can assume that RTX is some
14561 kind of constant in RTL. The argument MODE is redundant except in
14562 the case of a `const_int' rtx. Select the section by calling
14563 `text_section' or one of the alternatives for other sections.
14565 Do not define this macro if you put all constants in the read-only
14569 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
14570 unsigned HOST_WIDE_INT align)
14572 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
14575 default_elf_select_rtx_section (mode, x, align);
14578 /* A C statement or statements to switch to the appropriate
14579 section for output of DECL. DECL is either a `VAR_DECL' node
14580 or a constant of some sort. RELOC indicates whether forming
14581 the initial value of DECL requires link-time relocations. */
14584 rs6000_elf_select_section (tree decl, int reloc,
14585 unsigned HOST_WIDE_INT align)
14587 /* Pretend that we're always building for a shared library when
14588 ABI_AIX, because otherwise we end up with dynamic relocations
14589 in read-only sections. This happens for function pointers,
14590 references to vtables in typeinfo, and probably other cases. */
14591 default_elf_select_section_1 (decl, reloc, align,
14592 flag_pic || DEFAULT_ABI == ABI_AIX);
14595 /* A C statement to build up a unique section name, expressed as a
14596 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
14597 RELOC indicates whether the initial value of EXP requires
14598 link-time relocations. If you do not define this macro, GCC will use
14599 the symbol name prefixed by `.' as the section name. Note - this
14600 macro can now be called for uninitialized data items as well as
14601 initialized data and functions. */
14604 rs6000_elf_unique_section (tree decl, int reloc)
14606 /* As above, pretend that we're always building for a shared library
14607 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
14608 default_unique_section_1 (decl, reloc,
14609 flag_pic || DEFAULT_ABI == ABI_AIX);
14612 /* For a SYMBOL_REF, set generic flags and then perform some
14613 target-specific processing.
14615 When the AIX ABI is requested on a non-AIX system, replace the
14616 function name with the real name (with a leading .) rather than the
14617 function descriptor name. This saves a lot of overriding code to
14618 read the prefixes. */
14621 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
14623 default_encode_section_info (decl, rtl, first);
14626 && TREE_CODE (decl) == FUNCTION_DECL
14628 && DEFAULT_ABI == ABI_AIX)
14630 rtx sym_ref = XEXP (rtl, 0);
14631 size_t len = strlen (XSTR (sym_ref, 0));
14632 char *str = alloca (len + 2);
14634 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
14635 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
14640 rs6000_elf_in_small_data_p (tree decl)
14642 if (rs6000_sdata == SDATA_NONE)
14645 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
14647 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
14648 if (strcmp (section, ".sdata") == 0
14649 || strcmp (section, ".sdata2") == 0
14650 || strcmp (section, ".sbss") == 0
14651 || strcmp (section, ".sbss2") == 0
14652 || strcmp (section, ".PPC.EMB.sdata0") == 0
14653 || strcmp (section, ".PPC.EMB.sbss0") == 0)
14658 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
14661 && (unsigned HOST_WIDE_INT) size <= g_switch_value
14662 /* If it's not public, and we're not going to reference it there,
14663 there's no need to put it in the small data section. */
14664 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
14671 #endif /* USING_ELFOS_H */
14674 /* Return a REG that occurs in ADDR with coefficient 1.
14675 ADDR can be effectively incremented by incrementing REG.
14677 r0 is special and we must not select it as an address
14678 register by this routine since our caller will try to
14679 increment the returned register via an "la" instruction. */
14682 find_addr_reg (rtx addr)
14684 while (GET_CODE (addr) == PLUS)
14686 if (GET_CODE (XEXP (addr, 0)) == REG
14687 && REGNO (XEXP (addr, 0)) != 0)
14688 addr = XEXP (addr, 0);
14689 else if (GET_CODE (XEXP (addr, 1)) == REG
14690 && REGNO (XEXP (addr, 1)) != 0)
14691 addr = XEXP (addr, 1);
14692 else if (CONSTANT_P (XEXP (addr, 0)))
14693 addr = XEXP (addr, 1);
14694 else if (CONSTANT_P (XEXP (addr, 1)))
14695 addr = XEXP (addr, 0);
14699 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
14705 rs6000_fatal_bad_address (rtx op)
14707 fatal_insn ("bad address", op);
14713 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
14714 reference and a constant. */
14717 symbolic_operand (rtx op)
14719 switch (GET_CODE (op))
14726 return (GET_CODE (op) == SYMBOL_REF ||
14727 (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
14728 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
14729 && GET_CODE (XEXP (op, 1)) == CONST_INT);
14738 static tree branch_island_list = 0;
14740 /* Remember to generate a branch island for far calls to the given
14744 add_compiler_branch_island (tree label_name, tree function_name, int line_number)
14746 tree branch_island = build_tree_list (function_name, label_name);
14747 TREE_TYPE (branch_island) = build_int_2 (line_number, 0);
14748 TREE_CHAIN (branch_island) = branch_island_list;
14749 branch_island_list = branch_island;
14752 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
14753 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
14754 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
14755 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
14757 /* Generate far-jump branch islands for everything on the
14758 branch_island_list. Invoked immediately after the last instruction
14759 of the epilogue has been emitted; the branch-islands must be
14760 appended to, and contiguous with, the function body. Mach-O stubs
14761 are generated in machopic_output_stub(). */
14764 macho_branch_islands (void)
14767 tree branch_island;
14769 for (branch_island = branch_island_list;
14771 branch_island = TREE_CHAIN (branch_island))
14773 const char *label =
14774 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
14776 darwin_strip_name_encoding (
14777 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)));
14778 char name_buf[512];
14779 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
14780 if (name[0] == '*' || name[0] == '&')
14781 strcpy (name_buf, name+1);
14785 strcpy (name_buf+1, name);
14787 strcpy (tmp_buf, "\n");
14788 strcat (tmp_buf, label);
14789 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
14790 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
14791 fprintf (asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
14792 BRANCH_ISLAND_LINE_NUMBER(branch_island));
14793 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
14796 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
14797 strcat (tmp_buf, label);
14798 strcat (tmp_buf, "_pic\n");
14799 strcat (tmp_buf, label);
14800 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
14802 strcat (tmp_buf, "\taddis r11,r11,ha16(");
14803 strcat (tmp_buf, name_buf);
14804 strcat (tmp_buf, " - ");
14805 strcat (tmp_buf, label);
14806 strcat (tmp_buf, "_pic)\n");
14808 strcat (tmp_buf, "\tmtlr r0\n");
14810 strcat (tmp_buf, "\taddi r12,r11,lo16(");
14811 strcat (tmp_buf, name_buf);
14812 strcat (tmp_buf, " - ");
14813 strcat (tmp_buf, label);
14814 strcat (tmp_buf, "_pic)\n");
14816 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
14820 strcat (tmp_buf, ":\nlis r12,hi16(");
14821 strcat (tmp_buf, name_buf);
14822 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
14823 strcat (tmp_buf, name_buf);
14824 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
14826 output_asm_insn (tmp_buf, 0);
14827 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
14828 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
14829 fprintf(asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
14830 BRANCH_ISLAND_LINE_NUMBER (branch_island));
14831 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
14834 branch_island_list = 0;
14837 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
14838 already there or not. */
14841 no_previous_def (tree function_name)
14843 tree branch_island;
14844 for (branch_island = branch_island_list;
14846 branch_island = TREE_CHAIN (branch_island))
14847 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
14852 /* GET_PREV_LABEL gets the label name from the previous definition of
14856 get_prev_label (tree function_name)
14858 tree branch_island;
14859 for (branch_island = branch_island_list;
14861 branch_island = TREE_CHAIN (branch_island))
14862 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
14863 return BRANCH_ISLAND_LABEL_NAME (branch_island);
14867 /* INSN is either a function call or a millicode call. It may have an
14868 unconditional jump in its delay slot.
14870 CALL_DEST is the routine we are calling. */
14873 output_call (rtx insn, rtx *operands, int dest_operand_number, int cookie_operand_number)
14875 static char buf[256];
14876 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
14877 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
14880 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
14882 if (no_previous_def (funname))
14884 int line_number = 0;
14885 rtx label_rtx = gen_label_rtx ();
14886 char *label_buf, temp_buf[256];
14887 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
14888 CODE_LABEL_NUMBER (label_rtx));
14889 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
14890 labelname = get_identifier (label_buf);
14891 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
14893 line_number = NOTE_LINE_NUMBER (insn);
14894 add_compiler_branch_island (labelname, funname, line_number);
14897 labelname = get_prev_label (funname);
14899 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
14900 instruction will reach 'foo', otherwise link as 'bl L42'".
14901 "L42" should be a 'branch island', that will do a far jump to
14902 'foo'. Branch islands are generated in
14903 macho_branch_islands(). */
14904 sprintf (buf, "jbsr %%z%d,%.246s",
14905 dest_operand_number, IDENTIFIER_POINTER (labelname));
14908 sprintf (buf, "bl %%z%d", dest_operand_number);
14912 #endif /* TARGET_MACHO */
14914 /* Generate PIC and indirect symbol stubs. */
14917 machopic_output_stub (FILE *file, const char *symb, const char *stub)
14919 unsigned int length;
14920 char *symbol_name, *lazy_ptr_name;
14921 char *local_label_0;
14922 static int label = 0;
14924 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
14925 symb = (*targetm.strip_name_encoding) (symb);
14928 length = strlen (symb);
14929 symbol_name = alloca (length + 32);
14930 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
14932 lazy_ptr_name = alloca (length + 32);
14933 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
14936 machopic_picsymbol_stub1_section ();
14938 machopic_symbol_stub1_section ();
14939 fprintf (file, "\t.align 2\n");
14941 fprintf (file, "%s:\n", stub);
14942 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
14947 local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
14948 sprintf (local_label_0, "\"L%011d$spb\"", label);
14950 fprintf (file, "\tmflr r0\n");
14951 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
14952 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
14953 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
14954 lazy_ptr_name, local_label_0);
14955 fprintf (file, "\tmtlr r0\n");
14956 fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n",
14957 lazy_ptr_name, local_label_0);
14958 fprintf (file, "\tmtctr r12\n");
14959 fprintf (file, "\tbctr\n");
14963 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
14964 fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
14965 fprintf (file, "\tmtctr r12\n");
14966 fprintf (file, "\tbctr\n");
14969 machopic_lazy_symbol_ptr_section ();
14970 fprintf (file, "%s:\n", lazy_ptr_name);
14971 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
14972 fprintf (file, "\t.long dyld_stub_binding_helper\n");
14975 /* Legitimize PIC addresses. If the address is already
14976 position-independent, we return ORIG. Newly generated
14977 position-independent addresses go into a reg. This is REG if non
14978 zero, otherwise we allocate register(s) as necessary. */
14980 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
14983 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
14988 if (reg == NULL && ! reload_in_progress && ! reload_completed)
14989 reg = gen_reg_rtx (Pmode);
14991 if (GET_CODE (orig) == CONST)
14993 if (GET_CODE (XEXP (orig, 0)) == PLUS
14994 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
14997 if (GET_CODE (XEXP (orig, 0)) == PLUS)
14999 /* Use a different reg for the intermediate value, as
15000 it will be marked UNCHANGING. */
15001 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
15004 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
15007 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
15013 if (GET_CODE (offset) == CONST_INT)
15015 if (SMALL_INT (offset))
15016 return plus_constant (base, INTVAL (offset));
15017 else if (! reload_in_progress && ! reload_completed)
15018 offset = force_reg (Pmode, offset);
15021 rtx mem = force_const_mem (Pmode, orig);
15022 return machopic_legitimize_pic_address (mem, Pmode, reg);
15025 return gen_rtx (PLUS, Pmode, base, offset);
15028 /* Fall back on generic machopic code. */
15029 return machopic_legitimize_pic_address (orig, mode, reg);
15032 /* This is just a placeholder to make linking work without having to
15033 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
15034 ever needed for Darwin (not too likely!) this would have to get a
15035 real definition. */
15042 #endif /* TARGET_MACHO */
15045 static unsigned int
15046 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
15048 return default_section_type_flags_1 (decl, name, reloc,
15049 flag_pic || DEFAULT_ABI == ABI_AIX);
15052 /* Record an element in the table of global constructors. SYMBOL is
15053 a SYMBOL_REF of the function to be called; PRIORITY is a number
15054 between 0 and MAX_INIT_PRIORITY.
15056 This differs from default_named_section_asm_out_constructor in
15057 that we have special handling for -mrelocatable. */
15060 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
15062 const char *section = ".ctors";
15065 if (priority != DEFAULT_INIT_PRIORITY)
15067 sprintf (buf, ".ctors.%.5u",
15068 /* Invert the numbering so the linker puts us in the proper
15069 order; constructors are run from right to left, and the
15070 linker sorts in increasing order. */
15071 MAX_INIT_PRIORITY - priority);
15075 named_section_flags (section, SECTION_WRITE);
15076 assemble_align (POINTER_SIZE);
15078 if (TARGET_RELOCATABLE)
15080 fputs ("\t.long (", asm_out_file);
15081 output_addr_const (asm_out_file, symbol);
15082 fputs (")@fixup\n", asm_out_file);
15085 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15089 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
15091 const char *section = ".dtors";
15094 if (priority != DEFAULT_INIT_PRIORITY)
15096 sprintf (buf, ".dtors.%.5u",
15097 /* Invert the numbering so the linker puts us in the proper
15098 order; constructors are run from right to left, and the
15099 linker sorts in increasing order. */
15100 MAX_INIT_PRIORITY - priority);
15104 named_section_flags (section, SECTION_WRITE);
15105 assemble_align (POINTER_SIZE);
15107 if (TARGET_RELOCATABLE)
15109 fputs ("\t.long (", asm_out_file);
15110 output_addr_const (asm_out_file, symbol);
15111 fputs (")@fixup\n", asm_out_file);
15114 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15118 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
15122 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
15123 ASM_OUTPUT_LABEL (file, name);
15124 fputs (DOUBLE_INT_ASM_OP, file);
15126 assemble_name (file, name);
15127 fputs (",.TOC.@tocbase,0\n\t.previous\n\t.size\t", file);
15128 assemble_name (file, name);
15129 fputs (",24\n\t.type\t.", file);
15130 assemble_name (file, name);
15131 fputs (",@function\n", file);
15132 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
15134 fputs ("\t.globl\t.", file);
15135 assemble_name (file, name);
15138 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15140 ASM_OUTPUT_LABEL (file, name);
15144 if (TARGET_RELOCATABLE
15145 && (get_pool_size () != 0 || current_function_profile)
15150 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
15152 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
15153 fprintf (file, "\t.long ");
15154 assemble_name (file, buf);
15156 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15157 assemble_name (file, buf);
15161 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
15162 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15164 if (DEFAULT_ABI == ABI_AIX)
15166 const char *desc_name, *orig_name;
15168 orig_name = (*targetm.strip_name_encoding) (name);
15169 desc_name = orig_name;
15170 while (*desc_name == '.')
15173 if (TREE_PUBLIC (decl))
15174 fprintf (file, "\t.globl %s\n", desc_name);
15176 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
15177 fprintf (file, "%s:\n", desc_name);
15178 fprintf (file, "\t.long %s\n", orig_name);
15179 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
15180 if (DEFAULT_ABI == ABI_AIX)
15181 fputs ("\t.long 0\n", file);
15182 fprintf (file, "\t.previous\n");
15184 ASM_OUTPUT_LABEL (file, name);
15190 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
15192 fputs (GLOBAL_ASM_OP, stream);
15193 RS6000_OUTPUT_BASENAME (stream, name);
15194 putc ('\n', stream);
15198 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags)
15201 static const char * const suffix[3] = { "PR", "RO", "RW" };
15203 if (flags & SECTION_CODE)
15205 else if (flags & SECTION_WRITE)
15210 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
15211 (flags & SECTION_CODE) ? "." : "",
15212 name, suffix[smclass], flags & SECTION_ENTSIZE);
15216 rs6000_xcoff_select_section (tree decl, int reloc,
15217 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15219 if (decl_readonly_section_1 (decl, reloc, 1))
15221 if (TREE_PUBLIC (decl))
15222 read_only_data_section ();
15224 read_only_private_data_section ();
15228 if (TREE_PUBLIC (decl))
15231 private_data_section ();
15236 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
15240 /* Use select_section for private and uninitialized data. */
15241 if (!TREE_PUBLIC (decl)
15242 || DECL_COMMON (decl)
15243 || DECL_INITIAL (decl) == NULL_TREE
15244 || DECL_INITIAL (decl) == error_mark_node
15245 || (flag_zero_initialized_in_bss
15246 && initializer_zerop (DECL_INITIAL (decl))))
15249 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
15250 name = (*targetm.strip_name_encoding) (name);
15251 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
15254 /* Select section for constant in constant pool.
15256 On RS/6000, all constants are in the private read-only data area.
15257 However, if this is being placed in the TOC it must be output as a
15261 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
15262 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15264 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15267 read_only_private_data_section ();
15270 /* Remove any trailing [DS] or the like from the symbol name. */
15272 static const char *
15273 rs6000_xcoff_strip_name_encoding (const char *name)
15278 len = strlen (name);
15279 if (name[len - 1] == ']')
15280 return ggc_alloc_string (name, len - 4);
15285 /* Section attributes. AIX is always PIC. */
15287 static unsigned int
15288 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
15290 unsigned int align;
15291 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
15293 /* Align to at least UNIT size. */
15294 if (flags & SECTION_CODE)
15295 align = MIN_UNITS_PER_WORD;
15297 /* Increase alignment of large objects if not already stricter. */
15298 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
15299 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
15300 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
15302 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
15305 /* Output at beginning of assembler file.
15307 Initialize the section names for the RS/6000 at this point.
15309 Specify filename, including full path, to assembler.
15311 We want to go into the TOC section so at least one .toc will be emitted.
15312 Also, in order to output proper .bs/.es pairs, we need at least one static
15313 [RW] section emitted.
15315 Finally, declare mcount when profiling to make the assembler happy. */
15318 rs6000_xcoff_file_start (void)
15320 rs6000_gen_section_name (&xcoff_bss_section_name,
15321 main_input_filename, ".bss_");
15322 rs6000_gen_section_name (&xcoff_private_data_section_name,
15323 main_input_filename, ".rw_");
15324 rs6000_gen_section_name (&xcoff_read_only_section_name,
15325 main_input_filename, ".ro_");
15327 fputs ("\t.file\t", asm_out_file);
15328 output_quoted_string (asm_out_file, main_input_filename);
15329 fputc ('\n', asm_out_file);
15331 if (write_symbols != NO_DEBUG)
15332 private_data_section ();
15335 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
15336 rs6000_file_start ();
15339 /* Output at end of assembler file.
15340 On the RS/6000, referencing data should automatically pull in text. */
15343 rs6000_xcoff_file_end (void)
15346 fputs ("_section_.text:\n", asm_out_file);
15348 fputs (TARGET_32BIT
15349 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
15352 #endif /* TARGET_XCOFF */
15355 /* Cross-module name binding. Darwin does not support overriding
15356 functions at dynamic-link time. */
15359 rs6000_binds_local_p (tree decl)
15361 return default_binds_local_p_1 (decl, 0);
15365 /* Compute a (partial) cost for rtx X. Return true if the complete
15366 cost has been computed, and false if subexpressions should be
15367 scanned. In either case, *TOTAL contains the cost result. */
15370 rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED,
15375 /* On the RS/6000, if it is valid in the insn, it is free.
15376 So this always returns 0. */
15387 *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15388 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1))
15389 + 0x8000) >= 0x10000)
15390 && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15391 ? COSTS_N_INSNS (2)
15392 : COSTS_N_INSNS (1));
15398 *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15399 && (INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0
15400 && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15401 ? COSTS_N_INSNS (2)
15402 : COSTS_N_INSNS (1));
15408 *total = COSTS_N_INSNS (2);
15411 switch (rs6000_cpu)
15413 case PROCESSOR_RIOS1:
15414 case PROCESSOR_PPC405:
15415 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15416 ? COSTS_N_INSNS (5)
15417 : (INTVAL (XEXP (x, 1)) >= -256
15418 && INTVAL (XEXP (x, 1)) <= 255)
15419 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15422 case PROCESSOR_PPC440:
15423 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15424 ? COSTS_N_INSNS (3)
15425 : COSTS_N_INSNS (2));
15428 case PROCESSOR_RS64A:
15429 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15430 ? GET_MODE (XEXP (x, 1)) != DImode
15431 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34)
15432 : (INTVAL (XEXP (x, 1)) >= -256
15433 && INTVAL (XEXP (x, 1)) <= 255)
15434 ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12));
15437 case PROCESSOR_RIOS2:
15438 case PROCESSOR_MPCCORE:
15439 case PROCESSOR_PPC604e:
15440 *total = COSTS_N_INSNS (2);
15443 case PROCESSOR_PPC601:
15444 *total = COSTS_N_INSNS (5);
15447 case PROCESSOR_PPC603:
15448 case PROCESSOR_PPC7400:
15449 case PROCESSOR_PPC750:
15450 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15451 ? COSTS_N_INSNS (5)
15452 : (INTVAL (XEXP (x, 1)) >= -256
15453 && INTVAL (XEXP (x, 1)) <= 255)
15454 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3));
15457 case PROCESSOR_PPC7450:
15458 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15459 ? COSTS_N_INSNS (4)
15460 : COSTS_N_INSNS (3));
15463 case PROCESSOR_PPC403:
15464 case PROCESSOR_PPC604:
15465 case PROCESSOR_PPC8540:
15466 *total = COSTS_N_INSNS (4);
15469 case PROCESSOR_PPC620:
15470 case PROCESSOR_PPC630:
15471 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15472 ? GET_MODE (XEXP (x, 1)) != DImode
15473 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7)
15474 : (INTVAL (XEXP (x, 1)) >= -256
15475 && INTVAL (XEXP (x, 1)) <= 255)
15476 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15479 case PROCESSOR_POWER4:
15480 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15481 ? GET_MODE (XEXP (x, 1)) != DImode
15482 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)
15483 : COSTS_N_INSNS (2));
15492 if (GET_CODE (XEXP (x, 1)) == CONST_INT
15493 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
15495 *total = COSTS_N_INSNS (2);
15502 switch (rs6000_cpu)
15504 case PROCESSOR_RIOS1:
15505 *total = COSTS_N_INSNS (19);
15508 case PROCESSOR_RIOS2:
15509 *total = COSTS_N_INSNS (13);
15512 case PROCESSOR_RS64A:
15513 *total = (GET_MODE (XEXP (x, 1)) != DImode
15514 ? COSTS_N_INSNS (65)
15515 : COSTS_N_INSNS (67));
15518 case PROCESSOR_MPCCORE:
15519 *total = COSTS_N_INSNS (6);
15522 case PROCESSOR_PPC403:
15523 *total = COSTS_N_INSNS (33);
15526 case PROCESSOR_PPC405:
15527 *total = COSTS_N_INSNS (35);
15530 case PROCESSOR_PPC440:
15531 *total = COSTS_N_INSNS (34);
15534 case PROCESSOR_PPC601:
15535 *total = COSTS_N_INSNS (36);
15538 case PROCESSOR_PPC603:
15539 *total = COSTS_N_INSNS (37);
15542 case PROCESSOR_PPC604:
15543 case PROCESSOR_PPC604e:
15544 *total = COSTS_N_INSNS (20);
15547 case PROCESSOR_PPC620:
15548 case PROCESSOR_PPC630:
15549 *total = (GET_MODE (XEXP (x, 1)) != DImode
15550 ? COSTS_N_INSNS (21)
15551 : COSTS_N_INSNS (37));
15554 case PROCESSOR_PPC750:
15555 case PROCESSOR_PPC8540:
15556 case PROCESSOR_PPC7400:
15557 *total = COSTS_N_INSNS (19);
15560 case PROCESSOR_PPC7450:
15561 *total = COSTS_N_INSNS (23);
15564 case PROCESSOR_POWER4:
15565 *total = (GET_MODE (XEXP (x, 1)) != DImode
15566 ? COSTS_N_INSNS (18)
15567 : COSTS_N_INSNS (34));
15575 *total = COSTS_N_INSNS (4);
15579 /* MEM should be slightly more expensive than (plus (reg) (const)). */
15588 /* A C expression returning the cost of moving data from a register of class
15589 CLASS1 to one of CLASS2. */
15592 rs6000_register_move_cost (enum machine_mode mode,
15593 enum reg_class from, enum reg_class to)
15595 /* Moves from/to GENERAL_REGS. */
15596 if (reg_classes_intersect_p (to, GENERAL_REGS)
15597 || reg_classes_intersect_p (from, GENERAL_REGS))
15599 if (! reg_classes_intersect_p (to, GENERAL_REGS))
15602 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
15603 return (rs6000_memory_move_cost (mode, from, 0)
15604 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
15606 /* It's more expensive to move CR_REGS than CR0_REGS because of the shift.... */
15607 else if (from == CR_REGS)
15611 /* A move will cost one instruction per GPR moved. */
15612 return 2 * HARD_REGNO_NREGS (0, mode);
15615 /* Moving between two similar registers is just one instruction. */
15616 else if (reg_classes_intersect_p (to, from))
15617 return mode == TFmode ? 4 : 2;
15619 /* Everything else has to go through GENERAL_REGS. */
15621 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
15622 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
15625 /* A C expressions returning the cost of moving data of MODE from a register to
15629 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
15630 int in ATTRIBUTE_UNUSED)
15632 if (reg_classes_intersect_p (class, GENERAL_REGS))
15633 return 4 * HARD_REGNO_NREGS (0, mode);
15634 else if (reg_classes_intersect_p (class, FLOAT_REGS))
15635 return 4 * HARD_REGNO_NREGS (32, mode);
15636 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
15637 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
15639 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
15642 /* Return an RTX representing where to find the function value of a
15643 function returning MODE. */
15645 rs6000_complex_function_value (enum machine_mode mode)
15647 unsigned int regno;
15649 enum machine_mode inner = GET_MODE_INNER (mode);
15651 if (FLOAT_MODE_P (mode))
15652 regno = FP_ARG_RETURN;
15655 regno = GP_ARG_RETURN;
15657 /* 32-bit is OK since it'll go in r3/r4. */
15659 && GET_MODE_BITSIZE (inner) >= 32)
15660 return gen_rtx_REG (mode, regno);
15663 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
15665 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
15666 GEN_INT (GET_MODE_UNIT_SIZE (inner)));
15667 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
15670 /* Define how to find the value returned by a function.
15671 VALTYPE is the data type of the value (as a tree).
15672 If the precise function being called is known, FUNC is its FUNCTION_DECL;
15673 otherwise, FUNC is 0.
15675 On the SPE, both FPs and vectors are returned in r3.
15677 On RS/6000 an integer value is in r3 and a floating-point value is in
15678 fp1, unless -msoft-float. */
15681 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
15683 enum machine_mode mode;
15684 unsigned int regno;
15686 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
15688 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
15689 return gen_rtx_PARALLEL (DImode,
15691 gen_rtx_EXPR_LIST (VOIDmode,
15692 gen_rtx_REG (SImode, GP_ARG_RETURN),
15694 gen_rtx_EXPR_LIST (VOIDmode,
15695 gen_rtx_REG (SImode,
15696 GP_ARG_RETURN + 1),
15700 if ((INTEGRAL_TYPE_P (valtype)
15701 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
15702 || POINTER_TYPE_P (valtype))
15703 mode = TARGET_32BIT ? SImode : DImode;
15705 mode = TYPE_MODE (valtype);
15707 if (TREE_CODE (valtype) == REAL_TYPE && TARGET_HARD_FLOAT && TARGET_FPRS)
15708 regno = FP_ARG_RETURN;
15709 else if (TREE_CODE (valtype) == COMPLEX_TYPE
15710 && TARGET_HARD_FLOAT
15711 && SPLIT_COMPLEX_ARGS)
15712 return rs6000_complex_function_value (mode);
15713 else if (TREE_CODE (valtype) == VECTOR_TYPE && TARGET_ALTIVEC)
15714 regno = ALTIVEC_ARG_RETURN;
15716 regno = GP_ARG_RETURN;
15718 return gen_rtx_REG (mode, regno);
15721 /* Define how to find the value returned by a library function
15722 assuming the value has mode MODE. */
15724 rs6000_libcall_value (enum machine_mode mode)
15726 unsigned int regno;
15728 if (GET_MODE_CLASS (mode) == MODE_FLOAT
15729 && TARGET_HARD_FLOAT && TARGET_FPRS)
15730 regno = FP_ARG_RETURN;
15731 else if (ALTIVEC_VECTOR_MODE (mode))
15732 regno = ALTIVEC_ARG_RETURN;
15733 else if (COMPLEX_MODE_P (mode) && SPLIT_COMPLEX_ARGS)
15734 return rs6000_complex_function_value (mode);
15736 regno = GP_ARG_RETURN;
15738 return gen_rtx_REG (mode, regno);
15741 /* Define the offset between two registers, FROM to be eliminated and its
15742 replacement TO, at the start of a routine. */
15744 rs6000_initial_elimination_offset (int from, int to)
15746 rs6000_stack_t *info = rs6000_stack_info ();
15747 HOST_WIDE_INT offset;
15749 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
15750 offset = info->push_p ? 0 : -info->total_size;
15751 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
15752 offset = info->total_size;
15753 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
15754 offset = info->push_p ? info->total_size : 0;
15755 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
15763 /* Return true if TYPE is of type __ev64_opaque__. */
15766 is_ev64_opaque_type (tree type)
15769 && (type == opaque_V2SI_type_node
15770 || type == opaque_V2SF_type_node
15771 || type == opaque_p_V2SI_type_node));
15775 rs6000_dwarf_register_span (rtx reg)
15779 if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg)))
15782 regno = REGNO (reg);
15784 /* The duality of the SPE register size wreaks all kinds of havoc.
15785 This is a way of distinguishing r0 in 32-bits from r0 in
15788 gen_rtx_PARALLEL (VOIDmode,
15791 gen_rtx_REG (SImode, regno + 1200),
15792 gen_rtx_REG (SImode, regno))
15794 gen_rtx_REG (SImode, regno),
15795 gen_rtx_REG (SImode, regno + 1200)));
15798 /* Map internal gcc register numbers to DWARF2 register numbers. */
15801 rs6000_dbx_register_number (unsigned int regno)
15803 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
15805 if (regno == MQ_REGNO)
15807 if (regno == LINK_REGISTER_REGNUM)
15809 if (regno == COUNT_REGISTER_REGNUM)
15811 if (CR_REGNO_P (regno))
15812 return regno - CR0_REGNO + 86;
15813 if (regno == XER_REGNO)
15815 if (ALTIVEC_REGNO_P (regno))
15816 return regno - FIRST_ALTIVEC_REGNO + 1124;
15817 if (regno == VRSAVE_REGNO)
15819 if (regno == VSCR_REGNO)
15821 if (regno == SPE_ACC_REGNO)
15823 if (regno == SPEFSCR_REGNO)
15825 /* SPE high reg number. We get these values of regno from
15826 rs6000_dwarf_register_span. */
15827 if (regno >= 1200 && regno < 1232)
15833 #include "gt-rs6000.h"